[qemu.git] / target-ppc / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "kvm.h"

void cpu_save(QEMUFile *f, void *opaque)
{
    CPUState *env = (CPUState *)opaque;
    unsigned int i, j;

    for (i = 0; i < 32; i++)
        qemu_put_betls(f, &env->gpr[i]);
#if !defined(TARGET_PPC64)
    for (i = 0; i < 32; i++)
        qemu_put_betls(f, &env->gprh[i]);
#endif
    qemu_put_betls(f, &env->lr);
    qemu_put_betls(f, &env->ctr);
    for (i = 0; i < 8; i++)
        qemu_put_be32s(f, &env->crf[i]);
    qemu_put_betls(f, &env->xer);
    qemu_put_betls(f, &env->reserve_addr);
    qemu_put_betls(f, &env->msr);
    for (i = 0; i < 4; i++)
        qemu_put_betls(f, &env->tgpr[i]);
    for (i = 0; i < 32; i++) {
        union {
            float64 d;
            uint64_t l;
        } u;
        u.d = env->fpr[i];
        qemu_put_be64(f, u.l);
    }
    qemu_put_be32s(f, &env->fpscr);
    qemu_put_sbe32s(f, &env->access_type);
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
    qemu_put_betls(f, &env->asr);
    qemu_put_sbe32s(f, &env->slb_nr);
#endif
    qemu_put_betls(f, &env->spr[SPR_SDR1]);
    for (i = 0; i < 32; i++)
        qemu_put_betls(f, &env->sr[i]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_put_betls(f, &env->DBAT[i][j]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_put_betls(f, &env->IBAT[i][j]);
    qemu_put_sbe32s(f, &env->nb_tlb);
    qemu_put_sbe32s(f, &env->tlb_per_way);
    qemu_put_sbe32s(f, &env->nb_ways);
    qemu_put_sbe32s(f, &env->last_way);
    qemu_put_sbe32s(f, &env->id_tlbs);
    qemu_put_sbe32s(f, &env->nb_pids);
    if (env->tlb.tlb6) {
        // XXX assumes 6xx
        for (i = 0; i < env->nb_tlb; i++) {
            qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
            qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
            qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
        }
    }
    for (i = 0; i < 4; i++)
        qemu_put_betls(f, &env->pb[i]);
#endif
    for (i = 0; i < 1024; i++)
        qemu_put_betls(f, &env->spr[i]);
    qemu_put_be32s(f, &env->vscr);
    qemu_put_be64s(f, &env->spe_acc);
    qemu_put_be32s(f, &env->spe_fscr);
    qemu_put_betls(f, &env->msr_mask);
    qemu_put_be32s(f, &env->flags);
    qemu_put_sbe32s(f, &env->error_code);
    qemu_put_be32s(f, &env->pending_interrupts);
#if !defined(CONFIG_USER_ONLY)
    qemu_put_be32s(f, &env->irq_input_state);
    for (i = 0; i < POWERPC_EXCP_NB; i++)
        qemu_put_betls(f, &env->excp_vectors[i]);
    qemu_put_betls(f, &env->excp_prefix);
    qemu_put_betls(f, &env->hreset_excp_prefix);
    qemu_put_betls(f, &env->ivor_mask);
    qemu_put_betls(f, &env->ivpr_mask);
    qemu_put_betls(f, &env->hreset_vector);
#endif
    qemu_put_betls(f, &env->nip);
    qemu_put_betls(f, &env->hflags);
    qemu_put_betls(f, &env->hflags_nmsr);
    qemu_put_sbe32s(f, &env->mmu_idx);
    qemu_put_sbe32s(f, &env->power_mode);
}

int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
    CPUState *env = (CPUState *)opaque;
    unsigned int i, j;
    target_ulong sdr1;

    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gpr[i]);
#if !defined(TARGET_PPC64)
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gprh[i]);
#endif
    qemu_get_betls(f, &env->lr);
    qemu_get_betls(f, &env->ctr);
    for (i = 0; i < 8; i++)
        qemu_get_be32s(f, &env->crf[i]);
    qemu_get_betls(f, &env->xer);
    qemu_get_betls(f, &env->reserve_addr);
    qemu_get_betls(f, &env->msr);
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->tgpr[i]);
    for (i = 0; i < 32; i++) {
        union {
            float64 d;
            uint64_t l;
        } u;
        u.l = qemu_get_be64(f);
        env->fpr[i] = u.d;
    }
    qemu_get_be32s(f, &env->fpscr);
    qemu_get_sbe32s(f, &env->access_type);
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
    qemu_get_betls(f, &env->asr);
    qemu_get_sbe32s(f, &env->slb_nr);
#endif
    qemu_get_betls(f, &sdr1);
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->sr[i]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->DBAT[i][j]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->IBAT[i][j]);
    qemu_get_sbe32s(f, &env->nb_tlb);
    qemu_get_sbe32s(f, &env->tlb_per_way);
    qemu_get_sbe32s(f, &env->nb_ways);
    qemu_get_sbe32s(f, &env->last_way);
    qemu_get_sbe32s(f, &env->id_tlbs);
    qemu_get_sbe32s(f, &env->nb_pids);
    if (env->tlb.tlb6) {
        // XXX assumes 6xx
        for (i = 0; i < env->nb_tlb; i++) {
            qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
            qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
            qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
        }
    }
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->pb[i]);
#endif
    for (i = 0; i < 1024; i++)
        qemu_get_betls(f, &env->spr[i]);
    ppc_store_sdr1(env, sdr1);
    qemu_get_be32s(f, &env->vscr);
    qemu_get_be64s(f, &env->spe_acc);
    qemu_get_be32s(f, &env->spe_fscr);
    qemu_get_betls(f, &env->msr_mask);
    qemu_get_be32s(f, &env->flags);
    qemu_get_sbe32s(f, &env->error_code);
    qemu_get_be32s(f, &env->pending_interrupts);
#if !defined(CONFIG_USER_ONLY)
    qemu_get_be32s(f, &env->irq_input_state);
    for (i = 0; i < POWERPC_EXCP_NB; i++)
        qemu_get_betls(f, &env->excp_vectors[i]);
    qemu_get_betls(f, &env->excp_prefix);
    qemu_get_betls(f, &env->hreset_excp_prefix);
    qemu_get_betls(f, &env->ivor_mask);
    qemu_get_betls(f, &env->ivpr_mask);
    qemu_get_betls(f, &env->hreset_vector);
#endif
    qemu_get_betls(f, &env->nip);
    qemu_get_betls(f, &env->hflags);
    qemu_get_betls(f, &env->hflags_nmsr);
    qemu_get_sbe32s(f, &env->mmu_idx);
    qemu_get_sbe32s(f, &env->power_mode);

    return 0;
}
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
8dd3dca3 AJ	2	#include "hw/boards.h"
b0a46a33	3	#include "kvm.h"
8dd3dca3	4
8dd3dca3 AJ	5	void cpu_save(QEMUFile f, void opaque)
8dd3dca3 AJ	6	{
a456d59c BS	7	CPUState env = (CPUState )opaque;
	8	unsigned int i, j;
	9
	10	for (i = 0; i < 32; i++)
	11	qemu_put_betls(f, &env->gpr[i]);
	12	#if !defined(TARGET_PPC64)
	13	for (i = 0; i < 32; i++)
	14	qemu_put_betls(f, &env->gprh[i]);
	15	#endif
	16	qemu_put_betls(f, &env->lr);
	17	qemu_put_betls(f, &env->ctr);
	18	for (i = 0; i < 8; i++)
	19	qemu_put_be32s(f, &env->crf[i]);
	20	qemu_put_betls(f, &env->xer);
18b21a2f	21	qemu_put_betls(f, &env->reserve_addr);
a456d59c BS	22	qemu_put_betls(f, &env->msr);
	23	for (i = 0; i < 4; i++)
	24	qemu_put_betls(f, &env->tgpr[i]);
	25	for (i = 0; i < 32; i++) {
	26	union {
	27	float64 d;
	28	uint64_t l;
	29	} u;
	30	u.d = env->fpr[i];
	31	qemu_put_be64(f, u.l);
	32	}
	33	qemu_put_be32s(f, &env->fpscr);
	34	qemu_put_sbe32s(f, &env->access_type);
	35	#if !defined(CONFIG_USER_ONLY)
	36	#if defined(TARGET_PPC64)
	37	qemu_put_betls(f, &env->asr);
	38	qemu_put_sbe32s(f, &env->slb_nr);
	39	#endif
bb593904	40	qemu_put_betls(f, &env->spr[SPR_SDR1]);
a456d59c BS	41	for (i = 0; i < 32; i++)
	42	qemu_put_betls(f, &env->sr[i]);
	43	for (i = 0; i < 2; i++)
	44	for (j = 0; j < 8; j++)
	45	qemu_put_betls(f, &env->DBAT[i][j]);
	46	for (i = 0; i < 2; i++)
	47	for (j = 0; j < 8; j++)
	48	qemu_put_betls(f, &env->IBAT[i][j]);
	49	qemu_put_sbe32s(f, &env->nb_tlb);
	50	qemu_put_sbe32s(f, &env->tlb_per_way);
	51	qemu_put_sbe32s(f, &env->nb_ways);
	52	qemu_put_sbe32s(f, &env->last_way);
	53	qemu_put_sbe32s(f, &env->id_tlbs);
	54	qemu_put_sbe32s(f, &env->nb_pids);
1c53accc	55	if (env->tlb.tlb6) {
a456d59c BS	56	// XXX assumes 6xx
a456d59c BS	57	for (i = 0; i < env->nb_tlb; i++) {
1c53accc AG	58	qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
	59	qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
	60	qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
a456d59c BS	61	}
	62	}
	63	for (i = 0; i < 4; i++)
	64	qemu_put_betls(f, &env->pb[i]);
	65	#endif
	66	for (i = 0; i < 1024; i++)
	67	qemu_put_betls(f, &env->spr[i]);
	68	qemu_put_be32s(f, &env->vscr);
	69	qemu_put_be64s(f, &env->spe_acc);
	70	qemu_put_be32s(f, &env->spe_fscr);
	71	qemu_put_betls(f, &env->msr_mask);
	72	qemu_put_be32s(f, &env->flags);
	73	qemu_put_sbe32s(f, &env->error_code);
	74	qemu_put_be32s(f, &env->pending_interrupts);
	75	#if !defined(CONFIG_USER_ONLY)
	76	qemu_put_be32s(f, &env->irq_input_state);
	77	for (i = 0; i < POWERPC_EXCP_NB; i++)
	78	qemu_put_betls(f, &env->excp_vectors[i]);
	79	qemu_put_betls(f, &env->excp_prefix);
fc1c67bc	80	qemu_put_betls(f, &env->hreset_excp_prefix);
a456d59c BS	81	qemu_put_betls(f, &env->ivor_mask);
	82	qemu_put_betls(f, &env->ivpr_mask);
	83	qemu_put_betls(f, &env->hreset_vector);
	84	#endif
	85	qemu_put_betls(f, &env->nip);
	86	qemu_put_betls(f, &env->hflags);
	87	qemu_put_betls(f, &env->hflags_nmsr);
	88	qemu_put_sbe32s(f, &env->mmu_idx);
	89	qemu_put_sbe32s(f, &env->power_mode);
8dd3dca3 AJ	90	}
	91
	92	int cpu_load(QEMUFile f, void opaque, int version_id)
	93	{
a456d59c BS	94	CPUState env = (CPUState )opaque;
a456d59c BS	95	unsigned int i, j;
bb593904	96	target_ulong sdr1;
a456d59c BS	97
	98	for (i = 0; i < 32; i++)
	99	qemu_get_betls(f, &env->gpr[i]);
	100	#if !defined(TARGET_PPC64)
	101	for (i = 0; i < 32; i++)
	102	qemu_get_betls(f, &env->gprh[i]);
	103	#endif
	104	qemu_get_betls(f, &env->lr);
	105	qemu_get_betls(f, &env->ctr);
	106	for (i = 0; i < 8; i++)
	107	qemu_get_be32s(f, &env->crf[i]);
	108	qemu_get_betls(f, &env->xer);
18b21a2f	109	qemu_get_betls(f, &env->reserve_addr);
a456d59c BS	110	qemu_get_betls(f, &env->msr);
	111	for (i = 0; i < 4; i++)
	112	qemu_get_betls(f, &env->tgpr[i]);
	113	for (i = 0; i < 32; i++) {
	114	union {
	115	float64 d;
	116	uint64_t l;
	117	} u;
	118	u.l = qemu_get_be64(f);
	119	env->fpr[i] = u.d;
	120	}
	121	qemu_get_be32s(f, &env->fpscr);
	122	qemu_get_sbe32s(f, &env->access_type);
	123	#if !defined(CONFIG_USER_ONLY)
	124	#if defined(TARGET_PPC64)
	125	qemu_get_betls(f, &env->asr);
	126	qemu_get_sbe32s(f, &env->slb_nr);
	127	#endif
bb593904	128	qemu_get_betls(f, &sdr1);
a456d59c BS	129	for (i = 0; i < 32; i++)
	130	qemu_get_betls(f, &env->sr[i]);
	131	for (i = 0; i < 2; i++)
	132	for (j = 0; j < 8; j++)
	133	qemu_get_betls(f, &env->DBAT[i][j]);
	134	for (i = 0; i < 2; i++)
	135	for (j = 0; j < 8; j++)
	136	qemu_get_betls(f, &env->IBAT[i][j]);
	137	qemu_get_sbe32s(f, &env->nb_tlb);
	138	qemu_get_sbe32s(f, &env->tlb_per_way);
	139	qemu_get_sbe32s(f, &env->nb_ways);
	140	qemu_get_sbe32s(f, &env->last_way);
	141	qemu_get_sbe32s(f, &env->id_tlbs);
	142	qemu_get_sbe32s(f, &env->nb_pids);
1c53accc	143	if (env->tlb.tlb6) {
a456d59c BS	144	// XXX assumes 6xx
a456d59c BS	145	for (i = 0; i < env->nb_tlb; i++) {
1c53accc AG	146	qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
	147	qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
	148	qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
a456d59c BS	149	}
	150	}
	151	for (i = 0; i < 4; i++)
	152	qemu_get_betls(f, &env->pb[i]);
	153	#endif
	154	for (i = 0; i < 1024; i++)
	155	qemu_get_betls(f, &env->spr[i]);
bb593904	156	ppc_store_sdr1(env, sdr1);
a456d59c BS	157	qemu_get_be32s(f, &env->vscr);
	158	qemu_get_be64s(f, &env->spe_acc);
	159	qemu_get_be32s(f, &env->spe_fscr);
	160	qemu_get_betls(f, &env->msr_mask);
	161	qemu_get_be32s(f, &env->flags);
	162	qemu_get_sbe32s(f, &env->error_code);
	163	qemu_get_be32s(f, &env->pending_interrupts);
	164	#if !defined(CONFIG_USER_ONLY)
	165	qemu_get_be32s(f, &env->irq_input_state);
	166	for (i = 0; i < POWERPC_EXCP_NB; i++)
	167	qemu_get_betls(f, &env->excp_vectors[i]);
	168	qemu_get_betls(f, &env->excp_prefix);
fc1c67bc	169	qemu_get_betls(f, &env->hreset_excp_prefix);
a456d59c BS	170	qemu_get_betls(f, &env->ivor_mask);
	171	qemu_get_betls(f, &env->ivpr_mask);
	172	qemu_get_betls(f, &env->hreset_vector);
	173	#endif
	174	qemu_get_betls(f, &env->nip);
	175	qemu_get_betls(f, &env->hflags);
	176	qemu_get_betls(f, &env->hflags_nmsr);
	177	qemu_get_sbe32s(f, &env->mmu_idx);
	178	qemu_get_sbe32s(f, &env->power_mode);
	179
8dd3dca3 AJ	180	return 0;
8dd3dca3 AJ	181	}