]> git.proxmox.com Git - qemu.git/blame - target-ppc/machine.c
softmmu: move include files to include/sysemu/
[qemu.git] / target-ppc / machine.c
CommitLineData
8dd3dca3
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1#include "hw/hw.h"
2#include "hw/boards.h"
9c17d615 3#include "sysemu/kvm.h"
8dd3dca3 4
8dd3dca3
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5void cpu_save(QEMUFile *f, void *opaque)
6{
1328c2bf 7 CPUPPCState *env = (CPUPPCState *)opaque;
a456d59c 8 unsigned int i, j;
30304420 9 uint32_t fpscr;
a456d59c
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10
11 for (i = 0; i < 32; i++)
12 qemu_put_betls(f, &env->gpr[i]);
13#if !defined(TARGET_PPC64)
14 for (i = 0; i < 32; i++)
15 qemu_put_betls(f, &env->gprh[i]);
16#endif
17 qemu_put_betls(f, &env->lr);
18 qemu_put_betls(f, &env->ctr);
19 for (i = 0; i < 8; i++)
20 qemu_put_be32s(f, &env->crf[i]);
21 qemu_put_betls(f, &env->xer);
18b21a2f 22 qemu_put_betls(f, &env->reserve_addr);
a456d59c
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23 qemu_put_betls(f, &env->msr);
24 for (i = 0; i < 4; i++)
25 qemu_put_betls(f, &env->tgpr[i]);
26 for (i = 0; i < 32; i++) {
27 union {
28 float64 d;
29 uint64_t l;
30 } u;
31 u.d = env->fpr[i];
32 qemu_put_be64(f, u.l);
33 }
30304420
DG
34 fpscr = env->fpscr;
35 qemu_put_be32s(f, &fpscr);
a456d59c 36 qemu_put_sbe32s(f, &env->access_type);
a456d59c
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37#if defined(TARGET_PPC64)
38 qemu_put_betls(f, &env->asr);
39 qemu_put_sbe32s(f, &env->slb_nr);
40#endif
bb593904 41 qemu_put_betls(f, &env->spr[SPR_SDR1]);
a456d59c
BS
42 for (i = 0; i < 32; i++)
43 qemu_put_betls(f, &env->sr[i]);
44 for (i = 0; i < 2; i++)
45 for (j = 0; j < 8; j++)
46 qemu_put_betls(f, &env->DBAT[i][j]);
47 for (i = 0; i < 2; i++)
48 for (j = 0; j < 8; j++)
49 qemu_put_betls(f, &env->IBAT[i][j]);
50 qemu_put_sbe32s(f, &env->nb_tlb);
51 qemu_put_sbe32s(f, &env->tlb_per_way);
52 qemu_put_sbe32s(f, &env->nb_ways);
53 qemu_put_sbe32s(f, &env->last_way);
54 qemu_put_sbe32s(f, &env->id_tlbs);
55 qemu_put_sbe32s(f, &env->nb_pids);
1c53accc 56 if (env->tlb.tlb6) {
a456d59c
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57 // XXX assumes 6xx
58 for (i = 0; i < env->nb_tlb; i++) {
1c53accc
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59 qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
60 qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
61 qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
a456d59c
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62 }
63 }
64 for (i = 0; i < 4; i++)
65 qemu_put_betls(f, &env->pb[i]);
a456d59c
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66 for (i = 0; i < 1024; i++)
67 qemu_put_betls(f, &env->spr[i]);
68 qemu_put_be32s(f, &env->vscr);
69 qemu_put_be64s(f, &env->spe_acc);
70 qemu_put_be32s(f, &env->spe_fscr);
71 qemu_put_betls(f, &env->msr_mask);
72 qemu_put_be32s(f, &env->flags);
73 qemu_put_sbe32s(f, &env->error_code);
74 qemu_put_be32s(f, &env->pending_interrupts);
a456d59c
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75 qemu_put_be32s(f, &env->irq_input_state);
76 for (i = 0; i < POWERPC_EXCP_NB; i++)
77 qemu_put_betls(f, &env->excp_vectors[i]);
78 qemu_put_betls(f, &env->excp_prefix);
fc1c67bc 79 qemu_put_betls(f, &env->hreset_excp_prefix);
a456d59c
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80 qemu_put_betls(f, &env->ivor_mask);
81 qemu_put_betls(f, &env->ivpr_mask);
82 qemu_put_betls(f, &env->hreset_vector);
a456d59c
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83 qemu_put_betls(f, &env->nip);
84 qemu_put_betls(f, &env->hflags);
85 qemu_put_betls(f, &env->hflags_nmsr);
86 qemu_put_sbe32s(f, &env->mmu_idx);
011aba24 87 qemu_put_sbe32(f, 0);
8dd3dca3
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88}
89
90int cpu_load(QEMUFile *f, void *opaque, int version_id)
91{
1328c2bf 92 CPUPPCState *env = (CPUPPCState *)opaque;
a456d59c 93 unsigned int i, j;
bb593904 94 target_ulong sdr1;
30304420 95 uint32_t fpscr;
a456d59c
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96
97 for (i = 0; i < 32; i++)
98 qemu_get_betls(f, &env->gpr[i]);
99#if !defined(TARGET_PPC64)
100 for (i = 0; i < 32; i++)
101 qemu_get_betls(f, &env->gprh[i]);
102#endif
103 qemu_get_betls(f, &env->lr);
104 qemu_get_betls(f, &env->ctr);
105 for (i = 0; i < 8; i++)
106 qemu_get_be32s(f, &env->crf[i]);
107 qemu_get_betls(f, &env->xer);
18b21a2f 108 qemu_get_betls(f, &env->reserve_addr);
a456d59c
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109 qemu_get_betls(f, &env->msr);
110 for (i = 0; i < 4; i++)
111 qemu_get_betls(f, &env->tgpr[i]);
112 for (i = 0; i < 32; i++) {
113 union {
114 float64 d;
115 uint64_t l;
116 } u;
117 u.l = qemu_get_be64(f);
118 env->fpr[i] = u.d;
119 }
30304420
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120 qemu_get_be32s(f, &fpscr);
121 env->fpscr = fpscr;
a456d59c 122 qemu_get_sbe32s(f, &env->access_type);
a456d59c
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123#if defined(TARGET_PPC64)
124 qemu_get_betls(f, &env->asr);
125 qemu_get_sbe32s(f, &env->slb_nr);
126#endif
bb593904 127 qemu_get_betls(f, &sdr1);
a456d59c
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128 for (i = 0; i < 32; i++)
129 qemu_get_betls(f, &env->sr[i]);
130 for (i = 0; i < 2; i++)
131 for (j = 0; j < 8; j++)
132 qemu_get_betls(f, &env->DBAT[i][j]);
133 for (i = 0; i < 2; i++)
134 for (j = 0; j < 8; j++)
135 qemu_get_betls(f, &env->IBAT[i][j]);
136 qemu_get_sbe32s(f, &env->nb_tlb);
137 qemu_get_sbe32s(f, &env->tlb_per_way);
138 qemu_get_sbe32s(f, &env->nb_ways);
139 qemu_get_sbe32s(f, &env->last_way);
140 qemu_get_sbe32s(f, &env->id_tlbs);
141 qemu_get_sbe32s(f, &env->nb_pids);
1c53accc 142 if (env->tlb.tlb6) {
a456d59c
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143 // XXX assumes 6xx
144 for (i = 0; i < env->nb_tlb; i++) {
1c53accc
AG
145 qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
146 qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
147 qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
a456d59c
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148 }
149 }
150 for (i = 0; i < 4; i++)
151 qemu_get_betls(f, &env->pb[i]);
a456d59c
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152 for (i = 0; i < 1024; i++)
153 qemu_get_betls(f, &env->spr[i]);
bb593904 154 ppc_store_sdr1(env, sdr1);
a456d59c
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155 qemu_get_be32s(f, &env->vscr);
156 qemu_get_be64s(f, &env->spe_acc);
157 qemu_get_be32s(f, &env->spe_fscr);
158 qemu_get_betls(f, &env->msr_mask);
159 qemu_get_be32s(f, &env->flags);
160 qemu_get_sbe32s(f, &env->error_code);
161 qemu_get_be32s(f, &env->pending_interrupts);
a456d59c
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162 qemu_get_be32s(f, &env->irq_input_state);
163 for (i = 0; i < POWERPC_EXCP_NB; i++)
164 qemu_get_betls(f, &env->excp_vectors[i]);
165 qemu_get_betls(f, &env->excp_prefix);
fc1c67bc 166 qemu_get_betls(f, &env->hreset_excp_prefix);
a456d59c
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167 qemu_get_betls(f, &env->ivor_mask);
168 qemu_get_betls(f, &env->ivpr_mask);
169 qemu_get_betls(f, &env->hreset_vector);
a456d59c
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170 qemu_get_betls(f, &env->nip);
171 qemu_get_betls(f, &env->hflags);
172 qemu_get_betls(f, &env->hflags_nmsr);
173 qemu_get_sbe32s(f, &env->mmu_idx);
011aba24 174 qemu_get_sbe32(f); /* Discard unused power_mode */
a456d59c 175
8dd3dca3
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176 return 0;
177}