[qemu.git] / target-ppc / mmu-hash32.c

/*
 *  PowerPC MMU, TLB and BAT emulation helpers for QEMU.
 *
 *  Copyright (c) 2003-2007 Jocelyn Mayer
 *  Copyright (c) 2013 David Gibson, IBM Corporation
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "helper.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
#include "mmu-hash32.h"

//#define DEBUG_MMU
//#define DEBUG_BAT

#ifdef DEBUG_MMU
#  define LOG_MMU(...) qemu_log(__VA_ARGS__)
#  define LOG_MMU_STATE(env) log_cpu_state((env), 0)
#else
#  define LOG_MMU(...) do { } while (0)
#  define LOG_MMU_STATE(...) do { } while (0)
#endif

#ifdef DEBUG_BATS
#  define LOG_BATS(...) qemu_log(__VA_ARGS__)
#else
#  define LOG_BATS(...) do { } while (0)
#endif

struct mmu_ctx_hash32 {
    hwaddr raddr;      /* Real address              */
    int prot;                      /* Protection bits           */
    int key;                       /* Access key                */
};

static int ppc_hash32_pp_prot(int key, int pp, int nx)
{
    int prot;

    if (key == 0) {
        switch (pp) {
        case 0x0:
        case 0x1:
        case 0x2:
            prot = PAGE_READ | PAGE_WRITE;
            break;

        case 0x3:
            prot = PAGE_READ;
            break;

        default:
            abort();
        }
    } else {
        switch (pp) {
        case 0x0:
            prot = 0;
            break;

        case 0x1:
        case 0x3:
            prot = PAGE_READ;
            break;

        case 0x2:
            prot = PAGE_READ | PAGE_WRITE;
            break;

        default:
            abort();
        }
    }
    if (nx == 0) {
        prot |= PAGE_EXEC;
    }

    return prot;
}

static int ppc_hash32_pte_prot(CPUPPCState *env,
                               target_ulong sr, ppc_hash_pte32_t pte)
{
    unsigned pp, key;

    key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
    pp = pte.pte1 & HPTE32_R_PP;

    return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
}

static target_ulong hash32_bat_size(CPUPPCState *env,
                                    target_ulong batu, target_ulong batl)
{
    if ((msr_pr && !(batu & BATU32_VP))
        || (!msr_pr && !(batu & BATU32_VS))) {
        return 0;
    }

    return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
}

static int hash32_bat_prot(CPUPPCState *env,
                           target_ulong batu, target_ulong batl)
{
    int pp, prot;

    prot = 0;
    pp = batl & BATL32_PP;
    if (pp != 0) {
        prot = PAGE_READ | PAGE_EXEC;
        if (pp == 0x2) {
            prot |= PAGE_WRITE;
        }
    }
    return prot;
}

static target_ulong hash32_bat_601_size(CPUPPCState *env,
                                target_ulong batu, target_ulong batl)
{
    if (!(batl & BATL32_601_V)) {
        return 0;
    }

    return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
}

static int hash32_bat_601_prot(CPUPPCState *env,
                               target_ulong batu, target_ulong batl)
{
    int key, pp;

    pp = batu & BATU32_601_PP;
    if (msr_pr == 0) {
        key = !!(batu & BATU32_601_KS);
    } else {
        key = !!(batu & BATU32_601_KP);
    }
    return ppc_hash32_pp_prot(key, pp, 0);
}

static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
                                    int *prot)
{
    target_ulong *BATlt, *BATut;
    int i;

    LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
             rwx == 2 ? 'I' : 'D', ea);
    if (rwx == 2) {
        BATlt = env->IBAT[1];
        BATut = env->IBAT[0];
    } else {
        BATlt = env->DBAT[1];
        BATut = env->DBAT[0];
    }
    for (i = 0; i < env->nb_BATs; i++) {
        target_ulong batu = BATut[i];
        target_ulong batl = BATlt[i];
        target_ulong mask;

        if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
            mask = hash32_bat_601_size(env, batu, batl);
        } else {
            mask = hash32_bat_size(env, batu, batl);
        }
        LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
                 " BATl " TARGET_FMT_lx "\n", __func__,
                 type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl);

        if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
            hwaddr raddr = (batl & mask) | (ea & ~mask);

            if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
                *prot = hash32_bat_601_prot(env, batu, batl);
            } else {
                *prot = hash32_bat_prot(env, batu, batl);
            }

            return raddr & TARGET_PAGE_MASK;
        }
    }

    /* No hit */
#if defined(DEBUG_BATS)
    if (qemu_log_enabled()) {
        LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
        for (i = 0; i < 4; i++) {
            BATu = &BATut[i];
            BATl = &BATlt[i];
            BEPIu = *BATu & BATU32_BEPIU;
            BEPIl = *BATu & BATU32_BEPIL;
            bl = (*BATu & 0x00001FFC) << 15;
            LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
                     " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
                     TARGET_FMT_lx " " TARGET_FMT_lx "\n",
                     __func__, type == ACCESS_CODE ? 'I' : 'D', i, ea,
                     *BATu, *BATl, BEPIu, BEPIl, bl);
        }
    }
#endif

    return -1;
}

static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
                                   target_ulong eaddr, int rwx,
                                   hwaddr *raddr, int *prot)
{
    int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));

    LOG_MMU("direct store...\n");

    if ((sr & 0x1FF00000) >> 20 == 0x07f) {
        /* Memory-forced I/O controller interface access */
        /* If T=1 and BUID=x'07F', the 601 performs a memory access
         * to SR[28-31] LA[4-31], bypassing all protection mechanisms.
         */
        *raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
        return 0;
    }

    if (rwx == 2) {
        /* No code fetch is allowed in direct-store areas */
        env->exception_index = POWERPC_EXCP_ISI;
        env->error_code = 0x10000000;
        return 1;
    }

    switch (env->access_type) {
    case ACCESS_INT:
        /* Integer load/store : only access allowed */
        break;
    case ACCESS_FLOAT:
        /* Floating point load/store */
        env->exception_index = POWERPC_EXCP_ALIGN;
        env->error_code = POWERPC_EXCP_ALIGN_FP;
        env->spr[SPR_DAR] = eaddr;
        return 1;
    case ACCESS_RES:
        /* lwarx, ldarx or srwcx. */
        env->error_code = 0;
        env->spr[SPR_DAR] = eaddr;
        if (rwx == 1) {
            env->spr[SPR_DSISR] = 0x06000000;
        } else {
            env->spr[SPR_DSISR] = 0x04000000;
        }
        return 1;
    case ACCESS_CACHE:
        /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
        /* Should make the instruction do no-op.
         * As it already do no-op, it's quite easy :-)
         */
        *raddr = eaddr;
        return 0;
    case ACCESS_EXT:
        /* eciwx or ecowx */
        env->exception_index = POWERPC_EXCP_DSI;
        env->error_code = 0;
        env->spr[SPR_DAR] = eaddr;
        if (rwx == 1) {
            env->spr[SPR_DSISR] = 0x06100000;
        } else {
            env->spr[SPR_DSISR] = 0x04100000;
        }
        return 1;
    default:
        qemu_log("ERROR: instruction should not need "
                 "address translation\n");
        abort();
    }
    if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
        *raddr = eaddr;
        return 0;
    } else {
        env->exception_index = POWERPC_EXCP_DSI;
        env->error_code = 0;
        env->spr[SPR_DAR] = eaddr;
        if (rwx == 1) {
            env->spr[SPR_DSISR] = 0x0a000000;
        } else {
            env->spr[SPR_DSISR] = 0x08000000;
        }
        return 1;
    }
}

hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
{
    return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
}

static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
                                     bool secondary, target_ulong ptem,
                                     ppc_hash_pte32_t *pte)
{
    hwaddr pte_offset = pteg_off;
    target_ulong pte0, pte1;
    int i;

    for (i = 0; i < HPTES_PER_GROUP; i++) {
        pte0 = ppc_hash32_load_hpte0(env, pte_offset);
        pte1 = ppc_hash32_load_hpte1(env, pte_offset);

        if ((pte0 & HPTE32_V_VALID)
            && (secondary == !!(pte0 & HPTE32_V_SECONDARY))
            && HPTE32_V_COMPARE(pte0, ptem)) {
            pte->pte0 = pte0;
            pte->pte1 = pte1;
            return pte_offset;
        }

        pte_offset += HASH_PTE_SIZE_32;
    }

    return -1;
}

static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
                                     target_ulong sr, target_ulong eaddr,
                                     ppc_hash_pte32_t *pte)
{
    hwaddr pteg_off, pte_offset;
    hwaddr hash;
    uint32_t vsid, pgidx, ptem;

    vsid = sr & SR32_VSID;
    pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
    hash = vsid ^ pgidx;
    ptem = (vsid << 7) | (pgidx >> 10);

    /* Page address translation */
    LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
            " hash " TARGET_FMT_plx "\n",
            env->htab_base, env->htab_mask, hash);

    /* Primary PTEG lookup */
    LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
            " vsid=%" PRIx32 " ptem=%" PRIx32
            " hash=" TARGET_FMT_plx "\n",
            env->htab_base, env->htab_mask, vsid, ptem, hash);
    pteg_off = get_pteg_offset32(env, hash);
    pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
    if (pte_offset == -1) {
        /* Secondary PTEG lookup */
        LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
                " vsid=%" PRIx32 " api=%" PRIx32
                " hash=" TARGET_FMT_plx "\n", env->htab_base,
                env->htab_mask, vsid, ptem, ~hash);
        pteg_off = get_pteg_offset32(env, ~hash);
        pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
    }

    return pte_offset;
}

static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
                                   target_ulong eaddr)
{
    hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
    hwaddr mask = ~TARGET_PAGE_MASK;

    return (rpn & ~mask) | (eaddr & mask);
}

int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
                                int mmu_idx)
{
    target_ulong sr;
    hwaddr pte_offset;
    ppc_hash_pte32_t pte;
    int prot;
    uint32_t new_pte1;
    const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
    hwaddr raddr;

    assert((rwx == 0) || (rwx == 1) || (rwx == 2));

    /* 1. Handle real mode accesses */
    if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
        /* Translation is off */
        raddr = eaddr;
        tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
                     PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
                     TARGET_PAGE_SIZE);
        return 0;
    }

    /* 2. Check Block Address Translation entries (BATs) */
    if (env->nb_BATs != 0) {
        raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
        if (raddr != -1) {
            if (need_prot[rwx] & ~prot) {
                if (rwx == 2) {
                    env->exception_index = POWERPC_EXCP_ISI;
                    env->error_code = 0x08000000;
                } else {
                    env->exception_index = POWERPC_EXCP_DSI;
                    env->error_code = 0;
                    env->spr[SPR_DAR] = eaddr;
                    if (rwx == 1) {
                        env->spr[SPR_DSISR] = 0x0a000000;
                    } else {
                        env->spr[SPR_DSISR] = 0x08000000;
                    }
                }
                return 1;
            }

            tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
                         raddr & TARGET_PAGE_MASK, prot, mmu_idx,
                         TARGET_PAGE_SIZE);
            return 0;
        }
    }

    /* 3. Look up the Segment Register */
    sr = env->sr[eaddr >> 28];

    /* 4. Handle direct store segments */
    if (sr & SR32_T) {
        if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
                                    &raddr, &prot) == 0) {
            tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
                         raddr & TARGET_PAGE_MASK, prot, mmu_idx,
                         TARGET_PAGE_SIZE);
            return 0;
        } else {
            return 1;
        }
    }

    /* 5. Check for segment level no-execute violation */
    if ((rwx == 2) && (sr & SR32_NX)) {
        env->exception_index = POWERPC_EXCP_ISI;
        env->error_code = 0x10000000;
        return 1;
    }

    /* 6. Locate the PTE in the hash table */
    pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
    if (pte_offset == -1) {
        if (rwx == 2) {
            env->exception_index = POWERPC_EXCP_ISI;
            env->error_code = 0x40000000;
        } else {
            env->exception_index = POWERPC_EXCP_DSI;
            env->error_code = 0;
            env->spr[SPR_DAR] = eaddr;
            if (rwx == 1) {
                env->spr[SPR_DSISR] = 0x42000000;
            } else {
                env->spr[SPR_DSISR] = 0x40000000;
            }
        }

        return 1;
    }
    LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);

    /* 7. Check access permissions */

    prot = ppc_hash32_pte_prot(env, sr, pte);

    if (need_prot[rwx] & ~prot) {
        /* Access right violation */
        LOG_MMU("PTE access rejected\n");
        if (rwx == 2) {
            env->exception_index = POWERPC_EXCP_ISI;
            env->error_code = 0x08000000;
        } else {
            env->exception_index = POWERPC_EXCP_DSI;
            env->error_code = 0;
            env->spr[SPR_DAR] = eaddr;
            if (rwx == 1) {
                env->spr[SPR_DSISR] = 0x0a000000;
            } else {
                env->spr[SPR_DSISR] = 0x08000000;
            }
        }
        return 1;
    }

    LOG_MMU("PTE access granted !\n");

    /* 8. Update PTE referenced and changed bits if necessary */

    new_pte1 = pte.pte1 | HPTE32_R_R; /* set referenced bit */
    if (rwx == 1) {
        new_pte1 |= HPTE32_R_C; /* set changed (dirty) bit */
    } else {
        /* Treat the page as read-only for now, so that a later write
         * will pass through this function again to set the C bit */
        prot &= ~PAGE_WRITE;
    }

    if (new_pte1 != pte.pte1) {
        ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
    }

    /* 9. Determine the real address from the PTE */

    raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);

    tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
                 prot, mmu_idx, TARGET_PAGE_SIZE);

    return 0;
}

hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
{
    target_ulong sr;
    hwaddr pte_offset;
    ppc_hash_pte32_t pte;
    int prot;

    if (msr_dr == 0) {
        /* Translation is off */
        return eaddr;
    }

    if (env->nb_BATs != 0) {
        hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
        if (raddr != -1) {
            return raddr;
        }
    }

    sr = env->sr[eaddr >> 28];

    if (sr & SR32_T) {
        /* FIXME: Add suitable debug support for Direct Store segments */
        return -1;
    }

    pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
    if (pte_offset == -1) {
        return -1;
    }

    return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
}
Commit	Line	Data
9d7c3f4a DG	1	/*
	2	* PowerPC MMU, TLB and BAT emulation helpers for QEMU.
	3	*
	4	* Copyright (c) 2003-2007 Jocelyn Mayer
	5	* Copyright (c) 2013 David Gibson, IBM Corporation
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include "cpu.h"
	22	#include "helper.h"
	23	#include "sysemu/kvm.h"
	24	#include "kvm_ppc.h"
	25	#include "mmu-hash32.h"
	26
	27	//#define DEBUG_MMU
98132796	28	//#define DEBUG_BAT
9d7c3f4a DG	29
	30	#ifdef DEBUG_MMU
	31	# define LOG_MMU(...) qemu_log(__VA_ARGS__)
	32	# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
	33	#else
	34	# define LOG_MMU(...) do { } while (0)
	35	# define LOG_MMU_STATE(...) do { } while (0)
	36	#endif
	37
98132796 DG	38	#ifdef DEBUG_BATS
	39	# define LOG_BATS(...) qemu_log(__VA_ARGS__)
	40	#else
	41	# define LOG_BATS(...) do { } while (0)
	42	#endif
	43
5dc68eb0 DG	44	struct mmu_ctx_hash32 {
5dc68eb0 DG	45	hwaddr raddr; /* Real address */
5dc68eb0	46	int prot; /* Protection bits */
5dc68eb0	47	int key; /* Access key */
5dc68eb0 DG	48	};
5dc68eb0 DG	49
e01b4445	50	static int ppc_hash32_pp_prot(int key, int pp, int nx)
496272a7	51	{
e01b4445	52	int prot;
496272a7	53
496272a7 DG	54	if (key == 0) {
	55	switch (pp) {
	56	case 0x0:
	57	case 0x1:
	58	case 0x2:
e01b4445 DG	59	prot = PAGE_READ \| PAGE_WRITE;
	60	break;
	61
496272a7	62	case 0x3:
e01b4445	63	prot = PAGE_READ;
496272a7	64	break;
e01b4445 DG	65
	66	default:
	67	abort();
496272a7 DG	68	}
	69	} else {
	70	switch (pp) {
	71	case 0x0:
e01b4445	72	prot = 0;
496272a7	73	break;
e01b4445	74
496272a7 DG	75	case 0x1:
496272a7 DG	76	case 0x3:
e01b4445	77	prot = PAGE_READ;
496272a7	78	break;
e01b4445	79
496272a7	80	case 0x2:
e01b4445	81	prot = PAGE_READ \| PAGE_WRITE;
496272a7	82	break;
e01b4445 DG	83
	84	default:
	85	abort();
496272a7 DG	86	}
	87	}
	88	if (nx == 0) {
e01b4445	89	prot \|= PAGE_EXEC;
496272a7 DG	90	}
496272a7 DG	91
e01b4445	92	return prot;
496272a7 DG	93	}
496272a7 DG	94
e01b4445 DG	95	static int ppc_hash32_pte_prot(CPUPPCState *env,
e01b4445 DG	96	target_ulong sr, ppc_hash_pte32_t pte)
496272a7	97	{
e01b4445	98	unsigned pp, key;
496272a7	99
e01b4445 DG	100	key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
e01b4445 DG	101	pp = pte.pte1 & HPTE32_R_PP;
496272a7	102
e01b4445	103	return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
496272a7 DG	104	}
496272a7 DG	105
6fc76aa9 DG	106	static target_ulong hash32_bat_size(CPUPPCState *env,
6fc76aa9 DG	107	target_ulong batu, target_ulong batl)
98132796	108	{
6fc76aa9 DG	109	if ((msr_pr && !(batu & BATU32_VP))
	110	\|\| (!msr_pr && !(batu & BATU32_VS))) {
	111	return 0;
98132796	112	}
6fc76aa9 DG	113
6fc76aa9 DG	114	return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
98132796 DG	115	}
98132796 DG	116
e1d49515 DG	117	static int hash32_bat_prot(CPUPPCState *env,
	118	target_ulong batu, target_ulong batl)
	119	{
	120	int pp, prot;
	121
	122	prot = 0;
	123	pp = batl & BATL32_PP;
	124	if (pp != 0) {
	125	prot = PAGE_READ \| PAGE_EXEC;
	126	if (pp == 0x2) {
	127	prot \|= PAGE_WRITE;
	128	}
	129	}
	130	return prot;
	131	}
	132
6fc76aa9	133	static target_ulong hash32_bat_601_size(CPUPPCState *env,
e1d49515	134	target_ulong batu, target_ulong batl)
98132796	135	{
6fc76aa9 DG	136	if (!(batl & BATL32_601_V)) {
	137	return 0;
	138	}
	139
	140	return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
e1d49515 DG	141	}
	142
	143	static int hash32_bat_601_prot(CPUPPCState *env,
	144	target_ulong batu, target_ulong batl)
	145	{
	146	int key, pp;
	147
	148	pp = batu & BATU32_601_PP;
	149	if (msr_pr == 0) {
	150	key = !!(batu & BATU32_601_KS);
	151	} else {
	152	key = !!(batu & BATU32_601_KP);
	153	}
e01b4445	154	return ppc_hash32_pp_prot(key, pp, 0);
98132796 DG	155	}
98132796 DG	156
145e52f3 DG	157	static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
145e52f3 DG	158	int *prot)
98132796	159	{
9986ed1e	160	target_ulong BATlt, BATut;
145e52f3	161	int i;
98132796 DG	162
98132796 DG	163	LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
145e52f3	164	rwx == 2 ? 'I' : 'D', ea);
91cda45b	165	if (rwx == 2) {
98132796 DG	166	BATlt = env->IBAT[1];
98132796 DG	167	BATut = env->IBAT[0];
91cda45b	168	} else {
98132796 DG	169	BATlt = env->DBAT[1];
98132796 DG	170	BATut = env->DBAT[0];
98132796 DG	171	}
98132796 DG	172	for (i = 0; i < env->nb_BATs; i++) {
9986ed1e DG	173	target_ulong batu = BATut[i];
9986ed1e DG	174	target_ulong batl = BATlt[i];
6fc76aa9	175	target_ulong mask;
9986ed1e	176
98132796	177	if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
6fc76aa9	178	mask = hash32_bat_601_size(env, batu, batl);
98132796	179	} else {
6fc76aa9	180	mask = hash32_bat_size(env, batu, batl);
98132796 DG	181	}
	182	LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
	183	" BATl " TARGET_FMT_lx "\n", __func__,
145e52f3 DG	184	type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl);
	185
	186	if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
	187	hwaddr raddr = (batl & mask) \| (ea & ~mask);
	188
	189	if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
	190	*prot = hash32_bat_601_prot(env, batu, batl);
	191	} else {
	192	*prot = hash32_bat_prot(env, batu, batl);
98132796	193	}
145e52f3 DG	194
145e52f3 DG	195	return raddr & TARGET_PAGE_MASK;
98132796 DG	196	}
98132796 DG	197	}
145e52f3 DG	198
145e52f3 DG	199	/* No hit */
98132796	200	#if defined(DEBUG_BATS)
145e52f3 DG	201	if (qemu_log_enabled()) {
	202	LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
	203	for (i = 0; i < 4; i++) {
	204	BATu = &BATut[i];
	205	BATl = &BATlt[i];
	206	BEPIu = *BATu & BATU32_BEPIU;
	207	BEPIl = *BATu & BATU32_BEPIL;
	208	bl = (*BATu & 0x00001FFC) << 15;
	209	LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
	210	" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
	211	TARGET_FMT_lx " " TARGET_FMT_lx "\n",
	212	__func__, type == ACCESS_CODE ? 'I' : 'D', i, ea,
	213	BATu, BATl, BEPIu, BEPIl, bl);
98132796	214	}
98132796	215	}
145e52f3 DG	216	#endif
	217
	218	return -1;
98132796 DG	219	}
98132796 DG	220
723ed73a DG	221	static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
	222	target_ulong eaddr, int rwx,
	223	hwaddr raddr, int prot)
	224	{
	225	int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
	226
	227	LOG_MMU("direct store...\n");
	228
	229	if ((sr & 0x1FF00000) >> 20 == 0x07f) {
	230	/* Memory-forced I/O controller interface access */
	231	/* If T=1 and BUID=x'07F', the 601 performs a memory access
	232	* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
	233	*/
	234	*raddr = ((sr & 0xF) << 28) \| (eaddr & 0x0FFFFFFF);
	235	*prot = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
	236	return 0;
	237	}
	238
	239	if (rwx == 2) {
	240	/* No code fetch is allowed in direct-store areas */
caa597bd DG	241	env->exception_index = POWERPC_EXCP_ISI;
	242	env->error_code = 0x10000000;
	243	return 1;
723ed73a DG	244	}
	245
	246	switch (env->access_type) {
	247	case ACCESS_INT:
	248	/* Integer load/store : only access allowed */
	249	break;
	250	case ACCESS_FLOAT:
	251	/* Floating point load/store */
caa597bd DG	252	env->exception_index = POWERPC_EXCP_ALIGN;
	253	env->error_code = POWERPC_EXCP_ALIGN_FP;
	254	env->spr[SPR_DAR] = eaddr;
	255	return 1;
723ed73a DG	256	case ACCESS_RES:
723ed73a DG	257	/* lwarx, ldarx or srwcx. */
caa597bd DG	258	env->error_code = 0;
	259	env->spr[SPR_DAR] = eaddr;
	260	if (rwx == 1) {
	261	env->spr[SPR_DSISR] = 0x06000000;
	262	} else {
	263	env->spr[SPR_DSISR] = 0x04000000;
	264	}
	265	return 1;
723ed73a DG	266	case ACCESS_CACHE:
	267	/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
	268	/* Should make the instruction do no-op.
	269	* As it already do no-op, it's quite easy :-)
	270	*/
	271	*raddr = eaddr;
	272	return 0;
	273	case ACCESS_EXT:
	274	/* eciwx or ecowx */
caa597bd DG	275	env->exception_index = POWERPC_EXCP_DSI;
	276	env->error_code = 0;
	277	env->spr[SPR_DAR] = eaddr;
	278	if (rwx == 1) {
	279	env->spr[SPR_DSISR] = 0x06100000;
	280	} else {
	281	env->spr[SPR_DSISR] = 0x04100000;
	282	}
	283	return 1;
723ed73a DG	284	default:
	285	qemu_log("ERROR: instruction should not need "
	286	"address translation\n");
caa597bd	287	abort();
723ed73a DG	288	}
	289	if ((rwx == 1 \|\| key != 1) && (rwx == 0 \|\| key != 0)) {
	290	*raddr = eaddr;
caa597bd	291	return 0;
723ed73a	292	} else {
caa597bd DG	293	env->exception_index = POWERPC_EXCP_DSI;
	294	env->error_code = 0;
	295	env->spr[SPR_DAR] = eaddr;
	296	if (rwx == 1) {
	297	env->spr[SPR_DSISR] = 0x0a000000;
	298	} else {
	299	env->spr[SPR_DSISR] = 0x08000000;
	300	}
	301	return 1;
723ed73a DG	302	}
	303	}
	304
59191721 DG	305	hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
59191721 DG	306	{
d5aea6f3	307	return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
59191721 DG	308	}
59191721 DG	309
aea390e4 DG	310	static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
	311	bool secondary, target_ulong ptem,
	312	ppc_hash_pte32_t *pte)
	313	{
	314	hwaddr pte_offset = pteg_off;
	315	target_ulong pte0, pte1;
	316	int i;
	317
	318	for (i = 0; i < HPTES_PER_GROUP; i++) {
	319	pte0 = ppc_hash32_load_hpte0(env, pte_offset);
	320	pte1 = ppc_hash32_load_hpte1(env, pte_offset);
	321
	322	if ((pte0 & HPTE32_V_VALID)
	323	&& (secondary == !!(pte0 & HPTE32_V_SECONDARY))
	324	&& HPTE32_V_COMPARE(pte0, ptem)) {
	325	pte->pte0 = pte0;
	326	pte->pte1 = pte1;
	327	return pte_offset;
	328	}
	329
	330	pte_offset += HASH_PTE_SIZE_32;
	331	}
	332
	333	return -1;
	334	}
	335
7f3bdc2d DG	336	static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
	337	target_ulong sr, target_ulong eaddr,
	338	ppc_hash_pte32_t *pte)
c69b6151	339	{
aea390e4	340	hwaddr pteg_off, pte_offset;
a1ff751a DG	341	hwaddr hash;
a1ff751a DG	342	uint32_t vsid, pgidx, ptem;
c69b6151	343
a1ff751a	344	vsid = sr & SR32_VSID;
a1ff751a DG	345	pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
	346	hash = vsid ^ pgidx;
	347	ptem = (vsid << 7) \| (pgidx >> 10);
	348
	349	/* Page address translation */
	350	LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
	351	" hash " TARGET_FMT_plx "\n",
	352	env->htab_base, env->htab_mask, hash);
	353
	354	/* Primary PTEG lookup */
	355	LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
	356	" vsid=%" PRIx32 " ptem=%" PRIx32
	357	" hash=" TARGET_FMT_plx "\n",
	358	env->htab_base, env->htab_mask, vsid, ptem, hash);
	359	pteg_off = get_pteg_offset32(env, hash);
7f3bdc2d	360	pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
a1ff751a DG	361	if (pte_offset == -1) {
	362	/* Secondary PTEG lookup */
	363	LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
	364	" vsid=%" PRIx32 " api=%" PRIx32
	365	" hash=" TARGET_FMT_plx "\n", env->htab_base,
	366	env->htab_mask, vsid, ptem, ~hash);
	367	pteg_off = get_pteg_offset32(env, ~hash);
7f3bdc2d	368	pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
a1ff751a DG	369	}
a1ff751a DG	370
7f3bdc2d	371	return pte_offset;
c69b6151	372	}
0480884f	373
6d11d998 DG	374	static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
	375	target_ulong eaddr)
	376	{
75d5ec89	377	hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
6d11d998 DG	378	hwaddr mask = ~TARGET_PAGE_MASK;
	379
	380	return (rpn & ~mask) \| (eaddr & mask);
	381	}
	382
caa597bd DG	383	int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
caa597bd DG	384	int mmu_idx)
0480884f	385	{
a1ff751a	386	target_ulong sr;
7f3bdc2d DG	387	hwaddr pte_offset;
7f3bdc2d DG	388	ppc_hash_pte32_t pte;
caa597bd	389	int prot;
b3440746	390	uint32_t new_pte1;
e01b4445	391	const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
caa597bd	392	hwaddr raddr;
0480884f	393
6a980110 DG	394	assert((rwx == 0) \|\| (rwx == 1) \|\| (rwx == 2));
6a980110 DG	395
65d61643 DG	396	/* 1. Handle real mode accesses */
	397	if (((rwx == 2) && (msr_ir == 0)) \|\| ((rwx != 2) && (msr_dr == 0))) {
	398	/* Translation is off */
caa597bd DG	399	raddr = eaddr;
	400	tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
	401	PAGE_READ \| PAGE_WRITE \| PAGE_EXEC, mmu_idx,
	402	TARGET_PAGE_SIZE);
65d61643 DG	403	return 0;
	404	}
	405
	406	/* 2. Check Block Address Translation entries (BATs) */
	407	if (env->nb_BATs != 0) {
caa597bd DG	408	raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
	409	if (raddr != -1) {
	410	if (need_prot[rwx] & ~prot) {
	411	if (rwx == 2) {
	412	env->exception_index = POWERPC_EXCP_ISI;
	413	env->error_code = 0x08000000;
	414	} else {
	415	env->exception_index = POWERPC_EXCP_DSI;
	416	env->error_code = 0;
	417	env->spr[SPR_DAR] = eaddr;
	418	if (rwx == 1) {
	419	env->spr[SPR_DSISR] = 0x0a000000;
	420	} else {
	421	env->spr[SPR_DSISR] = 0x08000000;
	422	}
	423	}
	424	return 1;
e01b4445	425	}
caa597bd DG	426
	427	tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
	428	raddr & TARGET_PAGE_MASK, prot, mmu_idx,
	429	TARGET_PAGE_SIZE);
e01b4445	430	return 0;
65d61643 DG	431	}
	432	}
	433
4b9605a5	434	/* 3. Look up the Segment Register */
0480884f	435	sr = env->sr[eaddr >> 28];
4b9605a5	436
4b9605a5 DG	437	/* 4. Handle direct store segments */
4b9605a5 DG	438	if (sr & SR32_T) {
caa597bd DG	439	if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
	440	&raddr, &prot) == 0) {
	441	tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
	442	raddr & TARGET_PAGE_MASK, prot, mmu_idx,
	443	TARGET_PAGE_SIZE);
	444	return 0;
	445	} else {
	446	return 1;
	447	}
4b9605a5 DG	448	}
4b9605a5 DG	449
bb218042	450	/* 5. Check for segment level no-execute violation */
e01b4445	451	if ((rwx == 2) && (sr & SR32_NX)) {
caa597bd DG	452	env->exception_index = POWERPC_EXCP_ISI;
	453	env->error_code = 0x10000000;
	454	return 1;
bb218042	455	}
7f3bdc2d DG	456
	457	/* 6. Locate the PTE in the hash table */
	458	pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
	459	if (pte_offset == -1) {
caa597bd DG	460	if (rwx == 2) {
	461	env->exception_index = POWERPC_EXCP_ISI;
	462	env->error_code = 0x40000000;
	463	} else {
	464	env->exception_index = POWERPC_EXCP_DSI;
	465	env->error_code = 0;
	466	env->spr[SPR_DAR] = eaddr;
	467	if (rwx == 1) {
	468	env->spr[SPR_DSISR] = 0x42000000;
	469	} else {
	470	env->spr[SPR_DSISR] = 0x40000000;
	471	}
	472	}
	473
	474	return 1;
7f3bdc2d DG	475	}
	476	LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
	477
	478	/* 7. Check access permissions */
6a980110	479
caa597bd	480	prot = ppc_hash32_pte_prot(env, sr, pte);
6a980110	481
caa597bd	482	if (need_prot[rwx] & ~prot) {
6a980110 DG	483	/* Access right violation */
6a980110 DG	484	LOG_MMU("PTE access rejected\n");
caa597bd DG	485	if (rwx == 2) {
	486	env->exception_index = POWERPC_EXCP_ISI;
	487	env->error_code = 0x08000000;
	488	} else {
	489	env->exception_index = POWERPC_EXCP_DSI;
	490	env->error_code = 0;
	491	env->spr[SPR_DAR] = eaddr;
	492	if (rwx == 1) {
	493	env->spr[SPR_DSISR] = 0x0a000000;
	494	} else {
	495	env->spr[SPR_DSISR] = 0x08000000;
	496	}
	497	}
	498	return 1;
6a980110 DG	499	}
6a980110 DG	500
87dc3fd1 DG	501	LOG_MMU("PTE access granted !\n");
	502
	503	/* 8. Update PTE referenced and changed bits if necessary */
	504
b3440746 DG	505	new_pte1 = pte.pte1 \| HPTE32_R_R; /* set referenced bit */
	506	if (rwx == 1) {
	507	new_pte1 \|= HPTE32_R_C; /* set changed (dirty) bit */
	508	} else {
	509	/* Treat the page as read-only for now, so that a later write
	510	* will pass through this function again to set the C bit */
caa597bd	511	prot &= ~PAGE_WRITE;
b3440746 DG	512	}
	513
	514	if (new_pte1 != pte.pte1) {
	515	ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
7f3bdc2d	516	}
0480884f	517
6d11d998 DG	518	/* 9. Determine the real address from the PTE */
6d11d998 DG	519
caa597bd DG	520	raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
	521
	522	tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
	523	prot, mmu_idx, TARGET_PAGE_SIZE);
e01b4445 DG	524
e01b4445 DG	525	return 0;
0480884f	526	}
629bd516	527
5883d8b2	528	hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
f2ad6be8	529	{
5883d8b2 DG	530	target_ulong sr;
	531	hwaddr pte_offset;
	532	ppc_hash_pte32_t pte;
	533	int prot;
	534
	535	if (msr_dr == 0) {
	536	/* Translation is off */
	537	return eaddr;
	538	}
f2ad6be8	539
5883d8b2 DG	540	if (env->nb_BATs != 0) {
	541	hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
	542	if (raddr != -1) {
	543	return raddr;
	544	}
	545	}
	546
	547	sr = env->sr[eaddr >> 28];
	548
	549	if (sr & SR32_T) {
	550	/* FIXME: Add suitable debug support for Direct Store segments */
	551	return -1;
	552	}
	553
	554	pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
	555	if (pte_offset == -1) {
f2ad6be8 DG	556	return -1;
	557	}
	558
5883d8b2	559	return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
f2ad6be8	560	}