[qemu.git] / target-ppc / mmu-hash64.c

/*
 *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
 *
 *  Copyright (c) 2003-2007 Jocelyn Mayer
 *  Copyright (c) 2013 David Gibson, IBM Corporation
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "cpu.h"
#include "helper.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
#include "mmu-hash64.h"

//#define DEBUG_MMU
//#define DEBUG_SLB

#ifdef DEBUG_MMU
#  define LOG_MMU(...) qemu_log(__VA_ARGS__)
#  define LOG_MMU_STATE(env) log_cpu_state((env), 0)
#else
#  define LOG_MMU(...) do { } while (0)
#  define LOG_MMU_STATE(...) do { } while (0)
#endif

#ifdef DEBUG_SLB
#  define LOG_SLB(...) qemu_log(__VA_ARGS__)
#else
#  define LOG_SLB(...) do { } while (0)
#endif

struct mmu_ctx_hash64 {
    hwaddr raddr;      /* Real address              */
    int prot;                      /* Protection bits           */
    hwaddr hash[2];    /* Pagetable hash values     */
    target_ulong ptem;             /* Virtual segment ID | API  */
    int key;                       /* Access key                */
};

/*
 * SLB handling
 */

static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
{
    uint64_t esid_256M, esid_1T;
    int n;

    LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);

    esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
    esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;

    for (n = 0; n < env->slb_nr; n++) {
        ppc_slb_t *slb = &env->slb[n];

        LOG_SLB("%s: slot %d %016" PRIx64 " %016"
                    PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
        /* We check for 1T matches on all MMUs here - if the MMU
         * doesn't have 1T segment support, we will have prevented 1T
         * entries from being inserted in the slbmte code. */
        if (((slb->esid == esid_256M) &&
             ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
            || ((slb->esid == esid_1T) &&
                ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
            return slb;
        }
    }

    return NULL;
}

void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
{
    int i;
    uint64_t slbe, slbv;

    cpu_synchronize_state(env);

    cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
    for (i = 0; i < env->slb_nr; i++) {
        slbe = env->slb[i].esid;
        slbv = env->slb[i].vsid;
        if (slbe == 0 && slbv == 0) {
            continue;
        }
        cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
                    i, slbe, slbv);
    }
}

void helper_slbia(CPUPPCState *env)
{
    int n, do_invalidate;

    do_invalidate = 0;
    /* XXX: Warning: slbia never invalidates the first segment */
    for (n = 1; n < env->slb_nr; n++) {
        ppc_slb_t *slb = &env->slb[n];

        if (slb->esid & SLB_ESID_V) {
            slb->esid &= ~SLB_ESID_V;
            /* XXX: given the fact that segment size is 256 MB or 1TB,
             *      and we still don't have a tlb_flush_mask(env, n, mask)
             *      in QEMU, we just invalidate all TLBs
             */
            do_invalidate = 1;
        }
    }
    if (do_invalidate) {
        tlb_flush(env, 1);
    }
}

void helper_slbie(CPUPPCState *env, target_ulong addr)
{
    ppc_slb_t *slb;

    slb = slb_lookup(env, addr);
    if (!slb) {
        return;
    }

    if (slb->esid & SLB_ESID_V) {
        slb->esid &= ~SLB_ESID_V;

        /* XXX: given the fact that segment size is 256 MB or 1TB,
         *      and we still don't have a tlb_flush_mask(env, n, mask)
         *      in QEMU, we just invalidate all TLBs
         */
        tlb_flush(env, 1);
    }
}

int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
    int slot = rb & 0xfff;
    ppc_slb_t *slb = &env->slb[slot];

    if (rb & (0x1000 - env->slb_nr)) {
        return -1; /* Reserved bits set or slot too high */
    }
    if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
        return -1; /* Bad segment size */
    }
    if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
        return -1; /* 1T segment on MMU that doesn't support it */
    }

    /* Mask out the slot number as we store the entry */
    slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
    slb->vsid = rs;

    LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
            " %016" PRIx64 "\n", __func__, slot, rb, rs,
            slb->esid, slb->vsid);

    return 0;
}

static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
                             target_ulong *rt)
{
    int slot = rb & 0xfff;
    ppc_slb_t *slb = &env->slb[slot];

    if (slot >= env->slb_nr) {
        return -1;
    }

    *rt = slb->esid;
    return 0;
}

static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
                             target_ulong *rt)
{
    int slot = rb & 0xfff;
    ppc_slb_t *slb = &env->slb[slot];

    if (slot >= env->slb_nr) {
        return -1;
    }

    *rt = slb->vsid;
    return 0;
}

void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
    if (ppc_store_slb(env, rb, rs) < 0) {
        helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
                                   POWERPC_EXCP_INVAL);
    }
}

target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
{
    target_ulong rt = 0;

    if (ppc_load_slb_esid(env, rb, &rt) < 0) {
        helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
                                   POWERPC_EXCP_INVAL);
    }
    return rt;
}

target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
{
    target_ulong rt = 0;

    if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
        helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
                                   POWERPC_EXCP_INVAL);
    }
    return rt;
}

/*
 * 64-bit hash table MMU handling
 */

static int ppc_hash64_pp_check(int key, int pp, bool nx)
{
    int access;

    /* Compute access rights */
    /* When pp is 4, 5 or 7, the result is undefined. Set it to noaccess */
    access = 0;
    if (key == 0) {
        switch (pp) {
        case 0x0:
        case 0x1:
        case 0x2:
            access |= PAGE_WRITE;
            /* No break here */
        case 0x3:
        case 0x6:
            access |= PAGE_READ;
            break;
        }
    } else {
        switch (pp) {
        case 0x0:
        case 0x6:
            access = 0;
            break;
        case 0x1:
        case 0x3:
            access = PAGE_READ;
            break;
        case 0x2:
            access = PAGE_READ | PAGE_WRITE;
            break;
        }
    }
    if (!nx) {
        access |= PAGE_EXEC;
    }

    return access;
}

static int ppc_hash64_check_prot(int prot, int rwx)
{
    int ret;

    if (rwx == 2) {
        if (prot & PAGE_EXEC) {
            ret = 0;
        } else {
            ret = -2;
        }
    } else if (rwx == 1) {
        if (prot & PAGE_WRITE) {
            ret = 0;
        } else {
            ret = -2;
        }
    } else {
        if (prot & PAGE_READ) {
            ret = 0;
        } else {
            ret = -2;
        }
    }

    return ret;
}

static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0,
                       target_ulong pte1, int rwx)
{
    int access, ret, pp;
    bool nx;

    pp = (pte1 & HPTE64_R_PP) | ((pte1 & HPTE64_R_PP0) >> 61);
    /* No execute if either noexec or guarded bits set */
    nx = (pte1 & HPTE64_R_N) || (pte1 & HPTE64_R_G);
    /* Compute access rights */
    access = ppc_hash64_pp_check(ctx->key, pp, nx);
    /* Keep the matching PTE informations */
    ctx->raddr = pte1;
    ctx->prot = access;
    ret = ppc_hash64_check_prot(ctx->prot, rwx);
    if (ret == 0) {
        /* Access granted */
        LOG_MMU("PTE access granted !\n");
    } else {
        /* Access right violation */
        LOG_MMU("PTE access rejected\n");
    }

    return ret;
}

static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx,
                                       uint64_t *pte1p, int ret, int rw)
{
    int store = 0;

    /* Update page flags */
    if (!(*pte1p & HPTE64_R_R)) {
        /* Update accessed flag */
        *pte1p |= HPTE64_R_R;
        store = 1;
    }
    if (!(*pte1p & HPTE64_R_C)) {
        if (rw == 1 && ret == 0) {
            /* Update changed flag */
            *pte1p |= HPTE64_R_C;
            store = 1;
        } else {
            /* Force page fault for first write access */
            ctx->prot &= ~PAGE_WRITE;
        }
    }

    return store;
}

static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr pteg_off,
                                     bool secondary, target_ulong ptem,
                                     ppc_hash_pte64_t *pte)
{
    hwaddr pte_offset = pteg_off;
    target_ulong pte0, pte1;
    int i;

    for (i = 0; i < HPTES_PER_GROUP; i++) {
        pte0 = ppc_hash64_load_hpte0(env, pte_offset);
        pte1 = ppc_hash64_load_hpte1(env, pte_offset);

        if ((pte0 & HPTE64_V_VALID)
            && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
            && HPTE64_V_COMPARE(pte0, ptem)) {
            pte->pte0 = pte0;
            pte->pte1 = pte1;
            return pte_offset;
        }

        pte_offset += HASH_PTE_SIZE_64;
    }

    return -1;
}

static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
                      target_ulong eaddr, int h, int rwx, int target_page_bits)
{
    hwaddr pteg_off, pte_offset;
    ppc_hash_pte64_t pte;
    int ret;

    ret = -1; /* No entry found */
    pteg_off = (ctx->hash[h] * HASH_PTEG_SIZE_64) & env->htab_mask;
    pte_offset = ppc_hash64_pteg_search(env, pteg_off, h, ctx->ptem, &pte);
    if (pte_offset != -1) {
        ret = pte64_check(ctx, pte.pte0, pte.pte1, rwx);
        LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
                ctx->raddr, ctx->prot, ret);
        /* Update page flags */
        if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
            ppc_hash64_store_hpte1(env, pte_offset, pte.pte1);
        }
    }

    /* We have a TLB that saves 4K pages, so let's
     * split a huge page to 4k chunks */
    if (target_page_bits != TARGET_PAGE_BITS) {
        ctx->raddr |= (eaddr & ((1 << target_page_bits) - 1))
                      & TARGET_PAGE_MASK;
    }
    return ret;
}

static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
                                target_ulong eaddr, int rwx)
{
    hwaddr hash;
    target_ulong vsid;
    int pr, target_page_bits;
    int ret, ret2;
    ppc_slb_t *slb;
    target_ulong pageaddr;
    int segment_bits;

    /* 1. Handle real mode accesses */
    if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
        /* Translation is off */
        /* In real mode the top 4 effective address bits are ignored */
        ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
        ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
        return 0;
    }

    /* 2. Translation is on, so look up the SLB */
    slb = slb_lookup(env, eaddr);

    if (!slb) {
        return -5;
    }

    /* 3. Check for segment level no-execute violation */
    if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
        return -3;
    }

    pr = msr_pr;

    if (slb->vsid & SLB_VSID_B) {
        vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
        segment_bits = 40;
    } else {
        vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
        segment_bits = 28;
    }

    target_page_bits = (slb->vsid & SLB_VSID_L)
        ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
    ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)
                  : (slb->vsid & SLB_VSID_KS));

    pageaddr = eaddr & ((1ULL << segment_bits)
                            - (1ULL << target_page_bits));
    if (slb->vsid & SLB_VSID_B) {
        hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits);
    } else {
        hash = vsid ^ (pageaddr >> target_page_bits);
    }
    /* Only 5 bits of the page index are used in the AVPN */
    ctx->ptem = (slb->vsid & SLB_VSID_PTEM) |
        ((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));

    LOG_MMU("pte segment: key=%d nx %d vsid " TARGET_FMT_lx "\n",
            ctx->key, !!(slb->vsid & SLB_VSID_N), vsid);
    ret = -1;

    /* Page address translation */
    LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
            " hash " TARGET_FMT_plx "\n",
            env->htab_base, env->htab_mask, hash);
    ctx->hash[0] = hash;
    ctx->hash[1] = ~hash;

    LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
            " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
            " hash=" TARGET_FMT_plx "\n",
            env->htab_base, env->htab_mask, vsid, ctx->ptem,
            ctx->hash[0]);
    /* Primary table lookup */
    ret = find_pte64(env, ctx, eaddr, 0, rwx, target_page_bits);
    if (ret == -1) {
        /* Secondary table lookup */
        LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
                " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
                " hash=" TARGET_FMT_plx "\n", env->htab_base,
                env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
        ret2 = find_pte64(env, ctx, eaddr, 1, rwx, target_page_bits);
        if (ret2 != -1) {
            ret = ret2;
        }
    }

    return ret;
}

hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
{
    struct mmu_ctx_hash64 ctx;

    if (unlikely(ppc_hash64_translate(env, &ctx, addr, 0) != 0)) {
        return -1;
    }

    return ctx.raddr & TARGET_PAGE_MASK;
}

int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx,
                                int mmu_idx)
{
    struct mmu_ctx_hash64 ctx;
    int ret = 0;

    ret = ppc_hash64_translate(env, &ctx, address, rwx);
    if (ret == 0) {
        tlb_set_page(env, address & TARGET_PAGE_MASK,
                     ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
                     mmu_idx, TARGET_PAGE_SIZE);
        ret = 0;
    } else if (ret < 0) {
        LOG_MMU_STATE(env);
        if (rwx == 2) {
            switch (ret) {
            case -1:
                env->exception_index = POWERPC_EXCP_ISI;
                env->error_code = 0x40000000;
                break;
            case -2:
                /* Access rights violation */
                env->exception_index = POWERPC_EXCP_ISI;
                env->error_code = 0x08000000;
                break;
            case -3:
                /* No execute protection violation */
                env->exception_index = POWERPC_EXCP_ISI;
                env->error_code = 0x10000000;
                break;
            case -5:
                /* No match in segment table */
                env->exception_index = POWERPC_EXCP_ISEG;
                env->error_code = 0;
                break;
            }
        } else {
            switch (ret) {
            case -1:
                /* No matches in page tables or TLB */
                env->exception_index = POWERPC_EXCP_DSI;
                env->error_code = 0;
                env->spr[SPR_DAR] = address;
                if (rwx == 1) {
                    env->spr[SPR_DSISR] = 0x42000000;
                } else {
                    env->spr[SPR_DSISR] = 0x40000000;
                }
                break;
            case -2:
                /* Access rights violation */
                env->exception_index = POWERPC_EXCP_DSI;
                env->error_code = 0;
                env->spr[SPR_DAR] = address;
                if (rwx == 1) {
                    env->spr[SPR_DSISR] = 0x0A000000;
                } else {
                    env->spr[SPR_DSISR] = 0x08000000;
                }
                break;
            case -5:
                /* No match in segment table */
                env->exception_index = POWERPC_EXCP_DSEG;
                env->error_code = 0;
                env->spr[SPR_DAR] = address;
                break;
            }
        }
#if 0
        printf("%s: set exception to %d %02x\n", __func__,
               env->exception, env->error_code);
#endif
        ret = 1;
    }

    return ret;
}
Commit	Line	Data
10b46525 DG	1	/*
	2	* PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
	3	*
	4	* Copyright (c) 2003-2007 Jocelyn Mayer
	5	* Copyright (c) 2013 David Gibson, IBM Corporation
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20	#include "cpu.h"
	21	#include "helper.h"
	22	#include "sysemu/kvm.h"
	23	#include "kvm_ppc.h"
	24	#include "mmu-hash64.h"
	25
9d7c3f4a	26	//#define DEBUG_MMU
10b46525 DG	27	//#define DEBUG_SLB
10b46525 DG	28
9d7c3f4a DG	29	#ifdef DEBUG_MMU
	30	# define LOG_MMU(...) qemu_log(__VA_ARGS__)
	31	# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
	32	#else
	33	# define LOG_MMU(...) do { } while (0)
	34	# define LOG_MMU_STATE(...) do { } while (0)
	35	#endif
	36
10b46525 DG	37	#ifdef DEBUG_SLB
	38	# define LOG_SLB(...) qemu_log(__VA_ARGS__)
	39	#else
	40	# define LOG_SLB(...) do { } while (0)
	41	#endif
	42
5dc68eb0 DG	43	struct mmu_ctx_hash64 {
5dc68eb0 DG	44	hwaddr raddr; /* Real address */
5dc68eb0 DG	45	int prot; /* Protection bits */
	46	hwaddr hash[2]; /* Pagetable hash values */
	47	target_ulong ptem; /* Virtual segment ID \| API */
	48	int key; /* Access key */
5dc68eb0 DG	49	};
5dc68eb0 DG	50
10b46525 DG	51	/*
	52	* SLB handling
	53	*/
	54
0480884f	55	static ppc_slb_t slb_lookup(CPUPPCState env, target_ulong eaddr)
10b46525 DG	56	{
	57	uint64_t esid_256M, esid_1T;
	58	int n;
	59
	60	LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
	61
	62	esid_256M = (eaddr & SEGMENT_MASK_256M) \| SLB_ESID_V;
	63	esid_1T = (eaddr & SEGMENT_MASK_1T) \| SLB_ESID_V;
	64
	65	for (n = 0; n < env->slb_nr; n++) {
	66	ppc_slb_t *slb = &env->slb[n];
	67
	68	LOG_SLB("%s: slot %d %016" PRIx64 " %016"
	69	PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
	70	/* We check for 1T matches on all MMUs here - if the MMU
	71	* doesn't have 1T segment support, we will have prevented 1T
	72	* entries from being inserted in the slbmte code. */
	73	if (((slb->esid == esid_256M) &&
	74	((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
	75	\|\| ((slb->esid == esid_1T) &&
	76	((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
	77	return slb;
	78	}
	79	}
	80
	81	return NULL;
	82	}
	83
	84	void dump_slb(FILE f, fprintf_function cpu_fprintf, CPUPPCState env)
	85	{
	86	int i;
	87	uint64_t slbe, slbv;
	88
	89	cpu_synchronize_state(env);
	90
	91	cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
	92	for (i = 0; i < env->slb_nr; i++) {
	93	slbe = env->slb[i].esid;
	94	slbv = env->slb[i].vsid;
	95	if (slbe == 0 && slbv == 0) {
	96	continue;
	97	}
	98	cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
	99	i, slbe, slbv);
	100	}
	101	}
	102
	103	void helper_slbia(CPUPPCState *env)
	104	{
	105	int n, do_invalidate;
	106
	107	do_invalidate = 0;
	108	/* XXX: Warning: slbia never invalidates the first segment */
	109	for (n = 1; n < env->slb_nr; n++) {
	110	ppc_slb_t *slb = &env->slb[n];
	111
	112	if (slb->esid & SLB_ESID_V) {
	113	slb->esid &= ~SLB_ESID_V;
	114	/* XXX: given the fact that segment size is 256 MB or 1TB,
	115	* and we still don't have a tlb_flush_mask(env, n, mask)
	116	* in QEMU, we just invalidate all TLBs
	117	*/
	118	do_invalidate = 1;
	119	}
120	}
121	if (do_invalidate) {
122	tlb_flush(env, 1);
123	}
124	}
125
126	void helper_slbie(CPUPPCState *env, target_ulong addr)
127	{
128	ppc_slb_t *slb;
129
130	slb = slb_lookup(env, addr);
131	if (!slb) {
132	return;
133	}
134
135	if (slb->esid & SLB_ESID_V) {
136	slb->esid &= ~SLB_ESID_V;
137
138	/* XXX: given the fact that segment size is 256 MB or 1TB,
139	* and we still don't have a tlb_flush_mask(env, n, mask)
140	* in QEMU, we just invalidate all TLBs
141	*/
142	tlb_flush(env, 1);
143	}
144	}
145
146	int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
147	{
148	int slot = rb & 0xfff;
149	ppc_slb_t *slb = &env->slb[slot];
150
151	if (rb & (0x1000 - env->slb_nr)) {
152	return -1; /* Reserved bits set or slot too high */
153	}
154	if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
155	return -1; /* Bad segment size */
156	}
157	if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
158	return -1; /* 1T segment on MMU that doesn't support it */
159	}
160
161	/* Mask out the slot number as we store the entry */
162	slb->esid = rb & (SLB_ESID_ESID \| SLB_ESID_V);
163	slb->vsid = rs;
164
165	LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
166	" %016" PRIx64 "\n", __func__, slot, rb, rs,
167	slb->esid, slb->vsid);
168
169	return 0;
170	}
171
172	static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
173	target_ulong *rt)
174	{
175	int slot = rb & 0xfff;
176	ppc_slb_t *slb = &env->slb[slot];
177
178	if (slot >= env->slb_nr) {
179	return -1;
180	}
181
182	*rt = slb->esid;
183	return 0;
184	}
185
186	static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
187	target_ulong *rt)
188	{
189	int slot = rb & 0xfff;
190	ppc_slb_t *slb = &env->slb[slot];
191
192	if (slot >= env->slb_nr) {
193	return -1;
194	}
195
196	*rt = slb->vsid;
197	return 0;
198	}
199
200	void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
201	{
202	if (ppc_store_slb(env, rb, rs) < 0) {
203	helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
204	POWERPC_EXCP_INVAL);
205	}
206	}
207
208	target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
209	{
210	target_ulong rt = 0;
211
212	if (ppc_load_slb_esid(env, rb, &rt) < 0) {
213	helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
214	POWERPC_EXCP_INVAL);
215	}
216	return rt;
217	}
218
219	target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
220	{
221	target_ulong rt = 0;
222
223	if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
224	helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
225	POWERPC_EXCP_INVAL);
226	}
227	return rt;
228	}
9d7c3f4a DG	229
	230	/*
	231	* 64-bit hash table MMU handling
	232	*/
	233
ba36ed10	234	static int ppc_hash64_pp_check(int key, int pp, bool nx)
496272a7 DG	235	{
	236	int access;
	237
	238	/* Compute access rights */
	239	/* When pp is 4, 5 or 7, the result is undefined. Set it to noaccess */
	240	access = 0;
	241	if (key == 0) {
	242	switch (pp) {
	243	case 0x0:
	244	case 0x1:
	245	case 0x2:
	246	access \|= PAGE_WRITE;
	247	/* No break here */
	248	case 0x3:
	249	case 0x6:
	250	access \|= PAGE_READ;
	251	break;
	252	}
	253	} else {
	254	switch (pp) {
	255	case 0x0:
	256	case 0x6:
	257	access = 0;
	258	break;
	259	case 0x1:
	260	case 0x3:
	261	access = PAGE_READ;
	262	break;
	263	case 0x2:
	264	access = PAGE_READ \| PAGE_WRITE;
	265	break;
	266	}
	267	}
ba36ed10	268	if (!nx) {
496272a7 DG	269	access \|= PAGE_EXEC;
	270	}
	271
	272	return access;
	273	}
	274
91cda45b	275	static int ppc_hash64_check_prot(int prot, int rwx)
496272a7 DG	276	{
	277	int ret;
	278
91cda45b	279	if (rwx == 2) {
496272a7 DG	280	if (prot & PAGE_EXEC) {
	281	ret = 0;
	282	} else {
	283	ret = -2;
	284	}
91cda45b	285	} else if (rwx == 1) {
496272a7 DG	286	if (prot & PAGE_WRITE) {
	287	ret = 0;
	288	} else {
	289	ret = -2;
	290	}
	291	} else {
	292	if (prot & PAGE_READ) {
	293	ret = 0;
	294	} else {
	295	ret = -2;
	296	}
	297	}
	298
	299	return ret;
	300	}
	301
5dc68eb0	302	static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0,
f95d7cc7	303	target_ulong pte1, int rwx)
9d7c3f4a	304	{
d5aea6f3	305	int access, ret, pp;
f95d7cc7	306	bool nx;
9d7c3f4a	307
f95d7cc7 DG	308	pp = (pte1 & HPTE64_R_PP) \| ((pte1 & HPTE64_R_PP0) >> 61);
	309	/* No execute if either noexec or guarded bits set */
	310	nx = (pte1 & HPTE64_R_N) \|\| (pte1 & HPTE64_R_G);
	311	/* Compute access rights */
	312	access = ppc_hash64_pp_check(ctx->key, pp, nx);
	313	/* Keep the matching PTE informations */
	314	ctx->raddr = pte1;
	315	ctx->prot = access;
	316	ret = ppc_hash64_check_prot(ctx->prot, rwx);
	317	if (ret == 0) {
	318	/* Access granted */
	319	LOG_MMU("PTE access granted !\n");
	320	} else {
	321	/* Access right violation */
	322	LOG_MMU("PTE access rejected\n");
9d7c3f4a DG	323	}
	324
	325	return ret;
	326	}
c69b6151	327
5dc68eb0	328	static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx,
aea390e4	329	uint64_t *pte1p, int ret, int rw)
496272a7 DG	330	{
	331	int store = 0;
	332
	333	/* Update page flags */
d5aea6f3	334	if (!(*pte1p & HPTE64_R_R)) {
496272a7	335	/* Update accessed flag */
d5aea6f3	336	*pte1p \|= HPTE64_R_R;
496272a7 DG	337	store = 1;
496272a7 DG	338	}
d5aea6f3	339	if (!(*pte1p & HPTE64_R_C)) {
496272a7 DG	340	if (rw == 1 && ret == 0) {
496272a7 DG	341	/* Update changed flag */
d5aea6f3	342	*pte1p \|= HPTE64_R_C;
496272a7 DG	343	store = 1;
	344	} else {
	345	/* Force page fault for first write access */
	346	ctx->prot &= ~PAGE_WRITE;
	347	}
	348	}
	349
	350	return store;
	351	}
	352
aea390e4 DG	353	static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr pteg_off,
	354	bool secondary, target_ulong ptem,
	355	ppc_hash_pte64_t *pte)
	356	{
	357	hwaddr pte_offset = pteg_off;
	358	target_ulong pte0, pte1;
	359	int i;
	360
	361	for (i = 0; i < HPTES_PER_GROUP; i++) {
	362	pte0 = ppc_hash64_load_hpte0(env, pte_offset);
	363	pte1 = ppc_hash64_load_hpte1(env, pte_offset);
	364
	365	if ((pte0 & HPTE64_V_VALID)
	366	&& (secondary == !!(pte0 & HPTE64_V_SECONDARY))
	367	&& HPTE64_V_COMPARE(pte0, ptem)) {
	368	pte->pte0 = pte0;
	369	pte->pte1 = pte1;
	370	return pte_offset;
	371	}
	372
	373	pte_offset += HASH_PTE_SIZE_64;
	374	}
	375
	376	return -1;
	377	}
	378
f078cd46 DG	379	static int find_pte64(CPUPPCState env, struct mmu_ctx_hash64 ctx,
f078cd46 DG	380	target_ulong eaddr, int h, int rwx, int target_page_bits)
c69b6151	381	{
aea390e4 DG	382	hwaddr pteg_off, pte_offset;
aea390e4 DG	383	ppc_hash_pte64_t pte;
f95d7cc7	384	int ret;
c69b6151 DG	385
c69b6151 DG	386	ret = -1; /* No entry found */
d5aea6f3	387	pteg_off = (ctx->hash[h] * HASH_PTEG_SIZE_64) & env->htab_mask;
aea390e4 DG	388	pte_offset = ppc_hash64_pteg_search(env, pteg_off, h, ctx->ptem, &pte);
	389	if (pte_offset != -1) {
	390	ret = pte64_check(ctx, pte.pte0, pte.pte1, rwx);
c69b6151 DG	391	LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
	392	ctx->raddr, ctx->prot, ret);
	393	/* Update page flags */
aea390e4 DG	394	if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
aea390e4 DG	395	ppc_hash64_store_hpte1(env, pte_offset, pte.pte1);
c69b6151 DG	396	}
	397	}
	398
	399	/* We have a TLB that saves 4K pages, so let's
	400	* split a huge page to 4k chunks */
	401	if (target_page_bits != TARGET_PAGE_BITS) {
f078cd46	402	ctx->raddr \|= (eaddr & ((1 << target_page_bits) - 1))
c69b6151 DG	403	& TARGET_PAGE_MASK;
	404	}
	405	return ret;
	406	}
0480884f	407
65d61643 DG	408	static int ppc_hash64_translate(CPUPPCState env, struct mmu_ctx_hash64 ctx,
65d61643 DG	409	target_ulong eaddr, int rwx)
0480884f DG	410	{
	411	hwaddr hash;
	412	target_ulong vsid;
	413	int pr, target_page_bits;
	414	int ret, ret2;
0480884f DG	415	ppc_slb_t *slb;
	416	target_ulong pageaddr;
	417	int segment_bits;
	418
65d61643 DG	419	/* 1. Handle real mode accesses */
	420	if (((rwx == 2) && (msr_ir == 0)) \|\| ((rwx != 2) && (msr_dr == 0))) {
	421	/* Translation is off */
	422	/* In real mode the top 4 effective address bits are ignored */
	423	ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
	424	ctx->prot = PAGE_READ \| PAGE_EXEC \| PAGE_WRITE;
	425	return 0;
	426	}
	427
bb218042	428	/* 2. Translation is on, so look up the SLB */
0480884f	429	slb = slb_lookup(env, eaddr);
bb218042	430
0480884f DG	431	if (!slb) {
	432	return -5;
	433	}
	434
bb218042 DG	435	/* 3. Check for segment level no-execute violation */
	436	if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
	437	return -3;
	438	}
	439
	440	pr = msr_pr;
	441
0480884f DG	442	if (slb->vsid & SLB_VSID_B) {
	443	vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
	444	segment_bits = 40;
	445	} else {
	446	vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
	447	segment_bits = 28;
	448	}
	449
	450	target_page_bits = (slb->vsid & SLB_VSID_L)
	451	? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
	452	ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)
	453	: (slb->vsid & SLB_VSID_KS));
0480884f DG	454
	455	pageaddr = eaddr & ((1ULL << segment_bits)
	456	- (1ULL << target_page_bits));
	457	if (slb->vsid & SLB_VSID_B) {
	458	hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits);
	459	} else {
	460	hash = vsid ^ (pageaddr >> target_page_bits);
	461	}
	462	/* Only 5 bits of the page index are used in the AVPN */
	463	ctx->ptem = (slb->vsid & SLB_VSID_PTEM) \|
	464	((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
	465
	466	LOG_MMU("pte segment: key=%d nx %d vsid " TARGET_FMT_lx "\n",
ba36ed10	467	ctx->key, !!(slb->vsid & SLB_VSID_N), vsid);
0480884f DG	468	ret = -1;
0480884f DG	469
bb218042 DG	470	/* Page address translation */
	471	LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
	472	" hash " TARGET_FMT_plx "\n",
	473	env->htab_base, env->htab_mask, hash);
	474	ctx->hash[0] = hash;
	475	ctx->hash[1] = ~hash;
	476
bb218042 DG	477	LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
	478	" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
	479	" hash=" TARGET_FMT_plx "\n",
	480	env->htab_base, env->htab_mask, vsid, ctx->ptem,
	481	ctx->hash[0]);
	482	/* Primary table lookup */
	483	ret = find_pte64(env, ctx, eaddr, 0, rwx, target_page_bits);
f95d7cc7	484	if (ret == -1) {
bb218042 DG	485	/* Secondary table lookup */
	486	LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
	487	" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
	488	" hash=" TARGET_FMT_plx "\n", env->htab_base,
	489	env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
	490	ret2 = find_pte64(env, ctx, eaddr, 1, rwx, target_page_bits);
	491	if (ret2 != -1) {
	492	ret = ret2;
0480884f	493	}
0480884f DG	494	}
	495
	496	return ret;
	497	}
629bd516	498
f2ad6be8 DG	499	hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
f2ad6be8 DG	500	{
5dc68eb0	501	struct mmu_ctx_hash64 ctx;
f2ad6be8	502
65d61643	503	if (unlikely(ppc_hash64_translate(env, &ctx, addr, 0) != 0)) {
f2ad6be8 DG	504	return -1;
	505	}
	506
	507	return ctx.raddr & TARGET_PAGE_MASK;
	508	}
	509
91cda45b	510	int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx,
25de24ab DG	511	int mmu_idx)
25de24ab DG	512	{
5dc68eb0	513	struct mmu_ctx_hash64 ctx;
25de24ab DG	514	int ret = 0;
25de24ab DG	515
65d61643	516	ret = ppc_hash64_translate(env, &ctx, address, rwx);
25de24ab DG	517	if (ret == 0) {
	518	tlb_set_page(env, address & TARGET_PAGE_MASK,
	519	ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
	520	mmu_idx, TARGET_PAGE_SIZE);
	521	ret = 0;
	522	} else if (ret < 0) {
	523	LOG_MMU_STATE(env);
91cda45b	524	if (rwx == 2) {
25de24ab DG	525	switch (ret) {
	526	case -1:
	527	env->exception_index = POWERPC_EXCP_ISI;
	528	env->error_code = 0x40000000;
	529	break;
	530	case -2:
	531	/* Access rights violation */
	532	env->exception_index = POWERPC_EXCP_ISI;
	533	env->error_code = 0x08000000;
	534	break;
	535	case -3:
	536	/* No execute protection violation */
	537	env->exception_index = POWERPC_EXCP_ISI;
	538	env->error_code = 0x10000000;
	539	break;
	540	case -5:
	541	/* No match in segment table */
	542	env->exception_index = POWERPC_EXCP_ISEG;
	543	env->error_code = 0;
	544	break;
	545	}
	546	} else {
	547	switch (ret) {
	548	case -1:
	549	/* No matches in page tables or TLB */
	550	env->exception_index = POWERPC_EXCP_DSI;
	551	env->error_code = 0;
	552	env->spr[SPR_DAR] = address;
91cda45b	553	if (rwx == 1) {
25de24ab DG	554	env->spr[SPR_DSISR] = 0x42000000;
	555	} else {
	556	env->spr[SPR_DSISR] = 0x40000000;
	557	}
	558	break;
	559	case -2:
	560	/* Access rights violation */
	561	env->exception_index = POWERPC_EXCP_DSI;
	562	env->error_code = 0;
	563	env->spr[SPR_DAR] = address;
91cda45b	564	if (rwx == 1) {
25de24ab DG	565	env->spr[SPR_DSISR] = 0x0A000000;
	566	} else {
	567	env->spr[SPR_DSISR] = 0x08000000;
	568	}
	569	break;
	570	case -5:
	571	/* No match in segment table */
	572	env->exception_index = POWERPC_EXCP_DSEG;
	573	env->error_code = 0;
	574	env->spr[SPR_DAR] = address;
	575	break;
	576	}
	577	}
	578	#if 0
	579	printf("%s: set exception to %d %02x\n", __func__,
	580	env->exception, env->error_code);
	581	#endif
	582	ret = 1;
	583	}
	584
	585	return ret;
	586	}