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target-ppc: convert POWER bridge instructions to TCG
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation micro-operations for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
a541f297
FB
21//#define DEBUG_OP
22
79aceca5
FB
23#include "config.h"
24#include "exec.h"
603fccce 25#include "host-utils.h"
0411a972 26#include "helper_regs.h"
76a66253 27#include "op_helper.h"
79aceca5 28
76a66253
JM
29#if !defined(CONFIG_USER_ONLY)
30/* Segment registers load and store */
36081602 31void OPPROTO op_load_sr (void)
76a66253 32{
36081602 33 T0 = env->sr[T1];
76a66253
JM
34 RETURN();
35}
36
36081602 37void OPPROTO op_store_sr (void)
76a66253
JM
38{
39 do_store_sr(env, T1, T0);
40 RETURN();
41}
42
12de9a39
JM
43#if defined(TARGET_PPC64)
44void OPPROTO op_load_slb (void)
45{
46 T0 = ppc_load_slb(env, T1);
47 RETURN();
48}
49
50void OPPROTO op_store_slb (void)
51{
52 ppc_store_slb(env, T1, T0);
53 RETURN();
54}
55#endif /* defined(TARGET_PPC64) */
56
36081602 57void OPPROTO op_load_sdr1 (void)
76a66253 58{
36081602 59 T0 = env->sdr1;
76a66253
JM
60 RETURN();
61}
62
36081602 63void OPPROTO op_store_sdr1 (void)
76a66253
JM
64{
65 do_store_sdr1(env, T0);
79aceca5
FB
66 RETURN();
67}
68
d9bce9d9
JM
69#if defined (TARGET_PPC64)
70void OPPROTO op_load_asr (void)
71{
72 T0 = env->asr;
73 RETURN();
74}
75
76void OPPROTO op_store_asr (void)
77{
78 ppc_store_asr(env, T0);
79 RETURN();
80}
81#endif
82
6676f424
AJ
83void OPPROTO op_load_msr (void)
84{
85 T0 = env->msr;
86 RETURN();
87}
88
89void OPPROTO op_store_msr (void)
90{
91 do_store_msr();
92 RETURN();
93}
94
95#if defined (TARGET_PPC64)
96void OPPROTO op_store_msr_32 (void)
97{
98 T0 = (env->msr & ~0xFFFFFFFFULL) | (T0 & 0xFFFFFFFF);
99 do_store_msr();
100 RETURN();
101}
102#endif
103
0411a972 104void OPPROTO op_update_riee (void)
d9bce9d9 105{
0411a972
JM
106 /* We don't call do_store_msr here as we won't trigger
107 * any special case nor change hflags
108 */
109 T0 &= (1 << MSR_RI) | (1 << MSR_EE);
110 env->msr &= ~(1 << MSR_RI) | (1 << MSR_EE);
111 env->msr |= T0;
d9bce9d9
JM
112 RETURN();
113}
114#endif
9a64fbe4
FB
115
116/* SPR */
a496775f
JM
117void OPPROTO op_load_spr (void)
118{
119 T0 = env->spr[PARAM1];
120 RETURN();
121}
122
123void OPPROTO op_store_spr (void)
124{
125 env->spr[PARAM1] = T0;
126 RETURN();
127}
128
129void OPPROTO op_load_dump_spr (void)
130{
131 T0 = ppc_load_dump_spr(PARAM1);
132 RETURN();
133}
134
135void OPPROTO op_store_dump_spr (void)
9a64fbe4 136{
a496775f 137 ppc_store_dump_spr(PARAM1, T0);
9a64fbe4
FB
138 RETURN();
139}
140
a496775f 141void OPPROTO op_mask_spr (void)
9a64fbe4 142{
a496775f 143 env->spr[PARAM1] &= ~T0;
79aceca5
FB
144 RETURN();
145}
146
36081602 147void OPPROTO op_load_tbl (void)
9a64fbe4 148{
36081602 149 T0 = cpu_ppc_load_tbl(env);
9a64fbe4
FB
150 RETURN();
151}
152
36081602 153void OPPROTO op_load_tbu (void)
9a64fbe4 154{
36081602 155 T0 = cpu_ppc_load_tbu(env);
9a64fbe4
FB
156 RETURN();
157}
158
a062e36c
JM
159void OPPROTO op_load_atbl (void)
160{
161 T0 = cpu_ppc_load_atbl(env);
162 RETURN();
163}
164
165void OPPROTO op_load_atbu (void)
166{
167 T0 = cpu_ppc_load_atbu(env);
168 RETURN();
169}
170
76a66253 171#if !defined(CONFIG_USER_ONLY)
36081602 172void OPPROTO op_store_tbl (void)
9a64fbe4 173{
36081602 174 cpu_ppc_store_tbl(env, T0);
79aceca5
FB
175 RETURN();
176}
177
36081602 178void OPPROTO op_store_tbu (void)
9a64fbe4 179{
36081602 180 cpu_ppc_store_tbu(env, T0);
9a64fbe4
FB
181 RETURN();
182}
183
a062e36c
JM
184void OPPROTO op_store_atbl (void)
185{
186 cpu_ppc_store_atbl(env, T0);
187 RETURN();
188}
189
190void OPPROTO op_store_atbu (void)
191{
192 cpu_ppc_store_atbu(env, T0);
193 RETURN();
194}
195
36081602 196void OPPROTO op_load_decr (void)
9a64fbe4 197{
36081602 198 T0 = cpu_ppc_load_decr(env);
76a66253
JM
199 RETURN();
200}
9fddaa0c 201
36081602 202void OPPROTO op_store_decr (void)
9fddaa0c 203{
36081602 204 cpu_ppc_store_decr(env, T0);
9a64fbe4
FB
205 RETURN();
206}
207
36081602 208void OPPROTO op_load_ibat (void)
9a64fbe4 209{
36081602 210 T0 = env->IBAT[PARAM1][PARAM2];
76a66253 211 RETURN();
9a64fbe4
FB
212}
213
76a66253 214void OPPROTO op_store_ibatu (void)
9a64fbe4 215{
3fc6c082
FB
216 do_store_ibatu(env, PARAM1, T0);
217 RETURN();
218}
219
76a66253 220void OPPROTO op_store_ibatl (void)
3fc6c082
FB
221{
222#if 1
223 env->IBAT[1][PARAM1] = T0;
224#else
225 do_store_ibatl(env, PARAM1, T0);
226#endif
227 RETURN();
9a64fbe4
FB
228}
229
36081602 230void OPPROTO op_load_dbat (void)
9a64fbe4 231{
36081602 232 T0 = env->DBAT[PARAM1][PARAM2];
76a66253 233 RETURN();
9a64fbe4
FB
234}
235
76a66253 236void OPPROTO op_store_dbatu (void)
3fc6c082
FB
237{
238 do_store_dbatu(env, PARAM1, T0);
239 RETURN();
240}
241
76a66253 242void OPPROTO op_store_dbatl (void)
9a64fbe4 243{
3fc6c082
FB
244#if 1
245 env->DBAT[1][PARAM1] = T0;
246#else
247 do_store_dbatl(env, PARAM1, T0);
248#endif
249 RETURN();
9a64fbe4 250}
76a66253 251#endif /* !defined(CONFIG_USER_ONLY) */
9a64fbe4 252
79aceca5 253/*** Integer shift ***/
76a66253
JM
254void OPPROTO op_srli_T1 (void)
255{
d9bce9d9 256 T1 = (uint32_t)T1 >> PARAM1;
76a66253
JM
257 RETURN();
258}
259
9a64fbe4 260/* Return from interrupt */
76a66253 261#if !defined(CONFIG_USER_ONLY)
6f5d427d
JM
262/* Exception vectors */
263void OPPROTO op_store_excp_prefix (void)
264{
265 T0 &= env->ivpr_mask;
266 env->excp_prefix = T0;
267 RETURN();
268}
269
270void OPPROTO op_store_excp_vector (void)
271{
272 T0 &= env->ivor_mask;
273 env->excp_vectors[PARAM1] = T0;
274 RETURN();
275}
76a66253 276#endif
fb0eaffc 277
76a66253 278#if !defined(CONFIG_USER_ONLY)
9a64fbe4 279/* tlbia */
36081602 280void OPPROTO op_tlbia (void)
fb0eaffc 281{
daf4f96e 282 ppc_tlb_invalidate_all(env);
9a64fbe4
FB
283 RETURN();
284}
285
286/* tlbie */
d9bce9d9 287void OPPROTO op_tlbie (void)
9a64fbe4 288{
daf4f96e 289 ppc_tlb_invalidate_one(env, (uint32_t)T0);
fb0eaffc 290 RETURN();
28b6751f 291}
d9bce9d9
JM
292
293#if defined(TARGET_PPC64)
294void OPPROTO op_tlbie_64 (void)
295{
daf4f96e 296 ppc_tlb_invalidate_one(env, T0);
d9bce9d9
JM
297 RETURN();
298}
299#endif
300
301#if defined(TARGET_PPC64)
302void OPPROTO op_slbia (void)
303{
daf4f96e 304 ppc_slb_invalidate_all(env);
d9bce9d9
JM
305 RETURN();
306}
307
308void OPPROTO op_slbie (void)
309{
daf4f96e
JM
310 ppc_slb_invalidate_one(env, (uint32_t)T0);
311 RETURN();
312}
313
314void OPPROTO op_slbie_64 (void)
315{
316 ppc_slb_invalidate_one(env, T0);
d9bce9d9
JM
317 RETURN();
318}
319#endif
76a66253 320#endif
3fc6c082 321
76a66253 322/* 601 specific */
76a66253
JM
323void OPPROTO op_load_601_rtcl (void)
324{
325 T0 = cpu_ppc601_load_rtcl(env);
326 RETURN();
327}
328
76a66253
JM
329void OPPROTO op_load_601_rtcu (void)
330{
331 T0 = cpu_ppc601_load_rtcu(env);
332 RETURN();
333}
334
335#if !defined(CONFIG_USER_ONLY)
76a66253
JM
336void OPPROTO op_store_601_rtcl (void)
337{
338 cpu_ppc601_store_rtcl(env, T0);
339 RETURN();
340}
341
76a66253
JM
342void OPPROTO op_store_601_rtcu (void)
343{
344 cpu_ppc601_store_rtcu(env, T0);
345 RETURN();
346}
347
056401ea
JM
348void OPPROTO op_store_hid0_601 (void)
349{
350 do_store_hid0_601();
351 RETURN();
352}
353
76a66253
JM
354void OPPROTO op_load_601_bat (void)
355{
356 T0 = env->IBAT[PARAM1][PARAM2];
357 RETURN();
358}
76a66253 359
76a66253
JM
360void OPPROTO op_store_601_batl (void)
361{
056401ea 362 do_store_ibatl_601(env, PARAM1, T0);
76a66253
JM
363 RETURN();
364}
365
366void OPPROTO op_store_601_batu (void)
367{
056401ea 368 do_store_ibatu_601(env, PARAM1, T0);
76a66253
JM
369 RETURN();
370}
371#endif /* !defined(CONFIG_USER_ONLY) */
372
76a66253
JM
373/* POWER instructions not implemented in PowerPC 601 */
374#if !defined(CONFIG_USER_ONLY)
375void OPPROTO op_POWER_mfsri (void)
376{
377 T1 = T0 >> 28;
378 T0 = env->sr[T1];
379 RETURN();
380}
76a66253
JM
381#endif
382
76a66253 383/* PowerPC 4xx specific micro-ops */
a42bd6cc 384void OPPROTO op_load_dcr (void)
76a66253 385{
a42bd6cc 386 do_load_dcr();
76a66253
JM
387 RETURN();
388}
389
a42bd6cc 390void OPPROTO op_store_dcr (void)
76a66253 391{
a42bd6cc 392 do_store_dcr();
76a66253
JM
393 RETURN();
394}
395
a750fc0b 396#if !defined(CONFIG_USER_ONLY)
a42bd6cc 397void OPPROTO op_wrte (void)
76a66253 398{
0411a972
JM
399 /* We don't call do_store_msr here as we won't trigger
400 * any special case nor change hflags
401 */
402 T0 &= 1 << MSR_EE;
403 env->msr &= ~(1 << MSR_EE);
404 env->msr |= T0;
76a66253
JM
405 RETURN();
406}
407
a4bb6c3e 408void OPPROTO op_440_tlbre (void)
5eb7995e 409{
a4bb6c3e 410 do_440_tlbre(PARAM1);
5eb7995e
JM
411 RETURN();
412}
413
a4bb6c3e 414void OPPROTO op_440_tlbsx (void)
5eb7995e 415{
daf4f96e 416 T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR] & 0xFF);
5eb7995e
JM
417 RETURN();
418}
419
daf4f96e 420void OPPROTO op_4xx_tlbsx_check (void)
5eb7995e 421{
daf4f96e
JM
422 int tmp;
423
424 tmp = xer_so;
6f2d8978 425 if ((int)T0 != -1)
daf4f96e
JM
426 tmp |= 0x02;
427 env->crf[0] = tmp;
5eb7995e
JM
428 RETURN();
429}
430
a4bb6c3e 431void OPPROTO op_440_tlbwe (void)
5eb7995e 432{
a4bb6c3e 433 do_440_tlbwe(PARAM1);
5eb7995e
JM
434 RETURN();
435}
436
76a66253
JM
437void OPPROTO op_4xx_tlbre_lo (void)
438{
439 do_4xx_tlbre_lo();
440 RETURN();
441}
442
443void OPPROTO op_4xx_tlbre_hi (void)
444{
445 do_4xx_tlbre_hi();
446 RETURN();
447}
448
449void OPPROTO op_4xx_tlbsx (void)
450{
daf4f96e 451 T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]);
76a66253
JM
452 RETURN();
453}
454
455void OPPROTO op_4xx_tlbwe_lo (void)
456{
457 do_4xx_tlbwe_lo();
458 RETURN();
459}
460
461void OPPROTO op_4xx_tlbwe_hi (void)
462{
463 do_4xx_tlbwe_hi();
464 RETURN();
465}
466#endif
467
468/* SPR micro-ops */
469/* 440 specific */
76a66253
JM
470#if !defined(CONFIG_USER_ONLY)
471void OPPROTO op_store_pir (void)
3fc6c082
FB
472{
473 env->spr[SPR_PIR] = T0 & 0x0000000FUL;
474 RETURN();
475}
76a66253
JM
476
477void OPPROTO op_load_403_pb (void)
478{
479 do_load_403_pb(PARAM1);
480 RETURN();
481}
482
483void OPPROTO op_store_403_pb (void)
484{
485 do_store_403_pb(PARAM1);
486 RETURN();
487}
488
76a66253
JM
489void OPPROTO op_load_40x_pit (void)
490{
491 T0 = load_40x_pit(env);
492 RETURN();
493}
494
76a66253
JM
495void OPPROTO op_store_40x_pit (void)
496{
497 store_40x_pit(env, T0);
498 RETURN();
499}
500
8ecc7913
JM
501void OPPROTO op_store_40x_dbcr0 (void)
502{
503 store_40x_dbcr0(env, T0);
be147d08 504 RETURN();
8ecc7913
JM
505}
506
c294fc58
JM
507void OPPROTO op_store_40x_sler (void)
508{
509 store_40x_sler(env, T0);
510 RETURN();
511}
512
76a66253
JM
513void OPPROTO op_store_booke_tcr (void)
514{
515 store_booke_tcr(env, T0);
516 RETURN();
517}
518
76a66253
JM
519void OPPROTO op_store_booke_tsr (void)
520{
521 store_booke_tsr(env, T0);
522 RETURN();
523}
524#endif /* !defined(CONFIG_USER_ONLY) */
0487d6a8 525