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Commit | Line | Data |
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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation micro-operations for qemu. |
79aceca5 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
79aceca5 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
a541f297 FB |
21 | //#define DEBUG_OP |
22 | ||
79aceca5 FB |
23 | #include "config.h" |
24 | #include "exec.h" | |
76a66253 | 25 | #include "op_helper.h" |
79aceca5 | 26 | |
76a66253 | 27 | /* XXX: this is to be suppressed */ |
79aceca5 | 28 | #define regs (env) |
79aceca5 FB |
29 | #define Ts0 (int32_t)T0 |
30 | #define Ts1 (int32_t)T1 | |
31 | #define Ts2 (int32_t)T2 | |
32 | ||
28b6751f | 33 | #define FT0 (env->ft0) |
fb0eaffc FB |
34 | #define FT1 (env->ft1) |
35 | #define FT2 (env->ft2) | |
36 | ||
76a66253 JM |
37 | /* XXX: this is to be suppressed... */ |
38 | #define PPC_OP(name) void OPPROTO glue(op_, name)(void) | |
79aceca5 | 39 | |
28b6751f FB |
40 | #define REG 0 |
41 | #include "op_template.h" | |
42 | ||
43 | #define REG 1 | |
44 | #include "op_template.h" | |
45 | ||
46 | #define REG 2 | |
47 | #include "op_template.h" | |
48 | ||
49 | #define REG 3 | |
50 | #include "op_template.h" | |
51 | ||
52 | #define REG 4 | |
53 | #include "op_template.h" | |
54 | ||
55 | #define REG 5 | |
56 | #include "op_template.h" | |
57 | ||
58 | #define REG 6 | |
59 | #include "op_template.h" | |
60 | ||
61 | #define REG 7 | |
62 | #include "op_template.h" | |
63 | ||
64 | #define REG 8 | |
65 | #include "op_template.h" | |
66 | ||
67 | #define REG 9 | |
68 | #include "op_template.h" | |
69 | ||
70 | #define REG 10 | |
71 | #include "op_template.h" | |
72 | ||
73 | #define REG 11 | |
74 | #include "op_template.h" | |
75 | ||
76 | #define REG 12 | |
77 | #include "op_template.h" | |
78 | ||
79 | #define REG 13 | |
80 | #include "op_template.h" | |
81 | ||
82 | #define REG 14 | |
83 | #include "op_template.h" | |
84 | ||
85 | #define REG 15 | |
86 | #include "op_template.h" | |
87 | ||
88 | #define REG 16 | |
89 | #include "op_template.h" | |
90 | ||
91 | #define REG 17 | |
92 | #include "op_template.h" | |
93 | ||
94 | #define REG 18 | |
95 | #include "op_template.h" | |
96 | ||
97 | #define REG 19 | |
98 | #include "op_template.h" | |
99 | ||
100 | #define REG 20 | |
101 | #include "op_template.h" | |
102 | ||
103 | #define REG 21 | |
104 | #include "op_template.h" | |
105 | ||
106 | #define REG 22 | |
107 | #include "op_template.h" | |
108 | ||
109 | #define REG 23 | |
110 | #include "op_template.h" | |
111 | ||
112 | #define REG 24 | |
113 | #include "op_template.h" | |
114 | ||
115 | #define REG 25 | |
116 | #include "op_template.h" | |
117 | ||
118 | #define REG 26 | |
119 | #include "op_template.h" | |
120 | ||
121 | #define REG 27 | |
122 | #include "op_template.h" | |
123 | ||
124 | #define REG 28 | |
125 | #include "op_template.h" | |
126 | ||
127 | #define REG 29 | |
128 | #include "op_template.h" | |
129 | ||
130 | #define REG 30 | |
131 | #include "op_template.h" | |
132 | ||
133 | #define REG 31 | |
134 | #include "op_template.h" | |
135 | ||
3fc6c082 | 136 | /* PowerPC state maintenance operations */ |
79aceca5 FB |
137 | /* set_Rc0 */ |
138 | PPC_OP(set_Rc0) | |
139 | { | |
76a66253 | 140 | env->crf[0] = T0 | xer_ov; |
79aceca5 FB |
141 | RETURN(); |
142 | } | |
143 | ||
fb0eaffc FB |
144 | /* Set Rc1 (for floating point arithmetic) */ |
145 | PPC_OP(set_Rc1) | |
146 | { | |
147 | env->crf[1] = regs->fpscr[7]; | |
148 | RETURN(); | |
149 | } | |
150 | ||
9a64fbe4 | 151 | /* Constants load */ |
76a66253 JM |
152 | void OPPROTO op_reset_T0 (void) |
153 | { | |
154 | T0 = 0; | |
155 | RETURN(); | |
156 | } | |
157 | ||
79aceca5 FB |
158 | PPC_OP(set_T0) |
159 | { | |
160 | T0 = PARAM(1); | |
161 | RETURN(); | |
162 | } | |
163 | ||
164 | PPC_OP(set_T1) | |
165 | { | |
166 | T1 = PARAM(1); | |
167 | RETURN(); | |
168 | } | |
169 | ||
76a66253 | 170 | #if 0 // unused |
79aceca5 FB |
171 | PPC_OP(set_T2) |
172 | { | |
173 | T2 = PARAM(1); | |
174 | RETURN(); | |
175 | } | |
76a66253 | 176 | #endif |
79aceca5 | 177 | |
76a66253 | 178 | void OPPROTO op_move_T1_T0 (void) |
79aceca5 | 179 | { |
76a66253 JM |
180 | T1 = T0; |
181 | RETURN(); | |
9a64fbe4 FB |
182 | } |
183 | ||
76a66253 JM |
184 | /* Generate exceptions */ |
185 | PPC_OP(raise_exception_err) | |
9a64fbe4 | 186 | { |
76a66253 | 187 | do_raise_exception_err(PARAM(1), PARAM(2)); |
9a64fbe4 FB |
188 | } |
189 | ||
9fddaa0c | 190 | PPC_OP(update_nip) |
9a64fbe4 | 191 | { |
004bc62c | 192 | env->nip = PARAM(1); |
76a66253 | 193 | RETURN(); |
9a64fbe4 FB |
194 | } |
195 | ||
ea4e754f FB |
196 | PPC_OP(debug) |
197 | { | |
198 | do_raise_exception(EXCP_DEBUG); | |
199 | } | |
200 | ||
9a64fbe4 | 201 | |
76a66253 | 202 | PPC_OP(exit_tb) |
9a64fbe4 | 203 | { |
76a66253 | 204 | EXIT_TB(); |
9a64fbe4 FB |
205 | } |
206 | ||
76a66253 JM |
207 | /* Load/store special registers */ |
208 | PPC_OP(load_cr) | |
9a64fbe4 | 209 | { |
76a66253 | 210 | do_load_cr(); |
79aceca5 FB |
211 | RETURN(); |
212 | } | |
213 | ||
76a66253 | 214 | PPC_OP(store_cr) |
79aceca5 | 215 | { |
76a66253 | 216 | do_store_cr(PARAM(1)); |
79aceca5 FB |
217 | RETURN(); |
218 | } | |
219 | ||
76a66253 | 220 | void OPPROTO op_load_cro (void) |
79aceca5 | 221 | { |
76a66253 | 222 | T0 = env->crf[PARAM1]; |
79aceca5 FB |
223 | RETURN(); |
224 | } | |
225 | ||
76a66253 | 226 | void OPPROTO op_store_cro (void) |
79aceca5 | 227 | { |
76a66253 | 228 | env->crf[PARAM1] = T0; |
79aceca5 FB |
229 | RETURN(); |
230 | } | |
231 | ||
232 | PPC_OP(load_xer_cr) | |
233 | { | |
234 | T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1); | |
235 | RETURN(); | |
236 | } | |
237 | ||
238 | PPC_OP(clear_xer_cr) | |
239 | { | |
240 | xer_so = 0; | |
241 | xer_ov = 0; | |
242 | xer_ca = 0; | |
243 | RETURN(); | |
244 | } | |
245 | ||
246 | PPC_OP(load_xer_bc) | |
247 | { | |
9a64fbe4 | 248 | T1 = xer_bc; |
79aceca5 FB |
249 | RETURN(); |
250 | } | |
251 | ||
76a66253 JM |
252 | void OPPROTO op_store_xer_bc (void) |
253 | { | |
254 | xer_bc = T0; | |
255 | RETURN(); | |
256 | } | |
257 | ||
79aceca5 FB |
258 | PPC_OP(load_xer) |
259 | { | |
76a66253 | 260 | do_load_xer(); |
79aceca5 FB |
261 | RETURN(); |
262 | } | |
263 | ||
264 | PPC_OP(store_xer) | |
265 | { | |
76a66253 JM |
266 | do_store_xer(); |
267 | RETURN(); | |
268 | } | |
269 | ||
270 | #if !defined(CONFIG_USER_ONLY) | |
271 | /* Segment registers load and store */ | |
272 | PPC_OP(load_sr) | |
273 | { | |
274 | T0 = regs->sr[T1]; | |
275 | RETURN(); | |
276 | } | |
277 | ||
278 | PPC_OP(store_sr) | |
279 | { | |
280 | do_store_sr(env, T1, T0); | |
281 | RETURN(); | |
282 | } | |
283 | ||
284 | PPC_OP(load_sdr1) | |
285 | { | |
286 | T0 = regs->sdr1; | |
287 | RETURN(); | |
288 | } | |
289 | ||
290 | PPC_OP(store_sdr1) | |
291 | { | |
292 | do_store_sdr1(env, T0); | |
79aceca5 FB |
293 | RETURN(); |
294 | } | |
295 | ||
296 | PPC_OP(load_msr) | |
297 | { | |
3fc6c082 | 298 | T0 = do_load_msr(env); |
79aceca5 FB |
299 | RETURN(); |
300 | } | |
301 | ||
302 | PPC_OP(store_msr) | |
303 | { | |
3fc6c082 | 304 | do_store_msr(env, T0); |
9a64fbe4 FB |
305 | RETURN(); |
306 | } | |
76a66253 | 307 | #endif |
9a64fbe4 FB |
308 | |
309 | /* SPR */ | |
310 | PPC_OP(load_spr) | |
311 | { | |
312 | T0 = regs->spr[PARAM(1)]; | |
313 | RETURN(); | |
314 | } | |
315 | ||
316 | PPC_OP(store_spr) | |
317 | { | |
318 | regs->spr[PARAM(1)] = T0; | |
79aceca5 FB |
319 | RETURN(); |
320 | } | |
321 | ||
322 | PPC_OP(load_lr) | |
323 | { | |
9a64fbe4 FB |
324 | T0 = regs->lr; |
325 | RETURN(); | |
326 | } | |
327 | ||
328 | PPC_OP(store_lr) | |
329 | { | |
330 | regs->lr = T0; | |
331 | RETURN(); | |
332 | } | |
333 | ||
334 | PPC_OP(load_ctr) | |
335 | { | |
336 | T0 = regs->ctr; | |
337 | RETURN(); | |
338 | } | |
339 | ||
340 | PPC_OP(store_ctr) | |
341 | { | |
342 | regs->ctr = T0; | |
343 | RETURN(); | |
344 | } | |
345 | ||
9fddaa0c | 346 | PPC_OP(load_tbl) |
9a64fbe4 | 347 | { |
9fddaa0c | 348 | T0 = cpu_ppc_load_tbl(regs); |
9a64fbe4 FB |
349 | RETURN(); |
350 | } | |
351 | ||
9fddaa0c | 352 | PPC_OP(load_tbu) |
9a64fbe4 | 353 | { |
9fddaa0c | 354 | T0 = cpu_ppc_load_tbu(regs); |
9a64fbe4 FB |
355 | RETURN(); |
356 | } | |
357 | ||
76a66253 | 358 | #if !defined(CONFIG_USER_ONLY) |
9fddaa0c | 359 | PPC_OP(store_tbl) |
9a64fbe4 | 360 | { |
9fddaa0c | 361 | cpu_ppc_store_tbl(regs, T0); |
79aceca5 FB |
362 | RETURN(); |
363 | } | |
364 | ||
9fddaa0c | 365 | PPC_OP(store_tbu) |
9a64fbe4 | 366 | { |
9fddaa0c | 367 | cpu_ppc_store_tbu(regs, T0); |
9a64fbe4 FB |
368 | RETURN(); |
369 | } | |
370 | ||
9fddaa0c | 371 | PPC_OP(load_decr) |
9a64fbe4 | 372 | { |
9fddaa0c | 373 | T0 = cpu_ppc_load_decr(regs); |
76a66253 JM |
374 | RETURN(); |
375 | } | |
9fddaa0c FB |
376 | |
377 | PPC_OP(store_decr) | |
378 | { | |
379 | cpu_ppc_store_decr(regs, T0); | |
9a64fbe4 FB |
380 | RETURN(); |
381 | } | |
382 | ||
383 | PPC_OP(load_ibat) | |
384 | { | |
385 | T0 = regs->IBAT[PARAM(1)][PARAM(2)]; | |
76a66253 | 386 | RETURN(); |
9a64fbe4 FB |
387 | } |
388 | ||
76a66253 | 389 | void OPPROTO op_store_ibatu (void) |
9a64fbe4 | 390 | { |
3fc6c082 FB |
391 | do_store_ibatu(env, PARAM1, T0); |
392 | RETURN(); | |
393 | } | |
394 | ||
76a66253 | 395 | void OPPROTO op_store_ibatl (void) |
3fc6c082 FB |
396 | { |
397 | #if 1 | |
398 | env->IBAT[1][PARAM1] = T0; | |
399 | #else | |
400 | do_store_ibatl(env, PARAM1, T0); | |
401 | #endif | |
402 | RETURN(); | |
9a64fbe4 FB |
403 | } |
404 | ||
405 | PPC_OP(load_dbat) | |
406 | { | |
407 | T0 = regs->DBAT[PARAM(1)][PARAM(2)]; | |
76a66253 | 408 | RETURN(); |
9a64fbe4 FB |
409 | } |
410 | ||
76a66253 | 411 | void OPPROTO op_store_dbatu (void) |
3fc6c082 FB |
412 | { |
413 | do_store_dbatu(env, PARAM1, T0); | |
414 | RETURN(); | |
415 | } | |
416 | ||
76a66253 | 417 | void OPPROTO op_store_dbatl (void) |
9a64fbe4 | 418 | { |
3fc6c082 FB |
419 | #if 1 |
420 | env->DBAT[1][PARAM1] = T0; | |
421 | #else | |
422 | do_store_dbatl(env, PARAM1, T0); | |
423 | #endif | |
424 | RETURN(); | |
9a64fbe4 | 425 | } |
76a66253 | 426 | #endif /* !defined(CONFIG_USER_ONLY) */ |
9a64fbe4 | 427 | |
fb0eaffc FB |
428 | /* FPSCR */ |
429 | PPC_OP(load_fpscr) | |
430 | { | |
76a66253 | 431 | do_load_fpscr(); |
fb0eaffc FB |
432 | RETURN(); |
433 | } | |
434 | ||
435 | PPC_OP(store_fpscr) | |
436 | { | |
76a66253 | 437 | do_store_fpscr(PARAM1); |
fb0eaffc FB |
438 | RETURN(); |
439 | } | |
440 | ||
441 | PPC_OP(reset_scrfx) | |
442 | { | |
443 | regs->fpscr[7] &= ~0x8; | |
444 | RETURN(); | |
445 | } | |
446 | ||
79aceca5 FB |
447 | /* crf operations */ |
448 | PPC_OP(getbit_T0) | |
449 | { | |
450 | T0 = (T0 >> PARAM(1)) & 1; | |
451 | RETURN(); | |
452 | } | |
453 | ||
454 | PPC_OP(getbit_T1) | |
455 | { | |
456 | T1 = (T1 >> PARAM(1)) & 1; | |
457 | RETURN(); | |
458 | } | |
459 | ||
460 | PPC_OP(setcrfbit) | |
461 | { | |
462 | T1 = (T1 & PARAM(1)) | (T0 << PARAM(2)); | |
463 | RETURN(); | |
464 | } | |
465 | ||
466 | /* Branch */ | |
9a64fbe4 | 467 | #define EIP regs->nip |
9a64fbe4 | 468 | |
e98a6e40 FB |
469 | PPC_OP(setlr) |
470 | { | |
471 | regs->lr = PARAM1; | |
76a66253 | 472 | RETURN(); |
e98a6e40 FB |
473 | } |
474 | ||
c53be334 | 475 | PPC_OP(goto_tb0) |
e98a6e40 | 476 | { |
c53be334 FB |
477 | GOTO_TB(op_goto_tb0, PARAM1, 0); |
478 | } | |
479 | ||
480 | PPC_OP(goto_tb1) | |
481 | { | |
482 | GOTO_TB(op_goto_tb1, PARAM1, 1); | |
e98a6e40 FB |
483 | } |
484 | ||
485 | PPC_OP(b_T1) | |
486 | { | |
89934337 | 487 | regs->nip = T1 & ~3; |
76a66253 | 488 | RETURN(); |
e98a6e40 FB |
489 | } |
490 | ||
c53be334 | 491 | PPC_OP(jz_T0) |
e98a6e40 | 492 | { |
c53be334 FB |
493 | if (!T0) |
494 | GOTO_LABEL_PARAM(1); | |
e98a6e40 FB |
495 | RETURN(); |
496 | } | |
497 | ||
498 | PPC_OP(btest_T1) | |
499 | { | |
500 | if (T0) { | |
501 | regs->nip = T1 & ~3; | |
502 | } else { | |
503 | regs->nip = PARAM1; | |
504 | } | |
505 | RETURN(); | |
506 | } | |
507 | ||
508 | PPC_OP(movl_T1_ctr) | |
509 | { | |
510 | T1 = regs->ctr; | |
76a66253 | 511 | RETURN(); |
e98a6e40 FB |
512 | } |
513 | ||
514 | PPC_OP(movl_T1_lr) | |
515 | { | |
516 | T1 = regs->lr; | |
76a66253 | 517 | RETURN(); |
e98a6e40 FB |
518 | } |
519 | ||
520 | /* tests with result in T0 */ | |
521 | ||
522 | PPC_OP(test_ctr) | |
523 | { | |
b88e4a9a | 524 | T0 = regs->ctr; |
76a66253 | 525 | RETURN(); |
e98a6e40 FB |
526 | } |
527 | ||
528 | PPC_OP(test_ctr_true) | |
529 | { | |
530 | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) != 0); | |
76a66253 | 531 | RETURN(); |
e98a6e40 FB |
532 | } |
533 | ||
534 | PPC_OP(test_ctr_false) | |
535 | { | |
536 | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) == 0); | |
76a66253 | 537 | RETURN(); |
e98a6e40 FB |
538 | } |
539 | ||
540 | PPC_OP(test_ctrz) | |
541 | { | |
542 | T0 = (regs->ctr == 0); | |
76a66253 | 543 | RETURN(); |
e98a6e40 FB |
544 | } |
545 | ||
546 | PPC_OP(test_ctrz_true) | |
547 | { | |
548 | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) != 0); | |
76a66253 | 549 | RETURN(); |
e98a6e40 FB |
550 | } |
551 | ||
552 | PPC_OP(test_ctrz_false) | |
553 | { | |
554 | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0); | |
76a66253 | 555 | RETURN(); |
e98a6e40 FB |
556 | } |
557 | ||
558 | PPC_OP(test_true) | |
559 | { | |
b88e4a9a | 560 | T0 = (T0 & PARAM(1)); |
76a66253 | 561 | RETURN(); |
e98a6e40 FB |
562 | } |
563 | ||
564 | PPC_OP(test_false) | |
565 | { | |
566 | T0 = ((T0 & PARAM(1)) == 0); | |
76a66253 | 567 | RETURN(); |
e98a6e40 | 568 | } |
79aceca5 FB |
569 | |
570 | /* CTR maintenance */ | |
571 | PPC_OP(dec_ctr) | |
572 | { | |
9a64fbe4 | 573 | regs->ctr--; |
79aceca5 FB |
574 | RETURN(); |
575 | } | |
576 | ||
577 | /*** Integer arithmetic ***/ | |
578 | /* add */ | |
579 | PPC_OP(add) | |
580 | { | |
581 | T0 += T1; | |
582 | RETURN(); | |
583 | } | |
584 | ||
76a66253 | 585 | void OPPROTO op_addo (void) |
79aceca5 | 586 | { |
fdabc366 | 587 | do_addo(); |
79aceca5 FB |
588 | RETURN(); |
589 | } | |
590 | ||
591 | /* add carrying */ | |
592 | PPC_OP(addc) | |
593 | { | |
594 | T2 = T0; | |
595 | T0 += T1; | |
596 | if (T0 < T2) { | |
597 | xer_ca = 1; | |
598 | } else { | |
599 | xer_ca = 0; | |
600 | } | |
601 | RETURN(); | |
602 | } | |
603 | ||
76a66253 | 604 | void OPPROTO op_addco (void) |
79aceca5 | 605 | { |
fdabc366 | 606 | do_addco(); |
79aceca5 FB |
607 | RETURN(); |
608 | } | |
609 | ||
610 | /* add extended */ | |
76a66253 | 611 | void OPPROTO op_adde (void) |
79aceca5 | 612 | { |
fdabc366 | 613 | do_adde(); |
76a66253 | 614 | RETURN(); |
79aceca5 FB |
615 | } |
616 | ||
617 | PPC_OP(addeo) | |
618 | { | |
fdabc366 | 619 | do_addeo(); |
79aceca5 FB |
620 | RETURN(); |
621 | } | |
622 | ||
623 | /* add immediate */ | |
624 | PPC_OP(addi) | |
625 | { | |
626 | T0 += PARAM(1); | |
627 | RETURN(); | |
628 | } | |
629 | ||
630 | /* add immediate carrying */ | |
631 | PPC_OP(addic) | |
632 | { | |
633 | T1 = T0; | |
634 | T0 += PARAM(1); | |
635 | if (T0 < T1) { | |
636 | xer_ca = 1; | |
637 | } else { | |
638 | xer_ca = 0; | |
639 | } | |
640 | RETURN(); | |
641 | } | |
642 | ||
643 | /* add to minus one extended */ | |
644 | PPC_OP(addme) | |
645 | { | |
646 | T1 = T0; | |
647 | T0 += xer_ca + (-1); | |
648 | if (T1 != 0) | |
649 | xer_ca = 1; | |
650 | RETURN(); | |
651 | } | |
652 | ||
76a66253 | 653 | void OPPROTO op_addmeo (void) |
79aceca5 | 654 | { |
fdabc366 | 655 | do_addmeo(); |
79aceca5 FB |
656 | RETURN(); |
657 | } | |
658 | ||
659 | /* add to zero extended */ | |
660 | PPC_OP(addze) | |
661 | { | |
662 | T1 = T0; | |
663 | T0 += xer_ca; | |
664 | if (T0 < T1) { | |
665 | xer_ca = 1; | |
666 | } else { | |
667 | xer_ca = 0; | |
668 | } | |
669 | RETURN(); | |
670 | } | |
671 | ||
76a66253 | 672 | void OPPROTO op_addzeo (void) |
79aceca5 | 673 | { |
fdabc366 | 674 | do_addzeo(); |
79aceca5 FB |
675 | RETURN(); |
676 | } | |
677 | ||
678 | /* divide word */ | |
79aceca5 FB |
679 | PPC_OP(divw) |
680 | { | |
681 | if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) { | |
3cc62370 | 682 | T0 = (int32_t)((-1) * (T0 >> 31)); |
79aceca5 | 683 | } else { |
3cc62370 | 684 | T0 = (Ts0 / Ts1); |
79aceca5 FB |
685 | } |
686 | RETURN(); | |
687 | } | |
688 | ||
76a66253 | 689 | void OPPROTO op_divwo (void) |
79aceca5 | 690 | { |
fdabc366 | 691 | do_divwo(); |
79aceca5 FB |
692 | RETURN(); |
693 | } | |
694 | ||
695 | /* divide word unsigned */ | |
696 | PPC_OP(divwu) | |
697 | { | |
698 | if (T1 == 0) { | |
699 | T0 = 0; | |
700 | } else { | |
701 | T0 /= T1; | |
702 | } | |
703 | RETURN(); | |
704 | } | |
705 | ||
76a66253 | 706 | void OPPROTO op_divwuo (void) |
79aceca5 | 707 | { |
fdabc366 | 708 | do_divwuo(); |
79aceca5 FB |
709 | RETURN(); |
710 | } | |
711 | ||
712 | /* multiply high word */ | |
713 | PPC_OP(mulhw) | |
714 | { | |
3cc62370 | 715 | T0 = ((int64_t)Ts0 * (int64_t)Ts1) >> 32; |
79aceca5 FB |
716 | RETURN(); |
717 | } | |
718 | ||
719 | /* multiply high word unsigned */ | |
720 | PPC_OP(mulhwu) | |
721 | { | |
722 | T0 = ((uint64_t)T0 * (uint64_t)T1) >> 32; | |
723 | RETURN(); | |
724 | } | |
725 | ||
726 | /* multiply low immediate */ | |
727 | PPC_OP(mulli) | |
728 | { | |
3cc62370 | 729 | T0 = (Ts0 * SPARAM(1)); |
79aceca5 FB |
730 | RETURN(); |
731 | } | |
732 | ||
733 | /* multiply low word */ | |
734 | PPC_OP(mullw) | |
735 | { | |
736 | T0 *= T1; | |
737 | RETURN(); | |
738 | } | |
739 | ||
76a66253 | 740 | void OPPROTO op_mullwo (void) |
79aceca5 | 741 | { |
fdabc366 | 742 | do_mullwo(); |
79aceca5 FB |
743 | RETURN(); |
744 | } | |
745 | ||
746 | /* negate */ | |
747 | PPC_OP(neg) | |
748 | { | |
749 | if (T0 != 0x80000000) { | |
3cc62370 | 750 | T0 = -Ts0; |
79aceca5 FB |
751 | } |
752 | RETURN(); | |
753 | } | |
754 | ||
76a66253 | 755 | void OPPROTO op_nego (void) |
79aceca5 | 756 | { |
fdabc366 | 757 | do_nego(); |
79aceca5 FB |
758 | RETURN(); |
759 | } | |
760 | ||
761 | /* substract from */ | |
762 | PPC_OP(subf) | |
763 | { | |
764 | T0 = T1 - T0; | |
765 | RETURN(); | |
766 | } | |
767 | ||
76a66253 | 768 | void OPPROTO op_subfo (void) |
79aceca5 | 769 | { |
fdabc366 | 770 | do_subfo(); |
79aceca5 FB |
771 | RETURN(); |
772 | } | |
773 | ||
774 | /* substract from carrying */ | |
775 | PPC_OP(subfc) | |
776 | { | |
777 | T0 = T1 - T0; | |
778 | if (T0 <= T1) { | |
779 | xer_ca = 1; | |
780 | } else { | |
781 | xer_ca = 0; | |
782 | } | |
783 | RETURN(); | |
784 | } | |
785 | ||
76a66253 | 786 | void OPPROTO op_subfco (void) |
79aceca5 | 787 | { |
fdabc366 | 788 | do_subfco(); |
79aceca5 FB |
789 | RETURN(); |
790 | } | |
791 | ||
792 | /* substract from extended */ | |
76a66253 | 793 | void OPPROTO op_subfe (void) |
79aceca5 | 794 | { |
fdabc366 | 795 | do_subfe(); |
79aceca5 FB |
796 | RETURN(); |
797 | } | |
798 | ||
799 | PPC_OP(subfeo) | |
800 | { | |
fdabc366 | 801 | do_subfeo(); |
79aceca5 FB |
802 | RETURN(); |
803 | } | |
804 | ||
805 | /* substract from immediate carrying */ | |
806 | PPC_OP(subfic) | |
807 | { | |
808 | T0 = PARAM(1) + ~T0 + 1; | |
809 | if (T0 <= PARAM(1)) { | |
810 | xer_ca = 1; | |
811 | } else { | |
812 | xer_ca = 0; | |
813 | } | |
814 | RETURN(); | |
815 | } | |
816 | ||
817 | /* substract from minus one extended */ | |
818 | PPC_OP(subfme) | |
819 | { | |
820 | T0 = ~T0 + xer_ca - 1; | |
821 | ||
822 | if (T0 != -1) | |
823 | xer_ca = 1; | |
824 | RETURN(); | |
825 | } | |
826 | ||
76a66253 | 827 | void OPPROTO op_subfmeo (void) |
79aceca5 | 828 | { |
fdabc366 | 829 | do_subfmeo(); |
79aceca5 FB |
830 | RETURN(); |
831 | } | |
832 | ||
833 | /* substract from zero extended */ | |
834 | PPC_OP(subfze) | |
835 | { | |
836 | T1 = ~T0; | |
837 | T0 = T1 + xer_ca; | |
838 | if (T0 < T1) { | |
839 | xer_ca = 1; | |
840 | } else { | |
841 | xer_ca = 0; | |
842 | } | |
843 | RETURN(); | |
844 | } | |
845 | ||
76a66253 | 846 | void OPPROTO op_subfzeo (void) |
79aceca5 | 847 | { |
fdabc366 | 848 | do_subfzeo(); |
79aceca5 FB |
849 | RETURN(); |
850 | } | |
851 | ||
852 | /*** Integer comparison ***/ | |
853 | /* compare */ | |
854 | PPC_OP(cmp) | |
855 | { | |
856 | if (Ts0 < Ts1) { | |
857 | T0 = 0x08; | |
858 | } else if (Ts0 > Ts1) { | |
859 | T0 = 0x04; | |
860 | } else { | |
861 | T0 = 0x02; | |
862 | } | |
863 | RETURN(); | |
864 | } | |
865 | ||
866 | /* compare immediate */ | |
867 | PPC_OP(cmpi) | |
868 | { | |
869 | if (Ts0 < SPARAM(1)) { | |
870 | T0 = 0x08; | |
871 | } else if (Ts0 > SPARAM(1)) { | |
872 | T0 = 0x04; | |
873 | } else { | |
874 | T0 = 0x02; | |
875 | } | |
876 | RETURN(); | |
877 | } | |
878 | ||
879 | /* compare logical */ | |
880 | PPC_OP(cmpl) | |
881 | { | |
882 | if (T0 < T1) { | |
883 | T0 = 0x08; | |
884 | } else if (T0 > T1) { | |
885 | T0 = 0x04; | |
886 | } else { | |
887 | T0 = 0x02; | |
888 | } | |
889 | RETURN(); | |
890 | } | |
891 | ||
892 | /* compare logical immediate */ | |
893 | PPC_OP(cmpli) | |
894 | { | |
895 | if (T0 < PARAM(1)) { | |
896 | T0 = 0x08; | |
897 | } else if (T0 > PARAM(1)) { | |
898 | T0 = 0x04; | |
899 | } else { | |
900 | T0 = 0x02; | |
901 | } | |
902 | RETURN(); | |
903 | } | |
904 | ||
905 | /*** Integer logical ***/ | |
906 | /* and */ | |
907 | PPC_OP(and) | |
908 | { | |
909 | T0 &= T1; | |
910 | RETURN(); | |
911 | } | |
912 | ||
913 | /* andc */ | |
914 | PPC_OP(andc) | |
915 | { | |
916 | T0 &= ~T1; | |
917 | RETURN(); | |
918 | } | |
919 | ||
920 | /* andi. */ | |
76a66253 | 921 | void OPPROTO op_andi_T0 (void) |
79aceca5 FB |
922 | { |
923 | T0 &= PARAM(1); | |
924 | RETURN(); | |
925 | } | |
926 | ||
76a66253 JM |
927 | void OPPROTO op_andi_T1 (void) |
928 | { | |
929 | T1 &= PARAM1; | |
930 | RETURN(); | |
931 | } | |
932 | ||
79aceca5 | 933 | /* count leading zero */ |
76a66253 | 934 | void OPPROTO op_cntlzw (void) |
79aceca5 | 935 | { |
76a66253 JM |
936 | int cnt; |
937 | ||
938 | cnt = 0; | |
939 | if (!(T0 & 0xFFFF0000UL)) { | |
940 | cnt += 16; | |
941 | T0 <<= 16; | |
942 | } | |
943 | if (!(T0 & 0xFF000000UL)) { | |
944 | cnt += 8; | |
945 | T0 <<= 8; | |
946 | } | |
947 | if (!(T0 & 0xF0000000UL)) { | |
948 | cnt += 4; | |
949 | T0 <<= 4; | |
950 | } | |
951 | if (!(T0 & 0xC0000000UL)) { | |
952 | cnt += 2; | |
953 | T0 <<= 2; | |
954 | } | |
955 | if (!(T0 & 0x80000000UL)) { | |
956 | cnt++; | |
957 | T0 <<= 1; | |
958 | } | |
959 | if (!(T0 & 0x80000000UL)) { | |
960 | cnt++; | |
961 | } | |
962 | T0 = cnt; | |
79aceca5 FB |
963 | RETURN(); |
964 | } | |
965 | ||
966 | /* eqv */ | |
967 | PPC_OP(eqv) | |
968 | { | |
969 | T0 = ~(T0 ^ T1); | |
970 | RETURN(); | |
971 | } | |
972 | ||
973 | /* extend sign byte */ | |
974 | PPC_OP(extsb) | |
975 | { | |
3cc62370 | 976 | T0 = (int32_t)((int8_t)(Ts0)); |
79aceca5 FB |
977 | RETURN(); |
978 | } | |
979 | ||
980 | /* extend sign half word */ | |
981 | PPC_OP(extsh) | |
982 | { | |
3cc62370 | 983 | T0 = (int32_t)((int16_t)(Ts0)); |
79aceca5 FB |
984 | RETURN(); |
985 | } | |
986 | ||
987 | /* nand */ | |
988 | PPC_OP(nand) | |
989 | { | |
990 | T0 = ~(T0 & T1); | |
991 | RETURN(); | |
992 | } | |
993 | ||
994 | /* nor */ | |
995 | PPC_OP(nor) | |
996 | { | |
997 | T0 = ~(T0 | T1); | |
998 | RETURN(); | |
999 | } | |
1000 | ||
1001 | /* or */ | |
1002 | PPC_OP(or) | |
1003 | { | |
1004 | T0 |= T1; | |
1005 | RETURN(); | |
1006 | } | |
1007 | ||
1008 | /* orc */ | |
1009 | PPC_OP(orc) | |
1010 | { | |
1011 | T0 |= ~T1; | |
1012 | RETURN(); | |
1013 | } | |
1014 | ||
1015 | /* ori */ | |
1016 | PPC_OP(ori) | |
1017 | { | |
1018 | T0 |= PARAM(1); | |
1019 | RETURN(); | |
1020 | } | |
1021 | ||
1022 | /* xor */ | |
1023 | PPC_OP(xor) | |
1024 | { | |
1025 | T0 ^= T1; | |
1026 | RETURN(); | |
1027 | } | |
1028 | ||
1029 | /* xori */ | |
1030 | PPC_OP(xori) | |
1031 | { | |
1032 | T0 ^= PARAM(1); | |
1033 | RETURN(); | |
1034 | } | |
1035 | ||
1036 | /*** Integer rotate ***/ | |
76a66253 | 1037 | void OPPROTO op_rotl32_T0_T1 (void) |
79aceca5 | 1038 | { |
76a66253 | 1039 | T0 = rotl32(T0, T1 & 0x1F); |
79aceca5 FB |
1040 | RETURN(); |
1041 | } | |
1042 | ||
76a66253 | 1043 | void OPPROTO op_rotli32_T0 (void) |
79aceca5 | 1044 | { |
76a66253 | 1045 | T0 = rotl32(T0, PARAM1); |
79aceca5 FB |
1046 | RETURN(); |
1047 | } | |
1048 | ||
1049 | /*** Integer shift ***/ | |
1050 | /* shift left word */ | |
1051 | PPC_OP(slw) | |
1052 | { | |
1053 | if (T1 & 0x20) { | |
1054 | T0 = 0; | |
1055 | } else { | |
1056 | T0 = T0 << T1; | |
1057 | } | |
1058 | RETURN(); | |
1059 | } | |
1060 | ||
1061 | /* shift right algebraic word */ | |
76a66253 | 1062 | void OPPROTO op_sraw (void) |
79aceca5 | 1063 | { |
9a64fbe4 | 1064 | do_sraw(); |
79aceca5 FB |
1065 | RETURN(); |
1066 | } | |
1067 | ||
1068 | /* shift right algebraic word immediate */ | |
1069 | PPC_OP(srawi) | |
1070 | { | |
3cc62370 FB |
1071 | T1 = T0; |
1072 | T0 = (Ts0 >> PARAM(1)); | |
79aceca5 FB |
1073 | if (Ts1 < 0 && (Ts1 & PARAM(2)) != 0) { |
1074 | xer_ca = 1; | |
1075 | } else { | |
1076 | xer_ca = 0; | |
1077 | } | |
1078 | RETURN(); | |
1079 | } | |
1080 | ||
1081 | /* shift right word */ | |
1082 | PPC_OP(srw) | |
1083 | { | |
1084 | if (T1 & 0x20) { | |
1085 | T0 = 0; | |
1086 | } else { | |
1087 | T0 = T0 >> T1; | |
1088 | } | |
1089 | RETURN(); | |
1090 | } | |
1091 | ||
76a66253 JM |
1092 | void OPPROTO op_sl_T0_T1 (void) |
1093 | { | |
1094 | T0 = T0 << T1; | |
1095 | RETURN(); | |
1096 | } | |
1097 | ||
1098 | void OPPROTO op_sli_T0 (void) | |
1099 | { | |
1100 | T0 = T0 << PARAM1; | |
1101 | RETURN(); | |
1102 | } | |
1103 | ||
1104 | void OPPROTO op_srl_T0_T1 (void) | |
1105 | { | |
1106 | T0 = T0 >> T1; | |
1107 | RETURN(); | |
1108 | } | |
1109 | ||
1110 | void OPPROTO op_srli_T0 (void) | |
1111 | { | |
1112 | T0 = T0 >> PARAM1; | |
1113 | RETURN(); | |
1114 | } | |
1115 | ||
1116 | void OPPROTO op_srli_T1 (void) | |
1117 | { | |
1118 | T1 = T1 >> PARAM1; | |
1119 | RETURN(); | |
1120 | } | |
1121 | ||
79aceca5 | 1122 | /*** Floating-Point arithmetic ***/ |
9a64fbe4 FB |
1123 | /* fadd - fadd. */ |
1124 | PPC_OP(fadd) | |
79aceca5 | 1125 | { |
76a66253 | 1126 | FT0 = float64_add(FT0, FT1, &env->fp_status); |
79aceca5 FB |
1127 | RETURN(); |
1128 | } | |
1129 | ||
9a64fbe4 FB |
1130 | /* fsub - fsub. */ |
1131 | PPC_OP(fsub) | |
79aceca5 | 1132 | { |
76a66253 | 1133 | FT0 = float64_sub(FT0, FT1, &env->fp_status); |
79aceca5 FB |
1134 | RETURN(); |
1135 | } | |
1136 | ||
9a64fbe4 FB |
1137 | /* fmul - fmul. */ |
1138 | PPC_OP(fmul) | |
79aceca5 | 1139 | { |
76a66253 | 1140 | FT0 = float64_mul(FT0, FT1, &env->fp_status); |
79aceca5 FB |
1141 | RETURN(); |
1142 | } | |
1143 | ||
9a64fbe4 FB |
1144 | /* fdiv - fdiv. */ |
1145 | PPC_OP(fdiv) | |
79aceca5 | 1146 | { |
fdabc366 | 1147 | FT0 = float64_div(FT0, FT1, &env->fp_status); |
79aceca5 FB |
1148 | RETURN(); |
1149 | } | |
28b6751f | 1150 | |
9a64fbe4 FB |
1151 | /* fsqrt - fsqrt. */ |
1152 | PPC_OP(fsqrt) | |
28b6751f | 1153 | { |
9a64fbe4 FB |
1154 | do_fsqrt(); |
1155 | RETURN(); | |
28b6751f FB |
1156 | } |
1157 | ||
9a64fbe4 FB |
1158 | /* fres - fres. */ |
1159 | PPC_OP(fres) | |
28b6751f | 1160 | { |
9a64fbe4 FB |
1161 | do_fres(); |
1162 | RETURN(); | |
28b6751f FB |
1163 | } |
1164 | ||
9a64fbe4 FB |
1165 | /* frsqrte - frsqrte. */ |
1166 | PPC_OP(frsqrte) | |
28b6751f | 1167 | { |
4ecc3190 | 1168 | do_frsqrte(); |
9a64fbe4 | 1169 | RETURN(); |
28b6751f FB |
1170 | } |
1171 | ||
9a64fbe4 FB |
1172 | /* fsel - fsel. */ |
1173 | PPC_OP(fsel) | |
28b6751f | 1174 | { |
9a64fbe4 FB |
1175 | do_fsel(); |
1176 | RETURN(); | |
28b6751f FB |
1177 | } |
1178 | ||
9a64fbe4 FB |
1179 | /*** Floating-Point multiply-and-add ***/ |
1180 | /* fmadd - fmadd. */ | |
1181 | PPC_OP(fmadd) | |
28b6751f | 1182 | { |
76a66253 JM |
1183 | FT0 = float64_mul(FT0, FT1, &env->fp_status); |
1184 | FT0 = float64_add(FT0, FT2, &env->fp_status); | |
9a64fbe4 | 1185 | RETURN(); |
28b6751f FB |
1186 | } |
1187 | ||
9a64fbe4 FB |
1188 | /* fmsub - fmsub. */ |
1189 | PPC_OP(fmsub) | |
28b6751f | 1190 | { |
76a66253 JM |
1191 | FT0 = float64_mul(FT0, FT1, &env->fp_status); |
1192 | FT0 = float64_sub(FT0, FT2, &env->fp_status); | |
9a64fbe4 | 1193 | RETURN(); |
28b6751f FB |
1194 | } |
1195 | ||
9a64fbe4 FB |
1196 | /* fnmadd - fnmadd. - fnmadds - fnmadds. */ |
1197 | PPC_OP(fnmadd) | |
28b6751f | 1198 | { |
4b3686fa | 1199 | do_fnmadd(); |
9a64fbe4 | 1200 | RETURN(); |
28b6751f FB |
1201 | } |
1202 | ||
9a64fbe4 FB |
1203 | /* fnmsub - fnmsub. */ |
1204 | PPC_OP(fnmsub) | |
28b6751f | 1205 | { |
4b3686fa | 1206 | do_fnmsub(); |
9a64fbe4 | 1207 | RETURN(); |
28b6751f FB |
1208 | } |
1209 | ||
9a64fbe4 FB |
1210 | /*** Floating-Point round & convert ***/ |
1211 | /* frsp - frsp. */ | |
1212 | PPC_OP(frsp) | |
28b6751f | 1213 | { |
76a66253 | 1214 | FT0 = float64_to_float32(FT0, &env->fp_status); |
9a64fbe4 | 1215 | RETURN(); |
28b6751f FB |
1216 | } |
1217 | ||
9a64fbe4 FB |
1218 | /* fctiw - fctiw. */ |
1219 | PPC_OP(fctiw) | |
28b6751f | 1220 | { |
9a64fbe4 FB |
1221 | do_fctiw(); |
1222 | RETURN(); | |
28b6751f FB |
1223 | } |
1224 | ||
9a64fbe4 FB |
1225 | /* fctiwz - fctiwz. */ |
1226 | PPC_OP(fctiwz) | |
28b6751f | 1227 | { |
9a64fbe4 FB |
1228 | do_fctiwz(); |
1229 | RETURN(); | |
28b6751f FB |
1230 | } |
1231 | ||
9a64fbe4 FB |
1232 | /*** Floating-Point compare ***/ |
1233 | /* fcmpu */ | |
1234 | PPC_OP(fcmpu) | |
28b6751f | 1235 | { |
9a64fbe4 FB |
1236 | do_fcmpu(); |
1237 | RETURN(); | |
28b6751f FB |
1238 | } |
1239 | ||
9a64fbe4 FB |
1240 | /* fcmpo */ |
1241 | PPC_OP(fcmpo) | |
fb0eaffc | 1242 | { |
9a64fbe4 FB |
1243 | do_fcmpo(); |
1244 | RETURN(); | |
fb0eaffc FB |
1245 | } |
1246 | ||
9a64fbe4 FB |
1247 | /*** Floating-point move ***/ |
1248 | /* fabs */ | |
1249 | PPC_OP(fabs) | |
fb0eaffc | 1250 | { |
fdabc366 | 1251 | FT0 = float64_abs(FT0); |
fb0eaffc FB |
1252 | RETURN(); |
1253 | } | |
1254 | ||
9a64fbe4 FB |
1255 | /* fnabs */ |
1256 | PPC_OP(fnabs) | |
fb0eaffc | 1257 | { |
fdabc366 FB |
1258 | FT0 = float64_abs(FT0); |
1259 | FT0 = float64_chs(FT0); | |
fb0eaffc FB |
1260 | RETURN(); |
1261 | } | |
1262 | ||
9a64fbe4 FB |
1263 | /* fneg */ |
1264 | PPC_OP(fneg) | |
fb0eaffc | 1265 | { |
fdabc366 | 1266 | FT0 = float64_chs(FT0); |
fb0eaffc FB |
1267 | RETURN(); |
1268 | } | |
1269 | ||
9a64fbe4 | 1270 | /* Load and store */ |
9a64fbe4 | 1271 | #define MEMSUFFIX _raw |
76a66253 | 1272 | #include "op_helper.h" |
9a64fbe4 | 1273 | #include "op_mem.h" |
a541f297 | 1274 | #if !defined(CONFIG_USER_ONLY) |
9a64fbe4 | 1275 | #define MEMSUFFIX _user |
76a66253 | 1276 | #include "op_helper.h" |
9a64fbe4 | 1277 | #include "op_mem.h" |
9a64fbe4 | 1278 | #define MEMSUFFIX _kernel |
76a66253 | 1279 | #include "op_helper.h" |
9a64fbe4 FB |
1280 | #include "op_mem.h" |
1281 | #endif | |
1282 | ||
4b3686fa FB |
1283 | /* Special op to check and maybe clear reservation */ |
1284 | PPC_OP(check_reservation) | |
1285 | { | |
fdabc366 FB |
1286 | if ((uint32_t)env->reserve == (uint32_t)(T0 & ~0x00000003)) |
1287 | env->reserve = -1; | |
4b3686fa FB |
1288 | RETURN(); |
1289 | } | |
1290 | ||
9a64fbe4 | 1291 | /* Return from interrupt */ |
76a66253 JM |
1292 | #if !defined(CONFIG_USER_ONLY) |
1293 | void OPPROTO op_rfi (void) | |
28b6751f | 1294 | { |
fdabc366 | 1295 | do_rfi(); |
fb0eaffc FB |
1296 | RETURN(); |
1297 | } | |
76a66253 | 1298 | #endif |
fb0eaffc | 1299 | |
9a64fbe4 | 1300 | /* Trap word */ |
76a66253 | 1301 | void OPPROTO op_tw (void) |
fb0eaffc | 1302 | { |
76a66253 | 1303 | do_tw(PARAM1); |
fb0eaffc FB |
1304 | RETURN(); |
1305 | } | |
1306 | ||
1307 | /* Instruction cache block invalidate */ | |
9a64fbe4 | 1308 | PPC_OP(icbi) |
fb0eaffc FB |
1309 | { |
1310 | do_icbi(); | |
1311 | RETURN(); | |
1312 | } | |
1313 | ||
76a66253 | 1314 | #if !defined(CONFIG_USER_ONLY) |
9a64fbe4 FB |
1315 | /* tlbia */ |
1316 | PPC_OP(tlbia) | |
fb0eaffc | 1317 | { |
9a64fbe4 FB |
1318 | do_tlbia(); |
1319 | RETURN(); | |
1320 | } | |
1321 | ||
1322 | /* tlbie */ | |
1323 | PPC_OP(tlbie) | |
1324 | { | |
1325 | do_tlbie(); | |
fb0eaffc | 1326 | RETURN(); |
28b6751f | 1327 | } |
76a66253 | 1328 | #endif |
3fc6c082 | 1329 | |
76a66253 JM |
1330 | /* PowerPC 602/603/755 software TLB load instructions */ |
1331 | #if !defined(CONFIG_USER_ONLY) | |
1332 | void OPPROTO op_6xx_tlbld (void) | |
1333 | { | |
1334 | do_load_6xx_tlb(0); | |
1335 | RETURN(); | |
1336 | } | |
1337 | ||
1338 | void OPPROTO op_6xx_tlbli (void) | |
1339 | { | |
1340 | do_load_6xx_tlb(1); | |
1341 | RETURN(); | |
1342 | } | |
1343 | #endif | |
1344 | ||
1345 | /* 601 specific */ | |
1346 | uint32_t cpu_ppc601_load_rtcl (CPUState *env); | |
1347 | void OPPROTO op_load_601_rtcl (void) | |
1348 | { | |
1349 | T0 = cpu_ppc601_load_rtcl(env); | |
1350 | RETURN(); | |
1351 | } | |
1352 | ||
1353 | uint32_t cpu_ppc601_load_rtcu (CPUState *env); | |
1354 | void OPPROTO op_load_601_rtcu (void) | |
1355 | { | |
1356 | T0 = cpu_ppc601_load_rtcu(env); | |
1357 | RETURN(); | |
1358 | } | |
1359 | ||
1360 | #if !defined(CONFIG_USER_ONLY) | |
1361 | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value); | |
1362 | void OPPROTO op_store_601_rtcl (void) | |
1363 | { | |
1364 | cpu_ppc601_store_rtcl(env, T0); | |
1365 | RETURN(); | |
1366 | } | |
1367 | ||
1368 | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value); | |
1369 | void OPPROTO op_store_601_rtcu (void) | |
1370 | { | |
1371 | cpu_ppc601_store_rtcu(env, T0); | |
1372 | RETURN(); | |
1373 | } | |
1374 | ||
1375 | void OPPROTO op_load_601_bat (void) | |
1376 | { | |
1377 | T0 = env->IBAT[PARAM1][PARAM2]; | |
1378 | RETURN(); | |
1379 | } | |
1380 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
1381 | ||
1382 | /* 601 unified BATs store. | |
1383 | * To avoid using specific MMU code for 601, we store BATs in | |
1384 | * IBAT and DBAT simultaneously, then emulate unified BATs. | |
1385 | */ | |
1386 | #if !defined(CONFIG_USER_ONLY) | |
1387 | void OPPROTO op_store_601_batl (void) | |
1388 | { | |
1389 | int nr = PARAM1; | |
1390 | ||
1391 | env->IBAT[1][nr] = T0; | |
1392 | env->DBAT[1][nr] = T0; | |
1393 | RETURN(); | |
1394 | } | |
1395 | ||
1396 | void OPPROTO op_store_601_batu (void) | |
1397 | { | |
1398 | do_store_601_batu(PARAM1); | |
1399 | RETURN(); | |
1400 | } | |
1401 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
1402 | ||
1403 | /* PowerPC 601 specific instructions (POWER bridge) */ | |
1404 | /* XXX: those micro-ops need tests ! */ | |
1405 | void OPPROTO op_POWER_abs (void) | |
1406 | { | |
1407 | if (T0 == INT32_MIN) | |
1408 | T0 = INT32_MAX; | |
1409 | else if (T0 < 0) | |
1410 | T0 = -T0; | |
1411 | RETURN(); | |
1412 | } | |
1413 | ||
1414 | void OPPROTO op_POWER_abso (void) | |
1415 | { | |
1416 | do_POWER_abso(); | |
1417 | RETURN(); | |
1418 | } | |
1419 | ||
1420 | void OPPROTO op_POWER_clcs (void) | |
1421 | { | |
1422 | do_POWER_clcs(); | |
1423 | RETURN(); | |
1424 | } | |
1425 | ||
1426 | void OPPROTO op_POWER_div (void) | |
1427 | { | |
1428 | do_POWER_div(); | |
1429 | RETURN(); | |
1430 | } | |
1431 | ||
1432 | void OPPROTO op_POWER_divo (void) | |
1433 | { | |
1434 | do_POWER_divo(); | |
1435 | RETURN(); | |
1436 | } | |
1437 | ||
1438 | void OPPROTO op_POWER_divs (void) | |
1439 | { | |
1440 | do_POWER_divs(); | |
1441 | RETURN(); | |
1442 | } | |
1443 | ||
1444 | void OPPROTO op_POWER_divso (void) | |
1445 | { | |
1446 | do_POWER_divso(); | |
1447 | RETURN(); | |
1448 | } | |
1449 | ||
1450 | void OPPROTO op_POWER_doz (void) | |
1451 | { | |
1452 | if (Ts1 > Ts0) | |
1453 | T0 = T1 - T0; | |
1454 | else | |
1455 | T0 = 0; | |
1456 | RETURN(); | |
1457 | } | |
1458 | ||
1459 | void OPPROTO op_POWER_dozo (void) | |
1460 | { | |
1461 | do_POWER_dozo(); | |
1462 | RETURN(); | |
1463 | } | |
1464 | ||
1465 | void OPPROTO op_load_xer_cmp (void) | |
1466 | { | |
1467 | T2 = xer_cmp; | |
1468 | RETURN(); | |
1469 | } | |
1470 | ||
1471 | void OPPROTO op_POWER_maskg (void) | |
1472 | { | |
1473 | do_POWER_maskg(); | |
1474 | RETURN(); | |
1475 | } | |
1476 | ||
1477 | void OPPROTO op_POWER_maskir (void) | |
1478 | { | |
1479 | T0 = (T0 & ~T2) | (T1 & T2); | |
1480 | RETURN(); | |
1481 | } | |
1482 | ||
1483 | void OPPROTO op_POWER_mul (void) | |
1484 | { | |
1485 | uint64_t tmp; | |
1486 | ||
1487 | tmp = (uint64_t)T0 * (uint64_t)T1; | |
1488 | env->spr[SPR_MQ] = tmp >> 32; | |
1489 | T0 = tmp; | |
1490 | RETURN(); | |
1491 | } | |
1492 | ||
1493 | void OPPROTO op_POWER_mulo (void) | |
1494 | { | |
1495 | do_POWER_mulo(); | |
1496 | RETURN(); | |
1497 | } | |
1498 | ||
1499 | void OPPROTO op_POWER_nabs (void) | |
1500 | { | |
1501 | if (T0 > 0) | |
1502 | T0 = -T0; | |
1503 | RETURN(); | |
1504 | } | |
1505 | ||
1506 | void OPPROTO op_POWER_nabso (void) | |
1507 | { | |
1508 | /* nabs never overflows */ | |
1509 | if (T0 > 0) | |
1510 | T0 = -T0; | |
1511 | xer_ov = 0; | |
1512 | RETURN(); | |
1513 | } | |
1514 | ||
1515 | /* XXX: factorise POWER rotates... */ | |
1516 | void OPPROTO op_POWER_rlmi (void) | |
1517 | { | |
1518 | T0 = rotl32(T0, T2) & PARAM1; | |
1519 | T0 |= T1 & PARAM2; | |
1520 | RETURN(); | |
1521 | } | |
1522 | ||
1523 | void OPPROTO op_POWER_rrib (void) | |
1524 | { | |
1525 | T2 &= 0x1FUL; | |
1526 | T0 = rotl32(T0 & INT32_MIN, T2); | |
1527 | T0 |= T1 & ~rotl32(INT32_MIN, T2); | |
1528 | RETURN(); | |
1529 | } | |
1530 | ||
1531 | void OPPROTO op_POWER_sle (void) | |
1532 | { | |
1533 | T1 &= 0x1FUL; | |
1534 | env->spr[SPR_MQ] = rotl32(T0, T1); | |
1535 | T0 = T0 << T1; | |
1536 | RETURN(); | |
1537 | } | |
1538 | ||
1539 | void OPPROTO op_POWER_sleq (void) | |
1540 | { | |
1541 | uint32_t tmp = env->spr[SPR_MQ]; | |
1542 | ||
1543 | T1 &= 0x1FUL; | |
1544 | env->spr[SPR_MQ] = rotl32(T0, T1); | |
1545 | T0 = T0 << T1; | |
1546 | T0 |= tmp >> (32 - T1); | |
1547 | RETURN(); | |
1548 | } | |
1549 | ||
1550 | void OPPROTO op_POWER_sllq (void) | |
1551 | { | |
1552 | uint32_t msk = -1; | |
1553 | ||
1554 | msk = msk << (T1 & 0x1FUL); | |
1555 | if (T1 & 0x20UL) | |
1556 | msk = ~msk; | |
1557 | T1 &= 0x1FUL; | |
1558 | T0 = (T0 << T1) & msk; | |
1559 | T0 |= env->spr[SPR_MQ] & ~msk; | |
1560 | RETURN(); | |
1561 | } | |
1562 | ||
1563 | void OPPROTO op_POWER_slq (void) | |
1564 | { | |
1565 | uint32_t msk = -1, tmp; | |
1566 | ||
1567 | msk = msk << (T1 & 0x1FUL); | |
1568 | if (T1 & 0x20UL) | |
1569 | msk = ~msk; | |
1570 | T1 &= 0x1FUL; | |
1571 | tmp = rotl32(T0, T1); | |
1572 | T0 = tmp & msk; | |
1573 | env->spr[SPR_MQ] = tmp; | |
1574 | RETURN(); | |
1575 | } | |
1576 | ||
1577 | void OPPROTO op_POWER_sraq (void) | |
1578 | { | |
1579 | env->spr[SPR_MQ] = rotl32(T0, 32 - (T1 & 0x1FUL)); | |
1580 | if (T1 & 0x20UL) | |
1581 | T0 = -1L; | |
1582 | else | |
1583 | T0 = Ts0 >> T1; | |
1584 | RETURN(); | |
1585 | } | |
1586 | ||
1587 | void OPPROTO op_POWER_sre (void) | |
1588 | { | |
1589 | T1 &= 0x1FUL; | |
1590 | env->spr[SPR_MQ] = rotl32(T0, 32 - T1); | |
1591 | T0 = Ts0 >> T1; | |
1592 | RETURN(); | |
1593 | } | |
1594 | ||
1595 | void OPPROTO op_POWER_srea (void) | |
1596 | { | |
1597 | T1 &= 0x1FUL; | |
1598 | env->spr[SPR_MQ] = T0 >> T1; | |
1599 | T0 = Ts0 >> T1; | |
1600 | RETURN(); | |
1601 | } | |
1602 | ||
1603 | void OPPROTO op_POWER_sreq (void) | |
1604 | { | |
1605 | uint32_t tmp; | |
1606 | int32_t msk; | |
1607 | ||
1608 | T1 &= 0x1FUL; | |
1609 | msk = INT32_MIN >> T1; | |
1610 | tmp = env->spr[SPR_MQ]; | |
1611 | env->spr[SPR_MQ] = rotl32(T0, 32 - T1); | |
1612 | T0 = T0 >> T1; | |
1613 | T0 |= tmp & msk; | |
1614 | RETURN(); | |
1615 | } | |
1616 | ||
1617 | void OPPROTO op_POWER_srlq (void) | |
1618 | { | |
1619 | uint32_t tmp; | |
1620 | int32_t msk; | |
1621 | ||
1622 | msk = INT32_MIN >> (T1 & 0x1FUL); | |
1623 | if (T1 & 0x20UL) | |
1624 | msk = ~msk; | |
1625 | T1 &= 0x1FUL; | |
1626 | tmp = env->spr[SPR_MQ]; | |
1627 | env->spr[SPR_MQ] = rotl32(T0, 32 - T1); | |
1628 | T0 = T0 >> T1; | |
1629 | T0 &= msk; | |
1630 | T0 |= tmp & ~msk; | |
1631 | RETURN(); | |
1632 | } | |
1633 | ||
1634 | void OPPROTO op_POWER_srq (void) | |
1635 | { | |
1636 | T1 &= 0x1FUL; | |
1637 | env->spr[SPR_MQ] = rotl32(T0, 32 - T1); | |
1638 | T0 = T0 >> T1; | |
1639 | RETURN(); | |
1640 | } | |
1641 | ||
1642 | /* POWER instructions not implemented in PowerPC 601 */ | |
1643 | #if !defined(CONFIG_USER_ONLY) | |
1644 | void OPPROTO op_POWER_mfsri (void) | |
1645 | { | |
1646 | T1 = T0 >> 28; | |
1647 | T0 = env->sr[T1]; | |
1648 | RETURN(); | |
1649 | } | |
1650 | ||
1651 | void OPPROTO op_POWER_rac (void) | |
1652 | { | |
1653 | do_POWER_rac(); | |
1654 | RETURN(); | |
1655 | } | |
1656 | ||
1657 | void OPPROTO op_POWER_rfsvc (void) | |
1658 | { | |
1659 | do_POWER_rfsvc(); | |
1660 | RETURN(); | |
1661 | } | |
1662 | #endif | |
1663 | ||
1664 | /* PowerPC 602 specific instruction */ | |
1665 | #if !defined(CONFIG_USER_ONLY) | |
1666 | void OPPROTO op_602_mfrom (void) | |
1667 | { | |
1668 | do_op_602_mfrom(); | |
1669 | RETURN(); | |
1670 | } | |
1671 | #endif | |
1672 | ||
1673 | /* PowerPC 4xx specific micro-ops */ | |
1674 | void OPPROTO op_405_add_T0_T2 (void) | |
1675 | { | |
1676 | T0 = (int32_t)T0 + (int32_t)T2; | |
1677 | RETURN(); | |
1678 | } | |
1679 | ||
1680 | void OPPROTO op_405_mulchw (void) | |
1681 | { | |
1682 | T0 = ((int16_t)T0) * ((int16_t)(T1 >> 16)); | |
1683 | RETURN(); | |
1684 | } | |
1685 | ||
1686 | void OPPROTO op_405_mulchwu (void) | |
1687 | { | |
1688 | T0 = ((uint16_t)T0) * ((uint16_t)(T1 >> 16)); | |
1689 | RETURN(); | |
1690 | } | |
1691 | ||
1692 | void OPPROTO op_405_mulhhw (void) | |
1693 | { | |
1694 | T0 = ((int16_t)(T0 >> 16)) * ((int16_t)(T1 >> 16)); | |
1695 | RETURN(); | |
1696 | } | |
1697 | ||
1698 | void OPPROTO op_405_mulhhwu (void) | |
1699 | { | |
1700 | T0 = ((uint16_t)(T0 >> 16)) * ((uint16_t)(T1 >> 16)); | |
1701 | RETURN(); | |
1702 | } | |
1703 | ||
1704 | void OPPROTO op_405_mullhw (void) | |
1705 | { | |
1706 | T0 = ((int16_t)T0) * ((int16_t)T1); | |
1707 | RETURN(); | |
1708 | } | |
1709 | ||
1710 | void OPPROTO op_405_mullhwu (void) | |
1711 | { | |
1712 | T0 = ((uint16_t)T0) * ((uint16_t)T1); | |
1713 | RETURN(); | |
1714 | } | |
1715 | ||
1716 | void OPPROTO op_405_check_ov (void) | |
1717 | { | |
1718 | do_405_check_ov(); | |
1719 | RETURN(); | |
1720 | } | |
1721 | ||
1722 | void OPPROTO op_405_check_sat (void) | |
1723 | { | |
1724 | do_405_check_sat(); | |
1725 | RETURN(); | |
1726 | } | |
1727 | ||
1728 | void OPPROTO op_405_check_ovu (void) | |
1729 | { | |
1730 | if (likely(T0 >= T2)) { | |
1731 | xer_ov = 0; | |
1732 | } else { | |
1733 | xer_ov = 1; | |
1734 | xer_so = 1; | |
1735 | } | |
1736 | RETURN(); | |
1737 | } | |
1738 | ||
1739 | void OPPROTO op_405_check_satu (void) | |
1740 | { | |
1741 | if (unlikely(T0 < T2)) { | |
1742 | /* Saturate result */ | |
1743 | T0 = -1; | |
1744 | } | |
1745 | RETURN(); | |
1746 | } | |
1747 | ||
1748 | #if !defined(CONFIG_USER_ONLY) | |
1749 | void OPPROTO op_4xx_load_dcr (void) | |
1750 | { | |
1751 | do_4xx_load_dcr(PARAM1); | |
1752 | RETURN(); | |
1753 | } | |
1754 | ||
1755 | void OPPROTO op_4xx_store_dcr (void) | |
1756 | { | |
1757 | do_4xx_store_dcr(PARAM1); | |
1758 | RETURN(); | |
1759 | } | |
1760 | ||
1761 | /* Return from critical interrupt : | |
1762 | * same as rfi, except nip & MSR are loaded from SRR2/3 instead of SRR0/1 | |
1763 | */ | |
1764 | void OPPROTO op_4xx_rfci (void) | |
1765 | { | |
1766 | do_4xx_rfci(); | |
1767 | RETURN(); | |
1768 | } | |
1769 | ||
1770 | void OPPROTO op_4xx_wrte (void) | |
1771 | { | |
1772 | msr_ee = T0 >> 16; | |
1773 | RETURN(); | |
1774 | } | |
1775 | ||
1776 | void OPPROTO op_4xx_tlbre_lo (void) | |
1777 | { | |
1778 | do_4xx_tlbre_lo(); | |
1779 | RETURN(); | |
1780 | } | |
1781 | ||
1782 | void OPPROTO op_4xx_tlbre_hi (void) | |
1783 | { | |
1784 | do_4xx_tlbre_hi(); | |
1785 | RETURN(); | |
1786 | } | |
1787 | ||
1788 | void OPPROTO op_4xx_tlbsx (void) | |
1789 | { | |
1790 | do_4xx_tlbsx(); | |
1791 | RETURN(); | |
1792 | } | |
1793 | ||
1794 | void OPPROTO op_4xx_tlbsx_ (void) | |
1795 | { | |
1796 | do_4xx_tlbsx_(); | |
1797 | RETURN(); | |
1798 | } | |
1799 | ||
1800 | void OPPROTO op_4xx_tlbwe_lo (void) | |
1801 | { | |
1802 | do_4xx_tlbwe_lo(); | |
1803 | RETURN(); | |
1804 | } | |
1805 | ||
1806 | void OPPROTO op_4xx_tlbwe_hi (void) | |
1807 | { | |
1808 | do_4xx_tlbwe_hi(); | |
1809 | RETURN(); | |
1810 | } | |
1811 | #endif | |
1812 | ||
1813 | /* SPR micro-ops */ | |
1814 | /* 440 specific */ | |
1815 | void OPPROTO op_440_dlmzb (void) | |
1816 | { | |
1817 | do_440_dlmzb(); | |
1818 | RETURN(); | |
1819 | } | |
1820 | ||
1821 | void OPPROTO op_440_dlmzb_update_Rc (void) | |
1822 | { | |
1823 | if (T0 == 8) | |
1824 | T0 = 0x2; | |
1825 | else if (T0 < 4) | |
1826 | T0 = 0x4; | |
1827 | else | |
1828 | T0 = 0x8; | |
1829 | RETURN(); | |
1830 | } | |
1831 | ||
1832 | #if !defined(CONFIG_USER_ONLY) | |
1833 | void OPPROTO op_store_pir (void) | |
3fc6c082 FB |
1834 | { |
1835 | env->spr[SPR_PIR] = T0 & 0x0000000FUL; | |
1836 | RETURN(); | |
1837 | } | |
76a66253 JM |
1838 | |
1839 | void OPPROTO op_load_403_pb (void) | |
1840 | { | |
1841 | do_load_403_pb(PARAM1); | |
1842 | RETURN(); | |
1843 | } | |
1844 | ||
1845 | void OPPROTO op_store_403_pb (void) | |
1846 | { | |
1847 | do_store_403_pb(PARAM1); | |
1848 | RETURN(); | |
1849 | } | |
1850 | ||
1851 | target_ulong load_40x_pit (CPUState *env); | |
1852 | void OPPROTO op_load_40x_pit (void) | |
1853 | { | |
1854 | T0 = load_40x_pit(env); | |
1855 | RETURN(); | |
1856 | } | |
1857 | ||
1858 | void store_40x_pit (CPUState *env, target_ulong val); | |
1859 | void OPPROTO op_store_40x_pit (void) | |
1860 | { | |
1861 | store_40x_pit(env, T0); | |
1862 | RETURN(); | |
1863 | } | |
1864 | ||
1865 | void store_booke_tcr (CPUState *env, target_ulong val); | |
1866 | void OPPROTO op_store_booke_tcr (void) | |
1867 | { | |
1868 | store_booke_tcr(env, T0); | |
1869 | RETURN(); | |
1870 | } | |
1871 | ||
1872 | void store_booke_tsr (CPUState *env, target_ulong val); | |
1873 | void OPPROTO op_store_booke_tsr (void) | |
1874 | { | |
1875 | store_booke_tsr(env, T0); | |
1876 | RETURN(); | |
1877 | } | |
1878 | #endif /* !defined(CONFIG_USER_ONLY) */ |