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target-ppc: convert fp ops to TCG
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CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation micro-operations for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
a541f297
FB
21//#define DEBUG_OP
22
79aceca5
FB
23#include "config.h"
24#include "exec.h"
603fccce 25#include "host-utils.h"
0411a972 26#include "helper_regs.h"
76a66253 27#include "op_helper.h"
79aceca5 28
76a66253 29/* Generate exceptions */
36081602 30void OPPROTO op_raise_exception_err (void)
9a64fbe4 31{
36081602 32 do_raise_exception_err(PARAM1, PARAM2);
9a64fbe4
FB
33}
34
36081602 35void OPPROTO op_debug (void)
ea4e754f
FB
36{
37 do_raise_exception(EXCP_DEBUG);
38}
39
76a66253
JM
40#if !defined(CONFIG_USER_ONLY)
41/* Segment registers load and store */
36081602 42void OPPROTO op_load_sr (void)
76a66253 43{
36081602 44 T0 = env->sr[T1];
76a66253
JM
45 RETURN();
46}
47
36081602 48void OPPROTO op_store_sr (void)
76a66253
JM
49{
50 do_store_sr(env, T1, T0);
51 RETURN();
52}
53
12de9a39
JM
54#if defined(TARGET_PPC64)
55void OPPROTO op_load_slb (void)
56{
57 T0 = ppc_load_slb(env, T1);
58 RETURN();
59}
60
61void OPPROTO op_store_slb (void)
62{
63 ppc_store_slb(env, T1, T0);
64 RETURN();
65}
66#endif /* defined(TARGET_PPC64) */
67
36081602 68void OPPROTO op_load_sdr1 (void)
76a66253 69{
36081602 70 T0 = env->sdr1;
76a66253
JM
71 RETURN();
72}
73
36081602 74void OPPROTO op_store_sdr1 (void)
76a66253
JM
75{
76 do_store_sdr1(env, T0);
79aceca5
FB
77 RETURN();
78}
79
d9bce9d9
JM
80#if defined (TARGET_PPC64)
81void OPPROTO op_load_asr (void)
82{
83 T0 = env->asr;
84 RETURN();
85}
86
87void OPPROTO op_store_asr (void)
88{
89 ppc_store_asr(env, T0);
90 RETURN();
91}
92#endif
93
6676f424
AJ
94void OPPROTO op_load_msr (void)
95{
96 T0 = env->msr;
97 RETURN();
98}
99
100void OPPROTO op_store_msr (void)
101{
102 do_store_msr();
103 RETURN();
104}
105
106#if defined (TARGET_PPC64)
107void OPPROTO op_store_msr_32 (void)
108{
109 T0 = (env->msr & ~0xFFFFFFFFULL) | (T0 & 0xFFFFFFFF);
110 do_store_msr();
111 RETURN();
112}
113#endif
114
0411a972 115void OPPROTO op_update_riee (void)
d9bce9d9 116{
0411a972
JM
117 /* We don't call do_store_msr here as we won't trigger
118 * any special case nor change hflags
119 */
120 T0 &= (1 << MSR_RI) | (1 << MSR_EE);
121 env->msr &= ~(1 << MSR_RI) | (1 << MSR_EE);
122 env->msr |= T0;
d9bce9d9
JM
123 RETURN();
124}
125#endif
9a64fbe4
FB
126
127/* SPR */
a496775f
JM
128void OPPROTO op_load_spr (void)
129{
130 T0 = env->spr[PARAM1];
131 RETURN();
132}
133
134void OPPROTO op_store_spr (void)
135{
136 env->spr[PARAM1] = T0;
137 RETURN();
138}
139
140void OPPROTO op_load_dump_spr (void)
141{
142 T0 = ppc_load_dump_spr(PARAM1);
143 RETURN();
144}
145
146void OPPROTO op_store_dump_spr (void)
9a64fbe4 147{
a496775f 148 ppc_store_dump_spr(PARAM1, T0);
9a64fbe4
FB
149 RETURN();
150}
151
a496775f 152void OPPROTO op_mask_spr (void)
9a64fbe4 153{
a496775f 154 env->spr[PARAM1] &= ~T0;
79aceca5
FB
155 RETURN();
156}
157
36081602 158void OPPROTO op_load_tbl (void)
9a64fbe4 159{
36081602 160 T0 = cpu_ppc_load_tbl(env);
9a64fbe4
FB
161 RETURN();
162}
163
36081602 164void OPPROTO op_load_tbu (void)
9a64fbe4 165{
36081602 166 T0 = cpu_ppc_load_tbu(env);
9a64fbe4
FB
167 RETURN();
168}
169
a062e36c
JM
170void OPPROTO op_load_atbl (void)
171{
172 T0 = cpu_ppc_load_atbl(env);
173 RETURN();
174}
175
176void OPPROTO op_load_atbu (void)
177{
178 T0 = cpu_ppc_load_atbu(env);
179 RETURN();
180}
181
76a66253 182#if !defined(CONFIG_USER_ONLY)
36081602 183void OPPROTO op_store_tbl (void)
9a64fbe4 184{
36081602 185 cpu_ppc_store_tbl(env, T0);
79aceca5
FB
186 RETURN();
187}
188
36081602 189void OPPROTO op_store_tbu (void)
9a64fbe4 190{
36081602 191 cpu_ppc_store_tbu(env, T0);
9a64fbe4
FB
192 RETURN();
193}
194
a062e36c
JM
195void OPPROTO op_store_atbl (void)
196{
197 cpu_ppc_store_atbl(env, T0);
198 RETURN();
199}
200
201void OPPROTO op_store_atbu (void)
202{
203 cpu_ppc_store_atbu(env, T0);
204 RETURN();
205}
206
36081602 207void OPPROTO op_load_decr (void)
9a64fbe4 208{
36081602 209 T0 = cpu_ppc_load_decr(env);
76a66253
JM
210 RETURN();
211}
9fddaa0c 212
36081602 213void OPPROTO op_store_decr (void)
9fddaa0c 214{
36081602 215 cpu_ppc_store_decr(env, T0);
9a64fbe4
FB
216 RETURN();
217}
218
36081602 219void OPPROTO op_load_ibat (void)
9a64fbe4 220{
36081602 221 T0 = env->IBAT[PARAM1][PARAM2];
76a66253 222 RETURN();
9a64fbe4
FB
223}
224
76a66253 225void OPPROTO op_store_ibatu (void)
9a64fbe4 226{
3fc6c082
FB
227 do_store_ibatu(env, PARAM1, T0);
228 RETURN();
229}
230
76a66253 231void OPPROTO op_store_ibatl (void)
3fc6c082
FB
232{
233#if 1
234 env->IBAT[1][PARAM1] = T0;
235#else
236 do_store_ibatl(env, PARAM1, T0);
237#endif
238 RETURN();
9a64fbe4
FB
239}
240
36081602 241void OPPROTO op_load_dbat (void)
9a64fbe4 242{
36081602 243 T0 = env->DBAT[PARAM1][PARAM2];
76a66253 244 RETURN();
9a64fbe4
FB
245}
246
76a66253 247void OPPROTO op_store_dbatu (void)
3fc6c082
FB
248{
249 do_store_dbatu(env, PARAM1, T0);
250 RETURN();
251}
252
76a66253 253void OPPROTO op_store_dbatl (void)
9a64fbe4 254{
3fc6c082
FB
255#if 1
256 env->DBAT[1][PARAM1] = T0;
257#else
258 do_store_dbatl(env, PARAM1, T0);
259#endif
260 RETURN();
9a64fbe4 261}
76a66253 262#endif /* !defined(CONFIG_USER_ONLY) */
9a64fbe4 263
79aceca5 264/*** Integer shift ***/
76a66253
JM
265void OPPROTO op_srli_T1 (void)
266{
d9bce9d9 267 T1 = (uint32_t)T1 >> PARAM1;
76a66253
JM
268 RETURN();
269}
270
9a64fbe4 271/* Load and store */
9a64fbe4 272#define MEMSUFFIX _raw
76a66253 273#include "op_helper.h"
9a64fbe4 274#include "op_mem.h"
a541f297 275#if !defined(CONFIG_USER_ONLY)
9a64fbe4 276#define MEMSUFFIX _user
76a66253 277#include "op_helper.h"
9a64fbe4 278#include "op_mem.h"
9a64fbe4 279#define MEMSUFFIX _kernel
76a66253 280#include "op_helper.h"
9a64fbe4 281#include "op_mem.h"
1e42b8f0
JM
282#define MEMSUFFIX _hypv
283#include "op_helper.h"
284#include "op_mem.h"
285#endif
9a64fbe4 286
4b3686fa 287/* Special op to check and maybe clear reservation */
d9bce9d9 288void OPPROTO op_check_reservation (void)
4b3686fa 289{
fdabc366 290 if ((uint32_t)env->reserve == (uint32_t)(T0 & ~0x00000003))
a73666f6 291 env->reserve = (target_ulong)-1ULL;
4b3686fa
FB
292 RETURN();
293}
294
d9bce9d9
JM
295#if defined(TARGET_PPC64)
296void OPPROTO op_check_reservation_64 (void)
297{
298 if ((uint64_t)env->reserve == (uint64_t)(T0 & ~0x00000003))
6f2d8978 299 env->reserve = (target_ulong)-1ULL;
d9bce9d9
JM
300 RETURN();
301}
302#endif
303
be147d08
JM
304void OPPROTO op_wait (void)
305{
306 env->halted = 1;
307 RETURN();
308}
309
9a64fbe4 310/* Return from interrupt */
76a66253
JM
311#if !defined(CONFIG_USER_ONLY)
312void OPPROTO op_rfi (void)
28b6751f 313{
fdabc366 314 do_rfi();
fb0eaffc
FB
315 RETURN();
316}
d9bce9d9
JM
317
318#if defined(TARGET_PPC64)
426613db
JM
319void OPPROTO op_rfid (void)
320{
321 do_rfid();
322 RETURN();
323}
be147d08 324
be147d08
JM
325void OPPROTO op_hrfid (void)
326{
327 do_hrfid();
328 RETURN();
329}
330#endif
6f5d427d
JM
331
332/* Exception vectors */
333void OPPROTO op_store_excp_prefix (void)
334{
335 T0 &= env->ivpr_mask;
336 env->excp_prefix = T0;
337 RETURN();
338}
339
340void OPPROTO op_store_excp_vector (void)
341{
342 T0 &= env->ivor_mask;
343 env->excp_vectors[PARAM1] = T0;
344 RETURN();
345}
76a66253 346#endif
fb0eaffc 347
9a64fbe4 348/* Trap word */
76a66253 349void OPPROTO op_tw (void)
fb0eaffc 350{
76a66253 351 do_tw(PARAM1);
fb0eaffc
FB
352 RETURN();
353}
354
d9bce9d9
JM
355#if defined(TARGET_PPC64)
356void OPPROTO op_td (void)
357{
358 do_td(PARAM1);
359 RETURN();
360}
361#endif
362
76a66253 363#if !defined(CONFIG_USER_ONLY)
9a64fbe4 364/* tlbia */
36081602 365void OPPROTO op_tlbia (void)
fb0eaffc 366{
daf4f96e 367 ppc_tlb_invalidate_all(env);
9a64fbe4
FB
368 RETURN();
369}
370
371/* tlbie */
d9bce9d9 372void OPPROTO op_tlbie (void)
9a64fbe4 373{
daf4f96e 374 ppc_tlb_invalidate_one(env, (uint32_t)T0);
fb0eaffc 375 RETURN();
28b6751f 376}
d9bce9d9
JM
377
378#if defined(TARGET_PPC64)
379void OPPROTO op_tlbie_64 (void)
380{
daf4f96e 381 ppc_tlb_invalidate_one(env, T0);
d9bce9d9
JM
382 RETURN();
383}
384#endif
385
386#if defined(TARGET_PPC64)
387void OPPROTO op_slbia (void)
388{
daf4f96e 389 ppc_slb_invalidate_all(env);
d9bce9d9
JM
390 RETURN();
391}
392
393void OPPROTO op_slbie (void)
394{
daf4f96e
JM
395 ppc_slb_invalidate_one(env, (uint32_t)T0);
396 RETURN();
397}
398
399void OPPROTO op_slbie_64 (void)
400{
401 ppc_slb_invalidate_one(env, T0);
d9bce9d9
JM
402 RETURN();
403}
404#endif
76a66253 405#endif
3fc6c082 406
76a66253 407#if !defined(CONFIG_USER_ONLY)
7dbe11ac 408/* PowerPC 602/603/755 software TLB load instructions */
76a66253
JM
409void OPPROTO op_6xx_tlbld (void)
410{
411 do_load_6xx_tlb(0);
412 RETURN();
413}
414
415void OPPROTO op_6xx_tlbli (void)
416{
417 do_load_6xx_tlb(1);
418 RETURN();
419}
7dbe11ac
JM
420
421/* PowerPC 74xx software TLB load instructions */
422void OPPROTO op_74xx_tlbld (void)
423{
424 do_load_74xx_tlb(0);
425 RETURN();
426}
427
428void OPPROTO op_74xx_tlbli (void)
429{
430 do_load_74xx_tlb(1);
431 RETURN();
432}
76a66253
JM
433#endif
434
435/* 601 specific */
76a66253
JM
436void OPPROTO op_load_601_rtcl (void)
437{
438 T0 = cpu_ppc601_load_rtcl(env);
439 RETURN();
440}
441
76a66253
JM
442void OPPROTO op_load_601_rtcu (void)
443{
444 T0 = cpu_ppc601_load_rtcu(env);
445 RETURN();
446}
447
448#if !defined(CONFIG_USER_ONLY)
76a66253
JM
449void OPPROTO op_store_601_rtcl (void)
450{
451 cpu_ppc601_store_rtcl(env, T0);
452 RETURN();
453}
454
76a66253
JM
455void OPPROTO op_store_601_rtcu (void)
456{
457 cpu_ppc601_store_rtcu(env, T0);
458 RETURN();
459}
460
056401ea
JM
461void OPPROTO op_store_hid0_601 (void)
462{
463 do_store_hid0_601();
464 RETURN();
465}
466
76a66253
JM
467void OPPROTO op_load_601_bat (void)
468{
469 T0 = env->IBAT[PARAM1][PARAM2];
470 RETURN();
471}
76a66253 472
76a66253
JM
473void OPPROTO op_store_601_batl (void)
474{
056401ea 475 do_store_ibatl_601(env, PARAM1, T0);
76a66253
JM
476 RETURN();
477}
478
479void OPPROTO op_store_601_batu (void)
480{
056401ea 481 do_store_ibatu_601(env, PARAM1, T0);
76a66253
JM
482 RETURN();
483}
484#endif /* !defined(CONFIG_USER_ONLY) */
485
486/* PowerPC 601 specific instructions (POWER bridge) */
487/* XXX: those micro-ops need tests ! */
488void OPPROTO op_POWER_abs (void)
489{
9c7e37e7 490 if ((int32_t)T0 == INT32_MIN)
76a66253 491 T0 = INT32_MAX;
9c7e37e7 492 else if ((int32_t)T0 < 0)
76a66253
JM
493 T0 = -T0;
494 RETURN();
495}
496
497void OPPROTO op_POWER_abso (void)
498{
499 do_POWER_abso();
500 RETURN();
501}
502
503void OPPROTO op_POWER_clcs (void)
504{
505 do_POWER_clcs();
506 RETURN();
507}
508
509void OPPROTO op_POWER_div (void)
510{
511 do_POWER_div();
512 RETURN();
513}
514
515void OPPROTO op_POWER_divo (void)
516{
517 do_POWER_divo();
518 RETURN();
519}
520
521void OPPROTO op_POWER_divs (void)
522{
523 do_POWER_divs();
524 RETURN();
525}
526
527void OPPROTO op_POWER_divso (void)
528{
529 do_POWER_divso();
530 RETURN();
531}
532
533void OPPROTO op_POWER_doz (void)
534{
d9bce9d9 535 if ((int32_t)T1 > (int32_t)T0)
76a66253
JM
536 T0 = T1 - T0;
537 else
538 T0 = 0;
539 RETURN();
540}
541
542void OPPROTO op_POWER_dozo (void)
543{
544 do_POWER_dozo();
545 RETURN();
546}
547
548void OPPROTO op_load_xer_cmp (void)
549{
550 T2 = xer_cmp;
551 RETURN();
552}
553
554void OPPROTO op_POWER_maskg (void)
555{
556 do_POWER_maskg();
557 RETURN();
558}
559
560void OPPROTO op_POWER_maskir (void)
561{
562 T0 = (T0 & ~T2) | (T1 & T2);
563 RETURN();
564}
565
566void OPPROTO op_POWER_mul (void)
567{
568 uint64_t tmp;
569
570 tmp = (uint64_t)T0 * (uint64_t)T1;
571 env->spr[SPR_MQ] = tmp >> 32;
572 T0 = tmp;
573 RETURN();
574}
575
576void OPPROTO op_POWER_mulo (void)
577{
578 do_POWER_mulo();
579 RETURN();
580}
581
582void OPPROTO op_POWER_nabs (void)
583{
584 if (T0 > 0)
585 T0 = -T0;
586 RETURN();
587}
588
589void OPPROTO op_POWER_nabso (void)
590{
591 /* nabs never overflows */
592 if (T0 > 0)
593 T0 = -T0;
3d7b417e 594 env->xer &= ~(1 << XER_OV);
76a66253
JM
595 RETURN();
596}
597
598/* XXX: factorise POWER rotates... */
599void OPPROTO op_POWER_rlmi (void)
600{
601 T0 = rotl32(T0, T2) & PARAM1;
2f401176 602 T0 |= T1 & (uint32_t)PARAM2;
76a66253
JM
603 RETURN();
604}
605
606void OPPROTO op_POWER_rrib (void)
607{
608 T2 &= 0x1FUL;
609 T0 = rotl32(T0 & INT32_MIN, T2);
610 T0 |= T1 & ~rotl32(INT32_MIN, T2);
611 RETURN();
612}
613
614void OPPROTO op_POWER_sle (void)
615{
616 T1 &= 0x1FUL;
617 env->spr[SPR_MQ] = rotl32(T0, T1);
618 T0 = T0 << T1;
619 RETURN();
620}
621
622void OPPROTO op_POWER_sleq (void)
623{
624 uint32_t tmp = env->spr[SPR_MQ];
625
626 T1 &= 0x1FUL;
627 env->spr[SPR_MQ] = rotl32(T0, T1);
628 T0 = T0 << T1;
629 T0 |= tmp >> (32 - T1);
630 RETURN();
631}
632
633void OPPROTO op_POWER_sllq (void)
634{
6f2d8978 635 uint32_t msk = UINT32_MAX;
76a66253
JM
636
637 msk = msk << (T1 & 0x1FUL);
638 if (T1 & 0x20UL)
639 msk = ~msk;
640 T1 &= 0x1FUL;
641 T0 = (T0 << T1) & msk;
642 T0 |= env->spr[SPR_MQ] & ~msk;
643 RETURN();
644}
645
646void OPPROTO op_POWER_slq (void)
647{
6f2d8978 648 uint32_t msk = UINT32_MAX, tmp;
76a66253
JM
649
650 msk = msk << (T1 & 0x1FUL);
651 if (T1 & 0x20UL)
652 msk = ~msk;
653 T1 &= 0x1FUL;
654 tmp = rotl32(T0, T1);
655 T0 = tmp & msk;
656 env->spr[SPR_MQ] = tmp;
657 RETURN();
658}
659
660void OPPROTO op_POWER_sraq (void)
661{
662 env->spr[SPR_MQ] = rotl32(T0, 32 - (T1 & 0x1FUL));
663 if (T1 & 0x20UL)
6f2d8978 664 T0 = UINT32_MAX;
76a66253 665 else
d9bce9d9 666 T0 = (int32_t)T0 >> T1;
76a66253
JM
667 RETURN();
668}
669
670void OPPROTO op_POWER_sre (void)
671{
672 T1 &= 0x1FUL;
673 env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
d9bce9d9 674 T0 = (int32_t)T0 >> T1;
76a66253
JM
675 RETURN();
676}
677
678void OPPROTO op_POWER_srea (void)
679{
680 T1 &= 0x1FUL;
681 env->spr[SPR_MQ] = T0 >> T1;
d9bce9d9 682 T0 = (int32_t)T0 >> T1;
76a66253
JM
683 RETURN();
684}
685
686void OPPROTO op_POWER_sreq (void)
687{
688 uint32_t tmp;
689 int32_t msk;
690
691 T1 &= 0x1FUL;
692 msk = INT32_MIN >> T1;
693 tmp = env->spr[SPR_MQ];
694 env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
695 T0 = T0 >> T1;
696 T0 |= tmp & msk;
697 RETURN();
698}
699
700void OPPROTO op_POWER_srlq (void)
701{
702 uint32_t tmp;
703 int32_t msk;
704
705 msk = INT32_MIN >> (T1 & 0x1FUL);
706 if (T1 & 0x20UL)
707 msk = ~msk;
708 T1 &= 0x1FUL;
709 tmp = env->spr[SPR_MQ];
710 env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
711 T0 = T0 >> T1;
712 T0 &= msk;
713 T0 |= tmp & ~msk;
714 RETURN();
715}
716
717void OPPROTO op_POWER_srq (void)
718{
719 T1 &= 0x1FUL;
720 env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
721 T0 = T0 >> T1;
722 RETURN();
723}
724
725/* POWER instructions not implemented in PowerPC 601 */
726#if !defined(CONFIG_USER_ONLY)
727void OPPROTO op_POWER_mfsri (void)
728{
729 T1 = T0 >> 28;
730 T0 = env->sr[T1];
731 RETURN();
732}
733
734void OPPROTO op_POWER_rac (void)
735{
736 do_POWER_rac();
737 RETURN();
738}
739
740void OPPROTO op_POWER_rfsvc (void)
741{
742 do_POWER_rfsvc();
743 RETURN();
744}
745#endif
746
747/* PowerPC 602 specific instruction */
748#if !defined(CONFIG_USER_ONLY)
749void OPPROTO op_602_mfrom (void)
750{
751 do_op_602_mfrom();
752 RETURN();
753}
754#endif
755
756/* PowerPC 4xx specific micro-ops */
a42bd6cc 757void OPPROTO op_load_dcr (void)
76a66253 758{
a42bd6cc 759 do_load_dcr();
76a66253
JM
760 RETURN();
761}
762
a42bd6cc 763void OPPROTO op_store_dcr (void)
76a66253 764{
a42bd6cc 765 do_store_dcr();
76a66253
JM
766 RETURN();
767}
768
a750fc0b 769#if !defined(CONFIG_USER_ONLY)
76a66253
JM
770/* Return from critical interrupt :
771 * same as rfi, except nip & MSR are loaded from SRR2/3 instead of SRR0/1
772 */
a42bd6cc
JM
773void OPPROTO op_40x_rfci (void)
774{
775 do_40x_rfci();
776 RETURN();
777}
778
779void OPPROTO op_rfci (void)
780{
781 do_rfci();
782 RETURN();
783}
784
785void OPPROTO op_rfdi (void)
786{
787 do_rfdi();
788 RETURN();
789}
790
791void OPPROTO op_rfmci (void)
76a66253 792{
a42bd6cc 793 do_rfmci();
76a66253
JM
794 RETURN();
795}
796
a42bd6cc 797void OPPROTO op_wrte (void)
76a66253 798{
0411a972
JM
799 /* We don't call do_store_msr here as we won't trigger
800 * any special case nor change hflags
801 */
802 T0 &= 1 << MSR_EE;
803 env->msr &= ~(1 << MSR_EE);
804 env->msr |= T0;
76a66253
JM
805 RETURN();
806}
807
a4bb6c3e 808void OPPROTO op_440_tlbre (void)
5eb7995e 809{
a4bb6c3e 810 do_440_tlbre(PARAM1);
5eb7995e
JM
811 RETURN();
812}
813
a4bb6c3e 814void OPPROTO op_440_tlbsx (void)
5eb7995e 815{
daf4f96e 816 T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR] & 0xFF);
5eb7995e
JM
817 RETURN();
818}
819
daf4f96e 820void OPPROTO op_4xx_tlbsx_check (void)
5eb7995e 821{
daf4f96e
JM
822 int tmp;
823
824 tmp = xer_so;
6f2d8978 825 if ((int)T0 != -1)
daf4f96e
JM
826 tmp |= 0x02;
827 env->crf[0] = tmp;
5eb7995e
JM
828 RETURN();
829}
830
a4bb6c3e 831void OPPROTO op_440_tlbwe (void)
5eb7995e 832{
a4bb6c3e 833 do_440_tlbwe(PARAM1);
5eb7995e
JM
834 RETURN();
835}
836
76a66253
JM
837void OPPROTO op_4xx_tlbre_lo (void)
838{
839 do_4xx_tlbre_lo();
840 RETURN();
841}
842
843void OPPROTO op_4xx_tlbre_hi (void)
844{
845 do_4xx_tlbre_hi();
846 RETURN();
847}
848
849void OPPROTO op_4xx_tlbsx (void)
850{
daf4f96e 851 T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]);
76a66253
JM
852 RETURN();
853}
854
855void OPPROTO op_4xx_tlbwe_lo (void)
856{
857 do_4xx_tlbwe_lo();
858 RETURN();
859}
860
861void OPPROTO op_4xx_tlbwe_hi (void)
862{
863 do_4xx_tlbwe_hi();
864 RETURN();
865}
866#endif
867
868/* SPR micro-ops */
869/* 440 specific */
870void OPPROTO op_440_dlmzb (void)
871{
872 do_440_dlmzb();
873 RETURN();
874}
875
876void OPPROTO op_440_dlmzb_update_Rc (void)
877{
878 if (T0 == 8)
879 T0 = 0x2;
880 else if (T0 < 4)
881 T0 = 0x4;
882 else
883 T0 = 0x8;
884 RETURN();
885}
886
887#if !defined(CONFIG_USER_ONLY)
888void OPPROTO op_store_pir (void)
3fc6c082
FB
889{
890 env->spr[SPR_PIR] = T0 & 0x0000000FUL;
891 RETURN();
892}
76a66253
JM
893
894void OPPROTO op_load_403_pb (void)
895{
896 do_load_403_pb(PARAM1);
897 RETURN();
898}
899
900void OPPROTO op_store_403_pb (void)
901{
902 do_store_403_pb(PARAM1);
903 RETURN();
904}
905
76a66253
JM
906void OPPROTO op_load_40x_pit (void)
907{
908 T0 = load_40x_pit(env);
909 RETURN();
910}
911
76a66253
JM
912void OPPROTO op_store_40x_pit (void)
913{
914 store_40x_pit(env, T0);
915 RETURN();
916}
917
8ecc7913
JM
918void OPPROTO op_store_40x_dbcr0 (void)
919{
920 store_40x_dbcr0(env, T0);
be147d08 921 RETURN();
8ecc7913
JM
922}
923
c294fc58
JM
924void OPPROTO op_store_40x_sler (void)
925{
926 store_40x_sler(env, T0);
927 RETURN();
928}
929
76a66253
JM
930void OPPROTO op_store_booke_tcr (void)
931{
932 store_booke_tcr(env, T0);
933 RETURN();
934}
935
76a66253
JM
936void OPPROTO op_store_booke_tsr (void)
937{
938 store_booke_tsr(env, T0);
939 RETURN();
940}
941#endif /* !defined(CONFIG_USER_ONLY) */
0487d6a8 942
0487d6a8
JM
943/* SPE extension */
944void OPPROTO op_splatw_T1_64 (void)
945{
946 T1_64 = (T1_64 << 32) | (T1_64 & 0x00000000FFFFFFFFULL);
e864cabd 947 RETURN();
0487d6a8
JM
948}
949
0487d6a8
JM
950void OPPROTO op_extsh_T1_64 (void)
951{
952 T1_64 = (int32_t)((int16_t)T1_64);
953 RETURN();
954}
955
956void OPPROTO op_sli16_T1_64 (void)
957{
958 T1_64 = T1_64 << 16;
959 RETURN();
960}
961
962void OPPROTO op_sli32_T1_64 (void)
963{
964 T1_64 = T1_64 << 32;
965 RETURN();
966}
967
968void OPPROTO op_srli32_T1_64 (void)
969{
970 T1_64 = T1_64 >> 32;
971 RETURN();
972}
973
0487d6a8
JM
974void OPPROTO op_evfssub (void)
975{
976 do_evfssub();
977 RETURN();
978}
979
980void OPPROTO op_evfsadd (void)
981{
982 do_evfsadd();
983 RETURN();
984}
985
986void OPPROTO op_evfsnabs (void)
987{
988 do_evfsnabs();
989 RETURN();
990}
991
992void OPPROTO op_evfsabs (void)
993{
994 do_evfsabs();
995 RETURN();
996}
997
998void OPPROTO op_evfsneg (void)
999{
1000 do_evfsneg();
1001 RETURN();
1002}
1003
1004void OPPROTO op_evfsdiv (void)
1005{
1006 do_evfsdiv();
1007 RETURN();
1008}
1009
1010void OPPROTO op_evfsmul (void)
1011{
1012 do_evfsmul();
1013 RETURN();
1014}
1015
1016void OPPROTO op_evfscmplt (void)
1017{
1018 do_evfscmplt();
1019 RETURN();
1020}
1021
1022void OPPROTO op_evfscmpgt (void)
1023{
1024 do_evfscmpgt();
1025 RETURN();
1026}
1027
1028void OPPROTO op_evfscmpeq (void)
1029{
1030 do_evfscmpeq();
1031 RETURN();
1032}
1033
1034void OPPROTO op_evfscfsi (void)
1035{
1036 do_evfscfsi();
1037 RETURN();
1038}
1039
1040void OPPROTO op_evfscfui (void)
1041{
1042 do_evfscfui();
1043 RETURN();
1044}
1045
1046void OPPROTO op_evfscfsf (void)
1047{
1048 do_evfscfsf();
1049 RETURN();
1050}
1051
1052void OPPROTO op_evfscfuf (void)
1053{
1054 do_evfscfuf();
1055 RETURN();
1056}
1057
1058void OPPROTO op_evfsctsi (void)
1059{
1060 do_evfsctsi();
1061 RETURN();
1062}
1063
1064void OPPROTO op_evfsctui (void)
1065{
1066 do_evfsctui();
1067 RETURN();
1068}
1069
1070void OPPROTO op_evfsctsf (void)
1071{
1072 do_evfsctsf();
1073 RETURN();
1074}
1075
1076void OPPROTO op_evfsctuf (void)
1077{
1078 do_evfsctuf();
1079 RETURN();
1080}
1081
1082void OPPROTO op_evfsctuiz (void)
1083{
1084 do_evfsctuiz();
1085 RETURN();
1086}
1087
1088void OPPROTO op_evfsctsiz (void)
1089{
1090 do_evfsctsiz();
1091 RETURN();
1092}
1093
1094void OPPROTO op_evfststlt (void)
1095{
1096 do_evfststlt();
1097 RETURN();
1098}
1099
1100void OPPROTO op_evfststgt (void)
1101{
1102 do_evfststgt();
1103 RETURN();
1104}
1105
1106void OPPROTO op_evfststeq (void)
1107{
1108 do_evfststeq();
1109 RETURN();
1110}
1111
1112void OPPROTO op_efssub (void)
1113{
1114 T0_64 = _do_efssub(T0_64, T1_64);
1115 RETURN();
1116}
1117
1118void OPPROTO op_efsadd (void)
1119{
1120 T0_64 = _do_efsadd(T0_64, T1_64);
1121 RETURN();
1122}
1123
1124void OPPROTO op_efsnabs (void)
1125{
1126 T0_64 = _do_efsnabs(T0_64);
1127 RETURN();
1128}
1129
1130void OPPROTO op_efsabs (void)
1131{
1132 T0_64 = _do_efsabs(T0_64);
1133 RETURN();
1134}
1135
1136void OPPROTO op_efsneg (void)
1137{
1138 T0_64 = _do_efsneg(T0_64);
1139 RETURN();
1140}
1141
1142void OPPROTO op_efsdiv (void)
1143{
1144 T0_64 = _do_efsdiv(T0_64, T1_64);
1145 RETURN();
1146}
1147
1148void OPPROTO op_efsmul (void)
1149{
1150 T0_64 = _do_efsmul(T0_64, T1_64);
1151 RETURN();
1152}
1153
1154void OPPROTO op_efscmplt (void)
1155{
1156 do_efscmplt();
1157 RETURN();
1158}
1159
1160void OPPROTO op_efscmpgt (void)
1161{
1162 do_efscmpgt();
1163 RETURN();
1164}
1165
1166void OPPROTO op_efscfd (void)
1167{
1168 do_efscfd();
1169 RETURN();
1170}
1171
1172void OPPROTO op_efscmpeq (void)
1173{
1174 do_efscmpeq();
1175 RETURN();
1176}
1177
1178void OPPROTO op_efscfsi (void)
1179{
1180 do_efscfsi();
1181 RETURN();
1182}
1183
1184void OPPROTO op_efscfui (void)
1185{
1186 do_efscfui();
1187 RETURN();
1188}
1189
1190void OPPROTO op_efscfsf (void)
1191{
1192 do_efscfsf();
1193 RETURN();
1194}
1195
1196void OPPROTO op_efscfuf (void)
1197{
1198 do_efscfuf();
1199 RETURN();
1200}
1201
1202void OPPROTO op_efsctsi (void)
1203{
1204 do_efsctsi();
1205 RETURN();
1206}
1207
1208void OPPROTO op_efsctui (void)
1209{
1210 do_efsctui();
1211 RETURN();
1212}
1213
1214void OPPROTO op_efsctsf (void)
1215{
1216 do_efsctsf();
1217 RETURN();
1218}
1219
1220void OPPROTO op_efsctuf (void)
1221{
1222 do_efsctuf();
1223 RETURN();
1224}
1225
1226void OPPROTO op_efsctsiz (void)
1227{
1228 do_efsctsiz();
1229 RETURN();
1230}
1231
1232void OPPROTO op_efsctuiz (void)
1233{
1234 do_efsctuiz();
1235 RETURN();
1236}
1237
1238void OPPROTO op_efststlt (void)
1239{
1240 T0 = _do_efststlt(T0_64, T1_64);
1241 RETURN();
1242}
1243
1244void OPPROTO op_efststgt (void)
1245{
1246 T0 = _do_efststgt(T0_64, T1_64);
1247 RETURN();
1248}
1249
1250void OPPROTO op_efststeq (void)
1251{
1252 T0 = _do_efststeq(T0_64, T1_64);
1253 RETURN();
1254}
1255
1256void OPPROTO op_efdsub (void)
1257{
0ca9d380
AJ
1258 CPU_DoubleU u1, u2;
1259 u1.ll = T0_64;
1260 u2.ll = T1_64;
1261 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
1262 T0_64 = u1.ll;
0487d6a8
JM
1263 RETURN();
1264}
1265
1266void OPPROTO op_efdadd (void)
1267{
0ca9d380
AJ
1268 CPU_DoubleU u1, u2;
1269 u1.ll = T0_64;
1270 u2.ll = T1_64;
1271 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
1272 T0_64 = u1.ll;
0487d6a8
JM
1273 RETURN();
1274}
1275
1276void OPPROTO op_efdcfsid (void)
1277{
1278 do_efdcfsi();
1279 RETURN();
1280}
1281
1282void OPPROTO op_efdcfuid (void)
1283{
1284 do_efdcfui();
1285 RETURN();
1286}
1287
1288void OPPROTO op_efdnabs (void)
1289{
1290 T0_64 |= 0x8000000000000000ULL;
1291 RETURN();
1292}
1293
1294void OPPROTO op_efdabs (void)
1295{
1296 T0_64 &= ~0x8000000000000000ULL;
1297 RETURN();
1298}
1299
1300void OPPROTO op_efdneg (void)
1301{
1302 T0_64 ^= 0x8000000000000000ULL;
1303 RETURN();
1304}
1305
1306void OPPROTO op_efddiv (void)
1307{
0ca9d380
AJ
1308 CPU_DoubleU u1, u2;
1309 u1.ll = T0_64;
1310 u2.ll = T1_64;
1311 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
1312 T0_64 = u1.ll;
0487d6a8
JM
1313 RETURN();
1314}
1315
1316void OPPROTO op_efdmul (void)
1317{
0ca9d380
AJ
1318 CPU_DoubleU u1, u2;
1319 u1.ll = T0_64;
1320 u2.ll = T1_64;
1321 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
1322 T0_64 = u1.ll;
0487d6a8
JM
1323 RETURN();
1324}
1325
1326void OPPROTO op_efdctsidz (void)
1327{
1328 do_efdctsiz();
1329 RETURN();
1330}
1331
1332void OPPROTO op_efdctuidz (void)
1333{
1334 do_efdctuiz();
1335 RETURN();
1336}
1337
1338void OPPROTO op_efdcmplt (void)
1339{
1340 do_efdcmplt();
1341 RETURN();
1342}
1343
1344void OPPROTO op_efdcmpgt (void)
1345{
1346 do_efdcmpgt();
1347 RETURN();
1348}
1349
1350void OPPROTO op_efdcfs (void)
1351{
1352 do_efdcfs();
1353 RETURN();
1354}
1355
1356void OPPROTO op_efdcmpeq (void)
1357{
1358 do_efdcmpeq();
1359 RETURN();
1360}
1361
1362void OPPROTO op_efdcfsi (void)
1363{
1364 do_efdcfsi();
1365 RETURN();
1366}
1367
1368void OPPROTO op_efdcfui (void)
1369{
1370 do_efdcfui();
1371 RETURN();
1372}
1373
1374void OPPROTO op_efdcfsf (void)
1375{
1376 do_efdcfsf();
1377 RETURN();
1378}
1379
1380void OPPROTO op_efdcfuf (void)
1381{
1382 do_efdcfuf();
1383 RETURN();
1384}
1385
1386void OPPROTO op_efdctsi (void)
1387{
1388 do_efdctsi();
1389 RETURN();
1390}
1391
1392void OPPROTO op_efdctui (void)
1393{
1394 do_efdctui();
1395 RETURN();
1396}
1397
1398void OPPROTO op_efdctsf (void)
1399{
1400 do_efdctsf();
1401 RETURN();
1402}
1403
1404void OPPROTO op_efdctuf (void)
1405{
1406 do_efdctuf();
1407 RETURN();
1408}
1409
1410void OPPROTO op_efdctuiz (void)
1411{
1412 do_efdctuiz();
1413 RETURN();
1414}
1415
1416void OPPROTO op_efdctsiz (void)
1417{
1418 do_efdctsiz();
1419 RETURN();
1420}
1421
1422void OPPROTO op_efdtstlt (void)
1423{
1424 T0 = _do_efdtstlt(T0_64, T1_64);
1425 RETURN();
1426}
1427
1428void OPPROTO op_efdtstgt (void)
1429{
1430 T0 = _do_efdtstgt(T0_64, T1_64);
1431 RETURN();
1432}
1433
1434void OPPROTO op_efdtsteq (void)
1435{
1436 T0 = _do_efdtsteq(T0_64, T1_64);
1437 RETURN();
1438}