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target-ppc: convert arithmetic functions to TCG
[qemu.git] / target-ppc / op_helper.c
CommitLineData
9a64fbe4 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
9a64fbe4
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
9a64fbe4 20#include "exec.h"
603fccce 21#include "host-utils.h"
9a64fbe4 22
0411a972 23#include "helper_regs.h"
0487d6a8
JM		 24#include "op_helper.h"
25
9a64fbe4 26#define MEMSUFFIX _raw
0487d6a8 27#include "op_helper.h"
9a64fbe4 28#include "op_helper_mem.h"
a541f297 29#if !defined(CONFIG_USER_ONLY)
9a64fbe4 30#define MEMSUFFIX _user
0487d6a8 31#include "op_helper.h"
9a64fbe4
FB		 32#include "op_helper_mem.h"
33#define MEMSUFFIX _kernel
0487d6a8 34#include "op_helper.h"
9a64fbe4 35#include "op_helper_mem.h"
1e42b8f0
JM		 36#define MEMSUFFIX _hypv
37#include "op_helper.h"
38#include "op_helper_mem.h"
39#endif
9a64fbe4 40
fdabc366
FB		 41//#define DEBUG_OP
42//#define DEBUG_EXCEPTIONS
76a66253 43//#define DEBUG_SOFTWARE_TLB
fdabc366 44
9a64fbe4
FB		 45/*****************************************************************************/
46/* Exceptions processing helpers */
9a64fbe4 47
9fddaa0c 48void do_raise_exception_err (uint32_t exception, int error_code)
9a64fbe4 49{
9fddaa0c
FB		 50#if 0
51 printf("Raise exception %3x code : %d\n", exception, error_code);
52#endif
9fddaa0c
FB		 53 env->exception_index = exception;
54 env->error_code = error_code;
76a66253
JM		 55 cpu_loop_exit();
56}
9fddaa0c
FB		 57
58void do_raise_exception (uint32_t exception)
59{
60 do_raise_exception_err(exception, 0);
9a64fbe4
FB		 61}
62
76a66253
JM		 63/*****************************************************************************/
64/* Registers load and stores */
e1571908 65uint32_t helper_load_cr (void)
76a66253 66{
e1571908
AJ		 67 return (env->crf[0] << 28) |
68 (env->crf[1] << 24) |
69 (env->crf[2] << 20) |
70 (env->crf[3] << 16) |
71 (env->crf[4] << 12) |
72 (env->crf[5] << 8) |
73 (env->crf[6] << 4) |
74 (env->crf[7] << 0);
76a66253
JM		 75}
76
e1571908 77void helper_store_cr (target_ulong val, uint32_t mask)
76a66253
JM		 78{
79 int i, sh;
80
36081602 81 for (i = 0, sh = 7; i < 8; i++, sh--) {
76a66253 82 if (mask & (1 << sh))
e1571908 83 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
76a66253
JM		 84 }
85}
86
c80f84e3
JM		 87#if defined(TARGET_PPC64)
88void do_store_pri (int prio)
89{
90 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
91 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
92}
93#endif
94
a496775f
JM		 95target_ulong ppc_load_dump_spr (int sprn)
96{
6b80055d 97 if (loglevel != 0) {
a496775f
JM		 98 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
99 sprn, sprn, env->spr[sprn]);
100 }
101
102 return env->spr[sprn];
103}
104
105void ppc_store_dump_spr (int sprn, target_ulong val)
106{
6b80055d 107 if (loglevel != 0) {
a496775f
JM		 108 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
109 sprn, sprn, env->spr[sprn], val);
110 }
111 env->spr[sprn] = val;
112}
113
9a64fbe4 114/*****************************************************************************/
fdabc366 115/* Fixed point operations helpers */
d9bce9d9 116#if defined(TARGET_PPC64)
d9bce9d9 117
74637406
AJ		 118/* multiply high word */
119uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
fdabc366 120{
74637406 121 uint64_t tl, th;
fdabc366 122
74637406
AJ		 123 muls64(&tl, &th, arg1, arg2);
124 return th;
d9bce9d9 125}
d9bce9d9 126
74637406
AJ		 127/* multiply high word unsigned */
128uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
fdabc366 129{
74637406 130 uint64_t tl, th;
fdabc366 131
74637406
AJ		 132 mulu64(&tl, &th, arg1, arg2);
133 return th;
fdabc366
FB		 134}
135
74637406 136uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
fdabc366 137{
d9bce9d9
JM		 138 int64_t th;
139 uint64_t tl;
140
74637406 141 muls64(&tl, (uint64_t *)&th, arg1, arg2);
88ad920b 142 /* If th != 0 && th != -1, then we had an overflow */
6f2d8978 143 if (likely((uint64_t)(th + 1) <= 1)) {
3d7b417e 144 env->xer &= ~(1 << XER_OV);
fdabc366 145 } else {
3d7b417e 146 env->xer |= (1 << XER_OV) | (1 << XER_SO);
fdabc366 147 }
74637406 148 return (int64_t)tl;
d9bce9d9
JM		 149}
150#endif
151
26d67362 152target_ulong helper_cntlzw (target_ulong t)
603fccce 153{
26d67362 154 return clz32(t);
603fccce
JM		 155}
156
157#if defined(TARGET_PPC64)
26d67362 158target_ulong helper_cntlzd (target_ulong t)
603fccce 159{
26d67362 160 return clz64(t);
603fccce
JM		 161}
162#endif
163
9a64fbe4 164/* shift right arithmetic helper */
26d67362 165target_ulong helper_sraw (target_ulong value, target_ulong shift)
9a64fbe4
FB		 166{
167 int32_t ret;
168
26d67362
AJ		 169 if (likely(!(shift & 0x20))) {
170 if (likely((uint32_t)shift != 0)) {
171 shift &= 0x1f;
172 ret = (int32_t)value >> shift;
173 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
3d7b417e 174 env->xer &= ~(1 << XER_CA);
fdabc366 175 } else {
3d7b417e 176 env->xer |= (1 << XER_CA);
fdabc366
FB		 177 }
178 } else {
26d67362 179 ret = (int32_t)value;
3d7b417e 180 env->xer &= ~(1 << XER_CA);
fdabc366
FB		 181 }
182 } else {
26d67362
AJ		 183 ret = (int32_t)value >> 31;
184 if (ret) {
3d7b417e 185 env->xer |= (1 << XER_CA);
26d67362
AJ		 186 } else {
187 env->xer &= ~(1 << XER_CA);
76a66253 188 }
fdabc366 189 }
26d67362 190 return (target_long)ret;
9a64fbe4
FB		 191}
192
d9bce9d9 193#if defined(TARGET_PPC64)
26d67362 194target_ulong helper_srad (target_ulong value, target_ulong shift)
d9bce9d9
JM		 195{
196 int64_t ret;
197
26d67362
AJ		 198 if (likely(!(shift & 0x40))) {
199 if (likely((uint64_t)shift != 0)) {
200 shift &= 0x3f;
201 ret = (int64_t)value >> shift;
202 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
3d7b417e 203 env->xer &= ~(1 << XER_CA);
d9bce9d9 204 } else {
3d7b417e 205 env->xer |= (1 << XER_CA);
d9bce9d9
JM		 206 }
207 } else {
26d67362 208 ret = (int64_t)value;
3d7b417e 209 env->xer &= ~(1 << XER_CA);
d9bce9d9
JM		 210 }
211 } else {
26d67362
AJ		 212 ret = (int64_t)value >> 63;
213 if (ret) {
3d7b417e 214 env->xer |= (1 << XER_CA);
26d67362
AJ		 215 } else {
216 env->xer &= ~(1 << XER_CA);
d9bce9d9
JM		 217 }
218 }
26d67362 219 return ret;
d9bce9d9
JM		 220}
221#endif
222
26d67362 223target_ulong helper_popcntb (target_ulong val)
d9bce9d9
JM		 224{
225 uint32_t ret;
226 int i;
227
228 ret = 0;
229 for (i = 0; i < 32; i += 8)
26d67362
AJ		 230 ret |= ctpop8((val >> i) & 0xFF) << i;
231 return ret;
d9bce9d9
JM		 232}
233
234#if defined(TARGET_PPC64)
26d67362 235target_ulong helper_popcntb_64 (target_ulong val)
d9bce9d9
JM		 236{
237 uint64_t ret;
238 int i;
239
240 ret = 0;
241 for (i = 0; i < 64; i += 8)
26d67362
AJ		 242 ret |= ctpop8((val >> i) & 0xFF) << i;
243 return ret;
d9bce9d9
JM		 244}
245#endif
246
fdabc366 247/*****************************************************************************/
9a64fbe4 248/* Floating point operations helpers */
0ca9d380 249static always_inline int fpisneg (float64 d)
7c58044c 250{
0ca9d380 251 CPU_DoubleU u;
7c58044c 252
0ca9d380 253 u.d = d;
7c58044c 254
0ca9d380 255 return u.ll >> 63 != 0;
7c58044c
JM		 256}
257
0ca9d380 258static always_inline int isden (float64 d)
7c58044c 259{
0ca9d380 260 CPU_DoubleU u;
7c58044c 261
0ca9d380 262 u.d = d;
7c58044c 263
0ca9d380 264 return ((u.ll >> 52) & 0x7FF) == 0;
7c58044c
JM		 265}
266
0ca9d380 267static always_inline int iszero (float64 d)
7c58044c 268{
0ca9d380 269 CPU_DoubleU u;
7c58044c 270
0ca9d380 271 u.d = d;
7c58044c 272
0ca9d380 273 return (u.ll & ~0x8000000000000000ULL) == 0;
7c58044c
JM		 274}
275
0ca9d380 276static always_inline int isinfinity (float64 d)
7c58044c 277{
0ca9d380 278 CPU_DoubleU u;
7c58044c 279
0ca9d380 280 u.d = d;
7c58044c 281
0ca9d380
AJ		 282 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
283 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
7c58044c
JM		 284}
285
80621676
AJ		 286#ifdef CONFIG_SOFTFLOAT
287static always_inline int isfinite (float64 d)
288{
289 CPU_DoubleU u;
290
291 u.d = d;
292
293 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
294}
295
296static always_inline int isnormal (float64 d)
297{
298 CPU_DoubleU u;
299
300 u.d = d;
301
302 uint32_t exp = (u.ll >> 52) & 0x7FF;
303 return ((0 < exp) && (exp < 0x7FF));
304}
305#endif
306
7c58044c
JM		 307void do_compute_fprf (int set_fprf)
308{
309 int isneg;
310
311 isneg = fpisneg(FT0);
312 if (unlikely(float64_is_nan(FT0))) {
313 if (float64_is_signaling_nan(FT0)) {
314 /* Signaling NaN: flags are undefined */
315 T0 = 0x00;
316 } else {
317 /* Quiet NaN */
318 T0 = 0x11;
319 }
320 } else if (unlikely(isinfinity(FT0))) {
321 /* +/- infinity */
322 if (isneg)
323 T0 = 0x09;
324 else
325 T0 = 0x05;
326 } else {
327 if (iszero(FT0)) {
328 /* +/- zero */
329 if (isneg)
330 T0 = 0x12;
331 else
332 T0 = 0x02;
333 } else {
334 if (isden(FT0)) {
335 /* Denormalized numbers */
336 T0 = 0x10;
337 } else {
338 /* Normalized numbers */
339 T0 = 0x00;
340 }
341 if (isneg) {
342 T0 |= 0x08;
343 } else {
344 T0 |= 0x04;
345 }
346 }
347 }
348 if (set_fprf) {
349 /* We update FPSCR_FPRF */
350 env->fpscr &= ~(0x1F << FPSCR_FPRF);
351 env->fpscr |= T0 << FPSCR_FPRF;
352 }
353 /* We just need fpcc to update Rc1 */
354 T0 &= 0xF;
355}
356
357/* Floating-point invalid operations exception */
358static always_inline void fload_invalid_op_excp (int op)
359{
360 int ve;
361
362 ve = fpscr_ve;
363 if (op & POWERPC_EXCP_FP_VXSNAN) {
364 /* Operation on signaling NaN */
365 env->fpscr |= 1 << FPSCR_VXSNAN;
366 }
367 if (op & POWERPC_EXCP_FP_VXSOFT) {
368 /* Software-defined condition */
369 env->fpscr |= 1 << FPSCR_VXSOFT;
370 }
371 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
372 case POWERPC_EXCP_FP_VXISI:
373 /* Magnitude subtraction of infinities */
374 env->fpscr |= 1 << FPSCR_VXISI;
375 goto update_arith;
376 case POWERPC_EXCP_FP_VXIDI:
377 /* Division of infinity by infinity */
378 env->fpscr |= 1 << FPSCR_VXIDI;
379 goto update_arith;
380 case POWERPC_EXCP_FP_VXZDZ:
381 /* Division of zero by zero */
382 env->fpscr |= 1 << FPSCR_VXZDZ;
383 goto update_arith;
384 case POWERPC_EXCP_FP_VXIMZ:
385 /* Multiplication of zero by infinity */
386 env->fpscr |= 1 << FPSCR_VXIMZ;
387 goto update_arith;
388 case POWERPC_EXCP_FP_VXVC:
389 /* Ordered comparison of NaN */
390 env->fpscr |= 1 << FPSCR_VXVC;
391 env->fpscr &= ~(0xF << FPSCR_FPCC);
392 env->fpscr |= 0x11 << FPSCR_FPCC;
393 /* We must update the target FPR before raising the exception */
394 if (ve != 0) {
395 env->exception_index = POWERPC_EXCP_PROGRAM;
396 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
397 /* Update the floating-point enabled exception summary */
398 env->fpscr |= 1 << FPSCR_FEX;
399 /* Exception is differed */
400 ve = 0;
401 }
402 break;
403 case POWERPC_EXCP_FP_VXSQRT:
404 /* Square root of a negative number */
405 env->fpscr |= 1 << FPSCR_VXSQRT;
406 update_arith:
407 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
408 if (ve == 0) {
409 /* Set the result to quiet NaN */
6f2d8978 410 FT0 = UINT64_MAX;
7c58044c
JM		 411 env->fpscr &= ~(0xF << FPSCR_FPCC);
412 env->fpscr |= 0x11 << FPSCR_FPCC;
413 }
414 break;
415 case POWERPC_EXCP_FP_VXCVI:
416 /* Invalid conversion */
417 env->fpscr |= 1 << FPSCR_VXCVI;
418 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
419 if (ve == 0) {
420 /* Set the result to quiet NaN */
6f2d8978 421 FT0 = UINT64_MAX;
7c58044c
JM		 422 env->fpscr &= ~(0xF << FPSCR_FPCC);
423 env->fpscr |= 0x11 << FPSCR_FPCC;
424 }
425 break;
426 }
427 /* Update the floating-point invalid operation summary */
428 env->fpscr |= 1 << FPSCR_VX;
429 /* Update the floating-point exception summary */
430 env->fpscr |= 1 << FPSCR_FX;
431 if (ve != 0) {
432 /* Update the floating-point enabled exception summary */
433 env->fpscr |= 1 << FPSCR_FEX;
434 if (msr_fe0 != 0 || msr_fe1 != 0)
435 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
436 }
437}
438
439static always_inline void float_zero_divide_excp (void)
440{
0ca9d380 441 CPU_DoubleU u0, u1;
7c58044c
JM		 442
443 env->fpscr |= 1 << FPSCR_ZX;
444 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
445 /* Update the floating-point exception summary */
446 env->fpscr |= 1 << FPSCR_FX;
447 if (fpscr_ze != 0) {
448 /* Update the floating-point enabled exception summary */
449 env->fpscr |= 1 << FPSCR_FEX;
450 if (msr_fe0 != 0 || msr_fe1 != 0) {
451 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
452 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
453 }
454 } else {
455 /* Set the result to infinity */
0ca9d380
AJ		 456 u0.d = FT0;
457 u1.d = FT1;
458 u0.ll = ((u0.ll ^ u1.ll) & 0x8000000000000000ULL);
459 u0.ll |= 0x7FFULL << 52;
460 FT0 = u0.d;
7c58044c
JM		 461 }
462}
463
464static always_inline void float_overflow_excp (void)
465{
466 env->fpscr |= 1 << FPSCR_OX;
467 /* Update the floating-point exception summary */
468 env->fpscr |= 1 << FPSCR_FX;
469 if (fpscr_oe != 0) {
470 /* XXX: should adjust the result */
471 /* Update the floating-point enabled exception summary */
472 env->fpscr |= 1 << FPSCR_FEX;
473 /* We must update the target FPR before raising the exception */
474 env->exception_index = POWERPC_EXCP_PROGRAM;
475 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
476 } else {
477 env->fpscr |= 1 << FPSCR_XX;
478 env->fpscr |= 1 << FPSCR_FI;
479 }
480}
481
482static always_inline void float_underflow_excp (void)
483{
484 env->fpscr |= 1 << FPSCR_UX;
485 /* Update the floating-point exception summary */
486 env->fpscr |= 1 << FPSCR_FX;
487 if (fpscr_ue != 0) {
488 /* XXX: should adjust the result */
489 /* Update the floating-point enabled exception summary */
490 env->fpscr |= 1 << FPSCR_FEX;
491 /* We must update the target FPR before raising the exception */
492 env->exception_index = POWERPC_EXCP_PROGRAM;
493 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
494 }
495}
496
497static always_inline void float_inexact_excp (void)
498{
499 env->fpscr |= 1 << FPSCR_XX;
500 /* Update the floating-point exception summary */
501 env->fpscr |= 1 << FPSCR_FX;
502 if (fpscr_xe != 0) {
503 /* Update the floating-point enabled exception summary */
504 env->fpscr |= 1 << FPSCR_FEX;
505 /* We must update the target FPR before raising the exception */
506 env->exception_index = POWERPC_EXCP_PROGRAM;
507 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
508 }
509}
510
511static always_inline void fpscr_set_rounding_mode (void)
512{
513 int rnd_type;
514
515 /* Set rounding mode */
516 switch (fpscr_rn) {
517 case 0:
518 /* Best approximation (round to nearest) */
519 rnd_type = float_round_nearest_even;
520 break;
521 case 1:
522 /* Smaller magnitude (round toward zero) */
523 rnd_type = float_round_to_zero;
524 break;
525 case 2:
526 /* Round toward +infinite */
527 rnd_type = float_round_up;
528 break;
529 default:
530 case 3:
531 /* Round toward -infinite */
532 rnd_type = float_round_down;
533 break;
534 }
535 set_float_rounding_mode(rnd_type, &env->fp_status);
536}
537
538void do_fpscr_setbit (int bit)
539{
540 int prev;
541
542 prev = (env->fpscr >> bit) & 1;
543 env->fpscr |= 1 << bit;
544 if (prev == 0) {
545 switch (bit) {
546 case FPSCR_VX:
547 env->fpscr |= 1 << FPSCR_FX;
548 if (fpscr_ve)
549 goto raise_ve;
550 case FPSCR_OX:
551 env->fpscr |= 1 << FPSCR_FX;
552 if (fpscr_oe)
553 goto raise_oe;
554 break;
555 case FPSCR_UX:
556 env->fpscr |= 1 << FPSCR_FX;
557 if (fpscr_ue)
558 goto raise_ue;
559 break;
560 case FPSCR_ZX:
561 env->fpscr |= 1 << FPSCR_FX;
562 if (fpscr_ze)
563 goto raise_ze;
564 break;
565 case FPSCR_XX:
566 env->fpscr |= 1 << FPSCR_FX;
567 if (fpscr_xe)
568 goto raise_xe;
569 break;
570 case FPSCR_VXSNAN:
571 case FPSCR_VXISI:
572 case FPSCR_VXIDI:
573 case FPSCR_VXZDZ:
574 case FPSCR_VXIMZ:
575 case FPSCR_VXVC:
576 case FPSCR_VXSOFT:
577 case FPSCR_VXSQRT:
578 case FPSCR_VXCVI:
579 env->fpscr |= 1 << FPSCR_VX;
580 env->fpscr |= 1 << FPSCR_FX;
581 if (fpscr_ve != 0)
582 goto raise_ve;
583 break;
584 case FPSCR_VE:
585 if (fpscr_vx != 0) {
586 raise_ve:
587 env->error_code = POWERPC_EXCP_FP;
588 if (fpscr_vxsnan)
589 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
590 if (fpscr_vxisi)
591 env->error_code |= POWERPC_EXCP_FP_VXISI;
592 if (fpscr_vxidi)
593 env->error_code |= POWERPC_EXCP_FP_VXIDI;
594 if (fpscr_vxzdz)
595 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
596 if (fpscr_vximz)
597 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
598 if (fpscr_vxvc)
599 env->error_code |= POWERPC_EXCP_FP_VXVC;
600 if (fpscr_vxsoft)
601 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
602 if (fpscr_vxsqrt)
603 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
604 if (fpscr_vxcvi)
605 env->error_code |= POWERPC_EXCP_FP_VXCVI;
606 goto raise_excp;
607 }
608 break;
609 case FPSCR_OE:
610 if (fpscr_ox != 0) {
611 raise_oe:
612 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
613 goto raise_excp;
614 }
615 break;
616 case FPSCR_UE:
617 if (fpscr_ux != 0) {
618 raise_ue:
619 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
620 goto raise_excp;
621 }
622 break;
623 case FPSCR_ZE:
624 if (fpscr_zx != 0) {
625 raise_ze:
626 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
627 goto raise_excp;
628 }
629 break;
630 case FPSCR_XE:
631 if (fpscr_xx != 0) {
632 raise_xe:
633 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
634 goto raise_excp;
635 }
636 break;
637 case FPSCR_RN1:
638 case FPSCR_RN:
639 fpscr_set_rounding_mode();
640 break;
641 default:
642 break;
643 raise_excp:
644 /* Update the floating-point enabled exception summary */
645 env->fpscr |= 1 << FPSCR_FEX;
646 /* We have to update Rc1 before raising the exception */
647 env->exception_index = POWERPC_EXCP_PROGRAM;
648 break;
649 }
650 }
651}
652
653#if defined(WORDS_BIGENDIAN)
654#define WORD0 0
655#define WORD1 1
656#else
657#define WORD0 1
658#define WORD1 0
659#endif
660void do_store_fpscr (uint32_t mask)
661{
662 /*
663 * We use only the 32 LSB of the incoming fpr
664 */
0ca9d380 665 CPU_DoubleU u;
7c58044c
JM		 666 uint32_t prev, new;
667 int i;
668
669 u.d = FT0;
670 prev = env->fpscr;
0ca9d380 671 new = u.l.lower;
7c58044c
JM		 672 new &= ~0x90000000;
673 new |= prev & 0x90000000;
674 for (i = 0; i < 7; i++) {
675 if (mask & (1 << i)) {
676 env->fpscr &= ~(0xF << (4 * i));
677 env->fpscr |= new & (0xF << (4 * i));
678 }
679 }
680 /* Update VX and FEX */
681 if (fpscr_ix != 0)
682 env->fpscr |= 1 << FPSCR_VX;
5567025f
AJ		 683 else
684 env->fpscr &= ~(1 << FPSCR_VX);
7c58044c
JM		 685 if ((fpscr_ex & fpscr_eex) != 0) {
686 env->fpscr |= 1 << FPSCR_FEX;
687 env->exception_index = POWERPC_EXCP_PROGRAM;
688 /* XXX: we should compute it properly */
689 env->error_code = POWERPC_EXCP_FP;
690 }
5567025f
AJ		 691 else
692 env->fpscr &= ~(1 << FPSCR_FEX);
7c58044c
JM		 693 fpscr_set_rounding_mode();
694}
695#undef WORD0
696#undef WORD1
697
698#ifdef CONFIG_SOFTFLOAT
699void do_float_check_status (void)
700{
701 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
702 (env->error_code & POWERPC_EXCP_FP)) {
703 /* Differred floating-point exception after target FPR update */
704 if (msr_fe0 != 0 || msr_fe1 != 0)
705 do_raise_exception_err(env->exception_index, env->error_code);
706 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
707 float_overflow_excp();
708 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
709 float_underflow_excp();
710 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
711 float_inexact_excp();
712 }
713}
714#endif
715
1cdb9c3d 716#if USE_PRECISE_EMULATION
7c58044c
JM		 717void do_fadd (void)
718{
719 if (unlikely(float64_is_signaling_nan(FT0) ||
720 float64_is_signaling_nan(FT1))) {
721 /* sNaN addition */
722 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
723 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
724 fpisneg(FT0) == fpisneg(FT1))) {
725 FT0 = float64_add(FT0, FT1, &env->fp_status);
726 } else {
727 /* Magnitude subtraction of infinities */
728 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
729 }
730}
731
732void do_fsub (void)
733{
734 if (unlikely(float64_is_signaling_nan(FT0) ||
735 float64_is_signaling_nan(FT1))) {
736 /* sNaN subtraction */
737 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
738 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
739 fpisneg(FT0) != fpisneg(FT1))) {
740 FT0 = float64_sub(FT0, FT1, &env->fp_status);
741 } else {
742 /* Magnitude subtraction of infinities */
743 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
744 }
745}
746
747void do_fmul (void)
748{
749 if (unlikely(float64_is_signaling_nan(FT0) ||
750 float64_is_signaling_nan(FT1))) {
751 /* sNaN multiplication */
752 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
5bda2843
JM		 753 } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
754 (iszero(FT0) && isinfinity(FT1)))) {
7c58044c
JM		 755 /* Multiplication of zero by infinity */
756 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
757 } else {
758 FT0 = float64_mul(FT0, FT1, &env->fp_status);
759 }
760}
761
762void do_fdiv (void)
763{
764 if (unlikely(float64_is_signaling_nan(FT0) ||
765 float64_is_signaling_nan(FT1))) {
766 /* sNaN division */
767 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
768 } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
769 /* Division of infinity by infinity */
770 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
771 } else if (unlikely(iszero(FT1))) {
772 if (iszero(FT0)) {
773 /* Division of zero by zero */
774 fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
775 } else {
776 /* Division by zero */
777 float_zero_divide_excp();
778 }
779 } else {
780 FT0 = float64_div(FT0, FT1, &env->fp_status);
781 }
782}
1cdb9c3d 783#endif /* USE_PRECISE_EMULATION */
7c58044c 784
9a64fbe4
FB		 785void do_fctiw (void)
786{
0ca9d380 787 CPU_DoubleU p;
9a64fbe4 788
7c58044c
JM		 789 if (unlikely(float64_is_signaling_nan(FT0))) {
790 /* sNaN conversion */
791 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
792 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
793 /* qNan / infinity conversion */
794 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
795 } else {
0ca9d380 796 p.ll = float64_to_int32(FT0, &env->fp_status);
1cdb9c3d 797#if USE_PRECISE_EMULATION
7c58044c
JM		 798 /* XXX: higher bits are not supposed to be significant.
799 * to make tests easier, return the same as a real PowerPC 750
800 */
0ca9d380 801 p.ll |= 0xFFF80000ULL << 32;
e864cabd 802#endif
7c58044c
JM		 803 FT0 = p.d;
804 }
9a64fbe4
FB		 805}
806
807void do_fctiwz (void)
808{
0ca9d380 809 CPU_DoubleU p;
4ecc3190 810
7c58044c
JM		 811 if (unlikely(float64_is_signaling_nan(FT0))) {
812 /* sNaN conversion */
813 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
814 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
815 /* qNan / infinity conversion */
816 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
817 } else {
0ca9d380 818 p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status);
1cdb9c3d 819#if USE_PRECISE_EMULATION
7c58044c
JM		 820 /* XXX: higher bits are not supposed to be significant.
821 * to make tests easier, return the same as a real PowerPC 750
822 */
0ca9d380 823 p.ll |= 0xFFF80000ULL << 32;
e864cabd 824#endif
7c58044c
JM		 825 FT0 = p.d;
826 }
9a64fbe4
FB		 827}
828
426613db
JM		 829#if defined(TARGET_PPC64)
830void do_fcfid (void)
831{
0ca9d380 832 CPU_DoubleU p;
426613db
JM		 833
834 p.d = FT0;
0ca9d380 835 FT0 = int64_to_float64(p.ll, &env->fp_status);
426613db
JM		 836}
837
838void do_fctid (void)
839{
0ca9d380 840 CPU_DoubleU p;
426613db 841
7c58044c
JM		 842 if (unlikely(float64_is_signaling_nan(FT0))) {
843 /* sNaN conversion */
844 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
845 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
846 /* qNan / infinity conversion */
847 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
848 } else {
0ca9d380 849 p.ll = float64_to_int64(FT0, &env->fp_status);
7c58044c
JM		 850 FT0 = p.d;
851 }
426613db
JM		 852}
853
854void do_fctidz (void)
855{
0ca9d380 856 CPU_DoubleU p;
426613db 857
7c58044c
JM		 858 if (unlikely(float64_is_signaling_nan(FT0))) {
859 /* sNaN conversion */
860 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
861 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
862 /* qNan / infinity conversion */
863 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
864 } else {
0ca9d380 865 p.ll = float64_to_int64_round_to_zero(FT0, &env->fp_status);
7c58044c
JM		 866 FT0 = p.d;
867 }
426613db
JM		 868}
869
870#endif
871
b068d6a7 872static always_inline void do_fri (int rounding_mode)
d7e4b87e 873{
7c58044c
JM		 874 if (unlikely(float64_is_signaling_nan(FT0))) {
875 /* sNaN round */
876 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
877 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
878 /* qNan / infinity round */
879 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
880 } else {
881 set_float_rounding_mode(rounding_mode, &env->fp_status);
882 FT0 = float64_round_to_int(FT0, &env->fp_status);
883 /* Restore rounding mode from FPSCR */
884 fpscr_set_rounding_mode();
885 }
d7e4b87e
JM		 886}
887
888void do_frin (void)
889{
890 do_fri(float_round_nearest_even);
891}
892
893void do_friz (void)
894{
895 do_fri(float_round_to_zero);
896}
897
898void do_frip (void)
899{
900 do_fri(float_round_up);
901}
902
903void do_frim (void)
904{
905 do_fri(float_round_down);
906}
907
1cdb9c3d 908#if USE_PRECISE_EMULATION
e864cabd
JM		 909void do_fmadd (void)
910{
7c58044c
JM		 911 if (unlikely(float64_is_signaling_nan(FT0) ||
912 float64_is_signaling_nan(FT1) ||
913 float64_is_signaling_nan(FT2))) {
914 /* sNaN operation */
915 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
916 } else {
e864cabd 917#ifdef FLOAT128
7c58044c
JM		 918 /* This is the way the PowerPC specification defines it */
919 float128 ft0_128, ft1_128;
920
921 ft0_128 = float64_to_float128(FT0, &env->fp_status);
922 ft1_128 = float64_to_float128(FT1, &env->fp_status);
923 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
924 ft1_128 = float64_to_float128(FT2, &env->fp_status);
925 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
926 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 927#else
7c58044c
JM		 928 /* This is OK on x86 hosts */
929 FT0 = (FT0 * FT1) + FT2;
e864cabd 930#endif
7c58044c 931 }
e864cabd
JM		 932}
933
934void do_fmsub (void)
935{
7c58044c
JM		 936 if (unlikely(float64_is_signaling_nan(FT0) ||
937 float64_is_signaling_nan(FT1) ||
938 float64_is_signaling_nan(FT2))) {
939 /* sNaN operation */
940 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
941 } else {
e864cabd 942#ifdef FLOAT128
7c58044c
JM		 943 /* This is the way the PowerPC specification defines it */
944 float128 ft0_128, ft1_128;
945
946 ft0_128 = float64_to_float128(FT0, &env->fp_status);
947 ft1_128 = float64_to_float128(FT1, &env->fp_status);
948 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
949 ft1_128 = float64_to_float128(FT2, &env->fp_status);
950 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
951 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 952#else
7c58044c
JM		 953 /* This is OK on x86 hosts */
954 FT0 = (FT0 * FT1) - FT2;
e864cabd 955#endif
7c58044c 956 }
e864cabd 957}
1cdb9c3d 958#endif /* USE_PRECISE_EMULATION */
e864cabd 959
4b3686fa
FB		 960void do_fnmadd (void)
961{
7c58044c
JM		 962 if (unlikely(float64_is_signaling_nan(FT0) ||
963 float64_is_signaling_nan(FT1) ||
964 float64_is_signaling_nan(FT2))) {
965 /* sNaN operation */
966 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
967 } else {
1cdb9c3d 968#if USE_PRECISE_EMULATION
e864cabd 969#ifdef FLOAT128
7c58044c
JM		 970 /* This is the way the PowerPC specification defines it */
971 float128 ft0_128, ft1_128;
972
973 ft0_128 = float64_to_float128(FT0, &env->fp_status);
974 ft1_128 = float64_to_float128(FT1, &env->fp_status);
975 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
976 ft1_128 = float64_to_float128(FT2, &env->fp_status);
977 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
978 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 979#else
7c58044c
JM		 980 /* This is OK on x86 hosts */
981 FT0 = (FT0 * FT1) + FT2;
e864cabd
JM		 982#endif
983#else
7c58044c
JM		 984 FT0 = float64_mul(FT0, FT1, &env->fp_status);
985 FT0 = float64_add(FT0, FT2, &env->fp_status);
e864cabd 986#endif
7c58044c
JM		 987 if (likely(!isnan(FT0)))
988 FT0 = float64_chs(FT0);
989 }
4b3686fa
FB		 990}
991
992void do_fnmsub (void)
993{
7c58044c
JM		 994 if (unlikely(float64_is_signaling_nan(FT0) ||
995 float64_is_signaling_nan(FT1) ||
996 float64_is_signaling_nan(FT2))) {
997 /* sNaN operation */
998 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
999 } else {
1cdb9c3d 1000#if USE_PRECISE_EMULATION
e864cabd 1001#ifdef FLOAT128
7c58044c
JM		 1002 /* This is the way the PowerPC specification defines it */
1003 float128 ft0_128, ft1_128;
1004
1005 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1006 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1007 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1008 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1009 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1010 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1011#else
7c58044c
JM		 1012 /* This is OK on x86 hosts */
1013 FT0 = (FT0 * FT1) - FT2;
e864cabd
JM		 1014#endif
1015#else
7c58044c
JM		 1016 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1017 FT0 = float64_sub(FT0, FT2, &env->fp_status);
e864cabd 1018#endif
7c58044c
JM		 1019 if (likely(!isnan(FT0)))
1020 FT0 = float64_chs(FT0);
1021 }
1ef59d0a
FB		 1022}
1023
1cdb9c3d 1024#if USE_PRECISE_EMULATION
7c58044c
JM		 1025void do_frsp (void)
1026{
1027 if (unlikely(float64_is_signaling_nan(FT0))) {
1028 /* sNaN square root */
1029 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1030 } else {
1031 FT0 = float64_to_float32(FT0, &env->fp_status);
1032 }
1033}
1cdb9c3d 1034#endif /* USE_PRECISE_EMULATION */
7c58044c 1035
9a64fbe4
FB		 1036void do_fsqrt (void)
1037{
7c58044c
JM		 1038 if (unlikely(float64_is_signaling_nan(FT0))) {
1039 /* sNaN square root */
1040 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1041 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1042 /* Square root of a negative nonzero number */
1043 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1044 } else {
1045 FT0 = float64_sqrt(FT0, &env->fp_status);
1046 }
9a64fbe4
FB		 1047}
1048
d7e4b87e
JM		 1049void do_fre (void)
1050{
0ca9d380 1051 CPU_DoubleU p;
d7e4b87e 1052
7c58044c
JM		 1053 if (unlikely(float64_is_signaling_nan(FT0))) {
1054 /* sNaN reciprocal */
1055 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1056 } else if (unlikely(iszero(FT0))) {
1057 /* Zero reciprocal */
1058 float_zero_divide_excp();
1059 } else if (likely(isnormal(FT0))) {
d7e4b87e
JM		 1060 FT0 = float64_div(1.0, FT0, &env->fp_status);
1061 } else {
1062 p.d = FT0;
0ca9d380
AJ		 1063 if (p.ll == 0x8000000000000000ULL) {
1064 p.ll = 0xFFF0000000000000ULL;
1065 } else if (p.ll == 0x0000000000000000ULL) {
1066 p.ll = 0x7FF0000000000000ULL;
d7e4b87e 1067 } else if (isnan(FT0)) {
0ca9d380 1068 p.ll = 0x7FF8000000000000ULL;
7c58044c 1069 } else if (fpisneg(FT0)) {
0ca9d380 1070 p.ll = 0x8000000000000000ULL;
d7e4b87e 1071 } else {
0ca9d380 1072 p.ll = 0x0000000000000000ULL;
d7e4b87e
JM		 1073 }
1074 FT0 = p.d;
1075 }
1076}
1077
9a64fbe4
FB		 1078void do_fres (void)
1079{
0ca9d380 1080 CPU_DoubleU p;
4ecc3190 1081
7c58044c
JM		 1082 if (unlikely(float64_is_signaling_nan(FT0))) {
1083 /* sNaN reciprocal */
1084 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1085 } else if (unlikely(iszero(FT0))) {
1086 /* Zero reciprocal */
1087 float_zero_divide_excp();
1088 } else if (likely(isnormal(FT0))) {
1cdb9c3d 1089#if USE_PRECISE_EMULATION
e864cabd
JM		 1090 FT0 = float64_div(1.0, FT0, &env->fp_status);
1091 FT0 = float64_to_float32(FT0, &env->fp_status);
1092#else
76a66253 1093 FT0 = float32_div(1.0, FT0, &env->fp_status);
e864cabd 1094#endif
4ecc3190
FB		 1095 } else {
1096 p.d = FT0;
0ca9d380
AJ		 1097 if (p.ll == 0x8000000000000000ULL) {
1098 p.ll = 0xFFF0000000000000ULL;
1099 } else if (p.ll == 0x0000000000000000ULL) {
1100 p.ll = 0x7FF0000000000000ULL;
4ecc3190 1101 } else if (isnan(FT0)) {
0ca9d380 1102 p.ll = 0x7FF8000000000000ULL;
7c58044c 1103 } else if (fpisneg(FT0)) {
0ca9d380 1104 p.ll = 0x8000000000000000ULL;
4ecc3190 1105 } else {
0ca9d380 1106 p.ll = 0x0000000000000000ULL;
4ecc3190
FB		 1107 }
1108 FT0 = p.d;
1109 }
9a64fbe4
FB		 1110}
1111
4ecc3190 1112void do_frsqrte (void)
9a64fbe4 1113{
0ca9d380 1114 CPU_DoubleU p;
4ecc3190 1115
7c58044c
JM		 1116 if (unlikely(float64_is_signaling_nan(FT0))) {
1117 /* sNaN reciprocal square root */
1118 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1119 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1120 /* Reciprocal square root of a negative nonzero number */
1121 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1122 } else if (likely(isnormal(FT0))) {
fdabc366
FB		 1123 FT0 = float64_sqrt(FT0, &env->fp_status);
1124 FT0 = float32_div(1.0, FT0, &env->fp_status);
4ecc3190
FB		 1125 } else {
1126 p.d = FT0;
0ca9d380
AJ		 1127 if (p.ll == 0x8000000000000000ULL) {
1128 p.ll = 0xFFF0000000000000ULL;
1129 } else if (p.ll == 0x0000000000000000ULL) {
1130 p.ll = 0x7FF0000000000000ULL;
4ecc3190 1131 } else if (isnan(FT0)) {
0ca9d380 1132 p.ll |= 0x000FFFFFFFFFFFFFULL;
7c58044c 1133 } else if (fpisneg(FT0)) {
0ca9d380 1134 p.ll = 0x7FF8000000000000ULL;
4ecc3190 1135 } else {
0ca9d380 1136 p.ll = 0x0000000000000000ULL;
4ecc3190
FB		 1137 }
1138 FT0 = p.d;
1139 }
9a64fbe4
FB		 1140}
1141
1142void do_fsel (void)
1143{
7c58044c 1144 if (!fpisneg(FT0) || iszero(FT0))
9a64fbe4 1145 FT0 = FT1;
4ecc3190
FB		 1146 else
1147 FT0 = FT2;
9a64fbe4
FB		 1148}
1149
e1571908 1150uint32_t helper_fcmpu (void)
9a64fbe4 1151{
e1571908
AJ		 1152 uint32_t ret = 0;
1153
7c58044c
JM		 1154 if (unlikely(float64_is_signaling_nan(FT0) ||
1155 float64_is_signaling_nan(FT1))) {
1156 /* sNaN comparison */
1157 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1158 } else {
fdabc366 1159 if (float64_lt(FT0, FT1, &env->fp_status)) {
e1571908 1160 ret = 0x08UL;
fdabc366 1161 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
e1571908 1162 ret = 0x04UL;
fdabc366 1163 } else {
e1571908 1164 ret = 0x02UL;
fdabc366 1165 }
9a64fbe4 1166 }
7c58044c 1167 env->fpscr &= ~(0x0F << FPSCR_FPRF);
e1571908
AJ		 1168 env->fpscr |= ret << FPSCR_FPRF;
1169 return ret;
9a64fbe4
FB		 1170}
1171
e1571908 1172uint32_t helper_fcmpo (void)
9a64fbe4 1173{
e1571908
AJ		 1174 uint32_t ret = 0;
1175
7c58044c
JM		 1176 if (unlikely(float64_is_nan(FT0) ||
1177 float64_is_nan(FT1))) {
1178 if (float64_is_signaling_nan(FT0) ||
1179 float64_is_signaling_nan(FT1)) {
1180 /* sNaN comparison */
1181 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1182 POWERPC_EXCP_FP_VXVC);
1183 } else {
1184 /* qNaN comparison */
1185 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1186 }
1187 } else {
fdabc366 1188 if (float64_lt(FT0, FT1, &env->fp_status)) {
e1571908 1189 ret = 0x08UL;
fdabc366 1190 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
e1571908 1191 ret = 0x04UL;
fdabc366 1192 } else {
e1571908 1193 ret = 0x02UL;
fdabc366 1194 }
9a64fbe4 1195 }
7c58044c 1196 env->fpscr &= ~(0x0F << FPSCR_FPRF);
e1571908
AJ		 1197 env->fpscr |= ret << FPSCR_FPRF;
1198 return ret;
9a64fbe4
FB		 1199}
1200
76a66253 1201#if !defined (CONFIG_USER_ONLY)
6b80055d 1202void cpu_dump_rfi (target_ulong RA, target_ulong msr);
0411a972 1203
6676f424 1204void do_store_msr (void)
0411a972 1205{
6676f424
AJ		 1206 T0 = hreg_store_msr(env, T0, 0);
1207 if (T0 != 0) {
0411a972 1208 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
6676f424 1209 do_raise_exception(T0);
0411a972
JM		 1210 }
1211}
1212
1213static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1214 target_ulong msrm, int keep_msrh)
9a64fbe4 1215{
426613db 1216#if defined(TARGET_PPC64)
0411a972
JM		 1217 if (msr & (1ULL << MSR_SF)) {
1218 nip = (uint64_t)nip;
1219 msr &= (uint64_t)msrm;
a42bd6cc 1220 } else {
0411a972
JM		 1221 nip = (uint32_t)nip;
1222 msr = (uint32_t)(msr & msrm);
1223 if (keep_msrh)
1224 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
a42bd6cc 1225 }
426613db 1226#else
0411a972
JM		 1227 nip = (uint32_t)nip;
1228 msr &= (uint32_t)msrm;
426613db 1229#endif
0411a972
JM		 1230 /* XXX: beware: this is false if VLE is supported */
1231 env->nip = nip & ~((target_ulong)0x00000003);
a4f30719 1232 hreg_store_msr(env, msr, 1);
fdabc366 1233#if defined (DEBUG_OP)
0411a972 1234 cpu_dump_rfi(env->nip, env->msr);
fdabc366 1235#endif
0411a972
JM		 1236 /* No need to raise an exception here,
1237 * as rfi is always the last insn of a TB
1238 */
fdabc366 1239 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
9a64fbe4 1240}
d9bce9d9 1241
0411a972
JM		 1242void do_rfi (void)
1243{
1244 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1245 ~((target_ulong)0xFFFF0000), 1);
1246}
1247
d9bce9d9 1248#if defined(TARGET_PPC64)
426613db
JM		 1249void do_rfid (void)
1250{
0411a972
JM		 1251 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1252 ~((target_ulong)0xFFFF0000), 0);
d9bce9d9 1253}
7863667f 1254
be147d08
JM		 1255void do_hrfid (void)
1256{
0411a972
JM		 1257 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1258 ~((target_ulong)0xFFFF0000), 0);
be147d08
JM		 1259}
1260#endif
76a66253 1261#endif
9a64fbe4 1262
76a66253 1263void do_tw (int flags)
9a64fbe4 1264{
d9bce9d9
JM		 1265 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1266 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1267 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1268 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
a42bd6cc 1269 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
e1833e1f 1270 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
a42bd6cc 1271 }
9a64fbe4
FB		 1272}
1273
d9bce9d9
JM		 1274#if defined(TARGET_PPC64)
1275void do_td (int flags)
1276{
1277 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1278 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1279 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1280 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1281 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
e1833e1f 1282 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
d9bce9d9
JM		 1283}
1284#endif
1285
fdabc366 1286/*****************************************************************************/
76a66253
JM		 1287/* PowerPC 601 specific instructions (POWER bridge) */
1288void do_POWER_abso (void)
9a64fbe4 1289{
9c7e37e7 1290 if ((int32_t)T0 == INT32_MIN) {
76a66253 1291 T0 = INT32_MAX;
3d7b417e 1292 env->xer |= (1 << XER_OV) | (1 << XER_SO);
9c7e37e7 1293 } else if ((int32_t)T0 < 0) {
76a66253 1294 T0 = -T0;
3d7b417e 1295 env->xer &= ~(1 << XER_OV);
9c7e37e7 1296 } else {
3d7b417e 1297 env->xer &= ~(1 << XER_OV);
76a66253 1298 }
9a64fbe4
FB		 1299}
1300
76a66253 1301void do_POWER_clcs (void)
9a64fbe4 1302{
76a66253
JM		 1303 switch (T0) {
1304 case 0x0CUL:
1305 /* Instruction cache line size */
d63001d1 1306 T0 = env->icache_line_size;
76a66253
JM		 1307 break;
1308 case 0x0DUL:
1309 /* Data cache line size */
d63001d1 1310 T0 = env->dcache_line_size;
76a66253
JM		 1311 break;
1312 case 0x0EUL:
1313 /* Minimum cache line size */
d63001d1
JM		 1314 T0 = env->icache_line_size < env->dcache_line_size ?
1315 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1316 break;
1317 case 0x0FUL:
1318 /* Maximum cache line size */
d63001d1
JM		 1319 T0 = env->icache_line_size > env->dcache_line_size ?
1320 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1321 break;
1322 default:
1323 /* Undefined */
1324 break;
1325 }
1326}
1327
1328void do_POWER_div (void)
1329{
1330 uint64_t tmp;
1331
6f2d8978
JM		 1332 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1333 (int32_t)T1 == 0) {
1334 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253
JM		 1335 env->spr[SPR_MQ] = 0;
1336 } else {
1337 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1338 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 1339 T0 = tmp / (int32_t)T1;
76a66253
JM		 1340 }
1341}
1342
1343void do_POWER_divo (void)
1344{
1345 int64_t tmp;
1346
6f2d8978
JM		 1347 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1348 (int32_t)T1 == 0) {
1349 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253 1350 env->spr[SPR_MQ] = 0;
3d7b417e 1351 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253
JM		 1352 } else {
1353 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1354 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 1355 tmp /= (int32_t)T1;
76a66253 1356 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
3d7b417e 1357 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1358 } else {
3d7b417e 1359 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1360 }
1361 T0 = tmp;
1362 }
1363}
1364
1365void do_POWER_divs (void)
1366{
6f2d8978
JM		 1367 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1368 (int32_t)T1 == 0) {
1369 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253
JM		 1370 env->spr[SPR_MQ] = 0;
1371 } else {
1372 env->spr[SPR_MQ] = T0 % T1;
d9bce9d9 1373 T0 = (int32_t)T0 / (int32_t)T1;
76a66253
JM		 1374 }
1375}
1376
1377void do_POWER_divso (void)
1378{
6f2d8978
JM		 1379 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1380 (int32_t)T1 == 0) {
1381 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253 1382 env->spr[SPR_MQ] = 0;
3d7b417e 1383 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1384 } else {
d9bce9d9
JM		 1385 T0 = (int32_t)T0 / (int32_t)T1;
1386 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
3d7b417e 1387 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1388 }
1389}
1390
1391void do_POWER_dozo (void)
1392{
d9bce9d9 1393 if ((int32_t)T1 > (int32_t)T0) {
76a66253
JM		 1394 T2 = T0;
1395 T0 = T1 - T0;
d9bce9d9
JM		 1396 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1397 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
3d7b417e 1398 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1399 } else {
3d7b417e 1400 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1401 }
1402 } else {
1403 T0 = 0;
3d7b417e 1404 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1405 }
1406}
1407
1408void do_POWER_maskg (void)
1409{
1410 uint32_t ret;
1411
d9bce9d9 1412 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
6f2d8978 1413 ret = UINT32_MAX;
76a66253 1414 } else {
6f2d8978
JM		 1415 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1416 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
d9bce9d9 1417 if ((uint32_t)T0 > (uint32_t)T1)
76a66253
JM		 1418 ret = ~ret;
1419 }
1420 T0 = ret;
1421}
1422
1423void do_POWER_mulo (void)
1424{
1425 uint64_t tmp;
1426
1427 tmp = (uint64_t)T0 * (uint64_t)T1;
1428 env->spr[SPR_MQ] = tmp >> 32;
1429 T0 = tmp;
1430 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
3d7b417e 1431 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1432 } else {
3d7b417e 1433 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1434 }
1435}
1436
1437#if !defined (CONFIG_USER_ONLY)
1438void do_POWER_rac (void)
1439{
76a66253 1440 mmu_ctx_t ctx;
faadf50e 1441 int nb_BATs;
76a66253
JM		 1442
1443 /* We don't have to generate many instances of this instruction,
1444 * as rac is supervisor only.
1445 */
faadf50e
JM		 1446 /* XXX: FIX THIS: Pretend we have no BAT */
1447 nb_BATs = env->nb_BATs;
1448 env->nb_BATs = 0;
1449 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
76a66253 1450 T0 = ctx.raddr;
faadf50e 1451 env->nb_BATs = nb_BATs;
76a66253
JM		 1452}
1453
1454void do_POWER_rfsvc (void)
1455{
0411a972 1456 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
76a66253
JM		 1457}
1458
056401ea
JM		 1459void do_store_hid0_601 (void)
1460{
1461 uint32_t hid0;
1462
1463 hid0 = env->spr[SPR_HID0];
1464 if ((T0 ^ hid0) & 0x00000008) {
1465 /* Change current endianness */
1466 env->hflags &= ~(1 << MSR_LE);
1467 env->hflags_nmsr &= ~(1 << MSR_LE);
1468 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1469 env->hflags |= env->hflags_nmsr;
1470 if (loglevel != 0) {
1471 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1472 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1473 }
1474 }
1475 env->spr[SPR_HID0] = T0;
76a66253
JM		 1476}
1477#endif
1478
1479/*****************************************************************************/
1480/* 602 specific instructions */
1481/* mfrom is the most crazy instruction ever seen, imho ! */
1482/* Real implementation uses a ROM table. Do the same */
1483#define USE_MFROM_ROM_TABLE
1484void do_op_602_mfrom (void)
1485{
1486 if (likely(T0 < 602)) {
d9bce9d9 1487#if defined(USE_MFROM_ROM_TABLE)
76a66253
JM		 1488#include "mfrom_table.c"
1489 T0 = mfrom_ROM_table[T0];
fdabc366 1490#else
76a66253
JM		 1491 double d;
1492 /* Extremly decomposed:
1493 * -T0 / 256
1494 * T0 = 256 * log10(10 + 1.0) + 0.5
1495 */
1496 d = T0;
1497 d = float64_div(d, 256, &env->fp_status);
1498 d = float64_chs(d);
1499 d = exp10(d); // XXX: use float emulation function
1500 d = float64_add(d, 1.0, &env->fp_status);
1501 d = log10(d); // XXX: use float emulation function
1502 d = float64_mul(d, 256, &env->fp_status);
1503 d = float64_add(d, 0.5, &env->fp_status);
1504 T0 = float64_round_to_int(d, &env->fp_status);
fdabc366 1505#endif
76a66253
JM		 1506 } else {
1507 T0 = 0;
1508 }
1509}
1510
1511/*****************************************************************************/
1512/* Embedded PowerPC specific helpers */
76a66253
JM		 1513void do_405_check_sat (void)
1514{
d9bce9d9
JM		 1515 if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1516 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
76a66253
JM		 1517 /* Saturate result */
1518 if (T2 >> 31) {
1519 T0 = INT32_MIN;
1520 } else {
1521 T0 = INT32_MAX;
1522 }
1523 }
1524}
1525
a750fc0b
JM		 1526/* XXX: to be improved to check access rights when in user-mode */
1527void do_load_dcr (void)
1528{
1529 target_ulong val;
1530
1531 if (unlikely(env->dcr_env == NULL)) {
1532 if (loglevel != 0) {
1533 fprintf(logfile, "No DCR environment\n");
1534 }
e1833e1f
JM		 1535 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1536 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
a750fc0b
JM		 1537 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1538 if (loglevel != 0) {
1539 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1540 }
e1833e1f
JM		 1541 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1542 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b
JM		 1543 } else {
1544 T0 = val;
1545 }
1546}
1547
1548void do_store_dcr (void)
1549{
1550 if (unlikely(env->dcr_env == NULL)) {
1551 if (loglevel != 0) {
1552 fprintf(logfile, "No DCR environment\n");
1553 }
e1833e1f
JM		 1554 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1555 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
a750fc0b
JM		 1556 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1557 if (loglevel != 0) {
1558 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1559 }
e1833e1f
JM		 1560 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1561 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b
JM		 1562 }
1563}
1564
76a66253 1565#if !defined(CONFIG_USER_ONLY)
a42bd6cc 1566void do_40x_rfci (void)
76a66253 1567{
0411a972
JM		 1568 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1569 ~((target_ulong)0xFFFF0000), 0);
a42bd6cc
JM		 1570}
1571
1572void do_rfci (void)
1573{
0411a972
JM		 1574 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1575 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1576}
1577
1578void do_rfdi (void)
1579{
0411a972
JM		 1580 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1581 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1582}
1583
1584void do_rfmci (void)
1585{
0411a972
JM		 1586 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1587 ~((target_ulong)0x3FFF0000), 0);
76a66253
JM		 1588}
1589
76a66253
JM		 1590void do_load_403_pb (int num)
1591{
1592 T0 = env->pb[num];
1593}
1594
1595void do_store_403_pb (int num)
1596{
1597 if (likely(env->pb[num] != T0)) {
1598 env->pb[num] = T0;
1599 /* Should be optimized */
1600 tlb_flush(env, 1);
1601 }
1602}
1603#endif
1604
1605/* 440 specific */
1606void do_440_dlmzb (void)
1607{
1608 target_ulong mask;
1609 int i;
1610
1611 i = 1;
1612 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1613 if ((T0 & mask) == 0)
1614 goto done;
1615 i++;
1616 }
1617 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1618 if ((T1 & mask) == 0)
1619 break;
1620 i++;
1621 }
1622 done:
1623 T0 = i;
fdabc366
FB		 1624}
1625
0487d6a8
JM		 1626/* SPE extension helpers */
1627/* Use a table to make this quicker */
1628static uint8_t hbrev[16] = {
1629 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1630 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1631};
1632
b068d6a7 1633static always_inline uint8_t byte_reverse (uint8_t val)
0487d6a8
JM		 1634{
1635 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1636}
1637
b068d6a7 1638static always_inline uint32_t word_reverse (uint32_t val)
0487d6a8
JM		 1639{
1640 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1641 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1642}
1643
3cd7d1dd 1644#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
0487d6a8
JM		 1645void do_brinc (void)
1646{
1647 uint32_t a, b, d, mask;
1648
3cd7d1dd
JM		 1649 mask = UINT32_MAX >> (32 - MASKBITS);
1650 a = T0 & mask;
1651 b = T1 & mask;
1652 d = word_reverse(1 + word_reverse(a | ~b));
1653 T0 = (T0 & ~mask) | (d & b);
0487d6a8
JM		 1654}
1655
1656#define DO_SPE_OP2(name) \
1657void do_ev##name (void) \
1658{ \
1659 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1660 (uint64_t)_do_e##name(T0_64, T1_64); \
1661}
1662
1663#define DO_SPE_OP1(name) \
1664void do_ev##name (void) \
1665{ \
1666 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1667 (uint64_t)_do_e##name(T0_64); \
1668}
1669
1670/* Fixed-point vector arithmetic */
b068d6a7 1671static always_inline uint32_t _do_eabs (uint32_t val)
0487d6a8 1672{
9c7e37e7
JM		 1673 if ((val & 0x80000000) && val != 0x80000000)
1674 val -= val;
0487d6a8
JM		 1675
1676 return val;
1677}
1678
b068d6a7 1679static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1680{
1681 return op1 + op2;
1682}
1683
b068d6a7 1684static always_inline int _do_ecntlsw (uint32_t val)
0487d6a8
JM		 1685{
1686 if (val & 0x80000000)
603fccce 1687 return clz32(~val);
0487d6a8 1688 else
603fccce 1689 return clz32(val);
0487d6a8
JM		 1690}
1691
b068d6a7 1692static always_inline int _do_ecntlzw (uint32_t val)
0487d6a8 1693{
603fccce 1694 return clz32(val);
0487d6a8
JM		 1695}
1696
b068d6a7 1697static always_inline uint32_t _do_eneg (uint32_t val)
0487d6a8
JM		 1698{
1699 if (val != 0x80000000)
9c7e37e7 1700 val -= val;
0487d6a8
JM		 1701
1702 return val;
1703}
1704
b068d6a7 1705static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1706{
1707 return rotl32(op1, op2);
1708}
1709
b068d6a7 1710static always_inline uint32_t _do_erndw (uint32_t val)
0487d6a8
JM		 1711{
1712 return (val + 0x000080000000) & 0xFFFF0000;
1713}
1714
b068d6a7 1715static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1716{
1717 /* No error here: 6 bits are used */
1718 return op1 << (op2 & 0x3F);
1719}
1720
b068d6a7 1721static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
0487d6a8
JM		 1722{
1723 /* No error here: 6 bits are used */
1724 return op1 >> (op2 & 0x3F);
1725}
1726
b068d6a7 1727static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1728{
1729 /* No error here: 6 bits are used */
1730 return op1 >> (op2 & 0x3F);
1731}
1732
b068d6a7 1733static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1734{
1735 return op2 - op1;
1736}
1737
1738/* evabs */
1739DO_SPE_OP1(abs);
1740/* evaddw */
1741DO_SPE_OP2(addw);
1742/* evcntlsw */
1743DO_SPE_OP1(cntlsw);
1744/* evcntlzw */
1745DO_SPE_OP1(cntlzw);
1746/* evneg */
1747DO_SPE_OP1(neg);
1748/* evrlw */
1749DO_SPE_OP2(rlw);
1750/* evrnd */
1751DO_SPE_OP1(rndw);
1752/* evslw */
1753DO_SPE_OP2(slw);
1754/* evsrws */
1755DO_SPE_OP2(srws);
1756/* evsrwu */
1757DO_SPE_OP2(srwu);
1758/* evsubfw */
1759DO_SPE_OP2(subfw);
1760
1761/* evsel is a little bit more complicated... */
b068d6a7 1762static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
0487d6a8
JM		 1763{
1764 if (n)
1765 return op1;
1766 else
1767 return op2;
1768}
1769
1770void do_evsel (void)
1771{
1772 T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1773 (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1774}
1775
1776/* Fixed-point vector comparisons */
1777#define DO_SPE_CMP(name) \
1778void do_ev##name (void) \
1779{ \
1780 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1781 T1_64 >> 32) << 32, \
1782 _do_e##name(T0_64, T1_64)); \
1783}
1784
b068d6a7 1785static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
0487d6a8
JM		 1786{
1787 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1788}
b068d6a7 1789static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1790{
1791 return op1 == op2 ? 1 : 0;
1792}
1793
b068d6a7 1794static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
0487d6a8
JM		 1795{
1796 return op1 > op2 ? 1 : 0;
1797}
1798
b068d6a7 1799static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1800{
1801 return op1 > op2 ? 1 : 0;
1802}
1803
b068d6a7 1804static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
0487d6a8
JM		 1805{
1806 return op1 < op2 ? 1 : 0;
1807}
1808
b068d6a7 1809static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1810{
1811 return op1 < op2 ? 1 : 0;
1812}
1813
1814/* evcmpeq */
1815DO_SPE_CMP(cmpeq);
1816/* evcmpgts */
1817DO_SPE_CMP(cmpgts);
1818/* evcmpgtu */
1819DO_SPE_CMP(cmpgtu);
1820/* evcmplts */
1821DO_SPE_CMP(cmplts);
1822/* evcmpltu */
1823DO_SPE_CMP(cmpltu);
1824
1825/* Single precision floating-point conversions from/to integer */
b068d6a7 1826static always_inline uint32_t _do_efscfsi (int32_t val)
0487d6a8 1827{
0ca9d380 1828 CPU_FloatU u;
0487d6a8
JM		 1829
1830 u.f = int32_to_float32(val, &env->spe_status);
1831
0ca9d380 1832 return u.l;
0487d6a8
JM		 1833}
1834
b068d6a7 1835static always_inline uint32_t _do_efscfui (uint32_t val)
0487d6a8 1836{
0ca9d380 1837 CPU_FloatU u;
0487d6a8
JM		 1838
1839 u.f = uint32_to_float32(val, &env->spe_status);
1840
0ca9d380 1841 return u.l;
0487d6a8
JM		 1842}
1843
b068d6a7 1844static always_inline int32_t _do_efsctsi (uint32_t val)
0487d6a8 1845{
0ca9d380 1846 CPU_FloatU u;
0487d6a8 1847
0ca9d380 1848 u.l = val;
0487d6a8
JM		 1849 /* NaN are not treated the same way IEEE 754 does */
1850 if (unlikely(isnan(u.f)))
1851 return 0;
1852
1853 return float32_to_int32(u.f, &env->spe_status);
1854}
1855
b068d6a7 1856static always_inline uint32_t _do_efsctui (uint32_t val)
0487d6a8 1857{
0ca9d380 1858 CPU_FloatU u;
0487d6a8 1859
0ca9d380 1860 u.l = val;
0487d6a8
JM		 1861 /* NaN are not treated the same way IEEE 754 does */
1862 if (unlikely(isnan(u.f)))
1863 return 0;
1864
1865 return float32_to_uint32(u.f, &env->spe_status);
1866}
1867
b068d6a7 1868static always_inline int32_t _do_efsctsiz (uint32_t val)
0487d6a8 1869{
0ca9d380 1870 CPU_FloatU u;
0487d6a8 1871
0ca9d380 1872 u.l = val;
0487d6a8
JM		 1873 /* NaN are not treated the same way IEEE 754 does */
1874 if (unlikely(isnan(u.f)))
1875 return 0;
1876
1877 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1878}
1879
b068d6a7 1880static always_inline uint32_t _do_efsctuiz (uint32_t val)
0487d6a8 1881{
0ca9d380 1882 CPU_FloatU u;
0487d6a8 1883
0ca9d380 1884 u.l = val;
0487d6a8
JM		 1885 /* NaN are not treated the same way IEEE 754 does */
1886 if (unlikely(isnan(u.f)))
1887 return 0;
1888
1889 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1890}
1891
1892void do_efscfsi (void)
1893{
1894 T0_64 = _do_efscfsi(T0_64);
1895}
1896
1897void do_efscfui (void)
1898{
1899 T0_64 = _do_efscfui(T0_64);
1900}
1901
1902void do_efsctsi (void)
1903{
1904 T0_64 = _do_efsctsi(T0_64);
1905}
1906
1907void do_efsctui (void)
1908{
1909 T0_64 = _do_efsctui(T0_64);
1910}
1911
1912void do_efsctsiz (void)
1913{
1914 T0_64 = _do_efsctsiz(T0_64);
1915}
1916
1917void do_efsctuiz (void)
1918{
1919 T0_64 = _do_efsctuiz(T0_64);
1920}
1921
1922/* Single precision floating-point conversion to/from fractional */
b068d6a7 1923static always_inline uint32_t _do_efscfsf (uint32_t val)
0487d6a8 1924{
0ca9d380 1925 CPU_FloatU u;
0487d6a8
JM		 1926 float32 tmp;
1927
1928 u.f = int32_to_float32(val, &env->spe_status);
1929 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1930 u.f = float32_div(u.f, tmp, &env->spe_status);
1931
0ca9d380 1932 return u.l;
0487d6a8
JM		 1933}
1934
b068d6a7 1935static always_inline uint32_t _do_efscfuf (uint32_t val)
0487d6a8 1936{
0ca9d380 1937 CPU_FloatU u;
0487d6a8
JM		 1938 float32 tmp;
1939
1940 u.f = uint32_to_float32(val, &env->spe_status);
1941 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1942 u.f = float32_div(u.f, tmp, &env->spe_status);
1943
0ca9d380 1944 return u.l;
0487d6a8
JM		 1945}
1946
b068d6a7 1947static always_inline int32_t _do_efsctsf (uint32_t val)
0487d6a8 1948{
0ca9d380 1949 CPU_FloatU u;
0487d6a8
JM		 1950 float32 tmp;
1951
0ca9d380 1952 u.l = val;
0487d6a8
JM		 1953 /* NaN are not treated the same way IEEE 754 does */
1954 if (unlikely(isnan(u.f)))
1955 return 0;
1956 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1957 u.f = float32_mul(u.f, tmp, &env->spe_status);
1958
1959 return float32_to_int32(u.f, &env->spe_status);
1960}
1961
b068d6a7 1962static always_inline uint32_t _do_efsctuf (uint32_t val)
0487d6a8 1963{
0ca9d380 1964 CPU_FloatU u;
0487d6a8
JM		 1965 float32 tmp;
1966
0ca9d380 1967 u.l = val;
0487d6a8
JM		 1968 /* NaN are not treated the same way IEEE 754 does */
1969 if (unlikely(isnan(u.f)))
1970 return 0;
1971 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1972 u.f = float32_mul(u.f, tmp, &env->spe_status);
1973
1974 return float32_to_uint32(u.f, &env->spe_status);
1975}
1976
b068d6a7 1977static always_inline int32_t _do_efsctsfz (uint32_t val)
0487d6a8 1978{
0ca9d380 1979 CPU_FloatU u;
0487d6a8
JM		 1980 float32 tmp;
1981
0ca9d380 1982 u.l = val;
0487d6a8
JM		 1983 /* NaN are not treated the same way IEEE 754 does */
1984 if (unlikely(isnan(u.f)))
1985 return 0;
1986 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1987 u.f = float32_mul(u.f, tmp, &env->spe_status);
1988
1989 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1990}
1991
b068d6a7 1992static always_inline uint32_t _do_efsctufz (uint32_t val)
0487d6a8 1993{
0ca9d380 1994 CPU_FloatU u;
0487d6a8
JM		 1995 float32 tmp;
1996
0ca9d380 1997 u.l = val;
0487d6a8
JM		 1998 /* NaN are not treated the same way IEEE 754 does */
1999 if (unlikely(isnan(u.f)))
2000 return 0;
2001 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2002 u.f = float32_mul(u.f, tmp, &env->spe_status);
2003
2004 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2005}
2006
2007void do_efscfsf (void)
2008{
2009 T0_64 = _do_efscfsf(T0_64);
2010}
2011
2012void do_efscfuf (void)
2013{
2014 T0_64 = _do_efscfuf(T0_64);
2015}
2016
2017void do_efsctsf (void)
2018{
2019 T0_64 = _do_efsctsf(T0_64);
2020}
2021
2022void do_efsctuf (void)
2023{
2024 T0_64 = _do_efsctuf(T0_64);
2025}
2026
2027void do_efsctsfz (void)
2028{
2029 T0_64 = _do_efsctsfz(T0_64);
2030}
2031
2032void do_efsctufz (void)
2033{
2034 T0_64 = _do_efsctufz(T0_64);
2035}
2036
2037/* Double precision floating point helpers */
b068d6a7 2038static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
0487d6a8
JM		 2039{
2040 /* XXX: TODO: test special values (NaN, infinites, ...) */
2041 return _do_efdtstlt(op1, op2);
2042}
2043
b068d6a7 2044static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
0487d6a8
JM		 2045{
2046 /* XXX: TODO: test special values (NaN, infinites, ...) */
2047 return _do_efdtstgt(op1, op2);
2048}
2049
b068d6a7 2050static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
0487d6a8
JM		 2051{
2052 /* XXX: TODO: test special values (NaN, infinites, ...) */
2053 return _do_efdtsteq(op1, op2);
2054}
2055
2056void do_efdcmplt (void)
2057{
2058 T0 = _do_efdcmplt(T0_64, T1_64);
2059}
2060
2061void do_efdcmpgt (void)
2062{
2063 T0 = _do_efdcmpgt(T0_64, T1_64);
2064}
2065
2066void do_efdcmpeq (void)
2067{
2068 T0 = _do_efdcmpeq(T0_64, T1_64);
2069}
2070
2071/* Double precision floating-point conversion to/from integer */
b068d6a7 2072static always_inline uint64_t _do_efdcfsi (int64_t val)
0487d6a8 2073{
0ca9d380 2074 CPU_DoubleU u;
0487d6a8 2075
0ca9d380 2076 u.d = int64_to_float64(val, &env->spe_status);
0487d6a8 2077
0ca9d380 2078 return u.ll;
0487d6a8
JM		 2079}
2080
b068d6a7 2081static always_inline uint64_t _do_efdcfui (uint64_t val)
0487d6a8 2082{
0ca9d380 2083 CPU_DoubleU u;
0487d6a8 2084
0ca9d380 2085 u.d = uint64_to_float64(val, &env->spe_status);
0487d6a8 2086
0ca9d380 2087 return u.ll;
0487d6a8
JM		 2088}
2089
b068d6a7 2090static always_inline int64_t _do_efdctsi (uint64_t val)
0487d6a8 2091{
0ca9d380 2092 CPU_DoubleU u;
0487d6a8 2093
0ca9d380 2094 u.ll = val;
0487d6a8 2095 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2096 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2097 return 0;
2098
0ca9d380 2099 return float64_to_int64(u.d, &env->spe_status);
0487d6a8
JM		 2100}
2101
b068d6a7 2102static always_inline uint64_t _do_efdctui (uint64_t val)
0487d6a8 2103{
0ca9d380 2104 CPU_DoubleU u;
0487d6a8 2105
0ca9d380 2106 u.ll = val;
0487d6a8 2107 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2108 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2109 return 0;
2110
0ca9d380 2111 return float64_to_uint64(u.d, &env->spe_status);
0487d6a8
JM		 2112}
2113
b068d6a7 2114static always_inline int64_t _do_efdctsiz (uint64_t val)
0487d6a8 2115{
0ca9d380 2116 CPU_DoubleU u;
0487d6a8 2117
0ca9d380 2118 u.ll = val;
0487d6a8 2119 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2120 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2121 return 0;
2122
0ca9d380 2123 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2124}
2125
b068d6a7 2126static always_inline uint64_t _do_efdctuiz (uint64_t val)
0487d6a8 2127{
0ca9d380 2128 CPU_DoubleU u;
0487d6a8 2129
0ca9d380 2130 u.ll = val;
0487d6a8 2131 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2132 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2133 return 0;
2134
0ca9d380 2135 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2136}
2137
2138void do_efdcfsi (void)
2139{
2140 T0_64 = _do_efdcfsi(T0_64);
2141}
2142
2143void do_efdcfui (void)
2144{
2145 T0_64 = _do_efdcfui(T0_64);
2146}
2147
2148void do_efdctsi (void)
2149{
2150 T0_64 = _do_efdctsi(T0_64);
2151}
2152
2153void do_efdctui (void)
2154{
2155 T0_64 = _do_efdctui(T0_64);
2156}
2157
2158void do_efdctsiz (void)
2159{
2160 T0_64 = _do_efdctsiz(T0_64);
2161}
2162
2163void do_efdctuiz (void)
2164{
2165 T0_64 = _do_efdctuiz(T0_64);
2166}
2167
2168/* Double precision floating-point conversion to/from fractional */
b068d6a7 2169static always_inline uint64_t _do_efdcfsf (int64_t val)
0487d6a8 2170{
0ca9d380 2171 CPU_DoubleU u;
0487d6a8
JM		 2172 float64 tmp;
2173
0ca9d380 2174 u.d = int32_to_float64(val, &env->spe_status);
0487d6a8 2175 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2176 u.d = float64_div(u.d, tmp, &env->spe_status);
0487d6a8 2177
0ca9d380 2178 return u.ll;
0487d6a8
JM		 2179}
2180
b068d6a7 2181static always_inline uint64_t _do_efdcfuf (uint64_t val)
0487d6a8 2182{
0ca9d380 2183 CPU_DoubleU u;
0487d6a8
JM		 2184 float64 tmp;
2185
0ca9d380 2186 u.d = uint32_to_float64(val, &env->spe_status);
0487d6a8 2187 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2188 u.d = float64_div(u.d, tmp, &env->spe_status);
0487d6a8 2189
0ca9d380 2190 return u.ll;
0487d6a8
JM		 2191}
2192
b068d6a7 2193static always_inline int64_t _do_efdctsf (uint64_t val)
0487d6a8 2194{
0ca9d380 2195 CPU_DoubleU u;
0487d6a8
JM		 2196 float64 tmp;
2197
0ca9d380 2198 u.ll = val;
0487d6a8 2199 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2200 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2201 return 0;
2202 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2203 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2204
0ca9d380 2205 return float64_to_int32(u.d, &env->spe_status);
0487d6a8
JM		 2206}
2207
b068d6a7 2208static always_inline uint64_t _do_efdctuf (uint64_t val)
0487d6a8 2209{
0ca9d380 2210 CPU_DoubleU u;
0487d6a8
JM		 2211 float64 tmp;
2212
0ca9d380 2213 u.ll = val;
0487d6a8 2214 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2215 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2216 return 0;
2217 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2218 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2219
0ca9d380 2220 return float64_to_uint32(u.d, &env->spe_status);
0487d6a8
JM		 2221}
2222
b068d6a7 2223static always_inline int64_t _do_efdctsfz (uint64_t val)
0487d6a8 2224{
0ca9d380 2225 CPU_DoubleU u;
0487d6a8
JM		 2226 float64 tmp;
2227
0ca9d380 2228 u.ll = val;
0487d6a8 2229 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2230 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2231 return 0;
2232 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2233 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2234
0ca9d380 2235 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2236}
2237
b068d6a7 2238static always_inline uint64_t _do_efdctufz (uint64_t val)
0487d6a8 2239{
0ca9d380 2240 CPU_DoubleU u;
0487d6a8
JM		 2241 float64 tmp;
2242
0ca9d380 2243 u.ll = val;
0487d6a8 2244 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2245 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2246 return 0;
2247 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2248 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2249
0ca9d380 2250 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2251}
2252
2253void do_efdcfsf (void)
2254{
2255 T0_64 = _do_efdcfsf(T0_64);
2256}
2257
2258void do_efdcfuf (void)
2259{
2260 T0_64 = _do_efdcfuf(T0_64);
2261}
2262
2263void do_efdctsf (void)
2264{
2265 T0_64 = _do_efdctsf(T0_64);
2266}
2267
2268void do_efdctuf (void)
2269{
2270 T0_64 = _do_efdctuf(T0_64);
2271}
2272
2273void do_efdctsfz (void)
2274{
2275 T0_64 = _do_efdctsfz(T0_64);
2276}
2277
2278void do_efdctufz (void)
2279{
2280 T0_64 = _do_efdctufz(T0_64);
2281}
2282
2283/* Floating point conversion between single and double precision */
b068d6a7 2284static always_inline uint32_t _do_efscfd (uint64_t val)
0487d6a8 2285{
0ca9d380
AJ		 2286 CPU_DoubleU u1;
2287 CPU_FloatU u2;
0487d6a8 2288
0ca9d380
AJ		 2289 u1.ll = val;
2290 u2.f = float64_to_float32(u1.d, &env->spe_status);
0487d6a8 2291
0ca9d380 2292 return u2.l;
0487d6a8
JM		 2293}
2294
b068d6a7 2295static always_inline uint64_t _do_efdcfs (uint32_t val)
0487d6a8 2296{
0ca9d380
AJ		 2297 CPU_DoubleU u2;
2298 CPU_FloatU u1;
0487d6a8 2299
0ca9d380
AJ		 2300 u1.l = val;
2301 u2.d = float32_to_float64(u1.f, &env->spe_status);
0487d6a8 2302
0ca9d380 2303 return u2.ll;
0487d6a8
JM		 2304}
2305
2306void do_efscfd (void)
2307{
2308 T0_64 = _do_efscfd(T0_64);
2309}
2310
2311void do_efdcfs (void)
2312{
2313 T0_64 = _do_efdcfs(T0_64);
2314}
2315
2316/* Single precision fixed-point vector arithmetic */
2317/* evfsabs */
2318DO_SPE_OP1(fsabs);
2319/* evfsnabs */
2320DO_SPE_OP1(fsnabs);
2321/* evfsneg */
2322DO_SPE_OP1(fsneg);
2323/* evfsadd */
2324DO_SPE_OP2(fsadd);
2325/* evfssub */
2326DO_SPE_OP2(fssub);
2327/* evfsmul */
2328DO_SPE_OP2(fsmul);
2329/* evfsdiv */
2330DO_SPE_OP2(fsdiv);
2331
2332/* Single-precision floating-point comparisons */
b068d6a7 2333static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2334{
2335 /* XXX: TODO: test special values (NaN, infinites, ...) */
2336 return _do_efststlt(op1, op2);
2337}
2338
b068d6a7 2339static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2340{
2341 /* XXX: TODO: test special values (NaN, infinites, ...) */
2342 return _do_efststgt(op1, op2);
2343}
2344
b068d6a7 2345static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2346{
2347 /* XXX: TODO: test special values (NaN, infinites, ...) */
2348 return _do_efststeq(op1, op2);
2349}
2350
2351void do_efscmplt (void)
2352{
2353 T0 = _do_efscmplt(T0_64, T1_64);
2354}
2355
2356void do_efscmpgt (void)
2357{
2358 T0 = _do_efscmpgt(T0_64, T1_64);
2359}
2360
2361void do_efscmpeq (void)
2362{
2363 T0 = _do_efscmpeq(T0_64, T1_64);
2364}
2365
2366/* Single-precision floating-point vector comparisons */
2367/* evfscmplt */
2368DO_SPE_CMP(fscmplt);
2369/* evfscmpgt */
2370DO_SPE_CMP(fscmpgt);
2371/* evfscmpeq */
2372DO_SPE_CMP(fscmpeq);
2373/* evfststlt */
2374DO_SPE_CMP(fststlt);
2375/* evfststgt */
2376DO_SPE_CMP(fststgt);
2377/* evfststeq */
2378DO_SPE_CMP(fststeq);
2379
2380/* Single-precision floating-point vector conversions */
2381/* evfscfsi */
2382DO_SPE_OP1(fscfsi);
2383/* evfscfui */
2384DO_SPE_OP1(fscfui);
2385/* evfscfuf */
2386DO_SPE_OP1(fscfuf);
2387/* evfscfsf */
2388DO_SPE_OP1(fscfsf);
2389/* evfsctsi */
2390DO_SPE_OP1(fsctsi);
2391/* evfsctui */
2392DO_SPE_OP1(fsctui);
2393/* evfsctsiz */
2394DO_SPE_OP1(fsctsiz);
2395/* evfsctuiz */
2396DO_SPE_OP1(fsctuiz);
2397/* evfsctsf */
2398DO_SPE_OP1(fsctsf);
2399/* evfsctuf */
2400DO_SPE_OP1(fsctuf);
0487d6a8 2401
fdabc366
FB		 2402/*****************************************************************************/
2403/* Softmmu support */
2404#if !defined (CONFIG_USER_ONLY)
2405
2406#define MMUSUFFIX _mmu
fdabc366
FB		 2407
2408#define SHIFT 0
2409#include "softmmu_template.h"
2410
2411#define SHIFT 1
2412#include "softmmu_template.h"
2413
2414#define SHIFT 2
2415#include "softmmu_template.h"
2416
2417#define SHIFT 3
2418#include "softmmu_template.h"
2419
2420/* try to fill the TLB and return an exception if error. If retaddr is
2421 NULL, it means that the function was called in C code (i.e. not
2422 from generated code or from helper.c) */
2423/* XXX: fix it to restore all registers */
6ebbf390 2424void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
fdabc366
FB		 2425{
2426 TranslationBlock *tb;
2427 CPUState *saved_env;
44f8625d 2428 unsigned long pc;
fdabc366
FB		 2429 int ret;
2430
2431 /* XXX: hack to restore env in all cases, even if not called from
2432 generated code */
2433 saved_env = env;
2434 env = cpu_single_env;
6ebbf390 2435 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
76a66253 2436 if (unlikely(ret != 0)) {
fdabc366
FB		 2437 if (likely(retaddr)) {
2438 /* now we have a real cpu fault */
44f8625d 2439 pc = (unsigned long)retaddr;
fdabc366
FB		 2440 tb = tb_find_pc(pc);
2441 if (likely(tb)) {
2442 /* the PC is inside the translated code. It means that we have
2443 a virtual CPU fault */
2444 cpu_restore_state(tb, env, pc, NULL);
76a66253 2445 }
fdabc366
FB		 2446 }
2447 do_raise_exception_err(env->exception_index, env->error_code);
2448 }
2449 env = saved_env;
9a64fbe4
FB		 2450}
2451
76a66253
JM		 2452/* Software driven TLBs management */
2453/* PowerPC 602/603 software TLB load instructions helpers */
2454void do_load_6xx_tlb (int is_code)
2455{
2456 target_ulong RPN, CMP, EPN;
2457 int way;
d9bce9d9 2458
76a66253
JM		 2459 RPN = env->spr[SPR_RPA];
2460 if (is_code) {
2461 CMP = env->spr[SPR_ICMP];
2462 EPN = env->spr[SPR_IMISS];
2463 } else {
2464 CMP = env->spr[SPR_DCMP];
2465 EPN = env->spr[SPR_DMISS];
2466 }
2467 way = (env->spr[SPR_SRR1] >> 17) & 1;
2468#if defined (DEBUG_SOFTWARE_TLB)
2469 if (loglevel != 0) {
6b542af7
JM		 2470 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2471 " PTE1 " ADDRX " way %d\n",
2472 __func__, T0, EPN, CMP, RPN, way);
76a66253
JM		 2473 }
2474#endif
2475 /* Store this TLB */
d9bce9d9
JM		 2476 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2477 way, is_code, CMP, RPN);
76a66253
JM		 2478}
2479
7dbe11ac
JM		 2480void do_load_74xx_tlb (int is_code)
2481{
2482 target_ulong RPN, CMP, EPN;
2483 int way;
2484
2485 RPN = env->spr[SPR_PTELO];
2486 CMP = env->spr[SPR_PTEHI];
2487 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2488 way = env->spr[SPR_TLBMISS] & 0x3;
2489#if defined (DEBUG_SOFTWARE_TLB)
2490 if (loglevel != 0) {
6b542af7
JM		 2491 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2492 " PTE1 " ADDRX " way %d\n",
2493 __func__, T0, EPN, CMP, RPN, way);
7dbe11ac
JM		 2494 }
2495#endif
2496 /* Store this TLB */
2497 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2498 way, is_code, CMP, RPN);
2499}
2500
a11b8151 2501static always_inline target_ulong booke_tlb_to_page_size (int size)
a8dea12f
JM		 2502{
2503 return 1024 << (2 * size);
2504}
2505
a11b8151 2506static always_inline int booke_page_size_to_tlb (target_ulong page_size)
a8dea12f
JM		 2507{
2508 int size;
2509
2510 switch (page_size) {
2511 case 0x00000400UL:
2512 size = 0x0;
2513 break;
2514 case 0x00001000UL:
2515 size = 0x1;
2516 break;
2517 case 0x00004000UL:
2518 size = 0x2;
2519 break;
2520 case 0x00010000UL:
2521 size = 0x3;
2522 break;
2523 case 0x00040000UL:
2524 size = 0x4;
2525 break;
2526 case 0x00100000UL:
2527 size = 0x5;
2528 break;
2529 case 0x00400000UL:
2530 size = 0x6;
2531 break;
2532 case 0x01000000UL:
2533 size = 0x7;
2534 break;
2535 case 0x04000000UL:
2536 size = 0x8;
2537 break;
2538 case 0x10000000UL:
2539 size = 0x9;
2540 break;
2541 case 0x40000000UL:
2542 size = 0xA;
2543 break;
2544#if defined (TARGET_PPC64)
2545 case 0x000100000000ULL:
2546 size = 0xB;
2547 break;
2548 case 0x000400000000ULL:
2549 size = 0xC;
2550 break;
2551 case 0x001000000000ULL:
2552 size = 0xD;
2553 break;
2554 case 0x004000000000ULL:
2555 size = 0xE;
2556 break;
2557 case 0x010000000000ULL:
2558 size = 0xF;
2559 break;
2560#endif
2561 default:
2562 size = -1;
2563 break;
2564 }
2565
2566 return size;
2567}
2568
76a66253 2569/* Helpers for 4xx TLB management */
76a66253
JM		 2570void do_4xx_tlbre_lo (void)
2571{
a8dea12f
JM		 2572 ppcemb_tlb_t *tlb;
2573 int size;
76a66253
JM		 2574
2575 T0 &= 0x3F;
a8dea12f
JM		 2576 tlb = &env->tlb[T0].tlbe;
2577 T0 = tlb->EPN;
2578 if (tlb->prot & PAGE_VALID)
2579 T0 |= 0x400;
2580 size = booke_page_size_to_tlb(tlb->size);
2581 if (size < 0 || size > 0x7)
2582 size = 1;
2583 T0 |= size << 7;
2584 env->spr[SPR_40x_PID] = tlb->PID;
76a66253
JM		 2585}
2586
2587void do_4xx_tlbre_hi (void)
2588{
a8dea12f 2589 ppcemb_tlb_t *tlb;
76a66253
JM		 2590
2591 T0 &= 0x3F;
a8dea12f
JM		 2592 tlb = &env->tlb[T0].tlbe;
2593 T0 = tlb->RPN;
2594 if (tlb->prot & PAGE_EXEC)
2595 T0 |= 0x200;
2596 if (tlb->prot & PAGE_WRITE)
2597 T0 |= 0x100;
76a66253
JM		 2598}
2599
c55e9aef 2600void do_4xx_tlbwe_hi (void)
76a66253 2601{
a8dea12f 2602 ppcemb_tlb_t *tlb;
76a66253
JM		 2603 target_ulong page, end;
2604
c55e9aef 2605#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2606 if (loglevel != 0) {
6b542af7 2607 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
c55e9aef
JM		 2608 }
2609#endif
76a66253 2610 T0 &= 0x3F;
a8dea12f 2611 tlb = &env->tlb[T0].tlbe;
76a66253
JM		 2612 /* Invalidate previous TLB (if it's valid) */
2613 if (tlb->prot & PAGE_VALID) {
2614 end = tlb->EPN + tlb->size;
c55e9aef 2615#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2616 if (loglevel != 0) {
c55e9aef
JM		 2617 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2618 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2619 }
2620#endif
76a66253
JM		 2621 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2622 tlb_flush_page(env, page);
2623 }
a8dea12f 2624 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
c294fc58
JM		 2625 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2626 * If this ever occurs, one should use the ppcemb target instead
2627 * of the ppc or ppc64 one
2628 */
2629 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
71c8b8fd
JM		 2630 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2631 "are not supported (%d)\n",
c294fc58
JM		 2632 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2633 }
a750fc0b 2634 tlb->EPN = T1 & ~(tlb->size - 1);
c55e9aef 2635 if (T1 & 0x40)
76a66253
JM		 2636 tlb->prot |= PAGE_VALID;
2637 else
2638 tlb->prot &= ~PAGE_VALID;
c294fc58
JM		 2639 if (T1 & 0x20) {
2640 /* XXX: TO BE FIXED */
2641 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2642 }
c55e9aef 2643 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
a8dea12f 2644 tlb->attr = T1 & 0xFF;
c55e9aef 2645#if defined (DEBUG_SOFTWARE_TLB)
c294fc58
JM		 2646 if (loglevel != 0) {
2647 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 2648 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
5fafdf24 2649 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 2650 tlb->prot & PAGE_READ ? 'r' : '-',
2651 tlb->prot & PAGE_WRITE ? 'w' : '-',
2652 tlb->prot & PAGE_EXEC ? 'x' : '-',
2653 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2654 }
2655#endif
76a66253
JM		 2656 /* Invalidate new TLB (if valid) */
2657 if (tlb->prot & PAGE_VALID) {
2658 end = tlb->EPN + tlb->size;
c55e9aef 2659#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2660 if (loglevel != 0) {
c55e9aef
JM		 2661 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2662 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2663 }
2664#endif
76a66253
JM		 2665 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2666 tlb_flush_page(env, page);
2667 }
76a66253
JM		 2668}
2669
c55e9aef 2670void do_4xx_tlbwe_lo (void)
76a66253 2671{
a8dea12f 2672 ppcemb_tlb_t *tlb;
76a66253 2673
c55e9aef 2674#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2675 if (loglevel != 0) {
6b542af7 2676 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
c55e9aef
JM		 2677 }
2678#endif
76a66253 2679 T0 &= 0x3F;
a8dea12f 2680 tlb = &env->tlb[T0].tlbe;
76a66253
JM		 2681 tlb->RPN = T1 & 0xFFFFFC00;
2682 tlb->prot = PAGE_READ;
2683 if (T1 & 0x200)
2684 tlb->prot |= PAGE_EXEC;
2685 if (T1 & 0x100)
2686 tlb->prot |= PAGE_WRITE;
c55e9aef 2687#if defined (DEBUG_SOFTWARE_TLB)
6b80055d
JM		 2688 if (loglevel != 0) {
2689 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 2690 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
5fafdf24 2691 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 2692 tlb->prot & PAGE_READ ? 'r' : '-',
2693 tlb->prot & PAGE_WRITE ? 'w' : '-',
2694 tlb->prot & PAGE_EXEC ? 'x' : '-',
2695 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2696 }
2697#endif
76a66253 2698}
5eb7995e 2699
a4bb6c3e
JM		 2700/* PowerPC 440 TLB management */
2701void do_440_tlbwe (int word)
5eb7995e
JM		 2702{
2703 ppcemb_tlb_t *tlb;
a4bb6c3e 2704 target_ulong EPN, RPN, size;
5eb7995e
JM		 2705 int do_flush_tlbs;
2706
2707#if defined (DEBUG_SOFTWARE_TLB)
2708 if (loglevel != 0) {
6b542af7 2709 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
69facb78 2710 __func__, word, T0, T1);
5eb7995e
JM		 2711 }
2712#endif
2713 do_flush_tlbs = 0;
2714 T0 &= 0x3F;
2715 tlb = &env->tlb[T0].tlbe;
a4bb6c3e
JM		 2716 switch (word) {
2717 default:
2718 /* Just here to please gcc */
2719 case 0:
2720 EPN = T1 & 0xFFFFFC00;
2721 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
5eb7995e 2722 do_flush_tlbs = 1;
a4bb6c3e
JM		 2723 tlb->EPN = EPN;
2724 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2725 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2726 do_flush_tlbs = 1;
2727 tlb->size = size;
2728 tlb->attr &= ~0x1;
2729 tlb->attr |= (T1 >> 8) & 1;
2730 if (T1 & 0x200) {
2731 tlb->prot |= PAGE_VALID;
2732 } else {
2733 if (tlb->prot & PAGE_VALID) {
2734 tlb->prot &= ~PAGE_VALID;
2735 do_flush_tlbs = 1;
2736 }
5eb7995e 2737 }
a4bb6c3e
JM		 2738 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2739 if (do_flush_tlbs)
2740 tlb_flush(env, 1);
2741 break;
2742 case 1:
2743 RPN = T1 & 0xFFFFFC0F;
2744 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2745 tlb_flush(env, 1);
2746 tlb->RPN = RPN;
2747 break;
2748 case 2:
2749 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2750 tlb->prot = tlb->prot & PAGE_VALID;
2751 if (T1 & 0x1)
2752 tlb->prot |= PAGE_READ << 4;
2753 if (T1 & 0x2)
2754 tlb->prot |= PAGE_WRITE << 4;
2755 if (T1 & 0x4)
2756 tlb->prot |= PAGE_EXEC << 4;
2757 if (T1 & 0x8)
2758 tlb->prot |= PAGE_READ;
2759 if (T1 & 0x10)
2760 tlb->prot |= PAGE_WRITE;
2761 if (T1 & 0x20)
2762 tlb->prot |= PAGE_EXEC;
2763 break;
5eb7995e 2764 }
5eb7995e
JM		 2765}
2766
a4bb6c3e 2767void do_440_tlbre (int word)
5eb7995e
JM		 2768{
2769 ppcemb_tlb_t *tlb;
2770 int size;
2771
2772 T0 &= 0x3F;
2773 tlb = &env->tlb[T0].tlbe;
a4bb6c3e
JM		 2774 switch (word) {
2775 default:
2776 /* Just here to please gcc */
2777 case 0:
2778 T0 = tlb->EPN;
2779 size = booke_page_size_to_tlb(tlb->size);
2780 if (size < 0 || size > 0xF)
2781 size = 1;
2782 T0 |= size << 4;
2783 if (tlb->attr & 0x1)
2784 T0 |= 0x100;
2785 if (tlb->prot & PAGE_VALID)
2786 T0 |= 0x200;
2787 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2788 env->spr[SPR_440_MMUCR] |= tlb->PID;
2789 break;
2790 case 1:
2791 T0 = tlb->RPN;
2792 break;
2793 case 2:
2794 T0 = tlb->attr & ~0x1;
2795 if (tlb->prot & (PAGE_READ << 4))
2796 T0 |= 0x1;
2797 if (tlb->prot & (PAGE_WRITE << 4))
2798 T0 |= 0x2;
2799 if (tlb->prot & (PAGE_EXEC << 4))
2800 T0 |= 0x4;
2801 if (tlb->prot & PAGE_READ)
2802 T0 |= 0x8;
2803 if (tlb->prot & PAGE_WRITE)
2804 T0 |= 0x10;
2805 if (tlb->prot & PAGE_EXEC)
2806 T0 |= 0x20;
2807 break;
2808 }
5eb7995e 2809}
76a66253 2810#endif /* !CONFIG_USER_ONLY */
Qemu copy for testing