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Commit | Line | Data |
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9a64fbe4 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation helpers for qemu. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
9a64fbe4 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
9a64fbe4 | 20 | #include "exec.h" |
603fccce | 21 | #include "host-utils.h" |
a7812ae4 | 22 | #include "helper.h" |
9a64fbe4 | 23 | |
0411a972 | 24 | #include "helper_regs.h" |
0487d6a8 | 25 | |
fdabc366 FB |
26 | //#define DEBUG_OP |
27 | //#define DEBUG_EXCEPTIONS | |
76a66253 | 28 | //#define DEBUG_SOFTWARE_TLB |
fdabc366 | 29 | |
9a64fbe4 FB |
30 | /*****************************************************************************/ |
31 | /* Exceptions processing helpers */ | |
9a64fbe4 | 32 | |
64adab3f | 33 | void helper_raise_exception_err (uint32_t exception, uint32_t error_code) |
9a64fbe4 | 34 | { |
e06fcd75 AJ |
35 | #if 0 |
36 | printf("Raise exception %3x code : %d\n", exception, error_code); | |
37 | #endif | |
38 | env->exception_index = exception; | |
39 | env->error_code = error_code; | |
40 | cpu_loop_exit(); | |
76a66253 | 41 | } |
9fddaa0c | 42 | |
e06fcd75 | 43 | void helper_raise_exception (uint32_t exception) |
9fddaa0c | 44 | { |
e06fcd75 | 45 | helper_raise_exception_err(exception, 0); |
9a64fbe4 FB |
46 | } |
47 | ||
76a66253 JM |
48 | /*****************************************************************************/ |
49 | /* Registers load and stores */ | |
a7812ae4 | 50 | target_ulong helper_load_cr (void) |
76a66253 | 51 | { |
e1571908 AJ |
52 | return (env->crf[0] << 28) | |
53 | (env->crf[1] << 24) | | |
54 | (env->crf[2] << 20) | | |
55 | (env->crf[3] << 16) | | |
56 | (env->crf[4] << 12) | | |
57 | (env->crf[5] << 8) | | |
58 | (env->crf[6] << 4) | | |
59 | (env->crf[7] << 0); | |
76a66253 JM |
60 | } |
61 | ||
e1571908 | 62 | void helper_store_cr (target_ulong val, uint32_t mask) |
76a66253 JM |
63 | { |
64 | int i, sh; | |
65 | ||
36081602 | 66 | for (i = 0, sh = 7; i < 8; i++, sh--) { |
76a66253 | 67 | if (mask & (1 << sh)) |
e1571908 | 68 | env->crf[i] = (val >> (sh * 4)) & 0xFUL; |
76a66253 JM |
69 | } |
70 | } | |
71 | ||
45d827d2 AJ |
72 | /*****************************************************************************/ |
73 | /* SPR accesses */ | |
74 | void helper_load_dump_spr (uint32_t sprn) | |
a496775f | 75 | { |
6b80055d | 76 | if (loglevel != 0) { |
a496775f JM |
77 | fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n", |
78 | sprn, sprn, env->spr[sprn]); | |
79 | } | |
a496775f JM |
80 | } |
81 | ||
45d827d2 | 82 | void helper_store_dump_spr (uint32_t sprn) |
a496775f | 83 | { |
6b80055d | 84 | if (loglevel != 0) { |
45d827d2 AJ |
85 | fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n", |
86 | sprn, sprn, env->spr[sprn]); | |
87 | } | |
88 | } | |
89 | ||
90 | target_ulong helper_load_tbl (void) | |
91 | { | |
92 | return cpu_ppc_load_tbl(env); | |
93 | } | |
94 | ||
95 | target_ulong helper_load_tbu (void) | |
96 | { | |
97 | return cpu_ppc_load_tbu(env); | |
98 | } | |
99 | ||
100 | target_ulong helper_load_atbl (void) | |
101 | { | |
102 | return cpu_ppc_load_atbl(env); | |
103 | } | |
104 | ||
105 | target_ulong helper_load_atbu (void) | |
106 | { | |
107 | return cpu_ppc_load_atbu(env); | |
108 | } | |
109 | ||
110 | target_ulong helper_load_601_rtcl (void) | |
111 | { | |
112 | return cpu_ppc601_load_rtcl(env); | |
113 | } | |
114 | ||
115 | target_ulong helper_load_601_rtcu (void) | |
116 | { | |
117 | return cpu_ppc601_load_rtcu(env); | |
118 | } | |
119 | ||
120 | #if !defined(CONFIG_USER_ONLY) | |
121 | #if defined (TARGET_PPC64) | |
122 | void helper_store_asr (target_ulong val) | |
123 | { | |
124 | ppc_store_asr(env, val); | |
125 | } | |
126 | #endif | |
127 | ||
128 | void helper_store_sdr1 (target_ulong val) | |
129 | { | |
130 | ppc_store_sdr1(env, val); | |
131 | } | |
132 | ||
133 | void helper_store_tbl (target_ulong val) | |
134 | { | |
135 | cpu_ppc_store_tbl(env, val); | |
136 | } | |
137 | ||
138 | void helper_store_tbu (target_ulong val) | |
139 | { | |
140 | cpu_ppc_store_tbu(env, val); | |
141 | } | |
142 | ||
143 | void helper_store_atbl (target_ulong val) | |
144 | { | |
145 | cpu_ppc_store_atbl(env, val); | |
146 | } | |
147 | ||
148 | void helper_store_atbu (target_ulong val) | |
149 | { | |
150 | cpu_ppc_store_atbu(env, val); | |
151 | } | |
152 | ||
153 | void helper_store_601_rtcl (target_ulong val) | |
154 | { | |
155 | cpu_ppc601_store_rtcl(env, val); | |
156 | } | |
157 | ||
158 | void helper_store_601_rtcu (target_ulong val) | |
159 | { | |
160 | cpu_ppc601_store_rtcu(env, val); | |
161 | } | |
162 | ||
163 | target_ulong helper_load_decr (void) | |
164 | { | |
165 | return cpu_ppc_load_decr(env); | |
166 | } | |
167 | ||
168 | void helper_store_decr (target_ulong val) | |
169 | { | |
170 | cpu_ppc_store_decr(env, val); | |
171 | } | |
172 | ||
173 | void helper_store_hid0_601 (target_ulong val) | |
174 | { | |
175 | target_ulong hid0; | |
176 | ||
177 | hid0 = env->spr[SPR_HID0]; | |
178 | if ((val ^ hid0) & 0x00000008) { | |
179 | /* Change current endianness */ | |
180 | env->hflags &= ~(1 << MSR_LE); | |
181 | env->hflags_nmsr &= ~(1 << MSR_LE); | |
182 | env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE); | |
183 | env->hflags |= env->hflags_nmsr; | |
184 | if (loglevel != 0) { | |
185 | fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n", | |
186 | __func__, val & 0x8 ? 'l' : 'b', env->hflags); | |
187 | } | |
a496775f | 188 | } |
45d827d2 | 189 | env->spr[SPR_HID0] = (uint32_t)val; |
a496775f JM |
190 | } |
191 | ||
45d827d2 AJ |
192 | void helper_store_403_pbr (uint32_t num, target_ulong value) |
193 | { | |
194 | if (likely(env->pb[num] != value)) { | |
195 | env->pb[num] = value; | |
196 | /* Should be optimized */ | |
197 | tlb_flush(env, 1); | |
198 | } | |
199 | } | |
200 | ||
201 | target_ulong helper_load_40x_pit (void) | |
202 | { | |
203 | return load_40x_pit(env); | |
204 | } | |
205 | ||
206 | void helper_store_40x_pit (target_ulong val) | |
207 | { | |
208 | store_40x_pit(env, val); | |
209 | } | |
210 | ||
211 | void helper_store_40x_dbcr0 (target_ulong val) | |
212 | { | |
213 | store_40x_dbcr0(env, val); | |
214 | } | |
215 | ||
216 | void helper_store_40x_sler (target_ulong val) | |
217 | { | |
218 | store_40x_sler(env, val); | |
219 | } | |
220 | ||
221 | void helper_store_booke_tcr (target_ulong val) | |
222 | { | |
223 | store_booke_tcr(env, val); | |
224 | } | |
225 | ||
226 | void helper_store_booke_tsr (target_ulong val) | |
227 | { | |
228 | store_booke_tsr(env, val); | |
229 | } | |
230 | ||
231 | void helper_store_ibatu (uint32_t nr, target_ulong val) | |
232 | { | |
233 | ppc_store_ibatu(env, nr, val); | |
234 | } | |
235 | ||
236 | void helper_store_ibatl (uint32_t nr, target_ulong val) | |
237 | { | |
238 | ppc_store_ibatl(env, nr, val); | |
239 | } | |
240 | ||
241 | void helper_store_dbatu (uint32_t nr, target_ulong val) | |
242 | { | |
243 | ppc_store_dbatu(env, nr, val); | |
244 | } | |
245 | ||
246 | void helper_store_dbatl (uint32_t nr, target_ulong val) | |
247 | { | |
248 | ppc_store_dbatl(env, nr, val); | |
249 | } | |
250 | ||
251 | void helper_store_601_batl (uint32_t nr, target_ulong val) | |
252 | { | |
253 | ppc_store_ibatl_601(env, nr, val); | |
254 | } | |
255 | ||
256 | void helper_store_601_batu (uint32_t nr, target_ulong val) | |
257 | { | |
258 | ppc_store_ibatu_601(env, nr, val); | |
259 | } | |
260 | #endif | |
261 | ||
ff4a62cd AJ |
262 | /*****************************************************************************/ |
263 | /* Memory load and stores */ | |
264 | ||
76db3ba4 | 265 | static always_inline target_ulong addr_add(target_ulong addr, target_long arg) |
ff4a62cd AJ |
266 | { |
267 | #if defined(TARGET_PPC64) | |
76db3ba4 AJ |
268 | if (!msr_sf) |
269 | return (uint32_t)(addr + arg); | |
ff4a62cd AJ |
270 | else |
271 | #endif | |
76db3ba4 | 272 | return addr + arg; |
ff4a62cd AJ |
273 | } |
274 | ||
275 | void helper_lmw (target_ulong addr, uint32_t reg) | |
276 | { | |
76db3ba4 | 277 | for (; reg < 32; reg++) { |
ff4a62cd | 278 | if (msr_le) |
76db3ba4 | 279 | env->gpr[reg] = bswap32(ldl(addr)); |
ff4a62cd | 280 | else |
76db3ba4 AJ |
281 | env->gpr[reg] = ldl(addr); |
282 | addr = addr_add(addr, 4); | |
ff4a62cd AJ |
283 | } |
284 | } | |
285 | ||
286 | void helper_stmw (target_ulong addr, uint32_t reg) | |
287 | { | |
76db3ba4 | 288 | for (; reg < 32; reg++) { |
ff4a62cd | 289 | if (msr_le) |
76db3ba4 | 290 | stl(addr, bswap32((uint32_t)env->gpr[reg])); |
ff4a62cd | 291 | else |
76db3ba4 AJ |
292 | stl(addr, (uint32_t)env->gpr[reg]); |
293 | addr = addr_add(addr, 4); | |
ff4a62cd AJ |
294 | } |
295 | } | |
296 | ||
dfbc799d AJ |
297 | void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg) |
298 | { | |
299 | int sh; | |
76db3ba4 AJ |
300 | for (; nb > 3; nb -= 4) { |
301 | env->gpr[reg] = ldl(addr); | |
dfbc799d | 302 | reg = (reg + 1) % 32; |
76db3ba4 | 303 | addr = addr_add(addr, 4); |
dfbc799d AJ |
304 | } |
305 | if (unlikely(nb > 0)) { | |
306 | env->gpr[reg] = 0; | |
76db3ba4 AJ |
307 | for (sh = 24; nb > 0; nb--, sh -= 8) { |
308 | env->gpr[reg] |= ldub(addr) << sh; | |
309 | addr = addr_add(addr, 1); | |
dfbc799d AJ |
310 | } |
311 | } | |
312 | } | |
313 | /* PPC32 specification says we must generate an exception if | |
314 | * rA is in the range of registers to be loaded. | |
315 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
316 | * For now, I'll follow the spec... | |
317 | */ | |
318 | void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb) | |
319 | { | |
320 | if (likely(xer_bc != 0)) { | |
321 | if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) || | |
322 | (reg < rb && (reg + xer_bc) > rb))) { | |
e06fcd75 AJ |
323 | helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
324 | POWERPC_EXCP_INVAL | | |
325 | POWERPC_EXCP_INVAL_LSWX); | |
dfbc799d AJ |
326 | } else { |
327 | helper_lsw(addr, xer_bc, reg); | |
328 | } | |
329 | } | |
330 | } | |
331 | ||
332 | void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg) | |
333 | { | |
334 | int sh; | |
76db3ba4 AJ |
335 | for (; nb > 3; nb -= 4) { |
336 | stl(addr, env->gpr[reg]); | |
dfbc799d | 337 | reg = (reg + 1) % 32; |
76db3ba4 | 338 | addr = addr_add(addr, 4); |
dfbc799d AJ |
339 | } |
340 | if (unlikely(nb > 0)) { | |
76db3ba4 AJ |
341 | for (sh = 24; nb > 0; nb--, sh -= 8) |
342 | stb(addr, (env->gpr[reg] >> sh) & 0xFF); | |
343 | addr = addr_add(addr, 1); | |
dfbc799d AJ |
344 | } |
345 | } | |
346 | ||
799a8c8d AJ |
347 | static void do_dcbz(target_ulong addr, int dcache_line_size) |
348 | { | |
76db3ba4 | 349 | addr &= ~(dcache_line_size - 1); |
799a8c8d | 350 | int i; |
799a8c8d | 351 | for (i = 0 ; i < dcache_line_size ; i += 4) { |
dcc532c8 | 352 | stl(addr + i , 0); |
799a8c8d | 353 | } |
76db3ba4 | 354 | if (env->reserve == addr) |
799a8c8d AJ |
355 | env->reserve = (target_ulong)-1ULL; |
356 | } | |
357 | ||
358 | void helper_dcbz(target_ulong addr) | |
359 | { | |
360 | do_dcbz(addr, env->dcache_line_size); | |
361 | } | |
362 | ||
363 | void helper_dcbz_970(target_ulong addr) | |
364 | { | |
365 | if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) | |
366 | do_dcbz(addr, 32); | |
367 | else | |
368 | do_dcbz(addr, env->dcache_line_size); | |
369 | } | |
370 | ||
37d269df AJ |
371 | void helper_icbi(target_ulong addr) |
372 | { | |
373 | uint32_t tmp; | |
374 | ||
76db3ba4 | 375 | addr &= ~(env->dcache_line_size - 1); |
37d269df AJ |
376 | /* Invalidate one cache line : |
377 | * PowerPC specification says this is to be treated like a load | |
378 | * (not a fetch) by the MMU. To be sure it will be so, | |
379 | * do the load "by hand". | |
380 | */ | |
dcc532c8 | 381 | tmp = ldl(addr); |
37d269df AJ |
382 | tb_invalidate_page_range(addr, addr + env->icache_line_size); |
383 | } | |
384 | ||
bdb4b689 AJ |
385 | // XXX: to be tested |
386 | target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb) | |
387 | { | |
388 | int i, c, d; | |
bdb4b689 AJ |
389 | d = 24; |
390 | for (i = 0; i < xer_bc; i++) { | |
76db3ba4 AJ |
391 | c = ldub(addr); |
392 | addr = addr_add(addr, 1); | |
bdb4b689 AJ |
393 | /* ra (if not 0) and rb are never modified */ |
394 | if (likely(reg != rb && (ra == 0 || reg != ra))) { | |
395 | env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d); | |
396 | } | |
397 | if (unlikely(c == xer_cmp)) | |
398 | break; | |
399 | if (likely(d != 0)) { | |
400 | d -= 8; | |
401 | } else { | |
402 | d = 24; | |
403 | reg++; | |
404 | reg = reg & 0x1F; | |
405 | } | |
406 | } | |
407 | return i; | |
408 | } | |
409 | ||
9a64fbe4 | 410 | /*****************************************************************************/ |
fdabc366 | 411 | /* Fixed point operations helpers */ |
d9bce9d9 | 412 | #if defined(TARGET_PPC64) |
d9bce9d9 | 413 | |
74637406 AJ |
414 | /* multiply high word */ |
415 | uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2) | |
fdabc366 | 416 | { |
74637406 | 417 | uint64_t tl, th; |
fdabc366 | 418 | |
74637406 AJ |
419 | muls64(&tl, &th, arg1, arg2); |
420 | return th; | |
d9bce9d9 | 421 | } |
d9bce9d9 | 422 | |
74637406 AJ |
423 | /* multiply high word unsigned */ |
424 | uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2) | |
fdabc366 | 425 | { |
74637406 | 426 | uint64_t tl, th; |
fdabc366 | 427 | |
74637406 AJ |
428 | mulu64(&tl, &th, arg1, arg2); |
429 | return th; | |
fdabc366 FB |
430 | } |
431 | ||
74637406 | 432 | uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2) |
fdabc366 | 433 | { |
d9bce9d9 JM |
434 | int64_t th; |
435 | uint64_t tl; | |
436 | ||
74637406 | 437 | muls64(&tl, (uint64_t *)&th, arg1, arg2); |
88ad920b | 438 | /* If th != 0 && th != -1, then we had an overflow */ |
6f2d8978 | 439 | if (likely((uint64_t)(th + 1) <= 1)) { |
3d7b417e | 440 | env->xer &= ~(1 << XER_OV); |
fdabc366 | 441 | } else { |
3d7b417e | 442 | env->xer |= (1 << XER_OV) | (1 << XER_SO); |
fdabc366 | 443 | } |
74637406 | 444 | return (int64_t)tl; |
d9bce9d9 JM |
445 | } |
446 | #endif | |
447 | ||
26d67362 | 448 | target_ulong helper_cntlzw (target_ulong t) |
603fccce | 449 | { |
26d67362 | 450 | return clz32(t); |
603fccce JM |
451 | } |
452 | ||
453 | #if defined(TARGET_PPC64) | |
26d67362 | 454 | target_ulong helper_cntlzd (target_ulong t) |
603fccce | 455 | { |
26d67362 | 456 | return clz64(t); |
603fccce JM |
457 | } |
458 | #endif | |
459 | ||
9a64fbe4 | 460 | /* shift right arithmetic helper */ |
26d67362 | 461 | target_ulong helper_sraw (target_ulong value, target_ulong shift) |
9a64fbe4 FB |
462 | { |
463 | int32_t ret; | |
464 | ||
26d67362 AJ |
465 | if (likely(!(shift & 0x20))) { |
466 | if (likely((uint32_t)shift != 0)) { | |
467 | shift &= 0x1f; | |
468 | ret = (int32_t)value >> shift; | |
469 | if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) { | |
3d7b417e | 470 | env->xer &= ~(1 << XER_CA); |
fdabc366 | 471 | } else { |
3d7b417e | 472 | env->xer |= (1 << XER_CA); |
fdabc366 FB |
473 | } |
474 | } else { | |
26d67362 | 475 | ret = (int32_t)value; |
3d7b417e | 476 | env->xer &= ~(1 << XER_CA); |
fdabc366 FB |
477 | } |
478 | } else { | |
26d67362 AJ |
479 | ret = (int32_t)value >> 31; |
480 | if (ret) { | |
3d7b417e | 481 | env->xer |= (1 << XER_CA); |
26d67362 AJ |
482 | } else { |
483 | env->xer &= ~(1 << XER_CA); | |
76a66253 | 484 | } |
fdabc366 | 485 | } |
26d67362 | 486 | return (target_long)ret; |
9a64fbe4 FB |
487 | } |
488 | ||
d9bce9d9 | 489 | #if defined(TARGET_PPC64) |
26d67362 | 490 | target_ulong helper_srad (target_ulong value, target_ulong shift) |
d9bce9d9 JM |
491 | { |
492 | int64_t ret; | |
493 | ||
26d67362 AJ |
494 | if (likely(!(shift & 0x40))) { |
495 | if (likely((uint64_t)shift != 0)) { | |
496 | shift &= 0x3f; | |
497 | ret = (int64_t)value >> shift; | |
498 | if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) { | |
3d7b417e | 499 | env->xer &= ~(1 << XER_CA); |
d9bce9d9 | 500 | } else { |
3d7b417e | 501 | env->xer |= (1 << XER_CA); |
d9bce9d9 JM |
502 | } |
503 | } else { | |
26d67362 | 504 | ret = (int64_t)value; |
3d7b417e | 505 | env->xer &= ~(1 << XER_CA); |
d9bce9d9 JM |
506 | } |
507 | } else { | |
26d67362 AJ |
508 | ret = (int64_t)value >> 63; |
509 | if (ret) { | |
3d7b417e | 510 | env->xer |= (1 << XER_CA); |
26d67362 AJ |
511 | } else { |
512 | env->xer &= ~(1 << XER_CA); | |
d9bce9d9 JM |
513 | } |
514 | } | |
26d67362 | 515 | return ret; |
d9bce9d9 JM |
516 | } |
517 | #endif | |
518 | ||
26d67362 | 519 | target_ulong helper_popcntb (target_ulong val) |
d9bce9d9 | 520 | { |
6176a26d AJ |
521 | val = (val & 0x55555555) + ((val >> 1) & 0x55555555); |
522 | val = (val & 0x33333333) + ((val >> 2) & 0x33333333); | |
523 | val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f); | |
524 | return val; | |
d9bce9d9 JM |
525 | } |
526 | ||
527 | #if defined(TARGET_PPC64) | |
26d67362 | 528 | target_ulong helper_popcntb_64 (target_ulong val) |
d9bce9d9 | 529 | { |
6176a26d AJ |
530 | val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL); |
531 | val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL); | |
532 | val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL); | |
533 | return val; | |
d9bce9d9 JM |
534 | } |
535 | #endif | |
536 | ||
fdabc366 | 537 | /*****************************************************************************/ |
9a64fbe4 | 538 | /* Floating point operations helpers */ |
a0d7d5a7 AJ |
539 | uint64_t helper_float32_to_float64(uint32_t arg) |
540 | { | |
541 | CPU_FloatU f; | |
542 | CPU_DoubleU d; | |
543 | f.l = arg; | |
544 | d.d = float32_to_float64(f.f, &env->fp_status); | |
545 | return d.ll; | |
546 | } | |
547 | ||
548 | uint32_t helper_float64_to_float32(uint64_t arg) | |
549 | { | |
550 | CPU_FloatU f; | |
551 | CPU_DoubleU d; | |
552 | d.ll = arg; | |
553 | f.f = float64_to_float32(d.d, &env->fp_status); | |
554 | return f.l; | |
555 | } | |
556 | ||
0ca9d380 | 557 | static always_inline int isden (float64 d) |
7c58044c | 558 | { |
0ca9d380 | 559 | CPU_DoubleU u; |
7c58044c | 560 | |
0ca9d380 | 561 | u.d = d; |
7c58044c | 562 | |
0ca9d380 | 563 | return ((u.ll >> 52) & 0x7FF) == 0; |
7c58044c JM |
564 | } |
565 | ||
af12906f | 566 | uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf) |
7c58044c | 567 | { |
af12906f | 568 | CPU_DoubleU farg; |
7c58044c | 569 | int isneg; |
af12906f AJ |
570 | int ret; |
571 | farg.ll = arg; | |
f23c346e | 572 | isneg = float64_is_neg(farg.d); |
af12906f AJ |
573 | if (unlikely(float64_is_nan(farg.d))) { |
574 | if (float64_is_signaling_nan(farg.d)) { | |
7c58044c | 575 | /* Signaling NaN: flags are undefined */ |
af12906f | 576 | ret = 0x00; |
7c58044c JM |
577 | } else { |
578 | /* Quiet NaN */ | |
af12906f | 579 | ret = 0x11; |
7c58044c | 580 | } |
f23c346e | 581 | } else if (unlikely(float64_is_infinity(farg.d))) { |
7c58044c JM |
582 | /* +/- infinity */ |
583 | if (isneg) | |
af12906f | 584 | ret = 0x09; |
7c58044c | 585 | else |
af12906f | 586 | ret = 0x05; |
7c58044c | 587 | } else { |
f23c346e | 588 | if (float64_is_zero(farg.d)) { |
7c58044c JM |
589 | /* +/- zero */ |
590 | if (isneg) | |
af12906f | 591 | ret = 0x12; |
7c58044c | 592 | else |
af12906f | 593 | ret = 0x02; |
7c58044c | 594 | } else { |
af12906f | 595 | if (isden(farg.d)) { |
7c58044c | 596 | /* Denormalized numbers */ |
af12906f | 597 | ret = 0x10; |
7c58044c JM |
598 | } else { |
599 | /* Normalized numbers */ | |
af12906f | 600 | ret = 0x00; |
7c58044c JM |
601 | } |
602 | if (isneg) { | |
af12906f | 603 | ret |= 0x08; |
7c58044c | 604 | } else { |
af12906f | 605 | ret |= 0x04; |
7c58044c JM |
606 | } |
607 | } | |
608 | } | |
609 | if (set_fprf) { | |
610 | /* We update FPSCR_FPRF */ | |
611 | env->fpscr &= ~(0x1F << FPSCR_FPRF); | |
af12906f | 612 | env->fpscr |= ret << FPSCR_FPRF; |
7c58044c JM |
613 | } |
614 | /* We just need fpcc to update Rc1 */ | |
af12906f | 615 | return ret & 0xF; |
7c58044c JM |
616 | } |
617 | ||
618 | /* Floating-point invalid operations exception */ | |
af12906f | 619 | static always_inline uint64_t fload_invalid_op_excp (int op) |
7c58044c | 620 | { |
af12906f | 621 | uint64_t ret = 0; |
7c58044c JM |
622 | int ve; |
623 | ||
624 | ve = fpscr_ve; | |
e0147e41 AJ |
625 | switch (op) { |
626 | case POWERPC_EXCP_FP_VXSNAN: | |
7c58044c | 627 | env->fpscr |= 1 << FPSCR_VXSNAN; |
e0147e41 AJ |
628 | break; |
629 | case POWERPC_EXCP_FP_VXSOFT: | |
7c58044c | 630 | env->fpscr |= 1 << FPSCR_VXSOFT; |
e0147e41 | 631 | break; |
7c58044c JM |
632 | case POWERPC_EXCP_FP_VXISI: |
633 | /* Magnitude subtraction of infinities */ | |
634 | env->fpscr |= 1 << FPSCR_VXISI; | |
635 | goto update_arith; | |
636 | case POWERPC_EXCP_FP_VXIDI: | |
637 | /* Division of infinity by infinity */ | |
638 | env->fpscr |= 1 << FPSCR_VXIDI; | |
639 | goto update_arith; | |
640 | case POWERPC_EXCP_FP_VXZDZ: | |
641 | /* Division of zero by zero */ | |
642 | env->fpscr |= 1 << FPSCR_VXZDZ; | |
643 | goto update_arith; | |
644 | case POWERPC_EXCP_FP_VXIMZ: | |
645 | /* Multiplication of zero by infinity */ | |
646 | env->fpscr |= 1 << FPSCR_VXIMZ; | |
647 | goto update_arith; | |
648 | case POWERPC_EXCP_FP_VXVC: | |
649 | /* Ordered comparison of NaN */ | |
650 | env->fpscr |= 1 << FPSCR_VXVC; | |
651 | env->fpscr &= ~(0xF << FPSCR_FPCC); | |
652 | env->fpscr |= 0x11 << FPSCR_FPCC; | |
653 | /* We must update the target FPR before raising the exception */ | |
654 | if (ve != 0) { | |
655 | env->exception_index = POWERPC_EXCP_PROGRAM; | |
656 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; | |
657 | /* Update the floating-point enabled exception summary */ | |
658 | env->fpscr |= 1 << FPSCR_FEX; | |
659 | /* Exception is differed */ | |
660 | ve = 0; | |
661 | } | |
662 | break; | |
663 | case POWERPC_EXCP_FP_VXSQRT: | |
664 | /* Square root of a negative number */ | |
665 | env->fpscr |= 1 << FPSCR_VXSQRT; | |
666 | update_arith: | |
667 | env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); | |
668 | if (ve == 0) { | |
669 | /* Set the result to quiet NaN */ | |
e0147e41 | 670 | ret = 0xFFF8000000000000ULL; |
7c58044c JM |
671 | env->fpscr &= ~(0xF << FPSCR_FPCC); |
672 | env->fpscr |= 0x11 << FPSCR_FPCC; | |
673 | } | |
674 | break; | |
675 | case POWERPC_EXCP_FP_VXCVI: | |
676 | /* Invalid conversion */ | |
677 | env->fpscr |= 1 << FPSCR_VXCVI; | |
678 | env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); | |
679 | if (ve == 0) { | |
680 | /* Set the result to quiet NaN */ | |
e0147e41 | 681 | ret = 0xFFF8000000000000ULL; |
7c58044c JM |
682 | env->fpscr &= ~(0xF << FPSCR_FPCC); |
683 | env->fpscr |= 0x11 << FPSCR_FPCC; | |
684 | } | |
685 | break; | |
686 | } | |
687 | /* Update the floating-point invalid operation summary */ | |
688 | env->fpscr |= 1 << FPSCR_VX; | |
689 | /* Update the floating-point exception summary */ | |
690 | env->fpscr |= 1 << FPSCR_FX; | |
691 | if (ve != 0) { | |
692 | /* Update the floating-point enabled exception summary */ | |
693 | env->fpscr |= 1 << FPSCR_FEX; | |
694 | if (msr_fe0 != 0 || msr_fe1 != 0) | |
e06fcd75 | 695 | helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op); |
7c58044c | 696 | } |
af12906f | 697 | return ret; |
7c58044c JM |
698 | } |
699 | ||
e33e94f9 | 700 | static always_inline void float_zero_divide_excp (void) |
7c58044c | 701 | { |
7c58044c JM |
702 | env->fpscr |= 1 << FPSCR_ZX; |
703 | env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); | |
704 | /* Update the floating-point exception summary */ | |
705 | env->fpscr |= 1 << FPSCR_FX; | |
706 | if (fpscr_ze != 0) { | |
707 | /* Update the floating-point enabled exception summary */ | |
708 | env->fpscr |= 1 << FPSCR_FEX; | |
709 | if (msr_fe0 != 0 || msr_fe1 != 0) { | |
e06fcd75 AJ |
710 | helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
711 | POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX); | |
7c58044c | 712 | } |
7c58044c JM |
713 | } |
714 | } | |
715 | ||
716 | static always_inline void float_overflow_excp (void) | |
717 | { | |
718 | env->fpscr |= 1 << FPSCR_OX; | |
719 | /* Update the floating-point exception summary */ | |
720 | env->fpscr |= 1 << FPSCR_FX; | |
721 | if (fpscr_oe != 0) { | |
722 | /* XXX: should adjust the result */ | |
723 | /* Update the floating-point enabled exception summary */ | |
724 | env->fpscr |= 1 << FPSCR_FEX; | |
725 | /* We must update the target FPR before raising the exception */ | |
726 | env->exception_index = POWERPC_EXCP_PROGRAM; | |
727 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; | |
728 | } else { | |
729 | env->fpscr |= 1 << FPSCR_XX; | |
730 | env->fpscr |= 1 << FPSCR_FI; | |
731 | } | |
732 | } | |
733 | ||
734 | static always_inline void float_underflow_excp (void) | |
735 | { | |
736 | env->fpscr |= 1 << FPSCR_UX; | |
737 | /* Update the floating-point exception summary */ | |
738 | env->fpscr |= 1 << FPSCR_FX; | |
739 | if (fpscr_ue != 0) { | |
740 | /* XXX: should adjust the result */ | |
741 | /* Update the floating-point enabled exception summary */ | |
742 | env->fpscr |= 1 << FPSCR_FEX; | |
743 | /* We must update the target FPR before raising the exception */ | |
744 | env->exception_index = POWERPC_EXCP_PROGRAM; | |
745 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX; | |
746 | } | |
747 | } | |
748 | ||
749 | static always_inline void float_inexact_excp (void) | |
750 | { | |
751 | env->fpscr |= 1 << FPSCR_XX; | |
752 | /* Update the floating-point exception summary */ | |
753 | env->fpscr |= 1 << FPSCR_FX; | |
754 | if (fpscr_xe != 0) { | |
755 | /* Update the floating-point enabled exception summary */ | |
756 | env->fpscr |= 1 << FPSCR_FEX; | |
757 | /* We must update the target FPR before raising the exception */ | |
758 | env->exception_index = POWERPC_EXCP_PROGRAM; | |
759 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; | |
760 | } | |
761 | } | |
762 | ||
763 | static always_inline void fpscr_set_rounding_mode (void) | |
764 | { | |
765 | int rnd_type; | |
766 | ||
767 | /* Set rounding mode */ | |
768 | switch (fpscr_rn) { | |
769 | case 0: | |
770 | /* Best approximation (round to nearest) */ | |
771 | rnd_type = float_round_nearest_even; | |
772 | break; | |
773 | case 1: | |
774 | /* Smaller magnitude (round toward zero) */ | |
775 | rnd_type = float_round_to_zero; | |
776 | break; | |
777 | case 2: | |
778 | /* Round toward +infinite */ | |
779 | rnd_type = float_round_up; | |
780 | break; | |
781 | default: | |
782 | case 3: | |
783 | /* Round toward -infinite */ | |
784 | rnd_type = float_round_down; | |
785 | break; | |
786 | } | |
787 | set_float_rounding_mode(rnd_type, &env->fp_status); | |
788 | } | |
789 | ||
6e35d524 AJ |
790 | void helper_fpscr_clrbit (uint32_t bit) |
791 | { | |
792 | int prev; | |
793 | ||
794 | prev = (env->fpscr >> bit) & 1; | |
795 | env->fpscr &= ~(1 << bit); | |
796 | if (prev == 1) { | |
797 | switch (bit) { | |
798 | case FPSCR_RN1: | |
799 | case FPSCR_RN: | |
800 | fpscr_set_rounding_mode(); | |
801 | break; | |
802 | default: | |
803 | break; | |
804 | } | |
805 | } | |
806 | } | |
807 | ||
af12906f | 808 | void helper_fpscr_setbit (uint32_t bit) |
7c58044c JM |
809 | { |
810 | int prev; | |
811 | ||
812 | prev = (env->fpscr >> bit) & 1; | |
813 | env->fpscr |= 1 << bit; | |
814 | if (prev == 0) { | |
815 | switch (bit) { | |
816 | case FPSCR_VX: | |
817 | env->fpscr |= 1 << FPSCR_FX; | |
818 | if (fpscr_ve) | |
819 | goto raise_ve; | |
820 | case FPSCR_OX: | |
821 | env->fpscr |= 1 << FPSCR_FX; | |
822 | if (fpscr_oe) | |
823 | goto raise_oe; | |
824 | break; | |
825 | case FPSCR_UX: | |
826 | env->fpscr |= 1 << FPSCR_FX; | |
827 | if (fpscr_ue) | |
828 | goto raise_ue; | |
829 | break; | |
830 | case FPSCR_ZX: | |
831 | env->fpscr |= 1 << FPSCR_FX; | |
832 | if (fpscr_ze) | |
833 | goto raise_ze; | |
834 | break; | |
835 | case FPSCR_XX: | |
836 | env->fpscr |= 1 << FPSCR_FX; | |
837 | if (fpscr_xe) | |
838 | goto raise_xe; | |
839 | break; | |
840 | case FPSCR_VXSNAN: | |
841 | case FPSCR_VXISI: | |
842 | case FPSCR_VXIDI: | |
843 | case FPSCR_VXZDZ: | |
844 | case FPSCR_VXIMZ: | |
845 | case FPSCR_VXVC: | |
846 | case FPSCR_VXSOFT: | |
847 | case FPSCR_VXSQRT: | |
848 | case FPSCR_VXCVI: | |
849 | env->fpscr |= 1 << FPSCR_VX; | |
850 | env->fpscr |= 1 << FPSCR_FX; | |
851 | if (fpscr_ve != 0) | |
852 | goto raise_ve; | |
853 | break; | |
854 | case FPSCR_VE: | |
855 | if (fpscr_vx != 0) { | |
856 | raise_ve: | |
857 | env->error_code = POWERPC_EXCP_FP; | |
858 | if (fpscr_vxsnan) | |
859 | env->error_code |= POWERPC_EXCP_FP_VXSNAN; | |
860 | if (fpscr_vxisi) | |
861 | env->error_code |= POWERPC_EXCP_FP_VXISI; | |
862 | if (fpscr_vxidi) | |
863 | env->error_code |= POWERPC_EXCP_FP_VXIDI; | |
864 | if (fpscr_vxzdz) | |
865 | env->error_code |= POWERPC_EXCP_FP_VXZDZ; | |
866 | if (fpscr_vximz) | |
867 | env->error_code |= POWERPC_EXCP_FP_VXIMZ; | |
868 | if (fpscr_vxvc) | |
869 | env->error_code |= POWERPC_EXCP_FP_VXVC; | |
870 | if (fpscr_vxsoft) | |
871 | env->error_code |= POWERPC_EXCP_FP_VXSOFT; | |
872 | if (fpscr_vxsqrt) | |
873 | env->error_code |= POWERPC_EXCP_FP_VXSQRT; | |
874 | if (fpscr_vxcvi) | |
875 | env->error_code |= POWERPC_EXCP_FP_VXCVI; | |
876 | goto raise_excp; | |
877 | } | |
878 | break; | |
879 | case FPSCR_OE: | |
880 | if (fpscr_ox != 0) { | |
881 | raise_oe: | |
882 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; | |
883 | goto raise_excp; | |
884 | } | |
885 | break; | |
886 | case FPSCR_UE: | |
887 | if (fpscr_ux != 0) { | |
888 | raise_ue: | |
889 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX; | |
890 | goto raise_excp; | |
891 | } | |
892 | break; | |
893 | case FPSCR_ZE: | |
894 | if (fpscr_zx != 0) { | |
895 | raise_ze: | |
896 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX; | |
897 | goto raise_excp; | |
898 | } | |
899 | break; | |
900 | case FPSCR_XE: | |
901 | if (fpscr_xx != 0) { | |
902 | raise_xe: | |
903 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; | |
904 | goto raise_excp; | |
905 | } | |
906 | break; | |
907 | case FPSCR_RN1: | |
908 | case FPSCR_RN: | |
909 | fpscr_set_rounding_mode(); | |
910 | break; | |
911 | default: | |
912 | break; | |
913 | raise_excp: | |
914 | /* Update the floating-point enabled exception summary */ | |
915 | env->fpscr |= 1 << FPSCR_FEX; | |
916 | /* We have to update Rc1 before raising the exception */ | |
917 | env->exception_index = POWERPC_EXCP_PROGRAM; | |
918 | break; | |
919 | } | |
920 | } | |
921 | } | |
922 | ||
af12906f | 923 | void helper_store_fpscr (uint64_t arg, uint32_t mask) |
7c58044c JM |
924 | { |
925 | /* | |
926 | * We use only the 32 LSB of the incoming fpr | |
927 | */ | |
7c58044c JM |
928 | uint32_t prev, new; |
929 | int i; | |
930 | ||
7c58044c | 931 | prev = env->fpscr; |
af12906f | 932 | new = (uint32_t)arg; |
27ee5df0 AJ |
933 | new &= ~0x60000000; |
934 | new |= prev & 0x60000000; | |
935 | for (i = 0; i < 8; i++) { | |
7c58044c JM |
936 | if (mask & (1 << i)) { |
937 | env->fpscr &= ~(0xF << (4 * i)); | |
938 | env->fpscr |= new & (0xF << (4 * i)); | |
939 | } | |
940 | } | |
941 | /* Update VX and FEX */ | |
942 | if (fpscr_ix != 0) | |
943 | env->fpscr |= 1 << FPSCR_VX; | |
5567025f AJ |
944 | else |
945 | env->fpscr &= ~(1 << FPSCR_VX); | |
7c58044c JM |
946 | if ((fpscr_ex & fpscr_eex) != 0) { |
947 | env->fpscr |= 1 << FPSCR_FEX; | |
948 | env->exception_index = POWERPC_EXCP_PROGRAM; | |
949 | /* XXX: we should compute it properly */ | |
950 | env->error_code = POWERPC_EXCP_FP; | |
951 | } | |
5567025f AJ |
952 | else |
953 | env->fpscr &= ~(1 << FPSCR_FEX); | |
7c58044c JM |
954 | fpscr_set_rounding_mode(); |
955 | } | |
7c58044c | 956 | |
af12906f | 957 | void helper_float_check_status (void) |
7c58044c | 958 | { |
af12906f | 959 | #ifdef CONFIG_SOFTFLOAT |
7c58044c JM |
960 | if (env->exception_index == POWERPC_EXCP_PROGRAM && |
961 | (env->error_code & POWERPC_EXCP_FP)) { | |
962 | /* Differred floating-point exception after target FPR update */ | |
963 | if (msr_fe0 != 0 || msr_fe1 != 0) | |
e06fcd75 | 964 | helper_raise_exception_err(env->exception_index, env->error_code); |
be94c952 AJ |
965 | } else { |
966 | int status = get_float_exception_flags(&env->fp_status); | |
e33e94f9 AJ |
967 | if (status & float_flag_divbyzero) { |
968 | float_zero_divide_excp(); | |
969 | } else if (status & float_flag_overflow) { | |
be94c952 AJ |
970 | float_overflow_excp(); |
971 | } else if (status & float_flag_underflow) { | |
972 | float_underflow_excp(); | |
973 | } else if (status & float_flag_inexact) { | |
974 | float_inexact_excp(); | |
975 | } | |
7c58044c | 976 | } |
af12906f AJ |
977 | #else |
978 | if (env->exception_index == POWERPC_EXCP_PROGRAM && | |
979 | (env->error_code & POWERPC_EXCP_FP)) { | |
980 | /* Differred floating-point exception after target FPR update */ | |
981 | if (msr_fe0 != 0 || msr_fe1 != 0) | |
e06fcd75 | 982 | helper_raise_exception_err(env->exception_index, env->error_code); |
af12906f | 983 | } |
af12906f AJ |
984 | #endif |
985 | } | |
986 | ||
987 | #ifdef CONFIG_SOFTFLOAT | |
988 | void helper_reset_fpstatus (void) | |
989 | { | |
be94c952 | 990 | set_float_exception_flags(0, &env->fp_status); |
7c58044c JM |
991 | } |
992 | #endif | |
993 | ||
af12906f AJ |
994 | /* fadd - fadd. */ |
995 | uint64_t helper_fadd (uint64_t arg1, uint64_t arg2) | |
7c58044c | 996 | { |
af12906f AJ |
997 | CPU_DoubleU farg1, farg2; |
998 | ||
999 | farg1.ll = arg1; | |
1000 | farg2.ll = arg2; | |
1001 | #if USE_PRECISE_EMULATION | |
1002 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
1003 | float64_is_signaling_nan(farg2.d))) { | |
7c58044c | 1004 | /* sNaN addition */ |
af12906f | 1005 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
17218d1f AJ |
1006 | } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) && |
1007 | float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) { | |
7c58044c | 1008 | /* Magnitude subtraction of infinities */ |
cf1cf21e | 1009 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI); |
17218d1f AJ |
1010 | } else { |
1011 | farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status); | |
7c58044c | 1012 | } |
af12906f AJ |
1013 | #else |
1014 | farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status); | |
1015 | #endif | |
1016 | return farg1.ll; | |
7c58044c JM |
1017 | } |
1018 | ||
af12906f AJ |
1019 | /* fsub - fsub. */ |
1020 | uint64_t helper_fsub (uint64_t arg1, uint64_t arg2) | |
1021 | { | |
1022 | CPU_DoubleU farg1, farg2; | |
1023 | ||
1024 | farg1.ll = arg1; | |
1025 | farg2.ll = arg2; | |
1026 | #if USE_PRECISE_EMULATION | |
7c58044c | 1027 | { |
af12906f AJ |
1028 | if (unlikely(float64_is_signaling_nan(farg1.d) || |
1029 | float64_is_signaling_nan(farg2.d))) { | |
7c58044c | 1030 | /* sNaN subtraction */ |
af12906f | 1031 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
17218d1f AJ |
1032 | } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) && |
1033 | float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) { | |
7c58044c | 1034 | /* Magnitude subtraction of infinities */ |
af12906f | 1035 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI); |
17218d1f AJ |
1036 | } else { |
1037 | farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status); | |
7c58044c JM |
1038 | } |
1039 | } | |
af12906f AJ |
1040 | #else |
1041 | farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status); | |
1042 | #endif | |
1043 | return farg1.ll; | |
1044 | } | |
7c58044c | 1045 | |
af12906f AJ |
1046 | /* fmul - fmul. */ |
1047 | uint64_t helper_fmul (uint64_t arg1, uint64_t arg2) | |
7c58044c | 1048 | { |
af12906f AJ |
1049 | CPU_DoubleU farg1, farg2; |
1050 | ||
1051 | farg1.ll = arg1; | |
1052 | farg2.ll = arg2; | |
1053 | #if USE_PRECISE_EMULATION | |
1054 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
1055 | float64_is_signaling_nan(farg2.d))) { | |
7c58044c | 1056 | /* sNaN multiplication */ |
af12906f | 1057 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
f23c346e AJ |
1058 | } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || |
1059 | (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { | |
7c58044c | 1060 | /* Multiplication of zero by infinity */ |
af12906f | 1061 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ); |
7c58044c | 1062 | } else { |
af12906f | 1063 | farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status); |
7c58044c | 1064 | } |
af12906f AJ |
1065 | #else |
1066 | farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status); | |
1067 | #endif | |
1068 | return farg1.ll; | |
1069 | } | |
7c58044c | 1070 | |
af12906f AJ |
1071 | /* fdiv - fdiv. */ |
1072 | uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2) | |
7c58044c | 1073 | { |
af12906f AJ |
1074 | CPU_DoubleU farg1, farg2; |
1075 | ||
1076 | farg1.ll = arg1; | |
1077 | farg2.ll = arg2; | |
1078 | #if USE_PRECISE_EMULATION | |
1079 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
1080 | float64_is_signaling_nan(farg2.d))) { | |
7c58044c | 1081 | /* sNaN division */ |
af12906f | 1082 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
f23c346e | 1083 | } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) { |
7c58044c | 1084 | /* Division of infinity by infinity */ |
af12906f | 1085 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI); |
e33e94f9 AJ |
1086 | } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) { |
1087 | /* Division of zero by zero */ | |
1088 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ); | |
7c58044c | 1089 | } else { |
af12906f | 1090 | farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status); |
7c58044c | 1091 | } |
af12906f AJ |
1092 | #else |
1093 | farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status); | |
1094 | #endif | |
1095 | return farg1.ll; | |
7c58044c | 1096 | } |
7c58044c | 1097 | |
af12906f AJ |
1098 | /* fabs */ |
1099 | uint64_t helper_fabs (uint64_t arg) | |
9a64fbe4 | 1100 | { |
af12906f | 1101 | CPU_DoubleU farg; |
9a64fbe4 | 1102 | |
af12906f AJ |
1103 | farg.ll = arg; |
1104 | farg.d = float64_abs(farg.d); | |
1105 | return farg.ll; | |
1106 | } | |
1107 | ||
1108 | /* fnabs */ | |
1109 | uint64_t helper_fnabs (uint64_t arg) | |
1110 | { | |
1111 | CPU_DoubleU farg; | |
1112 | ||
1113 | farg.ll = arg; | |
1114 | farg.d = float64_abs(farg.d); | |
1115 | farg.d = float64_chs(farg.d); | |
1116 | return farg.ll; | |
1117 | } | |
1118 | ||
1119 | /* fneg */ | |
1120 | uint64_t helper_fneg (uint64_t arg) | |
1121 | { | |
1122 | CPU_DoubleU farg; | |
1123 | ||
1124 | farg.ll = arg; | |
1125 | farg.d = float64_chs(farg.d); | |
1126 | return farg.ll; | |
1127 | } | |
1128 | ||
1129 | /* fctiw - fctiw. */ | |
1130 | uint64_t helper_fctiw (uint64_t arg) | |
1131 | { | |
1132 | CPU_DoubleU farg; | |
1133 | farg.ll = arg; | |
1134 | ||
1135 | if (unlikely(float64_is_signaling_nan(farg.d))) { | |
7c58044c | 1136 | /* sNaN conversion */ |
af12906f | 1137 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
f23c346e | 1138 | } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) { |
7c58044c | 1139 | /* qNan / infinity conversion */ |
af12906f | 1140 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
7c58044c | 1141 | } else { |
af12906f | 1142 | farg.ll = float64_to_int32(farg.d, &env->fp_status); |
1cdb9c3d | 1143 | #if USE_PRECISE_EMULATION |
7c58044c JM |
1144 | /* XXX: higher bits are not supposed to be significant. |
1145 | * to make tests easier, return the same as a real PowerPC 750 | |
1146 | */ | |
af12906f | 1147 | farg.ll |= 0xFFF80000ULL << 32; |
e864cabd | 1148 | #endif |
7c58044c | 1149 | } |
af12906f | 1150 | return farg.ll; |
9a64fbe4 FB |
1151 | } |
1152 | ||
af12906f AJ |
1153 | /* fctiwz - fctiwz. */ |
1154 | uint64_t helper_fctiwz (uint64_t arg) | |
9a64fbe4 | 1155 | { |
af12906f AJ |
1156 | CPU_DoubleU farg; |
1157 | farg.ll = arg; | |
4ecc3190 | 1158 | |
af12906f | 1159 | if (unlikely(float64_is_signaling_nan(farg.d))) { |
7c58044c | 1160 | /* sNaN conversion */ |
af12906f | 1161 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
f23c346e | 1162 | } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) { |
7c58044c | 1163 | /* qNan / infinity conversion */ |
af12906f | 1164 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
7c58044c | 1165 | } else { |
af12906f | 1166 | farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status); |
1cdb9c3d | 1167 | #if USE_PRECISE_EMULATION |
7c58044c JM |
1168 | /* XXX: higher bits are not supposed to be significant. |
1169 | * to make tests easier, return the same as a real PowerPC 750 | |
1170 | */ | |
af12906f | 1171 | farg.ll |= 0xFFF80000ULL << 32; |
e864cabd | 1172 | #endif |
7c58044c | 1173 | } |
af12906f | 1174 | return farg.ll; |
9a64fbe4 FB |
1175 | } |
1176 | ||
426613db | 1177 | #if defined(TARGET_PPC64) |
af12906f AJ |
1178 | /* fcfid - fcfid. */ |
1179 | uint64_t helper_fcfid (uint64_t arg) | |
426613db | 1180 | { |
af12906f AJ |
1181 | CPU_DoubleU farg; |
1182 | farg.d = int64_to_float64(arg, &env->fp_status); | |
1183 | return farg.ll; | |
426613db JM |
1184 | } |
1185 | ||
af12906f AJ |
1186 | /* fctid - fctid. */ |
1187 | uint64_t helper_fctid (uint64_t arg) | |
426613db | 1188 | { |
af12906f AJ |
1189 | CPU_DoubleU farg; |
1190 | farg.ll = arg; | |
426613db | 1191 | |
af12906f | 1192 | if (unlikely(float64_is_signaling_nan(farg.d))) { |
7c58044c | 1193 | /* sNaN conversion */ |
af12906f | 1194 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
f23c346e | 1195 | } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) { |
7c58044c | 1196 | /* qNan / infinity conversion */ |
af12906f | 1197 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
7c58044c | 1198 | } else { |
af12906f | 1199 | farg.ll = float64_to_int64(farg.d, &env->fp_status); |
7c58044c | 1200 | } |
af12906f | 1201 | return farg.ll; |
426613db JM |
1202 | } |
1203 | ||
af12906f AJ |
1204 | /* fctidz - fctidz. */ |
1205 | uint64_t helper_fctidz (uint64_t arg) | |
426613db | 1206 | { |
af12906f AJ |
1207 | CPU_DoubleU farg; |
1208 | farg.ll = arg; | |
426613db | 1209 | |
af12906f | 1210 | if (unlikely(float64_is_signaling_nan(farg.d))) { |
7c58044c | 1211 | /* sNaN conversion */ |
af12906f | 1212 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
f23c346e | 1213 | } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) { |
7c58044c | 1214 | /* qNan / infinity conversion */ |
af12906f | 1215 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
7c58044c | 1216 | } else { |
af12906f | 1217 | farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status); |
7c58044c | 1218 | } |
af12906f | 1219 | return farg.ll; |
426613db JM |
1220 | } |
1221 | ||
1222 | #endif | |
1223 | ||
af12906f | 1224 | static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode) |
d7e4b87e | 1225 | { |
af12906f AJ |
1226 | CPU_DoubleU farg; |
1227 | farg.ll = arg; | |
1228 | ||
1229 | if (unlikely(float64_is_signaling_nan(farg.d))) { | |
7c58044c | 1230 | /* sNaN round */ |
af12906f | 1231 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
f23c346e | 1232 | } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) { |
7c58044c | 1233 | /* qNan / infinity round */ |
af12906f | 1234 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
7c58044c JM |
1235 | } else { |
1236 | set_float_rounding_mode(rounding_mode, &env->fp_status); | |
af12906f | 1237 | farg.ll = float64_round_to_int(farg.d, &env->fp_status); |
7c58044c JM |
1238 | /* Restore rounding mode from FPSCR */ |
1239 | fpscr_set_rounding_mode(); | |
1240 | } | |
af12906f | 1241 | return farg.ll; |
d7e4b87e JM |
1242 | } |
1243 | ||
af12906f | 1244 | uint64_t helper_frin (uint64_t arg) |
d7e4b87e | 1245 | { |
af12906f | 1246 | return do_fri(arg, float_round_nearest_even); |
d7e4b87e JM |
1247 | } |
1248 | ||
af12906f | 1249 | uint64_t helper_friz (uint64_t arg) |
d7e4b87e | 1250 | { |
af12906f | 1251 | return do_fri(arg, float_round_to_zero); |
d7e4b87e JM |
1252 | } |
1253 | ||
af12906f | 1254 | uint64_t helper_frip (uint64_t arg) |
d7e4b87e | 1255 | { |
af12906f | 1256 | return do_fri(arg, float_round_up); |
d7e4b87e JM |
1257 | } |
1258 | ||
af12906f | 1259 | uint64_t helper_frim (uint64_t arg) |
d7e4b87e | 1260 | { |
af12906f | 1261 | return do_fri(arg, float_round_down); |
d7e4b87e JM |
1262 | } |
1263 | ||
af12906f AJ |
1264 | /* fmadd - fmadd. */ |
1265 | uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3) | |
e864cabd | 1266 | { |
af12906f AJ |
1267 | CPU_DoubleU farg1, farg2, farg3; |
1268 | ||
1269 | farg1.ll = arg1; | |
1270 | farg2.ll = arg2; | |
1271 | farg3.ll = arg3; | |
1272 | #if USE_PRECISE_EMULATION | |
1273 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
1274 | float64_is_signaling_nan(farg2.d) || | |
1275 | float64_is_signaling_nan(farg3.d))) { | |
7c58044c | 1276 | /* sNaN operation */ |
af12906f | 1277 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
da1e7ac9 AJ |
1278 | } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || |
1279 | (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { | |
1280 | /* Multiplication of zero by infinity */ | |
1281 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ); | |
7c58044c | 1282 | } else { |
e864cabd | 1283 | #ifdef FLOAT128 |
7c58044c JM |
1284 | /* This is the way the PowerPC specification defines it */ |
1285 | float128 ft0_128, ft1_128; | |
1286 | ||
af12906f AJ |
1287 | ft0_128 = float64_to_float128(farg1.d, &env->fp_status); |
1288 | ft1_128 = float64_to_float128(farg2.d, &env->fp_status); | |
7c58044c | 1289 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); |
da1e7ac9 AJ |
1290 | if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) && |
1291 | float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) { | |
1292 | /* Magnitude subtraction of infinities */ | |
1293 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI); | |
1294 | } else { | |
1295 | ft1_128 = float64_to_float128(farg3.d, &env->fp_status); | |
1296 | ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status); | |
1297 | farg1.d = float128_to_float64(ft0_128, &env->fp_status); | |
1298 | } | |
e864cabd | 1299 | #else |
7c58044c | 1300 | /* This is OK on x86 hosts */ |
af12906f | 1301 | farg1.d = (farg1.d * farg2.d) + farg3.d; |
e864cabd | 1302 | #endif |
7c58044c | 1303 | } |
af12906f AJ |
1304 | #else |
1305 | farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status); | |
1306 | farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status); | |
1307 | #endif | |
1308 | return farg1.ll; | |
e864cabd JM |
1309 | } |
1310 | ||
af12906f AJ |
1311 | /* fmsub - fmsub. */ |
1312 | uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3) | |
e864cabd | 1313 | { |
af12906f AJ |
1314 | CPU_DoubleU farg1, farg2, farg3; |
1315 | ||
1316 | farg1.ll = arg1; | |
1317 | farg2.ll = arg2; | |
1318 | farg3.ll = arg3; | |
1319 | #if USE_PRECISE_EMULATION | |
1320 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
1321 | float64_is_signaling_nan(farg2.d) || | |
1322 | float64_is_signaling_nan(farg3.d))) { | |
7c58044c | 1323 | /* sNaN operation */ |
af12906f | 1324 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
da1e7ac9 AJ |
1325 | } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || |
1326 | (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { | |
1327 | /* Multiplication of zero by infinity */ | |
1328 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ); | |
7c58044c | 1329 | } else { |
e864cabd | 1330 | #ifdef FLOAT128 |
7c58044c JM |
1331 | /* This is the way the PowerPC specification defines it */ |
1332 | float128 ft0_128, ft1_128; | |
1333 | ||
af12906f AJ |
1334 | ft0_128 = float64_to_float128(farg1.d, &env->fp_status); |
1335 | ft1_128 = float64_to_float128(farg2.d, &env->fp_status); | |
7c58044c | 1336 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); |
da1e7ac9 AJ |
1337 | if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) && |
1338 | float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) { | |
1339 | /* Magnitude subtraction of infinities */ | |
1340 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI); | |
1341 | } else { | |
1342 | ft1_128 = float64_to_float128(farg3.d, &env->fp_status); | |
1343 | ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status); | |
1344 | farg1.d = float128_to_float64(ft0_128, &env->fp_status); | |
1345 | } | |
e864cabd | 1346 | #else |
7c58044c | 1347 | /* This is OK on x86 hosts */ |
af12906f | 1348 | farg1.d = (farg1.d * farg2.d) - farg3.d; |
e864cabd | 1349 | #endif |
7c58044c | 1350 | } |
af12906f AJ |
1351 | #else |
1352 | farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status); | |
1353 | farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status); | |
1354 | #endif | |
1355 | return farg1.ll; | |
e864cabd | 1356 | } |
e864cabd | 1357 | |
af12906f AJ |
1358 | /* fnmadd - fnmadd. */ |
1359 | uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3) | |
4b3686fa | 1360 | { |
af12906f AJ |
1361 | CPU_DoubleU farg1, farg2, farg3; |
1362 | ||
1363 | farg1.ll = arg1; | |
1364 | farg2.ll = arg2; | |
1365 | farg3.ll = arg3; | |
1366 | ||
1367 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
1368 | float64_is_signaling_nan(farg2.d) || | |
1369 | float64_is_signaling_nan(farg3.d))) { | |
7c58044c | 1370 | /* sNaN operation */ |
af12906f | 1371 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
da1e7ac9 AJ |
1372 | } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || |
1373 | (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { | |
1374 | /* Multiplication of zero by infinity */ | |
1375 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ); | |
7c58044c | 1376 | } else { |
1cdb9c3d | 1377 | #if USE_PRECISE_EMULATION |
e864cabd | 1378 | #ifdef FLOAT128 |
7c58044c JM |
1379 | /* This is the way the PowerPC specification defines it */ |
1380 | float128 ft0_128, ft1_128; | |
1381 | ||
af12906f AJ |
1382 | ft0_128 = float64_to_float128(farg1.d, &env->fp_status); |
1383 | ft1_128 = float64_to_float128(farg2.d, &env->fp_status); | |
7c58044c | 1384 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); |
da1e7ac9 AJ |
1385 | if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) && |
1386 | float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) { | |
1387 | /* Magnitude subtraction of infinities */ | |
1388 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI); | |
1389 | } else { | |
1390 | ft1_128 = float64_to_float128(farg3.d, &env->fp_status); | |
1391 | ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status); | |
1392 | farg1.d = float128_to_float64(ft0_128, &env->fp_status); | |
1393 | } | |
e864cabd | 1394 | #else |
7c58044c | 1395 | /* This is OK on x86 hosts */ |
af12906f | 1396 | farg1.d = (farg1.d * farg2.d) + farg3.d; |
e864cabd JM |
1397 | #endif |
1398 | #else | |
af12906f AJ |
1399 | farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status); |
1400 | farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status); | |
e864cabd | 1401 | #endif |
a44d2ce1 | 1402 | if (likely(!float64_is_nan(farg1.d))) |
af12906f | 1403 | farg1.d = float64_chs(farg1.d); |
7c58044c | 1404 | } |
af12906f | 1405 | return farg1.ll; |
4b3686fa FB |
1406 | } |
1407 | ||
af12906f AJ |
1408 | /* fnmsub - fnmsub. */ |
1409 | uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3) | |
4b3686fa | 1410 | { |
af12906f AJ |
1411 | CPU_DoubleU farg1, farg2, farg3; |
1412 | ||
1413 | farg1.ll = arg1; | |
1414 | farg2.ll = arg2; | |
1415 | farg3.ll = arg3; | |
1416 | ||
1417 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
1418 | float64_is_signaling_nan(farg2.d) || | |
1419 | float64_is_signaling_nan(farg3.d))) { | |
7c58044c | 1420 | /* sNaN operation */ |
af12906f | 1421 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
da1e7ac9 AJ |
1422 | } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || |
1423 | (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { | |
1424 | /* Multiplication of zero by infinity */ | |
1425 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ); | |
7c58044c | 1426 | } else { |
1cdb9c3d | 1427 | #if USE_PRECISE_EMULATION |
e864cabd | 1428 | #ifdef FLOAT128 |
7c58044c JM |
1429 | /* This is the way the PowerPC specification defines it */ |
1430 | float128 ft0_128, ft1_128; | |
1431 | ||
af12906f AJ |
1432 | ft0_128 = float64_to_float128(farg1.d, &env->fp_status); |
1433 | ft1_128 = float64_to_float128(farg2.d, &env->fp_status); | |
7c58044c | 1434 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); |
da1e7ac9 AJ |
1435 | if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) && |
1436 | float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) { | |
1437 | /* Magnitude subtraction of infinities */ | |
1438 | farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI); | |
1439 | } else { | |
1440 | ft1_128 = float64_to_float128(farg3.d, &env->fp_status); | |
1441 | ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status); | |
1442 | farg1.d = float128_to_float64(ft0_128, &env->fp_status); | |
1443 | } | |
e864cabd | 1444 | #else |
7c58044c | 1445 | /* This is OK on x86 hosts */ |
af12906f | 1446 | farg1.d = (farg1.d * farg2.d) - farg3.d; |
e864cabd JM |
1447 | #endif |
1448 | #else | |
af12906f AJ |
1449 | farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status); |
1450 | farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status); | |
e864cabd | 1451 | #endif |
a44d2ce1 | 1452 | if (likely(!float64_is_nan(farg1.d))) |
af12906f | 1453 | farg1.d = float64_chs(farg1.d); |
7c58044c | 1454 | } |
af12906f | 1455 | return farg1.ll; |
1ef59d0a FB |
1456 | } |
1457 | ||
af12906f AJ |
1458 | /* frsp - frsp. */ |
1459 | uint64_t helper_frsp (uint64_t arg) | |
7c58044c | 1460 | { |
af12906f | 1461 | CPU_DoubleU farg; |
6ad193ed | 1462 | float32 f32; |
af12906f AJ |
1463 | farg.ll = arg; |
1464 | ||
1465 | #if USE_PRECISE_EMULATION | |
1466 | if (unlikely(float64_is_signaling_nan(farg.d))) { | |
7c58044c | 1467 | /* sNaN square root */ |
af12906f | 1468 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
7c58044c | 1469 | } else { |
6ad193ed AJ |
1470 | f32 = float64_to_float32(farg.d, &env->fp_status); |
1471 | farg.d = float32_to_float64(f32, &env->fp_status); | |
7c58044c | 1472 | } |
af12906f | 1473 | #else |
6ad193ed AJ |
1474 | f32 = float64_to_float32(farg.d, &env->fp_status); |
1475 | farg.d = float32_to_float64(f32, &env->fp_status); | |
af12906f AJ |
1476 | #endif |
1477 | return farg.ll; | |
7c58044c | 1478 | } |
7c58044c | 1479 | |
af12906f AJ |
1480 | /* fsqrt - fsqrt. */ |
1481 | uint64_t helper_fsqrt (uint64_t arg) | |
9a64fbe4 | 1482 | { |
af12906f AJ |
1483 | CPU_DoubleU farg; |
1484 | farg.ll = arg; | |
1485 | ||
1486 | if (unlikely(float64_is_signaling_nan(farg.d))) { | |
7c58044c | 1487 | /* sNaN square root */ |
af12906f | 1488 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
f23c346e | 1489 | } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { |
7c58044c | 1490 | /* Square root of a negative nonzero number */ |
af12906f | 1491 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT); |
7c58044c | 1492 | } else { |
af12906f | 1493 | farg.d = float64_sqrt(farg.d, &env->fp_status); |
7c58044c | 1494 | } |
af12906f | 1495 | return farg.ll; |
9a64fbe4 FB |
1496 | } |
1497 | ||
af12906f AJ |
1498 | /* fre - fre. */ |
1499 | uint64_t helper_fre (uint64_t arg) | |
d7e4b87e | 1500 | { |
05b93603 | 1501 | CPU_DoubleU fone, farg; |
01feec08 | 1502 | fone.ll = 0x3FF0000000000000ULL; /* 1.0 */ |
af12906f | 1503 | farg.ll = arg; |
d7e4b87e | 1504 | |
af12906f | 1505 | if (unlikely(float64_is_signaling_nan(farg.d))) { |
7c58044c | 1506 | /* sNaN reciprocal */ |
af12906f | 1507 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
d7e4b87e | 1508 | } else { |
6c01bf6c | 1509 | farg.d = float64_div(fone.d, farg.d, &env->fp_status); |
d7e4b87e | 1510 | } |
af12906f | 1511 | return farg.d; |
d7e4b87e JM |
1512 | } |
1513 | ||
af12906f AJ |
1514 | /* fres - fres. */ |
1515 | uint64_t helper_fres (uint64_t arg) | |
9a64fbe4 | 1516 | { |
05b93603 | 1517 | CPU_DoubleU fone, farg; |
6c01bf6c | 1518 | float32 f32; |
01feec08 | 1519 | fone.ll = 0x3FF0000000000000ULL; /* 1.0 */ |
af12906f | 1520 | farg.ll = arg; |
4ecc3190 | 1521 | |
af12906f | 1522 | if (unlikely(float64_is_signaling_nan(farg.d))) { |
7c58044c | 1523 | /* sNaN reciprocal */ |
af12906f | 1524 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
4ecc3190 | 1525 | } else { |
6c01bf6c AJ |
1526 | farg.d = float64_div(fone.d, farg.d, &env->fp_status); |
1527 | f32 = float64_to_float32(farg.d, &env->fp_status); | |
1528 | farg.d = float32_to_float64(f32, &env->fp_status); | |
4ecc3190 | 1529 | } |
af12906f | 1530 | return farg.ll; |
9a64fbe4 FB |
1531 | } |
1532 | ||
af12906f AJ |
1533 | /* frsqrte - frsqrte. */ |
1534 | uint64_t helper_frsqrte (uint64_t arg) | |
9a64fbe4 | 1535 | { |
05b93603 | 1536 | CPU_DoubleU fone, farg; |
6c01bf6c | 1537 | float32 f32; |
01feec08 | 1538 | fone.ll = 0x3FF0000000000000ULL; /* 1.0 */ |
af12906f | 1539 | farg.ll = arg; |
4ecc3190 | 1540 | |
af12906f | 1541 | if (unlikely(float64_is_signaling_nan(farg.d))) { |
7c58044c | 1542 | /* sNaN reciprocal square root */ |
af12906f | 1543 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
f23c346e | 1544 | } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { |
7c58044c | 1545 | /* Reciprocal square root of a negative nonzero number */ |
af12906f | 1546 | farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT); |
4ecc3190 | 1547 | } else { |
6c01bf6c AJ |
1548 | farg.d = float64_sqrt(farg.d, &env->fp_status); |
1549 | farg.d = float64_div(fone.d, farg.d, &env->fp_status); | |
1550 | f32 = float64_to_float32(farg.d, &env->fp_status); | |
1551 | farg.d = float32_to_float64(f32, &env->fp_status); | |
4ecc3190 | 1552 | } |
af12906f | 1553 | return farg.ll; |
9a64fbe4 FB |
1554 | } |
1555 | ||
af12906f AJ |
1556 | /* fsel - fsel. */ |
1557 | uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3) | |
9a64fbe4 | 1558 | { |
6ad7365a | 1559 | CPU_DoubleU farg1; |
af12906f AJ |
1560 | |
1561 | farg1.ll = arg1; | |
af12906f | 1562 | |
f23c346e | 1563 | if (!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) |
6ad7365a | 1564 | return arg2; |
4ecc3190 | 1565 | else |
6ad7365a | 1566 | return arg3; |
9a64fbe4 FB |
1567 | } |
1568 | ||
9a819377 | 1569 | void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD) |
9a64fbe4 | 1570 | { |
af12906f | 1571 | CPU_DoubleU farg1, farg2; |
e1571908 | 1572 | uint32_t ret = 0; |
af12906f AJ |
1573 | farg1.ll = arg1; |
1574 | farg2.ll = arg2; | |
e1571908 | 1575 | |
9a819377 AJ |
1576 | if (unlikely(float64_is_nan(farg1.d) || |
1577 | float64_is_nan(farg2.d))) { | |
1578 | ret = 0x01UL; | |
1579 | } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) { | |
1580 | ret = 0x08UL; | |
1581 | } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) { | |
1582 | ret = 0x04UL; | |
7c58044c | 1583 | } else { |
9a819377 | 1584 | ret = 0x02UL; |
9a64fbe4 | 1585 | } |
9a819377 | 1586 | |
7c58044c | 1587 | env->fpscr &= ~(0x0F << FPSCR_FPRF); |
e1571908 | 1588 | env->fpscr |= ret << FPSCR_FPRF; |
9a819377 AJ |
1589 | env->crf[crfD] = ret; |
1590 | if (unlikely(ret == 0x01UL | |
1591 | && (float64_is_signaling_nan(farg1.d) || | |
1592 | float64_is_signaling_nan(farg2.d)))) { | |
1593 | /* sNaN comparison */ | |
1594 | fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); | |
1595 | } | |
9a64fbe4 FB |
1596 | } |
1597 | ||
9a819377 | 1598 | void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD) |
9a64fbe4 | 1599 | { |
af12906f | 1600 | CPU_DoubleU farg1, farg2; |
e1571908 | 1601 | uint32_t ret = 0; |
af12906f AJ |
1602 | farg1.ll = arg1; |
1603 | farg2.ll = arg2; | |
e1571908 | 1604 | |
af12906f AJ |
1605 | if (unlikely(float64_is_nan(farg1.d) || |
1606 | float64_is_nan(farg2.d))) { | |
9a819377 AJ |
1607 | ret = 0x01UL; |
1608 | } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) { | |
1609 | ret = 0x08UL; | |
1610 | } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) { | |
1611 | ret = 0x04UL; | |
1612 | } else { | |
1613 | ret = 0x02UL; | |
1614 | } | |
1615 | ||
1616 | env->fpscr &= ~(0x0F << FPSCR_FPRF); | |
1617 | env->fpscr |= ret << FPSCR_FPRF; | |
1618 | env->crf[crfD] = ret; | |
1619 | if (unlikely (ret == 0x01UL)) { | |
af12906f AJ |
1620 | if (float64_is_signaling_nan(farg1.d) || |
1621 | float64_is_signaling_nan(farg2.d)) { | |
7c58044c JM |
1622 | /* sNaN comparison */ |
1623 | fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | | |
1624 | POWERPC_EXCP_FP_VXVC); | |
1625 | } else { | |
1626 | /* qNaN comparison */ | |
1627 | fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC); | |
1628 | } | |
9a64fbe4 | 1629 | } |
9a64fbe4 FB |
1630 | } |
1631 | ||
76a66253 | 1632 | #if !defined (CONFIG_USER_ONLY) |
6527f6ea | 1633 | void helper_store_msr (target_ulong val) |
0411a972 | 1634 | { |
6527f6ea AJ |
1635 | val = hreg_store_msr(env, val, 0); |
1636 | if (val != 0) { | |
0411a972 | 1637 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
e06fcd75 | 1638 | helper_raise_exception(val); |
0411a972 JM |
1639 | } |
1640 | } | |
1641 | ||
d72a19f7 | 1642 | static always_inline void do_rfi (target_ulong nip, target_ulong msr, |
0411a972 | 1643 | target_ulong msrm, int keep_msrh) |
9a64fbe4 | 1644 | { |
426613db | 1645 | #if defined(TARGET_PPC64) |
0411a972 JM |
1646 | if (msr & (1ULL << MSR_SF)) { |
1647 | nip = (uint64_t)nip; | |
1648 | msr &= (uint64_t)msrm; | |
a42bd6cc | 1649 | } else { |
0411a972 JM |
1650 | nip = (uint32_t)nip; |
1651 | msr = (uint32_t)(msr & msrm); | |
1652 | if (keep_msrh) | |
1653 | msr |= env->msr & ~((uint64_t)0xFFFFFFFF); | |
a42bd6cc | 1654 | } |
426613db | 1655 | #else |
0411a972 JM |
1656 | nip = (uint32_t)nip; |
1657 | msr &= (uint32_t)msrm; | |
426613db | 1658 | #endif |
0411a972 JM |
1659 | /* XXX: beware: this is false if VLE is supported */ |
1660 | env->nip = nip & ~((target_ulong)0x00000003); | |
a4f30719 | 1661 | hreg_store_msr(env, msr, 1); |
fdabc366 | 1662 | #if defined (DEBUG_OP) |
0411a972 | 1663 | cpu_dump_rfi(env->nip, env->msr); |
fdabc366 | 1664 | #endif |
0411a972 JM |
1665 | /* No need to raise an exception here, |
1666 | * as rfi is always the last insn of a TB | |
1667 | */ | |
fdabc366 | 1668 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
9a64fbe4 | 1669 | } |
d9bce9d9 | 1670 | |
d72a19f7 | 1671 | void helper_rfi (void) |
0411a972 | 1672 | { |
d72a19f7 AJ |
1673 | do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
1674 | ~((target_ulong)0xFFFF0000), 1); | |
0411a972 JM |
1675 | } |
1676 | ||
d9bce9d9 | 1677 | #if defined(TARGET_PPC64) |
d72a19f7 | 1678 | void helper_rfid (void) |
426613db | 1679 | { |
d72a19f7 AJ |
1680 | do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
1681 | ~((target_ulong)0xFFFF0000), 0); | |
d9bce9d9 | 1682 | } |
7863667f | 1683 | |
d72a19f7 | 1684 | void helper_hrfid (void) |
be147d08 | 1685 | { |
d72a19f7 AJ |
1686 | do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1], |
1687 | ~((target_ulong)0xFFFF0000), 0); | |
be147d08 JM |
1688 | } |
1689 | #endif | |
76a66253 | 1690 | #endif |
9a64fbe4 | 1691 | |
cab3bee2 | 1692 | void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags) |
9a64fbe4 | 1693 | { |
cab3bee2 AJ |
1694 | if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) || |
1695 | ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) || | |
1696 | ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || | |
1697 | ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || | |
1698 | ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { | |
e06fcd75 | 1699 | helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); |
a42bd6cc | 1700 | } |
9a64fbe4 FB |
1701 | } |
1702 | ||
d9bce9d9 | 1703 | #if defined(TARGET_PPC64) |
cab3bee2 | 1704 | void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags) |
d9bce9d9 | 1705 | { |
cab3bee2 AJ |
1706 | if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) || |
1707 | ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) || | |
1708 | ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || | |
1709 | ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || | |
1710 | ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) | |
e06fcd75 | 1711 | helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); |
d9bce9d9 JM |
1712 | } |
1713 | #endif | |
1714 | ||
fdabc366 | 1715 | /*****************************************************************************/ |
76a66253 | 1716 | /* PowerPC 601 specific instructions (POWER bridge) */ |
9a64fbe4 | 1717 | |
22e0e173 | 1718 | target_ulong helper_clcs (uint32_t arg) |
9a64fbe4 | 1719 | { |
22e0e173 | 1720 | switch (arg) { |
76a66253 JM |
1721 | case 0x0CUL: |
1722 | /* Instruction cache line size */ | |
22e0e173 | 1723 | return env->icache_line_size; |
76a66253 JM |
1724 | break; |
1725 | case 0x0DUL: | |
1726 | /* Data cache line size */ | |
22e0e173 | 1727 | return env->dcache_line_size; |
76a66253 JM |
1728 | break; |
1729 | case 0x0EUL: | |
1730 | /* Minimum cache line size */ | |
22e0e173 AJ |
1731 | return (env->icache_line_size < env->dcache_line_size) ? |
1732 | env->icache_line_size : env->dcache_line_size; | |
76a66253 JM |
1733 | break; |
1734 | case 0x0FUL: | |
1735 | /* Maximum cache line size */ | |
22e0e173 AJ |
1736 | return (env->icache_line_size > env->dcache_line_size) ? |
1737 | env->icache_line_size : env->dcache_line_size; | |
76a66253 JM |
1738 | break; |
1739 | default: | |
1740 | /* Undefined */ | |
22e0e173 | 1741 | return 0; |
76a66253 JM |
1742 | break; |
1743 | } | |
1744 | } | |
1745 | ||
22e0e173 | 1746 | target_ulong helper_div (target_ulong arg1, target_ulong arg2) |
76a66253 | 1747 | { |
22e0e173 | 1748 | uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ]; |
76a66253 | 1749 | |
22e0e173 AJ |
1750 | if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) || |
1751 | (int32_t)arg2 == 0) { | |
76a66253 | 1752 | env->spr[SPR_MQ] = 0; |
22e0e173 | 1753 | return INT32_MIN; |
76a66253 | 1754 | } else { |
22e0e173 AJ |
1755 | env->spr[SPR_MQ] = tmp % arg2; |
1756 | return tmp / (int32_t)arg2; | |
76a66253 JM |
1757 | } |
1758 | } | |
1759 | ||
22e0e173 | 1760 | target_ulong helper_divo (target_ulong arg1, target_ulong arg2) |
76a66253 | 1761 | { |
22e0e173 | 1762 | uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ]; |
76a66253 | 1763 | |
22e0e173 AJ |
1764 | if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) || |
1765 | (int32_t)arg2 == 0) { | |
3d7b417e | 1766 | env->xer |= (1 << XER_OV) | (1 << XER_SO); |
76a66253 | 1767 | env->spr[SPR_MQ] = 0; |
22e0e173 | 1768 | return INT32_MIN; |
76a66253 | 1769 | } else { |
22e0e173 AJ |
1770 | env->spr[SPR_MQ] = tmp % arg2; |
1771 | tmp /= (int32_t)arg2; | |
1772 | if ((int32_t)tmp != tmp) { | |
3d7b417e | 1773 | env->xer |= (1 << XER_OV) | (1 << XER_SO); |
76a66253 | 1774 | } else { |
3d7b417e | 1775 | env->xer &= ~(1 << XER_OV); |
76a66253 | 1776 | } |
22e0e173 | 1777 | return tmp; |
76a66253 JM |
1778 | } |
1779 | } | |
1780 | ||
22e0e173 | 1781 | target_ulong helper_divs (target_ulong arg1, target_ulong arg2) |
76a66253 | 1782 | { |
22e0e173 AJ |
1783 | if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) || |
1784 | (int32_t)arg2 == 0) { | |
1785 | env->spr[SPR_MQ] = 0; | |
1786 | return INT32_MIN; | |
76a66253 | 1787 | } else { |
22e0e173 AJ |
1788 | env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2; |
1789 | return (int32_t)arg1 / (int32_t)arg2; | |
76a66253 | 1790 | } |
76a66253 JM |
1791 | } |
1792 | ||
22e0e173 | 1793 | target_ulong helper_divso (target_ulong arg1, target_ulong arg2) |
76a66253 | 1794 | { |
22e0e173 AJ |
1795 | if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) || |
1796 | (int32_t)arg2 == 0) { | |
3d7b417e | 1797 | env->xer |= (1 << XER_OV) | (1 << XER_SO); |
22e0e173 AJ |
1798 | env->spr[SPR_MQ] = 0; |
1799 | return INT32_MIN; | |
76a66253 | 1800 | } else { |
3d7b417e | 1801 | env->xer &= ~(1 << XER_OV); |
22e0e173 AJ |
1802 | env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2; |
1803 | return (int32_t)arg1 / (int32_t)arg2; | |
76a66253 JM |
1804 | } |
1805 | } | |
1806 | ||
1807 | #if !defined (CONFIG_USER_ONLY) | |
22e0e173 | 1808 | target_ulong helper_rac (target_ulong addr) |
76a66253 | 1809 | { |
76a66253 | 1810 | mmu_ctx_t ctx; |
faadf50e | 1811 | int nb_BATs; |
22e0e173 | 1812 | target_ulong ret = 0; |
76a66253 JM |
1813 | |
1814 | /* We don't have to generate many instances of this instruction, | |
1815 | * as rac is supervisor only. | |
1816 | */ | |
faadf50e JM |
1817 | /* XXX: FIX THIS: Pretend we have no BAT */ |
1818 | nb_BATs = env->nb_BATs; | |
1819 | env->nb_BATs = 0; | |
22e0e173 AJ |
1820 | if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0) |
1821 | ret = ctx.raddr; | |
faadf50e | 1822 | env->nb_BATs = nb_BATs; |
22e0e173 | 1823 | return ret; |
76a66253 JM |
1824 | } |
1825 | ||
d72a19f7 | 1826 | void helper_rfsvc (void) |
76a66253 | 1827 | { |
d72a19f7 | 1828 | do_rfi(env->lr, env->ctr, 0x0000FFFF, 0); |
76a66253 | 1829 | } |
76a66253 JM |
1830 | #endif |
1831 | ||
1832 | /*****************************************************************************/ | |
1833 | /* 602 specific instructions */ | |
1834 | /* mfrom is the most crazy instruction ever seen, imho ! */ | |
1835 | /* Real implementation uses a ROM table. Do the same */ | |
5e9ae189 AJ |
1836 | /* Extremly decomposed: |
1837 | * -arg / 256 | |
1838 | * return 256 * log10(10 + 1.0) + 0.5 | |
1839 | */ | |
db9a16a7 | 1840 | #if !defined (CONFIG_USER_ONLY) |
cf02a65c | 1841 | target_ulong helper_602_mfrom (target_ulong arg) |
76a66253 | 1842 | { |
cf02a65c | 1843 | if (likely(arg < 602)) { |
76a66253 | 1844 | #include "mfrom_table.c" |
45d827d2 | 1845 | return mfrom_ROM_table[arg]; |
76a66253 | 1846 | } else { |
cf02a65c | 1847 | return 0; |
76a66253 JM |
1848 | } |
1849 | } | |
db9a16a7 | 1850 | #endif |
76a66253 JM |
1851 | |
1852 | /*****************************************************************************/ | |
1853 | /* Embedded PowerPC specific helpers */ | |
76a66253 | 1854 | |
a750fc0b | 1855 | /* XXX: to be improved to check access rights when in user-mode */ |
06dca6a7 | 1856 | target_ulong helper_load_dcr (target_ulong dcrn) |
a750fc0b | 1857 | { |
06dca6a7 | 1858 | target_ulong val = 0; |
a750fc0b JM |
1859 | |
1860 | if (unlikely(env->dcr_env == NULL)) { | |
1861 | if (loglevel != 0) { | |
1862 | fprintf(logfile, "No DCR environment\n"); | |
1863 | } | |
e06fcd75 AJ |
1864 | helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1865 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); | |
06dca6a7 | 1866 | } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) { |
a750fc0b | 1867 | if (loglevel != 0) { |
45d827d2 | 1868 | fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn); |
a750fc0b | 1869 | } |
e06fcd75 AJ |
1870 | helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1871 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); | |
a750fc0b | 1872 | } |
06dca6a7 | 1873 | return val; |
a750fc0b JM |
1874 | } |
1875 | ||
06dca6a7 | 1876 | void helper_store_dcr (target_ulong dcrn, target_ulong val) |
a750fc0b JM |
1877 | { |
1878 | if (unlikely(env->dcr_env == NULL)) { | |
1879 | if (loglevel != 0) { | |
1880 | fprintf(logfile, "No DCR environment\n"); | |
1881 | } | |
e06fcd75 AJ |
1882 | helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1883 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); | |
06dca6a7 | 1884 | } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) { |
a750fc0b | 1885 | if (loglevel != 0) { |
45d827d2 | 1886 | fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn); |
a750fc0b | 1887 | } |
e06fcd75 AJ |
1888 | helper_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1889 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); | |
a750fc0b JM |
1890 | } |
1891 | } | |
1892 | ||
76a66253 | 1893 | #if !defined(CONFIG_USER_ONLY) |
d72a19f7 | 1894 | void helper_40x_rfci (void) |
76a66253 | 1895 | { |
d72a19f7 AJ |
1896 | do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3], |
1897 | ~((target_ulong)0xFFFF0000), 0); | |
a42bd6cc JM |
1898 | } |
1899 | ||
d72a19f7 | 1900 | void helper_rfci (void) |
a42bd6cc | 1901 | { |
d72a19f7 AJ |
1902 | do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1, |
1903 | ~((target_ulong)0x3FFF0000), 0); | |
a42bd6cc JM |
1904 | } |
1905 | ||
d72a19f7 | 1906 | void helper_rfdi (void) |
a42bd6cc | 1907 | { |
d72a19f7 AJ |
1908 | do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1, |
1909 | ~((target_ulong)0x3FFF0000), 0); | |
a42bd6cc JM |
1910 | } |
1911 | ||
d72a19f7 | 1912 | void helper_rfmci (void) |
a42bd6cc | 1913 | { |
d72a19f7 AJ |
1914 | do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1, |
1915 | ~((target_ulong)0x3FFF0000), 0); | |
76a66253 | 1916 | } |
76a66253 JM |
1917 | #endif |
1918 | ||
1919 | /* 440 specific */ | |
ef0d51af | 1920 | target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc) |
76a66253 JM |
1921 | { |
1922 | target_ulong mask; | |
1923 | int i; | |
1924 | ||
1925 | i = 1; | |
1926 | for (mask = 0xFF000000; mask != 0; mask = mask >> 8) { | |
ef0d51af AJ |
1927 | if ((high & mask) == 0) { |
1928 | if (update_Rc) { | |
1929 | env->crf[0] = 0x4; | |
1930 | } | |
76a66253 | 1931 | goto done; |
ef0d51af | 1932 | } |
76a66253 JM |
1933 | i++; |
1934 | } | |
1935 | for (mask = 0xFF000000; mask != 0; mask = mask >> 8) { | |
ef0d51af AJ |
1936 | if ((low & mask) == 0) { |
1937 | if (update_Rc) { | |
1938 | env->crf[0] = 0x8; | |
1939 | } | |
1940 | goto done; | |
1941 | } | |
76a66253 JM |
1942 | i++; |
1943 | } | |
ef0d51af AJ |
1944 | if (update_Rc) { |
1945 | env->crf[0] = 0x2; | |
1946 | } | |
76a66253 | 1947 | done: |
ef0d51af AJ |
1948 | env->xer = (env->xer & ~0x7F) | i; |
1949 | if (update_Rc) { | |
1950 | env->crf[0] |= xer_so; | |
1951 | } | |
1952 | return i; | |
fdabc366 FB |
1953 | } |
1954 | ||
1c97856d | 1955 | /*****************************************************************************/ |
0487d6a8 JM |
1956 | /* SPE extension helpers */ |
1957 | /* Use a table to make this quicker */ | |
1958 | static uint8_t hbrev[16] = { | |
1959 | 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, | |
1960 | 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF, | |
1961 | }; | |
1962 | ||
b068d6a7 | 1963 | static always_inline uint8_t byte_reverse (uint8_t val) |
0487d6a8 JM |
1964 | { |
1965 | return hbrev[val >> 4] | (hbrev[val & 0xF] << 4); | |
1966 | } | |
1967 | ||
b068d6a7 | 1968 | static always_inline uint32_t word_reverse (uint32_t val) |
0487d6a8 JM |
1969 | { |
1970 | return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) | | |
1971 | (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24); | |
1972 | } | |
1973 | ||
3cd7d1dd | 1974 | #define MASKBITS 16 // Random value - to be fixed (implementation dependant) |
57951c27 | 1975 | target_ulong helper_brinc (target_ulong arg1, target_ulong arg2) |
0487d6a8 JM |
1976 | { |
1977 | uint32_t a, b, d, mask; | |
1978 | ||
3cd7d1dd | 1979 | mask = UINT32_MAX >> (32 - MASKBITS); |
57951c27 AJ |
1980 | a = arg1 & mask; |
1981 | b = arg2 & mask; | |
3cd7d1dd | 1982 | d = word_reverse(1 + word_reverse(a | ~b)); |
57951c27 | 1983 | return (arg1 & ~mask) | (d & b); |
0487d6a8 JM |
1984 | } |
1985 | ||
57951c27 | 1986 | uint32_t helper_cntlsw32 (uint32_t val) |
0487d6a8 JM |
1987 | { |
1988 | if (val & 0x80000000) | |
603fccce | 1989 | return clz32(~val); |
0487d6a8 | 1990 | else |
603fccce | 1991 | return clz32(val); |
0487d6a8 JM |
1992 | } |
1993 | ||
57951c27 | 1994 | uint32_t helper_cntlzw32 (uint32_t val) |
0487d6a8 | 1995 | { |
603fccce | 1996 | return clz32(val); |
0487d6a8 JM |
1997 | } |
1998 | ||
1c97856d AJ |
1999 | /* Single-precision floating-point conversions */ |
2000 | static always_inline uint32_t efscfsi (uint32_t val) | |
0487d6a8 | 2001 | { |
0ca9d380 | 2002 | CPU_FloatU u; |
0487d6a8 JM |
2003 | |
2004 | u.f = int32_to_float32(val, &env->spe_status); | |
2005 | ||
0ca9d380 | 2006 | return u.l; |
0487d6a8 JM |
2007 | } |
2008 | ||
1c97856d | 2009 | static always_inline uint32_t efscfui (uint32_t val) |
0487d6a8 | 2010 | { |
0ca9d380 | 2011 | CPU_FloatU u; |
0487d6a8 JM |
2012 | |
2013 | u.f = uint32_to_float32(val, &env->spe_status); | |
2014 | ||
0ca9d380 | 2015 | return u.l; |
0487d6a8 JM |
2016 | } |
2017 | ||
1c97856d | 2018 | static always_inline int32_t efsctsi (uint32_t val) |
0487d6a8 | 2019 | { |
0ca9d380 | 2020 | CPU_FloatU u; |
0487d6a8 | 2021 | |
0ca9d380 | 2022 | u.l = val; |
0487d6a8 | 2023 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2024 | if (unlikely(float32_is_nan(u.f))) |
0487d6a8 JM |
2025 | return 0; |
2026 | ||
2027 | return float32_to_int32(u.f, &env->spe_status); | |
2028 | } | |
2029 | ||
1c97856d | 2030 | static always_inline uint32_t efsctui (uint32_t val) |
0487d6a8 | 2031 | { |
0ca9d380 | 2032 | CPU_FloatU u; |
0487d6a8 | 2033 | |
0ca9d380 | 2034 | u.l = val; |
0487d6a8 | 2035 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2036 | if (unlikely(float32_is_nan(u.f))) |
0487d6a8 JM |
2037 | return 0; |
2038 | ||
2039 | return float32_to_uint32(u.f, &env->spe_status); | |
2040 | } | |
2041 | ||
1c97856d | 2042 | static always_inline uint32_t efsctsiz (uint32_t val) |
0487d6a8 | 2043 | { |
0ca9d380 | 2044 | CPU_FloatU u; |
0487d6a8 | 2045 | |
0ca9d380 | 2046 | u.l = val; |
0487d6a8 | 2047 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2048 | if (unlikely(float32_is_nan(u.f))) |
0487d6a8 JM |
2049 | return 0; |
2050 | ||
2051 | return float32_to_int32_round_to_zero(u.f, &env->spe_status); | |
2052 | } | |
2053 | ||
1c97856d | 2054 | static always_inline uint32_t efsctuiz (uint32_t val) |
0487d6a8 | 2055 | { |
0ca9d380 | 2056 | CPU_FloatU u; |
0487d6a8 | 2057 | |
0ca9d380 | 2058 | u.l = val; |
0487d6a8 | 2059 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2060 | if (unlikely(float32_is_nan(u.f))) |
0487d6a8 JM |
2061 | return 0; |
2062 | ||
2063 | return float32_to_uint32_round_to_zero(u.f, &env->spe_status); | |
2064 | } | |
2065 | ||
1c97856d | 2066 | static always_inline uint32_t efscfsf (uint32_t val) |
0487d6a8 | 2067 | { |
0ca9d380 | 2068 | CPU_FloatU u; |
0487d6a8 JM |
2069 | float32 tmp; |
2070 | ||
2071 | u.f = int32_to_float32(val, &env->spe_status); | |
2072 | tmp = int64_to_float32(1ULL << 32, &env->spe_status); | |
2073 | u.f = float32_div(u.f, tmp, &env->spe_status); | |
2074 | ||
0ca9d380 | 2075 | return u.l; |
0487d6a8 JM |
2076 | } |
2077 | ||
1c97856d | 2078 | static always_inline uint32_t efscfuf (uint32_t val) |
0487d6a8 | 2079 | { |
0ca9d380 | 2080 | CPU_FloatU u; |
0487d6a8 JM |
2081 | float32 tmp; |
2082 | ||
2083 | u.f = uint32_to_float32(val, &env->spe_status); | |
2084 | tmp = uint64_to_float32(1ULL << 32, &env->spe_status); | |
2085 | u.f = float32_div(u.f, tmp, &env->spe_status); | |
2086 | ||
0ca9d380 | 2087 | return u.l; |
0487d6a8 JM |
2088 | } |
2089 | ||
1c97856d | 2090 | static always_inline uint32_t efsctsf (uint32_t val) |
0487d6a8 | 2091 | { |
0ca9d380 | 2092 | CPU_FloatU u; |
0487d6a8 JM |
2093 | float32 tmp; |
2094 | ||
0ca9d380 | 2095 | u.l = val; |
0487d6a8 | 2096 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2097 | if (unlikely(float32_is_nan(u.f))) |
0487d6a8 JM |
2098 | return 0; |
2099 | tmp = uint64_to_float32(1ULL << 32, &env->spe_status); | |
2100 | u.f = float32_mul(u.f, tmp, &env->spe_status); | |
2101 | ||
2102 | return float32_to_int32(u.f, &env->spe_status); | |
2103 | } | |
2104 | ||
1c97856d | 2105 | static always_inline uint32_t efsctuf (uint32_t val) |
0487d6a8 | 2106 | { |
0ca9d380 | 2107 | CPU_FloatU u; |
0487d6a8 JM |
2108 | float32 tmp; |
2109 | ||
0ca9d380 | 2110 | u.l = val; |
0487d6a8 | 2111 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2112 | if (unlikely(float32_is_nan(u.f))) |
0487d6a8 JM |
2113 | return 0; |
2114 | tmp = uint64_to_float32(1ULL << 32, &env->spe_status); | |
2115 | u.f = float32_mul(u.f, tmp, &env->spe_status); | |
2116 | ||
2117 | return float32_to_uint32(u.f, &env->spe_status); | |
2118 | } | |
2119 | ||
1c97856d AJ |
2120 | #define HELPER_SPE_SINGLE_CONV(name) \ |
2121 | uint32_t helper_e##name (uint32_t val) \ | |
2122 | { \ | |
2123 | return e##name(val); \ | |
2124 | } | |
2125 | /* efscfsi */ | |
2126 | HELPER_SPE_SINGLE_CONV(fscfsi); | |
2127 | /* efscfui */ | |
2128 | HELPER_SPE_SINGLE_CONV(fscfui); | |
2129 | /* efscfuf */ | |
2130 | HELPER_SPE_SINGLE_CONV(fscfuf); | |
2131 | /* efscfsf */ | |
2132 | HELPER_SPE_SINGLE_CONV(fscfsf); | |
2133 | /* efsctsi */ | |
2134 | HELPER_SPE_SINGLE_CONV(fsctsi); | |
2135 | /* efsctui */ | |
2136 | HELPER_SPE_SINGLE_CONV(fsctui); | |
2137 | /* efsctsiz */ | |
2138 | HELPER_SPE_SINGLE_CONV(fsctsiz); | |
2139 | /* efsctuiz */ | |
2140 | HELPER_SPE_SINGLE_CONV(fsctuiz); | |
2141 | /* efsctsf */ | |
2142 | HELPER_SPE_SINGLE_CONV(fsctsf); | |
2143 | /* efsctuf */ | |
2144 | HELPER_SPE_SINGLE_CONV(fsctuf); | |
2145 | ||
2146 | #define HELPER_SPE_VECTOR_CONV(name) \ | |
2147 | uint64_t helper_ev##name (uint64_t val) \ | |
2148 | { \ | |
2149 | return ((uint64_t)e##name(val >> 32) << 32) | \ | |
2150 | (uint64_t)e##name(val); \ | |
0487d6a8 | 2151 | } |
1c97856d AJ |
2152 | /* evfscfsi */ |
2153 | HELPER_SPE_VECTOR_CONV(fscfsi); | |
2154 | /* evfscfui */ | |
2155 | HELPER_SPE_VECTOR_CONV(fscfui); | |
2156 | /* evfscfuf */ | |
2157 | HELPER_SPE_VECTOR_CONV(fscfuf); | |
2158 | /* evfscfsf */ | |
2159 | HELPER_SPE_VECTOR_CONV(fscfsf); | |
2160 | /* evfsctsi */ | |
2161 | HELPER_SPE_VECTOR_CONV(fsctsi); | |
2162 | /* evfsctui */ | |
2163 | HELPER_SPE_VECTOR_CONV(fsctui); | |
2164 | /* evfsctsiz */ | |
2165 | HELPER_SPE_VECTOR_CONV(fsctsiz); | |
2166 | /* evfsctuiz */ | |
2167 | HELPER_SPE_VECTOR_CONV(fsctuiz); | |
2168 | /* evfsctsf */ | |
2169 | HELPER_SPE_VECTOR_CONV(fsctsf); | |
2170 | /* evfsctuf */ | |
2171 | HELPER_SPE_VECTOR_CONV(fsctuf); | |
0487d6a8 | 2172 | |
1c97856d AJ |
2173 | /* Single-precision floating-point arithmetic */ |
2174 | static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2) | |
0487d6a8 | 2175 | { |
1c97856d AJ |
2176 | CPU_FloatU u1, u2; |
2177 | u1.l = op1; | |
2178 | u2.l = op2; | |
2179 | u1.f = float32_add(u1.f, u2.f, &env->spe_status); | |
2180 | return u1.l; | |
0487d6a8 JM |
2181 | } |
2182 | ||
1c97856d | 2183 | static always_inline uint32_t efssub (uint32_t op1, uint32_t op2) |
0487d6a8 | 2184 | { |
1c97856d AJ |
2185 | CPU_FloatU u1, u2; |
2186 | u1.l = op1; | |
2187 | u2.l = op2; | |
2188 | u1.f = float32_sub(u1.f, u2.f, &env->spe_status); | |
2189 | return u1.l; | |
0487d6a8 JM |
2190 | } |
2191 | ||
1c97856d | 2192 | static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2) |
0487d6a8 | 2193 | { |
1c97856d AJ |
2194 | CPU_FloatU u1, u2; |
2195 | u1.l = op1; | |
2196 | u2.l = op2; | |
2197 | u1.f = float32_mul(u1.f, u2.f, &env->spe_status); | |
2198 | return u1.l; | |
0487d6a8 JM |
2199 | } |
2200 | ||
1c97856d | 2201 | static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2) |
0487d6a8 | 2202 | { |
1c97856d AJ |
2203 | CPU_FloatU u1, u2; |
2204 | u1.l = op1; | |
2205 | u2.l = op2; | |
2206 | u1.f = float32_div(u1.f, u2.f, &env->spe_status); | |
2207 | return u1.l; | |
0487d6a8 JM |
2208 | } |
2209 | ||
1c97856d AJ |
2210 | #define HELPER_SPE_SINGLE_ARITH(name) \ |
2211 | uint32_t helper_e##name (uint32_t op1, uint32_t op2) \ | |
2212 | { \ | |
2213 | return e##name(op1, op2); \ | |
2214 | } | |
2215 | /* efsadd */ | |
2216 | HELPER_SPE_SINGLE_ARITH(fsadd); | |
2217 | /* efssub */ | |
2218 | HELPER_SPE_SINGLE_ARITH(fssub); | |
2219 | /* efsmul */ | |
2220 | HELPER_SPE_SINGLE_ARITH(fsmul); | |
2221 | /* efsdiv */ | |
2222 | HELPER_SPE_SINGLE_ARITH(fsdiv); | |
2223 | ||
2224 | #define HELPER_SPE_VECTOR_ARITH(name) \ | |
2225 | uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \ | |
2226 | { \ | |
2227 | return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \ | |
2228 | (uint64_t)e##name(op1, op2); \ | |
2229 | } | |
2230 | /* evfsadd */ | |
2231 | HELPER_SPE_VECTOR_ARITH(fsadd); | |
2232 | /* evfssub */ | |
2233 | HELPER_SPE_VECTOR_ARITH(fssub); | |
2234 | /* evfsmul */ | |
2235 | HELPER_SPE_VECTOR_ARITH(fsmul); | |
2236 | /* evfsdiv */ | |
2237 | HELPER_SPE_VECTOR_ARITH(fsdiv); | |
2238 | ||
2239 | /* Single-precision floating-point comparisons */ | |
2240 | static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2) | |
0487d6a8 | 2241 | { |
1c97856d AJ |
2242 | CPU_FloatU u1, u2; |
2243 | u1.l = op1; | |
2244 | u2.l = op2; | |
2245 | return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0; | |
0487d6a8 JM |
2246 | } |
2247 | ||
1c97856d | 2248 | static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2) |
0487d6a8 | 2249 | { |
1c97856d AJ |
2250 | CPU_FloatU u1, u2; |
2251 | u1.l = op1; | |
2252 | u2.l = op2; | |
2253 | return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4; | |
0487d6a8 JM |
2254 | } |
2255 | ||
1c97856d | 2256 | static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2) |
0487d6a8 | 2257 | { |
1c97856d AJ |
2258 | CPU_FloatU u1, u2; |
2259 | u1.l = op1; | |
2260 | u2.l = op2; | |
2261 | return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0; | |
0487d6a8 JM |
2262 | } |
2263 | ||
1c97856d | 2264 | static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2) |
0487d6a8 JM |
2265 | { |
2266 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
1c97856d | 2267 | return efststlt(op1, op2); |
0487d6a8 JM |
2268 | } |
2269 | ||
1c97856d | 2270 | static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2) |
0487d6a8 JM |
2271 | { |
2272 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
1c97856d | 2273 | return efststgt(op1, op2); |
0487d6a8 JM |
2274 | } |
2275 | ||
1c97856d | 2276 | static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2) |
0487d6a8 JM |
2277 | { |
2278 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
1c97856d | 2279 | return efststeq(op1, op2); |
0487d6a8 JM |
2280 | } |
2281 | ||
1c97856d AJ |
2282 | #define HELPER_SINGLE_SPE_CMP(name) \ |
2283 | uint32_t helper_e##name (uint32_t op1, uint32_t op2) \ | |
2284 | { \ | |
2285 | return e##name(op1, op2) << 2; \ | |
2286 | } | |
2287 | /* efststlt */ | |
2288 | HELPER_SINGLE_SPE_CMP(fststlt); | |
2289 | /* efststgt */ | |
2290 | HELPER_SINGLE_SPE_CMP(fststgt); | |
2291 | /* efststeq */ | |
2292 | HELPER_SINGLE_SPE_CMP(fststeq); | |
2293 | /* efscmplt */ | |
2294 | HELPER_SINGLE_SPE_CMP(fscmplt); | |
2295 | /* efscmpgt */ | |
2296 | HELPER_SINGLE_SPE_CMP(fscmpgt); | |
2297 | /* efscmpeq */ | |
2298 | HELPER_SINGLE_SPE_CMP(fscmpeq); | |
2299 | ||
2300 | static always_inline uint32_t evcmp_merge (int t0, int t1) | |
0487d6a8 | 2301 | { |
1c97856d | 2302 | return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1); |
0487d6a8 JM |
2303 | } |
2304 | ||
1c97856d AJ |
2305 | #define HELPER_VECTOR_SPE_CMP(name) \ |
2306 | uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \ | |
2307 | { \ | |
2308 | return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \ | |
0487d6a8 | 2309 | } |
1c97856d AJ |
2310 | /* evfststlt */ |
2311 | HELPER_VECTOR_SPE_CMP(fststlt); | |
2312 | /* evfststgt */ | |
2313 | HELPER_VECTOR_SPE_CMP(fststgt); | |
2314 | /* evfststeq */ | |
2315 | HELPER_VECTOR_SPE_CMP(fststeq); | |
2316 | /* evfscmplt */ | |
2317 | HELPER_VECTOR_SPE_CMP(fscmplt); | |
2318 | /* evfscmpgt */ | |
2319 | HELPER_VECTOR_SPE_CMP(fscmpgt); | |
2320 | /* evfscmpeq */ | |
2321 | HELPER_VECTOR_SPE_CMP(fscmpeq); | |
0487d6a8 | 2322 | |
1c97856d AJ |
2323 | /* Double-precision floating-point conversion */ |
2324 | uint64_t helper_efdcfsi (uint32_t val) | |
0487d6a8 | 2325 | { |
1c97856d AJ |
2326 | CPU_DoubleU u; |
2327 | ||
2328 | u.d = int32_to_float64(val, &env->spe_status); | |
2329 | ||
2330 | return u.ll; | |
0487d6a8 JM |
2331 | } |
2332 | ||
1c97856d | 2333 | uint64_t helper_efdcfsid (uint64_t val) |
0487d6a8 | 2334 | { |
0ca9d380 | 2335 | CPU_DoubleU u; |
0487d6a8 | 2336 | |
0ca9d380 | 2337 | u.d = int64_to_float64(val, &env->spe_status); |
0487d6a8 | 2338 | |
0ca9d380 | 2339 | return u.ll; |
0487d6a8 JM |
2340 | } |
2341 | ||
1c97856d AJ |
2342 | uint64_t helper_efdcfui (uint32_t val) |
2343 | { | |
2344 | CPU_DoubleU u; | |
2345 | ||
2346 | u.d = uint32_to_float64(val, &env->spe_status); | |
2347 | ||
2348 | return u.ll; | |
2349 | } | |
2350 | ||
2351 | uint64_t helper_efdcfuid (uint64_t val) | |
0487d6a8 | 2352 | { |
0ca9d380 | 2353 | CPU_DoubleU u; |
0487d6a8 | 2354 | |
0ca9d380 | 2355 | u.d = uint64_to_float64(val, &env->spe_status); |
0487d6a8 | 2356 | |
0ca9d380 | 2357 | return u.ll; |
0487d6a8 JM |
2358 | } |
2359 | ||
1c97856d | 2360 | uint32_t helper_efdctsi (uint64_t val) |
0487d6a8 | 2361 | { |
0ca9d380 | 2362 | CPU_DoubleU u; |
0487d6a8 | 2363 | |
0ca9d380 | 2364 | u.ll = val; |
0487d6a8 | 2365 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2366 | if (unlikely(float64_is_nan(u.d))) |
0487d6a8 JM |
2367 | return 0; |
2368 | ||
1c97856d | 2369 | return float64_to_int32(u.d, &env->spe_status); |
0487d6a8 JM |
2370 | } |
2371 | ||
1c97856d | 2372 | uint32_t helper_efdctui (uint64_t val) |
0487d6a8 | 2373 | { |
0ca9d380 | 2374 | CPU_DoubleU u; |
0487d6a8 | 2375 | |
0ca9d380 | 2376 | u.ll = val; |
0487d6a8 | 2377 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2378 | if (unlikely(float64_is_nan(u.d))) |
0487d6a8 JM |
2379 | return 0; |
2380 | ||
1c97856d | 2381 | return float64_to_uint32(u.d, &env->spe_status); |
0487d6a8 JM |
2382 | } |
2383 | ||
1c97856d | 2384 | uint32_t helper_efdctsiz (uint64_t val) |
0487d6a8 | 2385 | { |
0ca9d380 | 2386 | CPU_DoubleU u; |
0487d6a8 | 2387 | |
0ca9d380 | 2388 | u.ll = val; |
0487d6a8 | 2389 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2390 | if (unlikely(float64_is_nan(u.d))) |
0487d6a8 JM |
2391 | return 0; |
2392 | ||
1c97856d | 2393 | return float64_to_int32_round_to_zero(u.d, &env->spe_status); |
0487d6a8 JM |
2394 | } |
2395 | ||
1c97856d | 2396 | uint64_t helper_efdctsidz (uint64_t val) |
0487d6a8 | 2397 | { |
0ca9d380 | 2398 | CPU_DoubleU u; |
0487d6a8 | 2399 | |
0ca9d380 | 2400 | u.ll = val; |
0487d6a8 | 2401 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2402 | if (unlikely(float64_is_nan(u.d))) |
0487d6a8 JM |
2403 | return 0; |
2404 | ||
1c97856d | 2405 | return float64_to_int64_round_to_zero(u.d, &env->spe_status); |
0487d6a8 JM |
2406 | } |
2407 | ||
1c97856d | 2408 | uint32_t helper_efdctuiz (uint64_t val) |
0487d6a8 | 2409 | { |
1c97856d | 2410 | CPU_DoubleU u; |
0487d6a8 | 2411 | |
1c97856d AJ |
2412 | u.ll = val; |
2413 | /* NaN are not treated the same way IEEE 754 does */ | |
a44d2ce1 | 2414 | if (unlikely(float64_is_nan(u.d))) |
1c97856d | 2415 | return 0; |
0487d6a8 | 2416 | |
1c97856d | 2417 | return float64_to_uint32_round_to_zero(u.d, &env->spe_status); |
0487d6a8 JM |
2418 | } |
2419 | ||
1c97856d | 2420 | uint64_t helper_efdctuidz (uint64_t val) |
0487d6a8 | 2421 | { |
1c97856d | 2422 | CPU_DoubleU u; |
0487d6a8 | 2423 | |
1c97856d AJ |
2424 | u.ll = val; |
2425 | /* NaN are not treated the same way IEEE 754 does */ | |
a44d2ce1 | 2426 | if (unlikely(float64_is_nan(u.d))) |
1c97856d | 2427 | return 0; |
0487d6a8 | 2428 | |
1c97856d | 2429 | return float64_to_uint64_round_to_zero(u.d, &env->spe_status); |
0487d6a8 JM |
2430 | } |
2431 | ||
1c97856d | 2432 | uint64_t helper_efdcfsf (uint32_t val) |
0487d6a8 | 2433 | { |
0ca9d380 | 2434 | CPU_DoubleU u; |
0487d6a8 JM |
2435 | float64 tmp; |
2436 | ||
0ca9d380 | 2437 | u.d = int32_to_float64(val, &env->spe_status); |
0487d6a8 | 2438 | tmp = int64_to_float64(1ULL << 32, &env->spe_status); |
0ca9d380 | 2439 | u.d = float64_div(u.d, tmp, &env->spe_status); |
0487d6a8 | 2440 | |
0ca9d380 | 2441 | return u.ll; |
0487d6a8 JM |
2442 | } |
2443 | ||
1c97856d | 2444 | uint64_t helper_efdcfuf (uint32_t val) |
0487d6a8 | 2445 | { |
0ca9d380 | 2446 | CPU_DoubleU u; |
0487d6a8 JM |
2447 | float64 tmp; |
2448 | ||
0ca9d380 | 2449 | u.d = uint32_to_float64(val, &env->spe_status); |
0487d6a8 | 2450 | tmp = int64_to_float64(1ULL << 32, &env->spe_status); |
0ca9d380 | 2451 | u.d = float64_div(u.d, tmp, &env->spe_status); |
0487d6a8 | 2452 | |
0ca9d380 | 2453 | return u.ll; |
0487d6a8 JM |
2454 | } |
2455 | ||
1c97856d | 2456 | uint32_t helper_efdctsf (uint64_t val) |
0487d6a8 | 2457 | { |
0ca9d380 | 2458 | CPU_DoubleU u; |
0487d6a8 JM |
2459 | float64 tmp; |
2460 | ||
0ca9d380 | 2461 | u.ll = val; |
0487d6a8 | 2462 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2463 | if (unlikely(float64_is_nan(u.d))) |
0487d6a8 JM |
2464 | return 0; |
2465 | tmp = uint64_to_float64(1ULL << 32, &env->spe_status); | |
0ca9d380 | 2466 | u.d = float64_mul(u.d, tmp, &env->spe_status); |
0487d6a8 | 2467 | |
0ca9d380 | 2468 | return float64_to_int32(u.d, &env->spe_status); |
0487d6a8 JM |
2469 | } |
2470 | ||
1c97856d | 2471 | uint32_t helper_efdctuf (uint64_t val) |
0487d6a8 | 2472 | { |
0ca9d380 | 2473 | CPU_DoubleU u; |
0487d6a8 JM |
2474 | float64 tmp; |
2475 | ||
0ca9d380 | 2476 | u.ll = val; |
0487d6a8 | 2477 | /* NaN are not treated the same way IEEE 754 does */ |
a44d2ce1 | 2478 | if (unlikely(float64_is_nan(u.d))) |
0487d6a8 JM |
2479 | return 0; |
2480 | tmp = uint64_to_float64(1ULL << 32, &env->spe_status); | |
0ca9d380 | 2481 | u.d = float64_mul(u.d, tmp, &env->spe_status); |
0487d6a8 | 2482 | |
0ca9d380 | 2483 | return float64_to_uint32(u.d, &env->spe_status); |
0487d6a8 JM |
2484 | } |
2485 | ||
1c97856d | 2486 | uint32_t helper_efscfd (uint64_t val) |
0487d6a8 | 2487 | { |
0ca9d380 AJ |
2488 | CPU_DoubleU u1; |
2489 | CPU_FloatU u2; | |
0487d6a8 | 2490 | |
0ca9d380 AJ |
2491 | u1.ll = val; |
2492 | u2.f = float64_to_float32(u1.d, &env->spe_status); | |
0487d6a8 | 2493 | |
0ca9d380 | 2494 | return u2.l; |
0487d6a8 JM |
2495 | } |
2496 | ||
1c97856d | 2497 | uint64_t helper_efdcfs (uint32_t val) |
0487d6a8 | 2498 | { |
0ca9d380 AJ |
2499 | CPU_DoubleU u2; |
2500 | CPU_FloatU u1; | |
0487d6a8 | 2501 | |
0ca9d380 AJ |
2502 | u1.l = val; |
2503 | u2.d = float32_to_float64(u1.f, &env->spe_status); | |
0487d6a8 | 2504 | |
0ca9d380 | 2505 | return u2.ll; |
0487d6a8 JM |
2506 | } |
2507 | ||
1c97856d AJ |
2508 | /* Double precision fixed-point arithmetic */ |
2509 | uint64_t helper_efdadd (uint64_t op1, uint64_t op2) | |
0487d6a8 | 2510 | { |
1c97856d AJ |
2511 | CPU_DoubleU u1, u2; |
2512 | u1.ll = op1; | |
2513 | u2.ll = op2; | |
2514 | u1.d = float64_add(u1.d, u2.d, &env->spe_status); | |
2515 | return u1.ll; | |
0487d6a8 JM |
2516 | } |
2517 | ||
1c97856d | 2518 | uint64_t helper_efdsub (uint64_t op1, uint64_t op2) |
0487d6a8 | 2519 | { |
1c97856d AJ |
2520 | CPU_DoubleU u1, u2; |
2521 | u1.ll = op1; | |
2522 | u2.ll = op2; | |
2523 | u1.d = float64_sub(u1.d, u2.d, &env->spe_status); | |
2524 | return u1.ll; | |
0487d6a8 JM |
2525 | } |
2526 | ||
1c97856d | 2527 | uint64_t helper_efdmul (uint64_t op1, uint64_t op2) |
0487d6a8 | 2528 | { |
1c97856d AJ |
2529 | CPU_DoubleU u1, u2; |
2530 | u1.ll = op1; | |
2531 | u2.ll = op2; | |
2532 | u1.d = float64_mul(u1.d, u2.d, &env->spe_status); | |
2533 | return u1.ll; | |
0487d6a8 JM |
2534 | } |
2535 | ||
1c97856d | 2536 | uint64_t helper_efddiv (uint64_t op1, uint64_t op2) |
0487d6a8 | 2537 | { |
1c97856d AJ |
2538 | CPU_DoubleU u1, u2; |
2539 | u1.ll = op1; | |
2540 | u2.ll = op2; | |
2541 | u1.d = float64_div(u1.d, u2.d, &env->spe_status); | |
2542 | return u1.ll; | |
0487d6a8 JM |
2543 | } |
2544 | ||
1c97856d AJ |
2545 | /* Double precision floating point helpers */ |
2546 | uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2) | |
0487d6a8 | 2547 | { |
1c97856d AJ |
2548 | CPU_DoubleU u1, u2; |
2549 | u1.ll = op1; | |
2550 | u2.ll = op2; | |
2551 | return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0; | |
0487d6a8 JM |
2552 | } |
2553 | ||
1c97856d | 2554 | uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2) |
0487d6a8 | 2555 | { |
1c97856d AJ |
2556 | CPU_DoubleU u1, u2; |
2557 | u1.ll = op1; | |
2558 | u2.ll = op2; | |
2559 | return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4; | |
0487d6a8 JM |
2560 | } |
2561 | ||
1c97856d | 2562 | uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2) |
0487d6a8 | 2563 | { |
1c97856d AJ |
2564 | CPU_DoubleU u1, u2; |
2565 | u1.ll = op1; | |
2566 | u2.ll = op2; | |
2567 | return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0; | |
0487d6a8 JM |
2568 | } |
2569 | ||
1c97856d | 2570 | uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2) |
0487d6a8 | 2571 | { |
1c97856d AJ |
2572 | /* XXX: TODO: test special values (NaN, infinites, ...) */ |
2573 | return helper_efdtstlt(op1, op2); | |
0487d6a8 JM |
2574 | } |
2575 | ||
1c97856d AJ |
2576 | uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2) |
2577 | { | |
2578 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
2579 | return helper_efdtstgt(op1, op2); | |
2580 | } | |
0487d6a8 | 2581 | |
1c97856d AJ |
2582 | uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2) |
2583 | { | |
2584 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
2585 | return helper_efdtsteq(op1, op2); | |
2586 | } | |
0487d6a8 | 2587 | |
fdabc366 FB |
2588 | /*****************************************************************************/ |
2589 | /* Softmmu support */ | |
2590 | #if !defined (CONFIG_USER_ONLY) | |
2591 | ||
2592 | #define MMUSUFFIX _mmu | |
fdabc366 FB |
2593 | |
2594 | #define SHIFT 0 | |
2595 | #include "softmmu_template.h" | |
2596 | ||
2597 | #define SHIFT 1 | |
2598 | #include "softmmu_template.h" | |
2599 | ||
2600 | #define SHIFT 2 | |
2601 | #include "softmmu_template.h" | |
2602 | ||
2603 | #define SHIFT 3 | |
2604 | #include "softmmu_template.h" | |
2605 | ||
2606 | /* try to fill the TLB and return an exception if error. If retaddr is | |
2607 | NULL, it means that the function was called in C code (i.e. not | |
2608 | from generated code or from helper.c) */ | |
2609 | /* XXX: fix it to restore all registers */ | |
6ebbf390 | 2610 | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
fdabc366 FB |
2611 | { |
2612 | TranslationBlock *tb; | |
2613 | CPUState *saved_env; | |
44f8625d | 2614 | unsigned long pc; |
fdabc366 FB |
2615 | int ret; |
2616 | ||
2617 | /* XXX: hack to restore env in all cases, even if not called from | |
2618 | generated code */ | |
2619 | saved_env = env; | |
2620 | env = cpu_single_env; | |
6ebbf390 | 2621 | ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); |
76a66253 | 2622 | if (unlikely(ret != 0)) { |
fdabc366 FB |
2623 | if (likely(retaddr)) { |
2624 | /* now we have a real cpu fault */ | |
44f8625d | 2625 | pc = (unsigned long)retaddr; |
fdabc366 FB |
2626 | tb = tb_find_pc(pc); |
2627 | if (likely(tb)) { | |
2628 | /* the PC is inside the translated code. It means that we have | |
2629 | a virtual CPU fault */ | |
2630 | cpu_restore_state(tb, env, pc, NULL); | |
76a66253 | 2631 | } |
fdabc366 | 2632 | } |
e06fcd75 | 2633 | helper_raise_exception_err(env->exception_index, env->error_code); |
fdabc366 FB |
2634 | } |
2635 | env = saved_env; | |
9a64fbe4 FB |
2636 | } |
2637 | ||
74d37793 AJ |
2638 | /* Segment registers load and store */ |
2639 | target_ulong helper_load_sr (target_ulong sr_num) | |
2640 | { | |
2641 | return env->sr[sr_num]; | |
2642 | } | |
2643 | ||
2644 | void helper_store_sr (target_ulong sr_num, target_ulong val) | |
2645 | { | |
45d827d2 | 2646 | ppc_store_sr(env, sr_num, val); |
74d37793 AJ |
2647 | } |
2648 | ||
2649 | /* SLB management */ | |
2650 | #if defined(TARGET_PPC64) | |
2651 | target_ulong helper_load_slb (target_ulong slb_nr) | |
2652 | { | |
2653 | return ppc_load_slb(env, slb_nr); | |
2654 | } | |
2655 | ||
2656 | void helper_store_slb (target_ulong slb_nr, target_ulong rs) | |
2657 | { | |
2658 | ppc_store_slb(env, slb_nr, rs); | |
2659 | } | |
2660 | ||
2661 | void helper_slbia (void) | |
2662 | { | |
2663 | ppc_slb_invalidate_all(env); | |
2664 | } | |
2665 | ||
2666 | void helper_slbie (target_ulong addr) | |
2667 | { | |
2668 | ppc_slb_invalidate_one(env, addr); | |
2669 | } | |
2670 | ||
2671 | #endif /* defined(TARGET_PPC64) */ | |
2672 | ||
2673 | /* TLB management */ | |
2674 | void helper_tlbia (void) | |
2675 | { | |
2676 | ppc_tlb_invalidate_all(env); | |
2677 | } | |
2678 | ||
2679 | void helper_tlbie (target_ulong addr) | |
2680 | { | |
2681 | ppc_tlb_invalidate_one(env, addr); | |
2682 | } | |
2683 | ||
76a66253 JM |
2684 | /* Software driven TLBs management */ |
2685 | /* PowerPC 602/603 software TLB load instructions helpers */ | |
74d37793 | 2686 | static void do_6xx_tlb (target_ulong new_EPN, int is_code) |
76a66253 JM |
2687 | { |
2688 | target_ulong RPN, CMP, EPN; | |
2689 | int way; | |
d9bce9d9 | 2690 | |
76a66253 JM |
2691 | RPN = env->spr[SPR_RPA]; |
2692 | if (is_code) { | |
2693 | CMP = env->spr[SPR_ICMP]; | |
2694 | EPN = env->spr[SPR_IMISS]; | |
2695 | } else { | |
2696 | CMP = env->spr[SPR_DCMP]; | |
2697 | EPN = env->spr[SPR_DMISS]; | |
2698 | } | |
2699 | way = (env->spr[SPR_SRR1] >> 17) & 1; | |
2700 | #if defined (DEBUG_SOFTWARE_TLB) | |
2701 | if (loglevel != 0) { | |
0e69805a | 2702 | fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX |
6b542af7 | 2703 | " PTE1 " ADDRX " way %d\n", |
0e69805a | 2704 | __func__, new_EPN, EPN, CMP, RPN, way); |
76a66253 JM |
2705 | } |
2706 | #endif | |
2707 | /* Store this TLB */ | |
0f3955e2 | 2708 | ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK), |
d9bce9d9 | 2709 | way, is_code, CMP, RPN); |
76a66253 JM |
2710 | } |
2711 | ||
74d37793 | 2712 | void helper_6xx_tlbd (target_ulong EPN) |
0f3955e2 | 2713 | { |
74d37793 | 2714 | do_6xx_tlb(EPN, 0); |
0f3955e2 AJ |
2715 | } |
2716 | ||
74d37793 | 2717 | void helper_6xx_tlbi (target_ulong EPN) |
0f3955e2 | 2718 | { |
74d37793 | 2719 | do_6xx_tlb(EPN, 1); |
0f3955e2 AJ |
2720 | } |
2721 | ||
2722 | /* PowerPC 74xx software TLB load instructions helpers */ | |
74d37793 | 2723 | static void do_74xx_tlb (target_ulong new_EPN, int is_code) |
7dbe11ac JM |
2724 | { |
2725 | target_ulong RPN, CMP, EPN; | |
2726 | int way; | |
2727 | ||
2728 | RPN = env->spr[SPR_PTELO]; | |
2729 | CMP = env->spr[SPR_PTEHI]; | |
2730 | EPN = env->spr[SPR_TLBMISS] & ~0x3; | |
2731 | way = env->spr[SPR_TLBMISS] & 0x3; | |
2732 | #if defined (DEBUG_SOFTWARE_TLB) | |
2733 | if (loglevel != 0) { | |
0e69805a | 2734 | fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX |
6b542af7 | 2735 | " PTE1 " ADDRX " way %d\n", |
0e69805a | 2736 | __func__, new_EPN, EPN, CMP, RPN, way); |
7dbe11ac JM |
2737 | } |
2738 | #endif | |
2739 | /* Store this TLB */ | |
0f3955e2 | 2740 | ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK), |
7dbe11ac JM |
2741 | way, is_code, CMP, RPN); |
2742 | } | |
2743 | ||
74d37793 | 2744 | void helper_74xx_tlbd (target_ulong EPN) |
0f3955e2 | 2745 | { |
74d37793 | 2746 | do_74xx_tlb(EPN, 0); |
0f3955e2 AJ |
2747 | } |
2748 | ||
74d37793 | 2749 | void helper_74xx_tlbi (target_ulong EPN) |
0f3955e2 | 2750 | { |
74d37793 | 2751 | do_74xx_tlb(EPN, 1); |
0f3955e2 AJ |
2752 | } |
2753 | ||
a11b8151 | 2754 | static always_inline target_ulong booke_tlb_to_page_size (int size) |
a8dea12f JM |
2755 | { |
2756 | return 1024 << (2 * size); | |
2757 | } | |
2758 | ||
a11b8151 | 2759 | static always_inline int booke_page_size_to_tlb (target_ulong page_size) |
a8dea12f JM |
2760 | { |
2761 | int size; | |
2762 | ||
2763 | switch (page_size) { | |
2764 | case 0x00000400UL: | |
2765 | size = 0x0; | |
2766 | break; | |
2767 | case 0x00001000UL: | |
2768 | size = 0x1; | |
2769 | break; | |
2770 | case 0x00004000UL: | |
2771 | size = 0x2; | |
2772 | break; | |
2773 | case 0x00010000UL: | |
2774 | size = 0x3; | |
2775 | break; | |
2776 | case 0x00040000UL: | |
2777 | size = 0x4; | |
2778 | break; | |
2779 | case 0x00100000UL: | |
2780 | size = 0x5; | |
2781 | break; | |
2782 | case 0x00400000UL: | |
2783 | size = 0x6; | |
2784 | break; | |
2785 | case 0x01000000UL: | |
2786 | size = 0x7; | |
2787 | break; | |
2788 | case 0x04000000UL: | |
2789 | size = 0x8; | |
2790 | break; | |
2791 | case 0x10000000UL: | |
2792 | size = 0x9; | |
2793 | break; | |
2794 | case 0x40000000UL: | |
2795 | size = 0xA; | |
2796 | break; | |
2797 | #if defined (TARGET_PPC64) | |
2798 | case 0x000100000000ULL: | |
2799 | size = 0xB; | |
2800 | break; | |
2801 | case 0x000400000000ULL: | |
2802 | size = 0xC; | |
2803 | break; | |
2804 | case 0x001000000000ULL: | |
2805 | size = 0xD; | |
2806 | break; | |
2807 | case 0x004000000000ULL: | |
2808 | size = 0xE; | |
2809 | break; | |
2810 | case 0x010000000000ULL: | |
2811 | size = 0xF; | |
2812 | break; | |
2813 | #endif | |
2814 | default: | |
2815 | size = -1; | |
2816 | break; | |
2817 | } | |
2818 | ||
2819 | return size; | |
2820 | } | |
2821 | ||
76a66253 | 2822 | /* Helpers for 4xx TLB management */ |
74d37793 | 2823 | target_ulong helper_4xx_tlbre_lo (target_ulong entry) |
76a66253 | 2824 | { |
a8dea12f | 2825 | ppcemb_tlb_t *tlb; |
74d37793 | 2826 | target_ulong ret; |
a8dea12f | 2827 | int size; |
76a66253 | 2828 | |
74d37793 AJ |
2829 | entry &= 0x3F; |
2830 | tlb = &env->tlb[entry].tlbe; | |
2831 | ret = tlb->EPN; | |
a8dea12f | 2832 | if (tlb->prot & PAGE_VALID) |
74d37793 | 2833 | ret |= 0x400; |
a8dea12f JM |
2834 | size = booke_page_size_to_tlb(tlb->size); |
2835 | if (size < 0 || size > 0x7) | |
2836 | size = 1; | |
74d37793 | 2837 | ret |= size << 7; |
a8dea12f | 2838 | env->spr[SPR_40x_PID] = tlb->PID; |
74d37793 | 2839 | return ret; |
76a66253 JM |
2840 | } |
2841 | ||
74d37793 | 2842 | target_ulong helper_4xx_tlbre_hi (target_ulong entry) |
76a66253 | 2843 | { |
a8dea12f | 2844 | ppcemb_tlb_t *tlb; |
74d37793 | 2845 | target_ulong ret; |
76a66253 | 2846 | |
74d37793 AJ |
2847 | entry &= 0x3F; |
2848 | tlb = &env->tlb[entry].tlbe; | |
2849 | ret = tlb->RPN; | |
a8dea12f | 2850 | if (tlb->prot & PAGE_EXEC) |
74d37793 | 2851 | ret |= 0x200; |
a8dea12f | 2852 | if (tlb->prot & PAGE_WRITE) |
74d37793 AJ |
2853 | ret |= 0x100; |
2854 | return ret; | |
76a66253 JM |
2855 | } |
2856 | ||
74d37793 | 2857 | void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val) |
76a66253 | 2858 | { |
a8dea12f | 2859 | ppcemb_tlb_t *tlb; |
76a66253 JM |
2860 | target_ulong page, end; |
2861 | ||
c55e9aef | 2862 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d | 2863 | if (loglevel != 0) { |
0e69805a | 2864 | fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val); |
c55e9aef JM |
2865 | } |
2866 | #endif | |
74d37793 AJ |
2867 | entry &= 0x3F; |
2868 | tlb = &env->tlb[entry].tlbe; | |
76a66253 JM |
2869 | /* Invalidate previous TLB (if it's valid) */ |
2870 | if (tlb->prot & PAGE_VALID) { | |
2871 | end = tlb->EPN + tlb->size; | |
c55e9aef | 2872 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d | 2873 | if (loglevel != 0) { |
c55e9aef | 2874 | fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX |
74d37793 | 2875 | " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end); |
c55e9aef JM |
2876 | } |
2877 | #endif | |
76a66253 JM |
2878 | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) |
2879 | tlb_flush_page(env, page); | |
2880 | } | |
74d37793 | 2881 | tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7); |
c294fc58 JM |
2882 | /* We cannot handle TLB size < TARGET_PAGE_SIZE. |
2883 | * If this ever occurs, one should use the ppcemb target instead | |
2884 | * of the ppc or ppc64 one | |
2885 | */ | |
74d37793 | 2886 | if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) { |
71c8b8fd JM |
2887 | cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u " |
2888 | "are not supported (%d)\n", | |
74d37793 | 2889 | tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7)); |
c294fc58 | 2890 | } |
74d37793 AJ |
2891 | tlb->EPN = val & ~(tlb->size - 1); |
2892 | if (val & 0x40) | |
76a66253 JM |
2893 | tlb->prot |= PAGE_VALID; |
2894 | else | |
2895 | tlb->prot &= ~PAGE_VALID; | |
74d37793 | 2896 | if (val & 0x20) { |
c294fc58 JM |
2897 | /* XXX: TO BE FIXED */ |
2898 | cpu_abort(env, "Little-endian TLB entries are not supported by now\n"); | |
2899 | } | |
c55e9aef | 2900 | tlb->PID = env->spr[SPR_40x_PID]; /* PID */ |
74d37793 | 2901 | tlb->attr = val & 0xFF; |
c55e9aef | 2902 | #if defined (DEBUG_SOFTWARE_TLB) |
c294fc58 JM |
2903 | if (loglevel != 0) { |
2904 | fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX | |
c55e9aef | 2905 | " size " ADDRX " prot %c%c%c%c PID %d\n", __func__, |
0e69805a | 2906 | (int)entry, tlb->RPN, tlb->EPN, tlb->size, |
c55e9aef JM |
2907 | tlb->prot & PAGE_READ ? 'r' : '-', |
2908 | tlb->prot & PAGE_WRITE ? 'w' : '-', | |
2909 | tlb->prot & PAGE_EXEC ? 'x' : '-', | |
2910 | tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); | |
2911 | } | |
2912 | #endif | |
76a66253 JM |
2913 | /* Invalidate new TLB (if valid) */ |
2914 | if (tlb->prot & PAGE_VALID) { | |
2915 | end = tlb->EPN + tlb->size; | |
c55e9aef | 2916 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d | 2917 | if (loglevel != 0) { |
c55e9aef | 2918 | fprintf(logfile, "%s: invalidate TLB %d start " ADDRX |
0e69805a | 2919 | " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end); |
c55e9aef JM |
2920 | } |
2921 | #endif | |
76a66253 JM |
2922 | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) |
2923 | tlb_flush_page(env, page); | |
2924 | } | |
76a66253 JM |
2925 | } |
2926 | ||
74d37793 | 2927 | void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val) |
76a66253 | 2928 | { |
a8dea12f | 2929 | ppcemb_tlb_t *tlb; |
76a66253 | 2930 | |
c55e9aef | 2931 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d | 2932 | if (loglevel != 0) { |
0e69805a | 2933 | fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val); |
c55e9aef JM |
2934 | } |
2935 | #endif | |
74d37793 AJ |
2936 | entry &= 0x3F; |
2937 | tlb = &env->tlb[entry].tlbe; | |
2938 | tlb->RPN = val & 0xFFFFFC00; | |
76a66253 | 2939 | tlb->prot = PAGE_READ; |
74d37793 | 2940 | if (val & 0x200) |
76a66253 | 2941 | tlb->prot |= PAGE_EXEC; |
74d37793 | 2942 | if (val & 0x100) |
76a66253 | 2943 | tlb->prot |= PAGE_WRITE; |
c55e9aef | 2944 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d JM |
2945 | if (loglevel != 0) { |
2946 | fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX | |
c55e9aef | 2947 | " size " ADDRX " prot %c%c%c%c PID %d\n", __func__, |
74d37793 | 2948 | (int)entry, tlb->RPN, tlb->EPN, tlb->size, |
c55e9aef JM |
2949 | tlb->prot & PAGE_READ ? 'r' : '-', |
2950 | tlb->prot & PAGE_WRITE ? 'w' : '-', | |
2951 | tlb->prot & PAGE_EXEC ? 'x' : '-', | |
2952 | tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); | |
2953 | } | |
2954 | #endif | |
76a66253 | 2955 | } |
5eb7995e | 2956 | |
74d37793 AJ |
2957 | target_ulong helper_4xx_tlbsx (target_ulong address) |
2958 | { | |
2959 | return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]); | |
2960 | } | |
2961 | ||
a4bb6c3e | 2962 | /* PowerPC 440 TLB management */ |
74d37793 | 2963 | void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value) |
5eb7995e JM |
2964 | { |
2965 | ppcemb_tlb_t *tlb; | |
a4bb6c3e | 2966 | target_ulong EPN, RPN, size; |
5eb7995e JM |
2967 | int do_flush_tlbs; |
2968 | ||
2969 | #if defined (DEBUG_SOFTWARE_TLB) | |
2970 | if (loglevel != 0) { | |
0e69805a AJ |
2971 | fprintf(logfile, "%s word %d entry %d value " ADDRX "\n", |
2972 | __func__, word, (int)entry, value); | |
5eb7995e JM |
2973 | } |
2974 | #endif | |
2975 | do_flush_tlbs = 0; | |
74d37793 AJ |
2976 | entry &= 0x3F; |
2977 | tlb = &env->tlb[entry].tlbe; | |
a4bb6c3e JM |
2978 | switch (word) { |
2979 | default: | |
2980 | /* Just here to please gcc */ | |
2981 | case 0: | |
74d37793 | 2982 | EPN = value & 0xFFFFFC00; |
a4bb6c3e | 2983 | if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN) |
5eb7995e | 2984 | do_flush_tlbs = 1; |
a4bb6c3e | 2985 | tlb->EPN = EPN; |
74d37793 | 2986 | size = booke_tlb_to_page_size((value >> 4) & 0xF); |
a4bb6c3e JM |
2987 | if ((tlb->prot & PAGE_VALID) && tlb->size < size) |
2988 | do_flush_tlbs = 1; | |
2989 | tlb->size = size; | |
2990 | tlb->attr &= ~0x1; | |
74d37793 AJ |
2991 | tlb->attr |= (value >> 8) & 1; |
2992 | if (value & 0x200) { | |
a4bb6c3e JM |
2993 | tlb->prot |= PAGE_VALID; |
2994 | } else { | |
2995 | if (tlb->prot & PAGE_VALID) { | |
2996 | tlb->prot &= ~PAGE_VALID; | |
2997 | do_flush_tlbs = 1; | |
2998 | } | |
5eb7995e | 2999 | } |
a4bb6c3e JM |
3000 | tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF; |
3001 | if (do_flush_tlbs) | |
3002 | tlb_flush(env, 1); | |
3003 | break; | |
3004 | case 1: | |
74d37793 | 3005 | RPN = value & 0xFFFFFC0F; |
a4bb6c3e JM |
3006 | if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) |
3007 | tlb_flush(env, 1); | |
3008 | tlb->RPN = RPN; | |
3009 | break; | |
3010 | case 2: | |
74d37793 | 3011 | tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00); |
a4bb6c3e | 3012 | tlb->prot = tlb->prot & PAGE_VALID; |
74d37793 | 3013 | if (value & 0x1) |
a4bb6c3e | 3014 | tlb->prot |= PAGE_READ << 4; |
74d37793 | 3015 | if (value & 0x2) |
a4bb6c3e | 3016 | tlb->prot |= PAGE_WRITE << 4; |
74d37793 | 3017 | if (value & 0x4) |
a4bb6c3e | 3018 | tlb->prot |= PAGE_EXEC << 4; |
74d37793 | 3019 | if (value & 0x8) |
a4bb6c3e | 3020 | tlb->prot |= PAGE_READ; |
74d37793 | 3021 | if (value & 0x10) |
a4bb6c3e | 3022 | tlb->prot |= PAGE_WRITE; |
74d37793 | 3023 | if (value & 0x20) |
a4bb6c3e JM |
3024 | tlb->prot |= PAGE_EXEC; |
3025 | break; | |
5eb7995e | 3026 | } |
5eb7995e JM |
3027 | } |
3028 | ||
74d37793 | 3029 | target_ulong helper_440_tlbre (uint32_t word, target_ulong entry) |
5eb7995e JM |
3030 | { |
3031 | ppcemb_tlb_t *tlb; | |
74d37793 | 3032 | target_ulong ret; |
5eb7995e JM |
3033 | int size; |
3034 | ||
74d37793 AJ |
3035 | entry &= 0x3F; |
3036 | tlb = &env->tlb[entry].tlbe; | |
a4bb6c3e JM |
3037 | switch (word) { |
3038 | default: | |
3039 | /* Just here to please gcc */ | |
3040 | case 0: | |
74d37793 | 3041 | ret = tlb->EPN; |
a4bb6c3e JM |
3042 | size = booke_page_size_to_tlb(tlb->size); |
3043 | if (size < 0 || size > 0xF) | |
3044 | size = 1; | |
74d37793 | 3045 | ret |= size << 4; |
a4bb6c3e | 3046 | if (tlb->attr & 0x1) |
74d37793 | 3047 | ret |= 0x100; |
a4bb6c3e | 3048 | if (tlb->prot & PAGE_VALID) |
74d37793 | 3049 | ret |= 0x200; |
a4bb6c3e JM |
3050 | env->spr[SPR_440_MMUCR] &= ~0x000000FF; |
3051 | env->spr[SPR_440_MMUCR] |= tlb->PID; | |
3052 | break; | |
3053 | case 1: | |
74d37793 | 3054 | ret = tlb->RPN; |
a4bb6c3e JM |
3055 | break; |
3056 | case 2: | |
74d37793 | 3057 | ret = tlb->attr & ~0x1; |
a4bb6c3e | 3058 | if (tlb->prot & (PAGE_READ << 4)) |
74d37793 | 3059 | ret |= 0x1; |
a4bb6c3e | 3060 | if (tlb->prot & (PAGE_WRITE << 4)) |
74d37793 | 3061 | ret |= 0x2; |
a4bb6c3e | 3062 | if (tlb->prot & (PAGE_EXEC << 4)) |
74d37793 | 3063 | ret |= 0x4; |
a4bb6c3e | 3064 | if (tlb->prot & PAGE_READ) |
74d37793 | 3065 | ret |= 0x8; |
a4bb6c3e | 3066 | if (tlb->prot & PAGE_WRITE) |
74d37793 | 3067 | ret |= 0x10; |
a4bb6c3e | 3068 | if (tlb->prot & PAGE_EXEC) |
74d37793 | 3069 | ret |= 0x20; |
a4bb6c3e JM |
3070 | break; |
3071 | } | |
74d37793 | 3072 | return ret; |
5eb7995e | 3073 | } |
74d37793 AJ |
3074 | |
3075 | target_ulong helper_440_tlbsx (target_ulong address) | |
3076 | { | |
3077 | return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF); | |
3078 | } | |
3079 | ||
76a66253 | 3080 | #endif /* !CONFIG_USER_ONLY */ |