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[qemu.git] / target-ppc / op_helper.c
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9a64fbe4 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
9a64fbe4 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
9a64fbe4
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
9a64fbe4
FB
20#include "exec.h"
21
0487d6a8
JM
22#include "op_helper.h"
23
9a64fbe4 24#define MEMSUFFIX _raw
0487d6a8 25#include "op_helper.h"
9a64fbe4 26#include "op_helper_mem.h"
a541f297 27#if !defined(CONFIG_USER_ONLY)
9a64fbe4 28#define MEMSUFFIX _user
0487d6a8 29#include "op_helper.h"
9a64fbe4
FB
30#include "op_helper_mem.h"
31#define MEMSUFFIX _kernel
0487d6a8 32#include "op_helper.h"
9a64fbe4
FB
33#include "op_helper_mem.h"
34#endif
35
fdabc366
FB
36//#define DEBUG_OP
37//#define DEBUG_EXCEPTIONS
76a66253 38//#define DEBUG_SOFTWARE_TLB
fdabc366
FB
39//#define FLUSH_ALL_TLBS
40
9a64fbe4
FB
41/*****************************************************************************/
42/* Exceptions processing helpers */
76a66253 43void cpu_loop_exit (void)
9a64fbe4 44{
9fddaa0c 45 longjmp(env->jmp_env, 1);
9a64fbe4
FB
46}
47
9fddaa0c 48void do_raise_exception_err (uint32_t exception, int error_code)
9a64fbe4 49{
9fddaa0c
FB
50#if 0
51 printf("Raise exception %3x code : %d\n", exception, error_code);
52#endif
53 switch (exception) {
9fddaa0c 54 case EXCP_PROGRAM:
76a66253
JM
55 if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
56 return;
57 break;
9fddaa0c 58 default:
76a66253
JM
59 break;
60 }
9fddaa0c
FB
61 env->exception_index = exception;
62 env->error_code = error_code;
76a66253
JM
63 cpu_loop_exit();
64}
9fddaa0c
FB
65
66void do_raise_exception (uint32_t exception)
67{
68 do_raise_exception_err(exception, 0);
9a64fbe4
FB
69}
70
76a66253
JM
71/*****************************************************************************/
72/* Registers load and stores */
73void do_load_cr (void)
74{
75 T0 = (env->crf[0] << 28) |
76 (env->crf[1] << 24) |
77 (env->crf[2] << 20) |
78 (env->crf[3] << 16) |
79 (env->crf[4] << 12) |
80 (env->crf[5] << 8) |
81 (env->crf[6] << 4) |
82 (env->crf[7] << 0);
83}
84
85void do_store_cr (uint32_t mask)
86{
87 int i, sh;
88
89 for (i = 0, sh = 7; i < 8; i++, sh --) {
90 if (mask & (1 << sh))
91 env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
92 }
93}
94
95void do_load_xer (void)
96{
97 T0 = (xer_so << XER_SO) |
98 (xer_ov << XER_OV) |
99 (xer_ca << XER_CA) |
100 (xer_bc << XER_BC) |
101 (xer_cmp << XER_CMP);
102}
103
104void do_store_xer (void)
105{
106 xer_so = (T0 >> XER_SO) & 0x01;
107 xer_ov = (T0 >> XER_OV) & 0x01;
108 xer_ca = (T0 >> XER_CA) & 0x01;
109 xer_cmp = (T0 >> XER_CMP) & 0xFF;
d9bce9d9 110 xer_bc = (T0 >> XER_BC) & 0x7F;
76a66253
JM
111}
112
113void do_load_fpscr (void)
114{
115 /* The 32 MSB of the target fpr are undefined.
116 * They'll be zero...
117 */
118 union {
119 float64 d;
120 struct {
121 uint32_t u[2];
122 } s;
123 } u;
124 int i;
125
d9bce9d9 126#if defined(WORDS_BIGENDIAN)
76a66253
JM
127#define WORD0 0
128#define WORD1 1
129#else
130#define WORD0 1
131#define WORD1 0
132#endif
133 u.s.u[WORD0] = 0;
134 u.s.u[WORD1] = 0;
135 for (i = 0; i < 8; i++)
136 u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
137 FT0 = u.d;
138}
139
140void do_store_fpscr (uint32_t mask)
141{
142 /*
143 * We use only the 32 LSB of the incoming fpr
144 */
145 union {
146 double d;
147 struct {
148 uint32_t u[2];
149 } s;
150 } u;
151 int i, rnd_type;
152
153 u.d = FT0;
154 if (mask & 0x80)
155 env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
156 for (i = 1; i < 7; i++) {
157 if (mask & (1 << (7 - i)))
158 env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
159 }
160 /* TODO: update FEX & VX */
161 /* Set rounding mode */
162 switch (env->fpscr[0] & 0x3) {
163 case 0:
164 /* Best approximation (round to nearest) */
165 rnd_type = float_round_nearest_even;
166 break;
167 case 1:
168 /* Smaller magnitude (round toward zero) */
169 rnd_type = float_round_to_zero;
170 break;
171 case 2:
172 /* Round toward +infinite */
173 rnd_type = float_round_up;
174 break;
175 default:
176 case 3:
177 /* Round toward -infinite */
178 rnd_type = float_round_down;
179 break;
180 }
181 set_float_rounding_mode(rnd_type, &env->fp_status);
182}
183
9a64fbe4 184/*****************************************************************************/
fdabc366 185/* Fixed point operations helpers */
d9bce9d9
JM
186#if defined(TARGET_PPC64)
187static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
fdabc366 188{
d9bce9d9
JM
189 *plow += a;
190 /* carry test */
191 if (*plow < a)
192 (*phigh)++;
193 *phigh += b;
fdabc366
FB
194}
195
d9bce9d9 196static void neg128 (uint64_t *plow, uint64_t *phigh)
fdabc366 197{
d9bce9d9
JM
198 *plow = ~ *plow;
199 *phigh = ~ *phigh;
200 add128(plow, phigh, 1, 0);
201}
202
203static void mul64 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
204{
205 uint32_t a0, a1, b0, b1;
206 uint64_t v;
207
208 a0 = a;
209 a1 = a >> 32;
210
211 b0 = b;
212 b1 = b >> 32;
213
214 v = (uint64_t)a0 * (uint64_t)b0;
215 *plow = v;
216 *phigh = 0;
217
218 v = (uint64_t)a0 * (uint64_t)b1;
219 add128(plow, phigh, v << 32, v >> 32);
220
221 v = (uint64_t)a1 * (uint64_t)b0;
222 add128(plow, phigh, v << 32, v >> 32);
223
224 v = (uint64_t)a1 * (uint64_t)b1;
225 *phigh += v;
226#if defined(DEBUG_MULDIV)
227 printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
228 a, b, *phigh, *plow);
229#endif
230}
231
232void do_mul64 (uint64_t *plow, uint64_t *phigh)
233{
234 mul64(plow, phigh, T0, T1);
235}
236
0487d6a8 237static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
d9bce9d9
JM
238{
239 int sa, sb;
240 sa = (a < 0);
241 if (sa)
242 a = -a;
243 sb = (b < 0);
244 if (sb)
245 b = -b;
246 mul64(plow, phigh, a, b);
247 if (sa ^ sb) {
248 neg128(plow, phigh);
fdabc366
FB
249 }
250}
251
d9bce9d9
JM
252void do_imul64 (uint64_t *plow, uint64_t *phigh)
253{
254 imul64(plow, phigh, T0, T1);
255}
256#endif
257
fdabc366
FB
258void do_adde (void)
259{
260 T2 = T0;
261 T0 += T1 + xer_ca;
d9bce9d9
JM
262 if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
263 (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
fdabc366
FB
264 xer_ca = 0;
265 } else {
266 xer_ca = 1;
267 }
268}
269
d9bce9d9
JM
270#if defined(TARGET_PPC64)
271void do_adde_64 (void)
fdabc366
FB
272{
273 T2 = T0;
274 T0 += T1 + xer_ca;
d9bce9d9
JM
275 if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
276 (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
fdabc366
FB
277 xer_ca = 0;
278 } else {
279 xer_ca = 1;
280 }
fdabc366 281}
d9bce9d9 282#endif
fdabc366
FB
283
284void do_addmeo (void)
285{
286 T1 = T0;
287 T0 += xer_ca + (-1);
d9bce9d9
JM
288 if (likely(!((uint32_t)T1 &
289 ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
fdabc366
FB
290 xer_ov = 0;
291 } else {
292 xer_so = 1;
293 xer_ov = 1;
294 }
295 if (likely(T1 != 0))
296 xer_ca = 1;
297}
298
d9bce9d9
JM
299#if defined(TARGET_PPC64)
300void do_addmeo_64 (void)
fdabc366
FB
301{
302 T1 = T0;
d9bce9d9
JM
303 T0 += xer_ca + (-1);
304 if (likely(!((uint64_t)T1 &
305 ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
fdabc366
FB
306 xer_ov = 0;
307 } else {
308 xer_so = 1;
309 xer_ov = 1;
310 }
d9bce9d9 311 if (likely(T1 != 0))
fdabc366 312 xer_ca = 1;
fdabc366 313}
d9bce9d9 314#endif
fdabc366
FB
315
316void do_divwo (void)
317{
d9bce9d9
JM
318 if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
319 (int32_t)T1 == 0))) {
fdabc366 320 xer_ov = 0;
d9bce9d9 321 T0 = (int32_t)T0 / (int32_t)T1;
fdabc366
FB
322 } else {
323 xer_so = 1;
324 xer_ov = 1;
325 T0 = (-1) * ((uint32_t)T0 >> 31);
326 }
327}
328
d9bce9d9
JM
329#if defined(TARGET_PPC64)
330void do_divdo (void)
331{
332 if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
333 (int64_t)T1 == 0))) {
334 xer_ov = 0;
335 T0 = (int64_t)T0 / (int64_t)T1;
336 } else {
337 xer_so = 1;
338 xer_ov = 1;
339 T0 = (-1ULL) * ((uint64_t)T0 >> 63);
340 }
341}
342#endif
343
fdabc366
FB
344void do_divwuo (void)
345{
346 if (likely((uint32_t)T1 != 0)) {
347 xer_ov = 0;
348 T0 = (uint32_t)T0 / (uint32_t)T1;
349 } else {
350 xer_so = 1;
351 xer_ov = 1;
352 T0 = 0;
353 }
354}
355
d9bce9d9
JM
356#if defined(TARGET_PPC64)
357void do_divduo (void)
358{
359 if (likely((uint64_t)T1 != 0)) {
360 xer_ov = 0;
361 T0 = (uint64_t)T0 / (uint64_t)T1;
362 } else {
363 xer_so = 1;
364 xer_ov = 1;
365 T0 = 0;
366 }
367}
368#endif
369
fdabc366
FB
370void do_mullwo (void)
371{
d9bce9d9 372 int64_t res = (int64_t)T0 * (int64_t)T1;
fdabc366
FB
373
374 if (likely((int32_t)res == res)) {
375 xer_ov = 0;
376 } else {
377 xer_ov = 1;
378 xer_so = 1;
379 }
380 T0 = (int32_t)res;
381}
382
d9bce9d9
JM
383#if defined(TARGET_PPC64)
384void do_mulldo (void)
fdabc366 385{
d9bce9d9
JM
386 int64_t th;
387 uint64_t tl;
388
389 do_imul64(&tl, &th);
390 if (likely(th == 0)) {
fdabc366 391 xer_ov = 0;
fdabc366
FB
392 } else {
393 xer_ov = 1;
394 xer_so = 1;
395 }
d9bce9d9 396 T0 = (int64_t)tl;
fdabc366 397}
d9bce9d9 398#endif
fdabc366 399
d9bce9d9 400void do_nego (void)
fdabc366 401{
d9bce9d9 402 if (likely((int32_t)T0 != INT32_MIN)) {
fdabc366 403 xer_ov = 0;
d9bce9d9 404 T0 = -(int32_t)T0;
fdabc366 405 } else {
fdabc366 406 xer_ov = 1;
d9bce9d9 407 xer_so = 1;
fdabc366 408 }
fdabc366
FB
409}
410
d9bce9d9
JM
411#if defined(TARGET_PPC64)
412void do_nego_64 (void)
fdabc366 413{
d9bce9d9 414 if (likely((int64_t)T0 != INT64_MIN)) {
fdabc366 415 xer_ov = 0;
d9bce9d9 416 T0 = -(int64_t)T0;
fdabc366 417 } else {
fdabc366 418 xer_ov = 1;
d9bce9d9 419 xer_so = 1;
fdabc366
FB
420 }
421}
d9bce9d9 422#endif
fdabc366
FB
423
424void do_subfe (void)
425{
426 T0 = T1 + ~T0 + xer_ca;
d9bce9d9
JM
427 if (likely((uint32_t)T0 >= (uint32_t)T1 &&
428 (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
fdabc366
FB
429 xer_ca = 0;
430 } else {
431 xer_ca = 1;
432 }
433}
434
d9bce9d9
JM
435#if defined(TARGET_PPC64)
436void do_subfe_64 (void)
fdabc366 437{
fdabc366 438 T0 = T1 + ~T0 + xer_ca;
d9bce9d9
JM
439 if (likely((uint64_t)T0 >= (uint64_t)T1 &&
440 (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
441 xer_ca = 0;
442 } else {
443 xer_ca = 1;
444 }
445}
446#endif
447
448void do_subfmeo (void)
449{
450 T1 = T0;
451 T0 = ~T0 + xer_ca - 1;
452 if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
453 (1UL << 31)))) {
fdabc366
FB
454 xer_ov = 0;
455 } else {
456 xer_so = 1;
457 xer_ov = 1;
458 }
d9bce9d9 459 if (likely((uint32_t)T1 != UINT32_MAX))
fdabc366 460 xer_ca = 1;
fdabc366
FB
461}
462
d9bce9d9
JM
463#if defined(TARGET_PPC64)
464void do_subfmeo_64 (void)
fdabc366
FB
465{
466 T1 = T0;
467 T0 = ~T0 + xer_ca - 1;
d9bce9d9
JM
468 if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
469 (1ULL << 63)))) {
fdabc366
FB
470 xer_ov = 0;
471 } else {
472 xer_so = 1;
473 xer_ov = 1;
474 }
d9bce9d9 475 if (likely((uint64_t)T1 != UINT64_MAX))
fdabc366
FB
476 xer_ca = 1;
477}
d9bce9d9 478#endif
fdabc366
FB
479
480void do_subfzeo (void)
481{
482 T1 = T0;
483 T0 = ~T0 + xer_ca;
d9bce9d9
JM
484 if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
485 ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
fdabc366
FB
486 xer_ov = 0;
487 } else {
488 xer_ov = 1;
489 xer_so = 1;
490 }
d9bce9d9 491 if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
fdabc366
FB
492 xer_ca = 0;
493 } else {
494 xer_ca = 1;
495 }
496}
497
d9bce9d9
JM
498#if defined(TARGET_PPC64)
499void do_subfzeo_64 (void)
500{
501 T1 = T0;
502 T0 = ~T0 + xer_ca;
503 if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
504 ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
505 xer_ov = 0;
506 } else {
507 xer_ov = 1;
508 xer_so = 1;
509 }
510 if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
511 xer_ca = 0;
512 } else {
513 xer_ca = 1;
514 }
515}
516#endif
517
9a64fbe4
FB
518/* shift right arithmetic helper */
519void do_sraw (void)
520{
521 int32_t ret;
522
fdabc366 523 if (likely(!(T1 & 0x20UL))) {
d9bce9d9 524 if (likely((uint32_t)T1 != 0)) {
fdabc366
FB
525 ret = (int32_t)T0 >> (T1 & 0x1fUL);
526 if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
76a66253 527 xer_ca = 0;
fdabc366 528 } else {
76a66253 529 xer_ca = 1;
fdabc366
FB
530 }
531 } else {
76a66253 532 ret = T0;
fdabc366
FB
533 xer_ca = 0;
534 }
535 } else {
536 ret = (-1) * ((uint32_t)T0 >> 31);
537 if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
538 xer_ca = 0;
76a66253 539 } else {
9a64fbe4 540 xer_ca = 1;
76a66253 541 }
fdabc366 542 }
4b3686fa 543 T0 = ret;
9a64fbe4
FB
544}
545
d9bce9d9
JM
546#if defined(TARGET_PPC64)
547void do_srad (void)
548{
549 int64_t ret;
550
551 if (likely(!(T1 & 0x40UL))) {
552 if (likely((uint64_t)T1 != 0)) {
553 ret = (int64_t)T0 >> (T1 & 0x3FUL);
554 if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
555 xer_ca = 0;
556 } else {
557 xer_ca = 1;
558 }
559 } else {
560 ret = T0;
561 xer_ca = 0;
562 }
563 } else {
564 ret = (-1) * ((uint64_t)T0 >> 63);
565 if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
566 xer_ca = 0;
567 } else {
568 xer_ca = 1;
569 }
570 }
571 T0 = ret;
572}
573#endif
574
575static inline int popcnt (uint32_t val)
576{
577 int i;
578
579 for (i = 0; val != 0;)
580 val = val ^ (val - 1);
581
582 return i;
583}
584
585void do_popcntb (void)
586{
587 uint32_t ret;
588 int i;
589
590 ret = 0;
591 for (i = 0; i < 32; i += 8)
592 ret |= popcnt((T0 >> i) & 0xFF) << i;
593 T0 = ret;
594}
595
596#if defined(TARGET_PPC64)
597void do_popcntb_64 (void)
598{
599 uint64_t ret;
600 int i;
601
602 ret = 0;
603 for (i = 0; i < 64; i += 8)
604 ret |= popcnt((T0 >> i) & 0xFF) << i;
605 T0 = ret;
606}
607#endif
608
fdabc366 609/*****************************************************************************/
9a64fbe4 610/* Floating point operations helpers */
9a64fbe4
FB
611void do_fctiw (void)
612{
613 union {
614 double d;
615 uint64_t i;
4ecc3190 616 } p;
9a64fbe4 617
e864cabd
JM
618 p.i = float64_to_int32(FT0, &env->fp_status);
619#if USE_PRECISE_EMULATION
4ecc3190 620 /* XXX: higher bits are not supposed to be significant.
76a66253 621 * to make tests easier, return the same as a real PowerPC 750 (aka G3)
4ecc3190 622 */
4ecc3190 623 p.i |= 0xFFF80000ULL << 32;
e864cabd 624#endif
4ecc3190 625 FT0 = p.d;
9a64fbe4
FB
626}
627
628void do_fctiwz (void)
629{
630 union {
631 double d;
632 uint64_t i;
4ecc3190
FB
633 } p;
634
e864cabd
JM
635 p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
636#if USE_PRECISE_EMULATION
4ecc3190 637 /* XXX: higher bits are not supposed to be significant.
d9bce9d9 638 * to make tests easier, return the same as a real PowerPC 750 (aka G3)
4ecc3190 639 */
4ecc3190 640 p.i |= 0xFFF80000ULL << 32;
e864cabd 641#endif
4ecc3190 642 FT0 = p.d;
9a64fbe4
FB
643}
644
e864cabd
JM
645#if USE_PRECISE_EMULATION
646void do_fmadd (void)
647{
648#ifdef FLOAT128
649 float128 ft0_128, ft1_128;
650
651 ft0_128 = float64_to_float128(FT0, &env->fp_status);
652 ft1_128 = float64_to_float128(FT1, &env->fp_status);
653 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
654 ft1_128 = float64_to_float128(FT2, &env->fp_status);
655 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
656 FT0 = float128_to_float64(ft0_128, &env->fp_status);
657#else
658 /* This is OK on x86 hosts */
659 FT0 = (FT0 * FT1) + FT2;
660#endif
661}
662
663void do_fmsub (void)
664{
665#ifdef FLOAT128
666 float128 ft0_128, ft1_128;
667
668 ft0_128 = float64_to_float128(FT0, &env->fp_status);
669 ft1_128 = float64_to_float128(FT1, &env->fp_status);
670 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
671 ft1_128 = float64_to_float128(FT2, &env->fp_status);
672 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
673 FT0 = float128_to_float64(ft0_128, &env->fp_status);
674#else
675 /* This is OK on x86 hosts */
676 FT0 = (FT0 * FT1) - FT2;
677#endif
678}
679#endif /* USE_PRECISE_EMULATION */
680
4b3686fa
FB
681void do_fnmadd (void)
682{
e864cabd
JM
683#if USE_PRECISE_EMULATION
684#ifdef FLOAT128
685 float128 ft0_128, ft1_128;
686
687 ft0_128 = float64_to_float128(FT0, &env->fp_status);
688 ft1_128 = float64_to_float128(FT1, &env->fp_status);
689 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
690 ft1_128 = float64_to_float128(FT2, &env->fp_status);
691 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
692 FT0 = float128_to_float64(ft0_128, &env->fp_status);
693#else
694 /* This is OK on x86 hosts */
695 FT0 = (FT0 * FT1) + FT2;
696#endif
697#else
fdabc366
FB
698 FT0 = float64_mul(FT0, FT1, &env->fp_status);
699 FT0 = float64_add(FT0, FT2, &env->fp_status);
e864cabd 700#endif
fdabc366
FB
701 if (likely(!isnan(FT0)))
702 FT0 = float64_chs(FT0);
4b3686fa
FB
703}
704
705void do_fnmsub (void)
706{
e864cabd
JM
707#if USE_PRECISE_EMULATION
708#ifdef FLOAT128
709 float128 ft0_128, ft1_128;
710
711 ft0_128 = float64_to_float128(FT0, &env->fp_status);
712 ft1_128 = float64_to_float128(FT1, &env->fp_status);
713 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
714 ft1_128 = float64_to_float128(FT2, &env->fp_status);
715 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
716 FT0 = float128_to_float64(ft0_128, &env->fp_status);
717#else
718 /* This is OK on x86 hosts */
719 FT0 = (FT0 * FT1) - FT2;
720#endif
721#else
fdabc366
FB
722 FT0 = float64_mul(FT0, FT1, &env->fp_status);
723 FT0 = float64_sub(FT0, FT2, &env->fp_status);
e864cabd 724#endif
fdabc366
FB
725 if (likely(!isnan(FT0)))
726 FT0 = float64_chs(FT0);
1ef59d0a
FB
727}
728
9a64fbe4
FB
729void do_fsqrt (void)
730{
fdabc366 731 FT0 = float64_sqrt(FT0, &env->fp_status);
9a64fbe4
FB
732}
733
9a64fbe4
FB
734void do_fres (void)
735{
4ecc3190
FB
736 union {
737 double d;
738 uint64_t i;
739 } p;
740
fdabc366 741 if (likely(isnormal(FT0))) {
e864cabd
JM
742#if USE_PRECISE_EMULATION
743 FT0 = float64_div(1.0, FT0, &env->fp_status);
744 FT0 = float64_to_float32(FT0, &env->fp_status);
745#else
76a66253 746 FT0 = float32_div(1.0, FT0, &env->fp_status);
e864cabd 747#endif
4ecc3190
FB
748 } else {
749 p.d = FT0;
750 if (p.i == 0x8000000000000000ULL) {
751 p.i = 0xFFF0000000000000ULL;
752 } else if (p.i == 0x0000000000000000ULL) {
753 p.i = 0x7FF0000000000000ULL;
754 } else if (isnan(FT0)) {
755 p.i = 0x7FF8000000000000ULL;
756 } else if (FT0 < 0.0) {
757 p.i = 0x8000000000000000ULL;
758 } else {
759 p.i = 0x0000000000000000ULL;
760 }
761 FT0 = p.d;
762 }
9a64fbe4
FB
763}
764
4ecc3190 765void do_frsqrte (void)
9a64fbe4 766{
4ecc3190
FB
767 union {
768 double d;
769 uint64_t i;
770 } p;
771
fdabc366
FB
772 if (likely(isnormal(FT0) && FT0 > 0.0)) {
773 FT0 = float64_sqrt(FT0, &env->fp_status);
774 FT0 = float32_div(1.0, FT0, &env->fp_status);
4ecc3190
FB
775 } else {
776 p.d = FT0;
777 if (p.i == 0x8000000000000000ULL) {
778 p.i = 0xFFF0000000000000ULL;
779 } else if (p.i == 0x0000000000000000ULL) {
780 p.i = 0x7FF0000000000000ULL;
781 } else if (isnan(FT0)) {
782 if (!(p.i & 0x0008000000000000ULL))
783 p.i |= 0x000FFFFFFFFFFFFFULL;
784 } else if (FT0 < 0) {
785 p.i = 0x7FF8000000000000ULL;
786 } else {
787 p.i = 0x0000000000000000ULL;
788 }
789 FT0 = p.d;
790 }
9a64fbe4
FB
791}
792
793void do_fsel (void)
794{
795 if (FT0 >= 0)
9a64fbe4 796 FT0 = FT1;
4ecc3190
FB
797 else
798 FT0 = FT2;
9a64fbe4
FB
799}
800
801void do_fcmpu (void)
802{
fdabc366
FB
803 if (likely(!isnan(FT0) && !isnan(FT1))) {
804 if (float64_lt(FT0, FT1, &env->fp_status)) {
805 T0 = 0x08UL;
806 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
807 T0 = 0x04UL;
808 } else {
809 T0 = 0x02UL;
810 }
811 } else {
812 T0 = 0x01UL;
9a64fbe4
FB
813 env->fpscr[4] |= 0x1;
814 env->fpscr[6] |= 0x1;
9a64fbe4 815 }
4b3686fa 816 env->fpscr[3] = T0;
9a64fbe4
FB
817}
818
819void do_fcmpo (void)
820{
821 env->fpscr[4] &= ~0x1;
fdabc366
FB
822 if (likely(!isnan(FT0) && !isnan(FT1))) {
823 if (float64_lt(FT0, FT1, &env->fp_status)) {
824 T0 = 0x08UL;
825 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
826 T0 = 0x04UL;
827 } else {
828 T0 = 0x02UL;
829 }
830 } else {
831 T0 = 0x01UL;
9a64fbe4 832 env->fpscr[4] |= 0x1;
76a66253
JM
833 if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) {
834 /* Quiet NaN case */
9a64fbe4
FB
835 env->fpscr[6] |= 0x1;
836 if (!(env->fpscr[1] & 0x8))
837 env->fpscr[4] |= 0x8;
838 } else {
839 env->fpscr[4] |= 0x8;
840 }
9a64fbe4 841 }
4b3686fa 842 env->fpscr[3] = T0;
9a64fbe4
FB
843}
844
76a66253 845#if !defined (CONFIG_USER_ONLY)
fdabc366 846void do_rfi (void)
9a64fbe4 847{
d9bce9d9
JM
848 env->nip = (target_ulong)(env->spr[SPR_SRR0] & ~0x00000003);
849 T0 = (target_ulong)(env->spr[SPR_SRR1] & ~0xFFFF0000UL);
fdabc366
FB
850 do_store_msr(env, T0);
851#if defined (DEBUG_OP)
852 dump_rfi();
853#endif
854 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
9a64fbe4 855}
d9bce9d9
JM
856
857#if defined(TARGET_PPC64)
858void do_rfi_32 (void)
859{
860 env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
861 T0 = (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL);
862 do_store_msr(env, T0);
863#if defined (DEBUG_OP)
864 dump_rfi();
865#endif
866 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
867}
868#endif
76a66253 869#endif
9a64fbe4 870
76a66253 871void do_tw (int flags)
9a64fbe4 872{
d9bce9d9
JM
873 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
874 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
875 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
876 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
877 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01)))))
fdabc366 878 do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
9a64fbe4
FB
879}
880
d9bce9d9
JM
881#if defined(TARGET_PPC64)
882void do_td (int flags)
883{
884 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
885 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
886 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
887 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
888 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
889 do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
890}
891#endif
892
fdabc366 893/*****************************************************************************/
76a66253
JM
894/* PowerPC 601 specific instructions (POWER bridge) */
895void do_POWER_abso (void)
9a64fbe4 896{
d9bce9d9 897 if ((uint32_t)T0 == INT32_MIN) {
76a66253
JM
898 T0 = INT32_MAX;
899 xer_ov = 1;
900 xer_so = 1;
901 } else {
902 T0 = -T0;
903 xer_ov = 0;
904 }
9a64fbe4
FB
905}
906
76a66253 907void do_POWER_clcs (void)
9a64fbe4 908{
76a66253
JM
909 switch (T0) {
910 case 0x0CUL:
911 /* Instruction cache line size */
912 T0 = ICACHE_LINE_SIZE;
913 break;
914 case 0x0DUL:
915 /* Data cache line size */
916 T0 = DCACHE_LINE_SIZE;
917 break;
918 case 0x0EUL:
919 /* Minimum cache line size */
920 T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
921 ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
922 break;
923 case 0x0FUL:
924 /* Maximum cache line size */
925 T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
926 ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
927 break;
928 default:
929 /* Undefined */
930 break;
931 }
932}
933
934void do_POWER_div (void)
935{
936 uint64_t tmp;
937
d9bce9d9 938 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM
939 T0 = (long)((-1) * (T0 >> 31));
940 env->spr[SPR_MQ] = 0;
941 } else {
942 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
943 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 944 T0 = tmp / (int32_t)T1;
76a66253
JM
945 }
946}
947
948void do_POWER_divo (void)
949{
950 int64_t tmp;
951
d9bce9d9 952 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM
953 T0 = (long)((-1) * (T0 >> 31));
954 env->spr[SPR_MQ] = 0;
955 xer_ov = 1;
956 xer_so = 1;
957 } else {
958 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
959 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 960 tmp /= (int32_t)T1;
76a66253
JM
961 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
962 xer_ov = 1;
963 xer_so = 1;
964 } else {
965 xer_ov = 0;
966 }
967 T0 = tmp;
968 }
969}
970
971void do_POWER_divs (void)
972{
d9bce9d9 973 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM
974 T0 = (long)((-1) * (T0 >> 31));
975 env->spr[SPR_MQ] = 0;
976 } else {
977 env->spr[SPR_MQ] = T0 % T1;
d9bce9d9 978 T0 = (int32_t)T0 / (int32_t)T1;
76a66253
JM
979 }
980}
981
982void do_POWER_divso (void)
983{
d9bce9d9 984 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM
985 T0 = (long)((-1) * (T0 >> 31));
986 env->spr[SPR_MQ] = 0;
987 xer_ov = 1;
988 xer_so = 1;
989 } else {
d9bce9d9
JM
990 T0 = (int32_t)T0 / (int32_t)T1;
991 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
76a66253
JM
992 xer_ov = 0;
993 }
994}
995
996void do_POWER_dozo (void)
997{
d9bce9d9 998 if ((int32_t)T1 > (int32_t)T0) {
76a66253
JM
999 T2 = T0;
1000 T0 = T1 - T0;
d9bce9d9
JM
1001 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1002 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
76a66253
JM
1003 xer_so = 1;
1004 xer_ov = 1;
1005 } else {
1006 xer_ov = 0;
1007 }
1008 } else {
1009 T0 = 0;
1010 xer_ov = 0;
1011 }
1012}
1013
1014void do_POWER_maskg (void)
1015{
1016 uint32_t ret;
1017
d9bce9d9 1018 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
76a66253
JM
1019 ret = -1;
1020 } else {
d9bce9d9
JM
1021 ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
1022 (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
1023 if ((uint32_t)T0 > (uint32_t)T1)
76a66253
JM
1024 ret = ~ret;
1025 }
1026 T0 = ret;
1027}
1028
1029void do_POWER_mulo (void)
1030{
1031 uint64_t tmp;
1032
1033 tmp = (uint64_t)T0 * (uint64_t)T1;
1034 env->spr[SPR_MQ] = tmp >> 32;
1035 T0 = tmp;
1036 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1037 xer_ov = 1;
1038 xer_so = 1;
1039 } else {
1040 xer_ov = 0;
1041 }
1042}
1043
1044#if !defined (CONFIG_USER_ONLY)
1045void do_POWER_rac (void)
1046{
1047#if 0
1048 mmu_ctx_t ctx;
1049
1050 /* We don't have to generate many instances of this instruction,
1051 * as rac is supervisor only.
1052 */
1053 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
1054 T0 = ctx.raddr;
1055#endif
1056}
1057
1058void do_POWER_rfsvc (void)
1059{
1060 env->nip = env->lr & ~0x00000003UL;
1061 T0 = env->ctr & 0x0000FFFFUL;
1062 do_store_msr(env, T0);
1063#if defined (DEBUG_OP)
1064 dump_rfi();
1065#endif
1066 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1067}
1068
1069/* PowerPC 601 BAT management helper */
1070void do_store_601_batu (int nr)
1071{
d9bce9d9 1072 do_store_ibatu(env, nr, (uint32_t)T0);
76a66253
JM
1073 env->DBAT[0][nr] = env->IBAT[0][nr];
1074 env->DBAT[1][nr] = env->IBAT[1][nr];
1075}
1076#endif
1077
1078/*****************************************************************************/
1079/* 602 specific instructions */
1080/* mfrom is the most crazy instruction ever seen, imho ! */
1081/* Real implementation uses a ROM table. Do the same */
1082#define USE_MFROM_ROM_TABLE
1083void do_op_602_mfrom (void)
1084{
1085 if (likely(T0 < 602)) {
d9bce9d9 1086#if defined(USE_MFROM_ROM_TABLE)
76a66253
JM
1087#include "mfrom_table.c"
1088 T0 = mfrom_ROM_table[T0];
fdabc366 1089#else
76a66253
JM
1090 double d;
1091 /* Extremly decomposed:
1092 * -T0 / 256
1093 * T0 = 256 * log10(10 + 1.0) + 0.5
1094 */
1095 d = T0;
1096 d = float64_div(d, 256, &env->fp_status);
1097 d = float64_chs(d);
1098 d = exp10(d); // XXX: use float emulation function
1099 d = float64_add(d, 1.0, &env->fp_status);
1100 d = log10(d); // XXX: use float emulation function
1101 d = float64_mul(d, 256, &env->fp_status);
1102 d = float64_add(d, 0.5, &env->fp_status);
1103 T0 = float64_round_to_int(d, &env->fp_status);
fdabc366 1104#endif
76a66253
JM
1105 } else {
1106 T0 = 0;
1107 }
1108}
1109
1110/*****************************************************************************/
1111/* Embedded PowerPC specific helpers */
1112void do_405_check_ov (void)
1113{
d9bce9d9
JM
1114 if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1115 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
76a66253
JM
1116 xer_ov = 0;
1117 } else {
1118 xer_ov = 1;
1119 xer_so = 1;
1120 }
1121}
1122
1123void do_405_check_sat (void)
1124{
d9bce9d9
JM
1125 if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1126 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
76a66253
JM
1127 /* Saturate result */
1128 if (T2 >> 31) {
1129 T0 = INT32_MIN;
1130 } else {
1131 T0 = INT32_MAX;
1132 }
1133 }
1134}
1135
1136#if !defined(CONFIG_USER_ONLY)
1137void do_4xx_rfci (void)
1138{
1139 env->nip = env->spr[SPR_40x_SRR2];
1140 T0 = env->spr[SPR_40x_SRR3] & ~0xFFFF0000;
1141 do_store_msr(env, T0);
1142#if defined (DEBUG_OP)
1143 dump_rfi();
1144#endif
1145 env->interrupt_request = CPU_INTERRUPT_EXITTB;
1146}
1147
1148void do_4xx_load_dcr (int dcrn)
1149{
1150 target_ulong val;
1151
1152 if (unlikely(env->dcr_read == NULL))
1153 do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1154 else if (unlikely((*env->dcr_read)(env->dcr_env, dcrn, &val) != 0))
1155 do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1156 else
1157 T0 = val;
1158}
1159
1160void do_4xx_store_dcr (int dcrn)
1161{
1162 if (unlikely(env->dcr_write == NULL))
1163 do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1164 else if (unlikely((*env->dcr_write)(env->dcr_env, dcrn, T0) != 0))
1165 do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1166}
1167
1168void do_load_403_pb (int num)
1169{
1170 T0 = env->pb[num];
1171}
1172
1173void do_store_403_pb (int num)
1174{
1175 if (likely(env->pb[num] != T0)) {
1176 env->pb[num] = T0;
1177 /* Should be optimized */
1178 tlb_flush(env, 1);
1179 }
1180}
1181#endif
1182
1183/* 440 specific */
1184void do_440_dlmzb (void)
1185{
1186 target_ulong mask;
1187 int i;
1188
1189 i = 1;
1190 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1191 if ((T0 & mask) == 0)
1192 goto done;
1193 i++;
1194 }
1195 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1196 if ((T1 & mask) == 0)
1197 break;
1198 i++;
1199 }
1200 done:
1201 T0 = i;
fdabc366
FB
1202}
1203
0487d6a8
JM
1204#if defined(TARGET_PPCSPE)
1205/* SPE extension helpers */
1206/* Use a table to make this quicker */
1207static uint8_t hbrev[16] = {
1208 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1209 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1210};
1211
1212static inline uint8_t byte_reverse (uint8_t val)
1213{
1214 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1215}
1216
1217static inline uint32_t word_reverse (uint32_t val)
1218{
1219 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1220 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1221}
1222
1223#define MASKBITS 16 // Random value - to be fixed
1224void do_brinc (void)
1225{
1226 uint32_t a, b, d, mask;
1227
1228 mask = (uint32_t)(-1UL) >> MASKBITS;
1229 b = T1_64 & mask;
1230 a = T0_64 & mask;
1231 d = word_reverse(1 + word_reverse(a | ~mask));
1232 T0_64 = (T0_64 & ~mask) | (d & mask);
1233}
1234
1235#define DO_SPE_OP2(name) \
1236void do_ev##name (void) \
1237{ \
1238 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1239 (uint64_t)_do_e##name(T0_64, T1_64); \
1240}
1241
1242#define DO_SPE_OP1(name) \
1243void do_ev##name (void) \
1244{ \
1245 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1246 (uint64_t)_do_e##name(T0_64); \
1247}
1248
1249/* Fixed-point vector arithmetic */
1250static inline uint32_t _do_eabs (uint32_t val)
1251{
1252 if (val != 0x80000000)
1253 val &= ~0x80000000;
1254
1255 return val;
1256}
1257
1258static inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1259{
1260 return op1 + op2;
1261}
1262
1263static inline int _do_ecntlsw (uint32_t val)
1264{
1265 if (val & 0x80000000)
1266 return _do_cntlzw(~val);
1267 else
1268 return _do_cntlzw(val);
1269}
1270
1271static inline int _do_ecntlzw (uint32_t val)
1272{
1273 return _do_cntlzw(val);
1274}
1275
1276static inline uint32_t _do_eneg (uint32_t val)
1277{
1278 if (val != 0x80000000)
1279 val ^= 0x80000000;
1280
1281 return val;
1282}
1283
1284static inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1285{
1286 return rotl32(op1, op2);
1287}
1288
1289static inline uint32_t _do_erndw (uint32_t val)
1290{
1291 return (val + 0x000080000000) & 0xFFFF0000;
1292}
1293
1294static inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1295{
1296 /* No error here: 6 bits are used */
1297 return op1 << (op2 & 0x3F);
1298}
1299
1300static inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1301{
1302 /* No error here: 6 bits are used */
1303 return op1 >> (op2 & 0x3F);
1304}
1305
1306static inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1307{
1308 /* No error here: 6 bits are used */
1309 return op1 >> (op2 & 0x3F);
1310}
1311
1312static inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1313{
1314 return op2 - op1;
1315}
1316
1317/* evabs */
1318DO_SPE_OP1(abs);
1319/* evaddw */
1320DO_SPE_OP2(addw);
1321/* evcntlsw */
1322DO_SPE_OP1(cntlsw);
1323/* evcntlzw */
1324DO_SPE_OP1(cntlzw);
1325/* evneg */
1326DO_SPE_OP1(neg);
1327/* evrlw */
1328DO_SPE_OP2(rlw);
1329/* evrnd */
1330DO_SPE_OP1(rndw);
1331/* evslw */
1332DO_SPE_OP2(slw);
1333/* evsrws */
1334DO_SPE_OP2(srws);
1335/* evsrwu */
1336DO_SPE_OP2(srwu);
1337/* evsubfw */
1338DO_SPE_OP2(subfw);
1339
1340/* evsel is a little bit more complicated... */
1341static inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
1342{
1343 if (n)
1344 return op1;
1345 else
1346 return op2;
1347}
1348
1349void do_evsel (void)
1350{
1351 T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1352 (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1353}
1354
1355/* Fixed-point vector comparisons */
1356#define DO_SPE_CMP(name) \
1357void do_ev##name (void) \
1358{ \
1359 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1360 T1_64 >> 32) << 32, \
1361 _do_e##name(T0_64, T1_64)); \
1362}
1363
1364static inline uint32_t _do_evcmp_merge (int t0, int t1)
1365{
1366 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1367}
1368static inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
1369{
1370 return op1 == op2 ? 1 : 0;
1371}
1372
1373static inline int _do_ecmpgts (int32_t op1, int32_t op2)
1374{
1375 return op1 > op2 ? 1 : 0;
1376}
1377
1378static inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
1379{
1380 return op1 > op2 ? 1 : 0;
1381}
1382
1383static inline int _do_ecmplts (int32_t op1, int32_t op2)
1384{
1385 return op1 < op2 ? 1 : 0;
1386}
1387
1388static inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
1389{
1390 return op1 < op2 ? 1 : 0;
1391}
1392
1393/* evcmpeq */
1394DO_SPE_CMP(cmpeq);
1395/* evcmpgts */
1396DO_SPE_CMP(cmpgts);
1397/* evcmpgtu */
1398DO_SPE_CMP(cmpgtu);
1399/* evcmplts */
1400DO_SPE_CMP(cmplts);
1401/* evcmpltu */
1402DO_SPE_CMP(cmpltu);
1403
1404/* Single precision floating-point conversions from/to integer */
1405static inline uint32_t _do_efscfsi (int32_t val)
1406{
1407 union {
1408 uint32_t u;
1409 float32 f;
1410 } u;
1411
1412 u.f = int32_to_float32(val, &env->spe_status);
1413
1414 return u.u;
1415}
1416
1417static inline uint32_t _do_efscfui (uint32_t val)
1418{
1419 union {
1420 uint32_t u;
1421 float32 f;
1422 } u;
1423
1424 u.f = uint32_to_float32(val, &env->spe_status);
1425
1426 return u.u;
1427}
1428
1429static inline int32_t _do_efsctsi (uint32_t val)
1430{
1431 union {
1432 int32_t u;
1433 float32 f;
1434 } u;
1435
1436 u.u = val;
1437 /* NaN are not treated the same way IEEE 754 does */
1438 if (unlikely(isnan(u.f)))
1439 return 0;
1440
1441 return float32_to_int32(u.f, &env->spe_status);
1442}
1443
1444static inline uint32_t _do_efsctui (uint32_t val)
1445{
1446 union {
1447 int32_t u;
1448 float32 f;
1449 } u;
1450
1451 u.u = val;
1452 /* NaN are not treated the same way IEEE 754 does */
1453 if (unlikely(isnan(u.f)))
1454 return 0;
1455
1456 return float32_to_uint32(u.f, &env->spe_status);
1457}
1458
1459static inline int32_t _do_efsctsiz (uint32_t val)
1460{
1461 union {
1462 int32_t u;
1463 float32 f;
1464 } u;
1465
1466 u.u = val;
1467 /* NaN are not treated the same way IEEE 754 does */
1468 if (unlikely(isnan(u.f)))
1469 return 0;
1470
1471 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1472}
1473
1474static inline uint32_t _do_efsctuiz (uint32_t val)
1475{
1476 union {
1477 int32_t u;
1478 float32 f;
1479 } u;
1480
1481 u.u = val;
1482 /* NaN are not treated the same way IEEE 754 does */
1483 if (unlikely(isnan(u.f)))
1484 return 0;
1485
1486 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1487}
1488
1489void do_efscfsi (void)
1490{
1491 T0_64 = _do_efscfsi(T0_64);
1492}
1493
1494void do_efscfui (void)
1495{
1496 T0_64 = _do_efscfui(T0_64);
1497}
1498
1499void do_efsctsi (void)
1500{
1501 T0_64 = _do_efsctsi(T0_64);
1502}
1503
1504void do_efsctui (void)
1505{
1506 T0_64 = _do_efsctui(T0_64);
1507}
1508
1509void do_efsctsiz (void)
1510{
1511 T0_64 = _do_efsctsiz(T0_64);
1512}
1513
1514void do_efsctuiz (void)
1515{
1516 T0_64 = _do_efsctuiz(T0_64);
1517}
1518
1519/* Single precision floating-point conversion to/from fractional */
1520static inline uint32_t _do_efscfsf (uint32_t val)
1521{
1522 union {
1523 uint32_t u;
1524 float32 f;
1525 } u;
1526 float32 tmp;
1527
1528 u.f = int32_to_float32(val, &env->spe_status);
1529 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1530 u.f = float32_div(u.f, tmp, &env->spe_status);
1531
1532 return u.u;
1533}
1534
1535static inline uint32_t _do_efscfuf (uint32_t val)
1536{
1537 union {
1538 uint32_t u;
1539 float32 f;
1540 } u;
1541 float32 tmp;
1542
1543 u.f = uint32_to_float32(val, &env->spe_status);
1544 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1545 u.f = float32_div(u.f, tmp, &env->spe_status);
1546
1547 return u.u;
1548}
1549
1550static inline int32_t _do_efsctsf (uint32_t val)
1551{
1552 union {
1553 int32_t u;
1554 float32 f;
1555 } u;
1556 float32 tmp;
1557
1558 u.u = val;
1559 /* NaN are not treated the same way IEEE 754 does */
1560 if (unlikely(isnan(u.f)))
1561 return 0;
1562 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1563 u.f = float32_mul(u.f, tmp, &env->spe_status);
1564
1565 return float32_to_int32(u.f, &env->spe_status);
1566}
1567
1568static inline uint32_t _do_efsctuf (uint32_t val)
1569{
1570 union {
1571 int32_t u;
1572 float32 f;
1573 } u;
1574 float32 tmp;
1575
1576 u.u = val;
1577 /* NaN are not treated the same way IEEE 754 does */
1578 if (unlikely(isnan(u.f)))
1579 return 0;
1580 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1581 u.f = float32_mul(u.f, tmp, &env->spe_status);
1582
1583 return float32_to_uint32(u.f, &env->spe_status);
1584}
1585
1586static inline int32_t _do_efsctsfz (uint32_t val)
1587{
1588 union {
1589 int32_t u;
1590 float32 f;
1591 } u;
1592 float32 tmp;
1593
1594 u.u = val;
1595 /* NaN are not treated the same way IEEE 754 does */
1596 if (unlikely(isnan(u.f)))
1597 return 0;
1598 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1599 u.f = float32_mul(u.f, tmp, &env->spe_status);
1600
1601 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1602}
1603
1604static inline uint32_t _do_efsctufz (uint32_t val)
1605{
1606 union {
1607 int32_t u;
1608 float32 f;
1609 } u;
1610 float32 tmp;
1611
1612 u.u = val;
1613 /* NaN are not treated the same way IEEE 754 does */
1614 if (unlikely(isnan(u.f)))
1615 return 0;
1616 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1617 u.f = float32_mul(u.f, tmp, &env->spe_status);
1618
1619 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1620}
1621
1622void do_efscfsf (void)
1623{
1624 T0_64 = _do_efscfsf(T0_64);
1625}
1626
1627void do_efscfuf (void)
1628{
1629 T0_64 = _do_efscfuf(T0_64);
1630}
1631
1632void do_efsctsf (void)
1633{
1634 T0_64 = _do_efsctsf(T0_64);
1635}
1636
1637void do_efsctuf (void)
1638{
1639 T0_64 = _do_efsctuf(T0_64);
1640}
1641
1642void do_efsctsfz (void)
1643{
1644 T0_64 = _do_efsctsfz(T0_64);
1645}
1646
1647void do_efsctufz (void)
1648{
1649 T0_64 = _do_efsctufz(T0_64);
1650}
1651
1652/* Double precision floating point helpers */
1653static inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
1654{
1655 /* XXX: TODO: test special values (NaN, infinites, ...) */
1656 return _do_efdtstlt(op1, op2);
1657}
1658
1659static inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
1660{
1661 /* XXX: TODO: test special values (NaN, infinites, ...) */
1662 return _do_efdtstgt(op1, op2);
1663}
1664
1665static inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
1666{
1667 /* XXX: TODO: test special values (NaN, infinites, ...) */
1668 return _do_efdtsteq(op1, op2);
1669}
1670
1671void do_efdcmplt (void)
1672{
1673 T0 = _do_efdcmplt(T0_64, T1_64);
1674}
1675
1676void do_efdcmpgt (void)
1677{
1678 T0 = _do_efdcmpgt(T0_64, T1_64);
1679}
1680
1681void do_efdcmpeq (void)
1682{
1683 T0 = _do_efdcmpeq(T0_64, T1_64);
1684}
1685
1686/* Double precision floating-point conversion to/from integer */
1687static inline uint64_t _do_efdcfsi (int64_t val)
1688{
1689 union {
1690 uint64_t u;
1691 float64 f;
1692 } u;
1693
1694 u.f = int64_to_float64(val, &env->spe_status);
1695
1696 return u.u;
1697}
1698
1699static inline uint64_t _do_efdcfui (uint64_t val)
1700{
1701 union {
1702 uint64_t u;
1703 float64 f;
1704 } u;
1705
1706 u.f = uint64_to_float64(val, &env->spe_status);
1707
1708 return u.u;
1709}
1710
1711static inline int64_t _do_efdctsi (uint64_t val)
1712{
1713 union {
1714 int64_t u;
1715 float64 f;
1716 } u;
1717
1718 u.u = val;
1719 /* NaN are not treated the same way IEEE 754 does */
1720 if (unlikely(isnan(u.f)))
1721 return 0;
1722
1723 return float64_to_int64(u.f, &env->spe_status);
1724}
1725
1726static inline uint64_t _do_efdctui (uint64_t val)
1727{
1728 union {
1729 int64_t u;
1730 float64 f;
1731 } u;
1732
1733 u.u = val;
1734 /* NaN are not treated the same way IEEE 754 does */
1735 if (unlikely(isnan(u.f)))
1736 return 0;
1737
1738 return float64_to_uint64(u.f, &env->spe_status);
1739}
1740
1741static inline int64_t _do_efdctsiz (uint64_t val)
1742{
1743 union {
1744 int64_t u;
1745 float64 f;
1746 } u;
1747
1748 u.u = val;
1749 /* NaN are not treated the same way IEEE 754 does */
1750 if (unlikely(isnan(u.f)))
1751 return 0;
1752
1753 return float64_to_int64_round_to_zero(u.f, &env->spe_status);
1754}
1755
1756static inline uint64_t _do_efdctuiz (uint64_t val)
1757{
1758 union {
1759 int64_t u;
1760 float64 f;
1761 } u;
1762
1763 u.u = val;
1764 /* NaN are not treated the same way IEEE 754 does */
1765 if (unlikely(isnan(u.f)))
1766 return 0;
1767
1768 return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
1769}
1770
1771void do_efdcfsi (void)
1772{
1773 T0_64 = _do_efdcfsi(T0_64);
1774}
1775
1776void do_efdcfui (void)
1777{
1778 T0_64 = _do_efdcfui(T0_64);
1779}
1780
1781void do_efdctsi (void)
1782{
1783 T0_64 = _do_efdctsi(T0_64);
1784}
1785
1786void do_efdctui (void)
1787{
1788 T0_64 = _do_efdctui(T0_64);
1789}
1790
1791void do_efdctsiz (void)
1792{
1793 T0_64 = _do_efdctsiz(T0_64);
1794}
1795
1796void do_efdctuiz (void)
1797{
1798 T0_64 = _do_efdctuiz(T0_64);
1799}
1800
1801/* Double precision floating-point conversion to/from fractional */
1802static inline uint64_t _do_efdcfsf (int64_t val)
1803{
1804 union {
1805 uint64_t u;
1806 float64 f;
1807 } u;
1808 float64 tmp;
1809
1810 u.f = int32_to_float64(val, &env->spe_status);
1811 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1812 u.f = float64_div(u.f, tmp, &env->spe_status);
1813
1814 return u.u;
1815}
1816
1817static inline uint64_t _do_efdcfuf (uint64_t val)
1818{
1819 union {
1820 uint64_t u;
1821 float64 f;
1822 } u;
1823 float64 tmp;
1824
1825 u.f = uint32_to_float64(val, &env->spe_status);
1826 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1827 u.f = float64_div(u.f, tmp, &env->spe_status);
1828
1829 return u.u;
1830}
1831
1832static inline int64_t _do_efdctsf (uint64_t val)
1833{
1834 union {
1835 int64_t u;
1836 float64 f;
1837 } u;
1838 float64 tmp;
1839
1840 u.u = val;
1841 /* NaN are not treated the same way IEEE 754 does */
1842 if (unlikely(isnan(u.f)))
1843 return 0;
1844 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1845 u.f = float64_mul(u.f, tmp, &env->spe_status);
1846
1847 return float64_to_int32(u.f, &env->spe_status);
1848}
1849
1850static inline uint64_t _do_efdctuf (uint64_t val)
1851{
1852 union {
1853 int64_t u;
1854 float64 f;
1855 } u;
1856 float64 tmp;
1857
1858 u.u = val;
1859 /* NaN are not treated the same way IEEE 754 does */
1860 if (unlikely(isnan(u.f)))
1861 return 0;
1862 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1863 u.f = float64_mul(u.f, tmp, &env->spe_status);
1864
1865 return float64_to_uint32(u.f, &env->spe_status);
1866}
1867
1868static inline int64_t _do_efdctsfz (uint64_t val)
1869{
1870 union {
1871 int64_t u;
1872 float64 f;
1873 } u;
1874 float64 tmp;
1875
1876 u.u = val;
1877 /* NaN are not treated the same way IEEE 754 does */
1878 if (unlikely(isnan(u.f)))
1879 return 0;
1880 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1881 u.f = float64_mul(u.f, tmp, &env->spe_status);
1882
1883 return float64_to_int32_round_to_zero(u.f, &env->spe_status);
1884}
1885
1886static inline uint64_t _do_efdctufz (uint64_t val)
1887{
1888 union {
1889 int64_t u;
1890 float64 f;
1891 } u;
1892 float64 tmp;
1893
1894 u.u = val;
1895 /* NaN are not treated the same way IEEE 754 does */
1896 if (unlikely(isnan(u.f)))
1897 return 0;
1898 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1899 u.f = float64_mul(u.f, tmp, &env->spe_status);
1900
1901 return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
1902}
1903
1904void do_efdcfsf (void)
1905{
1906 T0_64 = _do_efdcfsf(T0_64);
1907}
1908
1909void do_efdcfuf (void)
1910{
1911 T0_64 = _do_efdcfuf(T0_64);
1912}
1913
1914void do_efdctsf (void)
1915{
1916 T0_64 = _do_efdctsf(T0_64);
1917}
1918
1919void do_efdctuf (void)
1920{
1921 T0_64 = _do_efdctuf(T0_64);
1922}
1923
1924void do_efdctsfz (void)
1925{
1926 T0_64 = _do_efdctsfz(T0_64);
1927}
1928
1929void do_efdctufz (void)
1930{
1931 T0_64 = _do_efdctufz(T0_64);
1932}
1933
1934/* Floating point conversion between single and double precision */
1935static inline uint32_t _do_efscfd (uint64_t val)
1936{
1937 union {
1938 uint64_t u;
1939 float64 f;
1940 } u1;
1941 union {
1942 uint32_t u;
1943 float32 f;
1944 } u2;
1945
1946 u1.u = val;
1947 u2.f = float64_to_float32(u1.f, &env->spe_status);
1948
1949 return u2.u;
1950}
1951
1952static inline uint64_t _do_efdcfs (uint32_t val)
1953{
1954 union {
1955 uint64_t u;
1956 float64 f;
1957 } u2;
1958 union {
1959 uint32_t u;
1960 float32 f;
1961 } u1;
1962
1963 u1.u = val;
1964 u2.f = float32_to_float64(u1.f, &env->spe_status);
1965
1966 return u2.u;
1967}
1968
1969void do_efscfd (void)
1970{
1971 T0_64 = _do_efscfd(T0_64);
1972}
1973
1974void do_efdcfs (void)
1975{
1976 T0_64 = _do_efdcfs(T0_64);
1977}
1978
1979/* Single precision fixed-point vector arithmetic */
1980/* evfsabs */
1981DO_SPE_OP1(fsabs);
1982/* evfsnabs */
1983DO_SPE_OP1(fsnabs);
1984/* evfsneg */
1985DO_SPE_OP1(fsneg);
1986/* evfsadd */
1987DO_SPE_OP2(fsadd);
1988/* evfssub */
1989DO_SPE_OP2(fssub);
1990/* evfsmul */
1991DO_SPE_OP2(fsmul);
1992/* evfsdiv */
1993DO_SPE_OP2(fsdiv);
1994
1995/* Single-precision floating-point comparisons */
1996static inline int _do_efscmplt (uint32_t op1, uint32_t op2)
1997{
1998 /* XXX: TODO: test special values (NaN, infinites, ...) */
1999 return _do_efststlt(op1, op2);
2000}
2001
2002static inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2003{
2004 /* XXX: TODO: test special values (NaN, infinites, ...) */
2005 return _do_efststgt(op1, op2);
2006}
2007
2008static inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2009{
2010 /* XXX: TODO: test special values (NaN, infinites, ...) */
2011 return _do_efststeq(op1, op2);
2012}
2013
2014void do_efscmplt (void)
2015{
2016 T0 = _do_efscmplt(T0_64, T1_64);
2017}
2018
2019void do_efscmpgt (void)
2020{
2021 T0 = _do_efscmpgt(T0_64, T1_64);
2022}
2023
2024void do_efscmpeq (void)
2025{
2026 T0 = _do_efscmpeq(T0_64, T1_64);
2027}
2028
2029/* Single-precision floating-point vector comparisons */
2030/* evfscmplt */
2031DO_SPE_CMP(fscmplt);
2032/* evfscmpgt */
2033DO_SPE_CMP(fscmpgt);
2034/* evfscmpeq */
2035DO_SPE_CMP(fscmpeq);
2036/* evfststlt */
2037DO_SPE_CMP(fststlt);
2038/* evfststgt */
2039DO_SPE_CMP(fststgt);
2040/* evfststeq */
2041DO_SPE_CMP(fststeq);
2042
2043/* Single-precision floating-point vector conversions */
2044/* evfscfsi */
2045DO_SPE_OP1(fscfsi);
2046/* evfscfui */
2047DO_SPE_OP1(fscfui);
2048/* evfscfuf */
2049DO_SPE_OP1(fscfuf);
2050/* evfscfsf */
2051DO_SPE_OP1(fscfsf);
2052/* evfsctsi */
2053DO_SPE_OP1(fsctsi);
2054/* evfsctui */
2055DO_SPE_OP1(fsctui);
2056/* evfsctsiz */
2057DO_SPE_OP1(fsctsiz);
2058/* evfsctuiz */
2059DO_SPE_OP1(fsctuiz);
2060/* evfsctsf */
2061DO_SPE_OP1(fsctsf);
2062/* evfsctuf */
2063DO_SPE_OP1(fsctuf);
2064#endif /* defined(TARGET_PPCSPE) */
2065
fdabc366
FB
2066/*****************************************************************************/
2067/* Softmmu support */
2068#if !defined (CONFIG_USER_ONLY)
2069
2070#define MMUSUFFIX _mmu
2071#define GETPC() (__builtin_return_address(0))
2072
2073#define SHIFT 0
2074#include "softmmu_template.h"
2075
2076#define SHIFT 1
2077#include "softmmu_template.h"
2078
2079#define SHIFT 2
2080#include "softmmu_template.h"
2081
2082#define SHIFT 3
2083#include "softmmu_template.h"
2084
2085/* try to fill the TLB and return an exception if error. If retaddr is
2086 NULL, it means that the function was called in C code (i.e. not
2087 from generated code or from helper.c) */
2088/* XXX: fix it to restore all registers */
2089void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
2090{
2091 TranslationBlock *tb;
2092 CPUState *saved_env;
2093 target_phys_addr_t pc;
2094 int ret;
2095
2096 /* XXX: hack to restore env in all cases, even if not called from
2097 generated code */
2098 saved_env = env;
2099 env = cpu_single_env;
2100 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
76a66253 2101 if (unlikely(ret != 0)) {
fdabc366
FB
2102 if (likely(retaddr)) {
2103 /* now we have a real cpu fault */
2104 pc = (target_phys_addr_t)retaddr;
2105 tb = tb_find_pc(pc);
2106 if (likely(tb)) {
2107 /* the PC is inside the translated code. It means that we have
2108 a virtual CPU fault */
2109 cpu_restore_state(tb, env, pc, NULL);
76a66253 2110 }
fdabc366
FB
2111 }
2112 do_raise_exception_err(env->exception_index, env->error_code);
2113 }
2114 env = saved_env;
9a64fbe4
FB
2115}
2116
76a66253
JM
2117/* TLB invalidation helpers */
2118void do_tlbia (void)
2119{
2120 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2121 ppc6xx_tlb_invalidate_all(env);
2122 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2123 /* XXX: TODO */
2124#if 0
2125 ppcbooke_tlb_invalidate_all(env);
2126#endif
2127 } else {
2128 tlb_flush(env, 1);
2129 }
2130}
2131
2132void do_tlbie (void)
2133{
d9bce9d9 2134 T0 = (uint32_t)T0;
76a66253
JM
2135#if !defined(FLUSH_ALL_TLBS)
2136 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2137 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2138 if (env->id_tlbs == 1)
2139 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2140 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2141 /* XXX: TODO */
2142#if 0
2143 ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2144 env->spr[SPR_BOOKE_PID]);
2145#endif
2146 } else {
2147 /* tlbie invalidate TLBs for all segments */
2148 T0 &= TARGET_PAGE_MASK;
2149 T0 &= ~((target_ulong)-1 << 28);
2150 /* XXX: this case should be optimized,
2151 * giving a mask to tlb_flush_page
2152 */
2153 tlb_flush_page(env, T0 | (0x0 << 28));
2154 tlb_flush_page(env, T0 | (0x1 << 28));
2155 tlb_flush_page(env, T0 | (0x2 << 28));
2156 tlb_flush_page(env, T0 | (0x3 << 28));
2157 tlb_flush_page(env, T0 | (0x4 << 28));
2158 tlb_flush_page(env, T0 | (0x5 << 28));
2159 tlb_flush_page(env, T0 | (0x6 << 28));
2160 tlb_flush_page(env, T0 | (0x7 << 28));
2161 tlb_flush_page(env, T0 | (0x8 << 28));
2162 tlb_flush_page(env, T0 | (0x9 << 28));
2163 tlb_flush_page(env, T0 | (0xA << 28));
2164 tlb_flush_page(env, T0 | (0xB << 28));
2165 tlb_flush_page(env, T0 | (0xC << 28));
2166 tlb_flush_page(env, T0 | (0xD << 28));
2167 tlb_flush_page(env, T0 | (0xE << 28));
2168 tlb_flush_page(env, T0 | (0xF << 28));
2169 }
2170#else
2171 do_tlbia();
2172#endif
2173}
2174
d9bce9d9
JM
2175#if defined(TARGET_PPC64)
2176void do_tlbie_64 (void)
2177{
2178 T0 = (uint64_t)T0;
2179#if !defined(FLUSH_ALL_TLBS)
2180 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2181 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2182 if (env->id_tlbs == 1)
2183 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2184 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2185 /* XXX: TODO */
2186#if 0
2187 ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2188 env->spr[SPR_BOOKE_PID]);
2189#endif
2190 } else {
2191 /* tlbie invalidate TLBs for all segments
2192 * As we have 2^36 segments, invalidate all qemu TLBs
2193 */
2194#if 0
2195 T0 &= TARGET_PAGE_MASK;
2196 T0 &= ~((target_ulong)-1 << 28);
2197 /* XXX: this case should be optimized,
2198 * giving a mask to tlb_flush_page
2199 */
2200 tlb_flush_page(env, T0 | (0x0 << 28));
2201 tlb_flush_page(env, T0 | (0x1 << 28));
2202 tlb_flush_page(env, T0 | (0x2 << 28));
2203 tlb_flush_page(env, T0 | (0x3 << 28));
2204 tlb_flush_page(env, T0 | (0x4 << 28));
2205 tlb_flush_page(env, T0 | (0x5 << 28));
2206 tlb_flush_page(env, T0 | (0x6 << 28));
2207 tlb_flush_page(env, T0 | (0x7 << 28));
2208 tlb_flush_page(env, T0 | (0x8 << 28));
2209 tlb_flush_page(env, T0 | (0x9 << 28));
2210 tlb_flush_page(env, T0 | (0xA << 28));
2211 tlb_flush_page(env, T0 | (0xB << 28));
2212 tlb_flush_page(env, T0 | (0xC << 28));
2213 tlb_flush_page(env, T0 | (0xD << 28));
2214 tlb_flush_page(env, T0 | (0xE << 28));
2215 tlb_flush_page(env, T0 | (0xF << 28));
2216#else
2217 tlb_flush(env, 1);
2218#endif
2219 }
2220#else
2221 do_tlbia();
2222#endif
2223}
2224#endif
2225
2226#if defined(TARGET_PPC64)
2227void do_slbia (void)
2228{
2229 /* XXX: TODO */
2230 tlb_flush(env, 1);
2231}
2232
2233void do_slbie (void)
2234{
2235 /* XXX: TODO */
2236 tlb_flush(env, 1);
2237}
2238#endif
2239
76a66253
JM
2240/* Software driven TLBs management */
2241/* PowerPC 602/603 software TLB load instructions helpers */
2242void do_load_6xx_tlb (int is_code)
2243{
2244 target_ulong RPN, CMP, EPN;
2245 int way;
d9bce9d9 2246
76a66253
JM
2247 RPN = env->spr[SPR_RPA];
2248 if (is_code) {
2249 CMP = env->spr[SPR_ICMP];
2250 EPN = env->spr[SPR_IMISS];
2251 } else {
2252 CMP = env->spr[SPR_DCMP];
2253 EPN = env->spr[SPR_DMISS];
2254 }
2255 way = (env->spr[SPR_SRR1] >> 17) & 1;
2256#if defined (DEBUG_SOFTWARE_TLB)
2257 if (loglevel != 0) {
2258 fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2259 __func__, (unsigned long)T0, (unsigned long)EPN,
2260 (unsigned long)CMP, (unsigned long)RPN, way);
2261 }
2262#endif
2263 /* Store this TLB */
d9bce9d9
JM
2264 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2265 way, is_code, CMP, RPN);
76a66253
JM
2266}
2267
2268/* Helpers for 4xx TLB management */
2269void do_4xx_tlbia (void)
2270{
2271#if 0
2272 ppc_tlb_t *tlb;
2273 target_ulong page, end;
2274 int i;
2275
2276 for (i = 0; i < 64; i++) {
2277 tlb = &env->tlb[i];
2278 if (tlb->prot & PAGE_VALID) {
2279 end = tlb->EPN + tlb->size;
2280 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2281 tlb_flush_page(env, page);
2282 tlb->prot &= ~PAGE_VALID;
2283 }
2284 }
2285#endif
2286}
2287
2288void do_4xx_tlbre_lo (void)
2289{
2290#if 0
2291 ppc_tlb_t *tlb;
2292
2293 T0 &= 0x3F;
2294 tlb = &env->tlb[T0];
2295 T0 = tlb->stor[0];
2296 env->spr[SPR_40x_PID] = tlb->pid;
2297#endif
2298}
2299
2300void do_4xx_tlbre_hi (void)
2301{
2302#if 0
2303 ppc_tlb_t *tlb;
2304
2305 T0 &= 0x3F;
2306 tlb = &env->tlb[T0];
2307 T0 = tlb->stor[1];
2308#endif
2309}
2310
2311static int tlb_4xx_search (target_ulong virtual)
2312{
2313#if 0
2314 ppc_tlb_t *tlb;
2315 target_ulong base, mask;
2316 int i, ret;
2317
2318 /* Default return value is no match */
2319 ret = -1;
2320 for (i = 0; i < 64; i++) {
2321 tlb = &env->tlb[i];
2322 /* Check TLB validity */
2323 if (!(tlb->prot & PAGE_VALID))
2324 continue;
2325 /* Check TLB PID vs current PID */
2326 if (tlb->pid != 0 && tlb->pid != env->spr[SPR_40x_PID])
2327 continue;
2328 /* Check TLB address vs virtual address */
2329 base = tlb->EPN;
2330 mask = ~(tlb->size - 1);
2331 if ((base & mask) != (virtual & mask))
2332 continue;
2333 ret = i;
2334 break;
2335 }
2336
2337 return ret;
2338#else
2339 return -1;
2340#endif
2341}
2342
2343void do_4xx_tlbsx (void)
2344{
2345 T0 = tlb_4xx_search(T0);
2346}
2347
2348void do_4xx_tlbsx_ (void)
2349{
2350 int tmp = xer_ov;
2351
2352 T0 = tlb_4xx_search(T0);
2353 if (T0 != -1)
2354 tmp |= 0x02;
2355 env->crf[0] = tmp;
2356}
2357
2358void do_4xx_tlbwe_lo (void)
2359{
2360#if 0
2361 ppc_tlb_t *tlb;
2362 target_ulong page, end;
2363
2364 T0 &= 0x3F;
2365 tlb = &env->tlb[T0];
2366 /* Invalidate previous TLB (if it's valid) */
2367 if (tlb->prot & PAGE_VALID) {
2368 end = tlb->EPN + tlb->size;
2369 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2370 tlb_flush_page(env, page);
2371 }
2372 tlb->size = 1024 << (2 * ((T1 >> 7) & 0x7));
2373 tlb->EPN = (T1 & 0xFFFFFC00) & ~(tlb->size - 1);
2374 if (T1 & 0x400)
2375 tlb->prot |= PAGE_VALID;
2376 else
2377 tlb->prot &= ~PAGE_VALID;
2378 tlb->pid = env->spr[SPR_BOOKE_PID]; /* PID */
2379 /* Invalidate new TLB (if valid) */
2380 if (tlb->prot & PAGE_VALID) {
2381 end = tlb->EPN + tlb->size;
2382 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2383 tlb_flush_page(env, page);
2384 }
2385#endif
2386}
2387
2388void do_4xx_tlbwe_hi (void)
2389{
2390#if 0
2391 ppc_tlb_t *tlb;
2392
2393 T0 &= 0x3F;
2394 tlb = &env->tlb[T0];
2395 tlb->RPN = T1 & 0xFFFFFC00;
2396 tlb->prot = PAGE_READ;
2397 if (T1 & 0x200)
2398 tlb->prot |= PAGE_EXEC;
2399 if (T1 & 0x100)
2400 tlb->prot |= PAGE_WRITE;
2401#endif
2402}
2403#endif /* !CONFIG_USER_ONLY */