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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
79aceca5 | 21 | #include "cpu.h" |
76cad711 | 22 | #include "disas/disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
1de7afc9 | 24 | #include "qemu/host-utils.h" |
79aceca5 | 25 | |
a7812ae4 PB |
26 | #include "helper.h" |
27 | #define GEN_HELPER 1 | |
28 | #include "helper.h" | |
29 | ||
8cbcb4fa AJ |
30 | #define CPU_SINGLE_STEP 0x1 |
31 | #define CPU_BRANCH_STEP 0x2 | |
32 | #define GDBSTUB_SINGLE_STEP 0x4 | |
33 | ||
a750fc0b | 34 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 35 | //#define PPC_DEBUG_DISAS |
76a66253 | 36 | //#define DO_PPC_STATISTICS |
79aceca5 | 37 | |
d12d51d5 | 38 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 39 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
40 | #else |
41 | # define LOG_DISAS(...) do { } while (0) | |
42 | #endif | |
a750fc0b JM |
43 | /*****************************************************************************/ |
44 | /* Code translation helpers */ | |
c53be334 | 45 | |
f78fb44e | 46 | /* global register indexes */ |
a7812ae4 | 47 | static TCGv_ptr cpu_env; |
1d542695 | 48 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
f78fb44e | 49 | #if !defined(TARGET_PPC64) |
1d542695 | 50 | + 10*4 + 22*5 /* SPE GPRh */ |
f78fb44e | 51 | #endif |
a5e26afa | 52 | + 10*4 + 22*5 /* FPR */ |
47e4661c AJ |
53 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
54 | + 8*5 /* CRF */]; | |
f78fb44e AJ |
55 | static TCGv cpu_gpr[32]; |
56 | #if !defined(TARGET_PPC64) | |
57 | static TCGv cpu_gprh[32]; | |
58 | #endif | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fpr[32]; |
60 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
61 | static TCGv_i32 cpu_crf[8]; | |
bd568f18 | 62 | static TCGv cpu_nip; |
6527f6ea | 63 | static TCGv cpu_msr; |
cfdcd37a AJ |
64 | static TCGv cpu_ctr; |
65 | static TCGv cpu_lr; | |
697ab892 DG |
66 | #if defined(TARGET_PPC64) |
67 | static TCGv cpu_cfar; | |
68 | #endif | |
da91a00f | 69 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 70 | static TCGv cpu_reserve; |
30304420 | 71 | static TCGv cpu_fpscr; |
a7859e89 | 72 | static TCGv_i32 cpu_access_type; |
f78fb44e | 73 | |
022c62cb | 74 | #include "exec/gen-icount.h" |
2e70f6ef PB |
75 | |
76 | void ppc_translate_init(void) | |
77 | { | |
f78fb44e AJ |
78 | int i; |
79 | char* p; | |
2dc766da | 80 | size_t cpu_reg_names_size; |
b2437bf2 | 81 | static int done_init = 0; |
f78fb44e | 82 | |
2e70f6ef PB |
83 | if (done_init) |
84 | return; | |
f78fb44e | 85 | |
a7812ae4 | 86 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 87 | |
f78fb44e | 88 | p = cpu_reg_names; |
2dc766da | 89 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
90 | |
91 | for (i = 0; i < 8; i++) { | |
2dc766da | 92 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 | 93 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 94 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 95 | p += 5; |
2dc766da | 96 | cpu_reg_names_size -= 5; |
47e4661c AJ |
97 | } |
98 | ||
f78fb44e | 99 | for (i = 0; i < 32; i++) { |
2dc766da | 100 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 101 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 102 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 103 | p += (i < 10) ? 3 : 4; |
2dc766da | 104 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
f78fb44e | 105 | #if !defined(TARGET_PPC64) |
2dc766da | 106 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
a7812ae4 | 107 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 108 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 109 | p += (i < 10) ? 4 : 5; |
2dc766da | 110 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 111 | #endif |
1d542695 | 112 | |
2dc766da | 113 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 | 114 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 115 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 116 | p += (i < 10) ? 4 : 5; |
2dc766da | 117 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 118 | |
2dc766da | 119 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 120 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 121 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 122 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 123 | #else |
a7812ae4 | 124 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 125 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 126 | #endif |
1d542695 | 127 | p += (i < 10) ? 6 : 7; |
2dc766da | 128 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 129 | |
2dc766da | 130 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 131 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 132 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 133 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 134 | #else |
a7812ae4 | 135 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 136 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 137 | #endif |
1d542695 | 138 | p += (i < 10) ? 6 : 7; |
2dc766da | 139 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
f78fb44e | 140 | } |
f10dc08e | 141 | |
a7812ae4 | 142 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 143 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 144 | |
6527f6ea | 145 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 146 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 147 | |
a7812ae4 | 148 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 149 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 150 | |
a7812ae4 | 151 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 152 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 153 | |
697ab892 DG |
154 | #if defined(TARGET_PPC64) |
155 | cpu_cfar = tcg_global_mem_new(TCG_AREG0, | |
1328c2bf | 156 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
157 | #endif |
158 | ||
a7812ae4 | 159 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 160 | offsetof(CPUPPCState, xer), "xer"); |
da91a00f RH |
161 | cpu_so = tcg_global_mem_new(TCG_AREG0, |
162 | offsetof(CPUPPCState, so), "SO"); | |
163 | cpu_ov = tcg_global_mem_new(TCG_AREG0, | |
164 | offsetof(CPUPPCState, ov), "OV"); | |
165 | cpu_ca = tcg_global_mem_new(TCG_AREG0, | |
166 | offsetof(CPUPPCState, ca), "CA"); | |
3d7b417e | 167 | |
cf360a32 | 168 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 169 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 170 | "reserve_addr"); |
cf360a32 | 171 | |
30304420 DG |
172 | cpu_fpscr = tcg_global_mem_new(TCG_AREG0, |
173 | offsetof(CPUPPCState, fpscr), "fpscr"); | |
e1571908 | 174 | |
a7859e89 | 175 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 176 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 177 | |
f10dc08e | 178 | /* register helpers */ |
a7812ae4 | 179 | #define GEN_HELPER 2 |
f10dc08e AJ |
180 | #include "helper.h" |
181 | ||
2e70f6ef PB |
182 | done_init = 1; |
183 | } | |
184 | ||
79aceca5 FB |
185 | /* internal defines */ |
186 | typedef struct DisasContext { | |
187 | struct TranslationBlock *tb; | |
0fa85d43 | 188 | target_ulong nip; |
79aceca5 | 189 | uint32_t opcode; |
9a64fbe4 | 190 | uint32_t exception; |
3cc62370 FB |
191 | /* Routine used to access memory */ |
192 | int mem_idx; | |
76db3ba4 | 193 | int access_type; |
3cc62370 | 194 | /* Translation flags */ |
76db3ba4 | 195 | int le_mode; |
d9bce9d9 JM |
196 | #if defined(TARGET_PPC64) |
197 | int sf_mode; | |
697ab892 | 198 | int has_cfar; |
9a64fbe4 | 199 | #endif |
3cc62370 | 200 | int fpu_enabled; |
a9d9eb8f | 201 | int altivec_enabled; |
0487d6a8 | 202 | int spe_enabled; |
c227f099 | 203 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 204 | int singlestep_enabled; |
7d08d856 AJ |
205 | uint64_t insns_flags; |
206 | uint64_t insns_flags2; | |
79aceca5 FB |
207 | } DisasContext; |
208 | ||
79482e5a RH |
209 | /* True when active word size < size of target_long. */ |
210 | #ifdef TARGET_PPC64 | |
211 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
212 | #else | |
213 | # define NARROW_MODE(C) 0 | |
214 | #endif | |
215 | ||
c227f099 | 216 | struct opc_handler_t { |
70560da7 FC |
217 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
218 | uint32_t inval1; | |
219 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
220 | uint32_t inval2; | |
9a64fbe4 | 221 | /* instruction type */ |
0487d6a8 | 222 | uint64_t type; |
a5858d7a AG |
223 | /* extended instruction type */ |
224 | uint64_t type2; | |
79aceca5 FB |
225 | /* handler */ |
226 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 227 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 228 | const char *oname; |
a750fc0b JM |
229 | #endif |
230 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
231 | uint64_t count; |
232 | #endif | |
3fc6c082 | 233 | }; |
79aceca5 | 234 | |
636aa200 | 235 | static inline void gen_reset_fpstatus(void) |
7c58044c | 236 | { |
8e703949 | 237 | gen_helper_reset_fpstatus(cpu_env); |
7c58044c JM |
238 | } |
239 | ||
636aa200 | 240 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 241 | { |
0f2f39c2 | 242 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 243 | |
7c58044c JM |
244 | if (set_fprf != 0) { |
245 | /* This case might be optimized later */ | |
0f2f39c2 | 246 | tcg_gen_movi_i32(t0, 1); |
8e703949 | 247 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
a7812ae4 | 248 | if (unlikely(set_rc)) { |
0f2f39c2 | 249 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 250 | } |
8e703949 | 251 | gen_helper_float_check_status(cpu_env); |
7c58044c JM |
252 | } else if (unlikely(set_rc)) { |
253 | /* We always need to compute fpcc */ | |
0f2f39c2 | 254 | tcg_gen_movi_i32(t0, 0); |
8e703949 | 255 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
0f2f39c2 | 256 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 257 | } |
af12906f | 258 | |
0f2f39c2 | 259 | tcg_temp_free_i32(t0); |
7c58044c JM |
260 | } |
261 | ||
636aa200 | 262 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 263 | { |
76db3ba4 AJ |
264 | if (ctx->access_type != access_type) { |
265 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
266 | ctx->access_type = access_type; | |
267 | } | |
a7859e89 AJ |
268 | } |
269 | ||
636aa200 | 270 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 271 | { |
e0c8f9ce RH |
272 | if (NARROW_MODE(ctx)) { |
273 | nip = (uint32_t)nip; | |
274 | } | |
275 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
276 | } |
277 | ||
636aa200 | 278 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
279 | { |
280 | TCGv_i32 t0, t1; | |
281 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
282 | gen_update_nip(ctx, ctx->nip); | |
283 | } | |
284 | t0 = tcg_const_i32(excp); | |
285 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 286 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
287 | tcg_temp_free_i32(t0); |
288 | tcg_temp_free_i32(t1); | |
289 | ctx->exception = (excp); | |
290 | } | |
e1833e1f | 291 | |
636aa200 | 292 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
293 | { |
294 | TCGv_i32 t0; | |
295 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
296 | gen_update_nip(ctx, ctx->nip); | |
297 | } | |
298 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 299 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
300 | tcg_temp_free_i32(t0); |
301 | ctx->exception = (excp); | |
302 | } | |
e1833e1f | 303 | |
636aa200 | 304 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
305 | { |
306 | TCGv_i32 t0; | |
5518f3a6 | 307 | |
ee2b3994 SB |
308 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
309 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
5518f3a6 | 310 | gen_update_nip(ctx, ctx->nip); |
ee2b3994 | 311 | } |
e06fcd75 | 312 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 313 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
314 | tcg_temp_free_i32(t0); |
315 | } | |
9a64fbe4 | 316 | |
636aa200 | 317 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
318 | { |
319 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
320 | } | |
a9d9eb8f | 321 | |
f24e5695 | 322 | /* Stop translation */ |
636aa200 | 323 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 324 | { |
d9bce9d9 | 325 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 326 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
327 | } |
328 | ||
f24e5695 | 329 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 330 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 331 | { |
e1833e1f | 332 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
333 | } |
334 | ||
79aceca5 | 335 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
336 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
337 | ||
338 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
339 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 340 | |
c7697e1f | 341 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
342 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
343 | ||
344 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
345 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 346 | |
c227f099 | 347 | typedef struct opcode_t { |
79aceca5 | 348 | unsigned char opc1, opc2, opc3; |
1235fc06 | 349 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
350 | unsigned char pad[5]; |
351 | #else | |
352 | unsigned char pad[1]; | |
353 | #endif | |
c227f099 | 354 | opc_handler_t handler; |
b55266b5 | 355 | const char *oname; |
c227f099 | 356 | } opcode_t; |
79aceca5 | 357 | |
a750fc0b | 358 | /*****************************************************************************/ |
79aceca5 FB |
359 | /*** Instruction decoding ***/ |
360 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 361 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
362 | { \ |
363 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
364 | } | |
365 | ||
366 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 367 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 368 | { \ |
18fba28c | 369 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
370 | } |
371 | ||
372 | /* Opcode part 1 */ | |
373 | EXTRACT_HELPER(opc1, 26, 6); | |
374 | /* Opcode part 2 */ | |
375 | EXTRACT_HELPER(opc2, 1, 5); | |
376 | /* Opcode part 3 */ | |
377 | EXTRACT_HELPER(opc3, 6, 5); | |
378 | /* Update Cr0 flags */ | |
379 | EXTRACT_HELPER(Rc, 0, 1); | |
380 | /* Destination */ | |
381 | EXTRACT_HELPER(rD, 21, 5); | |
382 | /* Source */ | |
383 | EXTRACT_HELPER(rS, 21, 5); | |
384 | /* First operand */ | |
385 | EXTRACT_HELPER(rA, 16, 5); | |
386 | /* Second operand */ | |
387 | EXTRACT_HELPER(rB, 11, 5); | |
388 | /* Third operand */ | |
389 | EXTRACT_HELPER(rC, 6, 5); | |
390 | /*** Get CRn ***/ | |
391 | EXTRACT_HELPER(crfD, 23, 3); | |
392 | EXTRACT_HELPER(crfS, 18, 3); | |
393 | EXTRACT_HELPER(crbD, 21, 5); | |
394 | EXTRACT_HELPER(crbA, 16, 5); | |
395 | EXTRACT_HELPER(crbB, 11, 5); | |
396 | /* SPR / TBL */ | |
3fc6c082 | 397 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 398 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
399 | { |
400 | uint32_t sprn = _SPR(opcode); | |
401 | ||
402 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
403 | } | |
79aceca5 FB |
404 | /*** Get constants ***/ |
405 | EXTRACT_HELPER(IMM, 12, 8); | |
406 | /* 16 bits signed immediate value */ | |
407 | EXTRACT_SHELPER(SIMM, 0, 16); | |
408 | /* 16 bits unsigned immediate value */ | |
409 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
410 | /* 5 bits signed immediate value */ |
411 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
412 | /* 5 bits signed immediate value */ |
413 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
414 | /* Bit count */ |
415 | EXTRACT_HELPER(NB, 11, 5); | |
416 | /* Shift count */ | |
417 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
418 | /* Vector shift count */ |
419 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
420 | /* Mask start */ |
421 | EXTRACT_HELPER(MB, 6, 5); | |
422 | /* Mask end */ | |
423 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
424 | /* Trap operand */ |
425 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
426 | |
427 | EXTRACT_HELPER(CRM, 12, 8); | |
79aceca5 | 428 | EXTRACT_HELPER(SR, 16, 4); |
7d08d856 AJ |
429 | |
430 | /* mtfsf/mtfsfi */ | |
431 | EXTRACT_HELPER(FPBF, 19, 3); | |
e4bb997e | 432 | EXTRACT_HELPER(FPIMM, 12, 4); |
7d08d856 AJ |
433 | EXTRACT_HELPER(FPL, 21, 1); |
434 | EXTRACT_HELPER(FPFLM, 17, 8); | |
435 | EXTRACT_HELPER(FPW, 16, 1); | |
fb0eaffc | 436 | |
79aceca5 FB |
437 | /*** Jump target decoding ***/ |
438 | /* Displacement */ | |
439 | EXTRACT_SHELPER(d, 0, 16); | |
440 | /* Immediate address */ | |
636aa200 | 441 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
442 | { |
443 | return (opcode >> 0) & 0x03FFFFFC; | |
444 | } | |
445 | ||
636aa200 | 446 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
447 | { |
448 | return (opcode >> 0) & 0xFFFC; | |
449 | } | |
450 | ||
451 | EXTRACT_HELPER(BO, 21, 5); | |
452 | EXTRACT_HELPER(BI, 16, 5); | |
453 | /* Absolute/relative address */ | |
454 | EXTRACT_HELPER(AA, 1, 1); | |
455 | /* Link */ | |
456 | EXTRACT_HELPER(LK, 0, 1); | |
457 | ||
458 | /* Create a mask between <start> and <end> bits */ | |
636aa200 | 459 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 460 | { |
76a66253 | 461 | target_ulong ret; |
79aceca5 | 462 | |
76a66253 JM |
463 | #if defined(TARGET_PPC64) |
464 | if (likely(start == 0)) { | |
6f2d8978 | 465 | ret = UINT64_MAX << (63 - end); |
76a66253 | 466 | } else if (likely(end == 63)) { |
6f2d8978 | 467 | ret = UINT64_MAX >> start; |
76a66253 JM |
468 | } |
469 | #else | |
470 | if (likely(start == 0)) { | |
6f2d8978 | 471 | ret = UINT32_MAX << (31 - end); |
76a66253 | 472 | } else if (likely(end == 31)) { |
6f2d8978 | 473 | ret = UINT32_MAX >> start; |
76a66253 JM |
474 | } |
475 | #endif | |
476 | else { | |
477 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
478 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
479 | if (unlikely(start > end)) | |
480 | return ~ret; | |
481 | } | |
79aceca5 FB |
482 | |
483 | return ret; | |
484 | } | |
485 | ||
a750fc0b | 486 | /*****************************************************************************/ |
a750fc0b | 487 | /* PowerPC instructions table */ |
933dc6eb | 488 | |
76a66253 | 489 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 490 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 491 | { \ |
79aceca5 FB |
492 | .opc1 = op1, \ |
493 | .opc2 = op2, \ | |
494 | .opc3 = op3, \ | |
18fba28c | 495 | .pad = { 0, }, \ |
79aceca5 | 496 | .handler = { \ |
70560da7 FC |
497 | .inval1 = invl, \ |
498 | .type = _typ, \ | |
499 | .type2 = _typ2, \ | |
500 | .handler = &gen_##name, \ | |
501 | .oname = stringify(name), \ | |
502 | }, \ | |
503 | .oname = stringify(name), \ | |
504 | } | |
505 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
506 | { \ | |
507 | .opc1 = op1, \ | |
508 | .opc2 = op2, \ | |
509 | .opc3 = op3, \ | |
510 | .pad = { 0, }, \ | |
511 | .handler = { \ | |
512 | .inval1 = invl1, \ | |
513 | .inval2 = invl2, \ | |
9a64fbe4 | 514 | .type = _typ, \ |
a5858d7a | 515 | .type2 = _typ2, \ |
79aceca5 | 516 | .handler = &gen_##name, \ |
76a66253 | 517 | .oname = stringify(name), \ |
79aceca5 | 518 | }, \ |
3fc6c082 | 519 | .oname = stringify(name), \ |
79aceca5 | 520 | } |
a5858d7a | 521 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 522 | { \ |
c7697e1f JM |
523 | .opc1 = op1, \ |
524 | .opc2 = op2, \ | |
525 | .opc3 = op3, \ | |
526 | .pad = { 0, }, \ | |
527 | .handler = { \ | |
70560da7 | 528 | .inval1 = invl, \ |
c7697e1f | 529 | .type = _typ, \ |
a5858d7a | 530 | .type2 = _typ2, \ |
c7697e1f JM |
531 | .handler = &gen_##name, \ |
532 | .oname = onam, \ | |
533 | }, \ | |
534 | .oname = onam, \ | |
535 | } | |
76a66253 | 536 | #else |
a5858d7a | 537 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 538 | { \ |
c7697e1f JM |
539 | .opc1 = op1, \ |
540 | .opc2 = op2, \ | |
541 | .opc3 = op3, \ | |
542 | .pad = { 0, }, \ | |
543 | .handler = { \ | |
70560da7 FC |
544 | .inval1 = invl, \ |
545 | .type = _typ, \ | |
546 | .type2 = _typ2, \ | |
547 | .handler = &gen_##name, \ | |
548 | }, \ | |
549 | .oname = stringify(name), \ | |
550 | } | |
551 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
552 | { \ | |
553 | .opc1 = op1, \ | |
554 | .opc2 = op2, \ | |
555 | .opc3 = op3, \ | |
556 | .pad = { 0, }, \ | |
557 | .handler = { \ | |
558 | .inval1 = invl1, \ | |
559 | .inval2 = invl2, \ | |
c7697e1f | 560 | .type = _typ, \ |
a5858d7a | 561 | .type2 = _typ2, \ |
c7697e1f | 562 | .handler = &gen_##name, \ |
5c55ff99 BS |
563 | }, \ |
564 | .oname = stringify(name), \ | |
565 | } | |
a5858d7a | 566 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
567 | { \ |
568 | .opc1 = op1, \ | |
569 | .opc2 = op2, \ | |
570 | .opc3 = op3, \ | |
571 | .pad = { 0, }, \ | |
572 | .handler = { \ | |
70560da7 | 573 | .inval1 = invl, \ |
5c55ff99 | 574 | .type = _typ, \ |
a5858d7a | 575 | .type2 = _typ2, \ |
5c55ff99 BS |
576 | .handler = &gen_##name, \ |
577 | }, \ | |
578 | .oname = onam, \ | |
579 | } | |
580 | #endif | |
2e610050 | 581 | |
5c55ff99 | 582 | /* SPR load/store helpers */ |
636aa200 | 583 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 584 | { |
1328c2bf | 585 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 586 | } |
2e610050 | 587 | |
636aa200 | 588 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 589 | { |
1328c2bf | 590 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 591 | } |
2e610050 | 592 | |
54623277 | 593 | /* Invalid instruction */ |
99e300ef | 594 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 595 | { |
e06fcd75 | 596 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
597 | } |
598 | ||
c227f099 | 599 | static opc_handler_t invalid_handler = { |
70560da7 FC |
600 | .inval1 = 0xFFFFFFFF, |
601 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 602 | .type = PPC_NONE, |
a5858d7a | 603 | .type2 = PPC_NONE, |
79aceca5 FB |
604 | .handler = gen_invalid, |
605 | }; | |
606 | ||
e1571908 AJ |
607 | /*** Integer comparison ***/ |
608 | ||
636aa200 | 609 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 610 | { |
2fdcb629 RH |
611 | TCGv t0 = tcg_temp_new(); |
612 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 613 | |
da91a00f | 614 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 615 | |
2fdcb629 RH |
616 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
617 | tcg_gen_trunc_tl_i32(t1, t0); | |
618 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
619 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
620 | ||
621 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
622 | tcg_gen_trunc_tl_i32(t1, t0); | |
623 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
624 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
625 | ||
626 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
627 | tcg_gen_trunc_tl_i32(t1, t0); | |
628 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
629 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
630 | ||
631 | tcg_temp_free(t0); | |
632 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
633 | } |
634 | ||
636aa200 | 635 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 636 | { |
2fdcb629 | 637 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
638 | gen_op_cmp(arg0, t0, s, crf); |
639 | tcg_temp_free(t0); | |
e1571908 AJ |
640 | } |
641 | ||
636aa200 | 642 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 643 | { |
ea363694 | 644 | TCGv t0, t1; |
2fdcb629 RH |
645 | t0 = tcg_temp_new(); |
646 | t1 = tcg_temp_new(); | |
e1571908 | 647 | if (s) { |
ea363694 AJ |
648 | tcg_gen_ext32s_tl(t0, arg0); |
649 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 650 | } else { |
ea363694 AJ |
651 | tcg_gen_ext32u_tl(t0, arg0); |
652 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 653 | } |
ea363694 AJ |
654 | gen_op_cmp(t0, t1, s, crf); |
655 | tcg_temp_free(t1); | |
656 | tcg_temp_free(t0); | |
e1571908 AJ |
657 | } |
658 | ||
636aa200 | 659 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 660 | { |
2fdcb629 | 661 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
662 | gen_op_cmp32(arg0, t0, s, crf); |
663 | tcg_temp_free(t0); | |
e1571908 | 664 | } |
e1571908 | 665 | |
636aa200 | 666 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 667 | { |
02765534 | 668 | if (NARROW_MODE(ctx)) { |
e1571908 | 669 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 670 | } else { |
e1571908 | 671 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 672 | } |
e1571908 AJ |
673 | } |
674 | ||
675 | /* cmp */ | |
99e300ef | 676 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 677 | { |
02765534 | 678 | if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { |
e1571908 AJ |
679 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
680 | 1, crfD(ctx->opcode)); | |
02765534 | 681 | } else { |
e1571908 AJ |
682 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
683 | 1, crfD(ctx->opcode)); | |
02765534 | 684 | } |
e1571908 AJ |
685 | } |
686 | ||
687 | /* cmpi */ | |
99e300ef | 688 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 689 | { |
02765534 | 690 | if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { |
e1571908 AJ |
691 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
692 | 1, crfD(ctx->opcode)); | |
02765534 | 693 | } else { |
e1571908 AJ |
694 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
695 | 1, crfD(ctx->opcode)); | |
02765534 | 696 | } |
e1571908 AJ |
697 | } |
698 | ||
699 | /* cmpl */ | |
99e300ef | 700 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 701 | { |
02765534 | 702 | if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { |
e1571908 AJ |
703 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
704 | 0, crfD(ctx->opcode)); | |
02765534 | 705 | } else { |
e1571908 AJ |
706 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
707 | 0, crfD(ctx->opcode)); | |
02765534 | 708 | } |
e1571908 AJ |
709 | } |
710 | ||
711 | /* cmpli */ | |
99e300ef | 712 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 713 | { |
02765534 | 714 | if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { |
e1571908 AJ |
715 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
716 | 0, crfD(ctx->opcode)); | |
02765534 | 717 | } else { |
e1571908 AJ |
718 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
719 | 0, crfD(ctx->opcode)); | |
02765534 | 720 | } |
e1571908 AJ |
721 | } |
722 | ||
723 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 724 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
725 | { |
726 | int l1, l2; | |
727 | uint32_t bi = rC(ctx->opcode); | |
728 | uint32_t mask; | |
a7812ae4 | 729 | TCGv_i32 t0; |
e1571908 AJ |
730 | |
731 | l1 = gen_new_label(); | |
732 | l2 = gen_new_label(); | |
733 | ||
734 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 735 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
736 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
737 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
738 | if (rA(ctx->opcode) == 0) |
739 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
740 | else | |
741 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
742 | tcg_gen_br(l2); | |
743 | gen_set_label(l1); | |
744 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
745 | gen_set_label(l2); | |
a7812ae4 | 746 | tcg_temp_free_i32(t0); |
e1571908 AJ |
747 | } |
748 | ||
fcfda20f AJ |
749 | /* cmpb: PowerPC 2.05 specification */ |
750 | static void gen_cmpb(DisasContext *ctx) | |
751 | { | |
752 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
753 | cpu_gpr[rB(ctx->opcode)]); | |
754 | } | |
755 | ||
79aceca5 | 756 | /*** Integer arithmetic ***/ |
79aceca5 | 757 | |
636aa200 BS |
758 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
759 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 760 | { |
ffe30937 | 761 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 762 | |
8e7a6db9 | 763 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 764 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
765 | if (sub) { |
766 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
767 | } else { | |
768 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
769 | } | |
770 | tcg_temp_free(t0); | |
02765534 | 771 | if (NARROW_MODE(ctx)) { |
ffe30937 RH |
772 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
773 | } | |
ffe30937 RH |
774 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
775 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
776 | } |
777 | ||
74637406 | 778 | /* Common add function */ |
636aa200 | 779 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
780 | TCGv arg2, bool add_ca, bool compute_ca, |
781 | bool compute_ov, bool compute_rc0) | |
74637406 | 782 | { |
b5a73f8d | 783 | TCGv t0 = ret; |
d9bce9d9 | 784 | |
752d634e | 785 | if (compute_ca || compute_ov) { |
146de60d | 786 | t0 = tcg_temp_new(); |
74637406 | 787 | } |
79aceca5 | 788 | |
da91a00f | 789 | if (compute_ca) { |
79482e5a | 790 | if (NARROW_MODE(ctx)) { |
752d634e RH |
791 | /* Caution: a non-obvious corner case of the spec is that we |
792 | must produce the *entire* 64-bit addition, but produce the | |
793 | carry into bit 32. */ | |
79482e5a | 794 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
795 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
796 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
797 | if (add_ca) { |
798 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
799 | } | |
752d634e RH |
800 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
801 | tcg_temp_free(t1); | |
802 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
803 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
b5a73f8d | 804 | } else { |
79482e5a RH |
805 | TCGv zero = tcg_const_tl(0); |
806 | if (add_ca) { | |
807 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
808 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
809 | } else { | |
810 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
811 | } | |
812 | tcg_temp_free(zero); | |
b5a73f8d | 813 | } |
b5a73f8d RH |
814 | } else { |
815 | tcg_gen_add_tl(t0, arg1, arg2); | |
816 | if (add_ca) { | |
817 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
818 | } | |
da91a00f | 819 | } |
79aceca5 | 820 | |
74637406 AJ |
821 | if (compute_ov) { |
822 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
823 | } | |
b5a73f8d | 824 | if (unlikely(compute_rc0)) { |
74637406 | 825 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 826 | } |
74637406 | 827 | |
a7812ae4 | 828 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
829 | tcg_gen_mov_tl(ret, t0); |
830 | tcg_temp_free(t0); | |
831 | } | |
39dd32ee | 832 | } |
74637406 AJ |
833 | /* Add functions with two operands */ |
834 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 835 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
836 | { \ |
837 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
838 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 839 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
840 | } |
841 | /* Add functions with one operand and one immediate */ | |
842 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
843 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 844 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 845 | { \ |
b5a73f8d | 846 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
847 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
848 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 849 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
850 | tcg_temp_free(t0); \ |
851 | } | |
852 | ||
853 | /* add add. addo addo. */ | |
854 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
855 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
856 | /* addc addc. addco addco. */ | |
857 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
858 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
859 | /* adde adde. addeo addeo. */ | |
860 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
861 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
862 | /* addme addme. addmeo addmeo. */ | |
863 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
864 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
865 | /* addze addze. addzeo addzeo.*/ | |
866 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
867 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
868 | /* addi */ | |
99e300ef | 869 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 870 | { |
74637406 AJ |
871 | target_long simm = SIMM(ctx->opcode); |
872 | ||
873 | if (rA(ctx->opcode) == 0) { | |
874 | /* li case */ | |
875 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
876 | } else { | |
b5a73f8d RH |
877 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
878 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 879 | } |
d9bce9d9 | 880 | } |
74637406 | 881 | /* addic addic.*/ |
b5a73f8d | 882 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 883 | { |
b5a73f8d RH |
884 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
885 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
886 | c, 0, 1, 0, compute_rc0); | |
887 | tcg_temp_free(c); | |
d9bce9d9 | 888 | } |
99e300ef BS |
889 | |
890 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 891 | { |
b5a73f8d | 892 | gen_op_addic(ctx, 0); |
d9bce9d9 | 893 | } |
e8eaa2c0 BS |
894 | |
895 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 896 | { |
b5a73f8d | 897 | gen_op_addic(ctx, 1); |
d9bce9d9 | 898 | } |
99e300ef | 899 | |
54623277 | 900 | /* addis */ |
99e300ef | 901 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 902 | { |
74637406 AJ |
903 | target_long simm = SIMM(ctx->opcode); |
904 | ||
905 | if (rA(ctx->opcode) == 0) { | |
906 | /* lis case */ | |
907 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
908 | } else { | |
b5a73f8d RH |
909 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
910 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 911 | } |
d9bce9d9 | 912 | } |
74637406 | 913 | |
636aa200 BS |
914 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
915 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 916 | { |
2ef1b120 AJ |
917 | int l1 = gen_new_label(); |
918 | int l2 = gen_new_label(); | |
a7812ae4 PB |
919 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
920 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 921 | |
2ef1b120 AJ |
922 | tcg_gen_trunc_tl_i32(t0, arg1); |
923 | tcg_gen_trunc_tl_i32(t1, arg2); | |
924 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 925 | if (sign) { |
2ef1b120 AJ |
926 | int l3 = gen_new_label(); |
927 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
928 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 929 | gen_set_label(l3); |
2ef1b120 | 930 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 931 | } else { |
2ef1b120 | 932 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
933 | } |
934 | if (compute_ov) { | |
da91a00f | 935 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
936 | } |
937 | tcg_gen_br(l2); | |
938 | gen_set_label(l1); | |
939 | if (sign) { | |
2ef1b120 | 940 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
941 | } else { |
942 | tcg_gen_movi_i32(t0, 0); | |
943 | } | |
944 | if (compute_ov) { | |
da91a00f RH |
945 | tcg_gen_movi_tl(cpu_ov, 1); |
946 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
947 | } |
948 | gen_set_label(l2); | |
2ef1b120 | 949 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
950 | tcg_temp_free_i32(t0); |
951 | tcg_temp_free_i32(t1); | |
74637406 AJ |
952 | if (unlikely(Rc(ctx->opcode) != 0)) |
953 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 954 | } |
74637406 AJ |
955 | /* Div functions */ |
956 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 957 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
958 | { \ |
959 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
960 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
961 | sign, compute_ov); \ | |
962 | } | |
963 | /* divwu divwu. divwuo divwuo. */ | |
964 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
965 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
966 | /* divw divw. divwo divwo. */ | |
967 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
968 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
d9bce9d9 | 969 | #if defined(TARGET_PPC64) |
636aa200 BS |
970 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
971 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 972 | { |
2ef1b120 AJ |
973 | int l1 = gen_new_label(); |
974 | int l2 = gen_new_label(); | |
74637406 AJ |
975 | |
976 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
977 | if (sign) { | |
2ef1b120 | 978 | int l3 = gen_new_label(); |
74637406 AJ |
979 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
980 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
981 | gen_set_label(l3); | |
74637406 AJ |
982 | tcg_gen_div_i64(ret, arg1, arg2); |
983 | } else { | |
984 | tcg_gen_divu_i64(ret, arg1, arg2); | |
985 | } | |
986 | if (compute_ov) { | |
da91a00f | 987 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
988 | } |
989 | tcg_gen_br(l2); | |
990 | gen_set_label(l1); | |
991 | if (sign) { | |
992 | tcg_gen_sari_i64(ret, arg1, 63); | |
993 | } else { | |
994 | tcg_gen_movi_i64(ret, 0); | |
995 | } | |
996 | if (compute_ov) { | |
da91a00f RH |
997 | tcg_gen_movi_tl(cpu_ov, 1); |
998 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
999 | } |
1000 | gen_set_label(l2); | |
1001 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1002 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1003 | } |
74637406 | 1004 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1005 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1006 | { \ |
2ef1b120 AJ |
1007 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1008 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1009 | sign, compute_ov); \ | |
74637406 AJ |
1010 | } |
1011 | /* divwu divwu. divwuo divwuo. */ | |
1012 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1013 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1014 | /* divw divw. divwo divwo. */ | |
1015 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1016 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
d9bce9d9 | 1017 | #endif |
74637406 AJ |
1018 | |
1019 | /* mulhw mulhw. */ | |
99e300ef | 1020 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1021 | { |
23ad1d5d RH |
1022 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1023 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1024 | |
23ad1d5d RH |
1025 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1026 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1027 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1028 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1029 | tcg_temp_free_i32(t0); | |
1030 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1031 | if (unlikely(Rc(ctx->opcode) != 0)) |
1032 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1033 | } |
99e300ef | 1034 | |
54623277 | 1035 | /* mulhwu mulhwu. */ |
99e300ef | 1036 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1037 | { |
23ad1d5d RH |
1038 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1039 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1040 | |
23ad1d5d RH |
1041 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1042 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1043 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1044 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1045 | tcg_temp_free_i32(t0); | |
1046 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1047 | if (unlikely(Rc(ctx->opcode) != 0)) |
1048 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1049 | } |
99e300ef | 1050 | |
54623277 | 1051 | /* mullw mullw. */ |
99e300ef | 1052 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1053 | { |
74637406 AJ |
1054 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1055 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1056 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
74637406 AJ |
1057 | if (unlikely(Rc(ctx->opcode) != 0)) |
1058 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1059 | } |
99e300ef | 1060 | |
54623277 | 1061 | /* mullwo mullwo. */ |
99e300ef | 1062 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1063 | { |
e4a2c846 RH |
1064 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1065 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1066 | |
e4a2c846 RH |
1067 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1068 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1069 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1070 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1071 | ||
1072 | tcg_gen_sari_i32(t0, t0, 31); | |
1073 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1074 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
1075 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1076 | ||
1077 | tcg_temp_free_i32(t0); | |
1078 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1079 | if (unlikely(Rc(ctx->opcode) != 0)) |
1080 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1081 | } |
99e300ef | 1082 | |
54623277 | 1083 | /* mulli */ |
99e300ef | 1084 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1085 | { |
74637406 AJ |
1086 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1087 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1088 | } |
23ad1d5d | 1089 | |
d9bce9d9 | 1090 | #if defined(TARGET_PPC64) |
74637406 | 1091 | /* mulhd mulhd. */ |
23ad1d5d RH |
1092 | static void gen_mulhd(DisasContext *ctx) |
1093 | { | |
1094 | TCGv lo = tcg_temp_new(); | |
1095 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1096 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1097 | tcg_temp_free(lo); | |
1098 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1099 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1100 | } | |
1101 | } | |
1102 | ||
74637406 | 1103 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1104 | static void gen_mulhdu(DisasContext *ctx) |
1105 | { | |
1106 | TCGv lo = tcg_temp_new(); | |
1107 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1108 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1109 | tcg_temp_free(lo); | |
1110 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1111 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1112 | } | |
1113 | } | |
99e300ef | 1114 | |
54623277 | 1115 | /* mulld mulld. */ |
99e300ef | 1116 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1117 | { |
74637406 AJ |
1118 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1119 | cpu_gpr[rB(ctx->opcode)]); | |
1120 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1121 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1122 | } |
d15f74fb | 1123 | |
74637406 | 1124 | /* mulldo mulldo. */ |
d15f74fb BS |
1125 | static void gen_mulldo(DisasContext *ctx) |
1126 | { | |
1127 | gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env, | |
1128 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1129 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1130 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1131 | } | |
1132 | } | |
d9bce9d9 | 1133 | #endif |
74637406 | 1134 | |
74637406 | 1135 | /* Common subf function */ |
636aa200 | 1136 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1137 | TCGv arg2, bool add_ca, bool compute_ca, |
1138 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1139 | { |
b5a73f8d | 1140 | TCGv t0 = ret; |
79aceca5 | 1141 | |
752d634e | 1142 | if (compute_ca || compute_ov) { |
b5a73f8d | 1143 | t0 = tcg_temp_new(); |
da91a00f | 1144 | } |
74637406 | 1145 | |
79482e5a RH |
1146 | if (compute_ca) { |
1147 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1148 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1149 | /* Caution: a non-obvious corner case of the spec is that we |
1150 | must produce the *entire* 64-bit addition, but produce the | |
1151 | carry into bit 32. */ | |
79482e5a | 1152 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1153 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1154 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1155 | if (add_ca) { |
752d634e | 1156 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1157 | } else { |
752d634e | 1158 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1159 | } |
752d634e | 1160 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1161 | tcg_gen_add_tl(t0, t0, inv1); |
752d634e RH |
1162 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1163 | tcg_temp_free(t1); | |
1164 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
1165 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
79482e5a | 1166 | } else if (add_ca) { |
08f4a0f7 RH |
1167 | TCGv zero, inv1 = tcg_temp_new(); |
1168 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1169 | zero = tcg_const_tl(0); |
1170 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1171 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
b5a73f8d | 1172 | tcg_temp_free(zero); |
08f4a0f7 | 1173 | tcg_temp_free(inv1); |
b5a73f8d | 1174 | } else { |
79482e5a | 1175 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1176 | tcg_gen_sub_tl(t0, arg2, arg1); |
b5a73f8d | 1177 | } |
79482e5a RH |
1178 | } else if (add_ca) { |
1179 | /* Since we're ignoring carry-out, we can simplify the | |
1180 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1181 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1182 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1183 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1184 | } else { |
b5a73f8d | 1185 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1186 | } |
b5a73f8d | 1187 | |
74637406 AJ |
1188 | if (compute_ov) { |
1189 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1190 | } | |
b5a73f8d | 1191 | if (unlikely(compute_rc0)) { |
74637406 | 1192 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1193 | } |
74637406 | 1194 | |
a7812ae4 | 1195 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1196 | tcg_gen_mov_tl(ret, t0); |
1197 | tcg_temp_free(t0); | |
79aceca5 | 1198 | } |
79aceca5 | 1199 | } |
74637406 AJ |
1200 | /* Sub functions with Two operands functions */ |
1201 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1202 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1203 | { \ |
1204 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1205 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1206 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1207 | } |
1208 | /* Sub functions with one operand and one immediate */ | |
1209 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1210 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1211 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1212 | { \ |
b5a73f8d | 1213 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1214 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1215 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1216 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1217 | tcg_temp_free(t0); \ |
1218 | } | |
1219 | /* subf subf. subfo subfo. */ | |
1220 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1221 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1222 | /* subfc subfc. subfco subfco. */ | |
1223 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1224 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1225 | /* subfe subfe. subfeo subfo. */ | |
1226 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1227 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1228 | /* subfme subfme. subfmeo subfmeo. */ | |
1229 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1230 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1231 | /* subfze subfze. subfzeo subfzeo.*/ | |
1232 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1233 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1234 | |
54623277 | 1235 | /* subfic */ |
99e300ef | 1236 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1237 | { |
b5a73f8d RH |
1238 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1239 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1240 | c, 0, 1, 0, 0); | |
1241 | tcg_temp_free(c); | |
79aceca5 FB |
1242 | } |
1243 | ||
fd3f0081 RH |
1244 | /* neg neg. nego nego. */ |
1245 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1246 | { | |
1247 | TCGv zero = tcg_const_tl(0); | |
1248 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1249 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1250 | tcg_temp_free(zero); | |
1251 | } | |
1252 | ||
1253 | static void gen_neg(DisasContext *ctx) | |
1254 | { | |
1255 | gen_op_arith_neg(ctx, 0); | |
1256 | } | |
1257 | ||
1258 | static void gen_nego(DisasContext *ctx) | |
1259 | { | |
1260 | gen_op_arith_neg(ctx, 1); | |
1261 | } | |
1262 | ||
79aceca5 | 1263 | /*** Integer logical ***/ |
26d67362 | 1264 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1265 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1266 | { \ |
26d67362 AJ |
1267 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1268 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1269 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1270 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1271 | } |
79aceca5 | 1272 | |
26d67362 | 1273 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1274 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1275 | { \ |
26d67362 | 1276 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1277 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1278 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1279 | } |
1280 | ||
1281 | /* and & and. */ | |
26d67362 | 1282 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1283 | /* andc & andc. */ |
26d67362 | 1284 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1285 | |
54623277 | 1286 | /* andi. */ |
e8eaa2c0 | 1287 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1288 | { |
26d67362 AJ |
1289 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1290 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1291 | } |
e8eaa2c0 | 1292 | |
54623277 | 1293 | /* andis. */ |
e8eaa2c0 | 1294 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1295 | { |
26d67362 AJ |
1296 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1297 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1298 | } |
99e300ef | 1299 | |
54623277 | 1300 | /* cntlzw */ |
99e300ef | 1301 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1302 | { |
a7812ae4 | 1303 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1304 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1305 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1306 | } |
79aceca5 | 1307 | /* eqv & eqv. */ |
26d67362 | 1308 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1309 | /* extsb & extsb. */ |
26d67362 | 1310 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1311 | /* extsh & extsh. */ |
26d67362 | 1312 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1313 | /* nand & nand. */ |
26d67362 | 1314 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1315 | /* nor & nor. */ |
26d67362 | 1316 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1317 | |
54623277 | 1318 | /* or & or. */ |
99e300ef | 1319 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1320 | { |
76a66253 JM |
1321 | int rs, ra, rb; |
1322 | ||
1323 | rs = rS(ctx->opcode); | |
1324 | ra = rA(ctx->opcode); | |
1325 | rb = rB(ctx->opcode); | |
1326 | /* Optimisation for mr. ri case */ | |
1327 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1328 | if (rs != rb) |
1329 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1330 | else | |
1331 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1332 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1333 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1334 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1335 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1336 | #if defined(TARGET_PPC64) |
1337 | } else { | |
26d67362 AJ |
1338 | int prio = 0; |
1339 | ||
c80f84e3 JM |
1340 | switch (rs) { |
1341 | case 1: | |
1342 | /* Set process priority to low */ | |
26d67362 | 1343 | prio = 2; |
c80f84e3 JM |
1344 | break; |
1345 | case 6: | |
1346 | /* Set process priority to medium-low */ | |
26d67362 | 1347 | prio = 3; |
c80f84e3 JM |
1348 | break; |
1349 | case 2: | |
1350 | /* Set process priority to normal */ | |
26d67362 | 1351 | prio = 4; |
c80f84e3 | 1352 | break; |
be147d08 JM |
1353 | #if !defined(CONFIG_USER_ONLY) |
1354 | case 31: | |
76db3ba4 | 1355 | if (ctx->mem_idx > 0) { |
be147d08 | 1356 | /* Set process priority to very low */ |
26d67362 | 1357 | prio = 1; |
be147d08 JM |
1358 | } |
1359 | break; | |
1360 | case 5: | |
76db3ba4 | 1361 | if (ctx->mem_idx > 0) { |
be147d08 | 1362 | /* Set process priority to medium-hight */ |
26d67362 | 1363 | prio = 5; |
be147d08 JM |
1364 | } |
1365 | break; | |
1366 | case 3: | |
76db3ba4 | 1367 | if (ctx->mem_idx > 0) { |
be147d08 | 1368 | /* Set process priority to high */ |
26d67362 | 1369 | prio = 6; |
be147d08 JM |
1370 | } |
1371 | break; | |
be147d08 | 1372 | case 7: |
76db3ba4 | 1373 | if (ctx->mem_idx > 1) { |
be147d08 | 1374 | /* Set process priority to very high */ |
26d67362 | 1375 | prio = 7; |
be147d08 JM |
1376 | } |
1377 | break; | |
be147d08 | 1378 | #endif |
c80f84e3 JM |
1379 | default: |
1380 | /* nop */ | |
1381 | break; | |
1382 | } | |
26d67362 | 1383 | if (prio) { |
a7812ae4 | 1384 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1385 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1386 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1387 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1388 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1389 | tcg_temp_free(t0); |
26d67362 | 1390 | } |
c80f84e3 | 1391 | #endif |
9a64fbe4 | 1392 | } |
9a64fbe4 | 1393 | } |
79aceca5 | 1394 | /* orc & orc. */ |
26d67362 | 1395 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1396 | |
54623277 | 1397 | /* xor & xor. */ |
99e300ef | 1398 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1399 | { |
9a64fbe4 | 1400 | /* Optimisation for "set to zero" case */ |
26d67362 | 1401 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1402 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1403 | else |
1404 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1405 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1406 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1407 | } |
99e300ef | 1408 | |
54623277 | 1409 | /* ori */ |
99e300ef | 1410 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1411 | { |
76a66253 | 1412 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1413 | |
9a64fbe4 FB |
1414 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1415 | /* NOP */ | |
76a66253 | 1416 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1417 | return; |
76a66253 | 1418 | } |
26d67362 | 1419 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1420 | } |
99e300ef | 1421 | |
54623277 | 1422 | /* oris */ |
99e300ef | 1423 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1424 | { |
76a66253 | 1425 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1426 | |
9a64fbe4 FB |
1427 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1428 | /* NOP */ | |
1429 | return; | |
76a66253 | 1430 | } |
26d67362 | 1431 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1432 | } |
99e300ef | 1433 | |
54623277 | 1434 | /* xori */ |
99e300ef | 1435 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1436 | { |
76a66253 | 1437 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1438 | |
1439 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1440 | /* NOP */ | |
1441 | return; | |
1442 | } | |
26d67362 | 1443 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1444 | } |
99e300ef | 1445 | |
54623277 | 1446 | /* xoris */ |
99e300ef | 1447 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1448 | { |
76a66253 | 1449 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1450 | |
1451 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1452 | /* NOP */ | |
1453 | return; | |
1454 | } | |
26d67362 | 1455 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1456 | } |
99e300ef | 1457 | |
54623277 | 1458 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1459 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1460 | { |
eaabeef2 DG |
1461 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1462 | } | |
1463 | ||
1464 | static void gen_popcntw(DisasContext *ctx) | |
1465 | { | |
1466 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1467 | } | |
1468 | ||
d9bce9d9 | 1469 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1470 | /* popcntd: PowerPC 2.06 specification */ |
1471 | static void gen_popcntd(DisasContext *ctx) | |
1472 | { | |
1473 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1474 | } |
eaabeef2 | 1475 | #endif |
d9bce9d9 | 1476 | |
725bcec2 AJ |
1477 | /* prtyw: PowerPC 2.05 specification */ |
1478 | static void gen_prtyw(DisasContext *ctx) | |
1479 | { | |
1480 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1481 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1482 | TCGv t0 = tcg_temp_new(); | |
1483 | tcg_gen_shri_tl(t0, rs, 16); | |
1484 | tcg_gen_xor_tl(ra, rs, t0); | |
1485 | tcg_gen_shri_tl(t0, ra, 8); | |
1486 | tcg_gen_xor_tl(ra, ra, t0); | |
1487 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1488 | tcg_temp_free(t0); | |
1489 | } | |
1490 | ||
1491 | #if defined(TARGET_PPC64) | |
1492 | /* prtyd: PowerPC 2.05 specification */ | |
1493 | static void gen_prtyd(DisasContext *ctx) | |
1494 | { | |
1495 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1496 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1497 | TCGv t0 = tcg_temp_new(); | |
1498 | tcg_gen_shri_tl(t0, rs, 32); | |
1499 | tcg_gen_xor_tl(ra, rs, t0); | |
1500 | tcg_gen_shri_tl(t0, ra, 16); | |
1501 | tcg_gen_xor_tl(ra, ra, t0); | |
1502 | tcg_gen_shri_tl(t0, ra, 8); | |
1503 | tcg_gen_xor_tl(ra, ra, t0); | |
1504 | tcg_gen_andi_tl(ra, ra, 1); | |
1505 | tcg_temp_free(t0); | |
1506 | } | |
1507 | #endif | |
1508 | ||
d9bce9d9 JM |
1509 | #if defined(TARGET_PPC64) |
1510 | /* extsw & extsw. */ | |
26d67362 | 1511 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1512 | |
54623277 | 1513 | /* cntlzd */ |
99e300ef | 1514 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1515 | { |
a7812ae4 | 1516 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1517 | if (unlikely(Rc(ctx->opcode) != 0)) |
1518 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1519 | } | |
d9bce9d9 JM |
1520 | #endif |
1521 | ||
79aceca5 | 1522 | /*** Integer rotate ***/ |
99e300ef | 1523 | |
54623277 | 1524 | /* rlwimi & rlwimi. */ |
99e300ef | 1525 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1526 | { |
76a66253 | 1527 | uint32_t mb, me, sh; |
79aceca5 FB |
1528 | |
1529 | mb = MB(ctx->opcode); | |
1530 | me = ME(ctx->opcode); | |
76a66253 | 1531 | sh = SH(ctx->opcode); |
d03ef511 AJ |
1532 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1533 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1534 | } else { | |
d03ef511 | 1535 | target_ulong mask; |
a7812ae4 PB |
1536 | TCGv t1; |
1537 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1538 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1539 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1540 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1541 | tcg_gen_rotli_i32(t2, t2, sh); | |
1542 | tcg_gen_extu_i32_i64(t0, t2); | |
1543 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1544 | #else |
1545 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1546 | #endif | |
76a66253 | 1547 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1548 | mb += 32; |
1549 | me += 32; | |
76a66253 | 1550 | #endif |
d03ef511 | 1551 | mask = MASK(mb, me); |
a7812ae4 | 1552 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1553 | tcg_gen_andi_tl(t0, t0, mask); |
1554 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1555 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1556 | tcg_temp_free(t0); | |
1557 | tcg_temp_free(t1); | |
1558 | } | |
76a66253 | 1559 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1560 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1561 | } |
99e300ef | 1562 | |
54623277 | 1563 | /* rlwinm & rlwinm. */ |
99e300ef | 1564 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1565 | { |
1566 | uint32_t mb, me, sh; | |
3b46e624 | 1567 | |
79aceca5 FB |
1568 | sh = SH(ctx->opcode); |
1569 | mb = MB(ctx->opcode); | |
1570 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1571 | |
1572 | if (likely(mb == 0 && me == (31 - sh))) { | |
1573 | if (likely(sh == 0)) { | |
1574 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1575 | } else { | |
a7812ae4 | 1576 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1577 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1578 | tcg_gen_shli_tl(t0, t0, sh); | |
1579 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1580 | tcg_temp_free(t0); | |
79aceca5 | 1581 | } |
d03ef511 | 1582 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1583 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1584 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1585 | tcg_gen_shri_tl(t0, t0, mb); | |
1586 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1587 | tcg_temp_free(t0); | |
1588 | } else { | |
a7812ae4 | 1589 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1590 | #if defined(TARGET_PPC64) |
a7812ae4 | 1591 | TCGv_i32 t1 = tcg_temp_new_i32(); |
54843a58 AJ |
1592 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1593 | tcg_gen_rotli_i32(t1, t1, sh); | |
1594 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 | 1595 | tcg_temp_free_i32(t1); |
54843a58 AJ |
1596 | #else |
1597 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1598 | #endif | |
76a66253 | 1599 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1600 | mb += 32; |
1601 | me += 32; | |
76a66253 | 1602 | #endif |
d03ef511 AJ |
1603 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1604 | tcg_temp_free(t0); | |
1605 | } | |
76a66253 | 1606 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1607 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1608 | } |
99e300ef | 1609 | |
54623277 | 1610 | /* rlwnm & rlwnm. */ |
99e300ef | 1611 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1612 | { |
1613 | uint32_t mb, me; | |
54843a58 AJ |
1614 | TCGv t0; |
1615 | #if defined(TARGET_PPC64) | |
a7812ae4 | 1616 | TCGv_i32 t1, t2; |
54843a58 | 1617 | #endif |
79aceca5 FB |
1618 | |
1619 | mb = MB(ctx->opcode); | |
1620 | me = ME(ctx->opcode); | |
a7812ae4 | 1621 | t0 = tcg_temp_new(); |
d03ef511 | 1622 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1623 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1624 | t1 = tcg_temp_new_i32(); |
1625 | t2 = tcg_temp_new_i32(); | |
54843a58 AJ |
1626 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1627 | tcg_gen_trunc_i64_i32(t2, t0); | |
1628 | tcg_gen_rotl_i32(t1, t1, t2); | |
1629 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 PB |
1630 | tcg_temp_free_i32(t1); |
1631 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1632 | #else |
1633 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1634 | #endif | |
76a66253 JM |
1635 | if (unlikely(mb != 0 || me != 31)) { |
1636 | #if defined(TARGET_PPC64) | |
1637 | mb += 32; | |
1638 | me += 32; | |
1639 | #endif | |
54843a58 | 1640 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1641 | } else { |
54843a58 | 1642 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1643 | } |
54843a58 | 1644 | tcg_temp_free(t0); |
76a66253 | 1645 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1646 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1647 | } |
1648 | ||
d9bce9d9 JM |
1649 | #if defined(TARGET_PPC64) |
1650 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1651 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1652 | { \ |
1653 | gen_##name(ctx, 0); \ | |
1654 | } \ | |
e8eaa2c0 BS |
1655 | \ |
1656 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1657 | { \ |
1658 | gen_##name(ctx, 1); \ | |
1659 | } | |
1660 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1661 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1662 | { \ |
1663 | gen_##name(ctx, 0, 0); \ | |
1664 | } \ | |
e8eaa2c0 BS |
1665 | \ |
1666 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1667 | { \ |
1668 | gen_##name(ctx, 0, 1); \ | |
1669 | } \ | |
e8eaa2c0 BS |
1670 | \ |
1671 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1672 | { \ |
1673 | gen_##name(ctx, 1, 0); \ | |
1674 | } \ | |
e8eaa2c0 BS |
1675 | \ |
1676 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1677 | { \ |
1678 | gen_##name(ctx, 1, 1); \ | |
1679 | } | |
51789c41 | 1680 | |
636aa200 BS |
1681 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1682 | uint32_t sh) | |
51789c41 | 1683 | { |
d03ef511 AJ |
1684 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1685 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1686 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1687 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1688 | } else { | |
a7812ae4 | 1689 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1690 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1691 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1692 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1693 | } else { |
1694 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1695 | } |
d03ef511 | 1696 | tcg_temp_free(t0); |
51789c41 | 1697 | } |
51789c41 | 1698 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1699 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1700 | } |
d9bce9d9 | 1701 | /* rldicl - rldicl. */ |
636aa200 | 1702 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1703 | { |
51789c41 | 1704 | uint32_t sh, mb; |
d9bce9d9 | 1705 | |
9d53c753 JM |
1706 | sh = SH(ctx->opcode) | (shn << 5); |
1707 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1708 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1709 | } |
51789c41 | 1710 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1711 | /* rldicr - rldicr. */ |
636aa200 | 1712 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1713 | { |
51789c41 | 1714 | uint32_t sh, me; |
d9bce9d9 | 1715 | |
9d53c753 JM |
1716 | sh = SH(ctx->opcode) | (shn << 5); |
1717 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1718 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1719 | } |
51789c41 | 1720 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1721 | /* rldic - rldic. */ |
636aa200 | 1722 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1723 | { |
51789c41 | 1724 | uint32_t sh, mb; |
d9bce9d9 | 1725 | |
9d53c753 JM |
1726 | sh = SH(ctx->opcode) | (shn << 5); |
1727 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1728 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1729 | } | |
1730 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1731 | ||
636aa200 | 1732 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1733 | { |
54843a58 | 1734 | TCGv t0; |
d03ef511 AJ |
1735 | |
1736 | mb = MB(ctx->opcode); | |
1737 | me = ME(ctx->opcode); | |
a7812ae4 | 1738 | t0 = tcg_temp_new(); |
d03ef511 | 1739 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1740 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1741 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1742 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1743 | } else { | |
1744 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1745 | } | |
1746 | tcg_temp_free(t0); | |
51789c41 | 1747 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1748 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1749 | } |
51789c41 | 1750 | |
d9bce9d9 | 1751 | /* rldcl - rldcl. */ |
636aa200 | 1752 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1753 | { |
51789c41 | 1754 | uint32_t mb; |
d9bce9d9 | 1755 | |
9d53c753 | 1756 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1757 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1758 | } |
36081602 | 1759 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1760 | /* rldcr - rldcr. */ |
636aa200 | 1761 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1762 | { |
51789c41 | 1763 | uint32_t me; |
d9bce9d9 | 1764 | |
9d53c753 | 1765 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1766 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1767 | } |
36081602 | 1768 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1769 | /* rldimi - rldimi. */ |
636aa200 | 1770 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1771 | { |
271a916e | 1772 | uint32_t sh, mb, me; |
d9bce9d9 | 1773 | |
9d53c753 JM |
1774 | sh = SH(ctx->opcode) | (shn << 5); |
1775 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1776 | me = 63 - sh; |
d03ef511 AJ |
1777 | if (unlikely(sh == 0 && mb == 0)) { |
1778 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1779 | } else { | |
1780 | TCGv t0, t1; | |
1781 | target_ulong mask; | |
1782 | ||
a7812ae4 | 1783 | t0 = tcg_temp_new(); |
54843a58 | 1784 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1785 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1786 | mask = MASK(mb, me); |
1787 | tcg_gen_andi_tl(t0, t0, mask); | |
1788 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1789 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1790 | tcg_temp_free(t0); | |
1791 | tcg_temp_free(t1); | |
51789c41 | 1792 | } |
51789c41 | 1793 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1794 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1795 | } |
36081602 | 1796 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1797 | #endif |
1798 | ||
79aceca5 | 1799 | /*** Integer shift ***/ |
99e300ef | 1800 | |
54623277 | 1801 | /* slw & slw. */ |
99e300ef | 1802 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1803 | { |
7fd6bf7d | 1804 | TCGv t0, t1; |
26d67362 | 1805 | |
7fd6bf7d AJ |
1806 | t0 = tcg_temp_new(); |
1807 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1808 | #if defined(TARGET_PPC64) | |
1809 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1810 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1811 | #else | |
1812 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1813 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1814 | #endif | |
1815 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1816 | t1 = tcg_temp_new(); | |
1817 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1818 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1819 | tcg_temp_free(t1); | |
fea0c503 | 1820 | tcg_temp_free(t0); |
7fd6bf7d | 1821 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1822 | if (unlikely(Rc(ctx->opcode) != 0)) |
1823 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1824 | } | |
99e300ef | 1825 | |
54623277 | 1826 | /* sraw & sraw. */ |
99e300ef | 1827 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1828 | { |
d15f74fb | 1829 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1830 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1831 | if (unlikely(Rc(ctx->opcode) != 0)) |
1832 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1833 | } | |
99e300ef | 1834 | |
54623277 | 1835 | /* srawi & srawi. */ |
99e300ef | 1836 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1837 | { |
26d67362 | 1838 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
1839 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1840 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
1841 | if (sh == 0) { | |
1842 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 1843 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1844 | } else { |
ba4af3e4 RH |
1845 | TCGv t0; |
1846 | tcg_gen_ext32s_tl(dst, src); | |
1847 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
1848 | t0 = tcg_temp_new(); | |
1849 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
1850 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
1851 | tcg_temp_free(t0); | |
1852 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
1853 | tcg_gen_sari_tl(dst, dst, sh); | |
1854 | } | |
1855 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1856 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 1857 | } |
79aceca5 | 1858 | } |
99e300ef | 1859 | |
54623277 | 1860 | /* srw & srw. */ |
99e300ef | 1861 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1862 | { |
fea0c503 | 1863 | TCGv t0, t1; |
d9bce9d9 | 1864 | |
7fd6bf7d AJ |
1865 | t0 = tcg_temp_new(); |
1866 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1867 | #if defined(TARGET_PPC64) | |
1868 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1869 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1870 | #else | |
1871 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1872 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1873 | #endif | |
1874 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1875 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1876 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1877 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1878 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1879 | tcg_temp_free(t1); |
fea0c503 | 1880 | tcg_temp_free(t0); |
26d67362 AJ |
1881 | if (unlikely(Rc(ctx->opcode) != 0)) |
1882 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1883 | } | |
54623277 | 1884 | |
d9bce9d9 JM |
1885 | #if defined(TARGET_PPC64) |
1886 | /* sld & sld. */ | |
99e300ef | 1887 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1888 | { |
7fd6bf7d | 1889 | TCGv t0, t1; |
26d67362 | 1890 | |
7fd6bf7d AJ |
1891 | t0 = tcg_temp_new(); |
1892 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1893 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1894 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1895 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1896 | t1 = tcg_temp_new(); | |
1897 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1898 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1899 | tcg_temp_free(t1); | |
fea0c503 | 1900 | tcg_temp_free(t0); |
26d67362 AJ |
1901 | if (unlikely(Rc(ctx->opcode) != 0)) |
1902 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1903 | } | |
99e300ef | 1904 | |
54623277 | 1905 | /* srad & srad. */ |
99e300ef | 1906 | static void gen_srad(DisasContext *ctx) |
26d67362 | 1907 | { |
d15f74fb | 1908 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1909 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1910 | if (unlikely(Rc(ctx->opcode) != 0)) |
1911 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1912 | } | |
d9bce9d9 | 1913 | /* sradi & sradi. */ |
636aa200 | 1914 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 1915 | { |
26d67362 | 1916 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
1917 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1918 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
1919 | if (sh == 0) { | |
1920 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 1921 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1922 | } else { |
ba4af3e4 RH |
1923 | TCGv t0; |
1924 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
1925 | t0 = tcg_temp_new(); | |
1926 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
1927 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
1928 | tcg_temp_free(t0); | |
1929 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
1930 | tcg_gen_sari_tl(dst, src, sh); | |
1931 | } | |
1932 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1933 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 1934 | } |
d9bce9d9 | 1935 | } |
e8eaa2c0 BS |
1936 | |
1937 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
1938 | { |
1939 | gen_sradi(ctx, 0); | |
1940 | } | |
e8eaa2c0 BS |
1941 | |
1942 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
1943 | { |
1944 | gen_sradi(ctx, 1); | |
1945 | } | |
99e300ef | 1946 | |
54623277 | 1947 | /* srd & srd. */ |
99e300ef | 1948 | static void gen_srd(DisasContext *ctx) |
26d67362 | 1949 | { |
7fd6bf7d | 1950 | TCGv t0, t1; |
26d67362 | 1951 | |
7fd6bf7d AJ |
1952 | t0 = tcg_temp_new(); |
1953 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1954 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1955 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1956 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1957 | t1 = tcg_temp_new(); | |
1958 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1959 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1960 | tcg_temp_free(t1); | |
fea0c503 | 1961 | tcg_temp_free(t0); |
26d67362 AJ |
1962 | if (unlikely(Rc(ctx->opcode) != 0)) |
1963 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1964 | } | |
d9bce9d9 | 1965 | #endif |
79aceca5 FB |
1966 | |
1967 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 1968 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 1969 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1970 | { \ |
76a66253 | 1971 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1972 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1973 | return; \ |
1974 | } \ | |
eb44b959 AJ |
1975 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
1976 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 1977 | gen_reset_fpstatus(); \ |
8e703949 BS |
1978 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1979 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 1980 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 1981 | if (isfloat) { \ |
8e703949 BS |
1982 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1983 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 1984 | } \ |
af12906f AJ |
1985 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
1986 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
1987 | } |
1988 | ||
7c58044c JM |
1989 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
1990 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
1991 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 1992 | |
7c58044c | 1993 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 1994 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1995 | { \ |
76a66253 | 1996 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1997 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1998 | return; \ |
1999 | } \ | |
eb44b959 AJ |
2000 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2001 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2002 | gen_reset_fpstatus(); \ |
8e703949 BS |
2003 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2004 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2005 | cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2006 | if (isfloat) { \ |
8e703949 BS |
2007 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2008 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2009 | } \ |
af12906f AJ |
2010 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2011 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2012 | } |
7c58044c JM |
2013 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2014 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2015 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2016 | |
7c58044c | 2017 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2018 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2019 | { \ |
76a66253 | 2020 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2021 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2022 | return; \ |
2023 | } \ | |
eb44b959 AJ |
2024 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2025 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2026 | gen_reset_fpstatus(); \ |
8e703949 BS |
2027 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2028 | cpu_fpr[rA(ctx->opcode)], \ | |
2029 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2030 | if (isfloat) { \ |
8e703949 BS |
2031 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2032 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2033 | } \ |
af12906f AJ |
2034 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2035 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2036 | } |
7c58044c JM |
2037 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2038 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2039 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2040 | |
7c58044c | 2041 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 2042 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2043 | { \ |
76a66253 | 2044 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2045 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2046 | return; \ |
2047 | } \ | |
eb44b959 AJ |
2048 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2049 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2050 | gen_reset_fpstatus(); \ |
8e703949 BS |
2051 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2052 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2053 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2054 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2055 | } |
2056 | ||
7c58044c | 2057 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2058 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2059 | { \ |
76a66253 | 2060 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2061 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2062 | return; \ |
2063 | } \ | |
eb44b959 AJ |
2064 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2065 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2066 | gen_reset_fpstatus(); \ |
8e703949 BS |
2067 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2068 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2069 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2070 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2071 | } |
2072 | ||
9a64fbe4 | 2073 | /* fadd - fadds */ |
7c58044c | 2074 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2075 | /* fdiv - fdivs */ |
7c58044c | 2076 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2077 | /* fmul - fmuls */ |
7c58044c | 2078 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2079 | |
d7e4b87e | 2080 | /* fre */ |
7c58044c | 2081 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2082 | |
a750fc0b | 2083 | /* fres */ |
7c58044c | 2084 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2085 | |
a750fc0b | 2086 | /* frsqrte */ |
7c58044c JM |
2087 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2088 | ||
2089 | /* frsqrtes */ | |
99e300ef | 2090 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2091 | { |
af12906f | 2092 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2093 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2094 | return; |
2095 | } | |
eb44b959 AJ |
2096 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2097 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f | 2098 | gen_reset_fpstatus(); |
8e703949 BS |
2099 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2100 | cpu_fpr[rB(ctx->opcode)]); | |
2101 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2102 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2103 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
7c58044c | 2104 | } |
79aceca5 | 2105 | |
a750fc0b | 2106 | /* fsel */ |
7c58044c | 2107 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2108 | /* fsub - fsubs */ |
7c58044c | 2109 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2110 | /* Optional: */ |
99e300ef | 2111 | |
54623277 | 2112 | /* fsqrt */ |
99e300ef | 2113 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2114 | { |
76a66253 | 2115 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2116 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2117 | return; |
2118 | } | |
eb44b959 AJ |
2119 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2120 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2121 | gen_reset_fpstatus(); |
8e703949 BS |
2122 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2123 | cpu_fpr[rB(ctx->opcode)]); | |
af12906f | 2124 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
c7d344af | 2125 | } |
79aceca5 | 2126 | |
99e300ef | 2127 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2128 | { |
76a66253 | 2129 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2130 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2131 | return; |
2132 | } | |
eb44b959 AJ |
2133 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2134 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2135 | gen_reset_fpstatus(); |
8e703949 BS |
2136 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2137 | cpu_fpr[rB(ctx->opcode)]); | |
2138 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2139 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2140 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2141 | } |
2142 | ||
2143 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2144 | /* fmadd - fmadds */ |
7c58044c | 2145 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2146 | /* fmsub - fmsubs */ |
7c58044c | 2147 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2148 | /* fnmadd - fnmadds */ |
7c58044c | 2149 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2150 | /* fnmsub - fnmsubs */ |
7c58044c | 2151 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2152 | |
2153 | /*** Floating-Point round & convert ***/ | |
2154 | /* fctiw */ | |
7c58044c | 2155 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2156 | /* fctiwz */ |
7c58044c | 2157 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2158 | /* frsp */ |
7c58044c | 2159 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2160 | #if defined(TARGET_PPC64) |
2161 | /* fcfid */ | |
7c58044c | 2162 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
426613db | 2163 | /* fctid */ |
7c58044c | 2164 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
426613db | 2165 | /* fctidz */ |
7c58044c | 2166 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
426613db | 2167 | #endif |
79aceca5 | 2168 | |
d7e4b87e | 2169 | /* frin */ |
7c58044c | 2170 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2171 | /* friz */ |
7c58044c | 2172 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2173 | /* frip */ |
7c58044c | 2174 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2175 | /* frim */ |
7c58044c | 2176 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2177 | |
79aceca5 | 2178 | /*** Floating-Point compare ***/ |
99e300ef | 2179 | |
54623277 | 2180 | /* fcmpo */ |
99e300ef | 2181 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2182 | { |
330c483b | 2183 | TCGv_i32 crf; |
76a66253 | 2184 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2185 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2186 | return; |
2187 | } | |
eb44b959 AJ |
2188 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2189 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2190 | gen_reset_fpstatus(); |
9a819377 | 2191 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2192 | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2193 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2194 | tcg_temp_free_i32(crf); |
8e703949 | 2195 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2196 | } |
2197 | ||
2198 | /* fcmpu */ | |
99e300ef | 2199 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2200 | { |
330c483b | 2201 | TCGv_i32 crf; |
76a66253 | 2202 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2203 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2204 | return; |
2205 | } | |
eb44b959 AJ |
2206 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2207 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2208 | gen_reset_fpstatus(); |
9a819377 | 2209 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2210 | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2211 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2212 | tcg_temp_free_i32(crf); |
8e703949 | 2213 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2214 | } |
2215 | ||
9a64fbe4 FB |
2216 | /*** Floating-point move ***/ |
2217 | /* fabs */ | |
7c58044c | 2218 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2219 | static void gen_fabs(DisasContext *ctx) |
2220 | { | |
2221 | if (unlikely(!ctx->fpu_enabled)) { | |
2222 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2223 | return; | |
2224 | } | |
2225 | tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2226 | ~(1ULL << 63)); | |
2227 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2228 | } | |
9a64fbe4 FB |
2229 | |
2230 | /* fmr - fmr. */ | |
7c58044c | 2231 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2232 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2233 | { |
76a66253 | 2234 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2235 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2236 | return; |
2237 | } | |
af12906f AJ |
2238 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2239 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2240 | } |
2241 | ||
2242 | /* fnabs */ | |
7c58044c | 2243 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2244 | static void gen_fnabs(DisasContext *ctx) |
2245 | { | |
2246 | if (unlikely(!ctx->fpu_enabled)) { | |
2247 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2248 | return; | |
2249 | } | |
2250 | tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2251 | 1ULL << 63); | |
2252 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2253 | } | |
2254 | ||
9a64fbe4 | 2255 | /* fneg */ |
7c58044c | 2256 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2257 | static void gen_fneg(DisasContext *ctx) |
2258 | { | |
2259 | if (unlikely(!ctx->fpu_enabled)) { | |
2260 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2261 | return; | |
2262 | } | |
2263 | tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2264 | 1ULL << 63); | |
2265 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2266 | } | |
9a64fbe4 | 2267 | |
f0332888 AJ |
2268 | /* fcpsgn: PowerPC 2.05 specification */ |
2269 | /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ | |
2270 | static void gen_fcpsgn(DisasContext *ctx) | |
2271 | { | |
2272 | if (unlikely(!ctx->fpu_enabled)) { | |
2273 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2274 | return; | |
2275 | } | |
2276 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2277 | cpu_fpr[rB(ctx->opcode)], 0, 63); | |
2278 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2279 | } | |
2280 | ||
79aceca5 | 2281 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2282 | |
54623277 | 2283 | /* mcrfs */ |
99e300ef | 2284 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2285 | { |
30304420 | 2286 | TCGv tmp = tcg_temp_new(); |
7c58044c JM |
2287 | int bfa; |
2288 | ||
76a66253 | 2289 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2290 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2291 | return; |
2292 | } | |
7c58044c | 2293 | bfa = 4 * (7 - crfS(ctx->opcode)); |
30304420 DG |
2294 | tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); |
2295 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); | |
2296 | tcg_temp_free(tmp); | |
e1571908 | 2297 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
30304420 | 2298 | tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2299 | } |
2300 | ||
2301 | /* mffs */ | |
99e300ef | 2302 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2303 | { |
76a66253 | 2304 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2305 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2306 | return; |
2307 | } | |
7c58044c | 2308 | gen_reset_fpstatus(); |
30304420 | 2309 | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
af12906f | 2310 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2311 | } |
2312 | ||
2313 | /* mtfsb0 */ | |
99e300ef | 2314 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2315 | { |
fb0eaffc | 2316 | uint8_t crb; |
3b46e624 | 2317 | |
76a66253 | 2318 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2319 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2320 | return; |
2321 | } | |
6e35d524 | 2322 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2323 | gen_reset_fpstatus(); |
6e35d524 | 2324 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2325 | TCGv_i32 t0; |
2326 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2327 | gen_update_nip(ctx, ctx->nip - 4); | |
2328 | t0 = tcg_const_i32(crb); | |
8e703949 | 2329 | gen_helper_fpscr_clrbit(cpu_env, t0); |
6e35d524 AJ |
2330 | tcg_temp_free_i32(t0); |
2331 | } | |
7c58044c | 2332 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2333 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2334 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c | 2335 | } |
79aceca5 FB |
2336 | } |
2337 | ||
2338 | /* mtfsb1 */ | |
99e300ef | 2339 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2340 | { |
fb0eaffc | 2341 | uint8_t crb; |
3b46e624 | 2342 | |
76a66253 | 2343 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2344 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2345 | return; |
2346 | } | |
6e35d524 | 2347 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2348 | gen_reset_fpstatus(); |
2349 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2350 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2351 | TCGv_i32 t0; |
2352 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2353 | gen_update_nip(ctx, ctx->nip - 4); | |
2354 | t0 = tcg_const_i32(crb); | |
8e703949 | 2355 | gen_helper_fpscr_setbit(cpu_env, t0); |
0f2f39c2 | 2356 | tcg_temp_free_i32(t0); |
af12906f | 2357 | } |
7c58044c | 2358 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2359 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2360 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2361 | } |
2362 | /* We can raise a differed exception */ | |
8e703949 | 2363 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2364 | } |
2365 | ||
2366 | /* mtfsf */ | |
99e300ef | 2367 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2368 | { |
0f2f39c2 | 2369 | TCGv_i32 t0; |
7d08d856 | 2370 | int flm, l, w; |
af12906f | 2371 | |
76a66253 | 2372 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2373 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2374 | return; |
2375 | } | |
7d08d856 AJ |
2376 | flm = FPFLM(ctx->opcode); |
2377 | l = FPL(ctx->opcode); | |
2378 | w = FPW(ctx->opcode); | |
2379 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2380 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2381 | return; | |
2382 | } | |
eb44b959 AJ |
2383 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2384 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2385 | gen_reset_fpstatus(); |
7d08d856 AJ |
2386 | if (l) { |
2387 | t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); | |
2388 | } else { | |
2389 | t0 = tcg_const_i32(flm << (w * 8)); | |
2390 | } | |
8e703949 | 2391 | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2392 | tcg_temp_free_i32(t0); |
7c58044c | 2393 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2394 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2395 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2396 | } |
2397 | /* We can raise a differed exception */ | |
8e703949 | 2398 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2399 | } |
2400 | ||
2401 | /* mtfsfi */ | |
99e300ef | 2402 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2403 | { |
7d08d856 | 2404 | int bf, sh, w; |
0f2f39c2 AJ |
2405 | TCGv_i64 t0; |
2406 | TCGv_i32 t1; | |
7c58044c | 2407 | |
76a66253 | 2408 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2409 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2410 | return; |
2411 | } | |
7d08d856 AJ |
2412 | w = FPW(ctx->opcode); |
2413 | bf = FPBF(ctx->opcode); | |
2414 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2415 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2416 | return; | |
2417 | } | |
2418 | sh = (8 * w) + 7 - bf; | |
eb44b959 AJ |
2419 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2420 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2421 | gen_reset_fpstatus(); |
7d08d856 | 2422 | t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); |
af12906f | 2423 | t1 = tcg_const_i32(1 << sh); |
8e703949 | 2424 | gen_helper_store_fpscr(cpu_env, t0, t1); |
0f2f39c2 AJ |
2425 | tcg_temp_free_i64(t0); |
2426 | tcg_temp_free_i32(t1); | |
7c58044c | 2427 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2428 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2429 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2430 | } |
2431 | /* We can raise a differed exception */ | |
8e703949 | 2432 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2433 | } |
2434 | ||
76a66253 JM |
2435 | /*** Addressing modes ***/ |
2436 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2437 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2438 | target_long maskl) | |
76a66253 JM |
2439 | { |
2440 | target_long simm = SIMM(ctx->opcode); | |
2441 | ||
be147d08 | 2442 | simm &= ~maskl; |
76db3ba4 | 2443 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2444 | if (NARROW_MODE(ctx)) { |
2445 | simm = (uint32_t)simm; | |
2446 | } | |
e2be8d8d | 2447 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2448 | } else if (likely(simm != 0)) { |
e2be8d8d | 2449 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2450 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2451 | tcg_gen_ext32u_tl(EA, EA); |
2452 | } | |
76db3ba4 | 2453 | } else { |
c791fe84 | 2454 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2455 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2456 | } else { |
2457 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2458 | } | |
76db3ba4 | 2459 | } |
76a66253 JM |
2460 | } |
2461 | ||
636aa200 | 2462 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2463 | { |
76db3ba4 | 2464 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2465 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2466 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2467 | } else { |
2468 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2469 | } | |
76db3ba4 | 2470 | } else { |
e2be8d8d | 2471 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2472 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2473 | tcg_gen_ext32u_tl(EA, EA); |
2474 | } | |
76db3ba4 | 2475 | } |
76a66253 JM |
2476 | } |
2477 | ||
636aa200 | 2478 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2479 | { |
76db3ba4 | 2480 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2481 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2482 | } else if (NARROW_MODE(ctx)) { |
2483 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2484 | } else { |
c791fe84 | 2485 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2486 | } |
2487 | } | |
2488 | ||
636aa200 BS |
2489 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2490 | target_long val) | |
76db3ba4 AJ |
2491 | { |
2492 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2493 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2494 | tcg_gen_ext32u_tl(ret, ret); |
2495 | } | |
76a66253 JM |
2496 | } |
2497 | ||
636aa200 | 2498 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 AJ |
2499 | { |
2500 | int l1 = gen_new_label(); | |
2501 | TCGv t0 = tcg_temp_new(); | |
2502 | TCGv_i32 t1, t2; | |
2503 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2504 | gen_update_nip(ctx, ctx->nip - 4); | |
2505 | tcg_gen_andi_tl(t0, EA, mask); | |
2506 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2507 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2508 | t2 = tcg_const_i32(0); | |
e5f17ac6 | 2509 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2510 | tcg_temp_free_i32(t1); |
2511 | tcg_temp_free_i32(t2); | |
2512 | gen_set_label(l1); | |
2513 | tcg_temp_free(t0); | |
2514 | } | |
2515 | ||
7863667f | 2516 | /*** Integer load ***/ |
636aa200 | 2517 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2518 | { |
2519 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2520 | } | |
2521 | ||
636aa200 | 2522 | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2523 | { |
2524 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); | |
2525 | } | |
2526 | ||
636aa200 | 2527 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2528 | { |
2529 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); | |
2530 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2531 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2532 | } |
b61f2753 AJ |
2533 | } |
2534 | ||
636aa200 | 2535 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2536 | { |
76db3ba4 | 2537 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2538 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
fa3966a3 | 2539 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2540 | tcg_gen_ext16s_tl(arg1, arg1); |
76db3ba4 AJ |
2541 | } else { |
2542 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); | |
2543 | } | |
b61f2753 AJ |
2544 | } |
2545 | ||
636aa200 | 2546 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2547 | { |
76db3ba4 AJ |
2548 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2549 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2550 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2551 | } |
b61f2753 AJ |
2552 | } |
2553 | ||
636aa200 | 2554 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2555 | { |
a457e7ee | 2556 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2557 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
fa3966a3 AJ |
2558 | tcg_gen_bswap32_tl(arg1, arg1); |
2559 | tcg_gen_ext32s_tl(arg1, arg1); | |
b61f2753 | 2560 | } else |
76db3ba4 | 2561 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2562 | } |
2563 | ||
636aa200 | 2564 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2565 | { |
76db3ba4 AJ |
2566 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2567 | if (unlikely(ctx->le_mode)) { | |
66896cb8 | 2568 | tcg_gen_bswap64_i64(arg1, arg1); |
76db3ba4 | 2569 | } |
b61f2753 AJ |
2570 | } |
2571 | ||
636aa200 | 2572 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2573 | { |
76db3ba4 | 2574 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2575 | } |
2576 | ||
636aa200 | 2577 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2578 | { |
76db3ba4 | 2579 | if (unlikely(ctx->le_mode)) { |
76db3ba4 AJ |
2580 | TCGv t0 = tcg_temp_new(); |
2581 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2582 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2583 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2584 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2585 | } else { |
2586 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2587 | } | |
b61f2753 AJ |
2588 | } |
2589 | ||
636aa200 | 2590 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2591 | { |
76db3ba4 | 2592 | if (unlikely(ctx->le_mode)) { |
fa3966a3 AJ |
2593 | TCGv t0 = tcg_temp_new(); |
2594 | tcg_gen_ext32u_tl(t0, arg1); | |
2595 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2596 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2597 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2598 | } else { |
2599 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2600 | } | |
b61f2753 AJ |
2601 | } |
2602 | ||
636aa200 | 2603 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2604 | { |
76db3ba4 | 2605 | if (unlikely(ctx->le_mode)) { |
a7812ae4 | 2606 | TCGv_i64 t0 = tcg_temp_new_i64(); |
66896cb8 | 2607 | tcg_gen_bswap64_i64(t0, arg1); |
76db3ba4 | 2608 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
a7812ae4 | 2609 | tcg_temp_free_i64(t0); |
b61f2753 | 2610 | } else |
76db3ba4 | 2611 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2612 | } |
2613 | ||
0c8aacd4 | 2614 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2615 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2616 | { \ |
76db3ba4 AJ |
2617 | TCGv EA; \ |
2618 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2619 | EA = tcg_temp_new(); \ | |
2620 | gen_addr_imm_index(ctx, EA, 0); \ | |
2621 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2622 | tcg_temp_free(EA); \ |
79aceca5 FB |
2623 | } |
2624 | ||
0c8aacd4 | 2625 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2626 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2627 | { \ |
b61f2753 | 2628 | TCGv EA; \ |
76a66253 JM |
2629 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2630 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2631 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2632 | return; \ |
9a64fbe4 | 2633 | } \ |
76db3ba4 | 2634 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2635 | EA = tcg_temp_new(); \ |
9d53c753 | 2636 | if (type == PPC_64B) \ |
76db3ba4 | 2637 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2638 | else \ |
76db3ba4 AJ |
2639 | gen_addr_imm_index(ctx, EA, 0); \ |
2640 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2641 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2642 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2643 | } |
2644 | ||
0c8aacd4 | 2645 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2646 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2647 | { \ |
b61f2753 | 2648 | TCGv EA; \ |
76a66253 JM |
2649 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2650 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2651 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2652 | return; \ |
9a64fbe4 | 2653 | } \ |
76db3ba4 | 2654 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2655 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2656 | gen_addr_reg_index(ctx, EA); \ |
2657 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2658 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2659 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2660 | } |
2661 | ||
cd6e9320 | 2662 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
99e300ef | 2663 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2664 | { \ |
76db3ba4 AJ |
2665 | TCGv EA; \ |
2666 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2667 | EA = tcg_temp_new(); \ | |
2668 | gen_addr_reg_index(ctx, EA); \ | |
2669 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2670 | tcg_temp_free(EA); \ |
79aceca5 | 2671 | } |
cd6e9320 TH |
2672 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2673 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2674 | |
0c8aacd4 AJ |
2675 | #define GEN_LDS(name, ldop, op, type) \ |
2676 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2677 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2678 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2679 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2680 | |
2681 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2682 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2683 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2684 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2685 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2686 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2687 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2688 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2689 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2690 | /* lwaux */ |
0c8aacd4 | 2691 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2692 | /* lwax */ |
0c8aacd4 | 2693 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2694 | /* ldux */ |
0c8aacd4 | 2695 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2696 | /* ldx */ |
0c8aacd4 | 2697 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2698 | |
2699 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2700 | { |
b61f2753 | 2701 | TCGv EA; |
d9bce9d9 JM |
2702 | if (Rc(ctx->opcode)) { |
2703 | if (unlikely(rA(ctx->opcode) == 0 || | |
2704 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2705 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2706 | return; |
2707 | } | |
2708 | } | |
76db3ba4 | 2709 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2710 | EA = tcg_temp_new(); |
76db3ba4 | 2711 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2712 | if (ctx->opcode & 0x02) { |
2713 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2714 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2715 | } else { |
2716 | /* ld - ldu */ | |
76db3ba4 | 2717 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2718 | } |
d9bce9d9 | 2719 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2720 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2721 | tcg_temp_free(EA); | |
d9bce9d9 | 2722 | } |
99e300ef | 2723 | |
54623277 | 2724 | /* lq */ |
99e300ef | 2725 | static void gen_lq(DisasContext *ctx) |
be147d08 JM |
2726 | { |
2727 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2728 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2729 | #else |
2730 | int ra, rd; | |
b61f2753 | 2731 | TCGv EA; |
be147d08 JM |
2732 | |
2733 | /* Restore CPU state */ | |
76db3ba4 | 2734 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2735 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2736 | return; |
2737 | } | |
2738 | ra = rA(ctx->opcode); | |
2739 | rd = rD(ctx->opcode); | |
2740 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2741 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2742 | return; |
2743 | } | |
76db3ba4 | 2744 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2745 | /* Little-endian mode is not handled */ |
e06fcd75 | 2746 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2747 | return; |
2748 | } | |
76db3ba4 | 2749 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2750 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2751 | gen_addr_imm_index(ctx, EA, 0x0F); |
2752 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2753 | gen_addr_add(ctx, EA, EA, 8); | |
2754 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
b61f2753 | 2755 | tcg_temp_free(EA); |
be147d08 JM |
2756 | #endif |
2757 | } | |
d9bce9d9 | 2758 | #endif |
79aceca5 FB |
2759 | |
2760 | /*** Integer store ***/ | |
0c8aacd4 | 2761 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2762 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2763 | { \ |
76db3ba4 AJ |
2764 | TCGv EA; \ |
2765 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2766 | EA = tcg_temp_new(); \ | |
2767 | gen_addr_imm_index(ctx, EA, 0); \ | |
2768 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2769 | tcg_temp_free(EA); \ |
79aceca5 FB |
2770 | } |
2771 | ||
0c8aacd4 | 2772 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2773 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2774 | { \ |
b61f2753 | 2775 | TCGv EA; \ |
76a66253 | 2776 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2777 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2778 | return; \ |
9a64fbe4 | 2779 | } \ |
76db3ba4 | 2780 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2781 | EA = tcg_temp_new(); \ |
9d53c753 | 2782 | if (type == PPC_64B) \ |
76db3ba4 | 2783 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2784 | else \ |
76db3ba4 AJ |
2785 | gen_addr_imm_index(ctx, EA, 0); \ |
2786 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2787 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2788 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2789 | } |
2790 | ||
0c8aacd4 | 2791 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2792 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2793 | { \ |
b61f2753 | 2794 | TCGv EA; \ |
76a66253 | 2795 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2796 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2797 | return; \ |
9a64fbe4 | 2798 | } \ |
76db3ba4 | 2799 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2800 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2801 | gen_addr_reg_index(ctx, EA); \ |
2802 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2803 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2804 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2805 | } |
2806 | ||
cd6e9320 TH |
2807 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
2808 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 2809 | { \ |
76db3ba4 AJ |
2810 | TCGv EA; \ |
2811 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2812 | EA = tcg_temp_new(); \ | |
2813 | gen_addr_reg_index(ctx, EA); \ | |
2814 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2815 | tcg_temp_free(EA); \ |
79aceca5 | 2816 | } |
cd6e9320 TH |
2817 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
2818 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2819 | |
0c8aacd4 AJ |
2820 | #define GEN_STS(name, stop, op, type) \ |
2821 | GEN_ST(name, stop, op | 0x20, type); \ | |
2822 | GEN_STU(name, stop, op | 0x21, type); \ | |
2823 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2824 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2825 | |
2826 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2827 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2828 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2829 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2830 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2831 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2832 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
2833 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2834 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
2835 | |
2836 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2837 | { |
be147d08 | 2838 | int rs; |
b61f2753 | 2839 | TCGv EA; |
be147d08 JM |
2840 | |
2841 | rs = rS(ctx->opcode); | |
2842 | if ((ctx->opcode & 0x3) == 0x2) { | |
2843 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2844 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2845 | #else |
2846 | /* stq */ | |
76db3ba4 | 2847 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2848 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2849 | return; |
2850 | } | |
2851 | if (unlikely(rs & 1)) { | |
e06fcd75 | 2852 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2853 | return; |
2854 | } | |
76db3ba4 | 2855 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2856 | /* Little-endian mode is not handled */ |
e06fcd75 | 2857 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2858 | return; |
2859 | } | |
76db3ba4 | 2860 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2861 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2862 | gen_addr_imm_index(ctx, EA, 0x03); |
2863 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
2864 | gen_addr_add(ctx, EA, EA, 8); | |
2865 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
b61f2753 | 2866 | tcg_temp_free(EA); |
be147d08 JM |
2867 | #endif |
2868 | } else { | |
2869 | /* std / stdu */ | |
2870 | if (Rc(ctx->opcode)) { | |
2871 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2872 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2873 | return; |
2874 | } | |
2875 | } | |
76db3ba4 | 2876 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2877 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2878 | gen_addr_imm_index(ctx, EA, 0x03); |
2879 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 2880 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2881 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2882 | tcg_temp_free(EA); | |
d9bce9d9 | 2883 | } |
d9bce9d9 JM |
2884 | } |
2885 | #endif | |
79aceca5 FB |
2886 | /*** Integer load and store with byte reverse ***/ |
2887 | /* lhbrx */ | |
86178a57 | 2888 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2889 | { |
76db3ba4 AJ |
2890 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2891 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2892 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2893 | } |
b61f2753 | 2894 | } |
0c8aacd4 | 2895 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2896 | |
79aceca5 | 2897 | /* lwbrx */ |
86178a57 | 2898 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2899 | { |
76db3ba4 AJ |
2900 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2901 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2902 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2903 | } |
b61f2753 | 2904 | } |
0c8aacd4 | 2905 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2906 | |
cd6e9320 TH |
2907 | #if defined(TARGET_PPC64) |
2908 | /* ldbrx */ | |
2909 | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2910 | { | |
2911 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); | |
2912 | if (likely(!ctx->le_mode)) { | |
2913 | tcg_gen_bswap64_tl(arg1, arg1); | |
2914 | } | |
2915 | } | |
2916 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); | |
2917 | #endif /* TARGET_PPC64 */ | |
2918 | ||
79aceca5 | 2919 | /* sthbrx */ |
86178a57 | 2920 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2921 | { |
76db3ba4 | 2922 | if (likely(!ctx->le_mode)) { |
76db3ba4 AJ |
2923 | TCGv t0 = tcg_temp_new(); |
2924 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2925 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2926 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2927 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2928 | } else { |
2929 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2930 | } | |
b61f2753 | 2931 | } |
0c8aacd4 | 2932 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 2933 | |
79aceca5 | 2934 | /* stwbrx */ |
86178a57 | 2935 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2936 | { |
76db3ba4 | 2937 | if (likely(!ctx->le_mode)) { |
fa3966a3 AJ |
2938 | TCGv t0 = tcg_temp_new(); |
2939 | tcg_gen_ext32u_tl(t0, arg1); | |
2940 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2941 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2942 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2943 | } else { |
2944 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2945 | } | |
b61f2753 | 2946 | } |
0c8aacd4 | 2947 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 | 2948 | |
cd6e9320 TH |
2949 | #if defined(TARGET_PPC64) |
2950 | /* stdbrx */ | |
2951 | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2952 | { | |
2953 | if (likely(!ctx->le_mode)) { | |
2954 | TCGv t0 = tcg_temp_new(); | |
2955 | tcg_gen_bswap64_tl(t0, arg1); | |
2956 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); | |
2957 | tcg_temp_free(t0); | |
2958 | } else { | |
2959 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); | |
2960 | } | |
2961 | } | |
2962 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); | |
2963 | #endif /* TARGET_PPC64 */ | |
2964 | ||
79aceca5 | 2965 | /*** Integer load and store multiple ***/ |
99e300ef | 2966 | |
54623277 | 2967 | /* lmw */ |
99e300ef | 2968 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2969 | { |
76db3ba4 AJ |
2970 | TCGv t0; |
2971 | TCGv_i32 t1; | |
2972 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2973 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2974 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2975 | t0 = tcg_temp_new(); |
2976 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2977 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2978 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2979 | tcg_temp_free(t0); |
2980 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2981 | } |
2982 | ||
2983 | /* stmw */ | |
99e300ef | 2984 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2985 | { |
76db3ba4 AJ |
2986 | TCGv t0; |
2987 | TCGv_i32 t1; | |
2988 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2989 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2990 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2991 | t0 = tcg_temp_new(); |
2992 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2993 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2994 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2995 | tcg_temp_free(t0); |
2996 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2997 | } |
2998 | ||
2999 | /*** Integer load and store strings ***/ | |
54623277 | 3000 | |
79aceca5 | 3001 | /* lswi */ |
3fc6c082 | 3002 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
3003 | * rA is in the range of registers to be loaded. |
3004 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
3005 | * For now, I'll follow the spec... | |
3006 | */ | |
99e300ef | 3007 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 3008 | { |
dfbc799d AJ |
3009 | TCGv t0; |
3010 | TCGv_i32 t1, t2; | |
79aceca5 FB |
3011 | int nb = NB(ctx->opcode); |
3012 | int start = rD(ctx->opcode); | |
9a64fbe4 | 3013 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3014 | int nr; |
3015 | ||
3016 | if (nb == 0) | |
3017 | nb = 32; | |
3018 | nr = nb / 4; | |
76a66253 JM |
3019 | if (unlikely(((start + nr) > 32 && |
3020 | start <= ra && (start + nr - 32) > ra) || | |
3021 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 3022 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3023 | return; |
297d8e62 | 3024 | } |
76db3ba4 | 3025 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 3026 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3027 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 3028 | t0 = tcg_temp_new(); |
76db3ba4 | 3029 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
3030 | t1 = tcg_const_i32(nb); |
3031 | t2 = tcg_const_i32(start); | |
2f5a189c | 3032 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3033 | tcg_temp_free(t0); |
3034 | tcg_temp_free_i32(t1); | |
3035 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3036 | } |
3037 | ||
3038 | /* lswx */ | |
99e300ef | 3039 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3040 | { |
76db3ba4 AJ |
3041 | TCGv t0; |
3042 | TCGv_i32 t1, t2, t3; | |
3043 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3044 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3045 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3046 | t0 = tcg_temp_new(); |
3047 | gen_addr_reg_index(ctx, t0); | |
3048 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3049 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3050 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 3051 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
3052 | tcg_temp_free(t0); |
3053 | tcg_temp_free_i32(t1); | |
3054 | tcg_temp_free_i32(t2); | |
3055 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3056 | } |
3057 | ||
3058 | /* stswi */ | |
99e300ef | 3059 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3060 | { |
76db3ba4 AJ |
3061 | TCGv t0; |
3062 | TCGv_i32 t1, t2; | |
4b3686fa | 3063 | int nb = NB(ctx->opcode); |
76db3ba4 | 3064 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 3065 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3066 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3067 | t0 = tcg_temp_new(); |
3068 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3069 | if (nb == 0) |
3070 | nb = 32; | |
dfbc799d | 3071 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3072 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3073 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3074 | tcg_temp_free(t0); |
3075 | tcg_temp_free_i32(t1); | |
3076 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3077 | } |
3078 | ||
3079 | /* stswx */ | |
99e300ef | 3080 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3081 | { |
76db3ba4 AJ |
3082 | TCGv t0; |
3083 | TCGv_i32 t1, t2; | |
3084 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3085 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3086 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3087 | t0 = tcg_temp_new(); |
3088 | gen_addr_reg_index(ctx, t0); | |
3089 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3090 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3091 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3092 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3093 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3094 | tcg_temp_free(t0); |
3095 | tcg_temp_free_i32(t1); | |
3096 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3097 | } |
3098 | ||
3099 | /*** Memory synchronisation ***/ | |
3100 | /* eieio */ | |
99e300ef | 3101 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3102 | { |
79aceca5 FB |
3103 | } |
3104 | ||
3105 | /* isync */ | |
99e300ef | 3106 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3107 | { |
e06fcd75 | 3108 | gen_stop_exception(ctx); |
79aceca5 FB |
3109 | } |
3110 | ||
111bfab3 | 3111 | /* lwarx */ |
99e300ef | 3112 | static void gen_lwarx(DisasContext *ctx) |
79aceca5 | 3113 | { |
76db3ba4 | 3114 | TCGv t0; |
18b21a2f | 3115 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3116 | gen_set_access_type(ctx, ACCESS_RES); |
3117 | t0 = tcg_temp_local_new(); | |
3118 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3119 | gen_check_align(ctx, t0, 0x03); |
18b21a2f | 3120 | gen_qemu_ld32u(ctx, gpr, t0); |
cf360a32 | 3121 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3122 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3123 | tcg_temp_free(t0); |
79aceca5 FB |
3124 | } |
3125 | ||
4425265b NF |
3126 | #if defined(CONFIG_USER_ONLY) |
3127 | static void gen_conditional_store (DisasContext *ctx, TCGv EA, | |
3128 | int reg, int size) | |
3129 | { | |
3130 | TCGv t0 = tcg_temp_new(); | |
3131 | uint32_t save_exception = ctx->exception; | |
3132 | ||
1328c2bf | 3133 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
4425265b | 3134 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
1328c2bf | 3135 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b NF |
3136 | tcg_temp_free(t0); |
3137 | gen_update_nip(ctx, ctx->nip-4); | |
3138 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3139 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3140 | ctx->exception = save_exception; | |
3141 | } | |
3142 | #endif | |
3143 | ||
79aceca5 | 3144 | /* stwcx. */ |
e8eaa2c0 | 3145 | static void gen_stwcx_(DisasContext *ctx) |
79aceca5 | 3146 | { |
76db3ba4 AJ |
3147 | TCGv t0; |
3148 | gen_set_access_type(ctx, ACCESS_RES); | |
3149 | t0 = tcg_temp_local_new(); | |
3150 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3151 | gen_check_align(ctx, t0, 0x03); |
4425265b NF |
3152 | #if defined(CONFIG_USER_ONLY) |
3153 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); | |
3154 | #else | |
3155 | { | |
3156 | int l1; | |
3157 | ||
da91a00f | 3158 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3159 | l1 = gen_new_label(); |
3160 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3161 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3162 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3163 | gen_set_label(l1); | |
3164 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3165 | } | |
3166 | #endif | |
cf360a32 | 3167 | tcg_temp_free(t0); |
79aceca5 FB |
3168 | } |
3169 | ||
426613db | 3170 | #if defined(TARGET_PPC64) |
426613db | 3171 | /* ldarx */ |
99e300ef | 3172 | static void gen_ldarx(DisasContext *ctx) |
426613db | 3173 | { |
76db3ba4 | 3174 | TCGv t0; |
18b21a2f | 3175 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3176 | gen_set_access_type(ctx, ACCESS_RES); |
3177 | t0 = tcg_temp_local_new(); | |
3178 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3179 | gen_check_align(ctx, t0, 0x07); |
18b21a2f | 3180 | gen_qemu_ld64(ctx, gpr, t0); |
cf360a32 | 3181 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3182 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3183 | tcg_temp_free(t0); |
426613db JM |
3184 | } |
3185 | ||
3186 | /* stdcx. */ | |
e8eaa2c0 | 3187 | static void gen_stdcx_(DisasContext *ctx) |
426613db | 3188 | { |
76db3ba4 AJ |
3189 | TCGv t0; |
3190 | gen_set_access_type(ctx, ACCESS_RES); | |
3191 | t0 = tcg_temp_local_new(); | |
3192 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3193 | gen_check_align(ctx, t0, 0x07); |
4425265b NF |
3194 | #if defined(CONFIG_USER_ONLY) |
3195 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); | |
3196 | #else | |
3197 | { | |
3198 | int l1; | |
da91a00f | 3199 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3200 | l1 = gen_new_label(); |
3201 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3202 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3203 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3204 | gen_set_label(l1); | |
3205 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3206 | } | |
3207 | #endif | |
cf360a32 | 3208 | tcg_temp_free(t0); |
426613db JM |
3209 | } |
3210 | #endif /* defined(TARGET_PPC64) */ | |
3211 | ||
79aceca5 | 3212 | /* sync */ |
99e300ef | 3213 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3214 | { |
79aceca5 FB |
3215 | } |
3216 | ||
0db1b20e | 3217 | /* wait */ |
99e300ef | 3218 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3219 | { |
931ff272 | 3220 | TCGv_i32 t0 = tcg_temp_new_i32(); |
259186a7 AF |
3221 | tcg_gen_st_i32(t0, cpu_env, |
3222 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3223 | tcg_temp_free_i32(t0); |
0db1b20e | 3224 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3225 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3226 | } |
3227 | ||
79aceca5 | 3228 | /*** Floating-point load ***/ |
a0d7d5a7 | 3229 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3230 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3231 | { \ |
a0d7d5a7 | 3232 | TCGv EA; \ |
76a66253 | 3233 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3234 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3235 | return; \ |
3236 | } \ | |
76db3ba4 | 3237 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3238 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3239 | gen_addr_imm_index(ctx, EA, 0); \ |
3240 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3241 | tcg_temp_free(EA); \ |
79aceca5 FB |
3242 | } |
3243 | ||
a0d7d5a7 | 3244 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3245 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3246 | { \ |
a0d7d5a7 | 3247 | TCGv EA; \ |
76a66253 | 3248 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3249 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3250 | return; \ |
3251 | } \ | |
76a66253 | 3252 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3253 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3254 | return; \ |
9a64fbe4 | 3255 | } \ |
76db3ba4 | 3256 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3257 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3258 | gen_addr_imm_index(ctx, EA, 0); \ |
3259 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3260 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3261 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3262 | } |
3263 | ||
a0d7d5a7 | 3264 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3265 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3266 | { \ |
a0d7d5a7 | 3267 | TCGv EA; \ |
76a66253 | 3268 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3269 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3270 | return; \ |
3271 | } \ | |
76a66253 | 3272 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3273 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3274 | return; \ |
9a64fbe4 | 3275 | } \ |
76db3ba4 | 3276 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3277 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3278 | gen_addr_reg_index(ctx, EA); \ |
3279 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3280 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3281 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3282 | } |
3283 | ||
a0d7d5a7 | 3284 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3285 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3286 | { \ |
a0d7d5a7 | 3287 | TCGv EA; \ |
76a66253 | 3288 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3289 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3290 | return; \ |
3291 | } \ | |
76db3ba4 | 3292 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3293 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3294 | gen_addr_reg_index(ctx, EA); \ |
3295 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3296 | tcg_temp_free(EA); \ |
79aceca5 FB |
3297 | } |
3298 | ||
a0d7d5a7 AJ |
3299 | #define GEN_LDFS(name, ldop, op, type) \ |
3300 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3301 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3302 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3303 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3304 | ||
636aa200 | 3305 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3306 | { |
3307 | TCGv t0 = tcg_temp_new(); | |
3308 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3309 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3310 | tcg_gen_trunc_tl_i32(t1, t0); |
3311 | tcg_temp_free(t0); | |
8e703949 | 3312 | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
a0d7d5a7 AJ |
3313 | tcg_temp_free_i32(t1); |
3314 | } | |
79aceca5 | 3315 | |
a0d7d5a7 AJ |
3316 | /* lfd lfdu lfdux lfdx */ |
3317 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3318 | /* lfs lfsu lfsux lfsx */ | |
3319 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 | 3320 | |
05050ee8 AJ |
3321 | /* lfdp */ |
3322 | static void gen_lfdp(DisasContext *ctx) | |
3323 | { | |
3324 | TCGv EA; | |
3325 | if (unlikely(!ctx->fpu_enabled)) { | |
3326 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3327 | return; | |
3328 | } | |
3329 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3330 | EA = tcg_temp_new(); | |
3331 | gen_addr_imm_index(ctx, EA, 0); \ | |
3332 | if (unlikely(ctx->le_mode)) { | |
3333 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3334 | tcg_gen_addi_tl(EA, EA, 8); | |
3335 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3336 | } else { | |
3337 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3338 | tcg_gen_addi_tl(EA, EA, 8); | |
3339 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3340 | } | |
3341 | tcg_temp_free(EA); | |
3342 | } | |
3343 | ||
3344 | /* lfdpx */ | |
3345 | static void gen_lfdpx(DisasContext *ctx) | |
3346 | { | |
3347 | TCGv EA; | |
3348 | if (unlikely(!ctx->fpu_enabled)) { | |
3349 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3350 | return; | |
3351 | } | |
3352 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3353 | EA = tcg_temp_new(); | |
3354 | gen_addr_reg_index(ctx, EA); | |
3355 | if (unlikely(ctx->le_mode)) { | |
3356 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3357 | tcg_gen_addi_tl(EA, EA, 8); | |
3358 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3359 | } else { | |
3360 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3361 | tcg_gen_addi_tl(EA, EA, 8); | |
3362 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3363 | } | |
3364 | tcg_temp_free(EA); | |
3365 | } | |
3366 | ||
199f830d AJ |
3367 | /* lfiwax */ |
3368 | static void gen_lfiwax(DisasContext *ctx) | |
3369 | { | |
3370 | TCGv EA; | |
3371 | TCGv t0; | |
3372 | if (unlikely(!ctx->fpu_enabled)) { | |
3373 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3374 | return; | |
3375 | } | |
3376 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3377 | EA = tcg_temp_new(); | |
3378 | t0 = tcg_temp_new(); | |
3379 | gen_addr_reg_index(ctx, EA); | |
909eedb7 | 3380 | gen_qemu_ld32s(ctx, t0, EA); |
199f830d | 3381 | tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); |
199f830d AJ |
3382 | tcg_temp_free(EA); |
3383 | tcg_temp_free(t0); | |
3384 | } | |
3385 | ||
79aceca5 | 3386 | /*** Floating-point store ***/ |
a0d7d5a7 | 3387 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3388 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3389 | { \ |
a0d7d5a7 | 3390 | TCGv EA; \ |
76a66253 | 3391 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3392 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3393 | return; \ |
3394 | } \ | |
76db3ba4 | 3395 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3396 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3397 | gen_addr_imm_index(ctx, EA, 0); \ |
3398 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3399 | tcg_temp_free(EA); \ |
79aceca5 FB |
3400 | } |
3401 | ||
a0d7d5a7 | 3402 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3403 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3404 | { \ |
a0d7d5a7 | 3405 | TCGv EA; \ |
76a66253 | 3406 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3407 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3408 | return; \ |
3409 | } \ | |
76a66253 | 3410 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3411 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3412 | return; \ |
9a64fbe4 | 3413 | } \ |
76db3ba4 | 3414 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3415 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3416 | gen_addr_imm_index(ctx, EA, 0); \ |
3417 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3418 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3419 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3420 | } |
3421 | ||
a0d7d5a7 | 3422 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3423 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3424 | { \ |
a0d7d5a7 | 3425 | TCGv EA; \ |
76a66253 | 3426 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3427 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3428 | return; \ |
3429 | } \ | |
76a66253 | 3430 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3431 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3432 | return; \ |
9a64fbe4 | 3433 | } \ |
76db3ba4 | 3434 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3435 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3436 | gen_addr_reg_index(ctx, EA); \ |
3437 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3438 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3439 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3440 | } |
3441 | ||
a0d7d5a7 | 3442 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3443 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3444 | { \ |
a0d7d5a7 | 3445 | TCGv EA; \ |
76a66253 | 3446 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3447 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3448 | return; \ |
3449 | } \ | |
76db3ba4 | 3450 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3451 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3452 | gen_addr_reg_index(ctx, EA); \ |
3453 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3454 | tcg_temp_free(EA); \ |
79aceca5 FB |
3455 | } |
3456 | ||
a0d7d5a7 AJ |
3457 | #define GEN_STFS(name, stop, op, type) \ |
3458 | GEN_STF(name, stop, op | 0x20, type); \ | |
3459 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3460 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3461 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3462 | ||
636aa200 | 3463 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3464 | { |
3465 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3466 | TCGv t1 = tcg_temp_new(); | |
8e703949 | 3467 | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
a0d7d5a7 AJ |
3468 | tcg_gen_extu_i32_tl(t1, t0); |
3469 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3470 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3471 | tcg_temp_free(t1); |
3472 | } | |
79aceca5 FB |
3473 | |
3474 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3475 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3476 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3477 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 | 3478 | |
44bc0c4d AJ |
3479 | /* stfdp */ |
3480 | static void gen_stfdp(DisasContext *ctx) | |
3481 | { | |
3482 | TCGv EA; | |
3483 | if (unlikely(!ctx->fpu_enabled)) { | |
3484 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3485 | return; | |
3486 | } | |
3487 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3488 | EA = tcg_temp_new(); | |
3489 | gen_addr_imm_index(ctx, EA, 0); \ | |
3490 | if (unlikely(ctx->le_mode)) { | |
3491 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3492 | tcg_gen_addi_tl(EA, EA, 8); | |
3493 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3494 | } else { | |
3495 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3496 | tcg_gen_addi_tl(EA, EA, 8); | |
3497 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3498 | } | |
3499 | tcg_temp_free(EA); | |
3500 | } | |
3501 | ||
3502 | /* stfdpx */ | |
3503 | static void gen_stfdpx(DisasContext *ctx) | |
3504 | { | |
3505 | TCGv EA; | |
3506 | if (unlikely(!ctx->fpu_enabled)) { | |
3507 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3508 | return; | |
3509 | } | |
3510 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3511 | EA = tcg_temp_new(); | |
3512 | gen_addr_reg_index(ctx, EA); | |
3513 | if (unlikely(ctx->le_mode)) { | |
3514 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3515 | tcg_gen_addi_tl(EA, EA, 8); | |
3516 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3517 | } else { | |
3518 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3519 | tcg_gen_addi_tl(EA, EA, 8); | |
3520 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3521 | } | |
3522 | tcg_temp_free(EA); | |
3523 | } | |
3524 | ||
79aceca5 | 3525 | /* Optional: */ |
636aa200 | 3526 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3527 | { |
3528 | TCGv t0 = tcg_temp_new(); | |
3529 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3530 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3531 | tcg_temp_free(t0); |
3532 | } | |
79aceca5 | 3533 | /* stfiwx */ |
a0d7d5a7 | 3534 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 | 3535 | |
697ab892 DG |
3536 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3537 | { | |
3538 | #if defined(TARGET_PPC64) | |
3539 | if (ctx->has_cfar) | |
3540 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3541 | #endif | |
3542 | } | |
3543 | ||
79aceca5 | 3544 | /*** Branch ***/ |
636aa200 | 3545 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 FB |
3546 | { |
3547 | TranslationBlock *tb; | |
3548 | tb = ctx->tb; | |
e0c8f9ce | 3549 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3550 | dest = (uint32_t) dest; |
e0c8f9ce | 3551 | } |
57fec1fe | 3552 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3553 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3554 | tcg_gen_goto_tb(n); |
a2ffb812 | 3555 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
4b4a72e5 | 3556 | tcg_gen_exit_tb((tcg_target_long)tb + n); |
c1942362 | 3557 | } else { |
a2ffb812 | 3558 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3559 | if (unlikely(ctx->singlestep_enabled)) { |
3560 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3561 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3562 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3563 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
8cbcb4fa AJ |
3564 | target_ulong tmp = ctx->nip; |
3565 | ctx->nip = dest; | |
e06fcd75 | 3566 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3567 | ctx->nip = tmp; |
3568 | } | |
3569 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3570 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3571 | } |
3572 | } | |
57fec1fe | 3573 | tcg_gen_exit_tb(0); |
c1942362 | 3574 | } |
c53be334 FB |
3575 | } |
3576 | ||
636aa200 | 3577 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3578 | { |
e0c8f9ce RH |
3579 | if (NARROW_MODE(ctx)) { |
3580 | nip = (uint32_t)nip; | |
3581 | } | |
3582 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3583 | } |
3584 | ||
79aceca5 | 3585 | /* b ba bl bla */ |
99e300ef | 3586 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3587 | { |
76a66253 | 3588 | target_ulong li, target; |
38a64f9d | 3589 | |
8cbcb4fa | 3590 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3591 | /* sign extend LI */ |
e0c8f9ce RH |
3592 | li = LI(ctx->opcode); |
3593 | li = (li ^ 0x02000000) - 0x02000000; | |
3594 | if (likely(AA(ctx->opcode) == 0)) { | |
046d6672 | 3595 | target = ctx->nip + li - 4; |
e0c8f9ce | 3596 | } else { |
9a64fbe4 | 3597 | target = li; |
e0c8f9ce RH |
3598 | } |
3599 | if (LK(ctx->opcode)) { | |
e1833e1f | 3600 | gen_setlr(ctx, ctx->nip); |
e0c8f9ce | 3601 | } |
697ab892 | 3602 | gen_update_cfar(ctx, ctx->nip); |
c1942362 | 3603 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3604 | } |
3605 | ||
e98a6e40 FB |
3606 | #define BCOND_IM 0 |
3607 | #define BCOND_LR 1 | |
3608 | #define BCOND_CTR 2 | |
3609 | ||
636aa200 | 3610 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3611 | { |
d9bce9d9 | 3612 | uint32_t bo = BO(ctx->opcode); |
05f92404 | 3613 | int l1; |
a2ffb812 | 3614 | TCGv target; |
e98a6e40 | 3615 | |
8cbcb4fa | 3616 | ctx->exception = POWERPC_EXCP_BRANCH; |
a2ffb812 | 3617 | if (type == BCOND_LR || type == BCOND_CTR) { |
a7812ae4 | 3618 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3619 | if (type == BCOND_CTR) |
3620 | tcg_gen_mov_tl(target, cpu_ctr); | |
3621 | else | |
3622 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3623 | } else { |
3624 | TCGV_UNUSED(target); | |
e98a6e40 | 3625 | } |
e1833e1f JM |
3626 | if (LK(ctx->opcode)) |
3627 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3628 | l1 = gen_new_label(); |
3629 | if ((bo & 0x4) == 0) { | |
3630 | /* Decrement and test CTR */ | |
a7812ae4 | 3631 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3632 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3633 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3634 | return; |
3635 | } | |
3636 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3637 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3638 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3639 | } else { |
a2ffb812 | 3640 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3641 | } |
a2ffb812 AJ |
3642 | if (bo & 0x2) { |
3643 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3644 | } else { | |
3645 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3646 | } |
a7812ae4 | 3647 | tcg_temp_free(temp); |
a2ffb812 AJ |
3648 | } |
3649 | if ((bo & 0x10) == 0) { | |
3650 | /* Test CR */ | |
3651 | uint32_t bi = BI(ctx->opcode); | |
3652 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3653 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3654 | |
d9bce9d9 | 3655 | if (bo & 0x8) { |
a2ffb812 AJ |
3656 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3657 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3658 | } else { |
a2ffb812 AJ |
3659 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3660 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3661 | } |
a7812ae4 | 3662 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3663 | } |
697ab892 | 3664 | gen_update_cfar(ctx, ctx->nip); |
e98a6e40 | 3665 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3666 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3667 | if (likely(AA(ctx->opcode) == 0)) { | |
3668 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3669 | } else { | |
3670 | gen_goto_tb(ctx, 0, li); | |
3671 | } | |
c53be334 | 3672 | gen_set_label(l1); |
c1942362 | 3673 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3674 | } else { |
e0c8f9ce | 3675 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3676 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3677 | } else { |
a2ffb812 | 3678 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3679 | } |
a2ffb812 AJ |
3680 | tcg_gen_exit_tb(0); |
3681 | gen_set_label(l1); | |
e0c8f9ce | 3682 | gen_update_nip(ctx, ctx->nip); |
57fec1fe | 3683 | tcg_gen_exit_tb(0); |
08e46e54 | 3684 | } |
e98a6e40 FB |
3685 | } |
3686 | ||
99e300ef | 3687 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3688 | { |
e98a6e40 FB |
3689 | gen_bcond(ctx, BCOND_IM); |
3690 | } | |
3691 | ||
99e300ef | 3692 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3693 | { |
e98a6e40 FB |
3694 | gen_bcond(ctx, BCOND_CTR); |
3695 | } | |
3696 | ||
99e300ef | 3697 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3698 | { |
e98a6e40 FB |
3699 | gen_bcond(ctx, BCOND_LR); |
3700 | } | |
79aceca5 FB |
3701 | |
3702 | /*** Condition register logical ***/ | |
e1571908 | 3703 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3704 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3705 | { \ |
fc0d441e JM |
3706 | uint8_t bitmask; \ |
3707 | int sh; \ | |
a7812ae4 | 3708 | TCGv_i32 t0, t1; \ |
fc0d441e | 3709 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3710 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3711 | if (sh > 0) \ |
fea0c503 | 3712 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3713 | else if (sh < 0) \ |
fea0c503 | 3714 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3715 | else \ |
fea0c503 | 3716 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3717 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3718 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3719 | if (sh > 0) \ | |
fea0c503 | 3720 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3721 | else if (sh < 0) \ |
fea0c503 | 3722 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3723 | else \ |
fea0c503 AJ |
3724 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3725 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3726 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3727 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3728 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3729 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3730 | tcg_temp_free_i32(t0); \ |
3731 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3732 | } |
3733 | ||
3734 | /* crand */ | |
e1571908 | 3735 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3736 | /* crandc */ |
e1571908 | 3737 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3738 | /* creqv */ |
e1571908 | 3739 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3740 | /* crnand */ |
e1571908 | 3741 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3742 | /* crnor */ |
e1571908 | 3743 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3744 | /* cror */ |
e1571908 | 3745 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3746 | /* crorc */ |
e1571908 | 3747 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3748 | /* crxor */ |
e1571908 | 3749 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3750 | |
54623277 | 3751 | /* mcrf */ |
99e300ef | 3752 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3753 | { |
47e4661c | 3754 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3755 | } |
3756 | ||
3757 | /*** System linkage ***/ | |
99e300ef | 3758 | |
54623277 | 3759 | /* rfi (mem_idx only) */ |
99e300ef | 3760 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3761 | { |
9a64fbe4 | 3762 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3763 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3764 | #else |
3765 | /* Restore CPU state */ | |
76db3ba4 | 3766 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3767 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3768 | return; |
9a64fbe4 | 3769 | } |
697ab892 | 3770 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3771 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3772 | gen_sync_exception(ctx); |
9a64fbe4 | 3773 | #endif |
79aceca5 FB |
3774 | } |
3775 | ||
426613db | 3776 | #if defined(TARGET_PPC64) |
99e300ef | 3777 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3778 | { |
3779 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3780 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3781 | #else |
3782 | /* Restore CPU state */ | |
76db3ba4 | 3783 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3784 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3785 | return; |
3786 | } | |
697ab892 | 3787 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3788 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3789 | gen_sync_exception(ctx); |
426613db JM |
3790 | #endif |
3791 | } | |
426613db | 3792 | |
99e300ef | 3793 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3794 | { |
3795 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3796 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3797 | #else |
3798 | /* Restore CPU state */ | |
76db3ba4 | 3799 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 3800 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3801 | return; |
3802 | } | |
e5f17ac6 | 3803 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3804 | gen_sync_exception(ctx); |
be147d08 JM |
3805 | #endif |
3806 | } | |
3807 | #endif | |
3808 | ||
79aceca5 | 3809 | /* sc */ |
417bf010 JM |
3810 | #if defined(CONFIG_USER_ONLY) |
3811 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3812 | #else | |
3813 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3814 | #endif | |
99e300ef | 3815 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3816 | { |
e1833e1f JM |
3817 | uint32_t lev; |
3818 | ||
3819 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3820 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3821 | } |
3822 | ||
3823 | /*** Trap ***/ | |
99e300ef | 3824 | |
54623277 | 3825 | /* tw */ |
99e300ef | 3826 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3827 | { |
cab3bee2 | 3828 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3829 | /* Update the nip since this might generate a trap exception */ |
3830 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3831 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3832 | t0); | |
cab3bee2 | 3833 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3834 | } |
3835 | ||
3836 | /* twi */ | |
99e300ef | 3837 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3838 | { |
cab3bee2 AJ |
3839 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3840 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3841 | /* Update the nip since this might generate a trap exception */ |
3842 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3843 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3844 | tcg_temp_free(t0); |
3845 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3846 | } |
3847 | ||
d9bce9d9 JM |
3848 | #if defined(TARGET_PPC64) |
3849 | /* td */ | |
99e300ef | 3850 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3851 | { |
cab3bee2 | 3852 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3853 | /* Update the nip since this might generate a trap exception */ |
3854 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3855 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3856 | t0); | |
cab3bee2 | 3857 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3858 | } |
3859 | ||
3860 | /* tdi */ | |
99e300ef | 3861 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3862 | { |
cab3bee2 AJ |
3863 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3864 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3865 | /* Update the nip since this might generate a trap exception */ |
3866 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3867 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3868 | tcg_temp_free(t0); |
3869 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3870 | } |
3871 | #endif | |
3872 | ||
79aceca5 | 3873 | /*** Processor control ***/ |
99e300ef | 3874 | |
da91a00f RH |
3875 | static void gen_read_xer(TCGv dst) |
3876 | { | |
3877 | TCGv t0 = tcg_temp_new(); | |
3878 | TCGv t1 = tcg_temp_new(); | |
3879 | TCGv t2 = tcg_temp_new(); | |
3880 | tcg_gen_mov_tl(dst, cpu_xer); | |
3881 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
3882 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
3883 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
3884 | tcg_gen_or_tl(t0, t0, t1); | |
3885 | tcg_gen_or_tl(dst, dst, t2); | |
3886 | tcg_gen_or_tl(dst, dst, t0); | |
3887 | tcg_temp_free(t0); | |
3888 | tcg_temp_free(t1); | |
3889 | tcg_temp_free(t2); | |
3890 | } | |
3891 | ||
3892 | static void gen_write_xer(TCGv src) | |
3893 | { | |
3894 | tcg_gen_andi_tl(cpu_xer, src, | |
3895 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
3896 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
3897 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
3898 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
3899 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
3900 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
3901 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
3902 | } | |
3903 | ||
54623277 | 3904 | /* mcrxr */ |
99e300ef | 3905 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3906 | { |
da91a00f RH |
3907 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3908 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3909 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3910 | ||
3911 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
3912 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
3913 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
3914 | tcg_gen_shri_i32(t0, t0, 2); | |
3915 | tcg_gen_shri_i32(t1, t1, 1); | |
3916 | tcg_gen_or_i32(dst, dst, t0); | |
3917 | tcg_gen_or_i32(dst, dst, t1); | |
3918 | tcg_temp_free_i32(t0); | |
3919 | tcg_temp_free_i32(t1); | |
3920 | ||
3921 | tcg_gen_movi_tl(cpu_so, 0); | |
3922 | tcg_gen_movi_tl(cpu_ov, 0); | |
3923 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
3924 | } |
3925 | ||
0cfe11ea | 3926 | /* mfcr mfocrf */ |
99e300ef | 3927 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3928 | { |
76a66253 | 3929 | uint32_t crm, crn; |
3b46e624 | 3930 | |
76a66253 JM |
3931 | if (likely(ctx->opcode & 0x00100000)) { |
3932 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3933 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3934 | crn = ctz32 (crm); |
e1571908 | 3935 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3936 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3937 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3938 | } |
d9bce9d9 | 3939 | } else { |
651721b2 AJ |
3940 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3941 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3942 | tcg_gen_shli_i32(t0, t0, 4); | |
3943 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3944 | tcg_gen_shli_i32(t0, t0, 4); | |
3945 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3946 | tcg_gen_shli_i32(t0, t0, 4); | |
3947 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3948 | tcg_gen_shli_i32(t0, t0, 4); | |
3949 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3950 | tcg_gen_shli_i32(t0, t0, 4); | |
3951 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3952 | tcg_gen_shli_i32(t0, t0, 4); | |
3953 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3954 | tcg_gen_shli_i32(t0, t0, 4); | |
3955 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3956 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3957 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3958 | } |
79aceca5 FB |
3959 | } |
3960 | ||
3961 | /* mfmsr */ | |
99e300ef | 3962 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3963 | { |
9a64fbe4 | 3964 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3965 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3966 | #else |
76db3ba4 | 3967 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3968 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3969 | return; |
9a64fbe4 | 3970 | } |
6527f6ea | 3971 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 3972 | #endif |
79aceca5 FB |
3973 | } |
3974 | ||
7b13448f | 3975 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3fc6c082 | 3976 | { |
7b13448f | 3977 | #if 0 |
3fc6c082 FB |
3978 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3979 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3980 | #endif |
3fc6c082 FB |
3981 | } |
3982 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3983 | |
79aceca5 | 3984 | /* mfspr */ |
636aa200 | 3985 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 3986 | { |
45d827d2 | 3987 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
3988 | uint32_t sprn = SPR(ctx->opcode); |
3989 | ||
3fc6c082 | 3990 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 3991 | if (ctx->mem_idx == 2) |
be147d08 | 3992 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 3993 | else if (ctx->mem_idx) |
3fc6c082 FB |
3994 | read_cb = ctx->spr_cb[sprn].oea_read; |
3995 | else | |
9a64fbe4 | 3996 | #endif |
3fc6c082 | 3997 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
3998 | if (likely(read_cb != NULL)) { |
3999 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4000 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4001 | } else { |
4002 | /* Privilege exception */ | |
9fceefa7 JM |
4003 | /* This is a hack to avoid warnings when running Linux: |
4004 | * this OS breaks the PowerPC virtualisation model, | |
4005 | * allowing userland application to read the PVR | |
4006 | */ | |
4007 | if (sprn != SPR_PVR) { | |
c05541ee AB |
4008 | qemu_log("Trying to read privileged spr %d (0x%03x) at " |
4009 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4010 | printf("Trying to read privileged spr %d (0x%03x) at " | |
4011 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
f24e5695 | 4012 | } |
e06fcd75 | 4013 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4014 | } |
3fc6c082 FB |
4015 | } else { |
4016 | /* Not defined */ | |
c05541ee AB |
4017 | qemu_log("Trying to read invalid spr %d (0x%03x) at " |
4018 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4019 | printf("Trying to read invalid spr %d (0x%03x) at " | |
4020 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4021 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4022 | } |
79aceca5 FB |
4023 | } |
4024 | ||
99e300ef | 4025 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4026 | { |
3fc6c082 | 4027 | gen_op_mfspr(ctx); |
76a66253 | 4028 | } |
3fc6c082 FB |
4029 | |
4030 | /* mftb */ | |
99e300ef | 4031 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4032 | { |
4033 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4034 | } |
4035 | ||
0cfe11ea | 4036 | /* mtcrf mtocrf*/ |
99e300ef | 4037 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4038 | { |
76a66253 | 4039 | uint32_t crm, crn; |
3b46e624 | 4040 | |
76a66253 | 4041 | crm = CRM(ctx->opcode); |
8dd640e4 | 4042 | if (likely((ctx->opcode & 0x00100000))) { |
4043 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4044 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 4045 | crn = ctz32 (crm); |
8dd640e4 | 4046 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4047 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4048 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4049 | tcg_temp_free_i32(temp); |
4050 | } | |
76a66253 | 4051 | } else { |
651721b2 AJ |
4052 | TCGv_i32 temp = tcg_temp_new_i32(); |
4053 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4054 | for (crn = 0 ; crn < 8 ; crn++) { | |
4055 | if (crm & (1 << crn)) { | |
4056 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4057 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4058 | } | |
4059 | } | |
a7812ae4 | 4060 | tcg_temp_free_i32(temp); |
76a66253 | 4061 | } |
79aceca5 FB |
4062 | } |
4063 | ||
4064 | /* mtmsr */ | |
426613db | 4065 | #if defined(TARGET_PPC64) |
99e300ef | 4066 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
4067 | { |
4068 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4069 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 4070 | #else |
76db3ba4 | 4071 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4072 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
4073 | return; |
4074 | } | |
be147d08 JM |
4075 | if (ctx->opcode & 0x00010000) { |
4076 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4077 | TCGv t0 = tcg_temp_new(); |
4078 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4079 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4080 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4081 | tcg_temp_free(t0); | |
be147d08 | 4082 | } else { |
056b05f8 JM |
4083 | /* XXX: we need to update nip before the store |
4084 | * if we enter power saving mode, we will exit the loop | |
4085 | * directly from ppc_store_msr | |
4086 | */ | |
be147d08 | 4087 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 4088 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
4089 | /* Must stop the translation as machine state (may have) changed */ |
4090 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 4091 | gen_stop_exception(ctx); |
be147d08 | 4092 | } |
426613db JM |
4093 | #endif |
4094 | } | |
4095 | #endif | |
4096 | ||
99e300ef | 4097 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4098 | { |
9a64fbe4 | 4099 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4100 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4101 | #else |
76db3ba4 | 4102 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4103 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4104 | return; |
9a64fbe4 | 4105 | } |
be147d08 JM |
4106 | if (ctx->opcode & 0x00010000) { |
4107 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4108 | TCGv t0 = tcg_temp_new(); |
4109 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4110 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4111 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4112 | tcg_temp_free(t0); | |
be147d08 | 4113 | } else { |
8018dc63 AG |
4114 | TCGv msr = tcg_temp_new(); |
4115 | ||
056b05f8 JM |
4116 | /* XXX: we need to update nip before the store |
4117 | * if we enter power saving mode, we will exit the loop | |
4118 | * directly from ppc_store_msr | |
4119 | */ | |
be147d08 | 4120 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 4121 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4122 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4123 | #else | |
4124 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4125 | #endif |
e5f17ac6 | 4126 | gen_helper_store_msr(cpu_env, msr); |
be147d08 | 4127 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4128 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4129 | gen_stop_exception(ctx); |
be147d08 | 4130 | } |
9a64fbe4 | 4131 | #endif |
79aceca5 FB |
4132 | } |
4133 | ||
4134 | /* mtspr */ | |
99e300ef | 4135 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4136 | { |
45d827d2 | 4137 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
4138 | uint32_t sprn = SPR(ctx->opcode); |
4139 | ||
3fc6c082 | 4140 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4141 | if (ctx->mem_idx == 2) |
be147d08 | 4142 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 4143 | else if (ctx->mem_idx) |
3fc6c082 FB |
4144 | write_cb = ctx->spr_cb[sprn].oea_write; |
4145 | else | |
9a64fbe4 | 4146 | #endif |
3fc6c082 | 4147 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
4148 | if (likely(write_cb != NULL)) { |
4149 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4150 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4151 | } else { |
4152 | /* Privilege exception */ | |
c05541ee AB |
4153 | qemu_log("Trying to write privileged spr %d (0x%03x) at " |
4154 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4155 | printf("Trying to write privileged spr %d (0x%03x) at " | |
4156 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4157 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4158 | } |
3fc6c082 FB |
4159 | } else { |
4160 | /* Not defined */ | |
c05541ee AB |
4161 | qemu_log("Trying to write invalid spr %d (0x%03x) at " |
4162 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4163 | printf("Trying to write invalid spr %d (0x%03x) at " | |
4164 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4165 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4166 | } |
79aceca5 FB |
4167 | } |
4168 | ||
4169 | /*** Cache management ***/ | |
99e300ef | 4170 | |
54623277 | 4171 | /* dcbf */ |
99e300ef | 4172 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4173 | { |
dac454af | 4174 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4175 | TCGv t0; |
4176 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4177 | t0 = tcg_temp_new(); | |
4178 | gen_addr_reg_index(ctx, t0); | |
4179 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4180 | tcg_temp_free(t0); |
79aceca5 FB |
4181 | } |
4182 | ||
4183 | /* dcbi (Supervisor only) */ | |
99e300ef | 4184 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4185 | { |
a541f297 | 4186 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4187 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4188 | #else |
b61f2753 | 4189 | TCGv EA, val; |
76db3ba4 | 4190 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4191 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4192 | return; |
9a64fbe4 | 4193 | } |
a7812ae4 | 4194 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4195 | gen_set_access_type(ctx, ACCESS_CACHE); |
4196 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4197 | val = tcg_temp_new(); |
76a66253 | 4198 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4199 | gen_qemu_ld8u(ctx, val, EA); |
4200 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4201 | tcg_temp_free(val); |
4202 | tcg_temp_free(EA); | |
a541f297 | 4203 | #endif |
79aceca5 FB |
4204 | } |
4205 | ||
4206 | /* dcdst */ | |
99e300ef | 4207 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4208 | { |
76a66253 | 4209 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4210 | TCGv t0; |
4211 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4212 | t0 = tcg_temp_new(); | |
4213 | gen_addr_reg_index(ctx, t0); | |
4214 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4215 | tcg_temp_free(t0); |
79aceca5 FB |
4216 | } |
4217 | ||
4218 | /* dcbt */ | |
99e300ef | 4219 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4220 | { |
0db1b20e | 4221 | /* interpreted as no-op */ |
76a66253 JM |
4222 | /* XXX: specification say this is treated as a load by the MMU |
4223 | * but does not generate any exception | |
4224 | */ | |
79aceca5 FB |
4225 | } |
4226 | ||
4227 | /* dcbtst */ | |
99e300ef | 4228 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4229 | { |
0db1b20e | 4230 | /* interpreted as no-op */ |
76a66253 JM |
4231 | /* XXX: specification say this is treated as a load by the MMU |
4232 | * but does not generate any exception | |
4233 | */ | |
79aceca5 FB |
4234 | } |
4235 | ||
4236 | /* dcbz */ | |
99e300ef | 4237 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4238 | { |
8e33944f AG |
4239 | TCGv tcgv_addr; |
4240 | TCGv_i32 tcgv_is_dcbzl; | |
4241 | int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; | |
d63001d1 | 4242 | |
76db3ba4 | 4243 | gen_set_access_type(ctx, ACCESS_CACHE); |
799a8c8d AJ |
4244 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4245 | gen_update_nip(ctx, ctx->nip - 4); | |
8e33944f AG |
4246 | tcgv_addr = tcg_temp_new(); |
4247 | tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); | |
4248 | ||
4249 | gen_addr_reg_index(ctx, tcgv_addr); | |
4250 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); | |
4251 | ||
4252 | tcg_temp_free(tcgv_addr); | |
4253 | tcg_temp_free_i32(tcgv_is_dcbzl); | |
79aceca5 FB |
4254 | } |
4255 | ||
ae1c1a3d | 4256 | /* dst / dstt */ |
99e300ef | 4257 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4258 | { |
4259 | if (rA(ctx->opcode) == 0) { | |
4260 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4261 | } else { | |
4262 | /* interpreted as no-op */ | |
4263 | } | |
4264 | } | |
4265 | ||
4266 | /* dstst /dststt */ | |
99e300ef | 4267 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4268 | { |
4269 | if (rA(ctx->opcode) == 0) { | |
4270 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4271 | } else { | |
4272 | /* interpreted as no-op */ | |
4273 | } | |
4274 | ||
4275 | } | |
4276 | ||
4277 | /* dss / dssall */ | |
99e300ef | 4278 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4279 | { |
4280 | /* interpreted as no-op */ | |
4281 | } | |
4282 | ||
79aceca5 | 4283 | /* icbi */ |
99e300ef | 4284 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4285 | { |
76db3ba4 AJ |
4286 | TCGv t0; |
4287 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4288 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4289 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4290 | t0 = tcg_temp_new(); |
4291 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4292 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4293 | tcg_temp_free(t0); |
79aceca5 FB |
4294 | } |
4295 | ||
4296 | /* Optional: */ | |
4297 | /* dcba */ | |
99e300ef | 4298 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4299 | { |
0db1b20e JM |
4300 | /* interpreted as no-op */ |
4301 | /* XXX: specification say this is treated as a store by the MMU | |
4302 | * but does not generate any exception | |
4303 | */ | |
79aceca5 FB |
4304 | } |
4305 | ||
4306 | /*** Segment register manipulation ***/ | |
4307 | /* Supervisor only: */ | |
99e300ef | 4308 | |
54623277 | 4309 | /* mfsr */ |
99e300ef | 4310 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4311 | { |
9a64fbe4 | 4312 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4313 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4314 | #else |
74d37793 | 4315 | TCGv t0; |
76db3ba4 | 4316 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4317 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4318 | return; |
9a64fbe4 | 4319 | } |
74d37793 | 4320 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4321 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4322 | tcg_temp_free(t0); |
9a64fbe4 | 4323 | #endif |
79aceca5 FB |
4324 | } |
4325 | ||
4326 | /* mfsrin */ | |
99e300ef | 4327 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4328 | { |
9a64fbe4 | 4329 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4330 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4331 | #else |
74d37793 | 4332 | TCGv t0; |
76db3ba4 | 4333 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4334 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4335 | return; |
9a64fbe4 | 4336 | } |
74d37793 AJ |
4337 | t0 = tcg_temp_new(); |
4338 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4339 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4340 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4341 | tcg_temp_free(t0); |
9a64fbe4 | 4342 | #endif |
79aceca5 FB |
4343 | } |
4344 | ||
4345 | /* mtsr */ | |
99e300ef | 4346 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4347 | { |
9a64fbe4 | 4348 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4349 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4350 | #else |
74d37793 | 4351 | TCGv t0; |
76db3ba4 | 4352 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4353 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4354 | return; |
9a64fbe4 | 4355 | } |
74d37793 | 4356 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4357 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4358 | tcg_temp_free(t0); |
9a64fbe4 | 4359 | #endif |
79aceca5 FB |
4360 | } |
4361 | ||
4362 | /* mtsrin */ | |
99e300ef | 4363 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4364 | { |
9a64fbe4 | 4365 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4366 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4367 | #else |
74d37793 | 4368 | TCGv t0; |
76db3ba4 | 4369 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4370 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4371 | return; |
9a64fbe4 | 4372 | } |
74d37793 AJ |
4373 | t0 = tcg_temp_new(); |
4374 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4375 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4376 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4377 | tcg_temp_free(t0); |
9a64fbe4 | 4378 | #endif |
79aceca5 FB |
4379 | } |
4380 | ||
12de9a39 JM |
4381 | #if defined(TARGET_PPC64) |
4382 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4383 | |
54623277 | 4384 | /* mfsr */ |
e8eaa2c0 | 4385 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4386 | { |
4387 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4388 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4389 | #else |
74d37793 | 4390 | TCGv t0; |
76db3ba4 | 4391 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4392 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4393 | return; |
4394 | } | |
74d37793 | 4395 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4396 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4397 | tcg_temp_free(t0); |
12de9a39 JM |
4398 | #endif |
4399 | } | |
4400 | ||
4401 | /* mfsrin */ | |
e8eaa2c0 | 4402 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4403 | { |
4404 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4405 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4406 | #else |
74d37793 | 4407 | TCGv t0; |
76db3ba4 | 4408 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4409 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4410 | return; |
4411 | } | |
74d37793 AJ |
4412 | t0 = tcg_temp_new(); |
4413 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4414 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4415 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4416 | tcg_temp_free(t0); |
12de9a39 JM |
4417 | #endif |
4418 | } | |
4419 | ||
4420 | /* mtsr */ | |
e8eaa2c0 | 4421 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4422 | { |
4423 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4424 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4425 | #else |
74d37793 | 4426 | TCGv t0; |
76db3ba4 | 4427 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4428 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4429 | return; |
4430 | } | |
74d37793 | 4431 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4432 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4433 | tcg_temp_free(t0); |
12de9a39 JM |
4434 | #endif |
4435 | } | |
4436 | ||
4437 | /* mtsrin */ | |
e8eaa2c0 | 4438 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4439 | { |
4440 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4441 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4442 | #else |
74d37793 | 4443 | TCGv t0; |
76db3ba4 | 4444 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4445 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4446 | return; |
4447 | } | |
74d37793 AJ |
4448 | t0 = tcg_temp_new(); |
4449 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4450 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4451 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4452 | tcg_temp_free(t0); |
12de9a39 JM |
4453 | #endif |
4454 | } | |
f6b868fc BS |
4455 | |
4456 | /* slbmte */ | |
e8eaa2c0 | 4457 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4458 | { |
4459 | #if defined(CONFIG_USER_ONLY) | |
4460 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4461 | #else | |
4462 | if (unlikely(!ctx->mem_idx)) { | |
4463 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4464 | return; | |
4465 | } | |
c6c7cf05 BS |
4466 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4467 | cpu_gpr[rS(ctx->opcode)]); | |
f6b868fc BS |
4468 | #endif |
4469 | } | |
4470 | ||
efdef95f DG |
4471 | static void gen_slbmfee(DisasContext *ctx) |
4472 | { | |
4473 | #if defined(CONFIG_USER_ONLY) | |
4474 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4475 | #else | |
4476 | if (unlikely(!ctx->mem_idx)) { | |
4477 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4478 | return; | |
4479 | } | |
c6c7cf05 | 4480 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4481 | cpu_gpr[rB(ctx->opcode)]); |
4482 | #endif | |
4483 | } | |
4484 | ||
4485 | static void gen_slbmfev(DisasContext *ctx) | |
4486 | { | |
4487 | #if defined(CONFIG_USER_ONLY) | |
4488 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4489 | #else | |
4490 | if (unlikely(!ctx->mem_idx)) { | |
4491 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4492 | return; | |
4493 | } | |
c6c7cf05 | 4494 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4495 | cpu_gpr[rB(ctx->opcode)]); |
4496 | #endif | |
4497 | } | |
12de9a39 JM |
4498 | #endif /* defined(TARGET_PPC64) */ |
4499 | ||
79aceca5 | 4500 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4501 | /* Optional & mem_idx only: */ |
99e300ef | 4502 | |
54623277 | 4503 | /* tlbia */ |
99e300ef | 4504 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4505 | { |
9a64fbe4 | 4506 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4507 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4508 | #else |
76db3ba4 | 4509 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4510 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4511 | return; |
9a64fbe4 | 4512 | } |
c6c7cf05 | 4513 | gen_helper_tlbia(cpu_env); |
9a64fbe4 | 4514 | #endif |
79aceca5 FB |
4515 | } |
4516 | ||
bf14b1ce | 4517 | /* tlbiel */ |
99e300ef | 4518 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4519 | { |
4520 | #if defined(CONFIG_USER_ONLY) | |
4521 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4522 | #else | |
4523 | if (unlikely(!ctx->mem_idx)) { | |
4524 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4525 | return; | |
4526 | } | |
c6c7cf05 | 4527 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
bf14b1ce BS |
4528 | #endif |
4529 | } | |
4530 | ||
79aceca5 | 4531 | /* tlbie */ |
99e300ef | 4532 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4533 | { |
9a64fbe4 | 4534 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4535 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4536 | #else |
76db3ba4 | 4537 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4538 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4539 | return; |
9a64fbe4 | 4540 | } |
9ca3f7f3 | 4541 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4542 | TCGv t0 = tcg_temp_new(); |
4543 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4544 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4545 | tcg_temp_free(t0); |
9ca3f7f3 | 4546 | } else { |
c6c7cf05 | 4547 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4548 | } |
9a64fbe4 | 4549 | #endif |
79aceca5 FB |
4550 | } |
4551 | ||
4552 | /* tlbsync */ | |
99e300ef | 4553 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4554 | { |
9a64fbe4 | 4555 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4556 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4557 | #else |
76db3ba4 | 4558 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4559 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4560 | return; |
9a64fbe4 FB |
4561 | } |
4562 | /* This has no effect: it should ensure that all previous | |
4563 | * tlbie have completed | |
4564 | */ | |
e06fcd75 | 4565 | gen_stop_exception(ctx); |
9a64fbe4 | 4566 | #endif |
79aceca5 FB |
4567 | } |
4568 | ||
426613db JM |
4569 | #if defined(TARGET_PPC64) |
4570 | /* slbia */ | |
99e300ef | 4571 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4572 | { |
4573 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4574 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4575 | #else |
76db3ba4 | 4576 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4577 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4578 | return; |
4579 | } | |
c6c7cf05 | 4580 | gen_helper_slbia(cpu_env); |
426613db JM |
4581 | #endif |
4582 | } | |
4583 | ||
4584 | /* slbie */ | |
99e300ef | 4585 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4586 | { |
4587 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4588 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4589 | #else |
76db3ba4 | 4590 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4591 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4592 | return; |
4593 | } | |
c6c7cf05 | 4594 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4595 | #endif |
4596 | } | |
4597 | #endif | |
4598 | ||
79aceca5 FB |
4599 | /*** External control ***/ |
4600 | /* Optional: */ | |
99e300ef | 4601 | |
54623277 | 4602 | /* eciwx */ |
99e300ef | 4603 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4604 | { |
76db3ba4 | 4605 | TCGv t0; |
fa407c03 | 4606 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4607 | gen_set_access_type(ctx, ACCESS_EXT); |
4608 | t0 = tcg_temp_new(); | |
4609 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4610 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4611 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4612 | tcg_temp_free(t0); |
76a66253 JM |
4613 | } |
4614 | ||
4615 | /* ecowx */ | |
99e300ef | 4616 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4617 | { |
76db3ba4 | 4618 | TCGv t0; |
fa407c03 | 4619 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4620 | gen_set_access_type(ctx, ACCESS_EXT); |
4621 | t0 = tcg_temp_new(); | |
4622 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4623 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4624 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4625 | tcg_temp_free(t0); |
76a66253 JM |
4626 | } |
4627 | ||
4628 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4629 | |
54623277 | 4630 | /* abs - abs. */ |
99e300ef | 4631 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4632 | { |
22e0e173 AJ |
4633 | int l1 = gen_new_label(); |
4634 | int l2 = gen_new_label(); | |
4635 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4636 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4637 | tcg_gen_br(l2); | |
4638 | gen_set_label(l1); | |
4639 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4640 | gen_set_label(l2); | |
76a66253 | 4641 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4642 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4643 | } |
4644 | ||
4645 | /* abso - abso. */ | |
99e300ef | 4646 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4647 | { |
22e0e173 AJ |
4648 | int l1 = gen_new_label(); |
4649 | int l2 = gen_new_label(); | |
4650 | int l3 = gen_new_label(); | |
4651 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4652 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4653 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4654 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4655 | tcg_gen_movi_tl(cpu_ov, 1); |
4656 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4657 | tcg_gen_br(l2); |
4658 | gen_set_label(l1); | |
4659 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4660 | tcg_gen_br(l3); | |
4661 | gen_set_label(l2); | |
4662 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4663 | gen_set_label(l3); | |
76a66253 | 4664 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4665 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4666 | } |
4667 | ||
4668 | /* clcs */ | |
99e300ef | 4669 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4670 | { |
22e0e173 | 4671 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4672 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4673 | tcg_temp_free_i32(t0); |
c7697e1f | 4674 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4675 | } |
4676 | ||
4677 | /* div - div. */ | |
99e300ef | 4678 | static void gen_div(DisasContext *ctx) |
76a66253 | 4679 | { |
d15f74fb BS |
4680 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4681 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4682 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4683 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4684 | } |
4685 | ||
4686 | /* divo - divo. */ | |
99e300ef | 4687 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4688 | { |
d15f74fb BS |
4689 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4690 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4691 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4692 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4693 | } |
4694 | ||
4695 | /* divs - divs. */ | |
99e300ef | 4696 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4697 | { |
d15f74fb BS |
4698 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4699 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4700 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4701 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4702 | } |
4703 | ||
4704 | /* divso - divso. */ | |
99e300ef | 4705 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4706 | { |
d15f74fb BS |
4707 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4708 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4709 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4710 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4711 | } |
4712 | ||
4713 | /* doz - doz. */ | |
99e300ef | 4714 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4715 | { |
22e0e173 AJ |
4716 | int l1 = gen_new_label(); |
4717 | int l2 = gen_new_label(); | |
4718 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4719 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4720 | tcg_gen_br(l2); | |
4721 | gen_set_label(l1); | |
4722 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4723 | gen_set_label(l2); | |
76a66253 | 4724 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4725 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4726 | } |
4727 | ||
4728 | /* dozo - dozo. */ | |
99e300ef | 4729 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4730 | { |
22e0e173 AJ |
4731 | int l1 = gen_new_label(); |
4732 | int l2 = gen_new_label(); | |
4733 | TCGv t0 = tcg_temp_new(); | |
4734 | TCGv t1 = tcg_temp_new(); | |
4735 | TCGv t2 = tcg_temp_new(); | |
4736 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4737 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4738 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4739 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4740 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4741 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4742 | tcg_gen_andc_tl(t1, t1, t2); | |
4743 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4744 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4745 | tcg_gen_movi_tl(cpu_ov, 1); |
4746 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4747 | tcg_gen_br(l2); |
4748 | gen_set_label(l1); | |
4749 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4750 | gen_set_label(l2); | |
4751 | tcg_temp_free(t0); | |
4752 | tcg_temp_free(t1); | |
4753 | tcg_temp_free(t2); | |
76a66253 | 4754 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4755 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4756 | } |
4757 | ||
4758 | /* dozi */ | |
99e300ef | 4759 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4760 | { |
22e0e173 AJ |
4761 | target_long simm = SIMM(ctx->opcode); |
4762 | int l1 = gen_new_label(); | |
4763 | int l2 = gen_new_label(); | |
4764 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
4765 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4766 | tcg_gen_br(l2); | |
4767 | gen_set_label(l1); | |
4768 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4769 | gen_set_label(l2); | |
4770 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4771 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4772 | } |
4773 | ||
76a66253 | 4774 | /* lscbx - lscbx. */ |
99e300ef | 4775 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4776 | { |
bdb4b689 AJ |
4777 | TCGv t0 = tcg_temp_new(); |
4778 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4779 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4780 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4781 | |
76db3ba4 | 4782 | gen_addr_reg_index(ctx, t0); |
76a66253 | 4783 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 4784 | gen_update_nip(ctx, ctx->nip - 4); |
2f5a189c | 4785 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4786 | tcg_temp_free_i32(t1); |
4787 | tcg_temp_free_i32(t2); | |
4788 | tcg_temp_free_i32(t3); | |
3d7b417e | 4789 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4790 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4791 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4792 | gen_set_Rc0(ctx, t0); |
4793 | tcg_temp_free(t0); | |
76a66253 JM |
4794 | } |
4795 | ||
4796 | /* maskg - maskg. */ | |
99e300ef | 4797 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4798 | { |
22e0e173 AJ |
4799 | int l1 = gen_new_label(); |
4800 | TCGv t0 = tcg_temp_new(); | |
4801 | TCGv t1 = tcg_temp_new(); | |
4802 | TCGv t2 = tcg_temp_new(); | |
4803 | TCGv t3 = tcg_temp_new(); | |
4804 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4805 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4806 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4807 | tcg_gen_addi_tl(t2, t0, 1); | |
4808 | tcg_gen_shr_tl(t2, t3, t2); | |
4809 | tcg_gen_shr_tl(t3, t3, t1); | |
4810 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4811 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4812 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4813 | gen_set_label(l1); | |
4814 | tcg_temp_free(t0); | |
4815 | tcg_temp_free(t1); | |
4816 | tcg_temp_free(t2); | |
4817 | tcg_temp_free(t3); | |
76a66253 | 4818 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4819 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4820 | } |
4821 | ||
4822 | /* maskir - maskir. */ | |
99e300ef | 4823 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4824 | { |
22e0e173 AJ |
4825 | TCGv t0 = tcg_temp_new(); |
4826 | TCGv t1 = tcg_temp_new(); | |
4827 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4828 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4829 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4830 | tcg_temp_free(t0); | |
4831 | tcg_temp_free(t1); | |
76a66253 | 4832 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4833 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4834 | } |
4835 | ||
4836 | /* mul - mul. */ | |
99e300ef | 4837 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4838 | { |
22e0e173 AJ |
4839 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4840 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4841 | TCGv t2 = tcg_temp_new(); | |
4842 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4843 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4844 | tcg_gen_mul_i64(t0, t0, t1); | |
4845 | tcg_gen_trunc_i64_tl(t2, t0); | |
4846 | gen_store_spr(SPR_MQ, t2); | |
4847 | tcg_gen_shri_i64(t1, t0, 32); | |
4848 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4849 | tcg_temp_free_i64(t0); | |
4850 | tcg_temp_free_i64(t1); | |
4851 | tcg_temp_free(t2); | |
76a66253 | 4852 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4853 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4854 | } |
4855 | ||
4856 | /* mulo - mulo. */ | |
99e300ef | 4857 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4858 | { |
22e0e173 AJ |
4859 | int l1 = gen_new_label(); |
4860 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
4861 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4862 | TCGv t2 = tcg_temp_new(); | |
4863 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4864 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4865 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4866 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4867 | tcg_gen_mul_i64(t0, t0, t1); | |
4868 | tcg_gen_trunc_i64_tl(t2, t0); | |
4869 | gen_store_spr(SPR_MQ, t2); | |
4870 | tcg_gen_shri_i64(t1, t0, 32); | |
4871 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4872 | tcg_gen_ext32s_i64(t1, t0); | |
4873 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
4874 | tcg_gen_movi_tl(cpu_ov, 1); |
4875 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4876 | gen_set_label(l1); |
4877 | tcg_temp_free_i64(t0); | |
4878 | tcg_temp_free_i64(t1); | |
4879 | tcg_temp_free(t2); | |
76a66253 | 4880 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4881 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4882 | } |
4883 | ||
4884 | /* nabs - nabs. */ | |
99e300ef | 4885 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4886 | { |
22e0e173 AJ |
4887 | int l1 = gen_new_label(); |
4888 | int l2 = gen_new_label(); | |
4889 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4890 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4891 | tcg_gen_br(l2); | |
4892 | gen_set_label(l1); | |
4893 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4894 | gen_set_label(l2); | |
76a66253 | 4895 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4896 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4897 | } |
4898 | ||
4899 | /* nabso - nabso. */ | |
99e300ef | 4900 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4901 | { |
22e0e173 AJ |
4902 | int l1 = gen_new_label(); |
4903 | int l2 = gen_new_label(); | |
4904 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4905 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4906 | tcg_gen_br(l2); | |
4907 | gen_set_label(l1); | |
4908 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4909 | gen_set_label(l2); | |
4910 | /* nabs never overflows */ | |
da91a00f | 4911 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 4912 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4913 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4914 | } |
4915 | ||
4916 | /* rlmi - rlmi. */ | |
99e300ef | 4917 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4918 | { |
7487953d AJ |
4919 | uint32_t mb = MB(ctx->opcode); |
4920 | uint32_t me = ME(ctx->opcode); | |
4921 | TCGv t0 = tcg_temp_new(); | |
4922 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4923 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4924 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4925 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4926 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4927 | tcg_temp_free(t0); | |
76a66253 | 4928 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4929 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4930 | } |
4931 | ||
4932 | /* rrib - rrib. */ | |
99e300ef | 4933 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4934 | { |
7487953d AJ |
4935 | TCGv t0 = tcg_temp_new(); |
4936 | TCGv t1 = tcg_temp_new(); | |
4937 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4938 | tcg_gen_movi_tl(t1, 0x80000000); | |
4939 | tcg_gen_shr_tl(t1, t1, t0); | |
4940 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4941 | tcg_gen_and_tl(t0, t0, t1); | |
4942 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4943 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4944 | tcg_temp_free(t0); | |
4945 | tcg_temp_free(t1); | |
76a66253 | 4946 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4947 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4948 | } |
4949 | ||
4950 | /* sle - sle. */ | |
99e300ef | 4951 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4952 | { |
7487953d AJ |
4953 | TCGv t0 = tcg_temp_new(); |
4954 | TCGv t1 = tcg_temp_new(); | |
4955 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4956 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4957 | tcg_gen_subfi_tl(t1, 32, t1); | |
4958 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4959 | tcg_gen_or_tl(t1, t0, t1); | |
4960 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4961 | gen_store_spr(SPR_MQ, t1); | |
4962 | tcg_temp_free(t0); | |
4963 | tcg_temp_free(t1); | |
76a66253 | 4964 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4965 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4966 | } |
4967 | ||
4968 | /* sleq - sleq. */ | |
99e300ef | 4969 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4970 | { |
7487953d AJ |
4971 | TCGv t0 = tcg_temp_new(); |
4972 | TCGv t1 = tcg_temp_new(); | |
4973 | TCGv t2 = tcg_temp_new(); | |
4974 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4975 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
4976 | tcg_gen_shl_tl(t2, t2, t0); | |
4977 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4978 | gen_load_spr(t1, SPR_MQ); | |
4979 | gen_store_spr(SPR_MQ, t0); | |
4980 | tcg_gen_and_tl(t0, t0, t2); | |
4981 | tcg_gen_andc_tl(t1, t1, t2); | |
4982 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4983 | tcg_temp_free(t0); | |
4984 | tcg_temp_free(t1); | |
4985 | tcg_temp_free(t2); | |
76a66253 | 4986 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4987 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4988 | } |
4989 | ||
4990 | /* sliq - sliq. */ | |
99e300ef | 4991 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 4992 | { |
7487953d AJ |
4993 | int sh = SH(ctx->opcode); |
4994 | TCGv t0 = tcg_temp_new(); | |
4995 | TCGv t1 = tcg_temp_new(); | |
4996 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4997 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4998 | tcg_gen_or_tl(t1, t0, t1); | |
4999 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5000 | gen_store_spr(SPR_MQ, t1); | |
5001 | tcg_temp_free(t0); | |
5002 | tcg_temp_free(t1); | |
76a66253 | 5003 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5004 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5005 | } |
5006 | ||
5007 | /* slliq - slliq. */ | |
99e300ef | 5008 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5009 | { |
7487953d AJ |
5010 | int sh = SH(ctx->opcode); |
5011 | TCGv t0 = tcg_temp_new(); | |
5012 | TCGv t1 = tcg_temp_new(); | |
5013 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5014 | gen_load_spr(t1, SPR_MQ); | |
5015 | gen_store_spr(SPR_MQ, t0); | |
5016 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5017 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5018 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5019 | tcg_temp_free(t0); | |
5020 | tcg_temp_free(t1); | |
76a66253 | 5021 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5022 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5023 | } |
5024 | ||
5025 | /* sllq - sllq. */ | |
99e300ef | 5026 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5027 | { |
7487953d AJ |
5028 | int l1 = gen_new_label(); |
5029 | int l2 = gen_new_label(); | |
5030 | TCGv t0 = tcg_temp_local_new(); | |
5031 | TCGv t1 = tcg_temp_local_new(); | |
5032 | TCGv t2 = tcg_temp_local_new(); | |
5033 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5034 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5035 | tcg_gen_shl_tl(t1, t1, t2); | |
5036 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5037 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5038 | gen_load_spr(t0, SPR_MQ); | |
5039 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5040 | tcg_gen_br(l2); | |
5041 | gen_set_label(l1); | |
5042 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5043 | gen_load_spr(t2, SPR_MQ); | |
5044 | tcg_gen_andc_tl(t1, t2, t1); | |
5045 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5046 | gen_set_label(l2); | |
5047 | tcg_temp_free(t0); | |
5048 | tcg_temp_free(t1); | |
5049 | tcg_temp_free(t2); | |
76a66253 | 5050 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5051 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5052 | } |
5053 | ||
5054 | /* slq - slq. */ | |
99e300ef | 5055 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5056 | { |
7487953d AJ |
5057 | int l1 = gen_new_label(); |
5058 | TCGv t0 = tcg_temp_new(); | |
5059 | TCGv t1 = tcg_temp_new(); | |
5060 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5061 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5062 | tcg_gen_subfi_tl(t1, 32, t1); | |
5063 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5064 | tcg_gen_or_tl(t1, t0, t1); | |
5065 | gen_store_spr(SPR_MQ, t1); | |
5066 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5067 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5068 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5069 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5070 | gen_set_label(l1); | |
5071 | tcg_temp_free(t0); | |
5072 | tcg_temp_free(t1); | |
76a66253 | 5073 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5074 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5075 | } |
5076 | ||
d9bce9d9 | 5077 | /* sraiq - sraiq. */ |
99e300ef | 5078 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5079 | { |
7487953d AJ |
5080 | int sh = SH(ctx->opcode); |
5081 | int l1 = gen_new_label(); | |
5082 | TCGv t0 = tcg_temp_new(); | |
5083 | TCGv t1 = tcg_temp_new(); | |
5084 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5085 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5086 | tcg_gen_or_tl(t0, t0, t1); | |
5087 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 5088 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5089 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5090 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 5091 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5092 | gen_set_label(l1); |
5093 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5094 | tcg_temp_free(t0); | |
5095 | tcg_temp_free(t1); | |
76a66253 | 5096 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5097 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5098 | } |
5099 | ||
5100 | /* sraq - sraq. */ | |
99e300ef | 5101 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5102 | { |
7487953d AJ |
5103 | int l1 = gen_new_label(); |
5104 | int l2 = gen_new_label(); | |
5105 | TCGv t0 = tcg_temp_new(); | |
5106 | TCGv t1 = tcg_temp_local_new(); | |
5107 | TCGv t2 = tcg_temp_local_new(); | |
5108 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5109 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5110 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5111 | tcg_gen_subfi_tl(t2, 32, t2); | |
5112 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5113 | tcg_gen_or_tl(t0, t0, t2); | |
5114 | gen_store_spr(SPR_MQ, t0); | |
5115 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5116 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5117 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5118 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5119 | gen_set_label(l1); | |
5120 | tcg_temp_free(t0); | |
5121 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5122 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5123 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5124 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5125 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5126 | gen_set_label(l2); |
5127 | tcg_temp_free(t1); | |
5128 | tcg_temp_free(t2); | |
76a66253 | 5129 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5130 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5131 | } |
5132 | ||
5133 | /* sre - sre. */ | |
99e300ef | 5134 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5135 | { |
7487953d AJ |
5136 | TCGv t0 = tcg_temp_new(); |
5137 | TCGv t1 = tcg_temp_new(); | |
5138 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5139 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5140 | tcg_gen_subfi_tl(t1, 32, t1); | |
5141 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5142 | tcg_gen_or_tl(t1, t0, t1); | |
5143 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5144 | gen_store_spr(SPR_MQ, t1); | |
5145 | tcg_temp_free(t0); | |
5146 | tcg_temp_free(t1); | |
76a66253 | 5147 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5148 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5149 | } |
5150 | ||
5151 | /* srea - srea. */ | |
99e300ef | 5152 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5153 | { |
7487953d AJ |
5154 | TCGv t0 = tcg_temp_new(); |
5155 | TCGv t1 = tcg_temp_new(); | |
5156 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5157 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5158 | gen_store_spr(SPR_MQ, t0); | |
5159 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5160 | tcg_temp_free(t0); | |
5161 | tcg_temp_free(t1); | |
76a66253 | 5162 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5163 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5164 | } |
5165 | ||
5166 | /* sreq */ | |
99e300ef | 5167 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5168 | { |
7487953d AJ |
5169 | TCGv t0 = tcg_temp_new(); |
5170 | TCGv t1 = tcg_temp_new(); | |
5171 | TCGv t2 = tcg_temp_new(); | |
5172 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5173 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5174 | tcg_gen_shr_tl(t1, t1, t0); | |
5175 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5176 | gen_load_spr(t2, SPR_MQ); | |
5177 | gen_store_spr(SPR_MQ, t0); | |
5178 | tcg_gen_and_tl(t0, t0, t1); | |
5179 | tcg_gen_andc_tl(t2, t2, t1); | |
5180 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5181 | tcg_temp_free(t0); | |
5182 | tcg_temp_free(t1); | |
5183 | tcg_temp_free(t2); | |
76a66253 | 5184 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5185 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5186 | } |
5187 | ||
5188 | /* sriq */ | |
99e300ef | 5189 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5190 | { |
7487953d AJ |
5191 | int sh = SH(ctx->opcode); |
5192 | TCGv t0 = tcg_temp_new(); | |
5193 | TCGv t1 = tcg_temp_new(); | |
5194 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5195 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5196 | tcg_gen_or_tl(t1, t0, t1); | |
5197 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5198 | gen_store_spr(SPR_MQ, t1); | |
5199 | tcg_temp_free(t0); | |
5200 | tcg_temp_free(t1); | |
76a66253 | 5201 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5202 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5203 | } |
5204 | ||
5205 | /* srliq */ | |
99e300ef | 5206 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5207 | { |
7487953d AJ |
5208 | int sh = SH(ctx->opcode); |
5209 | TCGv t0 = tcg_temp_new(); | |
5210 | TCGv t1 = tcg_temp_new(); | |
5211 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5212 | gen_load_spr(t1, SPR_MQ); | |
5213 | gen_store_spr(SPR_MQ, t0); | |
5214 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5215 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5216 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5217 | tcg_temp_free(t0); | |
5218 | tcg_temp_free(t1); | |
76a66253 | 5219 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5220 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5221 | } |
5222 | ||
5223 | /* srlq */ | |
99e300ef | 5224 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5225 | { |
7487953d AJ |
5226 | int l1 = gen_new_label(); |
5227 | int l2 = gen_new_label(); | |
5228 | TCGv t0 = tcg_temp_local_new(); | |
5229 | TCGv t1 = tcg_temp_local_new(); | |
5230 | TCGv t2 = tcg_temp_local_new(); | |
5231 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5232 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5233 | tcg_gen_shr_tl(t2, t1, t2); | |
5234 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5235 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5236 | gen_load_spr(t0, SPR_MQ); | |
5237 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5238 | tcg_gen_br(l2); | |
5239 | gen_set_label(l1); | |
5240 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5241 | tcg_gen_and_tl(t0, t0, t2); | |
5242 | gen_load_spr(t1, SPR_MQ); | |
5243 | tcg_gen_andc_tl(t1, t1, t2); | |
5244 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5245 | gen_set_label(l2); | |
5246 | tcg_temp_free(t0); | |
5247 | tcg_temp_free(t1); | |
5248 | tcg_temp_free(t2); | |
76a66253 | 5249 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5250 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5251 | } |
5252 | ||
5253 | /* srq */ | |
99e300ef | 5254 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5255 | { |
7487953d AJ |
5256 | int l1 = gen_new_label(); |
5257 | TCGv t0 = tcg_temp_new(); | |
5258 | TCGv t1 = tcg_temp_new(); | |
5259 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5260 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5261 | tcg_gen_subfi_tl(t1, 32, t1); | |
5262 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5263 | tcg_gen_or_tl(t1, t0, t1); | |
5264 | gen_store_spr(SPR_MQ, t1); | |
5265 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5266 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5267 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5268 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5269 | gen_set_label(l1); | |
5270 | tcg_temp_free(t0); | |
5271 | tcg_temp_free(t1); | |
76a66253 | 5272 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5273 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5274 | } |
5275 | ||
5276 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5277 | |
54623277 | 5278 | /* dsa */ |
99e300ef | 5279 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5280 | { |
5281 | /* XXX: TODO */ | |
e06fcd75 | 5282 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5283 | } |
5284 | ||
5285 | /* esa */ | |
99e300ef | 5286 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5287 | { |
5288 | /* XXX: TODO */ | |
e06fcd75 | 5289 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5290 | } |
5291 | ||
5292 | /* mfrom */ | |
99e300ef | 5293 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5294 | { |
5295 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5296 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5297 | #else |
76db3ba4 | 5298 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5299 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5300 | return; |
5301 | } | |
cf02a65c | 5302 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5303 | #endif |
5304 | } | |
5305 | ||
5306 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5307 | |
54623277 | 5308 | /* tlbld */ |
e8eaa2c0 | 5309 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5310 | { |
5311 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5312 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5313 | #else |
76db3ba4 | 5314 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5315 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5316 | return; |
5317 | } | |
c6c7cf05 | 5318 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5319 | #endif |
5320 | } | |
5321 | ||
5322 | /* tlbli */ | |
e8eaa2c0 | 5323 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5324 | { |
5325 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5326 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5327 | #else |
76db3ba4 | 5328 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5329 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5330 | return; |
5331 | } | |
c6c7cf05 | 5332 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5333 | #endif |
5334 | } | |
5335 | ||
7dbe11ac | 5336 | /* 74xx TLB management */ |
e8eaa2c0 | 5337 | |
54623277 | 5338 | /* tlbld */ |
e8eaa2c0 | 5339 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5340 | { |
5341 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5342 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5343 | #else |
76db3ba4 | 5344 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5345 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5346 | return; |
5347 | } | |
c6c7cf05 | 5348 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5349 | #endif |
5350 | } | |
5351 | ||
5352 | /* tlbli */ | |
e8eaa2c0 | 5353 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5354 | { |
5355 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5356 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5357 | #else |
76db3ba4 | 5358 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5359 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5360 | return; |
5361 | } | |
c6c7cf05 | 5362 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5363 | #endif |
5364 | } | |
5365 | ||
76a66253 | 5366 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5367 | |
54623277 | 5368 | /* clf */ |
99e300ef | 5369 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5370 | { |
5371 | /* Cache line flush: implemented as no-op */ | |
5372 | } | |
5373 | ||
5374 | /* cli */ | |
99e300ef | 5375 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5376 | { |
7f75ffd3 | 5377 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5378 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5379 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5380 | #else |
76db3ba4 | 5381 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5382 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5383 | return; |
5384 | } | |
5385 | #endif | |
5386 | } | |
5387 | ||
5388 | /* dclst */ | |
99e300ef | 5389 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5390 | { |
5391 | /* Data cache line store: treated as no-op */ | |
5392 | } | |
5393 | ||
99e300ef | 5394 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5395 | { |
5396 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5397 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5398 | #else |
74d37793 AJ |
5399 | int ra = rA(ctx->opcode); |
5400 | int rd = rD(ctx->opcode); | |
5401 | TCGv t0; | |
76db3ba4 | 5402 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5403 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5404 | return; |
5405 | } | |
74d37793 | 5406 | t0 = tcg_temp_new(); |
76db3ba4 | 5407 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5408 | tcg_gen_shri_tl(t0, t0, 28); |
5409 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5410 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5411 | tcg_temp_free(t0); |
76a66253 | 5412 | if (ra != 0 && ra != rd) |
74d37793 | 5413 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5414 | #endif |
5415 | } | |
5416 | ||
99e300ef | 5417 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5418 | { |
5419 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5420 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5421 | #else |
22e0e173 | 5422 | TCGv t0; |
76db3ba4 | 5423 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5424 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5425 | return; |
5426 | } | |
22e0e173 | 5427 | t0 = tcg_temp_new(); |
76db3ba4 | 5428 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5429 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5430 | tcg_temp_free(t0); |
76a66253 JM |
5431 | #endif |
5432 | } | |
5433 | ||
99e300ef | 5434 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5435 | { |
5436 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5437 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5438 | #else |
76db3ba4 | 5439 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5440 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5441 | return; |
5442 | } | |
e5f17ac6 | 5443 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5444 | gen_sync_exception(ctx); |
76a66253 JM |
5445 | #endif |
5446 | } | |
5447 | ||
5448 | /* svc is not implemented for now */ | |
5449 | ||
5450 | /* POWER2 specific instructions */ | |
5451 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5452 | |
5453 | /* lfq */ | |
99e300ef | 5454 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5455 | { |
01a4afeb | 5456 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5457 | TCGv t0; |
5458 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5459 | t0 = tcg_temp_new(); | |
5460 | gen_addr_imm_index(ctx, t0, 0); | |
5461 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5462 | gen_addr_add(ctx, t0, t0, 8); | |
5463 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5464 | tcg_temp_free(t0); |
76a66253 JM |
5465 | } |
5466 | ||
5467 | /* lfqu */ | |
99e300ef | 5468 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5469 | { |
5470 | int ra = rA(ctx->opcode); | |
01a4afeb | 5471 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5472 | TCGv t0, t1; |
5473 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5474 | t0 = tcg_temp_new(); | |
5475 | t1 = tcg_temp_new(); | |
5476 | gen_addr_imm_index(ctx, t0, 0); | |
5477 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5478 | gen_addr_add(ctx, t1, t0, 8); | |
5479 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5480 | if (ra != 0) |
01a4afeb AJ |
5481 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5482 | tcg_temp_free(t0); | |
5483 | tcg_temp_free(t1); | |
76a66253 JM |
5484 | } |
5485 | ||
5486 | /* lfqux */ | |
99e300ef | 5487 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5488 | { |
5489 | int ra = rA(ctx->opcode); | |
01a4afeb | 5490 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5491 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5492 | TCGv t0, t1; | |
5493 | t0 = tcg_temp_new(); | |
5494 | gen_addr_reg_index(ctx, t0); | |
5495 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5496 | t1 = tcg_temp_new(); | |
5497 | gen_addr_add(ctx, t1, t0, 8); | |
5498 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5499 | tcg_temp_free(t1); | |
76a66253 | 5500 | if (ra != 0) |
01a4afeb AJ |
5501 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5502 | tcg_temp_free(t0); | |
76a66253 JM |
5503 | } |
5504 | ||
5505 | /* lfqx */ | |
99e300ef | 5506 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5507 | { |
01a4afeb | 5508 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5509 | TCGv t0; |
5510 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5511 | t0 = tcg_temp_new(); | |
5512 | gen_addr_reg_index(ctx, t0); | |
5513 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5514 | gen_addr_add(ctx, t0, t0, 8); | |
5515 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5516 | tcg_temp_free(t0); |
76a66253 JM |
5517 | } |
5518 | ||
5519 | /* stfq */ | |
99e300ef | 5520 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5521 | { |
01a4afeb | 5522 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5523 | TCGv t0; |
5524 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5525 | t0 = tcg_temp_new(); | |
5526 | gen_addr_imm_index(ctx, t0, 0); | |
5527 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5528 | gen_addr_add(ctx, t0, t0, 8); | |
5529 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5530 | tcg_temp_free(t0); |
76a66253 JM |
5531 | } |
5532 | ||
5533 | /* stfqu */ | |
99e300ef | 5534 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5535 | { |
5536 | int ra = rA(ctx->opcode); | |
01a4afeb | 5537 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5538 | TCGv t0, t1; |
5539 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5540 | t0 = tcg_temp_new(); | |
5541 | gen_addr_imm_index(ctx, t0, 0); | |
5542 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5543 | t1 = tcg_temp_new(); | |
5544 | gen_addr_add(ctx, t1, t0, 8); | |
5545 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5546 | tcg_temp_free(t1); | |
76a66253 | 5547 | if (ra != 0) |
01a4afeb AJ |
5548 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5549 | tcg_temp_free(t0); | |
76a66253 JM |
5550 | } |
5551 | ||
5552 | /* stfqux */ | |
99e300ef | 5553 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5554 | { |
5555 | int ra = rA(ctx->opcode); | |
01a4afeb | 5556 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5557 | TCGv t0, t1; |
5558 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5559 | t0 = tcg_temp_new(); | |
5560 | gen_addr_reg_index(ctx, t0); | |
5561 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5562 | t1 = tcg_temp_new(); | |
5563 | gen_addr_add(ctx, t1, t0, 8); | |
5564 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5565 | tcg_temp_free(t1); | |
76a66253 | 5566 | if (ra != 0) |
01a4afeb AJ |
5567 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5568 | tcg_temp_free(t0); | |
76a66253 JM |
5569 | } |
5570 | ||
5571 | /* stfqx */ | |
99e300ef | 5572 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5573 | { |
01a4afeb | 5574 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5575 | TCGv t0; |
5576 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5577 | t0 = tcg_temp_new(); | |
5578 | gen_addr_reg_index(ctx, t0); | |
5579 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5580 | gen_addr_add(ctx, t0, t0, 8); | |
5581 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5582 | tcg_temp_free(t0); |
76a66253 JM |
5583 | } |
5584 | ||
5585 | /* BookE specific instructions */ | |
99e300ef | 5586 | |
54623277 | 5587 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5588 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5589 | { |
5590 | /* XXX: TODO */ | |
e06fcd75 | 5591 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5592 | } |
5593 | ||
2662a059 | 5594 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5595 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5596 | { |
5597 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5598 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5599 | #else |
74d37793 | 5600 | TCGv t0; |
76db3ba4 | 5601 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5602 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5603 | return; |
5604 | } | |
ec72e276 | 5605 | t0 = tcg_temp_new(); |
76db3ba4 | 5606 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5607 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5608 | tcg_temp_free(t0); |
76a66253 JM |
5609 | #endif |
5610 | } | |
5611 | ||
5612 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5613 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5614 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5615 | { |
182608d4 AJ |
5616 | TCGv t0, t1; |
5617 | ||
a7812ae4 PB |
5618 | t0 = tcg_temp_local_new(); |
5619 | t1 = tcg_temp_local_new(); | |
182608d4 | 5620 | |
76a66253 JM |
5621 | switch (opc3 & 0x0D) { |
5622 | case 0x05: | |
5623 | /* macchw - macchw. - macchwo - macchwo. */ | |
5624 | /* macchws - macchws. - macchwso - macchwso. */ | |
5625 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5626 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5627 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5628 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5629 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5630 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5631 | break; |
5632 | case 0x04: | |
5633 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5634 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5635 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5636 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5637 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5638 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5639 | break; |
5640 | case 0x01: | |
5641 | /* machhw - machhw. - machhwo - machhwo. */ | |
5642 | /* machhws - machhws. - machhwso - machhwso. */ | |
5643 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5644 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5645 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5646 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5647 | tcg_gen_ext16s_tl(t0, t0); | |
5648 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5649 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5650 | break; |
5651 | case 0x00: | |
5652 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5653 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5654 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5655 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5656 | tcg_gen_ext16u_tl(t0, t0); | |
5657 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5658 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5659 | break; |
5660 | case 0x0D: | |
5661 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5662 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5663 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5664 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5665 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5666 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5667 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5668 | break; |
5669 | case 0x0C: | |
5670 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5671 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5672 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5673 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5674 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5675 | break; |
5676 | } | |
76a66253 | 5677 | if (opc2 & 0x04) { |
182608d4 AJ |
5678 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5679 | tcg_gen_mul_tl(t1, t0, t1); | |
5680 | if (opc2 & 0x02) { | |
5681 | /* nmultiply-and-accumulate (0x0E) */ | |
5682 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5683 | } else { | |
5684 | /* multiply-and-accumulate (0x0C) */ | |
5685 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5686 | } | |
5687 | ||
5688 | if (opc3 & 0x12) { | |
5689 | /* Check overflow and/or saturate */ | |
5690 | int l1 = gen_new_label(); | |
5691 | ||
5692 | if (opc3 & 0x10) { | |
5693 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5694 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5695 | } |
5696 | if (opc3 & 0x01) { | |
5697 | /* Signed */ | |
5698 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5699 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5700 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5701 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5702 | if (opc3 & 0x02) { |
182608d4 AJ |
5703 | /* Saturate */ |
5704 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5705 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5706 | } | |
5707 | } else { | |
5708 | /* Unsigned */ | |
5709 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5710 | if (opc3 & 0x02) { |
182608d4 AJ |
5711 | /* Saturate */ |
5712 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5713 | } | |
5714 | } | |
5715 | if (opc3 & 0x10) { | |
5716 | /* Check overflow */ | |
da91a00f RH |
5717 | tcg_gen_movi_tl(cpu_ov, 1); |
5718 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5719 | } |
5720 | gen_set_label(l1); | |
5721 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5722 | } | |
5723 | } else { | |
5724 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5725 | } |
182608d4 AJ |
5726 | tcg_temp_free(t0); |
5727 | tcg_temp_free(t1); | |
76a66253 JM |
5728 | if (unlikely(Rc) != 0) { |
5729 | /* Update Rc0 */ | |
182608d4 | 5730 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5731 | } |
5732 | } | |
5733 | ||
a750fc0b | 5734 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5735 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5736 | { \ |
5737 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5738 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5739 | } | |
5740 | ||
5741 | /* macchw - macchw. */ | |
a750fc0b | 5742 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5743 | /* macchwo - macchwo. */ |
a750fc0b | 5744 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5745 | /* macchws - macchws. */ |
a750fc0b | 5746 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5747 | /* macchwso - macchwso. */ |
a750fc0b | 5748 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5749 | /* macchwsu - macchwsu. */ |
a750fc0b | 5750 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5751 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5752 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5753 | /* macchwu - macchwu. */ |
a750fc0b | 5754 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5755 | /* macchwuo - macchwuo. */ |
a750fc0b | 5756 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5757 | /* machhw - machhw. */ |
a750fc0b | 5758 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5759 | /* machhwo - machhwo. */ |
a750fc0b | 5760 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5761 | /* machhws - machhws. */ |
a750fc0b | 5762 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5763 | /* machhwso - machhwso. */ |
a750fc0b | 5764 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5765 | /* machhwsu - machhwsu. */ |
a750fc0b | 5766 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5767 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5768 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5769 | /* machhwu - machhwu. */ |
a750fc0b | 5770 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5771 | /* machhwuo - machhwuo. */ |
a750fc0b | 5772 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5773 | /* maclhw - maclhw. */ |
a750fc0b | 5774 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5775 | /* maclhwo - maclhwo. */ |
a750fc0b | 5776 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5777 | /* maclhws - maclhws. */ |
a750fc0b | 5778 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5779 | /* maclhwso - maclhwso. */ |
a750fc0b | 5780 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5781 | /* maclhwu - maclhwu. */ |
a750fc0b | 5782 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5783 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5784 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5785 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5786 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5787 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5788 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5789 | /* nmacchw - nmacchw. */ |
a750fc0b | 5790 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5791 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5792 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5793 | /* nmacchws - nmacchws. */ |
a750fc0b | 5794 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5795 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5796 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5797 | /* nmachhw - nmachhw. */ |
a750fc0b | 5798 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5799 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5800 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5801 | /* nmachhws - nmachhws. */ |
a750fc0b | 5802 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5803 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5804 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5805 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5806 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5807 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5808 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5809 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5810 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5811 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5812 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5813 | |
5814 | /* mulchw - mulchw. */ | |
a750fc0b | 5815 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5816 | /* mulchwu - mulchwu. */ |
a750fc0b | 5817 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5818 | /* mulhhw - mulhhw. */ |
a750fc0b | 5819 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5820 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5821 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5822 | /* mullhw - mullhw. */ |
a750fc0b | 5823 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5824 | /* mullhwu - mullhwu. */ |
a750fc0b | 5825 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5826 | |
5827 | /* mfdcr */ | |
99e300ef | 5828 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5829 | { |
5830 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5831 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5832 | #else |
06dca6a7 | 5833 | TCGv dcrn; |
76db3ba4 | 5834 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5835 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5836 | return; |
5837 | } | |
06dca6a7 AJ |
5838 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5839 | gen_update_nip(ctx, ctx->nip - 4); | |
5840 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5841 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5842 | tcg_temp_free(dcrn); |
76a66253 JM |
5843 | #endif |
5844 | } | |
5845 | ||
5846 | /* mtdcr */ | |
99e300ef | 5847 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5848 | { |
5849 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5850 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5851 | #else |
06dca6a7 | 5852 | TCGv dcrn; |
76db3ba4 | 5853 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5854 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5855 | return; |
5856 | } | |
06dca6a7 AJ |
5857 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5858 | gen_update_nip(ctx, ctx->nip - 4); | |
5859 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5860 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5861 | tcg_temp_free(dcrn); |
a42bd6cc JM |
5862 | #endif |
5863 | } | |
5864 | ||
5865 | /* mfdcrx */ | |
2662a059 | 5866 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5867 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5868 | { |
5869 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5870 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5871 | #else |
76db3ba4 | 5872 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5873 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5874 | return; |
5875 | } | |
06dca6a7 AJ |
5876 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5877 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5878 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5879 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5880 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
5881 | #endif |
5882 | } | |
5883 | ||
5884 | /* mtdcrx */ | |
2662a059 | 5885 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5886 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5887 | { |
5888 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5889 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5890 | #else |
76db3ba4 | 5891 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5892 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5893 | return; |
5894 | } | |
06dca6a7 AJ |
5895 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5896 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5897 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5898 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5899 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
5900 | #endif |
5901 | } | |
5902 | ||
a750fc0b | 5903 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5904 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5905 | { |
06dca6a7 AJ |
5906 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5907 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5908 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5909 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5910 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5911 | } | |
5912 | ||
5913 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5914 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5915 | { |
06dca6a7 AJ |
5916 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5917 | gen_update_nip(ctx, ctx->nip - 4); | |
975e5463 | 5918 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5919 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5920 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5921 | } | |
5922 | ||
76a66253 | 5923 | /* dccci */ |
99e300ef | 5924 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
5925 | { |
5926 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5927 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5928 | #else |
76db3ba4 | 5929 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5930 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5931 | return; |
5932 | } | |
5933 | /* interpreted as no-op */ | |
5934 | #endif | |
5935 | } | |
5936 | ||
5937 | /* dcread */ | |
99e300ef | 5938 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5939 | { |
5940 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5941 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5942 | #else |
b61f2753 | 5943 | TCGv EA, val; |
76db3ba4 | 5944 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5945 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5946 | return; |
5947 | } | |
76db3ba4 | 5948 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5949 | EA = tcg_temp_new(); |
76db3ba4 | 5950 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5951 | val = tcg_temp_new(); |
76db3ba4 | 5952 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5953 | tcg_temp_free(val); |
5954 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5955 | tcg_temp_free(EA); | |
76a66253 JM |
5956 | #endif |
5957 | } | |
5958 | ||
5959 | /* icbt */ | |
e8eaa2c0 | 5960 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5961 | { |
5962 | /* interpreted as no-op */ | |
5963 | /* XXX: specification say this is treated as a load by the MMU | |
5964 | * but does not generate any exception | |
5965 | */ | |
5966 | } | |
5967 | ||
5968 | /* iccci */ | |
99e300ef | 5969 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
5970 | { |
5971 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5972 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5973 | #else |
76db3ba4 | 5974 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5975 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5976 | return; |
5977 | } | |
5978 | /* interpreted as no-op */ | |
5979 | #endif | |
5980 | } | |
5981 | ||
5982 | /* icread */ | |
99e300ef | 5983 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
5984 | { |
5985 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5986 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5987 | #else |
76db3ba4 | 5988 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5989 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5990 | return; |
5991 | } | |
5992 | /* interpreted as no-op */ | |
5993 | #endif | |
5994 | } | |
5995 | ||
76db3ba4 | 5996 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 5997 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5998 | { |
5999 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6000 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6001 | #else |
76db3ba4 | 6002 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6003 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6004 | return; |
6005 | } | |
6006 | /* Restore CPU state */ | |
e5f17ac6 | 6007 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 6008 | gen_sync_exception(ctx); |
a42bd6cc JM |
6009 | #endif |
6010 | } | |
6011 | ||
99e300ef | 6012 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
6013 | { |
6014 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6015 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6016 | #else |
76db3ba4 | 6017 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6018 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6019 | return; |
6020 | } | |
6021 | /* Restore CPU state */ | |
e5f17ac6 | 6022 | gen_helper_rfci(cpu_env); |
e06fcd75 | 6023 | gen_sync_exception(ctx); |
a42bd6cc JM |
6024 | #endif |
6025 | } | |
6026 | ||
6027 | /* BookE specific */ | |
99e300ef | 6028 | |
54623277 | 6029 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6030 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
6031 | { |
6032 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6033 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6034 | #else |
76db3ba4 | 6035 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6036 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6037 | return; |
6038 | } | |
6039 | /* Restore CPU state */ | |
e5f17ac6 | 6040 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 6041 | gen_sync_exception(ctx); |
76a66253 JM |
6042 | #endif |
6043 | } | |
6044 | ||
2662a059 | 6045 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6046 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
6047 | { |
6048 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6049 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6050 | #else |
76db3ba4 | 6051 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6052 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6053 | return; |
6054 | } | |
6055 | /* Restore CPU state */ | |
e5f17ac6 | 6056 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 6057 | gen_sync_exception(ctx); |
a42bd6cc JM |
6058 | #endif |
6059 | } | |
5eb7995e | 6060 | |
d9bce9d9 | 6061 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 6062 | |
54623277 | 6063 | /* tlbre */ |
e8eaa2c0 | 6064 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
6065 | { |
6066 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6067 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6068 | #else |
76db3ba4 | 6069 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6070 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6071 | return; |
6072 | } | |
6073 | switch (rB(ctx->opcode)) { | |
6074 | case 0: | |
c6c7cf05 BS |
6075 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6076 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6077 | break; |
6078 | case 1: | |
c6c7cf05 BS |
6079 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6080 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6081 | break; |
6082 | default: | |
e06fcd75 | 6083 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6084 | break; |
9a64fbe4 | 6085 | } |
76a66253 JM |
6086 | #endif |
6087 | } | |
6088 | ||
d9bce9d9 | 6089 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 6090 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
6091 | { |
6092 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6093 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6094 | #else |
74d37793 | 6095 | TCGv t0; |
76db3ba4 | 6096 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6097 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6098 | return; |
6099 | } | |
74d37793 | 6100 | t0 = tcg_temp_new(); |
76db3ba4 | 6101 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6102 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6103 | tcg_temp_free(t0); |
6104 | if (Rc(ctx->opcode)) { | |
6105 | int l1 = gen_new_label(); | |
da91a00f | 6106 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6107 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6108 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6109 | gen_set_label(l1); | |
6110 | } | |
76a66253 | 6111 | #endif |
79aceca5 FB |
6112 | } |
6113 | ||
76a66253 | 6114 | /* tlbwe */ |
e8eaa2c0 | 6115 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6116 | { |
76a66253 | 6117 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 6118 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6119 | #else |
76db3ba4 | 6120 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6121 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6122 | return; |
6123 | } | |
6124 | switch (rB(ctx->opcode)) { | |
6125 | case 0: | |
c6c7cf05 BS |
6126 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6127 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6128 | break; |
6129 | case 1: | |
c6c7cf05 BS |
6130 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6131 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6132 | break; |
6133 | default: | |
e06fcd75 | 6134 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6135 | break; |
9a64fbe4 | 6136 | } |
76a66253 JM |
6137 | #endif |
6138 | } | |
6139 | ||
a4bb6c3e | 6140 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6141 | |
54623277 | 6142 | /* tlbre */ |
e8eaa2c0 | 6143 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6144 | { |
6145 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6146 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6147 | #else |
76db3ba4 | 6148 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6149 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6150 | return; |
6151 | } | |
6152 | switch (rB(ctx->opcode)) { | |
6153 | case 0: | |
5eb7995e | 6154 | case 1: |
5eb7995e | 6155 | case 2: |
74d37793 AJ |
6156 | { |
6157 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6158 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6159 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6160 | tcg_temp_free_i32(t0); |
6161 | } | |
5eb7995e JM |
6162 | break; |
6163 | default: | |
e06fcd75 | 6164 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6165 | break; |
6166 | } | |
6167 | #endif | |
6168 | } | |
6169 | ||
6170 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6171 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6172 | { |
6173 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6174 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6175 | #else |
74d37793 | 6176 | TCGv t0; |
76db3ba4 | 6177 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6178 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6179 | return; |
6180 | } | |
74d37793 | 6181 | t0 = tcg_temp_new(); |
76db3ba4 | 6182 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6183 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6184 | tcg_temp_free(t0); |
6185 | if (Rc(ctx->opcode)) { | |
6186 | int l1 = gen_new_label(); | |
da91a00f | 6187 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6188 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6189 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6190 | gen_set_label(l1); | |
6191 | } | |
5eb7995e JM |
6192 | #endif |
6193 | } | |
6194 | ||
6195 | /* tlbwe */ | |
e8eaa2c0 | 6196 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6197 | { |
6198 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6199 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6200 | #else |
76db3ba4 | 6201 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6202 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6203 | return; |
6204 | } | |
6205 | switch (rB(ctx->opcode)) { | |
6206 | case 0: | |
5eb7995e | 6207 | case 1: |
5eb7995e | 6208 | case 2: |
74d37793 AJ |
6209 | { |
6210 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6211 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6212 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6213 | tcg_temp_free_i32(t0); |
6214 | } | |
5eb7995e JM |
6215 | break; |
6216 | default: | |
e06fcd75 | 6217 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6218 | break; |
6219 | } | |
6220 | #endif | |
6221 | } | |
6222 | ||
01662f3e AG |
6223 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6224 | ||
6225 | /* tlbre */ | |
6226 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6227 | { | |
6228 | #if defined(CONFIG_USER_ONLY) | |
6229 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6230 | #else | |
6231 | if (unlikely(!ctx->mem_idx)) { | |
6232 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6233 | return; | |
6234 | } | |
6235 | ||
c6c7cf05 | 6236 | gen_helper_booke206_tlbre(cpu_env); |
01662f3e AG |
6237 | #endif |
6238 | } | |
6239 | ||
6240 | /* tlbsx - tlbsx. */ | |
6241 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6242 | { | |
6243 | #if defined(CONFIG_USER_ONLY) | |
6244 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6245 | #else | |
6246 | TCGv t0; | |
6247 | if (unlikely(!ctx->mem_idx)) { | |
6248 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6249 | return; | |
6250 | } | |
6251 | ||
6252 | if (rA(ctx->opcode)) { | |
6253 | t0 = tcg_temp_new(); | |
6254 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6255 | } else { | |
6256 | t0 = tcg_const_tl(0); | |
6257 | } | |
6258 | ||
6259 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6260 | gen_helper_booke206_tlbsx(cpu_env, t0); |
01662f3e AG |
6261 | #endif |
6262 | } | |
6263 | ||
6264 | /* tlbwe */ | |
6265 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6266 | { | |
6267 | #if defined(CONFIG_USER_ONLY) | |
6268 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6269 | #else | |
6270 | if (unlikely(!ctx->mem_idx)) { | |
6271 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6272 | return; | |
6273 | } | |
3f162d11 | 6274 | gen_update_nip(ctx, ctx->nip - 4); |
c6c7cf05 | 6275 | gen_helper_booke206_tlbwe(cpu_env); |
01662f3e AG |
6276 | #endif |
6277 | } | |
6278 | ||
6279 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6280 | { | |
6281 | #if defined(CONFIG_USER_ONLY) | |
6282 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6283 | #else | |
6284 | TCGv t0; | |
6285 | if (unlikely(!ctx->mem_idx)) { | |
6286 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6287 | return; | |
6288 | } | |
6289 | ||
6290 | t0 = tcg_temp_new(); | |
6291 | gen_addr_reg_index(ctx, t0); | |
6292 | ||
c6c7cf05 | 6293 | gen_helper_booke206_tlbivax(cpu_env, t0); |
01662f3e AG |
6294 | #endif |
6295 | } | |
6296 | ||
6d3db821 AG |
6297 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6298 | { | |
6299 | #if defined(CONFIG_USER_ONLY) | |
6300 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6301 | #else | |
6302 | TCGv t0; | |
6303 | if (unlikely(!ctx->mem_idx)) { | |
6304 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6305 | return; | |
6306 | } | |
6307 | ||
6308 | t0 = tcg_temp_new(); | |
6309 | gen_addr_reg_index(ctx, t0); | |
6310 | ||
6311 | switch((ctx->opcode >> 21) & 0x3) { | |
6312 | case 0: | |
c6c7cf05 | 6313 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6314 | break; |
6315 | case 1: | |
c6c7cf05 | 6316 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6317 | break; |
6318 | case 3: | |
c6c7cf05 | 6319 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6320 | break; |
6321 | default: | |
6322 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6323 | break; | |
6324 | } | |
6325 | ||
6326 | tcg_temp_free(t0); | |
6327 | #endif | |
6328 | } | |
6329 | ||
01662f3e | 6330 | |
76a66253 | 6331 | /* wrtee */ |
99e300ef | 6332 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6333 | { |
6334 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6335 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6336 | #else |
6527f6ea | 6337 | TCGv t0; |
76db3ba4 | 6338 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6339 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6340 | return; |
6341 | } | |
6527f6ea AJ |
6342 | t0 = tcg_temp_new(); |
6343 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6344 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6345 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6346 | tcg_temp_free(t0); | |
dee96f6c JM |
6347 | /* Stop translation to have a chance to raise an exception |
6348 | * if we just set msr_ee to 1 | |
6349 | */ | |
e06fcd75 | 6350 | gen_stop_exception(ctx); |
76a66253 JM |
6351 | #endif |
6352 | } | |
6353 | ||
6354 | /* wrteei */ | |
99e300ef | 6355 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6356 | { |
6357 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6358 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6359 | #else |
76db3ba4 | 6360 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6361 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6362 | return; |
6363 | } | |
fbe73008 | 6364 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6365 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6366 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6367 | gen_stop_exception(ctx); |
6527f6ea | 6368 | } else { |
1b6e5f99 | 6369 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6370 | } |
76a66253 JM |
6371 | #endif |
6372 | } | |
6373 | ||
08e46e54 | 6374 | /* PowerPC 440 specific instructions */ |
99e300ef | 6375 | |
54623277 | 6376 | /* dlmzb */ |
99e300ef | 6377 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6378 | { |
ef0d51af | 6379 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6380 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6381 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6382 | tcg_temp_free_i32(t0); |
76a66253 JM |
6383 | } |
6384 | ||
6385 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6386 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6387 | { |
6388 | /* interpreted as no-op */ | |
6389 | } | |
6390 | ||
6391 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6392 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6393 | { |
6394 | /* interpreted as no-op */ | |
6395 | } | |
6396 | ||
6397 | /* icbt */ | |
e8eaa2c0 | 6398 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6399 | { |
6400 | /* interpreted as no-op */ | |
6401 | /* XXX: specification say this is treated as a load by the MMU | |
6402 | * but does not generate any exception | |
6403 | */ | |
79aceca5 FB |
6404 | } |
6405 | ||
9e0b5cb1 AG |
6406 | /* Embedded.Processor Control */ |
6407 | ||
6408 | static void gen_msgclr(DisasContext *ctx) | |
6409 | { | |
6410 | #if defined(CONFIG_USER_ONLY) | |
6411 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6412 | #else | |
6413 | if (unlikely(ctx->mem_idx == 0)) { | |
6414 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6415 | return; | |
6416 | } | |
6417 | ||
e5f17ac6 | 6418 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9e0b5cb1 AG |
6419 | #endif |
6420 | } | |
6421 | ||
d5d11a39 AG |
6422 | static void gen_msgsnd(DisasContext *ctx) |
6423 | { | |
6424 | #if defined(CONFIG_USER_ONLY) | |
6425 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6426 | #else | |
6427 | if (unlikely(ctx->mem_idx == 0)) { | |
6428 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6429 | return; | |
6430 | } | |
6431 | ||
6432 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6433 | #endif | |
6434 | } | |
6435 | ||
a9d9eb8f JM |
6436 | /*** Altivec vector extension ***/ |
6437 | /* Altivec registers moves */ | |
a9d9eb8f | 6438 | |
636aa200 | 6439 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6440 | { |
e4704b3b | 6441 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6442 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6443 | return r; | |
6444 | } | |
6445 | ||
a9d9eb8f | 6446 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6447 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6448 | { \ |
fe1e5c53 | 6449 | TCGv EA; \ |
a9d9eb8f | 6450 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6451 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6452 | return; \ |
6453 | } \ | |
76db3ba4 | 6454 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6455 | EA = tcg_temp_new(); \ |
76db3ba4 | 6456 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6457 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6458 | if (ctx->le_mode) { \ |
6459 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6460 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6461 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6462 | } else { \ |
76db3ba4 | 6463 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6464 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6465 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6466 | } \ |
6467 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6468 | } |
6469 | ||
6470 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6471 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6472 | { \ |
fe1e5c53 | 6473 | TCGv EA; \ |
a9d9eb8f | 6474 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6475 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6476 | return; \ |
6477 | } \ | |
76db3ba4 | 6478 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6479 | EA = tcg_temp_new(); \ |
76db3ba4 | 6480 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6481 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6482 | if (ctx->le_mode) { \ |
6483 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6484 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6485 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6486 | } else { \ |
76db3ba4 | 6487 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6488 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6489 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6490 | } \ |
6491 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6492 | } |
6493 | ||
cbfb6ae9 | 6494 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef | 6495 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6496 | { \ |
6497 | TCGv EA; \ | |
6498 | TCGv_ptr rs; \ | |
6499 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6500 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6501 | return; \ | |
6502 | } \ | |
6503 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6504 | EA = tcg_temp_new(); \ | |
6505 | gen_addr_reg_index(ctx, EA); \ | |
6506 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6507 | gen_helper_lve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6508 | tcg_temp_free(EA); \ |
6509 | tcg_temp_free_ptr(rs); \ | |
6510 | } | |
6511 | ||
6512 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef | 6513 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6514 | { \ |
6515 | TCGv EA; \ | |
6516 | TCGv_ptr rs; \ | |
6517 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6518 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6519 | return; \ | |
6520 | } \ | |
6521 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6522 | EA = tcg_temp_new(); \ | |
6523 | gen_addr_reg_index(ctx, EA); \ | |
6524 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6525 | gen_helper_stve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6526 | tcg_temp_free(EA); \ |
6527 | tcg_temp_free_ptr(rs); \ | |
6528 | } | |
6529 | ||
fe1e5c53 | 6530 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6531 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6532 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6533 | |
cbfb6ae9 AJ |
6534 | GEN_VR_LVE(bx, 0x07, 0x00); |
6535 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6536 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6537 | ||
fe1e5c53 | 6538 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6539 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6540 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6541 | |
cbfb6ae9 AJ |
6542 | GEN_VR_STVE(bx, 0x07, 0x04); |
6543 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6544 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6545 | ||
99e300ef | 6546 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6547 | { |
6548 | TCGv_ptr rd; | |
6549 | TCGv EA; | |
6550 | if (unlikely(!ctx->altivec_enabled)) { | |
6551 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6552 | return; | |
6553 | } | |
6554 | EA = tcg_temp_new(); | |
6555 | gen_addr_reg_index(ctx, EA); | |
6556 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6557 | gen_helper_lvsl(rd, EA); | |
6558 | tcg_temp_free(EA); | |
6559 | tcg_temp_free_ptr(rd); | |
6560 | } | |
6561 | ||
99e300ef | 6562 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6563 | { |
6564 | TCGv_ptr rd; | |
6565 | TCGv EA; | |
6566 | if (unlikely(!ctx->altivec_enabled)) { | |
6567 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6568 | return; | |
6569 | } | |
6570 | EA = tcg_temp_new(); | |
6571 | gen_addr_reg_index(ctx, EA); | |
6572 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6573 | gen_helper_lvsr(rd, EA); | |
6574 | tcg_temp_free(EA); | |
6575 | tcg_temp_free_ptr(rd); | |
6576 | } | |
6577 | ||
99e300ef | 6578 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6579 | { |
6580 | TCGv_i32 t; | |
6581 | if (unlikely(!ctx->altivec_enabled)) { | |
6582 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6583 | return; | |
6584 | } | |
6585 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6586 | t = tcg_temp_new_i32(); | |
1328c2bf | 6587 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
785f451b | 6588 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
fce5ecb7 | 6589 | tcg_temp_free_i32(t); |
785f451b AJ |
6590 | } |
6591 | ||
99e300ef | 6592 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6593 | { |
6e87b7c7 | 6594 | TCGv_ptr p; |
785f451b AJ |
6595 | if (unlikely(!ctx->altivec_enabled)) { |
6596 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6597 | return; | |
6598 | } | |
6e87b7c7 | 6599 | p = gen_avr_ptr(rD(ctx->opcode)); |
d15f74fb | 6600 | gen_helper_mtvscr(cpu_env, p); |
6e87b7c7 | 6601 | tcg_temp_free_ptr(p); |
785f451b AJ |
6602 | } |
6603 | ||
7a9b96cf AJ |
6604 | /* Logical operations */ |
6605 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6606 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6607 | { \ |
6608 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6609 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6610 | return; \ | |
6611 | } \ | |
6612 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6613 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6614 | } | |
6615 | ||
6616 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6617 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6618 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6619 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6620 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
6621 | ||
8e27dd6f | 6622 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6623 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6624 | { \ |
6625 | TCGv_ptr ra, rb, rd; \ | |
6626 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6627 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6628 | return; \ | |
6629 | } \ | |
6630 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6631 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6632 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6633 | gen_helper_##name (rd, ra, rb); \ | |
6634 | tcg_temp_free_ptr(ra); \ | |
6635 | tcg_temp_free_ptr(rb); \ | |
6636 | tcg_temp_free_ptr(rd); \ | |
6637 | } | |
6638 | ||
d15f74fb BS |
6639 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
6640 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6641 | { \ | |
6642 | TCGv_ptr ra, rb, rd; \ | |
6643 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6644 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6645 | return; \ | |
6646 | } \ | |
6647 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6648 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6649 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
54cddd21 | 6650 | gen_helper_##name(cpu_env, rd, ra, rb); \ |
d15f74fb BS |
6651 | tcg_temp_free_ptr(ra); \ |
6652 | tcg_temp_free_ptr(rb); \ | |
6653 | tcg_temp_free_ptr(rd); \ | |
6654 | } | |
6655 | ||
7872c51c AJ |
6656 | GEN_VXFORM(vaddubm, 0, 0); |
6657 | GEN_VXFORM(vadduhm, 0, 1); | |
6658 | GEN_VXFORM(vadduwm, 0, 2); | |
6659 | GEN_VXFORM(vsububm, 0, 16); | |
6660 | GEN_VXFORM(vsubuhm, 0, 17); | |
6661 | GEN_VXFORM(vsubuwm, 0, 18); | |
e4039339 AJ |
6662 | GEN_VXFORM(vmaxub, 1, 0); |
6663 | GEN_VXFORM(vmaxuh, 1, 1); | |
6664 | GEN_VXFORM(vmaxuw, 1, 2); | |
6665 | GEN_VXFORM(vmaxsb, 1, 4); | |
6666 | GEN_VXFORM(vmaxsh, 1, 5); | |
6667 | GEN_VXFORM(vmaxsw, 1, 6); | |
6668 | GEN_VXFORM(vminub, 1, 8); | |
6669 | GEN_VXFORM(vminuh, 1, 9); | |
6670 | GEN_VXFORM(vminuw, 1, 10); | |
6671 | GEN_VXFORM(vminsb, 1, 12); | |
6672 | GEN_VXFORM(vminsh, 1, 13); | |
6673 | GEN_VXFORM(vminsw, 1, 14); | |
fab3cbe9 AJ |
6674 | GEN_VXFORM(vavgub, 1, 16); |
6675 | GEN_VXFORM(vavguh, 1, 17); | |
6676 | GEN_VXFORM(vavguw, 1, 18); | |
6677 | GEN_VXFORM(vavgsb, 1, 20); | |
6678 | GEN_VXFORM(vavgsh, 1, 21); | |
6679 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6680 | GEN_VXFORM(vmrghb, 6, 0); |
6681 | GEN_VXFORM(vmrghh, 6, 1); | |
6682 | GEN_VXFORM(vmrghw, 6, 2); | |
6683 | GEN_VXFORM(vmrglb, 6, 4); | |
6684 | GEN_VXFORM(vmrglh, 6, 5); | |
6685 | GEN_VXFORM(vmrglw, 6, 6); | |
2c277908 AJ |
6686 | GEN_VXFORM(vmuloub, 4, 0); |
6687 | GEN_VXFORM(vmulouh, 4, 1); | |
6688 | GEN_VXFORM(vmulosb, 4, 4); | |
6689 | GEN_VXFORM(vmulosh, 4, 5); | |
6690 | GEN_VXFORM(vmuleub, 4, 8); | |
6691 | GEN_VXFORM(vmuleuh, 4, 9); | |
6692 | GEN_VXFORM(vmulesb, 4, 12); | |
6693 | GEN_VXFORM(vmulesh, 4, 13); | |
d79f0809 AJ |
6694 | GEN_VXFORM(vslb, 2, 4); |
6695 | GEN_VXFORM(vslh, 2, 5); | |
6696 | GEN_VXFORM(vslw, 2, 6); | |
07ef34c3 AJ |
6697 | GEN_VXFORM(vsrb, 2, 8); |
6698 | GEN_VXFORM(vsrh, 2, 9); | |
6699 | GEN_VXFORM(vsrw, 2, 10); | |
6700 | GEN_VXFORM(vsrab, 2, 12); | |
6701 | GEN_VXFORM(vsrah, 2, 13); | |
6702 | GEN_VXFORM(vsraw, 2, 14); | |
7b239bec AJ |
6703 | GEN_VXFORM(vslo, 6, 16); |
6704 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
6705 | GEN_VXFORM(vaddcuw, 0, 6); |
6706 | GEN_VXFORM(vsubcuw, 0, 22); | |
d15f74fb BS |
6707 | GEN_VXFORM_ENV(vaddubs, 0, 8); |
6708 | GEN_VXFORM_ENV(vadduhs, 0, 9); | |
6709 | GEN_VXFORM_ENV(vadduws, 0, 10); | |
6710 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
6711 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
6712 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
6713 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
6714 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
6715 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
6716 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
6717 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
6718 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
5e1d0985 AJ |
6719 | GEN_VXFORM(vrlb, 2, 0); |
6720 | GEN_VXFORM(vrlh, 2, 1); | |
6721 | GEN_VXFORM(vrlw, 2, 2); | |
d9430add AJ |
6722 | GEN_VXFORM(vsl, 2, 7); |
6723 | GEN_VXFORM(vsr, 2, 11); | |
d15f74fb BS |
6724 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
6725 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
6726 | GEN_VXFORM_ENV(vpkuhus, 7, 2); | |
6727 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
6728 | GEN_VXFORM_ENV(vpkshus, 7, 4); | |
6729 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
6730 | GEN_VXFORM_ENV(vpkshss, 7, 6); | |
6731 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
1dd9ffb9 | 6732 | GEN_VXFORM(vpkpx, 7, 12); |
d15f74fb BS |
6733 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
6734 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
6735 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
6736 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
6737 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
6738 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
6739 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
6740 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
6741 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
fab3cbe9 | 6742 | |
0cbcd906 | 6743 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 6744 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
6745 | { \ |
6746 | TCGv_ptr ra, rb, rd; \ | |
6747 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6748 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6749 | return; \ | |
6750 | } \ | |
6751 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6752 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6753 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
d15f74fb | 6754 | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
0cbcd906 AJ |
6755 | tcg_temp_free_ptr(ra); \ |
6756 | tcg_temp_free_ptr(rb); \ | |
6757 | tcg_temp_free_ptr(rd); \ | |
6758 | } | |
6759 | ||
6760 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
6761 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
6762 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
6763 | ||
1add6e23 AJ |
6764 | GEN_VXRFORM(vcmpequb, 3, 0) |
6765 | GEN_VXRFORM(vcmpequh, 3, 1) | |
6766 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6767 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
6768 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
6769 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6770 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
6771 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
6772 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
819ca121 AJ |
6773 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6774 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
6775 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
6776 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 6777 | |
c026766b | 6778 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6779 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
6780 | { \ |
6781 | TCGv_ptr rd; \ | |
6782 | TCGv_i32 simm; \ | |
6783 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6784 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6785 | return; \ | |
6786 | } \ | |
6787 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6788 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6789 | gen_helper_##name (rd, simm); \ | |
6790 | tcg_temp_free_i32(simm); \ | |
6791 | tcg_temp_free_ptr(rd); \ | |
6792 | } | |
6793 | ||
6794 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
6795 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
6796 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
6797 | ||
de5f2484 | 6798 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 6799 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
6800 | { \ |
6801 | TCGv_ptr rb, rd; \ | |
6802 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6803 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6804 | return; \ | |
6805 | } \ | |
6806 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6807 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6808 | gen_helper_##name (rd, rb); \ | |
6809 | tcg_temp_free_ptr(rb); \ | |
6810 | tcg_temp_free_ptr(rd); \ | |
6811 | } | |
6812 | ||
d15f74fb BS |
6813 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ |
6814 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6815 | { \ | |
6816 | TCGv_ptr rb, rd; \ | |
6817 | \ | |
6818 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6819 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6820 | return; \ | |
6821 | } \ | |
6822 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6823 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6824 | gen_helper_##name(cpu_env, rd, rb); \ | |
6825 | tcg_temp_free_ptr(rb); \ | |
6826 | tcg_temp_free_ptr(rd); \ | |
6827 | } | |
6828 | ||
6cf1c6e5 AJ |
6829 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6830 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
6831 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
6832 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
79f85c3a AJ |
6833 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6834 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
d15f74fb BS |
6835 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
6836 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
6837 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
6838 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
6839 | GEN_VXFORM_NOA_ENV(vrfim, 5, 8); | |
6840 | GEN_VXFORM_NOA_ENV(vrfin, 5, 9); | |
6841 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
6842 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 11); | |
79f85c3a | 6843 | |
21d21583 | 6844 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6845 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
6846 | { \ |
6847 | TCGv_ptr rd; \ | |
6848 | TCGv_i32 simm; \ | |
6849 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6850 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6851 | return; \ | |
6852 | } \ | |
6853 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6854 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6855 | gen_helper_##name (rd, simm); \ | |
6856 | tcg_temp_free_i32(simm); \ | |
6857 | tcg_temp_free_ptr(rd); \ | |
6858 | } | |
6859 | ||
27a4edb3 | 6860 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 6861 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
6862 | { \ |
6863 | TCGv_ptr rb, rd; \ | |
6864 | TCGv_i32 uimm; \ | |
6865 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6866 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6867 | return; \ | |
6868 | } \ | |
6869 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6870 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6871 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6872 | gen_helper_##name (rd, rb, uimm); \ | |
6873 | tcg_temp_free_i32(uimm); \ | |
6874 | tcg_temp_free_ptr(rb); \ | |
6875 | tcg_temp_free_ptr(rd); \ | |
6876 | } | |
6877 | ||
d15f74fb BS |
6878 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
6879 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6880 | { \ | |
6881 | TCGv_ptr rb, rd; \ | |
6882 | TCGv_i32 uimm; \ | |
6883 | \ | |
6884 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6885 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6886 | return; \ | |
6887 | } \ | |
6888 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6889 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6890 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6891 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
6892 | tcg_temp_free_i32(uimm); \ | |
6893 | tcg_temp_free_ptr(rb); \ | |
6894 | tcg_temp_free_ptr(rd); \ | |
6895 | } | |
6896 | ||
e4e6bee7 AJ |
6897 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6898 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
6899 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
d15f74fb BS |
6900 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
6901 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
6902 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
6903 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
e4e6bee7 | 6904 | |
99e300ef | 6905 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
6906 | { |
6907 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 6908 | TCGv_i32 sh; |
cd633b10 AJ |
6909 | if (unlikely(!ctx->altivec_enabled)) { |
6910 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6911 | return; | |
6912 | } | |
6913 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6914 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6915 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6916 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
6917 | gen_helper_vsldoi (rd, ra, rb, sh); | |
6918 | tcg_temp_free_ptr(ra); | |
6919 | tcg_temp_free_ptr(rb); | |
6920 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 6921 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
6922 | } |
6923 | ||
707cec33 | 6924 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
d15f74fb | 6925 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
6926 | { \ |
6927 | TCGv_ptr ra, rb, rc, rd; \ | |
6928 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6929 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6930 | return; \ | |
6931 | } \ | |
6932 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6933 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6934 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6935 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6936 | if (Rc(ctx->opcode)) { \ | |
d15f74fb | 6937 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
707cec33 | 6938 | } else { \ |
d15f74fb | 6939 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
707cec33 AJ |
6940 | } \ |
6941 | tcg_temp_free_ptr(ra); \ | |
6942 | tcg_temp_free_ptr(rb); \ | |
6943 | tcg_temp_free_ptr(rc); \ | |
6944 | tcg_temp_free_ptr(rd); \ | |
6945 | } | |
6946 | ||
b161ae27 AJ |
6947 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
6948 | ||
99e300ef | 6949 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
6950 | { |
6951 | TCGv_ptr ra, rb, rc, rd; | |
6952 | if (unlikely(!ctx->altivec_enabled)) { | |
6953 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6954 | return; | |
6955 | } | |
6956 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6957 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6958 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
6959 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6960 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
6961 | tcg_temp_free_ptr(ra); | |
6962 | tcg_temp_free_ptr(rb); | |
6963 | tcg_temp_free_ptr(rc); | |
6964 | tcg_temp_free_ptr(rd); | |
6965 | } | |
6966 | ||
b04ae981 | 6967 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 6968 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 6969 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 6970 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 6971 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 6972 | |
0487d6a8 | 6973 | /*** SPE extension ***/ |
0487d6a8 | 6974 | /* Register moves */ |
3cd7d1dd | 6975 | |
a0e13900 FC |
6976 | |
6977 | static inline void gen_evmra(DisasContext *ctx) | |
6978 | { | |
6979 | ||
6980 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 6981 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
6982 | return; |
6983 | } | |
6984 | ||
6985 | #if defined(TARGET_PPC64) | |
6986 | /* rD := rA */ | |
6987 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6988 | ||
6989 | /* spe_acc := rA */ | |
6990 | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], | |
6991 | cpu_env, | |
1328c2bf | 6992 | offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
6993 | #else |
6994 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
6995 | ||
6996 | /* tmp := rA_lo + rA_hi << 32 */ | |
6997 | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6998 | ||
6999 | /* spe_acc := tmp */ | |
1328c2bf | 7000 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7001 | tcg_temp_free_i64(tmp); |
7002 | ||
7003 | /* rD := rA */ | |
7004 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7005 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7006 | #endif | |
7007 | } | |
7008 | ||
636aa200 BS |
7009 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
7010 | { | |
f78fb44e AJ |
7011 | #if defined(TARGET_PPC64) |
7012 | tcg_gen_mov_i64(t, cpu_gpr[reg]); | |
7013 | #else | |
36aa55dc | 7014 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
3cd7d1dd | 7015 | #endif |
f78fb44e | 7016 | } |
3cd7d1dd | 7017 | |
636aa200 BS |
7018 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
7019 | { | |
f78fb44e AJ |
7020 | #if defined(TARGET_PPC64) |
7021 | tcg_gen_mov_i64(cpu_gpr[reg], t); | |
7022 | #else | |
a7812ae4 | 7023 | TCGv_i64 tmp = tcg_temp_new_i64(); |
f78fb44e | 7024 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
f78fb44e AJ |
7025 | tcg_gen_shri_i64(tmp, t, 32); |
7026 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); | |
a7812ae4 | 7027 | tcg_temp_free_i64(tmp); |
3cd7d1dd | 7028 | #endif |
f78fb44e | 7029 | } |
3cd7d1dd | 7030 | |
70560da7 | 7031 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
99e300ef | 7032 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
7033 | { \ |
7034 | if (Rc(ctx->opcode)) \ | |
7035 | gen_##name1(ctx); \ | |
7036 | else \ | |
7037 | gen_##name0(ctx); \ | |
7038 | } | |
7039 | ||
7040 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 7041 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 7042 | { |
e06fcd75 | 7043 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
7044 | } |
7045 | ||
57951c27 AJ |
7046 | /* SPE logic */ |
7047 | #if defined(TARGET_PPC64) | |
7048 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 7049 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7050 | { \ |
7051 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7052 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7053 | return; \ |
7054 | } \ | |
57951c27 AJ |
7055 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7056 | cpu_gpr[rB(ctx->opcode)]); \ | |
7057 | } | |
7058 | #else | |
7059 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 7060 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7061 | { \ |
7062 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7063 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7064 | return; \ |
7065 | } \ | |
7066 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
7067 | cpu_gpr[rB(ctx->opcode)]); \ | |
7068 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7069 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 7070 | } |
57951c27 AJ |
7071 | #endif |
7072 | ||
7073 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
7074 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
7075 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
7076 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
7077 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
7078 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
7079 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
7080 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 7081 | |
57951c27 AJ |
7082 | /* SPE logic immediate */ |
7083 | #if defined(TARGET_PPC64) | |
7084 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 7085 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a AJ |
7086 | { \ |
7087 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7088 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
3d3a6a0a AJ |
7089 | return; \ |
7090 | } \ | |
a7812ae4 PB |
7091 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7092 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7093 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7094 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7095 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
7096 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7097 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7098 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7099 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
7100 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7101 | tcg_temp_free_i32(t0); \ |
7102 | tcg_temp_free_i32(t1); \ | |
3d3a6a0a | 7103 | } |
57951c27 AJ |
7104 | #else |
7105 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 7106 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7107 | { \ |
7108 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7109 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7110 | return; \ |
7111 | } \ | |
57951c27 AJ |
7112 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7113 | rB(ctx->opcode)); \ | |
7114 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7115 | rB(ctx->opcode)); \ | |
0487d6a8 | 7116 | } |
57951c27 AJ |
7117 | #endif |
7118 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); | |
7119 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
7120 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
7121 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 7122 | |
57951c27 AJ |
7123 | /* SPE arithmetic */ |
7124 | #if defined(TARGET_PPC64) | |
7125 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
636aa200 | 7126 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7127 | { \ |
7128 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7129 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7130 | return; \ |
7131 | } \ | |
a7812ae4 PB |
7132 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7133 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7134 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7135 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7136 | tcg_op(t0, t0); \ | |
7137 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7138 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7139 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7140 | tcg_op(t1, t1); \ |
7141 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7142 | tcg_temp_free_i32(t0); \ |
7143 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7144 | } |
57951c27 | 7145 | #else |
a7812ae4 | 7146 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 7147 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7148 | { \ |
7149 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7150 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7151 | return; \ |
7152 | } \ | |
7153 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ | |
7154 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
7155 | } | |
7156 | #endif | |
0487d6a8 | 7157 | |
636aa200 | 7158 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
7159 | { |
7160 | int l1 = gen_new_label(); | |
7161 | int l2 = gen_new_label(); | |
0487d6a8 | 7162 | |
57951c27 AJ |
7163 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
7164 | tcg_gen_neg_i32(ret, arg1); | |
7165 | tcg_gen_br(l2); | |
7166 | gen_set_label(l1); | |
a7812ae4 | 7167 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
7168 | gen_set_label(l2); |
7169 | } | |
7170 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
7171 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
7172 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
7173 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 7174 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 7175 | { |
57951c27 AJ |
7176 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
7177 | tcg_gen_ext16u_i32(ret, ret); | |
7178 | } | |
7179 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
7180 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
7181 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 7182 | |
57951c27 AJ |
7183 | #if defined(TARGET_PPC64) |
7184 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7185 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7186 | { \ |
7187 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7188 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7189 | return; \ |
7190 | } \ | |
a7812ae4 PB |
7191 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7192 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7193 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ | |
501e23c4 | 7194 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
57951c27 AJ |
7195 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7196 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ | |
7197 | tcg_op(t0, t0, t2); \ | |
7198 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7199 | tcg_gen_trunc_i64_i32(t1, t3); \ | |
7200 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7201 | tcg_gen_trunc_i64_i32(t2, t3); \ | |
a7812ae4 | 7202 | tcg_temp_free_i64(t3); \ |
57951c27 | 7203 | tcg_op(t1, t1, t2); \ |
a7812ae4 | 7204 | tcg_temp_free_i32(t2); \ |
57951c27 | 7205 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
a7812ae4 PB |
7206 | tcg_temp_free_i32(t0); \ |
7207 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7208 | } |
57951c27 AJ |
7209 | #else |
7210 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7211 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7212 | { \ |
7213 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7214 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7215 | return; \ |
7216 | } \ | |
57951c27 AJ |
7217 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7218 | cpu_gpr[rB(ctx->opcode)]); \ | |
7219 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7220 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 7221 | } |
57951c27 | 7222 | #endif |
0487d6a8 | 7223 | |
636aa200 | 7224 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7225 | { |
a7812ae4 | 7226 | TCGv_i32 t0; |
57951c27 | 7227 | int l1, l2; |
0487d6a8 | 7228 | |
57951c27 AJ |
7229 | l1 = gen_new_label(); |
7230 | l2 = gen_new_label(); | |
a7812ae4 | 7231 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7232 | /* No error here: 6 bits are used */ |
7233 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7234 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7235 | tcg_gen_shr_i32(ret, arg1, t0); | |
7236 | tcg_gen_br(l2); | |
7237 | gen_set_label(l1); | |
7238 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7239 | gen_set_label(l2); |
a7812ae4 | 7240 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7241 | } |
7242 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 7243 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7244 | { |
a7812ae4 | 7245 | TCGv_i32 t0; |
57951c27 AJ |
7246 | int l1, l2; |
7247 | ||
7248 | l1 = gen_new_label(); | |
7249 | l2 = gen_new_label(); | |
a7812ae4 | 7250 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7251 | /* No error here: 6 bits are used */ |
7252 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7253 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7254 | tcg_gen_sar_i32(ret, arg1, t0); | |
7255 | tcg_gen_br(l2); | |
7256 | gen_set_label(l1); | |
7257 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7258 | gen_set_label(l2); |
a7812ae4 | 7259 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7260 | } |
7261 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 7262 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7263 | { |
a7812ae4 | 7264 | TCGv_i32 t0; |
57951c27 AJ |
7265 | int l1, l2; |
7266 | ||
7267 | l1 = gen_new_label(); | |
7268 | l2 = gen_new_label(); | |
a7812ae4 | 7269 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7270 | /* No error here: 6 bits are used */ |
7271 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7272 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7273 | tcg_gen_shl_i32(ret, arg1, t0); | |
7274 | tcg_gen_br(l2); | |
7275 | gen_set_label(l1); | |
7276 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 7277 | gen_set_label(l2); |
a7812ae4 | 7278 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7279 | } |
7280 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 7281 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7282 | { |
a7812ae4 | 7283 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
7284 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
7285 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 7286 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7287 | } |
7288 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 7289 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
7290 | { |
7291 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7292 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7293 | return; |
7294 | } | |
7295 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7296 | TCGv t0 = tcg_temp_new(); |
7297 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7298 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7299 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
7300 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7301 | tcg_temp_free(t0); | |
7302 | tcg_temp_free(t1); | |
7303 | #else | |
7304 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7305 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7306 | #endif | |
7307 | } | |
7308 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 7309 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 7310 | { |
57951c27 AJ |
7311 | tcg_gen_sub_i32(ret, arg2, arg1); |
7312 | } | |
7313 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 7314 | |
57951c27 AJ |
7315 | /* SPE arithmetic immediate */ |
7316 | #if defined(TARGET_PPC64) | |
7317 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7318 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7319 | { \ |
7320 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7321 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7322 | return; \ |
7323 | } \ | |
a7812ae4 PB |
7324 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7325 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7326 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7327 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7328 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
7329 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7330 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
e06fcd75 | 7331 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7332 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
7333 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7334 | tcg_temp_free_i32(t0); \ |
7335 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7336 | } |
7337 | #else | |
7338 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7339 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7340 | { \ |
7341 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7342 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7343 | return; \ |
7344 | } \ | |
7345 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
7346 | rA(ctx->opcode)); \ | |
7347 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ | |
7348 | rA(ctx->opcode)); \ | |
7349 | } | |
7350 | #endif | |
7351 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); | |
7352 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
7353 | ||
7354 | /* SPE comparison */ | |
7355 | #if defined(TARGET_PPC64) | |
7356 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7357 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7358 | { \ |
7359 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7360 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7361 | return; \ |
7362 | } \ | |
7363 | int l1 = gen_new_label(); \ | |
7364 | int l2 = gen_new_label(); \ | |
7365 | int l3 = gen_new_label(); \ | |
7366 | int l4 = gen_new_label(); \ | |
a7812ae4 PB |
7367 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7368 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7369 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7370 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7371 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7372 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ | |
a7812ae4 | 7373 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
7374 | tcg_gen_br(l2); \ |
7375 | gen_set_label(l1); \ | |
7376 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7377 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7378 | gen_set_label(l2); \ | |
7379 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7380 | tcg_gen_trunc_i64_i32(t0, t2); \ | |
7381 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7382 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7383 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7384 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
7385 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7386 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7387 | tcg_gen_br(l4); \ | |
7388 | gen_set_label(l3); \ | |
7389 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7390 | CRF_CH | CRF_CH_OR_CL); \ | |
7391 | gen_set_label(l4); \ | |
a7812ae4 PB |
7392 | tcg_temp_free_i32(t0); \ |
7393 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7394 | } |
7395 | #else | |
7396 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7397 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7398 | { \ |
7399 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7400 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7401 | return; \ |
7402 | } \ | |
7403 | int l1 = gen_new_label(); \ | |
7404 | int l2 = gen_new_label(); \ | |
7405 | int l3 = gen_new_label(); \ | |
7406 | int l4 = gen_new_label(); \ | |
7407 | \ | |
7408 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
7409 | cpu_gpr[rB(ctx->opcode)], l1); \ | |
7410 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ | |
7411 | tcg_gen_br(l2); \ | |
7412 | gen_set_label(l1); \ | |
7413 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7414 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7415 | gen_set_label(l2); \ | |
7416 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ | |
7417 | cpu_gprh[rB(ctx->opcode)], l3); \ | |
7418 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7419 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7420 | tcg_gen_br(l4); \ | |
7421 | gen_set_label(l3); \ | |
7422 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7423 | CRF_CH | CRF_CH_OR_CL); \ | |
7424 | gen_set_label(l4); \ | |
7425 | } | |
7426 | #endif | |
7427 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); | |
7428 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
7429 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
7430 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
7431 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
7432 | ||
7433 | /* SPE misc */ | |
636aa200 | 7434 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
7435 | { |
7436 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
7437 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
7438 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 7439 | } |
636aa200 | 7440 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
7441 | { |
7442 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7443 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7444 | return; |
7445 | } | |
7446 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7447 | TCGv t0 = tcg_temp_new(); |
7448 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7449 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7450 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); |
7451 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7452 | tcg_temp_free(t0); | |
7453 | tcg_temp_free(t1); | |
7454 | #else | |
57951c27 | 7455 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
33890b3e | 7456 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7457 | #endif |
7458 | } | |
636aa200 | 7459 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
7460 | { |
7461 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7462 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7463 | return; |
7464 | } | |
7465 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7466 | TCGv t0 = tcg_temp_new(); |
7467 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7468 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7469 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); |
7470 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7471 | tcg_temp_free(t0); | |
7472 | tcg_temp_free(t1); | |
7473 | #else | |
7474 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7475 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7476 | #endif | |
7477 | } | |
636aa200 | 7478 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
7479 | { |
7480 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7481 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7482 | return; |
7483 | } | |
7484 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7485 | TCGv t0 = tcg_temp_new(); |
7486 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7487 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7488 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
7489 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7490 | tcg_temp_free(t0); | |
7491 | tcg_temp_free(t1); | |
7492 | #else | |
33890b3e NF |
7493 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
7494 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
7495 | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); | |
7496 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7497 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); | |
7498 | tcg_temp_free_i32(tmp); | |
7499 | } else { | |
7500 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7501 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7502 | } | |
57951c27 AJ |
7503 | #endif |
7504 | } | |
636aa200 | 7505 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 7506 | { |
ae01847f | 7507 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 7508 | |
57951c27 | 7509 | #if defined(TARGET_PPC64) |
38d14952 | 7510 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7511 | #else |
7512 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7513 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7514 | #endif | |
7515 | } | |
636aa200 | 7516 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 7517 | { |
ae01847f | 7518 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 7519 | |
57951c27 | 7520 | #if defined(TARGET_PPC64) |
38d14952 | 7521 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7522 | #else |
7523 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7524 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7525 | #endif | |
0487d6a8 JM |
7526 | } |
7527 | ||
636aa200 | 7528 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 AJ |
7529 | { |
7530 | int l1 = gen_new_label(); | |
7531 | int l2 = gen_new_label(); | |
7532 | int l3 = gen_new_label(); | |
7533 | int l4 = gen_new_label(); | |
a7812ae4 | 7534 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 | 7535 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
7536 | TCGv t1 = tcg_temp_local_new(); |
7537 | TCGv t2 = tcg_temp_local_new(); | |
57951c27 AJ |
7538 | #endif |
7539 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); | |
7540 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
7541 | #if defined(TARGET_PPC64) | |
7542 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7543 | #else | |
7544 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7545 | #endif | |
7546 | tcg_gen_br(l2); | |
7547 | gen_set_label(l1); | |
7548 | #if defined(TARGET_PPC64) | |
7549 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7550 | #else | |
7551 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7552 | #endif | |
7553 | gen_set_label(l2); | |
7554 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
7555 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
7556 | #if defined(TARGET_PPC64) | |
17d9b3af | 7557 | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
7558 | #else |
7559 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7560 | #endif | |
7561 | tcg_gen_br(l4); | |
7562 | gen_set_label(l3); | |
7563 | #if defined(TARGET_PPC64) | |
17d9b3af | 7564 | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7565 | #else |
7566 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7567 | #endif | |
7568 | gen_set_label(l4); | |
a7812ae4 | 7569 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7570 | #if defined(TARGET_PPC64) |
7571 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); | |
7572 | tcg_temp_free(t1); | |
7573 | tcg_temp_free(t2); | |
7574 | #endif | |
7575 | } | |
e8eaa2c0 BS |
7576 | |
7577 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
7578 | { |
7579 | gen_evsel(ctx); | |
7580 | } | |
e8eaa2c0 BS |
7581 | |
7582 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
7583 | { |
7584 | gen_evsel(ctx); | |
7585 | } | |
e8eaa2c0 BS |
7586 | |
7587 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
7588 | { |
7589 | gen_evsel(ctx); | |
7590 | } | |
e8eaa2c0 BS |
7591 | |
7592 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
7593 | { |
7594 | gen_evsel(ctx); | |
7595 | } | |
0487d6a8 | 7596 | |
a0e13900 FC |
7597 | /* Multiply */ |
7598 | ||
7599 | static inline void gen_evmwumi(DisasContext *ctx) | |
7600 | { | |
7601 | TCGv_i64 t0, t1; | |
7602 | ||
7603 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7604 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7605 | return; |
7606 | } | |
7607 | ||
7608 | t0 = tcg_temp_new_i64(); | |
7609 | t1 = tcg_temp_new_i64(); | |
7610 | ||
7611 | /* t0 := rA; t1 := rB */ | |
7612 | #if defined(TARGET_PPC64) | |
7613 | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7614 | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7615 | #else | |
7616 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7617 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7618 | #endif | |
7619 | ||
7620 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7621 | ||
7622 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7623 | ||
7624 | tcg_temp_free_i64(t0); | |
7625 | tcg_temp_free_i64(t1); | |
7626 | } | |
7627 | ||
7628 | static inline void gen_evmwumia(DisasContext *ctx) | |
7629 | { | |
7630 | TCGv_i64 tmp; | |
7631 | ||
7632 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7633 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7634 | return; |
7635 | } | |
7636 | ||
7637 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7638 | ||
7639 | tmp = tcg_temp_new_i64(); | |
7640 | ||
7641 | /* acc := rD */ | |
7642 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7643 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7644 | tcg_temp_free_i64(tmp); |
7645 | } | |
7646 | ||
7647 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
7648 | { | |
7649 | TCGv_i64 acc; | |
7650 | TCGv_i64 tmp; | |
7651 | ||
7652 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7653 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7654 | return; |
7655 | } | |
7656 | ||
7657 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7658 | ||
7659 | acc = tcg_temp_new_i64(); | |
7660 | tmp = tcg_temp_new_i64(); | |
7661 | ||
7662 | /* tmp := rD */ | |
7663 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7664 | ||
7665 | /* Load acc */ | |
1328c2bf | 7666 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7667 | |
7668 | /* acc := tmp + acc */ | |
7669 | tcg_gen_add_i64(acc, acc, tmp); | |
7670 | ||
7671 | /* Store acc */ | |
1328c2bf | 7672 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7673 | |
7674 | /* rD := acc */ | |
7675 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7676 | ||
7677 | tcg_temp_free_i64(acc); | |
7678 | tcg_temp_free_i64(tmp); | |
7679 | } | |
7680 | ||
7681 | static inline void gen_evmwsmi(DisasContext *ctx) | |
7682 | { | |
7683 | TCGv_i64 t0, t1; | |
7684 | ||
7685 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7686 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7687 | return; |
7688 | } | |
7689 | ||
7690 | t0 = tcg_temp_new_i64(); | |
7691 | t1 = tcg_temp_new_i64(); | |
7692 | ||
7693 | /* t0 := rA; t1 := rB */ | |
7694 | #if defined(TARGET_PPC64) | |
7695 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7696 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7697 | #else | |
7698 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7699 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7700 | #endif | |
7701 | ||
7702 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7703 | ||
7704 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7705 | ||
7706 | tcg_temp_free_i64(t0); | |
7707 | tcg_temp_free_i64(t1); | |
7708 | } | |
7709 | ||
7710 | static inline void gen_evmwsmia(DisasContext *ctx) | |
7711 | { | |
7712 | TCGv_i64 tmp; | |
7713 | ||
7714 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7715 | ||
7716 | tmp = tcg_temp_new_i64(); | |
7717 | ||
7718 | /* acc := rD */ | |
7719 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7720 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7721 | |
7722 | tcg_temp_free_i64(tmp); | |
7723 | } | |
7724 | ||
7725 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
7726 | { | |
7727 | TCGv_i64 acc = tcg_temp_new_i64(); | |
7728 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
7729 | ||
7730 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7731 | ||
7732 | acc = tcg_temp_new_i64(); | |
7733 | tmp = tcg_temp_new_i64(); | |
7734 | ||
7735 | /* tmp := rD */ | |
7736 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7737 | ||
7738 | /* Load acc */ | |
1328c2bf | 7739 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7740 | |
7741 | /* acc := tmp + acc */ | |
7742 | tcg_gen_add_i64(acc, acc, tmp); | |
7743 | ||
7744 | /* Store acc */ | |
1328c2bf | 7745 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7746 | |
7747 | /* rD := acc */ | |
7748 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7749 | ||
7750 | tcg_temp_free_i64(acc); | |
7751 | tcg_temp_free_i64(tmp); | |
7752 | } | |
7753 | ||
70560da7 FC |
7754 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
7755 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7756 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7757 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7758 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7759 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7760 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7761 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // | |
7762 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); | |
7763 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7764 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7765 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7766 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7767 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7768 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7769 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
7770 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7771 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7772 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7773 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); | |
7774 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7775 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7776 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // | |
7777 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); | |
7778 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7779 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7780 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7781 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7782 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// | |
0487d6a8 | 7783 | |
6a6ae23f | 7784 | /* SPE load and stores */ |
636aa200 | 7785 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
7786 | { |
7787 | target_ulong uimm = rB(ctx->opcode); | |
7788 | ||
76db3ba4 | 7789 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 7790 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 7791 | } else { |
6a6ae23f | 7792 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
c791fe84 | 7793 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
7794 | tcg_gen_ext32u_tl(EA, EA); |
7795 | } | |
76db3ba4 | 7796 | } |
0487d6a8 | 7797 | } |
6a6ae23f | 7798 | |
636aa200 | 7799 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7800 | { |
7801 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7802 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
6a6ae23f AJ |
7803 | #else |
7804 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
76db3ba4 | 7805 | gen_qemu_ld64(ctx, t0, addr); |
6a6ae23f AJ |
7806 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7807 | tcg_gen_shri_i64(t0, t0, 32); | |
7808 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); | |
7809 | tcg_temp_free_i64(t0); | |
7810 | #endif | |
0487d6a8 | 7811 | } |
6a6ae23f | 7812 | |
636aa200 | 7813 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7814 | { |
0487d6a8 | 7815 | #if defined(TARGET_PPC64) |
6a6ae23f | 7816 | TCGv t0 = tcg_temp_new(); |
76db3ba4 | 7817 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f | 7818 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
76db3ba4 AJ |
7819 | gen_addr_add(ctx, addr, addr, 4); |
7820 | gen_qemu_ld32u(ctx, t0, addr); | |
6a6ae23f AJ |
7821 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7822 | tcg_temp_free(t0); | |
7823 | #else | |
76db3ba4 AJ |
7824 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7825 | gen_addr_add(ctx, addr, addr, 4); | |
7826 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f | 7827 | #endif |
0487d6a8 | 7828 | } |
6a6ae23f | 7829 | |
636aa200 | 7830 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7831 | { |
7832 | TCGv t0 = tcg_temp_new(); | |
7833 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7834 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7835 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7836 | gen_addr_add(ctx, addr, addr, 2); |
7837 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7838 | tcg_gen_shli_tl(t0, t0, 32); |
7839 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7840 | gen_addr_add(ctx, addr, addr, 2); |
7841 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7842 | tcg_gen_shli_tl(t0, t0, 16); |
7843 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7844 | gen_addr_add(ctx, addr, addr, 2); |
7845 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7846 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7847 | #else |
76db3ba4 | 7848 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7849 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7850 | gen_addr_add(ctx, addr, addr, 2); |
7851 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7852 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7853 | gen_addr_add(ctx, addr, addr, 2); |
7854 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7855 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7856 | gen_addr_add(ctx, addr, addr, 2); |
7857 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7858 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7859 | #endif |
6a6ae23f | 7860 | tcg_temp_free(t0); |
0487d6a8 JM |
7861 | } |
7862 | ||
636aa200 | 7863 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7864 | { |
7865 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7866 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7867 | #if defined(TARGET_PPC64) |
7868 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
7869 | tcg_gen_shli_tl(t0, t0, 16); | |
7870 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7871 | #else | |
7872 | tcg_gen_shli_tl(t0, t0, 16); | |
7873 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7874 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7875 | #endif | |
7876 | tcg_temp_free(t0); | |
0487d6a8 JM |
7877 | } |
7878 | ||
636aa200 | 7879 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7880 | { |
7881 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7882 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7883 | #if defined(TARGET_PPC64) |
7884 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7885 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7886 | #else | |
7887 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7888 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7889 | #endif | |
7890 | tcg_temp_free(t0); | |
0487d6a8 JM |
7891 | } |
7892 | ||
636aa200 | 7893 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7894 | { |
7895 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7896 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
7897 | #if defined(TARGET_PPC64) |
7898 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7899 | tcg_gen_ext32u_tl(t0, t0); | |
7900 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7901 | #else | |
7902 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7903 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7904 | #endif | |
7905 | tcg_temp_free(t0); | |
7906 | } | |
7907 | ||
636aa200 | 7908 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7909 | { |
7910 | TCGv t0 = tcg_temp_new(); | |
7911 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7912 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7913 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7914 | gen_addr_add(ctx, addr, addr, 2); |
7915 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7916 | tcg_gen_shli_tl(t0, t0, 16); |
7917 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7918 | #else | |
76db3ba4 | 7919 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7920 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7921 | gen_addr_add(ctx, addr, addr, 2); |
7922 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7923 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7924 | #endif | |
7925 | tcg_temp_free(t0); | |
7926 | } | |
7927 | ||
636aa200 | 7928 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7929 | { |
7930 | #if defined(TARGET_PPC64) | |
7931 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 AJ |
7932 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7933 | gen_addr_add(ctx, addr, addr, 2); | |
7934 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7935 | tcg_gen_shli_tl(t0, t0, 32); |
7936 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7937 | tcg_temp_free(t0); | |
7938 | #else | |
76db3ba4 AJ |
7939 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7940 | gen_addr_add(ctx, addr, addr, 2); | |
7941 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7942 | #endif |
7943 | } | |
7944 | ||
636aa200 | 7945 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7946 | { |
7947 | #if defined(TARGET_PPC64) | |
7948 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7949 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f | 7950 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7951 | gen_addr_add(ctx, addr, addr, 2); |
7952 | gen_qemu_ld16s(ctx, t0, addr); | |
6a6ae23f AJ |
7953 | tcg_gen_shli_tl(t0, t0, 32); |
7954 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7955 | tcg_temp_free(t0); | |
7956 | #else | |
76db3ba4 AJ |
7957 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7958 | gen_addr_add(ctx, addr, addr, 2); | |
7959 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7960 | #endif |
7961 | } | |
7962 | ||
636aa200 | 7963 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7964 | { |
7965 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7966 | gen_qemu_ld32u(ctx, t0, addr); |
0487d6a8 | 7967 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7968 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
7969 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7970 | #else | |
7971 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7972 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7973 | #endif | |
7974 | tcg_temp_free(t0); | |
7975 | } | |
7976 | ||
636aa200 | 7977 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7978 | { |
7979 | TCGv t0 = tcg_temp_new(); | |
7980 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7981 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7982 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
7983 | tcg_gen_shli_tl(t0, t0, 32); | |
7984 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7985 | gen_addr_add(ctx, addr, addr, 2); |
7986 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7987 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7988 | tcg_gen_shli_tl(t0, t0, 16); | |
7989 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7990 | #else | |
76db3ba4 | 7991 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7992 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
7993 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7994 | gen_addr_add(ctx, addr, addr, 2); |
7995 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7996 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7997 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
0487d6a8 | 7998 | #endif |
6a6ae23f AJ |
7999 | tcg_temp_free(t0); |
8000 | } | |
8001 | ||
636aa200 | 8002 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8003 | { |
8004 | #if defined(TARGET_PPC64) | |
76db3ba4 | 8005 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
0487d6a8 | 8006 | #else |
6a6ae23f AJ |
8007 | TCGv_i64 t0 = tcg_temp_new_i64(); |
8008 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); | |
76db3ba4 | 8009 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f AJ |
8010 | tcg_temp_free_i64(t0); |
8011 | #endif | |
8012 | } | |
8013 | ||
636aa200 | 8014 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 8015 | { |
0487d6a8 | 8016 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
8017 | TCGv t0 = tcg_temp_new(); |
8018 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 8019 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
8020 | tcg_temp_free(t0); |
8021 | #else | |
76db3ba4 | 8022 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 8023 | #endif |
76db3ba4 AJ |
8024 | gen_addr_add(ctx, addr, addr, 4); |
8025 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
8026 | } |
8027 | ||
636aa200 | 8028 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8029 | { |
8030 | TCGv t0 = tcg_temp_new(); | |
8031 | #if defined(TARGET_PPC64) | |
8032 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
8033 | #else | |
8034 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
8035 | #endif | |
76db3ba4 AJ |
8036 | gen_qemu_st16(ctx, t0, addr); |
8037 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f AJ |
8038 | #if defined(TARGET_PPC64) |
8039 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 8040 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 8041 | #else |
76db3ba4 | 8042 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 8043 | #endif |
76db3ba4 | 8044 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 8045 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 8046 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 8047 | tcg_temp_free(t0); |
76db3ba4 AJ |
8048 | gen_addr_add(ctx, addr, addr, 2); |
8049 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
8050 | } |
8051 | ||
636aa200 | 8052 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8053 | { |
8054 | TCGv t0 = tcg_temp_new(); | |
8055 | #if defined(TARGET_PPC64) | |
8056 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
8057 | #else | |
8058 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
8059 | #endif | |
76db3ba4 AJ |
8060 | gen_qemu_st16(ctx, t0, addr); |
8061 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 8062 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 8063 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
8064 | tcg_temp_free(t0); |
8065 | } | |
8066 | ||
636aa200 | 8067 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8068 | { |
8069 | #if defined(TARGET_PPC64) | |
8070 | TCGv t0 = tcg_temp_new(); | |
8071 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 8072 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
8073 | tcg_temp_free(t0); |
8074 | #else | |
76db3ba4 | 8075 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 8076 | #endif |
76db3ba4 AJ |
8077 | gen_addr_add(ctx, addr, addr, 2); |
8078 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
8079 | } |
8080 | ||
636aa200 | 8081 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
8082 | { |
8083 | #if defined(TARGET_PPC64) | |
8084 | TCGv t0 = tcg_temp_new(); | |
8085 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 8086 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
8087 | tcg_temp_free(t0); |
8088 | #else | |
76db3ba4 | 8089 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
8090 | #endif |
8091 | } | |
8092 | ||
636aa200 | 8093 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 8094 | { |
76db3ba4 | 8095 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
8096 | } |
8097 | ||
8098 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 8099 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
8100 | { \ |
8101 | TCGv t0; \ | |
8102 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8103 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
6a6ae23f AJ |
8104 | return; \ |
8105 | } \ | |
76db3ba4 | 8106 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
8107 | t0 = tcg_temp_new(); \ |
8108 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 8109 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 8110 | } else { \ |
76db3ba4 | 8111 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
8112 | } \ |
8113 | gen_op_##name(ctx, t0); \ | |
8114 | tcg_temp_free(t0); \ | |
8115 | } | |
8116 | ||
8117 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
8118 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
8119 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
8120 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
8121 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
8122 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
8123 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
8124 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
8125 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
8126 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
8127 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
8128 | ||
8129 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
8130 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
8131 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
8132 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
8133 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
8134 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
8135 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
8136 | |
8137 | /* Multiply and add - TODO */ | |
8138 | #if 0 | |
70560da7 FC |
8139 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
8140 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8141 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8142 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8143 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8144 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8145 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8146 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8147 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8148 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8149 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8150 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8151 | ||
8152 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8153 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8154 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8155 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8156 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8157 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8158 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8159 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8160 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8161 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8162 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8163 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8164 | ||
8165 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8166 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8167 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8168 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8169 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); | |
8170 | ||
8171 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8172 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8173 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8174 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8175 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8176 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8177 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8178 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8179 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8180 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8181 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8182 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8183 | ||
8184 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8185 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8186 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8187 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8188 | ||
8189 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8190 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8191 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8192 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8193 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8194 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8195 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8196 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8197 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8198 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8199 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8200 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8201 | ||
8202 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8203 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8204 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8205 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8206 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
8207 | #endif |
8208 | ||
8209 | /*** SPE floating-point extension ***/ | |
1c97856d AJ |
8210 | #if defined(TARGET_PPC64) |
8211 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8212 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8213 | { \ |
1c97856d AJ |
8214 | TCGv_i32 t0; \ |
8215 | TCGv t1; \ | |
8216 | t0 = tcg_temp_new_i32(); \ | |
8217 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8218 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8219 | t1 = tcg_temp_new(); \ |
8220 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8221 | tcg_temp_free_i32(t0); \ | |
8222 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8223 | 0xFFFFFFFF00000000ULL); \ | |
8224 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8225 | tcg_temp_free(t1); \ | |
0487d6a8 | 8226 | } |
1c97856d | 8227 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8228 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8229 | { \ |
8230 | TCGv_i32 t0; \ | |
8231 | TCGv t1; \ | |
8232 | t0 = tcg_temp_new_i32(); \ | |
8e703949 | 8233 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8234 | t1 = tcg_temp_new(); \ |
8235 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8236 | tcg_temp_free_i32(t0); \ | |
8237 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8238 | 0xFFFFFFFF00000000ULL); \ | |
8239 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8240 | tcg_temp_free(t1); \ | |
8241 | } | |
8242 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8243 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8244 | { \ |
8245 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
8246 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8247 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8248 | tcg_temp_free_i32(t0); \ |
8249 | } | |
8250 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8251 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8252 | { \ |
8e703949 BS |
8253 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8254 | cpu_gpr[rB(ctx->opcode)]); \ | |
1c97856d AJ |
8255 | } |
8256 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8257 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8258 | { \ |
1c97856d AJ |
8259 | TCGv_i32 t0, t1; \ |
8260 | TCGv_i64 t2; \ | |
57951c27 | 8261 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8262 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8263 | return; \ |
8264 | } \ | |
1c97856d AJ |
8265 | t0 = tcg_temp_new_i32(); \ |
8266 | t1 = tcg_temp_new_i32(); \ | |
8267 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8268 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8269 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8270 | tcg_temp_free_i32(t1); \ |
8271 | t2 = tcg_temp_new(); \ | |
8272 | tcg_gen_extu_i32_tl(t2, t0); \ | |
8273 | tcg_temp_free_i32(t0); \ | |
8274 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8275 | 0xFFFFFFFF00000000ULL); \ | |
8276 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ | |
8277 | tcg_temp_free(t2); \ | |
57951c27 | 8278 | } |
1c97856d | 8279 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
636aa200 | 8280 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8281 | { \ |
8282 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8283 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8284 | return; \ |
8285 | } \ | |
8e703949 BS |
8286 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8287 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8288 | } |
1c97856d | 8289 | #define GEN_SPEFPUOP_COMP_32(name) \ |
636aa200 | 8290 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8291 | { \ |
1c97856d | 8292 | TCGv_i32 t0, t1; \ |
57951c27 | 8293 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8294 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8295 | return; \ |
8296 | } \ | |
1c97856d AJ |
8297 | t0 = tcg_temp_new_i32(); \ |
8298 | t1 = tcg_temp_new_i32(); \ | |
8299 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8300 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8301 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8302 | tcg_temp_free_i32(t0); \ |
8303 | tcg_temp_free_i32(t1); \ | |
8304 | } | |
8305 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8306 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8307 | { \ |
8308 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8309 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8310 | return; \ |
8311 | } \ | |
8e703949 | 8312 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8313 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8314 | } | |
8315 | #else | |
8316 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8317 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8318 | { \ |
8e703949 BS |
8319 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8320 | cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8321 | } |
1c97856d | 8322 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8323 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8324 | { \ |
8325 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8326 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8327 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8328 | tcg_temp_free_i64(t0); \ |
8329 | } | |
8330 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8331 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8332 | { \ |
8333 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8e703949 | 8334 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8335 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8336 | tcg_temp_free_i64(t0); \ | |
8337 | } | |
8338 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8339 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8340 | { \ |
8341 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8342 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8343 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8344 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8345 | tcg_temp_free_i64(t0); \ | |
8346 | } | |
8347 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8348 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8349 | { \ |
8350 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8351 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8352 | return; \ |
8353 | } \ | |
8e703949 | 8354 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8355 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8356 | } | |
8357 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 8358 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8359 | { \ |
8360 | TCGv_i64 t0, t1; \ | |
8361 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8362 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8363 | return; \ |
8364 | } \ | |
8365 | t0 = tcg_temp_new_i64(); \ | |
8366 | t1 = tcg_temp_new_i64(); \ | |
8367 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8368 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8369 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8370 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8371 | tcg_temp_free_i64(t0); \ | |
8372 | tcg_temp_free_i64(t1); \ | |
8373 | } | |
8374 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 8375 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8376 | { \ |
8377 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8378 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8379 | return; \ |
8380 | } \ | |
8e703949 | 8381 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8382 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8383 | } | |
8384 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8385 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8386 | { \ |
8387 | TCGv_i64 t0, t1; \ | |
8388 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8389 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8390 | return; \ |
8391 | } \ | |
8392 | t0 = tcg_temp_new_i64(); \ | |
8393 | t1 = tcg_temp_new_i64(); \ | |
8394 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8395 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8396 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8397 | tcg_temp_free_i64(t0); \ |
8398 | tcg_temp_free_i64(t1); \ | |
8399 | } | |
8400 | #endif | |
57951c27 | 8401 | |
0487d6a8 JM |
8402 | /* Single precision floating-point vectors operations */ |
8403 | /* Arithmetic */ | |
1c97856d AJ |
8404 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
8405 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
8406 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
8407 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 8408 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
8409 | { |
8410 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8411 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8412 | return; |
8413 | } | |
8414 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8415 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); |
1c97856d | 8416 | #else |
6d5c34fa MP |
8417 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); |
8418 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8419 | #endif |
8420 | } | |
636aa200 | 8421 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
8422 | { |
8423 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8424 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8425 | return; |
8426 | } | |
8427 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8428 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8429 | #else |
6d5c34fa MP |
8430 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8431 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8432 | #endif |
8433 | } | |
636aa200 | 8434 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
8435 | { |
8436 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8437 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8438 | return; |
8439 | } | |
8440 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8441 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8442 | #else |
6d5c34fa MP |
8443 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8444 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8445 | #endif |
8446 | } | |
8447 | ||
0487d6a8 | 8448 | /* Conversion */ |
1c97856d AJ |
8449 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8450 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
8451 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
8452 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
8453 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
8454 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
8455 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
8456 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
8457 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
8458 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
8459 | ||
0487d6a8 | 8460 | /* Comparison */ |
1c97856d AJ |
8461 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8462 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
8463 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
8464 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
8465 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
8466 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
8467 | |
8468 | /* Opcodes definitions */ | |
70560da7 FC |
8469 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8470 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8471 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8472 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8473 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8474 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8475 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8476 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8477 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8478 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8479 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8480 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8481 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8482 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8483 | |
8484 | /* Single precision floating-point operations */ | |
8485 | /* Arithmetic */ | |
1c97856d AJ |
8486 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8487 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
8488 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
8489 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 8490 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
8491 | { |
8492 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8493 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8494 | return; |
8495 | } | |
6d5c34fa | 8496 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 8497 | } |
636aa200 | 8498 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
8499 | { |
8500 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8501 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8502 | return; |
8503 | } | |
6d5c34fa | 8504 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 8505 | } |
636aa200 | 8506 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
8507 | { |
8508 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8509 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8510 | return; |
8511 | } | |
6d5c34fa | 8512 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
8513 | } |
8514 | ||
0487d6a8 | 8515 | /* Conversion */ |
1c97856d AJ |
8516 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8517 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
8518 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
8519 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
8520 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
8521 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
8522 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
8523 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
8524 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
8525 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
8526 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
8527 | ||
0487d6a8 | 8528 | /* Comparison */ |
1c97856d AJ |
8529 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
8530 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
8531 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
8532 | GEN_SPEFPUOP_COMP_32(efststgt); | |
8533 | GEN_SPEFPUOP_COMP_32(efststlt); | |
8534 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
8535 | |
8536 | /* Opcodes definitions */ | |
70560da7 FC |
8537 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8538 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8539 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8540 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8541 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8542 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // | |
8543 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8544 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8545 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8546 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8547 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8548 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8549 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8550 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8551 | |
8552 | /* Double precision floating-point operations */ | |
8553 | /* Arithmetic */ | |
1c97856d AJ |
8554 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
8555 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
8556 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
8557 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 8558 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
8559 | { |
8560 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8561 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8562 | return; |
8563 | } | |
8564 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8565 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); |
1c97856d | 8566 | #else |
6d5c34fa MP |
8567 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8568 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8569 | #endif |
8570 | } | |
636aa200 | 8571 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
8572 | { |
8573 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8574 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8575 | return; |
8576 | } | |
8577 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8578 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8579 | #else |
6d5c34fa MP |
8580 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8581 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8582 | #endif |
8583 | } | |
636aa200 | 8584 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
8585 | { |
8586 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8587 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8588 | return; |
8589 | } | |
8590 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8591 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8592 | #else |
6d5c34fa MP |
8593 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8594 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8595 | #endif |
8596 | } | |
8597 | ||
0487d6a8 | 8598 | /* Conversion */ |
1c97856d AJ |
8599 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
8600 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
8601 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
8602 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
8603 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
8604 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
8605 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
8606 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
8607 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
8608 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
8609 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
8610 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
8611 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
8612 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
8613 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 8614 | |
0487d6a8 | 8615 | /* Comparison */ |
1c97856d AJ |
8616 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
8617 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
8618 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
8619 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
8620 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
8621 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
8622 | |
8623 | /* Opcodes definitions */ | |
70560da7 FC |
8624 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
8625 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8626 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // | |
8627 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8628 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // | |
8629 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8630 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8631 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // | |
8632 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8633 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8634 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8635 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8636 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8637 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8638 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8639 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
0487d6a8 | 8640 | |
c227f099 | 8641 | static opcode_t opcodes[] = { |
5c55ff99 BS |
8642 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
8643 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
8644 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8645 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
8646 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
fcfda20f | 8647 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
8648 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
8649 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8650 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8651 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8652 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8653 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
8654 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
8655 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
8656 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
8657 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8658 | #if defined(TARGET_PPC64) | |
8659 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
8660 | #endif | |
8661 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
8662 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
8663 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8664 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8665 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8666 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
8667 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
8668 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
8669 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8670 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8671 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8672 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8673 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), | |
eaabeef2 | 8674 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 8675 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 8676 | #if defined(TARGET_PPC64) |
eaabeef2 | 8677 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 8678 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
725bcec2 | 8679 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
8680 | #endif |
8681 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8682 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8683 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8684 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
8685 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
8686 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
8687 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
8688 | #if defined(TARGET_PPC64) | |
8689 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
8690 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
8691 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
8692 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
8693 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
8694 | #endif | |
8695 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
8696 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8697 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8698 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
8699 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
bf45a2e6 | 8700 | GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), |
5c55ff99 | 8701 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
bf45a2e6 AJ |
8702 | GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), |
8703 | GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), | |
f0332888 | 8704 | GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
8705 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
8706 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
8707 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
8708 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
7d08d856 AJ |
8709 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT), |
8710 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT), | |
5c55ff99 BS |
8711 | #if defined(TARGET_PPC64) |
8712 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8713 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
8714 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8715 | #endif | |
8716 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8717 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8718 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
8719 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
8720 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
8721 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
8722 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
8723 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
f844c817 | 8724 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
5c55ff99 BS |
8725 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
8726 | #if defined(TARGET_PPC64) | |
f844c817 | 8727 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
5c55ff99 BS |
8728 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
8729 | #endif | |
8730 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
8731 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
8732 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8733 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8734 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
8735 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
8736 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), | |
8737 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
8738 | #if defined(TARGET_PPC64) | |
8739 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
8740 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
8741 | #endif | |
8742 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
8743 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
8744 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8745 | #if defined(TARGET_PPC64) | |
8746 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
8747 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8748 | #endif | |
8749 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
8750 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
8751 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
8752 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
8753 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
8754 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
8755 | #if defined(TARGET_PPC64) | |
8756 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
8757 | #endif | |
8758 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
8759 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), | |
8760 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
8761 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
8762 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
8763 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), | |
8764 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), | |
8e33944f | 8765 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
8766 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
8767 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
8768 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
8769 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
8770 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
8771 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
8772 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
8773 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
8774 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
8775 | #if defined(TARGET_PPC64) | |
8776 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
8777 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
8778 | PPC_SEGMENT_64B), | |
8779 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
8780 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
8781 | PPC_SEGMENT_64B), | |
efdef95f DG |
8782 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
8783 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
8784 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
8785 | #endif |
8786 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
8787 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
8788 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
8789 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
8790 | #if defined(TARGET_PPC64) | |
8791 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
8792 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
8793 | #endif | |
8794 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
8795 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
8796 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
8797 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
8798 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
8799 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
8800 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
8801 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
8802 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
8803 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
8804 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
8805 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8806 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
8807 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
8808 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
8809 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
8810 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
8811 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
8812 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
8813 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8814 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
8815 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
8816 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
8817 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
8818 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
8819 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
8820 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
8821 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
8822 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
8823 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
8824 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
8825 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
8826 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
8827 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
8828 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
8829 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
8830 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
8831 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
8832 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
8833 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
8834 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
8835 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
8836 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
8837 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
8838 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
8839 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
8840 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
8841 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
8842 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
8843 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8844 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8845 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
8846 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
8847 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8848 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8849 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
8850 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
8851 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
8852 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
8853 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
8854 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
8855 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
8856 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
8857 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
8858 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
8859 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
8860 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
8861 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
8862 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
8863 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
8864 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 8865 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
8866 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
8867 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
8868 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
8869 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
8870 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
8871 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
8872 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
8873 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
8874 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
8875 | PPC_NONE, PPC2_BOOKE206), | |
8876 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
8877 | PPC_NONE, PPC2_BOOKE206), | |
8878 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
8879 | PPC_NONE, PPC2_BOOKE206), | |
8880 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
8881 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
8882 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
8883 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
8884 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
8885 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
8886 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
8887 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 8888 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 8889 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 8890 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
8891 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
8892 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 8893 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
8894 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
8895 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
8896 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
8897 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
8898 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
8899 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
8900 | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), | |
8901 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), | |
8902 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
8903 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
8904 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
8905 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
8906 | ||
8907 | #undef GEN_INT_ARITH_ADD | |
8908 | #undef GEN_INT_ARITH_ADD_CONST | |
8909 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8910 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
8911 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
8912 | add_ca, compute_ca, compute_ov) \ | |
8913 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
8914 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
8915 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
8916 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
8917 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
8918 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
8919 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
8920 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
8921 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
8922 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
8923 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
8924 | ||
8925 | #undef GEN_INT_ARITH_DIVW | |
8926 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
8927 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
8928 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
8929 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
8930 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
8931 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
8932 | ||
8933 | #if defined(TARGET_PPC64) | |
8934 | #undef GEN_INT_ARITH_DIVD | |
8935 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
8936 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8937 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
8938 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
8939 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
8940 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
8941 | ||
8942 | #undef GEN_INT_ARITH_MUL_HELPER | |
8943 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
8944 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8945 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
8946 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
8947 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
8948 | #endif | |
8949 | ||
8950 | #undef GEN_INT_ARITH_SUBF | |
8951 | #undef GEN_INT_ARITH_SUBF_CONST | |
8952 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8953 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
8954 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
8955 | add_ca, compute_ca, compute_ov) \ | |
8956 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
8957 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
8958 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
8959 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
8960 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
8961 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
8962 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
8963 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
8964 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
8965 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
8966 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
8967 | ||
8968 | #undef GEN_LOGICAL1 | |
8969 | #undef GEN_LOGICAL2 | |
8970 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
8971 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
8972 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
8973 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
8974 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
8975 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
8976 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
8977 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
8978 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
8979 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
8980 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
8981 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
8982 | #if defined(TARGET_PPC64) | |
8983 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
8984 | #endif | |
8985 | ||
8986 | #if defined(TARGET_PPC64) | |
8987 | #undef GEN_PPC64_R2 | |
8988 | #undef GEN_PPC64_R4 | |
8989 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
8990 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8991 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8992 | PPC_64B) | |
8993 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
8994 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8995 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
8996 | PPC_64B), \ | |
8997 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8998 | PPC_64B), \ | |
8999 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
9000 | PPC_64B) | |
9001 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
9002 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
9003 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
9004 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
9005 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
9006 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
9007 | #endif | |
9008 | ||
9009 | #undef _GEN_FLOAT_ACB | |
9010 | #undef GEN_FLOAT_ACB | |
9011 | #undef _GEN_FLOAT_AB | |
9012 | #undef GEN_FLOAT_AB | |
9013 | #undef _GEN_FLOAT_AC | |
9014 | #undef GEN_FLOAT_AC | |
9015 | #undef GEN_FLOAT_B | |
9016 | #undef GEN_FLOAT_BS | |
9017 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
9018 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
9019 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
9020 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
9021 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
9022 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
9023 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
9024 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
9025 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
9026 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
9027 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
9028 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
9029 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
9030 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
9031 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
9032 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
9033 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
9034 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
9035 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
9036 | ||
9037 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
9038 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
9039 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
9040 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
9041 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
9042 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
9043 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
9044 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
9045 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
9046 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
9047 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
9048 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
9049 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), | |
9050 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), | |
9051 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), | |
9052 | #if defined(TARGET_PPC64) | |
9053 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), | |
9054 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), | |
9055 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), | |
9056 | #endif | |
9057 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), | |
9058 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
9059 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
9060 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
5c55ff99 BS |
9061 | |
9062 | #undef GEN_LD | |
9063 | #undef GEN_LDU | |
9064 | #undef GEN_LDUX | |
cd6e9320 | 9065 | #undef GEN_LDX_E |
5c55ff99 BS |
9066 | #undef GEN_LDS |
9067 | #define GEN_LD(name, ldop, opc, type) \ | |
9068 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9069 | #define GEN_LDU(name, ldop, opc, type) \ | |
9070 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9071 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
9072 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
9073 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
9074 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
9075 | #define GEN_LDS(name, ldop, op, type) \ |
9076 | GEN_LD(name, ldop, op | 0x20, type) \ | |
9077 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
9078 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
9079 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
9080 | ||
9081 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
9082 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
9083 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
9084 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
9085 | #if defined(TARGET_PPC64) | |
9086 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
9087 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
9088 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
9089 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
cd6e9320 | 9090 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
9091 | #endif |
9092 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
9093 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
9094 | ||
9095 | #undef GEN_ST | |
9096 | #undef GEN_STU | |
9097 | #undef GEN_STUX | |
cd6e9320 | 9098 | #undef GEN_STX_E |
5c55ff99 BS |
9099 | #undef GEN_STS |
9100 | #define GEN_ST(name, stop, opc, type) \ | |
9101 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9102 | #define GEN_STU(name, stop, opc, type) \ | |
9103 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9104 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
9105 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
9106 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
9107 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
9108 | #define GEN_STS(name, stop, op, type) \ |
9109 | GEN_ST(name, stop, op | 0x20, type) \ | |
9110 | GEN_STU(name, stop, op | 0x21, type) \ | |
9111 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
9112 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
9113 | ||
9114 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
9115 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
9116 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
9117 | #if defined(TARGET_PPC64) | |
9118 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
9119 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
cd6e9320 | 9120 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
9121 | #endif |
9122 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
9123 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
9124 | ||
9125 | #undef GEN_LDF | |
9126 | #undef GEN_LDUF | |
9127 | #undef GEN_LDUXF | |
9128 | #undef GEN_LDXF | |
9129 | #undef GEN_LDFS | |
9130 | #define GEN_LDF(name, ldop, opc, type) \ | |
9131 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9132 | #define GEN_LDUF(name, ldop, opc, type) \ | |
9133 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9134 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
9135 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
9136 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
9137 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
9138 | #define GEN_LDFS(name, ldop, op, type) \ | |
9139 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
9140 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
9141 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
9142 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
9143 | ||
9144 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
9145 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
199f830d | 9146 | GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), |
05050ee8 AJ |
9147 | GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
9148 | GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
9149 | |
9150 | #undef GEN_STF | |
9151 | #undef GEN_STUF | |
9152 | #undef GEN_STUXF | |
9153 | #undef GEN_STXF | |
9154 | #undef GEN_STFS | |
9155 | #define GEN_STF(name, stop, opc, type) \ | |
9156 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9157 | #define GEN_STUF(name, stop, opc, type) \ | |
9158 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9159 | #define GEN_STUXF(name, stop, opc, type) \ | |
9160 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
9161 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
9162 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
9163 | #define GEN_STFS(name, stop, op, type) \ | |
9164 | GEN_STF(name, stop, op | 0x20, type) \ | |
9165 | GEN_STUF(name, stop, op | 0x21, type) \ | |
9166 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
9167 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
9168 | ||
9169 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
9170 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
9171 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
44bc0c4d AJ |
9172 | GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
9173 | GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
9174 | |
9175 | #undef GEN_CRLOGIC | |
9176 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
9177 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
9178 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
9179 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
9180 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
9181 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
9182 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
9183 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
9184 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
9185 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
9186 | ||
9187 | #undef GEN_MAC_HANDLER | |
9188 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
9189 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
9190 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
9191 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
9192 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
9193 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
9194 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
9195 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
9196 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
9197 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
9198 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
9199 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
9200 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
9201 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
9202 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
9203 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
9204 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
9205 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
9206 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
9207 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
9208 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
9209 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
9210 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
9211 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
9212 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
9213 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
9214 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
9215 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
9216 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
9217 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
9218 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
9219 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
9220 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
9221 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
9222 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
9223 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
9224 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
9225 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
9226 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
9227 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
9228 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
9229 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
9230 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
9231 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
9232 | ||
9233 | #undef GEN_VR_LDX | |
9234 | #undef GEN_VR_STX | |
9235 | #undef GEN_VR_LVE | |
9236 | #undef GEN_VR_STVE | |
9237 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
9238 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9239 | #define GEN_VR_STX(name, opc2, opc3) \ | |
9240 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9241 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
9242 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9243 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
9244 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9245 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
9246 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
9247 | GEN_VR_LVE(bx, 0x07, 0x00), | |
9248 | GEN_VR_LVE(hx, 0x07, 0x01), | |
9249 | GEN_VR_LVE(wx, 0x07, 0x02), | |
9250 | GEN_VR_STX(svx, 0x07, 0x07), | |
9251 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
9252 | GEN_VR_STVE(bx, 0x07, 0x04), | |
9253 | GEN_VR_STVE(hx, 0x07, 0x05), | |
9254 | GEN_VR_STVE(wx, 0x07, 0x06), | |
9255 | ||
9256 | #undef GEN_VX_LOGICAL | |
9257 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
9258 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9259 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), | |
9260 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
9261 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
9262 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
9263 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
9264 | ||
9265 | #undef GEN_VXFORM | |
9266 | #define GEN_VXFORM(name, opc2, opc3) \ | |
9267 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9268 | GEN_VXFORM(vaddubm, 0, 0), | |
9269 | GEN_VXFORM(vadduhm, 0, 1), | |
9270 | GEN_VXFORM(vadduwm, 0, 2), | |
9271 | GEN_VXFORM(vsububm, 0, 16), | |
9272 | GEN_VXFORM(vsubuhm, 0, 17), | |
9273 | GEN_VXFORM(vsubuwm, 0, 18), | |
9274 | GEN_VXFORM(vmaxub, 1, 0), | |
9275 | GEN_VXFORM(vmaxuh, 1, 1), | |
9276 | GEN_VXFORM(vmaxuw, 1, 2), | |
9277 | GEN_VXFORM(vmaxsb, 1, 4), | |
9278 | GEN_VXFORM(vmaxsh, 1, 5), | |
9279 | GEN_VXFORM(vmaxsw, 1, 6), | |
9280 | GEN_VXFORM(vminub, 1, 8), | |
9281 | GEN_VXFORM(vminuh, 1, 9), | |
9282 | GEN_VXFORM(vminuw, 1, 10), | |
9283 | GEN_VXFORM(vminsb, 1, 12), | |
9284 | GEN_VXFORM(vminsh, 1, 13), | |
9285 | GEN_VXFORM(vminsw, 1, 14), | |
9286 | GEN_VXFORM(vavgub, 1, 16), | |
9287 | GEN_VXFORM(vavguh, 1, 17), | |
9288 | GEN_VXFORM(vavguw, 1, 18), | |
9289 | GEN_VXFORM(vavgsb, 1, 20), | |
9290 | GEN_VXFORM(vavgsh, 1, 21), | |
9291 | GEN_VXFORM(vavgsw, 1, 22), | |
9292 | GEN_VXFORM(vmrghb, 6, 0), | |
9293 | GEN_VXFORM(vmrghh, 6, 1), | |
9294 | GEN_VXFORM(vmrghw, 6, 2), | |
9295 | GEN_VXFORM(vmrglb, 6, 4), | |
9296 | GEN_VXFORM(vmrglh, 6, 5), | |
9297 | GEN_VXFORM(vmrglw, 6, 6), | |
9298 | GEN_VXFORM(vmuloub, 4, 0), | |
9299 | GEN_VXFORM(vmulouh, 4, 1), | |
9300 | GEN_VXFORM(vmulosb, 4, 4), | |
9301 | GEN_VXFORM(vmulosh, 4, 5), | |
9302 | GEN_VXFORM(vmuleub, 4, 8), | |
9303 | GEN_VXFORM(vmuleuh, 4, 9), | |
9304 | GEN_VXFORM(vmulesb, 4, 12), | |
9305 | GEN_VXFORM(vmulesh, 4, 13), | |
9306 | GEN_VXFORM(vslb, 2, 4), | |
9307 | GEN_VXFORM(vslh, 2, 5), | |
9308 | GEN_VXFORM(vslw, 2, 6), | |
9309 | GEN_VXFORM(vsrb, 2, 8), | |
9310 | GEN_VXFORM(vsrh, 2, 9), | |
9311 | GEN_VXFORM(vsrw, 2, 10), | |
9312 | GEN_VXFORM(vsrab, 2, 12), | |
9313 | GEN_VXFORM(vsrah, 2, 13), | |
9314 | GEN_VXFORM(vsraw, 2, 14), | |
9315 | GEN_VXFORM(vslo, 6, 16), | |
9316 | GEN_VXFORM(vsro, 6, 17), | |
9317 | GEN_VXFORM(vaddcuw, 0, 6), | |
9318 | GEN_VXFORM(vsubcuw, 0, 22), | |
9319 | GEN_VXFORM(vaddubs, 0, 8), | |
9320 | GEN_VXFORM(vadduhs, 0, 9), | |
9321 | GEN_VXFORM(vadduws, 0, 10), | |
9322 | GEN_VXFORM(vaddsbs, 0, 12), | |
9323 | GEN_VXFORM(vaddshs, 0, 13), | |
9324 | GEN_VXFORM(vaddsws, 0, 14), | |
9325 | GEN_VXFORM(vsububs, 0, 24), | |
9326 | GEN_VXFORM(vsubuhs, 0, 25), | |
9327 | GEN_VXFORM(vsubuws, 0, 26), | |
9328 | GEN_VXFORM(vsubsbs, 0, 28), | |
9329 | GEN_VXFORM(vsubshs, 0, 29), | |
9330 | GEN_VXFORM(vsubsws, 0, 30), | |
9331 | GEN_VXFORM(vrlb, 2, 0), | |
9332 | GEN_VXFORM(vrlh, 2, 1), | |
9333 | GEN_VXFORM(vrlw, 2, 2), | |
9334 | GEN_VXFORM(vsl, 2, 7), | |
9335 | GEN_VXFORM(vsr, 2, 11), | |
9336 | GEN_VXFORM(vpkuhum, 7, 0), | |
9337 | GEN_VXFORM(vpkuwum, 7, 1), | |
9338 | GEN_VXFORM(vpkuhus, 7, 2), | |
9339 | GEN_VXFORM(vpkuwus, 7, 3), | |
9340 | GEN_VXFORM(vpkshus, 7, 4), | |
9341 | GEN_VXFORM(vpkswus, 7, 5), | |
9342 | GEN_VXFORM(vpkshss, 7, 6), | |
9343 | GEN_VXFORM(vpkswss, 7, 7), | |
9344 | GEN_VXFORM(vpkpx, 7, 12), | |
9345 | GEN_VXFORM(vsum4ubs, 4, 24), | |
9346 | GEN_VXFORM(vsum4sbs, 4, 28), | |
9347 | GEN_VXFORM(vsum4shs, 4, 25), | |
9348 | GEN_VXFORM(vsum2sws, 4, 26), | |
9349 | GEN_VXFORM(vsumsws, 4, 30), | |
9350 | GEN_VXFORM(vaddfp, 5, 0), | |
9351 | GEN_VXFORM(vsubfp, 5, 1), | |
9352 | GEN_VXFORM(vmaxfp, 5, 16), | |
9353 | GEN_VXFORM(vminfp, 5, 17), | |
9354 | ||
9355 | #undef GEN_VXRFORM1 | |
9356 | #undef GEN_VXRFORM | |
9357 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
9358 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
9359 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
9360 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
9361 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
9362 | GEN_VXRFORM(vcmpequb, 3, 0) | |
9363 | GEN_VXRFORM(vcmpequh, 3, 1) | |
9364 | GEN_VXRFORM(vcmpequw, 3, 2) | |
9365 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
9366 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
9367 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
9368 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
9369 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
9370 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
9371 | GEN_VXRFORM(vcmpeqfp, 3, 3) | |
9372 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
9373 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
9374 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
9375 | ||
9376 | #undef GEN_VXFORM_SIMM | |
9377 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
9378 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9379 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
9380 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
9381 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
9382 | ||
9383 | #undef GEN_VXFORM_NOA | |
9384 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
9385 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
9386 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
9387 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
9388 | GEN_VXFORM_NOA(vupklsb, 7, 10), | |
9389 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
9390 | GEN_VXFORM_NOA(vupkhpx, 7, 13), | |
9391 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
9392 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
9393 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 9394 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 BS |
9395 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
9396 | GEN_VXFORM_NOA(vrfim, 5, 8), | |
9397 | GEN_VXFORM_NOA(vrfin, 5, 9), | |
9398 | GEN_VXFORM_NOA(vrfip, 5, 10), | |
9399 | GEN_VXFORM_NOA(vrfiz, 5, 11), | |
9400 | ||
9401 | #undef GEN_VXFORM_UIMM | |
9402 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
9403 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9404 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
9405 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
9406 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
9407 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
9408 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
9409 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
9410 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
9411 | ||
9412 | #undef GEN_VAFORM_PAIRED | |
9413 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
9414 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
9415 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
9416 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
9417 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
9418 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
9419 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
9420 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
9421 | ||
9422 | #undef GEN_SPE | |
70560da7 FC |
9423 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
9424 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) | |
9425 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9426 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9427 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9428 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9429 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9430 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9431 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9432 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), | |
9433 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), | |
9434 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9435 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9436 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9437 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9438 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9439 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9440 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), | |
9441 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9442 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9443 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9444 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9445 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9446 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9447 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9448 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9449 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9450 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9451 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9452 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9453 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), | |
9454 | ||
9455 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9456 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9457 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9458 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9459 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9460 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9461 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9462 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9463 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9464 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9465 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9466 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9467 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9468 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9469 | ||
9470 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9471 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9472 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9473 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9474 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9475 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), | |
9476 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9477 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9478 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9479 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9480 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9481 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9482 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9483 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9484 | ||
9485 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9486 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9487 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), | |
9488 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9489 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9490 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9491 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9492 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), | |
9493 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9494 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9495 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9496 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9497 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9498 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9499 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9500 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
5c55ff99 BS |
9501 | |
9502 | #undef GEN_SPEOP_LDST | |
9503 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
9504 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
9505 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
9506 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
9507 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
9508 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
9509 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
9510 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
9511 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
9512 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
9513 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
9514 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
9515 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
9516 | ||
9517 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
9518 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
9519 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
9520 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
9521 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
9522 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
9523 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
9524 | }; | |
9525 | ||
0411a972 | 9526 | #include "helper_regs.h" |
a1389542 | 9527 | #include "translate_init.c" |
79aceca5 | 9528 | |
9a64fbe4 | 9529 | /*****************************************************************************/ |
3fc6c082 | 9530 | /* Misc PowerPC helpers */ |
1328c2bf | 9531 | void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf, |
36081602 | 9532 | int flags) |
79aceca5 | 9533 | { |
3fc6c082 FB |
9534 | #define RGPL 4 |
9535 | #define RFPL 4 | |
3fc6c082 | 9536 | |
79aceca5 FB |
9537 | int i; |
9538 | ||
29979a8d AG |
9539 | cpu_synchronize_state(env); |
9540 | ||
90e189ec | 9541 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9a78eead | 9542 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
da91a00f | 9543 | env->nip, env->lr, env->ctr, cpu_read_xer(env)); |
90e189ec BS |
9544 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9545 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
9546 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 9547 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 9548 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 9549 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 9550 | " DECR %08" PRIu32 |
76a66253 JM |
9551 | #endif |
9552 | "\n", | |
077fc206 | 9553 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
9554 | #if !defined(CONFIG_USER_ONLY) |
9555 | , cpu_ppc_load_decr(env) | |
9556 | #endif | |
9557 | ); | |
077fc206 | 9558 | #endif |
76a66253 | 9559 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
9560 | if ((i & (RGPL - 1)) == 0) |
9561 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 9562 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 9563 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 9564 | cpu_fprintf(f, "\n"); |
76a66253 | 9565 | } |
3fc6c082 | 9566 | cpu_fprintf(f, "CR "); |
76a66253 | 9567 | for (i = 0; i < 8; i++) |
7fe48483 FB |
9568 | cpu_fprintf(f, "%01x", env->crf[i]); |
9569 | cpu_fprintf(f, " ["); | |
76a66253 JM |
9570 | for (i = 0; i < 8; i++) { |
9571 | char a = '-'; | |
9572 | if (env->crf[i] & 0x08) | |
9573 | a = 'L'; | |
9574 | else if (env->crf[i] & 0x04) | |
9575 | a = 'G'; | |
9576 | else if (env->crf[i] & 0x02) | |
9577 | a = 'E'; | |
7fe48483 | 9578 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 9579 | } |
90e189ec BS |
9580 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
9581 | env->reserve_addr); | |
3fc6c082 FB |
9582 | for (i = 0; i < 32; i++) { |
9583 | if ((i & (RFPL - 1)) == 0) | |
9584 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 9585 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 9586 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 9587 | cpu_fprintf(f, "\n"); |
79aceca5 | 9588 | } |
30304420 | 9589 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 9590 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
9591 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
9592 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
9593 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
9594 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
9595 | ||
9596 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
9597 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
9598 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
9599 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
9600 | ||
9601 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
9602 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
9603 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
9604 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
9605 | ||
9606 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
9607 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
9608 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
9609 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
9610 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
9611 | ||
9612 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
9613 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
9614 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
9615 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
9616 | ||
9617 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
9618 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
9619 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
9620 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
9621 | ||
9622 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
9623 | " EPR " TARGET_FMT_lx "\n", | |
9624 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
9625 | env->spr[SPR_BOOKE_EPR]); | |
9626 | ||
9627 | /* FSL-specific */ | |
9628 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
9629 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
9630 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
9631 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
9632 | ||
9633 | /* | |
9634 | * IVORs are left out as they are large and do not change often -- | |
9635 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
9636 | */ | |
9637 | } | |
9638 | ||
697ab892 DG |
9639 | #if defined(TARGET_PPC64) |
9640 | if (env->flags & POWERPC_FLAG_CFAR) { | |
9641 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
9642 | } | |
9643 | #endif | |
9644 | ||
90dc8812 SW |
9645 | switch (env->mmu_model) { |
9646 | case POWERPC_MMU_32B: | |
9647 | case POWERPC_MMU_601: | |
9648 | case POWERPC_MMU_SOFT_6xx: | |
9649 | case POWERPC_MMU_SOFT_74xx: | |
9650 | #if defined(TARGET_PPC64) | |
90dc8812 SW |
9651 | case POWERPC_MMU_64B: |
9652 | #endif | |
9653 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); | |
9654 | break; | |
01662f3e | 9655 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
9656 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
9657 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
9658 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
9659 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
9660 | ||
9661 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
9662 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
9663 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
9664 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
9665 | ||
9666 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
9667 | " TLB1CFG " TARGET_FMT_lx "\n", | |
9668 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
9669 | env->spr[SPR_BOOKE_TLB1CFG]); | |
9670 | break; | |
9671 | default: | |
9672 | break; | |
9673 | } | |
f2e63a42 | 9674 | #endif |
79aceca5 | 9675 | |
3fc6c082 FB |
9676 | #undef RGPL |
9677 | #undef RFPL | |
79aceca5 FB |
9678 | } |
9679 | ||
1328c2bf | 9680 | void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf, |
76a66253 JM |
9681 | int flags) |
9682 | { | |
9683 | #if defined(DO_PPC_STATISTICS) | |
c227f099 | 9684 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
9685 | int op1, op2, op3; |
9686 | ||
9687 | t1 = env->opcodes; | |
9688 | for (op1 = 0; op1 < 64; op1++) { | |
9689 | handler = t1[op1]; | |
9690 | if (is_indirect_opcode(handler)) { | |
9691 | t2 = ind_table(handler); | |
9692 | for (op2 = 0; op2 < 32; op2++) { | |
9693 | handler = t2[op2]; | |
9694 | if (is_indirect_opcode(handler)) { | |
9695 | t3 = ind_table(handler); | |
9696 | for (op3 = 0; op3 < 32; op3++) { | |
9697 | handler = t3[op3]; | |
9698 | if (handler->count == 0) | |
9699 | continue; | |
9700 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9701 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9702 | op1, op2, op3, op1, (op3 << 5) | op2, |
9703 | handler->oname, | |
9704 | handler->count, handler->count); | |
9705 | } | |
9706 | } else { | |
9707 | if (handler->count == 0) | |
9708 | continue; | |
9709 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9710 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9711 | op1, op2, op1, op2, handler->oname, |
9712 | handler->count, handler->count); | |
9713 | } | |
9714 | } | |
9715 | } else { | |
9716 | if (handler->count == 0) | |
9717 | continue; | |
0bfcd599 BS |
9718 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
9719 | " %" PRId64 "\n", | |
76a66253 JM |
9720 | op1, op1, handler->oname, |
9721 | handler->count, handler->count); | |
9722 | } | |
9723 | } | |
9724 | #endif | |
9725 | } | |
9726 | ||
9a64fbe4 | 9727 | /*****************************************************************************/ |
1328c2bf | 9728 | static inline void gen_intermediate_code_internal(CPUPPCState *env, |
636aa200 BS |
9729 | TranslationBlock *tb, |
9730 | int search_pc) | |
79aceca5 | 9731 | { |
9fddaa0c | 9732 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 9733 | opc_handler_t **table, *handler; |
0fa85d43 | 9734 | target_ulong pc_start; |
79aceca5 | 9735 | uint16_t *gen_opc_end; |
a1d1bb31 | 9736 | CPUBreakpoint *bp; |
79aceca5 | 9737 | int j, lj = -1; |
2e70f6ef PB |
9738 | int num_insns; |
9739 | int max_insns; | |
79aceca5 FB |
9740 | |
9741 | pc_start = tb->pc; | |
92414b31 | 9742 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 9743 | ctx.nip = pc_start; |
79aceca5 | 9744 | ctx.tb = tb; |
e1833e1f | 9745 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 9746 | ctx.spr_cb = env->spr_cb; |
76db3ba4 | 9747 | ctx.mem_idx = env->mmu_idx; |
7d08d856 AJ |
9748 | ctx.insns_flags = env->insns_flags; |
9749 | ctx.insns_flags2 = env->insns_flags2; | |
76db3ba4 AJ |
9750 | ctx.access_type = -1; |
9751 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
d9bce9d9 | 9752 | #if defined(TARGET_PPC64) |
e42a61f1 | 9753 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 9754 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 9755 | #endif |
3cc62370 | 9756 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 9757 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
9758 | ctx.spe_enabled = msr_spe; |
9759 | else | |
9760 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
9761 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
9762 | ctx.altivec_enabled = msr_vr; | |
9763 | else | |
9764 | ctx.altivec_enabled = 0; | |
d26bfc9a | 9765 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 9766 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 9767 | else |
8cbcb4fa | 9768 | ctx.singlestep_enabled = 0; |
d26bfc9a | 9769 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa AJ |
9770 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
9771 | if (unlikely(env->singlestep_enabled)) | |
9772 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
3fc6c082 | 9773 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
9774 | /* Single step trace mode */ |
9775 | msr_se = 1; | |
9776 | #endif | |
2e70f6ef PB |
9777 | num_insns = 0; |
9778 | max_insns = tb->cflags & CF_COUNT_MASK; | |
9779 | if (max_insns == 0) | |
9780 | max_insns = CF_COUNT_MASK; | |
9781 | ||
806f352d | 9782 | gen_tb_start(); |
9a64fbe4 | 9783 | /* Set env in case of segfault during code fetch */ |
efd7f486 EV |
9784 | while (ctx.exception == POWERPC_EXCP_NONE |
9785 | && tcg_ctx.gen_opc_ptr < gen_opc_end) { | |
72cf2d4f BS |
9786 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
9787 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 9788 | if (bp->pc == ctx.nip) { |
e06fcd75 | 9789 | gen_debug_exception(ctxp); |
ea4e754f FB |
9790 | break; |
9791 | } | |
9792 | } | |
9793 | } | |
76a66253 | 9794 | if (unlikely(search_pc)) { |
92414b31 | 9795 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
79aceca5 FB |
9796 | if (lj < j) { |
9797 | lj++; | |
9798 | while (lj < j) | |
ab1103de | 9799 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
79aceca5 | 9800 | } |
25983cad | 9801 | tcg_ctx.gen_opc_pc[lj] = ctx.nip; |
ab1103de | 9802 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 9803 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
79aceca5 | 9804 | } |
d12d51d5 | 9805 | LOG_DISAS("----------------\n"); |
90e189ec | 9806 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 9807 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
2e70f6ef PB |
9808 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9809 | gen_io_start(); | |
76db3ba4 | 9810 | if (unlikely(ctx.le_mode)) { |
2f5a189c | 9811 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 9812 | } else { |
2f5a189c | 9813 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 9814 | } |
d12d51d5 | 9815 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 9816 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
476b6d16 | 9817 | opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); |
fdefe51c | 9818 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
731c54f8 | 9819 | tcg_gen_debug_insn_start(ctx.nip); |
fdefe51c | 9820 | } |
046d6672 | 9821 | ctx.nip += 4; |
3fc6c082 | 9822 | table = env->opcodes; |
2e70f6ef | 9823 | num_insns++; |
79aceca5 FB |
9824 | handler = table[opc1(ctx.opcode)]; |
9825 | if (is_indirect_opcode(handler)) { | |
9826 | table = ind_table(handler); | |
9827 | handler = table[opc2(ctx.opcode)]; | |
9828 | if (is_indirect_opcode(handler)) { | |
9829 | table = ind_table(handler); | |
9830 | handler = table[opc3(ctx.opcode)]; | |
9831 | } | |
9832 | } | |
9833 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 9834 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
9835 | if (qemu_log_enabled()) { |
9836 | qemu_log("invalid/unsupported opcode: " | |
90e189ec BS |
9837 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
9838 | opc1(ctx.opcode), opc2(ctx.opcode), | |
9839 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa | 9840 | } |
76a66253 | 9841 | } else { |
70560da7 FC |
9842 | uint32_t inval; |
9843 | ||
9844 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
9845 | inval = handler->inval2; | |
9846 | } else { | |
9847 | inval = handler->inval1; | |
9848 | } | |
9849 | ||
9850 | if (unlikely((ctx.opcode & inval) != 0)) { | |
93fcfe39 AL |
9851 | if (qemu_log_enabled()) { |
9852 | qemu_log("invalid bits: %08x for opcode: " | |
90e189ec | 9853 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
70560da7 | 9854 | ctx.opcode & inval, opc1(ctx.opcode), |
90e189ec BS |
9855 | opc2(ctx.opcode), opc3(ctx.opcode), |
9856 | ctx.opcode, ctx.nip - 4); | |
76a66253 | 9857 | } |
e06fcd75 | 9858 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 9859 | break; |
79aceca5 | 9860 | } |
79aceca5 | 9861 | } |
4b3686fa | 9862 | (*(handler->handler))(&ctx); |
76a66253 JM |
9863 | #if defined(DO_PPC_STATISTICS) |
9864 | handler->count++; | |
9865 | #endif | |
9a64fbe4 | 9866 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
9867 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
9868 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
9869 | ctx.exception != POWERPC_SYSCALL && | |
9870 | ctx.exception != POWERPC_EXCP_TRAP && | |
9871 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 9872 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 9873 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
2e70f6ef | 9874 | (env->singlestep_enabled) || |
1b530a6d | 9875 | singlestep || |
2e70f6ef | 9876 | num_insns >= max_insns)) { |
d26bfc9a JM |
9877 | /* if we reach a page boundary or are single stepping, stop |
9878 | * generation | |
9879 | */ | |
8dd4983c | 9880 | break; |
76a66253 | 9881 | } |
3fc6c082 | 9882 | } |
2e70f6ef PB |
9883 | if (tb->cflags & CF_LAST_IO) |
9884 | gen_io_end(); | |
e1833e1f | 9885 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 9886 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 9887 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
8cbcb4fa | 9888 | if (unlikely(env->singlestep_enabled)) { |
e06fcd75 | 9889 | gen_debug_exception(ctxp); |
8cbcb4fa | 9890 | } |
76a66253 | 9891 | /* Generate the return instruction */ |
57fec1fe | 9892 | tcg_gen_exit_tb(0); |
9a64fbe4 | 9893 | } |
806f352d | 9894 | gen_tb_end(tb, num_insns); |
efd7f486 | 9895 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
76a66253 | 9896 | if (unlikely(search_pc)) { |
92414b31 | 9897 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
9a64fbe4 FB |
9898 | lj++; |
9899 | while (lj <= j) | |
ab1103de | 9900 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
9a64fbe4 | 9901 | } else { |
046d6672 | 9902 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 9903 | tb->icount = num_insns; |
9a64fbe4 | 9904 | } |
d9bce9d9 | 9905 | #if defined(DEBUG_DISAS) |
8fec2b8c | 9906 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 9907 | int flags; |
237c0af0 | 9908 | flags = env->bfd_mach; |
76db3ba4 | 9909 | flags |= ctx.le_mode << 16; |
93fcfe39 | 9910 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
f4359b9f | 9911 | log_target_disas(env, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 9912 | qemu_log("\n"); |
9fddaa0c | 9913 | } |
79aceca5 | 9914 | #endif |
79aceca5 FB |
9915 | } |
9916 | ||
1328c2bf | 9917 | void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9918 | { |
2cfc5f17 | 9919 | gen_intermediate_code_internal(env, tb, 0); |
79aceca5 FB |
9920 | } |
9921 | ||
1328c2bf | 9922 | void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9923 | { |
2cfc5f17 | 9924 | gen_intermediate_code_internal(env, tb, 1); |
79aceca5 | 9925 | } |
d2856f1a | 9926 | |
1328c2bf | 9927 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 9928 | { |
25983cad | 9929 | env->nip = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 9930 | } |