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gdbstub: remove unused local variable
[qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
f10dc08e 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
79aceca5 32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
79aceca5 38//#define DO_SINGLE_STEP
9fddaa0c 39//#define PPC_DEBUG_DISAS
a496775f 40//#define DEBUG_MEMORY_ACCESSES
76a66253 41//#define DO_PPC_STATISTICS
7c58044c 42//#define OPTIMIZE_FPRF_UPDATE
79aceca5 43
a750fc0b
JM		 44/*****************************************************************************/
45/* Code translation helpers */
c53be334 46
f78fb44e
AJ		 47/* global register indexes */
48static TCGv cpu_env;
1d542695 49static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 50#if !defined(TARGET_PPC64)
1d542695 51 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 52#endif
a5e26afa 53 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 54 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 + 8*5 /* CRF */];
f78fb44e
AJ		 56static TCGv cpu_gpr[32];
57#if !defined(TARGET_PPC64)
58static TCGv cpu_gprh[32];
59#endif
a5e26afa 60static TCGv cpu_fpr[32];
1d542695 61static TCGv cpu_avrh[32], cpu_avrl[32];
47e4661c 62static TCGv cpu_crf[8];
bd568f18 63static TCGv cpu_nip;
cfdcd37a
AJ		 64static TCGv cpu_ctr;
65static TCGv cpu_lr;
f78fb44e
AJ		 66
67/* dyngen register indexes */
68static TCGv cpu_T[3];
69#if defined(TARGET_PPC64)
70#define cpu_T64 cpu_T
71#else
72static TCGv cpu_T64[3];
73#endif
a5e26afa 74static TCGv cpu_FT[3];
1d542695 75static TCGv cpu_AVRh[3], cpu_AVRl[3];
2e70f6ef
PB		 76
77#include "gen-icount.h"
78
79void ppc_translate_init(void)
80{
f78fb44e
AJ		 81 int i;
82 char* p;
b2437bf2 83 static int done_init = 0;
f78fb44e 84
2e70f6ef
PB		 85 if (done_init)
86 return;
f78fb44e 87
2e70f6ef 88 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
1c73fe5b
AJ		 89#if TARGET_LONG_BITS > HOST_LONG_BITS
90 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
91 TCG_AREG0, offsetof(CPUState, t0), "T0");
92 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
93 TCG_AREG0, offsetof(CPUState, t1), "T1");
94 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
95 TCG_AREG0, offsetof(CPUState, t2), "T2");
96#else
97 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
98 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
99 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
100#endif
f78fb44e
AJ		 101#if !defined(TARGET_PPC64)
102 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 103 TCG_AREG0, offsetof(CPUState, t0_64),
f78fb44e
AJ		 104 "T0_64");
105 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 106 TCG_AREG0, offsetof(CPUState, t1_64),
f78fb44e
AJ		 107 "T1_64");
108 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 109 TCG_AREG0, offsetof(CPUState, t2_64),
f78fb44e
AJ		 110 "T2_64");
111#endif
a5e26afa
AJ		 112
113 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
114 offsetof(CPUState, ft0), "FT0");
115 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
116 offsetof(CPUState, ft1), "FT1");
117 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
118 offsetof(CPUState, ft2), "FT2");
119
1d542695
AJ		 120 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
121 offsetof(CPUState, avr0.u64[0]), "AVR0H");
122 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
123 offsetof(CPUState, avr0.u64[1]), "AVR0L");
124 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
125 offsetof(CPUState, avr1.u64[0]), "AVR1H");
126 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
127 offsetof(CPUState, avr1.u64[1]), "AVR1L");
128 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
129 offsetof(CPUState, avr2.u64[0]), "AVR2H");
130 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
131 offsetof(CPUState, avr2.u64[1]), "AVR2L");
132
f78fb44e 133 p = cpu_reg_names;
47e4661c
AJ		 134
135 for (i = 0; i < 8; i++) {
136 sprintf(p, "crf%d", i);
137 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
138 offsetof(CPUState, crf[i]), p);
139 p += 5;
140 }
141
f78fb44e
AJ		 142 for (i = 0; i < 32; i++) {
143 sprintf(p, "r%d", i);
144 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
145 offsetof(CPUState, gpr[i]), p);
146 p += (i < 10) ? 3 : 4;
147#if !defined(TARGET_PPC64)
148 sprintf(p, "r%dH", i);
149 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
150 offsetof(CPUState, gprh[i]), p);
151 p += (i < 10) ? 4 : 5;
152#endif
1d542695 153
a5e26afa
AJ		 154 sprintf(p, "fp%d", i);
155 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
156 offsetof(CPUState, fpr[i]), p);
ec1ac72d 157 p += (i < 10) ? 4 : 5;
a5e26afa 158
1d542695
AJ		 159 sprintf(p, "avr%dH", i);
160 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
161 offsetof(CPUState, avr[i].u64[0]), p);
162 p += (i < 10) ? 6 : 7;
ec1ac72d 163
1d542695
AJ		 164 sprintf(p, "avr%dL", i);
165 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
166 offsetof(CPUState, avr[i].u64[1]), p);
167 p += (i < 10) ? 6 : 7;
f78fb44e 168 }
f10dc08e 169
bd568f18
AJ		 170 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
171 offsetof(CPUState, nip), "nip");
172
cfdcd37a
AJ		 173 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
174 offsetof(CPUState, ctr), "ctr");
175
176 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
177 offsetof(CPUState, lr), "lr");
178
f10dc08e
AJ		 179 /* register helpers */
180#undef DEF_HELPER
181#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
182#include "helper.h"
183
2e70f6ef
PB		 184 done_init = 1;
185}
186
7c58044c
JM		 187#if defined(OPTIMIZE_FPRF_UPDATE)
188static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
189static uint16_t **gen_fprf_ptr;
190#endif
79aceca5 191
79aceca5
FB		 192/* internal defines */
193typedef struct DisasContext {
194 struct TranslationBlock *tb;
0fa85d43 195 target_ulong nip;
79aceca5 196 uint32_t opcode;
9a64fbe4 197 uint32_t exception;
3cc62370
FB		 198 /* Routine used to access memory */
199 int mem_idx;
200 /* Translation flags */
9a64fbe4 201#if !defined(CONFIG_USER_ONLY)
79aceca5 202 int supervisor;
d9bce9d9
JM		 203#endif
204#if defined(TARGET_PPC64)
205 int sf_mode;
9a64fbe4 206#endif
3cc62370 207 int fpu_enabled;
a9d9eb8f 208 int altivec_enabled;
0487d6a8 209 int spe_enabled;
3fc6c082 210 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 211 int singlestep_enabled;
d63001d1 212 int dcache_line_size;
79aceca5
FB		 213} DisasContext;
214
3fc6c082 215struct opc_handler_t {
79aceca5
FB		 216 /* invalid bits */
217 uint32_t inval;
9a64fbe4 218 /* instruction type */
0487d6a8 219 uint64_t type;
79aceca5
FB		 220 /* handler */
221 void (*handler)(DisasContext *ctx);
a750fc0b 222#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 223 const char *oname;
a750fc0b
JM		 224#endif
225#if defined(DO_PPC_STATISTICS)
76a66253
JM		 226 uint64_t count;
227#endif
3fc6c082 228};
79aceca5 229
b068d6a7 230static always_inline void gen_set_Rc0 (DisasContext *ctx)
76a66253 231{
d9bce9d9
JM		 232#if defined(TARGET_PPC64)
233 if (ctx->sf_mode)
234 gen_op_cmpi_64(0);
235 else
236#endif
237 gen_op_cmpi(0);
76a66253
JM		 238 gen_op_set_Rc0();
239}
240
7c58044c
JM		 241static always_inline void gen_reset_fpstatus (void)
242{
243#ifdef CONFIG_SOFTFLOAT
244 gen_op_reset_fpstatus();
245#endif
246}
247
248static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
249{
250 if (set_fprf != 0) {
251 /* This case might be optimized later */
252#if defined(OPTIMIZE_FPRF_UPDATE)
253 *gen_fprf_ptr++ = gen_opc_ptr;
254#endif
255 gen_op_compute_fprf(1);
256 if (unlikely(set_rc))
47e4661c 257 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 258 gen_op_float_check_status();
259 } else if (unlikely(set_rc)) {
260 /* We always need to compute fpcc */
261 gen_op_compute_fprf(0);
47e4661c 262 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 263 if (set_fprf)
264 gen_op_float_check_status();
265 }
266}
267
268static always_inline void gen_optimize_fprf (void)
269{
270#if defined(OPTIMIZE_FPRF_UPDATE)
271 uint16_t **ptr;
272
273 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
274 *ptr = INDEX_op_nop1;
275 gen_fprf_ptr = gen_fprf_buf;
276#endif
277}
278
b068d6a7 279static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 280{
281#if defined(TARGET_PPC64)
282 if (ctx->sf_mode)
bd568f18 283 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 284 else
285#endif
bd568f18 286 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 287}
288
e1833e1f 289#define GEN_EXCP(ctx, excp, error) \
79aceca5 290do { \
e1833e1f 291 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 292 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 293 } \
294 gen_op_raise_exception_err((excp), (error)); \
295 ctx->exception = (excp); \
79aceca5
FB		 296} while (0)
297
e1833e1f
JM		 298#define GEN_EXCP_INVAL(ctx) \
299GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
300 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 301
e1833e1f
JM		 302#define GEN_EXCP_PRIVOPC(ctx) \
303GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
304 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 305
e1833e1f
JM		 306#define GEN_EXCP_PRIVREG(ctx) \
307GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
308 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
309
310#define GEN_EXCP_NO_FP(ctx) \
311GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
312
313#define GEN_EXCP_NO_AP(ctx) \
314GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 315
a9d9eb8f
JM		 316#define GEN_EXCP_NO_VR(ctx) \
317GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
318
f24e5695 319/* Stop translation */
b068d6a7 320static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 321{
d9bce9d9 322 gen_update_nip(ctx, ctx->nip);
e1833e1f 323 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 324}
325
f24e5695 326/* No need to update nip here, as execution flow will change */
b068d6a7 327static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 328{
e1833e1f 329 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 330}
331
79aceca5
FB		 332#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
333static void gen_##name (DisasContext *ctx); \
334GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
335static void gen_##name (DisasContext *ctx)
336
c7697e1f
JM		 337#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
338static void gen_##name (DisasContext *ctx); \
339GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
340static void gen_##name (DisasContext *ctx)
341
79aceca5
FB		 342typedef struct opcode_t {
343 unsigned char opc1, opc2, opc3;
1235fc06 344#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 345 unsigned char pad[5];
346#else
347 unsigned char pad[1];
348#endif
79aceca5 349 opc_handler_t handler;
b55266b5 350 const char *oname;
79aceca5
FB		 351} opcode_t;
352
a750fc0b 353/*****************************************************************************/
79aceca5
FB		 354/*** Instruction decoding ***/
355#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 356static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 357{ \
358 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
359}
360
361#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 362static always_inline int32_t name (uint32_t opcode) \
79aceca5 363{ \
18fba28c 364 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 365}
366
367/* Opcode part 1 */
368EXTRACT_HELPER(opc1, 26, 6);
369/* Opcode part 2 */
370EXTRACT_HELPER(opc2, 1, 5);
371/* Opcode part 3 */
372EXTRACT_HELPER(opc3, 6, 5);
373/* Update Cr0 flags */
374EXTRACT_HELPER(Rc, 0, 1);
375/* Destination */
376EXTRACT_HELPER(rD, 21, 5);
377/* Source */
378EXTRACT_HELPER(rS, 21, 5);
379/* First operand */
380EXTRACT_HELPER(rA, 16, 5);
381/* Second operand */
382EXTRACT_HELPER(rB, 11, 5);
383/* Third operand */
384EXTRACT_HELPER(rC, 6, 5);
385/*** Get CRn ***/
386EXTRACT_HELPER(crfD, 23, 3);
387EXTRACT_HELPER(crfS, 18, 3);
388EXTRACT_HELPER(crbD, 21, 5);
389EXTRACT_HELPER(crbA, 16, 5);
390EXTRACT_HELPER(crbB, 11, 5);
391/* SPR / TBL */
3fc6c082 392EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 393static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 394{
395 uint32_t sprn = _SPR(opcode);
396
397 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
398}
79aceca5
FB		 399/*** Get constants ***/
400EXTRACT_HELPER(IMM, 12, 8);
401/* 16 bits signed immediate value */
402EXTRACT_SHELPER(SIMM, 0, 16);
403/* 16 bits unsigned immediate value */
404EXTRACT_HELPER(UIMM, 0, 16);
405/* Bit count */
406EXTRACT_HELPER(NB, 11, 5);
407/* Shift count */
408EXTRACT_HELPER(SH, 11, 5);
409/* Mask start */
410EXTRACT_HELPER(MB, 6, 5);
411/* Mask end */
412EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 413/* Trap operand */
414EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 415
416EXTRACT_HELPER(CRM, 12, 8);
417EXTRACT_HELPER(FM, 17, 8);
418EXTRACT_HELPER(SR, 16, 4);
e4bb997e 419EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 420
79aceca5
FB		 421/*** Jump target decoding ***/
422/* Displacement */
423EXTRACT_SHELPER(d, 0, 16);
424/* Immediate address */
b068d6a7 425static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 426{
427 return (opcode >> 0) & 0x03FFFFFC;
428}
429
b068d6a7 430static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 431{
432 return (opcode >> 0) & 0xFFFC;
433}
434
435EXTRACT_HELPER(BO, 21, 5);
436EXTRACT_HELPER(BI, 16, 5);
437/* Absolute/relative address */
438EXTRACT_HELPER(AA, 1, 1);
439/* Link */
440EXTRACT_HELPER(LK, 0, 1);
441
442/* Create a mask between <start> and <end> bits */
b068d6a7 443static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 444{
76a66253 445 target_ulong ret;
79aceca5 446
76a66253
JM		 447#if defined(TARGET_PPC64)
448 if (likely(start == 0)) {
6f2d8978 449 ret = UINT64_MAX << (63 - end);
76a66253 450 } else if (likely(end == 63)) {
6f2d8978 451 ret = UINT64_MAX >> start;
76a66253
JM		 452 }
453#else
454 if (likely(start == 0)) {
6f2d8978 455 ret = UINT32_MAX << (31 - end);
76a66253 456 } else if (likely(end == 31)) {
6f2d8978 457 ret = UINT32_MAX >> start;
76a66253
JM		 458 }
459#endif
460 else {
461 ret = (((target_ulong)(-1ULL)) >> (start)) ^
462 (((target_ulong)(-1ULL) >> (end)) >> 1);
463 if (unlikely(start > end))
464 return ~ret;
465 }
79aceca5
FB		 466
467 return ret;
468}
469
a750fc0b
JM		 470/*****************************************************************************/
471/* PowerPC Instructions types definitions */
472enum {
1b413d55 473 PPC_NONE = 0x0000000000000000ULL,
12de9a39 474 /* PowerPC base instructions set */
1b413d55
JM		 475 PPC_INSNS_BASE = 0x0000000000000001ULL,
476 /* integer operations instructions */
a750fc0b 477#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 478 /* flow control instructions */
a750fc0b 479#define PPC_FLOW PPC_INSNS_BASE
1b413d55 480 /* virtual memory instructions */
a750fc0b 481#define PPC_MEM PPC_INSNS_BASE
1b413d55 482 /* ld/st with reservation instructions */
a750fc0b 483#define PPC_RES PPC_INSNS_BASE
1b413d55 484 /* spr/msr access instructions */
a750fc0b 485#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 486 /* Deprecated instruction sets */
487 /* Original POWER instruction set */
f610349f 488 PPC_POWER = 0x0000000000000002ULL,
1b413d55 489 /* POWER2 instruction set extension */
f610349f 490 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 491 /* Power RTC support */
f610349f 492 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 493 /* Power-to-PowerPC bridge (601) */
f610349f 494 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 495 /* 64 bits PowerPC instruction set */
f610349f 496 PPC_64B = 0x0000000000000020ULL,
1b413d55 497 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 498 PPC_64BX = 0x0000000000000040ULL,
1b413d55 499 /* 64 bits hypervisor extensions */
f610349f 500 PPC_64H = 0x0000000000000080ULL,
1b413d55 501 /* New wait instruction (PowerPC 2.0x) */
f610349f 502 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 503 /* Time base mftb instruction */
f610349f 504 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 505
506 /* Fixed-point unit extensions */
507 /* PowerPC 602 specific */
f610349f 508 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 509 /* isel instruction */
510 PPC_ISEL = 0x0000000000000800ULL,
511 /* popcntb instruction */
512 PPC_POPCNTB = 0x0000000000001000ULL,
513 /* string load / store */
514 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 515
516 /* Floating-point unit extensions */
517 /* Optional floating point instructions */
518 PPC_FLOAT = 0x0000000000010000ULL,
519 /* New floating-point extensions (PowerPC 2.0x) */
520 PPC_FLOAT_EXT = 0x0000000000020000ULL,
521 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
522 PPC_FLOAT_FRES = 0x0000000000080000ULL,
523 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
524 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
525 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
526 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
527
528 /* Vector/SIMD extensions */
529 /* Altivec support */
530 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 531 /* PowerPC 2.03 SPE extension */
05332d70 532 PPC_SPE = 0x0000000002000000ULL,
1b413d55 533 /* PowerPC 2.03 SPE floating-point extension */
05332d70 534 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 535
12de9a39 536 /* Optional memory control instructions */
1b413d55
JM		 537 PPC_MEM_TLBIA = 0x0000000010000000ULL,
538 PPC_MEM_TLBIE = 0x0000000020000000ULL,
539 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
540 /* sync instruction */
541 PPC_MEM_SYNC = 0x0000000080000000ULL,
542 /* eieio instruction */
543 PPC_MEM_EIEIO = 0x0000000100000000ULL,
544
545 /* Cache control instructions */
c8623f2e 546 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 547 /* icbi instruction */
05332d70 548 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 549 /* dcbz instruction with fixed cache line size */
05332d70 550 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 551 /* dcbz instruction with tunable cache line size */
05332d70 552 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 553 /* dcba instruction */
05332d70
JM		 554 PPC_CACHE_DCBA = 0x0000002000000000ULL,
555 /* Freescale cache locking instructions */
556 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 557
558 /* MMU related extensions */
559 /* external control instructions */
05332d70 560 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 561 /* segment register access instructions */
05332d70 562 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 563 /* PowerPC 6xx TLB management instructions */
05332d70 564 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 565 /* PowerPC 74xx TLB management instructions */
05332d70 566 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 567 /* PowerPC 40x TLB management instructions */
05332d70 568 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 569 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 570 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 571 /* SLB management */
05332d70 572 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 573
12de9a39 574 /* Embedded PowerPC dedicated instructions */
05332d70 575 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 576 /* PowerPC 40x exception model */
05332d70 577 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 578 /* PowerPC 405 Mac instructions */
05332d70 579 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 580 /* PowerPC 440 specific instructions */
05332d70 581 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 582 /* BookE (embedded) PowerPC specification */
05332d70
JM		 583 PPC_BOOKE = 0x0010000000000000ULL,
584 /* mfapidi instruction */
585 PPC_MFAPIDI = 0x0020000000000000ULL,
586 /* tlbiva instruction */
587 PPC_TLBIVA = 0x0040000000000000ULL,
588 /* tlbivax instruction */
589 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 590 /* PowerPC 4xx dedicated instructions */
05332d70 591 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 592 /* PowerPC 40x ibct instructions */
05332d70 593 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 594 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 595 PPC_RFMCI = 0x0400000000000000ULL,
596 /* rfdi instruction */
597 PPC_RFDI = 0x0800000000000000ULL,
598 /* DCR accesses */
599 PPC_DCR = 0x1000000000000000ULL,
600 /* DCR extended accesse */
601 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 602 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 603 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 604};
605
606/*****************************************************************************/
607/* PowerPC instructions table */
3fc6c082
FB		 608#if HOST_LONG_BITS == 64
609#define OPC_ALIGN 8
610#else
611#define OPC_ALIGN 4
612#endif
1b039c09 613#if defined(__APPLE__)
d9bce9d9 614#define OPCODES_SECTION \
3fc6c082 615 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 616#else
d9bce9d9 617#define OPCODES_SECTION \
3fc6c082 618 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 619#endif
620
76a66253 621#if defined(DO_PPC_STATISTICS)
79aceca5 622#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 623OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 624 .opc1 = op1, \
625 .opc2 = op2, \
626 .opc3 = op3, \
18fba28c 627 .pad = { 0, }, \
79aceca5
FB		 628 .handler = { \
629 .inval = invl, \
9a64fbe4 630 .type = _typ, \
79aceca5 631 .handler = &gen_##name, \
76a66253 632 .oname = stringify(name), \
79aceca5 633 }, \
3fc6c082 634 .oname = stringify(name), \
79aceca5 635}
c7697e1f
JM		 636#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
637OPCODES_SECTION opcode_t opc_##name = { \
638 .opc1 = op1, \
639 .opc2 = op2, \
640 .opc3 = op3, \
641 .pad = { 0, }, \
642 .handler = { \
643 .inval = invl, \
644 .type = _typ, \
645 .handler = &gen_##name, \
646 .oname = onam, \
647 }, \
648 .oname = onam, \
649}
76a66253
JM		 650#else
651#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
652OPCODES_SECTION opcode_t opc_##name = { \
653 .opc1 = op1, \
654 .opc2 = op2, \
655 .opc3 = op3, \
656 .pad = { 0, }, \
657 .handler = { \
658 .inval = invl, \
659 .type = _typ, \
660 .handler = &gen_##name, \
661 }, \
662 .oname = stringify(name), \
663}
c7697e1f
JM		 664#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
665OPCODES_SECTION opcode_t opc_##name = { \
666 .opc1 = op1, \
667 .opc2 = op2, \
668 .opc3 = op3, \
669 .pad = { 0, }, \
670 .handler = { \
671 .inval = invl, \
672 .type = _typ, \
673 .handler = &gen_##name, \
674 }, \
675 .oname = onam, \
676}
76a66253 677#endif
79aceca5
FB		 678
679#define GEN_OPCODE_MARK(name) \
18fba28c 680OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 681 .opc1 = 0xFF, \
682 .opc2 = 0xFF, \
683 .opc3 = 0xFF, \
18fba28c 684 .pad = { 0, }, \
79aceca5
FB		 685 .handler = { \
686 .inval = 0x00000000, \
9a64fbe4 687 .type = 0x00, \
79aceca5
FB		 688 .handler = NULL, \
689 }, \
3fc6c082 690 .oname = stringify(name), \
79aceca5
FB		 691}
692
693/* Start opcode list */
694GEN_OPCODE_MARK(start);
695
696/* Invalid instruction */
9a64fbe4
FB		 697GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
698{
e1833e1f 699 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 700}
701
79aceca5
FB		 702static opc_handler_t invalid_handler = {
703 .inval = 0xFFFFFFFF,
9a64fbe4 704 .type = PPC_NONE,
79aceca5
FB		 705 .handler = gen_invalid,
706};
707
708/*** Integer arithmetic ***/
d9bce9d9
JM		 709#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
710GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 711{ \
f78fb44e
AJ		 712 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
713 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 714 gen_op_##name(); \
f78fb44e 715 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 716 if (unlikely(Rc(ctx->opcode) != 0)) \
717 gen_set_Rc0(ctx); \
79aceca5
FB		 718}
719
d9bce9d9
JM		 720#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
721GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 722{ \
f78fb44e
AJ		 723 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
724 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 725 gen_op_##name(); \
f78fb44e 726 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 727 if (unlikely(Rc(ctx->opcode) != 0)) \
728 gen_set_Rc0(ctx); \
79aceca5
FB		 729}
730
d9bce9d9
JM		 731#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
732GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 733{ \
f78fb44e 734 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 735 gen_op_##name(); \
f78fb44e 736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 737 if (unlikely(Rc(ctx->opcode) != 0)) \
738 gen_set_Rc0(ctx); \
79aceca5 739}
d9bce9d9
JM		 740#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
741GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 742{ \
f78fb44e 743 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 744 gen_op_##name(); \
f78fb44e 745 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 746 if (unlikely(Rc(ctx->opcode) != 0)) \
747 gen_set_Rc0(ctx); \
79aceca5
FB		 748}
749
750/* Two operands arithmetic functions */
d9bce9d9
JM		 751#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
752__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
753__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
754
755/* Two operands arithmetic functions with no overflow allowed */
756#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
757__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
758
759/* One operand arithmetic functions */
760#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
761__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
762__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
763
764#if defined(TARGET_PPC64)
765#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
766GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
767{ \
f78fb44e
AJ		 768 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
769 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 770 if (ctx->sf_mode) \
771 gen_op_##name##_64(); \
772 else \
773 gen_op_##name(); \
f78fb44e 774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 775 if (unlikely(Rc(ctx->opcode) != 0)) \
776 gen_set_Rc0(ctx); \
777}
778
779#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
780GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
781{ \
f78fb44e
AJ		 782 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
783 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 784 if (ctx->sf_mode) \
785 gen_op_##name##_64(); \
786 else \
787 gen_op_##name(); \
f78fb44e 788 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 789 if (unlikely(Rc(ctx->opcode) != 0)) \
790 gen_set_Rc0(ctx); \
791}
792
793#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
794GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
795{ \
f78fb44e 796 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 797 if (ctx->sf_mode) \
798 gen_op_##name##_64(); \
799 else \
800 gen_op_##name(); \
f78fb44e 801 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 802 if (unlikely(Rc(ctx->opcode) != 0)) \
803 gen_set_Rc0(ctx); \
804}
805#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
806GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
807{ \
f78fb44e 808 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 809 if (ctx->sf_mode) \
810 gen_op_##name##_64(); \
811 else \
812 gen_op_##name(); \
f78fb44e 813 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 814 if (unlikely(Rc(ctx->opcode) != 0)) \
815 gen_set_Rc0(ctx); \
816}
817
818/* Two operands arithmetic functions */
819#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
820__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
821__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 822
823/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 824#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
825__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 826
827/* One operand arithmetic functions */
d9bce9d9
JM		 828#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
829__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
830__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
831#else
832#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
833#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
834#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
835#endif
79aceca5
FB		 836
837/* add add. addo addo. */
39dd32ee
AJ		 838static always_inline void gen_op_add (void)
839{
840 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
841}
b068d6a7 842static always_inline void gen_op_addo (void)
d9bce9d9 843{
e55fd934 844 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 845 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 846 gen_op_check_addo();
847}
848#if defined(TARGET_PPC64)
849#define gen_op_add_64 gen_op_add
b068d6a7 850static always_inline void gen_op_addo_64 (void)
d9bce9d9 851{
e55fd934 852 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 853 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 854 gen_op_check_addo_64();
855}
856#endif
857GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 858/* addc addc. addco addco. */
b068d6a7 859static always_inline void gen_op_addc (void)
d9bce9d9 860{
e55fd934 861 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 862 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 863 gen_op_check_addc();
864}
b068d6a7 865static always_inline void gen_op_addco (void)
d9bce9d9 866{
e55fd934 867 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 868 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 869 gen_op_check_addc();
870 gen_op_check_addo();
871}
872#if defined(TARGET_PPC64)
b068d6a7 873static always_inline void gen_op_addc_64 (void)
d9bce9d9 874{
e55fd934 875 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 876 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 877 gen_op_check_addc_64();
878}
b068d6a7 879static always_inline void gen_op_addco_64 (void)
d9bce9d9 880{
e55fd934 881 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 882 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 883 gen_op_check_addc_64();
884 gen_op_check_addo_64();
885}
886#endif
887GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 888/* adde adde. addeo addeo. */
b068d6a7 889static always_inline void gen_op_addeo (void)
d9bce9d9 890{
e55fd934 891 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 892 gen_op_adde();
893 gen_op_check_addo();
894}
895#if defined(TARGET_PPC64)
b068d6a7 896static always_inline void gen_op_addeo_64 (void)
d9bce9d9 897{
e55fd934 898 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 899 gen_op_adde_64();
900 gen_op_check_addo_64();
901}
902#endif
903GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 904/* addme addme. addmeo addmeo. */
b068d6a7 905static always_inline void gen_op_addme (void)
d9bce9d9 906{
e55fd934 907 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 908 gen_op_add_me();
909}
910#if defined(TARGET_PPC64)
b068d6a7 911static always_inline void gen_op_addme_64 (void)
d9bce9d9 912{
e55fd934 913 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 914 gen_op_add_me_64();
915}
916#endif
917GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 918/* addze addze. addzeo addzeo. */
b068d6a7 919static always_inline void gen_op_addze (void)
d9bce9d9 920{
e55fd934 921 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 922 gen_op_add_ze();
923 gen_op_check_addc();
924}
b068d6a7 925static always_inline void gen_op_addzeo (void)
d9bce9d9 926{
e55fd934 927 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 928 gen_op_add_ze();
929 gen_op_check_addc();
930 gen_op_check_addo();
931}
932#if defined(TARGET_PPC64)
b068d6a7 933static always_inline void gen_op_addze_64 (void)
d9bce9d9 934{
e55fd934 935 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 936 gen_op_add_ze();
937 gen_op_check_addc_64();
938}
b068d6a7 939static always_inline void gen_op_addzeo_64 (void)
d9bce9d9 940{
e55fd934 941 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 942 gen_op_add_ze();
943 gen_op_check_addc_64();
944 gen_op_check_addo_64();
945}
946#endif
947GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 948/* divw divw. divwo divwo. */
d9bce9d9 949GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 950/* divwu divwu. divwuo divwuo. */
d9bce9d9 951GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 952/* mulhw mulhw. */
d9bce9d9 953GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 954/* mulhwu mulhwu. */
d9bce9d9 955GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 956/* mullw mullw. mullwo mullwo. */
d9bce9d9 957GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 958/* neg neg. nego nego. */
d9bce9d9 959GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 960/* subf subf. subfo subfo. */
7c417963
AJ		 961static always_inline void gen_op_subf (void)
962{
963 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
964}
b068d6a7 965static always_inline void gen_op_subfo (void)
d9bce9d9 966{
f0413473 967 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 968 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 969 gen_op_check_addo();
d9bce9d9
JM		 970}
971#if defined(TARGET_PPC64)
972#define gen_op_subf_64 gen_op_subf
b068d6a7 973static always_inline void gen_op_subfo_64 (void)
d9bce9d9 974{
f0413473 975 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 976 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 977 gen_op_check_addo_64();
d9bce9d9
JM		 978}
979#endif
980GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 981/* subfc subfc. subfco subfco. */
b068d6a7 982static always_inline void gen_op_subfc (void)
d9bce9d9 983{
7c417963 984 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 985 gen_op_check_subfc();
986}
b068d6a7 987static always_inline void gen_op_subfco (void)
d9bce9d9 988{
f0413473 989 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 990 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 991 gen_op_check_subfc();
c3e10c7b 992 gen_op_check_addo();
d9bce9d9
JM		 993}
994#if defined(TARGET_PPC64)
b068d6a7 995static always_inline void gen_op_subfc_64 (void)
d9bce9d9 996{
7c417963 997 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 998 gen_op_check_subfc_64();
999}
b068d6a7 1000static always_inline void gen_op_subfco_64 (void)
d9bce9d9 1001{
f0413473 1002 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 1003 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 1004 gen_op_check_subfc_64();
c3e10c7b 1005 gen_op_check_addo_64();
d9bce9d9
JM		 1006}
1007#endif
1008GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 1009/* subfe subfe. subfeo subfeo. */
b068d6a7 1010static always_inline void gen_op_subfeo (void)
d9bce9d9 1011{
f0413473 1012 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
d9bce9d9 1013 gen_op_subfe();
c3e10c7b 1014 gen_op_check_addo();
d9bce9d9
JM		 1015}
1016#if defined(TARGET_PPC64)
1017#define gen_op_subfe_64 gen_op_subfe
b068d6a7 1018static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 1019{
f0413473 1020 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
d9bce9d9 1021 gen_op_subfe_64();
c3e10c7b 1022 gen_op_check_addo_64();
d9bce9d9
JM		 1023}
1024#endif
1025GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 1026/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 1027GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 1028/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 1029GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 1030/* addi */
1031GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1032{
76a66253 1033 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1034
1035 if (rA(ctx->opcode) == 0) {
76a66253 1036 /* li case */
02f4f6c2 1037 tcg_gen_movi_tl(cpu_T[0], simm);
79aceca5 1038 } else {
f78fb44e 1039 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1040 if (likely(simm != 0))
39dd32ee 1041 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
79aceca5 1042 }
f78fb44e 1043 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1044}
1045/* addic */
1046GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1047{
76a66253
JM		 1048 target_long simm = SIMM(ctx->opcode);
1049
f78fb44e 1050 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1051 if (likely(simm != 0)) {
e55fd934 1052 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1053 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1054#if defined(TARGET_PPC64)
1055 if (ctx->sf_mode)
1056 gen_op_check_addc_64();
1057 else
1058#endif
1059 gen_op_check_addc();
e864cabd
JM		 1060 } else {
1061 gen_op_clear_xer_ca();
d9bce9d9 1062 }
f78fb44e 1063 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1064}
1065/* addic. */
c7697e1f 1066GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1067{
76a66253
JM		 1068 target_long simm = SIMM(ctx->opcode);
1069
f78fb44e 1070 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1071 if (likely(simm != 0)) {
e55fd934 1072 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1073 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1074#if defined(TARGET_PPC64)
1075 if (ctx->sf_mode)
1076 gen_op_check_addc_64();
1077 else
1078#endif
1079 gen_op_check_addc();
966439a6
JM		 1080 } else {
1081 gen_op_clear_xer_ca();
d9bce9d9 1082 }
f78fb44e 1083 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 1084 gen_set_Rc0(ctx);
79aceca5
FB		 1085}
1086/* addis */
1087GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1088{
76a66253 1089 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1090
1091 if (rA(ctx->opcode) == 0) {
76a66253 1092 /* lis case */
02f4f6c2 1093 tcg_gen_movi_tl(cpu_T[0], simm << 16);
79aceca5 1094 } else {
f78fb44e 1095 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1096 if (likely(simm != 0))
39dd32ee 1097 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16);
79aceca5 1098 }
f78fb44e 1099 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1100}
1101/* mulli */
1102GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1103{
f78fb44e 1104 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
79aceca5 1105 gen_op_mulli(SIMM(ctx->opcode));
f78fb44e 1106 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1107}
1108/* subfic */
1109GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1110{
f78fb44e 1111 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9
JM		 1112#if defined(TARGET_PPC64)
1113 if (ctx->sf_mode)
1114 gen_op_subfic_64(SIMM(ctx->opcode));
1115 else
1116#endif
1117 gen_op_subfic(SIMM(ctx->opcode));
f78fb44e 1118 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1119}
1120
d9bce9d9
JM		 1121#if defined(TARGET_PPC64)
1122/* mulhd mulhd. */
a750fc0b 1123GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1124/* mulhdu mulhdu. */
a750fc0b 1125GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1126/* mulld mulld. mulldo mulldo. */
a750fc0b 1127GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1128/* divd divd. divdo divdo. */
a750fc0b 1129GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1130/* divdu divdu. divduo divduo. */
a750fc0b 1131GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1132#endif
1133
79aceca5 1134/*** Integer comparison ***/
d9bce9d9
JM		 1135#if defined(TARGET_PPC64)
1136#define GEN_CMP(name, opc, type) \
1137GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1138{ \
f78fb44e
AJ		 1139 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
1140 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
e3878283 1141 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
d9bce9d9
JM		 1142 gen_op_##name##_64(); \
1143 else \
1144 gen_op_##name(); \
47e4661c 1145 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
d9bce9d9
JM		 1146}
1147#else
1148#define GEN_CMP(name, opc, type) \
1149GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
79aceca5 1150{ \
f78fb44e
AJ		 1151 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
1152 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 1153 gen_op_##name(); \
47e4661c 1154 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
79aceca5 1155}
d9bce9d9 1156#endif
79aceca5
FB		 1157
1158/* cmp */
d9bce9d9 1159GEN_CMP(cmp, 0x00, PPC_INTEGER);
79aceca5
FB		 1160/* cmpi */
1161GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1162{
f78fb44e 1163 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1164#if defined(TARGET_PPC64)
e3878283 1165 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1166 gen_op_cmpi_64(SIMM(ctx->opcode));
1167 else
1168#endif
1169 gen_op_cmpi(SIMM(ctx->opcode));
47e4661c 1170 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
79aceca5
FB		 1171}
1172/* cmpl */
d9bce9d9 1173GEN_CMP(cmpl, 0x01, PPC_INTEGER);
79aceca5
FB		 1174/* cmpli */
1175GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1176{
f78fb44e 1177 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1178#if defined(TARGET_PPC64)
e3878283 1179 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1180 gen_op_cmpli_64(UIMM(ctx->opcode));
1181 else
1182#endif
1183 gen_op_cmpli(UIMM(ctx->opcode));
47e4661c 1184 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
79aceca5
FB		 1185}
1186
d9bce9d9 1187/* isel (PowerPC 2.03 specification) */
fd501a05 1188GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
d9bce9d9
JM		 1189{
1190 uint32_t bi = rC(ctx->opcode);
1191 uint32_t mask;
1192
1193 if (rA(ctx->opcode) == 0) {
02f4f6c2 1194 tcg_gen_movi_tl(cpu_T[0], 0);
d9bce9d9 1195 } else {
f78fb44e 1196 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1197 }
f78fb44e 1198 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1199 mask = 1 << (3 - (bi & 0x03));
47e4661c 1200 tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]);
d9bce9d9
JM		 1201 gen_op_test_true(mask);
1202 gen_op_isel();
f78fb44e 1203 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1204}
1205
79aceca5 1206/*** Integer logical ***/
d9bce9d9
JM		 1207#define __GEN_LOGICAL2(name, opc2, opc3, type) \
1208GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
79aceca5 1209{ \
f78fb44e
AJ		 1210 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
1211 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 1212 gen_op_##name(); \
f78fb44e 1213 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 1214 if (unlikely(Rc(ctx->opcode) != 0)) \
1215 gen_set_Rc0(ctx); \
79aceca5 1216}
d9bce9d9
JM		 1217#define GEN_LOGICAL2(name, opc, type) \
1218__GEN_LOGICAL2(name, 0x1C, opc, type)
79aceca5 1219
d9bce9d9
JM		 1220#define GEN_LOGICAL1(name, opc, type) \
1221GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1222{ \
f78fb44e 1223 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
79aceca5 1224 gen_op_##name(); \
f78fb44e 1225 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 1226 if (unlikely(Rc(ctx->opcode) != 0)) \
1227 gen_set_Rc0(ctx); \
79aceca5
FB		 1228}
1229
1230/* and & and. */
d9bce9d9 1231GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
79aceca5 1232/* andc & andc. */
d9bce9d9 1233GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
79aceca5 1234/* andi. */
c7697e1f 1235GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1236{
f78fb44e 1237 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
0df5bdbe 1238 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
f78fb44e 1239 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1240 gen_set_Rc0(ctx);
79aceca5
FB		 1241}
1242/* andis. */
c7697e1f 1243GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1244{
f78fb44e 1245 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
0df5bdbe 1246 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
f78fb44e 1247 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1248 gen_set_Rc0(ctx);
79aceca5
FB		 1249}
1250
1251/* cntlzw */
d9bce9d9 1252GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
79aceca5 1253/* eqv & eqv. */
d9bce9d9 1254GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
79aceca5 1255/* extsb & extsb. */
d9bce9d9 1256GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
79aceca5 1257/* extsh & extsh. */
d9bce9d9 1258GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
79aceca5 1259/* nand & nand. */
d9bce9d9 1260GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
79aceca5 1261/* nor & nor. */
d9bce9d9 1262GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
9a64fbe4 1263
79aceca5 1264/* or & or. */
9a64fbe4
FB		 1265GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1266{
76a66253
JM		 1267 int rs, ra, rb;
1268
1269 rs = rS(ctx->opcode);
1270 ra = rA(ctx->opcode);
1271 rb = rB(ctx->opcode);
1272 /* Optimisation for mr. ri case */
1273 if (rs != ra || rs != rb) {
f78fb44e 1274 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
76a66253 1275 if (rs != rb) {
f78fb44e 1276 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 1277 gen_op_or();
1278 }
f78fb44e 1279 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 1280 if (unlikely(Rc(ctx->opcode) != 0))
1281 gen_set_Rc0(ctx);
1282 } else if (unlikely(Rc(ctx->opcode) != 0)) {
f78fb44e 1283 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
76a66253 1284 gen_set_Rc0(ctx);
c80f84e3
JM		 1285#if defined(TARGET_PPC64)
1286 } else {
1287 switch (rs) {
1288 case 1:
1289 /* Set process priority to low */
1290 gen_op_store_pri(2);
1291 break;
1292 case 6:
1293 /* Set process priority to medium-low */
1294 gen_op_store_pri(3);
1295 break;
1296 case 2:
1297 /* Set process priority to normal */
1298 gen_op_store_pri(4);
1299 break;
be147d08
JM		 1300#if !defined(CONFIG_USER_ONLY)
1301 case 31:
1302 if (ctx->supervisor > 0) {
1303 /* Set process priority to very low */
1304 gen_op_store_pri(1);
1305 }
1306 break;
1307 case 5:
1308 if (ctx->supervisor > 0) {
1309 /* Set process priority to medium-hight */
1310 gen_op_store_pri(5);
1311 }
1312 break;
1313 case 3:
1314 if (ctx->supervisor > 0) {
1315 /* Set process priority to high */
1316 gen_op_store_pri(6);
1317 }
1318 break;
be147d08
JM		 1319 case 7:
1320 if (ctx->supervisor > 1) {
1321 /* Set process priority to very high */
1322 gen_op_store_pri(7);
1323 }
1324 break;
be147d08 1325#endif
c80f84e3
JM		 1326 default:
1327 /* nop */
1328 break;
1329 }
1330#endif
9a64fbe4 1331 }
9a64fbe4
FB		 1332}
1333
79aceca5 1334/* orc & orc. */
d9bce9d9 1335GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
79aceca5 1336/* xor & xor. */
9a64fbe4
FB		 1337GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1338{
f78fb44e 1339 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4
FB		 1340 /* Optimisation for "set to zero" case */
1341 if (rS(ctx->opcode) != rB(ctx->opcode)) {
f78fb44e 1342 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
9a64fbe4
FB		 1343 gen_op_xor();
1344 } else {
86c581dc 1345 tcg_gen_movi_tl(cpu_T[0], 0);
9a64fbe4 1346 }
f78fb44e 1347 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1348 if (unlikely(Rc(ctx->opcode) != 0))
1349 gen_set_Rc0(ctx);
9a64fbe4 1350}
79aceca5
FB		 1351/* ori */
1352GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1353{
76a66253 1354 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1355
9a64fbe4
FB		 1356 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1357 /* NOP */
76a66253 1358 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1359 return;
76a66253 1360 }
f78fb44e 1361 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253 1362 if (likely(uimm != 0))
79aceca5 1363 gen_op_ori(uimm);
f78fb44e 1364 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1365}
1366/* oris */
1367GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1368{
76a66253 1369 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1370
9a64fbe4
FB		 1371 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1372 /* NOP */
1373 return;
76a66253 1374 }
f78fb44e 1375 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253 1376 if (likely(uimm != 0))
79aceca5 1377 gen_op_ori(uimm << 16);
f78fb44e 1378 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1379}
1380/* xori */
1381GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1382{
76a66253 1383 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1384
1385 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1386 /* NOP */
1387 return;
1388 }
f78fb44e 1389 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1390 if (likely(uimm != 0))
1391 gen_op_xori(uimm);
f78fb44e 1392 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1393}
1394
1395/* xoris */
1396GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1397{
76a66253 1398 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1399
1400 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1401 /* NOP */
1402 return;
1403 }
f78fb44e 1404 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1405 if (likely(uimm != 0))
1406 gen_op_xori(uimm << 16);
f78fb44e 1407 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1408}
1409
d9bce9d9 1410/* popcntb : PowerPC 2.03 specification */
05332d70 1411GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1412{
f78fb44e 1413 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1414#if defined(TARGET_PPC64)
1415 if (ctx->sf_mode)
6676f424 1416 gen_op_popcntb_64();
d9bce9d9
JM		 1417 else
1418#endif
6676f424 1419 gen_op_popcntb();
f78fb44e 1420 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1421}
1422
1423#if defined(TARGET_PPC64)
1424/* extsw & extsw. */
1425GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1426/* cntlzd */
1427GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1428#endif
1429
79aceca5
FB		 1430/*** Integer rotate ***/
1431/* rlwimi & rlwimi. */
1432GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1433{
76a66253
JM		 1434 target_ulong mask;
1435 uint32_t mb, me, sh;
79aceca5
FB		 1436
1437 mb = MB(ctx->opcode);
1438 me = ME(ctx->opcode);
76a66253 1439 sh = SH(ctx->opcode);
76a66253
JM		 1440 if (likely(sh == 0)) {
1441 if (likely(mb == 0 && me == 31)) {
f78fb44e 1442 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1443 goto do_store;
1444 } else if (likely(mb == 31 && me == 0)) {
f78fb44e 1445 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1446 goto do_store;
1447 }
f78fb44e
AJ		 1448 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1449 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1450 goto do_mask;
1451 }
f78fb44e
AJ		 1452 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1453 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1454 gen_op_rotli32_T0(SH(ctx->opcode));
1455 do_mask:
1456#if defined(TARGET_PPC64)
1457 mb += 32;
1458 me += 32;
1459#endif
1460 mask = MASK(mb, me);
0df5bdbe
AJ		 1461 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1462 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
76a66253
JM		 1463 gen_op_or();
1464 do_store:
f78fb44e 1465 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1466 if (unlikely(Rc(ctx->opcode) != 0))
1467 gen_set_Rc0(ctx);
79aceca5
FB		 1468}
1469/* rlwinm & rlwinm. */
1470GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1471{
1472 uint32_t mb, me, sh;
3b46e624 1473
79aceca5
FB		 1474 sh = SH(ctx->opcode);
1475 mb = MB(ctx->opcode);
1476 me = ME(ctx->opcode);
f78fb44e 1477 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1478 if (likely(sh == 0)) {
1479 goto do_mask;
1480 }
1481 if (likely(mb == 0)) {
1482 if (likely(me == 31)) {
1483 gen_op_rotli32_T0(sh);
1484 goto do_store;
1485 } else if (likely(me == (31 - sh))) {
1486 gen_op_sli_T0(sh);
1487 goto do_store;
79aceca5 1488 }
76a66253
JM		 1489 } else if (likely(me == 31)) {
1490 if (likely(sh == (32 - mb))) {
1491 gen_op_srli_T0(mb);
1492 goto do_store;
79aceca5
FB		 1493 }
1494 }
76a66253
JM		 1495 gen_op_rotli32_T0(sh);
1496 do_mask:
1497#if defined(TARGET_PPC64)
1498 mb += 32;
1499 me += 32;
1500#endif
0df5bdbe 1501 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
76a66253 1502 do_store:
f78fb44e 1503 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1504 if (unlikely(Rc(ctx->opcode) != 0))
1505 gen_set_Rc0(ctx);
79aceca5
FB		 1506}
1507/* rlwnm & rlwnm. */
1508GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1509{
1510 uint32_t mb, me;
1511
1512 mb = MB(ctx->opcode);
1513 me = ME(ctx->opcode);
f78fb44e
AJ		 1514 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1515 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 1516 gen_op_rotl32_T0_T1();
1517 if (unlikely(mb != 0 || me != 31)) {
1518#if defined(TARGET_PPC64)
1519 mb += 32;
1520 me += 32;
1521#endif
0df5bdbe 1522 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
79aceca5 1523 }
f78fb44e 1524 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1525 if (unlikely(Rc(ctx->opcode) != 0))
1526 gen_set_Rc0(ctx);
79aceca5
FB		 1527}
1528
d9bce9d9
JM		 1529#if defined(TARGET_PPC64)
1530#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1531GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1532{ \
1533 gen_##name(ctx, 0); \
1534} \
c7697e1f
JM		 1535GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1536 PPC_64B) \
d9bce9d9
JM		 1537{ \
1538 gen_##name(ctx, 1); \
1539}
1540#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1541GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1542{ \
1543 gen_##name(ctx, 0, 0); \
1544} \
c7697e1f
JM		 1545GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1546 PPC_64B) \
d9bce9d9
JM		 1547{ \
1548 gen_##name(ctx, 0, 1); \
1549} \
c7697e1f
JM		 1550GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1551 PPC_64B) \
d9bce9d9
JM		 1552{ \
1553 gen_##name(ctx, 1, 0); \
1554} \
c7697e1f
JM		 1555GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1556 PPC_64B) \
d9bce9d9
JM		 1557{ \
1558 gen_##name(ctx, 1, 1); \
1559}
51789c41 1560
b068d6a7
JM		 1561static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1562 uint32_t me, uint32_t sh)
51789c41 1563{
f78fb44e 1564 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41
JM		 1565 if (likely(sh == 0)) {
1566 goto do_mask;
1567 }
1568 if (likely(mb == 0)) {
1569 if (likely(me == 63)) {
40d0591e 1570 gen_op_rotli64_T0(sh);
51789c41
JM		 1571 goto do_store;
1572 } else if (likely(me == (63 - sh))) {
1573 gen_op_sli_T0(sh);
1574 goto do_store;
1575 }
1576 } else if (likely(me == 63)) {
1577 if (likely(sh == (64 - mb))) {
40d0591e 1578 gen_op_srli_T0_64(mb);
51789c41
JM		 1579 goto do_store;
1580 }
1581 }
1582 gen_op_rotli64_T0(sh);
1583 do_mask:
0df5bdbe 1584 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1585 do_store:
f78fb44e 1586 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41
JM		 1587 if (unlikely(Rc(ctx->opcode) != 0))
1588 gen_set_Rc0(ctx);
1589}
d9bce9d9 1590/* rldicl - rldicl. */
b068d6a7 1591static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1592{
51789c41 1593 uint32_t sh, mb;
d9bce9d9 1594
9d53c753
JM		 1595 sh = SH(ctx->opcode) | (shn << 5);
1596 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1597 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1598}
51789c41 1599GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1600/* rldicr - rldicr. */
b068d6a7 1601static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1602{
51789c41 1603 uint32_t sh, me;
d9bce9d9 1604
9d53c753
JM		 1605 sh = SH(ctx->opcode) | (shn << 5);
1606 me = MB(ctx->opcode) | (men << 5);
51789c41 1607 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1608}
51789c41 1609GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1610/* rldic - rldic. */
b068d6a7 1611static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1612{
51789c41 1613 uint32_t sh, mb;
d9bce9d9 1614
9d53c753
JM		 1615 sh = SH(ctx->opcode) | (shn << 5);
1616 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1617 gen_rldinm(ctx, mb, 63 - sh, sh);
1618}
1619GEN_PPC64_R4(rldic, 0x1E, 0x04);
1620
b068d6a7
JM		 1621static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1622 uint32_t me)
51789c41 1623{
f78fb44e
AJ		 1624 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1625 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
51789c41
JM		 1626 gen_op_rotl64_T0_T1();
1627 if (unlikely(mb != 0 || me != 63)) {
0df5bdbe 1628 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1629 }
f78fb44e 1630 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41
JM		 1631 if (unlikely(Rc(ctx->opcode) != 0))
1632 gen_set_Rc0(ctx);
d9bce9d9 1633}
51789c41 1634
d9bce9d9 1635/* rldcl - rldcl. */
b068d6a7 1636static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1637{
51789c41 1638 uint32_t mb;
d9bce9d9 1639
9d53c753 1640 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1641 gen_rldnm(ctx, mb, 63);
d9bce9d9 1642}
36081602 1643GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1644/* rldcr - rldcr. */
b068d6a7 1645static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1646{
51789c41 1647 uint32_t me;
d9bce9d9 1648
9d53c753 1649 me = MB(ctx->opcode) | (men << 5);
51789c41 1650 gen_rldnm(ctx, 0, me);
d9bce9d9 1651}
36081602 1652GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1653/* rldimi - rldimi. */
b068d6a7 1654static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1655{
51789c41 1656 uint64_t mask;
271a916e 1657 uint32_t sh, mb, me;
d9bce9d9 1658
9d53c753
JM		 1659 sh = SH(ctx->opcode) | (shn << 5);
1660 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1661 me = 63 - sh;
51789c41
JM		 1662 if (likely(sh == 0)) {
1663 if (likely(mb == 0)) {
f78fb44e 1664 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41 1665 goto do_store;
51789c41 1666 }
f78fb44e
AJ		 1667 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1668 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
51789c41
JM		 1669 goto do_mask;
1670 }
f78fb44e
AJ		 1671 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1672 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
40d0591e 1673 gen_op_rotli64_T0(sh);
51789c41 1674 do_mask:
271a916e 1675 mask = MASK(mb, me);
0df5bdbe
AJ		 1676 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1677 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
51789c41
JM		 1678 gen_op_or();
1679 do_store:
f78fb44e 1680 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41
JM		 1681 if (unlikely(Rc(ctx->opcode) != 0))
1682 gen_set_Rc0(ctx);
d9bce9d9 1683}
36081602 1684GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1685#endif
1686
79aceca5
FB		 1687/*** Integer shift ***/
1688/* slw & slw. */
d9bce9d9 1689__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
79aceca5 1690/* sraw & sraw. */
d9bce9d9 1691__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
79aceca5
FB		 1692/* srawi & srawi. */
1693GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1694{
d9bce9d9 1695 int mb, me;
f78fb44e 1696 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1697 if (SH(ctx->opcode) != 0) {
e55fd934 1698 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1699 mb = 32 - SH(ctx->opcode);
1700 me = 31;
1701#if defined(TARGET_PPC64)
1702 mb += 32;
1703 me += 32;
1704#endif
1705 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1706 }
f78fb44e 1707 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1708 if (unlikely(Rc(ctx->opcode) != 0))
1709 gen_set_Rc0(ctx);
79aceca5
FB		 1710}
1711/* srw & srw. */
d9bce9d9
JM		 1712__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1713
1714#if defined(TARGET_PPC64)
1715/* sld & sld. */
1716__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1717/* srad & srad. */
1718__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1719/* sradi & sradi. */
b068d6a7 1720static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9
JM		 1721{
1722 uint64_t mask;
1723 int sh, mb, me;
1724
f78fb44e 1725 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1726 sh = SH(ctx->opcode) + (n << 5);
1727 if (sh != 0) {
e55fd934 1728 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1729 mb = 64 - SH(ctx->opcode);
1730 me = 63;
1731 mask = MASK(mb, me);
1732 gen_op_sradi(sh, mask >> 32, mask);
1733 }
f78fb44e 1734 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1735 if (unlikely(Rc(ctx->opcode) != 0))
1736 gen_set_Rc0(ctx);
1737}
c7697e1f 1738GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1739{
1740 gen_sradi(ctx, 0);
1741}
c7697e1f 1742GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1743{
1744 gen_sradi(ctx, 1);
1745}
1746/* srd & srd. */
1747__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1748#endif
79aceca5
FB		 1749
1750/*** Floating-Point arithmetic ***/
7c58044c 1751#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1752GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1753{ \
76a66253 1754 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1755 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1756 return; \
1757 } \
a5e26afa
AJ		 1758 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1759 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
1760 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1761 gen_reset_fpstatus(); \
4ecc3190
FB		 1762 gen_op_f##op(); \
1763 if (isfloat) { \
1764 gen_op_frsp(); \
1765 } \
a5e26afa 1766 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1767 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1768}
1769
7c58044c
JM		 1770#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1771_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1772_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1773
7c58044c
JM		 1774#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1775GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1776{ \
76a66253 1777 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1778 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1779 return; \
1780 } \
a5e26afa
AJ		 1781 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1782 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1783 gen_reset_fpstatus(); \
4ecc3190
FB		 1784 gen_op_f##op(); \
1785 if (isfloat) { \
1786 gen_op_frsp(); \
1787 } \
a5e26afa 1788 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1789 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1790}
7c58044c
JM		 1791#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1792_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1793_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1794
7c58044c
JM		 1795#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1796GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1797{ \
76a66253 1798 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1799 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1800 return; \
1801 } \
a5e26afa
AJ		 1802 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1803 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
7c58044c 1804 gen_reset_fpstatus(); \
4ecc3190
FB		 1805 gen_op_f##op(); \
1806 if (isfloat) { \
1807 gen_op_frsp(); \
1808 } \
a5e26afa 1809 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1810 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1811}
7c58044c
JM		 1812#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1813_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1814_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1815
7c58044c 1816#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 1817GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 1818{ \
76a66253 1819 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1820 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1821 return; \
1822 } \
a5e26afa 1823 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1824 gen_reset_fpstatus(); \
9a64fbe4 1825 gen_op_f##name(); \
a5e26afa 1826 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1827 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1828}
1829
7c58044c 1830#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 1831GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 1832{ \
76a66253 1833 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1834 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1835 return; \
1836 } \
a5e26afa 1837 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1838 gen_reset_fpstatus(); \
9a64fbe4 1839 gen_op_f##name(); \
a5e26afa 1840 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1841 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1842}
1843
9a64fbe4 1844/* fadd - fadds */
7c58044c 1845GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1846/* fdiv - fdivs */
7c58044c 1847GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1848/* fmul - fmuls */
7c58044c 1849GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 1850
d7e4b87e 1851/* fre */
7c58044c 1852GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 1853
a750fc0b 1854/* fres */
7c58044c 1855GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 1856
a750fc0b 1857/* frsqrte */
7c58044c
JM		 1858GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1859
1860/* frsqrtes */
1861static always_inline void gen_op_frsqrtes (void)
1862{
1863 gen_op_frsqrte();
1864 gen_op_frsp();
1865}
1b413d55 1866GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 1867
a750fc0b 1868/* fsel */
7c58044c 1869_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 1870/* fsub - fsubs */
7c58044c 1871GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 1872/* Optional: */
1873/* fsqrt */
a750fc0b 1874GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 1875{
76a66253 1876 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1877 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 1878 return;
1879 }
a5e26afa 1880 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1881 gen_reset_fpstatus();
c7d344af 1882 gen_op_fsqrt();
a5e26afa 1883 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1884 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 1885}
79aceca5 1886
a750fc0b 1887GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 1888{
76a66253 1889 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1890 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1891 return;
1892 }
a5e26afa 1893 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1894 gen_reset_fpstatus();
4ecc3190
FB		 1895 gen_op_fsqrt();
1896 gen_op_frsp();
a5e26afa 1897 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1898 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 1899}
1900
1901/*** Floating-Point multiply-and-add ***/
4ecc3190 1902/* fmadd - fmadds */
7c58044c 1903GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 1904/* fmsub - fmsubs */
7c58044c 1905GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 1906/* fnmadd - fnmadds */
7c58044c 1907GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 1908/* fnmsub - fnmsubs */
7c58044c 1909GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 1910
1911/*** Floating-Point round & convert ***/
1912/* fctiw */
7c58044c 1913GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 1914/* fctiwz */
7c58044c 1915GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 1916/* frsp */
7c58044c 1917GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 1918#if defined(TARGET_PPC64)
1919/* fcfid */
7c58044c 1920GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 1921/* fctid */
7c58044c 1922GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 1923/* fctidz */
7c58044c 1924GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 1925#endif
79aceca5 1926
d7e4b87e 1927/* frin */
7c58044c 1928GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 1929/* friz */
7c58044c 1930GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 1931/* frip */
7c58044c 1932GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 1933/* frim */
7c58044c 1934GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 1935
79aceca5
FB		 1936/*** Floating-Point compare ***/
1937/* fcmpo */
76a66253 1938GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 1939{
76a66253 1940 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1941 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1942 return;
1943 }
a5e26afa
AJ		 1944 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
1945 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1946 gen_reset_fpstatus();
9a64fbe4 1947 gen_op_fcmpo();
47e4661c 1948 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
7c58044c 1949 gen_op_float_check_status();
79aceca5
FB		 1950}
1951
1952/* fcmpu */
76a66253 1953GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 1954{
76a66253 1955 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1956 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1957 return;
1958 }
a5e26afa
AJ		 1959 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
1960 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1961 gen_reset_fpstatus();
9a64fbe4 1962 gen_op_fcmpu();
47e4661c 1963 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
7c58044c 1964 gen_op_float_check_status();
79aceca5
FB		 1965}
1966
9a64fbe4
FB		 1967/*** Floating-point move ***/
1968/* fabs */
7c58044c
JM		 1969/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1970GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 1971
1972/* fmr - fmr. */
7c58044c 1973/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 1974GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1975{
76a66253 1976 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1977 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1978 return;
1979 }
a5e26afa
AJ		 1980 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
1981 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1982 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 1983}
1984
1985/* fnabs */
7c58044c
JM		 1986/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1987GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 1988/* fneg */
7c58044c
JM		 1989/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1990GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 1991
79aceca5
FB		 1992/*** Floating-Point status & ctrl register ***/
1993/* mcrfs */
1994GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1995{
7c58044c
JM		 1996 int bfa;
1997
76a66253 1998 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1999 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2000 return;
2001 }
7c58044c
JM		 2002 gen_optimize_fprf();
2003 bfa = 4 * (7 - crfS(ctx->opcode));
2004 gen_op_load_fpscr_T0(bfa);
47e4661c 2005 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
7c58044c 2006 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 2007}
2008
2009/* mffs */
2010GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2011{
76a66253 2012 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2013 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2014 return;
2015 }
7c58044c
JM		 2016 gen_optimize_fprf();
2017 gen_reset_fpstatus();
2018 gen_op_load_fpscr_FT0();
a5e26afa 2019 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2020 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2021}
2022
2023/* mtfsb0 */
2024GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2025{
fb0eaffc 2026 uint8_t crb;
3b46e624 2027
76a66253 2028 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2029 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2030 return;
2031 }
7c58044c
JM		 2032 crb = 32 - (crbD(ctx->opcode) >> 2);
2033 gen_optimize_fprf();
2034 gen_reset_fpstatus();
2035 if (likely(crb != 30 && crb != 29))
2036 gen_op_fpscr_resetbit(~(1 << crb));
2037 if (unlikely(Rc(ctx->opcode) != 0)) {
2038 gen_op_load_fpcc();
2039 gen_op_set_Rc0();
2040 }
79aceca5
FB		 2041}
2042
2043/* mtfsb1 */
2044GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2045{
fb0eaffc 2046 uint8_t crb;
3b46e624 2047
76a66253 2048 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2049 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2050 return;
2051 }
7c58044c
JM		 2052 crb = 32 - (crbD(ctx->opcode) >> 2);
2053 gen_optimize_fprf();
2054 gen_reset_fpstatus();
2055 /* XXX: we pretend we can only do IEEE floating-point computations */
2056 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2057 gen_op_fpscr_setbit(crb);
2058 if (unlikely(Rc(ctx->opcode) != 0)) {
2059 gen_op_load_fpcc();
2060 gen_op_set_Rc0();
2061 }
2062 /* We can raise a differed exception */
2063 gen_op_float_check_status();
79aceca5
FB		 2064}
2065
2066/* mtfsf */
2067GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2068{
76a66253 2069 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2070 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2071 return;
2072 }
7c58044c 2073 gen_optimize_fprf();
a5e26afa 2074 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2075 gen_reset_fpstatus();
28b6751f 2076 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c
JM		 2077 if (unlikely(Rc(ctx->opcode) != 0)) {
2078 gen_op_load_fpcc();
2079 gen_op_set_Rc0();
2080 }
2081 /* We can raise a differed exception */
2082 gen_op_float_check_status();
79aceca5
FB		 2083}
2084
2085/* mtfsfi */
2086GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2087{
7c58044c
JM		 2088 int bf, sh;
2089
76a66253 2090 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2091 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2092 return;
2093 }
7c58044c
JM		 2094 bf = crbD(ctx->opcode) >> 2;
2095 sh = 7 - bf;
2096 gen_optimize_fprf();
489251fa 2097 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
7c58044c
JM		 2098 gen_reset_fpstatus();
2099 gen_op_store_fpscr(1 << sh);
2100 if (unlikely(Rc(ctx->opcode) != 0)) {
2101 gen_op_load_fpcc();
2102 gen_op_set_Rc0();
2103 }
2104 /* We can raise a differed exception */
2105 gen_op_float_check_status();
79aceca5
FB		 2106}
2107
76a66253
JM		 2108/*** Addressing modes ***/
2109/* Register indirect with immediate index : EA = (rA|0) + SIMM */
b068d6a7
JM		 2110static always_inline void gen_addr_imm_index (DisasContext *ctx,
2111 target_long maskl)
76a66253
JM		 2112{
2113 target_long simm = SIMM(ctx->opcode);
2114
be147d08 2115 simm &= ~maskl;
76a66253 2116 if (rA(ctx->opcode) == 0) {
02f4f6c2 2117 tcg_gen_movi_tl(cpu_T[0], simm);
76a66253 2118 } else {
f78fb44e 2119 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 2120 if (likely(simm != 0))
39dd32ee 2121 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
76a66253 2122 }
a496775f 2123#ifdef DEBUG_MEMORY_ACCESSES
6676f424 2124 gen_op_print_mem_EA();
a496775f 2125#endif
76a66253
JM		 2126}
2127
b068d6a7 2128static always_inline void gen_addr_reg_index (DisasContext *ctx)
76a66253
JM		 2129{
2130 if (rA(ctx->opcode) == 0) {
f78fb44e 2131 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 2132 } else {
f78fb44e
AJ		 2133 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
2134 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
39dd32ee 2135 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
76a66253 2136 }
a496775f 2137#ifdef DEBUG_MEMORY_ACCESSES
6676f424 2138 gen_op_print_mem_EA();
a496775f 2139#endif
76a66253
JM		 2140}
2141
b068d6a7 2142static always_inline void gen_addr_register (DisasContext *ctx)
76a66253
JM		 2143{
2144 if (rA(ctx->opcode) == 0) {
86c581dc 2145 tcg_gen_movi_tl(cpu_T[0], 0);
76a66253 2146 } else {
f78fb44e 2147 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 2148 }
a496775f 2149#ifdef DEBUG_MEMORY_ACCESSES
6676f424 2150 gen_op_print_mem_EA();
a496775f 2151#endif
76a66253
JM		 2152}
2153
7863667f
JM		 2154#if defined(TARGET_PPC64)
2155#define _GEN_MEM_FUNCS(name, mode) \
2156 &gen_op_##name##_##mode, \
2157 &gen_op_##name##_le_##mode, \
2158 &gen_op_##name##_64_##mode, \
2159 &gen_op_##name##_le_64_##mode
2160#else
2161#define _GEN_MEM_FUNCS(name, mode) \
2162 &gen_op_##name##_##mode, \
2163 &gen_op_##name##_le_##mode
2164#endif
9a64fbe4 2165#if defined(CONFIG_USER_ONLY)
d9bce9d9 2166#if defined(TARGET_PPC64)
7863667f 2167#define NB_MEM_FUNCS 4
d9bce9d9 2168#else
7863667f 2169#define NB_MEM_FUNCS 2
d9bce9d9 2170#endif
7863667f
JM		 2171#define GEN_MEM_FUNCS(name) \
2172 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2173#else
d9bce9d9 2174#if defined(TARGET_PPC64)
7863667f 2175#define NB_MEM_FUNCS 12
2857068e 2176#else
7863667f 2177#define NB_MEM_FUNCS 6
2857068e 2178#endif
7863667f
JM		 2179#define GEN_MEM_FUNCS(name) \
2180 _GEN_MEM_FUNCS(name, user), \
2181 _GEN_MEM_FUNCS(name, kernel), \
2182 _GEN_MEM_FUNCS(name, hypv)
2183#endif
2184
2185/*** Integer load ***/
2186#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
111bfab3 2187/* Byte access routine are endian safe */
7863667f
JM		 2188#define gen_op_lbz_le_raw gen_op_lbz_raw
2189#define gen_op_lbz_le_user gen_op_lbz_user
2190#define gen_op_lbz_le_kernel gen_op_lbz_kernel
2191#define gen_op_lbz_le_hypv gen_op_lbz_hypv
2192#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2857068e 2193#define gen_op_lbz_le_64_user gen_op_lbz_64_user
d9bce9d9 2194#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
7863667f
JM		 2195#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2196#define gen_op_stb_le_raw gen_op_stb_raw
2197#define gen_op_stb_le_user gen_op_stb_user
2198#define gen_op_stb_le_kernel gen_op_stb_kernel
2199#define gen_op_stb_le_hypv gen_op_stb_hypv
2200#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2201#define gen_op_stb_le_64_user gen_op_stb_64_user
2202#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2203#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
d9bce9d9 2204#define OP_LD_TABLE(width) \
7863667f
JM		 2205static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2206 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2207};
2208#define OP_ST_TABLE(width) \
7863667f
JM		 2209static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2210 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2211};
9a64fbe4 2212
d9bce9d9
JM		 2213#define GEN_LD(width, opc, type) \
2214GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2215{ \
9d53c753 2216 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2217 op_ldst(l##width); \
f78fb44e 2218 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
79aceca5
FB		 2219}
2220
d9bce9d9
JM		 2221#define GEN_LDU(width, opc, type) \
2222GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2223{ \
76a66253
JM		 2224 if (unlikely(rA(ctx->opcode) == 0 || \
2225 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2226 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2227 return; \
9a64fbe4 2228 } \
9d53c753 2229 if (type == PPC_64B) \
be147d08 2230 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2231 else \
2232 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2233 op_ldst(l##width); \
f78fb44e
AJ		 2234 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
2235 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2236}
2237
d9bce9d9
JM		 2238#define GEN_LDUX(width, opc2, opc3, type) \
2239GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2240{ \
76a66253
JM		 2241 if (unlikely(rA(ctx->opcode) == 0 || \
2242 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2243 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2244 return; \
9a64fbe4 2245 } \
76a66253 2246 gen_addr_reg_index(ctx); \
9a64fbe4 2247 op_ldst(l##width); \
f78fb44e
AJ		 2248 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
2249 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2250}
2251
d9bce9d9
JM		 2252#define GEN_LDX(width, opc2, opc3, type) \
2253GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2254{ \
76a66253 2255 gen_addr_reg_index(ctx); \
9a64fbe4 2256 op_ldst(l##width); \
f78fb44e 2257 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
79aceca5
FB		 2258}
2259
d9bce9d9 2260#define GEN_LDS(width, op, type) \
9a64fbe4 2261OP_LD_TABLE(width); \
d9bce9d9
JM		 2262GEN_LD(width, op | 0x20, type); \
2263GEN_LDU(width, op | 0x21, type); \
2264GEN_LDUX(width, 0x17, op | 0x01, type); \
2265GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2266
2267/* lbz lbzu lbzux lbzx */
d9bce9d9 2268GEN_LDS(bz, 0x02, PPC_INTEGER);
79aceca5 2269/* lha lhau lhaux lhax */
d9bce9d9 2270GEN_LDS(ha, 0x0A, PPC_INTEGER);
79aceca5 2271/* lhz lhzu lhzux lhzx */
d9bce9d9 2272GEN_LDS(hz, 0x08, PPC_INTEGER);
79aceca5 2273/* lwz lwzu lwzux lwzx */
d9bce9d9
JM		 2274GEN_LDS(wz, 0x00, PPC_INTEGER);
2275#if defined(TARGET_PPC64)
2276OP_LD_TABLE(wa);
2277OP_LD_TABLE(d);
2278/* lwaux */
2279GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2280/* lwax */
2281GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2282/* ldux */
2283GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2284/* ldx */
2285GEN_LDX(d, 0x15, 0x00, PPC_64B);
2286GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2287{
2288 if (Rc(ctx->opcode)) {
2289 if (unlikely(rA(ctx->opcode) == 0 ||
2290 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2291 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2292 return;
2293 }
2294 }
be147d08 2295 gen_addr_imm_index(ctx, 0x03);
d9bce9d9
JM		 2296 if (ctx->opcode & 0x02) {
2297 /* lwa (lwau is undefined) */
2298 op_ldst(lwa);
2299 } else {
2300 /* ld - ldu */
2301 op_ldst(ld);
2302 }
f78fb44e 2303 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
d9bce9d9 2304 if (Rc(ctx->opcode))
f78fb44e 2305 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9 2306}
be147d08
JM		 2307/* lq */
2308GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2309{
2310#if defined(CONFIG_USER_ONLY)
2311 GEN_EXCP_PRIVOPC(ctx);
2312#else
2313 int ra, rd;
2314
2315 /* Restore CPU state */
2316 if (unlikely(ctx->supervisor == 0)) {
2317 GEN_EXCP_PRIVOPC(ctx);
2318 return;
2319 }
2320 ra = rA(ctx->opcode);
2321 rd = rD(ctx->opcode);
2322 if (unlikely((rd & 1) || rd == ra)) {
2323 GEN_EXCP_INVAL(ctx);
2324 return;
2325 }
2326 if (unlikely(ctx->mem_idx & 1)) {
2327 /* Little-endian mode is not handled */
2328 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2329 return;
2330 }
2331 gen_addr_imm_index(ctx, 0x0F);
2332 op_ldst(ld);
f78fb44e 2333 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]);
39dd32ee 2334 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8);
be147d08 2335 op_ldst(ld);
f78fb44e 2336 tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]);
be147d08
JM		 2337#endif
2338}
d9bce9d9 2339#endif
79aceca5
FB		 2340
2341/*** Integer store ***/
d9bce9d9
JM		 2342#define GEN_ST(width, opc, type) \
2343GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2344{ \
9d53c753 2345 gen_addr_imm_index(ctx, 0); \
f78fb44e 2346 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
9a64fbe4 2347 op_ldst(st##width); \
79aceca5
FB		 2348}
2349
d9bce9d9
JM		 2350#define GEN_STU(width, opc, type) \
2351GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2352{ \
76a66253 2353 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2354 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2355 return; \
9a64fbe4 2356 } \
9d53c753 2357 if (type == PPC_64B) \
be147d08 2358 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2359 else \
2360 gen_addr_imm_index(ctx, 0); \
f78fb44e 2361 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
9a64fbe4 2362 op_ldst(st##width); \
f78fb44e 2363 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2364}
2365
d9bce9d9
JM		 2366#define GEN_STUX(width, opc2, opc3, type) \
2367GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2368{ \
76a66253 2369 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2370 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2371 return; \
9a64fbe4 2372 } \
76a66253 2373 gen_addr_reg_index(ctx); \
f78fb44e 2374 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
9a64fbe4 2375 op_ldst(st##width); \
f78fb44e 2376 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2377}
2378
d9bce9d9
JM		 2379#define GEN_STX(width, opc2, opc3, type) \
2380GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2381{ \
76a66253 2382 gen_addr_reg_index(ctx); \
f78fb44e 2383 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
9a64fbe4 2384 op_ldst(st##width); \
79aceca5
FB		 2385}
2386
d9bce9d9 2387#define GEN_STS(width, op, type) \
9a64fbe4 2388OP_ST_TABLE(width); \
d9bce9d9
JM		 2389GEN_ST(width, op | 0x20, type); \
2390GEN_STU(width, op | 0x21, type); \
2391GEN_STUX(width, 0x17, op | 0x01, type); \
2392GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2393
2394/* stb stbu stbux stbx */
d9bce9d9 2395GEN_STS(b, 0x06, PPC_INTEGER);
79aceca5 2396/* sth sthu sthux sthx */
d9bce9d9 2397GEN_STS(h, 0x0C, PPC_INTEGER);
79aceca5 2398/* stw stwu stwux stwx */
d9bce9d9
JM		 2399GEN_STS(w, 0x04, PPC_INTEGER);
2400#if defined(TARGET_PPC64)
2401OP_ST_TABLE(d);
426613db
JM		 2402GEN_STUX(d, 0x15, 0x05, PPC_64B);
2403GEN_STX(d, 0x15, 0x04, PPC_64B);
be147d08 2404GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2405{
be147d08
JM		 2406 int rs;
2407
2408 rs = rS(ctx->opcode);
2409 if ((ctx->opcode & 0x3) == 0x2) {
2410#if defined(CONFIG_USER_ONLY)
2411 GEN_EXCP_PRIVOPC(ctx);
2412#else
2413 /* stq */
2414 if (unlikely(ctx->supervisor == 0)) {
2415 GEN_EXCP_PRIVOPC(ctx);
2416 return;
2417 }
2418 if (unlikely(rs & 1)) {
e1833e1f 2419 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2420 return;
2421 }
be147d08
JM		 2422 if (unlikely(ctx->mem_idx & 1)) {
2423 /* Little-endian mode is not handled */
2424 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2425 return;
2426 }
2427 gen_addr_imm_index(ctx, 0x03);
f78fb44e 2428 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
be147d08 2429 op_ldst(std);
39dd32ee 2430 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8);
f78fb44e 2431 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]);
be147d08
JM		 2432 op_ldst(std);
2433#endif
2434 } else {
2435 /* std / stdu */
2436 if (Rc(ctx->opcode)) {
2437 if (unlikely(rA(ctx->opcode) == 0)) {
2438 GEN_EXCP_INVAL(ctx);
2439 return;
2440 }
2441 }
2442 gen_addr_imm_index(ctx, 0x03);
f78fb44e 2443 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
be147d08
JM		 2444 op_ldst(std);
2445 if (Rc(ctx->opcode))
f78fb44e 2446 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9 2447 }
d9bce9d9
JM		 2448}
2449#endif
79aceca5
FB		 2450/*** Integer load and store with byte reverse ***/
2451/* lhbrx */
9a64fbe4 2452OP_LD_TABLE(hbr);
d9bce9d9 2453GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
79aceca5 2454/* lwbrx */
9a64fbe4 2455OP_LD_TABLE(wbr);
d9bce9d9 2456GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
79aceca5 2457/* sthbrx */
9a64fbe4 2458OP_ST_TABLE(hbr);
d9bce9d9 2459GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
79aceca5 2460/* stwbrx */
9a64fbe4 2461OP_ST_TABLE(wbr);
d9bce9d9 2462GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2463
2464/*** Integer load and store multiple ***/
111bfab3 2465#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 2466static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2467 GEN_MEM_FUNCS(lmw),
d9bce9d9 2468};
7863667f
JM		 2469static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2470 GEN_MEM_FUNCS(stmw),
d9bce9d9 2471};
9a64fbe4 2472
79aceca5
FB		 2473/* lmw */
2474GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2475{
76a66253 2476 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2477 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2478 gen_addr_imm_index(ctx, 0);
9a64fbe4 2479 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2480}
2481
2482/* stmw */
2483GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2484{
76a66253 2485 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2486 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2487 gen_addr_imm_index(ctx, 0);
9a64fbe4 2488 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2489}
2490
2491/*** Integer load and store strings ***/
9a64fbe4
FB		 2492#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2493#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 2494/* string load & stores are by definition endian-safe */
2495#define gen_op_lswi_le_raw gen_op_lswi_raw
2496#define gen_op_lswi_le_user gen_op_lswi_user
2497#define gen_op_lswi_le_kernel gen_op_lswi_kernel
2498#define gen_op_lswi_le_hypv gen_op_lswi_hypv
2499#define gen_op_lswi_le_64_raw gen_op_lswi_raw
2500#define gen_op_lswi_le_64_user gen_op_lswi_user
2501#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2502#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 2503static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2504 GEN_MEM_FUNCS(lswi),
d9bce9d9 2505};
e7c24003
JM		 2506#define gen_op_lswx_le_raw gen_op_lswx_raw
2507#define gen_op_lswx_le_user gen_op_lswx_user
2508#define gen_op_lswx_le_kernel gen_op_lswx_kernel
2509#define gen_op_lswx_le_hypv gen_op_lswx_hypv
2510#define gen_op_lswx_le_64_raw gen_op_lswx_raw
2511#define gen_op_lswx_le_64_user gen_op_lswx_user
2512#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2513#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 2514static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2515 GEN_MEM_FUNCS(lswx),
d9bce9d9 2516};
e7c24003
JM		 2517#define gen_op_stsw_le_raw gen_op_stsw_raw
2518#define gen_op_stsw_le_user gen_op_stsw_user
2519#define gen_op_stsw_le_kernel gen_op_stsw_kernel
2520#define gen_op_stsw_le_hypv gen_op_stsw_hypv
2521#define gen_op_stsw_le_64_raw gen_op_stsw_raw
2522#define gen_op_stsw_le_64_user gen_op_stsw_user
2523#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2524#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 2525static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2526 GEN_MEM_FUNCS(stsw),
9a64fbe4 2527};
9a64fbe4 2528
79aceca5 2529/* lswi */
3fc6c082 2530/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2531 * rA is in the range of registers to be loaded.
2532 * In an other hand, IBM says this is valid, but rA won't be loaded.
2533 * For now, I'll follow the spec...
2534 */
05332d70 2535GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 2536{
2537 int nb = NB(ctx->opcode);
2538 int start = rD(ctx->opcode);
9a64fbe4 2539 int ra = rA(ctx->opcode);
79aceca5
FB		 2540 int nr;
2541
2542 if (nb == 0)
2543 nb = 32;
2544 nr = nb / 4;
76a66253
JM		 2545 if (unlikely(((start + nr) > 32 &&
2546 start <= ra && (start + nr - 32) > ra) ||
2547 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 2548 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2549 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2550 return;
297d8e62 2551 }
8dd4983c 2552 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2553 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2554 gen_addr_register(ctx);
86c581dc 2555 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 2556 op_ldsts(lswi, start);
79aceca5
FB		 2557}
2558
2559/* lswx */
05332d70 2560GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 2561{
9a64fbe4
FB		 2562 int ra = rA(ctx->opcode);
2563 int rb = rB(ctx->opcode);
2564
76a66253 2565 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2566 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2567 gen_addr_reg_index(ctx);
9a64fbe4 2568 if (ra == 0) {
9a64fbe4 2569 ra = rb;
79aceca5 2570 }
9a64fbe4
FB		 2571 gen_op_load_xer_bc();
2572 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 2573}
2574
2575/* stswi */
05332d70 2576GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 2577{
4b3686fa
FB		 2578 int nb = NB(ctx->opcode);
2579
76a66253 2580 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2581 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2582 gen_addr_register(ctx);
4b3686fa
FB		 2583 if (nb == 0)
2584 nb = 32;
86c581dc 2585 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 2586 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2587}
2588
2589/* stswx */
05332d70 2590GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 2591{
8dd4983c 2592 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 2593 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 2594 gen_addr_reg_index(ctx);
2595 gen_op_load_xer_bc();
9a64fbe4 2596 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2597}
2598
2599/*** Memory synchronisation ***/
2600/* eieio */
0db1b20e 2601GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 2602{
79aceca5
FB		 2603}
2604
2605/* isync */
0db1b20e 2606GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 2607{
e1833e1f 2608 GEN_STOP(ctx);
79aceca5
FB		 2609}
2610
111bfab3
FB		 2611#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2612#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 2613static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2614 GEN_MEM_FUNCS(lwarx),
111bfab3 2615};
7863667f
JM		 2616static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2617 GEN_MEM_FUNCS(stwcx),
985a19d6 2618};
9a64fbe4 2619
111bfab3 2620/* lwarx */
76a66253 2621GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 2622{
30032c94
JM		 2623 /* NIP cannot be restored if the memory exception comes from an helper */
2624 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2625 gen_addr_reg_index(ctx);
985a19d6 2626 op_lwarx();
f78fb44e 2627 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 2628}
2629
2630/* stwcx. */
c7697e1f 2631GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 2632{
30032c94
JM		 2633 /* NIP cannot be restored if the memory exception comes from an helper */
2634 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2635 gen_addr_reg_index(ctx);
f78fb44e 2636 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 2637 op_stwcx();
79aceca5
FB		 2638}
2639
426613db
JM		 2640#if defined(TARGET_PPC64)
2641#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2642#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 2643static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2644 GEN_MEM_FUNCS(ldarx),
426613db 2645};
7863667f
JM		 2646static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2647 GEN_MEM_FUNCS(stdcx),
426613db 2648};
426613db
JM		 2649
2650/* ldarx */
a750fc0b 2651GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 2652{
30032c94
JM		 2653 /* NIP cannot be restored if the memory exception comes from an helper */
2654 gen_update_nip(ctx, ctx->nip - 4);
426613db
JM		 2655 gen_addr_reg_index(ctx);
2656 op_ldarx();
f78fb44e 2657 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 2658}
2659
2660/* stdcx. */
c7697e1f 2661GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 2662{
30032c94
JM		 2663 /* NIP cannot be restored if the memory exception comes from an helper */
2664 gen_update_nip(ctx, ctx->nip - 4);
426613db 2665 gen_addr_reg_index(ctx);
f78fb44e 2666 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 2667 op_stdcx();
2668}
2669#endif /* defined(TARGET_PPC64) */
2670
79aceca5 2671/* sync */
a902d886 2672GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 2673{
79aceca5
FB		 2674}
2675
0db1b20e
JM		 2676/* wait */
2677GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2678{
2679 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 2680 gen_op_wait();
2681 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 2682}
2683
79aceca5 2684/*** Floating-point load ***/
477023a6
JM		 2685#define GEN_LDF(width, opc, type) \
2686GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2687{ \
76a66253 2688 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2689 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2690 return; \
2691 } \
9d53c753 2692 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2693 op_ldst(l##width); \
a5e26afa 2694 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 2695}
2696
477023a6
JM		 2697#define GEN_LDUF(width, opc, type) \
2698GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2699{ \
76a66253 2700 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2701 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2702 return; \
2703 } \
76a66253 2704 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2705 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2706 return; \
9a64fbe4 2707 } \
9d53c753 2708 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2709 op_ldst(l##width); \
a5e26afa 2710 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 2711 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2712}
2713
477023a6
JM		 2714#define GEN_LDUXF(width, opc, type) \
2715GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2716{ \
76a66253 2717 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2718 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2719 return; \
2720 } \
76a66253 2721 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2722 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2723 return; \
9a64fbe4 2724 } \
76a66253 2725 gen_addr_reg_index(ctx); \
9a64fbe4 2726 op_ldst(l##width); \
a5e26afa 2727 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 2728 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2729}
2730
477023a6
JM		 2731#define GEN_LDXF(width, opc2, opc3, type) \
2732GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2733{ \
76a66253 2734 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2735 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2736 return; \
2737 } \
76a66253 2738 gen_addr_reg_index(ctx); \
9a64fbe4 2739 op_ldst(l##width); \
a5e26afa 2740 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 2741}
2742
477023a6 2743#define GEN_LDFS(width, op, type) \
9a64fbe4 2744OP_LD_TABLE(width); \
477023a6
JM		 2745GEN_LDF(width, op | 0x20, type); \
2746GEN_LDUF(width, op | 0x21, type); \
2747GEN_LDUXF(width, op | 0x01, type); \
2748GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 2749
2750/* lfd lfdu lfdux lfdx */
477023a6 2751GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 2752/* lfs lfsu lfsux lfsx */
477023a6 2753GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 2754
2755/*** Floating-point store ***/
477023a6
JM		 2756#define GEN_STF(width, opc, type) \
2757GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2758{ \
76a66253 2759 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2760 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2761 return; \
2762 } \
9d53c753 2763 gen_addr_imm_index(ctx, 0); \
a5e26afa 2764 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 2765 op_ldst(st##width); \
79aceca5
FB		 2766}
2767
477023a6
JM		 2768#define GEN_STUF(width, opc, type) \
2769GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2770{ \
76a66253 2771 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2772 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2773 return; \
2774 } \
76a66253 2775 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2776 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2777 return; \
9a64fbe4 2778 } \
9d53c753 2779 gen_addr_imm_index(ctx, 0); \
a5e26afa 2780 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 2781 op_ldst(st##width); \
f78fb44e 2782 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2783}
2784
477023a6
JM		 2785#define GEN_STUXF(width, opc, type) \
2786GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2787{ \
76a66253 2788 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2789 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2790 return; \
2791 } \
76a66253 2792 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2793 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2794 return; \
9a64fbe4 2795 } \
76a66253 2796 gen_addr_reg_index(ctx); \
a5e26afa 2797 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 2798 op_ldst(st##width); \
f78fb44e 2799 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2800}
2801
477023a6
JM		 2802#define GEN_STXF(width, opc2, opc3, type) \
2803GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2804{ \
76a66253 2805 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2806 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2807 return; \
2808 } \
76a66253 2809 gen_addr_reg_index(ctx); \
a5e26afa 2810 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 2811 op_ldst(st##width); \
79aceca5
FB		 2812}
2813
477023a6 2814#define GEN_STFS(width, op, type) \
9a64fbe4 2815OP_ST_TABLE(width); \
477023a6
JM		 2816GEN_STF(width, op | 0x20, type); \
2817GEN_STUF(width, op | 0x21, type); \
2818GEN_STUXF(width, op | 0x01, type); \
2819GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 2820
2821/* stfd stfdu stfdux stfdx */
477023a6 2822GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 2823/* stfs stfsu stfsux stfsx */
477023a6 2824GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 2825
2826/* Optional: */
2827/* stfiwx */
5b8105fa
JM		 2828OP_ST_TABLE(fiw);
2829GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 2830
2831/*** Branch ***/
b068d6a7
JM		 2832static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2833 target_ulong dest)
c1942362
FB		 2834{
2835 TranslationBlock *tb;
2836 tb = ctx->tb;
57fec1fe 2837 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 2838 likely(!ctx->singlestep_enabled)) {
57fec1fe 2839 tcg_gen_goto_tb(n);
02f4f6c2 2840 tcg_gen_movi_tl(cpu_T[1], dest);
d9bce9d9
JM		 2841#if defined(TARGET_PPC64)
2842 if (ctx->sf_mode)
bd568f18 2843 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 2844 else
2845#endif
bd568f18 2846 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
57fec1fe 2847 tcg_gen_exit_tb((long)tb + n);
c1942362 2848 } else {
02f4f6c2 2849 tcg_gen_movi_tl(cpu_T[1], dest);
d9bce9d9
JM		 2850#if defined(TARGET_PPC64)
2851 if (ctx->sf_mode)
bd568f18 2852 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 2853 else
2854#endif
bd568f18 2855 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
8cbcb4fa
AJ		 2856 if (unlikely(ctx->singlestep_enabled)) {
2857 if ((ctx->singlestep_enabled &
2858 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
2859 ctx->exception == POWERPC_EXCP_BRANCH) {
2860 target_ulong tmp = ctx->nip;
2861 ctx->nip = dest;
2862 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
2863 ctx->nip = tmp;
2864 }
2865 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
2866 gen_update_nip(ctx, dest);
2867 gen_op_debug();
2868 }
2869 }
57fec1fe 2870 tcg_gen_exit_tb(0);
c1942362 2871 }
c53be334
FB		 2872}
2873
b068d6a7 2874static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 2875{
2876#if defined(TARGET_PPC64)
2877 if (ctx->sf_mode != 0 && (nip >> 32))
2878 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2879 else
2880#endif
2881 gen_op_setlr(ctx->nip);
2882}
2883
79aceca5
FB		 2884/* b ba bl bla */
2885GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2886{
76a66253 2887 target_ulong li, target;
38a64f9d 2888
8cbcb4fa 2889 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 2890 /* sign extend LI */
76a66253 2891#if defined(TARGET_PPC64)
d9bce9d9
JM		 2892 if (ctx->sf_mode)
2893 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
2894 else
76a66253 2895#endif
d9bce9d9 2896 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 2897 if (likely(AA(ctx->opcode) == 0))
046d6672 2898 target = ctx->nip + li - 4;
79aceca5 2899 else
9a64fbe4 2900 target = li;
d9bce9d9 2901#if defined(TARGET_PPC64)
e1833e1f
JM		 2902 if (!ctx->sf_mode)
2903 target = (uint32_t)target;
d9bce9d9 2904#endif
e1833e1f
JM		 2905 if (LK(ctx->opcode))
2906 gen_setlr(ctx, ctx->nip);
c1942362 2907 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 2908}
2909
e98a6e40
FB		 2910#define BCOND_IM 0
2911#define BCOND_LR 1
2912#define BCOND_CTR 2
2913
b068d6a7 2914static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 2915{
76a66253
JM		 2916 target_ulong target = 0;
2917 target_ulong li;
d9bce9d9
JM		 2918 uint32_t bo = BO(ctx->opcode);
2919 uint32_t bi = BI(ctx->opcode);
2920 uint32_t mask;
e98a6e40 2921
8cbcb4fa 2922 ctx->exception = POWERPC_EXCP_BRANCH;
e98a6e40 2923 if ((bo & 0x4) == 0)
d9bce9d9 2924 gen_op_dec_ctr();
e98a6e40
FB		 2925 switch(type) {
2926 case BCOND_IM:
76a66253
JM		 2927 li = (target_long)((int16_t)(BD(ctx->opcode)));
2928 if (likely(AA(ctx->opcode) == 0)) {
046d6672 2929 target = ctx->nip + li - 4;
e98a6e40
FB		 2930 } else {
2931 target = li;
2932 }
e1833e1f
JM		 2933#if defined(TARGET_PPC64)
2934 if (!ctx->sf_mode)
2935 target = (uint32_t)target;
2936#endif
e98a6e40
FB		 2937 break;
2938 case BCOND_CTR:
2939 gen_op_movl_T1_ctr();
2940 break;
2941 default:
2942 case BCOND_LR:
2943 gen_op_movl_T1_lr();
2944 break;
2945 }
e1833e1f
JM		 2946 if (LK(ctx->opcode))
2947 gen_setlr(ctx, ctx->nip);
e98a6e40 2948 if (bo & 0x10) {
d9bce9d9
JM		 2949 /* No CR condition */
2950 switch (bo & 0x6) {
2951 case 0:
2952#if defined(TARGET_PPC64)
2953 if (ctx->sf_mode)
2954 gen_op_test_ctr_64();
2955 else
2956#endif
2957 gen_op_test_ctr();
2958 break;
2959 case 2:
2960#if defined(TARGET_PPC64)
2961 if (ctx->sf_mode)
2962 gen_op_test_ctrz_64();
2963 else
2964#endif
2965 gen_op_test_ctrz();
e98a6e40 2966 break;
e98a6e40 2967 default:
d9bce9d9
JM		 2968 case 4:
2969 case 6:
e98a6e40 2970 if (type == BCOND_IM) {
c1942362 2971 gen_goto_tb(ctx, 0, target);
8cbcb4fa 2972 return;
e98a6e40 2973 } else {
d9bce9d9
JM		 2974#if defined(TARGET_PPC64)
2975 if (ctx->sf_mode)
bd568f18 2976 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 2977 else
2978#endif
bd568f18 2979 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
056b05f8 2980 goto no_test;
e98a6e40 2981 }
056b05f8 2982 break;
e98a6e40 2983 }
d9bce9d9
JM		 2984 } else {
2985 mask = 1 << (3 - (bi & 0x03));
47e4661c 2986 tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]);
d9bce9d9
JM		 2987 if (bo & 0x8) {
2988 switch (bo & 0x6) {
2989 case 0:
2990#if defined(TARGET_PPC64)
2991 if (ctx->sf_mode)
2992 gen_op_test_ctr_true_64(mask);
2993 else
2994#endif
2995 gen_op_test_ctr_true(mask);
2996 break;
2997 case 2:
2998#if defined(TARGET_PPC64)
2999 if (ctx->sf_mode)
3000 gen_op_test_ctrz_true_64(mask);
3001 else
3002#endif
3003 gen_op_test_ctrz_true(mask);
3004 break;
3005 default:
3006 case 4:
3007 case 6:
e98a6e40 3008 gen_op_test_true(mask);
d9bce9d9
JM		 3009 break;
3010 }
3011 } else {
3012 switch (bo & 0x6) {
3013 case 0:
3014#if defined(TARGET_PPC64)
3015 if (ctx->sf_mode)
3016 gen_op_test_ctr_false_64(mask);
3017 else
3018#endif
3019 gen_op_test_ctr_false(mask);
3b46e624 3020 break;
d9bce9d9
JM		 3021 case 2:
3022#if defined(TARGET_PPC64)
3023 if (ctx->sf_mode)
3024 gen_op_test_ctrz_false_64(mask);
3025 else
3026#endif
3027 gen_op_test_ctrz_false(mask);
3028 break;
e98a6e40 3029 default:
d9bce9d9
JM		 3030 case 4:
3031 case 6:
e98a6e40 3032 gen_op_test_false(mask);
d9bce9d9
JM		 3033 break;
3034 }
3035 }
3036 }
e98a6e40 3037 if (type == BCOND_IM) {
c53be334
FB		 3038 int l1 = gen_new_label();
3039 gen_op_jz_T0(l1);
c1942362 3040 gen_goto_tb(ctx, 0, target);
c53be334 3041 gen_set_label(l1);
c1942362 3042 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3043 } else {
d9bce9d9
JM		 3044#if defined(TARGET_PPC64)
3045 if (ctx->sf_mode)
3046 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3047 else
3048#endif
3049 gen_op_btest_T1(ctx->nip);
36081602 3050 no_test:
57fec1fe 3051 tcg_gen_exit_tb(0);
08e46e54 3052 }
e98a6e40
FB		 3053}
3054
3055GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3056{
e98a6e40
FB		 3057 gen_bcond(ctx, BCOND_IM);
3058}
3059
3060GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3061{
e98a6e40
FB		 3062 gen_bcond(ctx, BCOND_CTR);
3063}
3064
3065GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3066{
e98a6e40
FB		 3067 gen_bcond(ctx, BCOND_LR);
3068}
79aceca5
FB		 3069
3070/*** Condition register logical ***/
3071#define GEN_CRLOGIC(op, opc) \
3072GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3073{ \
fc0d441e
JM		 3074 uint8_t bitmask; \
3075 int sh; \
47e4661c 3076 tcg_gen_mov_i32(cpu_T[0], cpu_crf[crbA(ctx->opcode) >> 2]); \
fc0d441e
JM		 3077 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3078 if (sh > 0) \
3079 gen_op_srli_T0(sh); \
3080 else if (sh < 0) \
3081 gen_op_sli_T0(-sh); \
47e4661c 3082 tcg_gen_mov_i32(cpu_T[1], cpu_crf[crbB(ctx->opcode) >> 2]); \
fc0d441e
JM		 3083 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3084 if (sh > 0) \
3085 gen_op_srli_T1(sh); \
3086 else if (sh < 0) \
3087 gen_op_sli_T1(-sh); \
79aceca5 3088 gen_op_##op(); \
fc0d441e 3089 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
0df5bdbe 3090 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], bitmask); \
47e4661c 3091 tcg_gen_andi_i32(cpu_T[1], cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
fc0d441e 3092 gen_op_or(); \
47e4661c 3093 tcg_gen_andi_i32(cpu_crf[crbD(ctx->opcode) >> 2], cpu_T[0], 0xf); \
79aceca5
FB		 3094}
3095
3096/* crand */
76a66253 3097GEN_CRLOGIC(and, 0x08);
79aceca5 3098/* crandc */
76a66253 3099GEN_CRLOGIC(andc, 0x04);
79aceca5 3100/* creqv */
76a66253 3101GEN_CRLOGIC(eqv, 0x09);
79aceca5 3102/* crnand */
76a66253 3103GEN_CRLOGIC(nand, 0x07);
79aceca5 3104/* crnor */
76a66253 3105GEN_CRLOGIC(nor, 0x01);
79aceca5 3106/* cror */
76a66253 3107GEN_CRLOGIC(or, 0x0E);
79aceca5 3108/* crorc */
76a66253 3109GEN_CRLOGIC(orc, 0x0D);
79aceca5 3110/* crxor */
76a66253 3111GEN_CRLOGIC(xor, 0x06);
79aceca5
FB		 3112/* mcrf */
3113GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3114{
47e4661c 3115 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3116}
3117
3118/*** System linkage ***/
3119/* rfi (supervisor only) */
76a66253 3120GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3121{
9a64fbe4 3122#if defined(CONFIG_USER_ONLY)
e1833e1f 3123 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3124#else
3125 /* Restore CPU state */
76a66253 3126 if (unlikely(!ctx->supervisor)) {
e1833e1f 3127 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3128 return;
9a64fbe4 3129 }
a42bd6cc 3130 gen_op_rfi();
e1833e1f 3131 GEN_SYNC(ctx);
9a64fbe4 3132#endif
79aceca5
FB		 3133}
3134
426613db 3135#if defined(TARGET_PPC64)
a750fc0b 3136GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3137{
3138#if defined(CONFIG_USER_ONLY)
e1833e1f 3139 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3140#else
3141 /* Restore CPU state */
3142 if (unlikely(!ctx->supervisor)) {
e1833e1f 3143 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3144 return;
3145 }
a42bd6cc 3146 gen_op_rfid();
e1833e1f 3147 GEN_SYNC(ctx);
426613db
JM		 3148#endif
3149}
426613db 3150
5b8105fa 3151GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3152{
3153#if defined(CONFIG_USER_ONLY)
3154 GEN_EXCP_PRIVOPC(ctx);
3155#else
3156 /* Restore CPU state */
3157 if (unlikely(ctx->supervisor <= 1)) {
3158 GEN_EXCP_PRIVOPC(ctx);
3159 return;
3160 }
3161 gen_op_hrfid();
3162 GEN_SYNC(ctx);
3163#endif
3164}
3165#endif
3166
79aceca5 3167/* sc */
417bf010
JM		 3168#if defined(CONFIG_USER_ONLY)
3169#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3170#else
3171#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3172#endif
e1833e1f 3173GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3174{
e1833e1f
JM		 3175 uint32_t lev;
3176
3177 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3178 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3179}
3180
3181/*** Trap ***/
3182/* tw */
76a66253 3183GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3184{
f78fb44e
AJ		 3185 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3186 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
a0ae05aa 3187 /* Update the nip since this might generate a trap exception */
d9bce9d9 3188 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3189 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3190}
3191
3192/* twi */
3193GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3194{
f78fb44e 3195 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3196 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3197 /* Update the nip since this might generate a trap exception */
3198 gen_update_nip(ctx, ctx->nip);
76a66253 3199 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3200}
3201
d9bce9d9
JM		 3202#if defined(TARGET_PPC64)
3203/* td */
3204GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3205{
f78fb44e
AJ		 3206 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3207 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3208 /* Update the nip since this might generate a trap exception */
3209 gen_update_nip(ctx, ctx->nip);
3210 gen_op_td(TO(ctx->opcode));
3211}
3212
3213/* tdi */
3214GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3215{
f78fb44e 3216 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3217 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3218 /* Update the nip since this might generate a trap exception */
3219 gen_update_nip(ctx, ctx->nip);
3220 gen_op_td(TO(ctx->opcode));
3221}
3222#endif
3223
79aceca5 3224/*** Processor control ***/
79aceca5
FB		 3225/* mcrxr */
3226GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3227{
3228 gen_op_load_xer_cr();
47e4661c 3229 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
e864cabd
JM		 3230 gen_op_clear_xer_ov();
3231 gen_op_clear_xer_ca();
79aceca5
FB		 3232}
3233
3234/* mfcr */
76a66253 3235GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3236{
76a66253 3237 uint32_t crm, crn;
3b46e624 3238
76a66253
JM		 3239 if (likely(ctx->opcode & 0x00100000)) {
3240 crm = CRM(ctx->opcode);
3241 if (likely((crm ^ (crm - 1)) == 0)) {
3242 crn = ffs(crm);
47e4661c 3243 tcg_gen_mov_i32(cpu_T[0], cpu_crf[7 - crn]);
76a66253 3244 }
d9bce9d9 3245 } else {
6676f424 3246 gen_op_load_cr();
d9bce9d9 3247 }
f78fb44e 3248 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 3249}
3250
3251/* mfmsr */
3252GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3253{
9a64fbe4 3254#if defined(CONFIG_USER_ONLY)
e1833e1f 3255 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3256#else
76a66253 3257 if (unlikely(!ctx->supervisor)) {
e1833e1f 3258 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3259 return;
9a64fbe4 3260 }
6676f424 3261 gen_op_load_msr();
f78fb44e 3262 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3263#endif
79aceca5
FB		 3264}
3265
a11b8151 3266#if 1
6f2d8978 3267#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3268#else
3269static void spr_noaccess (void *opaque, int sprn)
3270{
3271 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3272 printf("ERROR: try to access SPR %d !\n", sprn);
3273}
3274#define SPR_NOACCESS (&spr_noaccess)
3275#endif
3276
79aceca5 3277/* mfspr */
b068d6a7 3278static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3279{
3fc6c082 3280 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3281 uint32_t sprn = SPR(ctx->opcode);
3282
3fc6c082 3283#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3284 if (ctx->supervisor == 2)
3285 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3286 else if (ctx->supervisor)
3fc6c082
FB		 3287 read_cb = ctx->spr_cb[sprn].oea_read;
3288 else
9a64fbe4 3289#endif
3fc6c082 3290 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3291 if (likely(read_cb != NULL)) {
3292 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3293 (*read_cb)(ctx, sprn);
f78fb44e 3294 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3295 } else {
3296 /* Privilege exception */
9fceefa7
JM		 3297 /* This is a hack to avoid warnings when running Linux:
3298 * this OS breaks the PowerPC virtualisation model,
3299 * allowing userland application to read the PVR
3300 */
3301 if (sprn != SPR_PVR) {
3302 if (loglevel != 0) {
6b542af7 3303 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3304 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3305 }
077fc206
JM		 3306 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3307 sprn, sprn, ctx->nip);
f24e5695 3308 }
e1833e1f 3309 GEN_EXCP_PRIVREG(ctx);
79aceca5 3310 }
3fc6c082
FB		 3311 } else {
3312 /* Not defined */
4a057712 3313 if (loglevel != 0) {
077fc206
JM		 3314 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3315 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3316 }
077fc206
JM		 3317 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3318 sprn, sprn, ctx->nip);
e1833e1f
JM		 3319 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3320 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3321 }
79aceca5
FB		 3322}
3323
3fc6c082 3324GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3325{
3fc6c082 3326 gen_op_mfspr(ctx);
76a66253 3327}
3fc6c082
FB		 3328
3329/* mftb */
a750fc0b 3330GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3331{
3332 gen_op_mfspr(ctx);
79aceca5
FB		 3333}
3334
3335/* mtcrf */
8dd4983c 3336GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3337{
76a66253 3338 uint32_t crm, crn;
3b46e624 3339
f78fb44e 3340 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 3341 crm = CRM(ctx->opcode);
3342 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3343 crn = ffs(crm);
3344 gen_op_srli_T0(crn * 4);
47e4661c 3345 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_T[0], 0xf);
76a66253 3346 } else {
6676f424 3347 gen_op_store_cr(crm);
76a66253 3348 }
79aceca5
FB		 3349}
3350
3351/* mtmsr */
426613db 3352#if defined(TARGET_PPC64)
be147d08 3353GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3354{
3355#if defined(CONFIG_USER_ONLY)
e1833e1f 3356 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3357#else
3358 if (unlikely(!ctx->supervisor)) {
e1833e1f 3359 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3360 return;
3361 }
f78fb44e 3362 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3363 if (ctx->opcode & 0x00010000) {
3364 /* Special form that does not need any synchronisation */
3365 gen_op_update_riee();
3366 } else {
056b05f8
JM		 3367 /* XXX: we need to update nip before the store
3368 * if we enter power saving mode, we will exit the loop
3369 * directly from ppc_store_msr
3370 */
be147d08 3371 gen_update_nip(ctx, ctx->nip);
6676f424 3372 gen_op_store_msr();
be147d08
JM		 3373 /* Must stop the translation as machine state (may have) changed */
3374 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3375 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3376 }
426613db
JM		 3377#endif
3378}
3379#endif
3380
79aceca5
FB		 3381GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3382{
9a64fbe4 3383#if defined(CONFIG_USER_ONLY)
e1833e1f 3384 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3385#else
76a66253 3386 if (unlikely(!ctx->supervisor)) {
e1833e1f 3387 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3388 return;
9a64fbe4 3389 }
f78fb44e 3390 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3391 if (ctx->opcode & 0x00010000) {
3392 /* Special form that does not need any synchronisation */
3393 gen_op_update_riee();
3394 } else {
056b05f8
JM		 3395 /* XXX: we need to update nip before the store
3396 * if we enter power saving mode, we will exit the loop
3397 * directly from ppc_store_msr
3398 */
be147d08 3399 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3400#if defined(TARGET_PPC64)
be147d08 3401 if (!ctx->sf_mode)
6676f424 3402 gen_op_store_msr_32();
be147d08 3403 else
d9bce9d9 3404#endif
6676f424 3405 gen_op_store_msr();
be147d08
JM		 3406 /* Must stop the translation as machine state (may have) changed */
3407 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3408 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3409 }
9a64fbe4 3410#endif
79aceca5
FB		 3411}
3412
3413/* mtspr */
3414GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3415{
3fc6c082 3416 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3417 uint32_t sprn = SPR(ctx->opcode);
3418
3fc6c082 3419#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3420 if (ctx->supervisor == 2)
3421 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3422 else if (ctx->supervisor)
3fc6c082
FB		 3423 write_cb = ctx->spr_cb[sprn].oea_write;
3424 else
9a64fbe4 3425#endif
3fc6c082 3426 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3427 if (likely(write_cb != NULL)) {
3428 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 3429 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 3430 (*write_cb)(ctx, sprn);
3431 } else {
3432 /* Privilege exception */
4a057712 3433 if (loglevel != 0) {
077fc206
JM		 3434 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3435 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3436 }
077fc206
JM		 3437 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3438 sprn, sprn, ctx->nip);
e1833e1f 3439 GEN_EXCP_PRIVREG(ctx);
76a66253 3440 }
3fc6c082
FB		 3441 } else {
3442 /* Not defined */
4a057712 3443 if (loglevel != 0) {
077fc206
JM		 3444 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3445 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3446 }
077fc206
JM		 3447 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3448 sprn, sprn, ctx->nip);
e1833e1f
JM		 3449 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3450 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3451 }
79aceca5
FB		 3452}
3453
3454/*** Cache management ***/
79aceca5 3455/* dcbf */
0db1b20e 3456GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3457{
dac454af 3458 /* XXX: specification says this is treated as a load by the MMU */
76a66253 3459 gen_addr_reg_index(ctx);
a541f297 3460 op_ldst(lbz);
79aceca5
FB		 3461}
3462
3463/* dcbi (Supervisor only) */
9a64fbe4 3464GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3465{
a541f297 3466#if defined(CONFIG_USER_ONLY)
e1833e1f 3467 GEN_EXCP_PRIVOPC(ctx);
a541f297 3468#else
76a66253 3469 if (unlikely(!ctx->supervisor)) {
e1833e1f 3470 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3471 return;
9a64fbe4 3472 }
76a66253
JM		 3473 gen_addr_reg_index(ctx);
3474 /* XXX: specification says this should be treated as a store by the MMU */
dac454af 3475 op_ldst(lbz);
a541f297
FB		 3476 op_ldst(stb);
3477#endif
79aceca5
FB		 3478}
3479
3480/* dcdst */
9a64fbe4 3481GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3482{
76a66253
JM		 3483 /* XXX: specification say this is treated as a load by the MMU */
3484 gen_addr_reg_index(ctx);
a541f297 3485 op_ldst(lbz);
79aceca5
FB		 3486}
3487
3488/* dcbt */
0db1b20e 3489GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3490{
0db1b20e 3491 /* interpreted as no-op */
76a66253
JM		 3492 /* XXX: specification say this is treated as a load by the MMU
3493 * but does not generate any exception
3494 */
79aceca5
FB		 3495}
3496
3497/* dcbtst */
0db1b20e 3498GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3499{
0db1b20e 3500 /* interpreted as no-op */
76a66253
JM		 3501 /* XXX: specification say this is treated as a load by the MMU
3502 * but does not generate any exception
3503 */
79aceca5
FB		 3504}
3505
3506/* dcbz */
d63001d1 3507#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 3508static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3509 /* 32 bytes cache line size */
d63001d1 3510 {
7863667f
JM		 3511#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3512#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3513#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3514#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3515#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3516#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3517#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3518#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3519 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 3520 },
7863667f 3521 /* 64 bytes cache line size */
d63001d1 3522 {
7863667f
JM		 3523#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3524#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3525#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3526#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3527#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3528#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3529#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3530#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3531 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 3532 },
7863667f 3533 /* 128 bytes cache line size */
d63001d1 3534 {
7863667f
JM		 3535#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3536#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3537#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3538#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3539#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3540#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3541#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3542#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3543 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 3544 },
7863667f 3545 /* tunable cache line size */
d63001d1 3546 {
7863667f
JM		 3547#define gen_op_dcbz_le_raw gen_op_dcbz_raw
3548#define gen_op_dcbz_le_user gen_op_dcbz_user
3549#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3550#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3551#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3552#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3553#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3554#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3555 GEN_MEM_FUNCS(dcbz),
d63001d1 3556 },
76a66253 3557};
9a64fbe4 3558
b068d6a7
JM		 3559static always_inline void handler_dcbz (DisasContext *ctx,
3560 int dcache_line_size)
d63001d1
JM		 3561{
3562 int n;
3563
3564 switch (dcache_line_size) {
3565 case 32:
3566 n = 0;
3567 break;
3568 case 64:
3569 n = 1;
3570 break;
3571 case 128:
3572 n = 2;
3573 break;
3574 default:
3575 n = 3;
3576 break;
3577 }
3578 op_dcbz(n);
3579}
3580
3581GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 3582{
76a66253 3583 gen_addr_reg_index(ctx);
d63001d1
JM		 3584 handler_dcbz(ctx, ctx->dcache_line_size);
3585 gen_op_check_reservation();
3586}
3587
c7697e1f 3588GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1
JM		 3589{
3590 gen_addr_reg_index(ctx);
3591 if (ctx->opcode & 0x00200000)
3592 handler_dcbz(ctx, ctx->dcache_line_size);
3593 else
3594 handler_dcbz(ctx, -1);
4b3686fa 3595 gen_op_check_reservation();
79aceca5
FB		 3596}
3597
3598/* icbi */
36f69651 3599#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 3600#define gen_op_icbi_le_raw gen_op_icbi_raw
3601#define gen_op_icbi_le_user gen_op_icbi_user
3602#define gen_op_icbi_le_kernel gen_op_icbi_kernel
3603#define gen_op_icbi_le_hypv gen_op_icbi_hypv
3604#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3605#define gen_op_icbi_le_64_user gen_op_icbi_64_user
3606#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3607#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3608static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3609 GEN_MEM_FUNCS(icbi),
36f69651 3610};
e1833e1f 3611
1b413d55 3612GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 3613{
30032c94
JM		 3614 /* NIP cannot be restored if the memory exception comes from an helper */
3615 gen_update_nip(ctx, ctx->nip - 4);
76a66253 3616 gen_addr_reg_index(ctx);
36f69651 3617 op_icbi();
79aceca5
FB		 3618}
3619
3620/* Optional: */
3621/* dcba */
a750fc0b 3622GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 3623{
0db1b20e
JM		 3624 /* interpreted as no-op */
3625 /* XXX: specification say this is treated as a store by the MMU
3626 * but does not generate any exception
3627 */
79aceca5
FB		 3628}
3629
3630/*** Segment register manipulation ***/
3631/* Supervisor only: */
3632/* mfsr */
3633GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3634{
9a64fbe4 3635#if defined(CONFIG_USER_ONLY)
e1833e1f 3636 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3637#else
76a66253 3638 if (unlikely(!ctx->supervisor)) {
e1833e1f 3639 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3640 return;
9a64fbe4 3641 }
86c581dc 3642 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 3643 gen_op_load_sr();
f78fb44e 3644 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3645#endif
79aceca5
FB		 3646}
3647
3648/* mfsrin */
9a64fbe4 3649GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 3650{
9a64fbe4 3651#if defined(CONFIG_USER_ONLY)
e1833e1f 3652 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3653#else
76a66253 3654 if (unlikely(!ctx->supervisor)) {
e1833e1f 3655 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3656 return;
9a64fbe4 3657 }
f78fb44e 3658 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 3659 gen_op_srli_T1(28);
3660 gen_op_load_sr();
f78fb44e 3661 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3662#endif
79aceca5
FB		 3663}
3664
3665/* mtsr */
e63c59cb 3666GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 3667{
9a64fbe4 3668#if defined(CONFIG_USER_ONLY)
e1833e1f 3669 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3670#else
76a66253 3671 if (unlikely(!ctx->supervisor)) {
e1833e1f 3672 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3673 return;
9a64fbe4 3674 }
f78fb44e 3675 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 3676 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 3677 gen_op_store_sr();
9a64fbe4 3678#endif
79aceca5
FB		 3679}
3680
3681/* mtsrin */
9a64fbe4 3682GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 3683{
9a64fbe4 3684#if defined(CONFIG_USER_ONLY)
e1833e1f 3685 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3686#else
76a66253 3687 if (unlikely(!ctx->supervisor)) {
e1833e1f 3688 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3689 return;
9a64fbe4 3690 }
f78fb44e
AJ		 3691 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3692 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 3693 gen_op_srli_T1(28);
3694 gen_op_store_sr();
9a64fbe4 3695#endif
79aceca5
FB		 3696}
3697
12de9a39
JM		 3698#if defined(TARGET_PPC64)
3699/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3700/* mfsr */
c7697e1f 3701GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 3702{
3703#if defined(CONFIG_USER_ONLY)
3704 GEN_EXCP_PRIVREG(ctx);
3705#else
3706 if (unlikely(!ctx->supervisor)) {
3707 GEN_EXCP_PRIVREG(ctx);
3708 return;
3709 }
86c581dc 3710 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 3711 gen_op_load_slb();
f78fb44e 3712 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 3713#endif
3714}
3715
3716/* mfsrin */
c7697e1f
JM		 3717GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3718 PPC_SEGMENT_64B)
12de9a39
JM		 3719{
3720#if defined(CONFIG_USER_ONLY)
3721 GEN_EXCP_PRIVREG(ctx);
3722#else
3723 if (unlikely(!ctx->supervisor)) {
3724 GEN_EXCP_PRIVREG(ctx);
3725 return;
3726 }
f78fb44e 3727 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 3728 gen_op_srli_T1(28);
3729 gen_op_load_slb();
f78fb44e 3730 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 3731#endif
3732}
3733
3734/* mtsr */
c7697e1f 3735GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 3736{
3737#if defined(CONFIG_USER_ONLY)
3738 GEN_EXCP_PRIVREG(ctx);
3739#else
3740 if (unlikely(!ctx->supervisor)) {
3741 GEN_EXCP_PRIVREG(ctx);
3742 return;
3743 }
f78fb44e 3744 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 3745 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 3746 gen_op_store_slb();
3747#endif
3748}
3749
3750/* mtsrin */
c7697e1f
JM		 3751GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3752 PPC_SEGMENT_64B)
12de9a39
JM		 3753{
3754#if defined(CONFIG_USER_ONLY)
3755 GEN_EXCP_PRIVREG(ctx);
3756#else
3757 if (unlikely(!ctx->supervisor)) {
3758 GEN_EXCP_PRIVREG(ctx);
3759 return;
3760 }
f78fb44e
AJ		 3761 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3762 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 3763 gen_op_srli_T1(28);
3764 gen_op_store_slb();
3765#endif
3766}
3767#endif /* defined(TARGET_PPC64) */
3768
79aceca5
FB		 3769/*** Lookaside buffer management ***/
3770/* Optional & supervisor only: */
3771/* tlbia */
3fc6c082 3772GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 3773{
9a64fbe4 3774#if defined(CONFIG_USER_ONLY)
e1833e1f 3775 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3776#else
76a66253 3777 if (unlikely(!ctx->supervisor)) {
e1833e1f 3778 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3779 return;
9a64fbe4
FB		 3780 }
3781 gen_op_tlbia();
3782#endif
79aceca5
FB		 3783}
3784
3785/* tlbie */
76a66253 3786GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 3787{
9a64fbe4 3788#if defined(CONFIG_USER_ONLY)
e1833e1f 3789 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3790#else
76a66253 3791 if (unlikely(!ctx->supervisor)) {
e1833e1f 3792 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3793 return;
9a64fbe4 3794 }
f78fb44e 3795 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3796#if defined(TARGET_PPC64)
3797 if (ctx->sf_mode)
3798 gen_op_tlbie_64();
3799 else
3800#endif
3801 gen_op_tlbie();
9a64fbe4 3802#endif
79aceca5
FB		 3803}
3804
3805/* tlbsync */
76a66253 3806GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 3807{
9a64fbe4 3808#if defined(CONFIG_USER_ONLY)
e1833e1f 3809 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3810#else
76a66253 3811 if (unlikely(!ctx->supervisor)) {
e1833e1f 3812 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3813 return;
9a64fbe4
FB		 3814 }
3815 /* This has no effect: it should ensure that all previous
3816 * tlbie have completed
3817 */
e1833e1f 3818 GEN_STOP(ctx);
9a64fbe4 3819#endif
79aceca5
FB		 3820}
3821
426613db
JM		 3822#if defined(TARGET_PPC64)
3823/* slbia */
3824GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
3825{
3826#if defined(CONFIG_USER_ONLY)
e1833e1f 3827 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3828#else
3829 if (unlikely(!ctx->supervisor)) {
e1833e1f 3830 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3831 return;
3832 }
3833 gen_op_slbia();
426613db
JM		 3834#endif
3835}
3836
3837/* slbie */
3838GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3839{
3840#if defined(CONFIG_USER_ONLY)
e1833e1f 3841 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3842#else
3843 if (unlikely(!ctx->supervisor)) {
e1833e1f 3844 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3845 return;
3846 }
f78fb44e 3847 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 3848 gen_op_slbie();
426613db
JM		 3849#endif
3850}
3851#endif
3852
79aceca5
FB		 3853/*** External control ***/
3854/* Optional: */
9a64fbe4
FB		 3855#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3856#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 3857static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
3858 GEN_MEM_FUNCS(eciwx),
111bfab3 3859};
7863667f
JM		 3860static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
3861 GEN_MEM_FUNCS(ecowx),
111bfab3 3862};
9a64fbe4 3863
111bfab3 3864/* eciwx */
79aceca5
FB		 3865GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
3866{
9a64fbe4 3867 /* Should check EAR[E] & alignment ! */
76a66253
JM		 3868 gen_addr_reg_index(ctx);
3869 op_eciwx();
f78fb44e 3870 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3871}
3872
3873/* ecowx */
3874GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3875{
3876 /* Should check EAR[E] & alignment ! */
3877 gen_addr_reg_index(ctx);
f78fb44e 3878 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 3879 op_ecowx();
3880}
3881
3882/* PowerPC 601 specific instructions */
3883/* abs - abs. */
3884GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3885{
f78fb44e 3886 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 3887 gen_op_POWER_abs();
f78fb44e 3888 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3889 if (unlikely(Rc(ctx->opcode) != 0))
3890 gen_set_Rc0(ctx);
3891}
3892
3893/* abso - abso. */
3894GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3895{
f78fb44e 3896 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 3897 gen_op_POWER_abso();
f78fb44e 3898 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3899 if (unlikely(Rc(ctx->opcode) != 0))
3900 gen_set_Rc0(ctx);
3901}
3902
3903/* clcs */
a750fc0b 3904GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 3905{
f78fb44e 3906 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 3907 gen_op_POWER_clcs();
c7697e1f 3908 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 3909 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3910}
3911
3912/* div - div. */
3913GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3914{
f78fb44e
AJ		 3915 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3916 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3917 gen_op_POWER_div();
f78fb44e 3918 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3919 if (unlikely(Rc(ctx->opcode) != 0))
3920 gen_set_Rc0(ctx);
3921}
3922
3923/* divo - divo. */
3924GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3925{
f78fb44e
AJ		 3926 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3927 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3928 gen_op_POWER_divo();
f78fb44e 3929 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3930 if (unlikely(Rc(ctx->opcode) != 0))
3931 gen_set_Rc0(ctx);
3932}
3933
3934/* divs - divs. */
3935GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3936{
f78fb44e
AJ		 3937 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3938 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3939 gen_op_POWER_divs();
f78fb44e 3940 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3941 if (unlikely(Rc(ctx->opcode) != 0))
3942 gen_set_Rc0(ctx);
3943}
3944
3945/* divso - divso. */
3946GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3947{
f78fb44e
AJ		 3948 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3949 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3950 gen_op_POWER_divso();
f78fb44e 3951 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3952 if (unlikely(Rc(ctx->opcode) != 0))
3953 gen_set_Rc0(ctx);
3954}
3955
3956/* doz - doz. */
3957GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3958{
f78fb44e
AJ		 3959 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3960 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3961 gen_op_POWER_doz();
f78fb44e 3962 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3963 if (unlikely(Rc(ctx->opcode) != 0))
3964 gen_set_Rc0(ctx);
3965}
3966
3967/* dozo - dozo. */
3968GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3969{
f78fb44e
AJ		 3970 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3971 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3972 gen_op_POWER_dozo();
f78fb44e 3973 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3974 if (unlikely(Rc(ctx->opcode) != 0))
3975 gen_set_Rc0(ctx);
3976}
3977
3978/* dozi */
3979GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
3980{
f78fb44e 3981 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 3982 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 3983 gen_op_POWER_doz();
f78fb44e 3984 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3985}
3986
7863667f
JM		 3987/* As lscbx load from memory byte after byte, it's always endian safe.
3988 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3989 */
2857068e 3990#define op_POWER_lscbx(start, ra, rb) \
76a66253 3991(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 3992#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
3993#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
3994#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
3995#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
3996#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
3997#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
3998#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
3999#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4000#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4001#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4002#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4003#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4004static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4005 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4006};
76a66253
JM		 4007
4008/* lscbx - lscbx. */
4009GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4010{
4011 int ra = rA(ctx->opcode);
4012 int rb = rB(ctx->opcode);
4013
4014 gen_addr_reg_index(ctx);
4015 if (ra == 0) {
4016 ra = rb;
4017 }
4018 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4019 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4020 gen_op_load_xer_bc();
4021 gen_op_load_xer_cmp();
4022 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4023 gen_op_store_xer_bc();
4024 if (unlikely(Rc(ctx->opcode) != 0))
4025 gen_set_Rc0(ctx);
4026}
4027
4028/* maskg - maskg. */
4029GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4030{
f78fb44e
AJ		 4031 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4032 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4033 gen_op_POWER_maskg();
f78fb44e 4034 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4035 if (unlikely(Rc(ctx->opcode) != 0))
4036 gen_set_Rc0(ctx);
4037}
4038
4039/* maskir - maskir. */
4040GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4041{
f78fb44e
AJ		 4042 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4043 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4044 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4045 gen_op_POWER_maskir();
f78fb44e 4046 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4047 if (unlikely(Rc(ctx->opcode) != 0))
4048 gen_set_Rc0(ctx);
4049}
4050
4051/* mul - mul. */
4052GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4053{
f78fb44e
AJ		 4054 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4055 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4056 gen_op_POWER_mul();
f78fb44e 4057 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4058 if (unlikely(Rc(ctx->opcode) != 0))
4059 gen_set_Rc0(ctx);
4060}
4061
4062/* mulo - mulo. */
4063GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4064{
f78fb44e
AJ		 4065 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4066 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4067 gen_op_POWER_mulo();
f78fb44e 4068 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4069 if (unlikely(Rc(ctx->opcode) != 0))
4070 gen_set_Rc0(ctx);
4071}
4072
4073/* nabs - nabs. */
4074GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4075{
f78fb44e 4076 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4077 gen_op_POWER_nabs();
f78fb44e 4078 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4079 if (unlikely(Rc(ctx->opcode) != 0))
4080 gen_set_Rc0(ctx);
4081}
4082
4083/* nabso - nabso. */
4084GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4085{
f78fb44e 4086 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4087 gen_op_POWER_nabso();
f78fb44e 4088 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4089 if (unlikely(Rc(ctx->opcode) != 0))
4090 gen_set_Rc0(ctx);
4091}
4092
4093/* rlmi - rlmi. */
4094GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4095{
4096 uint32_t mb, me;
4097
4098 mb = MB(ctx->opcode);
4099 me = ME(ctx->opcode);
f78fb44e
AJ		 4100 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4101 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4102 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4103 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4104 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4105 if (unlikely(Rc(ctx->opcode) != 0))
4106 gen_set_Rc0(ctx);
4107}
4108
4109/* rrib - rrib. */
4110GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4111{
f78fb44e
AJ		 4112 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4113 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4114 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4115 gen_op_POWER_rrib();
f78fb44e 4116 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4117 if (unlikely(Rc(ctx->opcode) != 0))
4118 gen_set_Rc0(ctx);
4119}
4120
4121/* sle - sle. */
4122GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4123{
f78fb44e
AJ		 4124 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4125 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4126 gen_op_POWER_sle();
f78fb44e 4127 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4128 if (unlikely(Rc(ctx->opcode) != 0))
4129 gen_set_Rc0(ctx);
4130}
4131
4132/* sleq - sleq. */
4133GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4134{
f78fb44e
AJ		 4135 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4136 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4137 gen_op_POWER_sleq();
f78fb44e 4138 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4139 if (unlikely(Rc(ctx->opcode) != 0))
4140 gen_set_Rc0(ctx);
4141}
4142
4143/* sliq - sliq. */
4144GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4145{
f78fb44e 4146 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4147 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4148 gen_op_POWER_sle();
f78fb44e 4149 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4150 if (unlikely(Rc(ctx->opcode) != 0))
4151 gen_set_Rc0(ctx);
4152}
4153
4154/* slliq - slliq. */
4155GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4156{
f78fb44e 4157 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4158 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4159 gen_op_POWER_sleq();
f78fb44e 4160 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4161 if (unlikely(Rc(ctx->opcode) != 0))
4162 gen_set_Rc0(ctx);
4163}
4164
4165/* sllq - sllq. */
4166GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4167{
f78fb44e
AJ		 4168 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4169 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4170 gen_op_POWER_sllq();
f78fb44e 4171 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4172 if (unlikely(Rc(ctx->opcode) != 0))
4173 gen_set_Rc0(ctx);
4174}
4175
4176/* slq - slq. */
4177GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4178{
f78fb44e
AJ		 4179 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4180 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4181 gen_op_POWER_slq();
f78fb44e 4182 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4183 if (unlikely(Rc(ctx->opcode) != 0))
4184 gen_set_Rc0(ctx);
4185}
4186
d9bce9d9 4187/* sraiq - sraiq. */
76a66253
JM		 4188GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4189{
f78fb44e 4190 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4191 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4192 gen_op_POWER_sraq();
f78fb44e 4193 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4194 if (unlikely(Rc(ctx->opcode) != 0))
4195 gen_set_Rc0(ctx);
4196}
4197
4198/* sraq - sraq. */
4199GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4200{
f78fb44e
AJ		 4201 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4202 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4203 gen_op_POWER_sraq();
f78fb44e 4204 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4205 if (unlikely(Rc(ctx->opcode) != 0))
4206 gen_set_Rc0(ctx);
4207}
4208
4209/* sre - sre. */
4210GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4211{
f78fb44e
AJ		 4212 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4213 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4214 gen_op_POWER_sre();
f78fb44e 4215 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4216 if (unlikely(Rc(ctx->opcode) != 0))
4217 gen_set_Rc0(ctx);
4218}
4219
4220/* srea - srea. */
4221GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4222{
f78fb44e
AJ		 4223 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4224 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4225 gen_op_POWER_srea();
f78fb44e 4226 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4227 if (unlikely(Rc(ctx->opcode) != 0))
4228 gen_set_Rc0(ctx);
4229}
4230
4231/* sreq */
4232GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4233{
f78fb44e
AJ		 4234 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4235 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4236 gen_op_POWER_sreq();
f78fb44e 4237 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4238 if (unlikely(Rc(ctx->opcode) != 0))
4239 gen_set_Rc0(ctx);
4240}
4241
4242/* sriq */
4243GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4244{
f78fb44e 4245 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4246 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4247 gen_op_POWER_srq();
f78fb44e 4248 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4249 if (unlikely(Rc(ctx->opcode) != 0))
4250 gen_set_Rc0(ctx);
4251}
4252
4253/* srliq */
4254GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4255{
f78fb44e
AJ		 4256 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4257 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4258 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4259 gen_op_POWER_srlq();
f78fb44e 4260 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4261 if (unlikely(Rc(ctx->opcode) != 0))
4262 gen_set_Rc0(ctx);
4263}
4264
4265/* srlq */
4266GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4267{
f78fb44e
AJ		 4268 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4269 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4270 gen_op_POWER_srlq();
f78fb44e 4271 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4272 if (unlikely(Rc(ctx->opcode) != 0))
4273 gen_set_Rc0(ctx);
4274}
4275
4276/* srq */
4277GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4278{
f78fb44e
AJ		 4279 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4280 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4281 gen_op_POWER_srq();
f78fb44e 4282 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4283 if (unlikely(Rc(ctx->opcode) != 0))
4284 gen_set_Rc0(ctx);
4285}
4286
4287/* PowerPC 602 specific instructions */
4288/* dsa */
4289GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4290{
4291 /* XXX: TODO */
e1833e1f 4292 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4293}
4294
4295/* esa */
4296GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4297{
4298 /* XXX: TODO */
e1833e1f 4299 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4300}
4301
4302/* mfrom */
4303GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4304{
4305#if defined(CONFIG_USER_ONLY)
e1833e1f 4306 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4307#else
4308 if (unlikely(!ctx->supervisor)) {
e1833e1f 4309 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4310 return;
4311 }
f78fb44e 4312 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4313 gen_op_602_mfrom();
f78fb44e 4314 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4315#endif
4316}
4317
4318/* 602 - 603 - G2 TLB management */
4319/* tlbld */
c7697e1f 4320GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4321{
4322#if defined(CONFIG_USER_ONLY)
e1833e1f 4323 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4324#else
4325 if (unlikely(!ctx->supervisor)) {
e1833e1f 4326 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4327 return;
4328 }
f78fb44e 4329 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4330 gen_op_6xx_tlbld();
76a66253
JM		 4331#endif
4332}
4333
4334/* tlbli */
c7697e1f 4335GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4336{
4337#if defined(CONFIG_USER_ONLY)
e1833e1f 4338 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4339#else
4340 if (unlikely(!ctx->supervisor)) {
e1833e1f 4341 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4342 return;
4343 }
f78fb44e 4344 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4345 gen_op_6xx_tlbli();
76a66253
JM		 4346#endif
4347}
4348
7dbe11ac
JM		 4349/* 74xx TLB management */
4350/* tlbld */
c7697e1f 4351GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4352{
4353#if defined(CONFIG_USER_ONLY)
4354 GEN_EXCP_PRIVOPC(ctx);
4355#else
4356 if (unlikely(!ctx->supervisor)) {
4357 GEN_EXCP_PRIVOPC(ctx);
4358 return;
4359 }
f78fb44e 4360 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4361 gen_op_74xx_tlbld();
4362#endif
4363}
4364
4365/* tlbli */
c7697e1f 4366GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4367{
4368#if defined(CONFIG_USER_ONLY)
4369 GEN_EXCP_PRIVOPC(ctx);
4370#else
4371 if (unlikely(!ctx->supervisor)) {
4372 GEN_EXCP_PRIVOPC(ctx);
4373 return;
4374 }
f78fb44e 4375 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4376 gen_op_74xx_tlbli();
4377#endif
4378}
4379
76a66253
JM		 4380/* POWER instructions not in PowerPC 601 */
4381/* clf */
4382GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4383{
4384 /* Cache line flush: implemented as no-op */
4385}
4386
4387/* cli */
4388GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4389{
7f75ffd3 4390 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4391#if defined(CONFIG_USER_ONLY)
e1833e1f 4392 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4393#else
4394 if (unlikely(!ctx->supervisor)) {
e1833e1f 4395 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4396 return;
4397 }
4398#endif
4399}
4400
4401/* dclst */
4402GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4403{
4404 /* Data cache line store: treated as no-op */
4405}
4406
4407GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4408{
4409#if defined(CONFIG_USER_ONLY)
e1833e1f 4410 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4411#else
4412 if (unlikely(!ctx->supervisor)) {
e1833e1f 4413 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4414 return;
4415 }
4416 int ra = rA(ctx->opcode);
4417 int rd = rD(ctx->opcode);
4418
4419 gen_addr_reg_index(ctx);
4420 gen_op_POWER_mfsri();
f78fb44e 4421 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4422 if (ra != 0 && ra != rd)
f78fb44e 4423 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4424#endif
4425}
4426
4427GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4428{
4429#if defined(CONFIG_USER_ONLY)
e1833e1f 4430 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4431#else
4432 if (unlikely(!ctx->supervisor)) {
e1833e1f 4433 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4434 return;
4435 }
4436 gen_addr_reg_index(ctx);
4437 gen_op_POWER_rac();
f78fb44e 4438 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4439#endif
4440}
4441
4442GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4443{
4444#if defined(CONFIG_USER_ONLY)
e1833e1f 4445 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4446#else
4447 if (unlikely(!ctx->supervisor)) {
e1833e1f 4448 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4449 return;
4450 }
4451 gen_op_POWER_rfsvc();
e1833e1f 4452 GEN_SYNC(ctx);
76a66253
JM		 4453#endif
4454}
4455
4456/* svc is not implemented for now */
4457
4458/* POWER2 specific instructions */
4459/* Quad manipulation (load/store two floats at a time) */
7863667f 4460/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 4461#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4462#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 4463#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4464#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4465#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4466#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4467#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4468#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4469#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4470#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4471#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4472#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4473#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4474#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4475#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4476#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4477#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4478#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4479static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4480 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 4481};
7863667f
JM		 4482static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4483 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 4484};
76a66253
JM		 4485
4486/* lfq */
4487GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4488{
4489 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4490 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4491 gen_addr_imm_index(ctx, 0);
76a66253 4492 op_POWER2_lfq();
a5e26afa
AJ		 4493 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4494 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4495}
4496
4497/* lfqu */
4498GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4499{
4500 int ra = rA(ctx->opcode);
4501
4502 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4503 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4504 gen_addr_imm_index(ctx, 0);
76a66253 4505 op_POWER2_lfq();
a5e26afa
AJ		 4506 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4507 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4508 if (ra != 0)
f78fb44e 4509 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4510}
4511
4512/* lfqux */
4513GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4514{
4515 int ra = rA(ctx->opcode);
4516
4517 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4518 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4519 gen_addr_reg_index(ctx);
4520 op_POWER2_lfq();
a5e26afa
AJ		 4521 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4522 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4523 if (ra != 0)
f78fb44e 4524 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4525}
4526
4527/* lfqx */
4528GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4529{
4530 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4531 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4532 gen_addr_reg_index(ctx);
4533 op_POWER2_lfq();
a5e26afa
AJ		 4534 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4535 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4536}
4537
4538/* stfq */
4539GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4540{
4541 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4542 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4543 gen_addr_imm_index(ctx, 0);
a5e26afa
AJ		 4544 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4545 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4546 op_POWER2_stfq();
4547}
4548
4549/* stfqu */
4550GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4551{
4552 int ra = rA(ctx->opcode);
4553
4554 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4555 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4556 gen_addr_imm_index(ctx, 0);
a5e26afa
AJ		 4557 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4558 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4559 op_POWER2_stfq();
4560 if (ra != 0)
f78fb44e 4561 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4562}
4563
4564/* stfqux */
4565GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4566{
4567 int ra = rA(ctx->opcode);
4568
4569 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4570 gen_update_nip(ctx, ctx->nip - 4);
76a66253 4571 gen_addr_reg_index(ctx);
a5e26afa
AJ		 4572 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4573 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4574 op_POWER2_stfq();
4575 if (ra != 0)
f78fb44e 4576 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4577}
4578
4579/* stfqx */
4580GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4581{
4582 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4583 gen_update_nip(ctx, ctx->nip - 4);
76a66253 4584 gen_addr_reg_index(ctx);
a5e26afa
AJ		 4585 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4586 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4587 op_POWER2_stfq();
4588}
4589
4590/* BookE specific instructions */
2662a059 4591/* XXX: not implemented on 440 ? */
05332d70 4592GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 4593{
4594 /* XXX: TODO */
e1833e1f 4595 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4596}
4597
2662a059 4598/* XXX: not implemented on 440 ? */
05332d70 4599GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 4600{
4601#if defined(CONFIG_USER_ONLY)
e1833e1f 4602 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4603#else
4604 if (unlikely(!ctx->supervisor)) {
e1833e1f 4605 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4606 return;
4607 }
4608 gen_addr_reg_index(ctx);
4609 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 4610#if defined(TARGET_PPC64)
4611 if (ctx->sf_mode)
4612 gen_op_tlbie_64();
4613 else
4614#endif
4615 gen_op_tlbie();
76a66253
JM		 4616#endif
4617}
4618
4619/* All 405 MAC instructions are translated here */
b068d6a7
JM		 4620static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4621 int opc2, int opc3,
4622 int ra, int rb, int rt, int Rc)
76a66253 4623{
f78fb44e
AJ		 4624 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
4625 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 4626 switch (opc3 & 0x0D) {
4627 case 0x05:
4628 /* macchw - macchw. - macchwo - macchwo. */
4629 /* macchws - macchws. - macchwso - macchwso. */
4630 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4631 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4632 /* mulchw - mulchw. */
4633 gen_op_405_mulchw();
4634 break;
4635 case 0x04:
4636 /* macchwu - macchwu. - macchwuo - macchwuo. */
4637 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4638 /* mulchwu - mulchwu. */
4639 gen_op_405_mulchwu();
4640 break;
4641 case 0x01:
4642 /* machhw - machhw. - machhwo - machhwo. */
4643 /* machhws - machhws. - machhwso - machhwso. */
4644 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4645 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4646 /* mulhhw - mulhhw. */
4647 gen_op_405_mulhhw();
4648 break;
4649 case 0x00:
4650 /* machhwu - machhwu. - machhwuo - machhwuo. */
4651 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4652 /* mulhhwu - mulhhwu. */
4653 gen_op_405_mulhhwu();
4654 break;
4655 case 0x0D:
4656 /* maclhw - maclhw. - maclhwo - maclhwo. */
4657 /* maclhws - maclhws. - maclhwso - maclhwso. */
4658 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4659 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4660 /* mullhw - mullhw. */
4661 gen_op_405_mullhw();
4662 break;
4663 case 0x0C:
4664 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4665 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4666 /* mullhwu - mullhwu. */
4667 gen_op_405_mullhwu();
4668 break;
4669 }
4670 if (opc2 & 0x02) {
4671 /* nmultiply-and-accumulate (0x0E) */
4672 gen_op_neg();
4673 }
4674 if (opc2 & 0x04) {
4675 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
f78fb44e 4676 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
e55fd934 4677 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
76a66253
JM		 4678 gen_op_405_add_T0_T2();
4679 }
4680 if (opc3 & 0x10) {
4681 /* Check overflow */
4682 if (opc3 & 0x01)
c3e10c7b 4683 gen_op_check_addo();
76a66253
JM		 4684 else
4685 gen_op_405_check_ovu();
4686 }
4687 if (opc3 & 0x02) {
4688 /* Saturate */
4689 if (opc3 & 0x01)
4690 gen_op_405_check_sat();
4691 else
4692 gen_op_405_check_satu();
4693 }
f78fb44e 4694 tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
76a66253
JM		 4695 if (unlikely(Rc) != 0) {
4696 /* Update Rc0 */
4697 gen_set_Rc0(ctx);
4698 }
4699}
4700
a750fc0b
JM		 4701#define GEN_MAC_HANDLER(name, opc2, opc3) \
4702GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 4703{ \
4704 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4705 rD(ctx->opcode), Rc(ctx->opcode)); \
4706}
4707
4708/* macchw - macchw. */
a750fc0b 4709GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 4710/* macchwo - macchwo. */
a750fc0b 4711GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 4712/* macchws - macchws. */
a750fc0b 4713GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 4714/* macchwso - macchwso. */
a750fc0b 4715GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 4716/* macchwsu - macchwsu. */
a750fc0b 4717GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 4718/* macchwsuo - macchwsuo. */
a750fc0b 4719GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 4720/* macchwu - macchwu. */
a750fc0b 4721GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 4722/* macchwuo - macchwuo. */
a750fc0b 4723GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 4724/* machhw - machhw. */
a750fc0b 4725GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 4726/* machhwo - machhwo. */
a750fc0b 4727GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 4728/* machhws - machhws. */
a750fc0b 4729GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 4730/* machhwso - machhwso. */
a750fc0b 4731GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 4732/* machhwsu - machhwsu. */
a750fc0b 4733GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 4734/* machhwsuo - machhwsuo. */
a750fc0b 4735GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 4736/* machhwu - machhwu. */
a750fc0b 4737GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 4738/* machhwuo - machhwuo. */
a750fc0b 4739GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 4740/* maclhw - maclhw. */
a750fc0b 4741GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 4742/* maclhwo - maclhwo. */
a750fc0b 4743GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 4744/* maclhws - maclhws. */
a750fc0b 4745GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 4746/* maclhwso - maclhwso. */
a750fc0b 4747GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 4748/* maclhwu - maclhwu. */
a750fc0b 4749GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 4750/* maclhwuo - maclhwuo. */
a750fc0b 4751GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 4752/* maclhwsu - maclhwsu. */
a750fc0b 4753GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 4754/* maclhwsuo - maclhwsuo. */
a750fc0b 4755GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 4756/* nmacchw - nmacchw. */
a750fc0b 4757GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 4758/* nmacchwo - nmacchwo. */
a750fc0b 4759GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 4760/* nmacchws - nmacchws. */
a750fc0b 4761GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 4762/* nmacchwso - nmacchwso. */
a750fc0b 4763GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 4764/* nmachhw - nmachhw. */
a750fc0b 4765GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 4766/* nmachhwo - nmachhwo. */
a750fc0b 4767GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 4768/* nmachhws - nmachhws. */
a750fc0b 4769GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 4770/* nmachhwso - nmachhwso. */
a750fc0b 4771GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 4772/* nmaclhw - nmaclhw. */
a750fc0b 4773GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 4774/* nmaclhwo - nmaclhwo. */
a750fc0b 4775GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 4776/* nmaclhws - nmaclhws. */
a750fc0b 4777GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 4778/* nmaclhwso - nmaclhwso. */
a750fc0b 4779GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 4780
4781/* mulchw - mulchw. */
a750fc0b 4782GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 4783/* mulchwu - mulchwu. */
a750fc0b 4784GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 4785/* mulhhw - mulhhw. */
a750fc0b 4786GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 4787/* mulhhwu - mulhhwu. */
a750fc0b 4788GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 4789/* mullhw - mullhw. */
a750fc0b 4790GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 4791/* mullhwu - mullhwu. */
a750fc0b 4792GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 4793
4794/* mfdcr */
05332d70 4795GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 4796{
4797#if defined(CONFIG_USER_ONLY)
e1833e1f 4798 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4799#else
4800 uint32_t dcrn = SPR(ctx->opcode);
4801
4802 if (unlikely(!ctx->supervisor)) {
e1833e1f 4803 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4804 return;
4805 }
86c581dc 4806 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 4807 gen_op_load_dcr();
f78fb44e 4808 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4809#endif
4810}
4811
4812/* mtdcr */
05332d70 4813GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 4814{
4815#if defined(CONFIG_USER_ONLY)
e1833e1f 4816 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4817#else
4818 uint32_t dcrn = SPR(ctx->opcode);
4819
4820 if (unlikely(!ctx->supervisor)) {
e1833e1f 4821 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4822 return;
4823 }
86c581dc 4824 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 4825 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 4826 gen_op_store_dcr();
4827#endif
4828}
4829
4830/* mfdcrx */
2662a059 4831/* XXX: not implemented on 440 ? */
05332d70 4832GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 4833{
4834#if defined(CONFIG_USER_ONLY)
e1833e1f 4835 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4836#else
4837 if (unlikely(!ctx->supervisor)) {
e1833e1f 4838 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4839 return;
4840 }
f78fb44e 4841 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 4842 gen_op_load_dcr();
f78fb44e 4843 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 4844 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 4845#endif
4846}
4847
4848/* mtdcrx */
2662a059 4849/* XXX: not implemented on 440 ? */
05332d70 4850GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 4851{
4852#if defined(CONFIG_USER_ONLY)
e1833e1f 4853 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4854#else
4855 if (unlikely(!ctx->supervisor)) {
e1833e1f 4856 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4857 return;
4858 }
f78fb44e
AJ		 4859 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4860 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 4861 gen_op_store_dcr();
a750fc0b 4862 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 4863#endif
4864}
4865
a750fc0b
JM		 4866/* mfdcrux (PPC 460) : user-mode access to DCR */
4867GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
4868{
f78fb44e 4869 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 4870 gen_op_load_dcr();
f78fb44e 4871 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 4872 /* Note: Rc update flag set leads to undefined state of Rc0 */
4873}
4874
4875/* mtdcrux (PPC 460) : user-mode access to DCR */
4876GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
4877{
f78fb44e
AJ		 4878 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4879 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 4880 gen_op_store_dcr();
4881 /* Note: Rc update flag set leads to undefined state of Rc0 */
4882}
4883
76a66253
JM		 4884/* dccci */
4885GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4886{
4887#if defined(CONFIG_USER_ONLY)
e1833e1f 4888 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4889#else
4890 if (unlikely(!ctx->supervisor)) {
e1833e1f 4891 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4892 return;
4893 }
4894 /* interpreted as no-op */
4895#endif
4896}
4897
4898/* dcread */
4899GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4900{
4901#if defined(CONFIG_USER_ONLY)
e1833e1f 4902 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4903#else
4904 if (unlikely(!ctx->supervisor)) {
e1833e1f 4905 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4906 return;
4907 }
4908 gen_addr_reg_index(ctx);
4909 op_ldst(lwz);
f78fb44e 4910 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4911#endif
4912}
4913
4914/* icbt */
c7697e1f 4915GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 4916{
4917 /* interpreted as no-op */
4918 /* XXX: specification say this is treated as a load by the MMU
4919 * but does not generate any exception
4920 */
4921}
4922
4923/* iccci */
4924GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
4925{
4926#if defined(CONFIG_USER_ONLY)
e1833e1f 4927 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4928#else
4929 if (unlikely(!ctx->supervisor)) {
e1833e1f 4930 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4931 return;
4932 }
4933 /* interpreted as no-op */
4934#endif
4935}
4936
4937/* icread */
4938GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
4939{
4940#if defined(CONFIG_USER_ONLY)
e1833e1f 4941 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4942#else
4943 if (unlikely(!ctx->supervisor)) {
e1833e1f 4944 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4945 return;
4946 }
4947 /* interpreted as no-op */
4948#endif
4949}
4950
4951/* rfci (supervisor only) */
c7697e1f 4952GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 4953{
4954#if defined(CONFIG_USER_ONLY)
e1833e1f 4955 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4956#else
4957 if (unlikely(!ctx->supervisor)) {
e1833e1f 4958 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4959 return;
4960 }
4961 /* Restore CPU state */
4962 gen_op_40x_rfci();
e1833e1f 4963 GEN_SYNC(ctx);
a42bd6cc
JM		 4964#endif
4965}
4966
4967GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4968{
4969#if defined(CONFIG_USER_ONLY)
e1833e1f 4970 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4971#else
4972 if (unlikely(!ctx->supervisor)) {
e1833e1f 4973 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4974 return;
4975 }
4976 /* Restore CPU state */
4977 gen_op_rfci();
e1833e1f 4978 GEN_SYNC(ctx);
a42bd6cc
JM		 4979#endif
4980}
4981
4982/* BookE specific */
2662a059 4983/* XXX: not implemented on 440 ? */
05332d70 4984GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 4985{
4986#if defined(CONFIG_USER_ONLY)
e1833e1f 4987 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4988#else
4989 if (unlikely(!ctx->supervisor)) {
e1833e1f 4990 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4991 return;
4992 }
4993 /* Restore CPU state */
a42bd6cc 4994 gen_op_rfdi();
e1833e1f 4995 GEN_SYNC(ctx);
76a66253
JM		 4996#endif
4997}
4998
2662a059 4999/* XXX: not implemented on 440 ? */
a750fc0b 5000GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5001{
5002#if defined(CONFIG_USER_ONLY)
e1833e1f 5003 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5004#else
5005 if (unlikely(!ctx->supervisor)) {
e1833e1f 5006 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5007 return;
5008 }
5009 /* Restore CPU state */
5010 gen_op_rfmci();
e1833e1f 5011 GEN_SYNC(ctx);
a42bd6cc
JM		 5012#endif
5013}
5eb7995e 5014
d9bce9d9 5015/* TLB management - PowerPC 405 implementation */
76a66253 5016/* tlbre */
c7697e1f 5017GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5018{
5019#if defined(CONFIG_USER_ONLY)
e1833e1f 5020 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5021#else
5022 if (unlikely(!ctx->supervisor)) {
e1833e1f 5023 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5024 return;
5025 }
5026 switch (rB(ctx->opcode)) {
5027 case 0:
f78fb44e 5028 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5029 gen_op_4xx_tlbre_hi();
f78fb44e 5030 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5031 break;
5032 case 1:
f78fb44e 5033 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5034 gen_op_4xx_tlbre_lo();
f78fb44e 5035 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5036 break;
5037 default:
e1833e1f 5038 GEN_EXCP_INVAL(ctx);
76a66253 5039 break;
9a64fbe4 5040 }
76a66253
JM		 5041#endif
5042}
5043
d9bce9d9 5044/* tlbsx - tlbsx. */
c7697e1f 5045GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5046{
5047#if defined(CONFIG_USER_ONLY)
e1833e1f 5048 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5049#else
5050 if (unlikely(!ctx->supervisor)) {
e1833e1f 5051 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5052 return;
5053 }
5054 gen_addr_reg_index(ctx);
daf4f96e 5055 gen_op_4xx_tlbsx();
76a66253 5056 if (Rc(ctx->opcode))
daf4f96e 5057 gen_op_4xx_tlbsx_check();
f78fb44e 5058 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5059#endif
79aceca5
FB		 5060}
5061
76a66253 5062/* tlbwe */
c7697e1f 5063GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5064{
76a66253 5065#if defined(CONFIG_USER_ONLY)
e1833e1f 5066 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5067#else
5068 if (unlikely(!ctx->supervisor)) {
e1833e1f 5069 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5070 return;
5071 }
5072 switch (rB(ctx->opcode)) {
5073 case 0:
f78fb44e
AJ		 5074 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5075 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5076 gen_op_4xx_tlbwe_hi();
5077 break;
5078 case 1:
f78fb44e
AJ		 5079 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5080 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5081 gen_op_4xx_tlbwe_lo();
5082 break;
5083 default:
e1833e1f 5084 GEN_EXCP_INVAL(ctx);
76a66253 5085 break;
9a64fbe4 5086 }
76a66253
JM		 5087#endif
5088}
5089
a4bb6c3e 5090/* TLB management - PowerPC 440 implementation */
5eb7995e 5091/* tlbre */
c7697e1f 5092GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5093{
5094#if defined(CONFIG_USER_ONLY)
e1833e1f 5095 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5096#else
5097 if (unlikely(!ctx->supervisor)) {
e1833e1f 5098 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5099 return;
5100 }
5101 switch (rB(ctx->opcode)) {
5102 case 0:
5eb7995e 5103 case 1:
5eb7995e 5104 case 2:
f78fb44e 5105 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5106 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5107 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5108 break;
5109 default:
e1833e1f 5110 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5111 break;
5112 }
5113#endif
5114}
5115
5116/* tlbsx - tlbsx. */
c7697e1f 5117GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5118{
5119#if defined(CONFIG_USER_ONLY)
e1833e1f 5120 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5121#else
5122 if (unlikely(!ctx->supervisor)) {
e1833e1f 5123 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5124 return;
5125 }
5126 gen_addr_reg_index(ctx);
daf4f96e 5127 gen_op_440_tlbsx();
5eb7995e 5128 if (Rc(ctx->opcode))
daf4f96e 5129 gen_op_4xx_tlbsx_check();
f78fb44e 5130 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5131#endif
5132}
5133
5134/* tlbwe */
c7697e1f 5135GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5136{
5137#if defined(CONFIG_USER_ONLY)
e1833e1f 5138 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5139#else
5140 if (unlikely(!ctx->supervisor)) {
e1833e1f 5141 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5142 return;
5143 }
5144 switch (rB(ctx->opcode)) {
5145 case 0:
5eb7995e 5146 case 1:
5eb7995e 5147 case 2:
f78fb44e
AJ		 5148 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5149 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5150 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5151 break;
5152 default:
e1833e1f 5153 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5154 break;
5155 }
5156#endif
5157}
5158
76a66253 5159/* wrtee */
05332d70 5160GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5161{
5162#if defined(CONFIG_USER_ONLY)
e1833e1f 5163 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5164#else
5165 if (unlikely(!ctx->supervisor)) {
e1833e1f 5166 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5167 return;
5168 }
f78fb44e 5169 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5170 gen_op_wrte();
dee96f6c
JM		 5171 /* Stop translation to have a chance to raise an exception
5172 * if we just set msr_ee to 1
5173 */
e1833e1f 5174 GEN_STOP(ctx);
76a66253
JM		 5175#endif
5176}
5177
5178/* wrteei */
05332d70 5179GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5180{
5181#if defined(CONFIG_USER_ONLY)
e1833e1f 5182 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5183#else
5184 if (unlikely(!ctx->supervisor)) {
e1833e1f 5185 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5186 return;
5187 }
86c581dc 5188 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5189 gen_op_wrte();
dee96f6c
JM		 5190 /* Stop translation to have a chance to raise an exception
5191 * if we just set msr_ee to 1
5192 */
e1833e1f 5193 GEN_STOP(ctx);
76a66253
JM		 5194#endif
5195}
5196
08e46e54 5197/* PowerPC 440 specific instructions */
76a66253
JM		 5198/* dlmzb */
5199GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5200{
f78fb44e
AJ		 5201 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5202 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5203 gen_op_440_dlmzb();
f78fb44e 5204 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5205 gen_op_store_xer_bc();
5206 if (Rc(ctx->opcode)) {
5207 gen_op_440_dlmzb_update_Rc();
47e4661c 5208 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
76a66253
JM		 5209 }
5210}
5211
5212/* mbar replaces eieio on 440 */
5213GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5214{
5215 /* interpreted as no-op */
5216}
5217
5218/* msync replaces sync on 440 */
0db1b20e 5219GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5220{
5221 /* interpreted as no-op */
5222}
5223
5224/* icbt */
c7697e1f 5225GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5226{
5227 /* interpreted as no-op */
5228 /* XXX: specification say this is treated as a load by the MMU
5229 * but does not generate any exception
5230 */
79aceca5
FB		 5231}
5232
a9d9eb8f
JM		 5233/*** Altivec vector extension ***/
5234/* Altivec registers moves */
a9d9eb8f 5235
1d542695
AJ		 5236static always_inline void gen_load_avr(int t, int reg) {
5237 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5238 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5239}
5240
5241static always_inline void gen_store_avr(int reg, int t) {
5242 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5243 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5244}
a9d9eb8f
JM		 5245
5246#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5247#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5248static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5249 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5250};
5251#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5252static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5253 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5254};
a9d9eb8f
JM		 5255
5256#define GEN_VR_LDX(name, opc2, opc3) \
5257GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5258{ \
5259 if (unlikely(!ctx->altivec_enabled)) { \
5260 GEN_EXCP_NO_VR(ctx); \
5261 return; \
5262 } \
5263 gen_addr_reg_index(ctx); \
5264 op_vr_ldst(vr_l##name); \
1d542695 5265 gen_store_avr(rD(ctx->opcode), 0); \
a9d9eb8f
JM		 5266}
5267
5268#define GEN_VR_STX(name, opc2, opc3) \
5269GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5270{ \
5271 if (unlikely(!ctx->altivec_enabled)) { \
5272 GEN_EXCP_NO_VR(ctx); \
5273 return; \
5274 } \
5275 gen_addr_reg_index(ctx); \
1d542695 5276 gen_load_avr(0, rS(ctx->opcode)); \
a9d9eb8f
JM		 5277 op_vr_ldst(vr_st##name); \
5278}
5279
5280OP_VR_LD_TABLE(vx);
5281GEN_VR_LDX(vx, 0x07, 0x03);
5282/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5283#define gen_op_vr_lvxl gen_op_vr_lvx
5284GEN_VR_LDX(vxl, 0x07, 0x0B);
5285
5286OP_VR_ST_TABLE(vx);
5287GEN_VR_STX(vx, 0x07, 0x07);
5288/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5289#define gen_op_vr_stvxl gen_op_vr_stvx
5290GEN_VR_STX(vxl, 0x07, 0x0F);
5291
0487d6a8 5292/*** SPE extension ***/
0487d6a8 5293/* Register moves */
3cd7d1dd 5294
f78fb44e
AJ		 5295static always_inline void gen_load_gpr64(TCGv t, int reg) {
5296#if defined(TARGET_PPC64)
5297 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5298#else
36aa55dc 5299 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5300#endif
f78fb44e 5301}
3cd7d1dd 5302
f78fb44e
AJ		 5303static always_inline void gen_store_gpr64(int reg, TCGv t) {
5304#if defined(TARGET_PPC64)
5305 tcg_gen_mov_i64(cpu_gpr[reg], t);
5306#else
5307 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
5308 TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64);
5309 tcg_gen_shri_i64(tmp, t, 32);
5310 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5311 tcg_temp_free(tmp);
3cd7d1dd 5312#endif
f78fb44e 5313}
3cd7d1dd 5314
0487d6a8
JM		 5315#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5316GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5317{ \
5318 if (Rc(ctx->opcode)) \
5319 gen_##name1(ctx); \
5320 else \
5321 gen_##name0(ctx); \
5322}
5323
5324/* Handler for undefined SPE opcodes */
b068d6a7 5325static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5326{
e1833e1f 5327 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5328}
5329
5330/* SPE load and stores */
b068d6a7 5331static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
0487d6a8
JM		 5332{
5333 target_long simm = rB(ctx->opcode);
5334
5335 if (rA(ctx->opcode) == 0) {
02f4f6c2 5336 tcg_gen_movi_tl(cpu_T[0], simm << sh);
0487d6a8 5337 } else {
f78fb44e 5338 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
0487d6a8 5339 if (likely(simm != 0))
39dd32ee 5340 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh);
0487d6a8
JM		 5341 }
5342}
5343
5344#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5345#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5346static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5347 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5348};
5349#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5350static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5351 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5352};
0487d6a8
JM		 5353
5354#define GEN_SPE_LD(name, sh) \
b068d6a7 5355static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5356{ \
5357 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5358 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5359 return; \
5360 } \
5361 gen_addr_spe_imm_index(ctx, sh); \
5362 op_spe_ldst(spe_l##name); \
f78fb44e 5363 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5364}
5365
5366#define GEN_SPE_LDX(name) \
b068d6a7 5367static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 5368{ \
5369 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5370 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5371 return; \
5372 } \
5373 gen_addr_reg_index(ctx); \
5374 op_spe_ldst(spe_l##name); \
f78fb44e 5375 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5376}
5377
5378#define GEN_SPEOP_LD(name, sh) \
5379OP_SPE_LD_TABLE(name); \
5380GEN_SPE_LD(name, sh); \
5381GEN_SPE_LDX(name)
5382
5383#define GEN_SPE_ST(name, sh) \
b068d6a7 5384static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 5385{ \
5386 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5387 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5388 return; \
5389 } \
5390 gen_addr_spe_imm_index(ctx, sh); \
f78fb44e 5391 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5392 op_spe_ldst(spe_st##name); \
5393}
5394
5395#define GEN_SPE_STX(name) \
b068d6a7 5396static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 5397{ \
5398 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5399 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5400 return; \
5401 } \
5402 gen_addr_reg_index(ctx); \
f78fb44e 5403 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5404 op_spe_ldst(spe_st##name); \
5405}
5406
5407#define GEN_SPEOP_ST(name, sh) \
5408OP_SPE_ST_TABLE(name); \
5409GEN_SPE_ST(name, sh); \
5410GEN_SPE_STX(name)
5411
5412#define GEN_SPEOP_LDST(name, sh) \
5413GEN_SPEOP_LD(name, sh); \
5414GEN_SPEOP_ST(name, sh)
5415
5416/* SPE arithmetic and logic */
5417#define GEN_SPEOP_ARITH2(name) \
b068d6a7 5418static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5419{ \
5420 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5421 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5422 return; \
5423 } \
f78fb44e
AJ		 5424 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5425 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5426 gen_op_##name(); \
f78fb44e 5427 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5428}
5429
5430#define GEN_SPEOP_ARITH1(name) \
b068d6a7 5431static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5432{ \
5433 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5434 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5435 return; \
5436 } \
f78fb44e 5437 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8 5438 gen_op_##name(); \
f78fb44e 5439 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5440}
5441
5442#define GEN_SPEOP_COMP(name) \
b068d6a7 5443static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5444{ \
5445 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5446 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5447 return; \
5448 } \
f78fb44e
AJ		 5449 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5450 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5451 gen_op_##name(); \
47e4661c 5452 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
0487d6a8
JM		 5453}
5454
5455/* Logical */
5456GEN_SPEOP_ARITH2(evand);
5457GEN_SPEOP_ARITH2(evandc);
5458GEN_SPEOP_ARITH2(evxor);
5459GEN_SPEOP_ARITH2(evor);
5460GEN_SPEOP_ARITH2(evnor);
5461GEN_SPEOP_ARITH2(eveqv);
5462GEN_SPEOP_ARITH2(evorc);
5463GEN_SPEOP_ARITH2(evnand);
5464GEN_SPEOP_ARITH2(evsrwu);
5465GEN_SPEOP_ARITH2(evsrws);
5466GEN_SPEOP_ARITH2(evslw);
5467GEN_SPEOP_ARITH2(evrlw);
5468GEN_SPEOP_ARITH2(evmergehi);
5469GEN_SPEOP_ARITH2(evmergelo);
5470GEN_SPEOP_ARITH2(evmergehilo);
5471GEN_SPEOP_ARITH2(evmergelohi);
5472
5473/* Arithmetic */
5474GEN_SPEOP_ARITH2(evaddw);
5475GEN_SPEOP_ARITH2(evsubfw);
5476GEN_SPEOP_ARITH1(evabs);
5477GEN_SPEOP_ARITH1(evneg);
5478GEN_SPEOP_ARITH1(evextsb);
5479GEN_SPEOP_ARITH1(evextsh);
5480GEN_SPEOP_ARITH1(evrndw);
5481GEN_SPEOP_ARITH1(evcntlzw);
5482GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 5483static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 5484{
5485 /* Note: brinc is usable even if SPE is disabled */
f78fb44e
AJ		 5486 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5487 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 5488 gen_op_brinc();
f78fb44e 5489 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
0487d6a8
JM		 5490}
5491
5492#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 5493static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5494{ \
5495 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5496 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5497 return; \
5498 } \
f78fb44e 5499 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8
JM		 5500 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5501 gen_op_##name(); \
f78fb44e 5502 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5503}
5504
5505#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 5506static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5507{ \
5508 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5509 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5510 return; \
5511 } \
f78fb44e 5512 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8
JM		 5513 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5514 gen_op_##name(); \
f78fb44e 5515 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5516}
5517
5518GEN_SPEOP_ARITH_IMM2(evaddw);
5519#define gen_evaddiw gen_evaddwi
5520GEN_SPEOP_ARITH_IMM2(evsubfw);
5521#define gen_evsubifw gen_evsubfwi
5522GEN_SPEOP_LOGIC_IMM2(evslw);
5523GEN_SPEOP_LOGIC_IMM2(evsrwu);
5524#define gen_evsrwis gen_evsrwsi
5525GEN_SPEOP_LOGIC_IMM2(evsrws);
5526#define gen_evsrwiu gen_evsrwui
5527GEN_SPEOP_LOGIC_IMM2(evrlw);
5528
b068d6a7 5529static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 5530{
5531 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5532
5533 gen_op_splatwi_T0_64(imm);
f78fb44e 5534 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5535}
5536
b068d6a7 5537static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 5538{
5539 uint32_t imm = rA(ctx->opcode) << 27;
5540
5541 gen_op_splatwi_T0_64(imm);
f78fb44e 5542 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5543}
5544
5545/* Comparison */
5546GEN_SPEOP_COMP(evcmpgtu);
5547GEN_SPEOP_COMP(evcmpgts);
5548GEN_SPEOP_COMP(evcmpltu);
5549GEN_SPEOP_COMP(evcmplts);
5550GEN_SPEOP_COMP(evcmpeq);
5551
5552GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5553GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5554GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5555GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5556GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5557GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5558GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5559GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5560GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5561GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5562GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5563GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5564GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5565GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5566GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5567GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5568GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5569GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5570GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5571GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5572GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5573GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5574GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5575GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5576GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5577
b068d6a7 5578static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 5579{
5580 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 5581 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 5582 return;
5583 }
47e4661c 5584 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
f78fb44e
AJ		 5585 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
5586 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
0487d6a8 5587 gen_op_evsel();
f78fb44e 5588 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5589}
5590
c7697e1f 5591GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5592{
5593 gen_evsel(ctx);
5594}
c7697e1f 5595GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5596{
5597 gen_evsel(ctx);
5598}
c7697e1f 5599GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5600{
5601 gen_evsel(ctx);
5602}
c7697e1f 5603GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5604{
5605 gen_evsel(ctx);
5606}
5607
5608/* Load and stores */
5609#if defined(TARGET_PPC64)
5610/* In that case, we already have 64 bits load & stores
5611 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5612 */
7863667f
JM		 5613#define gen_op_spe_ldd_raw gen_op_ld_raw
5614#define gen_op_spe_ldd_user gen_op_ld_user
5615#define gen_op_spe_ldd_kernel gen_op_ld_kernel
5616#define gen_op_spe_ldd_hypv gen_op_ld_hypv
5617#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5618#define gen_op_spe_ldd_64_user gen_op_ld_64_user
5619#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5620#define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
5621#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5622#define gen_op_spe_ldd_le_user gen_op_ld_le_user
5623#define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
5624#define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
5625#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5626#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5627#define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
5628#define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
5629#define gen_op_spe_stdd_raw gen_op_std_raw
5630#define gen_op_spe_stdd_user gen_op_std_user
5631#define gen_op_spe_stdd_kernel gen_op_std_kernel
5632#define gen_op_spe_stdd_hypv gen_op_std_hypv
5633#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5634#define gen_op_spe_stdd_64_user gen_op_std_64_user
5635#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5636#define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
5637#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5638#define gen_op_spe_stdd_le_user gen_op_std_le_user
5639#define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
5640#define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
5641#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5642#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5643#define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
5644#define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
0487d6a8
JM		 5645#endif /* defined(TARGET_PPC64) */
5646GEN_SPEOP_LDST(dd, 3);
5647GEN_SPEOP_LDST(dw, 3);
5648GEN_SPEOP_LDST(dh, 3);
5649GEN_SPEOP_LDST(whe, 2);
5650GEN_SPEOP_LD(whou, 2);
5651GEN_SPEOP_LD(whos, 2);
5652GEN_SPEOP_ST(who, 2);
5653
5654#if defined(TARGET_PPC64)
5655/* In that case, spe_stwwo is equivalent to stw */
7863667f
JM		 5656#define gen_op_spe_stwwo_raw gen_op_stw_raw
5657#define gen_op_spe_stwwo_user gen_op_stw_user
5658#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5659#define gen_op_spe_stwwo_hypv gen_op_stw_hypv
5660#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5661#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5662#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5663#define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
5664#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5665#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5666#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5667#define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
5668#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5669#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
0487d6a8 5670#define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
7863667f 5671#define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
0487d6a8
JM		 5672#endif
5673#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 5674static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 5675{ \
5676 gen_op_srli32_T1_64(); \
5677 gen_op_spe_stwwo_##suffix(); \
5678}
5679#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 5680static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 5681{ \
5682 gen_op_srli32_T1_64(); \
5683 gen_op_spe_stwwo_le_##suffix(); \
5684}
5685#if defined(TARGET_PPC64)
5686#define GEN_OP_SPE_STWWE(suffix) \
5687_GEN_OP_SPE_STWWE(suffix); \
5688_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 5689static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 5690{ \
5691 gen_op_srli32_T1_64(); \
5692 gen_op_spe_stwwo_64_##suffix(); \
5693} \
b068d6a7 5694static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 5695{ \
5696 gen_op_srli32_T1_64(); \
5697 gen_op_spe_stwwo_le_64_##suffix(); \
5698}
5699#else
5700#define GEN_OP_SPE_STWWE(suffix) \
5701_GEN_OP_SPE_STWWE(suffix); \
5702_GEN_OP_SPE_STWWE_LE(suffix)
5703#endif
5704#if defined(CONFIG_USER_ONLY)
5705GEN_OP_SPE_STWWE(raw);
5706#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 5707GEN_OP_SPE_STWWE(user);
7863667f
JM		 5708GEN_OP_SPE_STWWE(kernel);
5709GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 5710#endif /* defined(CONFIG_USER_ONLY) */
5711GEN_SPEOP_ST(wwe, 2);
5712GEN_SPEOP_ST(wwo, 2);
5713
5714#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 5715static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 5716{ \
5717 gen_op_##op##_##suffix(); \
5718 gen_op_splatw_T1_64(); \
5719}
5720
5721#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 5722static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 5723{ \
5724 gen_op_spe_lh_##suffix(); \
5725 gen_op_sli16_T1_64(); \
5726}
5727
5728#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 5729static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 5730{ \
5731 gen_op_spe_lh_##suffix(); \
5732 gen_op_extsh_T1_64(); \
5733}
5734
5735#if defined(CONFIG_USER_ONLY)
5736GEN_OP_SPE_LHE(raw);
5737GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
5738GEN_OP_SPE_LHE(le_raw);
5739GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
5740GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
5741GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
5742GEN_OP_SPE_LHX(raw);
5743GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
5744GEN_OP_SPE_LHX(le_raw);
5745GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
5746#if defined(TARGET_PPC64)
5747GEN_OP_SPE_LHE(64_raw);
5748GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
5749GEN_OP_SPE_LHE(le_64_raw);
5750GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
5751GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
5752GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
5753GEN_OP_SPE_LHX(64_raw);
5754GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
5755GEN_OP_SPE_LHX(le_64_raw);
5756GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
5757#endif
5758#else
0487d6a8 5759GEN_OP_SPE_LHE(user);
7863667f
JM		 5760GEN_OP_SPE_LHE(kernel);
5761GEN_OP_SPE_LHE(hypv);
0487d6a8 5762GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 5763GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
5764GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 5765GEN_OP_SPE_LHE(le_user);
7863667f
JM		 5766GEN_OP_SPE_LHE(le_kernel);
5767GEN_OP_SPE_LHE(le_hypv);
0487d6a8 5768GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 5769GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
5770GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 5771GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 5772GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
5773GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 5774GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 5775GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
5776GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 5777GEN_OP_SPE_LHX(user);
7863667f
JM		 5778GEN_OP_SPE_LHX(kernel);
5779GEN_OP_SPE_LHX(hypv);
0487d6a8 5780GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 5781GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
5782GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 5783GEN_OP_SPE_LHX(le_user);
7863667f
JM		 5784GEN_OP_SPE_LHX(le_kernel);
5785GEN_OP_SPE_LHX(le_hypv);
0487d6a8 5786GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 5787GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
5788GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 5789#if defined(TARGET_PPC64)
0487d6a8 5790GEN_OP_SPE_LHE(64_user);
7863667f
JM		 5791GEN_OP_SPE_LHE(64_kernel);
5792GEN_OP_SPE_LHE(64_hypv);
0487d6a8 5793GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 5794GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
5795GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 5796GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 5797GEN_OP_SPE_LHE(le_64_kernel);
5798GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 5799GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 5800GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
5801GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 5802GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 5803GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
5804GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 5805GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 5806GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
5807GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 5808GEN_OP_SPE_LHX(64_user);
7863667f
JM		 5809GEN_OP_SPE_LHX(64_kernel);
5810GEN_OP_SPE_LHX(64_hypv);
0487d6a8 5811GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 5812GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
5813GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 5814GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 5815GEN_OP_SPE_LHX(le_64_kernel);
5816GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 5817GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 5818GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
5819GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 5820#endif
5821#endif
5822GEN_SPEOP_LD(hhesplat, 1);
5823GEN_SPEOP_LD(hhousplat, 1);
5824GEN_SPEOP_LD(hhossplat, 1);
5825GEN_SPEOP_LD(wwsplat, 2);
5826GEN_SPEOP_LD(whsplat, 2);
5827
5828GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
5829GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
5830GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
5831GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
5832GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
5833GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
5834GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
5835GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
5836GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
5837GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
5838GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
5839GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
5840GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
5841GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
5842GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
5843GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
5844GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
5845GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
5846
5847/* Multiply and add - TODO */
5848#if 0
5849GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
5850GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
5851GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
5852GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
5853GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
5854GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
5855GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
5856GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
5857GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
5858GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
5859GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
5860GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
5861
5862GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
5863GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
5864GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
5865GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
5866GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
5867GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
5868GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
5869GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
5870GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
5871GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
5872GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
5873GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
5874GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
5875GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
5876
5877GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
5878GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
5879GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
5880GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
5881GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
5882GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
5883
5884GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
5885GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
5886GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
5887GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
5888GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
5889GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
5890GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
5891GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
5892GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
5893GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
5894GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
5895GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
5896
5897GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
5898GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
5899GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
5900GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
5901GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
5902
5903GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
5904GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
5905GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
5906GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
5907GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
5908GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
5909GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
5910GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
5911GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
5912GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
5913GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
5914GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
5915
5916GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
5917GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
5918GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
5919GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
5920GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
5921#endif
5922
5923/*** SPE floating-point extension ***/
5924#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 5925static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 5926{ \
f78fb44e 5927 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8 5928 gen_op_##name(); \
f78fb44e 5929 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5930}
5931
5932/* Single precision floating-point vectors operations */
5933/* Arithmetic */
5934GEN_SPEOP_ARITH2(evfsadd);
5935GEN_SPEOP_ARITH2(evfssub);
5936GEN_SPEOP_ARITH2(evfsmul);
5937GEN_SPEOP_ARITH2(evfsdiv);
5938GEN_SPEOP_ARITH1(evfsabs);
5939GEN_SPEOP_ARITH1(evfsnabs);
5940GEN_SPEOP_ARITH1(evfsneg);
5941/* Conversion */
5942GEN_SPEFPUOP_CONV(evfscfui);
5943GEN_SPEFPUOP_CONV(evfscfsi);
5944GEN_SPEFPUOP_CONV(evfscfuf);
5945GEN_SPEFPUOP_CONV(evfscfsf);
5946GEN_SPEFPUOP_CONV(evfsctui);
5947GEN_SPEFPUOP_CONV(evfsctsi);
5948GEN_SPEFPUOP_CONV(evfsctuf);
5949GEN_SPEFPUOP_CONV(evfsctsf);
5950GEN_SPEFPUOP_CONV(evfsctuiz);
5951GEN_SPEFPUOP_CONV(evfsctsiz);
5952/* Comparison */
5953GEN_SPEOP_COMP(evfscmpgt);
5954GEN_SPEOP_COMP(evfscmplt);
5955GEN_SPEOP_COMP(evfscmpeq);
5956GEN_SPEOP_COMP(evfststgt);
5957GEN_SPEOP_COMP(evfststlt);
5958GEN_SPEOP_COMP(evfststeq);
5959
5960/* Opcodes definitions */
5961GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
5962GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
5963GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
5964GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
5965GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
5966GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
5967GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
5968GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
5969GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
5970GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
5971GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
5972GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
5973GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
5974GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
5975
5976/* Single precision floating-point operations */
5977/* Arithmetic */
5978GEN_SPEOP_ARITH2(efsadd);
5979GEN_SPEOP_ARITH2(efssub);
5980GEN_SPEOP_ARITH2(efsmul);
5981GEN_SPEOP_ARITH2(efsdiv);
5982GEN_SPEOP_ARITH1(efsabs);
5983GEN_SPEOP_ARITH1(efsnabs);
5984GEN_SPEOP_ARITH1(efsneg);
5985/* Conversion */
5986GEN_SPEFPUOP_CONV(efscfui);
5987GEN_SPEFPUOP_CONV(efscfsi);
5988GEN_SPEFPUOP_CONV(efscfuf);
5989GEN_SPEFPUOP_CONV(efscfsf);
5990GEN_SPEFPUOP_CONV(efsctui);
5991GEN_SPEFPUOP_CONV(efsctsi);
5992GEN_SPEFPUOP_CONV(efsctuf);
5993GEN_SPEFPUOP_CONV(efsctsf);
5994GEN_SPEFPUOP_CONV(efsctuiz);
5995GEN_SPEFPUOP_CONV(efsctsiz);
5996GEN_SPEFPUOP_CONV(efscfd);
5997/* Comparison */
5998GEN_SPEOP_COMP(efscmpgt);
5999GEN_SPEOP_COMP(efscmplt);
6000GEN_SPEOP_COMP(efscmpeq);
6001GEN_SPEOP_COMP(efststgt);
6002GEN_SPEOP_COMP(efststlt);
6003GEN_SPEOP_COMP(efststeq);
6004
6005/* Opcodes definitions */
05332d70 6006GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 6007GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6008GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6009GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6010GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6011GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6012GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6013GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6014GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6015GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 6016GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6017GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 6018GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6019GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6020
6021/* Double precision floating-point operations */
6022/* Arithmetic */
6023GEN_SPEOP_ARITH2(efdadd);
6024GEN_SPEOP_ARITH2(efdsub);
6025GEN_SPEOP_ARITH2(efdmul);
6026GEN_SPEOP_ARITH2(efddiv);
6027GEN_SPEOP_ARITH1(efdabs);
6028GEN_SPEOP_ARITH1(efdnabs);
6029GEN_SPEOP_ARITH1(efdneg);
6030/* Conversion */
6031
6032GEN_SPEFPUOP_CONV(efdcfui);
6033GEN_SPEFPUOP_CONV(efdcfsi);
6034GEN_SPEFPUOP_CONV(efdcfuf);
6035GEN_SPEFPUOP_CONV(efdcfsf);
6036GEN_SPEFPUOP_CONV(efdctui);
6037GEN_SPEFPUOP_CONV(efdctsi);
6038GEN_SPEFPUOP_CONV(efdctuf);
6039GEN_SPEFPUOP_CONV(efdctsf);
6040GEN_SPEFPUOP_CONV(efdctuiz);
6041GEN_SPEFPUOP_CONV(efdctsiz);
6042GEN_SPEFPUOP_CONV(efdcfs);
6043GEN_SPEFPUOP_CONV(efdcfuid);
6044GEN_SPEFPUOP_CONV(efdcfsid);
6045GEN_SPEFPUOP_CONV(efdctuidz);
6046GEN_SPEFPUOP_CONV(efdctsidz);
6047/* Comparison */
6048GEN_SPEOP_COMP(efdcmpgt);
6049GEN_SPEOP_COMP(efdcmplt);
6050GEN_SPEOP_COMP(efdcmpeq);
6051GEN_SPEOP_COMP(efdtstgt);
6052GEN_SPEOP_COMP(efdtstlt);
6053GEN_SPEOP_COMP(efdtsteq);
6054
6055/* Opcodes definitions */
6056GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6057GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6058GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6059GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6060GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6061GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6062GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6063GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6064GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6065GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6066GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6067GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6068GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6069GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6070GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6071GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6072
79aceca5
FB		 6073/* End opcode list */
6074GEN_OPCODE_MARK(end);
6075
3fc6c082 6076#include "translate_init.c"
0411a972 6077#include "helper_regs.h"
79aceca5 6078
9a64fbe4 6079/*****************************************************************************/
3fc6c082 6080/* Misc PowerPC helpers */
36081602
JM		 6081void cpu_dump_state (CPUState *env, FILE *f,
6082 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6083 int flags)
79aceca5 6084{
3fc6c082
FB		 6085#define RGPL 4
6086#define RFPL 4
3fc6c082 6087
79aceca5
FB		 6088 int i;
6089
077fc206
JM		 6090 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6091 env->nip, env->lr, env->ctr, hreg_load_xer(env));
6b542af7
JM		 6092 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6093 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 6094#if !defined(NO_TIMER_DUMP)
077fc206 6095 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6096#if !defined(CONFIG_USER_ONLY)
6097 "DECR %08x"
6098#endif
6099 "\n",
077fc206 6100 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6101#if !defined(CONFIG_USER_ONLY)
6102 , cpu_ppc_load_decr(env)
6103#endif
6104 );
077fc206 6105#endif
76a66253 6106 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6107 if ((i & (RGPL - 1)) == 0)
6108 cpu_fprintf(f, "GPR%02d", i);
6b542af7 6109 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 6110 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6111 cpu_fprintf(f, "\n");
76a66253 6112 }
3fc6c082 6113 cpu_fprintf(f, "CR ");
76a66253 6114 for (i = 0; i < 8; i++)
7fe48483
FB		 6115 cpu_fprintf(f, "%01x", env->crf[i]);
6116 cpu_fprintf(f, " [");
76a66253
JM		 6117 for (i = 0; i < 8; i++) {
6118 char a = '-';
6119 if (env->crf[i] & 0x08)
6120 a = 'L';
6121 else if (env->crf[i] & 0x04)
6122 a = 'G';
6123 else if (env->crf[i] & 0x02)
6124 a = 'E';
7fe48483 6125 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6126 }
6b542af7 6127 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 6128 for (i = 0; i < 32; i++) {
6129 if ((i & (RFPL - 1)) == 0)
6130 cpu_fprintf(f, "FPR%02d", i);
26a76461 6131 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6132 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6133 cpu_fprintf(f, "\n");
79aceca5 6134 }
f2e63a42 6135#if !defined(CONFIG_USER_ONLY)
6b542af7 6136 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 6137 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6138#endif
79aceca5 6139
3fc6c082
FB		 6140#undef RGPL
6141#undef RFPL
79aceca5
FB		 6142}
6143
76a66253
JM		 6144void cpu_dump_statistics (CPUState *env, FILE*f,
6145 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6146 int flags)
6147{
6148#if defined(DO_PPC_STATISTICS)
6149 opc_handler_t **t1, **t2, **t3, *handler;
6150 int op1, op2, op3;
6151
6152 t1 = env->opcodes;
6153 for (op1 = 0; op1 < 64; op1++) {
6154 handler = t1[op1];
6155 if (is_indirect_opcode(handler)) {
6156 t2 = ind_table(handler);
6157 for (op2 = 0; op2 < 32; op2++) {
6158 handler = t2[op2];
6159 if (is_indirect_opcode(handler)) {
6160 t3 = ind_table(handler);
6161 for (op3 = 0; op3 < 32; op3++) {
6162 handler = t3[op3];
6163 if (handler->count == 0)
6164 continue;
6165 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6166 "%016llx %lld\n",
6167 op1, op2, op3, op1, (op3 << 5) | op2,
6168 handler->oname,
6169 handler->count, handler->count);
6170 }
6171 } else {
6172 if (handler->count == 0)
6173 continue;
6174 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6175 "%016llx %lld\n",
6176 op1, op2, op1, op2, handler->oname,
6177 handler->count, handler->count);
6178 }
6179 }
6180 } else {
6181 if (handler->count == 0)
6182 continue;
6183 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6184 op1, op1, handler->oname,
6185 handler->count, handler->count);
6186 }
6187 }
6188#endif
6189}
6190
9a64fbe4 6191/*****************************************************************************/
2cfc5f17
TS		 6192static always_inline void gen_intermediate_code_internal (CPUState *env,
6193 TranslationBlock *tb,
6194 int search_pc)
79aceca5 6195{
9fddaa0c 6196 DisasContext ctx, *ctxp = &ctx;
79aceca5 6197 opc_handler_t **table, *handler;
0fa85d43 6198 target_ulong pc_start;
79aceca5 6199 uint16_t *gen_opc_end;
056401ea 6200 int supervisor, little_endian;
79aceca5 6201 int j, lj = -1;
2e70f6ef
PB		 6202 int num_insns;
6203 int max_insns;
79aceca5
FB		 6204
6205 pc_start = tb->pc;
79aceca5 6206 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 6207#if defined(OPTIMIZE_FPRF_UPDATE)
6208 gen_fprf_ptr = gen_fprf_buf;
6209#endif
046d6672 6210 ctx.nip = pc_start;
79aceca5 6211 ctx.tb = tb;
e1833e1f 6212 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6213 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6214 supervisor = env->mmu_idx;
6215#if !defined(CONFIG_USER_ONLY)
2857068e 6216 ctx.supervisor = supervisor;
d9bce9d9 6217#endif
056401ea 6218 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6219#if defined(TARGET_PPC64)
6220 ctx.sf_mode = msr_sf;
056401ea 6221 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6222#else
056401ea 6223 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6224#endif
d63001d1 6225 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6226 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6227 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6228 ctx.spe_enabled = msr_spe;
6229 else
6230 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6231 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6232 ctx.altivec_enabled = msr_vr;
6233 else
6234 ctx.altivec_enabled = 0;
d26bfc9a 6235 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 6236 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 6237 else
8cbcb4fa 6238 ctx.singlestep_enabled = 0;
d26bfc9a 6239 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 6240 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6241 if (unlikely(env->singlestep_enabled))
6242 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 6243#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6244 /* Single step trace mode */
6245 msr_se = 1;
6246#endif
2e70f6ef
PB		 6247 num_insns = 0;
6248 max_insns = tb->cflags & CF_COUNT_MASK;
6249 if (max_insns == 0)
6250 max_insns = CF_COUNT_MASK;
6251
6252 gen_icount_start();
9a64fbe4 6253 /* Set env in case of segfault during code fetch */
e1833e1f 6254 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6255 if (unlikely(env->nb_breakpoints > 0)) {
6256 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6257 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6258 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6259 gen_op_debug();
6260 break;
6261 }
6262 }
6263 }
76a66253 6264 if (unlikely(search_pc)) {
79aceca5
FB		 6265 j = gen_opc_ptr - gen_opc_buf;
6266 if (lj < j) {
6267 lj++;
6268 while (lj < j)
6269 gen_opc_instr_start[lj++] = 0;
046d6672 6270 gen_opc_pc[lj] = ctx.nip;
79aceca5 6271 gen_opc_instr_start[lj] = 1;
2e70f6ef 6272 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 6273 }
6274 }
9fddaa0c
FB		 6275#if defined PPC_DEBUG_DISAS
6276 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6277 fprintf(logfile, "----------------\n");
1b9eb036 6278 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6279 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6280 }
6281#endif
2e70f6ef
PB		 6282 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6283 gen_io_start();
056401ea
JM		 6284 if (unlikely(little_endian)) {
6285 ctx.opcode = bswap32(ldl_code(ctx.nip));
6286 } else {
6287 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6288 }
9fddaa0c
FB		 6289#if defined PPC_DEBUG_DISAS
6290 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6291 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6292 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6293 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6294 }
6295#endif
046d6672 6296 ctx.nip += 4;
3fc6c082 6297 table = env->opcodes;
2e70f6ef 6298 num_insns++;
79aceca5
FB		 6299 handler = table[opc1(ctx.opcode)];
6300 if (is_indirect_opcode(handler)) {
6301 table = ind_table(handler);
6302 handler = table[opc2(ctx.opcode)];
6303 if (is_indirect_opcode(handler)) {
6304 table = ind_table(handler);
6305 handler = table[opc3(ctx.opcode)];
6306 }
6307 }
6308 /* Is opcode *REALLY* valid ? */
76a66253 6309 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6310 if (loglevel != 0) {
76a66253 6311 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 6312 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 6313 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6314 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6315 } else {
6316 printf("invalid/unsupported opcode: "
6b542af7 6317 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 6318 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6319 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6320 }
76a66253
JM		 6321 } else {
6322 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6323 if (loglevel != 0) {
79aceca5 6324 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 6325 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 6326 ctx.opcode & handler->inval, opc1(ctx.opcode),
6327 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6328 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6329 } else {
6330 printf("invalid bits: %08x for opcode: "
6b542af7 6331 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 6332 ctx.opcode & handler->inval, opc1(ctx.opcode),
6333 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6334 ctx.opcode, ctx.nip - 4);
76a66253 6335 }
e1833e1f 6336 GEN_EXCP_INVAL(ctxp);
4b3686fa 6337 break;
79aceca5 6338 }
79aceca5 6339 }
4b3686fa 6340 (*(handler->handler))(&ctx);
76a66253
JM		 6341#if defined(DO_PPC_STATISTICS)
6342 handler->count++;
6343#endif
9a64fbe4 6344 /* Check trace mode exceptions */
8cbcb4fa
AJ		 6345 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6346 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6347 ctx.exception != POWERPC_SYSCALL &&
6348 ctx.exception != POWERPC_EXCP_TRAP &&
6349 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 6350 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 6351 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 6352 (env->singlestep_enabled) ||
6353 num_insns >= max_insns)) {
d26bfc9a
JM		 6354 /* if we reach a page boundary or are single stepping, stop
6355 * generation
6356 */
8dd4983c 6357 break;
76a66253 6358 }
3fc6c082
FB		 6359#if defined (DO_SINGLE_STEP)
6360 break;
6361#endif
6362 }
2e70f6ef
PB		 6363 if (tb->cflags & CF_LAST_IO)
6364 gen_io_end();
e1833e1f 6365 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6366 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6367 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 6368 if (unlikely(env->singlestep_enabled)) {
6369 gen_update_nip(&ctx, ctx.nip);
6370 gen_op_debug();
6371 }
76a66253 6372 /* Generate the return instruction */
57fec1fe 6373 tcg_gen_exit_tb(0);
9a64fbe4 6374 }
2e70f6ef 6375 gen_icount_end(tb, num_insns);
79aceca5 6376 *gen_opc_ptr = INDEX_op_end;
76a66253 6377 if (unlikely(search_pc)) {
9a64fbe4
FB		 6378 j = gen_opc_ptr - gen_opc_buf;
6379 lj++;
6380 while (lj <= j)
6381 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6382 } else {
046d6672 6383 tb->size = ctx.nip - pc_start;
2e70f6ef 6384 tb->icount = num_insns;
9a64fbe4 6385 }
d9bce9d9 6386#if defined(DEBUG_DISAS)
9fddaa0c 6387 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6388 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6389 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6390 }
6391 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6392 int flags;
237c0af0 6393 flags = env->bfd_mach;
056401ea 6394 flags |= little_endian << 16;
0fa85d43 6395 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6396 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6397 fprintf(logfile, "\n");
9fddaa0c 6398 }
79aceca5 6399#endif
79aceca5
FB		 6400}
6401
2cfc5f17 6402void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 6403{
2cfc5f17 6404 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 6405}
6406
2cfc5f17 6407void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 6408{
2cfc5f17 6409 gen_intermediate_code_internal(env, tb, 1);
79aceca5 6410}
d2856f1a
AJ		 6411
6412void gen_pc_load(CPUState *env, TranslationBlock *tb,
6413 unsigned long searched_pc, int pc_pos, void *puc)
6414{
6415 int type, c;
6416 /* for PPC, we need to look at the micro operation to get the
6417 * access type */
6418 env->nip = gen_opc_pc[pc_pos];
6419 c = gen_opc_buf[pc_pos];
6420 switch(c) {
6421#if defined(CONFIG_USER_ONLY)
6422#define CASE3(op)\
6423 case INDEX_op_ ## op ## _raw
6424#else
6425#define CASE3(op)\
6426 case INDEX_op_ ## op ## _user:\
6427 case INDEX_op_ ## op ## _kernel:\
6428 case INDEX_op_ ## op ## _hypv
6429#endif
6430
6431 CASE3(stfd):
6432 CASE3(stfs):
6433 CASE3(lfd):
6434 CASE3(lfs):
6435 type = ACCESS_FLOAT;
6436 break;
6437 CASE3(lwarx):
6438 type = ACCESS_RES;
6439 break;
6440 CASE3(stwcx):
6441 type = ACCESS_RES;
6442 break;
6443 CASE3(eciwx):
6444 CASE3(ecowx):
6445 type = ACCESS_EXT;
6446 break;
6447 default:
6448 type = ACCESS_INT;
6449 break;
6450 }
6451 env->access_type = type;
6452}
Qemu copy for testing