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target-ppc: Add vrsqrtefp instruction
[qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
79aceca5 19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
e8fc4fa7 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
79aceca5 44
d12d51d5 45#ifdef PPC_DEBUG_DISAS
93fcfe39 46# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 47#else
48# define LOG_DISAS(...) do { } while (0)
49#endif
a750fc0b
JM		 50/*****************************************************************************/
51/* Code translation helpers */
c53be334 52
f78fb44e 53/* global register indexes */
a7812ae4 54static TCGv_ptr cpu_env;
1d542695 55static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 56#if !defined(TARGET_PPC64)
1d542695 57 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 58#endif
a5e26afa 59 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 60 + 2*(10*6 + 22*7) /* AVRh, AVRl */
61 + 8*5 /* CRF */];
f78fb44e
AJ		 62static TCGv cpu_gpr[32];
63#if !defined(TARGET_PPC64)
64static TCGv cpu_gprh[32];
65#endif
a7812ae4
PB		 66static TCGv_i64 cpu_fpr[32];
67static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
68static TCGv_i32 cpu_crf[8];
bd568f18 69static TCGv cpu_nip;
6527f6ea 70static TCGv cpu_msr;
cfdcd37a
AJ		 71static TCGv cpu_ctr;
72static TCGv cpu_lr;
3d7b417e 73static TCGv cpu_xer;
cf360a32 74static TCGv cpu_reserve;
a7812ae4 75static TCGv_i32 cpu_fpscr;
a7859e89 76static TCGv_i32 cpu_access_type;
f78fb44e 77
2e70f6ef
PB		 78#include "gen-icount.h"
79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
b2437bf2 84 static int done_init = 0;
f78fb44e 85
2e70f6ef
PB		 86 if (done_init)
87 return;
f78fb44e 88
a7812ae4 89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 90
f78fb44e 91 p = cpu_reg_names;
47e4661c
AJ		 92
93 for (i = 0; i < 8; i++) {
94 sprintf(p, "crf%d", i);
a7812ae4
PB		 95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 97 p += 5;
98 }
99
f78fb44e
AJ		 100 for (i = 0; i < 32; i++) {
101 sprintf(p, "r%d", i);
a7812ae4 102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 103 offsetof(CPUState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105#if !defined(TARGET_PPC64)
106 sprintf(p, "r%dH", i);
a7812ae4
PB		 107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 109 p += (i < 10) ? 4 : 5;
110#endif
1d542695 111
a5e26afa 112 sprintf(p, "fp%d", i);
a7812ae4
PB		 113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUState, fpr[i]), p);
ec1ac72d 115 p += (i < 10) ? 4 : 5;
a5e26afa 116
1d542695 117 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 118#ifdef WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
120 offsetof(CPUState, avr[i].u64[0]), p);
121#else
a7812ae4 122 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 123 offsetof(CPUState, avr[i].u64[1]), p);
124#endif
1d542695 125 p += (i < 10) ? 6 : 7;
ec1ac72d 126
1d542695 127 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 128#ifdef WORDS_BIGENDIAN
129 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
130 offsetof(CPUState, avr[i].u64[1]), p);
131#else
a7812ae4 132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 133 offsetof(CPUState, avr[i].u64[0]), p);
134#endif
1d542695 135 p += (i < 10) ? 6 : 7;
f78fb44e 136 }
f10dc08e 137
a7812ae4 138 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 139 offsetof(CPUState, nip), "nip");
140
6527f6ea
AJ		 141 cpu_msr = tcg_global_mem_new(TCG_AREG0,
142 offsetof(CPUState, msr), "msr");
143
a7812ae4 144 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 145 offsetof(CPUState, ctr), "ctr");
146
a7812ae4 147 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 148 offsetof(CPUState, lr), "lr");
149
a7812ae4 150 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 151 offsetof(CPUState, xer), "xer");
152
cf360a32
AJ		 153 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
154 offsetof(CPUState, reserve), "reserve");
155
a7812ae4
PB		 156 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
157 offsetof(CPUState, fpscr), "fpscr");
e1571908 158
a7859e89
AJ		 159 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
160 offsetof(CPUState, access_type), "access_type");
161
f10dc08e 162 /* register helpers */
a7812ae4 163#define GEN_HELPER 2
f10dc08e
AJ		 164#include "helper.h"
165
2e70f6ef
PB		 166 done_init = 1;
167}
168
79aceca5
FB		 169/* internal defines */
170typedef struct DisasContext {
171 struct TranslationBlock *tb;
0fa85d43 172 target_ulong nip;
79aceca5 173 uint32_t opcode;
9a64fbe4 174 uint32_t exception;
3cc62370
FB		 175 /* Routine used to access memory */
176 int mem_idx;
76db3ba4 177 int access_type;
3cc62370 178 /* Translation flags */
76db3ba4 179 int le_mode;
d9bce9d9
JM		 180#if defined(TARGET_PPC64)
181 int sf_mode;
9a64fbe4 182#endif
3cc62370 183 int fpu_enabled;
a9d9eb8f 184 int altivec_enabled;
0487d6a8 185 int spe_enabled;
3fc6c082 186 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 187 int singlestep_enabled;
79aceca5
FB		 188} DisasContext;
189
3fc6c082 190struct opc_handler_t {
79aceca5
FB		 191 /* invalid bits */
192 uint32_t inval;
9a64fbe4 193 /* instruction type */
0487d6a8 194 uint64_t type;
79aceca5
FB		 195 /* handler */
196 void (*handler)(DisasContext *ctx);
a750fc0b 197#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 198 const char *oname;
a750fc0b
JM		 199#endif
200#if defined(DO_PPC_STATISTICS)
76a66253
JM		 201 uint64_t count;
202#endif
3fc6c082 203};
79aceca5 204
7c58044c
JM		 205static always_inline void gen_reset_fpstatus (void)
206{
207#ifdef CONFIG_SOFTFLOAT
a44d2ce1 208 gen_helper_reset_fpstatus();
7c58044c
JM		 209#endif
210}
211
0f2f39c2 212static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 213{
0f2f39c2 214 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 215
7c58044c
JM		 216 if (set_fprf != 0) {
217 /* This case might be optimized later */
0f2f39c2 218 tcg_gen_movi_i32(t0, 1);
af12906f 219 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 220 if (unlikely(set_rc)) {
0f2f39c2 221 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 222 }
af12906f 223 gen_helper_float_check_status();
7c58044c
JM		 224 } else if (unlikely(set_rc)) {
225 /* We always need to compute fpcc */
0f2f39c2 226 tcg_gen_movi_i32(t0, 0);
af12906f 227 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 228 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 229 }
af12906f 230
0f2f39c2 231 tcg_temp_free_i32(t0);
7c58044c
JM		 232}
233
76db3ba4 234static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
a7859e89 235{
76db3ba4
AJ		 236 if (ctx->access_type != access_type) {
237 tcg_gen_movi_i32(cpu_access_type, access_type);
238 ctx->access_type = access_type;
239 }
a7859e89
AJ		 240}
241
b068d6a7 242static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 243{
244#if defined(TARGET_PPC64)
245 if (ctx->sf_mode)
bd568f18 246 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 247 else
248#endif
bd568f18 249 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 250}
251
e06fcd75
AJ		 252static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
253{
254 TCGv_i32 t0, t1;
255 if (ctx->exception == POWERPC_EXCP_NONE) {
256 gen_update_nip(ctx, ctx->nip);
257 }
258 t0 = tcg_const_i32(excp);
259 t1 = tcg_const_i32(error);
260 gen_helper_raise_exception_err(t0, t1);
261 tcg_temp_free_i32(t0);
262 tcg_temp_free_i32(t1);
263 ctx->exception = (excp);
264}
e1833e1f 265
e06fcd75
AJ		 266static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
267{
268 TCGv_i32 t0;
269 if (ctx->exception == POWERPC_EXCP_NONE) {
270 gen_update_nip(ctx, ctx->nip);
271 }
272 t0 = tcg_const_i32(excp);
273 gen_helper_raise_exception(t0);
274 tcg_temp_free_i32(t0);
275 ctx->exception = (excp);
276}
e1833e1f 277
e06fcd75
AJ		 278static always_inline void gen_debug_exception (DisasContext *ctx)
279{
280 TCGv_i32 t0;
281 gen_update_nip(ctx, ctx->nip);
282 t0 = tcg_const_i32(EXCP_DEBUG);
283 gen_helper_raise_exception(t0);
284 tcg_temp_free_i32(t0);
285}
9a64fbe4 286
e06fcd75
AJ		 287static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
288{
289 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
290}
a9d9eb8f 291
f24e5695 292/* Stop translation */
e06fcd75 293static always_inline void gen_stop_exception (DisasContext *ctx)
3fc6c082 294{
d9bce9d9 295 gen_update_nip(ctx, ctx->nip);
e1833e1f 296 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 297}
298
f24e5695 299/* No need to update nip here, as execution flow will change */
e06fcd75 300static always_inline void gen_sync_exception (DisasContext *ctx)
2be0071f 301{
e1833e1f 302 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 303}
304
79aceca5
FB		 305#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
306static void gen_##name (DisasContext *ctx); \
307GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
308static void gen_##name (DisasContext *ctx)
309
c7697e1f
JM		 310#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
311static void gen_##name (DisasContext *ctx); \
312GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
313static void gen_##name (DisasContext *ctx)
314
79aceca5
FB		 315typedef struct opcode_t {
316 unsigned char opc1, opc2, opc3;
1235fc06 317#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 318 unsigned char pad[5];
319#else
320 unsigned char pad[1];
321#endif
79aceca5 322 opc_handler_t handler;
b55266b5 323 const char *oname;
79aceca5
FB		 324} opcode_t;
325
a750fc0b 326/*****************************************************************************/
79aceca5
FB		 327/*** Instruction decoding ***/
328#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 329static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 330{ \
331 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
332}
333
334#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 335static always_inline int32_t name (uint32_t opcode) \
79aceca5 336{ \
18fba28c 337 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 338}
339
340/* Opcode part 1 */
341EXTRACT_HELPER(opc1, 26, 6);
342/* Opcode part 2 */
343EXTRACT_HELPER(opc2, 1, 5);
344/* Opcode part 3 */
345EXTRACT_HELPER(opc3, 6, 5);
346/* Update Cr0 flags */
347EXTRACT_HELPER(Rc, 0, 1);
348/* Destination */
349EXTRACT_HELPER(rD, 21, 5);
350/* Source */
351EXTRACT_HELPER(rS, 21, 5);
352/* First operand */
353EXTRACT_HELPER(rA, 16, 5);
354/* Second operand */
355EXTRACT_HELPER(rB, 11, 5);
356/* Third operand */
357EXTRACT_HELPER(rC, 6, 5);
358/*** Get CRn ***/
359EXTRACT_HELPER(crfD, 23, 3);
360EXTRACT_HELPER(crfS, 18, 3);
361EXTRACT_HELPER(crbD, 21, 5);
362EXTRACT_HELPER(crbA, 16, 5);
363EXTRACT_HELPER(crbB, 11, 5);
364/* SPR / TBL */
3fc6c082 365EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 366static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 367{
368 uint32_t sprn = _SPR(opcode);
369
370 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
371}
79aceca5
FB		 372/*** Get constants ***/
373EXTRACT_HELPER(IMM, 12, 8);
374/* 16 bits signed immediate value */
375EXTRACT_SHELPER(SIMM, 0, 16);
376/* 16 bits unsigned immediate value */
377EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 378/* 5 bits signed immediate value */
379EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 380/* 5 bits signed immediate value */
381EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 382/* Bit count */
383EXTRACT_HELPER(NB, 11, 5);
384/* Shift count */
385EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 386/* Vector shift count */
387EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 388/* Mask start */
389EXTRACT_HELPER(MB, 6, 5);
390/* Mask end */
391EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 392/* Trap operand */
393EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 394
395EXTRACT_HELPER(CRM, 12, 8);
396EXTRACT_HELPER(FM, 17, 8);
397EXTRACT_HELPER(SR, 16, 4);
e4bb997e 398EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 399
79aceca5
FB		 400/*** Jump target decoding ***/
401/* Displacement */
402EXTRACT_SHELPER(d, 0, 16);
403/* Immediate address */
b068d6a7 404static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 405{
406 return (opcode >> 0) & 0x03FFFFFC;
407}
408
b068d6a7 409static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 410{
411 return (opcode >> 0) & 0xFFFC;
412}
413
414EXTRACT_HELPER(BO, 21, 5);
415EXTRACT_HELPER(BI, 16, 5);
416/* Absolute/relative address */
417EXTRACT_HELPER(AA, 1, 1);
418/* Link */
419EXTRACT_HELPER(LK, 0, 1);
420
421/* Create a mask between <start> and <end> bits */
b068d6a7 422static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 423{
76a66253 424 target_ulong ret;
79aceca5 425
76a66253
JM		 426#if defined(TARGET_PPC64)
427 if (likely(start == 0)) {
6f2d8978 428 ret = UINT64_MAX << (63 - end);
76a66253 429 } else if (likely(end == 63)) {
6f2d8978 430 ret = UINT64_MAX >> start;
76a66253
JM		 431 }
432#else
433 if (likely(start == 0)) {
6f2d8978 434 ret = UINT32_MAX << (31 - end);
76a66253 435 } else if (likely(end == 31)) {
6f2d8978 436 ret = UINT32_MAX >> start;
76a66253
JM		 437 }
438#endif
439 else {
440 ret = (((target_ulong)(-1ULL)) >> (start)) ^
441 (((target_ulong)(-1ULL) >> (end)) >> 1);
442 if (unlikely(start > end))
443 return ~ret;
444 }
79aceca5
FB		 445
446 return ret;
447}
448
a750fc0b
JM		 449/*****************************************************************************/
450/* PowerPC Instructions types definitions */
451enum {
1b413d55 452 PPC_NONE = 0x0000000000000000ULL,
12de9a39 453 /* PowerPC base instructions set */
1b413d55
JM		 454 PPC_INSNS_BASE = 0x0000000000000001ULL,
455 /* integer operations instructions */
a750fc0b 456#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 457 /* flow control instructions */
a750fc0b 458#define PPC_FLOW PPC_INSNS_BASE
1b413d55 459 /* virtual memory instructions */
a750fc0b 460#define PPC_MEM PPC_INSNS_BASE
1b413d55 461 /* ld/st with reservation instructions */
a750fc0b 462#define PPC_RES PPC_INSNS_BASE
1b413d55 463 /* spr/msr access instructions */
a750fc0b 464#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 465 /* Deprecated instruction sets */
466 /* Original POWER instruction set */
f610349f 467 PPC_POWER = 0x0000000000000002ULL,
1b413d55 468 /* POWER2 instruction set extension */
f610349f 469 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 470 /* Power RTC support */
f610349f 471 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 472 /* Power-to-PowerPC bridge (601) */
f610349f 473 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 474 /* 64 bits PowerPC instruction set */
f610349f 475 PPC_64B = 0x0000000000000020ULL,
1b413d55 476 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 477 PPC_64BX = 0x0000000000000040ULL,
1b413d55 478 /* 64 bits hypervisor extensions */
f610349f 479 PPC_64H = 0x0000000000000080ULL,
1b413d55 480 /* New wait instruction (PowerPC 2.0x) */
f610349f 481 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 482 /* Time base mftb instruction */
f610349f 483 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 484
485 /* Fixed-point unit extensions */
486 /* PowerPC 602 specific */
f610349f 487 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 488 /* isel instruction */
489 PPC_ISEL = 0x0000000000000800ULL,
490 /* popcntb instruction */
491 PPC_POPCNTB = 0x0000000000001000ULL,
492 /* string load / store */
493 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 494
495 /* Floating-point unit extensions */
496 /* Optional floating point instructions */
497 PPC_FLOAT = 0x0000000000010000ULL,
498 /* New floating-point extensions (PowerPC 2.0x) */
499 PPC_FLOAT_EXT = 0x0000000000020000ULL,
500 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
501 PPC_FLOAT_FRES = 0x0000000000080000ULL,
502 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
503 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
504 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
505 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
506
507 /* Vector/SIMD extensions */
508 /* Altivec support */
509 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 510 /* PowerPC 2.03 SPE extension */
05332d70 511 PPC_SPE = 0x0000000002000000ULL,
1b413d55 512 /* PowerPC 2.03 SPE floating-point extension */
05332d70 513 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 514
12de9a39 515 /* Optional memory control instructions */
1b413d55
JM		 516 PPC_MEM_TLBIA = 0x0000000010000000ULL,
517 PPC_MEM_TLBIE = 0x0000000020000000ULL,
518 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
519 /* sync instruction */
520 PPC_MEM_SYNC = 0x0000000080000000ULL,
521 /* eieio instruction */
522 PPC_MEM_EIEIO = 0x0000000100000000ULL,
523
524 /* Cache control instructions */
c8623f2e 525 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 526 /* icbi instruction */
05332d70 527 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 528 /* dcbz instruction with fixed cache line size */
05332d70 529 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 530 /* dcbz instruction with tunable cache line size */
05332d70 531 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 532 /* dcba instruction */
05332d70
JM		 533 PPC_CACHE_DCBA = 0x0000002000000000ULL,
534 /* Freescale cache locking instructions */
535 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 536
537 /* MMU related extensions */
538 /* external control instructions */
05332d70 539 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 540 /* segment register access instructions */
05332d70 541 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 542 /* PowerPC 6xx TLB management instructions */
05332d70 543 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 544 /* PowerPC 74xx TLB management instructions */
05332d70 545 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 546 /* PowerPC 40x TLB management instructions */
05332d70 547 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 548 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 549 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 550 /* SLB management */
05332d70 551 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 552
12de9a39 553 /* Embedded PowerPC dedicated instructions */
05332d70 554 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 555 /* PowerPC 40x exception model */
05332d70 556 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 557 /* PowerPC 405 Mac instructions */
05332d70 558 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 559 /* PowerPC 440 specific instructions */
05332d70 560 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 561 /* BookE (embedded) PowerPC specification */
05332d70
JM		 562 PPC_BOOKE = 0x0010000000000000ULL,
563 /* mfapidi instruction */
564 PPC_MFAPIDI = 0x0020000000000000ULL,
565 /* tlbiva instruction */
566 PPC_TLBIVA = 0x0040000000000000ULL,
567 /* tlbivax instruction */
568 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 569 /* PowerPC 4xx dedicated instructions */
05332d70 570 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 571 /* PowerPC 40x ibct instructions */
05332d70 572 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 573 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 574 PPC_RFMCI = 0x0400000000000000ULL,
575 /* rfdi instruction */
576 PPC_RFDI = 0x0800000000000000ULL,
577 /* DCR accesses */
578 PPC_DCR = 0x1000000000000000ULL,
579 /* DCR extended accesse */
580 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 581 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 582 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 583};
584
585/*****************************************************************************/
586/* PowerPC instructions table */
3fc6c082
FB		 587#if HOST_LONG_BITS == 64
588#define OPC_ALIGN 8
589#else
590#define OPC_ALIGN 4
591#endif
1b039c09 592#if defined(__APPLE__)
d9bce9d9 593#define OPCODES_SECTION \
3fc6c082 594 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 595#else
d9bce9d9 596#define OPCODES_SECTION \
3fc6c082 597 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 598#endif
599
76a66253 600#if defined(DO_PPC_STATISTICS)
79aceca5 601#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 602OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 603 .opc1 = op1, \
604 .opc2 = op2, \
605 .opc3 = op3, \
18fba28c 606 .pad = { 0, }, \
79aceca5
FB		 607 .handler = { \
608 .inval = invl, \
9a64fbe4 609 .type = _typ, \
79aceca5 610 .handler = &gen_##name, \
76a66253 611 .oname = stringify(name), \
79aceca5 612 }, \
3fc6c082 613 .oname = stringify(name), \
79aceca5 614}
c7697e1f
JM		 615#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
616OPCODES_SECTION opcode_t opc_##name = { \
617 .opc1 = op1, \
618 .opc2 = op2, \
619 .opc3 = op3, \
620 .pad = { 0, }, \
621 .handler = { \
622 .inval = invl, \
623 .type = _typ, \
624 .handler = &gen_##name, \
625 .oname = onam, \
626 }, \
627 .oname = onam, \
628}
76a66253
JM		 629#else
630#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
631OPCODES_SECTION opcode_t opc_##name = { \
632 .opc1 = op1, \
633 .opc2 = op2, \
634 .opc3 = op3, \
635 .pad = { 0, }, \
636 .handler = { \
637 .inval = invl, \
638 .type = _typ, \
639 .handler = &gen_##name, \
640 }, \
641 .oname = stringify(name), \
642}
c7697e1f
JM		 643#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
644OPCODES_SECTION opcode_t opc_##name = { \
645 .opc1 = op1, \
646 .opc2 = op2, \
647 .opc3 = op3, \
648 .pad = { 0, }, \
649 .handler = { \
650 .inval = invl, \
651 .type = _typ, \
652 .handler = &gen_##name, \
653 }, \
654 .oname = onam, \
655}
76a66253 656#endif
79aceca5
FB		 657
658#define GEN_OPCODE_MARK(name) \
18fba28c 659OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 660 .opc1 = 0xFF, \
661 .opc2 = 0xFF, \
662 .opc3 = 0xFF, \
18fba28c 663 .pad = { 0, }, \
79aceca5
FB		 664 .handler = { \
665 .inval = 0x00000000, \
9a64fbe4 666 .type = 0x00, \
79aceca5
FB		 667 .handler = NULL, \
668 }, \
3fc6c082 669 .oname = stringify(name), \
79aceca5
FB		 670}
671
54cdcae6
AJ		 672/* SPR load/store helpers */
673static always_inline void gen_load_spr(TCGv t, int reg)
674{
675 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
676}
677
678static always_inline void gen_store_spr(int reg, TCGv t)
679{
680 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
681}
682
79aceca5
FB		 683/* Start opcode list */
684GEN_OPCODE_MARK(start);
685
686/* Invalid instruction */
9a64fbe4
FB		 687GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
688{
e06fcd75 689 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 690}
691
79aceca5
FB		 692static opc_handler_t invalid_handler = {
693 .inval = 0xFFFFFFFF,
9a64fbe4 694 .type = PPC_NONE,
79aceca5
FB		 695 .handler = gen_invalid,
696};
697
e1571908
AJ		 698/*** Integer comparison ***/
699
ea363694 700static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 701{
702 int l1, l2, l3;
703
269f3e95
AJ		 704 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
705 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 706 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
707
708 l1 = gen_new_label();
709 l2 = gen_new_label();
710 l3 = gen_new_label();
711 if (s) {
ea363694
AJ		 712 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
713 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 714 } else {
ea363694
AJ		 715 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
716 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 717 }
718 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
719 tcg_gen_br(l3);
720 gen_set_label(l1);
721 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
722 tcg_gen_br(l3);
723 gen_set_label(l2);
724 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
725 gen_set_label(l3);
726}
727
ea363694 728static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 729{
ea363694
AJ		 730 TCGv t0 = tcg_const_local_tl(arg1);
731 gen_op_cmp(arg0, t0, s, crf);
732 tcg_temp_free(t0);
e1571908
AJ		 733}
734
735#if defined(TARGET_PPC64)
ea363694 736static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 737{
ea363694 738 TCGv t0, t1;
a7812ae4
PB		 739 t0 = tcg_temp_local_new();
740 t1 = tcg_temp_local_new();
e1571908 741 if (s) {
ea363694
AJ		 742 tcg_gen_ext32s_tl(t0, arg0);
743 tcg_gen_ext32s_tl(t1, arg1);
e1571908 744 } else {
ea363694
AJ		 745 tcg_gen_ext32u_tl(t0, arg0);
746 tcg_gen_ext32u_tl(t1, arg1);
e1571908 747 }
ea363694
AJ		 748 gen_op_cmp(t0, t1, s, crf);
749 tcg_temp_free(t1);
750 tcg_temp_free(t0);
e1571908
AJ		 751}
752
ea363694 753static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 754{
ea363694
AJ		 755 TCGv t0 = tcg_const_local_tl(arg1);
756 gen_op_cmp32(arg0, t0, s, crf);
757 tcg_temp_free(t0);
e1571908
AJ		 758}
759#endif
760
761static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
762{
763#if defined(TARGET_PPC64)
764 if (!(ctx->sf_mode))
765 gen_op_cmpi32(reg, 0, 1, 0);
766 else
767#endif
768 gen_op_cmpi(reg, 0, 1, 0);
769}
770
771/* cmp */
772GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
773{
774#if defined(TARGET_PPC64)
775 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
776 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
777 1, crfD(ctx->opcode));
778 else
779#endif
780 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
781 1, crfD(ctx->opcode));
782}
783
784/* cmpi */
785GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
786{
787#if defined(TARGET_PPC64)
788 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
789 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
790 1, crfD(ctx->opcode));
791 else
792#endif
793 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
794 1, crfD(ctx->opcode));
795}
796
797/* cmpl */
798GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
799{
800#if defined(TARGET_PPC64)
801 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
802 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
803 0, crfD(ctx->opcode));
804 else
805#endif
806 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
807 0, crfD(ctx->opcode));
808}
809
810/* cmpli */
811GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
812{
813#if defined(TARGET_PPC64)
814 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
815 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
816 0, crfD(ctx->opcode));
817 else
818#endif
819 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
820 0, crfD(ctx->opcode));
821}
822
823/* isel (PowerPC 2.03 specification) */
824GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
825{
826 int l1, l2;
827 uint32_t bi = rC(ctx->opcode);
828 uint32_t mask;
a7812ae4 829 TCGv_i32 t0;
e1571908
AJ		 830
831 l1 = gen_new_label();
832 l2 = gen_new_label();
833
834 mask = 1 << (3 - (bi & 0x03));
a7812ae4 835 t0 = tcg_temp_new_i32();
fea0c503
AJ		 836 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
837 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 838 if (rA(ctx->opcode) == 0)
839 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
840 else
841 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
842 tcg_gen_br(l2);
843 gen_set_label(l1);
844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
845 gen_set_label(l2);
a7812ae4 846 tcg_temp_free_i32(t0);
e1571908
AJ		 847}
848
79aceca5 849/*** Integer arithmetic ***/
79aceca5 850
74637406
AJ		 851static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
852{
853 int l1;
854 TCGv t0;
79aceca5 855
74637406
AJ		 856 l1 = gen_new_label();
857 /* Start with XER OV disabled, the most likely case */
858 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 859 t0 = tcg_temp_local_new();
74637406
AJ		 860 tcg_gen_xor_tl(t0, arg0, arg1);
861#if defined(TARGET_PPC64)
862 if (!ctx->sf_mode)
863 tcg_gen_ext32s_tl(t0, t0);
864#endif
865 if (sub)
866 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
867 else
868 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
869 tcg_gen_xor_tl(t0, arg1, arg2);
870#if defined(TARGET_PPC64)
871 if (!ctx->sf_mode)
872 tcg_gen_ext32s_tl(t0, t0);
873#endif
874 if (sub)
875 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
876 else
877 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
878 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
879 gen_set_label(l1);
880 tcg_temp_free(t0);
79aceca5
FB		 881}
882
74637406
AJ		 883static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
884{
885 int l1 = gen_new_label();
d9bce9d9
JM		 886
887#if defined(TARGET_PPC64)
74637406
AJ		 888 if (!(ctx->sf_mode)) {
889 TCGv t0, t1;
a7812ae4
PB		 890 t0 = tcg_temp_new();
891 t1 = tcg_temp_new();
d9bce9d9 892
74637406
AJ		 893 tcg_gen_ext32u_tl(t0, arg1);
894 tcg_gen_ext32u_tl(t1, arg2);
895 if (sub) {
896 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 897 } else {
74637406
AJ		 898 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
899 }
a9730017
AJ		 900 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
901 gen_set_label(l1);
902 tcg_temp_free(t0);
903 tcg_temp_free(t1);
74637406
AJ		 904 } else
905#endif
a9730017
AJ		 906 {
907 if (sub) {
908 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
909 } else {
910 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
911 }
912 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
913 gen_set_label(l1);
74637406 914 }
d9bce9d9
JM		 915}
916
74637406
AJ		 917/* Common add function */
918static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
919 int add_ca, int compute_ca, int compute_ov)
920{
921 TCGv t0, t1;
d9bce9d9 922
74637406 923 if ((!compute_ca && !compute_ov) ||
a7812ae4 924 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 925 t0 = ret;
926 } else {
a7812ae4 927 t0 = tcg_temp_local_new();
74637406 928 }
79aceca5 929
74637406 930 if (add_ca) {
a7812ae4 931 t1 = tcg_temp_local_new();
74637406
AJ		 932 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
933 tcg_gen_shri_tl(t1, t1, XER_CA);
934 }
79aceca5 935
74637406
AJ		 936 if (compute_ca && compute_ov) {
937 /* Start with XER CA and OV disabled, the most likely case */
938 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
939 } else if (compute_ca) {
940 /* Start with XER CA disabled, the most likely case */
941 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
942 } else if (compute_ov) {
943 /* Start with XER OV disabled, the most likely case */
944 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
945 }
79aceca5 946
74637406
AJ		 947 tcg_gen_add_tl(t0, arg1, arg2);
948
949 if (compute_ca) {
950 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
951 }
952 if (add_ca) {
953 tcg_gen_add_tl(t0, t0, t1);
954 gen_op_arith_compute_ca(ctx, t0, t1, 0);
955 tcg_temp_free(t1);
956 }
957 if (compute_ov) {
958 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
959 }
960
961 if (unlikely(Rc(ctx->opcode) != 0))
962 gen_set_Rc0(ctx, t0);
963
a7812ae4 964 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 965 tcg_gen_mov_tl(ret, t0);
966 tcg_temp_free(t0);
967 }
39dd32ee 968}
74637406
AJ		 969/* Add functions with two operands */
970#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
971GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
972{ \
973 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
974 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
975 add_ca, compute_ca, compute_ov); \
976}
977/* Add functions with one operand and one immediate */
978#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
979 add_ca, compute_ca, compute_ov) \
980GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
981{ \
982 TCGv t0 = tcg_const_local_tl(const_val); \
983 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
984 cpu_gpr[rA(ctx->opcode)], t0, \
985 add_ca, compute_ca, compute_ov); \
986 tcg_temp_free(t0); \
987}
988
989/* add add. addo addo. */
990GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
991GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
992/* addc addc. addco addco. */
993GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
994GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
995/* adde adde. addeo addeo. */
996GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
997GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
998/* addme addme. addmeo addmeo. */
999GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1000GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1001/* addze addze. addzeo addzeo.*/
1002GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1003GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1004/* addi */
1005GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1006{
74637406
AJ		 1007 target_long simm = SIMM(ctx->opcode);
1008
1009 if (rA(ctx->opcode) == 0) {
1010 /* li case */
1011 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1012 } else {
1013 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1014 }
d9bce9d9 1015}
74637406
AJ		 1016/* addic addic.*/
1017static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1018 int compute_Rc0)
d9bce9d9 1019{
74637406
AJ		 1020 target_long simm = SIMM(ctx->opcode);
1021
1022 /* Start with XER CA and OV disabled, the most likely case */
1023 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1024
1025 if (likely(simm != 0)) {
a7812ae4 1026 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1027 tcg_gen_addi_tl(t0, arg1, simm);
1028 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1029 tcg_gen_mov_tl(ret, t0);
1030 tcg_temp_free(t0);
1031 } else {
1032 tcg_gen_mov_tl(ret, arg1);
1033 }
1034 if (compute_Rc0) {
1035 gen_set_Rc0(ctx, ret);
1036 }
d9bce9d9 1037}
74637406 1038GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1039{
74637406 1040 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1041}
74637406 1042GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1043{
74637406 1044 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1045}
74637406
AJ		 1046/* addis */
1047GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1048{
74637406
AJ		 1049 target_long simm = SIMM(ctx->opcode);
1050
1051 if (rA(ctx->opcode) == 0) {
1052 /* lis case */
1053 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1054 } else {
1055 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1056 }
d9bce9d9 1057}
74637406
AJ		 1058
1059static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1060 int sign, int compute_ov)
d9bce9d9 1061{
2ef1b120
AJ		 1062 int l1 = gen_new_label();
1063 int l2 = gen_new_label();
a7812ae4
PB		 1064 TCGv_i32 t0 = tcg_temp_local_new_i32();
1065 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1066
2ef1b120
AJ		 1067 tcg_gen_trunc_tl_i32(t0, arg1);
1068 tcg_gen_trunc_tl_i32(t1, arg2);
1069 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1070 if (sign) {
2ef1b120
AJ		 1071 int l3 = gen_new_label();
1072 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1073 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1074 gen_set_label(l3);
2ef1b120 1075 tcg_gen_div_i32(t0, t0, t1);
74637406 1076 } else {
2ef1b120 1077 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1078 }
1079 if (compute_ov) {
1080 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1081 }
1082 tcg_gen_br(l2);
1083 gen_set_label(l1);
1084 if (sign) {
2ef1b120 1085 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1086 } else {
1087 tcg_gen_movi_i32(t0, 0);
1088 }
1089 if (compute_ov) {
1090 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1091 }
1092 gen_set_label(l2);
2ef1b120 1093 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1094 tcg_temp_free_i32(t0);
1095 tcg_temp_free_i32(t1);
74637406
AJ		 1096 if (unlikely(Rc(ctx->opcode) != 0))
1097 gen_set_Rc0(ctx, ret);
d9bce9d9 1098}
74637406
AJ		 1099/* Div functions */
1100#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1101GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1102{ \
1103 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1104 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1105 sign, compute_ov); \
1106}
1107/* divwu divwu. divwuo divwuo. */
1108GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1109GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1110/* divw divw. divwo divwo. */
1111GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1112GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1113#if defined(TARGET_PPC64)
2ef1b120
AJ		 1114static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1115 int sign, int compute_ov)
d9bce9d9 1116{
2ef1b120
AJ		 1117 int l1 = gen_new_label();
1118 int l2 = gen_new_label();
74637406
AJ		 1119
1120 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1121 if (sign) {
2ef1b120 1122 int l3 = gen_new_label();
74637406
AJ		 1123 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1124 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1125 gen_set_label(l3);
74637406
AJ		 1126 tcg_gen_div_i64(ret, arg1, arg2);
1127 } else {
1128 tcg_gen_divu_i64(ret, arg1, arg2);
1129 }
1130 if (compute_ov) {
1131 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1132 }
1133 tcg_gen_br(l2);
1134 gen_set_label(l1);
1135 if (sign) {
1136 tcg_gen_sari_i64(ret, arg1, 63);
1137 } else {
1138 tcg_gen_movi_i64(ret, 0);
1139 }
1140 if (compute_ov) {
1141 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1142 }
1143 gen_set_label(l2);
1144 if (unlikely(Rc(ctx->opcode) != 0))
1145 gen_set_Rc0(ctx, ret);
d9bce9d9 1146}
74637406
AJ		 1147#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1148GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1149{ \
2ef1b120
AJ		 1150 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1151 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1152 sign, compute_ov); \
74637406
AJ		 1153}
1154/* divwu divwu. divwuo divwuo. */
1155GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1156GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1157/* divw divw. divwo divwo. */
1158GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1159GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1160#endif
74637406
AJ		 1161
1162/* mulhw mulhw. */
1163GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1164{
a7812ae4 1165 TCGv_i64 t0, t1;
74637406 1166
a7812ae4
PB		 1167 t0 = tcg_temp_new_i64();
1168 t1 = tcg_temp_new_i64();
74637406
AJ		 1169#if defined(TARGET_PPC64)
1170 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1171 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1172 tcg_gen_mul_i64(t0, t0, t1);
1173 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1174#else
1175 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1176 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1177 tcg_gen_mul_i64(t0, t0, t1);
1178 tcg_gen_shri_i64(t0, t0, 32);
1179 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1180#endif
a7812ae4
PB		 1181 tcg_temp_free_i64(t0);
1182 tcg_temp_free_i64(t1);
74637406
AJ		 1183 if (unlikely(Rc(ctx->opcode) != 0))
1184 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1185}
74637406
AJ		 1186/* mulhwu mulhwu. */
1187GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1188{
a7812ae4 1189 TCGv_i64 t0, t1;
74637406 1190
a7812ae4
PB		 1191 t0 = tcg_temp_new_i64();
1192 t1 = tcg_temp_new_i64();
d9bce9d9 1193#if defined(TARGET_PPC64)
74637406
AJ		 1194 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1195 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1196 tcg_gen_mul_i64(t0, t0, t1);
1197 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1198#else
1199 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1200 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1201 tcg_gen_mul_i64(t0, t0, t1);
1202 tcg_gen_shri_i64(t0, t0, 32);
1203 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1204#endif
a7812ae4
PB		 1205 tcg_temp_free_i64(t0);
1206 tcg_temp_free_i64(t1);
74637406
AJ		 1207 if (unlikely(Rc(ctx->opcode) != 0))
1208 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1209}
74637406
AJ		 1210/* mullw mullw. */
1211GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1212{
74637406
AJ		 1213 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1214 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1215 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1216 if (unlikely(Rc(ctx->opcode) != 0))
1217 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1218}
74637406
AJ		 1219/* mullwo mullwo. */
1220GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1221{
74637406 1222 int l1;
a7812ae4 1223 TCGv_i64 t0, t1;
74637406 1224
a7812ae4
PB		 1225 t0 = tcg_temp_new_i64();
1226 t1 = tcg_temp_new_i64();
74637406
AJ		 1227 l1 = gen_new_label();
1228 /* Start with XER OV disabled, the most likely case */
1229 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1230#if defined(TARGET_PPC64)
1231 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1232 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1233#else
1234 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1235 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1236#endif
74637406
AJ		 1237 tcg_gen_mul_i64(t0, t0, t1);
1238#if defined(TARGET_PPC64)
1239 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1240 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1241#else
1242 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1243 tcg_gen_ext32s_i64(t1, t0);
1244 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1245#endif
1246 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1247 gen_set_label(l1);
a7812ae4
PB		 1248 tcg_temp_free_i64(t0);
1249 tcg_temp_free_i64(t1);
74637406
AJ		 1250 if (unlikely(Rc(ctx->opcode) != 0))
1251 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1252}
74637406
AJ		 1253/* mulli */
1254GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1255{
74637406
AJ		 1256 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1257 SIMM(ctx->opcode));
d9bce9d9
JM		 1258}
1259#if defined(TARGET_PPC64)
74637406
AJ		 1260#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1261GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1262{ \
a7812ae4 1263 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1264 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1265 if (unlikely(Rc(ctx->opcode) != 0)) \
1266 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1267}
74637406
AJ		 1268/* mulhd mulhd. */
1269GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1270/* mulhdu mulhdu. */
1271GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1272/* mulld mulld. */
1273GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1274{
74637406
AJ		 1275 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1276 cpu_gpr[rB(ctx->opcode)]);
1277 if (unlikely(Rc(ctx->opcode) != 0))
1278 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1279}
74637406
AJ		 1280/* mulldo mulldo. */
1281GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1282#endif
74637406
AJ		 1283
1284/* neg neg. nego nego. */
ec6469a3 1285static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1286{
ec6469a3
AJ		 1287 int l1 = gen_new_label();
1288 int l2 = gen_new_label();
a7812ae4 1289 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1290#if defined(TARGET_PPC64)
74637406 1291 if (ctx->sf_mode) {
741a7444 1292 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1293 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1294 } else
1295#endif
1296 {
1297 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1298 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1299 }
74637406
AJ		 1300 tcg_gen_neg_tl(ret, arg1);
1301 if (ov_check) {
1302 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1303 }
1304 tcg_gen_br(l2);
1305 gen_set_label(l1);
ec6469a3 1306 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1307 if (ov_check) {
1308 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1309 }
1310 gen_set_label(l2);
ec6469a3 1311 tcg_temp_free(t0);
74637406
AJ		 1312 if (unlikely(Rc(ctx->opcode) != 0))
1313 gen_set_Rc0(ctx, ret);
1314}
1315GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1316{
ec6469a3 1317 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1318}
74637406 1319GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1320{
ec6469a3 1321 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1322}
74637406
AJ		 1323
1324/* Common subf function */
1325static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1326 int add_ca, int compute_ca, int compute_ov)
79aceca5 1327{
74637406 1328 TCGv t0, t1;
76a66253 1329
74637406 1330 if ((!compute_ca && !compute_ov) ||
a7812ae4 1331 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1332 t0 = ret;
e864cabd 1333 } else {
a7812ae4 1334 t0 = tcg_temp_local_new();
d9bce9d9 1335 }
76a66253 1336
74637406 1337 if (add_ca) {
a7812ae4 1338 t1 = tcg_temp_local_new();
74637406
AJ		 1339 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1340 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1341 }
79aceca5 1342
74637406
AJ		 1343 if (compute_ca && compute_ov) {
1344 /* Start with XER CA and OV disabled, the most likely case */
1345 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1346 } else if (compute_ca) {
1347 /* Start with XER CA disabled, the most likely case */
1348 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1349 } else if (compute_ov) {
1350 /* Start with XER OV disabled, the most likely case */
1351 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1352 }
1353
1354 if (add_ca) {
1355 tcg_gen_not_tl(t0, arg1);
1356 tcg_gen_add_tl(t0, t0, arg2);
1357 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1358 tcg_gen_add_tl(t0, t0, t1);
1359 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1360 tcg_temp_free(t1);
79aceca5 1361 } else {
74637406
AJ		 1362 tcg_gen_sub_tl(t0, arg2, arg1);
1363 if (compute_ca) {
1364 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1365 }
1366 }
1367 if (compute_ov) {
1368 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1369 }
1370
1371 if (unlikely(Rc(ctx->opcode) != 0))
1372 gen_set_Rc0(ctx, t0);
1373
a7812ae4 1374 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1375 tcg_gen_mov_tl(ret, t0);
1376 tcg_temp_free(t0);
79aceca5 1377 }
79aceca5 1378}
74637406
AJ		 1379/* Sub functions with Two operands functions */
1380#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1381GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1382{ \
1383 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1384 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1385 add_ca, compute_ca, compute_ov); \
1386}
1387/* Sub functions with one operand and one immediate */
1388#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1389 add_ca, compute_ca, compute_ov) \
1390GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1391{ \
1392 TCGv t0 = tcg_const_local_tl(const_val); \
1393 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1394 cpu_gpr[rA(ctx->opcode)], t0, \
1395 add_ca, compute_ca, compute_ov); \
1396 tcg_temp_free(t0); \
1397}
1398/* subf subf. subfo subfo. */
1399GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1400GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1401/* subfc subfc. subfco subfco. */
1402GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1403GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1404/* subfe subfe. subfeo subfo. */
1405GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1406GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1407/* subfme subfme. subfmeo subfmeo. */
1408GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1409GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1410/* subfze subfze. subfzeo subfzeo.*/
1411GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1412GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1413/* subfic */
1414GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1415{
74637406
AJ		 1416 /* Start with XER CA and OV disabled, the most likely case */
1417 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1418 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1419 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1420 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1421 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1422 tcg_temp_free(t1);
1423 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1424 tcg_temp_free(t0);
79aceca5
FB		 1425}
1426
79aceca5 1427/*** Integer logical ***/
26d67362
AJ		 1428#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1429GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1430{ \
26d67362
AJ		 1431 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1432 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1433 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1434 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1435}
79aceca5 1436
26d67362 1437#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1438GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1439{ \
26d67362 1440 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1441 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1442 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1443}
1444
1445/* and & and. */
26d67362 1446GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1447/* andc & andc. */
26d67362 1448GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1449/* andi. */
c7697e1f 1450GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1451{
26d67362
AJ		 1452 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1453 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1454}
1455/* andis. */
c7697e1f 1456GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1457{
26d67362
AJ		 1458 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1459 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1460}
79aceca5 1461/* cntlzw */
26d67362
AJ		 1462GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1463{
a7812ae4 1464 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1465 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1466 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1467}
79aceca5 1468/* eqv & eqv. */
26d67362 1469GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1470/* extsb & extsb. */
26d67362 1471GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1472/* extsh & extsh. */
26d67362 1473GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1474/* nand & nand. */
26d67362 1475GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1476/* nor & nor. */
26d67362 1477GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1478/* or & or. */
9a64fbe4
FB		 1479GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1480{
76a66253
JM		 1481 int rs, ra, rb;
1482
1483 rs = rS(ctx->opcode);
1484 ra = rA(ctx->opcode);
1485 rb = rB(ctx->opcode);
1486 /* Optimisation for mr. ri case */
1487 if (rs != ra || rs != rb) {
26d67362
AJ		 1488 if (rs != rb)
1489 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1490 else
1491 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1492 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1493 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1494 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1495 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1496#if defined(TARGET_PPC64)
1497 } else {
26d67362
AJ		 1498 int prio = 0;
1499
c80f84e3
JM		 1500 switch (rs) {
1501 case 1:
1502 /* Set process priority to low */
26d67362 1503 prio = 2;
c80f84e3
JM		 1504 break;
1505 case 6:
1506 /* Set process priority to medium-low */
26d67362 1507 prio = 3;
c80f84e3
JM		 1508 break;
1509 case 2:
1510 /* Set process priority to normal */
26d67362 1511 prio = 4;
c80f84e3 1512 break;
be147d08
JM		 1513#if !defined(CONFIG_USER_ONLY)
1514 case 31:
76db3ba4 1515 if (ctx->mem_idx > 0) {
be147d08 1516 /* Set process priority to very low */
26d67362 1517 prio = 1;
be147d08
JM		 1518 }
1519 break;
1520 case 5:
76db3ba4 1521 if (ctx->mem_idx > 0) {
be147d08 1522 /* Set process priority to medium-hight */
26d67362 1523 prio = 5;
be147d08
JM		 1524 }
1525 break;
1526 case 3:
76db3ba4 1527 if (ctx->mem_idx > 0) {
be147d08 1528 /* Set process priority to high */
26d67362 1529 prio = 6;
be147d08
JM		 1530 }
1531 break;
be147d08 1532 case 7:
76db3ba4 1533 if (ctx->mem_idx > 1) {
be147d08 1534 /* Set process priority to very high */
26d67362 1535 prio = 7;
be147d08
JM		 1536 }
1537 break;
be147d08 1538#endif
c80f84e3
JM		 1539 default:
1540 /* nop */
1541 break;
1542 }
26d67362 1543 if (prio) {
a7812ae4 1544 TCGv t0 = tcg_temp_new();
54cdcae6 1545 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1546 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1547 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1548 gen_store_spr(SPR_PPR, t0);
ea363694 1549 tcg_temp_free(t0);
26d67362 1550 }
c80f84e3 1551#endif
9a64fbe4 1552 }
9a64fbe4 1553}
79aceca5 1554/* orc & orc. */
26d67362 1555GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1556/* xor & xor. */
9a64fbe4
FB		 1557GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1558{
9a64fbe4 1559 /* Optimisation for "set to zero" case */
26d67362 1560 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1561 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1562 else
1563 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1564 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1565 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1566}
79aceca5
FB		 1567/* ori */
1568GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1569{
76a66253 1570 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1571
9a64fbe4
FB		 1572 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1573 /* NOP */
76a66253 1574 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1575 return;
76a66253 1576 }
26d67362 1577 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1578}
1579/* oris */
1580GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1581{
76a66253 1582 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1583
9a64fbe4
FB		 1584 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1585 /* NOP */
1586 return;
76a66253 1587 }
26d67362 1588 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1589}
1590/* xori */
1591GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1592{
76a66253 1593 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1594
1595 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1596 /* NOP */
1597 return;
1598 }
26d67362 1599 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1600}
79aceca5
FB		 1601/* xoris */
1602GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1603{
76a66253 1604 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1605
1606 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1607 /* NOP */
1608 return;
1609 }
26d67362 1610 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1611}
d9bce9d9 1612/* popcntb : PowerPC 2.03 specification */
05332d70 1613GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1614{
d9bce9d9
JM		 1615#if defined(TARGET_PPC64)
1616 if (ctx->sf_mode)
a7812ae4 1617 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1618 else
1619#endif
a7812ae4 1620 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1621}
1622
1623#if defined(TARGET_PPC64)
1624/* extsw & extsw. */
26d67362 1625GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1626/* cntlzd */
26d67362
AJ		 1627GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1628{
a7812ae4 1629 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1630 if (unlikely(Rc(ctx->opcode) != 0))
1631 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1632}
d9bce9d9
JM		 1633#endif
1634
79aceca5
FB		 1635/*** Integer rotate ***/
1636/* rlwimi & rlwimi. */
1637GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1638{
76a66253 1639 uint32_t mb, me, sh;
79aceca5
FB		 1640
1641 mb = MB(ctx->opcode);
1642 me = ME(ctx->opcode);
76a66253 1643 sh = SH(ctx->opcode);
d03ef511
AJ		 1644 if (likely(sh == 0 && mb == 0 && me == 31)) {
1645 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1646 } else {
d03ef511 1647 target_ulong mask;
a7812ae4
PB		 1648 TCGv t1;
1649 TCGv t0 = tcg_temp_new();
54843a58 1650#if defined(TARGET_PPC64)
a7812ae4
PB		 1651 TCGv_i32 t2 = tcg_temp_new_i32();
1652 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1653 tcg_gen_rotli_i32(t2, t2, sh);
1654 tcg_gen_extu_i32_i64(t0, t2);
1655 tcg_temp_free_i32(t2);
54843a58
AJ		 1656#else
1657 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1658#endif
76a66253 1659#if defined(TARGET_PPC64)
d03ef511
AJ		 1660 mb += 32;
1661 me += 32;
76a66253 1662#endif
d03ef511 1663 mask = MASK(mb, me);
a7812ae4 1664 t1 = tcg_temp_new();
d03ef511
AJ		 1665 tcg_gen_andi_tl(t0, t0, mask);
1666 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1667 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1668 tcg_temp_free(t0);
1669 tcg_temp_free(t1);
1670 }
76a66253 1671 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1672 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1673}
1674/* rlwinm & rlwinm. */
1675GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1676{
1677 uint32_t mb, me, sh;
3b46e624 1678
79aceca5
FB		 1679 sh = SH(ctx->opcode);
1680 mb = MB(ctx->opcode);
1681 me = ME(ctx->opcode);
d03ef511
AJ		 1682
1683 if (likely(mb == 0 && me == (31 - sh))) {
1684 if (likely(sh == 0)) {
1685 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1686 } else {
a7812ae4 1687 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1688 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1689 tcg_gen_shli_tl(t0, t0, sh);
1690 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1691 tcg_temp_free(t0);
79aceca5 1692 }
d03ef511 1693 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1694 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1695 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1696 tcg_gen_shri_tl(t0, t0, mb);
1697 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1698 tcg_temp_free(t0);
1699 } else {
a7812ae4 1700 TCGv t0 = tcg_temp_new();
54843a58 1701#if defined(TARGET_PPC64)
a7812ae4 1702 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1703 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1704 tcg_gen_rotli_i32(t1, t1, sh);
1705 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1706 tcg_temp_free_i32(t1);
54843a58
AJ		 1707#else
1708 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1709#endif
76a66253 1710#if defined(TARGET_PPC64)
d03ef511
AJ		 1711 mb += 32;
1712 me += 32;
76a66253 1713#endif
d03ef511
AJ		 1714 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1715 tcg_temp_free(t0);
1716 }
76a66253 1717 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1718 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1719}
1720/* rlwnm & rlwnm. */
1721GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1722{
1723 uint32_t mb, me;
54843a58
AJ		 1724 TCGv t0;
1725#if defined(TARGET_PPC64)
a7812ae4 1726 TCGv_i32 t1, t2;
54843a58 1727#endif
79aceca5
FB		 1728
1729 mb = MB(ctx->opcode);
1730 me = ME(ctx->opcode);
a7812ae4 1731 t0 = tcg_temp_new();
d03ef511 1732 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1733#if defined(TARGET_PPC64)
a7812ae4
PB		 1734 t1 = tcg_temp_new_i32();
1735 t2 = tcg_temp_new_i32();
54843a58
AJ		 1736 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1737 tcg_gen_trunc_i64_i32(t2, t0);
1738 tcg_gen_rotl_i32(t1, t1, t2);
1739 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1740 tcg_temp_free_i32(t1);
1741 tcg_temp_free_i32(t2);
54843a58
AJ		 1742#else
1743 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1744#endif
76a66253
JM		 1745 if (unlikely(mb != 0 || me != 31)) {
1746#if defined(TARGET_PPC64)
1747 mb += 32;
1748 me += 32;
1749#endif
54843a58 1750 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1751 } else {
54843a58 1752 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1753 }
54843a58 1754 tcg_temp_free(t0);
76a66253 1755 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1756 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1757}
1758
d9bce9d9
JM		 1759#if defined(TARGET_PPC64)
1760#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1761GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1762{ \
1763 gen_##name(ctx, 0); \
1764} \
c7697e1f
JM		 1765GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1766 PPC_64B) \
d9bce9d9
JM		 1767{ \
1768 gen_##name(ctx, 1); \
1769}
1770#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1771GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1772{ \
1773 gen_##name(ctx, 0, 0); \
1774} \
c7697e1f
JM		 1775GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1776 PPC_64B) \
d9bce9d9
JM		 1777{ \
1778 gen_##name(ctx, 0, 1); \
1779} \
c7697e1f
JM		 1780GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1781 PPC_64B) \
d9bce9d9
JM		 1782{ \
1783 gen_##name(ctx, 1, 0); \
1784} \
c7697e1f
JM		 1785GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1786 PPC_64B) \
d9bce9d9
JM		 1787{ \
1788 gen_##name(ctx, 1, 1); \
1789}
51789c41 1790
b068d6a7
JM		 1791static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1792 uint32_t me, uint32_t sh)
51789c41 1793{
d03ef511
AJ		 1794 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1795 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1796 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1797 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1798 } else {
a7812ae4 1799 TCGv t0 = tcg_temp_new();
54843a58 1800 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1801 if (likely(mb == 0 && me == 63)) {
54843a58 1802 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1803 } else {
1804 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1805 }
d03ef511 1806 tcg_temp_free(t0);
51789c41 1807 }
51789c41 1808 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1809 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1810}
d9bce9d9 1811/* rldicl - rldicl. */
b068d6a7 1812static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1813{
51789c41 1814 uint32_t sh, mb;
d9bce9d9 1815
9d53c753
JM		 1816 sh = SH(ctx->opcode) | (shn << 5);
1817 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1818 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1819}
51789c41 1820GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1821/* rldicr - rldicr. */
b068d6a7 1822static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1823{
51789c41 1824 uint32_t sh, me;
d9bce9d9 1825
9d53c753
JM		 1826 sh = SH(ctx->opcode) | (shn << 5);
1827 me = MB(ctx->opcode) | (men << 5);
51789c41 1828 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1829}
51789c41 1830GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1831/* rldic - rldic. */
b068d6a7 1832static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1833{
51789c41 1834 uint32_t sh, mb;
d9bce9d9 1835
9d53c753
JM		 1836 sh = SH(ctx->opcode) | (shn << 5);
1837 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1838 gen_rldinm(ctx, mb, 63 - sh, sh);
1839}
1840GEN_PPC64_R4(rldic, 0x1E, 0x04);
1841
b068d6a7
JM		 1842static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1843 uint32_t me)
51789c41 1844{
54843a58 1845 TCGv t0;
d03ef511
AJ		 1846
1847 mb = MB(ctx->opcode);
1848 me = ME(ctx->opcode);
a7812ae4 1849 t0 = tcg_temp_new();
d03ef511 1850 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1851 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1852 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1853 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1854 } else {
1855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1856 }
1857 tcg_temp_free(t0);
51789c41 1858 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1859 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1860}
51789c41 1861
d9bce9d9 1862/* rldcl - rldcl. */
b068d6a7 1863static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1864{
51789c41 1865 uint32_t mb;
d9bce9d9 1866
9d53c753 1867 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1868 gen_rldnm(ctx, mb, 63);
d9bce9d9 1869}
36081602 1870GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1871/* rldcr - rldcr. */
b068d6a7 1872static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1873{
51789c41 1874 uint32_t me;
d9bce9d9 1875
9d53c753 1876 me = MB(ctx->opcode) | (men << 5);
51789c41 1877 gen_rldnm(ctx, 0, me);
d9bce9d9 1878}
36081602 1879GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1880/* rldimi - rldimi. */
b068d6a7 1881static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1882{
271a916e 1883 uint32_t sh, mb, me;
d9bce9d9 1884
9d53c753
JM		 1885 sh = SH(ctx->opcode) | (shn << 5);
1886 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1887 me = 63 - sh;
d03ef511
AJ		 1888 if (unlikely(sh == 0 && mb == 0)) {
1889 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1890 } else {
1891 TCGv t0, t1;
1892 target_ulong mask;
1893
a7812ae4 1894 t0 = tcg_temp_new();
54843a58 1895 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1896 t1 = tcg_temp_new();
d03ef511
AJ		 1897 mask = MASK(mb, me);
1898 tcg_gen_andi_tl(t0, t0, mask);
1899 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1900 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1901 tcg_temp_free(t0);
1902 tcg_temp_free(t1);
51789c41 1903 }
51789c41 1904 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1905 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1906}
36081602 1907GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1908#endif
1909
79aceca5
FB		 1910/*** Integer shift ***/
1911/* slw & slw. */
26d67362
AJ		 1912GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1913{
fea0c503 1914 TCGv t0;
26d67362
AJ		 1915 int l1, l2;
1916 l1 = gen_new_label();
1917 l2 = gen_new_label();
1918
a7812ae4 1919 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1920 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1921 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1922 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1923 tcg_gen_br(l2);
1924 gen_set_label(l1);
fea0c503 1925 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1926 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1927 gen_set_label(l2);
fea0c503 1928 tcg_temp_free(t0);
26d67362
AJ		 1929 if (unlikely(Rc(ctx->opcode) != 0))
1930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1931}
79aceca5 1932/* sraw & sraw. */
26d67362
AJ		 1933GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1934{
a7812ae4
PB		 1935 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1936 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1937 if (unlikely(Rc(ctx->opcode) != 0))
1938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1939}
79aceca5
FB		 1940/* srawi & srawi. */
1941GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1942{
26d67362
AJ		 1943 int sh = SH(ctx->opcode);
1944 if (sh != 0) {
1945 int l1, l2;
fea0c503 1946 TCGv t0;
26d67362
AJ		 1947 l1 = gen_new_label();
1948 l2 = gen_new_label();
a7812ae4 1949 t0 = tcg_temp_local_new();
fea0c503
AJ		 1950 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1951 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1952 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1953 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1954 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1955 tcg_gen_br(l2);
1956 gen_set_label(l1);
269f3e95 1957 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1958 gen_set_label(l2);
fea0c503
AJ		 1959 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1960 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1961 tcg_temp_free(t0);
26d67362
AJ		 1962 } else {
1963 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1964 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1965 }
76a66253 1966 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1967 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1968}
1969/* srw & srw. */
26d67362
AJ		 1970GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1971{
fea0c503 1972 TCGv t0, t1;
26d67362
AJ		 1973 int l1, l2;
1974 l1 = gen_new_label();
1975 l2 = gen_new_label();
d9bce9d9 1976
a7812ae4 1977 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1978 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1979 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1980 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1981 tcg_gen_br(l2);
1982 gen_set_label(l1);
a7812ae4 1983 t1 = tcg_temp_new();
fea0c503
AJ		 1984 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1985 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1986 tcg_temp_free(t1);
26d67362 1987 gen_set_label(l2);
fea0c503 1988 tcg_temp_free(t0);
26d67362
AJ		 1989 if (unlikely(Rc(ctx->opcode) != 0))
1990 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1991}
d9bce9d9
JM		 1992#if defined(TARGET_PPC64)
1993/* sld & sld. */
26d67362
AJ		 1994GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1995{
fea0c503 1996 TCGv t0;
26d67362
AJ		 1997 int l1, l2;
1998 l1 = gen_new_label();
1999 l2 = gen_new_label();
2000
a7812ae4 2001 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2002 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2003 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2004 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2005 tcg_gen_br(l2);
2006 gen_set_label(l1);
fea0c503 2007 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2008 gen_set_label(l2);
fea0c503 2009 tcg_temp_free(t0);
26d67362
AJ		 2010 if (unlikely(Rc(ctx->opcode) != 0))
2011 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2012}
d9bce9d9 2013/* srad & srad. */
26d67362
AJ		 2014GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2015{
a7812ae4
PB		 2016 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2017 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2018 if (unlikely(Rc(ctx->opcode) != 0))
2019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2020}
d9bce9d9 2021/* sradi & sradi. */
b068d6a7 2022static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2023{
26d67362 2024 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2025 if (sh != 0) {
26d67362 2026 int l1, l2;
fea0c503 2027 TCGv t0;
26d67362
AJ		 2028 l1 = gen_new_label();
2029 l2 = gen_new_label();
a7812ae4 2030 t0 = tcg_temp_local_new();
26d67362 2031 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2032 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2033 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2034 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2035 tcg_gen_br(l2);
2036 gen_set_label(l1);
269f3e95 2037 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2038 gen_set_label(l2);
a9730017 2039 tcg_temp_free(t0);
26d67362
AJ		 2040 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2041 } else {
2042 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2043 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2044 }
d9bce9d9 2045 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2046 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2047}
c7697e1f 2048GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2049{
2050 gen_sradi(ctx, 0);
2051}
c7697e1f 2052GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2053{
2054 gen_sradi(ctx, 1);
2055}
2056/* srd & srd. */
26d67362
AJ		 2057GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2058{
fea0c503 2059 TCGv t0;
26d67362
AJ		 2060 int l1, l2;
2061 l1 = gen_new_label();
2062 l2 = gen_new_label();
2063
a7812ae4 2064 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2065 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2066 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2067 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2068 tcg_gen_br(l2);
2069 gen_set_label(l1);
fea0c503 2070 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2071 gen_set_label(l2);
fea0c503 2072 tcg_temp_free(t0);
26d67362
AJ		 2073 if (unlikely(Rc(ctx->opcode) != 0))
2074 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2075}
d9bce9d9 2076#endif
79aceca5
FB		 2077
2078/*** Floating-Point arithmetic ***/
7c58044c 2079#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2080GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2081{ \
76a66253 2082 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2083 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2084 return; \
2085 } \
eb44b959
AJ		 2086 /* NIP cannot be restored if the memory exception comes from an helper */ \
2087 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2088 gen_reset_fpstatus(); \
af12906f
AJ		 2089 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2090 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2091 if (isfloat) { \
af12906f 2092 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2093 } \
af12906f
AJ		 2094 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2095 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2096}
2097
7c58044c
JM		 2098#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2099_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2100_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2101
7c58044c
JM		 2102#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2103GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2104{ \
76a66253 2105 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2106 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2107 return; \
2108 } \
eb44b959
AJ		 2109 /* NIP cannot be restored if the memory exception comes from an helper */ \
2110 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2111 gen_reset_fpstatus(); \
af12906f
AJ		 2112 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2113 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2114 if (isfloat) { \
af12906f 2115 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2116 } \
af12906f
AJ		 2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2118 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2119}
7c58044c
JM		 2120#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2121_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2122_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2123
7c58044c
JM		 2124#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2125GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2126{ \
76a66253 2127 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2128 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2129 return; \
2130 } \
eb44b959
AJ		 2131 /* NIP cannot be restored if the memory exception comes from an helper */ \
2132 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2133 gen_reset_fpstatus(); \
af12906f
AJ		 2134 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2135 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2136 if (isfloat) { \
af12906f 2137 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2138 } \
af12906f
AJ		 2139 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2140 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2141}
7c58044c
JM		 2142#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2143_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2144_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2145
7c58044c 2146#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2147GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2148{ \
76a66253 2149 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2150 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2151 return; \
2152 } \
eb44b959
AJ		 2153 /* NIP cannot be restored if the memory exception comes from an helper */ \
2154 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2155 gen_reset_fpstatus(); \
af12906f
AJ		 2156 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2157 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2158 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2159}
2160
7c58044c 2161#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2162GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2163{ \
76a66253 2164 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2165 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2166 return; \
2167 } \
eb44b959
AJ		 2168 /* NIP cannot be restored if the memory exception comes from an helper */ \
2169 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2170 gen_reset_fpstatus(); \
af12906f
AJ		 2171 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2172 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2173 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2174}
2175
9a64fbe4 2176/* fadd - fadds */
7c58044c 2177GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2178/* fdiv - fdivs */
7c58044c 2179GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2180/* fmul - fmuls */
7c58044c 2181GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2182
d7e4b87e 2183/* fre */
7c58044c 2184GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2185
a750fc0b 2186/* fres */
7c58044c 2187GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2188
a750fc0b 2189/* frsqrte */
7c58044c
JM		 2190GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2191
2192/* frsqrtes */
af12906f 2193GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2194{
af12906f 2195 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2196 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2197 return;
2198 }
eb44b959
AJ		 2199 /* NIP cannot be restored if the memory exception comes from an helper */
2200 gen_update_nip(ctx, ctx->nip - 4);
af12906f
AJ		 2201 gen_reset_fpstatus();
2202 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2203 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2204 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2205}
79aceca5 2206
a750fc0b 2207/* fsel */
7c58044c 2208_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2209/* fsub - fsubs */
7c58044c 2210GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2211/* Optional: */
2212/* fsqrt */
a750fc0b 2213GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2214{
76a66253 2215 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2216 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2217 return;
2218 }
eb44b959
AJ		 2219 /* NIP cannot be restored if the memory exception comes from an helper */
2220 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2221 gen_reset_fpstatus();
af12906f
AJ		 2222 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2223 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2224}
79aceca5 2225
a750fc0b 2226GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2227{
76a66253 2228 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2229 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2230 return;
2231 }
eb44b959
AJ		 2232 /* NIP cannot be restored if the memory exception comes from an helper */
2233 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2234 gen_reset_fpstatus();
af12906f
AJ		 2235 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2236 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2237 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2238}
2239
2240/*** Floating-Point multiply-and-add ***/
4ecc3190 2241/* fmadd - fmadds */
7c58044c 2242GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2243/* fmsub - fmsubs */
7c58044c 2244GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2245/* fnmadd - fnmadds */
7c58044c 2246GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2247/* fnmsub - fnmsubs */
7c58044c 2248GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2249
2250/*** Floating-Point round & convert ***/
2251/* fctiw */
7c58044c 2252GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2253/* fctiwz */
7c58044c 2254GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2255/* frsp */
7c58044c 2256GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2257#if defined(TARGET_PPC64)
2258/* fcfid */
7c58044c 2259GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2260/* fctid */
7c58044c 2261GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2262/* fctidz */
7c58044c 2263GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2264#endif
79aceca5 2265
d7e4b87e 2266/* frin */
7c58044c 2267GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2268/* friz */
7c58044c 2269GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2270/* frip */
7c58044c 2271GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2272/* frim */
7c58044c 2273GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2274
79aceca5
FB		 2275/*** Floating-Point compare ***/
2276/* fcmpo */
76a66253 2277GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2278{
330c483b 2279 TCGv_i32 crf;
76a66253 2280 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2281 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2282 return;
2283 }
eb44b959
AJ		 2284 /* NIP cannot be restored if the memory exception comes from an helper */
2285 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2286 gen_reset_fpstatus();
9a819377
AJ		 2287 crf = tcg_const_i32(crfD(ctx->opcode));
2288 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2289 tcg_temp_free_i32(crf);
af12906f 2290 gen_helper_float_check_status();
79aceca5
FB		 2291}
2292
2293/* fcmpu */
76a66253 2294GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2295{
330c483b 2296 TCGv_i32 crf;
76a66253 2297 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2298 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2299 return;
2300 }
eb44b959
AJ		 2301 /* NIP cannot be restored if the memory exception comes from an helper */
2302 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2303 gen_reset_fpstatus();
9a819377
AJ		 2304 crf = tcg_const_i32(crfD(ctx->opcode));
2305 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2306 tcg_temp_free_i32(crf);
af12906f 2307 gen_helper_float_check_status();
79aceca5
FB		 2308}
2309
9a64fbe4
FB		 2310/*** Floating-point move ***/
2311/* fabs */
7c58044c
JM		 2312/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2313GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2314
2315/* fmr - fmr. */
7c58044c 2316/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2317GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2318{
76a66253 2319 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2320 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2321 return;
2322 }
af12906f
AJ		 2323 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2324 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2325}
2326
2327/* fnabs */
7c58044c
JM		 2328/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2329GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2330/* fneg */
7c58044c
JM		 2331/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2332GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2333
79aceca5
FB		 2334/*** Floating-Point status & ctrl register ***/
2335/* mcrfs */
2336GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2337{
7c58044c
JM		 2338 int bfa;
2339
76a66253 2340 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2341 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2342 return;
2343 }
7c58044c 2344 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2345 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2346 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2347 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2348}
2349
2350/* mffs */
2351GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2352{
76a66253 2353 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2354 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2355 return;
2356 }
7c58044c 2357 gen_reset_fpstatus();
af12906f
AJ		 2358 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2359 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2360}
2361
2362/* mtfsb0 */
2363GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2364{
fb0eaffc 2365 uint8_t crb;
3b46e624 2366
76a66253 2367 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2368 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2369 return;
2370 }
6e35d524 2371 crb = 31 - crbD(ctx->opcode);
7c58044c 2372 gen_reset_fpstatus();
6e35d524 2373 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2374 TCGv_i32 t0;
2375 /* NIP cannot be restored if the memory exception comes from an helper */
2376 gen_update_nip(ctx, ctx->nip - 4);
2377 t0 = tcg_const_i32(crb);
6e35d524
AJ		 2378 gen_helper_fpscr_clrbit(t0);
2379 tcg_temp_free_i32(t0);
2380 }
7c58044c 2381 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2382 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2383 }
79aceca5
FB		 2384}
2385
2386/* mtfsb1 */
2387GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2388{
fb0eaffc 2389 uint8_t crb;
3b46e624 2390
76a66253 2391 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2392 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2393 return;
2394 }
6e35d524 2395 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2396 gen_reset_fpstatus();
2397 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2398 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2399 TCGv_i32 t0;
2400 /* NIP cannot be restored if the memory exception comes from an helper */
2401 gen_update_nip(ctx, ctx->nip - 4);
2402 t0 = tcg_const_i32(crb);
af12906f 2403 gen_helper_fpscr_setbit(t0);
0f2f39c2 2404 tcg_temp_free_i32(t0);
af12906f 2405 }
7c58044c 2406 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2407 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2408 }
2409 /* We can raise a differed exception */
af12906f 2410 gen_helper_float_check_status();
79aceca5
FB		 2411}
2412
2413/* mtfsf */
2414GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2415{
0f2f39c2 2416 TCGv_i32 t0;
af12906f 2417
76a66253 2418 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2419 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2420 return;
2421 }
eb44b959
AJ		 2422 /* NIP cannot be restored if the memory exception comes from an helper */
2423 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2424 gen_reset_fpstatus();
af12906f
AJ		 2425 t0 = tcg_const_i32(FM(ctx->opcode));
2426 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2427 tcg_temp_free_i32(t0);
7c58044c 2428 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2429 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2430 }
2431 /* We can raise a differed exception */
af12906f 2432 gen_helper_float_check_status();
79aceca5
FB		 2433}
2434
2435/* mtfsfi */
2436GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2437{
7c58044c 2438 int bf, sh;
0f2f39c2
AJ		 2439 TCGv_i64 t0;
2440 TCGv_i32 t1;
7c58044c 2441
76a66253 2442 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2443 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2444 return;
2445 }
7c58044c
JM		 2446 bf = crbD(ctx->opcode) >> 2;
2447 sh = 7 - bf;
eb44b959
AJ		 2448 /* NIP cannot be restored if the memory exception comes from an helper */
2449 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2450 gen_reset_fpstatus();
0f2f39c2 2451 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2452 t1 = tcg_const_i32(1 << sh);
2453 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2454 tcg_temp_free_i64(t0);
2455 tcg_temp_free_i32(t1);
7c58044c 2456 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2457 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2458 }
2459 /* We can raise a differed exception */
af12906f 2460 gen_helper_float_check_status();
79aceca5
FB		 2461}
2462
76a66253
JM		 2463/*** Addressing modes ***/
2464/* Register indirect with immediate index : EA = (rA|0) + SIMM */
76db3ba4 2465static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
76a66253
JM		 2466{
2467 target_long simm = SIMM(ctx->opcode);
2468
be147d08 2469 simm &= ~maskl;
76db3ba4
AJ		 2470 if (rA(ctx->opcode) == 0) {
2471#if defined(TARGET_PPC64)
2472 if (!ctx->sf_mode) {
2473 tcg_gen_movi_tl(EA, (uint32_t)simm);
2474 } else
2475#endif
e2be8d8d 2476 tcg_gen_movi_tl(EA, simm);
76db3ba4 2477 } else if (likely(simm != 0)) {
e2be8d8d 2478 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
76db3ba4
AJ		 2479#if defined(TARGET_PPC64)
2480 if (!ctx->sf_mode) {
2481 tcg_gen_ext32u_tl(EA, EA);
2482 }
2483#endif
2484 } else {
2485#if defined(TARGET_PPC64)
2486 if (!ctx->sf_mode) {
2487 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2488 } else
2489#endif
e2be8d8d 2490 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2491 }
76a66253
JM		 2492}
2493
76db3ba4 2494static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
76a66253 2495{
76db3ba4
AJ		 2496 if (rA(ctx->opcode) == 0) {
2497#if defined(TARGET_PPC64)
2498 if (!ctx->sf_mode) {
2499 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2500 } else
2501#endif
e2be8d8d 2502 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
76db3ba4 2503 } else {
e2be8d8d 2504 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76db3ba4
AJ		 2505#if defined(TARGET_PPC64)
2506 if (!ctx->sf_mode) {
2507 tcg_gen_ext32u_tl(EA, EA);
2508 }
2509#endif
2510 }
76a66253
JM		 2511}
2512
76db3ba4 2513static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
76a66253 2514{
76db3ba4 2515 if (rA(ctx->opcode) == 0) {
e2be8d8d 2516 tcg_gen_movi_tl(EA, 0);
76db3ba4
AJ		 2517 } else {
2518#if defined(TARGET_PPC64)
2519 if (!ctx->sf_mode) {
2520 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2521 } else
2522#endif
2523 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2524 }
2525}
2526
2527static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2528{
2529 tcg_gen_addi_tl(ret, arg1, val);
2530#if defined(TARGET_PPC64)
2531 if (!ctx->sf_mode) {
2532 tcg_gen_ext32u_tl(ret, ret);
2533 }
2534#endif
76a66253
JM		 2535}
2536
cf360a32
AJ		 2537static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2538{
2539 int l1 = gen_new_label();
2540 TCGv t0 = tcg_temp_new();
2541 TCGv_i32 t1, t2;
2542 /* NIP cannot be restored if the memory exception comes from an helper */
2543 gen_update_nip(ctx, ctx->nip - 4);
2544 tcg_gen_andi_tl(t0, EA, mask);
2545 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2546 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2547 t2 = tcg_const_i32(0);
2548 gen_helper_raise_exception_err(t1, t2);
2549 tcg_temp_free_i32(t1);
2550 tcg_temp_free_i32(t2);
2551 gen_set_label(l1);
2552 tcg_temp_free(t0);
2553}
2554
7863667f 2555/*** Integer load ***/
76db3ba4
AJ		 2556static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2557{
2558 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2559}
2560
2561static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2562{
2563 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2564}
2565
2566static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2567{
2568 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2569 if (unlikely(ctx->le_mode)) {
b61f2753 2570#if defined(TARGET_PPC64)
76db3ba4
AJ		 2571 TCGv_i32 t0 = tcg_temp_new_i32();
2572 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2573 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2574 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2575 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2576#else
2577 tcg_gen_bswap16_i32(arg1, arg1);
2578#endif
2579 }
b61f2753
AJ		 2580}
2581
76db3ba4 2582static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2583{
76db3ba4
AJ		 2584 if (unlikely(ctx->le_mode)) {
2585#if defined(TARGET_PPC64)
a7812ae4 2586 TCGv_i32 t0;
76db3ba4 2587 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
a7812ae4 2588 t0 = tcg_temp_new_i32();
76db3ba4 2589 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2590 tcg_gen_bswap16_i32(t0, t0);
76db3ba4
AJ		 2591 tcg_gen_extu_i32_tl(arg1, t0);
2592 tcg_gen_ext16s_tl(arg1, arg1);
a7812ae4 2593 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2594#else
2595 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2596 tcg_gen_bswap16_i32(arg1, arg1);
2597 tcg_gen_ext16s_i32(arg1, arg1);
2598#endif
2599 } else {
2600 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2601 }
b61f2753
AJ		 2602}
2603
76db3ba4 2604static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2605{
76db3ba4
AJ		 2606 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2607 if (unlikely(ctx->le_mode)) {
2608#if defined(TARGET_PPC64)
2609 TCGv_i32 t0 = tcg_temp_new_i32();
2610 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2611 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2612 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2613 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2614#else
2615 tcg_gen_bswap_i32(arg1, arg1);
2616#endif
2617 }
b61f2753
AJ		 2618}
2619
76db3ba4
AJ		 2620#if defined(TARGET_PPC64)
2621static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2622{
76db3ba4 2623 if (unlikely(ctx->mem_idx)) {
a7812ae4 2624 TCGv_i32 t0;
76db3ba4 2625 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
a7812ae4 2626 t0 = tcg_temp_new_i32();
76db3ba4 2627 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2628 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2629 tcg_gen_ext_i32_tl(arg1, t0);
a7812ae4 2630 tcg_temp_free_i32(t0);
b61f2753 2631 } else
76db3ba4 2632 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753 2633}
76db3ba4 2634#endif
b61f2753 2635
76db3ba4 2636static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2637{
76db3ba4
AJ		 2638 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2639 if (unlikely(ctx->le_mode)) {
2640 tcg_gen_bswap_i64(arg1, arg1);
2641 }
b61f2753
AJ		 2642}
2643
76db3ba4 2644static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2645{
76db3ba4 2646 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2647}
2648
76db3ba4 2649static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2650{
76db3ba4
AJ		 2651 if (unlikely(ctx->le_mode)) {
2652#if defined(TARGET_PPC64)
a7812ae4 2653 TCGv_i32 t0;
76db3ba4 2654 TCGv t1;
a7812ae4 2655 t0 = tcg_temp_new_i32();
76db3ba4 2656 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694
AJ		 2657 tcg_gen_ext16u_i32(t0, t0);
2658 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2659 t1 = tcg_temp_new();
ea363694 2660 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2661 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2662 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2663 tcg_temp_free(t1);
2664#else
2665 TCGv t0 = tcg_temp_new();
2666 tcg_gen_ext16u_tl(t0, arg1);
2667 tcg_gen_bswap16_i32(t0, t0);
2668 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2669 tcg_temp_free(t0);
2670#endif
2671 } else {
2672 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2673 }
b61f2753
AJ		 2674}
2675
76db3ba4 2676static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2677{
76db3ba4
AJ		 2678 if (unlikely(ctx->le_mode)) {
2679#if defined(TARGET_PPC64)
a7812ae4 2680 TCGv_i32 t0;
76db3ba4 2681 TCGv t1;
a7812ae4 2682 t0 = tcg_temp_new_i32();
76db3ba4 2683 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2684 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2685 t1 = tcg_temp_new();
ea363694 2686 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2687 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2688 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2689 tcg_temp_free(t1);
2690#else
2691 TCGv t0 = tcg_temp_new_i32();
2692 tcg_gen_bswap_i32(t0, arg1);
2693 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2694 tcg_temp_free(t0);
2695#endif
2696 } else {
2697 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2698 }
b61f2753
AJ		 2699}
2700
76db3ba4 2701static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2702{
76db3ba4 2703 if (unlikely(ctx->le_mode)) {
a7812ae4 2704 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4
AJ		 2705 tcg_gen_bswap_i64(t0, arg1);
2706 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2707 tcg_temp_free_i64(t0);
b61f2753 2708 } else
76db3ba4 2709 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2710}
2711
0c8aacd4
AJ		 2712#define GEN_LD(name, ldop, opc, type) \
2713GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2714{ \
76db3ba4
AJ		 2715 TCGv EA; \
2716 gen_set_access_type(ctx, ACCESS_INT); \
2717 EA = tcg_temp_new(); \
2718 gen_addr_imm_index(ctx, EA, 0); \
2719 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2720 tcg_temp_free(EA); \
79aceca5
FB		 2721}
2722
0c8aacd4
AJ		 2723#define GEN_LDU(name, ldop, opc, type) \
2724GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2725{ \
b61f2753 2726 TCGv EA; \
76a66253
JM		 2727 if (unlikely(rA(ctx->opcode) == 0 || \
2728 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2729 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2730 return; \
9a64fbe4 2731 } \
76db3ba4 2732 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2733 EA = tcg_temp_new(); \
9d53c753 2734 if (type == PPC_64B) \
76db3ba4 2735 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2736 else \
76db3ba4
AJ		 2737 gen_addr_imm_index(ctx, EA, 0); \
2738 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2739 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2740 tcg_temp_free(EA); \
79aceca5
FB		 2741}
2742
0c8aacd4
AJ		 2743#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2744GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2745{ \
b61f2753 2746 TCGv EA; \
76a66253
JM		 2747 if (unlikely(rA(ctx->opcode) == 0 || \
2748 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2749 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2750 return; \
9a64fbe4 2751 } \
76db3ba4 2752 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2753 EA = tcg_temp_new(); \
76db3ba4
AJ		 2754 gen_addr_reg_index(ctx, EA); \
2755 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2756 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2757 tcg_temp_free(EA); \
79aceca5
FB		 2758}
2759
0c8aacd4
AJ		 2760#define GEN_LDX(name, ldop, opc2, opc3, type) \
2761GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2762{ \
76db3ba4
AJ		 2763 TCGv EA; \
2764 gen_set_access_type(ctx, ACCESS_INT); \
2765 EA = tcg_temp_new(); \
2766 gen_addr_reg_index(ctx, EA); \
2767 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2768 tcg_temp_free(EA); \
79aceca5
FB		 2769}
2770
0c8aacd4
AJ		 2771#define GEN_LDS(name, ldop, op, type) \
2772GEN_LD(name, ldop, op | 0x20, type); \
2773GEN_LDU(name, ldop, op | 0x21, type); \
2774GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2775GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2776
2777/* lbz lbzu lbzux lbzx */
0c8aacd4 2778GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2779/* lha lhau lhaux lhax */
0c8aacd4 2780GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2781/* lhz lhzu lhzux lhzx */
0c8aacd4 2782GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2783/* lwz lwzu lwzux lwzx */
0c8aacd4 2784GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2785#if defined(TARGET_PPC64)
d9bce9d9 2786/* lwaux */
0c8aacd4 2787GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2788/* lwax */
0c8aacd4 2789GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2790/* ldux */
0c8aacd4 2791GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2792/* ldx */
0c8aacd4 2793GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2794GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2795{
b61f2753 2796 TCGv EA;
d9bce9d9
JM		 2797 if (Rc(ctx->opcode)) {
2798 if (unlikely(rA(ctx->opcode) == 0 ||
2799 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2800 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2801 return;
2802 }
2803 }
76db3ba4 2804 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2805 EA = tcg_temp_new();
76db3ba4 2806 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2807 if (ctx->opcode & 0x02) {
2808 /* lwa (lwau is undefined) */
76db3ba4 2809 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2810 } else {
2811 /* ld - ldu */
76db3ba4 2812 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2813 }
d9bce9d9 2814 if (Rc(ctx->opcode))
b61f2753
AJ		 2815 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2816 tcg_temp_free(EA);
d9bce9d9 2817}
be147d08
JM		 2818/* lq */
2819GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2820{
2821#if defined(CONFIG_USER_ONLY)
e06fcd75 2822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2823#else
2824 int ra, rd;
b61f2753 2825 TCGv EA;
be147d08
JM		 2826
2827 /* Restore CPU state */
76db3ba4 2828 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2830 return;
2831 }
2832 ra = rA(ctx->opcode);
2833 rd = rD(ctx->opcode);
2834 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2835 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2836 return;
2837 }
76db3ba4 2838 if (unlikely(ctx->le_mode)) {
be147d08 2839 /* Little-endian mode is not handled */
e06fcd75 2840 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2841 return;
2842 }
76db3ba4 2843 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2844 EA = tcg_temp_new();
76db3ba4
AJ		 2845 gen_addr_imm_index(ctx, EA, 0x0F);
2846 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2847 gen_addr_add(ctx, EA, EA, 8);
2848 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
b61f2753 2849 tcg_temp_free(EA);
be147d08
JM		 2850#endif
2851}
d9bce9d9 2852#endif
79aceca5
FB		 2853
2854/*** Integer store ***/
0c8aacd4
AJ		 2855#define GEN_ST(name, stop, opc, type) \
2856GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2857{ \
76db3ba4
AJ		 2858 TCGv EA; \
2859 gen_set_access_type(ctx, ACCESS_INT); \
2860 EA = tcg_temp_new(); \
2861 gen_addr_imm_index(ctx, EA, 0); \
2862 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2863 tcg_temp_free(EA); \
79aceca5
FB		 2864}
2865
0c8aacd4
AJ		 2866#define GEN_STU(name, stop, opc, type) \
2867GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2868{ \
b61f2753 2869 TCGv EA; \
76a66253 2870 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2871 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2872 return; \
9a64fbe4 2873 } \
76db3ba4 2874 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2875 EA = tcg_temp_new(); \
9d53c753 2876 if (type == PPC_64B) \
76db3ba4 2877 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2878 else \
76db3ba4
AJ		 2879 gen_addr_imm_index(ctx, EA, 0); \
2880 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2881 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2882 tcg_temp_free(EA); \
79aceca5
FB		 2883}
2884
0c8aacd4
AJ		 2885#define GEN_STUX(name, stop, opc2, opc3, type) \
2886GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2887{ \
b61f2753 2888 TCGv EA; \
76a66253 2889 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2890 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2891 return; \
9a64fbe4 2892 } \
76db3ba4 2893 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2894 EA = tcg_temp_new(); \
76db3ba4
AJ		 2895 gen_addr_reg_index(ctx, EA); \
2896 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2897 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2898 tcg_temp_free(EA); \
79aceca5
FB		 2899}
2900
0c8aacd4
AJ		 2901#define GEN_STX(name, stop, opc2, opc3, type) \
2902GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2903{ \
76db3ba4
AJ		 2904 TCGv EA; \
2905 gen_set_access_type(ctx, ACCESS_INT); \
2906 EA = tcg_temp_new(); \
2907 gen_addr_reg_index(ctx, EA); \
2908 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2909 tcg_temp_free(EA); \
79aceca5
FB		 2910}
2911
0c8aacd4
AJ		 2912#define GEN_STS(name, stop, op, type) \
2913GEN_ST(name, stop, op | 0x20, type); \
2914GEN_STU(name, stop, op | 0x21, type); \
2915GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2916GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2917
2918/* stb stbu stbux stbx */
0c8aacd4 2919GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2920/* sth sthu sthux sthx */
0c8aacd4 2921GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2922/* stw stwu stwux stwx */
0c8aacd4 2923GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2924#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2925GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2926GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2927GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2928{
be147d08 2929 int rs;
b61f2753 2930 TCGv EA;
be147d08
JM		 2931
2932 rs = rS(ctx->opcode);
2933 if ((ctx->opcode & 0x3) == 0x2) {
2934#if defined(CONFIG_USER_ONLY)
e06fcd75 2935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2936#else
2937 /* stq */
76db3ba4 2938 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2940 return;
2941 }
2942 if (unlikely(rs & 1)) {
e06fcd75 2943 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2944 return;
2945 }
76db3ba4 2946 if (unlikely(ctx->le_mode)) {
be147d08 2947 /* Little-endian mode is not handled */
e06fcd75 2948 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2949 return;
2950 }
76db3ba4 2951 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2952 EA = tcg_temp_new();
76db3ba4
AJ		 2953 gen_addr_imm_index(ctx, EA, 0x03);
2954 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2955 gen_addr_add(ctx, EA, EA, 8);
2956 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
b61f2753 2957 tcg_temp_free(EA);
be147d08
JM		 2958#endif
2959 } else {
2960 /* std / stdu */
2961 if (Rc(ctx->opcode)) {
2962 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2963 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2964 return;
2965 }
2966 }
76db3ba4 2967 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2968 EA = tcg_temp_new();
76db3ba4
AJ		 2969 gen_addr_imm_index(ctx, EA, 0x03);
2970 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 2971 if (Rc(ctx->opcode))
b61f2753
AJ		 2972 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2973 tcg_temp_free(EA);
d9bce9d9 2974 }
d9bce9d9
JM		 2975}
2976#endif
79aceca5
FB		 2977/*** Integer load and store with byte reverse ***/
2978/* lhbrx */
76db3ba4 2979static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2980{
76db3ba4
AJ		 2981 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2982 if (likely(!ctx->le_mode)) {
2983#if defined(TARGET_PPC64)
2984 TCGv_i32 t0 = tcg_temp_new_i32();
2985 tcg_gen_trunc_tl_i32(t0, arg1);
2986 tcg_gen_bswap16_i32(t0, t0);
2987 tcg_gen_extu_i32_tl(arg1, t0);
2988 tcg_temp_free_i32(t0);
2989#else
2990 tcg_gen_bswap16_i32(arg1, arg1);
2991#endif
2992 }
b61f2753 2993}
0c8aacd4 2994GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 2995
79aceca5 2996/* lwbrx */
76db3ba4 2997static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2998{
76db3ba4
AJ		 2999 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3000 if (likely(!ctx->le_mode)) {
3001#if defined(TARGET_PPC64)
3002 TCGv_i32 t0 = tcg_temp_new_i32();
3003 tcg_gen_trunc_tl_i32(t0, arg1);
3004 tcg_gen_bswap_i32(t0, t0);
3005 tcg_gen_extu_i32_tl(arg1, t0);
3006 tcg_temp_free_i32(t0);
3007#else
3008 tcg_gen_bswap_i32(arg1, arg1);
3009#endif
3010 }
b61f2753 3011}
0c8aacd4 3012GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3013
79aceca5 3014/* sthbrx */
76db3ba4 3015static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3016{
76db3ba4
AJ		 3017 if (likely(!ctx->le_mode)) {
3018#if defined(TARGET_PPC64)
3019 TCGv_i32 t0;
3020 TCGv t1;
3021 t0 = tcg_temp_new_i32();
3022 tcg_gen_trunc_tl_i32(t0, arg1);
3023 tcg_gen_ext16u_i32(t0, t0);
3024 tcg_gen_bswap16_i32(t0, t0);
3025 t1 = tcg_temp_new();
3026 tcg_gen_extu_i32_tl(t1, t0);
3027 tcg_temp_free_i32(t0);
3028 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3029 tcg_temp_free(t1);
3030#else
3031 TCGv t0 = tcg_temp_new();
3032 tcg_gen_ext16u_tl(t0, arg1);
3033 tcg_gen_bswap16_i32(t0, t0);
3034 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3035 tcg_temp_free(t0);
3036#endif
3037 } else {
3038 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3039 }
b61f2753 3040}
0c8aacd4 3041GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3042
79aceca5 3043/* stwbrx */
76db3ba4 3044static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3045{
76db3ba4
AJ		 3046 if (likely(!ctx->le_mode)) {
3047#if defined(TARGET_PPC64)
3048 TCGv_i32 t0;
3049 TCGv t1;
3050 t0 = tcg_temp_new_i32();
3051 tcg_gen_trunc_tl_i32(t0, arg1);
3052 tcg_gen_bswap_i32(t0, t0);
3053 t1 = tcg_temp_new();
3054 tcg_gen_extu_i32_tl(t1, t0);
3055 tcg_temp_free_i32(t0);
3056 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3057 tcg_temp_free(t1);
3058#else
3059 TCGv t0 = tcg_temp_new_i32();
3060 tcg_gen_bswap_i32(t0, arg1);
3061 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3062 tcg_temp_free(t0);
3063#endif
3064 } else {
3065 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3066 }
b61f2753 3067}
0c8aacd4 3068GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3069
3070/*** Integer load and store multiple ***/
3071/* lmw */
3072GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3073{
76db3ba4
AJ		 3074 TCGv t0;
3075 TCGv_i32 t1;
3076 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3077 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3078 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3079 t0 = tcg_temp_new();
3080 t1 = tcg_const_i32(rD(ctx->opcode));
3081 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3082 gen_helper_lmw(t0, t1);
3083 tcg_temp_free(t0);
3084 tcg_temp_free_i32(t1);
79aceca5
FB		 3085}
3086
3087/* stmw */
3088GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3089{
76db3ba4
AJ		 3090 TCGv t0;
3091 TCGv_i32 t1;
3092 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3093 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3094 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3095 t0 = tcg_temp_new();
3096 t1 = tcg_const_i32(rS(ctx->opcode));
3097 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3098 gen_helper_stmw(t0, t1);
3099 tcg_temp_free(t0);
3100 tcg_temp_free_i32(t1);
79aceca5
FB		 3101}
3102
3103/*** Integer load and store strings ***/
3104/* lswi */
3fc6c082 3105/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3106 * rA is in the range of registers to be loaded.
3107 * In an other hand, IBM says this is valid, but rA won't be loaded.
3108 * For now, I'll follow the spec...
3109 */
05332d70 3110GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3111{
dfbc799d
AJ		 3112 TCGv t0;
3113 TCGv_i32 t1, t2;
79aceca5
FB		 3114 int nb = NB(ctx->opcode);
3115 int start = rD(ctx->opcode);
9a64fbe4 3116 int ra = rA(ctx->opcode);
79aceca5
FB		 3117 int nr;
3118
3119 if (nb == 0)
3120 nb = 32;
3121 nr = nb / 4;
76a66253
JM		 3122 if (unlikely(((start + nr) > 32 &&
3123 start <= ra && (start + nr - 32) > ra) ||
3124 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3125 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3126 return;
297d8e62 3127 }
76db3ba4 3128 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3129 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3130 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3131 t0 = tcg_temp_new();
76db3ba4 3132 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3133 t1 = tcg_const_i32(nb);
3134 t2 = tcg_const_i32(start);
3135 gen_helper_lsw(t0, t1, t2);
3136 tcg_temp_free(t0);
3137 tcg_temp_free_i32(t1);
3138 tcg_temp_free_i32(t2);
79aceca5
FB		 3139}
3140
3141/* lswx */
05332d70 3142GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3143{
76db3ba4
AJ		 3144 TCGv t0;
3145 TCGv_i32 t1, t2, t3;
3146 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3147 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3148 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3149 t0 = tcg_temp_new();
3150 gen_addr_reg_index(ctx, t0);
3151 t1 = tcg_const_i32(rD(ctx->opcode));
3152 t2 = tcg_const_i32(rA(ctx->opcode));
3153 t3 = tcg_const_i32(rB(ctx->opcode));
dfbc799d
AJ		 3154 gen_helper_lswx(t0, t1, t2, t3);
3155 tcg_temp_free(t0);
3156 tcg_temp_free_i32(t1);
3157 tcg_temp_free_i32(t2);
3158 tcg_temp_free_i32(t3);
79aceca5
FB		 3159}
3160
3161/* stswi */
05332d70 3162GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3163{
76db3ba4
AJ		 3164 TCGv t0;
3165 TCGv_i32 t1, t2;
4b3686fa 3166 int nb = NB(ctx->opcode);
76db3ba4 3167 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3168 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3169 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3170 t0 = tcg_temp_new();
3171 gen_addr_register(ctx, t0);
4b3686fa
FB		 3172 if (nb == 0)
3173 nb = 32;
dfbc799d 3174 t1 = tcg_const_i32(nb);
76db3ba4 3175 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3176 gen_helper_stsw(t0, t1, t2);
3177 tcg_temp_free(t0);
3178 tcg_temp_free_i32(t1);
3179 tcg_temp_free_i32(t2);
79aceca5
FB		 3180}
3181
3182/* stswx */
05332d70 3183GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3184{
76db3ba4
AJ		 3185 TCGv t0;
3186 TCGv_i32 t1, t2;
3187 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3188 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3189 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3190 t0 = tcg_temp_new();
3191 gen_addr_reg_index(ctx, t0);
3192 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3193 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3194 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3195 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3196 gen_helper_stsw(t0, t1, t2);
3197 tcg_temp_free(t0);
3198 tcg_temp_free_i32(t1);
3199 tcg_temp_free_i32(t2);
79aceca5
FB		 3200}
3201
3202/*** Memory synchronisation ***/
3203/* eieio */
0db1b20e 3204GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3205{
79aceca5
FB		 3206}
3207
3208/* isync */
0db1b20e 3209GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3210{
e06fcd75 3211 gen_stop_exception(ctx);
79aceca5
FB		 3212}
3213
111bfab3 3214/* lwarx */
76a66253 3215GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3216{
76db3ba4
AJ		 3217 TCGv t0;
3218 gen_set_access_type(ctx, ACCESS_RES);
3219 t0 = tcg_temp_local_new();
3220 gen_addr_reg_index(ctx, t0);
cf360a32 3221 gen_check_align(ctx, t0, 0x03);
76db3ba4 3222 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3223 tcg_gen_mov_tl(cpu_reserve, t0);
3224 tcg_temp_free(t0);
79aceca5
FB		 3225}
3226
3227/* stwcx. */
c7697e1f 3228GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3229{
76db3ba4
AJ		 3230 int l1;
3231 TCGv t0;
3232 gen_set_access_type(ctx, ACCESS_RES);
3233 t0 = tcg_temp_local_new();
3234 gen_addr_reg_index(ctx, t0);
cf360a32 3235 gen_check_align(ctx, t0, 0x03);
cf360a32
AJ		 3236 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3237 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3238 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3239 l1 = gen_new_label();
cf360a32
AJ		 3240 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3241 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3242 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3243 gen_set_label(l1);
3244 tcg_gen_movi_tl(cpu_reserve, -1);
3245 tcg_temp_free(t0);
79aceca5
FB		 3246}
3247
426613db 3248#if defined(TARGET_PPC64)
426613db 3249/* ldarx */
a750fc0b 3250GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3251{
76db3ba4
AJ		 3252 TCGv t0;
3253 gen_set_access_type(ctx, ACCESS_RES);
3254 t0 = tcg_temp_local_new();
3255 gen_addr_reg_index(ctx, t0);
cf360a32 3256 gen_check_align(ctx, t0, 0x07);
76db3ba4 3257 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3258 tcg_gen_mov_tl(cpu_reserve, t0);
3259 tcg_temp_free(t0);
426613db
JM		 3260}
3261
3262/* stdcx. */
c7697e1f 3263GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3264{
76db3ba4
AJ		 3265 int l1;
3266 TCGv t0;
3267 gen_set_access_type(ctx, ACCESS_RES);
3268 t0 = tcg_temp_local_new();
3269 gen_addr_reg_index(ctx, t0);
cf360a32 3270 gen_check_align(ctx, t0, 0x07);
cf360a32
AJ		 3271 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3272 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3273 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3274 l1 = gen_new_label();
cf360a32
AJ		 3275 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3276 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3277 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3278 gen_set_label(l1);
3279 tcg_gen_movi_tl(cpu_reserve, -1);
3280 tcg_temp_free(t0);
426613db
JM		 3281}
3282#endif /* defined(TARGET_PPC64) */
3283
79aceca5 3284/* sync */
a902d886 3285GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3286{
79aceca5
FB		 3287}
3288
0db1b20e
JM		 3289/* wait */
3290GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3291{
931ff272
AJ		 3292 TCGv_i32 t0 = tcg_temp_new_i32();
3293 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3294 tcg_temp_free_i32(t0);
0db1b20e 3295 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3296 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3297}
3298
79aceca5 3299/*** Floating-point load ***/
a0d7d5a7
AJ		 3300#define GEN_LDF(name, ldop, opc, type) \
3301GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3302{ \
a0d7d5a7 3303 TCGv EA; \
76a66253 3304 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3305 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3306 return; \
3307 } \
76db3ba4 3308 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3309 EA = tcg_temp_new(); \
76db3ba4
AJ		 3310 gen_addr_imm_index(ctx, EA, 0); \
3311 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3312 tcg_temp_free(EA); \
79aceca5
FB		 3313}
3314
a0d7d5a7
AJ		 3315#define GEN_LDUF(name, ldop, opc, type) \
3316GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3317{ \
a0d7d5a7 3318 TCGv EA; \
76a66253 3319 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3320 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3321 return; \
3322 } \
76a66253 3323 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3324 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3325 return; \
9a64fbe4 3326 } \
76db3ba4 3327 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3328 EA = tcg_temp_new(); \
76db3ba4
AJ		 3329 gen_addr_imm_index(ctx, EA, 0); \
3330 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3331 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3332 tcg_temp_free(EA); \
79aceca5
FB		 3333}
3334
a0d7d5a7
AJ		 3335#define GEN_LDUXF(name, ldop, opc, type) \
3336GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3337{ \
a0d7d5a7 3338 TCGv EA; \
76a66253 3339 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3340 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3341 return; \
3342 } \
76a66253 3343 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3344 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3345 return; \
9a64fbe4 3346 } \
76db3ba4 3347 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3348 EA = tcg_temp_new(); \
76db3ba4
AJ		 3349 gen_addr_reg_index(ctx, EA); \
3350 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3351 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3352 tcg_temp_free(EA); \
79aceca5
FB		 3353}
3354
a0d7d5a7
AJ		 3355#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3356GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3357{ \
a0d7d5a7 3358 TCGv EA; \
76a66253 3359 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3360 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3361 return; \
3362 } \
76db3ba4 3363 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3364 EA = tcg_temp_new(); \
76db3ba4
AJ		 3365 gen_addr_reg_index(ctx, EA); \
3366 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3367 tcg_temp_free(EA); \
79aceca5
FB		 3368}
3369
a0d7d5a7
AJ		 3370#define GEN_LDFS(name, ldop, op, type) \
3371GEN_LDF(name, ldop, op | 0x20, type); \
3372GEN_LDUF(name, ldop, op | 0x21, type); \
3373GEN_LDUXF(name, ldop, op | 0x01, type); \
3374GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3375
76db3ba4 3376static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3377{
3378 TCGv t0 = tcg_temp_new();
3379 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3380 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3381 tcg_gen_trunc_tl_i32(t1, t0);
3382 tcg_temp_free(t0);
3383 gen_helper_float32_to_float64(arg1, t1);
3384 tcg_temp_free_i32(t1);
3385}
79aceca5 3386
a0d7d5a7
AJ		 3387 /* lfd lfdu lfdux lfdx */
3388GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3389 /* lfs lfsu lfsux lfsx */
3390GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3391
3392/*** Floating-point store ***/
a0d7d5a7
AJ		 3393#define GEN_STF(name, stop, opc, type) \
3394GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3395{ \
a0d7d5a7 3396 TCGv EA; \
76a66253 3397 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3398 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3399 return; \
3400 } \
76db3ba4 3401 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3402 EA = tcg_temp_new(); \
76db3ba4
AJ		 3403 gen_addr_imm_index(ctx, EA, 0); \
3404 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3405 tcg_temp_free(EA); \
79aceca5
FB		 3406}
3407
a0d7d5a7
AJ		 3408#define GEN_STUF(name, stop, opc, type) \
3409GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3410{ \
a0d7d5a7 3411 TCGv EA; \
76a66253 3412 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3413 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3414 return; \
3415 } \
76a66253 3416 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3417 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3418 return; \
9a64fbe4 3419 } \
76db3ba4 3420 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3421 EA = tcg_temp_new(); \
76db3ba4
AJ		 3422 gen_addr_imm_index(ctx, EA, 0); \
3423 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3424 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3425 tcg_temp_free(EA); \
79aceca5
FB		 3426}
3427
a0d7d5a7
AJ		 3428#define GEN_STUXF(name, stop, opc, type) \
3429GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3430{ \
a0d7d5a7 3431 TCGv EA; \
76a66253 3432 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3433 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3434 return; \
3435 } \
76a66253 3436 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3437 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3438 return; \
9a64fbe4 3439 } \
76db3ba4 3440 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3441 EA = tcg_temp_new(); \
76db3ba4
AJ		 3442 gen_addr_reg_index(ctx, EA); \
3443 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3444 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3445 tcg_temp_free(EA); \
79aceca5
FB		 3446}
3447
a0d7d5a7
AJ		 3448#define GEN_STXF(name, stop, opc2, opc3, type) \
3449GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3450{ \
a0d7d5a7 3451 TCGv EA; \
76a66253 3452 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3453 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3454 return; \
3455 } \
76db3ba4 3456 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3457 EA = tcg_temp_new(); \
76db3ba4
AJ		 3458 gen_addr_reg_index(ctx, EA); \
3459 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3460 tcg_temp_free(EA); \
79aceca5
FB		 3461}
3462
a0d7d5a7
AJ		 3463#define GEN_STFS(name, stop, op, type) \
3464GEN_STF(name, stop, op | 0x20, type); \
3465GEN_STUF(name, stop, op | 0x21, type); \
3466GEN_STUXF(name, stop, op | 0x01, type); \
3467GEN_STXF(name, stop, 0x17, op | 0x00, type)
3468
76db3ba4 3469static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3470{
3471 TCGv_i32 t0 = tcg_temp_new_i32();
3472 TCGv t1 = tcg_temp_new();
3473 gen_helper_float64_to_float32(t0, arg1);
3474 tcg_gen_extu_i32_tl(t1, t0);
3475 tcg_temp_free_i32(t0);
76db3ba4 3476 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3477 tcg_temp_free(t1);
3478}
79aceca5
FB		 3479
3480/* stfd stfdu stfdux stfdx */
a0d7d5a7 3481GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3482/* stfs stfsu stfsux stfsx */
a0d7d5a7 3483GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3484
3485/* Optional: */
76db3ba4 3486static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3487{
3488 TCGv t0 = tcg_temp_new();
3489 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3490 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3491 tcg_temp_free(t0);
3492}
79aceca5 3493/* stfiwx */
a0d7d5a7 3494GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3495
3496/*** Branch ***/
b068d6a7
JM		 3497static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3498 target_ulong dest)
c1942362
FB		 3499{
3500 TranslationBlock *tb;
3501 tb = ctx->tb;
a2ffb812
AJ		 3502#if defined(TARGET_PPC64)
3503 if (!ctx->sf_mode)
3504 dest = (uint32_t) dest;
3505#endif
57fec1fe 3506 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3507 likely(!ctx->singlestep_enabled)) {
57fec1fe 3508 tcg_gen_goto_tb(n);
a2ffb812 3509 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3510 tcg_gen_exit_tb((long)tb + n);
c1942362 3511 } else {
a2ffb812 3512 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3513 if (unlikely(ctx->singlestep_enabled)) {
3514 if ((ctx->singlestep_enabled &
bdc4e053 3515 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3516 ctx->exception == POWERPC_EXCP_BRANCH) {
3517 target_ulong tmp = ctx->nip;
3518 ctx->nip = dest;
e06fcd75 3519 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3520 ctx->nip = tmp;
3521 }
3522 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3523 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3524 }
3525 }
57fec1fe 3526 tcg_gen_exit_tb(0);
c1942362 3527 }
c53be334
FB		 3528}
3529
b068d6a7 3530static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3531{
3532#if defined(TARGET_PPC64)
a2ffb812
AJ		 3533 if (ctx->sf_mode == 0)
3534 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3535 else
3536#endif
a2ffb812 3537 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3538}
3539
79aceca5
FB		 3540/* b ba bl bla */
3541GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3542{
76a66253 3543 target_ulong li, target;
38a64f9d 3544
8cbcb4fa 3545 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3546 /* sign extend LI */
76a66253 3547#if defined(TARGET_PPC64)
d9bce9d9
JM		 3548 if (ctx->sf_mode)
3549 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3550 else
76a66253 3551#endif
d9bce9d9 3552 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3553 if (likely(AA(ctx->opcode) == 0))
046d6672 3554 target = ctx->nip + li - 4;
79aceca5 3555 else
9a64fbe4 3556 target = li;
e1833e1f
JM		 3557 if (LK(ctx->opcode))
3558 gen_setlr(ctx, ctx->nip);
c1942362 3559 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3560}
3561
e98a6e40
FB		 3562#define BCOND_IM 0
3563#define BCOND_LR 1
3564#define BCOND_CTR 2
3565
b068d6a7 3566static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3567{
d9bce9d9 3568 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3569 int l1 = gen_new_label();
3570 TCGv target;
e98a6e40 3571
8cbcb4fa 3572 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3573 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3574 target = tcg_temp_local_new();
a2ffb812
AJ		 3575 if (type == BCOND_CTR)
3576 tcg_gen_mov_tl(target, cpu_ctr);
3577 else
3578 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3579 }
e1833e1f
JM		 3580 if (LK(ctx->opcode))
3581 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3582 l1 = gen_new_label();
3583 if ((bo & 0x4) == 0) {
3584 /* Decrement and test CTR */
a7812ae4 3585 TCGv temp = tcg_temp_new();
a2ffb812 3586 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3587 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3588 return;
3589 }
3590 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3591#if defined(TARGET_PPC64)
a2ffb812
AJ		 3592 if (!ctx->sf_mode)
3593 tcg_gen_ext32u_tl(temp, cpu_ctr);
3594 else
d9bce9d9 3595#endif
a2ffb812
AJ		 3596 tcg_gen_mov_tl(temp, cpu_ctr);
3597 if (bo & 0x2) {
3598 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3599 } else {
3600 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3601 }
a7812ae4 3602 tcg_temp_free(temp);
a2ffb812
AJ		 3603 }
3604 if ((bo & 0x10) == 0) {
3605 /* Test CR */
3606 uint32_t bi = BI(ctx->opcode);
3607 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3608 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3609
d9bce9d9 3610 if (bo & 0x8) {
a2ffb812
AJ		 3611 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3612 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3613 } else {
a2ffb812
AJ		 3614 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3615 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3616 }
a7812ae4 3617 tcg_temp_free_i32(temp);
d9bce9d9 3618 }
e98a6e40 3619 if (type == BCOND_IM) {
a2ffb812
AJ		 3620 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3621 if (likely(AA(ctx->opcode) == 0)) {
3622 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3623 } else {
3624 gen_goto_tb(ctx, 0, li);
3625 }
c53be334 3626 gen_set_label(l1);
c1942362 3627 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3628 } else {
d9bce9d9 3629#if defined(TARGET_PPC64)
a2ffb812
AJ		 3630 if (!(ctx->sf_mode))
3631 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3632 else
3633#endif
3634 tcg_gen_andi_tl(cpu_nip, target, ~3);
3635 tcg_gen_exit_tb(0);
3636 gen_set_label(l1);
3637#if defined(TARGET_PPC64)
3638 if (!(ctx->sf_mode))
3639 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3640 else
3641#endif
a2ffb812 3642 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3643 tcg_gen_exit_tb(0);
08e46e54 3644 }
e98a6e40
FB		 3645}
3646
3647GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3648{
e98a6e40
FB		 3649 gen_bcond(ctx, BCOND_IM);
3650}
3651
3652GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3653{
e98a6e40
FB		 3654 gen_bcond(ctx, BCOND_CTR);
3655}
3656
3657GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3658{
e98a6e40
FB		 3659 gen_bcond(ctx, BCOND_LR);
3660}
79aceca5
FB		 3661
3662/*** Condition register logical ***/
e1571908
AJ		 3663#define GEN_CRLOGIC(name, tcg_op, opc) \
3664GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3665{ \
fc0d441e
JM		 3666 uint8_t bitmask; \
3667 int sh; \
a7812ae4 3668 TCGv_i32 t0, t1; \
fc0d441e 3669 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3670 t0 = tcg_temp_new_i32(); \
fc0d441e 3671 if (sh > 0) \
fea0c503 3672 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3673 else if (sh < 0) \
fea0c503 3674 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3675 else \
fea0c503 3676 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3677 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3678 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3679 if (sh > 0) \
fea0c503 3680 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3681 else if (sh < 0) \
fea0c503 3682 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3683 else \
fea0c503
AJ		 3684 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3685 tcg_op(t0, t0, t1); \
fc0d441e 3686 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3687 tcg_gen_andi_i32(t0, t0, bitmask); \
3688 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3689 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3690 tcg_temp_free_i32(t0); \
3691 tcg_temp_free_i32(t1); \
79aceca5
FB		 3692}
3693
3694/* crand */
e1571908 3695GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3696/* crandc */
e1571908 3697GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3698/* creqv */
e1571908 3699GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3700/* crnand */
e1571908 3701GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3702/* crnor */
e1571908 3703GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3704/* cror */
e1571908 3705GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3706/* crorc */
e1571908 3707GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3708/* crxor */
e1571908 3709GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3710/* mcrf */
3711GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3712{
47e4661c 3713 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3714}
3715
3716/*** System linkage ***/
76db3ba4 3717/* rfi (mem_idx only) */
76a66253 3718GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3719{
9a64fbe4 3720#if defined(CONFIG_USER_ONLY)
e06fcd75 3721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 3722#else
3723 /* Restore CPU state */
76db3ba4 3724 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 3726 return;
9a64fbe4 3727 }
d72a19f7 3728 gen_helper_rfi();
e06fcd75 3729 gen_sync_exception(ctx);
9a64fbe4 3730#endif
79aceca5
FB		 3731}
3732
426613db 3733#if defined(TARGET_PPC64)
a750fc0b 3734GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3735{
3736#if defined(CONFIG_USER_ONLY)
e06fcd75 3737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3738#else
3739 /* Restore CPU state */
76db3ba4 3740 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3742 return;
3743 }
d72a19f7 3744 gen_helper_rfid();
e06fcd75 3745 gen_sync_exception(ctx);
426613db
JM		 3746#endif
3747}
426613db 3748
5b8105fa 3749GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3750{
3751#if defined(CONFIG_USER_ONLY)
e06fcd75 3752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3753#else
3754 /* Restore CPU state */
76db3ba4 3755 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 3756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3757 return;
3758 }
d72a19f7 3759 gen_helper_hrfid();
e06fcd75 3760 gen_sync_exception(ctx);
be147d08
JM		 3761#endif
3762}
3763#endif
3764
79aceca5 3765/* sc */
417bf010
JM		 3766#if defined(CONFIG_USER_ONLY)
3767#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3768#else
3769#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3770#endif
e1833e1f 3771GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3772{
e1833e1f
JM		 3773 uint32_t lev;
3774
3775 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3776 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3777}
3778
3779/*** Trap ***/
3780/* tw */
76a66253 3781GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3782{
cab3bee2 3783 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3784 /* Update the nip since this might generate a trap exception */
d9bce9d9 3785 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3786 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3787 tcg_temp_free_i32(t0);
79aceca5
FB		 3788}
3789
3790/* twi */
3791GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3792{
cab3bee2
AJ		 3793 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3794 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3795 /* Update the nip since this might generate a trap exception */
3796 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3797 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3798 tcg_temp_free(t0);
3799 tcg_temp_free_i32(t1);
79aceca5
FB		 3800}
3801
d9bce9d9
JM		 3802#if defined(TARGET_PPC64)
3803/* td */
3804GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3805{
cab3bee2 3806 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3807 /* Update the nip since this might generate a trap exception */
3808 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3809 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3810 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3811}
3812
3813/* tdi */
3814GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3815{
cab3bee2
AJ		 3816 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3817 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3818 /* Update the nip since this might generate a trap exception */
3819 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3820 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3821 tcg_temp_free(t0);
3822 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3823}
3824#endif
3825
79aceca5 3826/*** Processor control ***/
79aceca5
FB		 3827/* mcrxr */
3828GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3829{
3d7b417e
AJ		 3830 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3831 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3832 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3833}
3834
3835/* mfcr */
76a66253 3836GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3837{
76a66253 3838 uint32_t crm, crn;
3b46e624 3839
76a66253
JM		 3840 if (likely(ctx->opcode & 0x00100000)) {
3841 crm = CRM(ctx->opcode);
3842 if (likely((crm ^ (crm - 1)) == 0)) {
3843 crn = ffs(crm);
e1571908 3844 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3845 }
d9bce9d9 3846 } else {
a7812ae4 3847 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3848 }
79aceca5
FB		 3849}
3850
3851/* mfmsr */
3852GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3853{
9a64fbe4 3854#if defined(CONFIG_USER_ONLY)
e06fcd75 3855 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3856#else
76db3ba4 3857 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3859 return;
9a64fbe4 3860 }
6527f6ea 3861 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3862#endif
79aceca5
FB		 3863}
3864
a11b8151 3865#if 1
6f2d8978 3866#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3867#else
3868static void spr_noaccess (void *opaque, int sprn)
3869{
3870 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3871 printf("ERROR: try to access SPR %d !\n", sprn);
3872}
3873#define SPR_NOACCESS (&spr_noaccess)
3874#endif
3875
79aceca5 3876/* mfspr */
b068d6a7 3877static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3878{
45d827d2 3879 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3880 uint32_t sprn = SPR(ctx->opcode);
3881
3fc6c082 3882#if !defined(CONFIG_USER_ONLY)
76db3ba4 3883 if (ctx->mem_idx == 2)
be147d08 3884 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 3885 else if (ctx->mem_idx)
3fc6c082
FB		 3886 read_cb = ctx->spr_cb[sprn].oea_read;
3887 else
9a64fbe4 3888#endif
3fc6c082 3889 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3890 if (likely(read_cb != NULL)) {
3891 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3892 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3893 } else {
3894 /* Privilege exception */
9fceefa7
JM		 3895 /* This is a hack to avoid warnings when running Linux:
3896 * this OS breaks the PowerPC virtualisation model,
3897 * allowing userland application to read the PVR
3898 */
3899 if (sprn != SPR_PVR) {
93fcfe39 3900 qemu_log("Trying to read privileged spr %d %03x at "
077fc206 3901 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3902 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3903 sprn, sprn, ctx->nip);
f24e5695 3904 }
e06fcd75 3905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3906 }
3fc6c082
FB		 3907 } else {
3908 /* Not defined */
93fcfe39 3909 qemu_log("Trying to read invalid spr %d %03x at "
077fc206 3910 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3911 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3912 sprn, sprn, ctx->nip);
e06fcd75 3913 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3914 }
79aceca5
FB		 3915}
3916
3fc6c082 3917GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3918{
3fc6c082 3919 gen_op_mfspr(ctx);
76a66253 3920}
3fc6c082
FB		 3921
3922/* mftb */
a750fc0b 3923GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3924{
3925 gen_op_mfspr(ctx);
79aceca5
FB		 3926}
3927
3928/* mtcrf */
8dd4983c 3929GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3930{
76a66253 3931 uint32_t crm, crn;
3b46e624 3932
76a66253
JM		 3933 crm = CRM(ctx->opcode);
3934 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3935 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3936 crn = ffs(crm);
a7812ae4
PB		 3937 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3938 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3939 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3940 tcg_temp_free_i32(temp);
76a66253 3941 } else {
a7812ae4
PB		 3942 TCGv_i32 temp = tcg_const_i32(crm);
3943 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3944 tcg_temp_free_i32(temp);
76a66253 3945 }
79aceca5
FB		 3946}
3947
3948/* mtmsr */
426613db 3949#if defined(TARGET_PPC64)
be147d08 3950GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3951{
3952#if defined(CONFIG_USER_ONLY)
e06fcd75 3953 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 3954#else
76db3ba4 3955 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3956 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 3957 return;
3958 }
be147d08
JM		 3959 if (ctx->opcode & 0x00010000) {
3960 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3961 TCGv t0 = tcg_temp_new();
3962 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3963 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3964 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3965 tcg_temp_free(t0);
be147d08 3966 } else {
056b05f8
JM		 3967 /* XXX: we need to update nip before the store
3968 * if we enter power saving mode, we will exit the loop
3969 * directly from ppc_store_msr
3970 */
be147d08 3971 gen_update_nip(ctx, ctx->nip);
6527f6ea 3972 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3973 /* Must stop the translation as machine state (may have) changed */
3974 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3975 gen_stop_exception(ctx);
be147d08 3976 }
426613db
JM		 3977#endif
3978}
3979#endif
3980
79aceca5
FB		 3981GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3982{
9a64fbe4 3983#if defined(CONFIG_USER_ONLY)
e06fcd75 3984 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3985#else
76db3ba4 3986 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3987 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3988 return;
9a64fbe4 3989 }
be147d08
JM		 3990 if (ctx->opcode & 0x00010000) {
3991 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3992 TCGv t0 = tcg_temp_new();
3993 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3994 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3995 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3996 tcg_temp_free(t0);
be147d08 3997 } else {
056b05f8
JM		 3998 /* XXX: we need to update nip before the store
3999 * if we enter power saving mode, we will exit the loop
4000 * directly from ppc_store_msr
4001 */
be147d08 4002 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4003#if defined(TARGET_PPC64)
6527f6ea
AJ		 4004 if (!ctx->sf_mode) {
4005 TCGv t0 = tcg_temp_new();
4006 TCGv t1 = tcg_temp_new();
4007 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4008 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4009 tcg_gen_or_tl(t0, t0, t1);
4010 tcg_temp_free(t1);
4011 gen_helper_store_msr(t0);
4012 tcg_temp_free(t0);
4013 } else
d9bce9d9 4014#endif
6527f6ea 4015 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 4016 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4017 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4018 gen_stop_exception(ctx);
be147d08 4019 }
9a64fbe4 4020#endif
79aceca5
FB		 4021}
4022
4023/* mtspr */
4024GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4025{
45d827d2 4026 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4027 uint32_t sprn = SPR(ctx->opcode);
4028
3fc6c082 4029#if !defined(CONFIG_USER_ONLY)
76db3ba4 4030 if (ctx->mem_idx == 2)
be147d08 4031 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 4032 else if (ctx->mem_idx)
3fc6c082
FB		 4033 write_cb = ctx->spr_cb[sprn].oea_write;
4034 else
9a64fbe4 4035#endif
3fc6c082 4036 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4037 if (likely(write_cb != NULL)) {
4038 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4039 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4040 } else {
4041 /* Privilege exception */
93fcfe39 4042 qemu_log("Trying to write privileged spr %d %03x at "
077fc206 4043 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 4044 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4045 sprn, sprn, ctx->nip);
e06fcd75 4046 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4047 }
3fc6c082
FB		 4048 } else {
4049 /* Not defined */
93fcfe39 4050 qemu_log("Trying to write invalid spr %d %03x at "
077fc206 4051 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 4052 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4053 sprn, sprn, ctx->nip);
e06fcd75 4054 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4055 }
79aceca5
FB		 4056}
4057
4058/*** Cache management ***/
79aceca5 4059/* dcbf */
0db1b20e 4060GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4061{
dac454af 4062 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4063 TCGv t0;
4064 gen_set_access_type(ctx, ACCESS_CACHE);
4065 t0 = tcg_temp_new();
4066 gen_addr_reg_index(ctx, t0);
4067 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4068 tcg_temp_free(t0);
79aceca5
FB		 4069}
4070
4071/* dcbi (Supervisor only) */
9a64fbe4 4072GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4073{
a541f297 4074#if defined(CONFIG_USER_ONLY)
e06fcd75 4075 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4076#else
b61f2753 4077 TCGv EA, val;
76db3ba4 4078 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4080 return;
9a64fbe4 4081 }
a7812ae4 4082 EA = tcg_temp_new();
76db3ba4
AJ		 4083 gen_set_access_type(ctx, ACCESS_CACHE);
4084 gen_addr_reg_index(ctx, EA);
a7812ae4 4085 val = tcg_temp_new();
76a66253 4086 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4087 gen_qemu_ld8u(ctx, val, EA);
4088 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4089 tcg_temp_free(val);
4090 tcg_temp_free(EA);
a541f297 4091#endif
79aceca5
FB		 4092}
4093
4094/* dcdst */
9a64fbe4 4095GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4096{
76a66253 4097 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4098 TCGv t0;
4099 gen_set_access_type(ctx, ACCESS_CACHE);
4100 t0 = tcg_temp_new();
4101 gen_addr_reg_index(ctx, t0);
4102 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4103 tcg_temp_free(t0);
79aceca5
FB		 4104}
4105
4106/* dcbt */
0db1b20e 4107GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4108{
0db1b20e 4109 /* interpreted as no-op */
76a66253
JM		 4110 /* XXX: specification say this is treated as a load by the MMU
4111 * but does not generate any exception
4112 */
79aceca5
FB		 4113}
4114
4115/* dcbtst */
0db1b20e 4116GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4117{
0db1b20e 4118 /* interpreted as no-op */
76a66253
JM		 4119 /* XXX: specification say this is treated as a load by the MMU
4120 * but does not generate any exception
4121 */
79aceca5
FB		 4122}
4123
4124/* dcbz */
d63001d1 4125GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4126{
76db3ba4
AJ		 4127 TCGv t0;
4128 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4129 /* NIP cannot be restored if the memory exception comes from an helper */
4130 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4131 t0 = tcg_temp_new();
4132 gen_addr_reg_index(ctx, t0);
799a8c8d
AJ		 4133 gen_helper_dcbz(t0);
4134 tcg_temp_free(t0);
d63001d1
JM		 4135}
4136
c7697e1f 4137GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4138{
76db3ba4
AJ		 4139 TCGv t0;
4140 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4141 /* NIP cannot be restored if the memory exception comes from an helper */
4142 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4143 t0 = tcg_temp_new();
4144 gen_addr_reg_index(ctx, t0);
d63001d1 4145 if (ctx->opcode & 0x00200000)
799a8c8d 4146 gen_helper_dcbz(t0);
d63001d1 4147 else
799a8c8d
AJ		 4148 gen_helper_dcbz_970(t0);
4149 tcg_temp_free(t0);
79aceca5
FB		 4150}
4151
ae1c1a3d
AJ		 4152/* dst / dstt */
4153GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4154{
4155 if (rA(ctx->opcode) == 0) {
4156 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4157 } else {
4158 /* interpreted as no-op */
4159 }
4160}
4161
4162/* dstst /dststt */
4163GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4164{
4165 if (rA(ctx->opcode) == 0) {
4166 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4167 } else {
4168 /* interpreted as no-op */
4169 }
4170
4171}
4172
4173/* dss / dssall */
4174GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4175{
4176 /* interpreted as no-op */
4177}
4178
79aceca5 4179/* icbi */
1b413d55 4180GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4181{
76db3ba4
AJ		 4182 TCGv t0;
4183 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4184 /* NIP cannot be restored if the memory exception comes from an helper */
4185 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4186 t0 = tcg_temp_new();
4187 gen_addr_reg_index(ctx, t0);
37d269df
AJ		 4188 gen_helper_icbi(t0);
4189 tcg_temp_free(t0);
79aceca5
FB		 4190}
4191
4192/* Optional: */
4193/* dcba */
a750fc0b 4194GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4195{
0db1b20e
JM		 4196 /* interpreted as no-op */
4197 /* XXX: specification say this is treated as a store by the MMU
4198 * but does not generate any exception
4199 */
79aceca5
FB		 4200}
4201
4202/*** Segment register manipulation ***/
4203/* Supervisor only: */
4204/* mfsr */
4205GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4206{
9a64fbe4 4207#if defined(CONFIG_USER_ONLY)
e06fcd75 4208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4209#else
74d37793 4210 TCGv t0;
76db3ba4 4211 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4213 return;
9a64fbe4 4214 }
74d37793
AJ		 4215 t0 = tcg_const_tl(SR(ctx->opcode));
4216 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4217 tcg_temp_free(t0);
9a64fbe4 4218#endif
79aceca5
FB		 4219}
4220
4221/* mfsrin */
9a64fbe4 4222GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4223{
9a64fbe4 4224#if defined(CONFIG_USER_ONLY)
e06fcd75 4225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4226#else
74d37793 4227 TCGv t0;
76db3ba4 4228 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4230 return;
9a64fbe4 4231 }
74d37793
AJ		 4232 t0 = tcg_temp_new();
4233 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4234 tcg_gen_andi_tl(t0, t0, 0xF);
4235 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4236 tcg_temp_free(t0);
9a64fbe4 4237#endif
79aceca5
FB		 4238}
4239
4240/* mtsr */
e63c59cb 4241GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4242{
9a64fbe4 4243#if defined(CONFIG_USER_ONLY)
e06fcd75 4244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4245#else
74d37793 4246 TCGv t0;
76db3ba4 4247 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4249 return;
9a64fbe4 4250 }
74d37793
AJ		 4251 t0 = tcg_const_tl(SR(ctx->opcode));
4252 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4253 tcg_temp_free(t0);
9a64fbe4 4254#endif
79aceca5
FB		 4255}
4256
4257/* mtsrin */
9a64fbe4 4258GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4259{
9a64fbe4 4260#if defined(CONFIG_USER_ONLY)
e06fcd75 4261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4262#else
74d37793 4263 TCGv t0;
76db3ba4 4264 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4266 return;
9a64fbe4 4267 }
74d37793
AJ		 4268 t0 = tcg_temp_new();
4269 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4270 tcg_gen_andi_tl(t0, t0, 0xF);
4271 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4272 tcg_temp_free(t0);
9a64fbe4 4273#endif
79aceca5
FB		 4274}
4275
12de9a39
JM		 4276#if defined(TARGET_PPC64)
4277/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4278/* mfsr */
c7697e1f 4279GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4280{
4281#if defined(CONFIG_USER_ONLY)
e06fcd75 4282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4283#else
74d37793 4284 TCGv t0;
76db3ba4 4285 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4287 return;
4288 }
74d37793
AJ		 4289 t0 = tcg_const_tl(SR(ctx->opcode));
4290 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4291 tcg_temp_free(t0);
12de9a39
JM		 4292#endif
4293}
4294
4295/* mfsrin */
c7697e1f
JM		 4296GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4297 PPC_SEGMENT_64B)
12de9a39
JM		 4298{
4299#if defined(CONFIG_USER_ONLY)
e06fcd75 4300 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4301#else
74d37793 4302 TCGv t0;
76db3ba4 4303 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4305 return;
4306 }
74d37793
AJ		 4307 t0 = tcg_temp_new();
4308 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4309 tcg_gen_andi_tl(t0, t0, 0xF);
4310 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4311 tcg_temp_free(t0);
12de9a39
JM		 4312#endif
4313}
4314
4315/* mtsr */
c7697e1f 4316GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4317{
4318#if defined(CONFIG_USER_ONLY)
e06fcd75 4319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4320#else
74d37793 4321 TCGv t0;
76db3ba4 4322 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4324 return;
4325 }
74d37793
AJ		 4326 t0 = tcg_const_tl(SR(ctx->opcode));
4327 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4328 tcg_temp_free(t0);
12de9a39
JM		 4329#endif
4330}
4331
4332/* mtsrin */
c7697e1f
JM		 4333GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4334 PPC_SEGMENT_64B)
12de9a39
JM		 4335{
4336#if defined(CONFIG_USER_ONLY)
e06fcd75 4337 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4338#else
74d37793 4339 TCGv t0;
76db3ba4 4340 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4342 return;
4343 }
74d37793
AJ		 4344 t0 = tcg_temp_new();
4345 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4346 tcg_gen_andi_tl(t0, t0, 0xF);
4347 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4348 tcg_temp_free(t0);
12de9a39
JM		 4349#endif
4350}
4351#endif /* defined(TARGET_PPC64) */
4352
79aceca5 4353/*** Lookaside buffer management ***/
76db3ba4 4354/* Optional & mem_idx only: */
79aceca5 4355/* tlbia */
3fc6c082 4356GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4357{
9a64fbe4 4358#if defined(CONFIG_USER_ONLY)
e06fcd75 4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4360#else
76db3ba4 4361 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4363 return;
9a64fbe4 4364 }
74d37793 4365 gen_helper_tlbia();
9a64fbe4 4366#endif
79aceca5
FB		 4367}
4368
4369/* tlbie */
76a66253 4370GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4371{
9a64fbe4 4372#if defined(CONFIG_USER_ONLY)
e06fcd75 4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4374#else
76db3ba4 4375 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4376 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4377 return;
9a64fbe4 4378 }
d9bce9d9 4379#if defined(TARGET_PPC64)
74d37793
AJ		 4380 if (!ctx->sf_mode) {
4381 TCGv t0 = tcg_temp_new();
4382 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4383 gen_helper_tlbie(t0);
4384 tcg_temp_free(t0);
4385 } else
d9bce9d9 4386#endif
74d37793 4387 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4388#endif
79aceca5
FB		 4389}
4390
4391/* tlbsync */
76a66253 4392GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4393{
9a64fbe4 4394#if defined(CONFIG_USER_ONLY)
e06fcd75 4395 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4396#else
76db3ba4 4397 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4398 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4399 return;
9a64fbe4
FB		 4400 }
4401 /* This has no effect: it should ensure that all previous
4402 * tlbie have completed
4403 */
e06fcd75 4404 gen_stop_exception(ctx);
9a64fbe4 4405#endif
79aceca5
FB		 4406}
4407
426613db
JM		 4408#if defined(TARGET_PPC64)
4409/* slbia */
4410GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4411{
4412#if defined(CONFIG_USER_ONLY)
e06fcd75 4413 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4414#else
76db3ba4 4415 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4416 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4417 return;
4418 }
74d37793 4419 gen_helper_slbia();
426613db
JM		 4420#endif
4421}
4422
4423/* slbie */
4424GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4425{
4426#if defined(CONFIG_USER_ONLY)
e06fcd75 4427 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4428#else
76db3ba4 4429 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4430 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4431 return;
4432 }
74d37793 4433 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4434#endif
4435}
4436#endif
4437
79aceca5
FB		 4438/*** External control ***/
4439/* Optional: */
111bfab3 4440/* eciwx */
79aceca5
FB		 4441GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4442{
76db3ba4 4443 TCGv t0;
fa407c03 4444 /* Should check EAR[E] ! */
76db3ba4
AJ		 4445 gen_set_access_type(ctx, ACCESS_EXT);
4446 t0 = tcg_temp_new();
4447 gen_addr_reg_index(ctx, t0);
fa407c03 4448 gen_check_align(ctx, t0, 0x03);
76db3ba4 4449 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4450 tcg_temp_free(t0);
76a66253
JM		 4451}
4452
4453/* ecowx */
4454GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4455{
76db3ba4 4456 TCGv t0;
fa407c03 4457 /* Should check EAR[E] ! */
76db3ba4
AJ		 4458 gen_set_access_type(ctx, ACCESS_EXT);
4459 t0 = tcg_temp_new();
4460 gen_addr_reg_index(ctx, t0);
fa407c03 4461 gen_check_align(ctx, t0, 0x03);
76db3ba4 4462 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4463 tcg_temp_free(t0);
76a66253
JM		 4464}
4465
4466/* PowerPC 601 specific instructions */
4467/* abs - abs. */
4468GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4469{
22e0e173
AJ		 4470 int l1 = gen_new_label();
4471 int l2 = gen_new_label();
4472 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4473 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4474 tcg_gen_br(l2);
4475 gen_set_label(l1);
4476 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4477 gen_set_label(l2);
76a66253 4478 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4479 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4480}
4481
4482/* abso - abso. */
4483GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4484{
22e0e173
AJ		 4485 int l1 = gen_new_label();
4486 int l2 = gen_new_label();
4487 int l3 = gen_new_label();
4488 /* Start with XER OV disabled, the most likely case */
4489 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4490 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4491 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4492 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4493 tcg_gen_br(l2);
4494 gen_set_label(l1);
4495 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4496 tcg_gen_br(l3);
4497 gen_set_label(l2);
4498 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4499 gen_set_label(l3);
76a66253 4500 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4501 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4502}
4503
4504/* clcs */
a750fc0b 4505GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4506{
22e0e173
AJ		 4507 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4508 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4509 tcg_temp_free_i32(t0);
c7697e1f 4510 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4511}
4512
4513/* div - div. */
4514GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4515{
22e0e173 4516 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4517 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4518 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4519}
4520
4521/* divo - divo. */
4522GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4523{
22e0e173 4524 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4525 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4526 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4527}
4528
4529/* divs - divs. */
4530GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4531{
22e0e173 4532 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4533 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4534 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4535}
4536
4537/* divso - divso. */
4538GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4539{
22e0e173 4540 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4541 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4542 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4543}
4544
4545/* doz - doz. */
4546GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4547{
22e0e173
AJ		 4548 int l1 = gen_new_label();
4549 int l2 = gen_new_label();
4550 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4551 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4552 tcg_gen_br(l2);
4553 gen_set_label(l1);
4554 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4555 gen_set_label(l2);
76a66253 4556 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4557 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4558}
4559
4560/* dozo - dozo. */
4561GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4562{
22e0e173
AJ		 4563 int l1 = gen_new_label();
4564 int l2 = gen_new_label();
4565 TCGv t0 = tcg_temp_new();
4566 TCGv t1 = tcg_temp_new();
4567 TCGv t2 = tcg_temp_new();
4568 /* Start with XER OV disabled, the most likely case */
4569 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4570 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4571 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4572 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4573 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4574 tcg_gen_andc_tl(t1, t1, t2);
4575 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4576 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4577 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4578 tcg_gen_br(l2);
4579 gen_set_label(l1);
4580 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4581 gen_set_label(l2);
4582 tcg_temp_free(t0);
4583 tcg_temp_free(t1);
4584 tcg_temp_free(t2);
76a66253 4585 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4586 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4587}
4588
4589/* dozi */
4590GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4591{
22e0e173
AJ		 4592 target_long simm = SIMM(ctx->opcode);
4593 int l1 = gen_new_label();
4594 int l2 = gen_new_label();
4595 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4596 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4597 tcg_gen_br(l2);
4598 gen_set_label(l1);
4599 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4600 gen_set_label(l2);
4601 if (unlikely(Rc(ctx->opcode) != 0))
4602 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4603}
4604
76a66253
JM		 4605/* lscbx - lscbx. */
4606GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4607{
bdb4b689
AJ		 4608 TCGv t0 = tcg_temp_new();
4609 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4610 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4611 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4612
76db3ba4 4613 gen_addr_reg_index(ctx, t0);
76a66253 4614 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4615 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4616 gen_helper_lscbx(t0, t0, t1, t2, t3);
4617 tcg_temp_free_i32(t1);
4618 tcg_temp_free_i32(t2);
4619 tcg_temp_free_i32(t3);
3d7b417e 4620 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4621 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4622 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4623 gen_set_Rc0(ctx, t0);
4624 tcg_temp_free(t0);
76a66253
JM		 4625}
4626
4627/* maskg - maskg. */
4628GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4629{
22e0e173
AJ		 4630 int l1 = gen_new_label();
4631 TCGv t0 = tcg_temp_new();
4632 TCGv t1 = tcg_temp_new();
4633 TCGv t2 = tcg_temp_new();
4634 TCGv t3 = tcg_temp_new();
4635 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4636 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4637 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4638 tcg_gen_addi_tl(t2, t0, 1);
4639 tcg_gen_shr_tl(t2, t3, t2);
4640 tcg_gen_shr_tl(t3, t3, t1);
4641 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4642 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4643 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4644 gen_set_label(l1);
4645 tcg_temp_free(t0);
4646 tcg_temp_free(t1);
4647 tcg_temp_free(t2);
4648 tcg_temp_free(t3);
76a66253 4649 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4650 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4651}
4652
4653/* maskir - maskir. */
4654GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4655{
22e0e173
AJ		 4656 TCGv t0 = tcg_temp_new();
4657 TCGv t1 = tcg_temp_new();
4658 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4659 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4660 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4661 tcg_temp_free(t0);
4662 tcg_temp_free(t1);
76a66253 4663 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4664 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4665}
4666
4667/* mul - mul. */
4668GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4669{
22e0e173
AJ		 4670 TCGv_i64 t0 = tcg_temp_new_i64();
4671 TCGv_i64 t1 = tcg_temp_new_i64();
4672 TCGv t2 = tcg_temp_new();
4673 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4674 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4675 tcg_gen_mul_i64(t0, t0, t1);
4676 tcg_gen_trunc_i64_tl(t2, t0);
4677 gen_store_spr(SPR_MQ, t2);
4678 tcg_gen_shri_i64(t1, t0, 32);
4679 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4680 tcg_temp_free_i64(t0);
4681 tcg_temp_free_i64(t1);
4682 tcg_temp_free(t2);
76a66253 4683 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4684 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4685}
4686
4687/* mulo - mulo. */
4688GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4689{
22e0e173
AJ		 4690 int l1 = gen_new_label();
4691 TCGv_i64 t0 = tcg_temp_new_i64();
4692 TCGv_i64 t1 = tcg_temp_new_i64();
4693 TCGv t2 = tcg_temp_new();
4694 /* Start with XER OV disabled, the most likely case */
4695 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4696 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4697 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4698 tcg_gen_mul_i64(t0, t0, t1);
4699 tcg_gen_trunc_i64_tl(t2, t0);
4700 gen_store_spr(SPR_MQ, t2);
4701 tcg_gen_shri_i64(t1, t0, 32);
4702 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4703 tcg_gen_ext32s_i64(t1, t0);
4704 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4705 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4706 gen_set_label(l1);
4707 tcg_temp_free_i64(t0);
4708 tcg_temp_free_i64(t1);
4709 tcg_temp_free(t2);
76a66253 4710 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4711 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4712}
4713
4714/* nabs - nabs. */
4715GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4716{
22e0e173
AJ		 4717 int l1 = gen_new_label();
4718 int l2 = gen_new_label();
4719 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4720 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4721 tcg_gen_br(l2);
4722 gen_set_label(l1);
4723 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4724 gen_set_label(l2);
76a66253 4725 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4726 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4727}
4728
4729/* nabso - nabso. */
4730GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4731{
22e0e173
AJ		 4732 int l1 = gen_new_label();
4733 int l2 = gen_new_label();
4734 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4736 tcg_gen_br(l2);
4737 gen_set_label(l1);
4738 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4739 gen_set_label(l2);
4740 /* nabs never overflows */
4741 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4742 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4743 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4744}
4745
4746/* rlmi - rlmi. */
4747GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4748{
7487953d
AJ		 4749 uint32_t mb = MB(ctx->opcode);
4750 uint32_t me = ME(ctx->opcode);
4751 TCGv t0 = tcg_temp_new();
4752 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4753 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4754 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4755 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4756 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4757 tcg_temp_free(t0);
76a66253 4758 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4759 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4760}
4761
4762/* rrib - rrib. */
4763GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4764{
7487953d
AJ		 4765 TCGv t0 = tcg_temp_new();
4766 TCGv t1 = tcg_temp_new();
4767 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4768 tcg_gen_movi_tl(t1, 0x80000000);
4769 tcg_gen_shr_tl(t1, t1, t0);
4770 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4771 tcg_gen_and_tl(t0, t0, t1);
4772 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4773 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4774 tcg_temp_free(t0);
4775 tcg_temp_free(t1);
76a66253 4776 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4777 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4778}
4779
4780/* sle - sle. */
4781GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4782{
7487953d
AJ		 4783 TCGv t0 = tcg_temp_new();
4784 TCGv t1 = tcg_temp_new();
4785 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4786 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4787 tcg_gen_subfi_tl(t1, 32, t1);
4788 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4789 tcg_gen_or_tl(t1, t0, t1);
4790 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4791 gen_store_spr(SPR_MQ, t1);
4792 tcg_temp_free(t0);
4793 tcg_temp_free(t1);
76a66253 4794 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4795 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4796}
4797
4798/* sleq - sleq. */
4799GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4800{
7487953d
AJ		 4801 TCGv t0 = tcg_temp_new();
4802 TCGv t1 = tcg_temp_new();
4803 TCGv t2 = tcg_temp_new();
4804 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4805 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4806 tcg_gen_shl_tl(t2, t2, t0);
4807 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4808 gen_load_spr(t1, SPR_MQ);
4809 gen_store_spr(SPR_MQ, t0);
4810 tcg_gen_and_tl(t0, t0, t2);
4811 tcg_gen_andc_tl(t1, t1, t2);
4812 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4813 tcg_temp_free(t0);
4814 tcg_temp_free(t1);
4815 tcg_temp_free(t2);
76a66253 4816 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4817 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4818}
4819
4820/* sliq - sliq. */
4821GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4822{
7487953d
AJ		 4823 int sh = SH(ctx->opcode);
4824 TCGv t0 = tcg_temp_new();
4825 TCGv t1 = tcg_temp_new();
4826 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4827 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4828 tcg_gen_or_tl(t1, t0, t1);
4829 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4830 gen_store_spr(SPR_MQ, t1);
4831 tcg_temp_free(t0);
4832 tcg_temp_free(t1);
76a66253 4833 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4834 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4835}
4836
4837/* slliq - slliq. */
4838GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4839{
7487953d
AJ		 4840 int sh = SH(ctx->opcode);
4841 TCGv t0 = tcg_temp_new();
4842 TCGv t1 = tcg_temp_new();
4843 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4844 gen_load_spr(t1, SPR_MQ);
4845 gen_store_spr(SPR_MQ, t0);
4846 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4847 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4848 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4849 tcg_temp_free(t0);
4850 tcg_temp_free(t1);
76a66253 4851 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4852 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4853}
4854
4855/* sllq - sllq. */
4856GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4857{
7487953d
AJ		 4858 int l1 = gen_new_label();
4859 int l2 = gen_new_label();
4860 TCGv t0 = tcg_temp_local_new();
4861 TCGv t1 = tcg_temp_local_new();
4862 TCGv t2 = tcg_temp_local_new();
4863 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4864 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4865 tcg_gen_shl_tl(t1, t1, t2);
4866 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4867 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4868 gen_load_spr(t0, SPR_MQ);
4869 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4870 tcg_gen_br(l2);
4871 gen_set_label(l1);
4872 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4873 gen_load_spr(t2, SPR_MQ);
4874 tcg_gen_andc_tl(t1, t2, t1);
4875 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4876 gen_set_label(l2);
4877 tcg_temp_free(t0);
4878 tcg_temp_free(t1);
4879 tcg_temp_free(t2);
76a66253 4880 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4882}
4883
4884/* slq - slq. */
4885GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4886{
7487953d
AJ		 4887 int l1 = gen_new_label();
4888 TCGv t0 = tcg_temp_new();
4889 TCGv t1 = tcg_temp_new();
4890 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4891 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4892 tcg_gen_subfi_tl(t1, 32, t1);
4893 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4894 tcg_gen_or_tl(t1, t0, t1);
4895 gen_store_spr(SPR_MQ, t1);
4896 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4897 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4898 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4899 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4900 gen_set_label(l1);
4901 tcg_temp_free(t0);
4902 tcg_temp_free(t1);
76a66253 4903 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4904 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4905}
4906
d9bce9d9 4907/* sraiq - sraiq. */
76a66253
JM		 4908GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4909{
7487953d
AJ		 4910 int sh = SH(ctx->opcode);
4911 int l1 = gen_new_label();
4912 TCGv t0 = tcg_temp_new();
4913 TCGv t1 = tcg_temp_new();
4914 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4915 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4916 tcg_gen_or_tl(t0, t0, t1);
4917 gen_store_spr(SPR_MQ, t0);
4918 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4919 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4920 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4921 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4922 gen_set_label(l1);
4923 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4924 tcg_temp_free(t0);
4925 tcg_temp_free(t1);
76a66253 4926 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4927 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4928}
4929
4930/* sraq - sraq. */
4931GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4932{
7487953d
AJ		 4933 int l1 = gen_new_label();
4934 int l2 = gen_new_label();
4935 TCGv t0 = tcg_temp_new();
4936 TCGv t1 = tcg_temp_local_new();
4937 TCGv t2 = tcg_temp_local_new();
4938 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4939 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4940 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4941 tcg_gen_subfi_tl(t2, 32, t2);
4942 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4943 tcg_gen_or_tl(t0, t0, t2);
4944 gen_store_spr(SPR_MQ, t0);
4945 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4946 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4947 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4948 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4949 gen_set_label(l1);
4950 tcg_temp_free(t0);
4951 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4952 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4953 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4954 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4955 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4956 gen_set_label(l2);
4957 tcg_temp_free(t1);
4958 tcg_temp_free(t2);
76a66253 4959 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4960 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4961}
4962
4963/* sre - sre. */
4964GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4965{
7487953d
AJ		 4966 TCGv t0 = tcg_temp_new();
4967 TCGv t1 = tcg_temp_new();
4968 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4969 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4970 tcg_gen_subfi_tl(t1, 32, t1);
4971 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4972 tcg_gen_or_tl(t1, t0, t1);
4973 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4974 gen_store_spr(SPR_MQ, t1);
4975 tcg_temp_free(t0);
4976 tcg_temp_free(t1);
76a66253 4977 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4978 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4979}
4980
4981/* srea - srea. */
4982GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4983{
7487953d
AJ		 4984 TCGv t0 = tcg_temp_new();
4985 TCGv t1 = tcg_temp_new();
4986 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4987 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4988 gen_store_spr(SPR_MQ, t0);
4989 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4990 tcg_temp_free(t0);
4991 tcg_temp_free(t1);
76a66253 4992 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4994}
4995
4996/* sreq */
4997GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4998{
7487953d
AJ		 4999 TCGv t0 = tcg_temp_new();
5000 TCGv t1 = tcg_temp_new();
5001 TCGv t2 = tcg_temp_new();
5002 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5003 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5004 tcg_gen_shr_tl(t1, t1, t0);
5005 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5006 gen_load_spr(t2, SPR_MQ);
5007 gen_store_spr(SPR_MQ, t0);
5008 tcg_gen_and_tl(t0, t0, t1);
5009 tcg_gen_andc_tl(t2, t2, t1);
5010 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5011 tcg_temp_free(t0);
5012 tcg_temp_free(t1);
5013 tcg_temp_free(t2);
76a66253 5014 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5016}
5017
5018/* sriq */
5019GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5020{
7487953d
AJ		 5021 int sh = SH(ctx->opcode);
5022 TCGv t0 = tcg_temp_new();
5023 TCGv t1 = tcg_temp_new();
5024 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5025 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5026 tcg_gen_or_tl(t1, t0, t1);
5027 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5028 gen_store_spr(SPR_MQ, t1);
5029 tcg_temp_free(t0);
5030 tcg_temp_free(t1);
76a66253 5031 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5032 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5033}
5034
5035/* srliq */
5036GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5037{
7487953d
AJ		 5038 int sh = SH(ctx->opcode);
5039 TCGv t0 = tcg_temp_new();
5040 TCGv t1 = tcg_temp_new();
5041 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5042 gen_load_spr(t1, SPR_MQ);
5043 gen_store_spr(SPR_MQ, t0);
5044 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5045 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5046 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5047 tcg_temp_free(t0);
5048 tcg_temp_free(t1);
76a66253 5049 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5050 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5051}
5052
5053/* srlq */
5054GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5055{
7487953d
AJ		 5056 int l1 = gen_new_label();
5057 int l2 = gen_new_label();
5058 TCGv t0 = tcg_temp_local_new();
5059 TCGv t1 = tcg_temp_local_new();
5060 TCGv t2 = tcg_temp_local_new();
5061 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5062 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5063 tcg_gen_shr_tl(t2, t1, t2);
5064 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5065 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5066 gen_load_spr(t0, SPR_MQ);
5067 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5068 tcg_gen_br(l2);
5069 gen_set_label(l1);
5070 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5071 tcg_gen_and_tl(t0, t0, t2);
5072 gen_load_spr(t1, SPR_MQ);
5073 tcg_gen_andc_tl(t1, t1, t2);
5074 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5075 gen_set_label(l2);
5076 tcg_temp_free(t0);
5077 tcg_temp_free(t1);
5078 tcg_temp_free(t2);
76a66253 5079 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5080 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5081}
5082
5083/* srq */
5084GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5085{
7487953d
AJ		 5086 int l1 = gen_new_label();
5087 TCGv t0 = tcg_temp_new();
5088 TCGv t1 = tcg_temp_new();
5089 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5090 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5091 tcg_gen_subfi_tl(t1, 32, t1);
5092 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5093 tcg_gen_or_tl(t1, t0, t1);
5094 gen_store_spr(SPR_MQ, t1);
5095 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5096 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5097 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5098 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5099 gen_set_label(l1);
5100 tcg_temp_free(t0);
5101 tcg_temp_free(t1);
76a66253 5102 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5103 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5104}
5105
5106/* PowerPC 602 specific instructions */
5107/* dsa */
5108GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5109{
5110 /* XXX: TODO */
e06fcd75 5111 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5112}
5113
5114/* esa */
5115GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5116{
5117 /* XXX: TODO */
e06fcd75 5118 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5119}
5120
5121/* mfrom */
5122GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5123{
5124#if defined(CONFIG_USER_ONLY)
e06fcd75 5125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5126#else
76db3ba4 5127 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5129 return;
5130 }
cf02a65c 5131 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5132#endif
5133}
5134
5135/* 602 - 603 - G2 TLB management */
5136/* tlbld */
c7697e1f 5137GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5138{
5139#if defined(CONFIG_USER_ONLY)
e06fcd75 5140 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5141#else
76db3ba4 5142 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5144 return;
5145 }
74d37793 5146 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5147#endif
5148}
5149
5150/* tlbli */
c7697e1f 5151GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5152{
5153#if defined(CONFIG_USER_ONLY)
e06fcd75 5154 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5155#else
76db3ba4 5156 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5158 return;
5159 }
74d37793 5160 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5161#endif
5162}
5163
7dbe11ac
JM		 5164/* 74xx TLB management */
5165/* tlbld */
c7697e1f 5166GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5167{
5168#if defined(CONFIG_USER_ONLY)
e06fcd75 5169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5170#else
76db3ba4 5171 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5172 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5173 return;
5174 }
74d37793 5175 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5176#endif
5177}
5178
5179/* tlbli */
c7697e1f 5180GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5181{
5182#if defined(CONFIG_USER_ONLY)
e06fcd75 5183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5184#else
76db3ba4 5185 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5186 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5187 return;
5188 }
74d37793 5189 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5190#endif
5191}
5192
76a66253
JM		 5193/* POWER instructions not in PowerPC 601 */
5194/* clf */
5195GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5196{
5197 /* Cache line flush: implemented as no-op */
5198}
5199
5200/* cli */
5201GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5202{
7f75ffd3 5203 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5204#if defined(CONFIG_USER_ONLY)
e06fcd75 5205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5206#else
76db3ba4 5207 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5209 return;
5210 }
5211#endif
5212}
5213
5214/* dclst */
5215GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5216{
5217 /* Data cache line store: treated as no-op */
5218}
5219
5220GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5221{
5222#if defined(CONFIG_USER_ONLY)
e06fcd75 5223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5224#else
74d37793
AJ		 5225 int ra = rA(ctx->opcode);
5226 int rd = rD(ctx->opcode);
5227 TCGv t0;
76db3ba4 5228 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5230 return;
5231 }
74d37793 5232 t0 = tcg_temp_new();
76db3ba4 5233 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5234 tcg_gen_shri_tl(t0, t0, 28);
5235 tcg_gen_andi_tl(t0, t0, 0xF);
5236 gen_helper_load_sr(cpu_gpr[rd], t0);
5237 tcg_temp_free(t0);
76a66253 5238 if (ra != 0 && ra != rd)
74d37793 5239 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5240#endif
5241}
5242
5243GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5244{
5245#if defined(CONFIG_USER_ONLY)
e06fcd75 5246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5247#else
22e0e173 5248 TCGv t0;
76db3ba4 5249 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5251 return;
5252 }
22e0e173 5253 t0 = tcg_temp_new();
76db3ba4 5254 gen_addr_reg_index(ctx, t0);
22e0e173
AJ		 5255 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5256 tcg_temp_free(t0);
76a66253
JM		 5257#endif
5258}
5259
5260GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5261{
5262#if defined(CONFIG_USER_ONLY)
e06fcd75 5263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5264#else
76db3ba4 5265 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5266 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5267 return;
5268 }
d72a19f7 5269 gen_helper_rfsvc();
e06fcd75 5270 gen_sync_exception(ctx);
76a66253
JM		 5271#endif
5272}
5273
5274/* svc is not implemented for now */
5275
5276/* POWER2 specific instructions */
5277/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5278
5279/* lfq */
5280GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5281{
01a4afeb 5282 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5283 TCGv t0;
5284 gen_set_access_type(ctx, ACCESS_FLOAT);
5285 t0 = tcg_temp_new();
5286 gen_addr_imm_index(ctx, t0, 0);
5287 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5288 gen_addr_add(ctx, t0, t0, 8);
5289 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5290 tcg_temp_free(t0);
76a66253
JM		 5291}
5292
5293/* lfqu */
5294GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5295{
5296 int ra = rA(ctx->opcode);
01a4afeb 5297 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5298 TCGv t0, t1;
5299 gen_set_access_type(ctx, ACCESS_FLOAT);
5300 t0 = tcg_temp_new();
5301 t1 = tcg_temp_new();
5302 gen_addr_imm_index(ctx, t0, 0);
5303 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5304 gen_addr_add(ctx, t1, t0, 8);
5305 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5306 if (ra != 0)
01a4afeb
AJ		 5307 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5308 tcg_temp_free(t0);
5309 tcg_temp_free(t1);
76a66253
JM		 5310}
5311
5312/* lfqux */
5313GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5314{
5315 int ra = rA(ctx->opcode);
01a4afeb 5316 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5317 gen_set_access_type(ctx, ACCESS_FLOAT);
5318 TCGv t0, t1;
5319 t0 = tcg_temp_new();
5320 gen_addr_reg_index(ctx, t0);
5321 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5322 t1 = tcg_temp_new();
5323 gen_addr_add(ctx, t1, t0, 8);
5324 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5325 tcg_temp_free(t1);
76a66253 5326 if (ra != 0)
01a4afeb
AJ		 5327 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5328 tcg_temp_free(t0);
76a66253
JM		 5329}
5330
5331/* lfqx */
5332GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5333{
01a4afeb 5334 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5335 TCGv t0;
5336 gen_set_access_type(ctx, ACCESS_FLOAT);
5337 t0 = tcg_temp_new();
5338 gen_addr_reg_index(ctx, t0);
5339 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5340 gen_addr_add(ctx, t0, t0, 8);
5341 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5342 tcg_temp_free(t0);
76a66253
JM		 5343}
5344
5345/* stfq */
5346GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5347{
01a4afeb 5348 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5349 TCGv t0;
5350 gen_set_access_type(ctx, ACCESS_FLOAT);
5351 t0 = tcg_temp_new();
5352 gen_addr_imm_index(ctx, t0, 0);
5353 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5354 gen_addr_add(ctx, t0, t0, 8);
5355 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5356 tcg_temp_free(t0);
76a66253
JM		 5357}
5358
5359/* stfqu */
5360GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5361{
5362 int ra = rA(ctx->opcode);
01a4afeb 5363 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5364 TCGv t0, t1;
5365 gen_set_access_type(ctx, ACCESS_FLOAT);
5366 t0 = tcg_temp_new();
5367 gen_addr_imm_index(ctx, t0, 0);
5368 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5369 t1 = tcg_temp_new();
5370 gen_addr_add(ctx, t1, t0, 8);
5371 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5372 tcg_temp_free(t1);
76a66253 5373 if (ra != 0)
01a4afeb
AJ		 5374 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5375 tcg_temp_free(t0);
76a66253
JM		 5376}
5377
5378/* stfqux */
5379GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5380{
5381 int ra = rA(ctx->opcode);
01a4afeb 5382 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5383 TCGv t0, t1;
5384 gen_set_access_type(ctx, ACCESS_FLOAT);
5385 t0 = tcg_temp_new();
5386 gen_addr_reg_index(ctx, t0);
5387 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5388 t1 = tcg_temp_new();
5389 gen_addr_add(ctx, t1, t0, 8);
5390 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5391 tcg_temp_free(t1);
76a66253 5392 if (ra != 0)
01a4afeb
AJ		 5393 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5394 tcg_temp_free(t0);
76a66253
JM		 5395}
5396
5397/* stfqx */
5398GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5399{
01a4afeb 5400 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5401 TCGv t0;
5402 gen_set_access_type(ctx, ACCESS_FLOAT);
5403 t0 = tcg_temp_new();
5404 gen_addr_reg_index(ctx, t0);
5405 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5406 gen_addr_add(ctx, t0, t0, 8);
5407 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5408 tcg_temp_free(t0);
76a66253
JM		 5409}
5410
5411/* BookE specific instructions */
2662a059 5412/* XXX: not implemented on 440 ? */
05332d70 5413GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5414{
5415 /* XXX: TODO */
e06fcd75 5416 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5417}
5418
2662a059 5419/* XXX: not implemented on 440 ? */
05332d70 5420GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5421{
5422#if defined(CONFIG_USER_ONLY)
e06fcd75 5423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5424#else
74d37793 5425 TCGv t0;
76db3ba4 5426 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5427 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5428 return;
5429 }
ec72e276 5430 t0 = tcg_temp_new();
76db3ba4 5431 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5432 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5433 tcg_temp_free(t0);
76a66253
JM		 5434#endif
5435}
5436
5437/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5438static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5439 int opc2, int opc3,
5440 int ra, int rb, int rt, int Rc)
76a66253 5441{
182608d4
AJ		 5442 TCGv t0, t1;
5443
a7812ae4
PB		 5444 t0 = tcg_temp_local_new();
5445 t1 = tcg_temp_local_new();
182608d4 5446
76a66253
JM		 5447 switch (opc3 & 0x0D) {
5448 case 0x05:
5449 /* macchw - macchw. - macchwo - macchwo. */
5450 /* macchws - macchws. - macchwso - macchwso. */
5451 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5452 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5453 /* mulchw - mulchw. */
182608d4
AJ		 5454 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5455 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5456 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5457 break;
5458 case 0x04:
5459 /* macchwu - macchwu. - macchwuo - macchwuo. */
5460 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5461 /* mulchwu - mulchwu. */
182608d4
AJ		 5462 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5463 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5464 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5465 break;
5466 case 0x01:
5467 /* machhw - machhw. - machhwo - machhwo. */
5468 /* machhws - machhws. - machhwso - machhwso. */
5469 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5470 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5471 /* mulhhw - mulhhw. */
182608d4
AJ		 5472 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5473 tcg_gen_ext16s_tl(t0, t0);
5474 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5475 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5476 break;
5477 case 0x00:
5478 /* machhwu - machhwu. - machhwuo - machhwuo. */
5479 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5480 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5481 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5482 tcg_gen_ext16u_tl(t0, t0);
5483 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5484 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5485 break;
5486 case 0x0D:
5487 /* maclhw - maclhw. - maclhwo - maclhwo. */
5488 /* maclhws - maclhws. - maclhwso - maclhwso. */
5489 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5490 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5491 /* mullhw - mullhw. */
182608d4
AJ		 5492 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5493 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5494 break;
5495 case 0x0C:
5496 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5497 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5498 /* mullhwu - mullhwu. */
182608d4
AJ		 5499 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5500 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5501 break;
5502 }
76a66253 5503 if (opc2 & 0x04) {
182608d4
AJ		 5504 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5505 tcg_gen_mul_tl(t1, t0, t1);
5506 if (opc2 & 0x02) {
5507 /* nmultiply-and-accumulate (0x0E) */
5508 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5509 } else {
5510 /* multiply-and-accumulate (0x0C) */
5511 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5512 }
5513
5514 if (opc3 & 0x12) {
5515 /* Check overflow and/or saturate */
5516 int l1 = gen_new_label();
5517
5518 if (opc3 & 0x10) {
5519 /* Start with XER OV disabled, the most likely case */
5520 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5521 }
5522 if (opc3 & 0x01) {
5523 /* Signed */
5524 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5525 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5526 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5527 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5528 if (opc3 & 0x02) {
182608d4
AJ		 5529 /* Saturate */
5530 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5531 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5532 }
5533 } else {
5534 /* Unsigned */
5535 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5536 if (opc3 & 0x02) {
182608d4
AJ		 5537 /* Saturate */
5538 tcg_gen_movi_tl(t0, UINT32_MAX);
5539 }
5540 }
5541 if (opc3 & 0x10) {
5542 /* Check overflow */
5543 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5544 }
5545 gen_set_label(l1);
5546 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5547 }
5548 } else {
5549 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5550 }
182608d4
AJ		 5551 tcg_temp_free(t0);
5552 tcg_temp_free(t1);
76a66253
JM		 5553 if (unlikely(Rc) != 0) {
5554 /* Update Rc0 */
182608d4 5555 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5556 }
5557}
5558
a750fc0b
JM		 5559#define GEN_MAC_HANDLER(name, opc2, opc3) \
5560GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5561{ \
5562 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5563 rD(ctx->opcode), Rc(ctx->opcode)); \
5564}
5565
5566/* macchw - macchw. */
a750fc0b 5567GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5568/* macchwo - macchwo. */
a750fc0b 5569GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5570/* macchws - macchws. */
a750fc0b 5571GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5572/* macchwso - macchwso. */
a750fc0b 5573GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5574/* macchwsu - macchwsu. */
a750fc0b 5575GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5576/* macchwsuo - macchwsuo. */
a750fc0b 5577GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5578/* macchwu - macchwu. */
a750fc0b 5579GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5580/* macchwuo - macchwuo. */
a750fc0b 5581GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5582/* machhw - machhw. */
a750fc0b 5583GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5584/* machhwo - machhwo. */
a750fc0b 5585GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5586/* machhws - machhws. */
a750fc0b 5587GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5588/* machhwso - machhwso. */
a750fc0b 5589GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5590/* machhwsu - machhwsu. */
a750fc0b 5591GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5592/* machhwsuo - machhwsuo. */
a750fc0b 5593GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5594/* machhwu - machhwu. */
a750fc0b 5595GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5596/* machhwuo - machhwuo. */
a750fc0b 5597GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5598/* maclhw - maclhw. */
a750fc0b 5599GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5600/* maclhwo - maclhwo. */
a750fc0b 5601GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5602/* maclhws - maclhws. */
a750fc0b 5603GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5604/* maclhwso - maclhwso. */
a750fc0b 5605GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5606/* maclhwu - maclhwu. */
a750fc0b 5607GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5608/* maclhwuo - maclhwuo. */
a750fc0b 5609GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5610/* maclhwsu - maclhwsu. */
a750fc0b 5611GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5612/* maclhwsuo - maclhwsuo. */
a750fc0b 5613GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5614/* nmacchw - nmacchw. */
a750fc0b 5615GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5616/* nmacchwo - nmacchwo. */
a750fc0b 5617GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5618/* nmacchws - nmacchws. */
a750fc0b 5619GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5620/* nmacchwso - nmacchwso. */
a750fc0b 5621GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5622/* nmachhw - nmachhw. */
a750fc0b 5623GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5624/* nmachhwo - nmachhwo. */
a750fc0b 5625GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5626/* nmachhws - nmachhws. */
a750fc0b 5627GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5628/* nmachhwso - nmachhwso. */
a750fc0b 5629GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5630/* nmaclhw - nmaclhw. */
a750fc0b 5631GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5632/* nmaclhwo - nmaclhwo. */
a750fc0b 5633GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5634/* nmaclhws - nmaclhws. */
a750fc0b 5635GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5636/* nmaclhwso - nmaclhwso. */
a750fc0b 5637GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5638
5639/* mulchw - mulchw. */
a750fc0b 5640GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5641/* mulchwu - mulchwu. */
a750fc0b 5642GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5643/* mulhhw - mulhhw. */
a750fc0b 5644GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5645/* mulhhwu - mulhhwu. */
a750fc0b 5646GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5647/* mullhw - mullhw. */
a750fc0b 5648GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5649/* mullhwu - mullhwu. */
a750fc0b 5650GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5651
5652/* mfdcr */
05332d70 5653GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5654{
5655#if defined(CONFIG_USER_ONLY)
e06fcd75 5656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5657#else
06dca6a7 5658 TCGv dcrn;
76db3ba4 5659 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5661 return;
5662 }
06dca6a7
AJ		 5663 /* NIP cannot be restored if the memory exception comes from an helper */
5664 gen_update_nip(ctx, ctx->nip - 4);
5665 dcrn = tcg_const_tl(SPR(ctx->opcode));
5666 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5667 tcg_temp_free(dcrn);
76a66253
JM		 5668#endif
5669}
5670
5671/* mtdcr */
05332d70 5672GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5673{
5674#if defined(CONFIG_USER_ONLY)
e06fcd75 5675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5676#else
06dca6a7 5677 TCGv dcrn;
76db3ba4 5678 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5680 return;
5681 }
06dca6a7
AJ		 5682 /* NIP cannot be restored if the memory exception comes from an helper */
5683 gen_update_nip(ctx, ctx->nip - 4);
5684 dcrn = tcg_const_tl(SPR(ctx->opcode));
5685 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5686 tcg_temp_free(dcrn);
a42bd6cc
JM		 5687#endif
5688}
5689
5690/* mfdcrx */
2662a059 5691/* XXX: not implemented on 440 ? */
05332d70 5692GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5693{
5694#if defined(CONFIG_USER_ONLY)
e06fcd75 5695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5696#else
76db3ba4 5697 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5698 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5699 return;
5700 }
06dca6a7
AJ		 5701 /* NIP cannot be restored if the memory exception comes from an helper */
5702 gen_update_nip(ctx, ctx->nip - 4);
5703 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5704 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5705#endif
5706}
5707
5708/* mtdcrx */
2662a059 5709/* XXX: not implemented on 440 ? */
05332d70 5710GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5711{
5712#if defined(CONFIG_USER_ONLY)
e06fcd75 5713 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5714#else
76db3ba4 5715 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5717 return;
5718 }
06dca6a7
AJ		 5719 /* NIP cannot be restored if the memory exception comes from an helper */
5720 gen_update_nip(ctx, ctx->nip - 4);
5721 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5722 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5723#endif
5724}
5725
a750fc0b
JM		 5726/* mfdcrux (PPC 460) : user-mode access to DCR */
5727GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5728{
06dca6a7
AJ		 5729 /* NIP cannot be restored if the memory exception comes from an helper */
5730 gen_update_nip(ctx, ctx->nip - 4);
5731 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5732 /* Note: Rc update flag set leads to undefined state of Rc0 */
5733}
5734
5735/* mtdcrux (PPC 460) : user-mode access to DCR */
5736GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5737{
06dca6a7
AJ		 5738 /* NIP cannot be restored if the memory exception comes from an helper */
5739 gen_update_nip(ctx, ctx->nip - 4);
5740 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5741 /* Note: Rc update flag set leads to undefined state of Rc0 */
5742}
5743
76a66253
JM		 5744/* dccci */
5745GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5746{
5747#if defined(CONFIG_USER_ONLY)
e06fcd75 5748 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5749#else
76db3ba4 5750 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5752 return;
5753 }
5754 /* interpreted as no-op */
5755#endif
5756}
5757
5758/* dcread */
5759GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5760{
5761#if defined(CONFIG_USER_ONLY)
e06fcd75 5762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5763#else
b61f2753 5764 TCGv EA, val;
76db3ba4 5765 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5767 return;
5768 }
76db3ba4 5769 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5770 EA = tcg_temp_new();
76db3ba4 5771 gen_addr_reg_index(ctx, EA);
a7812ae4 5772 val = tcg_temp_new();
76db3ba4 5773 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5774 tcg_temp_free(val);
5775 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5776 tcg_temp_free(EA);
76a66253
JM		 5777#endif
5778}
5779
5780/* icbt */
c7697e1f 5781GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5782{
5783 /* interpreted as no-op */
5784 /* XXX: specification say this is treated as a load by the MMU
5785 * but does not generate any exception
5786 */
5787}
5788
5789/* iccci */
5790GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5791{
5792#if defined(CONFIG_USER_ONLY)
e06fcd75 5793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5794#else
76db3ba4 5795 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5796 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5797 return;
5798 }
5799 /* interpreted as no-op */
5800#endif
5801}
5802
5803/* icread */
5804GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5805{
5806#if defined(CONFIG_USER_ONLY)
e06fcd75 5807 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5808#else
76db3ba4 5809 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5810 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5811 return;
5812 }
5813 /* interpreted as no-op */
5814#endif
5815}
5816
76db3ba4 5817/* rfci (mem_idx only) */
c7697e1f 5818GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5819{
5820#if defined(CONFIG_USER_ONLY)
e06fcd75 5821 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5822#else
76db3ba4 5823 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5825 return;
5826 }
5827 /* Restore CPU state */
d72a19f7 5828 gen_helper_40x_rfci();
e06fcd75 5829 gen_sync_exception(ctx);
a42bd6cc
JM		 5830#endif
5831}
5832
5833GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5834{
5835#if defined(CONFIG_USER_ONLY)
e06fcd75 5836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5837#else
76db3ba4 5838 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5840 return;
5841 }
5842 /* Restore CPU state */
d72a19f7 5843 gen_helper_rfci();
e06fcd75 5844 gen_sync_exception(ctx);
a42bd6cc
JM		 5845#endif
5846}
5847
5848/* BookE specific */
2662a059 5849/* XXX: not implemented on 440 ? */
05332d70 5850GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5851{
5852#if defined(CONFIG_USER_ONLY)
e06fcd75 5853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5854#else
76db3ba4 5855 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5857 return;
5858 }
5859 /* Restore CPU state */
d72a19f7 5860 gen_helper_rfdi();
e06fcd75 5861 gen_sync_exception(ctx);
76a66253
JM		 5862#endif
5863}
5864
2662a059 5865/* XXX: not implemented on 440 ? */
a750fc0b 5866GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5867{
5868#if defined(CONFIG_USER_ONLY)
e06fcd75 5869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5870#else
76db3ba4 5871 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5872 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5873 return;
5874 }
5875 /* Restore CPU state */
d72a19f7 5876 gen_helper_rfmci();
e06fcd75 5877 gen_sync_exception(ctx);
a42bd6cc
JM		 5878#endif
5879}
5eb7995e 5880
d9bce9d9 5881/* TLB management - PowerPC 405 implementation */
76a66253 5882/* tlbre */
c7697e1f 5883GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5884{
5885#if defined(CONFIG_USER_ONLY)
e06fcd75 5886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5887#else
76db3ba4 5888 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5890 return;
5891 }
5892 switch (rB(ctx->opcode)) {
5893 case 0:
74d37793 5894 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5895 break;
5896 case 1:
74d37793 5897 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5898 break;
5899 default:
e06fcd75 5900 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5901 break;
9a64fbe4 5902 }
76a66253
JM		 5903#endif
5904}
5905
d9bce9d9 5906/* tlbsx - tlbsx. */
c7697e1f 5907GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5908{
5909#if defined(CONFIG_USER_ONLY)
e06fcd75 5910 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5911#else
74d37793 5912 TCGv t0;
76db3ba4 5913 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5915 return;
5916 }
74d37793 5917 t0 = tcg_temp_new();
76db3ba4 5918 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5919 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5920 tcg_temp_free(t0);
5921 if (Rc(ctx->opcode)) {
5922 int l1 = gen_new_label();
5923 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5924 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5925 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5926 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5927 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5928 gen_set_label(l1);
5929 }
76a66253 5930#endif
79aceca5
FB		 5931}
5932
76a66253 5933/* tlbwe */
c7697e1f 5934GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5935{
76a66253 5936#if defined(CONFIG_USER_ONLY)
e06fcd75 5937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5938#else
76db3ba4 5939 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5941 return;
5942 }
5943 switch (rB(ctx->opcode)) {
5944 case 0:
74d37793 5945 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5946 break;
5947 case 1:
74d37793 5948 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5949 break;
5950 default:
e06fcd75 5951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5952 break;
9a64fbe4 5953 }
76a66253
JM		 5954#endif
5955}
5956
a4bb6c3e 5957/* TLB management - PowerPC 440 implementation */
5eb7995e 5958/* tlbre */
c7697e1f 5959GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5960{
5961#if defined(CONFIG_USER_ONLY)
e06fcd75 5962 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5963#else
76db3ba4 5964 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5965 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5966 return;
5967 }
5968 switch (rB(ctx->opcode)) {
5969 case 0:
5eb7995e 5970 case 1:
5eb7995e 5971 case 2:
74d37793
AJ		 5972 {
5973 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5974 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5975 tcg_temp_free_i32(t0);
5976 }
5eb7995e
JM		 5977 break;
5978 default:
e06fcd75 5979 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 5980 break;
5981 }
5982#endif
5983}
5984
5985/* tlbsx - tlbsx. */
c7697e1f 5986GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5987{
5988#if defined(CONFIG_USER_ONLY)
e06fcd75 5989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5990#else
74d37793 5991 TCGv t0;
76db3ba4 5992 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5993 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5994 return;
5995 }
74d37793 5996 t0 = tcg_temp_new();
76db3ba4 5997 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5998 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5999 tcg_temp_free(t0);
6000 if (Rc(ctx->opcode)) {
6001 int l1 = gen_new_label();
6002 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6003 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6004 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6005 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6006 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6007 gen_set_label(l1);
6008 }
5eb7995e
JM		 6009#endif
6010}
6011
6012/* tlbwe */
c7697e1f 6013GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 6014{
6015#if defined(CONFIG_USER_ONLY)
e06fcd75 6016 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6017#else
76db3ba4 6018 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6020 return;
6021 }
6022 switch (rB(ctx->opcode)) {
6023 case 0:
5eb7995e 6024 case 1:
5eb7995e 6025 case 2:
74d37793
AJ		 6026 {
6027 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6028 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6029 tcg_temp_free_i32(t0);
6030 }
5eb7995e
JM		 6031 break;
6032 default:
e06fcd75 6033 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6034 break;
6035 }
6036#endif
6037}
6038
76a66253 6039/* wrtee */
05332d70 6040GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6041{
6042#if defined(CONFIG_USER_ONLY)
e06fcd75 6043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6044#else
6527f6ea 6045 TCGv t0;
76db3ba4 6046 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6048 return;
6049 }
6527f6ea
AJ		 6050 t0 = tcg_temp_new();
6051 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6052 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6053 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6054 tcg_temp_free(t0);
dee96f6c
JM		 6055 /* Stop translation to have a chance to raise an exception
6056 * if we just set msr_ee to 1
6057 */
e06fcd75 6058 gen_stop_exception(ctx);
76a66253
JM		 6059#endif
6060}
6061
6062/* wrteei */
05332d70 6063GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6064{
6065#if defined(CONFIG_USER_ONLY)
e06fcd75 6066 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6067#else
76db3ba4 6068 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6069 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6070 return;
6071 }
6527f6ea
AJ		 6072 if (ctx->opcode & 0x00010000) {
6073 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6074 /* Stop translation to have a chance to raise an exception */
e06fcd75 6075 gen_stop_exception(ctx);
6527f6ea 6076 } else {
1b6e5f99 6077 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6078 }
76a66253
JM		 6079#endif
6080}
6081
08e46e54 6082/* PowerPC 440 specific instructions */
76a66253
JM		 6083/* dlmzb */
6084GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6085{
ef0d51af
AJ		 6086 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6087 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6088 cpu_gpr[rB(ctx->opcode)], t0);
6089 tcg_temp_free_i32(t0);
76a66253
JM		 6090}
6091
6092/* mbar replaces eieio on 440 */
26370046 6093GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
76a66253
JM		 6094{
6095 /* interpreted as no-op */
6096}
6097
6098/* msync replaces sync on 440 */
0db1b20e 6099GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6100{
6101 /* interpreted as no-op */
6102}
6103
6104/* icbt */
c7697e1f 6105GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6106{
6107 /* interpreted as no-op */
6108 /* XXX: specification say this is treated as a load by the MMU
6109 * but does not generate any exception
6110 */
79aceca5
FB		 6111}
6112
a9d9eb8f
JM		 6113/*** Altivec vector extension ***/
6114/* Altivec registers moves */
a9d9eb8f 6115
564e571a
AJ		 6116static always_inline TCGv_ptr gen_avr_ptr(int reg)
6117{
e4704b3b 6118 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6119 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6120 return r;
6121}
6122
a9d9eb8f 6123#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6124GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6125{ \
fe1e5c53 6126 TCGv EA; \
a9d9eb8f 6127 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6128 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6129 return; \
6130 } \
76db3ba4 6131 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6132 EA = tcg_temp_new(); \
76db3ba4 6133 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6134 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6135 if (ctx->le_mode) { \
6136 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6137 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6138 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6139 } else { \
76db3ba4 6140 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6141 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6142 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6143 } \
6144 tcg_temp_free(EA); \
a9d9eb8f
JM		 6145}
6146
6147#define GEN_VR_STX(name, opc2, opc3) \
6148GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6149{ \
fe1e5c53 6150 TCGv EA; \
a9d9eb8f 6151 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6152 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6153 return; \
6154 } \
76db3ba4 6155 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6156 EA = tcg_temp_new(); \
76db3ba4 6157 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6158 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6159 if (ctx->le_mode) { \
6160 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6161 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6162 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6163 } else { \
76db3ba4 6164 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6165 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6166 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6167 } \
6168 tcg_temp_free(EA); \
a9d9eb8f
JM		 6169}
6170
cbfb6ae9
AJ		 6171#define GEN_VR_LVE(name, opc2, opc3) \
6172 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6173 { \
6174 TCGv EA; \
6175 TCGv_ptr rs; \
6176 if (unlikely(!ctx->altivec_enabled)) { \
6177 gen_exception(ctx, POWERPC_EXCP_VPU); \
6178 return; \
6179 } \
6180 gen_set_access_type(ctx, ACCESS_INT); \
6181 EA = tcg_temp_new(); \
6182 gen_addr_reg_index(ctx, EA); \
6183 rs = gen_avr_ptr(rS(ctx->opcode)); \
6184 gen_helper_lve##name (rs, EA); \
6185 tcg_temp_free(EA); \
6186 tcg_temp_free_ptr(rs); \
6187 }
6188
6189#define GEN_VR_STVE(name, opc2, opc3) \
6190 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6191 { \
6192 TCGv EA; \
6193 TCGv_ptr rs; \
6194 if (unlikely(!ctx->altivec_enabled)) { \
6195 gen_exception(ctx, POWERPC_EXCP_VPU); \
6196 return; \
6197 } \
6198 gen_set_access_type(ctx, ACCESS_INT); \
6199 EA = tcg_temp_new(); \
6200 gen_addr_reg_index(ctx, EA); \
6201 rs = gen_avr_ptr(rS(ctx->opcode)); \
6202 gen_helper_stve##name (rs, EA); \
6203 tcg_temp_free(EA); \
6204 tcg_temp_free_ptr(rs); \
6205 }
6206
fe1e5c53 6207GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6208/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6209GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6210
cbfb6ae9
AJ		 6211GEN_VR_LVE(bx, 0x07, 0x00);
6212GEN_VR_LVE(hx, 0x07, 0x01);
6213GEN_VR_LVE(wx, 0x07, 0x02);
6214
fe1e5c53 6215GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6216/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6217GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6218
cbfb6ae9
AJ		 6219GEN_VR_STVE(bx, 0x07, 0x04);
6220GEN_VR_STVE(hx, 0x07, 0x05);
6221GEN_VR_STVE(wx, 0x07, 0x06);
6222
bf8d8ded
AJ		 6223GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6224{
6225 TCGv_ptr rd;
6226 TCGv EA;
6227 if (unlikely(!ctx->altivec_enabled)) {
6228 gen_exception(ctx, POWERPC_EXCP_VPU);
6229 return;
6230 }
6231 EA = tcg_temp_new();
6232 gen_addr_reg_index(ctx, EA);
6233 rd = gen_avr_ptr(rD(ctx->opcode));
6234 gen_helper_lvsl(rd, EA);
6235 tcg_temp_free(EA);
6236 tcg_temp_free_ptr(rd);
6237}
6238
6239GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6240{
6241 TCGv_ptr rd;
6242 TCGv EA;
6243 if (unlikely(!ctx->altivec_enabled)) {
6244 gen_exception(ctx, POWERPC_EXCP_VPU);
6245 return;
6246 }
6247 EA = tcg_temp_new();
6248 gen_addr_reg_index(ctx, EA);
6249 rd = gen_avr_ptr(rD(ctx->opcode));
6250 gen_helper_lvsr(rd, EA);
6251 tcg_temp_free(EA);
6252 tcg_temp_free_ptr(rd);
6253}
6254
785f451b
AJ		 6255GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6256{
6257 TCGv_i32 t;
6258 if (unlikely(!ctx->altivec_enabled)) {
6259 gen_exception(ctx, POWERPC_EXCP_VPU);
6260 return;
6261 }
6262 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6263 t = tcg_temp_new_i32();
6264 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6265 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6266 tcg_temp_free_i32(t);
785f451b
AJ		 6267}
6268
6269GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6270{
6e87b7c7 6271 TCGv_ptr p;
785f451b
AJ		 6272 if (unlikely(!ctx->altivec_enabled)) {
6273 gen_exception(ctx, POWERPC_EXCP_VPU);
6274 return;
6275 }
6e87b7c7
AJ		 6276 p = gen_avr_ptr(rD(ctx->opcode));
6277 gen_helper_mtvscr(p);
6278 tcg_temp_free_ptr(p);
785f451b
AJ		 6279}
6280
7a9b96cf
AJ		 6281/* Logical operations */
6282#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6283GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6284{ \
6285 if (unlikely(!ctx->altivec_enabled)) { \
6286 gen_exception(ctx, POWERPC_EXCP_VPU); \
6287 return; \
6288 } \
6289 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6290 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6291}
6292
6293GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6294GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6295GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6296GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6297GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6298
8e27dd6f
AJ		 6299#define GEN_VXFORM(name, opc2, opc3) \
6300GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6301{ \
6302 TCGv_ptr ra, rb, rd; \
6303 if (unlikely(!ctx->altivec_enabled)) { \
6304 gen_exception(ctx, POWERPC_EXCP_VPU); \
6305 return; \
6306 } \
6307 ra = gen_avr_ptr(rA(ctx->opcode)); \
6308 rb = gen_avr_ptr(rB(ctx->opcode)); \
6309 rd = gen_avr_ptr(rD(ctx->opcode)); \
6310 gen_helper_##name (rd, ra, rb); \
6311 tcg_temp_free_ptr(ra); \
6312 tcg_temp_free_ptr(rb); \
6313 tcg_temp_free_ptr(rd); \
6314}
6315
7872c51c
AJ		 6316GEN_VXFORM(vaddubm, 0, 0);
6317GEN_VXFORM(vadduhm, 0, 1);
6318GEN_VXFORM(vadduwm, 0, 2);
6319GEN_VXFORM(vsububm, 0, 16);
6320GEN_VXFORM(vsubuhm, 0, 17);
6321GEN_VXFORM(vsubuwm, 0, 18);
e4039339
AJ		 6322GEN_VXFORM(vmaxub, 1, 0);
6323GEN_VXFORM(vmaxuh, 1, 1);
6324GEN_VXFORM(vmaxuw, 1, 2);
6325GEN_VXFORM(vmaxsb, 1, 4);
6326GEN_VXFORM(vmaxsh, 1, 5);
6327GEN_VXFORM(vmaxsw, 1, 6);
6328GEN_VXFORM(vminub, 1, 8);
6329GEN_VXFORM(vminuh, 1, 9);
6330GEN_VXFORM(vminuw, 1, 10);
6331GEN_VXFORM(vminsb, 1, 12);
6332GEN_VXFORM(vminsh, 1, 13);
6333GEN_VXFORM(vminsw, 1, 14);
fab3cbe9
AJ		 6334GEN_VXFORM(vavgub, 1, 16);
6335GEN_VXFORM(vavguh, 1, 17);
6336GEN_VXFORM(vavguw, 1, 18);
6337GEN_VXFORM(vavgsb, 1, 20);
6338GEN_VXFORM(vavgsh, 1, 21);
6339GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 6340GEN_VXFORM(vmrghb, 6, 0);
6341GEN_VXFORM(vmrghh, 6, 1);
6342GEN_VXFORM(vmrghw, 6, 2);
6343GEN_VXFORM(vmrglb, 6, 4);
6344GEN_VXFORM(vmrglh, 6, 5);
6345GEN_VXFORM(vmrglw, 6, 6);
2c277908
AJ		 6346GEN_VXFORM(vmuloub, 4, 0);
6347GEN_VXFORM(vmulouh, 4, 1);
6348GEN_VXFORM(vmulosb, 4, 4);
6349GEN_VXFORM(vmulosh, 4, 5);
6350GEN_VXFORM(vmuleub, 4, 8);
6351GEN_VXFORM(vmuleuh, 4, 9);
6352GEN_VXFORM(vmulesb, 4, 12);
6353GEN_VXFORM(vmulesh, 4, 13);
d79f0809
AJ		 6354GEN_VXFORM(vslb, 2, 4);
6355GEN_VXFORM(vslh, 2, 5);
6356GEN_VXFORM(vslw, 2, 6);
07ef34c3
AJ		 6357GEN_VXFORM(vsrb, 2, 8);
6358GEN_VXFORM(vsrh, 2, 9);
6359GEN_VXFORM(vsrw, 2, 10);
6360GEN_VXFORM(vsrab, 2, 12);
6361GEN_VXFORM(vsrah, 2, 13);
6362GEN_VXFORM(vsraw, 2, 14);
7b239bec
AJ		 6363GEN_VXFORM(vslo, 6, 16);
6364GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 6365GEN_VXFORM(vaddcuw, 0, 6);
6366GEN_VXFORM(vsubcuw, 0, 22);
5ab09f33
AJ		 6367GEN_VXFORM(vaddubs, 0, 8);
6368GEN_VXFORM(vadduhs, 0, 9);
6369GEN_VXFORM(vadduws, 0, 10);
6370GEN_VXFORM(vaddsbs, 0, 12);
6371GEN_VXFORM(vaddshs, 0, 13);
6372GEN_VXFORM(vaddsws, 0, 14);
6373GEN_VXFORM(vsububs, 0, 24);
6374GEN_VXFORM(vsubuhs, 0, 25);
6375GEN_VXFORM(vsubuws, 0, 26);
6376GEN_VXFORM(vsubsbs, 0, 28);
6377GEN_VXFORM(vsubshs, 0, 29);
6378GEN_VXFORM(vsubsws, 0, 30);
5e1d0985
AJ		 6379GEN_VXFORM(vrlb, 2, 0);
6380GEN_VXFORM(vrlh, 2, 1);
6381GEN_VXFORM(vrlw, 2, 2);
d9430add
AJ		 6382GEN_VXFORM(vsl, 2, 7);
6383GEN_VXFORM(vsr, 2, 11);
5335a145
AJ		 6384GEN_VXFORM(vpkuhum, 7, 0);
6385GEN_VXFORM(vpkuwum, 7, 1);
6386GEN_VXFORM(vpkuhus, 7, 2);
6387GEN_VXFORM(vpkuwus, 7, 3);
6388GEN_VXFORM(vpkshus, 7, 4);
6389GEN_VXFORM(vpkswus, 7, 5);
6390GEN_VXFORM(vpkshss, 7, 6);
6391GEN_VXFORM(vpkswss, 7, 7);
1dd9ffb9 6392GEN_VXFORM(vpkpx, 7, 12);
8142cddd
AJ		 6393GEN_VXFORM(vsum4ubs, 4, 24);
6394GEN_VXFORM(vsum4sbs, 4, 28);
6395GEN_VXFORM(vsum4shs, 4, 25);
6396GEN_VXFORM(vsum2sws, 4, 26);
6397GEN_VXFORM(vsumsws, 4, 30);
56fdd213
AJ		 6398GEN_VXFORM(vaddfp, 5, 0);
6399GEN_VXFORM(vsubfp, 5, 1);
1536ff64
AJ		 6400GEN_VXFORM(vmaxfp, 5, 16);
6401GEN_VXFORM(vminfp, 5, 17);
fab3cbe9 6402
0cbcd906
AJ		 6403#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6404 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6405 { \
6406 TCGv_ptr ra, rb, rd; \
6407 if (unlikely(!ctx->altivec_enabled)) { \
6408 gen_exception(ctx, POWERPC_EXCP_VPU); \
6409 return; \
6410 } \
6411 ra = gen_avr_ptr(rA(ctx->opcode)); \
6412 rb = gen_avr_ptr(rB(ctx->opcode)); \
6413 rd = gen_avr_ptr(rD(ctx->opcode)); \
6414 gen_helper_##opname (rd, ra, rb); \
6415 tcg_temp_free_ptr(ra); \
6416 tcg_temp_free_ptr(rb); \
6417 tcg_temp_free_ptr(rd); \
6418 }
6419
6420#define GEN_VXRFORM(name, opc2, opc3) \
6421 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6422 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6423
1add6e23
AJ		 6424GEN_VXRFORM(vcmpequb, 3, 0)
6425GEN_VXRFORM(vcmpequh, 3, 1)
6426GEN_VXRFORM(vcmpequw, 3, 2)
6427GEN_VXRFORM(vcmpgtsb, 3, 12)
6428GEN_VXRFORM(vcmpgtsh, 3, 13)
6429GEN_VXRFORM(vcmpgtsw, 3, 14)
6430GEN_VXRFORM(vcmpgtub, 3, 8)
6431GEN_VXRFORM(vcmpgtuh, 3, 9)
6432GEN_VXRFORM(vcmpgtuw, 3, 10)
819ca121
AJ		 6433GEN_VXRFORM(vcmpeqfp, 3, 3)
6434GEN_VXRFORM(vcmpgefp, 3, 7)
6435GEN_VXRFORM(vcmpgtfp, 3, 11)
6436GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 6437
c026766b
AJ		 6438#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6439 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6440 { \
6441 TCGv_ptr rd; \
6442 TCGv_i32 simm; \
6443 if (unlikely(!ctx->altivec_enabled)) { \
6444 gen_exception(ctx, POWERPC_EXCP_VPU); \
6445 return; \
6446 } \
6447 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6448 rd = gen_avr_ptr(rD(ctx->opcode)); \
6449 gen_helper_##name (rd, simm); \
6450 tcg_temp_free_i32(simm); \
6451 tcg_temp_free_ptr(rd); \
6452 }
6453
6454GEN_VXFORM_SIMM(vspltisb, 6, 12);
6455GEN_VXFORM_SIMM(vspltish, 6, 13);
6456GEN_VXFORM_SIMM(vspltisw, 6, 14);
6457
de5f2484
AJ		 6458#define GEN_VXFORM_NOA(name, opc2, opc3) \
6459 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6460 { \
6461 TCGv_ptr rb, rd; \
6462 if (unlikely(!ctx->altivec_enabled)) { \
6463 gen_exception(ctx, POWERPC_EXCP_VPU); \
6464 return; \
6465 } \
6466 rb = gen_avr_ptr(rB(ctx->opcode)); \
6467 rd = gen_avr_ptr(rD(ctx->opcode)); \
6468 gen_helper_##name (rd, rb); \
6469 tcg_temp_free_ptr(rb); \
6470 tcg_temp_free_ptr(rd); \
6471 }
6472
6cf1c6e5
AJ		 6473GEN_VXFORM_NOA(vupkhsb, 7, 8);
6474GEN_VXFORM_NOA(vupkhsh, 7, 9);
6475GEN_VXFORM_NOA(vupklsb, 7, 10);
6476GEN_VXFORM_NOA(vupklsh, 7, 11);
79f85c3a
AJ		 6477GEN_VXFORM_NOA(vupkhpx, 7, 13);
6478GEN_VXFORM_NOA(vupklpx, 7, 15);
bdfbac35 6479GEN_VXFORM_NOA(vrefp, 5, 4);
071fc3b1 6480GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
b580763f 6481GEN_VXFORM_NOA(vlogefp, 5, 7);
f6b19645
AJ		 6482GEN_VXFORM_NOA(vrfim, 5, 8);
6483GEN_VXFORM_NOA(vrfin, 5, 9);
6484GEN_VXFORM_NOA(vrfip, 5, 10);
6485GEN_VXFORM_NOA(vrfiz, 5, 11);
79f85c3a 6486
21d21583
AJ		 6487#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6488 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6489 { \
6490 TCGv_ptr rd; \
6491 TCGv_i32 simm; \
6492 if (unlikely(!ctx->altivec_enabled)) { \
6493 gen_exception(ctx, POWERPC_EXCP_VPU); \
6494 return; \
6495 } \
6496 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6497 rd = gen_avr_ptr(rD(ctx->opcode)); \
6498 gen_helper_##name (rd, simm); \
6499 tcg_temp_free_i32(simm); \
6500 tcg_temp_free_ptr(rd); \
6501 }
6502
27a4edb3
AJ		 6503#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6504 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6505 { \
6506 TCGv_ptr rb, rd; \
6507 TCGv_i32 uimm; \
6508 if (unlikely(!ctx->altivec_enabled)) { \
6509 gen_exception(ctx, POWERPC_EXCP_VPU); \
6510 return; \
6511 } \
6512 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6513 rb = gen_avr_ptr(rB(ctx->opcode)); \
6514 rd = gen_avr_ptr(rD(ctx->opcode)); \
6515 gen_helper_##name (rd, rb, uimm); \
6516 tcg_temp_free_i32(uimm); \
6517 tcg_temp_free_ptr(rb); \
6518 tcg_temp_free_ptr(rd); \
6519 }
6520
e4e6bee7
AJ		 6521GEN_VXFORM_UIMM(vspltb, 6, 8);
6522GEN_VXFORM_UIMM(vsplth, 6, 9);
6523GEN_VXFORM_UIMM(vspltw, 6, 10);
e140632e
AJ		 6524GEN_VXFORM_UIMM(vcfux, 5, 12);
6525GEN_VXFORM_UIMM(vcfsx, 5, 13);
875b31db
AJ		 6526GEN_VXFORM_UIMM(vctuxs, 5, 14);
6527GEN_VXFORM_UIMM(vctsxs, 5, 15);
e4e6bee7 6528
cd633b10
AJ		 6529GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6530{
6531 TCGv_ptr ra, rb, rd;
fce5ecb7 6532 TCGv_i32 sh;
cd633b10
AJ		 6533 if (unlikely(!ctx->altivec_enabled)) {
6534 gen_exception(ctx, POWERPC_EXCP_VPU);
6535 return;
6536 }
6537 ra = gen_avr_ptr(rA(ctx->opcode));
6538 rb = gen_avr_ptr(rB(ctx->opcode));
6539 rd = gen_avr_ptr(rD(ctx->opcode));
6540 sh = tcg_const_i32(VSH(ctx->opcode));
6541 gen_helper_vsldoi (rd, ra, rb, sh);
6542 tcg_temp_free_ptr(ra);
6543 tcg_temp_free_ptr(rb);
6544 tcg_temp_free_ptr(rd);
fce5ecb7 6545 tcg_temp_free_i32(sh);
cd633b10
AJ		 6546}
6547
707cec33
AJ		 6548#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6549 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6550 { \
6551 TCGv_ptr ra, rb, rc, rd; \
6552 if (unlikely(!ctx->altivec_enabled)) { \
6553 gen_exception(ctx, POWERPC_EXCP_VPU); \
6554 return; \
6555 } \
6556 ra = gen_avr_ptr(rA(ctx->opcode)); \
6557 rb = gen_avr_ptr(rB(ctx->opcode)); \
6558 rc = gen_avr_ptr(rC(ctx->opcode)); \
6559 rd = gen_avr_ptr(rD(ctx->opcode)); \
6560 if (Rc(ctx->opcode)) { \
6561 gen_helper_##name1 (rd, ra, rb, rc); \
6562 } else { \
6563 gen_helper_##name0 (rd, ra, rb, rc); \
6564 } \
6565 tcg_temp_free_ptr(ra); \
6566 tcg_temp_free_ptr(rb); \
6567 tcg_temp_free_ptr(rc); \
6568 tcg_temp_free_ptr(rd); \
6569 }
6570
b161ae27
AJ		 6571GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6572
bcd2ee23
AJ		 6573GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6574{
6575 TCGv_ptr ra, rb, rc, rd;
6576 if (unlikely(!ctx->altivec_enabled)) {
6577 gen_exception(ctx, POWERPC_EXCP_VPU);
6578 return;
6579 }
6580 ra = gen_avr_ptr(rA(ctx->opcode));
6581 rb = gen_avr_ptr(rB(ctx->opcode));
6582 rc = gen_avr_ptr(rC(ctx->opcode));
6583 rd = gen_avr_ptr(rD(ctx->opcode));
6584 gen_helper_vmladduhm(rd, ra, rb, rc);
6585 tcg_temp_free_ptr(ra);
6586 tcg_temp_free_ptr(rb);
6587 tcg_temp_free_ptr(rc);
6588 tcg_temp_free_ptr(rd);
6589}
6590
b04ae981 6591GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 6592GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 6593GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 6594GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 6595GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 6596
0487d6a8 6597/*** SPE extension ***/
0487d6a8 6598/* Register moves */
3cd7d1dd 6599
a7812ae4 6600static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6601#if defined(TARGET_PPC64)
6602 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6603#else
36aa55dc 6604 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6605#endif
f78fb44e 6606}
3cd7d1dd 6607
a7812ae4 6608static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6609#if defined(TARGET_PPC64)
6610 tcg_gen_mov_i64(cpu_gpr[reg], t);
6611#else
a7812ae4 6612 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6613 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6614 tcg_gen_shri_i64(tmp, t, 32);
6615 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6616 tcg_temp_free_i64(tmp);
3cd7d1dd 6617#endif
f78fb44e 6618}
3cd7d1dd 6619
0487d6a8
JM		 6620#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6621GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6622{ \
6623 if (Rc(ctx->opcode)) \
6624 gen_##name1(ctx); \
6625 else \
6626 gen_##name0(ctx); \
6627}
6628
6629/* Handler for undefined SPE opcodes */
b068d6a7 6630static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6631{
e06fcd75 6632 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 6633}
6634
57951c27
AJ		 6635/* SPE logic */
6636#if defined(TARGET_PPC64)
6637#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6638static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6639{ \
6640 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6641 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6642 return; \
6643 } \
57951c27
AJ		 6644 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6645 cpu_gpr[rB(ctx->opcode)]); \
6646}
6647#else
6648#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6649static always_inline void gen_##name (DisasContext *ctx) \
6650{ \
6651 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6652 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6653 return; \
6654 } \
6655 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6656 cpu_gpr[rB(ctx->opcode)]); \
6657 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6658 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6659}
57951c27
AJ		 6660#endif
6661
6662GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6663GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6664GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6665GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6666GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6667GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6668GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6669GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6670
57951c27
AJ		 6671/* SPE logic immediate */
6672#if defined(TARGET_PPC64)
6673#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6674static always_inline void gen_##name (DisasContext *ctx) \
6675{ \
6676 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6677 gen_exception(ctx, POWERPC_EXCP_APU); \
3d3a6a0a
AJ		 6678 return; \
6679 } \
a7812ae4
PB		 6680 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6681 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6682 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6683 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6684 tcg_opi(t0, t0, rB(ctx->opcode)); \
6685 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6686 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6687 tcg_temp_free_i64(t2); \
57951c27
AJ		 6688 tcg_opi(t1, t1, rB(ctx->opcode)); \
6689 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6690 tcg_temp_free_i32(t0); \
6691 tcg_temp_free_i32(t1); \
3d3a6a0a 6692}
57951c27
AJ		 6693#else
6694#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6695static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6696{ \
6697 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6698 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6699 return; \
6700 } \
57951c27
AJ		 6701 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6702 rB(ctx->opcode)); \
6703 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6704 rB(ctx->opcode)); \
0487d6a8 6705}
57951c27
AJ		 6706#endif
6707GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6708GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6709GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6710GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6711
57951c27
AJ		 6712/* SPE arithmetic */
6713#if defined(TARGET_PPC64)
6714#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6715static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6716{ \
6717 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6718 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6719 return; \
6720 } \
a7812ae4
PB		 6721 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6722 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6723 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6724 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6725 tcg_op(t0, t0); \
6726 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6727 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6728 tcg_temp_free_i64(t2); \
57951c27
AJ		 6729 tcg_op(t1, t1); \
6730 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6731 tcg_temp_free_i32(t0); \
6732 tcg_temp_free_i32(t1); \
0487d6a8 6733}
57951c27 6734#else
a7812ae4 6735#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6736static always_inline void gen_##name (DisasContext *ctx) \
6737{ \
6738 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6739 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6740 return; \
6741 } \
6742 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6743 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6744}
6745#endif
0487d6a8 6746
a7812ae4 6747static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6748{
6749 int l1 = gen_new_label();
6750 int l2 = gen_new_label();
0487d6a8 6751
57951c27
AJ		 6752 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6753 tcg_gen_neg_i32(ret, arg1);
6754 tcg_gen_br(l2);
6755 gen_set_label(l1);
a7812ae4 6756 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6757 gen_set_label(l2);
6758}
6759GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6760GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6761GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6762GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6763static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6764{
57951c27
AJ		 6765 tcg_gen_addi_i32(ret, arg1, 0x8000);
6766 tcg_gen_ext16u_i32(ret, ret);
6767}
6768GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6769GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6770GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6771
57951c27
AJ		 6772#if defined(TARGET_PPC64)
6773#define GEN_SPEOP_ARITH2(name, tcg_op) \
6774static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6775{ \
6776 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6777 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6778 return; \
6779 } \
a7812ae4
PB		 6780 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6781 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6782 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
501e23c4 6783 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6784 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6785 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6786 tcg_op(t0, t0, t2); \
6787 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6788 tcg_gen_trunc_i64_i32(t1, t3); \
6789 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6790 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6791 tcg_temp_free_i64(t3); \
57951c27 6792 tcg_op(t1, t1, t2); \
a7812ae4 6793 tcg_temp_free_i32(t2); \
57951c27 6794 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6795 tcg_temp_free_i32(t0); \
6796 tcg_temp_free_i32(t1); \
0487d6a8 6797}
57951c27
AJ		 6798#else
6799#define GEN_SPEOP_ARITH2(name, tcg_op) \
6800static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6801{ \
6802 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6803 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6804 return; \
6805 } \
57951c27
AJ		 6806 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6807 cpu_gpr[rB(ctx->opcode)]); \
6808 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6809 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6810}
57951c27 6811#endif
0487d6a8 6812
a7812ae4 6813static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6814{
a7812ae4 6815 TCGv_i32 t0;
57951c27 6816 int l1, l2;
0487d6a8 6817
57951c27
AJ		 6818 l1 = gen_new_label();
6819 l2 = gen_new_label();
a7812ae4 6820 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6821 /* No error here: 6 bits are used */
6822 tcg_gen_andi_i32(t0, arg2, 0x3F);
6823 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6824 tcg_gen_shr_i32(ret, arg1, t0);
6825 tcg_gen_br(l2);
6826 gen_set_label(l1);
6827 tcg_gen_movi_i32(ret, 0);
6828 tcg_gen_br(l2);
a7812ae4 6829 tcg_temp_free_i32(t0);
57951c27
AJ		 6830}
6831GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6832static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6833{
a7812ae4 6834 TCGv_i32 t0;
57951c27
AJ		 6835 int l1, l2;
6836
6837 l1 = gen_new_label();
6838 l2 = gen_new_label();
a7812ae4 6839 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6840 /* No error here: 6 bits are used */
6841 tcg_gen_andi_i32(t0, arg2, 0x3F);
6842 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6843 tcg_gen_sar_i32(ret, arg1, t0);
6844 tcg_gen_br(l2);
6845 gen_set_label(l1);
6846 tcg_gen_movi_i32(ret, 0);
6847 tcg_gen_br(l2);
a7812ae4 6848 tcg_temp_free_i32(t0);
57951c27
AJ		 6849}
6850GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6851static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6852{
a7812ae4 6853 TCGv_i32 t0;
57951c27
AJ		 6854 int l1, l2;
6855
6856 l1 = gen_new_label();
6857 l2 = gen_new_label();
a7812ae4 6858 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6859 /* No error here: 6 bits are used */
6860 tcg_gen_andi_i32(t0, arg2, 0x3F);
6861 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6862 tcg_gen_shl_i32(ret, arg1, t0);
6863 tcg_gen_br(l2);
6864 gen_set_label(l1);
6865 tcg_gen_movi_i32(ret, 0);
6866 tcg_gen_br(l2);
a7812ae4 6867 tcg_temp_free_i32(t0);
57951c27
AJ		 6868}
6869GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6870static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6871{
a7812ae4 6872 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6873 tcg_gen_andi_i32(t0, arg2, 0x1F);
6874 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6875 tcg_temp_free_i32(t0);
57951c27
AJ		 6876}
6877GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6878static always_inline void gen_evmergehi (DisasContext *ctx)
6879{
6880 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6881 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6882 return;
6883 }
6884#if defined(TARGET_PPC64)
a7812ae4
PB		 6885 TCGv t0 = tcg_temp_new();
6886 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6887 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6888 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6889 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6890 tcg_temp_free(t0);
6891 tcg_temp_free(t1);
6892#else
6893 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6894 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6895#endif
6896}
6897GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6898static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6899{
57951c27
AJ		 6900 tcg_gen_sub_i32(ret, arg2, arg1);
6901}
6902GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6903
57951c27
AJ		 6904/* SPE arithmetic immediate */
6905#if defined(TARGET_PPC64)
6906#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6907static always_inline void gen_##name (DisasContext *ctx) \
6908{ \
6909 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6910 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6911 return; \
6912 } \
a7812ae4
PB		 6913 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6914 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6915 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6916 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6917 tcg_op(t0, t0, rA(ctx->opcode)); \
6918 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6919 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 6920 tcg_temp_free_i64(t2); \
57951c27
AJ		 6921 tcg_op(t1, t1, rA(ctx->opcode)); \
6922 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6923 tcg_temp_free_i32(t0); \
6924 tcg_temp_free_i32(t1); \
57951c27
AJ		 6925}
6926#else
6927#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6928static always_inline void gen_##name (DisasContext *ctx) \
6929{ \
6930 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6931 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6932 return; \
6933 } \
6934 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6935 rA(ctx->opcode)); \
6936 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6937 rA(ctx->opcode)); \
6938}
6939#endif
6940GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6941GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6942
6943/* SPE comparison */
6944#if defined(TARGET_PPC64)
6945#define GEN_SPEOP_COMP(name, tcg_cond) \
6946static always_inline void gen_##name (DisasContext *ctx) \
6947{ \
6948 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6949 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6950 return; \
6951 } \
6952 int l1 = gen_new_label(); \
6953 int l2 = gen_new_label(); \
6954 int l3 = gen_new_label(); \
6955 int l4 = gen_new_label(); \
a7812ae4
PB		 6956 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6957 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6958 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6959 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6960 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6961 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6962 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6963 tcg_gen_br(l2); \
6964 gen_set_label(l1); \
6965 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6966 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6967 gen_set_label(l2); \
6968 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6969 tcg_gen_trunc_i64_i32(t0, t2); \
6970 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6971 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6972 tcg_temp_free_i64(t2); \
57951c27
AJ		 6973 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6974 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6975 ~(CRF_CH | CRF_CH_AND_CL)); \
6976 tcg_gen_br(l4); \
6977 gen_set_label(l3); \
6978 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6979 CRF_CH | CRF_CH_OR_CL); \
6980 gen_set_label(l4); \
a7812ae4
PB		 6981 tcg_temp_free_i32(t0); \
6982 tcg_temp_free_i32(t1); \
57951c27
AJ		 6983}
6984#else
6985#define GEN_SPEOP_COMP(name, tcg_cond) \
6986static always_inline void gen_##name (DisasContext *ctx) \
6987{ \
6988 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6989 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6990 return; \
6991 } \
6992 int l1 = gen_new_label(); \
6993 int l2 = gen_new_label(); \
6994 int l3 = gen_new_label(); \
6995 int l4 = gen_new_label(); \
6996 \
6997 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6998 cpu_gpr[rB(ctx->opcode)], l1); \
6999 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7000 tcg_gen_br(l2); \
7001 gen_set_label(l1); \
7002 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7003 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7004 gen_set_label(l2); \
7005 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7006 cpu_gprh[rB(ctx->opcode)], l3); \
7007 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7008 ~(CRF_CH | CRF_CH_AND_CL)); \
7009 tcg_gen_br(l4); \
7010 gen_set_label(l3); \
7011 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7012 CRF_CH | CRF_CH_OR_CL); \
7013 gen_set_label(l4); \
7014}
7015#endif
7016GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7017GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7018GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7019GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7020GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7021
7022/* SPE misc */
7023static always_inline void gen_brinc (DisasContext *ctx)
7024{
7025 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 7026 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7027 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 7028}
57951c27
AJ		 7029static always_inline void gen_evmergelo (DisasContext *ctx)
7030{
7031 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7032 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7033 return;
7034 }
7035#if defined(TARGET_PPC64)
a7812ae4
PB		 7036 TCGv t0 = tcg_temp_new();
7037 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7038 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7039 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7040 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7041 tcg_temp_free(t0);
7042 tcg_temp_free(t1);
7043#else
7044 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7045 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7046#endif
7047}
7048static always_inline void gen_evmergehilo (DisasContext *ctx)
7049{
7050 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7051 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7052 return;
7053 }
7054#if defined(TARGET_PPC64)
a7812ae4
PB		 7055 TCGv t0 = tcg_temp_new();
7056 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7057 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7058 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7059 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7060 tcg_temp_free(t0);
7061 tcg_temp_free(t1);
7062#else
7063 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7064 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7065#endif
7066}
7067static always_inline void gen_evmergelohi (DisasContext *ctx)
7068{
7069 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7070 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7071 return;
7072 }
7073#if defined(TARGET_PPC64)
a7812ae4
PB		 7074 TCGv t0 = tcg_temp_new();
7075 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7076 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7077 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7078 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7079 tcg_temp_free(t0);
7080 tcg_temp_free(t1);
7081#else
7082 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7083 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7084#endif
7085}
7086static always_inline void gen_evsplati (DisasContext *ctx)
7087{
38d14952 7088 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 7089
57951c27 7090#if defined(TARGET_PPC64)
38d14952 7091 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7092#else
7093 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7094 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7095#endif
7096}
b068d6a7 7097static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 7098{
38d14952 7099 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 7100
57951c27 7101#if defined(TARGET_PPC64)
38d14952 7102 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7103#else
7104 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7105 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7106#endif
0487d6a8
JM		 7107}
7108
57951c27
AJ		 7109static always_inline void gen_evsel (DisasContext *ctx)
7110{
7111 int l1 = gen_new_label();
7112 int l2 = gen_new_label();
7113 int l3 = gen_new_label();
7114 int l4 = gen_new_label();
a7812ae4 7115 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 7116#if defined(TARGET_PPC64)
a7812ae4
PB		 7117 TCGv t1 = tcg_temp_local_new();
7118 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 7119#endif
7120 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7121 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7122#if defined(TARGET_PPC64)
7123 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7124#else
7125 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7126#endif
7127 tcg_gen_br(l2);
7128 gen_set_label(l1);
7129#if defined(TARGET_PPC64)
7130 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7131#else
7132 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7133#endif
7134 gen_set_label(l2);
7135 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7136 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7137#if defined(TARGET_PPC64)
7138 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7139#else
7140 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7141#endif
7142 tcg_gen_br(l4);
7143 gen_set_label(l3);
7144#if defined(TARGET_PPC64)
7145 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7146#else
7147 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7148#endif
7149 gen_set_label(l4);
a7812ae4 7150 tcg_temp_free_i32(t0);
57951c27
AJ		 7151#if defined(TARGET_PPC64)
7152 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7153 tcg_temp_free(t1);
7154 tcg_temp_free(t2);
7155#endif
7156}
7157GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7158{
7159 gen_evsel(ctx);
7160}
7161GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7162{
7163 gen_evsel(ctx);
7164}
7165GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7166{
7167 gen_evsel(ctx);
7168}
7169GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7170{
7171 gen_evsel(ctx);
7172}
0487d6a8
JM		 7173
7174GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7175GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7176GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7177GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7178GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7179GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7180GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7181GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7182GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7183GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7184GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7185GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7186GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7187GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7188GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7189GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7190GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7191GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7192GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7193GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7194GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7195GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7196GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7197GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7198GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7199
6a6ae23f 7200/* SPE load and stores */
76db3ba4 7201static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 7202{
7203 target_ulong uimm = rB(ctx->opcode);
7204
76db3ba4 7205 if (rA(ctx->opcode) == 0) {
6a6ae23f 7206 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 7207 } else {
6a6ae23f 7208 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
76db3ba4
AJ		 7209#if defined(TARGET_PPC64)
7210 if (!ctx->sf_mode) {
7211 tcg_gen_ext32u_tl(EA, EA);
7212 }
7213#endif
7214 }
0487d6a8 7215}
6a6ae23f
AJ		 7216
7217static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7218{
7219#if defined(TARGET_PPC64)
76db3ba4 7220 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7221#else
7222 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 7223 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 7224 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7225 tcg_gen_shri_i64(t0, t0, 32);
7226 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7227 tcg_temp_free_i64(t0);
7228#endif
0487d6a8 7229}
6a6ae23f
AJ		 7230
7231static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7232{
0487d6a8 7233#if defined(TARGET_PPC64)
6a6ae23f 7234 TCGv t0 = tcg_temp_new();
76db3ba4 7235 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 7236 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 7237 gen_addr_add(ctx, addr, addr, 4);
7238 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 7239 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7240 tcg_temp_free(t0);
7241#else
76db3ba4
AJ		 7242 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7243 gen_addr_add(ctx, addr, addr, 4);
7244 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 7245#endif
0487d6a8 7246}
6a6ae23f
AJ		 7247
7248static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7249{
7250 TCGv t0 = tcg_temp_new();
7251#if defined(TARGET_PPC64)
76db3ba4 7252 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7253 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7254 gen_addr_add(ctx, addr, addr, 2);
7255 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7256 tcg_gen_shli_tl(t0, t0, 32);
7257 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7258 gen_addr_add(ctx, addr, addr, 2);
7259 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7260 tcg_gen_shli_tl(t0, t0, 16);
7261 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7262 gen_addr_add(ctx, addr, addr, 2);
7263 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7264 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7265#else
76db3ba4 7266 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7267 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7268 gen_addr_add(ctx, addr, addr, 2);
7269 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7270 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7271 gen_addr_add(ctx, addr, addr, 2);
7272 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7273 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7274 gen_addr_add(ctx, addr, addr, 2);
7275 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7276 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7277#endif
6a6ae23f 7278 tcg_temp_free(t0);
0487d6a8
JM		 7279}
7280
6a6ae23f
AJ		 7281static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7282{
7283 TCGv t0 = tcg_temp_new();
76db3ba4 7284 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7285#if defined(TARGET_PPC64)
7286 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7287 tcg_gen_shli_tl(t0, t0, 16);
7288 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7289#else
7290 tcg_gen_shli_tl(t0, t0, 16);
7291 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7292 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7293#endif
7294 tcg_temp_free(t0);
0487d6a8
JM		 7295}
7296
6a6ae23f
AJ		 7297static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7298{
7299 TCGv t0 = tcg_temp_new();
76db3ba4 7300 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7301#if defined(TARGET_PPC64)
7302 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7303 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7304#else
7305 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7306 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7307#endif
7308 tcg_temp_free(t0);
0487d6a8
JM		 7309}
7310
6a6ae23f
AJ		 7311static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7312{
7313 TCGv t0 = tcg_temp_new();
76db3ba4 7314 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7315#if defined(TARGET_PPC64)
7316 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7317 tcg_gen_ext32u_tl(t0, t0);
7318 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7319#else
7320 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7321 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7322#endif
7323 tcg_temp_free(t0);
7324}
7325
7326static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7327{
7328 TCGv t0 = tcg_temp_new();
7329#if defined(TARGET_PPC64)
76db3ba4 7330 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7331 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7332 gen_addr_add(ctx, addr, addr, 2);
7333 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7334 tcg_gen_shli_tl(t0, t0, 16);
7335 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7336#else
76db3ba4 7337 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7338 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7339 gen_addr_add(ctx, addr, addr, 2);
7340 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7341 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7342#endif
7343 tcg_temp_free(t0);
7344}
7345
7346static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7347{
7348#if defined(TARGET_PPC64)
7349 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 7350 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7351 gen_addr_add(ctx, addr, addr, 2);
7352 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7353 tcg_gen_shli_tl(t0, t0, 32);
7354 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7355 tcg_temp_free(t0);
7356#else
76db3ba4
AJ		 7357 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7358 gen_addr_add(ctx, addr, addr, 2);
7359 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7360#endif
7361}
7362
7363static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7364{
7365#if defined(TARGET_PPC64)
7366 TCGv t0 = tcg_temp_new();
76db3ba4 7367 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 7368 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7369 gen_addr_add(ctx, addr, addr, 2);
7370 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7371 tcg_gen_shli_tl(t0, t0, 32);
7372 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7373 tcg_temp_free(t0);
7374#else
76db3ba4
AJ		 7375 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7376 gen_addr_add(ctx, addr, addr, 2);
7377 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7378#endif
7379}
7380
7381static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7382{
7383 TCGv t0 = tcg_temp_new();
76db3ba4 7384 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 7385#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7386 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7387 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7388#else
7389 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7390 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7391#endif
7392 tcg_temp_free(t0);
7393}
7394
7395static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7396{
7397 TCGv t0 = tcg_temp_new();
7398#if defined(TARGET_PPC64)
76db3ba4 7399 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7400 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7401 tcg_gen_shli_tl(t0, t0, 32);
7402 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7403 gen_addr_add(ctx, addr, addr, 2);
7404 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7405 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7406 tcg_gen_shli_tl(t0, t0, 16);
7407 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7408#else
76db3ba4 7409 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7410 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7411 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7412 gen_addr_add(ctx, addr, addr, 2);
7413 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7414 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7415 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 7416#endif
6a6ae23f
AJ		 7417 tcg_temp_free(t0);
7418}
7419
7420static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7421{
7422#if defined(TARGET_PPC64)
76db3ba4 7423 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 7424#else
6a6ae23f
AJ		 7425 TCGv_i64 t0 = tcg_temp_new_i64();
7426 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 7427 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 7428 tcg_temp_free_i64(t0);
7429#endif
7430}
7431
7432static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7433{
0487d6a8 7434#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7435 TCGv t0 = tcg_temp_new();
7436 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7437 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7438 tcg_temp_free(t0);
7439#else
76db3ba4 7440 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7441#endif
76db3ba4
AJ		 7442 gen_addr_add(ctx, addr, addr, 4);
7443 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7444}
7445
7446static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7447{
7448 TCGv t0 = tcg_temp_new();
7449#if defined(TARGET_PPC64)
7450 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7451#else
7452 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7453#endif
76db3ba4
AJ		 7454 gen_qemu_st16(ctx, t0, addr);
7455 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 7456#if defined(TARGET_PPC64)
7457 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7458 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7459#else
76db3ba4 7460 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7461#endif
76db3ba4 7462 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7463 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7464 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7465 tcg_temp_free(t0);
76db3ba4
AJ		 7466 gen_addr_add(ctx, addr, addr, 2);
7467 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7468}
7469
7470static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7471{
7472 TCGv t0 = tcg_temp_new();
7473#if defined(TARGET_PPC64)
7474 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7475#else
7476 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7477#endif
76db3ba4
AJ		 7478 gen_qemu_st16(ctx, t0, addr);
7479 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7480 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7481 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7482 tcg_temp_free(t0);
7483}
7484
7485static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7486{
7487#if defined(TARGET_PPC64)
7488 TCGv t0 = tcg_temp_new();
7489 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7490 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7491 tcg_temp_free(t0);
7492#else
76db3ba4 7493 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7494#endif
76db3ba4
AJ		 7495 gen_addr_add(ctx, addr, addr, 2);
7496 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7497}
7498
7499static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7500{
7501#if defined(TARGET_PPC64)
7502 TCGv t0 = tcg_temp_new();
7503 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7504 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7505 tcg_temp_free(t0);
7506#else
76db3ba4 7507 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7508#endif
7509}
7510
7511static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7512{
76db3ba4 7513 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7514}
7515
7516#define GEN_SPEOP_LDST(name, opc2, sh) \
76db3ba4 7517GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6a6ae23f
AJ		 7518{ \
7519 TCGv t0; \
7520 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7521 gen_exception(ctx, POWERPC_EXCP_APU); \
6a6ae23f
AJ		 7522 return; \
7523 } \
76db3ba4 7524 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 7525 t0 = tcg_temp_new(); \
7526 if (Rc(ctx->opcode)) { \
76db3ba4 7527 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 7528 } else { \
76db3ba4 7529 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 7530 } \
7531 gen_op_##name(ctx, t0); \
7532 tcg_temp_free(t0); \
7533}
7534
7535GEN_SPEOP_LDST(evldd, 0x00, 3);
7536GEN_SPEOP_LDST(evldw, 0x01, 3);
7537GEN_SPEOP_LDST(evldh, 0x02, 3);
7538GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7539GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7540GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7541GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7542GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7543GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7544GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7545GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7546
7547GEN_SPEOP_LDST(evstdd, 0x10, 3);
7548GEN_SPEOP_LDST(evstdw, 0x11, 3);
7549GEN_SPEOP_LDST(evstdh, 0x12, 3);
7550GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7551GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7552GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7553GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7554
7555/* Multiply and add - TODO */
7556#if 0
7557GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7558GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7559GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7560GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7561GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7562GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7563GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7564GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7565GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7566GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7567GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7568GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7569
7570GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7571GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7572GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7573GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7574GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7575GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7576GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7577GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7578GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7579GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7580GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7581GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7582GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7583GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7584
7585GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7586GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7587GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7588GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7589GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7590GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7591
7592GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7593GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7594GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7595GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7596GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7597GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7598GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7599GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7600GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7601GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7602GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7603GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7604
7605GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7606GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7607GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7608GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7609GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7610
7611GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7612GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7613GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7614GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7615GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7616GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7617GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7618GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7619GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7620GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7621GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7622GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7623
7624GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7625GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7626GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7627GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7628GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7629#endif
7630
7631/*** SPE floating-point extension ***/
1c97856d
AJ		 7632#if defined(TARGET_PPC64)
7633#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7634static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7635{ \
1c97856d
AJ		 7636 TCGv_i32 t0; \
7637 TCGv t1; \
7638 t0 = tcg_temp_new_i32(); \
7639 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7640 gen_helper_##name(t0, t0); \
7641 t1 = tcg_temp_new(); \
7642 tcg_gen_extu_i32_tl(t1, t0); \
7643 tcg_temp_free_i32(t0); \
7644 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7645 0xFFFFFFFF00000000ULL); \
7646 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7647 tcg_temp_free(t1); \
0487d6a8 7648}
1c97856d
AJ		 7649#define GEN_SPEFPUOP_CONV_32_64(name) \
7650static always_inline void gen_##name (DisasContext *ctx) \
7651{ \
7652 TCGv_i32 t0; \
7653 TCGv t1; \
7654 t0 = tcg_temp_new_i32(); \
7655 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7656 t1 = tcg_temp_new(); \
7657 tcg_gen_extu_i32_tl(t1, t0); \
7658 tcg_temp_free_i32(t0); \
7659 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7660 0xFFFFFFFF00000000ULL); \
7661 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7662 tcg_temp_free(t1); \
7663}
7664#define GEN_SPEFPUOP_CONV_64_32(name) \
7665static always_inline void gen_##name (DisasContext *ctx) \
7666{ \
7667 TCGv_i32 t0 = tcg_temp_new_i32(); \
7668 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7669 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7670 tcg_temp_free_i32(t0); \
7671}
7672#define GEN_SPEFPUOP_CONV_64_64(name) \
7673static always_inline void gen_##name (DisasContext *ctx) \
7674{ \
7675 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7676}
7677#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7678static always_inline void gen_##name (DisasContext *ctx) \
7679{ \
1c97856d
AJ		 7680 TCGv_i32 t0, t1; \
7681 TCGv_i64 t2; \
57951c27 7682 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7683 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7684 return; \
7685 } \
1c97856d
AJ		 7686 t0 = tcg_temp_new_i32(); \
7687 t1 = tcg_temp_new_i32(); \
7688 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7689 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7690 gen_helper_##name(t0, t0, t1); \
7691 tcg_temp_free_i32(t1); \
7692 t2 = tcg_temp_new(); \
7693 tcg_gen_extu_i32_tl(t2, t0); \
7694 tcg_temp_free_i32(t0); \
7695 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7696 0xFFFFFFFF00000000ULL); \
7697 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7698 tcg_temp_free(t2); \
57951c27 7699}
1c97856d 7700#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7701static always_inline void gen_##name (DisasContext *ctx) \
7702{ \
7703 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7704 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7705 return; \
7706 } \
1c97856d
AJ		 7707 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7708 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7709}
1c97856d 7710#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7711static always_inline void gen_##name (DisasContext *ctx) \
7712{ \
1c97856d 7713 TCGv_i32 t0, t1; \
57951c27 7714 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7715 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7716 return; \
7717 } \
1c97856d
AJ		 7718 t0 = tcg_temp_new_i32(); \
7719 t1 = tcg_temp_new_i32(); \
7720 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7721 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7722 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7723 tcg_temp_free_i32(t0); \
7724 tcg_temp_free_i32(t1); \
7725}
7726#define GEN_SPEFPUOP_COMP_64(name) \
7727static always_inline void gen_##name (DisasContext *ctx) \
7728{ \
7729 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7730 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7731 return; \
7732 } \
7733 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7734 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7735}
7736#else
7737#define GEN_SPEFPUOP_CONV_32_32(name) \
7738static always_inline void gen_##name (DisasContext *ctx) \
7739{ \
7740 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7741}
1c97856d
AJ		 7742#define GEN_SPEFPUOP_CONV_32_64(name) \
7743static always_inline void gen_##name (DisasContext *ctx) \
7744{ \
7745 TCGv_i64 t0 = tcg_temp_new_i64(); \
7746 gen_load_gpr64(t0, rB(ctx->opcode)); \
7747 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7748 tcg_temp_free_i64(t0); \
7749}
7750#define GEN_SPEFPUOP_CONV_64_32(name) \
7751static always_inline void gen_##name (DisasContext *ctx) \
7752{ \
7753 TCGv_i64 t0 = tcg_temp_new_i64(); \
7754 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7755 gen_store_gpr64(rD(ctx->opcode), t0); \
7756 tcg_temp_free_i64(t0); \
7757}
7758#define GEN_SPEFPUOP_CONV_64_64(name) \
7759static always_inline void gen_##name (DisasContext *ctx) \
7760{ \
7761 TCGv_i64 t0 = tcg_temp_new_i64(); \
7762 gen_load_gpr64(t0, rB(ctx->opcode)); \
7763 gen_helper_##name(t0, t0); \
7764 gen_store_gpr64(rD(ctx->opcode), t0); \
7765 tcg_temp_free_i64(t0); \
7766}
7767#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7768static always_inline void gen_##name (DisasContext *ctx) \
7769{ \
7770 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7771 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7772 return; \
7773 } \
7774 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7775 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7776}
7777#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7778static always_inline void gen_##name (DisasContext *ctx) \
7779{ \
7780 TCGv_i64 t0, t1; \
7781 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7782 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7783 return; \
7784 } \
7785 t0 = tcg_temp_new_i64(); \
7786 t1 = tcg_temp_new_i64(); \
7787 gen_load_gpr64(t0, rA(ctx->opcode)); \
7788 gen_load_gpr64(t1, rB(ctx->opcode)); \
7789 gen_helper_##name(t0, t0, t1); \
7790 gen_store_gpr64(rD(ctx->opcode), t0); \
7791 tcg_temp_free_i64(t0); \
7792 tcg_temp_free_i64(t1); \
7793}
7794#define GEN_SPEFPUOP_COMP_32(name) \
7795static always_inline void gen_##name (DisasContext *ctx) \
7796{ \
7797 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7798 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7799 return; \
7800 } \
7801 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7802 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7803}
7804#define GEN_SPEFPUOP_COMP_64(name) \
7805static always_inline void gen_##name (DisasContext *ctx) \
7806{ \
7807 TCGv_i64 t0, t1; \
7808 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7809 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7810 return; \
7811 } \
7812 t0 = tcg_temp_new_i64(); \
7813 t1 = tcg_temp_new_i64(); \
7814 gen_load_gpr64(t0, rA(ctx->opcode)); \
7815 gen_load_gpr64(t1, rB(ctx->opcode)); \
7816 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7817 tcg_temp_free_i64(t0); \
7818 tcg_temp_free_i64(t1); \
7819}
7820#endif
57951c27 7821
0487d6a8
JM		 7822/* Single precision floating-point vectors operations */
7823/* Arithmetic */
1c97856d
AJ		 7824GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7825GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7826GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7827GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7828static always_inline void gen_evfsabs (DisasContext *ctx)
7829{
7830 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7831 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7832 return;
7833 }
7834#if defined(TARGET_PPC64)
7835 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7836#else
7837 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7838 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7839#endif
7840}
7841static always_inline void gen_evfsnabs (DisasContext *ctx)
7842{
7843 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7844 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7845 return;
7846 }
7847#if defined(TARGET_PPC64)
7848 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7849#else
7850 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7851 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7852#endif
7853}
7854static always_inline void gen_evfsneg (DisasContext *ctx)
7855{
7856 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7857 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7858 return;
7859 }
7860#if defined(TARGET_PPC64)
7861 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7862#else
7863 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7864 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7865#endif
7866}
7867
0487d6a8 7868/* Conversion */
1c97856d
AJ		 7869GEN_SPEFPUOP_CONV_64_64(evfscfui);
7870GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7871GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7872GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7873GEN_SPEFPUOP_CONV_64_64(evfsctui);
7874GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7875GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7876GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7877GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7878GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7879
0487d6a8 7880/* Comparison */
1c97856d
AJ		 7881GEN_SPEFPUOP_COMP_64(evfscmpgt);
7882GEN_SPEFPUOP_COMP_64(evfscmplt);
7883GEN_SPEFPUOP_COMP_64(evfscmpeq);
7884GEN_SPEFPUOP_COMP_64(evfststgt);
7885GEN_SPEFPUOP_COMP_64(evfststlt);
7886GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7887
7888/* Opcodes definitions */
7889GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7890GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7891GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7892GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7893GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7894GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7895GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7896GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7897GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7898GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7899GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7900GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7901GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7902GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7903
7904/* Single precision floating-point operations */
7905/* Arithmetic */
1c97856d
AJ		 7906GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7907GEN_SPEFPUOP_ARITH2_32_32(efssub);
7908GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7909GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7910static always_inline void gen_efsabs (DisasContext *ctx)
7911{
7912 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7913 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7914 return;
7915 }
7916 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7917}
7918static always_inline void gen_efsnabs (DisasContext *ctx)
7919{
7920 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7921 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7922 return;
7923 }
7924 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7925}
7926static always_inline void gen_efsneg (DisasContext *ctx)
7927{
7928 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7929 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7930 return;
7931 }
7932 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7933}
7934
0487d6a8 7935/* Conversion */
1c97856d
AJ		 7936GEN_SPEFPUOP_CONV_32_32(efscfui);
7937GEN_SPEFPUOP_CONV_32_32(efscfsi);
7938GEN_SPEFPUOP_CONV_32_32(efscfuf);
7939GEN_SPEFPUOP_CONV_32_32(efscfsf);
7940GEN_SPEFPUOP_CONV_32_32(efsctui);
7941GEN_SPEFPUOP_CONV_32_32(efsctsi);
7942GEN_SPEFPUOP_CONV_32_32(efsctuf);
7943GEN_SPEFPUOP_CONV_32_32(efsctsf);
7944GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7945GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7946GEN_SPEFPUOP_CONV_32_64(efscfd);
7947
0487d6a8 7948/* Comparison */
1c97856d
AJ		 7949GEN_SPEFPUOP_COMP_32(efscmpgt);
7950GEN_SPEFPUOP_COMP_32(efscmplt);
7951GEN_SPEFPUOP_COMP_32(efscmpeq);
7952GEN_SPEFPUOP_COMP_32(efststgt);
7953GEN_SPEFPUOP_COMP_32(efststlt);
7954GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7955
7956/* Opcodes definitions */
05332d70 7957GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7958GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7959GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7960GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7961GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7962GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7963GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7964GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7965GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7966GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7967GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7968GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7969GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7970GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7971
7972/* Double precision floating-point operations */
7973/* Arithmetic */
1c97856d
AJ		 7974GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7975GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7976GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7977GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7978static always_inline void gen_efdabs (DisasContext *ctx)
7979{
7980 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7981 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7982 return;
7983 }
7984#if defined(TARGET_PPC64)
7985 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7986#else
7987 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7988#endif
7989}
7990static always_inline void gen_efdnabs (DisasContext *ctx)
7991{
7992 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7993 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7994 return;
7995 }
7996#if defined(TARGET_PPC64)
7997 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7998#else
7999 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8000#endif
8001}
8002static always_inline void gen_efdneg (DisasContext *ctx)
8003{
8004 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 8005 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 8006 return;
8007 }
8008#if defined(TARGET_PPC64)
8009 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8010#else
8011 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8012#endif
8013}
8014
0487d6a8 8015/* Conversion */
1c97856d
AJ		 8016GEN_SPEFPUOP_CONV_64_32(efdcfui);
8017GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8018GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8019GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8020GEN_SPEFPUOP_CONV_32_64(efdctui);
8021GEN_SPEFPUOP_CONV_32_64(efdctsi);
8022GEN_SPEFPUOP_CONV_32_64(efdctuf);
8023GEN_SPEFPUOP_CONV_32_64(efdctsf);
8024GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8025GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8026GEN_SPEFPUOP_CONV_64_32(efdcfs);
8027GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8028GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8029GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8030GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 8031
0487d6a8 8032/* Comparison */
1c97856d
AJ		 8033GEN_SPEFPUOP_COMP_64(efdcmpgt);
8034GEN_SPEFPUOP_COMP_64(efdcmplt);
8035GEN_SPEFPUOP_COMP_64(efdcmpeq);
8036GEN_SPEFPUOP_COMP_64(efdtstgt);
8037GEN_SPEFPUOP_COMP_64(efdtstlt);
8038GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 8039
8040/* Opcodes definitions */
8041GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
8042GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
8043GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
8044GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
8045GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
8046GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
8047GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
8048GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
8049GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
8050GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
8051GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
8052GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
8053GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
8054GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
8055GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
8056GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 8057
79aceca5
FB		 8058/* End opcode list */
8059GEN_OPCODE_MARK(end);
8060
3fc6c082 8061#include "translate_init.c"
0411a972 8062#include "helper_regs.h"
79aceca5 8063
9a64fbe4 8064/*****************************************************************************/
3fc6c082 8065/* Misc PowerPC helpers */
36081602
JM		 8066void cpu_dump_state (CPUState *env, FILE *f,
8067 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8068 int flags)
79aceca5 8069{
3fc6c082
FB		 8070#define RGPL 4
8071#define RFPL 4
3fc6c082 8072
79aceca5
FB		 8073 int i;
8074
077fc206 8075 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 8076 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 8077 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8078 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 8079#if !defined(NO_TIMER_DUMP)
077fc206 8080 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 8081#if !defined(CONFIG_USER_ONLY)
8082 "DECR %08x"
8083#endif
8084 "\n",
077fc206 8085 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 8086#if !defined(CONFIG_USER_ONLY)
8087 , cpu_ppc_load_decr(env)
8088#endif
8089 );
077fc206 8090#endif
76a66253 8091 for (i = 0; i < 32; i++) {
3fc6c082
FB		 8092 if ((i & (RGPL - 1)) == 0)
8093 cpu_fprintf(f, "GPR%02d", i);
6b542af7 8094 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 8095 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 8096 cpu_fprintf(f, "\n");
76a66253 8097 }
3fc6c082 8098 cpu_fprintf(f, "CR ");
76a66253 8099 for (i = 0; i < 8; i++)
7fe48483
FB		 8100 cpu_fprintf(f, "%01x", env->crf[i]);
8101 cpu_fprintf(f, " [");
76a66253
JM		 8102 for (i = 0; i < 8; i++) {
8103 char a = '-';
8104 if (env->crf[i] & 0x08)
8105 a = 'L';
8106 else if (env->crf[i] & 0x04)
8107 a = 'G';
8108 else if (env->crf[i] & 0x02)
8109 a = 'E';
7fe48483 8110 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 8111 }
6b542af7 8112 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 8113 for (i = 0; i < 32; i++) {
8114 if ((i & (RFPL - 1)) == 0)
8115 cpu_fprintf(f, "FPR%02d", i);
26a76461 8116 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 8117 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 8118 cpu_fprintf(f, "\n");
79aceca5 8119 }
7889270a 8120 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
f2e63a42 8121#if !defined(CONFIG_USER_ONLY)
6b542af7 8122 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 8123 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 8124#endif
79aceca5 8125
3fc6c082
FB		 8126#undef RGPL
8127#undef RFPL
79aceca5
FB		 8128}
8129
76a66253
JM		 8130void cpu_dump_statistics (CPUState *env, FILE*f,
8131 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8132 int flags)
8133{
8134#if defined(DO_PPC_STATISTICS)
8135 opc_handler_t **t1, **t2, **t3, *handler;
8136 int op1, op2, op3;
8137
8138 t1 = env->opcodes;
8139 for (op1 = 0; op1 < 64; op1++) {
8140 handler = t1[op1];
8141 if (is_indirect_opcode(handler)) {
8142 t2 = ind_table(handler);
8143 for (op2 = 0; op2 < 32; op2++) {
8144 handler = t2[op2];
8145 if (is_indirect_opcode(handler)) {
8146 t3 = ind_table(handler);
8147 for (op3 = 0; op3 < 32; op3++) {
8148 handler = t3[op3];
8149 if (handler->count == 0)
8150 continue;
8151 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8152 "%016llx %lld\n",
8153 op1, op2, op3, op1, (op3 << 5) | op2,
8154 handler->oname,
8155 handler->count, handler->count);
8156 }
8157 } else {
8158 if (handler->count == 0)
8159 continue;
8160 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8161 "%016llx %lld\n",
8162 op1, op2, op1, op2, handler->oname,
8163 handler->count, handler->count);
8164 }
8165 }
8166 } else {
8167 if (handler->count == 0)
8168 continue;
8169 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8170 op1, op1, handler->oname,
8171 handler->count, handler->count);
8172 }
8173 }
8174#endif
8175}
8176
9a64fbe4 8177/*****************************************************************************/
2cfc5f17
TS		 8178static always_inline void gen_intermediate_code_internal (CPUState *env,
8179 TranslationBlock *tb,
8180 int search_pc)
79aceca5 8181{
9fddaa0c 8182 DisasContext ctx, *ctxp = &ctx;
79aceca5 8183 opc_handler_t **table, *handler;
0fa85d43 8184 target_ulong pc_start;
79aceca5 8185 uint16_t *gen_opc_end;
a1d1bb31 8186 CPUBreakpoint *bp;
79aceca5 8187 int j, lj = -1;
2e70f6ef
PB		 8188 int num_insns;
8189 int max_insns;
79aceca5
FB		 8190
8191 pc_start = tb->pc;
79aceca5 8192 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
046d6672 8193 ctx.nip = pc_start;
79aceca5 8194 ctx.tb = tb;
e1833e1f 8195 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 8196 ctx.spr_cb = env->spr_cb;
76db3ba4
AJ		 8197 ctx.mem_idx = env->mmu_idx;
8198 ctx.access_type = -1;
8199 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 8200#if defined(TARGET_PPC64)
8201 ctx.sf_mode = msr_sf;
9a64fbe4 8202#endif
3cc62370 8203 ctx.fpu_enabled = msr_fp;
a9d9eb8f 8204 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 8205 ctx.spe_enabled = msr_spe;
8206 else
8207 ctx.spe_enabled = 0;
a9d9eb8f
JM		 8208 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8209 ctx.altivec_enabled = msr_vr;
8210 else
8211 ctx.altivec_enabled = 0;
d26bfc9a 8212 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 8213 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 8214 else
8cbcb4fa 8215 ctx.singlestep_enabled = 0;
d26bfc9a 8216 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 8217 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8218 if (unlikely(env->singlestep_enabled))
8219 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 8220#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 8221 /* Single step trace mode */
8222 msr_se = 1;
8223#endif
2e70f6ef
PB		 8224 num_insns = 0;
8225 max_insns = tb->cflags & CF_COUNT_MASK;
8226 if (max_insns == 0)
8227 max_insns = CF_COUNT_MASK;
8228
8229 gen_icount_start();
9a64fbe4 8230 /* Set env in case of segfault during code fetch */
e1833e1f 8231 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 8232 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8233 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 8234 if (bp->pc == ctx.nip) {
e06fcd75 8235 gen_debug_exception(ctxp);
ea4e754f
FB		 8236 break;
8237 }
8238 }
8239 }
76a66253 8240 if (unlikely(search_pc)) {
79aceca5
FB		 8241 j = gen_opc_ptr - gen_opc_buf;
8242 if (lj < j) {
8243 lj++;
8244 while (lj < j)
8245 gen_opc_instr_start[lj++] = 0;
046d6672 8246 gen_opc_pc[lj] = ctx.nip;
79aceca5 8247 gen_opc_instr_start[lj] = 1;
2e70f6ef 8248 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 8249 }
8250 }
d12d51d5
AL		 8251 LOG_DISAS("----------------\n");
8252 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8253 ctx.nip, ctx.mem_idx, (int)msr_ir);
2e70f6ef
PB		 8254 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8255 gen_io_start();
76db3ba4 8256 if (unlikely(ctx.le_mode)) {
056401ea
JM		 8257 ctx.opcode = bswap32(ldl_code(ctx.nip));
8258 } else {
8259 ctx.opcode = ldl_code(ctx.nip);
111bfab3 8260 }
d12d51d5 8261 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 8262 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 8263 opc3(ctx.opcode), little_endian ? "little" : "big");
046d6672 8264 ctx.nip += 4;
3fc6c082 8265 table = env->opcodes;
2e70f6ef 8266 num_insns++;
79aceca5
FB		 8267 handler = table[opc1(ctx.opcode)];
8268 if (is_indirect_opcode(handler)) {
8269 table = ind_table(handler);
8270 handler = table[opc2(ctx.opcode)];
8271 if (is_indirect_opcode(handler)) {
8272 table = ind_table(handler);
8273 handler = table[opc3(ctx.opcode)];
8274 }
8275 }
8276 /* Is opcode *REALLY* valid ? */
76a66253 8277 if (unlikely(handler->handler == &gen_invalid)) {
93fcfe39
AL		 8278 if (qemu_log_enabled()) {
8279 qemu_log("invalid/unsupported opcode: "
8280 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8281 opc1(ctx.opcode), opc2(ctx.opcode),
8282 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 8283 } else {
8284 printf("invalid/unsupported opcode: "
6b542af7 8285 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 8286 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8287 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 8288 }
76a66253
JM		 8289 } else {
8290 if (unlikely((ctx.opcode & handler->inval) != 0)) {
93fcfe39
AL		 8291 if (qemu_log_enabled()) {
8292 qemu_log("invalid bits: %08x for opcode: "
8293 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8294 ctx.opcode & handler->inval, opc1(ctx.opcode),
8295 opc2(ctx.opcode), opc3(ctx.opcode),
8296 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 8297 } else {
8298 printf("invalid bits: %08x for opcode: "
6b542af7 8299 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 8300 ctx.opcode & handler->inval, opc1(ctx.opcode),
8301 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8302 ctx.opcode, ctx.nip - 4);
76a66253 8303 }
e06fcd75 8304 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 8305 break;
79aceca5 8306 }
79aceca5 8307 }
4b3686fa 8308 (*(handler->handler))(&ctx);
76a66253
JM		 8309#if defined(DO_PPC_STATISTICS)
8310 handler->count++;
8311#endif
9a64fbe4 8312 /* Check trace mode exceptions */
8cbcb4fa
AJ		 8313 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8314 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8315 ctx.exception != POWERPC_SYSCALL &&
8316 ctx.exception != POWERPC_EXCP_TRAP &&
8317 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 8318 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 8319 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 8320 (env->singlestep_enabled) ||
8321 num_insns >= max_insns)) {
d26bfc9a
JM		 8322 /* if we reach a page boundary or are single stepping, stop
8323 * generation
8324 */
8dd4983c 8325 break;
76a66253 8326 }
3fc6c082
FB		 8327#if defined (DO_SINGLE_STEP)
8328 break;
8329#endif
8330 }
2e70f6ef
PB		 8331 if (tb->cflags & CF_LAST_IO)
8332 gen_io_end();
e1833e1f 8333 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 8334 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 8335 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa 8336 if (unlikely(env->singlestep_enabled)) {
e06fcd75 8337 gen_debug_exception(ctxp);
8cbcb4fa 8338 }
76a66253 8339 /* Generate the return instruction */
57fec1fe 8340 tcg_gen_exit_tb(0);
9a64fbe4 8341 }
2e70f6ef 8342 gen_icount_end(tb, num_insns);
79aceca5 8343 *gen_opc_ptr = INDEX_op_end;
76a66253 8344 if (unlikely(search_pc)) {
9a64fbe4
FB		 8345 j = gen_opc_ptr - gen_opc_buf;
8346 lj++;
8347 while (lj <= j)
8348 gen_opc_instr_start[lj++] = 0;
9a64fbe4 8349 } else {
046d6672 8350 tb->size = ctx.nip - pc_start;
2e70f6ef 8351 tb->icount = num_insns;
9a64fbe4 8352 }
d9bce9d9 8353#if defined(DEBUG_DISAS)
93fcfe39
AL		 8354 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8355 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8fec2b8c 8356 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 8357 int flags;
237c0af0 8358 flags = env->bfd_mach;
76db3ba4 8359 flags |= ctx.le_mode << 16;
93fcfe39
AL		 8360 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8361 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8362 qemu_log("\n");
9fddaa0c 8363 }
79aceca5 8364#endif
79aceca5
FB		 8365}
8366
2cfc5f17 8367void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 8368{
2cfc5f17 8369 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 8370}
8371
2cfc5f17 8372void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 8373{
2cfc5f17 8374 gen_intermediate_code_internal(env, tb, 1);
79aceca5 8375}
d2856f1a
AJ		 8376
8377void gen_pc_load(CPUState *env, TranslationBlock *tb,
8378 unsigned long searched_pc, int pc_pos, void *puc)
8379{
d2856f1a 8380 env->nip = gen_opc_pc[pc_pos];
d2856f1a 8381}
Qemu copy for testing