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tcg-ops.h: add rotl/rotli and rotr/rotri TCG instructions
[qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
f10dc08e 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
79aceca5 32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
79aceca5 38//#define DO_SINGLE_STEP
9fddaa0c 39//#define PPC_DEBUG_DISAS
76a66253 40//#define DO_PPC_STATISTICS
7c58044c 41//#define OPTIMIZE_FPRF_UPDATE
79aceca5 42
a750fc0b
JM		 43/*****************************************************************************/
44/* Code translation helpers */
c53be334 45
f78fb44e
AJ		 46/* global register indexes */
47static TCGv cpu_env;
1d542695 48static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 49#if !defined(TARGET_PPC64)
1d542695 50 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 51#endif
a5e26afa 52 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
f78fb44e
AJ		 55static TCGv cpu_gpr[32];
56#if !defined(TARGET_PPC64)
57static TCGv cpu_gprh[32];
58#endif
a5e26afa 59static TCGv cpu_fpr[32];
1d542695 60static TCGv cpu_avrh[32], cpu_avrl[32];
47e4661c 61static TCGv cpu_crf[8];
bd568f18 62static TCGv cpu_nip;
cfdcd37a
AJ		 63static TCGv cpu_ctr;
64static TCGv cpu_lr;
3d7b417e 65static TCGv cpu_xer;
e1571908 66static TCGv cpu_fpscr;
f78fb44e
AJ		 67
68/* dyngen register indexes */
69static TCGv cpu_T[3];
70#if defined(TARGET_PPC64)
71#define cpu_T64 cpu_T
72#else
73static TCGv cpu_T64[3];
74#endif
a5e26afa 75static TCGv cpu_FT[3];
1d542695 76static TCGv cpu_AVRh[3], cpu_AVRl[3];
2e70f6ef
PB		 77
78#include "gen-icount.h"
79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
b2437bf2 84 static int done_init = 0;
f78fb44e 85
2e70f6ef
PB		 86 if (done_init)
87 return;
f78fb44e 88
2e70f6ef 89 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
1c73fe5b
AJ		 90#if TARGET_LONG_BITS > HOST_LONG_BITS
91 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
92 TCG_AREG0, offsetof(CPUState, t0), "T0");
93 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
94 TCG_AREG0, offsetof(CPUState, t1), "T1");
95 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
96 TCG_AREG0, offsetof(CPUState, t2), "T2");
97#else
98 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
99 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
100 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
101#endif
f78fb44e
AJ		 102#if !defined(TARGET_PPC64)
103 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 104 TCG_AREG0, offsetof(CPUState, t0_64),
f78fb44e
AJ		 105 "T0_64");
106 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 107 TCG_AREG0, offsetof(CPUState, t1_64),
f78fb44e
AJ		 108 "T1_64");
109 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 110 TCG_AREG0, offsetof(CPUState, t2_64),
f78fb44e
AJ		 111 "T2_64");
112#endif
a5e26afa
AJ		 113
114 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
115 offsetof(CPUState, ft0), "FT0");
116 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
117 offsetof(CPUState, ft1), "FT1");
118 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
119 offsetof(CPUState, ft2), "FT2");
120
1d542695
AJ		 121 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
122 offsetof(CPUState, avr0.u64[0]), "AVR0H");
123 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124 offsetof(CPUState, avr0.u64[1]), "AVR0L");
125 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126 offsetof(CPUState, avr1.u64[0]), "AVR1H");
127 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128 offsetof(CPUState, avr1.u64[1]), "AVR1L");
129 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
130 offsetof(CPUState, avr2.u64[0]), "AVR2H");
131 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
132 offsetof(CPUState, avr2.u64[1]), "AVR2L");
133
f78fb44e 134 p = cpu_reg_names;
47e4661c
AJ		 135
136 for (i = 0; i < 8; i++) {
137 sprintf(p, "crf%d", i);
138 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
139 offsetof(CPUState, crf[i]), p);
140 p += 5;
141 }
142
f78fb44e
AJ		 143 for (i = 0; i < 32; i++) {
144 sprintf(p, "r%d", i);
145 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
146 offsetof(CPUState, gpr[i]), p);
147 p += (i < 10) ? 3 : 4;
148#if !defined(TARGET_PPC64)
149 sprintf(p, "r%dH", i);
150 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
151 offsetof(CPUState, gprh[i]), p);
152 p += (i < 10) ? 4 : 5;
153#endif
1d542695 154
a5e26afa
AJ		 155 sprintf(p, "fp%d", i);
156 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
157 offsetof(CPUState, fpr[i]), p);
ec1ac72d 158 p += (i < 10) ? 4 : 5;
a5e26afa 159
1d542695
AJ		 160 sprintf(p, "avr%dH", i);
161 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
162 offsetof(CPUState, avr[i].u64[0]), p);
163 p += (i < 10) ? 6 : 7;
ec1ac72d 164
1d542695
AJ		 165 sprintf(p, "avr%dL", i);
166 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
167 offsetof(CPUState, avr[i].u64[1]), p);
168 p += (i < 10) ? 6 : 7;
f78fb44e 169 }
f10dc08e 170
bd568f18
AJ		 171 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
172 offsetof(CPUState, nip), "nip");
173
cfdcd37a
AJ		 174 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
175 offsetof(CPUState, ctr), "ctr");
176
177 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
178 offsetof(CPUState, lr), "lr");
179
3d7b417e
AJ		 180 cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
181 offsetof(CPUState, xer), "xer");
182
e1571908
AJ		 183 cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
184 offsetof(CPUState, fpscr), "fpscr");
185
f10dc08e
AJ		 186 /* register helpers */
187#undef DEF_HELPER
188#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
189#include "helper.h"
190
2e70f6ef
PB		 191 done_init = 1;
192}
193
7c58044c
JM		 194#if defined(OPTIMIZE_FPRF_UPDATE)
195static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
196static uint16_t **gen_fprf_ptr;
197#endif
79aceca5 198
79aceca5
FB		 199/* internal defines */
200typedef struct DisasContext {
201 struct TranslationBlock *tb;
0fa85d43 202 target_ulong nip;
79aceca5 203 uint32_t opcode;
9a64fbe4 204 uint32_t exception;
3cc62370
FB		 205 /* Routine used to access memory */
206 int mem_idx;
207 /* Translation flags */
9a64fbe4 208#if !defined(CONFIG_USER_ONLY)
79aceca5 209 int supervisor;
d9bce9d9
JM		 210#endif
211#if defined(TARGET_PPC64)
212 int sf_mode;
9a64fbe4 213#endif
3cc62370 214 int fpu_enabled;
a9d9eb8f 215 int altivec_enabled;
0487d6a8 216 int spe_enabled;
3fc6c082 217 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 218 int singlestep_enabled;
d63001d1 219 int dcache_line_size;
79aceca5
FB		 220} DisasContext;
221
3fc6c082 222struct opc_handler_t {
79aceca5
FB		 223 /* invalid bits */
224 uint32_t inval;
9a64fbe4 225 /* instruction type */
0487d6a8 226 uint64_t type;
79aceca5
FB		 227 /* handler */
228 void (*handler)(DisasContext *ctx);
a750fc0b 229#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 230 const char *oname;
a750fc0b
JM		 231#endif
232#if defined(DO_PPC_STATISTICS)
76a66253
JM		 233 uint64_t count;
234#endif
3fc6c082 235};
79aceca5 236
7c58044c
JM		 237static always_inline void gen_reset_fpstatus (void)
238{
239#ifdef CONFIG_SOFTFLOAT
240 gen_op_reset_fpstatus();
241#endif
242}
243
244static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
245{
246 if (set_fprf != 0) {
247 /* This case might be optimized later */
248#if defined(OPTIMIZE_FPRF_UPDATE)
249 *gen_fprf_ptr++ = gen_opc_ptr;
250#endif
251 gen_op_compute_fprf(1);
252 if (unlikely(set_rc))
47e4661c 253 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 254 gen_op_float_check_status();
255 } else if (unlikely(set_rc)) {
256 /* We always need to compute fpcc */
257 gen_op_compute_fprf(0);
47e4661c 258 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 259 if (set_fprf)
260 gen_op_float_check_status();
261 }
262}
263
264static always_inline void gen_optimize_fprf (void)
265{
266#if defined(OPTIMIZE_FPRF_UPDATE)
267 uint16_t **ptr;
268
269 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
270 *ptr = INDEX_op_nop1;
271 gen_fprf_ptr = gen_fprf_buf;
272#endif
273}
274
b068d6a7 275static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 276{
277#if defined(TARGET_PPC64)
278 if (ctx->sf_mode)
bd568f18 279 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 280 else
281#endif
bd568f18 282 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 283}
284
e1833e1f 285#define GEN_EXCP(ctx, excp, error) \
79aceca5 286do { \
e1833e1f 287 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 288 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 289 } \
290 gen_op_raise_exception_err((excp), (error)); \
291 ctx->exception = (excp); \
79aceca5
FB		 292} while (0)
293
e1833e1f
JM		 294#define GEN_EXCP_INVAL(ctx) \
295GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
296 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 297
e1833e1f
JM		 298#define GEN_EXCP_PRIVOPC(ctx) \
299GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
300 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 301
e1833e1f
JM		 302#define GEN_EXCP_PRIVREG(ctx) \
303GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
304 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
305
306#define GEN_EXCP_NO_FP(ctx) \
307GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
308
309#define GEN_EXCP_NO_AP(ctx) \
310GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 311
a9d9eb8f
JM		 312#define GEN_EXCP_NO_VR(ctx) \
313GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
314
f24e5695 315/* Stop translation */
b068d6a7 316static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 317{
d9bce9d9 318 gen_update_nip(ctx, ctx->nip);
e1833e1f 319 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 320}
321
f24e5695 322/* No need to update nip here, as execution flow will change */
b068d6a7 323static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 324{
e1833e1f 325 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 326}
327
79aceca5
FB		 328#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329static void gen_##name (DisasContext *ctx); \
330GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
331static void gen_##name (DisasContext *ctx)
332
c7697e1f
JM		 333#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
334static void gen_##name (DisasContext *ctx); \
335GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
336static void gen_##name (DisasContext *ctx)
337
79aceca5
FB		 338typedef struct opcode_t {
339 unsigned char opc1, opc2, opc3;
1235fc06 340#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 341 unsigned char pad[5];
342#else
343 unsigned char pad[1];
344#endif
79aceca5 345 opc_handler_t handler;
b55266b5 346 const char *oname;
79aceca5
FB		 347} opcode_t;
348
a750fc0b 349/*****************************************************************************/
79aceca5
FB		 350/*** Instruction decoding ***/
351#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 352static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 353{ \
354 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
355}
356
357#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 358static always_inline int32_t name (uint32_t opcode) \
79aceca5 359{ \
18fba28c 360 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 361}
362
363/* Opcode part 1 */
364EXTRACT_HELPER(opc1, 26, 6);
365/* Opcode part 2 */
366EXTRACT_HELPER(opc2, 1, 5);
367/* Opcode part 3 */
368EXTRACT_HELPER(opc3, 6, 5);
369/* Update Cr0 flags */
370EXTRACT_HELPER(Rc, 0, 1);
371/* Destination */
372EXTRACT_HELPER(rD, 21, 5);
373/* Source */
374EXTRACT_HELPER(rS, 21, 5);
375/* First operand */
376EXTRACT_HELPER(rA, 16, 5);
377/* Second operand */
378EXTRACT_HELPER(rB, 11, 5);
379/* Third operand */
380EXTRACT_HELPER(rC, 6, 5);
381/*** Get CRn ***/
382EXTRACT_HELPER(crfD, 23, 3);
383EXTRACT_HELPER(crfS, 18, 3);
384EXTRACT_HELPER(crbD, 21, 5);
385EXTRACT_HELPER(crbA, 16, 5);
386EXTRACT_HELPER(crbB, 11, 5);
387/* SPR / TBL */
3fc6c082 388EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 389static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 390{
391 uint32_t sprn = _SPR(opcode);
392
393 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
394}
79aceca5
FB		 395/*** Get constants ***/
396EXTRACT_HELPER(IMM, 12, 8);
397/* 16 bits signed immediate value */
398EXTRACT_SHELPER(SIMM, 0, 16);
399/* 16 bits unsigned immediate value */
400EXTRACT_HELPER(UIMM, 0, 16);
401/* Bit count */
402EXTRACT_HELPER(NB, 11, 5);
403/* Shift count */
404EXTRACT_HELPER(SH, 11, 5);
405/* Mask start */
406EXTRACT_HELPER(MB, 6, 5);
407/* Mask end */
408EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 409/* Trap operand */
410EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 411
412EXTRACT_HELPER(CRM, 12, 8);
413EXTRACT_HELPER(FM, 17, 8);
414EXTRACT_HELPER(SR, 16, 4);
e4bb997e 415EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 416
79aceca5
FB		 417/*** Jump target decoding ***/
418/* Displacement */
419EXTRACT_SHELPER(d, 0, 16);
420/* Immediate address */
b068d6a7 421static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 422{
423 return (opcode >> 0) & 0x03FFFFFC;
424}
425
b068d6a7 426static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 427{
428 return (opcode >> 0) & 0xFFFC;
429}
430
431EXTRACT_HELPER(BO, 21, 5);
432EXTRACT_HELPER(BI, 16, 5);
433/* Absolute/relative address */
434EXTRACT_HELPER(AA, 1, 1);
435/* Link */
436EXTRACT_HELPER(LK, 0, 1);
437
438/* Create a mask between <start> and <end> bits */
b068d6a7 439static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 440{
76a66253 441 target_ulong ret;
79aceca5 442
76a66253
JM		 443#if defined(TARGET_PPC64)
444 if (likely(start == 0)) {
6f2d8978 445 ret = UINT64_MAX << (63 - end);
76a66253 446 } else if (likely(end == 63)) {
6f2d8978 447 ret = UINT64_MAX >> start;
76a66253
JM		 448 }
449#else
450 if (likely(start == 0)) {
6f2d8978 451 ret = UINT32_MAX << (31 - end);
76a66253 452 } else if (likely(end == 31)) {
6f2d8978 453 ret = UINT32_MAX >> start;
76a66253
JM		 454 }
455#endif
456 else {
457 ret = (((target_ulong)(-1ULL)) >> (start)) ^
458 (((target_ulong)(-1ULL) >> (end)) >> 1);
459 if (unlikely(start > end))
460 return ~ret;
461 }
79aceca5
FB		 462
463 return ret;
464}
465
a750fc0b
JM		 466/*****************************************************************************/
467/* PowerPC Instructions types definitions */
468enum {
1b413d55 469 PPC_NONE = 0x0000000000000000ULL,
12de9a39 470 /* PowerPC base instructions set */
1b413d55
JM		 471 PPC_INSNS_BASE = 0x0000000000000001ULL,
472 /* integer operations instructions */
a750fc0b 473#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 474 /* flow control instructions */
a750fc0b 475#define PPC_FLOW PPC_INSNS_BASE
1b413d55 476 /* virtual memory instructions */
a750fc0b 477#define PPC_MEM PPC_INSNS_BASE
1b413d55 478 /* ld/st with reservation instructions */
a750fc0b 479#define PPC_RES PPC_INSNS_BASE
1b413d55 480 /* spr/msr access instructions */
a750fc0b 481#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 482 /* Deprecated instruction sets */
483 /* Original POWER instruction set */
f610349f 484 PPC_POWER = 0x0000000000000002ULL,
1b413d55 485 /* POWER2 instruction set extension */
f610349f 486 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 487 /* Power RTC support */
f610349f 488 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 489 /* Power-to-PowerPC bridge (601) */
f610349f 490 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 491 /* 64 bits PowerPC instruction set */
f610349f 492 PPC_64B = 0x0000000000000020ULL,
1b413d55 493 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 494 PPC_64BX = 0x0000000000000040ULL,
1b413d55 495 /* 64 bits hypervisor extensions */
f610349f 496 PPC_64H = 0x0000000000000080ULL,
1b413d55 497 /* New wait instruction (PowerPC 2.0x) */
f610349f 498 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 499 /* Time base mftb instruction */
f610349f 500 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 501
502 /* Fixed-point unit extensions */
503 /* PowerPC 602 specific */
f610349f 504 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 505 /* isel instruction */
506 PPC_ISEL = 0x0000000000000800ULL,
507 /* popcntb instruction */
508 PPC_POPCNTB = 0x0000000000001000ULL,
509 /* string load / store */
510 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 511
512 /* Floating-point unit extensions */
513 /* Optional floating point instructions */
514 PPC_FLOAT = 0x0000000000010000ULL,
515 /* New floating-point extensions (PowerPC 2.0x) */
516 PPC_FLOAT_EXT = 0x0000000000020000ULL,
517 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
518 PPC_FLOAT_FRES = 0x0000000000080000ULL,
519 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
520 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
521 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
522 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
523
524 /* Vector/SIMD extensions */
525 /* Altivec support */
526 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 527 /* PowerPC 2.03 SPE extension */
05332d70 528 PPC_SPE = 0x0000000002000000ULL,
1b413d55 529 /* PowerPC 2.03 SPE floating-point extension */
05332d70 530 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 531
12de9a39 532 /* Optional memory control instructions */
1b413d55
JM		 533 PPC_MEM_TLBIA = 0x0000000010000000ULL,
534 PPC_MEM_TLBIE = 0x0000000020000000ULL,
535 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
536 /* sync instruction */
537 PPC_MEM_SYNC = 0x0000000080000000ULL,
538 /* eieio instruction */
539 PPC_MEM_EIEIO = 0x0000000100000000ULL,
540
541 /* Cache control instructions */
c8623f2e 542 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 543 /* icbi instruction */
05332d70 544 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 545 /* dcbz instruction with fixed cache line size */
05332d70 546 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 547 /* dcbz instruction with tunable cache line size */
05332d70 548 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 549 /* dcba instruction */
05332d70
JM		 550 PPC_CACHE_DCBA = 0x0000002000000000ULL,
551 /* Freescale cache locking instructions */
552 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 553
554 /* MMU related extensions */
555 /* external control instructions */
05332d70 556 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 557 /* segment register access instructions */
05332d70 558 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 559 /* PowerPC 6xx TLB management instructions */
05332d70 560 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 561 /* PowerPC 74xx TLB management instructions */
05332d70 562 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 563 /* PowerPC 40x TLB management instructions */
05332d70 564 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 565 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 566 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 567 /* SLB management */
05332d70 568 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 569
12de9a39 570 /* Embedded PowerPC dedicated instructions */
05332d70 571 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 572 /* PowerPC 40x exception model */
05332d70 573 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 574 /* PowerPC 405 Mac instructions */
05332d70 575 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 576 /* PowerPC 440 specific instructions */
05332d70 577 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 578 /* BookE (embedded) PowerPC specification */
05332d70
JM		 579 PPC_BOOKE = 0x0010000000000000ULL,
580 /* mfapidi instruction */
581 PPC_MFAPIDI = 0x0020000000000000ULL,
582 /* tlbiva instruction */
583 PPC_TLBIVA = 0x0040000000000000ULL,
584 /* tlbivax instruction */
585 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 586 /* PowerPC 4xx dedicated instructions */
05332d70 587 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 588 /* PowerPC 40x ibct instructions */
05332d70 589 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 590 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 591 PPC_RFMCI = 0x0400000000000000ULL,
592 /* rfdi instruction */
593 PPC_RFDI = 0x0800000000000000ULL,
594 /* DCR accesses */
595 PPC_DCR = 0x1000000000000000ULL,
596 /* DCR extended accesse */
597 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 598 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 599 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 600};
601
602/*****************************************************************************/
603/* PowerPC instructions table */
3fc6c082
FB		 604#if HOST_LONG_BITS == 64
605#define OPC_ALIGN 8
606#else
607#define OPC_ALIGN 4
608#endif
1b039c09 609#if defined(__APPLE__)
d9bce9d9 610#define OPCODES_SECTION \
3fc6c082 611 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 612#else
d9bce9d9 613#define OPCODES_SECTION \
3fc6c082 614 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 615#endif
616
76a66253 617#if defined(DO_PPC_STATISTICS)
79aceca5 618#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 619OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
18fba28c 623 .pad = { 0, }, \
79aceca5
FB		 624 .handler = { \
625 .inval = invl, \
9a64fbe4 626 .type = _typ, \
79aceca5 627 .handler = &gen_##name, \
76a66253 628 .oname = stringify(name), \
79aceca5 629 }, \
3fc6c082 630 .oname = stringify(name), \
79aceca5 631}
c7697e1f
JM		 632#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
633OPCODES_SECTION opcode_t opc_##name = { \
634 .opc1 = op1, \
635 .opc2 = op2, \
636 .opc3 = op3, \
637 .pad = { 0, }, \
638 .handler = { \
639 .inval = invl, \
640 .type = _typ, \
641 .handler = &gen_##name, \
642 .oname = onam, \
643 }, \
644 .oname = onam, \
645}
76a66253
JM		 646#else
647#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
648OPCODES_SECTION opcode_t opc_##name = { \
649 .opc1 = op1, \
650 .opc2 = op2, \
651 .opc3 = op3, \
652 .pad = { 0, }, \
653 .handler = { \
654 .inval = invl, \
655 .type = _typ, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = stringify(name), \
659}
c7697e1f
JM		 660#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
661OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = op1, \
663 .opc2 = op2, \
664 .opc3 = op3, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = invl, \
668 .type = _typ, \
669 .handler = &gen_##name, \
670 }, \
671 .oname = onam, \
672}
76a66253 673#endif
79aceca5
FB		 674
675#define GEN_OPCODE_MARK(name) \
18fba28c 676OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 677 .opc1 = 0xFF, \
678 .opc2 = 0xFF, \
679 .opc3 = 0xFF, \
18fba28c 680 .pad = { 0, }, \
79aceca5
FB		 681 .handler = { \
682 .inval = 0x00000000, \
9a64fbe4 683 .type = 0x00, \
79aceca5
FB		 684 .handler = NULL, \
685 }, \
3fc6c082 686 .oname = stringify(name), \
79aceca5
FB		 687}
688
689/* Start opcode list */
690GEN_OPCODE_MARK(start);
691
692/* Invalid instruction */
9a64fbe4
FB		 693GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
694{
e1833e1f 695 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 696}
697
79aceca5
FB		 698static opc_handler_t invalid_handler = {
699 .inval = 0xFFFFFFFF,
9a64fbe4 700 .type = PPC_NONE,
79aceca5
FB		 701 .handler = gen_invalid,
702};
703
e1571908
AJ		 704/*** Integer comparison ***/
705
ea363694 706static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 707{
708 int l1, l2, l3;
709
269f3e95
AJ		 710 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
711 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 712 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
713
714 l1 = gen_new_label();
715 l2 = gen_new_label();
716 l3 = gen_new_label();
717 if (s) {
ea363694
AJ		 718 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
719 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 720 } else {
ea363694
AJ		 721 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 723 }
724 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
725 tcg_gen_br(l3);
726 gen_set_label(l1);
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
728 tcg_gen_br(l3);
729 gen_set_label(l2);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
731 gen_set_label(l3);
732}
733
ea363694 734static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 735{
ea363694
AJ		 736 TCGv t0 = tcg_const_local_tl(arg1);
737 gen_op_cmp(arg0, t0, s, crf);
738 tcg_temp_free(t0);
e1571908
AJ		 739}
740
741#if defined(TARGET_PPC64)
ea363694 742static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 743{
ea363694
AJ		 744 TCGv t0, t1;
745 t0 = tcg_temp_local_new(TCG_TYPE_TL);
746 t1 = tcg_temp_local_new(TCG_TYPE_TL);
e1571908 747 if (s) {
ea363694
AJ		 748 tcg_gen_ext32s_tl(t0, arg0);
749 tcg_gen_ext32s_tl(t1, arg1);
e1571908 750 } else {
ea363694
AJ		 751 tcg_gen_ext32u_tl(t0, arg0);
752 tcg_gen_ext32u_tl(t1, arg1);
e1571908 753 }
ea363694
AJ		 754 gen_op_cmp(t0, t1, s, crf);
755 tcg_temp_free(t1);
756 tcg_temp_free(t0);
e1571908
AJ		 757}
758
ea363694 759static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 760{
ea363694
AJ		 761 TCGv t0 = tcg_const_local_tl(arg1);
762 gen_op_cmp32(arg0, t0, s, crf);
763 tcg_temp_free(t0);
e1571908
AJ		 764}
765#endif
766
767static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
768{
769#if defined(TARGET_PPC64)
770 if (!(ctx->sf_mode))
771 gen_op_cmpi32(reg, 0, 1, 0);
772 else
773#endif
774 gen_op_cmpi(reg, 0, 1, 0);
775}
776
777/* cmp */
778GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
779{
780#if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
782 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
783 1, crfD(ctx->opcode));
784 else
785#endif
786 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
787 1, crfD(ctx->opcode));
788}
789
790/* cmpi */
791GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
792{
793#if defined(TARGET_PPC64)
794 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
795 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
796 1, crfD(ctx->opcode));
797 else
798#endif
799 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
800 1, crfD(ctx->opcode));
801}
802
803/* cmpl */
804GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
805{
806#if defined(TARGET_PPC64)
807 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
808 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
809 0, crfD(ctx->opcode));
810 else
811#endif
812 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
813 0, crfD(ctx->opcode));
814}
815
816/* cmpli */
817GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
818{
819#if defined(TARGET_PPC64)
820 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
821 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
822 0, crfD(ctx->opcode));
823 else
824#endif
825 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
826 0, crfD(ctx->opcode));
827}
828
829/* isel (PowerPC 2.03 specification) */
830GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
831{
832 int l1, l2;
833 uint32_t bi = rC(ctx->opcode);
834 uint32_t mask;
fea0c503 835 TCGv t0;
e1571908
AJ		 836
837 l1 = gen_new_label();
838 l2 = gen_new_label();
839
840 mask = 1 << (3 - (bi & 0x03));
fea0c503
AJ		 841 t0 = tcg_temp_new(TCG_TYPE_I32);
842 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
843 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 844 if (rA(ctx->opcode) == 0)
845 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
846 else
847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
848 tcg_gen_br(l2);
849 gen_set_label(l1);
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
851 gen_set_label(l2);
852}
853
79aceca5 854/*** Integer arithmetic ***/
79aceca5 855
74637406
AJ		 856static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
857{
858 int l1;
859 TCGv t0;
79aceca5 860
74637406
AJ		 861 l1 = gen_new_label();
862 /* Start with XER OV disabled, the most likely case */
863 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
864 t0 = tcg_temp_local_new(TCG_TYPE_TL);
865 tcg_gen_xor_tl(t0, arg0, arg1);
866#if defined(TARGET_PPC64)
867 if (!ctx->sf_mode)
868 tcg_gen_ext32s_tl(t0, t0);
869#endif
870 if (sub)
871 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
872 else
873 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
874 tcg_gen_xor_tl(t0, arg1, arg2);
875#if defined(TARGET_PPC64)
876 if (!ctx->sf_mode)
877 tcg_gen_ext32s_tl(t0, t0);
878#endif
879 if (sub)
880 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
881 else
882 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
883 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
884 gen_set_label(l1);
885 tcg_temp_free(t0);
79aceca5
FB		 886}
887
74637406
AJ		 888static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
889{
890 int l1 = gen_new_label();
d9bce9d9
JM		 891
892#if defined(TARGET_PPC64)
74637406
AJ		 893 if (!(ctx->sf_mode)) {
894 TCGv t0, t1;
895 t0 = tcg_temp_new(TCG_TYPE_TL);
896 t1 = tcg_temp_new(TCG_TYPE_TL);
d9bce9d9 897
74637406
AJ		 898 tcg_gen_ext32u_tl(t0, arg1);
899 tcg_gen_ext32u_tl(t1, arg2);
900 if (sub) {
901 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
902 } else {
903 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
904 }
905 } else
906#endif
907 if (sub) {
908 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
909 } else {
910 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
911 }
912 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
913 gen_set_label(l1);
d9bce9d9
JM		 914}
915
74637406
AJ		 916/* Common add function */
917static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
918 int add_ca, int compute_ca, int compute_ov)
919{
920 TCGv t0, t1;
d9bce9d9 921
74637406
AJ		 922 if ((!compute_ca && !compute_ov) ||
923 (GET_TCGV(ret) != GET_TCGV(arg1) && GET_TCGV(ret) != GET_TCGV(arg2))) {
924 t0 = ret;
925 } else {
926 t0 = tcg_temp_local_new(TCG_TYPE_TL);
927 }
79aceca5 928
74637406
AJ		 929 if (add_ca) {
930 t1 = tcg_temp_local_new(TCG_TYPE_TL);
931 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
932 tcg_gen_shri_tl(t1, t1, XER_CA);
933 }
79aceca5 934
74637406
AJ		 935 if (compute_ca && compute_ov) {
936 /* Start with XER CA and OV disabled, the most likely case */
937 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
938 } else if (compute_ca) {
939 /* Start with XER CA disabled, the most likely case */
940 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
941 } else if (compute_ov) {
942 /* Start with XER OV disabled, the most likely case */
943 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
944 }
79aceca5 945
74637406
AJ		 946 tcg_gen_add_tl(t0, arg1, arg2);
947
948 if (compute_ca) {
949 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
950 }
951 if (add_ca) {
952 tcg_gen_add_tl(t0, t0, t1);
953 gen_op_arith_compute_ca(ctx, t0, t1, 0);
954 tcg_temp_free(t1);
955 }
956 if (compute_ov) {
957 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
958 }
959
960 if (unlikely(Rc(ctx->opcode) != 0))
961 gen_set_Rc0(ctx, t0);
962
963 if (GET_TCGV(t0) != GET_TCGV(ret)) {
964 tcg_gen_mov_tl(ret, t0);
965 tcg_temp_free(t0);
966 }
39dd32ee 967}
74637406
AJ		 968/* Add functions with two operands */
969#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
970GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
971{ \
972 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
973 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
974 add_ca, compute_ca, compute_ov); \
975}
976/* Add functions with one operand and one immediate */
977#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
978 add_ca, compute_ca, compute_ov) \
979GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
980{ \
981 TCGv t0 = tcg_const_local_tl(const_val); \
982 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], t0, \
984 add_ca, compute_ca, compute_ov); \
985 tcg_temp_free(t0); \
986}
987
988/* add add. addo addo. */
989GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
990GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
991/* addc addc. addco addco. */
992GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
993GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
994/* adde adde. addeo addeo. */
995GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
996GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
997/* addme addme. addmeo addmeo. */
998GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
999GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1000/* addze addze. addzeo addzeo.*/
1001GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1002GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1003/* addi */
1004GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1005{
74637406
AJ		 1006 target_long simm = SIMM(ctx->opcode);
1007
1008 if (rA(ctx->opcode) == 0) {
1009 /* li case */
1010 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1011 } else {
1012 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1013 }
d9bce9d9 1014}
74637406
AJ		 1015/* addic addic.*/
1016static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1017 int compute_Rc0)
d9bce9d9 1018{
74637406
AJ		 1019 target_long simm = SIMM(ctx->opcode);
1020
1021 /* Start with XER CA and OV disabled, the most likely case */
1022 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1023
1024 if (likely(simm != 0)) {
1025 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1026 tcg_gen_addi_tl(t0, arg1, simm);
1027 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1028 tcg_gen_mov_tl(ret, t0);
1029 tcg_temp_free(t0);
1030 } else {
1031 tcg_gen_mov_tl(ret, arg1);
1032 }
1033 if (compute_Rc0) {
1034 gen_set_Rc0(ctx, ret);
1035 }
d9bce9d9 1036}
74637406 1037GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1038{
74637406 1039 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1040}
74637406 1041GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1042{
74637406 1043 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1044}
74637406
AJ		 1045/* addis */
1046GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1047{
74637406
AJ		 1048 target_long simm = SIMM(ctx->opcode);
1049
1050 if (rA(ctx->opcode) == 0) {
1051 /* lis case */
1052 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1053 } else {
1054 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1055 }
d9bce9d9 1056}
74637406
AJ		 1057
1058static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1059 int sign, int compute_ov)
d9bce9d9 1060{
74637406
AJ		 1061 int l1, l2, l3;
1062 TCGv t0, t1, t2;
1063
1064#if defined(TARGET_PPC64)
1065 t0 = tcg_temp_local_new(TCG_TYPE_I32);
1066 t1 = t0;
1067 t2 = tcg_temp_local_new(TCG_TYPE_I32);
1068 tcg_gen_trunc_i64_i32(t1, arg1);
1069 tcg_gen_trunc_i64_i32(t2, arg2);
1070#else
1071 t0 = ret;
1072 t1 = arg1;
1073 t2 = arg2;
d9bce9d9 1074#endif
74637406
AJ		 1075 l1 = gen_new_label();
1076 l2 = gen_new_label();
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l1);
1078 if (sign) {
1079 l3 = gen_new_label();
1080 tcg_gen_brcondi_i32(TCG_COND_NE, t2, -1, l3);
1081 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, INT32_MIN, l1);
1082 gen_set_label(l3);
1083 }
1084 if (sign) {
1085 tcg_gen_div_i32(t0, t1, t2);
1086 } else {
1087 tcg_gen_divu_i32(t0, t1, t2);
1088 }
1089 if (compute_ov) {
1090 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1091 }
1092 tcg_gen_br(l2);
1093 gen_set_label(l1);
1094 if (sign) {
1095 tcg_gen_sari_i32(t0, t1, 31);
1096 } else {
1097 tcg_gen_movi_i32(t0, 0);
1098 }
1099 if (compute_ov) {
1100 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1101 }
1102 gen_set_label(l2);
d9bce9d9 1103#if defined(TARGET_PPC64)
74637406
AJ		 1104 tcg_gen_extu_i32_i64(ret, t0);
1105 tcg_temp_free(t0);
d9bce9d9 1106#endif
74637406
AJ		 1107 if (unlikely(Rc(ctx->opcode) != 0))
1108 gen_set_Rc0(ctx, ret);
d9bce9d9 1109}
74637406
AJ		 1110/* Div functions */
1111#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1112GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1113{ \
1114 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1115 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1116 sign, compute_ov); \
1117}
1118/* divwu divwu. divwuo divwuo. */
1119GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1120GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1121/* divw divw. divwo divwo. */
1122GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1123GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1124#if defined(TARGET_PPC64)
74637406
AJ		 1125static always_inline void gen_op_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1126 int sign, int compute_ov)
d9bce9d9 1127{
74637406
AJ		 1128 int l1, l2, l3;
1129
1130 l1 = gen_new_label();
1131 l2 = gen_new_label();
1132
1133 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1134 if (sign) {
1135 l3 = gen_new_label();
1136 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1137 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1138 gen_set_label(l3);
1139 }
1140 if (sign) {
1141 tcg_gen_div_i64(ret, arg1, arg2);
1142 } else {
1143 tcg_gen_divu_i64(ret, arg1, arg2);
1144 }
1145 if (compute_ov) {
1146 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1147 }
1148 tcg_gen_br(l2);
1149 gen_set_label(l1);
1150 if (sign) {
1151 tcg_gen_sari_i64(ret, arg1, 63);
1152 } else {
1153 tcg_gen_movi_i64(ret, 0);
1154 }
1155 if (compute_ov) {
1156 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1157 }
1158 gen_set_label(l2);
1159 if (unlikely(Rc(ctx->opcode) != 0))
1160 gen_set_Rc0(ctx, ret);
d9bce9d9 1161}
74637406
AJ		 1162#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1163GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1164{ \
1165 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1166 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1167 sign, compute_ov); \
1168}
1169/* divwu divwu. divwuo divwuo. */
1170GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1171GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1172/* divw divw. divwo divwo. */
1173GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1174GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1175#endif
74637406
AJ		 1176
1177/* mulhw mulhw. */
1178GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1179{
74637406
AJ		 1180 TCGv t0, t1;
1181
1182 t0 = tcg_temp_new(TCG_TYPE_I64);
1183 t1 = tcg_temp_new(TCG_TYPE_I64);
1184#if defined(TARGET_PPC64)
1185 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1186 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1187 tcg_gen_mul_i64(t0, t0, t1);
1188 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1189#else
1190 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1191 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1192 tcg_gen_mul_i64(t0, t0, t1);
1193 tcg_gen_shri_i64(t0, t0, 32);
1194 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1195#endif
1196 tcg_temp_free(t0);
1197 tcg_temp_free(t1);
1198 if (unlikely(Rc(ctx->opcode) != 0))
1199 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1200}
74637406
AJ		 1201/* mulhwu mulhwu. */
1202GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1203{
74637406
AJ		 1204 TCGv t0, t1;
1205
1206 t0 = tcg_temp_new(TCG_TYPE_I64);
1207 t1 = tcg_temp_new(TCG_TYPE_I64);
d9bce9d9 1208#if defined(TARGET_PPC64)
74637406
AJ		 1209 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1210 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1211 tcg_gen_mul_i64(t0, t0, t1);
1212 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1213#else
1214 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1215 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1216 tcg_gen_mul_i64(t0, t0, t1);
1217 tcg_gen_shri_i64(t0, t0, 32);
1218 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1219#endif
1220 tcg_temp_free(t0);
1221 tcg_temp_free(t1);
1222 if (unlikely(Rc(ctx->opcode) != 0))
1223 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1224}
74637406
AJ		 1225/* mullw mullw. */
1226GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1227{
74637406
AJ		 1228#if defined(TARGET_PPC64)
1229 TCGv t0, t1;
1230 t0 = tcg_temp_new(TCG_TYPE_TL);
1231 t1 = tcg_temp_new(TCG_TYPE_TL);
1232 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1233 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1234 tcg_gen_mul_tl(t0, t0, t1);
1235 tcg_temp_free(t0);
1236 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], t0);
1237 tcg_temp_free(t1);
1238#else
1239 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1240 cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1241#endif
74637406
AJ		 1242 if (unlikely(Rc(ctx->opcode) != 0))
1243 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1244}
74637406
AJ		 1245/* mullwo mullwo. */
1246GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1247{
74637406
AJ		 1248 int l1;
1249 TCGv t0, t1;
1250
1251 t0 = tcg_temp_local_new(TCG_TYPE_I64);
1252 t1 = tcg_temp_local_new(TCG_TYPE_I64);
1253 l1 = gen_new_label();
1254 /* Start with XER OV disabled, the most likely case */
1255 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1256#if defined(TARGET_PPC64)
1257 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1258 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1259#else
1260 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1261 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1262#endif
74637406
AJ		 1263 tcg_gen_mul_i64(t0, t0, t1);
1264#if defined(TARGET_PPC64)
1265 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1266 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1267#else
1268 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1269 tcg_gen_ext32s_i64(t1, t0);
1270 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1271#endif
1272 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1273 gen_set_label(l1);
1274 if (unlikely(Rc(ctx->opcode) != 0))
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1276}
74637406
AJ		 1277/* mulli */
1278GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1279{
74637406
AJ		 1280 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1281 SIMM(ctx->opcode));
d9bce9d9
JM		 1282}
1283#if defined(TARGET_PPC64)
74637406
AJ		 1284#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1285GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1286{ \
1287 tcg_gen_helper_1_2(helper_##name, cpu_gpr[rD(ctx->opcode)], \
1288 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1289 if (unlikely(Rc(ctx->opcode) != 0)) \
1290 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1291}
74637406
AJ		 1292/* mulhd mulhd. */
1293GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1294/* mulhdu mulhdu. */
1295GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1296/* mulld mulld. */
1297GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1298{
74637406
AJ		 1299 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1300 cpu_gpr[rB(ctx->opcode)]);
1301 if (unlikely(Rc(ctx->opcode) != 0))
1302 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1303}
74637406
AJ		 1304/* mulldo mulldo. */
1305GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1306#endif
74637406
AJ		 1307
1308/* neg neg. nego nego. */
1309static always_inline void gen_op_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1310{
74637406
AJ		 1311 int l1, l2;
1312
1313 l1 = gen_new_label();
1314 l2 = gen_new_label();
d9bce9d9 1315#if defined(TARGET_PPC64)
74637406
AJ		 1316 if (ctx->sf_mode) {
1317 tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT64_MIN, l1);
1318 } else {
1319 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1320 tcg_gen_ext32s_tl(t0, arg1);
1321 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1322 }
1323#else
1324 tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT32_MIN, l1);
1325#endif
1326 tcg_gen_neg_tl(ret, arg1);
1327 if (ov_check) {
1328 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1329 }
1330 tcg_gen_br(l2);
1331 gen_set_label(l1);
1332 tcg_gen_mov_tl(ret, arg1);
1333 if (ov_check) {
1334 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1335 }
1336 gen_set_label(l2);
1337 if (unlikely(Rc(ctx->opcode) != 0))
1338 gen_set_Rc0(ctx, ret);
1339}
1340GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1341{
74637406 1342 gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1343}
74637406 1344GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1345{
74637406 1346 gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1347}
74637406
AJ		 1348
1349/* Common subf function */
1350static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1351 int add_ca, int compute_ca, int compute_ov)
79aceca5 1352{
74637406 1353 TCGv t0, t1;
76a66253 1354
74637406
AJ		 1355 if ((!compute_ca && !compute_ov) ||
1356 (GET_TCGV(ret) != GET_TCGV(arg1) && GET_TCGV(ret) != GET_TCGV(arg2))) {
1357 t0 = ret;
e864cabd 1358 } else {
74637406 1359 t0 = tcg_temp_local_new(TCG_TYPE_TL);
d9bce9d9 1360 }
76a66253 1361
74637406
AJ		 1362 if (add_ca) {
1363 t1 = tcg_temp_local_new(TCG_TYPE_TL);
1364 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1365 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1366 }
79aceca5 1367
74637406
AJ		 1368 if (compute_ca && compute_ov) {
1369 /* Start with XER CA and OV disabled, the most likely case */
1370 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1371 } else if (compute_ca) {
1372 /* Start with XER CA disabled, the most likely case */
1373 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1374 } else if (compute_ov) {
1375 /* Start with XER OV disabled, the most likely case */
1376 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1377 }
1378
1379 if (add_ca) {
1380 tcg_gen_not_tl(t0, arg1);
1381 tcg_gen_add_tl(t0, t0, arg2);
1382 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1383 tcg_gen_add_tl(t0, t0, t1);
1384 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1385 tcg_temp_free(t1);
79aceca5 1386 } else {
74637406
AJ		 1387 tcg_gen_sub_tl(t0, arg2, arg1);
1388 if (compute_ca) {
1389 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1390 }
1391 }
1392 if (compute_ov) {
1393 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1394 }
1395
1396 if (unlikely(Rc(ctx->opcode) != 0))
1397 gen_set_Rc0(ctx, t0);
1398
1399 if (GET_TCGV(t0) != GET_TCGV(ret)) {
1400 tcg_gen_mov_tl(ret, t0);
1401 tcg_temp_free(t0);
79aceca5 1402 }
79aceca5 1403}
74637406
AJ		 1404/* Sub functions with Two operands functions */
1405#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1406GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1407{ \
1408 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1409 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1410 add_ca, compute_ca, compute_ov); \
1411}
1412/* Sub functions with one operand and one immediate */
1413#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1414 add_ca, compute_ca, compute_ov) \
1415GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1416{ \
1417 TCGv t0 = tcg_const_local_tl(const_val); \
1418 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1419 cpu_gpr[rA(ctx->opcode)], t0, \
1420 add_ca, compute_ca, compute_ov); \
1421 tcg_temp_free(t0); \
1422}
1423/* subf subf. subfo subfo. */
1424GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1425GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1426/* subfc subfc. subfco subfco. */
1427GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1428GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1429/* subfe subfe. subfeo subfo. */
1430GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1431GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1432/* subfme subfme. subfmeo subfmeo. */
1433GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1434GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1435/* subfze subfze. subfzeo subfzeo.*/
1436GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1437GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1438/* subfic */
1439GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1440{
74637406
AJ		 1441 /* Start with XER CA and OV disabled, the most likely case */
1442 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1443 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1444 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1445 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1446 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1447 tcg_temp_free(t1);
1448 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1449 tcg_temp_free(t0);
79aceca5
FB		 1450}
1451
79aceca5 1452/*** Integer logical ***/
26d67362
AJ		 1453#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1454GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1455{ \
26d67362
AJ		 1456 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1457 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1458 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1459 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1460}
79aceca5 1461
26d67362 1462#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1463GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1464{ \
26d67362 1465 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1466 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1467 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1468}
1469
1470/* and & and. */
26d67362 1471GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1472/* andc & andc. */
26d67362 1473GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1474/* andi. */
c7697e1f 1475GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1476{
26d67362
AJ		 1477 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1478 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1479}
1480/* andis. */
c7697e1f 1481GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1482{
26d67362
AJ		 1483 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1485}
79aceca5 1486/* cntlzw */
26d67362
AJ		 1487GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1488{
1489 tcg_gen_helper_1_1(helper_cntlzw, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1490 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1491 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1492}
79aceca5 1493/* eqv & eqv. */
26d67362 1494GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1495/* extsb & extsb. */
26d67362 1496GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1497/* extsh & extsh. */
26d67362 1498GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1499/* nand & nand. */
26d67362 1500GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1501/* nor & nor. */
26d67362 1502GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1503/* or & or. */
9a64fbe4
FB		 1504GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1505{
76a66253
JM		 1506 int rs, ra, rb;
1507
1508 rs = rS(ctx->opcode);
1509 ra = rA(ctx->opcode);
1510 rb = rB(ctx->opcode);
1511 /* Optimisation for mr. ri case */
1512 if (rs != ra || rs != rb) {
26d67362
AJ		 1513 if (rs != rb)
1514 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1515 else
1516 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1517 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1518 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1519 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1520 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1521#if defined(TARGET_PPC64)
1522 } else {
26d67362
AJ		 1523 int prio = 0;
1524
c80f84e3
JM		 1525 switch (rs) {
1526 case 1:
1527 /* Set process priority to low */
26d67362 1528 prio = 2;
c80f84e3
JM		 1529 break;
1530 case 6:
1531 /* Set process priority to medium-low */
26d67362 1532 prio = 3;
c80f84e3
JM		 1533 break;
1534 case 2:
1535 /* Set process priority to normal */
26d67362 1536 prio = 4;
c80f84e3 1537 break;
be147d08
JM		 1538#if !defined(CONFIG_USER_ONLY)
1539 case 31:
1540 if (ctx->supervisor > 0) {
1541 /* Set process priority to very low */
26d67362 1542 prio = 1;
be147d08
JM		 1543 }
1544 break;
1545 case 5:
1546 if (ctx->supervisor > 0) {
1547 /* Set process priority to medium-hight */
26d67362 1548 prio = 5;
be147d08
JM		 1549 }
1550 break;
1551 case 3:
1552 if (ctx->supervisor > 0) {
1553 /* Set process priority to high */
26d67362 1554 prio = 6;
be147d08
JM		 1555 }
1556 break;
be147d08
JM		 1557 case 7:
1558 if (ctx->supervisor > 1) {
1559 /* Set process priority to very high */
26d67362 1560 prio = 7;
be147d08
JM		 1561 }
1562 break;
be147d08 1563#endif
c80f84e3
JM		 1564 default:
1565 /* nop */
1566 break;
1567 }
26d67362 1568 if (prio) {
ea363694
AJ		 1569 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1570 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1571 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1572 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1573 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1574 tcg_temp_free(t0);
26d67362 1575 }
c80f84e3 1576#endif
9a64fbe4 1577 }
9a64fbe4 1578}
79aceca5 1579/* orc & orc. */
26d67362 1580GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1581/* xor & xor. */
9a64fbe4
FB		 1582GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1583{
9a64fbe4 1584 /* Optimisation for "set to zero" case */
26d67362 1585 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1586 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1587 else
1588 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1589 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1590 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1591}
79aceca5
FB		 1592/* ori */
1593GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1594{
76a66253 1595 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1596
9a64fbe4
FB		 1597 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1598 /* NOP */
76a66253 1599 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1600 return;
76a66253 1601 }
26d67362 1602 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1603}
1604/* oris */
1605GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1606{
76a66253 1607 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1608
9a64fbe4
FB		 1609 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1610 /* NOP */
1611 return;
76a66253 1612 }
26d67362 1613 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1614}
1615/* xori */
1616GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1617{
76a66253 1618 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1619
1620 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1621 /* NOP */
1622 return;
1623 }
26d67362 1624 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1625}
79aceca5
FB		 1626/* xoris */
1627GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1628{
76a66253 1629 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1630
1631 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1632 /* NOP */
1633 return;
1634 }
26d67362 1635 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1636}
d9bce9d9 1637/* popcntb : PowerPC 2.03 specification */
05332d70 1638GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1639{
d9bce9d9
JM		 1640#if defined(TARGET_PPC64)
1641 if (ctx->sf_mode)
26d67362 1642 tcg_gen_helper_1_1(helper_popcntb_64, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1643 else
1644#endif
26d67362 1645 tcg_gen_helper_1_1(helper_popcntb, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1646}
1647
1648#if defined(TARGET_PPC64)
1649/* extsw & extsw. */
26d67362 1650GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1651/* cntlzd */
26d67362
AJ		 1652GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1653{
1654 tcg_gen_helper_1_1(helper_cntlzd, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1655 if (unlikely(Rc(ctx->opcode) != 0))
1656 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1657}
d9bce9d9
JM		 1658#endif
1659
79aceca5
FB		 1660/*** Integer rotate ***/
1661/* rlwimi & rlwimi. */
1662GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1663{
76a66253 1664 uint32_t mb, me, sh;
79aceca5
FB		 1665
1666 mb = MB(ctx->opcode);
1667 me = ME(ctx->opcode);
76a66253 1668 sh = SH(ctx->opcode);
d03ef511
AJ		 1669 if (likely(sh == 0 && mb == 0 && me == 31)) {
1670 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1671 } else {
1672 TCGv t0, t1;
1673 target_ulong mask;
1674
1675 t0 = tcg_temp_new(TCG_TYPE_TL);
1676 t1 = tcg_temp_new(TCG_TYPE_TL);
1677 if (likely(sh == 0)) {
1678 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1679 } else {
1680 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1681 tcg_gen_shli_tl(t0, t1, sh);
1682 tcg_gen_shri_tl(t1, t1, 32 - sh);
1683 tcg_gen_or_tl(t0, t0, t1);
76a66253 1684 }
76a66253 1685#if defined(TARGET_PPC64)
d03ef511
AJ		 1686 mb += 32;
1687 me += 32;
76a66253 1688#endif
d03ef511
AJ		 1689 mask = MASK(mb, me);
1690 tcg_gen_andi_tl(t0, t0, mask);
1691 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1692 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1693 tcg_temp_free(t0);
1694 tcg_temp_free(t1);
1695 }
76a66253 1696 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1698}
1699/* rlwinm & rlwinm. */
1700GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1701{
1702 uint32_t mb, me, sh;
3b46e624 1703
79aceca5
FB		 1704 sh = SH(ctx->opcode);
1705 mb = MB(ctx->opcode);
1706 me = ME(ctx->opcode);
d03ef511
AJ		 1707
1708 if (likely(mb == 0 && me == (31 - sh))) {
1709 if (likely(sh == 0)) {
1710 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1711 } else {
1712 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1713 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1714 tcg_gen_shli_tl(t0, t0, sh);
1715 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1716 tcg_temp_free(t0);
79aceca5 1717 }
d03ef511
AJ		 1718 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1719 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1720 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1721 tcg_gen_shri_tl(t0, t0, mb);
1722 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1723 tcg_temp_free(t0);
1724 } else {
1725 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1726 if (likely(sh != 0)) {
1727 TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
1728 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1729 tcg_gen_shli_tl(t1, t0, sh);
1730 tcg_gen_shri_tl(t0, t0, 32 - sh);
1731 tcg_gen_or_tl(t0, t0, t1);
1732 tcg_temp_free(t1);
1733 } else {
1734 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
79aceca5 1735 }
76a66253 1736#if defined(TARGET_PPC64)
d03ef511
AJ		 1737 mb += 32;
1738 me += 32;
76a66253 1739#endif
d03ef511
AJ		 1740 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1741 tcg_temp_free(t0);
1742 }
76a66253 1743 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1744 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1745}
1746/* rlwnm & rlwnm. */
1747GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1748{
1749 uint32_t mb, me;
fdce4963 1750 TCGv t0, t1, t2;
79aceca5
FB		 1751
1752 mb = MB(ctx->opcode);
1753 me = ME(ctx->opcode);
d03ef511
AJ		 1754 t0 = tcg_temp_new(TCG_TYPE_TL);
1755 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1756 t1 = tcg_temp_new(TCG_TYPE_TL);
1757 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1758 t2 = tcg_temp_new(TCG_TYPE_TL);
1759 tcg_gen_shl_tl(t2, t1, t0);
fdce4963 1760 tcg_gen_subfi_tl(t0, 32, t0);
d03ef511
AJ		 1761 tcg_gen_shr_tl(t1, t1, t0);
1762 tcg_temp_free(t0);
1763 tcg_gen_or_tl(t2, t2, t1);
1764 tcg_temp_free(t1);
76a66253
JM		 1765 if (unlikely(mb != 0 || me != 31)) {
1766#if defined(TARGET_PPC64)
1767 mb += 32;
1768 me += 32;
1769#endif
d03ef511
AJ		 1770 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t2, MASK(mb, me));
1771 } else {
1772 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t2);
79aceca5 1773 }
d03ef511 1774 tcg_temp_free(t2);
76a66253 1775 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1776 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1777}
1778
d9bce9d9
JM		 1779#if defined(TARGET_PPC64)
1780#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1781GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1782{ \
1783 gen_##name(ctx, 0); \
1784} \
c7697e1f
JM		 1785GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1786 PPC_64B) \
d9bce9d9
JM		 1787{ \
1788 gen_##name(ctx, 1); \
1789}
1790#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1791GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1792{ \
1793 gen_##name(ctx, 0, 0); \
1794} \
c7697e1f
JM		 1795GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1796 PPC_64B) \
d9bce9d9
JM		 1797{ \
1798 gen_##name(ctx, 0, 1); \
1799} \
c7697e1f
JM		 1800GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1801 PPC_64B) \
d9bce9d9
JM		 1802{ \
1803 gen_##name(ctx, 1, 0); \
1804} \
c7697e1f
JM		 1805GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1806 PPC_64B) \
d9bce9d9
JM		 1807{ \
1808 gen_##name(ctx, 1, 1); \
1809}
51789c41 1810
b068d6a7
JM		 1811static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1812 uint32_t me, uint32_t sh)
51789c41 1813{
d03ef511
AJ		 1814 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1815 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1816 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1817 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1818 } else {
1819 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1820 if (likely(sh != 0)) {
1821 TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
1822 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1823 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
1824 tcg_gen_or_tl(t0, t0, t1);
1825 tcg_temp_free(t1);
1826 } else {
1827 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
51789c41 1828 }
d03ef511
AJ		 1829 if (likely(mb == 0 && me == 63)) {
1830 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1831 } else {
1832 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1833 }
d03ef511 1834 tcg_temp_free(t0);
51789c41 1835 }
51789c41 1836 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1837 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1838}
d9bce9d9 1839/* rldicl - rldicl. */
b068d6a7 1840static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1841{
51789c41 1842 uint32_t sh, mb;
d9bce9d9 1843
9d53c753
JM		 1844 sh = SH(ctx->opcode) | (shn << 5);
1845 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1846 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1847}
51789c41 1848GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1849/* rldicr - rldicr. */
b068d6a7 1850static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1851{
51789c41 1852 uint32_t sh, me;
d9bce9d9 1853
9d53c753
JM		 1854 sh = SH(ctx->opcode) | (shn << 5);
1855 me = MB(ctx->opcode) | (men << 5);
51789c41 1856 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1857}
51789c41 1858GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1859/* rldic - rldic. */
b068d6a7 1860static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1861{
51789c41 1862 uint32_t sh, mb;
d9bce9d9 1863
9d53c753
JM		 1864 sh = SH(ctx->opcode) | (shn << 5);
1865 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1866 gen_rldinm(ctx, mb, 63 - sh, sh);
1867}
1868GEN_PPC64_R4(rldic, 0x1E, 0x04);
1869
b068d6a7
JM		 1870static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1871 uint32_t me)
51789c41 1872{
fdce4963 1873 TCGv t0, t1;
d03ef511
AJ		 1874
1875 mb = MB(ctx->opcode);
1876 me = ME(ctx->opcode);
1877 t0 = tcg_temp_new(TCG_TYPE_TL);
1878 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1879 t1 = tcg_temp_new(TCG_TYPE_TL);
1880 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t0);
fdce4963 1881 tcg_gen_subfi_tl(t0, 64, t0);
d03ef511
AJ		 1882 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1883 tcg_gen_or_tl(t1, t1, t0);
1884 tcg_temp_free(t0);
51789c41 1885 if (unlikely(mb != 0 || me != 63)) {
d03ef511
AJ		 1886 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t1, MASK(mb, me));
1887 } else
1888 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
1889 tcg_temp_free(t1);
51789c41 1890 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1892}
51789c41 1893
d9bce9d9 1894/* rldcl - rldcl. */
b068d6a7 1895static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1896{
51789c41 1897 uint32_t mb;
d9bce9d9 1898
9d53c753 1899 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1900 gen_rldnm(ctx, mb, 63);
d9bce9d9 1901}
36081602 1902GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1903/* rldcr - rldcr. */
b068d6a7 1904static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1905{
51789c41 1906 uint32_t me;
d9bce9d9 1907
9d53c753 1908 me = MB(ctx->opcode) | (men << 5);
51789c41 1909 gen_rldnm(ctx, 0, me);
d9bce9d9 1910}
36081602 1911GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1912/* rldimi - rldimi. */
b068d6a7 1913static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1914{
271a916e 1915 uint32_t sh, mb, me;
d9bce9d9 1916
9d53c753
JM		 1917 sh = SH(ctx->opcode) | (shn << 5);
1918 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1919 me = 63 - sh;
d03ef511
AJ		 1920 if (unlikely(sh == 0 && mb == 0)) {
1921 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1922 } else {
1923 TCGv t0, t1;
1924 target_ulong mask;
1925
1926 t0 = tcg_temp_new(TCG_TYPE_TL);
1927 t1 = tcg_temp_new(TCG_TYPE_TL);
1928 if (likely(sh == 0)) {
1929 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1930 } else {
1931 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1932 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
1933 tcg_gen_or_tl(t0, t0, t1);
51789c41 1934 }
d03ef511
AJ		 1935 mask = MASK(mb, me);
1936 tcg_gen_andi_tl(t0, t0, mask);
1937 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1938 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1939 tcg_temp_free(t0);
1940 tcg_temp_free(t1);
51789c41 1941 }
51789c41 1942 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1943 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1944}
36081602 1945GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1946#endif
1947
79aceca5
FB		 1948/*** Integer shift ***/
1949/* slw & slw. */
26d67362
AJ		 1950GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1951{
fea0c503 1952 TCGv t0;
26d67362
AJ		 1953 int l1, l2;
1954 l1 = gen_new_label();
1955 l2 = gen_new_label();
1956
fea0c503 1957 t0 = tcg_temp_local_new(TCG_TYPE_TL);
0cfe58cd
AJ		 1958 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1959 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1960 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1961 tcg_gen_br(l2);
1962 gen_set_label(l1);
fea0c503 1963 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1964 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1965 gen_set_label(l2);
fea0c503 1966 tcg_temp_free(t0);
26d67362
AJ		 1967 if (unlikely(Rc(ctx->opcode) != 0))
1968 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1969}
79aceca5 1970/* sraw & sraw. */
26d67362
AJ		 1971GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1972{
1973 tcg_gen_helper_1_2(helper_sraw, cpu_gpr[rA(ctx->opcode)],
1974 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1975 if (unlikely(Rc(ctx->opcode) != 0))
1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1977}
79aceca5
FB		 1978/* srawi & srawi. */
1979GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1980{
26d67362
AJ		 1981 int sh = SH(ctx->opcode);
1982 if (sh != 0) {
1983 int l1, l2;
fea0c503 1984 TCGv t0;
26d67362
AJ		 1985 l1 = gen_new_label();
1986 l2 = gen_new_label();
fea0c503
AJ		 1987 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1988 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1989 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1990 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1991 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1992 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1993 tcg_gen_br(l2);
1994 gen_set_label(l1);
269f3e95 1995 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1996 gen_set_label(l2);
fea0c503
AJ		 1997 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1998 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1999 tcg_temp_free(t0);
26d67362
AJ		 2000 } else {
2001 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2002 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2003 }
76a66253 2004 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2005 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 2006}
2007/* srw & srw. */
26d67362
AJ		 2008GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
2009{
fea0c503 2010 TCGv t0, t1;
26d67362
AJ		 2011 int l1, l2;
2012 l1 = gen_new_label();
2013 l2 = gen_new_label();
d9bce9d9 2014
fea0c503 2015 t0 = tcg_temp_local_new(TCG_TYPE_TL);
0cfe58cd
AJ		 2016 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
2017 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 2018 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2019 tcg_gen_br(l2);
2020 gen_set_label(l1);
fea0c503
AJ		 2021 t1 = tcg_temp_new(TCG_TYPE_TL);
2022 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
2023 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
2024 tcg_temp_free(t1);
26d67362 2025 gen_set_label(l2);
fea0c503 2026 tcg_temp_free(t0);
26d67362
AJ		 2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029}
d9bce9d9
JM		 2030#if defined(TARGET_PPC64)
2031/* sld & sld. */
26d67362
AJ		 2032GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2033{
fea0c503 2034 TCGv t0;
26d67362
AJ		 2035 int l1, l2;
2036 l1 = gen_new_label();
2037 l2 = gen_new_label();
2038
fea0c503 2039 t0 = tcg_temp_local_new(TCG_TYPE_TL);
0cfe58cd
AJ		 2040 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2041 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2042 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2043 tcg_gen_br(l2);
2044 gen_set_label(l1);
fea0c503 2045 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2046 gen_set_label(l2);
fea0c503 2047 tcg_temp_free(t0);
26d67362
AJ		 2048 if (unlikely(Rc(ctx->opcode) != 0))
2049 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2050}
d9bce9d9 2051/* srad & srad. */
26d67362
AJ		 2052GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2053{
2054 tcg_gen_helper_1_2(helper_srad, cpu_gpr[rA(ctx->opcode)],
2055 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2056 if (unlikely(Rc(ctx->opcode) != 0))
2057 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2058}
d9bce9d9 2059/* sradi & sradi. */
b068d6a7 2060static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2061{
26d67362 2062 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2063 if (sh != 0) {
26d67362 2064 int l1, l2;
fea0c503 2065 TCGv t0;
26d67362
AJ		 2066 l1 = gen_new_label();
2067 l2 = gen_new_label();
2068 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2069 t0 = tcg_temp_new(TCG_TYPE_TL);
2070 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2071 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2072 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2073 tcg_gen_br(l2);
2074 gen_set_label(l1);
269f3e95 2075 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362
AJ		 2076 gen_set_label(l2);
2077 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2078 } else {
2079 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2080 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2081 }
d9bce9d9 2082 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2084}
c7697e1f 2085GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2086{
2087 gen_sradi(ctx, 0);
2088}
c7697e1f 2089GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2090{
2091 gen_sradi(ctx, 1);
2092}
2093/* srd & srd. */
26d67362
AJ		 2094GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2095{
fea0c503 2096 TCGv t0;
26d67362
AJ		 2097 int l1, l2;
2098 l1 = gen_new_label();
2099 l2 = gen_new_label();
2100
fea0c503 2101 t0 = tcg_temp_local_new(TCG_TYPE_TL);
0cfe58cd
AJ		 2102 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2103 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2104 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2105 tcg_gen_br(l2);
2106 gen_set_label(l1);
fea0c503 2107 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2108 gen_set_label(l2);
fea0c503 2109 tcg_temp_free(t0);
26d67362
AJ		 2110 if (unlikely(Rc(ctx->opcode) != 0))
2111 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2112}
d9bce9d9 2113#endif
79aceca5
FB		 2114
2115/*** Floating-Point arithmetic ***/
7c58044c 2116#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2117GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2118{ \
76a66253 2119 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2120 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2121 return; \
2122 } \
a5e26afa
AJ		 2123 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2124 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
2125 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2126 gen_reset_fpstatus(); \
4ecc3190
FB		 2127 gen_op_f##op(); \
2128 if (isfloat) { \
2129 gen_op_frsp(); \
2130 } \
a5e26afa 2131 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2132 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2133}
2134
7c58044c
JM		 2135#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2136_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2137_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2138
7c58044c
JM		 2139#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2140GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2141{ \
76a66253 2142 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2143 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2144 return; \
2145 } \
a5e26afa
AJ		 2146 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2147 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2148 gen_reset_fpstatus(); \
4ecc3190
FB		 2149 gen_op_f##op(); \
2150 if (isfloat) { \
2151 gen_op_frsp(); \
2152 } \
a5e26afa 2153 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2154 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2155}
7c58044c
JM		 2156#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2157_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2158_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2159
7c58044c
JM		 2160#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2161GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2162{ \
76a66253 2163 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2164 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2165 return; \
2166 } \
a5e26afa
AJ		 2167 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2168 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
7c58044c 2169 gen_reset_fpstatus(); \
4ecc3190
FB		 2170 gen_op_f##op(); \
2171 if (isfloat) { \
2172 gen_op_frsp(); \
2173 } \
a5e26afa 2174 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2175 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2176}
7c58044c
JM		 2177#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2178_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2179_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2180
7c58044c 2181#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2182GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2183{ \
76a66253 2184 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2185 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2186 return; \
2187 } \
a5e26afa 2188 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2189 gen_reset_fpstatus(); \
9a64fbe4 2190 gen_op_f##name(); \
a5e26afa 2191 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2192 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2193}
2194
7c58044c 2195#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2196GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2197{ \
76a66253 2198 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2199 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2200 return; \
2201 } \
a5e26afa 2202 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2203 gen_reset_fpstatus(); \
9a64fbe4 2204 gen_op_f##name(); \
a5e26afa 2205 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2206 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2207}
2208
9a64fbe4 2209/* fadd - fadds */
7c58044c 2210GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2211/* fdiv - fdivs */
7c58044c 2212GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2213/* fmul - fmuls */
7c58044c 2214GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2215
d7e4b87e 2216/* fre */
7c58044c 2217GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2218
a750fc0b 2219/* fres */
7c58044c 2220GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2221
a750fc0b 2222/* frsqrte */
7c58044c
JM		 2223GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2224
2225/* frsqrtes */
2226static always_inline void gen_op_frsqrtes (void)
2227{
2228 gen_op_frsqrte();
2229 gen_op_frsp();
2230}
1b413d55 2231GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 2232
a750fc0b 2233/* fsel */
7c58044c 2234_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2235/* fsub - fsubs */
7c58044c 2236GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2237/* Optional: */
2238/* fsqrt */
a750fc0b 2239GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2240{
76a66253 2241 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2242 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2243 return;
2244 }
a5e26afa 2245 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2246 gen_reset_fpstatus();
c7d344af 2247 gen_op_fsqrt();
a5e26afa 2248 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2249 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 2250}
79aceca5 2251
a750fc0b 2252GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2253{
76a66253 2254 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2255 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2256 return;
2257 }
a5e26afa 2258 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2259 gen_reset_fpstatus();
4ecc3190
FB		 2260 gen_op_fsqrt();
2261 gen_op_frsp();
a5e26afa 2262 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2263 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2264}
2265
2266/*** Floating-Point multiply-and-add ***/
4ecc3190 2267/* fmadd - fmadds */
7c58044c 2268GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2269/* fmsub - fmsubs */
7c58044c 2270GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2271/* fnmadd - fnmadds */
7c58044c 2272GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2273/* fnmsub - fnmsubs */
7c58044c 2274GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2275
2276/*** Floating-Point round & convert ***/
2277/* fctiw */
7c58044c 2278GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2279/* fctiwz */
7c58044c 2280GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2281/* frsp */
7c58044c 2282GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2283#if defined(TARGET_PPC64)
2284/* fcfid */
7c58044c 2285GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2286/* fctid */
7c58044c 2287GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2288/* fctidz */
7c58044c 2289GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2290#endif
79aceca5 2291
d7e4b87e 2292/* frin */
7c58044c 2293GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2294/* friz */
7c58044c 2295GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2296/* frip */
7c58044c 2297GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2298/* frim */
7c58044c 2299GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2300
79aceca5
FB		 2301/*** Floating-Point compare ***/
2302/* fcmpo */
76a66253 2303GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2304{
76a66253 2305 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2306 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2307 return;
2308 }
a5e26afa
AJ		 2309 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2310 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2311 gen_reset_fpstatus();
e1571908 2312 tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2313 gen_op_float_check_status();
79aceca5
FB		 2314}
2315
2316/* fcmpu */
76a66253 2317GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2318{
76a66253 2319 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2320 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2321 return;
2322 }
a5e26afa
AJ		 2323 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2324 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2325 gen_reset_fpstatus();
e1571908 2326 tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2327 gen_op_float_check_status();
79aceca5
FB		 2328}
2329
9a64fbe4
FB		 2330/*** Floating-point move ***/
2331/* fabs */
7c58044c
JM		 2332/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2333GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2334
2335/* fmr - fmr. */
7c58044c 2336/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2337GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2338{
76a66253 2339 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2340 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2341 return;
2342 }
a5e26afa
AJ		 2343 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2344 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2345 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2346}
2347
2348/* fnabs */
7c58044c
JM		 2349/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2350GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2351/* fneg */
7c58044c
JM		 2352/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2353GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2354
79aceca5
FB		 2355/*** Floating-Point status & ctrl register ***/
2356/* mcrfs */
2357GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2358{
7c58044c
JM		 2359 int bfa;
2360
76a66253 2361 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2362 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2363 return;
2364 }
7c58044c
JM		 2365 gen_optimize_fprf();
2366 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2367 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2368 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
7c58044c 2369 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 2370}
2371
2372/* mffs */
2373GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2374{
76a66253 2375 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2376 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2377 return;
2378 }
7c58044c
JM		 2379 gen_optimize_fprf();
2380 gen_reset_fpstatus();
2381 gen_op_load_fpscr_FT0();
a5e26afa 2382 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2383 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2384}
2385
2386/* mtfsb0 */
2387GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2388{
fb0eaffc 2389 uint8_t crb;
3b46e624 2390
76a66253 2391 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2392 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2393 return;
2394 }
7c58044c
JM		 2395 crb = 32 - (crbD(ctx->opcode) >> 2);
2396 gen_optimize_fprf();
2397 gen_reset_fpstatus();
2398 if (likely(crb != 30 && crb != 29))
2399 gen_op_fpscr_resetbit(~(1 << crb));
2400 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2401 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2402 }
79aceca5
FB		 2403}
2404
2405/* mtfsb1 */
2406GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2407{
fb0eaffc 2408 uint8_t crb;
3b46e624 2409
76a66253 2410 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2411 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2412 return;
2413 }
7c58044c
JM		 2414 crb = 32 - (crbD(ctx->opcode) >> 2);
2415 gen_optimize_fprf();
2416 gen_reset_fpstatus();
2417 /* XXX: we pretend we can only do IEEE floating-point computations */
2418 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2419 gen_op_fpscr_setbit(crb);
2420 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2421 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2422 }
2423 /* We can raise a differed exception */
2424 gen_op_float_check_status();
79aceca5
FB		 2425}
2426
2427/* mtfsf */
2428GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2429{
76a66253 2430 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2431 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2432 return;
2433 }
7c58044c 2434 gen_optimize_fprf();
a5e26afa 2435 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2436 gen_reset_fpstatus();
28b6751f 2437 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c 2438 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2439 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2440 }
2441 /* We can raise a differed exception */
2442 gen_op_float_check_status();
79aceca5
FB		 2443}
2444
2445/* mtfsfi */
2446GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2447{
7c58044c
JM		 2448 int bf, sh;
2449
76a66253 2450 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2451 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2452 return;
2453 }
7c58044c
JM		 2454 bf = crbD(ctx->opcode) >> 2;
2455 sh = 7 - bf;
2456 gen_optimize_fprf();
489251fa 2457 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
7c58044c
JM		 2458 gen_reset_fpstatus();
2459 gen_op_store_fpscr(1 << sh);
2460 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2461 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2462 }
2463 /* We can raise a differed exception */
2464 gen_op_float_check_status();
79aceca5
FB		 2465}
2466
76a66253
JM		 2467/*** Addressing modes ***/
2468/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2469static always_inline void gen_addr_imm_index (TCGv EA,
2470 DisasContext *ctx,
b068d6a7 2471 target_long maskl)
76a66253
JM		 2472{
2473 target_long simm = SIMM(ctx->opcode);
2474
be147d08 2475 simm &= ~maskl;
e2be8d8d
AJ		 2476 if (rA(ctx->opcode) == 0)
2477 tcg_gen_movi_tl(EA, simm);
2478 else if (likely(simm != 0))
2479 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2480 else
2481 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2482}
2483
e2be8d8d
AJ		 2484static always_inline void gen_addr_reg_index (TCGv EA,
2485 DisasContext *ctx)
76a66253 2486{
e2be8d8d
AJ		 2487 if (rA(ctx->opcode) == 0)
2488 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2489 else
2490 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2491}
2492
e2be8d8d
AJ		 2493static always_inline void gen_addr_register (TCGv EA,
2494 DisasContext *ctx)
76a66253 2495{
e2be8d8d
AJ		 2496 if (rA(ctx->opcode) == 0)
2497 tcg_gen_movi_tl(EA, 0);
2498 else
2499 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2500}
2501
7863667f
JM		 2502#if defined(TARGET_PPC64)
2503#define _GEN_MEM_FUNCS(name, mode) \
2504 &gen_op_##name##_##mode, \
2505 &gen_op_##name##_le_##mode, \
2506 &gen_op_##name##_64_##mode, \
2507 &gen_op_##name##_le_64_##mode
2508#else
2509#define _GEN_MEM_FUNCS(name, mode) \
2510 &gen_op_##name##_##mode, \
2511 &gen_op_##name##_le_##mode
2512#endif
9a64fbe4 2513#if defined(CONFIG_USER_ONLY)
d9bce9d9 2514#if defined(TARGET_PPC64)
7863667f 2515#define NB_MEM_FUNCS 4
d9bce9d9 2516#else
7863667f 2517#define NB_MEM_FUNCS 2
d9bce9d9 2518#endif
7863667f
JM		 2519#define GEN_MEM_FUNCS(name) \
2520 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2521#else
d9bce9d9 2522#if defined(TARGET_PPC64)
7863667f 2523#define NB_MEM_FUNCS 12
2857068e 2524#else
7863667f 2525#define NB_MEM_FUNCS 6
2857068e 2526#endif
7863667f
JM		 2527#define GEN_MEM_FUNCS(name) \
2528 _GEN_MEM_FUNCS(name, user), \
2529 _GEN_MEM_FUNCS(name, kernel), \
2530 _GEN_MEM_FUNCS(name, hypv)
2531#endif
2532
2533/*** Integer load ***/
2534#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
d9bce9d9 2535#define OP_LD_TABLE(width) \
7863667f
JM		 2536static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2537 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2538};
2539#define OP_ST_TABLE(width) \
7863667f
JM		 2540static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2541 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2542};
9a64fbe4 2543
b61f2753
AJ		 2544
2545#if defined(TARGET_PPC64)
2546#define GEN_QEMU_LD_PPC64(width) \
2547static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2548{ \
2549 if (likely(flags & 2)) \
2550 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2551 else { \
2552 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2553 tcg_gen_ext32u_tl(addr, t1); \
2554 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2555 tcg_temp_free(addr); \
2556 } \
2557}
2558GEN_QEMU_LD_PPC64(8u)
2559GEN_QEMU_LD_PPC64(8s)
2560GEN_QEMU_LD_PPC64(16u)
2561GEN_QEMU_LD_PPC64(16s)
2562GEN_QEMU_LD_PPC64(32u)
2563GEN_QEMU_LD_PPC64(32s)
2564GEN_QEMU_LD_PPC64(64)
2565
2566#define GEN_QEMU_ST_PPC64(width) \
2567static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2568{ \
2569 if (likely(flags & 2)) \
2570 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2571 else { \
2572 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2573 tcg_gen_ext32u_tl(addr, t1); \
2574 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2575 tcg_temp_free(addr); \
2576 } \
2577}
2578GEN_QEMU_ST_PPC64(8)
2579GEN_QEMU_ST_PPC64(16)
2580GEN_QEMU_ST_PPC64(32)
2581GEN_QEMU_ST_PPC64(64)
2582
ea363694 2583static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2584{
ea363694 2585 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2586}
2587
ea363694 2588static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2589{
ea363694 2590 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2591}
2592
ea363694 2593static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2594{
2595 if (unlikely(flags & 1)) {
ea363694
AJ		 2596 TCGv t0;
2597 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2598 t0 = tcg_temp_new(TCG_TYPE_I32);
2599 tcg_gen_trunc_tl_i32(t0, arg0);
2600 tcg_gen_bswap16_i32(t0, t0);
2601 tcg_gen_extu_i32_tl(arg0, t0);
2602 tcg_temp_free(t0);
b61f2753 2603 } else
ea363694 2604 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2605}
2606
ea363694 2607static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2608{
2609 if (unlikely(flags & 1)) {
ea363694
AJ		 2610 TCGv t0;
2611 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2612 t0 = tcg_temp_new(TCG_TYPE_I32);
2613 tcg_gen_trunc_tl_i32(t0, arg0);
2614 tcg_gen_bswap16_i32(t0, t0);
2615 tcg_gen_extu_i32_tl(arg0, t0);
2616 tcg_gen_ext16s_tl(arg0, arg0);
2617 tcg_temp_free(t0);
b61f2753 2618 } else
ea363694 2619 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2620}
2621
ea363694 2622static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2623{
2624 if (unlikely(flags & 1)) {
ea363694
AJ		 2625 TCGv t0;
2626 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2627 t0 = tcg_temp_new(TCG_TYPE_I32);
2628 tcg_gen_trunc_tl_i32(t0, arg0);
2629 tcg_gen_bswap_i32(t0, t0);
2630 tcg_gen_extu_i32_tl(arg0, t0);
2631 tcg_temp_free(t0);
b61f2753 2632 } else
ea363694 2633 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2634}
2635
ea363694 2636static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2637{
2638 if (unlikely(flags & 1)) {
ea363694
AJ		 2639 TCGv t0;
2640 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2641 t0 = tcg_temp_new(TCG_TYPE_I32);
2642 tcg_gen_trunc_tl_i32(t0, arg0);
2643 tcg_gen_bswap_i32(t0, t0);
2644 tcg_gen_ext_i32_tl(arg0, t0);
2645 tcg_temp_free(t0);
b61f2753 2646 } else
ea363694 2647 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2648}
2649
ea363694 2650static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2651{
ea363694 2652 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2653 if (unlikely(flags & 1))
ea363694 2654 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2655}
2656
ea363694 2657static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2658{
ea363694 2659 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2660}
2661
ea363694 2662static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2663{
2664 if (unlikely(flags & 1)) {
ea363694
AJ		 2665 TCGv t0, t1;
2666 t0 = tcg_temp_new(TCG_TYPE_I32);
2667 tcg_gen_trunc_tl_i32(t0, arg0);
2668 tcg_gen_ext16u_i32(t0, t0);
2669 tcg_gen_bswap16_i32(t0, t0);
2670 t1 = tcg_temp_new(TCG_TYPE_I64);
2671 tcg_gen_extu_i32_tl(t1, t0);
2672 tcg_temp_free(t0);
2673 gen_qemu_st16_ppc64(t1, arg1, flags);
2674 tcg_temp_free(t1);
b61f2753 2675 } else
ea363694 2676 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2677}
2678
ea363694 2679static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2680{
2681 if (unlikely(flags & 1)) {
ea363694
AJ		 2682 TCGv t0, t1;
2683 t0 = tcg_temp_new(TCG_TYPE_I32);
2684 tcg_gen_trunc_tl_i32(t0, arg0);
2685 tcg_gen_bswap_i32(t0, t0);
2686 t1 = tcg_temp_new(TCG_TYPE_I64);
2687 tcg_gen_extu_i32_tl(t1, t0);
2688 tcg_temp_free(t0);
2689 gen_qemu_st32_ppc64(t1, arg1, flags);
2690 tcg_temp_free(t1);
b61f2753 2691 } else
ea363694 2692 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2693}
2694
ea363694 2695static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2696{
2697 if (unlikely(flags & 1)) {
ea363694
AJ		 2698 TCGv t0 = tcg_temp_new(TCG_TYPE_I64);
2699 tcg_gen_bswap_i64(t0, arg0);
2700 gen_qemu_st64_ppc64(t0, arg1, flags);
2701 tcg_temp_free(t0);
b61f2753 2702 } else
ea363694 2703 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2704}
2705
2706
2707#else /* defined(TARGET_PPC64) */
2708#define GEN_QEMU_LD_PPC32(width) \
ea363694 2709static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
b61f2753 2710{ \
ea363694 2711 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2712}
2713GEN_QEMU_LD_PPC32(8u)
2714GEN_QEMU_LD_PPC32(8s)
2715GEN_QEMU_LD_PPC32(16u)
2716GEN_QEMU_LD_PPC32(16s)
2717GEN_QEMU_LD_PPC32(32u)
2718GEN_QEMU_LD_PPC32(32s)
2719GEN_QEMU_LD_PPC32(64)
2720
2721#define GEN_QEMU_ST_PPC32(width) \
ea363694 2722static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
b61f2753 2723{ \
ea363694 2724 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2725}
2726GEN_QEMU_ST_PPC32(8)
2727GEN_QEMU_ST_PPC32(16)
2728GEN_QEMU_ST_PPC32(32)
2729GEN_QEMU_ST_PPC32(64)
2730
ea363694 2731static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2732{
ea363694 2733 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2734}
2735
ea363694 2736static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2737{
ea363694 2738 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2739}
2740
ea363694 2741static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2742{
ea363694 2743 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2744 if (unlikely(flags & 1))
ea363694 2745 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2746}
2747
ea363694 2748static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2749{
2750 if (unlikely(flags & 1)) {
ea363694
AJ		 2751 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2752 tcg_gen_bswap16_i32(arg0, arg0);
2753 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2754 } else
ea363694 2755 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2756}
2757
ea363694 2758static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2759{
ea363694 2760 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2761 if (unlikely(flags & 1))
ea363694 2762 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2763}
2764
ea363694 2765static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2766{
ea363694 2767 gen_qemu_ld64_ppc32(arg0, arg1, flags);
b61f2753 2768 if (unlikely(flags & 1))
ea363694 2769 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2770}
2771
ea363694 2772static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2773{
ea363694 2774 gen_qemu_st8_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2775}
2776
ea363694 2777static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2778{
2779 if (unlikely(flags & 1)) {
2780 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
ea363694 2781 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2782 tcg_gen_bswap16_i32(temp, temp);
ea363694 2783 gen_qemu_st16_ppc32(temp, arg1, flags >> 1);
312179c4 2784 tcg_temp_free(temp);
b61f2753 2785 } else
ea363694 2786 gen_qemu_st16_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2787}
2788
ea363694 2789static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2790{
2791 if (unlikely(flags & 1)) {
2792 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
ea363694
AJ		 2793 tcg_gen_bswap_i32(temp, arg0);
2794 gen_qemu_st32_ppc32(temp, arg1, flags >> 1);
312179c4 2795 tcg_temp_free(temp);
b61f2753 2796 } else
ea363694 2797 gen_qemu_st32_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2798}
2799
ea363694 2800static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2801{
2802 if (unlikely(flags & 1)) {
2803 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
ea363694
AJ		 2804 tcg_gen_bswap_i64(temp, arg0);
2805 gen_qemu_st64_ppc32(temp, arg1, flags >> 1);
312179c4 2806 tcg_temp_free(temp);
b61f2753 2807 } else
ea363694 2808 gen_qemu_st64_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2809}
2810
2811#endif
2812
d9bce9d9
JM		 2813#define GEN_LD(width, opc, type) \
2814GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2815{ \
b61f2753
AJ		 2816 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2817 gen_addr_imm_index(EA, ctx, 0); \
2818 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2819 tcg_temp_free(EA); \
79aceca5
FB		 2820}
2821
d9bce9d9
JM		 2822#define GEN_LDU(width, opc, type) \
2823GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2824{ \
b61f2753 2825 TCGv EA; \
76a66253
JM		 2826 if (unlikely(rA(ctx->opcode) == 0 || \
2827 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2828 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2829 return; \
9a64fbe4 2830 } \
b61f2753 2831 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2832 if (type == PPC_64B) \
b61f2753 2833 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2834 else \
b61f2753
AJ		 2835 gen_addr_imm_index(EA, ctx, 0); \
2836 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2837 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2838 tcg_temp_free(EA); \
79aceca5
FB		 2839}
2840
d9bce9d9
JM		 2841#define GEN_LDUX(width, opc2, opc3, type) \
2842GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2843{ \
b61f2753 2844 TCGv EA; \
76a66253
JM		 2845 if (unlikely(rA(ctx->opcode) == 0 || \
2846 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2847 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2848 return; \
9a64fbe4 2849 } \
b61f2753
AJ		 2850 EA = tcg_temp_new(TCG_TYPE_TL); \
2851 gen_addr_reg_index(EA, ctx); \
2852 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2853 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2854 tcg_temp_free(EA); \
79aceca5
FB		 2855}
2856
d9bce9d9
JM		 2857#define GEN_LDX(width, opc2, opc3, type) \
2858GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2859{ \
b61f2753
AJ		 2860 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2861 gen_addr_reg_index(EA, ctx); \
2862 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2863 tcg_temp_free(EA); \
79aceca5
FB		 2864}
2865
d9bce9d9 2866#define GEN_LDS(width, op, type) \
d9bce9d9
JM		 2867GEN_LD(width, op | 0x20, type); \
2868GEN_LDU(width, op | 0x21, type); \
2869GEN_LDUX(width, 0x17, op | 0x01, type); \
2870GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2871
2872/* lbz lbzu lbzux lbzx */
b61f2753 2873GEN_LDS(8u, 0x02, PPC_INTEGER);
79aceca5 2874/* lha lhau lhaux lhax */
b61f2753 2875GEN_LDS(16s, 0x0A, PPC_INTEGER);
79aceca5 2876/* lhz lhzu lhzux lhzx */
b61f2753 2877GEN_LDS(16u, 0x08, PPC_INTEGER);
79aceca5 2878/* lwz lwzu lwzux lwzx */
b61f2753 2879GEN_LDS(32u, 0x00, PPC_INTEGER);
d9bce9d9 2880#if defined(TARGET_PPC64)
d9bce9d9 2881/* lwaux */
b61f2753 2882GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2883/* lwax */
b61f2753 2884GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2885/* ldux */
b61f2753 2886GEN_LDUX(64, 0x15, 0x01, PPC_64B);
d9bce9d9 2887/* ldx */
b61f2753 2888GEN_LDX(64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2889GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2890{
b61f2753 2891 TCGv EA;
d9bce9d9
JM		 2892 if (Rc(ctx->opcode)) {
2893 if (unlikely(rA(ctx->opcode) == 0 ||
2894 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2895 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2896 return;
2897 }
2898 }
b61f2753
AJ		 2899 EA = tcg_temp_new(TCG_TYPE_TL);
2900 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2901 if (ctx->opcode & 0x02) {
2902 /* lwa (lwau is undefined) */
b61f2753 2903 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2904 } else {
2905 /* ld - ldu */
b61f2753 2906 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2907 }
d9bce9d9 2908 if (Rc(ctx->opcode))
b61f2753
AJ		 2909 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2910 tcg_temp_free(EA);
d9bce9d9 2911}
be147d08
JM		 2912/* lq */
2913GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2914{
2915#if defined(CONFIG_USER_ONLY)
2916 GEN_EXCP_PRIVOPC(ctx);
2917#else
2918 int ra, rd;
b61f2753 2919 TCGv EA;
be147d08
JM		 2920
2921 /* Restore CPU state */
2922 if (unlikely(ctx->supervisor == 0)) {
2923 GEN_EXCP_PRIVOPC(ctx);
2924 return;
2925 }
2926 ra = rA(ctx->opcode);
2927 rd = rD(ctx->opcode);
2928 if (unlikely((rd & 1) || rd == ra)) {
2929 GEN_EXCP_INVAL(ctx);
2930 return;
2931 }
2932 if (unlikely(ctx->mem_idx & 1)) {
2933 /* Little-endian mode is not handled */
2934 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2935 return;
2936 }
b61f2753
AJ		 2937 EA = tcg_temp_new(TCG_TYPE_TL);
2938 gen_addr_imm_index(EA, ctx, 0x0F);
2939 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2940 tcg_gen_addi_tl(EA, EA, 8);
2941 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2942 tcg_temp_free(EA);
be147d08
JM		 2943#endif
2944}
d9bce9d9 2945#endif
79aceca5
FB		 2946
2947/*** Integer store ***/
d9bce9d9
JM		 2948#define GEN_ST(width, opc, type) \
2949GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2950{ \
b61f2753
AJ		 2951 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2952 gen_addr_imm_index(EA, ctx, 0); \
2953 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2954 tcg_temp_free(EA); \
79aceca5
FB		 2955}
2956
d9bce9d9
JM		 2957#define GEN_STU(width, opc, type) \
2958GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2959{ \
b61f2753 2960 TCGv EA; \
76a66253 2961 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2962 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2963 return; \
9a64fbe4 2964 } \
b61f2753 2965 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2966 if (type == PPC_64B) \
b61f2753 2967 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2968 else \
b61f2753
AJ		 2969 gen_addr_imm_index(EA, ctx, 0); \
2970 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2971 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2972 tcg_temp_free(EA); \
79aceca5
FB		 2973}
2974
d9bce9d9
JM		 2975#define GEN_STUX(width, opc2, opc3, type) \
2976GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2977{ \
b61f2753 2978 TCGv EA; \
76a66253 2979 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2980 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2981 return; \
9a64fbe4 2982 } \
b61f2753
AJ		 2983 EA = tcg_temp_new(TCG_TYPE_TL); \
2984 gen_addr_reg_index(EA, ctx); \
2985 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2986 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2987 tcg_temp_free(EA); \
79aceca5
FB		 2988}
2989
d9bce9d9
JM		 2990#define GEN_STX(width, opc2, opc3, type) \
2991GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2992{ \
b61f2753
AJ		 2993 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2994 gen_addr_reg_index(EA, ctx); \
2995 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2996 tcg_temp_free(EA); \
79aceca5
FB		 2997}
2998
d9bce9d9 2999#define GEN_STS(width, op, type) \
d9bce9d9
JM		 3000GEN_ST(width, op | 0x20, type); \
3001GEN_STU(width, op | 0x21, type); \
3002GEN_STUX(width, 0x17, op | 0x01, type); \
3003GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 3004
3005/* stb stbu stbux stbx */
b61f2753 3006GEN_STS(8, 0x06, PPC_INTEGER);
79aceca5 3007/* sth sthu sthux sthx */
b61f2753 3008GEN_STS(16, 0x0C, PPC_INTEGER);
79aceca5 3009/* stw stwu stwux stwx */
b61f2753 3010GEN_STS(32, 0x04, PPC_INTEGER);
d9bce9d9 3011#if defined(TARGET_PPC64)
b61f2753
AJ		 3012GEN_STUX(64, 0x15, 0x05, PPC_64B);
3013GEN_STX(64, 0x15, 0x04, PPC_64B);
be147d08 3014GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 3015{
be147d08 3016 int rs;
b61f2753 3017 TCGv EA;
be147d08
JM		 3018
3019 rs = rS(ctx->opcode);
3020 if ((ctx->opcode & 0x3) == 0x2) {
3021#if defined(CONFIG_USER_ONLY)
3022 GEN_EXCP_PRIVOPC(ctx);
3023#else
3024 /* stq */
3025 if (unlikely(ctx->supervisor == 0)) {
3026 GEN_EXCP_PRIVOPC(ctx);
3027 return;
3028 }
3029 if (unlikely(rs & 1)) {
e1833e1f 3030 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 3031 return;
3032 }
be147d08
JM		 3033 if (unlikely(ctx->mem_idx & 1)) {
3034 /* Little-endian mode is not handled */
3035 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3036 return;
3037 }
b61f2753
AJ		 3038 EA = tcg_temp_new(TCG_TYPE_TL);
3039 gen_addr_imm_index(EA, ctx, 0x03);
3040 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3041 tcg_gen_addi_tl(EA, EA, 8);
3042 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3043 tcg_temp_free(EA);
be147d08
JM		 3044#endif
3045 } else {
3046 /* std / stdu */
3047 if (Rc(ctx->opcode)) {
3048 if (unlikely(rA(ctx->opcode) == 0)) {
3049 GEN_EXCP_INVAL(ctx);
3050 return;
3051 }
3052 }
b61f2753
AJ		 3053 EA = tcg_temp_new(TCG_TYPE_TL);
3054 gen_addr_imm_index(EA, ctx, 0x03);
3055 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 3056 if (Rc(ctx->opcode))
b61f2753
AJ		 3057 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3058 tcg_temp_free(EA);
d9bce9d9 3059 }
d9bce9d9
JM		 3060}
3061#endif
79aceca5
FB		 3062/*** Integer load and store with byte reverse ***/
3063/* lhbrx */
b61f2753
AJ		 3064void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3065{
3066 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3067 gen_qemu_ld16u(temp, t1, flags);
3068 tcg_gen_bswap16_i32(temp, temp);
3069 tcg_gen_extu_i32_tl(t0, temp);
3070 tcg_temp_free(temp);
3071}
3072GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
3073
79aceca5 3074/* lwbrx */
b61f2753
AJ		 3075void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3076{
3077 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3078 gen_qemu_ld32u(temp, t1, flags);
3079 tcg_gen_bswap_i32(temp, temp);
3080 tcg_gen_extu_i32_tl(t0, temp);
3081 tcg_temp_free(temp);
3082}
3083GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
3084
79aceca5 3085/* sthbrx */
b61f2753
AJ		 3086void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3087{
3088 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3089 tcg_gen_trunc_tl_i32(temp, t0);
3090 tcg_gen_ext16u_i32(temp, temp);
3091 tcg_gen_bswap16_i32(temp, temp);
3092 gen_qemu_st16(temp, t1, flags);
3093 tcg_temp_free(temp);
3094}
3095GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
3096
79aceca5 3097/* stwbrx */
b61f2753
AJ		 3098void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3099{
3100 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3101 tcg_gen_trunc_tl_i32(temp, t0);
3102 tcg_gen_bswap_i32(temp, temp);
3103 gen_qemu_st32(temp, t1, flags);
3104 tcg_temp_free(temp);
3105}
3106GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3107
3108/*** Integer load and store multiple ***/
111bfab3 3109#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 3110static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
3111 GEN_MEM_FUNCS(lmw),
d9bce9d9 3112};
7863667f
JM		 3113static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
3114 GEN_MEM_FUNCS(stmw),
d9bce9d9 3115};
9a64fbe4 3116
79aceca5
FB		 3117/* lmw */
3118GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3119{
76a66253 3120 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3121 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3122 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 3123 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 3124}
3125
3126/* stmw */
3127GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3128{
76a66253 3129 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3130 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3131 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 3132 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 3133}
3134
3135/*** Integer load and store strings ***/
9a64fbe4
FB		 3136#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
3137#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 3138/* string load & stores are by definition endian-safe */
3139#define gen_op_lswi_le_raw gen_op_lswi_raw
3140#define gen_op_lswi_le_user gen_op_lswi_user
3141#define gen_op_lswi_le_kernel gen_op_lswi_kernel
3142#define gen_op_lswi_le_hypv gen_op_lswi_hypv
3143#define gen_op_lswi_le_64_raw gen_op_lswi_raw
3144#define gen_op_lswi_le_64_user gen_op_lswi_user
3145#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
3146#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 3147static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
3148 GEN_MEM_FUNCS(lswi),
d9bce9d9 3149};
e7c24003
JM		 3150#define gen_op_lswx_le_raw gen_op_lswx_raw
3151#define gen_op_lswx_le_user gen_op_lswx_user
3152#define gen_op_lswx_le_kernel gen_op_lswx_kernel
3153#define gen_op_lswx_le_hypv gen_op_lswx_hypv
3154#define gen_op_lswx_le_64_raw gen_op_lswx_raw
3155#define gen_op_lswx_le_64_user gen_op_lswx_user
3156#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
3157#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 3158static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
3159 GEN_MEM_FUNCS(lswx),
d9bce9d9 3160};
e7c24003
JM		 3161#define gen_op_stsw_le_raw gen_op_stsw_raw
3162#define gen_op_stsw_le_user gen_op_stsw_user
3163#define gen_op_stsw_le_kernel gen_op_stsw_kernel
3164#define gen_op_stsw_le_hypv gen_op_stsw_hypv
3165#define gen_op_stsw_le_64_raw gen_op_stsw_raw
3166#define gen_op_stsw_le_64_user gen_op_stsw_user
3167#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3168#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 3169static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3170 GEN_MEM_FUNCS(stsw),
9a64fbe4 3171};
9a64fbe4 3172
79aceca5 3173/* lswi */
3fc6c082 3174/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3175 * rA is in the range of registers to be loaded.
3176 * In an other hand, IBM says this is valid, but rA won't be loaded.
3177 * For now, I'll follow the spec...
3178 */
05332d70 3179GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 3180{
3181 int nb = NB(ctx->opcode);
3182 int start = rD(ctx->opcode);
9a64fbe4 3183 int ra = rA(ctx->opcode);
79aceca5
FB		 3184 int nr;
3185
3186 if (nb == 0)
3187 nb = 32;
3188 nr = nb / 4;
76a66253
JM		 3189 if (unlikely(((start + nr) > 32 &&
3190 start <= ra && (start + nr - 32) > ra) ||
3191 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3192 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3193 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3194 return;
297d8e62 3195 }
8dd4983c 3196 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3197 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3198 gen_addr_register(cpu_T[0], ctx);
86c581dc 3199 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3200 op_ldsts(lswi, start);
79aceca5
FB		 3201}
3202
3203/* lswx */
05332d70 3204GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3205{
9a64fbe4
FB		 3206 int ra = rA(ctx->opcode);
3207 int rb = rB(ctx->opcode);
3208
76a66253 3209 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3210 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3211 gen_addr_reg_index(cpu_T[0], ctx);
9a64fbe4 3212 if (ra == 0) {
9a64fbe4 3213 ra = rb;
79aceca5 3214 }
3d7b417e 3215 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3216 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 3217}
3218
3219/* stswi */
05332d70 3220GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3221{
4b3686fa
FB		 3222 int nb = NB(ctx->opcode);
3223
76a66253 3224 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3225 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3226 gen_addr_register(cpu_T[0], ctx);
4b3686fa
FB		 3227 if (nb == 0)
3228 nb = 32;
86c581dc 3229 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3230 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3231}
3232
3233/* stswx */
05332d70 3234GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3235{
8dd4983c 3236 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3237 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3238 gen_addr_reg_index(cpu_T[0], ctx);
3d7b417e 3239 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3240 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3241}
3242
3243/*** Memory synchronisation ***/
3244/* eieio */
0db1b20e 3245GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3246{
79aceca5
FB		 3247}
3248
3249/* isync */
0db1b20e 3250GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3251{
e1833e1f 3252 GEN_STOP(ctx);
79aceca5
FB		 3253}
3254
111bfab3
FB		 3255#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3256#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 3257static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3258 GEN_MEM_FUNCS(lwarx),
111bfab3 3259};
7863667f
JM		 3260static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3261 GEN_MEM_FUNCS(stwcx),
985a19d6 3262};
9a64fbe4 3263
111bfab3 3264/* lwarx */
76a66253 3265GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3266{
30032c94
JM		 3267 /* NIP cannot be restored if the memory exception comes from an helper */
3268 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3269 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 3270 op_lwarx();
f78fb44e 3271 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 3272}
3273
3274/* stwcx. */
c7697e1f 3275GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3276{
30032c94
JM		 3277 /* NIP cannot be restored if the memory exception comes from an helper */
3278 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3279 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3280 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 3281 op_stwcx();
79aceca5
FB		 3282}
3283
426613db
JM		 3284#if defined(TARGET_PPC64)
3285#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3286#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 3287static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3288 GEN_MEM_FUNCS(ldarx),
426613db 3289};
7863667f
JM		 3290static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3291 GEN_MEM_FUNCS(stdcx),
426613db 3292};
426613db
JM		 3293
3294/* ldarx */
a750fc0b 3295GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3296{
30032c94
JM		 3297 /* NIP cannot be restored if the memory exception comes from an helper */
3298 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3299 gen_addr_reg_index(cpu_T[0], ctx);
426613db 3300 op_ldarx();
f78fb44e 3301 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 3302}
3303
3304/* stdcx. */
c7697e1f 3305GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3306{
30032c94
JM		 3307 /* NIP cannot be restored if the memory exception comes from an helper */
3308 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3309 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3310 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 3311 op_stdcx();
3312}
3313#endif /* defined(TARGET_PPC64) */
3314
79aceca5 3315/* sync */
a902d886 3316GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3317{
79aceca5
FB		 3318}
3319
0db1b20e
JM		 3320/* wait */
3321GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3322{
3323 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 3324 gen_op_wait();
3325 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3326}
3327
79aceca5 3328/*** Floating-point load ***/
477023a6
JM		 3329#define GEN_LDF(width, opc, type) \
3330GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3331{ \
76a66253 3332 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3333 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3334 return; \
3335 } \
e2be8d8d 3336 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3337 op_ldst(l##width); \
a5e26afa 3338 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3339}
3340
477023a6
JM		 3341#define GEN_LDUF(width, opc, type) \
3342GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3343{ \
76a66253 3344 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3345 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3346 return; \
3347 } \
76a66253 3348 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3349 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3350 return; \
9a64fbe4 3351 } \
e2be8d8d 3352 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3353 op_ldst(l##width); \
a5e26afa 3354 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3355 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3356}
3357
477023a6
JM		 3358#define GEN_LDUXF(width, opc, type) \
3359GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3360{ \
76a66253 3361 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3362 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3363 return; \
3364 } \
76a66253 3365 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3366 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3367 return; \
9a64fbe4 3368 } \
e2be8d8d 3369 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3370 op_ldst(l##width); \
a5e26afa 3371 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3372 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3373}
3374
477023a6
JM		 3375#define GEN_LDXF(width, opc2, opc3, type) \
3376GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3377{ \
76a66253 3378 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3379 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3380 return; \
3381 } \
e2be8d8d 3382 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3383 op_ldst(l##width); \
a5e26afa 3384 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3385}
3386
477023a6 3387#define GEN_LDFS(width, op, type) \
9a64fbe4 3388OP_LD_TABLE(width); \
477023a6
JM		 3389GEN_LDF(width, op | 0x20, type); \
3390GEN_LDUF(width, op | 0x21, type); \
3391GEN_LDUXF(width, op | 0x01, type); \
3392GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3393
3394/* lfd lfdu lfdux lfdx */
477023a6 3395GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 3396/* lfs lfsu lfsux lfsx */
477023a6 3397GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3398
3399/*** Floating-point store ***/
477023a6
JM		 3400#define GEN_STF(width, opc, type) \
3401GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3402{ \
76a66253 3403 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3404 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3405 return; \
3406 } \
e2be8d8d 3407 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3408 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3409 op_ldst(st##width); \
79aceca5
FB		 3410}
3411
477023a6
JM		 3412#define GEN_STUF(width, opc, type) \
3413GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3414{ \
76a66253 3415 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3416 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3417 return; \
3418 } \
76a66253 3419 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3420 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3421 return; \
9a64fbe4 3422 } \
e2be8d8d 3423 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3424 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3425 op_ldst(st##width); \
f78fb44e 3426 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3427}
3428
477023a6
JM		 3429#define GEN_STUXF(width, opc, type) \
3430GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3431{ \
76a66253 3432 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3433 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3434 return; \
3435 } \
76a66253 3436 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3437 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3438 return; \
9a64fbe4 3439 } \
e2be8d8d 3440 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3441 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3442 op_ldst(st##width); \
f78fb44e 3443 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3444}
3445
477023a6
JM		 3446#define GEN_STXF(width, opc2, opc3, type) \
3447GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3448{ \
76a66253 3449 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3450 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3451 return; \
3452 } \
e2be8d8d 3453 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3454 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3455 op_ldst(st##width); \
79aceca5
FB		 3456}
3457
477023a6 3458#define GEN_STFS(width, op, type) \
9a64fbe4 3459OP_ST_TABLE(width); \
477023a6
JM		 3460GEN_STF(width, op | 0x20, type); \
3461GEN_STUF(width, op | 0x21, type); \
3462GEN_STUXF(width, op | 0x01, type); \
3463GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3464
3465/* stfd stfdu stfdux stfdx */
477023a6 3466GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 3467/* stfs stfsu stfsux stfsx */
477023a6 3468GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3469
3470/* Optional: */
3471/* stfiwx */
5b8105fa
JM		 3472OP_ST_TABLE(fiw);
3473GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3474
3475/*** Branch ***/
b068d6a7
JM		 3476static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3477 target_ulong dest)
c1942362
FB		 3478{
3479 TranslationBlock *tb;
3480 tb = ctx->tb;
a2ffb812
AJ		 3481#if defined(TARGET_PPC64)
3482 if (!ctx->sf_mode)
3483 dest = (uint32_t) dest;
3484#endif
57fec1fe 3485 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3486 likely(!ctx->singlestep_enabled)) {
57fec1fe 3487 tcg_gen_goto_tb(n);
a2ffb812 3488 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3489 tcg_gen_exit_tb((long)tb + n);
c1942362 3490 } else {
a2ffb812 3491 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3492 if (unlikely(ctx->singlestep_enabled)) {
3493 if ((ctx->singlestep_enabled &
3494 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3495 ctx->exception == POWERPC_EXCP_BRANCH) {
3496 target_ulong tmp = ctx->nip;
3497 ctx->nip = dest;
3498 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3499 ctx->nip = tmp;
3500 }
3501 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3502 gen_update_nip(ctx, dest);
3503 gen_op_debug();
3504 }
3505 }
57fec1fe 3506 tcg_gen_exit_tb(0);
c1942362 3507 }
c53be334
FB		 3508}
3509
b068d6a7 3510static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3511{
3512#if defined(TARGET_PPC64)
a2ffb812
AJ		 3513 if (ctx->sf_mode == 0)
3514 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3515 else
3516#endif
a2ffb812 3517 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3518}
3519
79aceca5
FB		 3520/* b ba bl bla */
3521GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3522{
76a66253 3523 target_ulong li, target;
38a64f9d 3524
8cbcb4fa 3525 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3526 /* sign extend LI */
76a66253 3527#if defined(TARGET_PPC64)
d9bce9d9
JM		 3528 if (ctx->sf_mode)
3529 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3530 else
76a66253 3531#endif
d9bce9d9 3532 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3533 if (likely(AA(ctx->opcode) == 0))
046d6672 3534 target = ctx->nip + li - 4;
79aceca5 3535 else
9a64fbe4 3536 target = li;
e1833e1f
JM		 3537 if (LK(ctx->opcode))
3538 gen_setlr(ctx, ctx->nip);
c1942362 3539 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3540}
3541
e98a6e40
FB		 3542#define BCOND_IM 0
3543#define BCOND_LR 1
3544#define BCOND_CTR 2
3545
b068d6a7 3546static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3547{
d9bce9d9 3548 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3549 int l1 = gen_new_label();
3550 TCGv target;
e98a6e40 3551
8cbcb4fa 3552 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812
AJ		 3553 if (type == BCOND_LR || type == BCOND_CTR) {
3554 target = tcg_temp_local_new(TCG_TYPE_TL);
3555 if (type == BCOND_CTR)
3556 tcg_gen_mov_tl(target, cpu_ctr);
3557 else
3558 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3559 }
e1833e1f
JM		 3560 if (LK(ctx->opcode))
3561 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3562 l1 = gen_new_label();
3563 if ((bo & 0x4) == 0) {
3564 /* Decrement and test CTR */
3565 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3566 if (unlikely(type == BCOND_CTR)) {
3567 GEN_EXCP_INVAL(ctx);
3568 return;
3569 }
3570 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3571#if defined(TARGET_PPC64)
a2ffb812
AJ		 3572 if (!ctx->sf_mode)
3573 tcg_gen_ext32u_tl(temp, cpu_ctr);
3574 else
d9bce9d9 3575#endif
a2ffb812
AJ		 3576 tcg_gen_mov_tl(temp, cpu_ctr);
3577 if (bo & 0x2) {
3578 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3579 } else {
3580 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3581 }
a2ffb812
AJ		 3582 }
3583 if ((bo & 0x10) == 0) {
3584 /* Test CR */
3585 uint32_t bi = BI(ctx->opcode);
3586 uint32_t mask = 1 << (3 - (bi & 0x03));
3587 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3588
d9bce9d9 3589 if (bo & 0x8) {
a2ffb812
AJ		 3590 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3591 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3592 } else {
a2ffb812
AJ		 3593 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3594 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9
JM		 3595 }
3596 }
e98a6e40 3597 if (type == BCOND_IM) {
a2ffb812
AJ		 3598
3599 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3600 if (likely(AA(ctx->opcode) == 0)) {
3601 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3602 } else {
3603 gen_goto_tb(ctx, 0, li);
3604 }
c53be334 3605 gen_set_label(l1);
c1942362 3606 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3607 } else {
d9bce9d9 3608#if defined(TARGET_PPC64)
a2ffb812
AJ		 3609 if (!(ctx->sf_mode))
3610 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3611 else
3612#endif
3613 tcg_gen_andi_tl(cpu_nip, target, ~3);
3614 tcg_gen_exit_tb(0);
3615 gen_set_label(l1);
3616#if defined(TARGET_PPC64)
3617 if (!(ctx->sf_mode))
3618 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3619 else
3620#endif
a2ffb812 3621 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3622 tcg_gen_exit_tb(0);
08e46e54 3623 }
e98a6e40
FB		 3624}
3625
3626GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3627{
e98a6e40
FB		 3628 gen_bcond(ctx, BCOND_IM);
3629}
3630
3631GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3632{
e98a6e40
FB		 3633 gen_bcond(ctx, BCOND_CTR);
3634}
3635
3636GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3637{
e98a6e40
FB		 3638 gen_bcond(ctx, BCOND_LR);
3639}
79aceca5
FB		 3640
3641/*** Condition register logical ***/
e1571908
AJ		 3642#define GEN_CRLOGIC(name, tcg_op, opc) \
3643GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3644{ \
fc0d441e
JM		 3645 uint8_t bitmask; \
3646 int sh; \
fea0c503 3647 TCGv t0, t1; \
fc0d441e 3648 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
fea0c503 3649 t0 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e 3650 if (sh > 0) \
fea0c503 3651 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3652 else if (sh < 0) \
fea0c503 3653 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3654 else \
fea0c503
AJ		 3655 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3656 t1 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e
JM		 3657 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3658 if (sh > 0) \
fea0c503 3659 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3660 else if (sh < 0) \
fea0c503 3661 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3662 else \
fea0c503
AJ		 3663 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3664 tcg_op(t0, t0, t1); \
fc0d441e 3665 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3666 tcg_gen_andi_i32(t0, t0, bitmask); \
3667 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3668 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3669 tcg_temp_free(t0); \
3670 tcg_temp_free(t1); \
79aceca5
FB		 3671}
3672
3673/* crand */
e1571908 3674GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3675/* crandc */
e1571908 3676GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3677/* creqv */
e1571908 3678GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3679/* crnand */
e1571908 3680GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3681/* crnor */
e1571908 3682GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3683/* cror */
e1571908 3684GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3685/* crorc */
e1571908 3686GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3687/* crxor */
e1571908 3688GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3689/* mcrf */
3690GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3691{
47e4661c 3692 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3693}
3694
3695/*** System linkage ***/
3696/* rfi (supervisor only) */
76a66253 3697GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3698{
9a64fbe4 3699#if defined(CONFIG_USER_ONLY)
e1833e1f 3700 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3701#else
3702 /* Restore CPU state */
76a66253 3703 if (unlikely(!ctx->supervisor)) {
e1833e1f 3704 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3705 return;
9a64fbe4 3706 }
a42bd6cc 3707 gen_op_rfi();
e1833e1f 3708 GEN_SYNC(ctx);
9a64fbe4 3709#endif
79aceca5
FB		 3710}
3711
426613db 3712#if defined(TARGET_PPC64)
a750fc0b 3713GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3714{
3715#if defined(CONFIG_USER_ONLY)
e1833e1f 3716 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3717#else
3718 /* Restore CPU state */
3719 if (unlikely(!ctx->supervisor)) {
e1833e1f 3720 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3721 return;
3722 }
a42bd6cc 3723 gen_op_rfid();
e1833e1f 3724 GEN_SYNC(ctx);
426613db
JM		 3725#endif
3726}
426613db 3727
5b8105fa 3728GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3729{
3730#if defined(CONFIG_USER_ONLY)
3731 GEN_EXCP_PRIVOPC(ctx);
3732#else
3733 /* Restore CPU state */
3734 if (unlikely(ctx->supervisor <= 1)) {
3735 GEN_EXCP_PRIVOPC(ctx);
3736 return;
3737 }
3738 gen_op_hrfid();
3739 GEN_SYNC(ctx);
3740#endif
3741}
3742#endif
3743
79aceca5 3744/* sc */
417bf010
JM		 3745#if defined(CONFIG_USER_ONLY)
3746#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3747#else
3748#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3749#endif
e1833e1f 3750GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3751{
e1833e1f
JM		 3752 uint32_t lev;
3753
3754 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3755 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3756}
3757
3758/*** Trap ***/
3759/* tw */
76a66253 3760GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3761{
f78fb44e
AJ		 3762 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3763 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
a0ae05aa 3764 /* Update the nip since this might generate a trap exception */
d9bce9d9 3765 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3766 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3767}
3768
3769/* twi */
3770GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3771{
f78fb44e 3772 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3773 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3774 /* Update the nip since this might generate a trap exception */
3775 gen_update_nip(ctx, ctx->nip);
76a66253 3776 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3777}
3778
d9bce9d9
JM		 3779#if defined(TARGET_PPC64)
3780/* td */
3781GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3782{
f78fb44e
AJ		 3783 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3784 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3785 /* Update the nip since this might generate a trap exception */
3786 gen_update_nip(ctx, ctx->nip);
3787 gen_op_td(TO(ctx->opcode));
3788}
3789
3790/* tdi */
3791GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3792{
f78fb44e 3793 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3794 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3795 /* Update the nip since this might generate a trap exception */
3796 gen_update_nip(ctx, ctx->nip);
3797 gen_op_td(TO(ctx->opcode));
3798}
3799#endif
3800
79aceca5 3801/*** Processor control ***/
79aceca5
FB		 3802/* mcrxr */
3803GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3804{
3d7b417e
AJ		 3805 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3806 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3807 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3808}
3809
3810/* mfcr */
76a66253 3811GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3812{
76a66253 3813 uint32_t crm, crn;
3b46e624 3814
76a66253
JM		 3815 if (likely(ctx->opcode & 0x00100000)) {
3816 crm = CRM(ctx->opcode);
3817 if (likely((crm ^ (crm - 1)) == 0)) {
3818 crn = ffs(crm);
e1571908 3819 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3820 }
d9bce9d9 3821 } else {
e1571908 3822 tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3823 }
79aceca5
FB		 3824}
3825
3826/* mfmsr */
3827GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3828{
9a64fbe4 3829#if defined(CONFIG_USER_ONLY)
e1833e1f 3830 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3831#else
76a66253 3832 if (unlikely(!ctx->supervisor)) {
e1833e1f 3833 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3834 return;
9a64fbe4 3835 }
6676f424 3836 gen_op_load_msr();
f78fb44e 3837 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3838#endif
79aceca5
FB		 3839}
3840
a11b8151 3841#if 1
6f2d8978 3842#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3843#else
3844static void spr_noaccess (void *opaque, int sprn)
3845{
3846 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3847 printf("ERROR: try to access SPR %d !\n", sprn);
3848}
3849#define SPR_NOACCESS (&spr_noaccess)
3850#endif
3851
79aceca5 3852/* mfspr */
b068d6a7 3853static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3854{
3fc6c082 3855 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3856 uint32_t sprn = SPR(ctx->opcode);
3857
3fc6c082 3858#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3859 if (ctx->supervisor == 2)
3860 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3861 else if (ctx->supervisor)
3fc6c082
FB		 3862 read_cb = ctx->spr_cb[sprn].oea_read;
3863 else
9a64fbe4 3864#endif
3fc6c082 3865 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3866 if (likely(read_cb != NULL)) {
3867 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3868 (*read_cb)(ctx, sprn);
f78fb44e 3869 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3870 } else {
3871 /* Privilege exception */
9fceefa7
JM		 3872 /* This is a hack to avoid warnings when running Linux:
3873 * this OS breaks the PowerPC virtualisation model,
3874 * allowing userland application to read the PVR
3875 */
3876 if (sprn != SPR_PVR) {
3877 if (loglevel != 0) {
6b542af7 3878 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3879 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3880 }
077fc206
JM		 3881 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3882 sprn, sprn, ctx->nip);
f24e5695 3883 }
e1833e1f 3884 GEN_EXCP_PRIVREG(ctx);
79aceca5 3885 }
3fc6c082
FB		 3886 } else {
3887 /* Not defined */
4a057712 3888 if (loglevel != 0) {
077fc206
JM		 3889 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3890 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3891 }
077fc206
JM		 3892 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3893 sprn, sprn, ctx->nip);
e1833e1f
JM		 3894 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3895 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3896 }
79aceca5
FB		 3897}
3898
3fc6c082 3899GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3900{
3fc6c082 3901 gen_op_mfspr(ctx);
76a66253 3902}
3fc6c082
FB		 3903
3904/* mftb */
a750fc0b 3905GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3906{
3907 gen_op_mfspr(ctx);
79aceca5
FB		 3908}
3909
3910/* mtcrf */
8dd4983c 3911GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3912{
76a66253 3913 uint32_t crm, crn;
3b46e624 3914
76a66253
JM		 3915 crm = CRM(ctx->opcode);
3916 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3917 crn = ffs(crm);
e1571908
AJ		 3918 tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3919 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
76a66253 3920 } else {
fea0c503
AJ		 3921 TCGv t0 = tcg_const_tl(crm);
3922 tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], t0);
3923 tcg_temp_free(t0);
76a66253 3924 }
79aceca5
FB		 3925}
3926
3927/* mtmsr */
426613db 3928#if defined(TARGET_PPC64)
be147d08 3929GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3930{
3931#if defined(CONFIG_USER_ONLY)
e1833e1f 3932 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3933#else
3934 if (unlikely(!ctx->supervisor)) {
e1833e1f 3935 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3936 return;
3937 }
f78fb44e 3938 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3939 if (ctx->opcode & 0x00010000) {
3940 /* Special form that does not need any synchronisation */
3941 gen_op_update_riee();
3942 } else {
056b05f8
JM		 3943 /* XXX: we need to update nip before the store
3944 * if we enter power saving mode, we will exit the loop
3945 * directly from ppc_store_msr
3946 */
be147d08 3947 gen_update_nip(ctx, ctx->nip);
6676f424 3948 gen_op_store_msr();
be147d08
JM		 3949 /* Must stop the translation as machine state (may have) changed */
3950 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3951 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3952 }
426613db
JM		 3953#endif
3954}
3955#endif
3956
79aceca5
FB		 3957GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3958{
9a64fbe4 3959#if defined(CONFIG_USER_ONLY)
e1833e1f 3960 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3961#else
76a66253 3962 if (unlikely(!ctx->supervisor)) {
e1833e1f 3963 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3964 return;
9a64fbe4 3965 }
f78fb44e 3966 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3967 if (ctx->opcode & 0x00010000) {
3968 /* Special form that does not need any synchronisation */
3969 gen_op_update_riee();
3970 } else {
056b05f8
JM		 3971 /* XXX: we need to update nip before the store
3972 * if we enter power saving mode, we will exit the loop
3973 * directly from ppc_store_msr
3974 */
be147d08 3975 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3976#if defined(TARGET_PPC64)
be147d08 3977 if (!ctx->sf_mode)
6676f424 3978 gen_op_store_msr_32();
be147d08 3979 else
d9bce9d9 3980#endif
6676f424 3981 gen_op_store_msr();
be147d08
JM		 3982 /* Must stop the translation as machine state (may have) changed */
3983 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3984 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3985 }
9a64fbe4 3986#endif
79aceca5
FB		 3987}
3988
3989/* mtspr */
3990GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3991{
3fc6c082 3992 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3993 uint32_t sprn = SPR(ctx->opcode);
3994
3fc6c082 3995#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3996 if (ctx->supervisor == 2)
3997 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3998 else if (ctx->supervisor)
3fc6c082
FB		 3999 write_cb = ctx->spr_cb[sprn].oea_write;
4000 else
9a64fbe4 4001#endif
3fc6c082 4002 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4003 if (likely(write_cb != NULL)) {
4004 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 4005 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 4006 (*write_cb)(ctx, sprn);
4007 } else {
4008 /* Privilege exception */
4a057712 4009 if (loglevel != 0) {
077fc206
JM		 4010 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4011 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4012 }
077fc206
JM		 4013 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4014 sprn, sprn, ctx->nip);
e1833e1f 4015 GEN_EXCP_PRIVREG(ctx);
76a66253 4016 }
3fc6c082
FB		 4017 } else {
4018 /* Not defined */
4a057712 4019 if (loglevel != 0) {
077fc206
JM		 4020 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4021 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4022 }
077fc206
JM		 4023 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4024 sprn, sprn, ctx->nip);
e1833e1f
JM		 4025 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4026 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 4027 }
79aceca5
FB		 4028}
4029
4030/*** Cache management ***/
79aceca5 4031/* dcbf */
0db1b20e 4032GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4033{
dac454af 4034 /* XXX: specification says this is treated as a load by the MMU */
fea0c503
AJ		 4035 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
4036 gen_addr_reg_index(t0, ctx);
4037 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4038 tcg_temp_free(t0);
79aceca5
FB		 4039}
4040
4041/* dcbi (Supervisor only) */
9a64fbe4 4042GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4043{
a541f297 4044#if defined(CONFIG_USER_ONLY)
e1833e1f 4045 GEN_EXCP_PRIVOPC(ctx);
a541f297 4046#else
b61f2753 4047 TCGv EA, val;
76a66253 4048 if (unlikely(!ctx->supervisor)) {
e1833e1f 4049 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4050 return;
9a64fbe4 4051 }
b61f2753
AJ		 4052 EA = tcg_temp_new(TCG_TYPE_TL);
4053 gen_addr_reg_index(EA, ctx);
ed69522c 4054 val = tcg_temp_new(TCG_TYPE_TL);
76a66253 4055 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 4056 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4057 gen_qemu_st8(val, EA, ctx->mem_idx);
4058 tcg_temp_free(val);
4059 tcg_temp_free(EA);
a541f297 4060#endif
79aceca5
FB		 4061}
4062
4063/* dcdst */
9a64fbe4 4064GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4065{
76a66253 4066 /* XXX: specification say this is treated as a load by the MMU */
fea0c503
AJ		 4067 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
4068 gen_addr_reg_index(t0, ctx);
4069 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4070 tcg_temp_free(t0);
79aceca5
FB		 4071}
4072
4073/* dcbt */
0db1b20e 4074GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4075{
0db1b20e 4076 /* interpreted as no-op */
76a66253
JM		 4077 /* XXX: specification say this is treated as a load by the MMU
4078 * but does not generate any exception
4079 */
79aceca5
FB		 4080}
4081
4082/* dcbtst */
0db1b20e 4083GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4084{
0db1b20e 4085 /* interpreted as no-op */
76a66253
JM		 4086 /* XXX: specification say this is treated as a load by the MMU
4087 * but does not generate any exception
4088 */
79aceca5
FB		 4089}
4090
4091/* dcbz */
d63001d1 4092#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 4093static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
4094 /* 32 bytes cache line size */
d63001d1 4095 {
7863667f
JM		 4096#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
4097#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
4098#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
4099#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
4100#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
4101#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
4102#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
4103#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
4104 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 4105 },
7863667f 4106 /* 64 bytes cache line size */
d63001d1 4107 {
7863667f
JM		 4108#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
4109#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
4110#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
4111#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
4112#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
4113#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
4114#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
4115#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
4116 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 4117 },
7863667f 4118 /* 128 bytes cache line size */
d63001d1 4119 {
7863667f
JM		 4120#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
4121#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
4122#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
4123#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
4124#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
4125#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
4126#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
4127#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
4128 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 4129 },
7863667f 4130 /* tunable cache line size */
d63001d1 4131 {
7863667f
JM		 4132#define gen_op_dcbz_le_raw gen_op_dcbz_raw
4133#define gen_op_dcbz_le_user gen_op_dcbz_user
4134#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
4135#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
4136#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
4137#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
4138#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
4139#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
4140 GEN_MEM_FUNCS(dcbz),
d63001d1 4141 },
76a66253 4142};
9a64fbe4 4143
b068d6a7
JM		 4144static always_inline void handler_dcbz (DisasContext *ctx,
4145 int dcache_line_size)
d63001d1
JM		 4146{
4147 int n;
4148
4149 switch (dcache_line_size) {
4150 case 32:
4151 n = 0;
4152 break;
4153 case 64:
4154 n = 1;
4155 break;
4156 case 128:
4157 n = 2;
4158 break;
4159 default:
4160 n = 3;
4161 break;
4162 }
4163 op_dcbz(n);
4164}
4165
4166GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4167{
e2be8d8d 4168 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 4169 handler_dcbz(ctx, ctx->dcache_line_size);
4170 gen_op_check_reservation();
4171}
4172
c7697e1f 4173GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4174{
e2be8d8d 4175 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 4176 if (ctx->opcode & 0x00200000)
4177 handler_dcbz(ctx, ctx->dcache_line_size);
4178 else
4179 handler_dcbz(ctx, -1);
4b3686fa 4180 gen_op_check_reservation();
79aceca5
FB		 4181}
4182
4183/* icbi */
36f69651 4184#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 4185#define gen_op_icbi_le_raw gen_op_icbi_raw
4186#define gen_op_icbi_le_user gen_op_icbi_user
4187#define gen_op_icbi_le_kernel gen_op_icbi_kernel
4188#define gen_op_icbi_le_hypv gen_op_icbi_hypv
4189#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4190#define gen_op_icbi_le_64_user gen_op_icbi_64_user
4191#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4192#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4193static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4194 GEN_MEM_FUNCS(icbi),
36f69651 4195};
e1833e1f 4196
1b413d55 4197GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4198{
30032c94
JM		 4199 /* NIP cannot be restored if the memory exception comes from an helper */
4200 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4201 gen_addr_reg_index(cpu_T[0], ctx);
36f69651 4202 op_icbi();
79aceca5
FB		 4203}
4204
4205/* Optional: */
4206/* dcba */
a750fc0b 4207GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4208{
0db1b20e
JM		 4209 /* interpreted as no-op */
4210 /* XXX: specification say this is treated as a store by the MMU
4211 * but does not generate any exception
4212 */
79aceca5
FB		 4213}
4214
4215/*** Segment register manipulation ***/
4216/* Supervisor only: */
4217/* mfsr */
4218GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4219{
9a64fbe4 4220#if defined(CONFIG_USER_ONLY)
e1833e1f 4221 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4222#else
76a66253 4223 if (unlikely(!ctx->supervisor)) {
e1833e1f 4224 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4225 return;
9a64fbe4 4226 }
86c581dc 4227 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4228 gen_op_load_sr();
f78fb44e 4229 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4230#endif
79aceca5
FB		 4231}
4232
4233/* mfsrin */
9a64fbe4 4234GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4235{
9a64fbe4 4236#if defined(CONFIG_USER_ONLY)
e1833e1f 4237 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4238#else
76a66253 4239 if (unlikely(!ctx->supervisor)) {
e1833e1f 4240 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4241 return;
9a64fbe4 4242 }
f78fb44e 4243 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4244 gen_op_srli_T1(28);
4245 gen_op_load_sr();
f78fb44e 4246 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4247#endif
79aceca5
FB		 4248}
4249
4250/* mtsr */
e63c59cb 4251GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4252{
9a64fbe4 4253#if defined(CONFIG_USER_ONLY)
e1833e1f 4254 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4255#else
76a66253 4256 if (unlikely(!ctx->supervisor)) {
e1833e1f 4257 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4258 return;
9a64fbe4 4259 }
f78fb44e 4260 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4261 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4262 gen_op_store_sr();
9a64fbe4 4263#endif
79aceca5
FB		 4264}
4265
4266/* mtsrin */
9a64fbe4 4267GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4268{
9a64fbe4 4269#if defined(CONFIG_USER_ONLY)
e1833e1f 4270 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4271#else
76a66253 4272 if (unlikely(!ctx->supervisor)) {
e1833e1f 4273 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4274 return;
9a64fbe4 4275 }
f78fb44e
AJ		 4276 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4277 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4278 gen_op_srli_T1(28);
4279 gen_op_store_sr();
9a64fbe4 4280#endif
79aceca5
FB		 4281}
4282
12de9a39
JM		 4283#if defined(TARGET_PPC64)
4284/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4285/* mfsr */
c7697e1f 4286GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4287{
4288#if defined(CONFIG_USER_ONLY)
4289 GEN_EXCP_PRIVREG(ctx);
4290#else
4291 if (unlikely(!ctx->supervisor)) {
4292 GEN_EXCP_PRIVREG(ctx);
4293 return;
4294 }
86c581dc 4295 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4296 gen_op_load_slb();
f78fb44e 4297 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4298#endif
4299}
4300
4301/* mfsrin */
c7697e1f
JM		 4302GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4303 PPC_SEGMENT_64B)
12de9a39
JM		 4304{
4305#if defined(CONFIG_USER_ONLY)
4306 GEN_EXCP_PRIVREG(ctx);
4307#else
4308 if (unlikely(!ctx->supervisor)) {
4309 GEN_EXCP_PRIVREG(ctx);
4310 return;
4311 }
f78fb44e 4312 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4313 gen_op_srli_T1(28);
4314 gen_op_load_slb();
f78fb44e 4315 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4316#endif
4317}
4318
4319/* mtsr */
c7697e1f 4320GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4321{
4322#if defined(CONFIG_USER_ONLY)
4323 GEN_EXCP_PRIVREG(ctx);
4324#else
4325 if (unlikely(!ctx->supervisor)) {
4326 GEN_EXCP_PRIVREG(ctx);
4327 return;
4328 }
f78fb44e 4329 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4330 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4331 gen_op_store_slb();
4332#endif
4333}
4334
4335/* mtsrin */
c7697e1f
JM		 4336GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4337 PPC_SEGMENT_64B)
12de9a39
JM		 4338{
4339#if defined(CONFIG_USER_ONLY)
4340 GEN_EXCP_PRIVREG(ctx);
4341#else
4342 if (unlikely(!ctx->supervisor)) {
4343 GEN_EXCP_PRIVREG(ctx);
4344 return;
4345 }
f78fb44e
AJ		 4346 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4347 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4348 gen_op_srli_T1(28);
4349 gen_op_store_slb();
4350#endif
4351}
4352#endif /* defined(TARGET_PPC64) */
4353
79aceca5
FB		 4354/*** Lookaside buffer management ***/
4355/* Optional & supervisor only: */
4356/* tlbia */
3fc6c082 4357GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4358{
9a64fbe4 4359#if defined(CONFIG_USER_ONLY)
e1833e1f 4360 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4361#else
76a66253 4362 if (unlikely(!ctx->supervisor)) {
e1833e1f 4363 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4364 return;
9a64fbe4
FB		 4365 }
4366 gen_op_tlbia();
4367#endif
79aceca5
FB		 4368}
4369
4370/* tlbie */
76a66253 4371GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4372{
9a64fbe4 4373#if defined(CONFIG_USER_ONLY)
e1833e1f 4374 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4375#else
76a66253 4376 if (unlikely(!ctx->supervisor)) {
e1833e1f 4377 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4378 return;
9a64fbe4 4379 }
f78fb44e 4380 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4381#if defined(TARGET_PPC64)
4382 if (ctx->sf_mode)
4383 gen_op_tlbie_64();
4384 else
4385#endif
4386 gen_op_tlbie();
9a64fbe4 4387#endif
79aceca5
FB		 4388}
4389
4390/* tlbsync */
76a66253 4391GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4392{
9a64fbe4 4393#if defined(CONFIG_USER_ONLY)
e1833e1f 4394 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4395#else
76a66253 4396 if (unlikely(!ctx->supervisor)) {
e1833e1f 4397 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4398 return;
9a64fbe4
FB		 4399 }
4400 /* This has no effect: it should ensure that all previous
4401 * tlbie have completed
4402 */
e1833e1f 4403 GEN_STOP(ctx);
9a64fbe4 4404#endif
79aceca5
FB		 4405}
4406
426613db
JM		 4407#if defined(TARGET_PPC64)
4408/* slbia */
4409GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4410{
4411#if defined(CONFIG_USER_ONLY)
e1833e1f 4412 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4413#else
4414 if (unlikely(!ctx->supervisor)) {
e1833e1f 4415 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4416 return;
4417 }
4418 gen_op_slbia();
426613db
JM		 4419#endif
4420}
4421
4422/* slbie */
4423GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4424{
4425#if defined(CONFIG_USER_ONLY)
e1833e1f 4426 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4427#else
4428 if (unlikely(!ctx->supervisor)) {
e1833e1f 4429 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4430 return;
4431 }
f78fb44e 4432 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4433 gen_op_slbie();
426613db
JM		 4434#endif
4435}
4436#endif
4437
79aceca5
FB		 4438/*** External control ***/
4439/* Optional: */
9a64fbe4
FB		 4440#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4441#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4442static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4443 GEN_MEM_FUNCS(eciwx),
111bfab3 4444};
7863667f
JM		 4445static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4446 GEN_MEM_FUNCS(ecowx),
111bfab3 4447};
9a64fbe4 4448
111bfab3 4449/* eciwx */
79aceca5
FB		 4450GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4451{
9a64fbe4 4452 /* Should check EAR[E] & alignment ! */
e2be8d8d 4453 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4454 op_eciwx();
f78fb44e 4455 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4456}
4457
4458/* ecowx */
4459GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4460{
4461 /* Should check EAR[E] & alignment ! */
e2be8d8d 4462 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4463 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4464 op_ecowx();
4465}
4466
4467/* PowerPC 601 specific instructions */
4468/* abs - abs. */
4469GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4470{
f78fb44e 4471 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4472 gen_op_POWER_abs();
f78fb44e 4473 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4474 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4475 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4476}
4477
4478/* abso - abso. */
4479GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4480{
f78fb44e 4481 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4482 gen_op_POWER_abso();
f78fb44e 4483 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4484 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4485 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4486}
4487
4488/* clcs */
a750fc0b 4489GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4490{
f78fb44e 4491 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4492 gen_op_POWER_clcs();
c7697e1f 4493 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4494 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4495}
4496
4497/* div - div. */
4498GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4499{
f78fb44e
AJ		 4500 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4501 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4502 gen_op_POWER_div();
f78fb44e 4503 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4504 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4505 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4506}
4507
4508/* divo - divo. */
4509GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4510{
f78fb44e
AJ		 4511 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4512 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4513 gen_op_POWER_divo();
f78fb44e 4514 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4515 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4516 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4517}
4518
4519/* divs - divs. */
4520GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4521{
f78fb44e
AJ		 4522 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4523 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4524 gen_op_POWER_divs();
f78fb44e 4525 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4526 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4527 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4528}
4529
4530/* divso - divso. */
4531GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4532{
f78fb44e
AJ		 4533 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4534 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4535 gen_op_POWER_divso();
f78fb44e 4536 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4537 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4538 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4539}
4540
4541/* doz - doz. */
4542GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4543{
f78fb44e
AJ		 4544 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4545 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4546 gen_op_POWER_doz();
f78fb44e 4547 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4548 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4549 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4550}
4551
4552/* dozo - dozo. */
4553GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4554{
f78fb44e
AJ		 4555 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4556 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4557 gen_op_POWER_dozo();
f78fb44e 4558 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4559 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4560 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4561}
4562
4563/* dozi */
4564GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4565{
f78fb44e 4566 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4567 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4568 gen_op_POWER_doz();
f78fb44e 4569 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4570}
4571
7863667f
JM		 4572/* As lscbx load from memory byte after byte, it's always endian safe.
4573 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4574 */
2857068e 4575#define op_POWER_lscbx(start, ra, rb) \
76a66253 4576(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 4577#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4578#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4579#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4580#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4581#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4582#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4583#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4584#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4585#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4586#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4587#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4588#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4589static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4590 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4591};
76a66253
JM		 4592
4593/* lscbx - lscbx. */
4594GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4595{
4596 int ra = rA(ctx->opcode);
4597 int rb = rB(ctx->opcode);
4598
e2be8d8d 4599 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4600 if (ra == 0) {
4601 ra = rb;
4602 }
4603 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4604 gen_update_nip(ctx, ctx->nip - 4);
3d7b417e
AJ		 4605 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4606 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4607 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
76a66253 4608 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3d7b417e
AJ		 4609 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4610 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253 4611 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4612 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4613}
4614
4615/* maskg - maskg. */
4616GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4617{
f78fb44e
AJ		 4618 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4619 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4620 gen_op_POWER_maskg();
f78fb44e 4621 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4622 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4623 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4624}
4625
4626/* maskir - maskir. */
4627GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4628{
f78fb44e
AJ		 4629 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4630 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4631 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4632 gen_op_POWER_maskir();
f78fb44e 4633 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4634 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4635 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4636}
4637
4638/* mul - mul. */
4639GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4640{
f78fb44e
AJ		 4641 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4642 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4643 gen_op_POWER_mul();
f78fb44e 4644 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4645 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4646 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4647}
4648
4649/* mulo - mulo. */
4650GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4651{
f78fb44e
AJ		 4652 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4653 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4654 gen_op_POWER_mulo();
f78fb44e 4655 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4656 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4657 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4658}
4659
4660/* nabs - nabs. */
4661GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4662{
f78fb44e 4663 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4664 gen_op_POWER_nabs();
f78fb44e 4665 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4666 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4667 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4668}
4669
4670/* nabso - nabso. */
4671GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4672{
f78fb44e 4673 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4674 gen_op_POWER_nabso();
f78fb44e 4675 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4676 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4677 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4678}
4679
4680/* rlmi - rlmi. */
4681GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4682{
4683 uint32_t mb, me;
4684
4685 mb = MB(ctx->opcode);
4686 me = ME(ctx->opcode);
f78fb44e
AJ		 4687 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4688 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4689 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4690 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4691 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4692 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4693 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4694}
4695
4696/* rrib - rrib. */
4697GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4698{
f78fb44e
AJ		 4699 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4700 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4701 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4702 gen_op_POWER_rrib();
f78fb44e 4703 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4704 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4705 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4706}
4707
4708/* sle - sle. */
4709GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4710{
f78fb44e
AJ		 4711 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4712 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4713 gen_op_POWER_sle();
f78fb44e 4714 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4715 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4716 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4717}
4718
4719/* sleq - sleq. */
4720GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4721{
f78fb44e
AJ		 4722 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4723 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4724 gen_op_POWER_sleq();
f78fb44e 4725 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4726 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4727 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4728}
4729
4730/* sliq - sliq. */
4731GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4732{
f78fb44e 4733 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4734 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4735 gen_op_POWER_sle();
f78fb44e 4736 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4737 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4738 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4739}
4740
4741/* slliq - slliq. */
4742GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4743{
f78fb44e 4744 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4745 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4746 gen_op_POWER_sleq();
f78fb44e 4747 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4748 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4749 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4750}
4751
4752/* sllq - sllq. */
4753GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4754{
f78fb44e
AJ		 4755 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4756 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4757 gen_op_POWER_sllq();
f78fb44e 4758 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4759 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4760 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4761}
4762
4763/* slq - slq. */
4764GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4765{
f78fb44e
AJ		 4766 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4767 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4768 gen_op_POWER_slq();
f78fb44e 4769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4770 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4771 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4772}
4773
d9bce9d9 4774/* sraiq - sraiq. */
76a66253
JM		 4775GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4776{
f78fb44e 4777 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4778 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4779 gen_op_POWER_sraq();
f78fb44e 4780 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4781 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4782 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4783}
4784
4785/* sraq - sraq. */
4786GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4787{
f78fb44e
AJ		 4788 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4789 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4790 gen_op_POWER_sraq();
f78fb44e 4791 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4792 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4793 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4794}
4795
4796/* sre - sre. */
4797GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4798{
f78fb44e
AJ		 4799 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4800 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4801 gen_op_POWER_sre();
f78fb44e 4802 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4803 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4804 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4805}
4806
4807/* srea - srea. */
4808GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4809{
f78fb44e
AJ		 4810 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4811 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4812 gen_op_POWER_srea();
f78fb44e 4813 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4814 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4815 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4816}
4817
4818/* sreq */
4819GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4820{
f78fb44e
AJ		 4821 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4822 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4823 gen_op_POWER_sreq();
f78fb44e 4824 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4825 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4826 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4827}
4828
4829/* sriq */
4830GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4831{
f78fb44e 4832 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4833 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4834 gen_op_POWER_srq();
f78fb44e 4835 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4836 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4837 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4838}
4839
4840/* srliq */
4841GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4842{
f78fb44e
AJ		 4843 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4844 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4845 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4846 gen_op_POWER_srlq();
f78fb44e 4847 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4848 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4849 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4850}
4851
4852/* srlq */
4853GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4854{
f78fb44e
AJ		 4855 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4856 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4857 gen_op_POWER_srlq();
f78fb44e 4858 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4859 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4860 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4861}
4862
4863/* srq */
4864GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4865{
f78fb44e
AJ		 4866 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4867 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4868 gen_op_POWER_srq();
f78fb44e 4869 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4870 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4871 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4872}
4873
4874/* PowerPC 602 specific instructions */
4875/* dsa */
4876GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4877{
4878 /* XXX: TODO */
e1833e1f 4879 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4880}
4881
4882/* esa */
4883GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4884{
4885 /* XXX: TODO */
e1833e1f 4886 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4887}
4888
4889/* mfrom */
4890GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4891{
4892#if defined(CONFIG_USER_ONLY)
e1833e1f 4893 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4894#else
4895 if (unlikely(!ctx->supervisor)) {
e1833e1f 4896 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4897 return;
4898 }
f78fb44e 4899 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4900 gen_op_602_mfrom();
f78fb44e 4901 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4902#endif
4903}
4904
4905/* 602 - 603 - G2 TLB management */
4906/* tlbld */
c7697e1f 4907GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4908{
4909#if defined(CONFIG_USER_ONLY)
e1833e1f 4910 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4911#else
4912 if (unlikely(!ctx->supervisor)) {
e1833e1f 4913 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4914 return;
4915 }
f78fb44e 4916 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4917 gen_op_6xx_tlbld();
76a66253
JM		 4918#endif
4919}
4920
4921/* tlbli */
c7697e1f 4922GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4923{
4924#if defined(CONFIG_USER_ONLY)
e1833e1f 4925 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4926#else
4927 if (unlikely(!ctx->supervisor)) {
e1833e1f 4928 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4929 return;
4930 }
f78fb44e 4931 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4932 gen_op_6xx_tlbli();
76a66253
JM		 4933#endif
4934}
4935
7dbe11ac
JM		 4936/* 74xx TLB management */
4937/* tlbld */
c7697e1f 4938GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4939{
4940#if defined(CONFIG_USER_ONLY)
4941 GEN_EXCP_PRIVOPC(ctx);
4942#else
4943 if (unlikely(!ctx->supervisor)) {
4944 GEN_EXCP_PRIVOPC(ctx);
4945 return;
4946 }
f78fb44e 4947 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4948 gen_op_74xx_tlbld();
4949#endif
4950}
4951
4952/* tlbli */
c7697e1f 4953GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4954{
4955#if defined(CONFIG_USER_ONLY)
4956 GEN_EXCP_PRIVOPC(ctx);
4957#else
4958 if (unlikely(!ctx->supervisor)) {
4959 GEN_EXCP_PRIVOPC(ctx);
4960 return;
4961 }
f78fb44e 4962 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4963 gen_op_74xx_tlbli();
4964#endif
4965}
4966
76a66253
JM		 4967/* POWER instructions not in PowerPC 601 */
4968/* clf */
4969GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4970{
4971 /* Cache line flush: implemented as no-op */
4972}
4973
4974/* cli */
4975GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4976{
7f75ffd3 4977 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4978#if defined(CONFIG_USER_ONLY)
e1833e1f 4979 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4980#else
4981 if (unlikely(!ctx->supervisor)) {
e1833e1f 4982 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4983 return;
4984 }
4985#endif
4986}
4987
4988/* dclst */
4989GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4990{
4991 /* Data cache line store: treated as no-op */
4992}
4993
4994GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4995{
4996#if defined(CONFIG_USER_ONLY)
e1833e1f 4997 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4998#else
4999 if (unlikely(!ctx->supervisor)) {
e1833e1f 5000 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5001 return;
5002 }
5003 int ra = rA(ctx->opcode);
5004 int rd = rD(ctx->opcode);
5005
e2be8d8d 5006 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5007 gen_op_POWER_mfsri();
f78fb44e 5008 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 5009 if (ra != 0 && ra != rd)
f78fb44e 5010 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 5011#endif
5012}
5013
5014GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5015{
5016#if defined(CONFIG_USER_ONLY)
e1833e1f 5017 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5018#else
5019 if (unlikely(!ctx->supervisor)) {
e1833e1f 5020 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5021 return;
5022 }
e2be8d8d 5023 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5024 gen_op_POWER_rac();
f78fb44e 5025 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5026#endif
5027}
5028
5029GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5030{
5031#if defined(CONFIG_USER_ONLY)
e1833e1f 5032 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5033#else
5034 if (unlikely(!ctx->supervisor)) {
e1833e1f 5035 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5036 return;
5037 }
5038 gen_op_POWER_rfsvc();
e1833e1f 5039 GEN_SYNC(ctx);
76a66253
JM		 5040#endif
5041}
5042
5043/* svc is not implemented for now */
5044
5045/* POWER2 specific instructions */
5046/* Quad manipulation (load/store two floats at a time) */
7863667f 5047/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 5048#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
5049#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 5050#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
5051#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
5052#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
5053#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
5054#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
5055#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
5056#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
5057#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
5058#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
5059#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
5060#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
5061#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
5062#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
5063#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
5064#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
5065#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
5066static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
5067 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 5068};
7863667f
JM		 5069static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
5070 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 5071};
76a66253
JM		 5072
5073/* lfq */
5074GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5075{
5076 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5077 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5078 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 5079 op_POWER2_lfq();
a5e26afa
AJ		 5080 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5081 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 5082}
5083
5084/* lfqu */
5085GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5086{
5087 int ra = rA(ctx->opcode);
5088
5089 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5090 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5091 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 5092 op_POWER2_lfq();
a5e26afa
AJ		 5093 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5094 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 5095 if (ra != 0)
f78fb44e 5096 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5097}
5098
5099/* lfqux */
5100GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5101{
5102 int ra = rA(ctx->opcode);
5103
5104 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5105 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5106 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5107 op_POWER2_lfq();
a5e26afa
AJ		 5108 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5109 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 5110 if (ra != 0)
f78fb44e 5111 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5112}
5113
5114/* lfqx */
5115GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5116{
5117 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5118 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5119 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5120 op_POWER2_lfq();
a5e26afa
AJ		 5121 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5122 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 5123}
5124
5125/* stfq */
5126GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5127{
5128 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5129 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5130 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 5131 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5132 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5133 op_POWER2_stfq();
5134}
5135
5136/* stfqu */
5137GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5138{
5139 int ra = rA(ctx->opcode);
5140
5141 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5142 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5143 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 5144 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5145 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5146 op_POWER2_stfq();
5147 if (ra != 0)
f78fb44e 5148 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5149}
5150
5151/* stfqux */
5152GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5153{
5154 int ra = rA(ctx->opcode);
5155
5156 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5157 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5158 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 5159 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5160 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5161 op_POWER2_stfq();
5162 if (ra != 0)
f78fb44e 5163 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5164}
5165
5166/* stfqx */
5167GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5168{
5169 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5170 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5171 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 5172 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5173 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5174 op_POWER2_stfq();
5175}
5176
5177/* BookE specific instructions */
2662a059 5178/* XXX: not implemented on 440 ? */
05332d70 5179GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5180{
5181 /* XXX: TODO */
e1833e1f 5182 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5183}
5184
2662a059 5185/* XXX: not implemented on 440 ? */
05332d70 5186GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5187{
5188#if defined(CONFIG_USER_ONLY)
e1833e1f 5189 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5190#else
5191 if (unlikely(!ctx->supervisor)) {
e1833e1f 5192 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5193 return;
5194 }
e2be8d8d 5195 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5196 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5197#if defined(TARGET_PPC64)
5198 if (ctx->sf_mode)
5199 gen_op_tlbie_64();
5200 else
5201#endif
5202 gen_op_tlbie();
76a66253
JM		 5203#endif
5204}
5205
5206/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5207static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5208 int opc2, int opc3,
5209 int ra, int rb, int rt, int Rc)
76a66253 5210{
182608d4
AJ		 5211 TCGv t0, t1;
5212
5213 t0 = tcg_temp_local_new(TCG_TYPE_TL);
5214 t1 = tcg_temp_local_new(TCG_TYPE_TL);
5215
76a66253
JM		 5216 switch (opc3 & 0x0D) {
5217 case 0x05:
5218 /* macchw - macchw. - macchwo - macchwo. */
5219 /* macchws - macchws. - macchwso - macchwso. */
5220 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5221 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5222 /* mulchw - mulchw. */
182608d4
AJ		 5223 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5224 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5225 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5226 break;
5227 case 0x04:
5228 /* macchwu - macchwu. - macchwuo - macchwuo. */
5229 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5230 /* mulchwu - mulchwu. */
182608d4
AJ		 5231 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5232 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5233 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5234 break;
5235 case 0x01:
5236 /* machhw - machhw. - machhwo - machhwo. */
5237 /* machhws - machhws. - machhwso - machhwso. */
5238 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5239 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5240 /* mulhhw - mulhhw. */
182608d4
AJ		 5241 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5242 tcg_gen_ext16s_tl(t0, t0);
5243 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5244 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5245 break;
5246 case 0x00:
5247 /* machhwu - machhwu. - machhwuo - machhwuo. */
5248 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5249 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5250 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5251 tcg_gen_ext16u_tl(t0, t0);
5252 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5253 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5254 break;
5255 case 0x0D:
5256 /* maclhw - maclhw. - maclhwo - maclhwo. */
5257 /* maclhws - maclhws. - maclhwso - maclhwso. */
5258 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5259 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5260 /* mullhw - mullhw. */
182608d4
AJ		 5261 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5262 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5263 break;
5264 case 0x0C:
5265 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5266 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5267 /* mullhwu - mullhwu. */
182608d4
AJ		 5268 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5269 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5270 break;
5271 }
76a66253 5272 if (opc2 & 0x04) {
182608d4
AJ		 5273 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5274 tcg_gen_mul_tl(t1, t0, t1);
5275 if (opc2 & 0x02) {
5276 /* nmultiply-and-accumulate (0x0E) */
5277 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5278 } else {
5279 /* multiply-and-accumulate (0x0C) */
5280 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5281 }
5282
5283 if (opc3 & 0x12) {
5284 /* Check overflow and/or saturate */
5285 int l1 = gen_new_label();
5286
5287 if (opc3 & 0x10) {
5288 /* Start with XER OV disabled, the most likely case */
5289 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5290 }
5291 if (opc3 & 0x01) {
5292 /* Signed */
5293 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5294 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5295 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5296 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5297 if (opc3 & 0x02) {
5298 /* Saturate */
5299 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5300 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5301 }
5302 } else {
5303 /* Unsigned */
5304 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5305 if (opc3 & 0x02) {
5306 /* Saturate */
5307 tcg_gen_movi_tl(t0, UINT32_MAX);
5308 }
5309 }
5310 if (opc3 & 0x10) {
5311 /* Check overflow */
5312 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5313 }
5314 gen_set_label(l1);
5315 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5316 }
5317 } else {
5318 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5319 }
182608d4
AJ		 5320 tcg_temp_free(t0);
5321 tcg_temp_free(t1);
76a66253
JM		 5322 if (unlikely(Rc) != 0) {
5323 /* Update Rc0 */
182608d4 5324 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5325 }
5326}
5327
a750fc0b
JM		 5328#define GEN_MAC_HANDLER(name, opc2, opc3) \
5329GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5330{ \
5331 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5332 rD(ctx->opcode), Rc(ctx->opcode)); \
5333}
5334
5335/* macchw - macchw. */
a750fc0b 5336GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5337/* macchwo - macchwo. */
a750fc0b 5338GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5339/* macchws - macchws. */
a750fc0b 5340GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5341/* macchwso - macchwso. */
a750fc0b 5342GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5343/* macchwsu - macchwsu. */
a750fc0b 5344GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5345/* macchwsuo - macchwsuo. */
a750fc0b 5346GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5347/* macchwu - macchwu. */
a750fc0b 5348GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5349/* macchwuo - macchwuo. */
a750fc0b 5350GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5351/* machhw - machhw. */
a750fc0b 5352GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5353/* machhwo - machhwo. */
a750fc0b 5354GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5355/* machhws - machhws. */
a750fc0b 5356GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5357/* machhwso - machhwso. */
a750fc0b 5358GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5359/* machhwsu - machhwsu. */
a750fc0b 5360GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5361/* machhwsuo - machhwsuo. */
a750fc0b 5362GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5363/* machhwu - machhwu. */
a750fc0b 5364GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5365/* machhwuo - machhwuo. */
a750fc0b 5366GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5367/* maclhw - maclhw. */
a750fc0b 5368GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5369/* maclhwo - maclhwo. */
a750fc0b 5370GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5371/* maclhws - maclhws. */
a750fc0b 5372GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5373/* maclhwso - maclhwso. */
a750fc0b 5374GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5375/* maclhwu - maclhwu. */
a750fc0b 5376GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5377/* maclhwuo - maclhwuo. */
a750fc0b 5378GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5379/* maclhwsu - maclhwsu. */
a750fc0b 5380GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5381/* maclhwsuo - maclhwsuo. */
a750fc0b 5382GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5383/* nmacchw - nmacchw. */
a750fc0b 5384GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5385/* nmacchwo - nmacchwo. */
a750fc0b 5386GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5387/* nmacchws - nmacchws. */
a750fc0b 5388GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5389/* nmacchwso - nmacchwso. */
a750fc0b 5390GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5391/* nmachhw - nmachhw. */
a750fc0b 5392GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5393/* nmachhwo - nmachhwo. */
a750fc0b 5394GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5395/* nmachhws - nmachhws. */
a750fc0b 5396GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5397/* nmachhwso - nmachhwso. */
a750fc0b 5398GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5399/* nmaclhw - nmaclhw. */
a750fc0b 5400GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5401/* nmaclhwo - nmaclhwo. */
a750fc0b 5402GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5403/* nmaclhws - nmaclhws. */
a750fc0b 5404GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5405/* nmaclhwso - nmaclhwso. */
a750fc0b 5406GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5407
5408/* mulchw - mulchw. */
a750fc0b 5409GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5410/* mulchwu - mulchwu. */
a750fc0b 5411GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5412/* mulhhw - mulhhw. */
a750fc0b 5413GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5414/* mulhhwu - mulhhwu. */
a750fc0b 5415GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5416/* mullhw - mullhw. */
a750fc0b 5417GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5418/* mullhwu - mullhwu. */
a750fc0b 5419GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5420
5421/* mfdcr */
05332d70 5422GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5423{
5424#if defined(CONFIG_USER_ONLY)
e1833e1f 5425 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5426#else
5427 uint32_t dcrn = SPR(ctx->opcode);
5428
5429 if (unlikely(!ctx->supervisor)) {
e1833e1f 5430 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5431 return;
5432 }
86c581dc 5433 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5434 gen_op_load_dcr();
f78fb44e 5435 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5436#endif
5437}
5438
5439/* mtdcr */
05332d70 5440GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5441{
5442#if defined(CONFIG_USER_ONLY)
e1833e1f 5443 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5444#else
5445 uint32_t dcrn = SPR(ctx->opcode);
5446
5447 if (unlikely(!ctx->supervisor)) {
e1833e1f 5448 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5449 return;
5450 }
86c581dc 5451 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5452 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5453 gen_op_store_dcr();
5454#endif
5455}
5456
5457/* mfdcrx */
2662a059 5458/* XXX: not implemented on 440 ? */
05332d70 5459GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5460{
5461#if defined(CONFIG_USER_ONLY)
e1833e1f 5462 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5463#else
5464 if (unlikely(!ctx->supervisor)) {
e1833e1f 5465 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5466 return;
5467 }
f78fb44e 5468 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5469 gen_op_load_dcr();
f78fb44e 5470 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5471 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5472#endif
5473}
5474
5475/* mtdcrx */
2662a059 5476/* XXX: not implemented on 440 ? */
05332d70 5477GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5478{
5479#if defined(CONFIG_USER_ONLY)
e1833e1f 5480 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5481#else
5482 if (unlikely(!ctx->supervisor)) {
e1833e1f 5483 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5484 return;
5485 }
f78fb44e
AJ		 5486 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5487 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5488 gen_op_store_dcr();
a750fc0b 5489 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5490#endif
5491}
5492
a750fc0b
JM		 5493/* mfdcrux (PPC 460) : user-mode access to DCR */
5494GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5495{
f78fb44e 5496 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5497 gen_op_load_dcr();
f78fb44e 5498 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5499 /* Note: Rc update flag set leads to undefined state of Rc0 */
5500}
5501
5502/* mtdcrux (PPC 460) : user-mode access to DCR */
5503GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5504{
f78fb44e
AJ		 5505 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5506 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5507 gen_op_store_dcr();
5508 /* Note: Rc update flag set leads to undefined state of Rc0 */
5509}
5510
76a66253
JM		 5511/* dccci */
5512GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5513{
5514#if defined(CONFIG_USER_ONLY)
e1833e1f 5515 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5516#else
5517 if (unlikely(!ctx->supervisor)) {
e1833e1f 5518 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5519 return;
5520 }
5521 /* interpreted as no-op */
5522#endif
5523}
5524
5525/* dcread */
5526GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5527{
5528#if defined(CONFIG_USER_ONLY)
e1833e1f 5529 GEN_EXCP_PRIVOPC(ctx);
76a66253 5530#else
b61f2753 5531 TCGv EA, val;
76a66253 5532 if (unlikely(!ctx->supervisor)) {
e1833e1f 5533 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5534 return;
5535 }
b61f2753
AJ		 5536 EA = tcg_temp_new(TCG_TYPE_TL);
5537 gen_addr_reg_index(EA, ctx);
5538 val = tcg_temp_new(TCG_TYPE_TL);
5539 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5540 tcg_temp_free(val);
5541 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5542 tcg_temp_free(EA);
76a66253
JM		 5543#endif
5544}
5545
5546/* icbt */
c7697e1f 5547GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5548{
5549 /* interpreted as no-op */
5550 /* XXX: specification say this is treated as a load by the MMU
5551 * but does not generate any exception
5552 */
5553}
5554
5555/* iccci */
5556GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5557{
5558#if defined(CONFIG_USER_ONLY)
e1833e1f 5559 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5560#else
5561 if (unlikely(!ctx->supervisor)) {
e1833e1f 5562 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5563 return;
5564 }
5565 /* interpreted as no-op */
5566#endif
5567}
5568
5569/* icread */
5570GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5571{
5572#if defined(CONFIG_USER_ONLY)
e1833e1f 5573 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5574#else
5575 if (unlikely(!ctx->supervisor)) {
e1833e1f 5576 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5577 return;
5578 }
5579 /* interpreted as no-op */
5580#endif
5581}
5582
5583/* rfci (supervisor only) */
c7697e1f 5584GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5585{
5586#if defined(CONFIG_USER_ONLY)
e1833e1f 5587 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5588#else
5589 if (unlikely(!ctx->supervisor)) {
e1833e1f 5590 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5591 return;
5592 }
5593 /* Restore CPU state */
5594 gen_op_40x_rfci();
e1833e1f 5595 GEN_SYNC(ctx);
a42bd6cc
JM		 5596#endif
5597}
5598
5599GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5600{
5601#if defined(CONFIG_USER_ONLY)
e1833e1f 5602 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5603#else
5604 if (unlikely(!ctx->supervisor)) {
e1833e1f 5605 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5606 return;
5607 }
5608 /* Restore CPU state */
5609 gen_op_rfci();
e1833e1f 5610 GEN_SYNC(ctx);
a42bd6cc
JM		 5611#endif
5612}
5613
5614/* BookE specific */
2662a059 5615/* XXX: not implemented on 440 ? */
05332d70 5616GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5617{
5618#if defined(CONFIG_USER_ONLY)
e1833e1f 5619 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5620#else
5621 if (unlikely(!ctx->supervisor)) {
e1833e1f 5622 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5623 return;
5624 }
5625 /* Restore CPU state */
a42bd6cc 5626 gen_op_rfdi();
e1833e1f 5627 GEN_SYNC(ctx);
76a66253
JM		 5628#endif
5629}
5630
2662a059 5631/* XXX: not implemented on 440 ? */
a750fc0b 5632GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5633{
5634#if defined(CONFIG_USER_ONLY)
e1833e1f 5635 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5636#else
5637 if (unlikely(!ctx->supervisor)) {
e1833e1f 5638 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5639 return;
5640 }
5641 /* Restore CPU state */
5642 gen_op_rfmci();
e1833e1f 5643 GEN_SYNC(ctx);
a42bd6cc
JM		 5644#endif
5645}
5eb7995e 5646
d9bce9d9 5647/* TLB management - PowerPC 405 implementation */
76a66253 5648/* tlbre */
c7697e1f 5649GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5650{
5651#if defined(CONFIG_USER_ONLY)
e1833e1f 5652 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5653#else
5654 if (unlikely(!ctx->supervisor)) {
e1833e1f 5655 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5656 return;
5657 }
5658 switch (rB(ctx->opcode)) {
5659 case 0:
f78fb44e 5660 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5661 gen_op_4xx_tlbre_hi();
f78fb44e 5662 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5663 break;
5664 case 1:
f78fb44e 5665 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5666 gen_op_4xx_tlbre_lo();
f78fb44e 5667 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5668 break;
5669 default:
e1833e1f 5670 GEN_EXCP_INVAL(ctx);
76a66253 5671 break;
9a64fbe4 5672 }
76a66253
JM		 5673#endif
5674}
5675
d9bce9d9 5676/* tlbsx - tlbsx. */
c7697e1f 5677GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5678{
5679#if defined(CONFIG_USER_ONLY)
e1833e1f 5680 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5681#else
5682 if (unlikely(!ctx->supervisor)) {
e1833e1f 5683 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5684 return;
5685 }
e2be8d8d 5686 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5687 gen_op_4xx_tlbsx();
76a66253 5688 if (Rc(ctx->opcode))
daf4f96e 5689 gen_op_4xx_tlbsx_check();
f78fb44e 5690 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5691#endif
79aceca5
FB		 5692}
5693
76a66253 5694/* tlbwe */
c7697e1f 5695GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5696{
76a66253 5697#if defined(CONFIG_USER_ONLY)
e1833e1f 5698 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5699#else
5700 if (unlikely(!ctx->supervisor)) {
e1833e1f 5701 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5702 return;
5703 }
5704 switch (rB(ctx->opcode)) {
5705 case 0:
f78fb44e
AJ		 5706 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5707 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5708 gen_op_4xx_tlbwe_hi();
5709 break;
5710 case 1:
f78fb44e
AJ		 5711 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5712 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5713 gen_op_4xx_tlbwe_lo();
5714 break;
5715 default:
e1833e1f 5716 GEN_EXCP_INVAL(ctx);
76a66253 5717 break;
9a64fbe4 5718 }
76a66253
JM		 5719#endif
5720}
5721
a4bb6c3e 5722/* TLB management - PowerPC 440 implementation */
5eb7995e 5723/* tlbre */
c7697e1f 5724GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5725{
5726#if defined(CONFIG_USER_ONLY)
e1833e1f 5727 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5728#else
5729 if (unlikely(!ctx->supervisor)) {
e1833e1f 5730 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5731 return;
5732 }
5733 switch (rB(ctx->opcode)) {
5734 case 0:
5eb7995e 5735 case 1:
5eb7995e 5736 case 2:
f78fb44e 5737 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5738 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5740 break;
5741 default:
e1833e1f 5742 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5743 break;
5744 }
5745#endif
5746}
5747
5748/* tlbsx - tlbsx. */
c7697e1f 5749GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5750{
5751#if defined(CONFIG_USER_ONLY)
e1833e1f 5752 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5753#else
5754 if (unlikely(!ctx->supervisor)) {
e1833e1f 5755 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5756 return;
5757 }
e2be8d8d 5758 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5759 gen_op_440_tlbsx();
5eb7995e 5760 if (Rc(ctx->opcode))
daf4f96e 5761 gen_op_4xx_tlbsx_check();
f78fb44e 5762 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5763#endif
5764}
5765
5766/* tlbwe */
c7697e1f 5767GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5768{
5769#if defined(CONFIG_USER_ONLY)
e1833e1f 5770 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5771#else
5772 if (unlikely(!ctx->supervisor)) {
e1833e1f 5773 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5774 return;
5775 }
5776 switch (rB(ctx->opcode)) {
5777 case 0:
5eb7995e 5778 case 1:
5eb7995e 5779 case 2:
f78fb44e
AJ		 5780 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5781 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5782 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5783 break;
5784 default:
e1833e1f 5785 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5786 break;
5787 }
5788#endif
5789}
5790
76a66253 5791/* wrtee */
05332d70 5792GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5793{
5794#if defined(CONFIG_USER_ONLY)
e1833e1f 5795 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5796#else
5797 if (unlikely(!ctx->supervisor)) {
e1833e1f 5798 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5799 return;
5800 }
f78fb44e 5801 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5802 gen_op_wrte();
dee96f6c
JM		 5803 /* Stop translation to have a chance to raise an exception
5804 * if we just set msr_ee to 1
5805 */
e1833e1f 5806 GEN_STOP(ctx);
76a66253
JM		 5807#endif
5808}
5809
5810/* wrteei */
05332d70 5811GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5812{
5813#if defined(CONFIG_USER_ONLY)
e1833e1f 5814 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5815#else
5816 if (unlikely(!ctx->supervisor)) {
e1833e1f 5817 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5818 return;
5819 }
86c581dc 5820 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5821 gen_op_wrte();
dee96f6c
JM		 5822 /* Stop translation to have a chance to raise an exception
5823 * if we just set msr_ee to 1
5824 */
e1833e1f 5825 GEN_STOP(ctx);
76a66253
JM		 5826#endif
5827}
5828
08e46e54 5829/* PowerPC 440 specific instructions */
76a66253
JM		 5830/* dlmzb */
5831GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5832{
f78fb44e
AJ		 5833 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5834 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5835 gen_op_440_dlmzb();
f78fb44e 5836 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5837 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5838 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5839 if (Rc(ctx->opcode)) {
5840 gen_op_440_dlmzb_update_Rc();
47e4661c 5841 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
76a66253
JM		 5842 }
5843}
5844
5845/* mbar replaces eieio on 440 */
5846GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5847{
5848 /* interpreted as no-op */
5849}
5850
5851/* msync replaces sync on 440 */
0db1b20e 5852GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5853{
5854 /* interpreted as no-op */
5855}
5856
5857/* icbt */
c7697e1f 5858GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5859{
5860 /* interpreted as no-op */
5861 /* XXX: specification say this is treated as a load by the MMU
5862 * but does not generate any exception
5863 */
79aceca5
FB		 5864}
5865
a9d9eb8f
JM		 5866/*** Altivec vector extension ***/
5867/* Altivec registers moves */
a9d9eb8f 5868
1d542695
AJ		 5869static always_inline void gen_load_avr(int t, int reg) {
5870 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5871 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5872}
5873
5874static always_inline void gen_store_avr(int reg, int t) {
5875 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5876 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5877}
a9d9eb8f
JM		 5878
5879#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5880#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5881static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5882 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5883};
5884#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5885static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5886 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5887};
a9d9eb8f
JM		 5888
5889#define GEN_VR_LDX(name, opc2, opc3) \
5890GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5891{ \
5892 if (unlikely(!ctx->altivec_enabled)) { \
5893 GEN_EXCP_NO_VR(ctx); \
5894 return; \
5895 } \
e2be8d8d 5896 gen_addr_reg_index(cpu_T[0], ctx); \
a9d9eb8f 5897 op_vr_ldst(vr_l##name); \
1d542695 5898 gen_store_avr(rD(ctx->opcode), 0); \
a9d9eb8f
JM		 5899}
5900
5901#define GEN_VR_STX(name, opc2, opc3) \
5902GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5903{ \
5904 if (unlikely(!ctx->altivec_enabled)) { \
5905 GEN_EXCP_NO_VR(ctx); \
5906 return; \
5907 } \
e2be8d8d 5908 gen_addr_reg_index(cpu_T[0], ctx); \
1d542695 5909 gen_load_avr(0, rS(ctx->opcode)); \
a9d9eb8f
JM		 5910 op_vr_ldst(vr_st##name); \
5911}
5912
5913OP_VR_LD_TABLE(vx);
5914GEN_VR_LDX(vx, 0x07, 0x03);
5915/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5916#define gen_op_vr_lvxl gen_op_vr_lvx
5917GEN_VR_LDX(vxl, 0x07, 0x0B);
5918
5919OP_VR_ST_TABLE(vx);
5920GEN_VR_STX(vx, 0x07, 0x07);
5921/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5922#define gen_op_vr_stvxl gen_op_vr_stvx
5923GEN_VR_STX(vxl, 0x07, 0x0F);
5924
0487d6a8 5925/*** SPE extension ***/
0487d6a8 5926/* Register moves */
3cd7d1dd 5927
f78fb44e
AJ		 5928static always_inline void gen_load_gpr64(TCGv t, int reg) {
5929#if defined(TARGET_PPC64)
5930 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5931#else
36aa55dc 5932 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5933#endif
f78fb44e 5934}
3cd7d1dd 5935
f78fb44e
AJ		 5936static always_inline void gen_store_gpr64(int reg, TCGv t) {
5937#if defined(TARGET_PPC64)
5938 tcg_gen_mov_i64(cpu_gpr[reg], t);
5939#else
5940 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
19f98ff6 5941 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
f78fb44e
AJ		 5942 tcg_gen_shri_i64(tmp, t, 32);
5943 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5944 tcg_temp_free(tmp);
3cd7d1dd 5945#endif
f78fb44e 5946}
3cd7d1dd 5947
0487d6a8
JM		 5948#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5949GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5950{ \
5951 if (Rc(ctx->opcode)) \
5952 gen_##name1(ctx); \
5953 else \
5954 gen_##name0(ctx); \
5955}
5956
5957/* Handler for undefined SPE opcodes */
b068d6a7 5958static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5959{
e1833e1f 5960 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5961}
5962
5963/* SPE load and stores */
f0aabd1a 5964static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
0487d6a8
JM		 5965{
5966 target_long simm = rB(ctx->opcode);
5967
f0aabd1a
AJ		 5968 if (rA(ctx->opcode) == 0)
5969 tcg_gen_movi_tl(EA, simm << sh);
5970 else if (likely(simm != 0))
5971 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5972 else
5973 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
0487d6a8
JM		 5974}
5975
5976#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5977#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5978static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5979 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5980};
5981#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5982static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5983 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5984};
0487d6a8
JM		 5985
5986#define GEN_SPE_LD(name, sh) \
b068d6a7 5987static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5988{ \
5989 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5990 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5991 return; \
5992 } \
f0aabd1a 5993 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
0487d6a8 5994 op_spe_ldst(spe_l##name); \
f78fb44e 5995 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5996}
5997
5998#define GEN_SPE_LDX(name) \
b068d6a7 5999static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 6000{ \
6001 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6002 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6003 return; \
6004 } \
e2be8d8d 6005 gen_addr_reg_index(cpu_T[0], ctx); \
0487d6a8 6006 op_spe_ldst(spe_l##name); \
f78fb44e 6007 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 6008}
6009
6010#define GEN_SPEOP_LD(name, sh) \
6011OP_SPE_LD_TABLE(name); \
6012GEN_SPE_LD(name, sh); \
6013GEN_SPE_LDX(name)
6014
6015#define GEN_SPE_ST(name, sh) \
b068d6a7 6016static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 6017{ \
6018 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6019 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6020 return; \
6021 } \
f0aabd1a 6022 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
f78fb44e 6023 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 6024 op_spe_ldst(spe_st##name); \
6025}
6026
6027#define GEN_SPE_STX(name) \
b068d6a7 6028static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 6029{ \
6030 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6031 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6032 return; \
6033 } \
e2be8d8d 6034 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 6035 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 6036 op_spe_ldst(spe_st##name); \
6037}
6038
6039#define GEN_SPEOP_ST(name, sh) \
6040OP_SPE_ST_TABLE(name); \
6041GEN_SPE_ST(name, sh); \
6042GEN_SPE_STX(name)
6043
6044#define GEN_SPEOP_LDST(name, sh) \
6045GEN_SPEOP_LD(name, sh); \
6046GEN_SPEOP_ST(name, sh)
6047
6048/* SPE arithmetic and logic */
6049#define GEN_SPEOP_ARITH2(name) \
b068d6a7 6050static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6051{ \
6052 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6053 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6054 return; \
6055 } \
f78fb44e
AJ		 6056 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6057 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 6058 gen_op_##name(); \
f78fb44e 6059 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6060}
6061
cf960816 6062#define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \
3d3a6a0a
AJ		 6063static always_inline void gen_##name (DisasContext *ctx) \
6064{ \
6065 if (unlikely(!ctx->spe_enabled)) { \
6066 GEN_EXCP_NO_AP(ctx); \
6067 return; \
6068 } \
6069 TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \
6070 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
6071 gen_load_gpr64(t0, rA(ctx->opcode)); \
6072 gen_load_gpr64(t1, rB(ctx->opcode)); \
cf960816 6073 tcg_op(t0, t0, t1); \
3d3a6a0a
AJ		 6074 gen_store_gpr64(rD(ctx->opcode), t0); \
6075 tcg_temp_free(t0); \
6076 tcg_temp_free(t1); \
6077}
6078
0487d6a8 6079#define GEN_SPEOP_ARITH1(name) \
b068d6a7 6080static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6081{ \
6082 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6083 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6084 return; \
6085 } \
f78fb44e 6086 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8 6087 gen_op_##name(); \
f78fb44e 6088 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6089}
6090
6091#define GEN_SPEOP_COMP(name) \
b068d6a7 6092static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6093{ \
6094 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6095 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6096 return; \
6097 } \
f78fb44e
AJ		 6098 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6099 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 6100 gen_op_##name(); \
47e4661c 6101 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
0487d6a8
JM		 6102}
6103
6104/* Logical */
cf960816
AJ		 6105GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64);
6106GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64);
6107GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64);
6108GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64);
6109GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64);
6110GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64);
6111GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64);
6112GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64);
0487d6a8
JM		 6113GEN_SPEOP_ARITH2(evsrwu);
6114GEN_SPEOP_ARITH2(evsrws);
6115GEN_SPEOP_ARITH2(evslw);
6116GEN_SPEOP_ARITH2(evrlw);
6117GEN_SPEOP_ARITH2(evmergehi);
6118GEN_SPEOP_ARITH2(evmergelo);
6119GEN_SPEOP_ARITH2(evmergehilo);
6120GEN_SPEOP_ARITH2(evmergelohi);
6121
6122/* Arithmetic */
6123GEN_SPEOP_ARITH2(evaddw);
6124GEN_SPEOP_ARITH2(evsubfw);
6125GEN_SPEOP_ARITH1(evabs);
6126GEN_SPEOP_ARITH1(evneg);
6127GEN_SPEOP_ARITH1(evextsb);
6128GEN_SPEOP_ARITH1(evextsh);
6129GEN_SPEOP_ARITH1(evrndw);
6130GEN_SPEOP_ARITH1(evcntlzw);
6131GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 6132static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 6133{
6134 /* Note: brinc is usable even if SPE is disabled */
f78fb44e
AJ		 6135 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
6136 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6137 gen_op_brinc();
f78fb44e 6138 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
0487d6a8
JM		 6139}
6140
6141#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 6142static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 6143{ \
6144 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6145 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6146 return; \
6147 } \
f78fb44e 6148 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8
JM		 6149 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
6150 gen_op_##name(); \
f78fb44e 6151 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6152}
6153
6154#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 6155static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 6156{ \
6157 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6158 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6159 return; \
6160 } \
f78fb44e 6161 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8
JM		 6162 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6163 gen_op_##name(); \
f78fb44e 6164 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6165}
6166
6167GEN_SPEOP_ARITH_IMM2(evaddw);
6168#define gen_evaddiw gen_evaddwi
6169GEN_SPEOP_ARITH_IMM2(evsubfw);
6170#define gen_evsubifw gen_evsubfwi
6171GEN_SPEOP_LOGIC_IMM2(evslw);
6172GEN_SPEOP_LOGIC_IMM2(evsrwu);
6173#define gen_evsrwis gen_evsrwsi
6174GEN_SPEOP_LOGIC_IMM2(evsrws);
6175#define gen_evsrwiu gen_evsrwui
6176GEN_SPEOP_LOGIC_IMM2(evrlw);
6177
b068d6a7 6178static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 6179{
6180 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
6181
6182 gen_op_splatwi_T0_64(imm);
f78fb44e 6183 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 6184}
6185
b068d6a7 6186static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 6187{
6188 uint32_t imm = rA(ctx->opcode) << 27;
6189
6190 gen_op_splatwi_T0_64(imm);
f78fb44e 6191 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 6192}
6193
6194/* Comparison */
6195GEN_SPEOP_COMP(evcmpgtu);
6196GEN_SPEOP_COMP(evcmpgts);
6197GEN_SPEOP_COMP(evcmpltu);
6198GEN_SPEOP_COMP(evcmplts);
6199GEN_SPEOP_COMP(evcmpeq);
6200
6201GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6202GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6203GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6204GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6205GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6206GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6207GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6208GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6209GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6210GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6211GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6212GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6213GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6214GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6215GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6216GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6217GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6218GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6219GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6220GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6221GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6222GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6223GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6224GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6225GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6226
b068d6a7 6227static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 6228{
6229 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 6230 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 6231 return;
6232 }
47e4661c 6233 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
f78fb44e
AJ		 6234 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
6235 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
0487d6a8 6236 gen_op_evsel();
f78fb44e 6237 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 6238}
6239
c7697e1f 6240GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6241{
6242 gen_evsel(ctx);
6243}
c7697e1f 6244GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6245{
6246 gen_evsel(ctx);
6247}
c7697e1f 6248GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6249{
6250 gen_evsel(ctx);
6251}
c7697e1f 6252GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6253{
6254 gen_evsel(ctx);
6255}
6256
6257/* Load and stores */
0487d6a8
JM		 6258GEN_SPEOP_LDST(dd, 3);
6259GEN_SPEOP_LDST(dw, 3);
6260GEN_SPEOP_LDST(dh, 3);
6261GEN_SPEOP_LDST(whe, 2);
6262GEN_SPEOP_LD(whou, 2);
6263GEN_SPEOP_LD(whos, 2);
6264GEN_SPEOP_ST(who, 2);
6265
0487d6a8 6266#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 6267static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 6268{ \
6269 gen_op_srli32_T1_64(); \
6270 gen_op_spe_stwwo_##suffix(); \
6271}
6272#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 6273static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 6274{ \
6275 gen_op_srli32_T1_64(); \
6276 gen_op_spe_stwwo_le_##suffix(); \
6277}
6278#if defined(TARGET_PPC64)
6279#define GEN_OP_SPE_STWWE(suffix) \
6280_GEN_OP_SPE_STWWE(suffix); \
6281_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 6282static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 6283{ \
6284 gen_op_srli32_T1_64(); \
6285 gen_op_spe_stwwo_64_##suffix(); \
6286} \
b068d6a7 6287static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 6288{ \
6289 gen_op_srli32_T1_64(); \
6290 gen_op_spe_stwwo_le_64_##suffix(); \
6291}
6292#else
6293#define GEN_OP_SPE_STWWE(suffix) \
6294_GEN_OP_SPE_STWWE(suffix); \
6295_GEN_OP_SPE_STWWE_LE(suffix)
6296#endif
6297#if defined(CONFIG_USER_ONLY)
6298GEN_OP_SPE_STWWE(raw);
6299#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 6300GEN_OP_SPE_STWWE(user);
7863667f
JM		 6301GEN_OP_SPE_STWWE(kernel);
6302GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 6303#endif /* defined(CONFIG_USER_ONLY) */
6304GEN_SPEOP_ST(wwe, 2);
6305GEN_SPEOP_ST(wwo, 2);
6306
6307#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 6308static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 6309{ \
6310 gen_op_##op##_##suffix(); \
6311 gen_op_splatw_T1_64(); \
6312}
6313
6314#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 6315static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 6316{ \
6317 gen_op_spe_lh_##suffix(); \
6318 gen_op_sli16_T1_64(); \
6319}
6320
6321#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 6322static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 6323{ \
6324 gen_op_spe_lh_##suffix(); \
6325 gen_op_extsh_T1_64(); \
6326}
6327
6328#if defined(CONFIG_USER_ONLY)
6329GEN_OP_SPE_LHE(raw);
6330GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6331GEN_OP_SPE_LHE(le_raw);
6332GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6333GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6334GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6335GEN_OP_SPE_LHX(raw);
6336GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6337GEN_OP_SPE_LHX(le_raw);
6338GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6339#if defined(TARGET_PPC64)
6340GEN_OP_SPE_LHE(64_raw);
6341GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6342GEN_OP_SPE_LHE(le_64_raw);
6343GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6344GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6345GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6346GEN_OP_SPE_LHX(64_raw);
6347GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6348GEN_OP_SPE_LHX(le_64_raw);
6349GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6350#endif
6351#else
0487d6a8 6352GEN_OP_SPE_LHE(user);
7863667f
JM		 6353GEN_OP_SPE_LHE(kernel);
6354GEN_OP_SPE_LHE(hypv);
0487d6a8 6355GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 6356GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6357GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 6358GEN_OP_SPE_LHE(le_user);
7863667f
JM		 6359GEN_OP_SPE_LHE(le_kernel);
6360GEN_OP_SPE_LHE(le_hypv);
0487d6a8 6361GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 6362GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6363GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 6364GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 6365GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6366GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 6367GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 6368GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6369GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 6370GEN_OP_SPE_LHX(user);
7863667f
JM		 6371GEN_OP_SPE_LHX(kernel);
6372GEN_OP_SPE_LHX(hypv);
0487d6a8 6373GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 6374GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6375GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 6376GEN_OP_SPE_LHX(le_user);
7863667f
JM		 6377GEN_OP_SPE_LHX(le_kernel);
6378GEN_OP_SPE_LHX(le_hypv);
0487d6a8 6379GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 6380GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6381GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 6382#if defined(TARGET_PPC64)
0487d6a8 6383GEN_OP_SPE_LHE(64_user);
7863667f
JM		 6384GEN_OP_SPE_LHE(64_kernel);
6385GEN_OP_SPE_LHE(64_hypv);
0487d6a8 6386GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 6387GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6388GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 6389GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 6390GEN_OP_SPE_LHE(le_64_kernel);
6391GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 6392GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 6393GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6394GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 6395GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 6396GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6397GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 6398GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 6399GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6400GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 6401GEN_OP_SPE_LHX(64_user);
7863667f
JM		 6402GEN_OP_SPE_LHX(64_kernel);
6403GEN_OP_SPE_LHX(64_hypv);
0487d6a8 6404GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 6405GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6406GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 6407GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 6408GEN_OP_SPE_LHX(le_64_kernel);
6409GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 6410GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 6411GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6412GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 6413#endif
6414#endif
6415GEN_SPEOP_LD(hhesplat, 1);
6416GEN_SPEOP_LD(hhousplat, 1);
6417GEN_SPEOP_LD(hhossplat, 1);
6418GEN_SPEOP_LD(wwsplat, 2);
6419GEN_SPEOP_LD(whsplat, 2);
6420
6421GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6422GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6423GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6424GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6425GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6426GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6427GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6428GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6429GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6430GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6431GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6432GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6433GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6434GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6435GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6436GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6437GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6438GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6439
6440/* Multiply and add - TODO */
6441#if 0
6442GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6443GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6444GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6445GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6446GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6447GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6448GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6449GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6450GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6451GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6452GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6453GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6454
6455GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6456GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6457GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6458GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6459GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6460GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6461GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6462GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6463GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6464GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6465GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6466GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6467GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6468GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6469
6470GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6471GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6472GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6473GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6474GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6475GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6476
6477GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6478GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6479GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6480GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6481GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6482GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6483GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6484GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6485GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6486GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6487GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6488GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6489
6490GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6491GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6492GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6493GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6494GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6495
6496GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6497GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6498GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6499GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6500GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6501GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6502GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6503GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6504GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6505GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6506GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6507GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6508
6509GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6510GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6511GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6512GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6513GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6514#endif
6515
6516/*** SPE floating-point extension ***/
6517#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 6518static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6519{ \
f78fb44e 6520 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8 6521 gen_op_##name(); \
f78fb44e 6522 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6523}
6524
6525/* Single precision floating-point vectors operations */
6526/* Arithmetic */
6527GEN_SPEOP_ARITH2(evfsadd);
6528GEN_SPEOP_ARITH2(evfssub);
6529GEN_SPEOP_ARITH2(evfsmul);
6530GEN_SPEOP_ARITH2(evfsdiv);
6531GEN_SPEOP_ARITH1(evfsabs);
6532GEN_SPEOP_ARITH1(evfsnabs);
6533GEN_SPEOP_ARITH1(evfsneg);
6534/* Conversion */
6535GEN_SPEFPUOP_CONV(evfscfui);
6536GEN_SPEFPUOP_CONV(evfscfsi);
6537GEN_SPEFPUOP_CONV(evfscfuf);
6538GEN_SPEFPUOP_CONV(evfscfsf);
6539GEN_SPEFPUOP_CONV(evfsctui);
6540GEN_SPEFPUOP_CONV(evfsctsi);
6541GEN_SPEFPUOP_CONV(evfsctuf);
6542GEN_SPEFPUOP_CONV(evfsctsf);
6543GEN_SPEFPUOP_CONV(evfsctuiz);
6544GEN_SPEFPUOP_CONV(evfsctsiz);
6545/* Comparison */
6546GEN_SPEOP_COMP(evfscmpgt);
6547GEN_SPEOP_COMP(evfscmplt);
6548GEN_SPEOP_COMP(evfscmpeq);
6549GEN_SPEOP_COMP(evfststgt);
6550GEN_SPEOP_COMP(evfststlt);
6551GEN_SPEOP_COMP(evfststeq);
6552
6553/* Opcodes definitions */
6554GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6555GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6556GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6557GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6558GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6559GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6560GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6561GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6562GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6563GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6564GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6565GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6566GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6567GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6568
6569/* Single precision floating-point operations */
6570/* Arithmetic */
6571GEN_SPEOP_ARITH2(efsadd);
6572GEN_SPEOP_ARITH2(efssub);
6573GEN_SPEOP_ARITH2(efsmul);
6574GEN_SPEOP_ARITH2(efsdiv);
6575GEN_SPEOP_ARITH1(efsabs);
6576GEN_SPEOP_ARITH1(efsnabs);
6577GEN_SPEOP_ARITH1(efsneg);
6578/* Conversion */
6579GEN_SPEFPUOP_CONV(efscfui);
6580GEN_SPEFPUOP_CONV(efscfsi);
6581GEN_SPEFPUOP_CONV(efscfuf);
6582GEN_SPEFPUOP_CONV(efscfsf);
6583GEN_SPEFPUOP_CONV(efsctui);
6584GEN_SPEFPUOP_CONV(efsctsi);
6585GEN_SPEFPUOP_CONV(efsctuf);
6586GEN_SPEFPUOP_CONV(efsctsf);
6587GEN_SPEFPUOP_CONV(efsctuiz);
6588GEN_SPEFPUOP_CONV(efsctsiz);
6589GEN_SPEFPUOP_CONV(efscfd);
6590/* Comparison */
6591GEN_SPEOP_COMP(efscmpgt);
6592GEN_SPEOP_COMP(efscmplt);
6593GEN_SPEOP_COMP(efscmpeq);
6594GEN_SPEOP_COMP(efststgt);
6595GEN_SPEOP_COMP(efststlt);
6596GEN_SPEOP_COMP(efststeq);
6597
6598/* Opcodes definitions */
05332d70 6599GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 6600GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6601GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6602GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6603GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6604GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6605GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6606GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6607GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6608GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 6609GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6610GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 6611GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6612GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6613
6614/* Double precision floating-point operations */
6615/* Arithmetic */
6616GEN_SPEOP_ARITH2(efdadd);
6617GEN_SPEOP_ARITH2(efdsub);
6618GEN_SPEOP_ARITH2(efdmul);
6619GEN_SPEOP_ARITH2(efddiv);
6620GEN_SPEOP_ARITH1(efdabs);
6621GEN_SPEOP_ARITH1(efdnabs);
6622GEN_SPEOP_ARITH1(efdneg);
6623/* Conversion */
6624
6625GEN_SPEFPUOP_CONV(efdcfui);
6626GEN_SPEFPUOP_CONV(efdcfsi);
6627GEN_SPEFPUOP_CONV(efdcfuf);
6628GEN_SPEFPUOP_CONV(efdcfsf);
6629GEN_SPEFPUOP_CONV(efdctui);
6630GEN_SPEFPUOP_CONV(efdctsi);
6631GEN_SPEFPUOP_CONV(efdctuf);
6632GEN_SPEFPUOP_CONV(efdctsf);
6633GEN_SPEFPUOP_CONV(efdctuiz);
6634GEN_SPEFPUOP_CONV(efdctsiz);
6635GEN_SPEFPUOP_CONV(efdcfs);
6636GEN_SPEFPUOP_CONV(efdcfuid);
6637GEN_SPEFPUOP_CONV(efdcfsid);
6638GEN_SPEFPUOP_CONV(efdctuidz);
6639GEN_SPEFPUOP_CONV(efdctsidz);
6640/* Comparison */
6641GEN_SPEOP_COMP(efdcmpgt);
6642GEN_SPEOP_COMP(efdcmplt);
6643GEN_SPEOP_COMP(efdcmpeq);
6644GEN_SPEOP_COMP(efdtstgt);
6645GEN_SPEOP_COMP(efdtstlt);
6646GEN_SPEOP_COMP(efdtsteq);
6647
6648/* Opcodes definitions */
6649GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6650GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6651GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6652GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6653GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6654GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6655GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6656GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6657GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6658GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6659GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6660GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6661GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6662GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6663GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6664GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6665
79aceca5
FB		 6666/* End opcode list */
6667GEN_OPCODE_MARK(end);
6668
3fc6c082 6669#include "translate_init.c"
0411a972 6670#include "helper_regs.h"
79aceca5 6671
9a64fbe4 6672/*****************************************************************************/
3fc6c082 6673/* Misc PowerPC helpers */
36081602
JM		 6674void cpu_dump_state (CPUState *env, FILE *f,
6675 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6676 int flags)
79aceca5 6677{
3fc6c082
FB		 6678#define RGPL 4
6679#define RFPL 4
3fc6c082 6680
79aceca5
FB		 6681 int i;
6682
077fc206 6683 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 6684 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 6685 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6686 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 6687#if !defined(NO_TIMER_DUMP)
077fc206 6688 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6689#if !defined(CONFIG_USER_ONLY)
6690 "DECR %08x"
6691#endif
6692 "\n",
077fc206 6693 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6694#if !defined(CONFIG_USER_ONLY)
6695 , cpu_ppc_load_decr(env)
6696#endif
6697 );
077fc206 6698#endif
76a66253 6699 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6700 if ((i & (RGPL - 1)) == 0)
6701 cpu_fprintf(f, "GPR%02d", i);
6b542af7 6702 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 6703 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6704 cpu_fprintf(f, "\n");
76a66253 6705 }
3fc6c082 6706 cpu_fprintf(f, "CR ");
76a66253 6707 for (i = 0; i < 8; i++)
7fe48483
FB		 6708 cpu_fprintf(f, "%01x", env->crf[i]);
6709 cpu_fprintf(f, " [");
76a66253
JM		 6710 for (i = 0; i < 8; i++) {
6711 char a = '-';
6712 if (env->crf[i] & 0x08)
6713 a = 'L';
6714 else if (env->crf[i] & 0x04)
6715 a = 'G';
6716 else if (env->crf[i] & 0x02)
6717 a = 'E';
7fe48483 6718 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6719 }
6b542af7 6720 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 6721 for (i = 0; i < 32; i++) {
6722 if ((i & (RFPL - 1)) == 0)
6723 cpu_fprintf(f, "FPR%02d", i);
26a76461 6724 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6725 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6726 cpu_fprintf(f, "\n");
79aceca5 6727 }
f2e63a42 6728#if !defined(CONFIG_USER_ONLY)
6b542af7 6729 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 6730 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6731#endif
79aceca5 6732
3fc6c082
FB		 6733#undef RGPL
6734#undef RFPL
79aceca5
FB		 6735}
6736
76a66253
JM		 6737void cpu_dump_statistics (CPUState *env, FILE*f,
6738 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6739 int flags)
6740{
6741#if defined(DO_PPC_STATISTICS)
6742 opc_handler_t **t1, **t2, **t3, *handler;
6743 int op1, op2, op3;
6744
6745 t1 = env->opcodes;
6746 for (op1 = 0; op1 < 64; op1++) {
6747 handler = t1[op1];
6748 if (is_indirect_opcode(handler)) {
6749 t2 = ind_table(handler);
6750 for (op2 = 0; op2 < 32; op2++) {
6751 handler = t2[op2];
6752 if (is_indirect_opcode(handler)) {
6753 t3 = ind_table(handler);
6754 for (op3 = 0; op3 < 32; op3++) {
6755 handler = t3[op3];
6756 if (handler->count == 0)
6757 continue;
6758 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6759 "%016llx %lld\n",
6760 op1, op2, op3, op1, (op3 << 5) | op2,
6761 handler->oname,
6762 handler->count, handler->count);
6763 }
6764 } else {
6765 if (handler->count == 0)
6766 continue;
6767 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6768 "%016llx %lld\n",
6769 op1, op2, op1, op2, handler->oname,
6770 handler->count, handler->count);
6771 }
6772 }
6773 } else {
6774 if (handler->count == 0)
6775 continue;
6776 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6777 op1, op1, handler->oname,
6778 handler->count, handler->count);
6779 }
6780 }
6781#endif
6782}
6783
9a64fbe4 6784/*****************************************************************************/
2cfc5f17
TS		 6785static always_inline void gen_intermediate_code_internal (CPUState *env,
6786 TranslationBlock *tb,
6787 int search_pc)
79aceca5 6788{
9fddaa0c 6789 DisasContext ctx, *ctxp = &ctx;
79aceca5 6790 opc_handler_t **table, *handler;
0fa85d43 6791 target_ulong pc_start;
79aceca5 6792 uint16_t *gen_opc_end;
056401ea 6793 int supervisor, little_endian;
79aceca5 6794 int j, lj = -1;
2e70f6ef
PB		 6795 int num_insns;
6796 int max_insns;
79aceca5
FB		 6797
6798 pc_start = tb->pc;
79aceca5 6799 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 6800#if defined(OPTIMIZE_FPRF_UPDATE)
6801 gen_fprf_ptr = gen_fprf_buf;
6802#endif
046d6672 6803 ctx.nip = pc_start;
79aceca5 6804 ctx.tb = tb;
e1833e1f 6805 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6806 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6807 supervisor = env->mmu_idx;
6808#if !defined(CONFIG_USER_ONLY)
2857068e 6809 ctx.supervisor = supervisor;
d9bce9d9 6810#endif
056401ea 6811 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6812#if defined(TARGET_PPC64)
6813 ctx.sf_mode = msr_sf;
056401ea 6814 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6815#else
056401ea 6816 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6817#endif
d63001d1 6818 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6819 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6820 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6821 ctx.spe_enabled = msr_spe;
6822 else
6823 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6824 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6825 ctx.altivec_enabled = msr_vr;
6826 else
6827 ctx.altivec_enabled = 0;
d26bfc9a 6828 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 6829 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 6830 else
8cbcb4fa 6831 ctx.singlestep_enabled = 0;
d26bfc9a 6832 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 6833 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6834 if (unlikely(env->singlestep_enabled))
6835 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 6836#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6837 /* Single step trace mode */
6838 msr_se = 1;
6839#endif
2e70f6ef
PB		 6840 num_insns = 0;
6841 max_insns = tb->cflags & CF_COUNT_MASK;
6842 if (max_insns == 0)
6843 max_insns = CF_COUNT_MASK;
6844
6845 gen_icount_start();
9a64fbe4 6846 /* Set env in case of segfault during code fetch */
e1833e1f 6847 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6848 if (unlikely(env->nb_breakpoints > 0)) {
6849 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6850 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6851 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6852 gen_op_debug();
6853 break;
6854 }
6855 }
6856 }
76a66253 6857 if (unlikely(search_pc)) {
79aceca5
FB		 6858 j = gen_opc_ptr - gen_opc_buf;
6859 if (lj < j) {
6860 lj++;
6861 while (lj < j)
6862 gen_opc_instr_start[lj++] = 0;
046d6672 6863 gen_opc_pc[lj] = ctx.nip;
79aceca5 6864 gen_opc_instr_start[lj] = 1;
2e70f6ef 6865 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 6866 }
6867 }
9fddaa0c
FB		 6868#if defined PPC_DEBUG_DISAS
6869 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6870 fprintf(logfile, "----------------\n");
1b9eb036 6871 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6872 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6873 }
6874#endif
2e70f6ef
PB		 6875 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6876 gen_io_start();
056401ea
JM		 6877 if (unlikely(little_endian)) {
6878 ctx.opcode = bswap32(ldl_code(ctx.nip));
6879 } else {
6880 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6881 }
9fddaa0c
FB		 6882#if defined PPC_DEBUG_DISAS
6883 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6884 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6885 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6886 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6887 }
6888#endif
046d6672 6889 ctx.nip += 4;
3fc6c082 6890 table = env->opcodes;
2e70f6ef 6891 num_insns++;
79aceca5
FB		 6892 handler = table[opc1(ctx.opcode)];
6893 if (is_indirect_opcode(handler)) {
6894 table = ind_table(handler);
6895 handler = table[opc2(ctx.opcode)];
6896 if (is_indirect_opcode(handler)) {
6897 table = ind_table(handler);
6898 handler = table[opc3(ctx.opcode)];
6899 }
6900 }
6901 /* Is opcode *REALLY* valid ? */
76a66253 6902 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6903 if (loglevel != 0) {
76a66253 6904 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 6905 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 6906 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6907 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6908 } else {
6909 printf("invalid/unsupported opcode: "
6b542af7 6910 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 6911 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6912 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6913 }
76a66253
JM		 6914 } else {
6915 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6916 if (loglevel != 0) {
79aceca5 6917 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 6918 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 6919 ctx.opcode & handler->inval, opc1(ctx.opcode),
6920 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6921 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6922 } else {
6923 printf("invalid bits: %08x for opcode: "
6b542af7 6924 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 6925 ctx.opcode & handler->inval, opc1(ctx.opcode),
6926 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6927 ctx.opcode, ctx.nip - 4);
76a66253 6928 }
e1833e1f 6929 GEN_EXCP_INVAL(ctxp);
4b3686fa 6930 break;
79aceca5 6931 }
79aceca5 6932 }
4b3686fa 6933 (*(handler->handler))(&ctx);
76a66253
JM		 6934#if defined(DO_PPC_STATISTICS)
6935 handler->count++;
6936#endif
9a64fbe4 6937 /* Check trace mode exceptions */
8cbcb4fa
AJ		 6938 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6939 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6940 ctx.exception != POWERPC_SYSCALL &&
6941 ctx.exception != POWERPC_EXCP_TRAP &&
6942 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 6943 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 6944 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 6945 (env->singlestep_enabled) ||
6946 num_insns >= max_insns)) {
d26bfc9a
JM		 6947 /* if we reach a page boundary or are single stepping, stop
6948 * generation
6949 */
8dd4983c 6950 break;
76a66253 6951 }
3fc6c082
FB		 6952#if defined (DO_SINGLE_STEP)
6953 break;
6954#endif
6955 }
2e70f6ef
PB		 6956 if (tb->cflags & CF_LAST_IO)
6957 gen_io_end();
e1833e1f 6958 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6959 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6960 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 6961 if (unlikely(env->singlestep_enabled)) {
6962 gen_update_nip(&ctx, ctx.nip);
6963 gen_op_debug();
6964 }
76a66253 6965 /* Generate the return instruction */
57fec1fe 6966 tcg_gen_exit_tb(0);
9a64fbe4 6967 }
2e70f6ef 6968 gen_icount_end(tb, num_insns);
79aceca5 6969 *gen_opc_ptr = INDEX_op_end;
76a66253 6970 if (unlikely(search_pc)) {
9a64fbe4
FB		 6971 j = gen_opc_ptr - gen_opc_buf;
6972 lj++;
6973 while (lj <= j)
6974 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6975 } else {
046d6672 6976 tb->size = ctx.nip - pc_start;
2e70f6ef 6977 tb->icount = num_insns;
9a64fbe4 6978 }
d9bce9d9 6979#if defined(DEBUG_DISAS)
9fddaa0c 6980 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6981 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6982 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6983 }
6984 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6985 int flags;
237c0af0 6986 flags = env->bfd_mach;
056401ea 6987 flags |= little_endian << 16;
0fa85d43 6988 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6989 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6990 fprintf(logfile, "\n");
9fddaa0c 6991 }
79aceca5 6992#endif
79aceca5
FB		 6993}
6994
2cfc5f17 6995void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 6996{
2cfc5f17 6997 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 6998}
6999
2cfc5f17 7000void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7001{
2cfc5f17 7002 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7003}
d2856f1a
AJ		 7004
7005void gen_pc_load(CPUState *env, TranslationBlock *tb,
7006 unsigned long searched_pc, int pc_pos, void *puc)
7007{
7008 int type, c;
7009 /* for PPC, we need to look at the micro operation to get the
7010 * access type */
7011 env->nip = gen_opc_pc[pc_pos];
7012 c = gen_opc_buf[pc_pos];
7013 switch(c) {
7014#if defined(CONFIG_USER_ONLY)
7015#define CASE3(op)\
7016 case INDEX_op_ ## op ## _raw
7017#else
7018#define CASE3(op)\
7019 case INDEX_op_ ## op ## _user:\
7020 case INDEX_op_ ## op ## _kernel:\
7021 case INDEX_op_ ## op ## _hypv
7022#endif
7023
7024 CASE3(stfd):
7025 CASE3(stfs):
7026 CASE3(lfd):
7027 CASE3(lfs):
7028 type = ACCESS_FLOAT;
7029 break;
7030 CASE3(lwarx):
7031 type = ACCESS_RES;
7032 break;
7033 CASE3(stwcx):
7034 type = ACCESS_RES;
7035 break;
7036 CASE3(eciwx):
7037 CASE3(ecowx):
7038 type = ACCESS_EXT;
7039 break;
7040 default:
7041 type = ACCESS_INT;
7042 break;
7043 }
7044 env->access_type = type;
7045}
Qemu copy for testing