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Add new command line option -singlestep for tcg single stepping.
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
79aceca5 19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
0cfe11ea 31#include "host-utils.h"
79aceca5 32
a7812ae4
PB		 33#include "helper.h"
34#define GEN_HELPER 1
35#include "helper.h"
36
8cbcb4fa
AJ		 37#define CPU_SINGLE_STEP 0x1
38#define CPU_BRANCH_STEP 0x2
39#define GDBSTUB_SINGLE_STEP 0x4
40
a750fc0b 41/* Include definitions for instructions classes and implementations flags */
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
79aceca5 44
d12d51d5 45#ifdef PPC_DEBUG_DISAS
93fcfe39 46# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 47#else
48# define LOG_DISAS(...) do { } while (0)
49#endif
a750fc0b
JM		 50/*****************************************************************************/
51/* Code translation helpers */
c53be334 52
f78fb44e 53/* global register indexes */
a7812ae4 54static TCGv_ptr cpu_env;
1d542695 55static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 56#if !defined(TARGET_PPC64)
1d542695 57 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 58#endif
a5e26afa 59 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 60 + 2*(10*6 + 22*7) /* AVRh, AVRl */
61 + 8*5 /* CRF */];
f78fb44e
AJ		 62static TCGv cpu_gpr[32];
63#if !defined(TARGET_PPC64)
64static TCGv cpu_gprh[32];
65#endif
a7812ae4
PB		 66static TCGv_i64 cpu_fpr[32];
67static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
68static TCGv_i32 cpu_crf[8];
bd568f18 69static TCGv cpu_nip;
6527f6ea 70static TCGv cpu_msr;
cfdcd37a
AJ		 71static TCGv cpu_ctr;
72static TCGv cpu_lr;
3d7b417e 73static TCGv cpu_xer;
cf360a32 74static TCGv cpu_reserve;
a7812ae4 75static TCGv_i32 cpu_fpscr;
a7859e89 76static TCGv_i32 cpu_access_type;
f78fb44e 77
2e70f6ef
PB		 78#include "gen-icount.h"
79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
b2437bf2 84 static int done_init = 0;
f78fb44e 85
2e70f6ef
PB		 86 if (done_init)
87 return;
f78fb44e 88
a7812ae4 89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 90
f78fb44e 91 p = cpu_reg_names;
47e4661c
AJ		 92
93 for (i = 0; i < 8; i++) {
94 sprintf(p, "crf%d", i);
a7812ae4
PB		 95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 97 p += 5;
98 }
99
f78fb44e
AJ		 100 for (i = 0; i < 32; i++) {
101 sprintf(p, "r%d", i);
a7812ae4 102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 103 offsetof(CPUState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105#if !defined(TARGET_PPC64)
106 sprintf(p, "r%dH", i);
a7812ae4
PB		 107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 109 p += (i < 10) ? 4 : 5;
110#endif
1d542695 111
a5e26afa 112 sprintf(p, "fp%d", i);
a7812ae4
PB		 113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUState, fpr[i]), p);
ec1ac72d 115 p += (i < 10) ? 4 : 5;
a5e26afa 116
1d542695 117 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 118#ifdef WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
120 offsetof(CPUState, avr[i].u64[0]), p);
121#else
a7812ae4 122 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 123 offsetof(CPUState, avr[i].u64[1]), p);
124#endif
1d542695 125 p += (i < 10) ? 6 : 7;
ec1ac72d 126
1d542695 127 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 128#ifdef WORDS_BIGENDIAN
129 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
130 offsetof(CPUState, avr[i].u64[1]), p);
131#else
a7812ae4 132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 133 offsetof(CPUState, avr[i].u64[0]), p);
134#endif
1d542695 135 p += (i < 10) ? 6 : 7;
f78fb44e 136 }
f10dc08e 137
a7812ae4 138 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 139 offsetof(CPUState, nip), "nip");
140
6527f6ea
AJ		 141 cpu_msr = tcg_global_mem_new(TCG_AREG0,
142 offsetof(CPUState, msr), "msr");
143
a7812ae4 144 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 145 offsetof(CPUState, ctr), "ctr");
146
a7812ae4 147 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 148 offsetof(CPUState, lr), "lr");
149
a7812ae4 150 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 151 offsetof(CPUState, xer), "xer");
152
cf360a32
AJ		 153 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
154 offsetof(CPUState, reserve), "reserve");
155
a7812ae4
PB		 156 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
157 offsetof(CPUState, fpscr), "fpscr");
e1571908 158
a7859e89
AJ		 159 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
160 offsetof(CPUState, access_type), "access_type");
161
f10dc08e 162 /* register helpers */
a7812ae4 163#define GEN_HELPER 2
f10dc08e
AJ		 164#include "helper.h"
165
2e70f6ef
PB		 166 done_init = 1;
167}
168
79aceca5
FB		 169/* internal defines */
170typedef struct DisasContext {
171 struct TranslationBlock *tb;
0fa85d43 172 target_ulong nip;
79aceca5 173 uint32_t opcode;
9a64fbe4 174 uint32_t exception;
3cc62370
FB		 175 /* Routine used to access memory */
176 int mem_idx;
76db3ba4 177 int access_type;
3cc62370 178 /* Translation flags */
76db3ba4 179 int le_mode;
d9bce9d9
JM		 180#if defined(TARGET_PPC64)
181 int sf_mode;
9a64fbe4 182#endif
3cc62370 183 int fpu_enabled;
a9d9eb8f 184 int altivec_enabled;
0487d6a8 185 int spe_enabled;
3fc6c082 186 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 187 int singlestep_enabled;
79aceca5
FB		 188} DisasContext;
189
3fc6c082 190struct opc_handler_t {
79aceca5
FB		 191 /* invalid bits */
192 uint32_t inval;
9a64fbe4 193 /* instruction type */
0487d6a8 194 uint64_t type;
79aceca5
FB		 195 /* handler */
196 void (*handler)(DisasContext *ctx);
a750fc0b 197#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 198 const char *oname;
a750fc0b
JM		 199#endif
200#if defined(DO_PPC_STATISTICS)
76a66253
JM		 201 uint64_t count;
202#endif
3fc6c082 203};
79aceca5 204
7c58044c
JM		 205static always_inline void gen_reset_fpstatus (void)
206{
207#ifdef CONFIG_SOFTFLOAT
a44d2ce1 208 gen_helper_reset_fpstatus();
7c58044c
JM		 209#endif
210}
211
0f2f39c2 212static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 213{
0f2f39c2 214 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 215
7c58044c
JM		 216 if (set_fprf != 0) {
217 /* This case might be optimized later */
0f2f39c2 218 tcg_gen_movi_i32(t0, 1);
af12906f 219 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 220 if (unlikely(set_rc)) {
0f2f39c2 221 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 222 }
af12906f 223 gen_helper_float_check_status();
7c58044c
JM		 224 } else if (unlikely(set_rc)) {
225 /* We always need to compute fpcc */
0f2f39c2 226 tcg_gen_movi_i32(t0, 0);
af12906f 227 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 228 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 229 }
af12906f 230
0f2f39c2 231 tcg_temp_free_i32(t0);
7c58044c
JM		 232}
233
76db3ba4 234static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
a7859e89 235{
76db3ba4
AJ		 236 if (ctx->access_type != access_type) {
237 tcg_gen_movi_i32(cpu_access_type, access_type);
238 ctx->access_type = access_type;
239 }
a7859e89
AJ		 240}
241
b068d6a7 242static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 243{
244#if defined(TARGET_PPC64)
245 if (ctx->sf_mode)
bd568f18 246 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 247 else
248#endif
bd568f18 249 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 250}
251
e06fcd75
AJ		 252static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
253{
254 TCGv_i32 t0, t1;
255 if (ctx->exception == POWERPC_EXCP_NONE) {
256 gen_update_nip(ctx, ctx->nip);
257 }
258 t0 = tcg_const_i32(excp);
259 t1 = tcg_const_i32(error);
260 gen_helper_raise_exception_err(t0, t1);
261 tcg_temp_free_i32(t0);
262 tcg_temp_free_i32(t1);
263 ctx->exception = (excp);
264}
e1833e1f 265
e06fcd75
AJ		 266static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
267{
268 TCGv_i32 t0;
269 if (ctx->exception == POWERPC_EXCP_NONE) {
270 gen_update_nip(ctx, ctx->nip);
271 }
272 t0 = tcg_const_i32(excp);
273 gen_helper_raise_exception(t0);
274 tcg_temp_free_i32(t0);
275 ctx->exception = (excp);
276}
e1833e1f 277
e06fcd75
AJ		 278static always_inline void gen_debug_exception (DisasContext *ctx)
279{
280 TCGv_i32 t0;
5518f3a6
BS		 281
282 if (ctx->exception != POWERPC_EXCP_BRANCH)
283 gen_update_nip(ctx, ctx->nip);
e06fcd75
AJ		 284 t0 = tcg_const_i32(EXCP_DEBUG);
285 gen_helper_raise_exception(t0);
286 tcg_temp_free_i32(t0);
287}
9a64fbe4 288
e06fcd75
AJ		 289static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
290{
291 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
292}
a9d9eb8f 293
f24e5695 294/* Stop translation */
e06fcd75 295static always_inline void gen_stop_exception (DisasContext *ctx)
3fc6c082 296{
d9bce9d9 297 gen_update_nip(ctx, ctx->nip);
e1833e1f 298 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 299}
300
f24e5695 301/* No need to update nip here, as execution flow will change */
e06fcd75 302static always_inline void gen_sync_exception (DisasContext *ctx)
2be0071f 303{
e1833e1f 304 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 305}
306
79aceca5
FB		 307#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
308static void gen_##name (DisasContext *ctx); \
309GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
310static void gen_##name (DisasContext *ctx)
311
c7697e1f
JM		 312#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
313static void gen_##name (DisasContext *ctx); \
314GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
315static void gen_##name (DisasContext *ctx)
316
79aceca5
FB		 317typedef struct opcode_t {
318 unsigned char opc1, opc2, opc3;
1235fc06 319#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 320 unsigned char pad[5];
321#else
322 unsigned char pad[1];
323#endif
79aceca5 324 opc_handler_t handler;
b55266b5 325 const char *oname;
79aceca5
FB		 326} opcode_t;
327
a750fc0b 328/*****************************************************************************/
79aceca5
FB		 329/*** Instruction decoding ***/
330#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 331static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 332{ \
333 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
334}
335
336#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 337static always_inline int32_t name (uint32_t opcode) \
79aceca5 338{ \
18fba28c 339 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 340}
341
342/* Opcode part 1 */
343EXTRACT_HELPER(opc1, 26, 6);
344/* Opcode part 2 */
345EXTRACT_HELPER(opc2, 1, 5);
346/* Opcode part 3 */
347EXTRACT_HELPER(opc3, 6, 5);
348/* Update Cr0 flags */
349EXTRACT_HELPER(Rc, 0, 1);
350/* Destination */
351EXTRACT_HELPER(rD, 21, 5);
352/* Source */
353EXTRACT_HELPER(rS, 21, 5);
354/* First operand */
355EXTRACT_HELPER(rA, 16, 5);
356/* Second operand */
357EXTRACT_HELPER(rB, 11, 5);
358/* Third operand */
359EXTRACT_HELPER(rC, 6, 5);
360/*** Get CRn ***/
361EXTRACT_HELPER(crfD, 23, 3);
362EXTRACT_HELPER(crfS, 18, 3);
363EXTRACT_HELPER(crbD, 21, 5);
364EXTRACT_HELPER(crbA, 16, 5);
365EXTRACT_HELPER(crbB, 11, 5);
366/* SPR / TBL */
3fc6c082 367EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 368static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 369{
370 uint32_t sprn = _SPR(opcode);
371
372 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
373}
79aceca5
FB		 374/*** Get constants ***/
375EXTRACT_HELPER(IMM, 12, 8);
376/* 16 bits signed immediate value */
377EXTRACT_SHELPER(SIMM, 0, 16);
378/* 16 bits unsigned immediate value */
379EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 380/* 5 bits signed immediate value */
381EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 382/* 5 bits signed immediate value */
383EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 384/* Bit count */
385EXTRACT_HELPER(NB, 11, 5);
386/* Shift count */
387EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 388/* Vector shift count */
389EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 390/* Mask start */
391EXTRACT_HELPER(MB, 6, 5);
392/* Mask end */
393EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 394/* Trap operand */
395EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 396
397EXTRACT_HELPER(CRM, 12, 8);
398EXTRACT_HELPER(FM, 17, 8);
399EXTRACT_HELPER(SR, 16, 4);
e4bb997e 400EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 401
79aceca5
FB		 402/*** Jump target decoding ***/
403/* Displacement */
404EXTRACT_SHELPER(d, 0, 16);
405/* Immediate address */
b068d6a7 406static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 407{
408 return (opcode >> 0) & 0x03FFFFFC;
409}
410
b068d6a7 411static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 412{
413 return (opcode >> 0) & 0xFFFC;
414}
415
416EXTRACT_HELPER(BO, 21, 5);
417EXTRACT_HELPER(BI, 16, 5);
418/* Absolute/relative address */
419EXTRACT_HELPER(AA, 1, 1);
420/* Link */
421EXTRACT_HELPER(LK, 0, 1);
422
423/* Create a mask between <start> and <end> bits */
b068d6a7 424static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 425{
76a66253 426 target_ulong ret;
79aceca5 427
76a66253
JM		 428#if defined(TARGET_PPC64)
429 if (likely(start == 0)) {
6f2d8978 430 ret = UINT64_MAX << (63 - end);
76a66253 431 } else if (likely(end == 63)) {
6f2d8978 432 ret = UINT64_MAX >> start;
76a66253
JM		 433 }
434#else
435 if (likely(start == 0)) {
6f2d8978 436 ret = UINT32_MAX << (31 - end);
76a66253 437 } else if (likely(end == 31)) {
6f2d8978 438 ret = UINT32_MAX >> start;
76a66253
JM		 439 }
440#endif
441 else {
442 ret = (((target_ulong)(-1ULL)) >> (start)) ^
443 (((target_ulong)(-1ULL) >> (end)) >> 1);
444 if (unlikely(start > end))
445 return ~ret;
446 }
79aceca5
FB		 447
448 return ret;
449}
450
a750fc0b
JM		 451/*****************************************************************************/
452/* PowerPC Instructions types definitions */
453enum {
1b413d55 454 PPC_NONE = 0x0000000000000000ULL,
12de9a39 455 /* PowerPC base instructions set */
1b413d55
JM		 456 PPC_INSNS_BASE = 0x0000000000000001ULL,
457 /* integer operations instructions */
a750fc0b 458#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 459 /* flow control instructions */
a750fc0b 460#define PPC_FLOW PPC_INSNS_BASE
1b413d55 461 /* virtual memory instructions */
a750fc0b 462#define PPC_MEM PPC_INSNS_BASE
1b413d55 463 /* ld/st with reservation instructions */
a750fc0b 464#define PPC_RES PPC_INSNS_BASE
1b413d55 465 /* spr/msr access instructions */
a750fc0b 466#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 467 /* Deprecated instruction sets */
468 /* Original POWER instruction set */
f610349f 469 PPC_POWER = 0x0000000000000002ULL,
1b413d55 470 /* POWER2 instruction set extension */
f610349f 471 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 472 /* Power RTC support */
f610349f 473 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 474 /* Power-to-PowerPC bridge (601) */
f610349f 475 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 476 /* 64 bits PowerPC instruction set */
f610349f 477 PPC_64B = 0x0000000000000020ULL,
1b413d55 478 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 479 PPC_64BX = 0x0000000000000040ULL,
1b413d55 480 /* 64 bits hypervisor extensions */
f610349f 481 PPC_64H = 0x0000000000000080ULL,
1b413d55 482 /* New wait instruction (PowerPC 2.0x) */
f610349f 483 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 484 /* Time base mftb instruction */
f610349f 485 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 486
487 /* Fixed-point unit extensions */
488 /* PowerPC 602 specific */
f610349f 489 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 490 /* isel instruction */
491 PPC_ISEL = 0x0000000000000800ULL,
492 /* popcntb instruction */
493 PPC_POPCNTB = 0x0000000000001000ULL,
494 /* string load / store */
495 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 496
497 /* Floating-point unit extensions */
498 /* Optional floating point instructions */
499 PPC_FLOAT = 0x0000000000010000ULL,
500 /* New floating-point extensions (PowerPC 2.0x) */
501 PPC_FLOAT_EXT = 0x0000000000020000ULL,
502 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
503 PPC_FLOAT_FRES = 0x0000000000080000ULL,
504 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
505 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
506 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
507 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
508
509 /* Vector/SIMD extensions */
510 /* Altivec support */
511 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 512 /* PowerPC 2.03 SPE extension */
05332d70 513 PPC_SPE = 0x0000000002000000ULL,
40569b7e
AJ		 514 /* PowerPC 2.03 SPE single-precision floating-point extension */
515 PPC_SPE_SINGLE = 0x0000000004000000ULL,
516 /* PowerPC 2.03 SPE double-precision floating-point extension */
517 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1b413d55 518
12de9a39 519 /* Optional memory control instructions */
1b413d55
JM		 520 PPC_MEM_TLBIA = 0x0000000010000000ULL,
521 PPC_MEM_TLBIE = 0x0000000020000000ULL,
522 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
523 /* sync instruction */
524 PPC_MEM_SYNC = 0x0000000080000000ULL,
525 /* eieio instruction */
526 PPC_MEM_EIEIO = 0x0000000100000000ULL,
527
528 /* Cache control instructions */
c8623f2e 529 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 530 /* icbi instruction */
05332d70 531 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 532 /* dcbz instruction with fixed cache line size */
05332d70 533 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 534 /* dcbz instruction with tunable cache line size */
05332d70 535 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 536 /* dcba instruction */
05332d70
JM		 537 PPC_CACHE_DCBA = 0x0000002000000000ULL,
538 /* Freescale cache locking instructions */
539 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 540
541 /* MMU related extensions */
542 /* external control instructions */
05332d70 543 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 544 /* segment register access instructions */
05332d70 545 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 546 /* PowerPC 6xx TLB management instructions */
05332d70 547 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 548 /* PowerPC 74xx TLB management instructions */
05332d70 549 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 550 /* PowerPC 40x TLB management instructions */
05332d70 551 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 552 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 553 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 554 /* SLB management */
05332d70 555 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 556
12de9a39 557 /* Embedded PowerPC dedicated instructions */
05332d70 558 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 559 /* PowerPC 40x exception model */
05332d70 560 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 561 /* PowerPC 405 Mac instructions */
05332d70 562 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 563 /* PowerPC 440 specific instructions */
05332d70 564 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 565 /* BookE (embedded) PowerPC specification */
05332d70
JM		 566 PPC_BOOKE = 0x0010000000000000ULL,
567 /* mfapidi instruction */
568 PPC_MFAPIDI = 0x0020000000000000ULL,
569 /* tlbiva instruction */
570 PPC_TLBIVA = 0x0040000000000000ULL,
571 /* tlbivax instruction */
572 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 573 /* PowerPC 4xx dedicated instructions */
05332d70 574 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 575 /* PowerPC 40x ibct instructions */
05332d70 576 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 577 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 578 PPC_RFMCI = 0x0400000000000000ULL,
579 /* rfdi instruction */
580 PPC_RFDI = 0x0800000000000000ULL,
581 /* DCR accesses */
582 PPC_DCR = 0x1000000000000000ULL,
583 /* DCR extended accesse */
584 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 585 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 586 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 587};
588
589/*****************************************************************************/
590/* PowerPC instructions table */
3fc6c082
FB		 591#if HOST_LONG_BITS == 64
592#define OPC_ALIGN 8
593#else
594#define OPC_ALIGN 4
595#endif
1b039c09 596#if defined(__APPLE__)
d9bce9d9 597#define OPCODES_SECTION \
3fc6c082 598 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 599#else
d9bce9d9 600#define OPCODES_SECTION \
3fc6c082 601 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 602#endif
603
76a66253 604#if defined(DO_PPC_STATISTICS)
79aceca5 605#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
50773fd2 606extern opcode_t opc_##name; \
18fba28c 607OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
18fba28c 611 .pad = { 0, }, \
79aceca5
FB		 612 .handler = { \
613 .inval = invl, \
9a64fbe4 614 .type = _typ, \
79aceca5 615 .handler = &gen_##name, \
76a66253 616 .oname = stringify(name), \
79aceca5 617 }, \
3fc6c082 618 .oname = stringify(name), \
79aceca5 619}
c7697e1f
JM		 620#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
621OPCODES_SECTION opcode_t opc_##name = { \
622 .opc1 = op1, \
623 .opc2 = op2, \
624 .opc3 = op3, \
625 .pad = { 0, }, \
626 .handler = { \
627 .inval = invl, \
628 .type = _typ, \
629 .handler = &gen_##name, \
630 .oname = onam, \
631 }, \
632 .oname = onam, \
633}
76a66253
JM		 634#else
635#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
50773fd2 636extern opcode_t opc_##name; \
76a66253
JM		 637OPCODES_SECTION opcode_t opc_##name = { \
638 .opc1 = op1, \
639 .opc2 = op2, \
640 .opc3 = op3, \
641 .pad = { 0, }, \
642 .handler = { \
643 .inval = invl, \
644 .type = _typ, \
645 .handler = &gen_##name, \
646 }, \
647 .oname = stringify(name), \
648}
c7697e1f 649#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
50773fd2 650extern opcode_t opc_##name; \
c7697e1f
JM		 651OPCODES_SECTION opcode_t opc_##name = { \
652 .opc1 = op1, \
653 .opc2 = op2, \
654 .opc3 = op3, \
655 .pad = { 0, }, \
656 .handler = { \
657 .inval = invl, \
658 .type = _typ, \
659 .handler = &gen_##name, \
660 }, \
661 .oname = onam, \
662}
76a66253 663#endif
79aceca5
FB		 664
665#define GEN_OPCODE_MARK(name) \
50773fd2 666extern opcode_t opc_##name; \
18fba28c 667OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 668 .opc1 = 0xFF, \
669 .opc2 = 0xFF, \
670 .opc3 = 0xFF, \
18fba28c 671 .pad = { 0, }, \
79aceca5
FB		 672 .handler = { \
673 .inval = 0x00000000, \
9a64fbe4 674 .type = 0x00, \
79aceca5
FB		 675 .handler = NULL, \
676 }, \
3fc6c082 677 .oname = stringify(name), \
79aceca5
FB		 678}
679
54cdcae6
AJ		 680/* SPR load/store helpers */
681static always_inline void gen_load_spr(TCGv t, int reg)
682{
683 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
684}
685
686static always_inline void gen_store_spr(int reg, TCGv t)
687{
688 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
689}
690
79aceca5
FB		 691/* Start opcode list */
692GEN_OPCODE_MARK(start);
693
694/* Invalid instruction */
9a64fbe4
FB		 695GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
696{
e06fcd75 697 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 698}
699
79aceca5
FB		 700static opc_handler_t invalid_handler = {
701 .inval = 0xFFFFFFFF,
9a64fbe4 702 .type = PPC_NONE,
79aceca5
FB		 703 .handler = gen_invalid,
704};
705
e1571908
AJ		 706/*** Integer comparison ***/
707
ea363694 708static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 709{
710 int l1, l2, l3;
711
269f3e95
AJ		 712 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
713 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 714 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
715
716 l1 = gen_new_label();
717 l2 = gen_new_label();
718 l3 = gen_new_label();
719 if (s) {
ea363694
AJ		 720 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
721 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 722 } else {
ea363694
AJ		 723 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
724 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 725 }
726 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
727 tcg_gen_br(l3);
728 gen_set_label(l1);
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
730 tcg_gen_br(l3);
731 gen_set_label(l2);
732 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
733 gen_set_label(l3);
734}
735
ea363694 736static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 737{
ea363694
AJ		 738 TCGv t0 = tcg_const_local_tl(arg1);
739 gen_op_cmp(arg0, t0, s, crf);
740 tcg_temp_free(t0);
e1571908
AJ		 741}
742
743#if defined(TARGET_PPC64)
ea363694 744static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 745{
ea363694 746 TCGv t0, t1;
a7812ae4
PB		 747 t0 = tcg_temp_local_new();
748 t1 = tcg_temp_local_new();
e1571908 749 if (s) {
ea363694
AJ		 750 tcg_gen_ext32s_tl(t0, arg0);
751 tcg_gen_ext32s_tl(t1, arg1);
e1571908 752 } else {
ea363694
AJ		 753 tcg_gen_ext32u_tl(t0, arg0);
754 tcg_gen_ext32u_tl(t1, arg1);
e1571908 755 }
ea363694
AJ		 756 gen_op_cmp(t0, t1, s, crf);
757 tcg_temp_free(t1);
758 tcg_temp_free(t0);
e1571908
AJ		 759}
760
ea363694 761static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 762{
ea363694
AJ		 763 TCGv t0 = tcg_const_local_tl(arg1);
764 gen_op_cmp32(arg0, t0, s, crf);
765 tcg_temp_free(t0);
e1571908
AJ		 766}
767#endif
768
769static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
770{
771#if defined(TARGET_PPC64)
772 if (!(ctx->sf_mode))
773 gen_op_cmpi32(reg, 0, 1, 0);
774 else
775#endif
776 gen_op_cmpi(reg, 0, 1, 0);
777}
778
779/* cmp */
780GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
781{
782#if defined(TARGET_PPC64)
783 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
784 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
785 1, crfD(ctx->opcode));
786 else
787#endif
788 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
789 1, crfD(ctx->opcode));
790}
791
792/* cmpi */
793GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
794{
795#if defined(TARGET_PPC64)
796 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
797 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
798 1, crfD(ctx->opcode));
799 else
800#endif
801 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
802 1, crfD(ctx->opcode));
803}
804
805/* cmpl */
806GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
807{
808#if defined(TARGET_PPC64)
809 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
810 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
811 0, crfD(ctx->opcode));
812 else
813#endif
814 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
815 0, crfD(ctx->opcode));
816}
817
818/* cmpli */
819GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
820{
821#if defined(TARGET_PPC64)
822 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
823 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
824 0, crfD(ctx->opcode));
825 else
826#endif
827 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
828 0, crfD(ctx->opcode));
829}
830
831/* isel (PowerPC 2.03 specification) */
832GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
833{
834 int l1, l2;
835 uint32_t bi = rC(ctx->opcode);
836 uint32_t mask;
a7812ae4 837 TCGv_i32 t0;
e1571908
AJ		 838
839 l1 = gen_new_label();
840 l2 = gen_new_label();
841
842 mask = 1 << (3 - (bi & 0x03));
a7812ae4 843 t0 = tcg_temp_new_i32();
fea0c503
AJ		 844 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
845 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 846 if (rA(ctx->opcode) == 0)
847 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
848 else
849 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
850 tcg_gen_br(l2);
851 gen_set_label(l1);
852 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
853 gen_set_label(l2);
a7812ae4 854 tcg_temp_free_i32(t0);
e1571908
AJ		 855}
856
79aceca5 857/*** Integer arithmetic ***/
79aceca5 858
74637406
AJ		 859static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
860{
861 int l1;
862 TCGv t0;
79aceca5 863
74637406
AJ		 864 l1 = gen_new_label();
865 /* Start with XER OV disabled, the most likely case */
866 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 867 t0 = tcg_temp_local_new();
74637406
AJ		 868 tcg_gen_xor_tl(t0, arg0, arg1);
869#if defined(TARGET_PPC64)
870 if (!ctx->sf_mode)
871 tcg_gen_ext32s_tl(t0, t0);
872#endif
873 if (sub)
874 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
875 else
876 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
877 tcg_gen_xor_tl(t0, arg1, arg2);
878#if defined(TARGET_PPC64)
879 if (!ctx->sf_mode)
880 tcg_gen_ext32s_tl(t0, t0);
881#endif
882 if (sub)
883 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
884 else
885 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
886 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
887 gen_set_label(l1);
888 tcg_temp_free(t0);
79aceca5
FB		 889}
890
74637406
AJ		 891static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
892{
893 int l1 = gen_new_label();
d9bce9d9
JM		 894
895#if defined(TARGET_PPC64)
74637406
AJ		 896 if (!(ctx->sf_mode)) {
897 TCGv t0, t1;
a7812ae4
PB		 898 t0 = tcg_temp_new();
899 t1 = tcg_temp_new();
d9bce9d9 900
74637406
AJ		 901 tcg_gen_ext32u_tl(t0, arg1);
902 tcg_gen_ext32u_tl(t1, arg2);
903 if (sub) {
904 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 905 } else {
74637406
AJ		 906 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
907 }
a9730017
AJ		 908 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
909 gen_set_label(l1);
910 tcg_temp_free(t0);
911 tcg_temp_free(t1);
74637406
AJ		 912 } else
913#endif
a9730017
AJ		 914 {
915 if (sub) {
916 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
917 } else {
918 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
919 }
920 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
921 gen_set_label(l1);
74637406 922 }
d9bce9d9
JM		 923}
924
74637406
AJ		 925/* Common add function */
926static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
927 int add_ca, int compute_ca, int compute_ov)
928{
929 TCGv t0, t1;
d9bce9d9 930
74637406 931 if ((!compute_ca && !compute_ov) ||
a7812ae4 932 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 933 t0 = ret;
934 } else {
a7812ae4 935 t0 = tcg_temp_local_new();
74637406 936 }
79aceca5 937
74637406 938 if (add_ca) {
a7812ae4 939 t1 = tcg_temp_local_new();
74637406
AJ		 940 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
941 tcg_gen_shri_tl(t1, t1, XER_CA);
942 }
79aceca5 943
74637406
AJ		 944 if (compute_ca && compute_ov) {
945 /* Start with XER CA and OV disabled, the most likely case */
946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
947 } else if (compute_ca) {
948 /* Start with XER CA disabled, the most likely case */
949 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
950 } else if (compute_ov) {
951 /* Start with XER OV disabled, the most likely case */
952 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
953 }
79aceca5 954
74637406
AJ		 955 tcg_gen_add_tl(t0, arg1, arg2);
956
957 if (compute_ca) {
958 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
959 }
960 if (add_ca) {
961 tcg_gen_add_tl(t0, t0, t1);
962 gen_op_arith_compute_ca(ctx, t0, t1, 0);
963 tcg_temp_free(t1);
964 }
965 if (compute_ov) {
966 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
967 }
968
969 if (unlikely(Rc(ctx->opcode) != 0))
970 gen_set_Rc0(ctx, t0);
971
a7812ae4 972 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 973 tcg_gen_mov_tl(ret, t0);
974 tcg_temp_free(t0);
975 }
39dd32ee 976}
74637406
AJ		 977/* Add functions with two operands */
978#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
979GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
980{ \
981 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
982 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
983 add_ca, compute_ca, compute_ov); \
984}
985/* Add functions with one operand and one immediate */
986#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
987 add_ca, compute_ca, compute_ov) \
988GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
989{ \
990 TCGv t0 = tcg_const_local_tl(const_val); \
991 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
992 cpu_gpr[rA(ctx->opcode)], t0, \
993 add_ca, compute_ca, compute_ov); \
994 tcg_temp_free(t0); \
995}
996
997/* add add. addo addo. */
998GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
999GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1000/* addc addc. addco addco. */
1001GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1002GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1003/* adde adde. addeo addeo. */
1004GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1005GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1006/* addme addme. addmeo addmeo. */
1007GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1008GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1009/* addze addze. addzeo addzeo.*/
1010GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1011GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1012/* addi */
1013GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1014{
74637406
AJ		 1015 target_long simm = SIMM(ctx->opcode);
1016
1017 if (rA(ctx->opcode) == 0) {
1018 /* li case */
1019 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1020 } else {
1021 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1022 }
d9bce9d9 1023}
74637406
AJ		 1024/* addic addic.*/
1025static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1026 int compute_Rc0)
d9bce9d9 1027{
74637406
AJ		 1028 target_long simm = SIMM(ctx->opcode);
1029
1030 /* Start with XER CA and OV disabled, the most likely case */
1031 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1032
1033 if (likely(simm != 0)) {
a7812ae4 1034 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1035 tcg_gen_addi_tl(t0, arg1, simm);
1036 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1037 tcg_gen_mov_tl(ret, t0);
1038 tcg_temp_free(t0);
1039 } else {
1040 tcg_gen_mov_tl(ret, arg1);
1041 }
1042 if (compute_Rc0) {
1043 gen_set_Rc0(ctx, ret);
1044 }
d9bce9d9 1045}
74637406 1046GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1047{
74637406 1048 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1049}
74637406 1050GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1051{
74637406 1052 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1053}
74637406
AJ		 1054/* addis */
1055GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1056{
74637406
AJ		 1057 target_long simm = SIMM(ctx->opcode);
1058
1059 if (rA(ctx->opcode) == 0) {
1060 /* lis case */
1061 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1062 } else {
1063 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1064 }
d9bce9d9 1065}
74637406
AJ		 1066
1067static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1068 int sign, int compute_ov)
d9bce9d9 1069{
2ef1b120
AJ		 1070 int l1 = gen_new_label();
1071 int l2 = gen_new_label();
a7812ae4
PB		 1072 TCGv_i32 t0 = tcg_temp_local_new_i32();
1073 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1074
2ef1b120
AJ		 1075 tcg_gen_trunc_tl_i32(t0, arg1);
1076 tcg_gen_trunc_tl_i32(t1, arg2);
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1078 if (sign) {
2ef1b120
AJ		 1079 int l3 = gen_new_label();
1080 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1081 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1082 gen_set_label(l3);
2ef1b120 1083 tcg_gen_div_i32(t0, t0, t1);
74637406 1084 } else {
2ef1b120 1085 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1086 }
1087 if (compute_ov) {
1088 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1089 }
1090 tcg_gen_br(l2);
1091 gen_set_label(l1);
1092 if (sign) {
2ef1b120 1093 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1094 } else {
1095 tcg_gen_movi_i32(t0, 0);
1096 }
1097 if (compute_ov) {
1098 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1099 }
1100 gen_set_label(l2);
2ef1b120 1101 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1102 tcg_temp_free_i32(t0);
1103 tcg_temp_free_i32(t1);
74637406
AJ		 1104 if (unlikely(Rc(ctx->opcode) != 0))
1105 gen_set_Rc0(ctx, ret);
d9bce9d9 1106}
74637406
AJ		 1107/* Div functions */
1108#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1109GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1110{ \
1111 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1112 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1113 sign, compute_ov); \
1114}
1115/* divwu divwu. divwuo divwuo. */
1116GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1117GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1118/* divw divw. divwo divwo. */
1119GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1120GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1121#if defined(TARGET_PPC64)
2ef1b120
AJ		 1122static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1123 int sign, int compute_ov)
d9bce9d9 1124{
2ef1b120
AJ		 1125 int l1 = gen_new_label();
1126 int l2 = gen_new_label();
74637406
AJ		 1127
1128 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1129 if (sign) {
2ef1b120 1130 int l3 = gen_new_label();
74637406
AJ		 1131 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1132 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1133 gen_set_label(l3);
74637406
AJ		 1134 tcg_gen_div_i64(ret, arg1, arg2);
1135 } else {
1136 tcg_gen_divu_i64(ret, arg1, arg2);
1137 }
1138 if (compute_ov) {
1139 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1140 }
1141 tcg_gen_br(l2);
1142 gen_set_label(l1);
1143 if (sign) {
1144 tcg_gen_sari_i64(ret, arg1, 63);
1145 } else {
1146 tcg_gen_movi_i64(ret, 0);
1147 }
1148 if (compute_ov) {
1149 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1150 }
1151 gen_set_label(l2);
1152 if (unlikely(Rc(ctx->opcode) != 0))
1153 gen_set_Rc0(ctx, ret);
d9bce9d9 1154}
74637406
AJ		 1155#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1156GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1157{ \
2ef1b120
AJ		 1158 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1159 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1160 sign, compute_ov); \
74637406
AJ		 1161}
1162/* divwu divwu. divwuo divwuo. */
1163GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1164GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1165/* divw divw. divwo divwo. */
1166GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1167GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1168#endif
74637406
AJ		 1169
1170/* mulhw mulhw. */
1171GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1172{
a7812ae4 1173 TCGv_i64 t0, t1;
74637406 1174
a7812ae4
PB		 1175 t0 = tcg_temp_new_i64();
1176 t1 = tcg_temp_new_i64();
74637406
AJ		 1177#if defined(TARGET_PPC64)
1178 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1179 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1180 tcg_gen_mul_i64(t0, t0, t1);
1181 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1182#else
1183 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1184 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1185 tcg_gen_mul_i64(t0, t0, t1);
1186 tcg_gen_shri_i64(t0, t0, 32);
1187 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1188#endif
a7812ae4
PB		 1189 tcg_temp_free_i64(t0);
1190 tcg_temp_free_i64(t1);
74637406
AJ		 1191 if (unlikely(Rc(ctx->opcode) != 0))
1192 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1193}
74637406
AJ		 1194/* mulhwu mulhwu. */
1195GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1196{
a7812ae4 1197 TCGv_i64 t0, t1;
74637406 1198
a7812ae4
PB		 1199 t0 = tcg_temp_new_i64();
1200 t1 = tcg_temp_new_i64();
d9bce9d9 1201#if defined(TARGET_PPC64)
74637406
AJ		 1202 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1203 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1204 tcg_gen_mul_i64(t0, t0, t1);
1205 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1206#else
1207 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1208 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1209 tcg_gen_mul_i64(t0, t0, t1);
1210 tcg_gen_shri_i64(t0, t0, 32);
1211 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1212#endif
a7812ae4
PB		 1213 tcg_temp_free_i64(t0);
1214 tcg_temp_free_i64(t1);
74637406
AJ		 1215 if (unlikely(Rc(ctx->opcode) != 0))
1216 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1217}
74637406
AJ		 1218/* mullw mullw. */
1219GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1220{
74637406
AJ		 1221 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1222 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1223 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1224 if (unlikely(Rc(ctx->opcode) != 0))
1225 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1226}
74637406
AJ		 1227/* mullwo mullwo. */
1228GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1229{
74637406 1230 int l1;
a7812ae4 1231 TCGv_i64 t0, t1;
74637406 1232
a7812ae4
PB		 1233 t0 = tcg_temp_new_i64();
1234 t1 = tcg_temp_new_i64();
74637406
AJ		 1235 l1 = gen_new_label();
1236 /* Start with XER OV disabled, the most likely case */
1237 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1238#if defined(TARGET_PPC64)
1239 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1240 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1241#else
1242 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1243 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1244#endif
74637406
AJ		 1245 tcg_gen_mul_i64(t0, t0, t1);
1246#if defined(TARGET_PPC64)
1247 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1248 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1249#else
1250 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1251 tcg_gen_ext32s_i64(t1, t0);
1252 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1253#endif
1254 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1255 gen_set_label(l1);
a7812ae4
PB		 1256 tcg_temp_free_i64(t0);
1257 tcg_temp_free_i64(t1);
74637406
AJ		 1258 if (unlikely(Rc(ctx->opcode) != 0))
1259 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1260}
74637406
AJ		 1261/* mulli */
1262GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1263{
74637406
AJ		 1264 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1265 SIMM(ctx->opcode));
d9bce9d9
JM		 1266}
1267#if defined(TARGET_PPC64)
74637406
AJ		 1268#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1269GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1270{ \
a7812ae4 1271 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1272 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1273 if (unlikely(Rc(ctx->opcode) != 0)) \
1274 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1275}
74637406
AJ		 1276/* mulhd mulhd. */
1277GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1278/* mulhdu mulhdu. */
1279GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1280/* mulld mulld. */
1281GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1282{
74637406
AJ		 1283 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1284 cpu_gpr[rB(ctx->opcode)]);
1285 if (unlikely(Rc(ctx->opcode) != 0))
1286 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1287}
74637406
AJ		 1288/* mulldo mulldo. */
1289GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1290#endif
74637406
AJ		 1291
1292/* neg neg. nego nego. */
ec6469a3 1293static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1294{
ec6469a3
AJ		 1295 int l1 = gen_new_label();
1296 int l2 = gen_new_label();
a7812ae4 1297 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1298#if defined(TARGET_PPC64)
74637406 1299 if (ctx->sf_mode) {
741a7444 1300 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1301 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1302 } else
1303#endif
1304 {
1305 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1306 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1307 }
74637406
AJ		 1308 tcg_gen_neg_tl(ret, arg1);
1309 if (ov_check) {
1310 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1311 }
1312 tcg_gen_br(l2);
1313 gen_set_label(l1);
ec6469a3 1314 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1315 if (ov_check) {
1316 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1317 }
1318 gen_set_label(l2);
ec6469a3 1319 tcg_temp_free(t0);
74637406
AJ		 1320 if (unlikely(Rc(ctx->opcode) != 0))
1321 gen_set_Rc0(ctx, ret);
1322}
1323GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1324{
ec6469a3 1325 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1326}
74637406 1327GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1328{
ec6469a3 1329 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1330}
74637406
AJ		 1331
1332/* Common subf function */
1333static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1334 int add_ca, int compute_ca, int compute_ov)
79aceca5 1335{
74637406 1336 TCGv t0, t1;
76a66253 1337
74637406 1338 if ((!compute_ca && !compute_ov) ||
a7812ae4 1339 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1340 t0 = ret;
e864cabd 1341 } else {
a7812ae4 1342 t0 = tcg_temp_local_new();
d9bce9d9 1343 }
76a66253 1344
74637406 1345 if (add_ca) {
a7812ae4 1346 t1 = tcg_temp_local_new();
74637406
AJ		 1347 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1348 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1349 }
79aceca5 1350
74637406
AJ		 1351 if (compute_ca && compute_ov) {
1352 /* Start with XER CA and OV disabled, the most likely case */
1353 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1354 } else if (compute_ca) {
1355 /* Start with XER CA disabled, the most likely case */
1356 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1357 } else if (compute_ov) {
1358 /* Start with XER OV disabled, the most likely case */
1359 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1360 }
1361
1362 if (add_ca) {
1363 tcg_gen_not_tl(t0, arg1);
1364 tcg_gen_add_tl(t0, t0, arg2);
1365 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1366 tcg_gen_add_tl(t0, t0, t1);
1367 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1368 tcg_temp_free(t1);
79aceca5 1369 } else {
74637406
AJ		 1370 tcg_gen_sub_tl(t0, arg2, arg1);
1371 if (compute_ca) {
1372 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1373 }
1374 }
1375 if (compute_ov) {
1376 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1377 }
1378
1379 if (unlikely(Rc(ctx->opcode) != 0))
1380 gen_set_Rc0(ctx, t0);
1381
a7812ae4 1382 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1383 tcg_gen_mov_tl(ret, t0);
1384 tcg_temp_free(t0);
79aceca5 1385 }
79aceca5 1386}
74637406
AJ		 1387/* Sub functions with Two operands functions */
1388#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1389GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1390{ \
1391 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1392 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1393 add_ca, compute_ca, compute_ov); \
1394}
1395/* Sub functions with one operand and one immediate */
1396#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1397 add_ca, compute_ca, compute_ov) \
1398GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1399{ \
1400 TCGv t0 = tcg_const_local_tl(const_val); \
1401 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1402 cpu_gpr[rA(ctx->opcode)], t0, \
1403 add_ca, compute_ca, compute_ov); \
1404 tcg_temp_free(t0); \
1405}
1406/* subf subf. subfo subfo. */
1407GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1408GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1409/* subfc subfc. subfco subfco. */
1410GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1411GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1412/* subfe subfe. subfeo subfo. */
1413GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1414GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1415/* subfme subfme. subfmeo subfmeo. */
1416GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1417GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1418/* subfze subfze. subfzeo subfzeo.*/
1419GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1420GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1421/* subfic */
1422GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1423{
74637406
AJ		 1424 /* Start with XER CA and OV disabled, the most likely case */
1425 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1426 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1427 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1428 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1429 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1430 tcg_temp_free(t1);
1431 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1432 tcg_temp_free(t0);
79aceca5
FB		 1433}
1434
79aceca5 1435/*** Integer logical ***/
26d67362
AJ		 1436#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1437GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1438{ \
26d67362
AJ		 1439 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1440 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1441 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1442 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1443}
79aceca5 1444
26d67362 1445#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1446GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1447{ \
26d67362 1448 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1449 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1450 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1451}
1452
1453/* and & and. */
26d67362 1454GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1455/* andc & andc. */
26d67362 1456GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1457/* andi. */
c7697e1f 1458GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1459{
26d67362
AJ		 1460 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1462}
1463/* andis. */
c7697e1f 1464GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1465{
26d67362
AJ		 1466 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1467 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1468}
79aceca5 1469/* cntlzw */
26d67362
AJ		 1470GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1471{
a7812ae4 1472 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1473 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1474 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1475}
79aceca5 1476/* eqv & eqv. */
26d67362 1477GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1478/* extsb & extsb. */
26d67362 1479GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1480/* extsh & extsh. */
26d67362 1481GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1482/* nand & nand. */
26d67362 1483GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1484/* nor & nor. */
26d67362 1485GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1486/* or & or. */
9a64fbe4
FB		 1487GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1488{
76a66253
JM		 1489 int rs, ra, rb;
1490
1491 rs = rS(ctx->opcode);
1492 ra = rA(ctx->opcode);
1493 rb = rB(ctx->opcode);
1494 /* Optimisation for mr. ri case */
1495 if (rs != ra || rs != rb) {
26d67362
AJ		 1496 if (rs != rb)
1497 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1498 else
1499 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1500 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1501 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1502 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1503 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1504#if defined(TARGET_PPC64)
1505 } else {
26d67362
AJ		 1506 int prio = 0;
1507
c80f84e3
JM		 1508 switch (rs) {
1509 case 1:
1510 /* Set process priority to low */
26d67362 1511 prio = 2;
c80f84e3
JM		 1512 break;
1513 case 6:
1514 /* Set process priority to medium-low */
26d67362 1515 prio = 3;
c80f84e3
JM		 1516 break;
1517 case 2:
1518 /* Set process priority to normal */
26d67362 1519 prio = 4;
c80f84e3 1520 break;
be147d08
JM		 1521#if !defined(CONFIG_USER_ONLY)
1522 case 31:
76db3ba4 1523 if (ctx->mem_idx > 0) {
be147d08 1524 /* Set process priority to very low */
26d67362 1525 prio = 1;
be147d08
JM		 1526 }
1527 break;
1528 case 5:
76db3ba4 1529 if (ctx->mem_idx > 0) {
be147d08 1530 /* Set process priority to medium-hight */
26d67362 1531 prio = 5;
be147d08
JM		 1532 }
1533 break;
1534 case 3:
76db3ba4 1535 if (ctx->mem_idx > 0) {
be147d08 1536 /* Set process priority to high */
26d67362 1537 prio = 6;
be147d08
JM		 1538 }
1539 break;
be147d08 1540 case 7:
76db3ba4 1541 if (ctx->mem_idx > 1) {
be147d08 1542 /* Set process priority to very high */
26d67362 1543 prio = 7;
be147d08
JM		 1544 }
1545 break;
be147d08 1546#endif
c80f84e3
JM		 1547 default:
1548 /* nop */
1549 break;
1550 }
26d67362 1551 if (prio) {
a7812ae4 1552 TCGv t0 = tcg_temp_new();
54cdcae6 1553 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1554 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1555 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1556 gen_store_spr(SPR_PPR, t0);
ea363694 1557 tcg_temp_free(t0);
26d67362 1558 }
c80f84e3 1559#endif
9a64fbe4 1560 }
9a64fbe4 1561}
79aceca5 1562/* orc & orc. */
26d67362 1563GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1564/* xor & xor. */
9a64fbe4
FB		 1565GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1566{
9a64fbe4 1567 /* Optimisation for "set to zero" case */
26d67362 1568 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1569 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1570 else
1571 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1572 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1573 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1574}
79aceca5
FB		 1575/* ori */
1576GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1577{
76a66253 1578 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1579
9a64fbe4
FB		 1580 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1581 /* NOP */
76a66253 1582 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1583 return;
76a66253 1584 }
26d67362 1585 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1586}
1587/* oris */
1588GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1589{
76a66253 1590 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1591
9a64fbe4
FB		 1592 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1593 /* NOP */
1594 return;
76a66253 1595 }
26d67362 1596 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1597}
1598/* xori */
1599GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1600{
76a66253 1601 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1602
1603 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1604 /* NOP */
1605 return;
1606 }
26d67362 1607 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1608}
79aceca5
FB		 1609/* xoris */
1610GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1611{
76a66253 1612 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1613
1614 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1615 /* NOP */
1616 return;
1617 }
26d67362 1618 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1619}
d9bce9d9 1620/* popcntb : PowerPC 2.03 specification */
05332d70 1621GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1622{
d9bce9d9
JM		 1623#if defined(TARGET_PPC64)
1624 if (ctx->sf_mode)
a7812ae4 1625 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1626 else
1627#endif
a7812ae4 1628 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1629}
1630
1631#if defined(TARGET_PPC64)
1632/* extsw & extsw. */
26d67362 1633GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1634/* cntlzd */
26d67362
AJ		 1635GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1636{
a7812ae4 1637 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1638 if (unlikely(Rc(ctx->opcode) != 0))
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640}
d9bce9d9
JM		 1641#endif
1642
79aceca5
FB		 1643/*** Integer rotate ***/
1644/* rlwimi & rlwimi. */
1645GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1646{
76a66253 1647 uint32_t mb, me, sh;
79aceca5
FB		 1648
1649 mb = MB(ctx->opcode);
1650 me = ME(ctx->opcode);
76a66253 1651 sh = SH(ctx->opcode);
d03ef511
AJ		 1652 if (likely(sh == 0 && mb == 0 && me == 31)) {
1653 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1654 } else {
d03ef511 1655 target_ulong mask;
a7812ae4
PB		 1656 TCGv t1;
1657 TCGv t0 = tcg_temp_new();
54843a58 1658#if defined(TARGET_PPC64)
a7812ae4
PB		 1659 TCGv_i32 t2 = tcg_temp_new_i32();
1660 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1661 tcg_gen_rotli_i32(t2, t2, sh);
1662 tcg_gen_extu_i32_i64(t0, t2);
1663 tcg_temp_free_i32(t2);
54843a58
AJ		 1664#else
1665 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1666#endif
76a66253 1667#if defined(TARGET_PPC64)
d03ef511
AJ		 1668 mb += 32;
1669 me += 32;
76a66253 1670#endif
d03ef511 1671 mask = MASK(mb, me);
a7812ae4 1672 t1 = tcg_temp_new();
d03ef511
AJ		 1673 tcg_gen_andi_tl(t0, t0, mask);
1674 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1675 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1676 tcg_temp_free(t0);
1677 tcg_temp_free(t1);
1678 }
76a66253 1679 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1680 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1681}
1682/* rlwinm & rlwinm. */
1683GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1684{
1685 uint32_t mb, me, sh;
3b46e624 1686
79aceca5
FB		 1687 sh = SH(ctx->opcode);
1688 mb = MB(ctx->opcode);
1689 me = ME(ctx->opcode);
d03ef511
AJ		 1690
1691 if (likely(mb == 0 && me == (31 - sh))) {
1692 if (likely(sh == 0)) {
1693 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1694 } else {
a7812ae4 1695 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1696 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1697 tcg_gen_shli_tl(t0, t0, sh);
1698 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1699 tcg_temp_free(t0);
79aceca5 1700 }
d03ef511 1701 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1702 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1703 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1704 tcg_gen_shri_tl(t0, t0, mb);
1705 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1706 tcg_temp_free(t0);
1707 } else {
a7812ae4 1708 TCGv t0 = tcg_temp_new();
54843a58 1709#if defined(TARGET_PPC64)
a7812ae4 1710 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1711 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1712 tcg_gen_rotli_i32(t1, t1, sh);
1713 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1714 tcg_temp_free_i32(t1);
54843a58
AJ		 1715#else
1716 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1717#endif
76a66253 1718#if defined(TARGET_PPC64)
d03ef511
AJ		 1719 mb += 32;
1720 me += 32;
76a66253 1721#endif
d03ef511
AJ		 1722 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1723 tcg_temp_free(t0);
1724 }
76a66253 1725 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1726 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1727}
1728/* rlwnm & rlwnm. */
1729GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1730{
1731 uint32_t mb, me;
54843a58
AJ		 1732 TCGv t0;
1733#if defined(TARGET_PPC64)
a7812ae4 1734 TCGv_i32 t1, t2;
54843a58 1735#endif
79aceca5
FB		 1736
1737 mb = MB(ctx->opcode);
1738 me = ME(ctx->opcode);
a7812ae4 1739 t0 = tcg_temp_new();
d03ef511 1740 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1741#if defined(TARGET_PPC64)
a7812ae4
PB		 1742 t1 = tcg_temp_new_i32();
1743 t2 = tcg_temp_new_i32();
54843a58
AJ		 1744 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1745 tcg_gen_trunc_i64_i32(t2, t0);
1746 tcg_gen_rotl_i32(t1, t1, t2);
1747 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1748 tcg_temp_free_i32(t1);
1749 tcg_temp_free_i32(t2);
54843a58
AJ		 1750#else
1751 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1752#endif
76a66253
JM		 1753 if (unlikely(mb != 0 || me != 31)) {
1754#if defined(TARGET_PPC64)
1755 mb += 32;
1756 me += 32;
1757#endif
54843a58 1758 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1759 } else {
54843a58 1760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1761 }
54843a58 1762 tcg_temp_free(t0);
76a66253 1763 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1765}
1766
d9bce9d9
JM		 1767#if defined(TARGET_PPC64)
1768#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1769GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1770{ \
1771 gen_##name(ctx, 0); \
1772} \
c7697e1f
JM		 1773GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1774 PPC_64B) \
d9bce9d9
JM		 1775{ \
1776 gen_##name(ctx, 1); \
1777}
1778#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1779GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1780{ \
1781 gen_##name(ctx, 0, 0); \
1782} \
c7697e1f
JM		 1783GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1784 PPC_64B) \
d9bce9d9
JM		 1785{ \
1786 gen_##name(ctx, 0, 1); \
1787} \
c7697e1f
JM		 1788GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1789 PPC_64B) \
d9bce9d9
JM		 1790{ \
1791 gen_##name(ctx, 1, 0); \
1792} \
c7697e1f
JM		 1793GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1794 PPC_64B) \
d9bce9d9
JM		 1795{ \
1796 gen_##name(ctx, 1, 1); \
1797}
51789c41 1798
b068d6a7
JM		 1799static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1800 uint32_t me, uint32_t sh)
51789c41 1801{
d03ef511
AJ		 1802 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1803 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1804 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1805 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1806 } else {
a7812ae4 1807 TCGv t0 = tcg_temp_new();
54843a58 1808 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1809 if (likely(mb == 0 && me == 63)) {
54843a58 1810 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1811 } else {
1812 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1813 }
d03ef511 1814 tcg_temp_free(t0);
51789c41 1815 }
51789c41 1816 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1817 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1818}
d9bce9d9 1819/* rldicl - rldicl. */
b068d6a7 1820static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1821{
51789c41 1822 uint32_t sh, mb;
d9bce9d9 1823
9d53c753
JM		 1824 sh = SH(ctx->opcode) | (shn << 5);
1825 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1826 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1827}
51789c41 1828GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1829/* rldicr - rldicr. */
b068d6a7 1830static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1831{
51789c41 1832 uint32_t sh, me;
d9bce9d9 1833
9d53c753
JM		 1834 sh = SH(ctx->opcode) | (shn << 5);
1835 me = MB(ctx->opcode) | (men << 5);
51789c41 1836 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1837}
51789c41 1838GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1839/* rldic - rldic. */
b068d6a7 1840static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1841{
51789c41 1842 uint32_t sh, mb;
d9bce9d9 1843
9d53c753
JM		 1844 sh = SH(ctx->opcode) | (shn << 5);
1845 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1846 gen_rldinm(ctx, mb, 63 - sh, sh);
1847}
1848GEN_PPC64_R4(rldic, 0x1E, 0x04);
1849
b068d6a7
JM		 1850static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1851 uint32_t me)
51789c41 1852{
54843a58 1853 TCGv t0;
d03ef511
AJ		 1854
1855 mb = MB(ctx->opcode);
1856 me = ME(ctx->opcode);
a7812ae4 1857 t0 = tcg_temp_new();
d03ef511 1858 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1859 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1860 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1861 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1862 } else {
1863 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1864 }
1865 tcg_temp_free(t0);
51789c41 1866 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1867 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1868}
51789c41 1869
d9bce9d9 1870/* rldcl - rldcl. */
b068d6a7 1871static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1872{
51789c41 1873 uint32_t mb;
d9bce9d9 1874
9d53c753 1875 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1876 gen_rldnm(ctx, mb, 63);
d9bce9d9 1877}
36081602 1878GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1879/* rldcr - rldcr. */
b068d6a7 1880static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1881{
51789c41 1882 uint32_t me;
d9bce9d9 1883
9d53c753 1884 me = MB(ctx->opcode) | (men << 5);
51789c41 1885 gen_rldnm(ctx, 0, me);
d9bce9d9 1886}
36081602 1887GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1888/* rldimi - rldimi. */
b068d6a7 1889static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1890{
271a916e 1891 uint32_t sh, mb, me;
d9bce9d9 1892
9d53c753
JM		 1893 sh = SH(ctx->opcode) | (shn << 5);
1894 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1895 me = 63 - sh;
d03ef511
AJ		 1896 if (unlikely(sh == 0 && mb == 0)) {
1897 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1898 } else {
1899 TCGv t0, t1;
1900 target_ulong mask;
1901
a7812ae4 1902 t0 = tcg_temp_new();
54843a58 1903 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1904 t1 = tcg_temp_new();
d03ef511
AJ		 1905 mask = MASK(mb, me);
1906 tcg_gen_andi_tl(t0, t0, mask);
1907 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1908 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1909 tcg_temp_free(t0);
1910 tcg_temp_free(t1);
51789c41 1911 }
51789c41 1912 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1914}
36081602 1915GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1916#endif
1917
79aceca5
FB		 1918/*** Integer shift ***/
1919/* slw & slw. */
26d67362
AJ		 1920GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1921{
fea0c503 1922 TCGv t0;
26d67362
AJ		 1923 int l1, l2;
1924 l1 = gen_new_label();
1925 l2 = gen_new_label();
1926
a7812ae4 1927 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1928 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1929 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1930 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1931 tcg_gen_br(l2);
1932 gen_set_label(l1);
fea0c503 1933 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1934 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1935 gen_set_label(l2);
fea0c503 1936 tcg_temp_free(t0);
26d67362
AJ		 1937 if (unlikely(Rc(ctx->opcode) != 0))
1938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1939}
79aceca5 1940/* sraw & sraw. */
26d67362
AJ		 1941GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1942{
a7812ae4
PB		 1943 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1944 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1945 if (unlikely(Rc(ctx->opcode) != 0))
1946 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1947}
79aceca5
FB		 1948/* srawi & srawi. */
1949GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1950{
26d67362
AJ		 1951 int sh = SH(ctx->opcode);
1952 if (sh != 0) {
1953 int l1, l2;
fea0c503 1954 TCGv t0;
26d67362
AJ		 1955 l1 = gen_new_label();
1956 l2 = gen_new_label();
a7812ae4 1957 t0 = tcg_temp_local_new();
fea0c503
AJ		 1958 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1959 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1960 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1961 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1962 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1963 tcg_gen_br(l2);
1964 gen_set_label(l1);
269f3e95 1965 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1966 gen_set_label(l2);
fea0c503
AJ		 1967 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1968 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1969 tcg_temp_free(t0);
26d67362
AJ		 1970 } else {
1971 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1972 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1973 }
76a66253 1974 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1975 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1976}
1977/* srw & srw. */
26d67362
AJ		 1978GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1979{
fea0c503 1980 TCGv t0, t1;
26d67362
AJ		 1981 int l1, l2;
1982 l1 = gen_new_label();
1983 l2 = gen_new_label();
d9bce9d9 1984
a7812ae4 1985 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1986 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1987 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1988 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1989 tcg_gen_br(l2);
1990 gen_set_label(l1);
a7812ae4 1991 t1 = tcg_temp_new();
fea0c503
AJ		 1992 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1993 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1994 tcg_temp_free(t1);
26d67362 1995 gen_set_label(l2);
fea0c503 1996 tcg_temp_free(t0);
26d67362
AJ		 1997 if (unlikely(Rc(ctx->opcode) != 0))
1998 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1999}
d9bce9d9
JM		 2000#if defined(TARGET_PPC64)
2001/* sld & sld. */
26d67362
AJ		 2002GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2003{
fea0c503 2004 TCGv t0;
26d67362
AJ		 2005 int l1, l2;
2006 l1 = gen_new_label();
2007 l2 = gen_new_label();
2008
a7812ae4 2009 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2010 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2011 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2012 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2013 tcg_gen_br(l2);
2014 gen_set_label(l1);
fea0c503 2015 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2016 gen_set_label(l2);
fea0c503 2017 tcg_temp_free(t0);
26d67362
AJ		 2018 if (unlikely(Rc(ctx->opcode) != 0))
2019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2020}
d9bce9d9 2021/* srad & srad. */
26d67362
AJ		 2022GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2023{
a7812ae4
PB		 2024 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2025 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2026 if (unlikely(Rc(ctx->opcode) != 0))
2027 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2028}
d9bce9d9 2029/* sradi & sradi. */
b068d6a7 2030static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2031{
26d67362 2032 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2033 if (sh != 0) {
26d67362 2034 int l1, l2;
fea0c503 2035 TCGv t0;
26d67362
AJ		 2036 l1 = gen_new_label();
2037 l2 = gen_new_label();
a7812ae4 2038 t0 = tcg_temp_local_new();
26d67362 2039 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2040 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2041 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2042 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2043 tcg_gen_br(l2);
2044 gen_set_label(l1);
269f3e95 2045 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2046 gen_set_label(l2);
a9730017 2047 tcg_temp_free(t0);
26d67362
AJ		 2048 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2049 } else {
2050 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2051 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2052 }
d9bce9d9 2053 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2054 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2055}
c7697e1f 2056GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2057{
2058 gen_sradi(ctx, 0);
2059}
c7697e1f 2060GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2061{
2062 gen_sradi(ctx, 1);
2063}
2064/* srd & srd. */
26d67362
AJ		 2065GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2066{
fea0c503 2067 TCGv t0;
26d67362
AJ		 2068 int l1, l2;
2069 l1 = gen_new_label();
2070 l2 = gen_new_label();
2071
a7812ae4 2072 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2073 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2074 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2075 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2076 tcg_gen_br(l2);
2077 gen_set_label(l1);
fea0c503 2078 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2079 gen_set_label(l2);
fea0c503 2080 tcg_temp_free(t0);
26d67362
AJ		 2081 if (unlikely(Rc(ctx->opcode) != 0))
2082 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2083}
d9bce9d9 2084#endif
79aceca5
FB		 2085
2086/*** Floating-Point arithmetic ***/
7c58044c 2087#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2088GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2089{ \
76a66253 2090 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2091 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2092 return; \
2093 } \
eb44b959
AJ		 2094 /* NIP cannot be restored if the memory exception comes from an helper */ \
2095 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2096 gen_reset_fpstatus(); \
af12906f
AJ		 2097 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2098 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2099 if (isfloat) { \
af12906f 2100 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2101 } \
af12906f
AJ		 2102 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2103 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2104}
2105
7c58044c
JM		 2106#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2107_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2108_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2109
7c58044c
JM		 2110#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2111GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2112{ \
76a66253 2113 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2114 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2115 return; \
2116 } \
eb44b959
AJ		 2117 /* NIP cannot be restored if the memory exception comes from an helper */ \
2118 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2119 gen_reset_fpstatus(); \
af12906f
AJ		 2120 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2121 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2122 if (isfloat) { \
af12906f 2123 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2124 } \
af12906f
AJ		 2125 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2126 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2127}
7c58044c
JM		 2128#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2129_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2130_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2131
7c58044c
JM		 2132#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2133GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2134{ \
76a66253 2135 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2136 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2137 return; \
2138 } \
eb44b959
AJ		 2139 /* NIP cannot be restored if the memory exception comes from an helper */ \
2140 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2141 gen_reset_fpstatus(); \
af12906f
AJ		 2142 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2143 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2144 if (isfloat) { \
af12906f 2145 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2146 } \
af12906f
AJ		 2147 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2148 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2149}
7c58044c
JM		 2150#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2151_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2152_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2153
7c58044c 2154#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2155GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2156{ \
76a66253 2157 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2158 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2159 return; \
2160 } \
eb44b959
AJ		 2161 /* NIP cannot be restored if the memory exception comes from an helper */ \
2162 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2163 gen_reset_fpstatus(); \
af12906f
AJ		 2164 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2165 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2166 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2167}
2168
7c58044c 2169#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2170GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2171{ \
76a66253 2172 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2173 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2174 return; \
2175 } \
eb44b959
AJ		 2176 /* NIP cannot be restored if the memory exception comes from an helper */ \
2177 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2178 gen_reset_fpstatus(); \
af12906f
AJ		 2179 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2180 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2181 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2182}
2183
9a64fbe4 2184/* fadd - fadds */
7c58044c 2185GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2186/* fdiv - fdivs */
7c58044c 2187GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2188/* fmul - fmuls */
7c58044c 2189GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2190
d7e4b87e 2191/* fre */
7c58044c 2192GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2193
a750fc0b 2194/* fres */
7c58044c 2195GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2196
a750fc0b 2197/* frsqrte */
7c58044c
JM		 2198GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2199
2200/* frsqrtes */
af12906f 2201GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2202{
af12906f 2203 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2204 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2205 return;
2206 }
eb44b959
AJ		 2207 /* NIP cannot be restored if the memory exception comes from an helper */
2208 gen_update_nip(ctx, ctx->nip - 4);
af12906f
AJ		 2209 gen_reset_fpstatus();
2210 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2211 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2212 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2213}
79aceca5 2214
a750fc0b 2215/* fsel */
7c58044c 2216_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2217/* fsub - fsubs */
7c58044c 2218GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2219/* Optional: */
2220/* fsqrt */
a750fc0b 2221GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2222{
76a66253 2223 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2224 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2225 return;
2226 }
eb44b959
AJ		 2227 /* NIP cannot be restored if the memory exception comes from an helper */
2228 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2229 gen_reset_fpstatus();
af12906f
AJ		 2230 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2231 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2232}
79aceca5 2233
a750fc0b 2234GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2235{
76a66253 2236 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2237 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2238 return;
2239 }
eb44b959
AJ		 2240 /* NIP cannot be restored if the memory exception comes from an helper */
2241 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2242 gen_reset_fpstatus();
af12906f
AJ		 2243 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2244 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2245 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2246}
2247
2248/*** Floating-Point multiply-and-add ***/
4ecc3190 2249/* fmadd - fmadds */
7c58044c 2250GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2251/* fmsub - fmsubs */
7c58044c 2252GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2253/* fnmadd - fnmadds */
7c58044c 2254GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2255/* fnmsub - fnmsubs */
7c58044c 2256GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2257
2258/*** Floating-Point round & convert ***/
2259/* fctiw */
7c58044c 2260GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2261/* fctiwz */
7c58044c 2262GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2263/* frsp */
7c58044c 2264GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2265#if defined(TARGET_PPC64)
2266/* fcfid */
7c58044c 2267GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2268/* fctid */
7c58044c 2269GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2270/* fctidz */
7c58044c 2271GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2272#endif
79aceca5 2273
d7e4b87e 2274/* frin */
7c58044c 2275GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2276/* friz */
7c58044c 2277GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2278/* frip */
7c58044c 2279GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2280/* frim */
7c58044c 2281GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2282
79aceca5
FB		 2283/*** Floating-Point compare ***/
2284/* fcmpo */
76a66253 2285GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2286{
330c483b 2287 TCGv_i32 crf;
76a66253 2288 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2289 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2290 return;
2291 }
eb44b959
AJ		 2292 /* NIP cannot be restored if the memory exception comes from an helper */
2293 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2294 gen_reset_fpstatus();
9a819377
AJ		 2295 crf = tcg_const_i32(crfD(ctx->opcode));
2296 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2297 tcg_temp_free_i32(crf);
af12906f 2298 gen_helper_float_check_status();
79aceca5
FB		 2299}
2300
2301/* fcmpu */
76a66253 2302GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2303{
330c483b 2304 TCGv_i32 crf;
76a66253 2305 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2306 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2307 return;
2308 }
eb44b959
AJ		 2309 /* NIP cannot be restored if the memory exception comes from an helper */
2310 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2311 gen_reset_fpstatus();
9a819377
AJ		 2312 crf = tcg_const_i32(crfD(ctx->opcode));
2313 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2314 tcg_temp_free_i32(crf);
af12906f 2315 gen_helper_float_check_status();
79aceca5
FB		 2316}
2317
9a64fbe4
FB		 2318/*** Floating-point move ***/
2319/* fabs */
7c58044c
JM		 2320/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2321GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2322
2323/* fmr - fmr. */
7c58044c 2324/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2325GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2326{
76a66253 2327 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2328 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2329 return;
2330 }
af12906f
AJ		 2331 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2332 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2333}
2334
2335/* fnabs */
7c58044c
JM		 2336/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2337GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2338/* fneg */
7c58044c
JM		 2339/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2340GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2341
79aceca5
FB		 2342/*** Floating-Point status & ctrl register ***/
2343/* mcrfs */
2344GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2345{
7c58044c
JM		 2346 int bfa;
2347
76a66253 2348 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2349 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2350 return;
2351 }
7c58044c 2352 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2353 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2354 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2355 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2356}
2357
2358/* mffs */
2359GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2360{
76a66253 2361 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2362 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2363 return;
2364 }
7c58044c 2365 gen_reset_fpstatus();
af12906f
AJ		 2366 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2367 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2368}
2369
2370/* mtfsb0 */
2371GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2372{
fb0eaffc 2373 uint8_t crb;
3b46e624 2374
76a66253 2375 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2376 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2377 return;
2378 }
6e35d524 2379 crb = 31 - crbD(ctx->opcode);
7c58044c 2380 gen_reset_fpstatus();
6e35d524 2381 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2382 TCGv_i32 t0;
2383 /* NIP cannot be restored if the memory exception comes from an helper */
2384 gen_update_nip(ctx, ctx->nip - 4);
2385 t0 = tcg_const_i32(crb);
6e35d524
AJ		 2386 gen_helper_fpscr_clrbit(t0);
2387 tcg_temp_free_i32(t0);
2388 }
7c58044c 2389 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2390 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2391 }
79aceca5
FB		 2392}
2393
2394/* mtfsb1 */
2395GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2396{
fb0eaffc 2397 uint8_t crb;
3b46e624 2398
76a66253 2399 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2400 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2401 return;
2402 }
6e35d524 2403 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2404 gen_reset_fpstatus();
2405 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2406 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2407 TCGv_i32 t0;
2408 /* NIP cannot be restored if the memory exception comes from an helper */
2409 gen_update_nip(ctx, ctx->nip - 4);
2410 t0 = tcg_const_i32(crb);
af12906f 2411 gen_helper_fpscr_setbit(t0);
0f2f39c2 2412 tcg_temp_free_i32(t0);
af12906f 2413 }
7c58044c 2414 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2415 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2416 }
2417 /* We can raise a differed exception */
af12906f 2418 gen_helper_float_check_status();
79aceca5
FB		 2419}
2420
2421/* mtfsf */
4911012d 2422GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT)
79aceca5 2423{
0f2f39c2 2424 TCGv_i32 t0;
4911012d 2425 int L = ctx->opcode & 0x02000000;
af12906f 2426
76a66253 2427 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2428 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2429 return;
2430 }
eb44b959
AJ		 2431 /* NIP cannot be restored if the memory exception comes from an helper */
2432 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2433 gen_reset_fpstatus();
4911012d
BS		 2434 if (L)
2435 t0 = tcg_const_i32(0xff);
2436 else
2437 t0 = tcg_const_i32(FM(ctx->opcode));
af12906f 2438 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2439 tcg_temp_free_i32(t0);
7c58044c 2440 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2441 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2442 }
2443 /* We can raise a differed exception */
af12906f 2444 gen_helper_float_check_status();
79aceca5
FB		 2445}
2446
2447/* mtfsfi */
2448GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2449{
7c58044c 2450 int bf, sh;
0f2f39c2
AJ		 2451 TCGv_i64 t0;
2452 TCGv_i32 t1;
7c58044c 2453
76a66253 2454 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2455 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2456 return;
2457 }
7c58044c
JM		 2458 bf = crbD(ctx->opcode) >> 2;
2459 sh = 7 - bf;
eb44b959
AJ		 2460 /* NIP cannot be restored if the memory exception comes from an helper */
2461 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2462 gen_reset_fpstatus();
0f2f39c2 2463 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2464 t1 = tcg_const_i32(1 << sh);
2465 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2466 tcg_temp_free_i64(t0);
2467 tcg_temp_free_i32(t1);
7c58044c 2468 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2469 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2470 }
2471 /* We can raise a differed exception */
af12906f 2472 gen_helper_float_check_status();
79aceca5
FB		 2473}
2474
76a66253
JM		 2475/*** Addressing modes ***/
2476/* Register indirect with immediate index : EA = (rA|0) + SIMM */
76db3ba4 2477static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
76a66253
JM		 2478{
2479 target_long simm = SIMM(ctx->opcode);
2480
be147d08 2481 simm &= ~maskl;
76db3ba4
AJ		 2482 if (rA(ctx->opcode) == 0) {
2483#if defined(TARGET_PPC64)
2484 if (!ctx->sf_mode) {
2485 tcg_gen_movi_tl(EA, (uint32_t)simm);
2486 } else
2487#endif
e2be8d8d 2488 tcg_gen_movi_tl(EA, simm);
76db3ba4 2489 } else if (likely(simm != 0)) {
e2be8d8d 2490 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
76db3ba4
AJ		 2491#if defined(TARGET_PPC64)
2492 if (!ctx->sf_mode) {
2493 tcg_gen_ext32u_tl(EA, EA);
2494 }
2495#endif
2496 } else {
2497#if defined(TARGET_PPC64)
2498 if (!ctx->sf_mode) {
2499 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2500 } else
2501#endif
e2be8d8d 2502 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2503 }
76a66253
JM		 2504}
2505
76db3ba4 2506static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
76a66253 2507{
76db3ba4
AJ		 2508 if (rA(ctx->opcode) == 0) {
2509#if defined(TARGET_PPC64)
2510 if (!ctx->sf_mode) {
2511 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2512 } else
2513#endif
e2be8d8d 2514 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
76db3ba4 2515 } else {
e2be8d8d 2516 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76db3ba4
AJ		 2517#if defined(TARGET_PPC64)
2518 if (!ctx->sf_mode) {
2519 tcg_gen_ext32u_tl(EA, EA);
2520 }
2521#endif
2522 }
76a66253
JM		 2523}
2524
76db3ba4 2525static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
76a66253 2526{
76db3ba4 2527 if (rA(ctx->opcode) == 0) {
e2be8d8d 2528 tcg_gen_movi_tl(EA, 0);
76db3ba4
AJ		 2529 } else {
2530#if defined(TARGET_PPC64)
2531 if (!ctx->sf_mode) {
2532 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2533 } else
2534#endif
2535 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2536 }
2537}
2538
2539static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2540{
2541 tcg_gen_addi_tl(ret, arg1, val);
2542#if defined(TARGET_PPC64)
2543 if (!ctx->sf_mode) {
2544 tcg_gen_ext32u_tl(ret, ret);
2545 }
2546#endif
76a66253
JM		 2547}
2548
cf360a32
AJ		 2549static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2550{
2551 int l1 = gen_new_label();
2552 TCGv t0 = tcg_temp_new();
2553 TCGv_i32 t1, t2;
2554 /* NIP cannot be restored if the memory exception comes from an helper */
2555 gen_update_nip(ctx, ctx->nip - 4);
2556 tcg_gen_andi_tl(t0, EA, mask);
2557 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2558 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2559 t2 = tcg_const_i32(0);
2560 gen_helper_raise_exception_err(t1, t2);
2561 tcg_temp_free_i32(t1);
2562 tcg_temp_free_i32(t2);
2563 gen_set_label(l1);
2564 tcg_temp_free(t0);
2565}
2566
7863667f 2567/*** Integer load ***/
76db3ba4
AJ		 2568static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2569{
2570 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2571}
2572
2573static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2574{
2575 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2576}
2577
2578static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2579{
2580 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2581 if (unlikely(ctx->le_mode)) {
fa3966a3 2582 tcg_gen_bswap16_tl(arg1, arg1);
76db3ba4 2583 }
b61f2753
AJ		 2584}
2585
76db3ba4 2586static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2587{
76db3ba4 2588 if (unlikely(ctx->le_mode)) {
76db3ba4 2589 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
fa3966a3 2590 tcg_gen_bswap16_tl(arg1, arg1);
76db3ba4 2591 tcg_gen_ext16s_tl(arg1, arg1);
76db3ba4
AJ		 2592 } else {
2593 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2594 }
b61f2753
AJ		 2595}
2596
76db3ba4 2597static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2598{
76db3ba4
AJ		 2599 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2600 if (unlikely(ctx->le_mode)) {
fa3966a3 2601 tcg_gen_bswap32_tl(arg1, arg1);
76db3ba4 2602 }
b61f2753
AJ		 2603}
2604
76db3ba4
AJ		 2605#if defined(TARGET_PPC64)
2606static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2607{
a457e7ee 2608 if (unlikely(ctx->le_mode)) {
76db3ba4 2609 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
fa3966a3
AJ		 2610 tcg_gen_bswap32_tl(arg1, arg1);
2611 tcg_gen_ext32s_tl(arg1, arg1);
b61f2753 2612 } else
76db3ba4 2613 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753 2614}
76db3ba4 2615#endif
b61f2753 2616
76db3ba4 2617static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2618{
76db3ba4
AJ		 2619 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2620 if (unlikely(ctx->le_mode)) {
66896cb8 2621 tcg_gen_bswap64_i64(arg1, arg1);
76db3ba4 2622 }
b61f2753
AJ		 2623}
2624
76db3ba4 2625static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2626{
76db3ba4 2627 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2628}
2629
76db3ba4 2630static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2631{
76db3ba4 2632 if (unlikely(ctx->le_mode)) {
76db3ba4
AJ		 2633 TCGv t0 = tcg_temp_new();
2634 tcg_gen_ext16u_tl(t0, arg1);
fa3966a3 2635 tcg_gen_bswap16_tl(t0, t0);
76db3ba4
AJ		 2636 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2637 tcg_temp_free(t0);
76db3ba4
AJ		 2638 } else {
2639 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2640 }
b61f2753
AJ		 2641}
2642
76db3ba4 2643static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2644{
76db3ba4 2645 if (unlikely(ctx->le_mode)) {
fa3966a3
AJ		 2646 TCGv t0 = tcg_temp_new();
2647 tcg_gen_ext32u_tl(t0, arg1);
2648 tcg_gen_bswap32_tl(t0, t0);
76db3ba4
AJ		 2649 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2650 tcg_temp_free(t0);
76db3ba4
AJ		 2651 } else {
2652 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2653 }
b61f2753
AJ		 2654}
2655
76db3ba4 2656static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2657{
76db3ba4 2658 if (unlikely(ctx->le_mode)) {
a7812ae4 2659 TCGv_i64 t0 = tcg_temp_new_i64();
66896cb8 2660 tcg_gen_bswap64_i64(t0, arg1);
76db3ba4 2661 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2662 tcg_temp_free_i64(t0);
b61f2753 2663 } else
76db3ba4 2664 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2665}
2666
0c8aacd4
AJ		 2667#define GEN_LD(name, ldop, opc, type) \
2668GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2669{ \
76db3ba4
AJ		 2670 TCGv EA; \
2671 gen_set_access_type(ctx, ACCESS_INT); \
2672 EA = tcg_temp_new(); \
2673 gen_addr_imm_index(ctx, EA, 0); \
2674 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2675 tcg_temp_free(EA); \
79aceca5
FB		 2676}
2677
0c8aacd4
AJ		 2678#define GEN_LDU(name, ldop, opc, type) \
2679GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2680{ \
b61f2753 2681 TCGv EA; \
76a66253
JM		 2682 if (unlikely(rA(ctx->opcode) == 0 || \
2683 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2684 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2685 return; \
9a64fbe4 2686 } \
76db3ba4 2687 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2688 EA = tcg_temp_new(); \
9d53c753 2689 if (type == PPC_64B) \
76db3ba4 2690 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2691 else \
76db3ba4
AJ		 2692 gen_addr_imm_index(ctx, EA, 0); \
2693 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2694 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2695 tcg_temp_free(EA); \
79aceca5
FB		 2696}
2697
0c8aacd4
AJ		 2698#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2699GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2700{ \
b61f2753 2701 TCGv EA; \
76a66253
JM		 2702 if (unlikely(rA(ctx->opcode) == 0 || \
2703 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2704 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2705 return; \
9a64fbe4 2706 } \
76db3ba4 2707 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2708 EA = tcg_temp_new(); \
76db3ba4
AJ		 2709 gen_addr_reg_index(ctx, EA); \
2710 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2711 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2712 tcg_temp_free(EA); \
79aceca5
FB		 2713}
2714
0c8aacd4
AJ		 2715#define GEN_LDX(name, ldop, opc2, opc3, type) \
2716GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2717{ \
76db3ba4
AJ		 2718 TCGv EA; \
2719 gen_set_access_type(ctx, ACCESS_INT); \
2720 EA = tcg_temp_new(); \
2721 gen_addr_reg_index(ctx, EA); \
2722 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2723 tcg_temp_free(EA); \
79aceca5
FB		 2724}
2725
0c8aacd4
AJ		 2726#define GEN_LDS(name, ldop, op, type) \
2727GEN_LD(name, ldop, op | 0x20, type); \
2728GEN_LDU(name, ldop, op | 0x21, type); \
2729GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2730GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2731
2732/* lbz lbzu lbzux lbzx */
0c8aacd4 2733GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2734/* lha lhau lhaux lhax */
0c8aacd4 2735GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2736/* lhz lhzu lhzux lhzx */
0c8aacd4 2737GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2738/* lwz lwzu lwzux lwzx */
0c8aacd4 2739GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2740#if defined(TARGET_PPC64)
d9bce9d9 2741/* lwaux */
0c8aacd4 2742GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2743/* lwax */
0c8aacd4 2744GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2745/* ldux */
0c8aacd4 2746GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2747/* ldx */
0c8aacd4 2748GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2749GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2750{
b61f2753 2751 TCGv EA;
d9bce9d9
JM		 2752 if (Rc(ctx->opcode)) {
2753 if (unlikely(rA(ctx->opcode) == 0 ||
2754 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2755 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2756 return;
2757 }
2758 }
76db3ba4 2759 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2760 EA = tcg_temp_new();
76db3ba4 2761 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2762 if (ctx->opcode & 0x02) {
2763 /* lwa (lwau is undefined) */
76db3ba4 2764 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2765 } else {
2766 /* ld - ldu */
76db3ba4 2767 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2768 }
d9bce9d9 2769 if (Rc(ctx->opcode))
b61f2753
AJ		 2770 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2771 tcg_temp_free(EA);
d9bce9d9 2772}
be147d08
JM		 2773/* lq */
2774GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2775{
2776#if defined(CONFIG_USER_ONLY)
e06fcd75 2777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2778#else
2779 int ra, rd;
b61f2753 2780 TCGv EA;
be147d08
JM		 2781
2782 /* Restore CPU state */
76db3ba4 2783 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2784 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2785 return;
2786 }
2787 ra = rA(ctx->opcode);
2788 rd = rD(ctx->opcode);
2789 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2790 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2791 return;
2792 }
76db3ba4 2793 if (unlikely(ctx->le_mode)) {
be147d08 2794 /* Little-endian mode is not handled */
e06fcd75 2795 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2796 return;
2797 }
76db3ba4 2798 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2799 EA = tcg_temp_new();
76db3ba4
AJ		 2800 gen_addr_imm_index(ctx, EA, 0x0F);
2801 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2802 gen_addr_add(ctx, EA, EA, 8);
2803 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
b61f2753 2804 tcg_temp_free(EA);
be147d08
JM		 2805#endif
2806}
d9bce9d9 2807#endif
79aceca5
FB		 2808
2809/*** Integer store ***/
0c8aacd4
AJ		 2810#define GEN_ST(name, stop, opc, type) \
2811GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2812{ \
76db3ba4
AJ		 2813 TCGv EA; \
2814 gen_set_access_type(ctx, ACCESS_INT); \
2815 EA = tcg_temp_new(); \
2816 gen_addr_imm_index(ctx, EA, 0); \
2817 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2818 tcg_temp_free(EA); \
79aceca5
FB		 2819}
2820
0c8aacd4
AJ		 2821#define GEN_STU(name, stop, opc, type) \
2822GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2823{ \
b61f2753 2824 TCGv EA; \
76a66253 2825 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2826 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2827 return; \
9a64fbe4 2828 } \
76db3ba4 2829 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2830 EA = tcg_temp_new(); \
9d53c753 2831 if (type == PPC_64B) \
76db3ba4 2832 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2833 else \
76db3ba4
AJ		 2834 gen_addr_imm_index(ctx, EA, 0); \
2835 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2836 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2837 tcg_temp_free(EA); \
79aceca5
FB		 2838}
2839
0c8aacd4
AJ		 2840#define GEN_STUX(name, stop, opc2, opc3, type) \
2841GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2842{ \
b61f2753 2843 TCGv EA; \
76a66253 2844 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2845 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2846 return; \
9a64fbe4 2847 } \
76db3ba4 2848 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2849 EA = tcg_temp_new(); \
76db3ba4
AJ		 2850 gen_addr_reg_index(ctx, EA); \
2851 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2852 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2853 tcg_temp_free(EA); \
79aceca5
FB		 2854}
2855
0c8aacd4
AJ		 2856#define GEN_STX(name, stop, opc2, opc3, type) \
2857GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2858{ \
76db3ba4
AJ		 2859 TCGv EA; \
2860 gen_set_access_type(ctx, ACCESS_INT); \
2861 EA = tcg_temp_new(); \
2862 gen_addr_reg_index(ctx, EA); \
2863 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2864 tcg_temp_free(EA); \
79aceca5
FB		 2865}
2866
0c8aacd4
AJ		 2867#define GEN_STS(name, stop, op, type) \
2868GEN_ST(name, stop, op | 0x20, type); \
2869GEN_STU(name, stop, op | 0x21, type); \
2870GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2871GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2872
2873/* stb stbu stbux stbx */
0c8aacd4 2874GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2875/* sth sthu sthux sthx */
0c8aacd4 2876GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2877/* stw stwu stwux stwx */
0c8aacd4 2878GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2879#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2880GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2881GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2882GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2883{
be147d08 2884 int rs;
b61f2753 2885 TCGv EA;
be147d08
JM		 2886
2887 rs = rS(ctx->opcode);
2888 if ((ctx->opcode & 0x3) == 0x2) {
2889#if defined(CONFIG_USER_ONLY)
e06fcd75 2890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2891#else
2892 /* stq */
76db3ba4 2893 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2895 return;
2896 }
2897 if (unlikely(rs & 1)) {
e06fcd75 2898 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2899 return;
2900 }
76db3ba4 2901 if (unlikely(ctx->le_mode)) {
be147d08 2902 /* Little-endian mode is not handled */
e06fcd75 2903 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2904 return;
2905 }
76db3ba4 2906 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2907 EA = tcg_temp_new();
76db3ba4
AJ		 2908 gen_addr_imm_index(ctx, EA, 0x03);
2909 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2910 gen_addr_add(ctx, EA, EA, 8);
2911 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
b61f2753 2912 tcg_temp_free(EA);
be147d08
JM		 2913#endif
2914 } else {
2915 /* std / stdu */
2916 if (Rc(ctx->opcode)) {
2917 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2918 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2919 return;
2920 }
2921 }
76db3ba4 2922 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2923 EA = tcg_temp_new();
76db3ba4
AJ		 2924 gen_addr_imm_index(ctx, EA, 0x03);
2925 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 2926 if (Rc(ctx->opcode))
b61f2753
AJ		 2927 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2928 tcg_temp_free(EA);
d9bce9d9 2929 }
d9bce9d9
JM		 2930}
2931#endif
79aceca5
FB		 2932/*** Integer load and store with byte reverse ***/
2933/* lhbrx */
76db3ba4 2934static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2935{
76db3ba4
AJ		 2936 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2937 if (likely(!ctx->le_mode)) {
fa3966a3 2938 tcg_gen_bswap16_tl(arg1, arg1);
76db3ba4 2939 }
b61f2753 2940}
0c8aacd4 2941GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 2942
79aceca5 2943/* lwbrx */
76db3ba4 2944static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2945{
76db3ba4
AJ		 2946 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2947 if (likely(!ctx->le_mode)) {
fa3966a3 2948 tcg_gen_bswap32_tl(arg1, arg1);
76db3ba4 2949 }
b61f2753 2950}
0c8aacd4 2951GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 2952
79aceca5 2953/* sthbrx */
76db3ba4 2954static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2955{
76db3ba4 2956 if (likely(!ctx->le_mode)) {
76db3ba4
AJ		 2957 TCGv t0 = tcg_temp_new();
2958 tcg_gen_ext16u_tl(t0, arg1);
fa3966a3 2959 tcg_gen_bswap16_tl(t0, t0);
76db3ba4
AJ		 2960 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2961 tcg_temp_free(t0);
76db3ba4
AJ		 2962 } else {
2963 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2964 }
b61f2753 2965}
0c8aacd4 2966GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 2967
79aceca5 2968/* stwbrx */
76db3ba4 2969static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2970{
76db3ba4 2971 if (likely(!ctx->le_mode)) {
fa3966a3
AJ		 2972 TCGv t0 = tcg_temp_new();
2973 tcg_gen_ext32u_tl(t0, arg1);
2974 tcg_gen_bswap32_tl(t0, t0);
76db3ba4
AJ		 2975 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2976 tcg_temp_free(t0);
76db3ba4
AJ		 2977 } else {
2978 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2979 }
b61f2753 2980}
0c8aacd4 2981GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2982
2983/*** Integer load and store multiple ***/
2984/* lmw */
2985GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2986{
76db3ba4
AJ		 2987 TCGv t0;
2988 TCGv_i32 t1;
2989 gen_set_access_type(ctx, ACCESS_INT);
76a66253 2990 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2991 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 2992 t0 = tcg_temp_new();
2993 t1 = tcg_const_i32(rD(ctx->opcode));
2994 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 2995 gen_helper_lmw(t0, t1);
2996 tcg_temp_free(t0);
2997 tcg_temp_free_i32(t1);
79aceca5
FB		 2998}
2999
3000/* stmw */
3001GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3002{
76db3ba4
AJ		 3003 TCGv t0;
3004 TCGv_i32 t1;
3005 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3006 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3007 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3008 t0 = tcg_temp_new();
3009 t1 = tcg_const_i32(rS(ctx->opcode));
3010 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3011 gen_helper_stmw(t0, t1);
3012 tcg_temp_free(t0);
3013 tcg_temp_free_i32(t1);
79aceca5
FB		 3014}
3015
3016/*** Integer load and store strings ***/
3017/* lswi */
3fc6c082 3018/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3019 * rA is in the range of registers to be loaded.
3020 * In an other hand, IBM says this is valid, but rA won't be loaded.
3021 * For now, I'll follow the spec...
3022 */
05332d70 3023GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3024{
dfbc799d
AJ		 3025 TCGv t0;
3026 TCGv_i32 t1, t2;
79aceca5
FB		 3027 int nb = NB(ctx->opcode);
3028 int start = rD(ctx->opcode);
9a64fbe4 3029 int ra = rA(ctx->opcode);
79aceca5
FB		 3030 int nr;
3031
3032 if (nb == 0)
3033 nb = 32;
3034 nr = nb / 4;
76a66253
JM		 3035 if (unlikely(((start + nr) > 32 &&
3036 start <= ra && (start + nr - 32) > ra) ||
3037 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3038 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3039 return;
297d8e62 3040 }
76db3ba4 3041 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3042 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3043 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3044 t0 = tcg_temp_new();
76db3ba4 3045 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3046 t1 = tcg_const_i32(nb);
3047 t2 = tcg_const_i32(start);
3048 gen_helper_lsw(t0, t1, t2);
3049 tcg_temp_free(t0);
3050 tcg_temp_free_i32(t1);
3051 tcg_temp_free_i32(t2);
79aceca5
FB		 3052}
3053
3054/* lswx */
05332d70 3055GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3056{
76db3ba4
AJ		 3057 TCGv t0;
3058 TCGv_i32 t1, t2, t3;
3059 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3060 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3061 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3062 t0 = tcg_temp_new();
3063 gen_addr_reg_index(ctx, t0);
3064 t1 = tcg_const_i32(rD(ctx->opcode));
3065 t2 = tcg_const_i32(rA(ctx->opcode));
3066 t3 = tcg_const_i32(rB(ctx->opcode));
dfbc799d
AJ		 3067 gen_helper_lswx(t0, t1, t2, t3);
3068 tcg_temp_free(t0);
3069 tcg_temp_free_i32(t1);
3070 tcg_temp_free_i32(t2);
3071 tcg_temp_free_i32(t3);
79aceca5
FB		 3072}
3073
3074/* stswi */
05332d70 3075GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3076{
76db3ba4
AJ		 3077 TCGv t0;
3078 TCGv_i32 t1, t2;
4b3686fa 3079 int nb = NB(ctx->opcode);
76db3ba4 3080 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3081 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3082 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3083 t0 = tcg_temp_new();
3084 gen_addr_register(ctx, t0);
4b3686fa
FB		 3085 if (nb == 0)
3086 nb = 32;
dfbc799d 3087 t1 = tcg_const_i32(nb);
76db3ba4 3088 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3089 gen_helper_stsw(t0, t1, t2);
3090 tcg_temp_free(t0);
3091 tcg_temp_free_i32(t1);
3092 tcg_temp_free_i32(t2);
79aceca5
FB		 3093}
3094
3095/* stswx */
05332d70 3096GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3097{
76db3ba4
AJ		 3098 TCGv t0;
3099 TCGv_i32 t1, t2;
3100 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3101 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3102 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3103 t0 = tcg_temp_new();
3104 gen_addr_reg_index(ctx, t0);
3105 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3106 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3107 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3108 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3109 gen_helper_stsw(t0, t1, t2);
3110 tcg_temp_free(t0);
3111 tcg_temp_free_i32(t1);
3112 tcg_temp_free_i32(t2);
79aceca5
FB		 3113}
3114
3115/*** Memory synchronisation ***/
3116/* eieio */
0db1b20e 3117GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3118{
79aceca5
FB		 3119}
3120
3121/* isync */
0db1b20e 3122GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3123{
e06fcd75 3124 gen_stop_exception(ctx);
79aceca5
FB		 3125}
3126
111bfab3 3127/* lwarx */
76a66253 3128GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3129{
76db3ba4
AJ		 3130 TCGv t0;
3131 gen_set_access_type(ctx, ACCESS_RES);
3132 t0 = tcg_temp_local_new();
3133 gen_addr_reg_index(ctx, t0);
cf360a32 3134 gen_check_align(ctx, t0, 0x03);
76db3ba4 3135 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3136 tcg_gen_mov_tl(cpu_reserve, t0);
3137 tcg_temp_free(t0);
79aceca5
FB		 3138}
3139
3140/* stwcx. */
c7697e1f 3141GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3142{
76db3ba4
AJ		 3143 int l1;
3144 TCGv t0;
3145 gen_set_access_type(ctx, ACCESS_RES);
3146 t0 = tcg_temp_local_new();
3147 gen_addr_reg_index(ctx, t0);
cf360a32 3148 gen_check_align(ctx, t0, 0x03);
cf360a32
AJ		 3149 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3150 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3151 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3152 l1 = gen_new_label();
cf360a32
AJ		 3153 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3154 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3155 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3156 gen_set_label(l1);
3157 tcg_gen_movi_tl(cpu_reserve, -1);
3158 tcg_temp_free(t0);
79aceca5
FB		 3159}
3160
426613db 3161#if defined(TARGET_PPC64)
426613db 3162/* ldarx */
a750fc0b 3163GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3164{
76db3ba4
AJ		 3165 TCGv t0;
3166 gen_set_access_type(ctx, ACCESS_RES);
3167 t0 = tcg_temp_local_new();
3168 gen_addr_reg_index(ctx, t0);
cf360a32 3169 gen_check_align(ctx, t0, 0x07);
76db3ba4 3170 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3171 tcg_gen_mov_tl(cpu_reserve, t0);
3172 tcg_temp_free(t0);
426613db
JM		 3173}
3174
3175/* stdcx. */
c7697e1f 3176GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3177{
76db3ba4
AJ		 3178 int l1;
3179 TCGv t0;
3180 gen_set_access_type(ctx, ACCESS_RES);
3181 t0 = tcg_temp_local_new();
3182 gen_addr_reg_index(ctx, t0);
cf360a32 3183 gen_check_align(ctx, t0, 0x07);
cf360a32
AJ		 3184 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3185 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3186 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3187 l1 = gen_new_label();
cf360a32
AJ		 3188 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3189 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3190 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3191 gen_set_label(l1);
3192 tcg_gen_movi_tl(cpu_reserve, -1);
3193 tcg_temp_free(t0);
426613db
JM		 3194}
3195#endif /* defined(TARGET_PPC64) */
3196
79aceca5 3197/* sync */
a902d886 3198GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3199{
79aceca5
FB		 3200}
3201
0db1b20e
JM		 3202/* wait */
3203GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3204{
931ff272
AJ		 3205 TCGv_i32 t0 = tcg_temp_new_i32();
3206 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3207 tcg_temp_free_i32(t0);
0db1b20e 3208 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3209 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3210}
3211
79aceca5 3212/*** Floating-point load ***/
a0d7d5a7
AJ		 3213#define GEN_LDF(name, ldop, opc, type) \
3214GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3215{ \
a0d7d5a7 3216 TCGv EA; \
76a66253 3217 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3218 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3219 return; \
3220 } \
76db3ba4 3221 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3222 EA = tcg_temp_new(); \
76db3ba4
AJ		 3223 gen_addr_imm_index(ctx, EA, 0); \
3224 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3225 tcg_temp_free(EA); \
79aceca5
FB		 3226}
3227
a0d7d5a7
AJ		 3228#define GEN_LDUF(name, ldop, opc, type) \
3229GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3230{ \
a0d7d5a7 3231 TCGv EA; \
76a66253 3232 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3233 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3234 return; \
3235 } \
76a66253 3236 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3237 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3238 return; \
9a64fbe4 3239 } \
76db3ba4 3240 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3241 EA = tcg_temp_new(); \
76db3ba4
AJ		 3242 gen_addr_imm_index(ctx, EA, 0); \
3243 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3244 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3245 tcg_temp_free(EA); \
79aceca5
FB		 3246}
3247
a0d7d5a7
AJ		 3248#define GEN_LDUXF(name, ldop, opc, type) \
3249GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3250{ \
a0d7d5a7 3251 TCGv EA; \
76a66253 3252 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3253 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3254 return; \
3255 } \
76a66253 3256 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3257 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3258 return; \
9a64fbe4 3259 } \
76db3ba4 3260 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3261 EA = tcg_temp_new(); \
76db3ba4
AJ		 3262 gen_addr_reg_index(ctx, EA); \
3263 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3264 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3265 tcg_temp_free(EA); \
79aceca5
FB		 3266}
3267
a0d7d5a7
AJ		 3268#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3269GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3270{ \
a0d7d5a7 3271 TCGv EA; \
76a66253 3272 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3273 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3274 return; \
3275 } \
76db3ba4 3276 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3277 EA = tcg_temp_new(); \
76db3ba4
AJ		 3278 gen_addr_reg_index(ctx, EA); \
3279 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3280 tcg_temp_free(EA); \
79aceca5
FB		 3281}
3282
a0d7d5a7
AJ		 3283#define GEN_LDFS(name, ldop, op, type) \
3284GEN_LDF(name, ldop, op | 0x20, type); \
3285GEN_LDUF(name, ldop, op | 0x21, type); \
3286GEN_LDUXF(name, ldop, op | 0x01, type); \
3287GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3288
76db3ba4 3289static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3290{
3291 TCGv t0 = tcg_temp_new();
3292 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3293 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3294 tcg_gen_trunc_tl_i32(t1, t0);
3295 tcg_temp_free(t0);
3296 gen_helper_float32_to_float64(arg1, t1);
3297 tcg_temp_free_i32(t1);
3298}
79aceca5 3299
a0d7d5a7
AJ		 3300 /* lfd lfdu lfdux lfdx */
3301GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3302 /* lfs lfsu lfsux lfsx */
3303GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3304
3305/*** Floating-point store ***/
a0d7d5a7
AJ		 3306#define GEN_STF(name, stop, opc, type) \
3307GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3308{ \
a0d7d5a7 3309 TCGv EA; \
76a66253 3310 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3311 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3312 return; \
3313 } \
76db3ba4 3314 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3315 EA = tcg_temp_new(); \
76db3ba4
AJ		 3316 gen_addr_imm_index(ctx, EA, 0); \
3317 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3318 tcg_temp_free(EA); \
79aceca5
FB		 3319}
3320
a0d7d5a7
AJ		 3321#define GEN_STUF(name, stop, opc, type) \
3322GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3323{ \
a0d7d5a7 3324 TCGv EA; \
76a66253 3325 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3326 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3327 return; \
3328 } \
76a66253 3329 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3330 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3331 return; \
9a64fbe4 3332 } \
76db3ba4 3333 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3334 EA = tcg_temp_new(); \
76db3ba4
AJ		 3335 gen_addr_imm_index(ctx, EA, 0); \
3336 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3337 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3338 tcg_temp_free(EA); \
79aceca5
FB		 3339}
3340
a0d7d5a7
AJ		 3341#define GEN_STUXF(name, stop, opc, type) \
3342GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3343{ \
a0d7d5a7 3344 TCGv EA; \
76a66253 3345 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3346 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3347 return; \
3348 } \
76a66253 3349 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3350 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3351 return; \
9a64fbe4 3352 } \
76db3ba4 3353 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3354 EA = tcg_temp_new(); \
76db3ba4
AJ		 3355 gen_addr_reg_index(ctx, EA); \
3356 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3357 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3358 tcg_temp_free(EA); \
79aceca5
FB		 3359}
3360
a0d7d5a7
AJ		 3361#define GEN_STXF(name, stop, opc2, opc3, type) \
3362GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3363{ \
a0d7d5a7 3364 TCGv EA; \
76a66253 3365 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3366 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3367 return; \
3368 } \
76db3ba4 3369 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3370 EA = tcg_temp_new(); \
76db3ba4
AJ		 3371 gen_addr_reg_index(ctx, EA); \
3372 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3373 tcg_temp_free(EA); \
79aceca5
FB		 3374}
3375
a0d7d5a7
AJ		 3376#define GEN_STFS(name, stop, op, type) \
3377GEN_STF(name, stop, op | 0x20, type); \
3378GEN_STUF(name, stop, op | 0x21, type); \
3379GEN_STUXF(name, stop, op | 0x01, type); \
3380GEN_STXF(name, stop, 0x17, op | 0x00, type)
3381
76db3ba4 3382static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3383{
3384 TCGv_i32 t0 = tcg_temp_new_i32();
3385 TCGv t1 = tcg_temp_new();
3386 gen_helper_float64_to_float32(t0, arg1);
3387 tcg_gen_extu_i32_tl(t1, t0);
3388 tcg_temp_free_i32(t0);
76db3ba4 3389 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3390 tcg_temp_free(t1);
3391}
79aceca5
FB		 3392
3393/* stfd stfdu stfdux stfdx */
a0d7d5a7 3394GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3395/* stfs stfsu stfsux stfsx */
a0d7d5a7 3396GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3397
3398/* Optional: */
76db3ba4 3399static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3400{
3401 TCGv t0 = tcg_temp_new();
3402 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3403 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3404 tcg_temp_free(t0);
3405}
79aceca5 3406/* stfiwx */
a0d7d5a7 3407GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3408
3409/*** Branch ***/
b068d6a7
JM		 3410static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3411 target_ulong dest)
c1942362
FB		 3412{
3413 TranslationBlock *tb;
3414 tb = ctx->tb;
a2ffb812
AJ		 3415#if defined(TARGET_PPC64)
3416 if (!ctx->sf_mode)
3417 dest = (uint32_t) dest;
3418#endif
57fec1fe 3419 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3420 likely(!ctx->singlestep_enabled)) {
57fec1fe 3421 tcg_gen_goto_tb(n);
a2ffb812 3422 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3423 tcg_gen_exit_tb((long)tb + n);
c1942362 3424 } else {
a2ffb812 3425 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3426 if (unlikely(ctx->singlestep_enabled)) {
3427 if ((ctx->singlestep_enabled &
bdc4e053 3428 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3429 ctx->exception == POWERPC_EXCP_BRANCH) {
3430 target_ulong tmp = ctx->nip;
3431 ctx->nip = dest;
e06fcd75 3432 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3433 ctx->nip = tmp;
3434 }
3435 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3436 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3437 }
3438 }
57fec1fe 3439 tcg_gen_exit_tb(0);
c1942362 3440 }
c53be334
FB		 3441}
3442
b068d6a7 3443static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3444{
3445#if defined(TARGET_PPC64)
a2ffb812
AJ		 3446 if (ctx->sf_mode == 0)
3447 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3448 else
3449#endif
a2ffb812 3450 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3451}
3452
79aceca5
FB		 3453/* b ba bl bla */
3454GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3455{
76a66253 3456 target_ulong li, target;
38a64f9d 3457
8cbcb4fa 3458 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3459 /* sign extend LI */
76a66253 3460#if defined(TARGET_PPC64)
d9bce9d9
JM		 3461 if (ctx->sf_mode)
3462 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3463 else
76a66253 3464#endif
d9bce9d9 3465 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3466 if (likely(AA(ctx->opcode) == 0))
046d6672 3467 target = ctx->nip + li - 4;
79aceca5 3468 else
9a64fbe4 3469 target = li;
e1833e1f
JM		 3470 if (LK(ctx->opcode))
3471 gen_setlr(ctx, ctx->nip);
c1942362 3472 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3473}
3474
e98a6e40
FB		 3475#define BCOND_IM 0
3476#define BCOND_LR 1
3477#define BCOND_CTR 2
3478
b068d6a7 3479static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3480{
d9bce9d9 3481 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3482 int l1 = gen_new_label();
3483 TCGv target;
e98a6e40 3484
8cbcb4fa 3485 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3486 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3487 target = tcg_temp_local_new();
a2ffb812
AJ		 3488 if (type == BCOND_CTR)
3489 tcg_gen_mov_tl(target, cpu_ctr);
3490 else
3491 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3492 }
e1833e1f
JM		 3493 if (LK(ctx->opcode))
3494 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3495 l1 = gen_new_label();
3496 if ((bo & 0x4) == 0) {
3497 /* Decrement and test CTR */
a7812ae4 3498 TCGv temp = tcg_temp_new();
a2ffb812 3499 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3500 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3501 return;
3502 }
3503 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3504#if defined(TARGET_PPC64)
a2ffb812
AJ		 3505 if (!ctx->sf_mode)
3506 tcg_gen_ext32u_tl(temp, cpu_ctr);
3507 else
d9bce9d9 3508#endif
a2ffb812
AJ		 3509 tcg_gen_mov_tl(temp, cpu_ctr);
3510 if (bo & 0x2) {
3511 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3512 } else {
3513 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3514 }
a7812ae4 3515 tcg_temp_free(temp);
a2ffb812
AJ		 3516 }
3517 if ((bo & 0x10) == 0) {
3518 /* Test CR */
3519 uint32_t bi = BI(ctx->opcode);
3520 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3521 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3522
d9bce9d9 3523 if (bo & 0x8) {
a2ffb812
AJ		 3524 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3525 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3526 } else {
a2ffb812
AJ		 3527 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3528 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3529 }
a7812ae4 3530 tcg_temp_free_i32(temp);
d9bce9d9 3531 }
e98a6e40 3532 if (type == BCOND_IM) {
a2ffb812
AJ		 3533 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3534 if (likely(AA(ctx->opcode) == 0)) {
3535 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3536 } else {
3537 gen_goto_tb(ctx, 0, li);
3538 }
c53be334 3539 gen_set_label(l1);
c1942362 3540 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3541 } else {
d9bce9d9 3542#if defined(TARGET_PPC64)
a2ffb812
AJ		 3543 if (!(ctx->sf_mode))
3544 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3545 else
3546#endif
3547 tcg_gen_andi_tl(cpu_nip, target, ~3);
3548 tcg_gen_exit_tb(0);
3549 gen_set_label(l1);
3550#if defined(TARGET_PPC64)
3551 if (!(ctx->sf_mode))
3552 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3553 else
3554#endif
a2ffb812 3555 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3556 tcg_gen_exit_tb(0);
08e46e54 3557 }
e98a6e40
FB		 3558}
3559
3560GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3561{
e98a6e40
FB		 3562 gen_bcond(ctx, BCOND_IM);
3563}
3564
3565GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3566{
e98a6e40
FB		 3567 gen_bcond(ctx, BCOND_CTR);
3568}
3569
3570GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3571{
e98a6e40
FB		 3572 gen_bcond(ctx, BCOND_LR);
3573}
79aceca5
FB		 3574
3575/*** Condition register logical ***/
e1571908
AJ		 3576#define GEN_CRLOGIC(name, tcg_op, opc) \
3577GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3578{ \
fc0d441e
JM		 3579 uint8_t bitmask; \
3580 int sh; \
a7812ae4 3581 TCGv_i32 t0, t1; \
fc0d441e 3582 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3583 t0 = tcg_temp_new_i32(); \
fc0d441e 3584 if (sh > 0) \
fea0c503 3585 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3586 else if (sh < 0) \
fea0c503 3587 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3588 else \
fea0c503 3589 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3590 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3591 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3592 if (sh > 0) \
fea0c503 3593 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3594 else if (sh < 0) \
fea0c503 3595 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3596 else \
fea0c503
AJ		 3597 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3598 tcg_op(t0, t0, t1); \
fc0d441e 3599 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3600 tcg_gen_andi_i32(t0, t0, bitmask); \
3601 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3602 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3603 tcg_temp_free_i32(t0); \
3604 tcg_temp_free_i32(t1); \
79aceca5
FB		 3605}
3606
3607/* crand */
e1571908 3608GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3609/* crandc */
e1571908 3610GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3611/* creqv */
e1571908 3612GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3613/* crnand */
e1571908 3614GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3615/* crnor */
e1571908 3616GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3617/* cror */
e1571908 3618GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3619/* crorc */
e1571908 3620GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3621/* crxor */
e1571908 3622GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3623/* mcrf */
3624GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3625{
47e4661c 3626 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3627}
3628
3629/*** System linkage ***/
76db3ba4 3630/* rfi (mem_idx only) */
76a66253 3631GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3632{
9a64fbe4 3633#if defined(CONFIG_USER_ONLY)
e06fcd75 3634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 3635#else
3636 /* Restore CPU state */
76db3ba4 3637 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 3639 return;
9a64fbe4 3640 }
d72a19f7 3641 gen_helper_rfi();
e06fcd75 3642 gen_sync_exception(ctx);
9a64fbe4 3643#endif
79aceca5
FB		 3644}
3645
426613db 3646#if defined(TARGET_PPC64)
a750fc0b 3647GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3648{
3649#if defined(CONFIG_USER_ONLY)
e06fcd75 3650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3651#else
3652 /* Restore CPU state */
76db3ba4 3653 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3655 return;
3656 }
d72a19f7 3657 gen_helper_rfid();
e06fcd75 3658 gen_sync_exception(ctx);
426613db
JM		 3659#endif
3660}
426613db 3661
5b8105fa 3662GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3663{
3664#if defined(CONFIG_USER_ONLY)
e06fcd75 3665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3666#else
3667 /* Restore CPU state */
76db3ba4 3668 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 3669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3670 return;
3671 }
d72a19f7 3672 gen_helper_hrfid();
e06fcd75 3673 gen_sync_exception(ctx);
be147d08
JM		 3674#endif
3675}
3676#endif
3677
79aceca5 3678/* sc */
417bf010
JM		 3679#if defined(CONFIG_USER_ONLY)
3680#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3681#else
3682#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3683#endif
e1833e1f 3684GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3685{
e1833e1f
JM		 3686 uint32_t lev;
3687
3688 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3689 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3690}
3691
3692/*** Trap ***/
3693/* tw */
76a66253 3694GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3695{
cab3bee2 3696 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3697 /* Update the nip since this might generate a trap exception */
d9bce9d9 3698 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3699 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3700 tcg_temp_free_i32(t0);
79aceca5
FB		 3701}
3702
3703/* twi */
3704GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3705{
cab3bee2
AJ		 3706 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3707 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3708 /* Update the nip since this might generate a trap exception */
3709 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3710 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3711 tcg_temp_free(t0);
3712 tcg_temp_free_i32(t1);
79aceca5
FB		 3713}
3714
d9bce9d9
JM		 3715#if defined(TARGET_PPC64)
3716/* td */
3717GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3718{
cab3bee2 3719 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3720 /* Update the nip since this might generate a trap exception */
3721 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3722 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3723 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3724}
3725
3726/* tdi */
3727GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3728{
cab3bee2
AJ		 3729 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3730 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3731 /* Update the nip since this might generate a trap exception */
3732 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3733 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3734 tcg_temp_free(t0);
3735 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3736}
3737#endif
3738
79aceca5 3739/*** Processor control ***/
79aceca5
FB		 3740/* mcrxr */
3741GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3742{
3d7b417e
AJ		 3743 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3744 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3745 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3746}
3747
0cfe11ea 3748/* mfcr mfocrf */
76a66253 3749GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3750{
76a66253 3751 uint32_t crm, crn;
3b46e624 3752
76a66253
JM		 3753 if (likely(ctx->opcode & 0x00100000)) {
3754 crm = CRM(ctx->opcode);
8dd640e4 3755 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 3756 crn = ctz32 (crm);
e1571908 3757 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 3758 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3759 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 3760 }
d9bce9d9 3761 } else {
651721b2
AJ		 3762 TCGv_i32 t0 = tcg_temp_new_i32();
3763 tcg_gen_mov_i32(t0, cpu_crf[0]);
3764 tcg_gen_shli_i32(t0, t0, 4);
3765 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3766 tcg_gen_shli_i32(t0, t0, 4);
3767 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3768 tcg_gen_shli_i32(t0, t0, 4);
3769 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3770 tcg_gen_shli_i32(t0, t0, 4);
3771 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3772 tcg_gen_shli_i32(t0, t0, 4);
3773 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3774 tcg_gen_shli_i32(t0, t0, 4);
3775 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3776 tcg_gen_shli_i32(t0, t0, 4);
3777 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3778 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3779 tcg_temp_free_i32(t0);
d9bce9d9 3780 }
79aceca5
FB		 3781}
3782
3783/* mfmsr */
3784GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3785{
9a64fbe4 3786#if defined(CONFIG_USER_ONLY)
e06fcd75 3787 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3788#else
76db3ba4 3789 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3791 return;
9a64fbe4 3792 }
6527f6ea 3793 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3794#endif
79aceca5
FB		 3795}
3796
a11b8151 3797#if 1
6f2d8978 3798#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3799#else
3800static void spr_noaccess (void *opaque, int sprn)
3801{
3802 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3803 printf("ERROR: try to access SPR %d !\n", sprn);
3804}
3805#define SPR_NOACCESS (&spr_noaccess)
3806#endif
3807
79aceca5 3808/* mfspr */
b068d6a7 3809static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3810{
45d827d2 3811 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3812 uint32_t sprn = SPR(ctx->opcode);
3813
3fc6c082 3814#if !defined(CONFIG_USER_ONLY)
76db3ba4 3815 if (ctx->mem_idx == 2)
be147d08 3816 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 3817 else if (ctx->mem_idx)
3fc6c082
FB		 3818 read_cb = ctx->spr_cb[sprn].oea_read;
3819 else
9a64fbe4 3820#endif
3fc6c082 3821 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3822 if (likely(read_cb != NULL)) {
3823 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3824 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3825 } else {
3826 /* Privilege exception */
9fceefa7
JM		 3827 /* This is a hack to avoid warnings when running Linux:
3828 * this OS breaks the PowerPC virtualisation model,
3829 * allowing userland application to read the PVR
3830 */
3831 if (sprn != SPR_PVR) {
93fcfe39 3832 qemu_log("Trying to read privileged spr %d %03x at "
077fc206 3833 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3834 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3835 sprn, sprn, ctx->nip);
f24e5695 3836 }
e06fcd75 3837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3838 }
3fc6c082
FB		 3839 } else {
3840 /* Not defined */
93fcfe39 3841 qemu_log("Trying to read invalid spr %d %03x at "
077fc206 3842 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3843 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3844 sprn, sprn, ctx->nip);
e06fcd75 3845 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3846 }
79aceca5
FB		 3847}
3848
3fc6c082 3849GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3850{
3fc6c082 3851 gen_op_mfspr(ctx);
76a66253 3852}
3fc6c082
FB		 3853
3854/* mftb */
a750fc0b 3855GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3856{
3857 gen_op_mfspr(ctx);
79aceca5
FB		 3858}
3859
0cfe11ea 3860/* mtcrf mtocrf*/
8dd4983c 3861GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3862{
76a66253 3863 uint32_t crm, crn;
3b46e624 3864
76a66253 3865 crm = CRM(ctx->opcode);
8dd640e4 3866 if (likely((ctx->opcode & 0x00100000))) {
3867 if (crm && ((crm & (crm - 1)) == 0)) {
3868 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 3869 crn = ctz32 (crm);
8dd640e4 3870 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 3871 tcg_gen_shri_i32(temp, temp, crn * 4);
3872 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 3873 tcg_temp_free_i32(temp);
3874 }
76a66253 3875 } else {
651721b2
AJ		 3876 TCGv_i32 temp = tcg_temp_new_i32();
3877 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3878 for (crn = 0 ; crn < 8 ; crn++) {
3879 if (crm & (1 << crn)) {
3880 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3881 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3882 }
3883 }
a7812ae4 3884 tcg_temp_free_i32(temp);
76a66253 3885 }
79aceca5
FB		 3886}
3887
3888/* mtmsr */
426613db 3889#if defined(TARGET_PPC64)
be147d08 3890GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3891{
3892#if defined(CONFIG_USER_ONLY)
e06fcd75 3893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 3894#else
76db3ba4 3895 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3896 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 3897 return;
3898 }
be147d08
JM		 3899 if (ctx->opcode & 0x00010000) {
3900 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3901 TCGv t0 = tcg_temp_new();
3902 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3903 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3904 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3905 tcg_temp_free(t0);
be147d08 3906 } else {
056b05f8
JM		 3907 /* XXX: we need to update nip before the store
3908 * if we enter power saving mode, we will exit the loop
3909 * directly from ppc_store_msr
3910 */
be147d08 3911 gen_update_nip(ctx, ctx->nip);
6527f6ea 3912 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3913 /* Must stop the translation as machine state (may have) changed */
3914 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3915 gen_stop_exception(ctx);
be147d08 3916 }
426613db
JM		 3917#endif
3918}
3919#endif
3920
79aceca5
FB		 3921GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3922{
9a64fbe4 3923#if defined(CONFIG_USER_ONLY)
e06fcd75 3924 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3925#else
76db3ba4 3926 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3927 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3928 return;
9a64fbe4 3929 }
be147d08
JM		 3930 if (ctx->opcode & 0x00010000) {
3931 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3932 TCGv t0 = tcg_temp_new();
3933 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3934 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3935 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3936 tcg_temp_free(t0);
be147d08 3937 } else {
056b05f8
JM		 3938 /* XXX: we need to update nip before the store
3939 * if we enter power saving mode, we will exit the loop
3940 * directly from ppc_store_msr
3941 */
be147d08 3942 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3943#if defined(TARGET_PPC64)
6527f6ea
AJ		 3944 if (!ctx->sf_mode) {
3945 TCGv t0 = tcg_temp_new();
3946 TCGv t1 = tcg_temp_new();
3947 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3948 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3949 tcg_gen_or_tl(t0, t0, t1);
3950 tcg_temp_free(t1);
3951 gen_helper_store_msr(t0);
3952 tcg_temp_free(t0);
3953 } else
d9bce9d9 3954#endif
6527f6ea 3955 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 3956 /* Must stop the translation as machine state (may have) changed */
6527f6ea 3957 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3958 gen_stop_exception(ctx);
be147d08 3959 }
9a64fbe4 3960#endif
79aceca5
FB		 3961}
3962
3963/* mtspr */
3964GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3965{
45d827d2 3966 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 3967 uint32_t sprn = SPR(ctx->opcode);
3968
3fc6c082 3969#if !defined(CONFIG_USER_ONLY)
76db3ba4 3970 if (ctx->mem_idx == 2)
be147d08 3971 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 3972 else if (ctx->mem_idx)
3fc6c082
FB		 3973 write_cb = ctx->spr_cb[sprn].oea_write;
3974 else
9a64fbe4 3975#endif
3fc6c082 3976 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3977 if (likely(write_cb != NULL)) {
3978 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 3979 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 3980 } else {
3981 /* Privilege exception */
93fcfe39 3982 qemu_log("Trying to write privileged spr %d %03x at "
077fc206 3983 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3984 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3985 sprn, sprn, ctx->nip);
e06fcd75 3986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 3987 }
3fc6c082
FB		 3988 } else {
3989 /* Not defined */
93fcfe39 3990 qemu_log("Trying to write invalid spr %d %03x at "
077fc206 3991 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3992 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3993 sprn, sprn, ctx->nip);
e06fcd75 3994 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3995 }
79aceca5
FB		 3996}
3997
3998/*** Cache management ***/
79aceca5 3999/* dcbf */
0db1b20e 4000GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4001{
dac454af 4002 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4003 TCGv t0;
4004 gen_set_access_type(ctx, ACCESS_CACHE);
4005 t0 = tcg_temp_new();
4006 gen_addr_reg_index(ctx, t0);
4007 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4008 tcg_temp_free(t0);
79aceca5
FB		 4009}
4010
4011/* dcbi (Supervisor only) */
9a64fbe4 4012GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4013{
a541f297 4014#if defined(CONFIG_USER_ONLY)
e06fcd75 4015 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4016#else
b61f2753 4017 TCGv EA, val;
76db3ba4 4018 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4020 return;
9a64fbe4 4021 }
a7812ae4 4022 EA = tcg_temp_new();
76db3ba4
AJ		 4023 gen_set_access_type(ctx, ACCESS_CACHE);
4024 gen_addr_reg_index(ctx, EA);
a7812ae4 4025 val = tcg_temp_new();
76a66253 4026 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4027 gen_qemu_ld8u(ctx, val, EA);
4028 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4029 tcg_temp_free(val);
4030 tcg_temp_free(EA);
a541f297 4031#endif
79aceca5
FB		 4032}
4033
4034/* dcdst */
9a64fbe4 4035GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4036{
76a66253 4037 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4038 TCGv t0;
4039 gen_set_access_type(ctx, ACCESS_CACHE);
4040 t0 = tcg_temp_new();
4041 gen_addr_reg_index(ctx, t0);
4042 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4043 tcg_temp_free(t0);
79aceca5
FB		 4044}
4045
4046/* dcbt */
0db1b20e 4047GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4048{
0db1b20e 4049 /* interpreted as no-op */
76a66253
JM		 4050 /* XXX: specification say this is treated as a load by the MMU
4051 * but does not generate any exception
4052 */
79aceca5
FB		 4053}
4054
4055/* dcbtst */
0db1b20e 4056GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4057{
0db1b20e 4058 /* interpreted as no-op */
76a66253
JM		 4059 /* XXX: specification say this is treated as a load by the MMU
4060 * but does not generate any exception
4061 */
79aceca5
FB		 4062}
4063
4064/* dcbz */
d63001d1 4065GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4066{
76db3ba4
AJ		 4067 TCGv t0;
4068 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4069 /* NIP cannot be restored if the memory exception comes from an helper */
4070 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4071 t0 = tcg_temp_new();
4072 gen_addr_reg_index(ctx, t0);
799a8c8d
AJ		 4073 gen_helper_dcbz(t0);
4074 tcg_temp_free(t0);
d63001d1
JM		 4075}
4076
c7697e1f 4077GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4078{
76db3ba4
AJ		 4079 TCGv t0;
4080 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4081 /* NIP cannot be restored if the memory exception comes from an helper */
4082 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4083 t0 = tcg_temp_new();
4084 gen_addr_reg_index(ctx, t0);
d63001d1 4085 if (ctx->opcode & 0x00200000)
799a8c8d 4086 gen_helper_dcbz(t0);
d63001d1 4087 else
799a8c8d
AJ		 4088 gen_helper_dcbz_970(t0);
4089 tcg_temp_free(t0);
79aceca5
FB		 4090}
4091
ae1c1a3d
AJ		 4092/* dst / dstt */
4093GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4094{
4095 if (rA(ctx->opcode) == 0) {
4096 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4097 } else {
4098 /* interpreted as no-op */
4099 }
4100}
4101
4102/* dstst /dststt */
4103GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4104{
4105 if (rA(ctx->opcode) == 0) {
4106 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4107 } else {
4108 /* interpreted as no-op */
4109 }
4110
4111}
4112
4113/* dss / dssall */
4114GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4115{
4116 /* interpreted as no-op */
4117}
4118
79aceca5 4119/* icbi */
1b413d55 4120GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4121{
76db3ba4
AJ		 4122 TCGv t0;
4123 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4124 /* NIP cannot be restored if the memory exception comes from an helper */
4125 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4126 t0 = tcg_temp_new();
4127 gen_addr_reg_index(ctx, t0);
37d269df
AJ		 4128 gen_helper_icbi(t0);
4129 tcg_temp_free(t0);
79aceca5
FB		 4130}
4131
4132/* Optional: */
4133/* dcba */
a750fc0b 4134GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4135{
0db1b20e
JM		 4136 /* interpreted as no-op */
4137 /* XXX: specification say this is treated as a store by the MMU
4138 * but does not generate any exception
4139 */
79aceca5
FB		 4140}
4141
4142/*** Segment register manipulation ***/
4143/* Supervisor only: */
4144/* mfsr */
4145GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4146{
9a64fbe4 4147#if defined(CONFIG_USER_ONLY)
e06fcd75 4148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4149#else
74d37793 4150 TCGv t0;
76db3ba4 4151 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4153 return;
9a64fbe4 4154 }
74d37793
AJ		 4155 t0 = tcg_const_tl(SR(ctx->opcode));
4156 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4157 tcg_temp_free(t0);
9a64fbe4 4158#endif
79aceca5
FB		 4159}
4160
4161/* mfsrin */
9a64fbe4 4162GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4163{
9a64fbe4 4164#if defined(CONFIG_USER_ONLY)
e06fcd75 4165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4166#else
74d37793 4167 TCGv t0;
76db3ba4 4168 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4170 return;
9a64fbe4 4171 }
74d37793
AJ		 4172 t0 = tcg_temp_new();
4173 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4174 tcg_gen_andi_tl(t0, t0, 0xF);
4175 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4176 tcg_temp_free(t0);
9a64fbe4 4177#endif
79aceca5
FB		 4178}
4179
4180/* mtsr */
e63c59cb 4181GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4182{
9a64fbe4 4183#if defined(CONFIG_USER_ONLY)
e06fcd75 4184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4185#else
74d37793 4186 TCGv t0;
76db3ba4 4187 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4189 return;
9a64fbe4 4190 }
74d37793
AJ		 4191 t0 = tcg_const_tl(SR(ctx->opcode));
4192 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4193 tcg_temp_free(t0);
9a64fbe4 4194#endif
79aceca5
FB		 4195}
4196
4197/* mtsrin */
9a64fbe4 4198GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4199{
9a64fbe4 4200#if defined(CONFIG_USER_ONLY)
e06fcd75 4201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4202#else
74d37793 4203 TCGv t0;
76db3ba4 4204 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4206 return;
9a64fbe4 4207 }
74d37793
AJ		 4208 t0 = tcg_temp_new();
4209 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4210 tcg_gen_andi_tl(t0, t0, 0xF);
4211 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4212 tcg_temp_free(t0);
9a64fbe4 4213#endif
79aceca5
FB		 4214}
4215
12de9a39
JM		 4216#if defined(TARGET_PPC64)
4217/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4218/* mfsr */
c7697e1f 4219GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4220{
4221#if defined(CONFIG_USER_ONLY)
e06fcd75 4222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4223#else
74d37793 4224 TCGv t0;
76db3ba4 4225 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4227 return;
4228 }
74d37793 4229 t0 = tcg_const_tl(SR(ctx->opcode));
f6b868fc 4230 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
74d37793 4231 tcg_temp_free(t0);
12de9a39
JM		 4232#endif
4233}
4234
4235/* mfsrin */
c7697e1f
JM		 4236GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4237 PPC_SEGMENT_64B)
12de9a39
JM		 4238{
4239#if defined(CONFIG_USER_ONLY)
e06fcd75 4240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4241#else
74d37793 4242 TCGv t0;
76db3ba4 4243 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4245 return;
4246 }
74d37793
AJ		 4247 t0 = tcg_temp_new();
4248 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4249 tcg_gen_andi_tl(t0, t0, 0xF);
f6b868fc 4250 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
74d37793 4251 tcg_temp_free(t0);
12de9a39
JM		 4252#endif
4253}
4254
4255/* mtsr */
c7697e1f 4256GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4257{
4258#if defined(CONFIG_USER_ONLY)
e06fcd75 4259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4260#else
74d37793 4261 TCGv t0;
76db3ba4 4262 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4264 return;
4265 }
74d37793 4266 t0 = tcg_const_tl(SR(ctx->opcode));
f6b868fc 4267 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4268 tcg_temp_free(t0);
12de9a39
JM		 4269#endif
4270}
4271
4272/* mtsrin */
c7697e1f
JM		 4273GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4274 PPC_SEGMENT_64B)
12de9a39
JM		 4275{
4276#if defined(CONFIG_USER_ONLY)
e06fcd75 4277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4278#else
74d37793 4279 TCGv t0;
76db3ba4 4280 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4282 return;
4283 }
74d37793
AJ		 4284 t0 = tcg_temp_new();
4285 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4286 tcg_gen_andi_tl(t0, t0, 0xF);
f6b868fc 4287 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4288 tcg_temp_free(t0);
12de9a39
JM		 4289#endif
4290}
f6b868fc
BS		 4291
4292/* slbmte */
4293GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B)
4294{
4295#if defined(CONFIG_USER_ONLY)
4296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4297#else
4298 if (unlikely(!ctx->mem_idx)) {
4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4300 return;
4301 }
4302 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4303#endif
4304}
4305
12de9a39
JM		 4306#endif /* defined(TARGET_PPC64) */
4307
79aceca5 4308/*** Lookaside buffer management ***/
76db3ba4 4309/* Optional & mem_idx only: */
79aceca5 4310/* tlbia */
3fc6c082 4311GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4312{
9a64fbe4 4313#if defined(CONFIG_USER_ONLY)
e06fcd75 4314 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4315#else
76db3ba4 4316 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4318 return;
9a64fbe4 4319 }
74d37793 4320 gen_helper_tlbia();
9a64fbe4 4321#endif
79aceca5
FB		 4322}
4323
bf14b1ce
BS		 4324/* tlbiel */
4325GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE)
4326{
4327#if defined(CONFIG_USER_ONLY)
4328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4329#else
4330 if (unlikely(!ctx->mem_idx)) {
4331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4332 return;
4333 }
4334 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4335#endif
4336}
4337
79aceca5 4338/* tlbie */
76a66253 4339GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4340{
9a64fbe4 4341#if defined(CONFIG_USER_ONLY)
e06fcd75 4342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4343#else
76db3ba4 4344 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4346 return;
9a64fbe4 4347 }
d9bce9d9 4348#if defined(TARGET_PPC64)
74d37793
AJ		 4349 if (!ctx->sf_mode) {
4350 TCGv t0 = tcg_temp_new();
4351 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4352 gen_helper_tlbie(t0);
4353 tcg_temp_free(t0);
4354 } else
d9bce9d9 4355#endif
74d37793 4356 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4357#endif
79aceca5
FB		 4358}
4359
4360/* tlbsync */
76a66253 4361GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4362{
9a64fbe4 4363#if defined(CONFIG_USER_ONLY)
e06fcd75 4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4365#else
76db3ba4 4366 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4368 return;
9a64fbe4
FB		 4369 }
4370 /* This has no effect: it should ensure that all previous
4371 * tlbie have completed
4372 */
e06fcd75 4373 gen_stop_exception(ctx);
9a64fbe4 4374#endif
79aceca5
FB		 4375}
4376
426613db
JM		 4377#if defined(TARGET_PPC64)
4378/* slbia */
4379GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4380{
4381#if defined(CONFIG_USER_ONLY)
e06fcd75 4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4383#else
76db3ba4 4384 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4386 return;
4387 }
74d37793 4388 gen_helper_slbia();
426613db
JM		 4389#endif
4390}
4391
4392/* slbie */
4393GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4394{
4395#if defined(CONFIG_USER_ONLY)
e06fcd75 4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4397#else
76db3ba4 4398 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4400 return;
4401 }
74d37793 4402 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4403#endif
4404}
4405#endif
4406
79aceca5
FB		 4407/*** External control ***/
4408/* Optional: */
111bfab3 4409/* eciwx */
79aceca5
FB		 4410GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4411{
76db3ba4 4412 TCGv t0;
fa407c03 4413 /* Should check EAR[E] ! */
76db3ba4
AJ		 4414 gen_set_access_type(ctx, ACCESS_EXT);
4415 t0 = tcg_temp_new();
4416 gen_addr_reg_index(ctx, t0);
fa407c03 4417 gen_check_align(ctx, t0, 0x03);
76db3ba4 4418 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4419 tcg_temp_free(t0);
76a66253
JM		 4420}
4421
4422/* ecowx */
4423GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4424{
76db3ba4 4425 TCGv t0;
fa407c03 4426 /* Should check EAR[E] ! */
76db3ba4
AJ		 4427 gen_set_access_type(ctx, ACCESS_EXT);
4428 t0 = tcg_temp_new();
4429 gen_addr_reg_index(ctx, t0);
fa407c03 4430 gen_check_align(ctx, t0, 0x03);
76db3ba4 4431 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4432 tcg_temp_free(t0);
76a66253
JM		 4433}
4434
4435/* PowerPC 601 specific instructions */
4436/* abs - abs. */
4437GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4438{
22e0e173
AJ		 4439 int l1 = gen_new_label();
4440 int l2 = gen_new_label();
4441 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4442 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4443 tcg_gen_br(l2);
4444 gen_set_label(l1);
4445 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4446 gen_set_label(l2);
76a66253 4447 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4448 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4449}
4450
4451/* abso - abso. */
4452GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4453{
22e0e173
AJ		 4454 int l1 = gen_new_label();
4455 int l2 = gen_new_label();
4456 int l3 = gen_new_label();
4457 /* Start with XER OV disabled, the most likely case */
4458 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4459 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4460 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4461 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4462 tcg_gen_br(l2);
4463 gen_set_label(l1);
4464 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4465 tcg_gen_br(l3);
4466 gen_set_label(l2);
4467 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4468 gen_set_label(l3);
76a66253 4469 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4470 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4471}
4472
4473/* clcs */
a750fc0b 4474GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4475{
22e0e173
AJ		 4476 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4477 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4478 tcg_temp_free_i32(t0);
c7697e1f 4479 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4480}
4481
4482/* div - div. */
4483GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4484{
22e0e173 4485 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4486 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4487 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4488}
4489
4490/* divo - divo. */
4491GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4492{
22e0e173 4493 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4494 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4495 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4496}
4497
4498/* divs - divs. */
4499GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4500{
22e0e173 4501 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4502 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4503 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4504}
4505
4506/* divso - divso. */
4507GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4508{
22e0e173 4509 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4510 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4511 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4512}
4513
4514/* doz - doz. */
4515GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4516{
22e0e173
AJ		 4517 int l1 = gen_new_label();
4518 int l2 = gen_new_label();
4519 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4520 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4521 tcg_gen_br(l2);
4522 gen_set_label(l1);
4523 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4524 gen_set_label(l2);
76a66253 4525 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4526 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4527}
4528
4529/* dozo - dozo. */
4530GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4531{
22e0e173
AJ		 4532 int l1 = gen_new_label();
4533 int l2 = gen_new_label();
4534 TCGv t0 = tcg_temp_new();
4535 TCGv t1 = tcg_temp_new();
4536 TCGv t2 = tcg_temp_new();
4537 /* Start with XER OV disabled, the most likely case */
4538 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4539 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4540 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4541 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4542 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4543 tcg_gen_andc_tl(t1, t1, t2);
4544 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4545 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4546 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4547 tcg_gen_br(l2);
4548 gen_set_label(l1);
4549 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4550 gen_set_label(l2);
4551 tcg_temp_free(t0);
4552 tcg_temp_free(t1);
4553 tcg_temp_free(t2);
76a66253 4554 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4555 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4556}
4557
4558/* dozi */
4559GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4560{
22e0e173
AJ		 4561 target_long simm = SIMM(ctx->opcode);
4562 int l1 = gen_new_label();
4563 int l2 = gen_new_label();
4564 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4565 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4566 tcg_gen_br(l2);
4567 gen_set_label(l1);
4568 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4569 gen_set_label(l2);
4570 if (unlikely(Rc(ctx->opcode) != 0))
4571 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4572}
4573
76a66253
JM		 4574/* lscbx - lscbx. */
4575GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4576{
bdb4b689
AJ		 4577 TCGv t0 = tcg_temp_new();
4578 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4579 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4580 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4581
76db3ba4 4582 gen_addr_reg_index(ctx, t0);
76a66253 4583 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4584 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4585 gen_helper_lscbx(t0, t0, t1, t2, t3);
4586 tcg_temp_free_i32(t1);
4587 tcg_temp_free_i32(t2);
4588 tcg_temp_free_i32(t3);
3d7b417e 4589 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4590 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4591 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4592 gen_set_Rc0(ctx, t0);
4593 tcg_temp_free(t0);
76a66253
JM		 4594}
4595
4596/* maskg - maskg. */
4597GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4598{
22e0e173
AJ		 4599 int l1 = gen_new_label();
4600 TCGv t0 = tcg_temp_new();
4601 TCGv t1 = tcg_temp_new();
4602 TCGv t2 = tcg_temp_new();
4603 TCGv t3 = tcg_temp_new();
4604 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4605 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4606 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4607 tcg_gen_addi_tl(t2, t0, 1);
4608 tcg_gen_shr_tl(t2, t3, t2);
4609 tcg_gen_shr_tl(t3, t3, t1);
4610 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4611 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4612 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4613 gen_set_label(l1);
4614 tcg_temp_free(t0);
4615 tcg_temp_free(t1);
4616 tcg_temp_free(t2);
4617 tcg_temp_free(t3);
76a66253 4618 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4619 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4620}
4621
4622/* maskir - maskir. */
4623GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4624{
22e0e173
AJ		 4625 TCGv t0 = tcg_temp_new();
4626 TCGv t1 = tcg_temp_new();
4627 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4628 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4629 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4630 tcg_temp_free(t0);
4631 tcg_temp_free(t1);
76a66253 4632 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4633 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4634}
4635
4636/* mul - mul. */
4637GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4638{
22e0e173
AJ		 4639 TCGv_i64 t0 = tcg_temp_new_i64();
4640 TCGv_i64 t1 = tcg_temp_new_i64();
4641 TCGv t2 = tcg_temp_new();
4642 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4643 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4644 tcg_gen_mul_i64(t0, t0, t1);
4645 tcg_gen_trunc_i64_tl(t2, t0);
4646 gen_store_spr(SPR_MQ, t2);
4647 tcg_gen_shri_i64(t1, t0, 32);
4648 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4649 tcg_temp_free_i64(t0);
4650 tcg_temp_free_i64(t1);
4651 tcg_temp_free(t2);
76a66253 4652 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4653 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4654}
4655
4656/* mulo - mulo. */
4657GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4658{
22e0e173
AJ		 4659 int l1 = gen_new_label();
4660 TCGv_i64 t0 = tcg_temp_new_i64();
4661 TCGv_i64 t1 = tcg_temp_new_i64();
4662 TCGv t2 = tcg_temp_new();
4663 /* Start with XER OV disabled, the most likely case */
4664 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4665 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4666 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4667 tcg_gen_mul_i64(t0, t0, t1);
4668 tcg_gen_trunc_i64_tl(t2, t0);
4669 gen_store_spr(SPR_MQ, t2);
4670 tcg_gen_shri_i64(t1, t0, 32);
4671 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4672 tcg_gen_ext32s_i64(t1, t0);
4673 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4674 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4675 gen_set_label(l1);
4676 tcg_temp_free_i64(t0);
4677 tcg_temp_free_i64(t1);
4678 tcg_temp_free(t2);
76a66253 4679 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4680 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4681}
4682
4683/* nabs - nabs. */
4684GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4685{
22e0e173
AJ		 4686 int l1 = gen_new_label();
4687 int l2 = gen_new_label();
4688 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4689 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4690 tcg_gen_br(l2);
4691 gen_set_label(l1);
4692 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4693 gen_set_label(l2);
76a66253 4694 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4695 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4696}
4697
4698/* nabso - nabso. */
4699GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4700{
22e0e173
AJ		 4701 int l1 = gen_new_label();
4702 int l2 = gen_new_label();
4703 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4704 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4705 tcg_gen_br(l2);
4706 gen_set_label(l1);
4707 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4708 gen_set_label(l2);
4709 /* nabs never overflows */
4710 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4711 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4712 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4713}
4714
4715/* rlmi - rlmi. */
4716GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4717{
7487953d
AJ		 4718 uint32_t mb = MB(ctx->opcode);
4719 uint32_t me = ME(ctx->opcode);
4720 TCGv t0 = tcg_temp_new();
4721 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4722 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4723 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4724 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4725 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4726 tcg_temp_free(t0);
76a66253 4727 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4728 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4729}
4730
4731/* rrib - rrib. */
4732GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4733{
7487953d
AJ		 4734 TCGv t0 = tcg_temp_new();
4735 TCGv t1 = tcg_temp_new();
4736 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4737 tcg_gen_movi_tl(t1, 0x80000000);
4738 tcg_gen_shr_tl(t1, t1, t0);
4739 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4740 tcg_gen_and_tl(t0, t0, t1);
4741 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4742 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4743 tcg_temp_free(t0);
4744 tcg_temp_free(t1);
76a66253 4745 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4746 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4747}
4748
4749/* sle - sle. */
4750GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4751{
7487953d
AJ		 4752 TCGv t0 = tcg_temp_new();
4753 TCGv t1 = tcg_temp_new();
4754 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4755 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4756 tcg_gen_subfi_tl(t1, 32, t1);
4757 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4758 tcg_gen_or_tl(t1, t0, t1);
4759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4760 gen_store_spr(SPR_MQ, t1);
4761 tcg_temp_free(t0);
4762 tcg_temp_free(t1);
76a66253 4763 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4765}
4766
4767/* sleq - sleq. */
4768GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4769{
7487953d
AJ		 4770 TCGv t0 = tcg_temp_new();
4771 TCGv t1 = tcg_temp_new();
4772 TCGv t2 = tcg_temp_new();
4773 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4774 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4775 tcg_gen_shl_tl(t2, t2, t0);
4776 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4777 gen_load_spr(t1, SPR_MQ);
4778 gen_store_spr(SPR_MQ, t0);
4779 tcg_gen_and_tl(t0, t0, t2);
4780 tcg_gen_andc_tl(t1, t1, t2);
4781 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4782 tcg_temp_free(t0);
4783 tcg_temp_free(t1);
4784 tcg_temp_free(t2);
76a66253 4785 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4786 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4787}
4788
4789/* sliq - sliq. */
4790GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4791{
7487953d
AJ		 4792 int sh = SH(ctx->opcode);
4793 TCGv t0 = tcg_temp_new();
4794 TCGv t1 = tcg_temp_new();
4795 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4796 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4797 tcg_gen_or_tl(t1, t0, t1);
4798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4799 gen_store_spr(SPR_MQ, t1);
4800 tcg_temp_free(t0);
4801 tcg_temp_free(t1);
76a66253 4802 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4803 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4804}
4805
4806/* slliq - slliq. */
4807GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4808{
7487953d
AJ		 4809 int sh = SH(ctx->opcode);
4810 TCGv t0 = tcg_temp_new();
4811 TCGv t1 = tcg_temp_new();
4812 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4813 gen_load_spr(t1, SPR_MQ);
4814 gen_store_spr(SPR_MQ, t0);
4815 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4816 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4817 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4818 tcg_temp_free(t0);
4819 tcg_temp_free(t1);
76a66253 4820 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4822}
4823
4824/* sllq - sllq. */
4825GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4826{
7487953d
AJ		 4827 int l1 = gen_new_label();
4828 int l2 = gen_new_label();
4829 TCGv t0 = tcg_temp_local_new();
4830 TCGv t1 = tcg_temp_local_new();
4831 TCGv t2 = tcg_temp_local_new();
4832 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4833 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4834 tcg_gen_shl_tl(t1, t1, t2);
4835 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4836 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4837 gen_load_spr(t0, SPR_MQ);
4838 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4839 tcg_gen_br(l2);
4840 gen_set_label(l1);
4841 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4842 gen_load_spr(t2, SPR_MQ);
4843 tcg_gen_andc_tl(t1, t2, t1);
4844 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4845 gen_set_label(l2);
4846 tcg_temp_free(t0);
4847 tcg_temp_free(t1);
4848 tcg_temp_free(t2);
76a66253 4849 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4850 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4851}
4852
4853/* slq - slq. */
4854GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4855{
7487953d
AJ		 4856 int l1 = gen_new_label();
4857 TCGv t0 = tcg_temp_new();
4858 TCGv t1 = tcg_temp_new();
4859 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4860 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4861 tcg_gen_subfi_tl(t1, 32, t1);
4862 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4863 tcg_gen_or_tl(t1, t0, t1);
4864 gen_store_spr(SPR_MQ, t1);
4865 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4866 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4867 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4868 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4869 gen_set_label(l1);
4870 tcg_temp_free(t0);
4871 tcg_temp_free(t1);
76a66253 4872 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4873 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4874}
4875
d9bce9d9 4876/* sraiq - sraiq. */
76a66253
JM		 4877GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4878{
7487953d
AJ		 4879 int sh = SH(ctx->opcode);
4880 int l1 = gen_new_label();
4881 TCGv t0 = tcg_temp_new();
4882 TCGv t1 = tcg_temp_new();
4883 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4884 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4885 tcg_gen_or_tl(t0, t0, t1);
4886 gen_store_spr(SPR_MQ, t0);
4887 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4888 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4889 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4890 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4891 gen_set_label(l1);
4892 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4893 tcg_temp_free(t0);
4894 tcg_temp_free(t1);
76a66253 4895 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4896 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4897}
4898
4899/* sraq - sraq. */
4900GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4901{
7487953d
AJ		 4902 int l1 = gen_new_label();
4903 int l2 = gen_new_label();
4904 TCGv t0 = tcg_temp_new();
4905 TCGv t1 = tcg_temp_local_new();
4906 TCGv t2 = tcg_temp_local_new();
4907 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4908 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4909 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4910 tcg_gen_subfi_tl(t2, 32, t2);
4911 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4912 tcg_gen_or_tl(t0, t0, t2);
4913 gen_store_spr(SPR_MQ, t0);
4914 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4915 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4916 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4917 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4918 gen_set_label(l1);
4919 tcg_temp_free(t0);
4920 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4921 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4922 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4923 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4924 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4925 gen_set_label(l2);
4926 tcg_temp_free(t1);
4927 tcg_temp_free(t2);
76a66253 4928 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4930}
4931
4932/* sre - sre. */
4933GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4934{
7487953d
AJ		 4935 TCGv t0 = tcg_temp_new();
4936 TCGv t1 = tcg_temp_new();
4937 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4938 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4939 tcg_gen_subfi_tl(t1, 32, t1);
4940 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4941 tcg_gen_or_tl(t1, t0, t1);
4942 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4943 gen_store_spr(SPR_MQ, t1);
4944 tcg_temp_free(t0);
4945 tcg_temp_free(t1);
76a66253 4946 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4948}
4949
4950/* srea - srea. */
4951GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4952{
7487953d
AJ		 4953 TCGv t0 = tcg_temp_new();
4954 TCGv t1 = tcg_temp_new();
4955 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4956 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4957 gen_store_spr(SPR_MQ, t0);
4958 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4959 tcg_temp_free(t0);
4960 tcg_temp_free(t1);
76a66253 4961 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4962 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4963}
4964
4965/* sreq */
4966GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4967{
7487953d
AJ		 4968 TCGv t0 = tcg_temp_new();
4969 TCGv t1 = tcg_temp_new();
4970 TCGv t2 = tcg_temp_new();
4971 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4972 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4973 tcg_gen_shr_tl(t1, t1, t0);
4974 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4975 gen_load_spr(t2, SPR_MQ);
4976 gen_store_spr(SPR_MQ, t0);
4977 tcg_gen_and_tl(t0, t0, t1);
4978 tcg_gen_andc_tl(t2, t2, t1);
4979 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4980 tcg_temp_free(t0);
4981 tcg_temp_free(t1);
4982 tcg_temp_free(t2);
76a66253 4983 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4984 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4985}
4986
4987/* sriq */
4988GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4989{
7487953d
AJ		 4990 int sh = SH(ctx->opcode);
4991 TCGv t0 = tcg_temp_new();
4992 TCGv t1 = tcg_temp_new();
4993 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4994 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4995 tcg_gen_or_tl(t1, t0, t1);
4996 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4997 gen_store_spr(SPR_MQ, t1);
4998 tcg_temp_free(t0);
4999 tcg_temp_free(t1);
76a66253 5000 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5002}
5003
5004/* srliq */
5005GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5006{
7487953d
AJ		 5007 int sh = SH(ctx->opcode);
5008 TCGv t0 = tcg_temp_new();
5009 TCGv t1 = tcg_temp_new();
5010 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5011 gen_load_spr(t1, SPR_MQ);
5012 gen_store_spr(SPR_MQ, t0);
5013 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5014 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5015 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
76a66253 5018 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5020}
5021
5022/* srlq */
5023GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5024{
7487953d
AJ		 5025 int l1 = gen_new_label();
5026 int l2 = gen_new_label();
5027 TCGv t0 = tcg_temp_local_new();
5028 TCGv t1 = tcg_temp_local_new();
5029 TCGv t2 = tcg_temp_local_new();
5030 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5031 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5032 tcg_gen_shr_tl(t2, t1, t2);
5033 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5034 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5035 gen_load_spr(t0, SPR_MQ);
5036 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5037 tcg_gen_br(l2);
5038 gen_set_label(l1);
5039 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5040 tcg_gen_and_tl(t0, t0, t2);
5041 gen_load_spr(t1, SPR_MQ);
5042 tcg_gen_andc_tl(t1, t1, t2);
5043 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5044 gen_set_label(l2);
5045 tcg_temp_free(t0);
5046 tcg_temp_free(t1);
5047 tcg_temp_free(t2);
76a66253 5048 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5049 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5050}
5051
5052/* srq */
5053GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5054{
7487953d
AJ		 5055 int l1 = gen_new_label();
5056 TCGv t0 = tcg_temp_new();
5057 TCGv t1 = tcg_temp_new();
5058 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5059 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5060 tcg_gen_subfi_tl(t1, 32, t1);
5061 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5062 tcg_gen_or_tl(t1, t0, t1);
5063 gen_store_spr(SPR_MQ, t1);
5064 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5065 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5066 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5067 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5068 gen_set_label(l1);
5069 tcg_temp_free(t0);
5070 tcg_temp_free(t1);
76a66253 5071 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5072 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5073}
5074
5075/* PowerPC 602 specific instructions */
5076/* dsa */
5077GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5078{
5079 /* XXX: TODO */
e06fcd75 5080 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5081}
5082
5083/* esa */
5084GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5085{
5086 /* XXX: TODO */
e06fcd75 5087 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5088}
5089
5090/* mfrom */
5091GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5092{
5093#if defined(CONFIG_USER_ONLY)
e06fcd75 5094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5095#else
76db3ba4 5096 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5098 return;
5099 }
cf02a65c 5100 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5101#endif
5102}
5103
5104/* 602 - 603 - G2 TLB management */
5105/* tlbld */
c7697e1f 5106GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5107{
5108#if defined(CONFIG_USER_ONLY)
e06fcd75 5109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5110#else
76db3ba4 5111 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5113 return;
5114 }
74d37793 5115 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5116#endif
5117}
5118
5119/* tlbli */
c7697e1f 5120GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5121{
5122#if defined(CONFIG_USER_ONLY)
e06fcd75 5123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5124#else
76db3ba4 5125 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5127 return;
5128 }
74d37793 5129 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5130#endif
5131}
5132
7dbe11ac
JM		 5133/* 74xx TLB management */
5134/* tlbld */
c7697e1f 5135GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5136{
5137#if defined(CONFIG_USER_ONLY)
e06fcd75 5138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5139#else
76db3ba4 5140 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5142 return;
5143 }
74d37793 5144 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5145#endif
5146}
5147
5148/* tlbli */
c7697e1f 5149GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5150{
5151#if defined(CONFIG_USER_ONLY)
e06fcd75 5152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5153#else
76db3ba4 5154 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5156 return;
5157 }
74d37793 5158 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5159#endif
5160}
5161
76a66253
JM		 5162/* POWER instructions not in PowerPC 601 */
5163/* clf */
5164GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5165{
5166 /* Cache line flush: implemented as no-op */
5167}
5168
5169/* cli */
5170GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5171{
7f75ffd3 5172 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5173#if defined(CONFIG_USER_ONLY)
e06fcd75 5174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5175#else
76db3ba4 5176 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5178 return;
5179 }
5180#endif
5181}
5182
5183/* dclst */
5184GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5185{
5186 /* Data cache line store: treated as no-op */
5187}
5188
5189GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5190{
5191#if defined(CONFIG_USER_ONLY)
e06fcd75 5192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5193#else
74d37793
AJ		 5194 int ra = rA(ctx->opcode);
5195 int rd = rD(ctx->opcode);
5196 TCGv t0;
76db3ba4 5197 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5198 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5199 return;
5200 }
74d37793 5201 t0 = tcg_temp_new();
76db3ba4 5202 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5203 tcg_gen_shri_tl(t0, t0, 28);
5204 tcg_gen_andi_tl(t0, t0, 0xF);
5205 gen_helper_load_sr(cpu_gpr[rd], t0);
5206 tcg_temp_free(t0);
76a66253 5207 if (ra != 0 && ra != rd)
74d37793 5208 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5209#endif
5210}
5211
5212GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5213{
5214#if defined(CONFIG_USER_ONLY)
e06fcd75 5215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5216#else
22e0e173 5217 TCGv t0;
76db3ba4 5218 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5220 return;
5221 }
22e0e173 5222 t0 = tcg_temp_new();
76db3ba4 5223 gen_addr_reg_index(ctx, t0);
22e0e173
AJ		 5224 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5225 tcg_temp_free(t0);
76a66253
JM		 5226#endif
5227}
5228
5229GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5230{
5231#if defined(CONFIG_USER_ONLY)
e06fcd75 5232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5233#else
76db3ba4 5234 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5236 return;
5237 }
d72a19f7 5238 gen_helper_rfsvc();
e06fcd75 5239 gen_sync_exception(ctx);
76a66253
JM		 5240#endif
5241}
5242
5243/* svc is not implemented for now */
5244
5245/* POWER2 specific instructions */
5246/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5247
5248/* lfq */
5249GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5250{
01a4afeb 5251 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5252 TCGv t0;
5253 gen_set_access_type(ctx, ACCESS_FLOAT);
5254 t0 = tcg_temp_new();
5255 gen_addr_imm_index(ctx, t0, 0);
5256 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5257 gen_addr_add(ctx, t0, t0, 8);
5258 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5259 tcg_temp_free(t0);
76a66253
JM		 5260}
5261
5262/* lfqu */
5263GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5264{
5265 int ra = rA(ctx->opcode);
01a4afeb 5266 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5267 TCGv t0, t1;
5268 gen_set_access_type(ctx, ACCESS_FLOAT);
5269 t0 = tcg_temp_new();
5270 t1 = tcg_temp_new();
5271 gen_addr_imm_index(ctx, t0, 0);
5272 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5273 gen_addr_add(ctx, t1, t0, 8);
5274 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5275 if (ra != 0)
01a4afeb
AJ		 5276 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5277 tcg_temp_free(t0);
5278 tcg_temp_free(t1);
76a66253
JM		 5279}
5280
5281/* lfqux */
5282GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5283{
5284 int ra = rA(ctx->opcode);
01a4afeb 5285 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5286 gen_set_access_type(ctx, ACCESS_FLOAT);
5287 TCGv t0, t1;
5288 t0 = tcg_temp_new();
5289 gen_addr_reg_index(ctx, t0);
5290 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5291 t1 = tcg_temp_new();
5292 gen_addr_add(ctx, t1, t0, 8);
5293 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5294 tcg_temp_free(t1);
76a66253 5295 if (ra != 0)
01a4afeb
AJ		 5296 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5297 tcg_temp_free(t0);
76a66253
JM		 5298}
5299
5300/* lfqx */
5301GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5302{
01a4afeb 5303 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5304 TCGv t0;
5305 gen_set_access_type(ctx, ACCESS_FLOAT);
5306 t0 = tcg_temp_new();
5307 gen_addr_reg_index(ctx, t0);
5308 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5309 gen_addr_add(ctx, t0, t0, 8);
5310 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5311 tcg_temp_free(t0);
76a66253
JM		 5312}
5313
5314/* stfq */
5315GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5316{
01a4afeb 5317 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5318 TCGv t0;
5319 gen_set_access_type(ctx, ACCESS_FLOAT);
5320 t0 = tcg_temp_new();
5321 gen_addr_imm_index(ctx, t0, 0);
5322 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5323 gen_addr_add(ctx, t0, t0, 8);
5324 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5325 tcg_temp_free(t0);
76a66253
JM		 5326}
5327
5328/* stfqu */
5329GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5330{
5331 int ra = rA(ctx->opcode);
01a4afeb 5332 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5333 TCGv t0, t1;
5334 gen_set_access_type(ctx, ACCESS_FLOAT);
5335 t0 = tcg_temp_new();
5336 gen_addr_imm_index(ctx, t0, 0);
5337 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5338 t1 = tcg_temp_new();
5339 gen_addr_add(ctx, t1, t0, 8);
5340 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5341 tcg_temp_free(t1);
76a66253 5342 if (ra != 0)
01a4afeb
AJ		 5343 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5344 tcg_temp_free(t0);
76a66253
JM		 5345}
5346
5347/* stfqux */
5348GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5349{
5350 int ra = rA(ctx->opcode);
01a4afeb 5351 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5352 TCGv t0, t1;
5353 gen_set_access_type(ctx, ACCESS_FLOAT);
5354 t0 = tcg_temp_new();
5355 gen_addr_reg_index(ctx, t0);
5356 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5357 t1 = tcg_temp_new();
5358 gen_addr_add(ctx, t1, t0, 8);
5359 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5360 tcg_temp_free(t1);
76a66253 5361 if (ra != 0)
01a4afeb
AJ		 5362 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5363 tcg_temp_free(t0);
76a66253
JM		 5364}
5365
5366/* stfqx */
5367GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5368{
01a4afeb 5369 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5370 TCGv t0;
5371 gen_set_access_type(ctx, ACCESS_FLOAT);
5372 t0 = tcg_temp_new();
5373 gen_addr_reg_index(ctx, t0);
5374 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5375 gen_addr_add(ctx, t0, t0, 8);
5376 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5377 tcg_temp_free(t0);
76a66253
JM		 5378}
5379
5380/* BookE specific instructions */
2662a059 5381/* XXX: not implemented on 440 ? */
05332d70 5382GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5383{
5384 /* XXX: TODO */
e06fcd75 5385 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5386}
5387
2662a059 5388/* XXX: not implemented on 440 ? */
05332d70 5389GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5390{
5391#if defined(CONFIG_USER_ONLY)
e06fcd75 5392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5393#else
74d37793 5394 TCGv t0;
76db3ba4 5395 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5397 return;
5398 }
ec72e276 5399 t0 = tcg_temp_new();
76db3ba4 5400 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5401 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5402 tcg_temp_free(t0);
76a66253
JM		 5403#endif
5404}
5405
5406/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5407static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5408 int opc2, int opc3,
5409 int ra, int rb, int rt, int Rc)
76a66253 5410{
182608d4
AJ		 5411 TCGv t0, t1;
5412
a7812ae4
PB		 5413 t0 = tcg_temp_local_new();
5414 t1 = tcg_temp_local_new();
182608d4 5415
76a66253
JM		 5416 switch (opc3 & 0x0D) {
5417 case 0x05:
5418 /* macchw - macchw. - macchwo - macchwo. */
5419 /* macchws - macchws. - macchwso - macchwso. */
5420 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5421 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5422 /* mulchw - mulchw. */
182608d4
AJ		 5423 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5424 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5425 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5426 break;
5427 case 0x04:
5428 /* macchwu - macchwu. - macchwuo - macchwuo. */
5429 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5430 /* mulchwu - mulchwu. */
182608d4
AJ		 5431 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5432 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5433 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5434 break;
5435 case 0x01:
5436 /* machhw - machhw. - machhwo - machhwo. */
5437 /* machhws - machhws. - machhwso - machhwso. */
5438 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5439 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5440 /* mulhhw - mulhhw. */
182608d4
AJ		 5441 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5442 tcg_gen_ext16s_tl(t0, t0);
5443 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5444 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5445 break;
5446 case 0x00:
5447 /* machhwu - machhwu. - machhwuo - machhwuo. */
5448 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5449 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5450 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5451 tcg_gen_ext16u_tl(t0, t0);
5452 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5453 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5454 break;
5455 case 0x0D:
5456 /* maclhw - maclhw. - maclhwo - maclhwo. */
5457 /* maclhws - maclhws. - maclhwso - maclhwso. */
5458 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5459 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5460 /* mullhw - mullhw. */
182608d4
AJ		 5461 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5462 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5463 break;
5464 case 0x0C:
5465 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5466 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5467 /* mullhwu - mullhwu. */
182608d4
AJ		 5468 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5469 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5470 break;
5471 }
76a66253 5472 if (opc2 & 0x04) {
182608d4
AJ		 5473 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5474 tcg_gen_mul_tl(t1, t0, t1);
5475 if (opc2 & 0x02) {
5476 /* nmultiply-and-accumulate (0x0E) */
5477 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5478 } else {
5479 /* multiply-and-accumulate (0x0C) */
5480 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5481 }
5482
5483 if (opc3 & 0x12) {
5484 /* Check overflow and/or saturate */
5485 int l1 = gen_new_label();
5486
5487 if (opc3 & 0x10) {
5488 /* Start with XER OV disabled, the most likely case */
5489 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5490 }
5491 if (opc3 & 0x01) {
5492 /* Signed */
5493 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5494 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5495 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5496 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5497 if (opc3 & 0x02) {
182608d4
AJ		 5498 /* Saturate */
5499 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5500 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5501 }
5502 } else {
5503 /* Unsigned */
5504 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5505 if (opc3 & 0x02) {
182608d4
AJ		 5506 /* Saturate */
5507 tcg_gen_movi_tl(t0, UINT32_MAX);
5508 }
5509 }
5510 if (opc3 & 0x10) {
5511 /* Check overflow */
5512 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5513 }
5514 gen_set_label(l1);
5515 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5516 }
5517 } else {
5518 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5519 }
182608d4
AJ		 5520 tcg_temp_free(t0);
5521 tcg_temp_free(t1);
76a66253
JM		 5522 if (unlikely(Rc) != 0) {
5523 /* Update Rc0 */
182608d4 5524 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5525 }
5526}
5527
a750fc0b
JM		 5528#define GEN_MAC_HANDLER(name, opc2, opc3) \
5529GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5530{ \
5531 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5532 rD(ctx->opcode), Rc(ctx->opcode)); \
5533}
5534
5535/* macchw - macchw. */
a750fc0b 5536GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5537/* macchwo - macchwo. */
a750fc0b 5538GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5539/* macchws - macchws. */
a750fc0b 5540GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5541/* macchwso - macchwso. */
a750fc0b 5542GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5543/* macchwsu - macchwsu. */
a750fc0b 5544GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5545/* macchwsuo - macchwsuo. */
a750fc0b 5546GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5547/* macchwu - macchwu. */
a750fc0b 5548GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5549/* macchwuo - macchwuo. */
a750fc0b 5550GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5551/* machhw - machhw. */
a750fc0b 5552GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5553/* machhwo - machhwo. */
a750fc0b 5554GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5555/* machhws - machhws. */
a750fc0b 5556GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5557/* machhwso - machhwso. */
a750fc0b 5558GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5559/* machhwsu - machhwsu. */
a750fc0b 5560GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5561/* machhwsuo - machhwsuo. */
a750fc0b 5562GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5563/* machhwu - machhwu. */
a750fc0b 5564GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5565/* machhwuo - machhwuo. */
a750fc0b 5566GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5567/* maclhw - maclhw. */
a750fc0b 5568GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5569/* maclhwo - maclhwo. */
a750fc0b 5570GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5571/* maclhws - maclhws. */
a750fc0b 5572GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5573/* maclhwso - maclhwso. */
a750fc0b 5574GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5575/* maclhwu - maclhwu. */
a750fc0b 5576GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5577/* maclhwuo - maclhwuo. */
a750fc0b 5578GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5579/* maclhwsu - maclhwsu. */
a750fc0b 5580GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5581/* maclhwsuo - maclhwsuo. */
a750fc0b 5582GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5583/* nmacchw - nmacchw. */
a750fc0b 5584GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5585/* nmacchwo - nmacchwo. */
a750fc0b 5586GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5587/* nmacchws - nmacchws. */
a750fc0b 5588GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5589/* nmacchwso - nmacchwso. */
a750fc0b 5590GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5591/* nmachhw - nmachhw. */
a750fc0b 5592GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5593/* nmachhwo - nmachhwo. */
a750fc0b 5594GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5595/* nmachhws - nmachhws. */
a750fc0b 5596GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5597/* nmachhwso - nmachhwso. */
a750fc0b 5598GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5599/* nmaclhw - nmaclhw. */
a750fc0b 5600GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5601/* nmaclhwo - nmaclhwo. */
a750fc0b 5602GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5603/* nmaclhws - nmaclhws. */
a750fc0b 5604GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5605/* nmaclhwso - nmaclhwso. */
a750fc0b 5606GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5607
5608/* mulchw - mulchw. */
a750fc0b 5609GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5610/* mulchwu - mulchwu. */
a750fc0b 5611GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5612/* mulhhw - mulhhw. */
a750fc0b 5613GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5614/* mulhhwu - mulhhwu. */
a750fc0b 5615GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5616/* mullhw - mullhw. */
a750fc0b 5617GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5618/* mullhwu - mullhwu. */
a750fc0b 5619GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5620
5621/* mfdcr */
05332d70 5622GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5623{
5624#if defined(CONFIG_USER_ONLY)
e06fcd75 5625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5626#else
06dca6a7 5627 TCGv dcrn;
76db3ba4 5628 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5630 return;
5631 }
06dca6a7
AJ		 5632 /* NIP cannot be restored if the memory exception comes from an helper */
5633 gen_update_nip(ctx, ctx->nip - 4);
5634 dcrn = tcg_const_tl(SPR(ctx->opcode));
5635 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5636 tcg_temp_free(dcrn);
76a66253
JM		 5637#endif
5638}
5639
5640/* mtdcr */
05332d70 5641GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5642{
5643#if defined(CONFIG_USER_ONLY)
e06fcd75 5644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5645#else
06dca6a7 5646 TCGv dcrn;
76db3ba4 5647 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5649 return;
5650 }
06dca6a7
AJ		 5651 /* NIP cannot be restored if the memory exception comes from an helper */
5652 gen_update_nip(ctx, ctx->nip - 4);
5653 dcrn = tcg_const_tl(SPR(ctx->opcode));
5654 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5655 tcg_temp_free(dcrn);
a42bd6cc
JM		 5656#endif
5657}
5658
5659/* mfdcrx */
2662a059 5660/* XXX: not implemented on 440 ? */
05332d70 5661GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5662{
5663#if defined(CONFIG_USER_ONLY)
e06fcd75 5664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5665#else
76db3ba4 5666 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5668 return;
5669 }
06dca6a7
AJ		 5670 /* NIP cannot be restored if the memory exception comes from an helper */
5671 gen_update_nip(ctx, ctx->nip - 4);
5672 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5673 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5674#endif
5675}
5676
5677/* mtdcrx */
2662a059 5678/* XXX: not implemented on 440 ? */
05332d70 5679GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5680{
5681#if defined(CONFIG_USER_ONLY)
e06fcd75 5682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5683#else
76db3ba4 5684 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5686 return;
5687 }
06dca6a7
AJ		 5688 /* NIP cannot be restored if the memory exception comes from an helper */
5689 gen_update_nip(ctx, ctx->nip - 4);
5690 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5691 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5692#endif
5693}
5694
a750fc0b
JM		 5695/* mfdcrux (PPC 460) : user-mode access to DCR */
5696GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5697{
06dca6a7
AJ		 5698 /* NIP cannot be restored if the memory exception comes from an helper */
5699 gen_update_nip(ctx, ctx->nip - 4);
5700 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5701 /* Note: Rc update flag set leads to undefined state of Rc0 */
5702}
5703
5704/* mtdcrux (PPC 460) : user-mode access to DCR */
5705GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5706{
06dca6a7
AJ		 5707 /* NIP cannot be restored if the memory exception comes from an helper */
5708 gen_update_nip(ctx, ctx->nip - 4);
5709 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5710 /* Note: Rc update flag set leads to undefined state of Rc0 */
5711}
5712
76a66253
JM		 5713/* dccci */
5714GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5715{
5716#if defined(CONFIG_USER_ONLY)
e06fcd75 5717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5718#else
76db3ba4 5719 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5721 return;
5722 }
5723 /* interpreted as no-op */
5724#endif
5725}
5726
5727/* dcread */
5728GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5729{
5730#if defined(CONFIG_USER_ONLY)
e06fcd75 5731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5732#else
b61f2753 5733 TCGv EA, val;
76db3ba4 5734 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5735 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5736 return;
5737 }
76db3ba4 5738 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5739 EA = tcg_temp_new();
76db3ba4 5740 gen_addr_reg_index(ctx, EA);
a7812ae4 5741 val = tcg_temp_new();
76db3ba4 5742 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5743 tcg_temp_free(val);
5744 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5745 tcg_temp_free(EA);
76a66253
JM		 5746#endif
5747}
5748
5749/* icbt */
c7697e1f 5750GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5751{
5752 /* interpreted as no-op */
5753 /* XXX: specification say this is treated as a load by the MMU
5754 * but does not generate any exception
5755 */
5756}
5757
5758/* iccci */
5759GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5760{
5761#if defined(CONFIG_USER_ONLY)
e06fcd75 5762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5763#else
76db3ba4 5764 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5765 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5766 return;
5767 }
5768 /* interpreted as no-op */
5769#endif
5770}
5771
5772/* icread */
5773GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5774{
5775#if defined(CONFIG_USER_ONLY)
e06fcd75 5776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5777#else
76db3ba4 5778 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5780 return;
5781 }
5782 /* interpreted as no-op */
5783#endif
5784}
5785
76db3ba4 5786/* rfci (mem_idx only) */
c7697e1f 5787GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5788{
5789#if defined(CONFIG_USER_ONLY)
e06fcd75 5790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5791#else
76db3ba4 5792 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5794 return;
5795 }
5796 /* Restore CPU state */
d72a19f7 5797 gen_helper_40x_rfci();
e06fcd75 5798 gen_sync_exception(ctx);
a42bd6cc
JM		 5799#endif
5800}
5801
5802GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5803{
5804#if defined(CONFIG_USER_ONLY)
e06fcd75 5805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5806#else
76db3ba4 5807 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5809 return;
5810 }
5811 /* Restore CPU state */
d72a19f7 5812 gen_helper_rfci();
e06fcd75 5813 gen_sync_exception(ctx);
a42bd6cc
JM		 5814#endif
5815}
5816
5817/* BookE specific */
2662a059 5818/* XXX: not implemented on 440 ? */
05332d70 5819GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5820{
5821#if defined(CONFIG_USER_ONLY)
e06fcd75 5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5823#else
76db3ba4 5824 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5826 return;
5827 }
5828 /* Restore CPU state */
d72a19f7 5829 gen_helper_rfdi();
e06fcd75 5830 gen_sync_exception(ctx);
76a66253
JM		 5831#endif
5832}
5833
2662a059 5834/* XXX: not implemented on 440 ? */
a750fc0b 5835GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5836{
5837#if defined(CONFIG_USER_ONLY)
e06fcd75 5838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5839#else
76db3ba4 5840 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5842 return;
5843 }
5844 /* Restore CPU state */
d72a19f7 5845 gen_helper_rfmci();
e06fcd75 5846 gen_sync_exception(ctx);
a42bd6cc
JM		 5847#endif
5848}
5eb7995e 5849
d9bce9d9 5850/* TLB management - PowerPC 405 implementation */
76a66253 5851/* tlbre */
c7697e1f 5852GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5853{
5854#if defined(CONFIG_USER_ONLY)
e06fcd75 5855 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5856#else
76db3ba4 5857 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5859 return;
5860 }
5861 switch (rB(ctx->opcode)) {
5862 case 0:
74d37793 5863 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5864 break;
5865 case 1:
74d37793 5866 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5867 break;
5868 default:
e06fcd75 5869 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5870 break;
9a64fbe4 5871 }
76a66253
JM		 5872#endif
5873}
5874
d9bce9d9 5875/* tlbsx - tlbsx. */
c7697e1f 5876GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5877{
5878#if defined(CONFIG_USER_ONLY)
e06fcd75 5879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5880#else
74d37793 5881 TCGv t0;
76db3ba4 5882 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5884 return;
5885 }
74d37793 5886 t0 = tcg_temp_new();
76db3ba4 5887 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5888 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5889 tcg_temp_free(t0);
5890 if (Rc(ctx->opcode)) {
5891 int l1 = gen_new_label();
5892 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5893 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5894 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5895 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5896 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5897 gen_set_label(l1);
5898 }
76a66253 5899#endif
79aceca5
FB		 5900}
5901
76a66253 5902/* tlbwe */
c7697e1f 5903GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5904{
76a66253 5905#if defined(CONFIG_USER_ONLY)
e06fcd75 5906 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5907#else
76db3ba4 5908 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5909 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5910 return;
5911 }
5912 switch (rB(ctx->opcode)) {
5913 case 0:
74d37793 5914 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5915 break;
5916 case 1:
74d37793 5917 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5918 break;
5919 default:
e06fcd75 5920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5921 break;
9a64fbe4 5922 }
76a66253
JM		 5923#endif
5924}
5925
a4bb6c3e 5926/* TLB management - PowerPC 440 implementation */
5eb7995e 5927/* tlbre */
c7697e1f 5928GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5929{
5930#if defined(CONFIG_USER_ONLY)
e06fcd75 5931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5932#else
76db3ba4 5933 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5934 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5935 return;
5936 }
5937 switch (rB(ctx->opcode)) {
5938 case 0:
5eb7995e 5939 case 1:
5eb7995e 5940 case 2:
74d37793
AJ		 5941 {
5942 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5943 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5944 tcg_temp_free_i32(t0);
5945 }
5eb7995e
JM		 5946 break;
5947 default:
e06fcd75 5948 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 5949 break;
5950 }
5951#endif
5952}
5953
5954/* tlbsx - tlbsx. */
c7697e1f 5955GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5956{
5957#if defined(CONFIG_USER_ONLY)
e06fcd75 5958 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5959#else
74d37793 5960 TCGv t0;
76db3ba4 5961 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5962 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5963 return;
5964 }
74d37793 5965 t0 = tcg_temp_new();
76db3ba4 5966 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5967 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5968 tcg_temp_free(t0);
5969 if (Rc(ctx->opcode)) {
5970 int l1 = gen_new_label();
5971 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5972 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5973 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5974 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5975 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5976 gen_set_label(l1);
5977 }
5eb7995e
JM		 5978#endif
5979}
5980
5981/* tlbwe */
c7697e1f 5982GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5983{
5984#if defined(CONFIG_USER_ONLY)
e06fcd75 5985 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5986#else
76db3ba4 5987 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5988 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5989 return;
5990 }
5991 switch (rB(ctx->opcode)) {
5992 case 0:
5eb7995e 5993 case 1:
5eb7995e 5994 case 2:
74d37793
AJ		 5995 {
5996 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5997 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5998 tcg_temp_free_i32(t0);
5999 }
5eb7995e
JM		 6000 break;
6001 default:
e06fcd75 6002 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6003 break;
6004 }
6005#endif
6006}
6007
76a66253 6008/* wrtee */
05332d70 6009GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6010{
6011#if defined(CONFIG_USER_ONLY)
e06fcd75 6012 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6013#else
6527f6ea 6014 TCGv t0;
76db3ba4 6015 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6016 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6017 return;
6018 }
6527f6ea
AJ		 6019 t0 = tcg_temp_new();
6020 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6021 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6022 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6023 tcg_temp_free(t0);
dee96f6c
JM		 6024 /* Stop translation to have a chance to raise an exception
6025 * if we just set msr_ee to 1
6026 */
e06fcd75 6027 gen_stop_exception(ctx);
76a66253
JM		 6028#endif
6029}
6030
6031/* wrteei */
05332d70 6032GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6033{
6034#if defined(CONFIG_USER_ONLY)
e06fcd75 6035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6036#else
76db3ba4 6037 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6038 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6039 return;
6040 }
6527f6ea
AJ		 6041 if (ctx->opcode & 0x00010000) {
6042 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6043 /* Stop translation to have a chance to raise an exception */
e06fcd75 6044 gen_stop_exception(ctx);
6527f6ea 6045 } else {
1b6e5f99 6046 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6047 }
76a66253
JM		 6048#endif
6049}
6050
08e46e54 6051/* PowerPC 440 specific instructions */
76a66253
JM		 6052/* dlmzb */
6053GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6054{
ef0d51af
AJ		 6055 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6056 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6057 cpu_gpr[rB(ctx->opcode)], t0);
6058 tcg_temp_free_i32(t0);
76a66253
JM		 6059}
6060
6061/* mbar replaces eieio on 440 */
26370046 6062GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
76a66253
JM		 6063{
6064 /* interpreted as no-op */
6065}
6066
6067/* msync replaces sync on 440 */
0db1b20e 6068GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6069{
6070 /* interpreted as no-op */
6071}
6072
6073/* icbt */
c7697e1f 6074GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6075{
6076 /* interpreted as no-op */
6077 /* XXX: specification say this is treated as a load by the MMU
6078 * but does not generate any exception
6079 */
79aceca5
FB		 6080}
6081
a9d9eb8f
JM		 6082/*** Altivec vector extension ***/
6083/* Altivec registers moves */
a9d9eb8f 6084
564e571a
AJ		 6085static always_inline TCGv_ptr gen_avr_ptr(int reg)
6086{
e4704b3b 6087 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6088 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6089 return r;
6090}
6091
a9d9eb8f 6092#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6093GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6094{ \
fe1e5c53 6095 TCGv EA; \
a9d9eb8f 6096 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6097 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6098 return; \
6099 } \
76db3ba4 6100 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6101 EA = tcg_temp_new(); \
76db3ba4 6102 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6103 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6104 if (ctx->le_mode) { \
6105 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6106 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6107 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6108 } else { \
76db3ba4 6109 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6110 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6111 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6112 } \
6113 tcg_temp_free(EA); \
a9d9eb8f
JM		 6114}
6115
6116#define GEN_VR_STX(name, opc2, opc3) \
6117GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6118{ \
fe1e5c53 6119 TCGv EA; \
a9d9eb8f 6120 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6121 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6122 return; \
6123 } \
76db3ba4 6124 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6125 EA = tcg_temp_new(); \
76db3ba4 6126 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6127 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6128 if (ctx->le_mode) { \
6129 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6130 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6131 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6132 } else { \
76db3ba4 6133 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6134 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6135 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6136 } \
6137 tcg_temp_free(EA); \
a9d9eb8f
JM		 6138}
6139
cbfb6ae9
AJ		 6140#define GEN_VR_LVE(name, opc2, opc3) \
6141 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6142 { \
6143 TCGv EA; \
6144 TCGv_ptr rs; \
6145 if (unlikely(!ctx->altivec_enabled)) { \
6146 gen_exception(ctx, POWERPC_EXCP_VPU); \
6147 return; \
6148 } \
6149 gen_set_access_type(ctx, ACCESS_INT); \
6150 EA = tcg_temp_new(); \
6151 gen_addr_reg_index(ctx, EA); \
6152 rs = gen_avr_ptr(rS(ctx->opcode)); \
6153 gen_helper_lve##name (rs, EA); \
6154 tcg_temp_free(EA); \
6155 tcg_temp_free_ptr(rs); \
6156 }
6157
6158#define GEN_VR_STVE(name, opc2, opc3) \
6159 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6160 { \
6161 TCGv EA; \
6162 TCGv_ptr rs; \
6163 if (unlikely(!ctx->altivec_enabled)) { \
6164 gen_exception(ctx, POWERPC_EXCP_VPU); \
6165 return; \
6166 } \
6167 gen_set_access_type(ctx, ACCESS_INT); \
6168 EA = tcg_temp_new(); \
6169 gen_addr_reg_index(ctx, EA); \
6170 rs = gen_avr_ptr(rS(ctx->opcode)); \
6171 gen_helper_stve##name (rs, EA); \
6172 tcg_temp_free(EA); \
6173 tcg_temp_free_ptr(rs); \
6174 }
6175
fe1e5c53 6176GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6177/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6178GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6179
cbfb6ae9
AJ		 6180GEN_VR_LVE(bx, 0x07, 0x00);
6181GEN_VR_LVE(hx, 0x07, 0x01);
6182GEN_VR_LVE(wx, 0x07, 0x02);
6183
fe1e5c53 6184GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6185/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6186GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6187
cbfb6ae9
AJ		 6188GEN_VR_STVE(bx, 0x07, 0x04);
6189GEN_VR_STVE(hx, 0x07, 0x05);
6190GEN_VR_STVE(wx, 0x07, 0x06);
6191
bf8d8ded
AJ		 6192GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6193{
6194 TCGv_ptr rd;
6195 TCGv EA;
6196 if (unlikely(!ctx->altivec_enabled)) {
6197 gen_exception(ctx, POWERPC_EXCP_VPU);
6198 return;
6199 }
6200 EA = tcg_temp_new();
6201 gen_addr_reg_index(ctx, EA);
6202 rd = gen_avr_ptr(rD(ctx->opcode));
6203 gen_helper_lvsl(rd, EA);
6204 tcg_temp_free(EA);
6205 tcg_temp_free_ptr(rd);
6206}
6207
6208GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6209{
6210 TCGv_ptr rd;
6211 TCGv EA;
6212 if (unlikely(!ctx->altivec_enabled)) {
6213 gen_exception(ctx, POWERPC_EXCP_VPU);
6214 return;
6215 }
6216 EA = tcg_temp_new();
6217 gen_addr_reg_index(ctx, EA);
6218 rd = gen_avr_ptr(rD(ctx->opcode));
6219 gen_helper_lvsr(rd, EA);
6220 tcg_temp_free(EA);
6221 tcg_temp_free_ptr(rd);
6222}
6223
785f451b
AJ		 6224GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6225{
6226 TCGv_i32 t;
6227 if (unlikely(!ctx->altivec_enabled)) {
6228 gen_exception(ctx, POWERPC_EXCP_VPU);
6229 return;
6230 }
6231 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6232 t = tcg_temp_new_i32();
6233 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6234 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6235 tcg_temp_free_i32(t);
785f451b
AJ		 6236}
6237
6238GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6239{
6e87b7c7 6240 TCGv_ptr p;
785f451b
AJ		 6241 if (unlikely(!ctx->altivec_enabled)) {
6242 gen_exception(ctx, POWERPC_EXCP_VPU);
6243 return;
6244 }
6e87b7c7
AJ		 6245 p = gen_avr_ptr(rD(ctx->opcode));
6246 gen_helper_mtvscr(p);
6247 tcg_temp_free_ptr(p);
785f451b
AJ		 6248}
6249
7a9b96cf
AJ		 6250/* Logical operations */
6251#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6252GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6253{ \
6254 if (unlikely(!ctx->altivec_enabled)) { \
6255 gen_exception(ctx, POWERPC_EXCP_VPU); \
6256 return; \
6257 } \
6258 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6259 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6260}
6261
6262GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6263GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6264GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6265GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6266GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6267
8e27dd6f
AJ		 6268#define GEN_VXFORM(name, opc2, opc3) \
6269GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6270{ \
6271 TCGv_ptr ra, rb, rd; \
6272 if (unlikely(!ctx->altivec_enabled)) { \
6273 gen_exception(ctx, POWERPC_EXCP_VPU); \
6274 return; \
6275 } \
6276 ra = gen_avr_ptr(rA(ctx->opcode)); \
6277 rb = gen_avr_ptr(rB(ctx->opcode)); \
6278 rd = gen_avr_ptr(rD(ctx->opcode)); \
6279 gen_helper_##name (rd, ra, rb); \
6280 tcg_temp_free_ptr(ra); \
6281 tcg_temp_free_ptr(rb); \
6282 tcg_temp_free_ptr(rd); \
6283}
6284
7872c51c
AJ		 6285GEN_VXFORM(vaddubm, 0, 0);
6286GEN_VXFORM(vadduhm, 0, 1);
6287GEN_VXFORM(vadduwm, 0, 2);
6288GEN_VXFORM(vsububm, 0, 16);
6289GEN_VXFORM(vsubuhm, 0, 17);
6290GEN_VXFORM(vsubuwm, 0, 18);
e4039339
AJ		 6291GEN_VXFORM(vmaxub, 1, 0);
6292GEN_VXFORM(vmaxuh, 1, 1);
6293GEN_VXFORM(vmaxuw, 1, 2);
6294GEN_VXFORM(vmaxsb, 1, 4);
6295GEN_VXFORM(vmaxsh, 1, 5);
6296GEN_VXFORM(vmaxsw, 1, 6);
6297GEN_VXFORM(vminub, 1, 8);
6298GEN_VXFORM(vminuh, 1, 9);
6299GEN_VXFORM(vminuw, 1, 10);
6300GEN_VXFORM(vminsb, 1, 12);
6301GEN_VXFORM(vminsh, 1, 13);
6302GEN_VXFORM(vminsw, 1, 14);
fab3cbe9
AJ		 6303GEN_VXFORM(vavgub, 1, 16);
6304GEN_VXFORM(vavguh, 1, 17);
6305GEN_VXFORM(vavguw, 1, 18);
6306GEN_VXFORM(vavgsb, 1, 20);
6307GEN_VXFORM(vavgsh, 1, 21);
6308GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 6309GEN_VXFORM(vmrghb, 6, 0);
6310GEN_VXFORM(vmrghh, 6, 1);
6311GEN_VXFORM(vmrghw, 6, 2);
6312GEN_VXFORM(vmrglb, 6, 4);
6313GEN_VXFORM(vmrglh, 6, 5);
6314GEN_VXFORM(vmrglw, 6, 6);
2c277908
AJ		 6315GEN_VXFORM(vmuloub, 4, 0);
6316GEN_VXFORM(vmulouh, 4, 1);
6317GEN_VXFORM(vmulosb, 4, 4);
6318GEN_VXFORM(vmulosh, 4, 5);
6319GEN_VXFORM(vmuleub, 4, 8);
6320GEN_VXFORM(vmuleuh, 4, 9);
6321GEN_VXFORM(vmulesb, 4, 12);
6322GEN_VXFORM(vmulesh, 4, 13);
d79f0809
AJ		 6323GEN_VXFORM(vslb, 2, 4);
6324GEN_VXFORM(vslh, 2, 5);
6325GEN_VXFORM(vslw, 2, 6);
07ef34c3
AJ		 6326GEN_VXFORM(vsrb, 2, 8);
6327GEN_VXFORM(vsrh, 2, 9);
6328GEN_VXFORM(vsrw, 2, 10);
6329GEN_VXFORM(vsrab, 2, 12);
6330GEN_VXFORM(vsrah, 2, 13);
6331GEN_VXFORM(vsraw, 2, 14);
7b239bec
AJ		 6332GEN_VXFORM(vslo, 6, 16);
6333GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 6334GEN_VXFORM(vaddcuw, 0, 6);
6335GEN_VXFORM(vsubcuw, 0, 22);
5ab09f33
AJ		 6336GEN_VXFORM(vaddubs, 0, 8);
6337GEN_VXFORM(vadduhs, 0, 9);
6338GEN_VXFORM(vadduws, 0, 10);
6339GEN_VXFORM(vaddsbs, 0, 12);
6340GEN_VXFORM(vaddshs, 0, 13);
6341GEN_VXFORM(vaddsws, 0, 14);
6342GEN_VXFORM(vsububs, 0, 24);
6343GEN_VXFORM(vsubuhs, 0, 25);
6344GEN_VXFORM(vsubuws, 0, 26);
6345GEN_VXFORM(vsubsbs, 0, 28);
6346GEN_VXFORM(vsubshs, 0, 29);
6347GEN_VXFORM(vsubsws, 0, 30);
5e1d0985
AJ		 6348GEN_VXFORM(vrlb, 2, 0);
6349GEN_VXFORM(vrlh, 2, 1);
6350GEN_VXFORM(vrlw, 2, 2);
d9430add
AJ		 6351GEN_VXFORM(vsl, 2, 7);
6352GEN_VXFORM(vsr, 2, 11);
5335a145
AJ		 6353GEN_VXFORM(vpkuhum, 7, 0);
6354GEN_VXFORM(vpkuwum, 7, 1);
6355GEN_VXFORM(vpkuhus, 7, 2);
6356GEN_VXFORM(vpkuwus, 7, 3);
6357GEN_VXFORM(vpkshus, 7, 4);
6358GEN_VXFORM(vpkswus, 7, 5);
6359GEN_VXFORM(vpkshss, 7, 6);
6360GEN_VXFORM(vpkswss, 7, 7);
1dd9ffb9 6361GEN_VXFORM(vpkpx, 7, 12);
8142cddd
AJ		 6362GEN_VXFORM(vsum4ubs, 4, 24);
6363GEN_VXFORM(vsum4sbs, 4, 28);
6364GEN_VXFORM(vsum4shs, 4, 25);
6365GEN_VXFORM(vsum2sws, 4, 26);
6366GEN_VXFORM(vsumsws, 4, 30);
56fdd213
AJ		 6367GEN_VXFORM(vaddfp, 5, 0);
6368GEN_VXFORM(vsubfp, 5, 1);
1536ff64
AJ		 6369GEN_VXFORM(vmaxfp, 5, 16);
6370GEN_VXFORM(vminfp, 5, 17);
fab3cbe9 6371
0cbcd906
AJ		 6372#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6373 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6374 { \
6375 TCGv_ptr ra, rb, rd; \
6376 if (unlikely(!ctx->altivec_enabled)) { \
6377 gen_exception(ctx, POWERPC_EXCP_VPU); \
6378 return; \
6379 } \
6380 ra = gen_avr_ptr(rA(ctx->opcode)); \
6381 rb = gen_avr_ptr(rB(ctx->opcode)); \
6382 rd = gen_avr_ptr(rD(ctx->opcode)); \
6383 gen_helper_##opname (rd, ra, rb); \
6384 tcg_temp_free_ptr(ra); \
6385 tcg_temp_free_ptr(rb); \
6386 tcg_temp_free_ptr(rd); \
6387 }
6388
6389#define GEN_VXRFORM(name, opc2, opc3) \
6390 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6391 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6392
1add6e23
AJ		 6393GEN_VXRFORM(vcmpequb, 3, 0)
6394GEN_VXRFORM(vcmpequh, 3, 1)
6395GEN_VXRFORM(vcmpequw, 3, 2)
6396GEN_VXRFORM(vcmpgtsb, 3, 12)
6397GEN_VXRFORM(vcmpgtsh, 3, 13)
6398GEN_VXRFORM(vcmpgtsw, 3, 14)
6399GEN_VXRFORM(vcmpgtub, 3, 8)
6400GEN_VXRFORM(vcmpgtuh, 3, 9)
6401GEN_VXRFORM(vcmpgtuw, 3, 10)
819ca121
AJ		 6402GEN_VXRFORM(vcmpeqfp, 3, 3)
6403GEN_VXRFORM(vcmpgefp, 3, 7)
6404GEN_VXRFORM(vcmpgtfp, 3, 11)
6405GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 6406
c026766b
AJ		 6407#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6408 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6409 { \
6410 TCGv_ptr rd; \
6411 TCGv_i32 simm; \
6412 if (unlikely(!ctx->altivec_enabled)) { \
6413 gen_exception(ctx, POWERPC_EXCP_VPU); \
6414 return; \
6415 } \
6416 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6417 rd = gen_avr_ptr(rD(ctx->opcode)); \
6418 gen_helper_##name (rd, simm); \
6419 tcg_temp_free_i32(simm); \
6420 tcg_temp_free_ptr(rd); \
6421 }
6422
6423GEN_VXFORM_SIMM(vspltisb, 6, 12);
6424GEN_VXFORM_SIMM(vspltish, 6, 13);
6425GEN_VXFORM_SIMM(vspltisw, 6, 14);
6426
de5f2484
AJ		 6427#define GEN_VXFORM_NOA(name, opc2, opc3) \
6428 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6429 { \
6430 TCGv_ptr rb, rd; \
6431 if (unlikely(!ctx->altivec_enabled)) { \
6432 gen_exception(ctx, POWERPC_EXCP_VPU); \
6433 return; \
6434 } \
6435 rb = gen_avr_ptr(rB(ctx->opcode)); \
6436 rd = gen_avr_ptr(rD(ctx->opcode)); \
6437 gen_helper_##name (rd, rb); \
6438 tcg_temp_free_ptr(rb); \
6439 tcg_temp_free_ptr(rd); \
6440 }
6441
6cf1c6e5
AJ		 6442GEN_VXFORM_NOA(vupkhsb, 7, 8);
6443GEN_VXFORM_NOA(vupkhsh, 7, 9);
6444GEN_VXFORM_NOA(vupklsb, 7, 10);
6445GEN_VXFORM_NOA(vupklsh, 7, 11);
79f85c3a
AJ		 6446GEN_VXFORM_NOA(vupkhpx, 7, 13);
6447GEN_VXFORM_NOA(vupklpx, 7, 15);
bdfbac35 6448GEN_VXFORM_NOA(vrefp, 5, 4);
071fc3b1 6449GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
b580763f 6450GEN_VXFORM_NOA(vlogefp, 5, 7);
f6b19645
AJ		 6451GEN_VXFORM_NOA(vrfim, 5, 8);
6452GEN_VXFORM_NOA(vrfin, 5, 9);
6453GEN_VXFORM_NOA(vrfip, 5, 10);
6454GEN_VXFORM_NOA(vrfiz, 5, 11);
79f85c3a 6455
21d21583
AJ		 6456#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6457 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6458 { \
6459 TCGv_ptr rd; \
6460 TCGv_i32 simm; \
6461 if (unlikely(!ctx->altivec_enabled)) { \
6462 gen_exception(ctx, POWERPC_EXCP_VPU); \
6463 return; \
6464 } \
6465 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6466 rd = gen_avr_ptr(rD(ctx->opcode)); \
6467 gen_helper_##name (rd, simm); \
6468 tcg_temp_free_i32(simm); \
6469 tcg_temp_free_ptr(rd); \
6470 }
6471
27a4edb3
AJ		 6472#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6473 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6474 { \
6475 TCGv_ptr rb, rd; \
6476 TCGv_i32 uimm; \
6477 if (unlikely(!ctx->altivec_enabled)) { \
6478 gen_exception(ctx, POWERPC_EXCP_VPU); \
6479 return; \
6480 } \
6481 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6482 rb = gen_avr_ptr(rB(ctx->opcode)); \
6483 rd = gen_avr_ptr(rD(ctx->opcode)); \
6484 gen_helper_##name (rd, rb, uimm); \
6485 tcg_temp_free_i32(uimm); \
6486 tcg_temp_free_ptr(rb); \
6487 tcg_temp_free_ptr(rd); \
6488 }
6489
e4e6bee7
AJ		 6490GEN_VXFORM_UIMM(vspltb, 6, 8);
6491GEN_VXFORM_UIMM(vsplth, 6, 9);
6492GEN_VXFORM_UIMM(vspltw, 6, 10);
e140632e
AJ		 6493GEN_VXFORM_UIMM(vcfux, 5, 12);
6494GEN_VXFORM_UIMM(vcfsx, 5, 13);
875b31db
AJ		 6495GEN_VXFORM_UIMM(vctuxs, 5, 14);
6496GEN_VXFORM_UIMM(vctsxs, 5, 15);
e4e6bee7 6497
cd633b10
AJ		 6498GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6499{
6500 TCGv_ptr ra, rb, rd;
fce5ecb7 6501 TCGv_i32 sh;
cd633b10
AJ		 6502 if (unlikely(!ctx->altivec_enabled)) {
6503 gen_exception(ctx, POWERPC_EXCP_VPU);
6504 return;
6505 }
6506 ra = gen_avr_ptr(rA(ctx->opcode));
6507 rb = gen_avr_ptr(rB(ctx->opcode));
6508 rd = gen_avr_ptr(rD(ctx->opcode));
6509 sh = tcg_const_i32(VSH(ctx->opcode));
6510 gen_helper_vsldoi (rd, ra, rb, sh);
6511 tcg_temp_free_ptr(ra);
6512 tcg_temp_free_ptr(rb);
6513 tcg_temp_free_ptr(rd);
fce5ecb7 6514 tcg_temp_free_i32(sh);
cd633b10
AJ		 6515}
6516
707cec33
AJ		 6517#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6518 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6519 { \
6520 TCGv_ptr ra, rb, rc, rd; \
6521 if (unlikely(!ctx->altivec_enabled)) { \
6522 gen_exception(ctx, POWERPC_EXCP_VPU); \
6523 return; \
6524 } \
6525 ra = gen_avr_ptr(rA(ctx->opcode)); \
6526 rb = gen_avr_ptr(rB(ctx->opcode)); \
6527 rc = gen_avr_ptr(rC(ctx->opcode)); \
6528 rd = gen_avr_ptr(rD(ctx->opcode)); \
6529 if (Rc(ctx->opcode)) { \
6530 gen_helper_##name1 (rd, ra, rb, rc); \
6531 } else { \
6532 gen_helper_##name0 (rd, ra, rb, rc); \
6533 } \
6534 tcg_temp_free_ptr(ra); \
6535 tcg_temp_free_ptr(rb); \
6536 tcg_temp_free_ptr(rc); \
6537 tcg_temp_free_ptr(rd); \
6538 }
6539
b161ae27
AJ		 6540GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6541
bcd2ee23
AJ		 6542GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6543{
6544 TCGv_ptr ra, rb, rc, rd;
6545 if (unlikely(!ctx->altivec_enabled)) {
6546 gen_exception(ctx, POWERPC_EXCP_VPU);
6547 return;
6548 }
6549 ra = gen_avr_ptr(rA(ctx->opcode));
6550 rb = gen_avr_ptr(rB(ctx->opcode));
6551 rc = gen_avr_ptr(rC(ctx->opcode));
6552 rd = gen_avr_ptr(rD(ctx->opcode));
6553 gen_helper_vmladduhm(rd, ra, rb, rc);
6554 tcg_temp_free_ptr(ra);
6555 tcg_temp_free_ptr(rb);
6556 tcg_temp_free_ptr(rc);
6557 tcg_temp_free_ptr(rd);
6558}
6559
b04ae981 6560GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 6561GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 6562GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 6563GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 6564GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 6565
0487d6a8 6566/*** SPE extension ***/
0487d6a8 6567/* Register moves */
3cd7d1dd 6568
a7812ae4 6569static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6570#if defined(TARGET_PPC64)
6571 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6572#else
36aa55dc 6573 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6574#endif
f78fb44e 6575}
3cd7d1dd 6576
a7812ae4 6577static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6578#if defined(TARGET_PPC64)
6579 tcg_gen_mov_i64(cpu_gpr[reg], t);
6580#else
a7812ae4 6581 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6582 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6583 tcg_gen_shri_i64(tmp, t, 32);
6584 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6585 tcg_temp_free_i64(tmp);
3cd7d1dd 6586#endif
f78fb44e 6587}
3cd7d1dd 6588
0487d6a8
JM		 6589#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6590GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6591{ \
6592 if (Rc(ctx->opcode)) \
6593 gen_##name1(ctx); \
6594 else \
6595 gen_##name0(ctx); \
6596}
6597
6598/* Handler for undefined SPE opcodes */
b068d6a7 6599static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6600{
e06fcd75 6601 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 6602}
6603
57951c27
AJ		 6604/* SPE logic */
6605#if defined(TARGET_PPC64)
6606#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6607static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6608{ \
6609 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6610 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6611 return; \
6612 } \
57951c27
AJ		 6613 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6614 cpu_gpr[rB(ctx->opcode)]); \
6615}
6616#else
6617#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6618static always_inline void gen_##name (DisasContext *ctx) \
6619{ \
6620 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6621 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6622 return; \
6623 } \
6624 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6625 cpu_gpr[rB(ctx->opcode)]); \
6626 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6627 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6628}
57951c27
AJ		 6629#endif
6630
6631GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6632GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6633GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6634GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6635GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6636GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6637GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6638GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6639
57951c27
AJ		 6640/* SPE logic immediate */
6641#if defined(TARGET_PPC64)
6642#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6643static always_inline void gen_##name (DisasContext *ctx) \
6644{ \
6645 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6646 gen_exception(ctx, POWERPC_EXCP_APU); \
3d3a6a0a
AJ		 6647 return; \
6648 } \
a7812ae4
PB		 6649 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6650 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6651 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6652 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6653 tcg_opi(t0, t0, rB(ctx->opcode)); \
6654 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6655 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6656 tcg_temp_free_i64(t2); \
57951c27
AJ		 6657 tcg_opi(t1, t1, rB(ctx->opcode)); \
6658 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6659 tcg_temp_free_i32(t0); \
6660 tcg_temp_free_i32(t1); \
3d3a6a0a 6661}
57951c27
AJ		 6662#else
6663#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6664static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6665{ \
6666 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6667 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6668 return; \
6669 } \
57951c27
AJ		 6670 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6671 rB(ctx->opcode)); \
6672 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6673 rB(ctx->opcode)); \
0487d6a8 6674}
57951c27
AJ		 6675#endif
6676GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6677GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6678GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6679GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6680
57951c27
AJ		 6681/* SPE arithmetic */
6682#if defined(TARGET_PPC64)
6683#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6684static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6685{ \
6686 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6687 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6688 return; \
6689 } \
a7812ae4
PB		 6690 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6691 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6692 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6693 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6694 tcg_op(t0, t0); \
6695 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6696 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6697 tcg_temp_free_i64(t2); \
57951c27
AJ		 6698 tcg_op(t1, t1); \
6699 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6700 tcg_temp_free_i32(t0); \
6701 tcg_temp_free_i32(t1); \
0487d6a8 6702}
57951c27 6703#else
a7812ae4 6704#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6705static always_inline void gen_##name (DisasContext *ctx) \
6706{ \
6707 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6708 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6709 return; \
6710 } \
6711 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6712 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6713}
6714#endif
0487d6a8 6715
a7812ae4 6716static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6717{
6718 int l1 = gen_new_label();
6719 int l2 = gen_new_label();
0487d6a8 6720
57951c27
AJ		 6721 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6722 tcg_gen_neg_i32(ret, arg1);
6723 tcg_gen_br(l2);
6724 gen_set_label(l1);
a7812ae4 6725 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6726 gen_set_label(l2);
6727}
6728GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6729GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6730GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6731GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6732static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6733{
57951c27
AJ		 6734 tcg_gen_addi_i32(ret, arg1, 0x8000);
6735 tcg_gen_ext16u_i32(ret, ret);
6736}
6737GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6738GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6739GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6740
57951c27
AJ		 6741#if defined(TARGET_PPC64)
6742#define GEN_SPEOP_ARITH2(name, tcg_op) \
6743static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6744{ \
6745 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6746 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6747 return; \
6748 } \
a7812ae4
PB		 6749 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6750 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6751 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
501e23c4 6752 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6753 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6754 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6755 tcg_op(t0, t0, t2); \
6756 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6757 tcg_gen_trunc_i64_i32(t1, t3); \
6758 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6759 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6760 tcg_temp_free_i64(t3); \
57951c27 6761 tcg_op(t1, t1, t2); \
a7812ae4 6762 tcg_temp_free_i32(t2); \
57951c27 6763 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6764 tcg_temp_free_i32(t0); \
6765 tcg_temp_free_i32(t1); \
0487d6a8 6766}
57951c27
AJ		 6767#else
6768#define GEN_SPEOP_ARITH2(name, tcg_op) \
6769static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6770{ \
6771 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6772 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6773 return; \
6774 } \
57951c27
AJ		 6775 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6776 cpu_gpr[rB(ctx->opcode)]); \
6777 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6778 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6779}
57951c27 6780#endif
0487d6a8 6781
a7812ae4 6782static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6783{
a7812ae4 6784 TCGv_i32 t0;
57951c27 6785 int l1, l2;
0487d6a8 6786
57951c27
AJ		 6787 l1 = gen_new_label();
6788 l2 = gen_new_label();
a7812ae4 6789 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6790 /* No error here: 6 bits are used */
6791 tcg_gen_andi_i32(t0, arg2, 0x3F);
6792 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6793 tcg_gen_shr_i32(ret, arg1, t0);
6794 tcg_gen_br(l2);
6795 gen_set_label(l1);
6796 tcg_gen_movi_i32(ret, 0);
6797 tcg_gen_br(l2);
a7812ae4 6798 tcg_temp_free_i32(t0);
57951c27
AJ		 6799}
6800GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6801static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6802{
a7812ae4 6803 TCGv_i32 t0;
57951c27
AJ		 6804 int l1, l2;
6805
6806 l1 = gen_new_label();
6807 l2 = gen_new_label();
a7812ae4 6808 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6809 /* No error here: 6 bits are used */
6810 tcg_gen_andi_i32(t0, arg2, 0x3F);
6811 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6812 tcg_gen_sar_i32(ret, arg1, t0);
6813 tcg_gen_br(l2);
6814 gen_set_label(l1);
6815 tcg_gen_movi_i32(ret, 0);
6816 tcg_gen_br(l2);
a7812ae4 6817 tcg_temp_free_i32(t0);
57951c27
AJ		 6818}
6819GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6820static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6821{
a7812ae4 6822 TCGv_i32 t0;
57951c27
AJ		 6823 int l1, l2;
6824
6825 l1 = gen_new_label();
6826 l2 = gen_new_label();
a7812ae4 6827 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6828 /* No error here: 6 bits are used */
6829 tcg_gen_andi_i32(t0, arg2, 0x3F);
6830 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6831 tcg_gen_shl_i32(ret, arg1, t0);
6832 tcg_gen_br(l2);
6833 gen_set_label(l1);
6834 tcg_gen_movi_i32(ret, 0);
6835 tcg_gen_br(l2);
a7812ae4 6836 tcg_temp_free_i32(t0);
57951c27
AJ		 6837}
6838GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6839static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6840{
a7812ae4 6841 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6842 tcg_gen_andi_i32(t0, arg2, 0x1F);
6843 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6844 tcg_temp_free_i32(t0);
57951c27
AJ		 6845}
6846GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6847static always_inline void gen_evmergehi (DisasContext *ctx)
6848{
6849 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6850 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6851 return;
6852 }
6853#if defined(TARGET_PPC64)
a7812ae4
PB		 6854 TCGv t0 = tcg_temp_new();
6855 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6856 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6857 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6858 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6859 tcg_temp_free(t0);
6860 tcg_temp_free(t1);
6861#else
6862 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6863 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6864#endif
6865}
6866GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6867static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6868{
57951c27
AJ		 6869 tcg_gen_sub_i32(ret, arg2, arg1);
6870}
6871GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6872
57951c27
AJ		 6873/* SPE arithmetic immediate */
6874#if defined(TARGET_PPC64)
6875#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6876static always_inline void gen_##name (DisasContext *ctx) \
6877{ \
6878 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6879 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6880 return; \
6881 } \
a7812ae4
PB		 6882 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6883 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6884 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6885 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6886 tcg_op(t0, t0, rA(ctx->opcode)); \
6887 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6888 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 6889 tcg_temp_free_i64(t2); \
57951c27
AJ		 6890 tcg_op(t1, t1, rA(ctx->opcode)); \
6891 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6892 tcg_temp_free_i32(t0); \
6893 tcg_temp_free_i32(t1); \
57951c27
AJ		 6894}
6895#else
6896#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6897static always_inline void gen_##name (DisasContext *ctx) \
6898{ \
6899 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6900 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6901 return; \
6902 } \
6903 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6904 rA(ctx->opcode)); \
6905 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6906 rA(ctx->opcode)); \
6907}
6908#endif
6909GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6910GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6911
6912/* SPE comparison */
6913#if defined(TARGET_PPC64)
6914#define GEN_SPEOP_COMP(name, tcg_cond) \
6915static always_inline void gen_##name (DisasContext *ctx) \
6916{ \
6917 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6918 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6919 return; \
6920 } \
6921 int l1 = gen_new_label(); \
6922 int l2 = gen_new_label(); \
6923 int l3 = gen_new_label(); \
6924 int l4 = gen_new_label(); \
a7812ae4
PB		 6925 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6926 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6927 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6928 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6929 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6930 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6931 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6932 tcg_gen_br(l2); \
6933 gen_set_label(l1); \
6934 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6935 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6936 gen_set_label(l2); \
6937 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6938 tcg_gen_trunc_i64_i32(t0, t2); \
6939 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6940 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6941 tcg_temp_free_i64(t2); \
57951c27
AJ		 6942 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6943 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6944 ~(CRF_CH | CRF_CH_AND_CL)); \
6945 tcg_gen_br(l4); \
6946 gen_set_label(l3); \
6947 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6948 CRF_CH | CRF_CH_OR_CL); \
6949 gen_set_label(l4); \
a7812ae4
PB		 6950 tcg_temp_free_i32(t0); \
6951 tcg_temp_free_i32(t1); \
57951c27
AJ		 6952}
6953#else
6954#define GEN_SPEOP_COMP(name, tcg_cond) \
6955static always_inline void gen_##name (DisasContext *ctx) \
6956{ \
6957 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6958 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6959 return; \
6960 } \
6961 int l1 = gen_new_label(); \
6962 int l2 = gen_new_label(); \
6963 int l3 = gen_new_label(); \
6964 int l4 = gen_new_label(); \
6965 \
6966 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6967 cpu_gpr[rB(ctx->opcode)], l1); \
6968 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6969 tcg_gen_br(l2); \
6970 gen_set_label(l1); \
6971 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6972 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6973 gen_set_label(l2); \
6974 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6975 cpu_gprh[rB(ctx->opcode)], l3); \
6976 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6977 ~(CRF_CH | CRF_CH_AND_CL)); \
6978 tcg_gen_br(l4); \
6979 gen_set_label(l3); \
6980 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6981 CRF_CH | CRF_CH_OR_CL); \
6982 gen_set_label(l4); \
6983}
6984#endif
6985GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6986GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6987GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6988GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6989GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6990
6991/* SPE misc */
6992static always_inline void gen_brinc (DisasContext *ctx)
6993{
6994 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6995 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6996 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6997}
57951c27
AJ		 6998static always_inline void gen_evmergelo (DisasContext *ctx)
6999{
7000 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7001 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7002 return;
7003 }
7004#if defined(TARGET_PPC64)
a7812ae4
PB		 7005 TCGv t0 = tcg_temp_new();
7006 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7007 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7008 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7009 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7010 tcg_temp_free(t0);
7011 tcg_temp_free(t1);
7012#else
7013 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7014 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7015#endif
7016}
7017static always_inline void gen_evmergehilo (DisasContext *ctx)
7018{
7019 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7020 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7021 return;
7022 }
7023#if defined(TARGET_PPC64)
a7812ae4
PB		 7024 TCGv t0 = tcg_temp_new();
7025 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7026 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7027 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7028 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7029 tcg_temp_free(t0);
7030 tcg_temp_free(t1);
7031#else
7032 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7033 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7034#endif
7035}
7036static always_inline void gen_evmergelohi (DisasContext *ctx)
7037{
7038 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7039 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7040 return;
7041 }
7042#if defined(TARGET_PPC64)
a7812ae4
PB		 7043 TCGv t0 = tcg_temp_new();
7044 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7045 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7046 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7047 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7048 tcg_temp_free(t0);
7049 tcg_temp_free(t1);
7050#else
7051 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7052 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7053#endif
7054}
7055static always_inline void gen_evsplati (DisasContext *ctx)
7056{
38d14952 7057 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 7058
57951c27 7059#if defined(TARGET_PPC64)
38d14952 7060 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7061#else
7062 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7063 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7064#endif
7065}
b068d6a7 7066static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 7067{
38d14952 7068 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 7069
57951c27 7070#if defined(TARGET_PPC64)
38d14952 7071 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7072#else
7073 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7074 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7075#endif
0487d6a8
JM		 7076}
7077
57951c27
AJ		 7078static always_inline void gen_evsel (DisasContext *ctx)
7079{
7080 int l1 = gen_new_label();
7081 int l2 = gen_new_label();
7082 int l3 = gen_new_label();
7083 int l4 = gen_new_label();
a7812ae4 7084 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 7085#if defined(TARGET_PPC64)
a7812ae4
PB		 7086 TCGv t1 = tcg_temp_local_new();
7087 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 7088#endif
7089 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7090 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7091#if defined(TARGET_PPC64)
7092 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7093#else
7094 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7095#endif
7096 tcg_gen_br(l2);
7097 gen_set_label(l1);
7098#if defined(TARGET_PPC64)
7099 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7100#else
7101 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7102#endif
7103 gen_set_label(l2);
7104 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7105 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7106#if defined(TARGET_PPC64)
7107 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7108#else
7109 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7110#endif
7111 tcg_gen_br(l4);
7112 gen_set_label(l3);
7113#if defined(TARGET_PPC64)
7114 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7115#else
7116 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7117#endif
7118 gen_set_label(l4);
a7812ae4 7119 tcg_temp_free_i32(t0);
57951c27
AJ		 7120#if defined(TARGET_PPC64)
7121 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7122 tcg_temp_free(t1);
7123 tcg_temp_free(t2);
7124#endif
7125}
7126GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7127{
7128 gen_evsel(ctx);
7129}
7130GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7131{
7132 gen_evsel(ctx);
7133}
7134GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7135{
7136 gen_evsel(ctx);
7137}
7138GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7139{
7140 gen_evsel(ctx);
7141}
0487d6a8
JM		 7142
7143GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7144GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7145GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7146GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7147GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7148GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7149GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7150GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7151GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7152GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7153GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7154GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7155GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7156GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7157GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7158GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7159GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7160GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7161GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7162GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7163GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7164GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7165GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7166GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7167GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7168
6a6ae23f 7169/* SPE load and stores */
76db3ba4 7170static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 7171{
7172 target_ulong uimm = rB(ctx->opcode);
7173
76db3ba4 7174 if (rA(ctx->opcode) == 0) {
6a6ae23f 7175 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 7176 } else {
6a6ae23f 7177 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
76db3ba4
AJ		 7178#if defined(TARGET_PPC64)
7179 if (!ctx->sf_mode) {
7180 tcg_gen_ext32u_tl(EA, EA);
7181 }
7182#endif
7183 }
0487d6a8 7184}
6a6ae23f
AJ		 7185
7186static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7187{
7188#if defined(TARGET_PPC64)
76db3ba4 7189 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7190#else
7191 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 7192 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 7193 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7194 tcg_gen_shri_i64(t0, t0, 32);
7195 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7196 tcg_temp_free_i64(t0);
7197#endif
0487d6a8 7198}
6a6ae23f
AJ		 7199
7200static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7201{
0487d6a8 7202#if defined(TARGET_PPC64)
6a6ae23f 7203 TCGv t0 = tcg_temp_new();
76db3ba4 7204 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 7205 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 7206 gen_addr_add(ctx, addr, addr, 4);
7207 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 7208 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7209 tcg_temp_free(t0);
7210#else
76db3ba4
AJ		 7211 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7212 gen_addr_add(ctx, addr, addr, 4);
7213 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 7214#endif
0487d6a8 7215}
6a6ae23f
AJ		 7216
7217static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7218{
7219 TCGv t0 = tcg_temp_new();
7220#if defined(TARGET_PPC64)
76db3ba4 7221 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7222 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7223 gen_addr_add(ctx, addr, addr, 2);
7224 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7225 tcg_gen_shli_tl(t0, t0, 32);
7226 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7227 gen_addr_add(ctx, addr, addr, 2);
7228 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7229 tcg_gen_shli_tl(t0, t0, 16);
7230 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7231 gen_addr_add(ctx, addr, addr, 2);
7232 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7233 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7234#else
76db3ba4 7235 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7236 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7237 gen_addr_add(ctx, addr, addr, 2);
7238 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7239 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7240 gen_addr_add(ctx, addr, addr, 2);
7241 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7242 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7243 gen_addr_add(ctx, addr, addr, 2);
7244 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7245 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7246#endif
6a6ae23f 7247 tcg_temp_free(t0);
0487d6a8
JM		 7248}
7249
6a6ae23f
AJ		 7250static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7251{
7252 TCGv t0 = tcg_temp_new();
76db3ba4 7253 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7254#if defined(TARGET_PPC64)
7255 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7256 tcg_gen_shli_tl(t0, t0, 16);
7257 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7258#else
7259 tcg_gen_shli_tl(t0, t0, 16);
7260 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7261 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7262#endif
7263 tcg_temp_free(t0);
0487d6a8
JM		 7264}
7265
6a6ae23f
AJ		 7266static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7267{
7268 TCGv t0 = tcg_temp_new();
76db3ba4 7269 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7270#if defined(TARGET_PPC64)
7271 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7272 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7273#else
7274 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7276#endif
7277 tcg_temp_free(t0);
0487d6a8
JM		 7278}
7279
6a6ae23f
AJ		 7280static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7281{
7282 TCGv t0 = tcg_temp_new();
76db3ba4 7283 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7284#if defined(TARGET_PPC64)
7285 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7286 tcg_gen_ext32u_tl(t0, t0);
7287 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7288#else
7289 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7290 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7291#endif
7292 tcg_temp_free(t0);
7293}
7294
7295static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7296{
7297 TCGv t0 = tcg_temp_new();
7298#if defined(TARGET_PPC64)
76db3ba4 7299 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7300 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7301 gen_addr_add(ctx, addr, addr, 2);
7302 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7303 tcg_gen_shli_tl(t0, t0, 16);
7304 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7305#else
76db3ba4 7306 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7307 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7308 gen_addr_add(ctx, addr, addr, 2);
7309 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7310 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7311#endif
7312 tcg_temp_free(t0);
7313}
7314
7315static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7316{
7317#if defined(TARGET_PPC64)
7318 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 7319 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7320 gen_addr_add(ctx, addr, addr, 2);
7321 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7322 tcg_gen_shli_tl(t0, t0, 32);
7323 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7324 tcg_temp_free(t0);
7325#else
76db3ba4
AJ		 7326 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7327 gen_addr_add(ctx, addr, addr, 2);
7328 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7329#endif
7330}
7331
7332static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7333{
7334#if defined(TARGET_PPC64)
7335 TCGv t0 = tcg_temp_new();
76db3ba4 7336 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 7337 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7338 gen_addr_add(ctx, addr, addr, 2);
7339 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7340 tcg_gen_shli_tl(t0, t0, 32);
7341 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7342 tcg_temp_free(t0);
7343#else
76db3ba4
AJ		 7344 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7345 gen_addr_add(ctx, addr, addr, 2);
7346 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7347#endif
7348}
7349
7350static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7351{
7352 TCGv t0 = tcg_temp_new();
76db3ba4 7353 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 7354#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7355 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7356 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7357#else
7358 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7359 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7360#endif
7361 tcg_temp_free(t0);
7362}
7363
7364static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7365{
7366 TCGv t0 = tcg_temp_new();
7367#if defined(TARGET_PPC64)
76db3ba4 7368 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7369 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7370 tcg_gen_shli_tl(t0, t0, 32);
7371 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7372 gen_addr_add(ctx, addr, addr, 2);
7373 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7374 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7375 tcg_gen_shli_tl(t0, t0, 16);
7376 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7377#else
76db3ba4 7378 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7379 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7380 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7381 gen_addr_add(ctx, addr, addr, 2);
7382 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7383 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7384 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 7385#endif
6a6ae23f
AJ		 7386 tcg_temp_free(t0);
7387}
7388
7389static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7390{
7391#if defined(TARGET_PPC64)
76db3ba4 7392 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 7393#else
6a6ae23f
AJ		 7394 TCGv_i64 t0 = tcg_temp_new_i64();
7395 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 7396 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 7397 tcg_temp_free_i64(t0);
7398#endif
7399}
7400
7401static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7402{
0487d6a8 7403#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7404 TCGv t0 = tcg_temp_new();
7405 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7406 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7407 tcg_temp_free(t0);
7408#else
76db3ba4 7409 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7410#endif
76db3ba4
AJ		 7411 gen_addr_add(ctx, addr, addr, 4);
7412 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7413}
7414
7415static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7416{
7417 TCGv t0 = tcg_temp_new();
7418#if defined(TARGET_PPC64)
7419 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7420#else
7421 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7422#endif
76db3ba4
AJ		 7423 gen_qemu_st16(ctx, t0, addr);
7424 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 7425#if defined(TARGET_PPC64)
7426 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7427 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7428#else
76db3ba4 7429 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7430#endif
76db3ba4 7431 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7432 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7433 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7434 tcg_temp_free(t0);
76db3ba4
AJ		 7435 gen_addr_add(ctx, addr, addr, 2);
7436 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7437}
7438
7439static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7440{
7441 TCGv t0 = tcg_temp_new();
7442#if defined(TARGET_PPC64)
7443 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7444#else
7445 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7446#endif
76db3ba4
AJ		 7447 gen_qemu_st16(ctx, t0, addr);
7448 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7449 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7450 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7451 tcg_temp_free(t0);
7452}
7453
7454static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7455{
7456#if defined(TARGET_PPC64)
7457 TCGv t0 = tcg_temp_new();
7458 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7459 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7460 tcg_temp_free(t0);
7461#else
76db3ba4 7462 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7463#endif
76db3ba4
AJ		 7464 gen_addr_add(ctx, addr, addr, 2);
7465 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7466}
7467
7468static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7469{
7470#if defined(TARGET_PPC64)
7471 TCGv t0 = tcg_temp_new();
7472 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7473 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7474 tcg_temp_free(t0);
7475#else
76db3ba4 7476 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7477#endif
7478}
7479
7480static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7481{
76db3ba4 7482 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7483}
7484
7485#define GEN_SPEOP_LDST(name, opc2, sh) \
76db3ba4 7486GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6a6ae23f
AJ		 7487{ \
7488 TCGv t0; \
7489 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7490 gen_exception(ctx, POWERPC_EXCP_APU); \
6a6ae23f
AJ		 7491 return; \
7492 } \
76db3ba4 7493 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 7494 t0 = tcg_temp_new(); \
7495 if (Rc(ctx->opcode)) { \
76db3ba4 7496 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 7497 } else { \
76db3ba4 7498 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 7499 } \
7500 gen_op_##name(ctx, t0); \
7501 tcg_temp_free(t0); \
7502}
7503
7504GEN_SPEOP_LDST(evldd, 0x00, 3);
7505GEN_SPEOP_LDST(evldw, 0x01, 3);
7506GEN_SPEOP_LDST(evldh, 0x02, 3);
7507GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7508GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7509GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7510GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7511GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7512GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7513GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7514GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7515
7516GEN_SPEOP_LDST(evstdd, 0x10, 3);
7517GEN_SPEOP_LDST(evstdw, 0x11, 3);
7518GEN_SPEOP_LDST(evstdh, 0x12, 3);
7519GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7520GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7521GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7522GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7523
7524/* Multiply and add - TODO */
7525#if 0
7526GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7527GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7528GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7529GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7530GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7531GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7532GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7533GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7534GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7535GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7536GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7537GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7538
7539GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7540GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7541GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7542GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7543GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7544GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7545GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7546GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7547GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7548GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7549GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7550GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7551GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7552GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7553
7554GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7555GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7556GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7557GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7558GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7559GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7560
7561GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7562GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7563GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7564GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7565GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7566GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7567GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7568GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7569GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7570GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7571GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7572GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7573
7574GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7575GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7576GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7577GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7578GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7579
7580GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7581GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7582GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7583GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7584GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7585GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7586GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7587GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7588GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7589GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7590GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7591GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7592
7593GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7594GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7595GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7596GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7597GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7598#endif
7599
7600/*** SPE floating-point extension ***/
1c97856d
AJ		 7601#if defined(TARGET_PPC64)
7602#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7603static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7604{ \
1c97856d
AJ		 7605 TCGv_i32 t0; \
7606 TCGv t1; \
7607 t0 = tcg_temp_new_i32(); \
7608 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7609 gen_helper_##name(t0, t0); \
7610 t1 = tcg_temp_new(); \
7611 tcg_gen_extu_i32_tl(t1, t0); \
7612 tcg_temp_free_i32(t0); \
7613 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7614 0xFFFFFFFF00000000ULL); \
7615 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7616 tcg_temp_free(t1); \
0487d6a8 7617}
1c97856d
AJ		 7618#define GEN_SPEFPUOP_CONV_32_64(name) \
7619static always_inline void gen_##name (DisasContext *ctx) \
7620{ \
7621 TCGv_i32 t0; \
7622 TCGv t1; \
7623 t0 = tcg_temp_new_i32(); \
7624 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7625 t1 = tcg_temp_new(); \
7626 tcg_gen_extu_i32_tl(t1, t0); \
7627 tcg_temp_free_i32(t0); \
7628 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7629 0xFFFFFFFF00000000ULL); \
7630 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7631 tcg_temp_free(t1); \
7632}
7633#define GEN_SPEFPUOP_CONV_64_32(name) \
7634static always_inline void gen_##name (DisasContext *ctx) \
7635{ \
7636 TCGv_i32 t0 = tcg_temp_new_i32(); \
7637 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7638 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7639 tcg_temp_free_i32(t0); \
7640}
7641#define GEN_SPEFPUOP_CONV_64_64(name) \
7642static always_inline void gen_##name (DisasContext *ctx) \
7643{ \
7644 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7645}
7646#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7647static always_inline void gen_##name (DisasContext *ctx) \
7648{ \
1c97856d
AJ		 7649 TCGv_i32 t0, t1; \
7650 TCGv_i64 t2; \
57951c27 7651 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7652 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7653 return; \
7654 } \
1c97856d
AJ		 7655 t0 = tcg_temp_new_i32(); \
7656 t1 = tcg_temp_new_i32(); \
7657 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7658 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7659 gen_helper_##name(t0, t0, t1); \
7660 tcg_temp_free_i32(t1); \
7661 t2 = tcg_temp_new(); \
7662 tcg_gen_extu_i32_tl(t2, t0); \
7663 tcg_temp_free_i32(t0); \
7664 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7665 0xFFFFFFFF00000000ULL); \
7666 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7667 tcg_temp_free(t2); \
57951c27 7668}
1c97856d 7669#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7670static always_inline void gen_##name (DisasContext *ctx) \
7671{ \
7672 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7673 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7674 return; \
7675 } \
1c97856d
AJ		 7676 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7677 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7678}
1c97856d 7679#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7680static always_inline void gen_##name (DisasContext *ctx) \
7681{ \
1c97856d 7682 TCGv_i32 t0, t1; \
57951c27 7683 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7684 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7685 return; \
7686 } \
1c97856d
AJ		 7687 t0 = tcg_temp_new_i32(); \
7688 t1 = tcg_temp_new_i32(); \
7689 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7690 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7691 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7692 tcg_temp_free_i32(t0); \
7693 tcg_temp_free_i32(t1); \
7694}
7695#define GEN_SPEFPUOP_COMP_64(name) \
7696static always_inline void gen_##name (DisasContext *ctx) \
7697{ \
7698 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7699 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7700 return; \
7701 } \
7702 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7703 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7704}
7705#else
7706#define GEN_SPEFPUOP_CONV_32_32(name) \
7707static always_inline void gen_##name (DisasContext *ctx) \
7708{ \
7709 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7710}
1c97856d
AJ		 7711#define GEN_SPEFPUOP_CONV_32_64(name) \
7712static always_inline void gen_##name (DisasContext *ctx) \
7713{ \
7714 TCGv_i64 t0 = tcg_temp_new_i64(); \
7715 gen_load_gpr64(t0, rB(ctx->opcode)); \
7716 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7717 tcg_temp_free_i64(t0); \
7718}
7719#define GEN_SPEFPUOP_CONV_64_32(name) \
7720static always_inline void gen_##name (DisasContext *ctx) \
7721{ \
7722 TCGv_i64 t0 = tcg_temp_new_i64(); \
7723 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7724 gen_store_gpr64(rD(ctx->opcode), t0); \
7725 tcg_temp_free_i64(t0); \
7726}
7727#define GEN_SPEFPUOP_CONV_64_64(name) \
7728static always_inline void gen_##name (DisasContext *ctx) \
7729{ \
7730 TCGv_i64 t0 = tcg_temp_new_i64(); \
7731 gen_load_gpr64(t0, rB(ctx->opcode)); \
7732 gen_helper_##name(t0, t0); \
7733 gen_store_gpr64(rD(ctx->opcode), t0); \
7734 tcg_temp_free_i64(t0); \
7735}
7736#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7737static always_inline void gen_##name (DisasContext *ctx) \
7738{ \
7739 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7740 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7741 return; \
7742 } \
7743 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7744 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7745}
7746#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7747static always_inline void gen_##name (DisasContext *ctx) \
7748{ \
7749 TCGv_i64 t0, t1; \
7750 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7751 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7752 return; \
7753 } \
7754 t0 = tcg_temp_new_i64(); \
7755 t1 = tcg_temp_new_i64(); \
7756 gen_load_gpr64(t0, rA(ctx->opcode)); \
7757 gen_load_gpr64(t1, rB(ctx->opcode)); \
7758 gen_helper_##name(t0, t0, t1); \
7759 gen_store_gpr64(rD(ctx->opcode), t0); \
7760 tcg_temp_free_i64(t0); \
7761 tcg_temp_free_i64(t1); \
7762}
7763#define GEN_SPEFPUOP_COMP_32(name) \
7764static always_inline void gen_##name (DisasContext *ctx) \
7765{ \
7766 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7767 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7768 return; \
7769 } \
7770 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7771 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7772}
7773#define GEN_SPEFPUOP_COMP_64(name) \
7774static always_inline void gen_##name (DisasContext *ctx) \
7775{ \
7776 TCGv_i64 t0, t1; \
7777 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7778 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7779 return; \
7780 } \
7781 t0 = tcg_temp_new_i64(); \
7782 t1 = tcg_temp_new_i64(); \
7783 gen_load_gpr64(t0, rA(ctx->opcode)); \
7784 gen_load_gpr64(t1, rB(ctx->opcode)); \
7785 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7786 tcg_temp_free_i64(t0); \
7787 tcg_temp_free_i64(t1); \
7788}
7789#endif
57951c27 7790
0487d6a8
JM		 7791/* Single precision floating-point vectors operations */
7792/* Arithmetic */
1c97856d
AJ		 7793GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7794GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7795GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7796GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7797static always_inline void gen_evfsabs (DisasContext *ctx)
7798{
7799 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7800 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7801 return;
7802 }
7803#if defined(TARGET_PPC64)
7804 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7805#else
7806 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7807 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7808#endif
7809}
7810static always_inline void gen_evfsnabs (DisasContext *ctx)
7811{
7812 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7813 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7814 return;
7815 }
7816#if defined(TARGET_PPC64)
7817 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7818#else
7819 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7820 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7821#endif
7822}
7823static always_inline void gen_evfsneg (DisasContext *ctx)
7824{
7825 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7826 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7827 return;
7828 }
7829#if defined(TARGET_PPC64)
7830 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7831#else
7832 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7833 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7834#endif
7835}
7836
0487d6a8 7837/* Conversion */
1c97856d
AJ		 7838GEN_SPEFPUOP_CONV_64_64(evfscfui);
7839GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7840GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7841GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7842GEN_SPEFPUOP_CONV_64_64(evfsctui);
7843GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7844GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7845GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7846GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7847GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7848
0487d6a8 7849/* Comparison */
1c97856d
AJ		 7850GEN_SPEFPUOP_COMP_64(evfscmpgt);
7851GEN_SPEFPUOP_COMP_64(evfscmplt);
7852GEN_SPEFPUOP_COMP_64(evfscmpeq);
7853GEN_SPEFPUOP_COMP_64(evfststgt);
7854GEN_SPEFPUOP_COMP_64(evfststlt);
7855GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7856
7857/* Opcodes definitions */
40569b7e
AJ		 7858GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7859GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7860GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7861GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7862GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7863GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7864GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7865GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7866GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7867GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7868GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7869GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7870GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7871GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 7872
7873/* Single precision floating-point operations */
7874/* Arithmetic */
1c97856d
AJ		 7875GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7876GEN_SPEFPUOP_ARITH2_32_32(efssub);
7877GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7878GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7879static always_inline void gen_efsabs (DisasContext *ctx)
7880{
7881 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7882 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7883 return;
7884 }
7885 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7886}
7887static always_inline void gen_efsnabs (DisasContext *ctx)
7888{
7889 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7890 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7891 return;
7892 }
7893 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7894}
7895static always_inline void gen_efsneg (DisasContext *ctx)
7896{
7897 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7898 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7899 return;
7900 }
7901 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7902}
7903
0487d6a8 7904/* Conversion */
1c97856d
AJ		 7905GEN_SPEFPUOP_CONV_32_32(efscfui);
7906GEN_SPEFPUOP_CONV_32_32(efscfsi);
7907GEN_SPEFPUOP_CONV_32_32(efscfuf);
7908GEN_SPEFPUOP_CONV_32_32(efscfsf);
7909GEN_SPEFPUOP_CONV_32_32(efsctui);
7910GEN_SPEFPUOP_CONV_32_32(efsctsi);
7911GEN_SPEFPUOP_CONV_32_32(efsctuf);
7912GEN_SPEFPUOP_CONV_32_32(efsctsf);
7913GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7914GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7915GEN_SPEFPUOP_CONV_32_64(efscfd);
7916
0487d6a8 7917/* Comparison */
1c97856d
AJ		 7918GEN_SPEFPUOP_COMP_32(efscmpgt);
7919GEN_SPEFPUOP_COMP_32(efscmplt);
7920GEN_SPEFPUOP_COMP_32(efscmpeq);
7921GEN_SPEFPUOP_COMP_32(efststgt);
7922GEN_SPEFPUOP_COMP_32(efststlt);
7923GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7924
7925/* Opcodes definitions */
40569b7e
AJ		 7926GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7927GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7928GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7929GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7930GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7931GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7932GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7933GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7934GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7935GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7936GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7937GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7938GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7939GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 7940
7941/* Double precision floating-point operations */
7942/* Arithmetic */
1c97856d
AJ		 7943GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7944GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7945GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7946GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7947static always_inline void gen_efdabs (DisasContext *ctx)
7948{
7949 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7950 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7951 return;
7952 }
7953#if defined(TARGET_PPC64)
7954 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7955#else
7956 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7957#endif
7958}
7959static always_inline void gen_efdnabs (DisasContext *ctx)
7960{
7961 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7962 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7963 return;
7964 }
7965#if defined(TARGET_PPC64)
7966 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7967#else
7968 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7969#endif
7970}
7971static always_inline void gen_efdneg (DisasContext *ctx)
7972{
7973 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7974 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7975 return;
7976 }
7977#if defined(TARGET_PPC64)
7978 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7979#else
7980 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7981#endif
7982}
7983
0487d6a8 7984/* Conversion */
1c97856d
AJ		 7985GEN_SPEFPUOP_CONV_64_32(efdcfui);
7986GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7987GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7988GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7989GEN_SPEFPUOP_CONV_32_64(efdctui);
7990GEN_SPEFPUOP_CONV_32_64(efdctsi);
7991GEN_SPEFPUOP_CONV_32_64(efdctuf);
7992GEN_SPEFPUOP_CONV_32_64(efdctsf);
7993GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7994GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7995GEN_SPEFPUOP_CONV_64_32(efdcfs);
7996GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7997GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7998GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7999GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 8000
0487d6a8 8001/* Comparison */
1c97856d
AJ		 8002GEN_SPEFPUOP_COMP_64(efdcmpgt);
8003GEN_SPEFPUOP_COMP_64(efdcmplt);
8004GEN_SPEFPUOP_COMP_64(efdcmpeq);
8005GEN_SPEFPUOP_COMP_64(efdtstgt);
8006GEN_SPEFPUOP_COMP_64(efdtstlt);
8007GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 8008
8009/* Opcodes definitions */
40569b7e
AJ		 8010GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8011GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8012GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8013GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8014GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8015GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8016GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8017GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8018GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8019GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8020GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8021GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8022GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8023GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8024GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8025GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
0487d6a8 8026
79aceca5
FB		 8027/* End opcode list */
8028GEN_OPCODE_MARK(end);
8029
3fc6c082 8030#include "translate_init.c"
0411a972 8031#include "helper_regs.h"
79aceca5 8032
9a64fbe4 8033/*****************************************************************************/
3fc6c082 8034/* Misc PowerPC helpers */
36081602
JM		 8035void cpu_dump_state (CPUState *env, FILE *f,
8036 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8037 int flags)
79aceca5 8038{
3fc6c082
FB		 8039#define RGPL 4
8040#define RFPL 4
3fc6c082 8041
79aceca5
FB		 8042 int i;
8043
077fc206 8044 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 8045 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 8046 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8047 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 8048#if !defined(NO_TIMER_DUMP)
077fc206 8049 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 8050#if !defined(CONFIG_USER_ONLY)
8051 "DECR %08x"
8052#endif
8053 "\n",
077fc206 8054 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 8055#if !defined(CONFIG_USER_ONLY)
8056 , cpu_ppc_load_decr(env)
8057#endif
8058 );
077fc206 8059#endif
76a66253 8060 for (i = 0; i < 32; i++) {
3fc6c082
FB		 8061 if ((i & (RGPL - 1)) == 0)
8062 cpu_fprintf(f, "GPR%02d", i);
6b542af7 8063 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 8064 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 8065 cpu_fprintf(f, "\n");
76a66253 8066 }
3fc6c082 8067 cpu_fprintf(f, "CR ");
76a66253 8068 for (i = 0; i < 8; i++)
7fe48483
FB		 8069 cpu_fprintf(f, "%01x", env->crf[i]);
8070 cpu_fprintf(f, " [");
76a66253
JM		 8071 for (i = 0; i < 8; i++) {
8072 char a = '-';
8073 if (env->crf[i] & 0x08)
8074 a = 'L';
8075 else if (env->crf[i] & 0x04)
8076 a = 'G';
8077 else if (env->crf[i] & 0x02)
8078 a = 'E';
7fe48483 8079 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 8080 }
6b542af7 8081 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 8082 for (i = 0; i < 32; i++) {
8083 if ((i & (RFPL - 1)) == 0)
8084 cpu_fprintf(f, "FPR%02d", i);
26a76461 8085 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 8086 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 8087 cpu_fprintf(f, "\n");
79aceca5 8088 }
7889270a 8089 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
f2e63a42 8090#if !defined(CONFIG_USER_ONLY)
6b542af7 8091 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 8092 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 8093#endif
79aceca5 8094
3fc6c082
FB		 8095#undef RGPL
8096#undef RFPL
79aceca5
FB		 8097}
8098
76a66253
JM		 8099void cpu_dump_statistics (CPUState *env, FILE*f,
8100 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8101 int flags)
8102{
8103#if defined(DO_PPC_STATISTICS)
8104 opc_handler_t **t1, **t2, **t3, *handler;
8105 int op1, op2, op3;
8106
8107 t1 = env->opcodes;
8108 for (op1 = 0; op1 < 64; op1++) {
8109 handler = t1[op1];
8110 if (is_indirect_opcode(handler)) {
8111 t2 = ind_table(handler);
8112 for (op2 = 0; op2 < 32; op2++) {
8113 handler = t2[op2];
8114 if (is_indirect_opcode(handler)) {
8115 t3 = ind_table(handler);
8116 for (op3 = 0; op3 < 32; op3++) {
8117 handler = t3[op3];
8118 if (handler->count == 0)
8119 continue;
8120 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8121 "%016llx %lld\n",
8122 op1, op2, op3, op1, (op3 << 5) | op2,
8123 handler->oname,
8124 handler->count, handler->count);
8125 }
8126 } else {
8127 if (handler->count == 0)
8128 continue;
8129 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8130 "%016llx %lld\n",
8131 op1, op2, op1, op2, handler->oname,
8132 handler->count, handler->count);
8133 }
8134 }
8135 } else {
8136 if (handler->count == 0)
8137 continue;
8138 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8139 op1, op1, handler->oname,
8140 handler->count, handler->count);
8141 }
8142 }
8143#endif
8144}
8145
9a64fbe4 8146/*****************************************************************************/
2cfc5f17
TS		 8147static always_inline void gen_intermediate_code_internal (CPUState *env,
8148 TranslationBlock *tb,
8149 int search_pc)
79aceca5 8150{
9fddaa0c 8151 DisasContext ctx, *ctxp = &ctx;
79aceca5 8152 opc_handler_t **table, *handler;
0fa85d43 8153 target_ulong pc_start;
79aceca5 8154 uint16_t *gen_opc_end;
a1d1bb31 8155 CPUBreakpoint *bp;
79aceca5 8156 int j, lj = -1;
2e70f6ef
PB		 8157 int num_insns;
8158 int max_insns;
79aceca5
FB		 8159
8160 pc_start = tb->pc;
79aceca5 8161 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
046d6672 8162 ctx.nip = pc_start;
79aceca5 8163 ctx.tb = tb;
e1833e1f 8164 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 8165 ctx.spr_cb = env->spr_cb;
76db3ba4
AJ		 8166 ctx.mem_idx = env->mmu_idx;
8167 ctx.access_type = -1;
8168 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 8169#if defined(TARGET_PPC64)
8170 ctx.sf_mode = msr_sf;
9a64fbe4 8171#endif
3cc62370 8172 ctx.fpu_enabled = msr_fp;
a9d9eb8f 8173 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 8174 ctx.spe_enabled = msr_spe;
8175 else
8176 ctx.spe_enabled = 0;
a9d9eb8f
JM		 8177 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8178 ctx.altivec_enabled = msr_vr;
8179 else
8180 ctx.altivec_enabled = 0;
d26bfc9a 8181 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 8182 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 8183 else
8cbcb4fa 8184 ctx.singlestep_enabled = 0;
d26bfc9a 8185 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 8186 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8187 if (unlikely(env->singlestep_enabled))
8188 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 8189#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 8190 /* Single step trace mode */
8191 msr_se = 1;
8192#endif
2e70f6ef
PB		 8193 num_insns = 0;
8194 max_insns = tb->cflags & CF_COUNT_MASK;
8195 if (max_insns == 0)
8196 max_insns = CF_COUNT_MASK;
8197
8198 gen_icount_start();
9a64fbe4 8199 /* Set env in case of segfault during code fetch */
e1833e1f 8200 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 8201 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8202 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 8203 if (bp->pc == ctx.nip) {
e06fcd75 8204 gen_debug_exception(ctxp);
ea4e754f
FB		 8205 break;
8206 }
8207 }
8208 }
76a66253 8209 if (unlikely(search_pc)) {
79aceca5
FB		 8210 j = gen_opc_ptr - gen_opc_buf;
8211 if (lj < j) {
8212 lj++;
8213 while (lj < j)
8214 gen_opc_instr_start[lj++] = 0;
79aceca5 8215 }
af4b6c54
AJ		 8216 gen_opc_pc[lj] = ctx.nip;
8217 gen_opc_instr_start[lj] = 1;
8218 gen_opc_icount[lj] = num_insns;
79aceca5 8219 }
d12d51d5
AL		 8220 LOG_DISAS("----------------\n");
8221 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8222 ctx.nip, ctx.mem_idx, (int)msr_ir);
2e70f6ef
PB		 8223 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8224 gen_io_start();
76db3ba4 8225 if (unlikely(ctx.le_mode)) {
056401ea
JM		 8226 ctx.opcode = bswap32(ldl_code(ctx.nip));
8227 } else {
8228 ctx.opcode = ldl_code(ctx.nip);
111bfab3 8229 }
d12d51d5 8230 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 8231 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 8232 opc3(ctx.opcode), little_endian ? "little" : "big");
046d6672 8233 ctx.nip += 4;
3fc6c082 8234 table = env->opcodes;
2e70f6ef 8235 num_insns++;
79aceca5
FB		 8236 handler = table[opc1(ctx.opcode)];
8237 if (is_indirect_opcode(handler)) {
8238 table = ind_table(handler);
8239 handler = table[opc2(ctx.opcode)];
8240 if (is_indirect_opcode(handler)) {
8241 table = ind_table(handler);
8242 handler = table[opc3(ctx.opcode)];
8243 }
8244 }
8245 /* Is opcode *REALLY* valid ? */
76a66253 8246 if (unlikely(handler->handler == &gen_invalid)) {
93fcfe39
AL		 8247 if (qemu_log_enabled()) {
8248 qemu_log("invalid/unsupported opcode: "
8249 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8250 opc1(ctx.opcode), opc2(ctx.opcode),
8251 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 8252 } else {
8253 printf("invalid/unsupported opcode: "
6b542af7 8254 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 8255 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8256 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 8257 }
76a66253
JM		 8258 } else {
8259 if (unlikely((ctx.opcode & handler->inval) != 0)) {
93fcfe39
AL		 8260 if (qemu_log_enabled()) {
8261 qemu_log("invalid bits: %08x for opcode: "
8262 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8263 ctx.opcode & handler->inval, opc1(ctx.opcode),
8264 opc2(ctx.opcode), opc3(ctx.opcode),
8265 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 8266 } else {
8267 printf("invalid bits: %08x for opcode: "
6b542af7 8268 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 8269 ctx.opcode & handler->inval, opc1(ctx.opcode),
8270 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8271 ctx.opcode, ctx.nip - 4);
76a66253 8272 }
e06fcd75 8273 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 8274 break;
79aceca5 8275 }
79aceca5 8276 }
4b3686fa 8277 (*(handler->handler))(&ctx);
76a66253
JM		 8278#if defined(DO_PPC_STATISTICS)
8279 handler->count++;
8280#endif
9a64fbe4 8281 /* Check trace mode exceptions */
8cbcb4fa
AJ		 8282 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8283 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8284 ctx.exception != POWERPC_SYSCALL &&
8285 ctx.exception != POWERPC_EXCP_TRAP &&
8286 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 8287 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 8288 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef 8289 (env->singlestep_enabled) ||
1b530a6d 8290 singlestep ||
2e70f6ef 8291 num_insns >= max_insns)) {
d26bfc9a
JM		 8292 /* if we reach a page boundary or are single stepping, stop
8293 * generation
8294 */
8dd4983c 8295 break;
76a66253 8296 }
3fc6c082 8297 }
2e70f6ef
PB		 8298 if (tb->cflags & CF_LAST_IO)
8299 gen_io_end();
e1833e1f 8300 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 8301 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 8302 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa 8303 if (unlikely(env->singlestep_enabled)) {
e06fcd75 8304 gen_debug_exception(ctxp);
8cbcb4fa 8305 }
76a66253 8306 /* Generate the return instruction */
57fec1fe 8307 tcg_gen_exit_tb(0);
9a64fbe4 8308 }
2e70f6ef 8309 gen_icount_end(tb, num_insns);
79aceca5 8310 *gen_opc_ptr = INDEX_op_end;
76a66253 8311 if (unlikely(search_pc)) {
9a64fbe4
FB		 8312 j = gen_opc_ptr - gen_opc_buf;
8313 lj++;
8314 while (lj <= j)
8315 gen_opc_instr_start[lj++] = 0;
9a64fbe4 8316 } else {
046d6672 8317 tb->size = ctx.nip - pc_start;
2e70f6ef 8318 tb->icount = num_insns;
9a64fbe4 8319 }
d9bce9d9 8320#if defined(DEBUG_DISAS)
93fcfe39
AL		 8321 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8322 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8fec2b8c 8323 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 8324 int flags;
237c0af0 8325 flags = env->bfd_mach;
76db3ba4 8326 flags |= ctx.le_mode << 16;
93fcfe39
AL		 8327 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8328 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8329 qemu_log("\n");
9fddaa0c 8330 }
79aceca5 8331#endif
79aceca5
FB		 8332}
8333
2cfc5f17 8334void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 8335{
2cfc5f17 8336 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 8337}
8338
2cfc5f17 8339void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 8340{
2cfc5f17 8341 gen_intermediate_code_internal(env, tb, 1);
79aceca5 8342}
d2856f1a
AJ		 8343
8344void gen_pc_load(CPUState *env, TranslationBlock *tb,
8345 unsigned long searched_pc, int pc_pos, void *puc)
8346{
d2856f1a 8347 env->nip = gen_opc_pc[pc_pos];
d2856f1a 8348}
Qemu copy for testing