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target-ppc: convert SPE FP ops to TCG
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
79aceca5 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
7c58044c 44//#define OPTIMIZE_FPRF_UPDATE
79aceca5 45
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 52#if !defined(TARGET_PPC64)
1d542695 53 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 54#endif
a5e26afa 55 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
f78fb44e
AJ		 58static TCGv cpu_gpr[32];
59#if !defined(TARGET_PPC64)
60static TCGv cpu_gprh[32];
61#endif
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64static TCGv_i32 cpu_crf[8];
bd568f18 65static TCGv cpu_nip;
cfdcd37a
AJ		 66static TCGv cpu_ctr;
67static TCGv cpu_lr;
3d7b417e 68static TCGv cpu_xer;
a7812ae4 69static TCGv_i32 cpu_fpscr;
f78fb44e
AJ		 70
71/* dyngen register indexes */
72static TCGv cpu_T[3];
73#if defined(TARGET_PPC64)
74#define cpu_T64 cpu_T
75#else
a7812ae4 76static TCGv_i64 cpu_T64[3];
f78fb44e 77#endif
af12906f 78static TCGv_i64 cpu_FT[2];
a7812ae4 79static TCGv_i64 cpu_AVRh[3], cpu_AVRl[3];
2e70f6ef
PB		 80
81#include "gen-icount.h"
82
83void ppc_translate_init(void)
84{
f78fb44e
AJ		 85 int i;
86 char* p;
b2437bf2 87 static int done_init = 0;
f78fb44e 88
2e70f6ef
PB		 89 if (done_init)
90 return;
f78fb44e 91
a7812ae4 92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1c73fe5b 93#if TARGET_LONG_BITS > HOST_LONG_BITS
a7812ae4
PB		 94 cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");
95 cpu_T[1] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t1), "T1");
96 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
1c73fe5b 97#else
a7812ae4
PB		 98 cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");
99 cpu_T[1] = tcg_global_reg_new(TCG_AREG2, "T1");
4870167d
AJ		 100#ifdef HOST_I386
101 /* XXX: This is a temporary workaround for i386.
102 * On i386 qemu_st32 runs out of registers.
103 * The proper fix is to remove cpu_T.
104 */
a7812ae4 105 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
4870167d 106#else
a7812ae4 107 cpu_T[2] = tcg_global_reg_new(TCG_AREG3, "T2");
1c73fe5b 108#endif
4870167d 109#endif
f78fb44e 110#if !defined(TARGET_PPC64)
a7812ae4
PB		 111 cpu_T64[0] = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, t0_64),
112 "T0_64");
113 cpu_T64[1] = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, t1_64),
114 "T1_64");
115 cpu_T64[2] = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, t2_64),
116 "T2_64");
117#endif
118
119 cpu_FT[0] = tcg_global_mem_new_i64(TCG_AREG0,
120 offsetof(CPUState, ft0), "FT0");
121 cpu_FT[1] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUState, ft1), "FT1");
a7812ae4
PB		 123
124 cpu_AVRh[0] = tcg_global_mem_new_i64(TCG_AREG0,
1d542695 125 offsetof(CPUState, avr0.u64[0]), "AVR0H");
a7812ae4 126 cpu_AVRl[0] = tcg_global_mem_new_i64(TCG_AREG0,
1d542695 127 offsetof(CPUState, avr0.u64[1]), "AVR0L");
a7812ae4 128 cpu_AVRh[1] = tcg_global_mem_new_i64(TCG_AREG0,
1d542695 129 offsetof(CPUState, avr1.u64[0]), "AVR1H");
a7812ae4 130 cpu_AVRl[1] = tcg_global_mem_new_i64(TCG_AREG0,
1d542695 131 offsetof(CPUState, avr1.u64[1]), "AVR1L");
a7812ae4 132 cpu_AVRh[2] = tcg_global_mem_new_i64(TCG_AREG0,
1d542695 133 offsetof(CPUState, avr2.u64[0]), "AVR2H");
a7812ae4 134 cpu_AVRl[2] = tcg_global_mem_new_i64(TCG_AREG0,
1d542695
AJ		 135 offsetof(CPUState, avr2.u64[1]), "AVR2L");
136
f78fb44e 137 p = cpu_reg_names;
47e4661c
AJ		 138
139 for (i = 0; i < 8; i++) {
140 sprintf(p, "crf%d", i);
a7812ae4
PB		 141 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
142 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 143 p += 5;
144 }
145
f78fb44e
AJ		 146 for (i = 0; i < 32; i++) {
147 sprintf(p, "r%d", i);
a7812ae4 148 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 149 offsetof(CPUState, gpr[i]), p);
150 p += (i < 10) ? 3 : 4;
151#if !defined(TARGET_PPC64)
152 sprintf(p, "r%dH", i);
a7812ae4
PB		 153 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
154 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 155 p += (i < 10) ? 4 : 5;
156#endif
1d542695 157
a5e26afa 158 sprintf(p, "fp%d", i);
a7812ae4
PB		 159 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
160 offsetof(CPUState, fpr[i]), p);
ec1ac72d 161 p += (i < 10) ? 4 : 5;
a5e26afa 162
1d542695 163 sprintf(p, "avr%dH", i);
a7812ae4 164 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
1d542695
AJ		 165 offsetof(CPUState, avr[i].u64[0]), p);
166 p += (i < 10) ? 6 : 7;
ec1ac72d 167
1d542695 168 sprintf(p, "avr%dL", i);
a7812ae4 169 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
1d542695
AJ		 170 offsetof(CPUState, avr[i].u64[1]), p);
171 p += (i < 10) ? 6 : 7;
f78fb44e 172 }
f10dc08e 173
a7812ae4 174 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 175 offsetof(CPUState, nip), "nip");
176
a7812ae4 177 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 178 offsetof(CPUState, ctr), "ctr");
179
a7812ae4 180 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 181 offsetof(CPUState, lr), "lr");
182
a7812ae4 183 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 184 offsetof(CPUState, xer), "xer");
185
a7812ae4
PB		 186 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
187 offsetof(CPUState, fpscr), "fpscr");
e1571908 188
f10dc08e 189 /* register helpers */
a7812ae4 190#define GEN_HELPER 2
f10dc08e
AJ		 191#include "helper.h"
192
2e70f6ef
PB		 193 done_init = 1;
194}
195
7c58044c
JM		 196#if defined(OPTIMIZE_FPRF_UPDATE)
197static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
198static uint16_t **gen_fprf_ptr;
199#endif
79aceca5 200
79aceca5
FB		 201/* internal defines */
202typedef struct DisasContext {
203 struct TranslationBlock *tb;
0fa85d43 204 target_ulong nip;
79aceca5 205 uint32_t opcode;
9a64fbe4 206 uint32_t exception;
3cc62370
FB		 207 /* Routine used to access memory */
208 int mem_idx;
209 /* Translation flags */
9a64fbe4 210#if !defined(CONFIG_USER_ONLY)
79aceca5 211 int supervisor;
d9bce9d9
JM		 212#endif
213#if defined(TARGET_PPC64)
214 int sf_mode;
9a64fbe4 215#endif
3cc62370 216 int fpu_enabled;
a9d9eb8f 217 int altivec_enabled;
0487d6a8 218 int spe_enabled;
3fc6c082 219 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 220 int singlestep_enabled;
d63001d1 221 int dcache_line_size;
79aceca5
FB		 222} DisasContext;
223
3fc6c082 224struct opc_handler_t {
79aceca5
FB		 225 /* invalid bits */
226 uint32_t inval;
9a64fbe4 227 /* instruction type */
0487d6a8 228 uint64_t type;
79aceca5
FB		 229 /* handler */
230 void (*handler)(DisasContext *ctx);
a750fc0b 231#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 232 const char *oname;
a750fc0b
JM		 233#endif
234#if defined(DO_PPC_STATISTICS)
76a66253
JM		 235 uint64_t count;
236#endif
3fc6c082 237};
79aceca5 238
7c58044c
JM		 239static always_inline void gen_reset_fpstatus (void)
240{
241#ifdef CONFIG_SOFTFLOAT
242 gen_op_reset_fpstatus();
243#endif
244}
245
0f2f39c2 246static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 247{
0f2f39c2 248 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 249
7c58044c
JM		 250 if (set_fprf != 0) {
251 /* This case might be optimized later */
252#if defined(OPTIMIZE_FPRF_UPDATE)
253 *gen_fprf_ptr++ = gen_opc_ptr;
254#endif
0f2f39c2 255 tcg_gen_movi_i32(t0, 1);
af12906f 256 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 257 if (unlikely(set_rc)) {
0f2f39c2 258 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 259 }
af12906f 260 gen_helper_float_check_status();
7c58044c
JM		 261 } else if (unlikely(set_rc)) {
262 /* We always need to compute fpcc */
0f2f39c2 263 tcg_gen_movi_i32(t0, 0);
af12906f 264 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 265 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 266 if (set_fprf)
af12906f 267 gen_helper_float_check_status();
7c58044c 268 }
af12906f 269
0f2f39c2 270 tcg_temp_free_i32(t0);
7c58044c
JM		 271}
272
273static always_inline void gen_optimize_fprf (void)
274{
275#if defined(OPTIMIZE_FPRF_UPDATE)
276 uint16_t **ptr;
277
278 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
279 *ptr = INDEX_op_nop1;
280 gen_fprf_ptr = gen_fprf_buf;
281#endif
282}
283
b068d6a7 284static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 285{
286#if defined(TARGET_PPC64)
287 if (ctx->sf_mode)
bd568f18 288 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 289 else
290#endif
bd568f18 291 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 292}
293
e1833e1f 294#define GEN_EXCP(ctx, excp, error) \
79aceca5 295do { \
64adab3f
AJ		 296 TCGv_i32 t0 = tcg_const_i32(excp); \
297 TCGv_i32 t1 = tcg_const_i32(error); \
e1833e1f 298 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 299 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c 300 } \
64adab3f
AJ		 301 gen_helper_raise_exception_err(t0, t1); \
302 tcg_temp_free_i32(t0); \
303 tcg_temp_free_i32(t1); \
9fddaa0c 304 ctx->exception = (excp); \
79aceca5
FB		 305} while (0)
306
e1833e1f
JM		 307#define GEN_EXCP_INVAL(ctx) \
308GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
309 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 310
e1833e1f
JM		 311#define GEN_EXCP_PRIVOPC(ctx) \
312GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
313 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 314
e1833e1f
JM		 315#define GEN_EXCP_PRIVREG(ctx) \
316GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
317 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
318
319#define GEN_EXCP_NO_FP(ctx) \
320GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
321
322#define GEN_EXCP_NO_AP(ctx) \
323GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 324
a9d9eb8f
JM		 325#define GEN_EXCP_NO_VR(ctx) \
326GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
327
f24e5695 328/* Stop translation */
b068d6a7 329static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 330{
d9bce9d9 331 gen_update_nip(ctx, ctx->nip);
e1833e1f 332 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 333}
334
f24e5695 335/* No need to update nip here, as execution flow will change */
b068d6a7 336static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 337{
e1833e1f 338 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 339}
340
79aceca5
FB		 341#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
342static void gen_##name (DisasContext *ctx); \
343GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
344static void gen_##name (DisasContext *ctx)
345
c7697e1f
JM		 346#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
347static void gen_##name (DisasContext *ctx); \
348GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
349static void gen_##name (DisasContext *ctx)
350
79aceca5
FB		 351typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
1235fc06 353#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 354 unsigned char pad[5];
355#else
356 unsigned char pad[1];
357#endif
79aceca5 358 opc_handler_t handler;
b55266b5 359 const char *oname;
79aceca5
FB		 360} opcode_t;
361
a750fc0b 362/*****************************************************************************/
79aceca5
FB		 363/*** Instruction decoding ***/
364#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 365static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 366{ \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368}
369
370#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 371static always_inline int32_t name (uint32_t opcode) \
79aceca5 372{ \
18fba28c 373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 374}
375
376/* Opcode part 1 */
377EXTRACT_HELPER(opc1, 26, 6);
378/* Opcode part 2 */
379EXTRACT_HELPER(opc2, 1, 5);
380/* Opcode part 3 */
381EXTRACT_HELPER(opc3, 6, 5);
382/* Update Cr0 flags */
383EXTRACT_HELPER(Rc, 0, 1);
384/* Destination */
385EXTRACT_HELPER(rD, 21, 5);
386/* Source */
387EXTRACT_HELPER(rS, 21, 5);
388/* First operand */
389EXTRACT_HELPER(rA, 16, 5);
390/* Second operand */
391EXTRACT_HELPER(rB, 11, 5);
392/* Third operand */
393EXTRACT_HELPER(rC, 6, 5);
394/*** Get CRn ***/
395EXTRACT_HELPER(crfD, 23, 3);
396EXTRACT_HELPER(crfS, 18, 3);
397EXTRACT_HELPER(crbD, 21, 5);
398EXTRACT_HELPER(crbA, 16, 5);
399EXTRACT_HELPER(crbB, 11, 5);
400/* SPR / TBL */
3fc6c082 401EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 402static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 403{
404 uint32_t sprn = _SPR(opcode);
405
406 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
407}
79aceca5
FB		 408/*** Get constants ***/
409EXTRACT_HELPER(IMM, 12, 8);
410/* 16 bits signed immediate value */
411EXTRACT_SHELPER(SIMM, 0, 16);
412/* 16 bits unsigned immediate value */
413EXTRACT_HELPER(UIMM, 0, 16);
414/* Bit count */
415EXTRACT_HELPER(NB, 11, 5);
416/* Shift count */
417EXTRACT_HELPER(SH, 11, 5);
418/* Mask start */
419EXTRACT_HELPER(MB, 6, 5);
420/* Mask end */
421EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 422/* Trap operand */
423EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 424
425EXTRACT_HELPER(CRM, 12, 8);
426EXTRACT_HELPER(FM, 17, 8);
427EXTRACT_HELPER(SR, 16, 4);
e4bb997e 428EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 429
79aceca5
FB		 430/*** Jump target decoding ***/
431/* Displacement */
432EXTRACT_SHELPER(d, 0, 16);
433/* Immediate address */
b068d6a7 434static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 435{
436 return (opcode >> 0) & 0x03FFFFFC;
437}
438
b068d6a7 439static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 440{
441 return (opcode >> 0) & 0xFFFC;
442}
443
444EXTRACT_HELPER(BO, 21, 5);
445EXTRACT_HELPER(BI, 16, 5);
446/* Absolute/relative address */
447EXTRACT_HELPER(AA, 1, 1);
448/* Link */
449EXTRACT_HELPER(LK, 0, 1);
450
451/* Create a mask between <start> and <end> bits */
b068d6a7 452static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 453{
76a66253 454 target_ulong ret;
79aceca5 455
76a66253
JM		 456#if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
6f2d8978 458 ret = UINT64_MAX << (63 - end);
76a66253 459 } else if (likely(end == 63)) {
6f2d8978 460 ret = UINT64_MAX >> start;
76a66253
JM		 461 }
462#else
463 if (likely(start == 0)) {
6f2d8978 464 ret = UINT32_MAX << (31 - end);
76a66253 465 } else if (likely(end == 31)) {
6f2d8978 466 ret = UINT32_MAX >> start;
76a66253
JM		 467 }
468#endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
79aceca5
FB		 475
476 return ret;
477}
478
a750fc0b
JM		 479/*****************************************************************************/
480/* PowerPC Instructions types definitions */
481enum {
1b413d55 482 PPC_NONE = 0x0000000000000000ULL,
12de9a39 483 /* PowerPC base instructions set */
1b413d55
JM		 484 PPC_INSNS_BASE = 0x0000000000000001ULL,
485 /* integer operations instructions */
a750fc0b 486#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 487 /* flow control instructions */
a750fc0b 488#define PPC_FLOW PPC_INSNS_BASE
1b413d55 489 /* virtual memory instructions */
a750fc0b 490#define PPC_MEM PPC_INSNS_BASE
1b413d55 491 /* ld/st with reservation instructions */
a750fc0b 492#define PPC_RES PPC_INSNS_BASE
1b413d55 493 /* spr/msr access instructions */
a750fc0b 494#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 495 /* Deprecated instruction sets */
496 /* Original POWER instruction set */
f610349f 497 PPC_POWER = 0x0000000000000002ULL,
1b413d55 498 /* POWER2 instruction set extension */
f610349f 499 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 500 /* Power RTC support */
f610349f 501 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 502 /* Power-to-PowerPC bridge (601) */
f610349f 503 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 504 /* 64 bits PowerPC instruction set */
f610349f 505 PPC_64B = 0x0000000000000020ULL,
1b413d55 506 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 507 PPC_64BX = 0x0000000000000040ULL,
1b413d55 508 /* 64 bits hypervisor extensions */
f610349f 509 PPC_64H = 0x0000000000000080ULL,
1b413d55 510 /* New wait instruction (PowerPC 2.0x) */
f610349f 511 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 512 /* Time base mftb instruction */
f610349f 513 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 514
515 /* Fixed-point unit extensions */
516 /* PowerPC 602 specific */
f610349f 517 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 518 /* isel instruction */
519 PPC_ISEL = 0x0000000000000800ULL,
520 /* popcntb instruction */
521 PPC_POPCNTB = 0x0000000000001000ULL,
522 /* string load / store */
523 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 524
525 /* Floating-point unit extensions */
526 /* Optional floating point instructions */
527 PPC_FLOAT = 0x0000000000010000ULL,
528 /* New floating-point extensions (PowerPC 2.0x) */
529 PPC_FLOAT_EXT = 0x0000000000020000ULL,
530 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
531 PPC_FLOAT_FRES = 0x0000000000080000ULL,
532 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
533 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
534 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
535 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
536
537 /* Vector/SIMD extensions */
538 /* Altivec support */
539 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 540 /* PowerPC 2.03 SPE extension */
05332d70 541 PPC_SPE = 0x0000000002000000ULL,
1b413d55 542 /* PowerPC 2.03 SPE floating-point extension */
05332d70 543 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 544
12de9a39 545 /* Optional memory control instructions */
1b413d55
JM		 546 PPC_MEM_TLBIA = 0x0000000010000000ULL,
547 PPC_MEM_TLBIE = 0x0000000020000000ULL,
548 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
549 /* sync instruction */
550 PPC_MEM_SYNC = 0x0000000080000000ULL,
551 /* eieio instruction */
552 PPC_MEM_EIEIO = 0x0000000100000000ULL,
553
554 /* Cache control instructions */
c8623f2e 555 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 556 /* icbi instruction */
05332d70 557 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 558 /* dcbz instruction with fixed cache line size */
05332d70 559 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 560 /* dcbz instruction with tunable cache line size */
05332d70 561 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 562 /* dcba instruction */
05332d70
JM		 563 PPC_CACHE_DCBA = 0x0000002000000000ULL,
564 /* Freescale cache locking instructions */
565 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 566
567 /* MMU related extensions */
568 /* external control instructions */
05332d70 569 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 570 /* segment register access instructions */
05332d70 571 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 572 /* PowerPC 6xx TLB management instructions */
05332d70 573 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 574 /* PowerPC 74xx TLB management instructions */
05332d70 575 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 576 /* PowerPC 40x TLB management instructions */
05332d70 577 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 578 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 579 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 580 /* SLB management */
05332d70 581 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 582
12de9a39 583 /* Embedded PowerPC dedicated instructions */
05332d70 584 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 585 /* PowerPC 40x exception model */
05332d70 586 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 587 /* PowerPC 405 Mac instructions */
05332d70 588 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 589 /* PowerPC 440 specific instructions */
05332d70 590 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 591 /* BookE (embedded) PowerPC specification */
05332d70
JM		 592 PPC_BOOKE = 0x0010000000000000ULL,
593 /* mfapidi instruction */
594 PPC_MFAPIDI = 0x0020000000000000ULL,
595 /* tlbiva instruction */
596 PPC_TLBIVA = 0x0040000000000000ULL,
597 /* tlbivax instruction */
598 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 599 /* PowerPC 4xx dedicated instructions */
05332d70 600 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 601 /* PowerPC 40x ibct instructions */
05332d70 602 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 603 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 604 PPC_RFMCI = 0x0400000000000000ULL,
605 /* rfdi instruction */
606 PPC_RFDI = 0x0800000000000000ULL,
607 /* DCR accesses */
608 PPC_DCR = 0x1000000000000000ULL,
609 /* DCR extended accesse */
610 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 611 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 612 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 613};
614
615/*****************************************************************************/
616/* PowerPC instructions table */
3fc6c082
FB		 617#if HOST_LONG_BITS == 64
618#define OPC_ALIGN 8
619#else
620#define OPC_ALIGN 4
621#endif
1b039c09 622#if defined(__APPLE__)
d9bce9d9 623#define OPCODES_SECTION \
3fc6c082 624 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 625#else
d9bce9d9 626#define OPCODES_SECTION \
3fc6c082 627 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 628#endif
629
76a66253 630#if defined(DO_PPC_STATISTICS)
79aceca5 631#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 632OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 633 .opc1 = op1, \
634 .opc2 = op2, \
635 .opc3 = op3, \
18fba28c 636 .pad = { 0, }, \
79aceca5
FB		 637 .handler = { \
638 .inval = invl, \
9a64fbe4 639 .type = _typ, \
79aceca5 640 .handler = &gen_##name, \
76a66253 641 .oname = stringify(name), \
79aceca5 642 }, \
3fc6c082 643 .oname = stringify(name), \
79aceca5 644}
c7697e1f
JM		 645#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
646OPCODES_SECTION opcode_t opc_##name = { \
647 .opc1 = op1, \
648 .opc2 = op2, \
649 .opc3 = op3, \
650 .pad = { 0, }, \
651 .handler = { \
652 .inval = invl, \
653 .type = _typ, \
654 .handler = &gen_##name, \
655 .oname = onam, \
656 }, \
657 .oname = onam, \
658}
76a66253
JM		 659#else
660#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
661OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = op1, \
663 .opc2 = op2, \
664 .opc3 = op3, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = invl, \
668 .type = _typ, \
669 .handler = &gen_##name, \
670 }, \
671 .oname = stringify(name), \
672}
c7697e1f
JM		 673#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
674OPCODES_SECTION opcode_t opc_##name = { \
675 .opc1 = op1, \
676 .opc2 = op2, \
677 .opc3 = op3, \
678 .pad = { 0, }, \
679 .handler = { \
680 .inval = invl, \
681 .type = _typ, \
682 .handler = &gen_##name, \
683 }, \
684 .oname = onam, \
685}
76a66253 686#endif
79aceca5
FB		 687
688#define GEN_OPCODE_MARK(name) \
18fba28c 689OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 690 .opc1 = 0xFF, \
691 .opc2 = 0xFF, \
692 .opc3 = 0xFF, \
18fba28c 693 .pad = { 0, }, \
79aceca5
FB		 694 .handler = { \
695 .inval = 0x00000000, \
9a64fbe4 696 .type = 0x00, \
79aceca5
FB		 697 .handler = NULL, \
698 }, \
3fc6c082 699 .oname = stringify(name), \
79aceca5
FB		 700}
701
702/* Start opcode list */
703GEN_OPCODE_MARK(start);
704
705/* Invalid instruction */
9a64fbe4
FB		 706GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
707{
e1833e1f 708 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 709}
710
79aceca5
FB		 711static opc_handler_t invalid_handler = {
712 .inval = 0xFFFFFFFF,
9a64fbe4 713 .type = PPC_NONE,
79aceca5
FB		 714 .handler = gen_invalid,
715};
716
e1571908
AJ		 717/*** Integer comparison ***/
718
ea363694 719static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 720{
721 int l1, l2, l3;
722
269f3e95
AJ		 723 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
724 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 725 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
726
727 l1 = gen_new_label();
728 l2 = gen_new_label();
729 l3 = gen_new_label();
730 if (s) {
ea363694
AJ		 731 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
732 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 733 } else {
ea363694
AJ		 734 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
735 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 736 }
737 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
738 tcg_gen_br(l3);
739 gen_set_label(l1);
740 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
741 tcg_gen_br(l3);
742 gen_set_label(l2);
743 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
744 gen_set_label(l3);
745}
746
ea363694 747static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 748{
ea363694
AJ		 749 TCGv t0 = tcg_const_local_tl(arg1);
750 gen_op_cmp(arg0, t0, s, crf);
751 tcg_temp_free(t0);
e1571908
AJ		 752}
753
754#if defined(TARGET_PPC64)
ea363694 755static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 756{
ea363694 757 TCGv t0, t1;
a7812ae4
PB		 758 t0 = tcg_temp_local_new();
759 t1 = tcg_temp_local_new();
e1571908 760 if (s) {
ea363694
AJ		 761 tcg_gen_ext32s_tl(t0, arg0);
762 tcg_gen_ext32s_tl(t1, arg1);
e1571908 763 } else {
ea363694
AJ		 764 tcg_gen_ext32u_tl(t0, arg0);
765 tcg_gen_ext32u_tl(t1, arg1);
e1571908 766 }
ea363694
AJ		 767 gen_op_cmp(t0, t1, s, crf);
768 tcg_temp_free(t1);
769 tcg_temp_free(t0);
e1571908
AJ		 770}
771
ea363694 772static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 773{
ea363694
AJ		 774 TCGv t0 = tcg_const_local_tl(arg1);
775 gen_op_cmp32(arg0, t0, s, crf);
776 tcg_temp_free(t0);
e1571908
AJ		 777}
778#endif
779
780static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
781{
782#if defined(TARGET_PPC64)
783 if (!(ctx->sf_mode))
784 gen_op_cmpi32(reg, 0, 1, 0);
785 else
786#endif
787 gen_op_cmpi(reg, 0, 1, 0);
788}
789
790/* cmp */
791GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
792{
793#if defined(TARGET_PPC64)
794 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
795 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
796 1, crfD(ctx->opcode));
797 else
798#endif
799 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
800 1, crfD(ctx->opcode));
801}
802
803/* cmpi */
804GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
805{
806#if defined(TARGET_PPC64)
807 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
808 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
809 1, crfD(ctx->opcode));
810 else
811#endif
812 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
813 1, crfD(ctx->opcode));
814}
815
816/* cmpl */
817GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
818{
819#if defined(TARGET_PPC64)
820 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
821 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
822 0, crfD(ctx->opcode));
823 else
824#endif
825 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
826 0, crfD(ctx->opcode));
827}
828
829/* cmpli */
830GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
831{
832#if defined(TARGET_PPC64)
833 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
834 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
835 0, crfD(ctx->opcode));
836 else
837#endif
838 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
839 0, crfD(ctx->opcode));
840}
841
842/* isel (PowerPC 2.03 specification) */
843GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
844{
845 int l1, l2;
846 uint32_t bi = rC(ctx->opcode);
847 uint32_t mask;
a7812ae4 848 TCGv_i32 t0;
e1571908
AJ		 849
850 l1 = gen_new_label();
851 l2 = gen_new_label();
852
853 mask = 1 << (3 - (bi & 0x03));
a7812ae4 854 t0 = tcg_temp_new_i32();
fea0c503
AJ		 855 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
856 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 857 if (rA(ctx->opcode) == 0)
858 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
859 else
860 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
861 tcg_gen_br(l2);
862 gen_set_label(l1);
863 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
864 gen_set_label(l2);
a7812ae4 865 tcg_temp_free_i32(t0);
e1571908
AJ		 866}
867
79aceca5 868/*** Integer arithmetic ***/
79aceca5 869
74637406
AJ		 870static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
871{
872 int l1;
873 TCGv t0;
79aceca5 874
74637406
AJ		 875 l1 = gen_new_label();
876 /* Start with XER OV disabled, the most likely case */
877 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 878 t0 = tcg_temp_local_new();
74637406
AJ		 879 tcg_gen_xor_tl(t0, arg0, arg1);
880#if defined(TARGET_PPC64)
881 if (!ctx->sf_mode)
882 tcg_gen_ext32s_tl(t0, t0);
883#endif
884 if (sub)
885 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
886 else
887 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
888 tcg_gen_xor_tl(t0, arg1, arg2);
889#if defined(TARGET_PPC64)
890 if (!ctx->sf_mode)
891 tcg_gen_ext32s_tl(t0, t0);
892#endif
893 if (sub)
894 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
895 else
896 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
897 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
898 gen_set_label(l1);
899 tcg_temp_free(t0);
79aceca5
FB		 900}
901
74637406
AJ		 902static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
903{
904 int l1 = gen_new_label();
d9bce9d9
JM		 905
906#if defined(TARGET_PPC64)
74637406
AJ		 907 if (!(ctx->sf_mode)) {
908 TCGv t0, t1;
a7812ae4
PB		 909 t0 = tcg_temp_new();
910 t1 = tcg_temp_new();
d9bce9d9 911
74637406
AJ		 912 tcg_gen_ext32u_tl(t0, arg1);
913 tcg_gen_ext32u_tl(t1, arg2);
914 if (sub) {
915 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 916 } else {
74637406
AJ		 917 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
918 }
a9730017
AJ		 919 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
920 gen_set_label(l1);
921 tcg_temp_free(t0);
922 tcg_temp_free(t1);
74637406
AJ		 923 } else
924#endif
a9730017
AJ		 925 {
926 if (sub) {
927 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
928 } else {
929 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
930 }
931 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
932 gen_set_label(l1);
74637406 933 }
d9bce9d9
JM		 934}
935
74637406
AJ		 936/* Common add function */
937static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
938 int add_ca, int compute_ca, int compute_ov)
939{
940 TCGv t0, t1;
d9bce9d9 941
74637406 942 if ((!compute_ca && !compute_ov) ||
a7812ae4 943 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 944 t0 = ret;
945 } else {
a7812ae4 946 t0 = tcg_temp_local_new();
74637406 947 }
79aceca5 948
74637406 949 if (add_ca) {
a7812ae4 950 t1 = tcg_temp_local_new();
74637406
AJ		 951 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
952 tcg_gen_shri_tl(t1, t1, XER_CA);
953 }
79aceca5 954
74637406
AJ		 955 if (compute_ca && compute_ov) {
956 /* Start with XER CA and OV disabled, the most likely case */
957 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
958 } else if (compute_ca) {
959 /* Start with XER CA disabled, the most likely case */
960 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
961 } else if (compute_ov) {
962 /* Start with XER OV disabled, the most likely case */
963 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
964 }
79aceca5 965
74637406
AJ		 966 tcg_gen_add_tl(t0, arg1, arg2);
967
968 if (compute_ca) {
969 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
970 }
971 if (add_ca) {
972 tcg_gen_add_tl(t0, t0, t1);
973 gen_op_arith_compute_ca(ctx, t0, t1, 0);
974 tcg_temp_free(t1);
975 }
976 if (compute_ov) {
977 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
978 }
979
980 if (unlikely(Rc(ctx->opcode) != 0))
981 gen_set_Rc0(ctx, t0);
982
a7812ae4 983 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 984 tcg_gen_mov_tl(ret, t0);
985 tcg_temp_free(t0);
986 }
39dd32ee 987}
74637406
AJ		 988/* Add functions with two operands */
989#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
990GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
991{ \
992 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
994 add_ca, compute_ca, compute_ov); \
995}
996/* Add functions with one operand and one immediate */
997#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
998 add_ca, compute_ca, compute_ov) \
999GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
1000{ \
1001 TCGv t0 = tcg_const_local_tl(const_val); \
1002 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], t0, \
1004 add_ca, compute_ca, compute_ov); \
1005 tcg_temp_free(t0); \
1006}
1007
1008/* add add. addo addo. */
1009GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1010GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1011/* addc addc. addco addco. */
1012GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1013GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1014/* adde adde. addeo addeo. */
1015GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1016GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1017/* addme addme. addmeo addmeo. */
1018GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1019GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1020/* addze addze. addzeo addzeo.*/
1021GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1022GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1023/* addi */
1024GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1025{
74637406
AJ		 1026 target_long simm = SIMM(ctx->opcode);
1027
1028 if (rA(ctx->opcode) == 0) {
1029 /* li case */
1030 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1031 } else {
1032 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1033 }
d9bce9d9 1034}
74637406
AJ		 1035/* addic addic.*/
1036static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1037 int compute_Rc0)
d9bce9d9 1038{
74637406
AJ		 1039 target_long simm = SIMM(ctx->opcode);
1040
1041 /* Start with XER CA and OV disabled, the most likely case */
1042 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1043
1044 if (likely(simm != 0)) {
a7812ae4 1045 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1046 tcg_gen_addi_tl(t0, arg1, simm);
1047 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1048 tcg_gen_mov_tl(ret, t0);
1049 tcg_temp_free(t0);
1050 } else {
1051 tcg_gen_mov_tl(ret, arg1);
1052 }
1053 if (compute_Rc0) {
1054 gen_set_Rc0(ctx, ret);
1055 }
d9bce9d9 1056}
74637406 1057GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1058{
74637406 1059 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1060}
74637406 1061GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1062{
74637406 1063 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1064}
74637406
AJ		 1065/* addis */
1066GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1067{
74637406
AJ		 1068 target_long simm = SIMM(ctx->opcode);
1069
1070 if (rA(ctx->opcode) == 0) {
1071 /* lis case */
1072 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1073 } else {
1074 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1075 }
d9bce9d9 1076}
74637406
AJ		 1077
1078static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1079 int sign, int compute_ov)
d9bce9d9 1080{
2ef1b120
AJ		 1081 int l1 = gen_new_label();
1082 int l2 = gen_new_label();
a7812ae4
PB		 1083 TCGv_i32 t0 = tcg_temp_local_new_i32();
1084 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1085
2ef1b120
AJ		 1086 tcg_gen_trunc_tl_i32(t0, arg1);
1087 tcg_gen_trunc_tl_i32(t1, arg2);
1088 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1089 if (sign) {
2ef1b120
AJ		 1090 int l3 = gen_new_label();
1091 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1092 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1093 gen_set_label(l3);
2ef1b120 1094 tcg_gen_div_i32(t0, t0, t1);
74637406 1095 } else {
2ef1b120 1096 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1097 }
1098 if (compute_ov) {
1099 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1100 }
1101 tcg_gen_br(l2);
1102 gen_set_label(l1);
1103 if (sign) {
2ef1b120 1104 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1105 } else {
1106 tcg_gen_movi_i32(t0, 0);
1107 }
1108 if (compute_ov) {
1109 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1110 }
1111 gen_set_label(l2);
2ef1b120 1112 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1113 tcg_temp_free_i32(t0);
1114 tcg_temp_free_i32(t1);
74637406
AJ		 1115 if (unlikely(Rc(ctx->opcode) != 0))
1116 gen_set_Rc0(ctx, ret);
d9bce9d9 1117}
74637406
AJ		 1118/* Div functions */
1119#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1120GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1121{ \
1122 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1123 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1124 sign, compute_ov); \
1125}
1126/* divwu divwu. divwuo divwuo. */
1127GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1128GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1129/* divw divw. divwo divwo. */
1130GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1131GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1132#if defined(TARGET_PPC64)
2ef1b120
AJ		 1133static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1134 int sign, int compute_ov)
d9bce9d9 1135{
2ef1b120
AJ		 1136 int l1 = gen_new_label();
1137 int l2 = gen_new_label();
74637406
AJ		 1138
1139 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1140 if (sign) {
2ef1b120 1141 int l3 = gen_new_label();
74637406
AJ		 1142 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1143 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1144 gen_set_label(l3);
74637406
AJ		 1145 tcg_gen_div_i64(ret, arg1, arg2);
1146 } else {
1147 tcg_gen_divu_i64(ret, arg1, arg2);
1148 }
1149 if (compute_ov) {
1150 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1151 }
1152 tcg_gen_br(l2);
1153 gen_set_label(l1);
1154 if (sign) {
1155 tcg_gen_sari_i64(ret, arg1, 63);
1156 } else {
1157 tcg_gen_movi_i64(ret, 0);
1158 }
1159 if (compute_ov) {
1160 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1161 }
1162 gen_set_label(l2);
1163 if (unlikely(Rc(ctx->opcode) != 0))
1164 gen_set_Rc0(ctx, ret);
d9bce9d9 1165}
74637406
AJ		 1166#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1167GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1168{ \
2ef1b120
AJ		 1169 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1170 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1171 sign, compute_ov); \
74637406
AJ		 1172}
1173/* divwu divwu. divwuo divwuo. */
1174GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1175GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1176/* divw divw. divwo divwo. */
1177GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1178GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1179#endif
74637406
AJ		 1180
1181/* mulhw mulhw. */
1182GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1183{
a7812ae4 1184 TCGv_i64 t0, t1;
74637406 1185
a7812ae4
PB		 1186 t0 = tcg_temp_new_i64();
1187 t1 = tcg_temp_new_i64();
74637406
AJ		 1188#if defined(TARGET_PPC64)
1189 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1190 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1191 tcg_gen_mul_i64(t0, t0, t1);
1192 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1193#else
1194 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1195 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1196 tcg_gen_mul_i64(t0, t0, t1);
1197 tcg_gen_shri_i64(t0, t0, 32);
1198 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1199#endif
a7812ae4
PB		 1200 tcg_temp_free_i64(t0);
1201 tcg_temp_free_i64(t1);
74637406
AJ		 1202 if (unlikely(Rc(ctx->opcode) != 0))
1203 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1204}
74637406
AJ		 1205/* mulhwu mulhwu. */
1206GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1207{
a7812ae4 1208 TCGv_i64 t0, t1;
74637406 1209
a7812ae4
PB		 1210 t0 = tcg_temp_new_i64();
1211 t1 = tcg_temp_new_i64();
d9bce9d9 1212#if defined(TARGET_PPC64)
74637406
AJ		 1213 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1214 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1215 tcg_gen_mul_i64(t0, t0, t1);
1216 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1217#else
1218 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1219 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1220 tcg_gen_mul_i64(t0, t0, t1);
1221 tcg_gen_shri_i64(t0, t0, 32);
1222 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1223#endif
a7812ae4
PB		 1224 tcg_temp_free_i64(t0);
1225 tcg_temp_free_i64(t1);
74637406
AJ		 1226 if (unlikely(Rc(ctx->opcode) != 0))
1227 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1228}
74637406
AJ		 1229/* mullw mullw. */
1230GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1231{
74637406
AJ		 1232 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1233 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1234 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1235 if (unlikely(Rc(ctx->opcode) != 0))
1236 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1237}
74637406
AJ		 1238/* mullwo mullwo. */
1239GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1240{
74637406 1241 int l1;
a7812ae4 1242 TCGv_i64 t0, t1;
74637406 1243
a7812ae4
PB		 1244 t0 = tcg_temp_new_i64();
1245 t1 = tcg_temp_new_i64();
74637406
AJ		 1246 l1 = gen_new_label();
1247 /* Start with XER OV disabled, the most likely case */
1248 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1249#if defined(TARGET_PPC64)
1250 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1251 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1252#else
1253 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1254 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1255#endif
74637406
AJ		 1256 tcg_gen_mul_i64(t0, t0, t1);
1257#if defined(TARGET_PPC64)
1258 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1259 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1260#else
1261 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1262 tcg_gen_ext32s_i64(t1, t0);
1263 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1264#endif
1265 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1266 gen_set_label(l1);
a7812ae4
PB		 1267 tcg_temp_free_i64(t0);
1268 tcg_temp_free_i64(t1);
74637406
AJ		 1269 if (unlikely(Rc(ctx->opcode) != 0))
1270 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1271}
74637406
AJ		 1272/* mulli */
1273GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1274{
74637406
AJ		 1275 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1276 SIMM(ctx->opcode));
d9bce9d9
JM		 1277}
1278#if defined(TARGET_PPC64)
74637406
AJ		 1279#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1280GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1281{ \
a7812ae4 1282 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1284 if (unlikely(Rc(ctx->opcode) != 0)) \
1285 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1286}
74637406
AJ		 1287/* mulhd mulhd. */
1288GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1289/* mulhdu mulhdu. */
1290GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1291/* mulld mulld. */
1292GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1293{
74637406
AJ		 1294 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1295 cpu_gpr[rB(ctx->opcode)]);
1296 if (unlikely(Rc(ctx->opcode) != 0))
1297 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1298}
74637406
AJ		 1299/* mulldo mulldo. */
1300GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1301#endif
74637406
AJ		 1302
1303/* neg neg. nego nego. */
ec6469a3 1304static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1305{
ec6469a3
AJ		 1306 int l1 = gen_new_label();
1307 int l2 = gen_new_label();
a7812ae4 1308 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1309#if defined(TARGET_PPC64)
74637406 1310 if (ctx->sf_mode) {
741a7444 1311 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1312 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1313 } else
1314#endif
1315 {
1316 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1317 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1318 }
74637406
AJ		 1319 tcg_gen_neg_tl(ret, arg1);
1320 if (ov_check) {
1321 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1322 }
1323 tcg_gen_br(l2);
1324 gen_set_label(l1);
ec6469a3 1325 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1326 if (ov_check) {
1327 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1328 }
1329 gen_set_label(l2);
ec6469a3 1330 tcg_temp_free(t0);
74637406
AJ		 1331 if (unlikely(Rc(ctx->opcode) != 0))
1332 gen_set_Rc0(ctx, ret);
1333}
1334GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1335{
ec6469a3 1336 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1337}
74637406 1338GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1339{
ec6469a3 1340 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1341}
74637406
AJ		 1342
1343/* Common subf function */
1344static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1345 int add_ca, int compute_ca, int compute_ov)
79aceca5 1346{
74637406 1347 TCGv t0, t1;
76a66253 1348
74637406 1349 if ((!compute_ca && !compute_ov) ||
a7812ae4 1350 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1351 t0 = ret;
e864cabd 1352 } else {
a7812ae4 1353 t0 = tcg_temp_local_new();
d9bce9d9 1354 }
76a66253 1355
74637406 1356 if (add_ca) {
a7812ae4 1357 t1 = tcg_temp_local_new();
74637406
AJ		 1358 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1359 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1360 }
79aceca5 1361
74637406
AJ		 1362 if (compute_ca && compute_ov) {
1363 /* Start with XER CA and OV disabled, the most likely case */
1364 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1365 } else if (compute_ca) {
1366 /* Start with XER CA disabled, the most likely case */
1367 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1368 } else if (compute_ov) {
1369 /* Start with XER OV disabled, the most likely case */
1370 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1371 }
1372
1373 if (add_ca) {
1374 tcg_gen_not_tl(t0, arg1);
1375 tcg_gen_add_tl(t0, t0, arg2);
1376 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1377 tcg_gen_add_tl(t0, t0, t1);
1378 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1379 tcg_temp_free(t1);
79aceca5 1380 } else {
74637406
AJ		 1381 tcg_gen_sub_tl(t0, arg2, arg1);
1382 if (compute_ca) {
1383 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1384 }
1385 }
1386 if (compute_ov) {
1387 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1388 }
1389
1390 if (unlikely(Rc(ctx->opcode) != 0))
1391 gen_set_Rc0(ctx, t0);
1392
a7812ae4 1393 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1394 tcg_gen_mov_tl(ret, t0);
1395 tcg_temp_free(t0);
79aceca5 1396 }
79aceca5 1397}
74637406
AJ		 1398/* Sub functions with Two operands functions */
1399#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1400GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1401{ \
1402 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1403 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1404 add_ca, compute_ca, compute_ov); \
1405}
1406/* Sub functions with one operand and one immediate */
1407#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1408 add_ca, compute_ca, compute_ov) \
1409GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1410{ \
1411 TCGv t0 = tcg_const_local_tl(const_val); \
1412 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1413 cpu_gpr[rA(ctx->opcode)], t0, \
1414 add_ca, compute_ca, compute_ov); \
1415 tcg_temp_free(t0); \
1416}
1417/* subf subf. subfo subfo. */
1418GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1419GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1420/* subfc subfc. subfco subfco. */
1421GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1422GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1423/* subfe subfe. subfeo subfo. */
1424GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1425GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1426/* subfme subfme. subfmeo subfmeo. */
1427GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1428GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1429/* subfze subfze. subfzeo subfzeo.*/
1430GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1431GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1432/* subfic */
1433GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1434{
74637406
AJ		 1435 /* Start with XER CA and OV disabled, the most likely case */
1436 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1437 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1438 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1439 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1440 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1441 tcg_temp_free(t1);
1442 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1443 tcg_temp_free(t0);
79aceca5
FB		 1444}
1445
79aceca5 1446/*** Integer logical ***/
26d67362
AJ		 1447#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1448GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1449{ \
26d67362
AJ		 1450 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1451 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1452 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1453 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1454}
79aceca5 1455
26d67362 1456#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1457GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1458{ \
26d67362 1459 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1460 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1462}
1463
1464/* and & and. */
26d67362 1465GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1466/* andc & andc. */
26d67362 1467GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1468/* andi. */
c7697e1f 1469GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1470{
26d67362
AJ		 1471 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1472 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1473}
1474/* andis. */
c7697e1f 1475GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1476{
26d67362
AJ		 1477 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1478 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1479}
79aceca5 1480/* cntlzw */
26d67362
AJ		 1481GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1482{
a7812ae4 1483 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1484 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1485 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1486}
79aceca5 1487/* eqv & eqv. */
26d67362 1488GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1489/* extsb & extsb. */
26d67362 1490GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1491/* extsh & extsh. */
26d67362 1492GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1493/* nand & nand. */
26d67362 1494GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1495/* nor & nor. */
26d67362 1496GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1497/* or & or. */
9a64fbe4
FB		 1498GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1499{
76a66253
JM		 1500 int rs, ra, rb;
1501
1502 rs = rS(ctx->opcode);
1503 ra = rA(ctx->opcode);
1504 rb = rB(ctx->opcode);
1505 /* Optimisation for mr. ri case */
1506 if (rs != ra || rs != rb) {
26d67362
AJ		 1507 if (rs != rb)
1508 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1509 else
1510 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1511 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1512 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1513 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1514 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1515#if defined(TARGET_PPC64)
1516 } else {
26d67362
AJ		 1517 int prio = 0;
1518
c80f84e3
JM		 1519 switch (rs) {
1520 case 1:
1521 /* Set process priority to low */
26d67362 1522 prio = 2;
c80f84e3
JM		 1523 break;
1524 case 6:
1525 /* Set process priority to medium-low */
26d67362 1526 prio = 3;
c80f84e3
JM		 1527 break;
1528 case 2:
1529 /* Set process priority to normal */
26d67362 1530 prio = 4;
c80f84e3 1531 break;
be147d08
JM		 1532#if !defined(CONFIG_USER_ONLY)
1533 case 31:
1534 if (ctx->supervisor > 0) {
1535 /* Set process priority to very low */
26d67362 1536 prio = 1;
be147d08
JM		 1537 }
1538 break;
1539 case 5:
1540 if (ctx->supervisor > 0) {
1541 /* Set process priority to medium-hight */
26d67362 1542 prio = 5;
be147d08
JM		 1543 }
1544 break;
1545 case 3:
1546 if (ctx->supervisor > 0) {
1547 /* Set process priority to high */
26d67362 1548 prio = 6;
be147d08
JM		 1549 }
1550 break;
be147d08
JM		 1551 case 7:
1552 if (ctx->supervisor > 1) {
1553 /* Set process priority to very high */
26d67362 1554 prio = 7;
be147d08
JM		 1555 }
1556 break;
be147d08 1557#endif
c80f84e3
JM		 1558 default:
1559 /* nop */
1560 break;
1561 }
26d67362 1562 if (prio) {
a7812ae4 1563 TCGv t0 = tcg_temp_new();
ea363694
AJ		 1564 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1565 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1566 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1567 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1568 tcg_temp_free(t0);
26d67362 1569 }
c80f84e3 1570#endif
9a64fbe4 1571 }
9a64fbe4 1572}
79aceca5 1573/* orc & orc. */
26d67362 1574GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1575/* xor & xor. */
9a64fbe4
FB		 1576GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1577{
9a64fbe4 1578 /* Optimisation for "set to zero" case */
26d67362 1579 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1580 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1581 else
1582 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1583 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1584 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1585}
79aceca5
FB		 1586/* ori */
1587GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1588{
76a66253 1589 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1590
9a64fbe4
FB		 1591 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1592 /* NOP */
76a66253 1593 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1594 return;
76a66253 1595 }
26d67362 1596 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1597}
1598/* oris */
1599GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1600{
76a66253 1601 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1602
9a64fbe4
FB		 1603 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1604 /* NOP */
1605 return;
76a66253 1606 }
26d67362 1607 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1608}
1609/* xori */
1610GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1611{
76a66253 1612 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1613
1614 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1615 /* NOP */
1616 return;
1617 }
26d67362 1618 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1619}
79aceca5
FB		 1620/* xoris */
1621GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1622{
76a66253 1623 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1624
1625 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1626 /* NOP */
1627 return;
1628 }
26d67362 1629 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1630}
d9bce9d9 1631/* popcntb : PowerPC 2.03 specification */
05332d70 1632GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1633{
d9bce9d9
JM		 1634#if defined(TARGET_PPC64)
1635 if (ctx->sf_mode)
a7812ae4 1636 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1637 else
1638#endif
a7812ae4 1639 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1640}
1641
1642#if defined(TARGET_PPC64)
1643/* extsw & extsw. */
26d67362 1644GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1645/* cntlzd */
26d67362
AJ		 1646GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1647{
a7812ae4 1648 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1649 if (unlikely(Rc(ctx->opcode) != 0))
1650 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1651}
d9bce9d9
JM		 1652#endif
1653
79aceca5
FB		 1654/*** Integer rotate ***/
1655/* rlwimi & rlwimi. */
1656GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1657{
76a66253 1658 uint32_t mb, me, sh;
79aceca5
FB		 1659
1660 mb = MB(ctx->opcode);
1661 me = ME(ctx->opcode);
76a66253 1662 sh = SH(ctx->opcode);
d03ef511
AJ		 1663 if (likely(sh == 0 && mb == 0 && me == 31)) {
1664 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1665 } else {
d03ef511 1666 target_ulong mask;
a7812ae4
PB		 1667 TCGv t1;
1668 TCGv t0 = tcg_temp_new();
54843a58 1669#if defined(TARGET_PPC64)
a7812ae4
PB		 1670 TCGv_i32 t2 = tcg_temp_new_i32();
1671 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1672 tcg_gen_rotli_i32(t2, t2, sh);
1673 tcg_gen_extu_i32_i64(t0, t2);
1674 tcg_temp_free_i32(t2);
54843a58
AJ		 1675#else
1676 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1677#endif
76a66253 1678#if defined(TARGET_PPC64)
d03ef511
AJ		 1679 mb += 32;
1680 me += 32;
76a66253 1681#endif
d03ef511 1682 mask = MASK(mb, me);
a7812ae4 1683 t1 = tcg_temp_new();
d03ef511
AJ		 1684 tcg_gen_andi_tl(t0, t0, mask);
1685 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1686 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1687 tcg_temp_free(t0);
1688 tcg_temp_free(t1);
1689 }
76a66253 1690 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1691 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1692}
1693/* rlwinm & rlwinm. */
1694GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1695{
1696 uint32_t mb, me, sh;
3b46e624 1697
79aceca5
FB		 1698 sh = SH(ctx->opcode);
1699 mb = MB(ctx->opcode);
1700 me = ME(ctx->opcode);
d03ef511
AJ		 1701
1702 if (likely(mb == 0 && me == (31 - sh))) {
1703 if (likely(sh == 0)) {
1704 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1705 } else {
a7812ae4 1706 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1707 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1708 tcg_gen_shli_tl(t0, t0, sh);
1709 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1710 tcg_temp_free(t0);
79aceca5 1711 }
d03ef511 1712 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1713 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1714 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1715 tcg_gen_shri_tl(t0, t0, mb);
1716 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1717 tcg_temp_free(t0);
1718 } else {
a7812ae4 1719 TCGv t0 = tcg_temp_new();
54843a58 1720#if defined(TARGET_PPC64)
a7812ae4 1721 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1722 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1723 tcg_gen_rotli_i32(t1, t1, sh);
1724 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1725 tcg_temp_free_i32(t1);
54843a58
AJ		 1726#else
1727 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1728#endif
76a66253 1729#if defined(TARGET_PPC64)
d03ef511
AJ		 1730 mb += 32;
1731 me += 32;
76a66253 1732#endif
d03ef511
AJ		 1733 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1734 tcg_temp_free(t0);
1735 }
76a66253 1736 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1737 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1738}
1739/* rlwnm & rlwnm. */
1740GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1741{
1742 uint32_t mb, me;
54843a58
AJ		 1743 TCGv t0;
1744#if defined(TARGET_PPC64)
a7812ae4 1745 TCGv_i32 t1, t2;
54843a58 1746#endif
79aceca5
FB		 1747
1748 mb = MB(ctx->opcode);
1749 me = ME(ctx->opcode);
a7812ae4 1750 t0 = tcg_temp_new();
d03ef511 1751 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1752#if defined(TARGET_PPC64)
a7812ae4
PB		 1753 t1 = tcg_temp_new_i32();
1754 t2 = tcg_temp_new_i32();
54843a58
AJ		 1755 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1756 tcg_gen_trunc_i64_i32(t2, t0);
1757 tcg_gen_rotl_i32(t1, t1, t2);
1758 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1759 tcg_temp_free_i32(t1);
1760 tcg_temp_free_i32(t2);
54843a58
AJ		 1761#else
1762 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1763#endif
76a66253
JM		 1764 if (unlikely(mb != 0 || me != 31)) {
1765#if defined(TARGET_PPC64)
1766 mb += 32;
1767 me += 32;
1768#endif
54843a58 1769 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1770 } else {
54843a58 1771 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1772 }
54843a58 1773 tcg_temp_free(t0);
76a66253 1774 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1775 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1776}
1777
d9bce9d9
JM		 1778#if defined(TARGET_PPC64)
1779#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1780GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1781{ \
1782 gen_##name(ctx, 0); \
1783} \
c7697e1f
JM		 1784GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1785 PPC_64B) \
d9bce9d9
JM		 1786{ \
1787 gen_##name(ctx, 1); \
1788}
1789#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1790GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1791{ \
1792 gen_##name(ctx, 0, 0); \
1793} \
c7697e1f
JM		 1794GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1795 PPC_64B) \
d9bce9d9
JM		 1796{ \
1797 gen_##name(ctx, 0, 1); \
1798} \
c7697e1f
JM		 1799GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1800 PPC_64B) \
d9bce9d9
JM		 1801{ \
1802 gen_##name(ctx, 1, 0); \
1803} \
c7697e1f
JM		 1804GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1805 PPC_64B) \
d9bce9d9
JM		 1806{ \
1807 gen_##name(ctx, 1, 1); \
1808}
51789c41 1809
b068d6a7
JM		 1810static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1811 uint32_t me, uint32_t sh)
51789c41 1812{
d03ef511
AJ		 1813 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1814 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1815 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1816 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1817 } else {
a7812ae4 1818 TCGv t0 = tcg_temp_new();
54843a58 1819 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1820 if (likely(mb == 0 && me == 63)) {
54843a58 1821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1822 } else {
1823 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1824 }
d03ef511 1825 tcg_temp_free(t0);
51789c41 1826 }
51789c41 1827 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1829}
d9bce9d9 1830/* rldicl - rldicl. */
b068d6a7 1831static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1832{
51789c41 1833 uint32_t sh, mb;
d9bce9d9 1834
9d53c753
JM		 1835 sh = SH(ctx->opcode) | (shn << 5);
1836 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1837 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1838}
51789c41 1839GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1840/* rldicr - rldicr. */
b068d6a7 1841static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1842{
51789c41 1843 uint32_t sh, me;
d9bce9d9 1844
9d53c753
JM		 1845 sh = SH(ctx->opcode) | (shn << 5);
1846 me = MB(ctx->opcode) | (men << 5);
51789c41 1847 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1848}
51789c41 1849GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1850/* rldic - rldic. */
b068d6a7 1851static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1852{
51789c41 1853 uint32_t sh, mb;
d9bce9d9 1854
9d53c753
JM		 1855 sh = SH(ctx->opcode) | (shn << 5);
1856 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1857 gen_rldinm(ctx, mb, 63 - sh, sh);
1858}
1859GEN_PPC64_R4(rldic, 0x1E, 0x04);
1860
b068d6a7
JM		 1861static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1862 uint32_t me)
51789c41 1863{
54843a58 1864 TCGv t0;
d03ef511
AJ		 1865
1866 mb = MB(ctx->opcode);
1867 me = ME(ctx->opcode);
a7812ae4 1868 t0 = tcg_temp_new();
d03ef511 1869 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1870 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1871 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1872 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1873 } else {
1874 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1875 }
1876 tcg_temp_free(t0);
51789c41 1877 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1878 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1879}
51789c41 1880
d9bce9d9 1881/* rldcl - rldcl. */
b068d6a7 1882static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1883{
51789c41 1884 uint32_t mb;
d9bce9d9 1885
9d53c753 1886 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1887 gen_rldnm(ctx, mb, 63);
d9bce9d9 1888}
36081602 1889GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1890/* rldcr - rldcr. */
b068d6a7 1891static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1892{
51789c41 1893 uint32_t me;
d9bce9d9 1894
9d53c753 1895 me = MB(ctx->opcode) | (men << 5);
51789c41 1896 gen_rldnm(ctx, 0, me);
d9bce9d9 1897}
36081602 1898GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1899/* rldimi - rldimi. */
b068d6a7 1900static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1901{
271a916e 1902 uint32_t sh, mb, me;
d9bce9d9 1903
9d53c753
JM		 1904 sh = SH(ctx->opcode) | (shn << 5);
1905 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1906 me = 63 - sh;
d03ef511
AJ		 1907 if (unlikely(sh == 0 && mb == 0)) {
1908 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1909 } else {
1910 TCGv t0, t1;
1911 target_ulong mask;
1912
a7812ae4 1913 t0 = tcg_temp_new();
54843a58 1914 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1915 t1 = tcg_temp_new();
d03ef511
AJ		 1916 mask = MASK(mb, me);
1917 tcg_gen_andi_tl(t0, t0, mask);
1918 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1919 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1920 tcg_temp_free(t0);
1921 tcg_temp_free(t1);
51789c41 1922 }
51789c41 1923 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1924 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1925}
36081602 1926GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1927#endif
1928
79aceca5
FB		 1929/*** Integer shift ***/
1930/* slw & slw. */
26d67362
AJ		 1931GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1932{
fea0c503 1933 TCGv t0;
26d67362
AJ		 1934 int l1, l2;
1935 l1 = gen_new_label();
1936 l2 = gen_new_label();
1937
a7812ae4 1938 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1939 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1940 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1941 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1942 tcg_gen_br(l2);
1943 gen_set_label(l1);
fea0c503 1944 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1945 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1946 gen_set_label(l2);
fea0c503 1947 tcg_temp_free(t0);
26d67362
AJ		 1948 if (unlikely(Rc(ctx->opcode) != 0))
1949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1950}
79aceca5 1951/* sraw & sraw. */
26d67362
AJ		 1952GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1953{
a7812ae4
PB		 1954 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1955 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1956 if (unlikely(Rc(ctx->opcode) != 0))
1957 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1958}
79aceca5
FB		 1959/* srawi & srawi. */
1960GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1961{
26d67362
AJ		 1962 int sh = SH(ctx->opcode);
1963 if (sh != 0) {
1964 int l1, l2;
fea0c503 1965 TCGv t0;
26d67362
AJ		 1966 l1 = gen_new_label();
1967 l2 = gen_new_label();
a7812ae4 1968 t0 = tcg_temp_local_new();
fea0c503
AJ		 1969 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1970 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1971 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1972 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1973 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1974 tcg_gen_br(l2);
1975 gen_set_label(l1);
269f3e95 1976 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1977 gen_set_label(l2);
fea0c503
AJ		 1978 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1979 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1980 tcg_temp_free(t0);
26d67362
AJ		 1981 } else {
1982 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1983 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1984 }
76a66253 1985 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1987}
1988/* srw & srw. */
26d67362
AJ		 1989GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1990{
fea0c503 1991 TCGv t0, t1;
26d67362
AJ		 1992 int l1, l2;
1993 l1 = gen_new_label();
1994 l2 = gen_new_label();
d9bce9d9 1995
a7812ae4 1996 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1997 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1998 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1999 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2000 tcg_gen_br(l2);
2001 gen_set_label(l1);
a7812ae4 2002 t1 = tcg_temp_new();
fea0c503
AJ		 2003 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
2004 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
2005 tcg_temp_free(t1);
26d67362 2006 gen_set_label(l2);
fea0c503 2007 tcg_temp_free(t0);
26d67362
AJ		 2008 if (unlikely(Rc(ctx->opcode) != 0))
2009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2010}
d9bce9d9
JM		 2011#if defined(TARGET_PPC64)
2012/* sld & sld. */
26d67362
AJ		 2013GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2014{
fea0c503 2015 TCGv t0;
26d67362
AJ		 2016 int l1, l2;
2017 l1 = gen_new_label();
2018 l2 = gen_new_label();
2019
a7812ae4 2020 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2021 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2022 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2023 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2024 tcg_gen_br(l2);
2025 gen_set_label(l1);
fea0c503 2026 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2027 gen_set_label(l2);
fea0c503 2028 tcg_temp_free(t0);
26d67362
AJ		 2029 if (unlikely(Rc(ctx->opcode) != 0))
2030 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2031}
d9bce9d9 2032/* srad & srad. */
26d67362
AJ		 2033GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2034{
a7812ae4
PB		 2035 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2036 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2037 if (unlikely(Rc(ctx->opcode) != 0))
2038 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2039}
d9bce9d9 2040/* sradi & sradi. */
b068d6a7 2041static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2042{
26d67362 2043 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2044 if (sh != 0) {
26d67362 2045 int l1, l2;
fea0c503 2046 TCGv t0;
26d67362
AJ		 2047 l1 = gen_new_label();
2048 l2 = gen_new_label();
a7812ae4 2049 t0 = tcg_temp_local_new();
26d67362 2050 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2051 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2052 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2053 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2054 tcg_gen_br(l2);
2055 gen_set_label(l1);
269f3e95 2056 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2057 gen_set_label(l2);
a9730017 2058 tcg_temp_free(t0);
26d67362
AJ		 2059 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2060 } else {
2061 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2062 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2063 }
d9bce9d9 2064 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2065 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2066}
c7697e1f 2067GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2068{
2069 gen_sradi(ctx, 0);
2070}
c7697e1f 2071GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2072{
2073 gen_sradi(ctx, 1);
2074}
2075/* srd & srd. */
26d67362
AJ		 2076GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2077{
fea0c503 2078 TCGv t0;
26d67362
AJ		 2079 int l1, l2;
2080 l1 = gen_new_label();
2081 l2 = gen_new_label();
2082
a7812ae4 2083 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2084 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2085 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2086 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2087 tcg_gen_br(l2);
2088 gen_set_label(l1);
fea0c503 2089 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2090 gen_set_label(l2);
fea0c503 2091 tcg_temp_free(t0);
26d67362
AJ		 2092 if (unlikely(Rc(ctx->opcode) != 0))
2093 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2094}
d9bce9d9 2095#endif
79aceca5
FB		 2096
2097/*** Floating-Point arithmetic ***/
7c58044c 2098#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2099GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2100{ \
76a66253 2101 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2102 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2103 return; \
2104 } \
7c58044c 2105 gen_reset_fpstatus(); \
af12906f
AJ		 2106 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2107 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2108 if (isfloat) { \
af12906f 2109 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2110 } \
af12906f
AJ		 2111 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2112 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2113}
2114
7c58044c
JM		 2115#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2116_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2117_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2118
7c58044c
JM		 2119#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2120GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2121{ \
76a66253 2122 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2123 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2124 return; \
2125 } \
7c58044c 2126 gen_reset_fpstatus(); \
af12906f
AJ		 2127 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2128 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2129 if (isfloat) { \
af12906f 2130 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2131 } \
af12906f
AJ		 2132 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2133 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2134}
7c58044c
JM		 2135#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2136_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2137_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2138
7c58044c
JM		 2139#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2140GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2141{ \
76a66253 2142 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2143 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2144 return; \
2145 } \
7c58044c 2146 gen_reset_fpstatus(); \
af12906f
AJ		 2147 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2148 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2149 if (isfloat) { \
af12906f 2150 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2151 } \
af12906f
AJ		 2152 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2153 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2154}
7c58044c
JM		 2155#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2156_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2157_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2158
7c58044c 2159#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2160GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2161{ \
76a66253 2162 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2163 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2164 return; \
2165 } \
7c58044c 2166 gen_reset_fpstatus(); \
af12906f
AJ		 2167 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2168 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2169 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2170}
2171
7c58044c 2172#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2173GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2174{ \
76a66253 2175 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2176 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2177 return; \
2178 } \
7c58044c 2179 gen_reset_fpstatus(); \
af12906f
AJ		 2180 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2181 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2182 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2183}
2184
9a64fbe4 2185/* fadd - fadds */
7c58044c 2186GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2187/* fdiv - fdivs */
7c58044c 2188GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2189/* fmul - fmuls */
7c58044c 2190GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2191
d7e4b87e 2192/* fre */
7c58044c 2193GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2194
a750fc0b 2195/* fres */
7c58044c 2196GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2197
a750fc0b 2198/* frsqrte */
7c58044c
JM		 2199GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2200
2201/* frsqrtes */
af12906f 2202GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2203{
af12906f
AJ		 2204 if (unlikely(!ctx->fpu_enabled)) {
2205 GEN_EXCP_NO_FP(ctx);
2206 return;
2207 }
2208 gen_reset_fpstatus();
2209 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2210 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2211 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2212}
79aceca5 2213
a750fc0b 2214/* fsel */
7c58044c 2215_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2216/* fsub - fsubs */
7c58044c 2217GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2218/* Optional: */
2219/* fsqrt */
a750fc0b 2220GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2221{
76a66253 2222 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2223 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2224 return;
2225 }
7c58044c 2226 gen_reset_fpstatus();
af12906f
AJ		 2227 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2228 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2229}
79aceca5 2230
a750fc0b 2231GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2232{
76a66253 2233 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2234 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2235 return;
2236 }
7c58044c 2237 gen_reset_fpstatus();
af12906f
AJ		 2238 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2239 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2240 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2241}
2242
2243/*** Floating-Point multiply-and-add ***/
4ecc3190 2244/* fmadd - fmadds */
7c58044c 2245GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2246/* fmsub - fmsubs */
7c58044c 2247GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2248/* fnmadd - fnmadds */
7c58044c 2249GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2250/* fnmsub - fnmsubs */
7c58044c 2251GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2252
2253/*** Floating-Point round & convert ***/
2254/* fctiw */
7c58044c 2255GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2256/* fctiwz */
7c58044c 2257GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2258/* frsp */
7c58044c 2259GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2260#if defined(TARGET_PPC64)
2261/* fcfid */
7c58044c 2262GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2263/* fctid */
7c58044c 2264GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2265/* fctidz */
7c58044c 2266GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2267#endif
79aceca5 2268
d7e4b87e 2269/* frin */
7c58044c 2270GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2271/* friz */
7c58044c 2272GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2273/* frip */
7c58044c 2274GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2275/* frim */
7c58044c 2276GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2277
79aceca5
FB		 2278/*** Floating-Point compare ***/
2279/* fcmpo */
76a66253 2280GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2281{
76a66253 2282 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2283 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2284 return;
2285 }
7c58044c 2286 gen_reset_fpstatus();
af12906f
AJ		 2287 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2288 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2289 gen_helper_float_check_status();
79aceca5
FB		 2290}
2291
2292/* fcmpu */
76a66253 2293GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2294{
76a66253 2295 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2296 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2297 return;
2298 }
7c58044c 2299 gen_reset_fpstatus();
af12906f
AJ		 2300 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2301 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2302 gen_helper_float_check_status();
79aceca5
FB		 2303}
2304
9a64fbe4
FB		 2305/*** Floating-point move ***/
2306/* fabs */
7c58044c
JM		 2307/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2308GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2309
2310/* fmr - fmr. */
7c58044c 2311/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2312GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2313{
76a66253 2314 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2315 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2316 return;
2317 }
af12906f
AJ		 2318 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2319 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2320}
2321
2322/* fnabs */
7c58044c
JM		 2323/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2324GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2325/* fneg */
7c58044c
JM		 2326/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2327GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2328
79aceca5
FB		 2329/*** Floating-Point status & ctrl register ***/
2330/* mcrfs */
2331GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2332{
7c58044c
JM		 2333 int bfa;
2334
76a66253 2335 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2336 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2337 return;
2338 }
7c58044c
JM		 2339 gen_optimize_fprf();
2340 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2341 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2342 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2343 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2344}
2345
2346/* mffs */
2347GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2348{
76a66253 2349 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2350 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2351 return;
2352 }
7c58044c
JM		 2353 gen_optimize_fprf();
2354 gen_reset_fpstatus();
af12906f
AJ		 2355 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2356 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2357}
2358
2359/* mtfsb0 */
2360GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2361{
fb0eaffc 2362 uint8_t crb;
3b46e624 2363
76a66253 2364 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2365 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2366 return;
2367 }
7c58044c
JM		 2368 crb = 32 - (crbD(ctx->opcode) >> 2);
2369 gen_optimize_fprf();
2370 gen_reset_fpstatus();
2371 if (likely(crb != 30 && crb != 29))
af12906f 2372 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
7c58044c 2373 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2374 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2375 }
79aceca5
FB		 2376}
2377
2378/* mtfsb1 */
2379GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2380{
fb0eaffc 2381 uint8_t crb;
3b46e624 2382
76a66253 2383 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2384 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2385 return;
2386 }
7c58044c
JM		 2387 crb = 32 - (crbD(ctx->opcode) >> 2);
2388 gen_optimize_fprf();
2389 gen_reset_fpstatus();
2390 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2391 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
0f2f39c2 2392 TCGv_i32 t0 = tcg_const_i32(crb);
af12906f 2393 gen_helper_fpscr_setbit(t0);
0f2f39c2 2394 tcg_temp_free_i32(t0);
af12906f 2395 }
7c58044c 2396 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2397 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2398 }
2399 /* We can raise a differed exception */
af12906f 2400 gen_helper_float_check_status();
79aceca5
FB		 2401}
2402
2403/* mtfsf */
2404GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2405{
0f2f39c2 2406 TCGv_i32 t0;
af12906f 2407
76a66253 2408 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2409 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2410 return;
2411 }
7c58044c 2412 gen_optimize_fprf();
7c58044c 2413 gen_reset_fpstatus();
af12906f
AJ		 2414 t0 = tcg_const_i32(FM(ctx->opcode));
2415 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2416 tcg_temp_free_i32(t0);
7c58044c 2417 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2418 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2419 }
2420 /* We can raise a differed exception */
af12906f 2421 gen_helper_float_check_status();
79aceca5
FB		 2422}
2423
2424/* mtfsfi */
2425GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2426{
7c58044c 2427 int bf, sh;
0f2f39c2
AJ		 2428 TCGv_i64 t0;
2429 TCGv_i32 t1;
7c58044c 2430
76a66253 2431 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2432 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2433 return;
2434 }
7c58044c
JM		 2435 bf = crbD(ctx->opcode) >> 2;
2436 sh = 7 - bf;
2437 gen_optimize_fprf();
7c58044c 2438 gen_reset_fpstatus();
0f2f39c2 2439 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2440 t1 = tcg_const_i32(1 << sh);
2441 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2442 tcg_temp_free_i64(t0);
2443 tcg_temp_free_i32(t1);
7c58044c 2444 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2445 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2446 }
2447 /* We can raise a differed exception */
af12906f 2448 gen_helper_float_check_status();
79aceca5
FB		 2449}
2450
76a66253
JM		 2451/*** Addressing modes ***/
2452/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2453static always_inline void gen_addr_imm_index (TCGv EA,
2454 DisasContext *ctx,
b068d6a7 2455 target_long maskl)
76a66253
JM		 2456{
2457 target_long simm = SIMM(ctx->opcode);
2458
be147d08 2459 simm &= ~maskl;
e2be8d8d
AJ		 2460 if (rA(ctx->opcode) == 0)
2461 tcg_gen_movi_tl(EA, simm);
2462 else if (likely(simm != 0))
2463 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2464 else
2465 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2466}
2467
e2be8d8d
AJ		 2468static always_inline void gen_addr_reg_index (TCGv EA,
2469 DisasContext *ctx)
76a66253 2470{
e2be8d8d
AJ		 2471 if (rA(ctx->opcode) == 0)
2472 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2473 else
2474 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2475}
2476
e2be8d8d
AJ		 2477static always_inline void gen_addr_register (TCGv EA,
2478 DisasContext *ctx)
76a66253 2479{
e2be8d8d
AJ		 2480 if (rA(ctx->opcode) == 0)
2481 tcg_gen_movi_tl(EA, 0);
2482 else
2483 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2484}
2485
7863667f
JM		 2486#if defined(TARGET_PPC64)
2487#define _GEN_MEM_FUNCS(name, mode) \
2488 &gen_op_##name##_##mode, \
2489 &gen_op_##name##_le_##mode, \
2490 &gen_op_##name##_64_##mode, \
2491 &gen_op_##name##_le_64_##mode
2492#else
2493#define _GEN_MEM_FUNCS(name, mode) \
2494 &gen_op_##name##_##mode, \
2495 &gen_op_##name##_le_##mode
2496#endif
9a64fbe4 2497#if defined(CONFIG_USER_ONLY)
d9bce9d9 2498#if defined(TARGET_PPC64)
7863667f 2499#define NB_MEM_FUNCS 4
d9bce9d9 2500#else
7863667f 2501#define NB_MEM_FUNCS 2
d9bce9d9 2502#endif
7863667f
JM		 2503#define GEN_MEM_FUNCS(name) \
2504 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2505#else
d9bce9d9 2506#if defined(TARGET_PPC64)
7863667f 2507#define NB_MEM_FUNCS 12
2857068e 2508#else
7863667f 2509#define NB_MEM_FUNCS 6
2857068e 2510#endif
7863667f
JM		 2511#define GEN_MEM_FUNCS(name) \
2512 _GEN_MEM_FUNCS(name, user), \
2513 _GEN_MEM_FUNCS(name, kernel), \
2514 _GEN_MEM_FUNCS(name, hypv)
2515#endif
2516
2517/*** Integer load ***/
2518#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
d9bce9d9 2519#define OP_LD_TABLE(width) \
7863667f
JM		 2520static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2521 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2522};
2523#define OP_ST_TABLE(width) \
7863667f
JM		 2524static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2525 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2526};
9a64fbe4 2527
b61f2753
AJ		 2528
2529#if defined(TARGET_PPC64)
2530#define GEN_QEMU_LD_PPC64(width) \
2531static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2532{ \
2533 if (likely(flags & 2)) \
2534 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2535 else { \
a7812ae4 2536 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2537 tcg_gen_ext32u_tl(addr, t1); \
2538 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2539 tcg_temp_free(addr); \
2540 } \
2541}
2542GEN_QEMU_LD_PPC64(8u)
2543GEN_QEMU_LD_PPC64(8s)
2544GEN_QEMU_LD_PPC64(16u)
2545GEN_QEMU_LD_PPC64(16s)
2546GEN_QEMU_LD_PPC64(32u)
2547GEN_QEMU_LD_PPC64(32s)
2548GEN_QEMU_LD_PPC64(64)
2549
2550#define GEN_QEMU_ST_PPC64(width) \
2551static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2552{ \
2553 if (likely(flags & 2)) \
2554 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2555 else { \
a7812ae4 2556 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2557 tcg_gen_ext32u_tl(addr, t1); \
2558 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2559 tcg_temp_free(addr); \
2560 } \
2561}
2562GEN_QEMU_ST_PPC64(8)
2563GEN_QEMU_ST_PPC64(16)
2564GEN_QEMU_ST_PPC64(32)
2565GEN_QEMU_ST_PPC64(64)
2566
ea363694 2567static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2568{
ea363694 2569 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2570}
2571
ea363694 2572static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2573{
ea363694 2574 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2575}
2576
ea363694 2577static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2578{
2579 if (unlikely(flags & 1)) {
a7812ae4 2580 TCGv_i32 t0;
ea363694 2581 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2582 t0 = tcg_temp_new_i32();
ea363694
AJ		 2583 tcg_gen_trunc_tl_i32(t0, arg0);
2584 tcg_gen_bswap16_i32(t0, t0);
2585 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2586 tcg_temp_free_i32(t0);
b61f2753 2587 } else
ea363694 2588 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2589}
2590
ea363694 2591static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2592{
2593 if (unlikely(flags & 1)) {
a7812ae4 2594 TCGv_i32 t0;
ea363694 2595 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2596 t0 = tcg_temp_new_i32();
ea363694
AJ		 2597 tcg_gen_trunc_tl_i32(t0, arg0);
2598 tcg_gen_bswap16_i32(t0, t0);
2599 tcg_gen_extu_i32_tl(arg0, t0);
2600 tcg_gen_ext16s_tl(arg0, arg0);
a7812ae4 2601 tcg_temp_free_i32(t0);
b61f2753 2602 } else
ea363694 2603 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2604}
2605
ea363694 2606static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2607{
2608 if (unlikely(flags & 1)) {
a7812ae4 2609 TCGv_i32 t0;
ea363694 2610 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2611 t0 = tcg_temp_new_i32();
ea363694
AJ		 2612 tcg_gen_trunc_tl_i32(t0, arg0);
2613 tcg_gen_bswap_i32(t0, t0);
2614 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2615 tcg_temp_free_i32(t0);
b61f2753 2616 } else
ea363694 2617 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2618}
2619
ea363694 2620static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2621{
2622 if (unlikely(flags & 1)) {
a7812ae4 2623 TCGv_i32 t0;
ea363694 2624 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2625 t0 = tcg_temp_new_i32();
ea363694
AJ		 2626 tcg_gen_trunc_tl_i32(t0, arg0);
2627 tcg_gen_bswap_i32(t0, t0);
2628 tcg_gen_ext_i32_tl(arg0, t0);
a7812ae4 2629 tcg_temp_free_i32(t0);
b61f2753 2630 } else
ea363694 2631 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2632}
2633
ea363694 2634static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2635{
ea363694 2636 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2637 if (unlikely(flags & 1))
ea363694 2638 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2639}
2640
ea363694 2641static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2642{
ea363694 2643 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2644}
2645
ea363694 2646static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2647{
2648 if (unlikely(flags & 1)) {
a7812ae4
PB		 2649 TCGv_i32 t0;
2650 TCGv_i64 t1;
2651 t0 = tcg_temp_new_i32();
ea363694
AJ		 2652 tcg_gen_trunc_tl_i32(t0, arg0);
2653 tcg_gen_ext16u_i32(t0, t0);
2654 tcg_gen_bswap16_i32(t0, t0);
a7812ae4 2655 t1 = tcg_temp_new_i64();
ea363694 2656 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2657 tcg_temp_free_i32(t0);
ea363694 2658 gen_qemu_st16_ppc64(t1, arg1, flags);
a7812ae4 2659 tcg_temp_free_i64(t1);
b61f2753 2660 } else
ea363694 2661 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2662}
2663
ea363694 2664static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2665{
2666 if (unlikely(flags & 1)) {
a7812ae4
PB		 2667 TCGv_i32 t0;
2668 TCGv_i64 t1;
2669 t0 = tcg_temp_new_i32();
ea363694
AJ		 2670 tcg_gen_trunc_tl_i32(t0, arg0);
2671 tcg_gen_bswap_i32(t0, t0);
a7812ae4 2672 t1 = tcg_temp_new_i64();
ea363694 2673 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2674 tcg_temp_free_i32(t0);
ea363694 2675 gen_qemu_st32_ppc64(t1, arg1, flags);
a7812ae4 2676 tcg_temp_free_i64(t1);
b61f2753 2677 } else
ea363694 2678 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2679}
2680
ea363694 2681static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2682{
2683 if (unlikely(flags & 1)) {
a7812ae4 2684 TCGv_i64 t0 = tcg_temp_new_i64();
ea363694
AJ		 2685 tcg_gen_bswap_i64(t0, arg0);
2686 gen_qemu_st64_ppc64(t0, arg1, flags);
a7812ae4 2687 tcg_temp_free_i64(t0);
b61f2753 2688 } else
ea363694 2689 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2690}
2691
2692
2693#else /* defined(TARGET_PPC64) */
2694#define GEN_QEMU_LD_PPC32(width) \
ea363694 2695static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
b61f2753 2696{ \
ea363694 2697 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2698}
2699GEN_QEMU_LD_PPC32(8u)
2700GEN_QEMU_LD_PPC32(8s)
2701GEN_QEMU_LD_PPC32(16u)
2702GEN_QEMU_LD_PPC32(16s)
2703GEN_QEMU_LD_PPC32(32u)
2704GEN_QEMU_LD_PPC32(32s)
b61f2753
AJ		 2705
2706#define GEN_QEMU_ST_PPC32(width) \
ea363694 2707static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
b61f2753 2708{ \
ea363694 2709 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2710}
2711GEN_QEMU_ST_PPC32(8)
2712GEN_QEMU_ST_PPC32(16)
2713GEN_QEMU_ST_PPC32(32)
b61f2753 2714
ea363694 2715static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2716{
ea363694 2717 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2718}
2719
ea363694 2720static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2721{
ea363694 2722 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2723}
2724
ea363694 2725static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2726{
ea363694 2727 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2728 if (unlikely(flags & 1))
ea363694 2729 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2730}
2731
ea363694 2732static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2733{
2734 if (unlikely(flags & 1)) {
ea363694
AJ		 2735 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2736 tcg_gen_bswap16_i32(arg0, arg0);
2737 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2738 } else
ea363694 2739 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2740}
2741
ea363694 2742static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2743{
ea363694 2744 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2745 if (unlikely(flags & 1))
ea363694 2746 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2747}
2748
ea363694 2749static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2750{
e32ad5c2 2751 gen_qemu_st8_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2752}
2753
ea363694 2754static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2755{
2756 if (unlikely(flags & 1)) {
a7812ae4 2757 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2758 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2759 tcg_gen_bswap16_i32(temp, temp);
e32ad5c2 2760 gen_qemu_st16_ppc32(temp, arg1, flags);
a7812ae4 2761 tcg_temp_free_i32(temp);
b61f2753 2762 } else
e32ad5c2 2763 gen_qemu_st16_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2764}
2765
ea363694 2766static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2767{
2768 if (unlikely(flags & 1)) {
a7812ae4 2769 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2770 tcg_gen_bswap_i32(temp, arg0);
e32ad5c2 2771 gen_qemu_st32_ppc32(temp, arg1, flags);
a7812ae4 2772 tcg_temp_free_i32(temp);
b61f2753 2773 } else
e32ad5c2 2774 gen_qemu_st32_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2775}
2776
b61f2753
AJ		 2777#endif
2778
d9bce9d9
JM		 2779#define GEN_LD(width, opc, type) \
2780GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2781{ \
a7812ae4 2782 TCGv EA = tcg_temp_new(); \
b61f2753
AJ		 2783 gen_addr_imm_index(EA, ctx, 0); \
2784 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2785 tcg_temp_free(EA); \
79aceca5
FB		 2786}
2787
d9bce9d9
JM		 2788#define GEN_LDU(width, opc, type) \
2789GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2790{ \
b61f2753 2791 TCGv EA; \
76a66253
JM		 2792 if (unlikely(rA(ctx->opcode) == 0 || \
2793 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2794 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2795 return; \
9a64fbe4 2796 } \
a7812ae4 2797 EA = tcg_temp_new(); \
9d53c753 2798 if (type == PPC_64B) \
b61f2753 2799 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2800 else \
b61f2753
AJ		 2801 gen_addr_imm_index(EA, ctx, 0); \
2802 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2803 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2804 tcg_temp_free(EA); \
79aceca5
FB		 2805}
2806
d9bce9d9
JM		 2807#define GEN_LDUX(width, opc2, opc3, type) \
2808GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2809{ \
b61f2753 2810 TCGv EA; \
76a66253
JM		 2811 if (unlikely(rA(ctx->opcode) == 0 || \
2812 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2813 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2814 return; \
9a64fbe4 2815 } \
a7812ae4 2816 EA = tcg_temp_new(); \
b61f2753
AJ		 2817 gen_addr_reg_index(EA, ctx); \
2818 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2819 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2820 tcg_temp_free(EA); \
79aceca5
FB		 2821}
2822
d9bce9d9
JM		 2823#define GEN_LDX(width, opc2, opc3, type) \
2824GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2825{ \
a7812ae4 2826 TCGv EA = tcg_temp_new(); \
b61f2753
AJ		 2827 gen_addr_reg_index(EA, ctx); \
2828 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2829 tcg_temp_free(EA); \
79aceca5
FB		 2830}
2831
d9bce9d9 2832#define GEN_LDS(width, op, type) \
d9bce9d9
JM		 2833GEN_LD(width, op | 0x20, type); \
2834GEN_LDU(width, op | 0x21, type); \
2835GEN_LDUX(width, 0x17, op | 0x01, type); \
2836GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2837
2838/* lbz lbzu lbzux lbzx */
b61f2753 2839GEN_LDS(8u, 0x02, PPC_INTEGER);
79aceca5 2840/* lha lhau lhaux lhax */
b61f2753 2841GEN_LDS(16s, 0x0A, PPC_INTEGER);
79aceca5 2842/* lhz lhzu lhzux lhzx */
b61f2753 2843GEN_LDS(16u, 0x08, PPC_INTEGER);
79aceca5 2844/* lwz lwzu lwzux lwzx */
b61f2753 2845GEN_LDS(32u, 0x00, PPC_INTEGER);
d9bce9d9 2846#if defined(TARGET_PPC64)
d9bce9d9 2847/* lwaux */
b61f2753 2848GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2849/* lwax */
b61f2753 2850GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2851/* ldux */
b61f2753 2852GEN_LDUX(64, 0x15, 0x01, PPC_64B);
d9bce9d9 2853/* ldx */
b61f2753 2854GEN_LDX(64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2855GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2856{
b61f2753 2857 TCGv EA;
d9bce9d9
JM		 2858 if (Rc(ctx->opcode)) {
2859 if (unlikely(rA(ctx->opcode) == 0 ||
2860 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2861 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2862 return;
2863 }
2864 }
a7812ae4 2865 EA = tcg_temp_new();
b61f2753 2866 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2867 if (ctx->opcode & 0x02) {
2868 /* lwa (lwau is undefined) */
b61f2753 2869 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2870 } else {
2871 /* ld - ldu */
b61f2753 2872 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2873 }
d9bce9d9 2874 if (Rc(ctx->opcode))
b61f2753
AJ		 2875 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2876 tcg_temp_free(EA);
d9bce9d9 2877}
be147d08
JM		 2878/* lq */
2879GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2880{
2881#if defined(CONFIG_USER_ONLY)
2882 GEN_EXCP_PRIVOPC(ctx);
2883#else
2884 int ra, rd;
b61f2753 2885 TCGv EA;
be147d08
JM		 2886
2887 /* Restore CPU state */
2888 if (unlikely(ctx->supervisor == 0)) {
2889 GEN_EXCP_PRIVOPC(ctx);
2890 return;
2891 }
2892 ra = rA(ctx->opcode);
2893 rd = rD(ctx->opcode);
2894 if (unlikely((rd & 1) || rd == ra)) {
2895 GEN_EXCP_INVAL(ctx);
2896 return;
2897 }
2898 if (unlikely(ctx->mem_idx & 1)) {
2899 /* Little-endian mode is not handled */
2900 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2901 return;
2902 }
a7812ae4 2903 EA = tcg_temp_new();
b61f2753
AJ		 2904 gen_addr_imm_index(EA, ctx, 0x0F);
2905 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2906 tcg_gen_addi_tl(EA, EA, 8);
2907 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2908 tcg_temp_free(EA);
be147d08
JM		 2909#endif
2910}
d9bce9d9 2911#endif
79aceca5
FB		 2912
2913/*** Integer store ***/
d9bce9d9
JM		 2914#define GEN_ST(width, opc, type) \
2915GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2916{ \
a7812ae4 2917 TCGv EA = tcg_temp_new(); \
b61f2753
AJ		 2918 gen_addr_imm_index(EA, ctx, 0); \
2919 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2920 tcg_temp_free(EA); \
79aceca5
FB		 2921}
2922
d9bce9d9
JM		 2923#define GEN_STU(width, opc, type) \
2924GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2925{ \
b61f2753 2926 TCGv EA; \
76a66253 2927 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2928 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2929 return; \
9a64fbe4 2930 } \
a7812ae4 2931 EA = tcg_temp_new(); \
9d53c753 2932 if (type == PPC_64B) \
b61f2753 2933 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2934 else \
b61f2753
AJ		 2935 gen_addr_imm_index(EA, ctx, 0); \
2936 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2937 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2938 tcg_temp_free(EA); \
79aceca5
FB		 2939}
2940
d9bce9d9
JM		 2941#define GEN_STUX(width, opc2, opc3, type) \
2942GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2943{ \
b61f2753 2944 TCGv EA; \
76a66253 2945 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2946 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2947 return; \
9a64fbe4 2948 } \
a7812ae4 2949 EA = tcg_temp_new(); \
b61f2753
AJ		 2950 gen_addr_reg_index(EA, ctx); \
2951 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2952 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2953 tcg_temp_free(EA); \
79aceca5
FB		 2954}
2955
d9bce9d9
JM		 2956#define GEN_STX(width, opc2, opc3, type) \
2957GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2958{ \
a7812ae4 2959 TCGv EA = tcg_temp_new(); \
b61f2753
AJ		 2960 gen_addr_reg_index(EA, ctx); \
2961 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2962 tcg_temp_free(EA); \
79aceca5
FB		 2963}
2964
d9bce9d9 2965#define GEN_STS(width, op, type) \
d9bce9d9
JM		 2966GEN_ST(width, op | 0x20, type); \
2967GEN_STU(width, op | 0x21, type); \
2968GEN_STUX(width, 0x17, op | 0x01, type); \
2969GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2970
2971/* stb stbu stbux stbx */
b61f2753 2972GEN_STS(8, 0x06, PPC_INTEGER);
79aceca5 2973/* sth sthu sthux sthx */
b61f2753 2974GEN_STS(16, 0x0C, PPC_INTEGER);
79aceca5 2975/* stw stwu stwux stwx */
b61f2753 2976GEN_STS(32, 0x04, PPC_INTEGER);
d9bce9d9 2977#if defined(TARGET_PPC64)
b61f2753
AJ		 2978GEN_STUX(64, 0x15, 0x05, PPC_64B);
2979GEN_STX(64, 0x15, 0x04, PPC_64B);
be147d08 2980GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2981{
be147d08 2982 int rs;
b61f2753 2983 TCGv EA;
be147d08
JM		 2984
2985 rs = rS(ctx->opcode);
2986 if ((ctx->opcode & 0x3) == 0x2) {
2987#if defined(CONFIG_USER_ONLY)
2988 GEN_EXCP_PRIVOPC(ctx);
2989#else
2990 /* stq */
2991 if (unlikely(ctx->supervisor == 0)) {
2992 GEN_EXCP_PRIVOPC(ctx);
2993 return;
2994 }
2995 if (unlikely(rs & 1)) {
e1833e1f 2996 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2997 return;
2998 }
be147d08
JM		 2999 if (unlikely(ctx->mem_idx & 1)) {
3000 /* Little-endian mode is not handled */
3001 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3002 return;
3003 }
a7812ae4 3004 EA = tcg_temp_new();
b61f2753
AJ		 3005 gen_addr_imm_index(EA, ctx, 0x03);
3006 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3007 tcg_gen_addi_tl(EA, EA, 8);
3008 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3009 tcg_temp_free(EA);
be147d08
JM		 3010#endif
3011 } else {
3012 /* std / stdu */
3013 if (Rc(ctx->opcode)) {
3014 if (unlikely(rA(ctx->opcode) == 0)) {
3015 GEN_EXCP_INVAL(ctx);
3016 return;
3017 }
3018 }
a7812ae4 3019 EA = tcg_temp_new();
b61f2753
AJ		 3020 gen_addr_imm_index(EA, ctx, 0x03);
3021 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 3022 if (Rc(ctx->opcode))
b61f2753
AJ		 3023 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3024 tcg_temp_free(EA);
d9bce9d9 3025 }
d9bce9d9
JM		 3026}
3027#endif
79aceca5
FB		 3028/*** Integer load and store with byte reverse ***/
3029/* lhbrx */
b61f2753
AJ		 3030void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3031{
a7812ae4
PB		 3032 TCGv_i32 temp = tcg_temp_new_i32();
3033 gen_qemu_ld16u(t0, t1, flags);
3034 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3035 tcg_gen_bswap16_i32(temp, temp);
3036 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3037 tcg_temp_free_i32(temp);
b61f2753
AJ		 3038}
3039GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
3040
79aceca5 3041/* lwbrx */
b61f2753
AJ		 3042void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3043{
a7812ae4
PB		 3044 TCGv_i32 temp = tcg_temp_new_i32();
3045 gen_qemu_ld32u(t0, t1, flags);
3046 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3047 tcg_gen_bswap_i32(temp, temp);
3048 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3049 tcg_temp_free_i32(temp);
b61f2753
AJ		 3050}
3051GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
3052
79aceca5 3053/* sthbrx */
b61f2753
AJ		 3054void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3055{
a7812ae4
PB		 3056 TCGv_i32 temp = tcg_temp_new_i32();
3057 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3058 tcg_gen_trunc_tl_i32(temp, t0);
3059 tcg_gen_ext16u_i32(temp, temp);
3060 tcg_gen_bswap16_i32(temp, temp);
a7812ae4
PB		 3061 tcg_gen_extu_i32_tl(t2, temp);
3062 tcg_temp_free_i32(temp);
3063 gen_qemu_st16(t2, t1, flags);
3064 tcg_temp_free(t2);
b61f2753
AJ		 3065}
3066GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
3067
79aceca5 3068/* stwbrx */
b61f2753
AJ		 3069void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3070{
a7812ae4
PB		 3071 TCGv_i32 temp = tcg_temp_new_i32();
3072 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3073 tcg_gen_trunc_tl_i32(temp, t0);
3074 tcg_gen_bswap_i32(temp, temp);
a7812ae4
PB		 3075 tcg_gen_extu_i32_tl(t2, temp);
3076 tcg_temp_free_i32(temp);
87006d13 3077 gen_qemu_st32(t2, t1, flags);
a7812ae4 3078 tcg_temp_free(t2);
b61f2753
AJ		 3079}
3080GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3081
3082/*** Integer load and store multiple ***/
111bfab3 3083#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 3084static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
3085 GEN_MEM_FUNCS(lmw),
d9bce9d9 3086};
7863667f
JM		 3087static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
3088 GEN_MEM_FUNCS(stmw),
d9bce9d9 3089};
9a64fbe4 3090
79aceca5
FB		 3091/* lmw */
3092GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3093{
76a66253 3094 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3095 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3096 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 3097 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 3098}
3099
3100/* stmw */
3101GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3102{
76a66253 3103 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3104 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3105 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 3106 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 3107}
3108
3109/*** Integer load and store strings ***/
9a64fbe4
FB		 3110#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
3111#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 3112/* string load & stores are by definition endian-safe */
3113#define gen_op_lswi_le_raw gen_op_lswi_raw
3114#define gen_op_lswi_le_user gen_op_lswi_user
3115#define gen_op_lswi_le_kernel gen_op_lswi_kernel
3116#define gen_op_lswi_le_hypv gen_op_lswi_hypv
3117#define gen_op_lswi_le_64_raw gen_op_lswi_raw
3118#define gen_op_lswi_le_64_user gen_op_lswi_user
3119#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
3120#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 3121static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
3122 GEN_MEM_FUNCS(lswi),
d9bce9d9 3123};
e7c24003
JM		 3124#define gen_op_lswx_le_raw gen_op_lswx_raw
3125#define gen_op_lswx_le_user gen_op_lswx_user
3126#define gen_op_lswx_le_kernel gen_op_lswx_kernel
3127#define gen_op_lswx_le_hypv gen_op_lswx_hypv
3128#define gen_op_lswx_le_64_raw gen_op_lswx_raw
3129#define gen_op_lswx_le_64_user gen_op_lswx_user
3130#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
3131#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 3132static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
3133 GEN_MEM_FUNCS(lswx),
d9bce9d9 3134};
e7c24003
JM		 3135#define gen_op_stsw_le_raw gen_op_stsw_raw
3136#define gen_op_stsw_le_user gen_op_stsw_user
3137#define gen_op_stsw_le_kernel gen_op_stsw_kernel
3138#define gen_op_stsw_le_hypv gen_op_stsw_hypv
3139#define gen_op_stsw_le_64_raw gen_op_stsw_raw
3140#define gen_op_stsw_le_64_user gen_op_stsw_user
3141#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3142#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 3143static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3144 GEN_MEM_FUNCS(stsw),
9a64fbe4 3145};
9a64fbe4 3146
79aceca5 3147/* lswi */
3fc6c082 3148/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3149 * rA is in the range of registers to be loaded.
3150 * In an other hand, IBM says this is valid, but rA won't be loaded.
3151 * For now, I'll follow the spec...
3152 */
05332d70 3153GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 3154{
3155 int nb = NB(ctx->opcode);
3156 int start = rD(ctx->opcode);
9a64fbe4 3157 int ra = rA(ctx->opcode);
79aceca5
FB		 3158 int nr;
3159
3160 if (nb == 0)
3161 nb = 32;
3162 nr = nb / 4;
76a66253
JM		 3163 if (unlikely(((start + nr) > 32 &&
3164 start <= ra && (start + nr - 32) > ra) ||
3165 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3166 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3167 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3168 return;
297d8e62 3169 }
8dd4983c 3170 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3171 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3172 gen_addr_register(cpu_T[0], ctx);
86c581dc 3173 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3174 op_ldsts(lswi, start);
79aceca5
FB		 3175}
3176
3177/* lswx */
05332d70 3178GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3179{
9a64fbe4
FB		 3180 int ra = rA(ctx->opcode);
3181 int rb = rB(ctx->opcode);
3182
76a66253 3183 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3184 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3185 gen_addr_reg_index(cpu_T[0], ctx);
9a64fbe4 3186 if (ra == 0) {
9a64fbe4 3187 ra = rb;
79aceca5 3188 }
3d7b417e 3189 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3190 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 3191}
3192
3193/* stswi */
05332d70 3194GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3195{
4b3686fa
FB		 3196 int nb = NB(ctx->opcode);
3197
76a66253 3198 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3199 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3200 gen_addr_register(cpu_T[0], ctx);
4b3686fa
FB		 3201 if (nb == 0)
3202 nb = 32;
86c581dc 3203 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3204 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3205}
3206
3207/* stswx */
05332d70 3208GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3209{
8dd4983c 3210 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3211 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3212 gen_addr_reg_index(cpu_T[0], ctx);
3d7b417e 3213 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3214 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3215}
3216
3217/*** Memory synchronisation ***/
3218/* eieio */
0db1b20e 3219GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3220{
79aceca5
FB		 3221}
3222
3223/* isync */
0db1b20e 3224GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3225{
e1833e1f 3226 GEN_STOP(ctx);
79aceca5
FB		 3227}
3228
111bfab3
FB		 3229#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3230#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 3231static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3232 GEN_MEM_FUNCS(lwarx),
111bfab3 3233};
7863667f
JM		 3234static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3235 GEN_MEM_FUNCS(stwcx),
985a19d6 3236};
9a64fbe4 3237
111bfab3 3238/* lwarx */
76a66253 3239GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3240{
30032c94
JM		 3241 /* NIP cannot be restored if the memory exception comes from an helper */
3242 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3243 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 3244 op_lwarx();
f78fb44e 3245 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 3246}
3247
3248/* stwcx. */
c7697e1f 3249GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3250{
30032c94
JM		 3251 /* NIP cannot be restored if the memory exception comes from an helper */
3252 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3253 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3254 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 3255 op_stwcx();
79aceca5
FB		 3256}
3257
426613db
JM		 3258#if defined(TARGET_PPC64)
3259#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3260#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 3261static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3262 GEN_MEM_FUNCS(ldarx),
426613db 3263};
7863667f
JM		 3264static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3265 GEN_MEM_FUNCS(stdcx),
426613db 3266};
426613db
JM		 3267
3268/* ldarx */
a750fc0b 3269GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3270{
30032c94
JM		 3271 /* NIP cannot be restored if the memory exception comes from an helper */
3272 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3273 gen_addr_reg_index(cpu_T[0], ctx);
426613db 3274 op_ldarx();
f78fb44e 3275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 3276}
3277
3278/* stdcx. */
c7697e1f 3279GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3280{
30032c94
JM		 3281 /* NIP cannot be restored if the memory exception comes from an helper */
3282 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3283 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3284 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 3285 op_stdcx();
3286}
3287#endif /* defined(TARGET_PPC64) */
3288
79aceca5 3289/* sync */
a902d886 3290GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3291{
79aceca5
FB		 3292}
3293
0db1b20e
JM		 3294/* wait */
3295GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3296{
3297 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 3298 gen_op_wait();
3299 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3300}
3301
79aceca5 3302/*** Floating-point load ***/
477023a6
JM		 3303#define GEN_LDF(width, opc, type) \
3304GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3305{ \
76a66253 3306 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3307 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3308 return; \
3309 } \
e2be8d8d 3310 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3311 op_ldst(l##width); \
a5e26afa 3312 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3313}
3314
477023a6
JM		 3315#define GEN_LDUF(width, opc, type) \
3316GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3317{ \
76a66253 3318 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3319 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3320 return; \
3321 } \
76a66253 3322 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3323 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3324 return; \
9a64fbe4 3325 } \
e2be8d8d 3326 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3327 op_ldst(l##width); \
a5e26afa 3328 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3329 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3330}
3331
477023a6
JM		 3332#define GEN_LDUXF(width, opc, type) \
3333GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3334{ \
76a66253 3335 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3336 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3337 return; \
3338 } \
76a66253 3339 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3340 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3341 return; \
9a64fbe4 3342 } \
e2be8d8d 3343 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3344 op_ldst(l##width); \
a5e26afa 3345 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3346 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3347}
3348
477023a6
JM		 3349#define GEN_LDXF(width, opc2, opc3, type) \
3350GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3351{ \
76a66253 3352 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3353 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3354 return; \
3355 } \
e2be8d8d 3356 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3357 op_ldst(l##width); \
a5e26afa 3358 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3359}
3360
477023a6 3361#define GEN_LDFS(width, op, type) \
9a64fbe4 3362OP_LD_TABLE(width); \
477023a6
JM		 3363GEN_LDF(width, op | 0x20, type); \
3364GEN_LDUF(width, op | 0x21, type); \
3365GEN_LDUXF(width, op | 0x01, type); \
3366GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3367
3368/* lfd lfdu lfdux lfdx */
477023a6 3369GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 3370/* lfs lfsu lfsux lfsx */
477023a6 3371GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3372
3373/*** Floating-point store ***/
477023a6
JM		 3374#define GEN_STF(width, opc, type) \
3375GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3376{ \
76a66253 3377 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3378 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3379 return; \
3380 } \
e2be8d8d 3381 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3382 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3383 op_ldst(st##width); \
79aceca5
FB		 3384}
3385
477023a6
JM		 3386#define GEN_STUF(width, opc, type) \
3387GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3388{ \
76a66253 3389 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3390 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3391 return; \
3392 } \
76a66253 3393 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3394 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3395 return; \
9a64fbe4 3396 } \
e2be8d8d 3397 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3398 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3399 op_ldst(st##width); \
f78fb44e 3400 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3401}
3402
477023a6
JM		 3403#define GEN_STUXF(width, opc, type) \
3404GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3405{ \
76a66253 3406 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3407 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3408 return; \
3409 } \
76a66253 3410 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3411 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3412 return; \
9a64fbe4 3413 } \
e2be8d8d 3414 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3415 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3416 op_ldst(st##width); \
f78fb44e 3417 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3418}
3419
477023a6
JM		 3420#define GEN_STXF(width, opc2, opc3, type) \
3421GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3422{ \
76a66253 3423 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3424 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3425 return; \
3426 } \
e2be8d8d 3427 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3428 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3429 op_ldst(st##width); \
79aceca5
FB		 3430}
3431
477023a6 3432#define GEN_STFS(width, op, type) \
9a64fbe4 3433OP_ST_TABLE(width); \
477023a6
JM		 3434GEN_STF(width, op | 0x20, type); \
3435GEN_STUF(width, op | 0x21, type); \
3436GEN_STUXF(width, op | 0x01, type); \
3437GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3438
3439/* stfd stfdu stfdux stfdx */
477023a6 3440GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 3441/* stfs stfsu stfsux stfsx */
477023a6 3442GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3443
3444/* Optional: */
3445/* stfiwx */
5b8105fa
JM		 3446OP_ST_TABLE(fiw);
3447GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3448
3449/*** Branch ***/
b068d6a7
JM		 3450static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3451 target_ulong dest)
c1942362
FB		 3452{
3453 TranslationBlock *tb;
3454 tb = ctx->tb;
a2ffb812
AJ		 3455#if defined(TARGET_PPC64)
3456 if (!ctx->sf_mode)
3457 dest = (uint32_t) dest;
3458#endif
57fec1fe 3459 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3460 likely(!ctx->singlestep_enabled)) {
57fec1fe 3461 tcg_gen_goto_tb(n);
a2ffb812 3462 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3463 tcg_gen_exit_tb((long)tb + n);
c1942362 3464 } else {
a2ffb812 3465 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3466 if (unlikely(ctx->singlestep_enabled)) {
3467 if ((ctx->singlestep_enabled &
bdc4e053 3468 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3469 ctx->exception == POWERPC_EXCP_BRANCH) {
3470 target_ulong tmp = ctx->nip;
3471 ctx->nip = dest;
3472 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3473 ctx->nip = tmp;
3474 }
3475 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3476 gen_update_nip(ctx, dest);
64adab3f 3477 gen_helper_raise_debug();
8cbcb4fa
AJ		 3478 }
3479 }
57fec1fe 3480 tcg_gen_exit_tb(0);
c1942362 3481 }
c53be334
FB		 3482}
3483
b068d6a7 3484static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3485{
3486#if defined(TARGET_PPC64)
a2ffb812
AJ		 3487 if (ctx->sf_mode == 0)
3488 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3489 else
3490#endif
a2ffb812 3491 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3492}
3493
79aceca5
FB		 3494/* b ba bl bla */
3495GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3496{
76a66253 3497 target_ulong li, target;
38a64f9d 3498
8cbcb4fa 3499 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3500 /* sign extend LI */
76a66253 3501#if defined(TARGET_PPC64)
d9bce9d9
JM		 3502 if (ctx->sf_mode)
3503 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3504 else
76a66253 3505#endif
d9bce9d9 3506 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3507 if (likely(AA(ctx->opcode) == 0))
046d6672 3508 target = ctx->nip + li - 4;
79aceca5 3509 else
9a64fbe4 3510 target = li;
e1833e1f
JM		 3511 if (LK(ctx->opcode))
3512 gen_setlr(ctx, ctx->nip);
c1942362 3513 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3514}
3515
e98a6e40
FB		 3516#define BCOND_IM 0
3517#define BCOND_LR 1
3518#define BCOND_CTR 2
3519
b068d6a7 3520static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3521{
d9bce9d9 3522 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3523 int l1 = gen_new_label();
3524 TCGv target;
e98a6e40 3525
8cbcb4fa 3526 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3527 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3528 target = tcg_temp_local_new();
a2ffb812
AJ		 3529 if (type == BCOND_CTR)
3530 tcg_gen_mov_tl(target, cpu_ctr);
3531 else
3532 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3533 }
e1833e1f
JM		 3534 if (LK(ctx->opcode))
3535 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3536 l1 = gen_new_label();
3537 if ((bo & 0x4) == 0) {
3538 /* Decrement and test CTR */
a7812ae4 3539 TCGv temp = tcg_temp_new();
a2ffb812
AJ		 3540 if (unlikely(type == BCOND_CTR)) {
3541 GEN_EXCP_INVAL(ctx);
3542 return;
3543 }
3544 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3545#if defined(TARGET_PPC64)
a2ffb812
AJ		 3546 if (!ctx->sf_mode)
3547 tcg_gen_ext32u_tl(temp, cpu_ctr);
3548 else
d9bce9d9 3549#endif
a2ffb812
AJ		 3550 tcg_gen_mov_tl(temp, cpu_ctr);
3551 if (bo & 0x2) {
3552 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3553 } else {
3554 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3555 }
a7812ae4 3556 tcg_temp_free(temp);
a2ffb812
AJ		 3557 }
3558 if ((bo & 0x10) == 0) {
3559 /* Test CR */
3560 uint32_t bi = BI(ctx->opcode);
3561 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3562 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3563
d9bce9d9 3564 if (bo & 0x8) {
a2ffb812
AJ		 3565 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3566 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3567 } else {
a2ffb812
AJ		 3568 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3569 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3570 }
a7812ae4 3571 tcg_temp_free_i32(temp);
d9bce9d9 3572 }
e98a6e40 3573 if (type == BCOND_IM) {
a2ffb812
AJ		 3574 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3575 if (likely(AA(ctx->opcode) == 0)) {
3576 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3577 } else {
3578 gen_goto_tb(ctx, 0, li);
3579 }
c53be334 3580 gen_set_label(l1);
c1942362 3581 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3582 } else {
d9bce9d9 3583#if defined(TARGET_PPC64)
a2ffb812
AJ		 3584 if (!(ctx->sf_mode))
3585 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3586 else
3587#endif
3588 tcg_gen_andi_tl(cpu_nip, target, ~3);
3589 tcg_gen_exit_tb(0);
3590 gen_set_label(l1);
3591#if defined(TARGET_PPC64)
3592 if (!(ctx->sf_mode))
3593 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3594 else
3595#endif
a2ffb812 3596 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3597 tcg_gen_exit_tb(0);
08e46e54 3598 }
e98a6e40
FB		 3599}
3600
3601GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3602{
e98a6e40
FB		 3603 gen_bcond(ctx, BCOND_IM);
3604}
3605
3606GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3607{
e98a6e40
FB		 3608 gen_bcond(ctx, BCOND_CTR);
3609}
3610
3611GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3612{
e98a6e40
FB		 3613 gen_bcond(ctx, BCOND_LR);
3614}
79aceca5
FB		 3615
3616/*** Condition register logical ***/
e1571908
AJ		 3617#define GEN_CRLOGIC(name, tcg_op, opc) \
3618GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3619{ \
fc0d441e
JM		 3620 uint8_t bitmask; \
3621 int sh; \
a7812ae4 3622 TCGv_i32 t0, t1; \
fc0d441e 3623 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3624 t0 = tcg_temp_new_i32(); \
fc0d441e 3625 if (sh > 0) \
fea0c503 3626 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3627 else if (sh < 0) \
fea0c503 3628 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3629 else \
fea0c503 3630 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3631 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3632 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3633 if (sh > 0) \
fea0c503 3634 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3635 else if (sh < 0) \
fea0c503 3636 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3637 else \
fea0c503
AJ		 3638 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3639 tcg_op(t0, t0, t1); \
fc0d441e 3640 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3641 tcg_gen_andi_i32(t0, t0, bitmask); \
3642 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3643 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3644 tcg_temp_free_i32(t0); \
3645 tcg_temp_free_i32(t1); \
79aceca5
FB		 3646}
3647
3648/* crand */
e1571908 3649GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3650/* crandc */
e1571908 3651GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3652/* creqv */
e1571908 3653GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3654/* crnand */
e1571908 3655GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3656/* crnor */
e1571908 3657GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3658/* cror */
e1571908 3659GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3660/* crorc */
e1571908 3661GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3662/* crxor */
e1571908 3663GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3664/* mcrf */
3665GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3666{
47e4661c 3667 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3668}
3669
3670/*** System linkage ***/
3671/* rfi (supervisor only) */
76a66253 3672GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3673{
9a64fbe4 3674#if defined(CONFIG_USER_ONLY)
e1833e1f 3675 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3676#else
3677 /* Restore CPU state */
76a66253 3678 if (unlikely(!ctx->supervisor)) {
e1833e1f 3679 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3680 return;
9a64fbe4 3681 }
a42bd6cc 3682 gen_op_rfi();
e1833e1f 3683 GEN_SYNC(ctx);
9a64fbe4 3684#endif
79aceca5
FB		 3685}
3686
426613db 3687#if defined(TARGET_PPC64)
a750fc0b 3688GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3689{
3690#if defined(CONFIG_USER_ONLY)
e1833e1f 3691 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3692#else
3693 /* Restore CPU state */
3694 if (unlikely(!ctx->supervisor)) {
e1833e1f 3695 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3696 return;
3697 }
a42bd6cc 3698 gen_op_rfid();
e1833e1f 3699 GEN_SYNC(ctx);
426613db
JM		 3700#endif
3701}
426613db 3702
5b8105fa 3703GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3704{
3705#if defined(CONFIG_USER_ONLY)
3706 GEN_EXCP_PRIVOPC(ctx);
3707#else
3708 /* Restore CPU state */
3709 if (unlikely(ctx->supervisor <= 1)) {
3710 GEN_EXCP_PRIVOPC(ctx);
3711 return;
3712 }
3713 gen_op_hrfid();
3714 GEN_SYNC(ctx);
3715#endif
3716}
3717#endif
3718
79aceca5 3719/* sc */
417bf010
JM		 3720#if defined(CONFIG_USER_ONLY)
3721#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3722#else
3723#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3724#endif
e1833e1f 3725GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3726{
e1833e1f
JM		 3727 uint32_t lev;
3728
3729 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3730 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3731}
3732
3733/*** Trap ***/
3734/* tw */
76a66253 3735GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3736{
f78fb44e
AJ		 3737 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3738 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
a0ae05aa 3739 /* Update the nip since this might generate a trap exception */
d9bce9d9 3740 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3741 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3742}
3743
3744/* twi */
3745GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3746{
f78fb44e 3747 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3748 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3749 /* Update the nip since this might generate a trap exception */
3750 gen_update_nip(ctx, ctx->nip);
76a66253 3751 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3752}
3753
d9bce9d9
JM		 3754#if defined(TARGET_PPC64)
3755/* td */
3756GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3757{
f78fb44e
AJ		 3758 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3759 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3760 /* Update the nip since this might generate a trap exception */
3761 gen_update_nip(ctx, ctx->nip);
3762 gen_op_td(TO(ctx->opcode));
3763}
3764
3765/* tdi */
3766GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3767{
f78fb44e 3768 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3769 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3770 /* Update the nip since this might generate a trap exception */
3771 gen_update_nip(ctx, ctx->nip);
3772 gen_op_td(TO(ctx->opcode));
3773}
3774#endif
3775
79aceca5 3776/*** Processor control ***/
79aceca5
FB		 3777/* mcrxr */
3778GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3779{
3d7b417e
AJ		 3780 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3781 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3782 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3783}
3784
3785/* mfcr */
76a66253 3786GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3787{
76a66253 3788 uint32_t crm, crn;
3b46e624 3789
76a66253
JM		 3790 if (likely(ctx->opcode & 0x00100000)) {
3791 crm = CRM(ctx->opcode);
3792 if (likely((crm ^ (crm - 1)) == 0)) {
3793 crn = ffs(crm);
e1571908 3794 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3795 }
d9bce9d9 3796 } else {
a7812ae4 3797 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3798 }
79aceca5
FB		 3799}
3800
3801/* mfmsr */
3802GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3803{
9a64fbe4 3804#if defined(CONFIG_USER_ONLY)
e1833e1f 3805 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3806#else
76a66253 3807 if (unlikely(!ctx->supervisor)) {
e1833e1f 3808 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3809 return;
9a64fbe4 3810 }
6676f424 3811 gen_op_load_msr();
f78fb44e 3812 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3813#endif
79aceca5
FB		 3814}
3815
a11b8151 3816#if 1
6f2d8978 3817#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3818#else
3819static void spr_noaccess (void *opaque, int sprn)
3820{
3821 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3822 printf("ERROR: try to access SPR %d !\n", sprn);
3823}
3824#define SPR_NOACCESS (&spr_noaccess)
3825#endif
3826
79aceca5 3827/* mfspr */
b068d6a7 3828static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3829{
3fc6c082 3830 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3831 uint32_t sprn = SPR(ctx->opcode);
3832
3fc6c082 3833#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3834 if (ctx->supervisor == 2)
3835 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3836 else if (ctx->supervisor)
3fc6c082
FB		 3837 read_cb = ctx->spr_cb[sprn].oea_read;
3838 else
9a64fbe4 3839#endif
3fc6c082 3840 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3841 if (likely(read_cb != NULL)) {
3842 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3843 (*read_cb)(ctx, sprn);
f78fb44e 3844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3845 } else {
3846 /* Privilege exception */
9fceefa7
JM		 3847 /* This is a hack to avoid warnings when running Linux:
3848 * this OS breaks the PowerPC virtualisation model,
3849 * allowing userland application to read the PVR
3850 */
3851 if (sprn != SPR_PVR) {
3852 if (loglevel != 0) {
6b542af7 3853 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3854 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3855 }
077fc206
JM		 3856 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3857 sprn, sprn, ctx->nip);
f24e5695 3858 }
e1833e1f 3859 GEN_EXCP_PRIVREG(ctx);
79aceca5 3860 }
3fc6c082
FB		 3861 } else {
3862 /* Not defined */
4a057712 3863 if (loglevel != 0) {
077fc206
JM		 3864 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3865 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3866 }
077fc206
JM		 3867 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3868 sprn, sprn, ctx->nip);
e1833e1f
JM		 3869 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3870 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3871 }
79aceca5
FB		 3872}
3873
3fc6c082 3874GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3875{
3fc6c082 3876 gen_op_mfspr(ctx);
76a66253 3877}
3fc6c082
FB		 3878
3879/* mftb */
a750fc0b 3880GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3881{
3882 gen_op_mfspr(ctx);
79aceca5
FB		 3883}
3884
3885/* mtcrf */
8dd4983c 3886GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3887{
76a66253 3888 uint32_t crm, crn;
3b46e624 3889
76a66253
JM		 3890 crm = CRM(ctx->opcode);
3891 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3892 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3893 crn = ffs(crm);
a7812ae4
PB		 3894 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3895 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3896 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3897 tcg_temp_free_i32(temp);
76a66253 3898 } else {
a7812ae4
PB		 3899 TCGv_i32 temp = tcg_const_i32(crm);
3900 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3901 tcg_temp_free_i32(temp);
76a66253 3902 }
79aceca5
FB		 3903}
3904
3905/* mtmsr */
426613db 3906#if defined(TARGET_PPC64)
be147d08 3907GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3908{
3909#if defined(CONFIG_USER_ONLY)
e1833e1f 3910 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3911#else
3912 if (unlikely(!ctx->supervisor)) {
e1833e1f 3913 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3914 return;
3915 }
f78fb44e 3916 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3917 if (ctx->opcode & 0x00010000) {
3918 /* Special form that does not need any synchronisation */
3919 gen_op_update_riee();
3920 } else {
056b05f8
JM		 3921 /* XXX: we need to update nip before the store
3922 * if we enter power saving mode, we will exit the loop
3923 * directly from ppc_store_msr
3924 */
be147d08 3925 gen_update_nip(ctx, ctx->nip);
6676f424 3926 gen_op_store_msr();
be147d08
JM		 3927 /* Must stop the translation as machine state (may have) changed */
3928 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3929 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3930 }
426613db
JM		 3931#endif
3932}
3933#endif
3934
79aceca5
FB		 3935GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3936{
9a64fbe4 3937#if defined(CONFIG_USER_ONLY)
e1833e1f 3938 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3939#else
76a66253 3940 if (unlikely(!ctx->supervisor)) {
e1833e1f 3941 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3942 return;
9a64fbe4 3943 }
f78fb44e 3944 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3945 if (ctx->opcode & 0x00010000) {
3946 /* Special form that does not need any synchronisation */
3947 gen_op_update_riee();
3948 } else {
056b05f8
JM		 3949 /* XXX: we need to update nip before the store
3950 * if we enter power saving mode, we will exit the loop
3951 * directly from ppc_store_msr
3952 */
be147d08 3953 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3954#if defined(TARGET_PPC64)
be147d08 3955 if (!ctx->sf_mode)
6676f424 3956 gen_op_store_msr_32();
be147d08 3957 else
d9bce9d9 3958#endif
6676f424 3959 gen_op_store_msr();
be147d08
JM		 3960 /* Must stop the translation as machine state (may have) changed */
3961 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3962 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3963 }
9a64fbe4 3964#endif
79aceca5
FB		 3965}
3966
3967/* mtspr */
3968GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3969{
3fc6c082 3970 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3971 uint32_t sprn = SPR(ctx->opcode);
3972
3fc6c082 3973#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3974 if (ctx->supervisor == 2)
3975 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3976 else if (ctx->supervisor)
3fc6c082
FB		 3977 write_cb = ctx->spr_cb[sprn].oea_write;
3978 else
9a64fbe4 3979#endif
3fc6c082 3980 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3981 if (likely(write_cb != NULL)) {
3982 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 3983 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 3984 (*write_cb)(ctx, sprn);
3985 } else {
3986 /* Privilege exception */
4a057712 3987 if (loglevel != 0) {
077fc206
JM		 3988 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3989 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3990 }
077fc206
JM		 3991 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3992 sprn, sprn, ctx->nip);
e1833e1f 3993 GEN_EXCP_PRIVREG(ctx);
76a66253 3994 }
3fc6c082
FB		 3995 } else {
3996 /* Not defined */
4a057712 3997 if (loglevel != 0) {
077fc206
JM		 3998 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3999 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4000 }
077fc206
JM		 4001 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4002 sprn, sprn, ctx->nip);
e1833e1f
JM		 4003 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4004 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 4005 }
79aceca5
FB		 4006}
4007
4008/*** Cache management ***/
79aceca5 4009/* dcbf */
0db1b20e 4010GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4011{
dac454af 4012 /* XXX: specification says this is treated as a load by the MMU */
a7812ae4 4013 TCGv t0 = tcg_temp_new();
fea0c503
AJ		 4014 gen_addr_reg_index(t0, ctx);
4015 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4016 tcg_temp_free(t0);
79aceca5
FB		 4017}
4018
4019/* dcbi (Supervisor only) */
9a64fbe4 4020GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4021{
a541f297 4022#if defined(CONFIG_USER_ONLY)
e1833e1f 4023 GEN_EXCP_PRIVOPC(ctx);
a541f297 4024#else
b61f2753 4025 TCGv EA, val;
76a66253 4026 if (unlikely(!ctx->supervisor)) {
e1833e1f 4027 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4028 return;
9a64fbe4 4029 }
a7812ae4 4030 EA = tcg_temp_new();
b61f2753 4031 gen_addr_reg_index(EA, ctx);
a7812ae4 4032 val = tcg_temp_new();
76a66253 4033 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 4034 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4035 gen_qemu_st8(val, EA, ctx->mem_idx);
4036 tcg_temp_free(val);
4037 tcg_temp_free(EA);
a541f297 4038#endif
79aceca5
FB		 4039}
4040
4041/* dcdst */
9a64fbe4 4042GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4043{
76a66253 4044 /* XXX: specification say this is treated as a load by the MMU */
a7812ae4 4045 TCGv t0 = tcg_temp_new();
fea0c503
AJ		 4046 gen_addr_reg_index(t0, ctx);
4047 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4048 tcg_temp_free(t0);
79aceca5
FB		 4049}
4050
4051/* dcbt */
0db1b20e 4052GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4053{
0db1b20e 4054 /* interpreted as no-op */
76a66253
JM		 4055 /* XXX: specification say this is treated as a load by the MMU
4056 * but does not generate any exception
4057 */
79aceca5
FB		 4058}
4059
4060/* dcbtst */
0db1b20e 4061GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4062{
0db1b20e 4063 /* interpreted as no-op */
76a66253
JM		 4064 /* XXX: specification say this is treated as a load by the MMU
4065 * but does not generate any exception
4066 */
79aceca5
FB		 4067}
4068
4069/* dcbz */
d63001d1 4070#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 4071static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
4072 /* 32 bytes cache line size */
d63001d1 4073 {
7863667f
JM		 4074#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
4075#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
4076#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
4077#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
4078#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
4079#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
4080#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
4081#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
4082 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 4083 },
7863667f 4084 /* 64 bytes cache line size */
d63001d1 4085 {
7863667f
JM		 4086#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
4087#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
4088#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
4089#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
4090#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
4091#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
4092#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
4093#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
4094 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 4095 },
7863667f 4096 /* 128 bytes cache line size */
d63001d1 4097 {
7863667f
JM		 4098#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
4099#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
4100#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
4101#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
4102#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
4103#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
4104#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
4105#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
4106 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 4107 },
7863667f 4108 /* tunable cache line size */
d63001d1 4109 {
7863667f
JM		 4110#define gen_op_dcbz_le_raw gen_op_dcbz_raw
4111#define gen_op_dcbz_le_user gen_op_dcbz_user
4112#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
4113#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
4114#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
4115#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
4116#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
4117#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
4118 GEN_MEM_FUNCS(dcbz),
d63001d1 4119 },
76a66253 4120};
9a64fbe4 4121
b068d6a7
JM		 4122static always_inline void handler_dcbz (DisasContext *ctx,
4123 int dcache_line_size)
d63001d1
JM		 4124{
4125 int n;
4126
4127 switch (dcache_line_size) {
4128 case 32:
4129 n = 0;
4130 break;
4131 case 64:
4132 n = 1;
4133 break;
4134 case 128:
4135 n = 2;
4136 break;
4137 default:
4138 n = 3;
4139 break;
4140 }
4141 op_dcbz(n);
4142}
4143
4144GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4145{
e2be8d8d 4146 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 4147 handler_dcbz(ctx, ctx->dcache_line_size);
4148 gen_op_check_reservation();
4149}
4150
c7697e1f 4151GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4152{
e2be8d8d 4153 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 4154 if (ctx->opcode & 0x00200000)
4155 handler_dcbz(ctx, ctx->dcache_line_size);
4156 else
4157 handler_dcbz(ctx, -1);
4b3686fa 4158 gen_op_check_reservation();
79aceca5
FB		 4159}
4160
4161/* icbi */
36f69651 4162#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 4163#define gen_op_icbi_le_raw gen_op_icbi_raw
4164#define gen_op_icbi_le_user gen_op_icbi_user
4165#define gen_op_icbi_le_kernel gen_op_icbi_kernel
4166#define gen_op_icbi_le_hypv gen_op_icbi_hypv
4167#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4168#define gen_op_icbi_le_64_user gen_op_icbi_64_user
4169#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4170#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4171static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4172 GEN_MEM_FUNCS(icbi),
36f69651 4173};
e1833e1f 4174
1b413d55 4175GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4176{
30032c94
JM		 4177 /* NIP cannot be restored if the memory exception comes from an helper */
4178 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4179 gen_addr_reg_index(cpu_T[0], ctx);
36f69651 4180 op_icbi();
79aceca5
FB		 4181}
4182
4183/* Optional: */
4184/* dcba */
a750fc0b 4185GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4186{
0db1b20e
JM		 4187 /* interpreted as no-op */
4188 /* XXX: specification say this is treated as a store by the MMU
4189 * but does not generate any exception
4190 */
79aceca5
FB		 4191}
4192
4193/*** Segment register manipulation ***/
4194/* Supervisor only: */
4195/* mfsr */
4196GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4197{
9a64fbe4 4198#if defined(CONFIG_USER_ONLY)
e1833e1f 4199 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4200#else
76a66253 4201 if (unlikely(!ctx->supervisor)) {
e1833e1f 4202 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4203 return;
9a64fbe4 4204 }
86c581dc 4205 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4206 gen_op_load_sr();
f78fb44e 4207 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4208#endif
79aceca5
FB		 4209}
4210
4211/* mfsrin */
9a64fbe4 4212GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4213{
9a64fbe4 4214#if defined(CONFIG_USER_ONLY)
e1833e1f 4215 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4216#else
76a66253 4217 if (unlikely(!ctx->supervisor)) {
e1833e1f 4218 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4219 return;
9a64fbe4 4220 }
f78fb44e 4221 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4222 gen_op_srli_T1(28);
4223 gen_op_load_sr();
f78fb44e 4224 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4225#endif
79aceca5
FB		 4226}
4227
4228/* mtsr */
e63c59cb 4229GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4230{
9a64fbe4 4231#if defined(CONFIG_USER_ONLY)
e1833e1f 4232 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4233#else
76a66253 4234 if (unlikely(!ctx->supervisor)) {
e1833e1f 4235 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4236 return;
9a64fbe4 4237 }
f78fb44e 4238 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4239 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4240 gen_op_store_sr();
9a64fbe4 4241#endif
79aceca5
FB		 4242}
4243
4244/* mtsrin */
9a64fbe4 4245GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4246{
9a64fbe4 4247#if defined(CONFIG_USER_ONLY)
e1833e1f 4248 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4249#else
76a66253 4250 if (unlikely(!ctx->supervisor)) {
e1833e1f 4251 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4252 return;
9a64fbe4 4253 }
f78fb44e
AJ		 4254 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4255 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4256 gen_op_srli_T1(28);
4257 gen_op_store_sr();
9a64fbe4 4258#endif
79aceca5
FB		 4259}
4260
12de9a39
JM		 4261#if defined(TARGET_PPC64)
4262/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4263/* mfsr */
c7697e1f 4264GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4265{
4266#if defined(CONFIG_USER_ONLY)
4267 GEN_EXCP_PRIVREG(ctx);
4268#else
4269 if (unlikely(!ctx->supervisor)) {
4270 GEN_EXCP_PRIVREG(ctx);
4271 return;
4272 }
86c581dc 4273 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4274 gen_op_load_slb();
f78fb44e 4275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4276#endif
4277}
4278
4279/* mfsrin */
c7697e1f
JM		 4280GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4281 PPC_SEGMENT_64B)
12de9a39
JM		 4282{
4283#if defined(CONFIG_USER_ONLY)
4284 GEN_EXCP_PRIVREG(ctx);
4285#else
4286 if (unlikely(!ctx->supervisor)) {
4287 GEN_EXCP_PRIVREG(ctx);
4288 return;
4289 }
f78fb44e 4290 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4291 gen_op_srli_T1(28);
4292 gen_op_load_slb();
f78fb44e 4293 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4294#endif
4295}
4296
4297/* mtsr */
c7697e1f 4298GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4299{
4300#if defined(CONFIG_USER_ONLY)
4301 GEN_EXCP_PRIVREG(ctx);
4302#else
4303 if (unlikely(!ctx->supervisor)) {
4304 GEN_EXCP_PRIVREG(ctx);
4305 return;
4306 }
f78fb44e 4307 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4308 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4309 gen_op_store_slb();
4310#endif
4311}
4312
4313/* mtsrin */
c7697e1f
JM		 4314GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4315 PPC_SEGMENT_64B)
12de9a39
JM		 4316{
4317#if defined(CONFIG_USER_ONLY)
4318 GEN_EXCP_PRIVREG(ctx);
4319#else
4320 if (unlikely(!ctx->supervisor)) {
4321 GEN_EXCP_PRIVREG(ctx);
4322 return;
4323 }
f78fb44e
AJ		 4324 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4325 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4326 gen_op_srli_T1(28);
4327 gen_op_store_slb();
4328#endif
4329}
4330#endif /* defined(TARGET_PPC64) */
4331
79aceca5
FB		 4332/*** Lookaside buffer management ***/
4333/* Optional & supervisor only: */
4334/* tlbia */
3fc6c082 4335GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4336{
9a64fbe4 4337#if defined(CONFIG_USER_ONLY)
e1833e1f 4338 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4339#else
76a66253 4340 if (unlikely(!ctx->supervisor)) {
e1833e1f 4341 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4342 return;
9a64fbe4
FB		 4343 }
4344 gen_op_tlbia();
4345#endif
79aceca5
FB		 4346}
4347
4348/* tlbie */
76a66253 4349GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4350{
9a64fbe4 4351#if defined(CONFIG_USER_ONLY)
e1833e1f 4352 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4353#else
76a66253 4354 if (unlikely(!ctx->supervisor)) {
e1833e1f 4355 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4356 return;
9a64fbe4 4357 }
f78fb44e 4358 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4359#if defined(TARGET_PPC64)
4360 if (ctx->sf_mode)
4361 gen_op_tlbie_64();
4362 else
4363#endif
4364 gen_op_tlbie();
9a64fbe4 4365#endif
79aceca5
FB		 4366}
4367
4368/* tlbsync */
76a66253 4369GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4370{
9a64fbe4 4371#if defined(CONFIG_USER_ONLY)
e1833e1f 4372 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4373#else
76a66253 4374 if (unlikely(!ctx->supervisor)) {
e1833e1f 4375 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4376 return;
9a64fbe4
FB		 4377 }
4378 /* This has no effect: it should ensure that all previous
4379 * tlbie have completed
4380 */
e1833e1f 4381 GEN_STOP(ctx);
9a64fbe4 4382#endif
79aceca5
FB		 4383}
4384
426613db
JM		 4385#if defined(TARGET_PPC64)
4386/* slbia */
4387GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4388{
4389#if defined(CONFIG_USER_ONLY)
e1833e1f 4390 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4391#else
4392 if (unlikely(!ctx->supervisor)) {
e1833e1f 4393 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4394 return;
4395 }
4396 gen_op_slbia();
426613db
JM		 4397#endif
4398}
4399
4400/* slbie */
4401GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4402{
4403#if defined(CONFIG_USER_ONLY)
e1833e1f 4404 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4405#else
4406 if (unlikely(!ctx->supervisor)) {
e1833e1f 4407 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4408 return;
4409 }
f78fb44e 4410 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4411 gen_op_slbie();
426613db
JM		 4412#endif
4413}
4414#endif
4415
79aceca5
FB		 4416/*** External control ***/
4417/* Optional: */
9a64fbe4
FB		 4418#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4419#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4420static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4421 GEN_MEM_FUNCS(eciwx),
111bfab3 4422};
7863667f
JM		 4423static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4424 GEN_MEM_FUNCS(ecowx),
111bfab3 4425};
9a64fbe4 4426
111bfab3 4427/* eciwx */
79aceca5
FB		 4428GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4429{
9a64fbe4 4430 /* Should check EAR[E] & alignment ! */
e2be8d8d 4431 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4432 op_eciwx();
f78fb44e 4433 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4434}
4435
4436/* ecowx */
4437GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4438{
4439 /* Should check EAR[E] & alignment ! */
e2be8d8d 4440 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4441 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4442 op_ecowx();
4443}
4444
4445/* PowerPC 601 specific instructions */
4446/* abs - abs. */
4447GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4448{
f78fb44e 4449 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4450 gen_op_POWER_abs();
f78fb44e 4451 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4452 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4453 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4454}
4455
4456/* abso - abso. */
4457GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4458{
f78fb44e 4459 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4460 gen_op_POWER_abso();
f78fb44e 4461 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4462 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4463 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4464}
4465
4466/* clcs */
a750fc0b 4467GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4468{
f78fb44e 4469 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4470 gen_op_POWER_clcs();
c7697e1f 4471 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4472 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4473}
4474
4475/* div - div. */
4476GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4477{
f78fb44e
AJ		 4478 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4479 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4480 gen_op_POWER_div();
f78fb44e 4481 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4482 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4483 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4484}
4485
4486/* divo - divo. */
4487GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4488{
f78fb44e
AJ		 4489 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4490 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4491 gen_op_POWER_divo();
f78fb44e 4492 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4493 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4494 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4495}
4496
4497/* divs - divs. */
4498GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4499{
f78fb44e
AJ		 4500 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4501 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4502 gen_op_POWER_divs();
f78fb44e 4503 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4504 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4505 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4506}
4507
4508/* divso - divso. */
4509GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4510{
f78fb44e
AJ		 4511 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4512 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4513 gen_op_POWER_divso();
f78fb44e 4514 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4515 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4516 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4517}
4518
4519/* doz - doz. */
4520GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4521{
f78fb44e
AJ		 4522 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4523 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4524 gen_op_POWER_doz();
f78fb44e 4525 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4526 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4527 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4528}
4529
4530/* dozo - dozo. */
4531GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4532{
f78fb44e
AJ		 4533 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4534 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4535 gen_op_POWER_dozo();
f78fb44e 4536 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4537 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4538 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4539}
4540
4541/* dozi */
4542GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4543{
f78fb44e 4544 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4545 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4546 gen_op_POWER_doz();
f78fb44e 4547 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4548}
4549
7863667f
JM		 4550/* As lscbx load from memory byte after byte, it's always endian safe.
4551 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4552 */
2857068e 4553#define op_POWER_lscbx(start, ra, rb) \
76a66253 4554(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 4555#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4556#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4557#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4558#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4559#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4560#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4561#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4562#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4563#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4564#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4565#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4566#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4567static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4568 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4569};
76a66253
JM		 4570
4571/* lscbx - lscbx. */
4572GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4573{
4574 int ra = rA(ctx->opcode);
4575 int rb = rB(ctx->opcode);
4576
e2be8d8d 4577 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4578 if (ra == 0) {
4579 ra = rb;
4580 }
4581 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4582 gen_update_nip(ctx, ctx->nip - 4);
3d7b417e
AJ		 4583 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4584 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4585 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
76a66253 4586 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3d7b417e
AJ		 4587 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4588 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253 4589 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4590 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4591}
4592
4593/* maskg - maskg. */
4594GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4595{
f78fb44e
AJ		 4596 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4597 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4598 gen_op_POWER_maskg();
f78fb44e 4599 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4600 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4601 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4602}
4603
4604/* maskir - maskir. */
4605GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4606{
f78fb44e
AJ		 4607 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4608 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4609 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4610 gen_op_POWER_maskir();
f78fb44e 4611 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4612 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4613 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4614}
4615
4616/* mul - mul. */
4617GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4618{
f78fb44e
AJ		 4619 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4620 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4621 gen_op_POWER_mul();
f78fb44e 4622 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4623 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4624 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4625}
4626
4627/* mulo - mulo. */
4628GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4629{
f78fb44e
AJ		 4630 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4631 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4632 gen_op_POWER_mulo();
f78fb44e 4633 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4634 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4635 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4636}
4637
4638/* nabs - nabs. */
4639GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4640{
f78fb44e 4641 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4642 gen_op_POWER_nabs();
f78fb44e 4643 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4644 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4645 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4646}
4647
4648/* nabso - nabso. */
4649GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4650{
f78fb44e 4651 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4652 gen_op_POWER_nabso();
f78fb44e 4653 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4654 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4655 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4656}
4657
4658/* rlmi - rlmi. */
4659GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4660{
4661 uint32_t mb, me;
4662
4663 mb = MB(ctx->opcode);
4664 me = ME(ctx->opcode);
f78fb44e
AJ		 4665 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4666 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4667 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4668 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4669 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4670 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4671 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4672}
4673
4674/* rrib - rrib. */
4675GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4676{
f78fb44e
AJ		 4677 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4678 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4679 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4680 gen_op_POWER_rrib();
f78fb44e 4681 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4682 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4683 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4684}
4685
4686/* sle - sle. */
4687GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4688{
f78fb44e
AJ		 4689 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4690 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4691 gen_op_POWER_sle();
f78fb44e 4692 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4693 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4694 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4695}
4696
4697/* sleq - sleq. */
4698GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4699{
f78fb44e
AJ		 4700 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4701 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4702 gen_op_POWER_sleq();
f78fb44e 4703 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4704 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4705 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4706}
4707
4708/* sliq - sliq. */
4709GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4710{
f78fb44e 4711 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4712 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4713 gen_op_POWER_sle();
f78fb44e 4714 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4715 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4716 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4717}
4718
4719/* slliq - slliq. */
4720GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4721{
f78fb44e 4722 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4723 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4724 gen_op_POWER_sleq();
f78fb44e 4725 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4726 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4727 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4728}
4729
4730/* sllq - sllq. */
4731GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4732{
f78fb44e
AJ		 4733 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4734 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4735 gen_op_POWER_sllq();
f78fb44e 4736 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4737 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4738 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4739}
4740
4741/* slq - slq. */
4742GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4743{
f78fb44e
AJ		 4744 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4745 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4746 gen_op_POWER_slq();
f78fb44e 4747 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4748 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4749 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4750}
4751
d9bce9d9 4752/* sraiq - sraiq. */
76a66253
JM		 4753GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4754{
f78fb44e 4755 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4756 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4757 gen_op_POWER_sraq();
f78fb44e 4758 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4759 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4760 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4761}
4762
4763/* sraq - sraq. */
4764GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4765{
f78fb44e
AJ		 4766 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4767 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4768 gen_op_POWER_sraq();
f78fb44e 4769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4770 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4771 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4772}
4773
4774/* sre - sre. */
4775GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4776{
f78fb44e
AJ		 4777 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4778 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4779 gen_op_POWER_sre();
f78fb44e 4780 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4781 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4782 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4783}
4784
4785/* srea - srea. */
4786GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4787{
f78fb44e
AJ		 4788 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4789 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4790 gen_op_POWER_srea();
f78fb44e 4791 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4792 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4793 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4794}
4795
4796/* sreq */
4797GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4798{
f78fb44e
AJ		 4799 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4800 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4801 gen_op_POWER_sreq();
f78fb44e 4802 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4803 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4804 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4805}
4806
4807/* sriq */
4808GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4809{
f78fb44e 4810 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4811 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4812 gen_op_POWER_srq();
f78fb44e 4813 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4814 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4815 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4816}
4817
4818/* srliq */
4819GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4820{
f78fb44e
AJ		 4821 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4822 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4823 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4824 gen_op_POWER_srlq();
f78fb44e 4825 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4826 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4827 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4828}
4829
4830/* srlq */
4831GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4832{
f78fb44e
AJ		 4833 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4834 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4835 gen_op_POWER_srlq();
f78fb44e 4836 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4837 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4838 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4839}
4840
4841/* srq */
4842GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4843{
f78fb44e
AJ		 4844 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4845 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4846 gen_op_POWER_srq();
f78fb44e 4847 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4848 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4849 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4850}
4851
4852/* PowerPC 602 specific instructions */
4853/* dsa */
4854GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4855{
4856 /* XXX: TODO */
e1833e1f 4857 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4858}
4859
4860/* esa */
4861GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4862{
4863 /* XXX: TODO */
e1833e1f 4864 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4865}
4866
4867/* mfrom */
4868GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4869{
4870#if defined(CONFIG_USER_ONLY)
e1833e1f 4871 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4872#else
4873 if (unlikely(!ctx->supervisor)) {
e1833e1f 4874 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4875 return;
4876 }
f78fb44e 4877 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4878 gen_op_602_mfrom();
f78fb44e 4879 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4880#endif
4881}
4882
4883/* 602 - 603 - G2 TLB management */
4884/* tlbld */
c7697e1f 4885GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4886{
4887#if defined(CONFIG_USER_ONLY)
e1833e1f 4888 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4889#else
4890 if (unlikely(!ctx->supervisor)) {
e1833e1f 4891 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4892 return;
4893 }
f78fb44e 4894 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4895 gen_op_6xx_tlbld();
76a66253
JM		 4896#endif
4897}
4898
4899/* tlbli */
c7697e1f 4900GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4901{
4902#if defined(CONFIG_USER_ONLY)
e1833e1f 4903 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4904#else
4905 if (unlikely(!ctx->supervisor)) {
e1833e1f 4906 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4907 return;
4908 }
f78fb44e 4909 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4910 gen_op_6xx_tlbli();
76a66253
JM		 4911#endif
4912}
4913
7dbe11ac
JM		 4914/* 74xx TLB management */
4915/* tlbld */
c7697e1f 4916GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4917{
4918#if defined(CONFIG_USER_ONLY)
4919 GEN_EXCP_PRIVOPC(ctx);
4920#else
4921 if (unlikely(!ctx->supervisor)) {
4922 GEN_EXCP_PRIVOPC(ctx);
4923 return;
4924 }
f78fb44e 4925 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4926 gen_op_74xx_tlbld();
4927#endif
4928}
4929
4930/* tlbli */
c7697e1f 4931GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4932{
4933#if defined(CONFIG_USER_ONLY)
4934 GEN_EXCP_PRIVOPC(ctx);
4935#else
4936 if (unlikely(!ctx->supervisor)) {
4937 GEN_EXCP_PRIVOPC(ctx);
4938 return;
4939 }
f78fb44e 4940 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4941 gen_op_74xx_tlbli();
4942#endif
4943}
4944
76a66253
JM		 4945/* POWER instructions not in PowerPC 601 */
4946/* clf */
4947GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4948{
4949 /* Cache line flush: implemented as no-op */
4950}
4951
4952/* cli */
4953GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4954{
7f75ffd3 4955 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4956#if defined(CONFIG_USER_ONLY)
e1833e1f 4957 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4958#else
4959 if (unlikely(!ctx->supervisor)) {
e1833e1f 4960 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4961 return;
4962 }
4963#endif
4964}
4965
4966/* dclst */
4967GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4968{
4969 /* Data cache line store: treated as no-op */
4970}
4971
4972GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4973{
4974#if defined(CONFIG_USER_ONLY)
e1833e1f 4975 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4976#else
4977 if (unlikely(!ctx->supervisor)) {
e1833e1f 4978 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4979 return;
4980 }
4981 int ra = rA(ctx->opcode);
4982 int rd = rD(ctx->opcode);
4983
e2be8d8d 4984 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4985 gen_op_POWER_mfsri();
f78fb44e 4986 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4987 if (ra != 0 && ra != rd)
f78fb44e 4988 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4989#endif
4990}
4991
4992GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4993{
4994#if defined(CONFIG_USER_ONLY)
e1833e1f 4995 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4996#else
4997 if (unlikely(!ctx->supervisor)) {
e1833e1f 4998 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4999 return;
5000 }
e2be8d8d 5001 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5002 gen_op_POWER_rac();
f78fb44e 5003 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5004#endif
5005}
5006
5007GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5008{
5009#if defined(CONFIG_USER_ONLY)
e1833e1f 5010 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5011#else
5012 if (unlikely(!ctx->supervisor)) {
e1833e1f 5013 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5014 return;
5015 }
5016 gen_op_POWER_rfsvc();
e1833e1f 5017 GEN_SYNC(ctx);
76a66253
JM		 5018#endif
5019}
5020
5021/* svc is not implemented for now */
5022
5023/* POWER2 specific instructions */
5024/* Quad manipulation (load/store two floats at a time) */
7863667f 5025/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 5026#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
5027#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 5028#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
5029#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
5030#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
5031#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
5032#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
5033#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
5034#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
5035#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
5036#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
5037#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
5038#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
5039#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
5040#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
5041#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
5042#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
5043#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
5044static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
5045 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 5046};
7863667f
JM		 5047static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
5048 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 5049};
76a66253
JM		 5050
5051/* lfq */
5052GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5053{
5054 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5055 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5056 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 5057 op_POWER2_lfq();
a5e26afa
AJ		 5058 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5059 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 5060}
5061
5062/* lfqu */
5063GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5064{
5065 int ra = rA(ctx->opcode);
5066
5067 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5068 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5069 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 5070 op_POWER2_lfq();
a5e26afa
AJ		 5071 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5072 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 5073 if (ra != 0)
f78fb44e 5074 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5075}
5076
5077/* lfqux */
5078GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5079{
5080 int ra = rA(ctx->opcode);
5081
5082 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5083 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5084 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5085 op_POWER2_lfq();
a5e26afa
AJ		 5086 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5087 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 5088 if (ra != 0)
f78fb44e 5089 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5090}
5091
5092/* lfqx */
5093GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5094{
5095 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5096 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5097 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5098 op_POWER2_lfq();
a5e26afa
AJ		 5099 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5100 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 5101}
5102
5103/* stfq */
5104GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5105{
5106 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5107 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5108 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 5109 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5110 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5111 op_POWER2_stfq();
5112}
5113
5114/* stfqu */
5115GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5116{
5117 int ra = rA(ctx->opcode);
5118
5119 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5120 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5121 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 5122 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5123 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5124 op_POWER2_stfq();
5125 if (ra != 0)
f78fb44e 5126 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5127}
5128
5129/* stfqux */
5130GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5131{
5132 int ra = rA(ctx->opcode);
5133
5134 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5135 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5136 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 5137 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5138 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5139 op_POWER2_stfq();
5140 if (ra != 0)
f78fb44e 5141 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5142}
5143
5144/* stfqx */
5145GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5146{
5147 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5148 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5149 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 5150 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5151 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5152 op_POWER2_stfq();
5153}
5154
5155/* BookE specific instructions */
2662a059 5156/* XXX: not implemented on 440 ? */
05332d70 5157GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5158{
5159 /* XXX: TODO */
e1833e1f 5160 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5161}
5162
2662a059 5163/* XXX: not implemented on 440 ? */
05332d70 5164GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5165{
5166#if defined(CONFIG_USER_ONLY)
e1833e1f 5167 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5168#else
5169 if (unlikely(!ctx->supervisor)) {
e1833e1f 5170 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5171 return;
5172 }
e2be8d8d 5173 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5174 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5175#if defined(TARGET_PPC64)
5176 if (ctx->sf_mode)
5177 gen_op_tlbie_64();
5178 else
5179#endif
5180 gen_op_tlbie();
76a66253
JM		 5181#endif
5182}
5183
5184/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5185static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5186 int opc2, int opc3,
5187 int ra, int rb, int rt, int Rc)
76a66253 5188{
182608d4
AJ		 5189 TCGv t0, t1;
5190
a7812ae4
PB		 5191 t0 = tcg_temp_local_new();
5192 t1 = tcg_temp_local_new();
182608d4 5193
76a66253
JM		 5194 switch (opc3 & 0x0D) {
5195 case 0x05:
5196 /* macchw - macchw. - macchwo - macchwo. */
5197 /* macchws - macchws. - macchwso - macchwso. */
5198 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5199 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5200 /* mulchw - mulchw. */
182608d4
AJ		 5201 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5202 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5203 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5204 break;
5205 case 0x04:
5206 /* macchwu - macchwu. - macchwuo - macchwuo. */
5207 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5208 /* mulchwu - mulchwu. */
182608d4
AJ		 5209 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5210 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5211 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5212 break;
5213 case 0x01:
5214 /* machhw - machhw. - machhwo - machhwo. */
5215 /* machhws - machhws. - machhwso - machhwso. */
5216 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5217 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5218 /* mulhhw - mulhhw. */
182608d4
AJ		 5219 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5220 tcg_gen_ext16s_tl(t0, t0);
5221 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5222 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5223 break;
5224 case 0x00:
5225 /* machhwu - machhwu. - machhwuo - machhwuo. */
5226 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5227 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5228 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5229 tcg_gen_ext16u_tl(t0, t0);
5230 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5231 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5232 break;
5233 case 0x0D:
5234 /* maclhw - maclhw. - maclhwo - maclhwo. */
5235 /* maclhws - maclhws. - maclhwso - maclhwso. */
5236 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5237 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5238 /* mullhw - mullhw. */
182608d4
AJ		 5239 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5240 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5241 break;
5242 case 0x0C:
5243 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5244 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5245 /* mullhwu - mullhwu. */
182608d4
AJ		 5246 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5247 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5248 break;
5249 }
76a66253 5250 if (opc2 & 0x04) {
182608d4
AJ		 5251 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5252 tcg_gen_mul_tl(t1, t0, t1);
5253 if (opc2 & 0x02) {
5254 /* nmultiply-and-accumulate (0x0E) */
5255 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5256 } else {
5257 /* multiply-and-accumulate (0x0C) */
5258 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5259 }
5260
5261 if (opc3 & 0x12) {
5262 /* Check overflow and/or saturate */
5263 int l1 = gen_new_label();
5264
5265 if (opc3 & 0x10) {
5266 /* Start with XER OV disabled, the most likely case */
5267 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5268 }
5269 if (opc3 & 0x01) {
5270 /* Signed */
5271 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5272 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5273 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5274 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5275 if (opc3 & 0x02) {
182608d4
AJ		 5276 /* Saturate */
5277 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5278 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5279 }
5280 } else {
5281 /* Unsigned */
5282 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5283 if (opc3 & 0x02) {
182608d4
AJ		 5284 /* Saturate */
5285 tcg_gen_movi_tl(t0, UINT32_MAX);
5286 }
5287 }
5288 if (opc3 & 0x10) {
5289 /* Check overflow */
5290 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5291 }
5292 gen_set_label(l1);
5293 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5294 }
5295 } else {
5296 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5297 }
182608d4
AJ		 5298 tcg_temp_free(t0);
5299 tcg_temp_free(t1);
76a66253
JM		 5300 if (unlikely(Rc) != 0) {
5301 /* Update Rc0 */
182608d4 5302 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5303 }
5304}
5305
a750fc0b
JM		 5306#define GEN_MAC_HANDLER(name, opc2, opc3) \
5307GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5308{ \
5309 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5310 rD(ctx->opcode), Rc(ctx->opcode)); \
5311}
5312
5313/* macchw - macchw. */
a750fc0b 5314GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5315/* macchwo - macchwo. */
a750fc0b 5316GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5317/* macchws - macchws. */
a750fc0b 5318GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5319/* macchwso - macchwso. */
a750fc0b 5320GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5321/* macchwsu - macchwsu. */
a750fc0b 5322GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5323/* macchwsuo - macchwsuo. */
a750fc0b 5324GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5325/* macchwu - macchwu. */
a750fc0b 5326GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5327/* macchwuo - macchwuo. */
a750fc0b 5328GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5329/* machhw - machhw. */
a750fc0b 5330GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5331/* machhwo - machhwo. */
a750fc0b 5332GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5333/* machhws - machhws. */
a750fc0b 5334GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5335/* machhwso - machhwso. */
a750fc0b 5336GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5337/* machhwsu - machhwsu. */
a750fc0b 5338GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5339/* machhwsuo - machhwsuo. */
a750fc0b 5340GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5341/* machhwu - machhwu. */
a750fc0b 5342GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5343/* machhwuo - machhwuo. */
a750fc0b 5344GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5345/* maclhw - maclhw. */
a750fc0b 5346GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5347/* maclhwo - maclhwo. */
a750fc0b 5348GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5349/* maclhws - maclhws. */
a750fc0b 5350GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5351/* maclhwso - maclhwso. */
a750fc0b 5352GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5353/* maclhwu - maclhwu. */
a750fc0b 5354GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5355/* maclhwuo - maclhwuo. */
a750fc0b 5356GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5357/* maclhwsu - maclhwsu. */
a750fc0b 5358GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5359/* maclhwsuo - maclhwsuo. */
a750fc0b 5360GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5361/* nmacchw - nmacchw. */
a750fc0b 5362GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5363/* nmacchwo - nmacchwo. */
a750fc0b 5364GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5365/* nmacchws - nmacchws. */
a750fc0b 5366GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5367/* nmacchwso - nmacchwso. */
a750fc0b 5368GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5369/* nmachhw - nmachhw. */
a750fc0b 5370GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5371/* nmachhwo - nmachhwo. */
a750fc0b 5372GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5373/* nmachhws - nmachhws. */
a750fc0b 5374GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5375/* nmachhwso - nmachhwso. */
a750fc0b 5376GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5377/* nmaclhw - nmaclhw. */
a750fc0b 5378GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5379/* nmaclhwo - nmaclhwo. */
a750fc0b 5380GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5381/* nmaclhws - nmaclhws. */
a750fc0b 5382GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5383/* nmaclhwso - nmaclhwso. */
a750fc0b 5384GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5385
5386/* mulchw - mulchw. */
a750fc0b 5387GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5388/* mulchwu - mulchwu. */
a750fc0b 5389GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5390/* mulhhw - mulhhw. */
a750fc0b 5391GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5392/* mulhhwu - mulhhwu. */
a750fc0b 5393GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5394/* mullhw - mullhw. */
a750fc0b 5395GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5396/* mullhwu - mullhwu. */
a750fc0b 5397GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5398
5399/* mfdcr */
05332d70 5400GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5401{
5402#if defined(CONFIG_USER_ONLY)
e1833e1f 5403 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5404#else
5405 uint32_t dcrn = SPR(ctx->opcode);
5406
5407 if (unlikely(!ctx->supervisor)) {
e1833e1f 5408 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5409 return;
5410 }
86c581dc 5411 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5412 gen_op_load_dcr();
f78fb44e 5413 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5414#endif
5415}
5416
5417/* mtdcr */
05332d70 5418GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5419{
5420#if defined(CONFIG_USER_ONLY)
e1833e1f 5421 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5422#else
5423 uint32_t dcrn = SPR(ctx->opcode);
5424
5425 if (unlikely(!ctx->supervisor)) {
e1833e1f 5426 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5427 return;
5428 }
86c581dc 5429 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5430 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5431 gen_op_store_dcr();
5432#endif
5433}
5434
5435/* mfdcrx */
2662a059 5436/* XXX: not implemented on 440 ? */
05332d70 5437GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5438{
5439#if defined(CONFIG_USER_ONLY)
e1833e1f 5440 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5441#else
5442 if (unlikely(!ctx->supervisor)) {
e1833e1f 5443 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5444 return;
5445 }
f78fb44e 5446 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5447 gen_op_load_dcr();
f78fb44e 5448 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5449 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5450#endif
5451}
5452
5453/* mtdcrx */
2662a059 5454/* XXX: not implemented on 440 ? */
05332d70 5455GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5456{
5457#if defined(CONFIG_USER_ONLY)
e1833e1f 5458 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5459#else
5460 if (unlikely(!ctx->supervisor)) {
e1833e1f 5461 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5462 return;
5463 }
f78fb44e
AJ		 5464 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5465 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5466 gen_op_store_dcr();
a750fc0b 5467 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5468#endif
5469}
5470
a750fc0b
JM		 5471/* mfdcrux (PPC 460) : user-mode access to DCR */
5472GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5473{
f78fb44e 5474 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5475 gen_op_load_dcr();
f78fb44e 5476 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5477 /* Note: Rc update flag set leads to undefined state of Rc0 */
5478}
5479
5480/* mtdcrux (PPC 460) : user-mode access to DCR */
5481GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5482{
f78fb44e
AJ		 5483 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5484 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5485 gen_op_store_dcr();
5486 /* Note: Rc update flag set leads to undefined state of Rc0 */
5487}
5488
76a66253
JM		 5489/* dccci */
5490GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5491{
5492#if defined(CONFIG_USER_ONLY)
e1833e1f 5493 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5494#else
5495 if (unlikely(!ctx->supervisor)) {
e1833e1f 5496 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5497 return;
5498 }
5499 /* interpreted as no-op */
5500#endif
5501}
5502
5503/* dcread */
5504GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5505{
5506#if defined(CONFIG_USER_ONLY)
e1833e1f 5507 GEN_EXCP_PRIVOPC(ctx);
76a66253 5508#else
b61f2753 5509 TCGv EA, val;
76a66253 5510 if (unlikely(!ctx->supervisor)) {
e1833e1f 5511 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5512 return;
5513 }
a7812ae4 5514 EA = tcg_temp_new();
b61f2753 5515 gen_addr_reg_index(EA, ctx);
a7812ae4 5516 val = tcg_temp_new();
b61f2753
AJ		 5517 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5518 tcg_temp_free(val);
5519 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5520 tcg_temp_free(EA);
76a66253
JM		 5521#endif
5522}
5523
5524/* icbt */
c7697e1f 5525GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5526{
5527 /* interpreted as no-op */
5528 /* XXX: specification say this is treated as a load by the MMU
5529 * but does not generate any exception
5530 */
5531}
5532
5533/* iccci */
5534GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5535{
5536#if defined(CONFIG_USER_ONLY)
e1833e1f 5537 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5538#else
5539 if (unlikely(!ctx->supervisor)) {
e1833e1f 5540 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5541 return;
5542 }
5543 /* interpreted as no-op */
5544#endif
5545}
5546
5547/* icread */
5548GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5549{
5550#if defined(CONFIG_USER_ONLY)
e1833e1f 5551 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5552#else
5553 if (unlikely(!ctx->supervisor)) {
e1833e1f 5554 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5555 return;
5556 }
5557 /* interpreted as no-op */
5558#endif
5559}
5560
5561/* rfci (supervisor only) */
c7697e1f 5562GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5563{
5564#if defined(CONFIG_USER_ONLY)
e1833e1f 5565 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5566#else
5567 if (unlikely(!ctx->supervisor)) {
e1833e1f 5568 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5569 return;
5570 }
5571 /* Restore CPU state */
5572 gen_op_40x_rfci();
e1833e1f 5573 GEN_SYNC(ctx);
a42bd6cc
JM		 5574#endif
5575}
5576
5577GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5578{
5579#if defined(CONFIG_USER_ONLY)
e1833e1f 5580 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5581#else
5582 if (unlikely(!ctx->supervisor)) {
e1833e1f 5583 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5584 return;
5585 }
5586 /* Restore CPU state */
5587 gen_op_rfci();
e1833e1f 5588 GEN_SYNC(ctx);
a42bd6cc
JM		 5589#endif
5590}
5591
5592/* BookE specific */
2662a059 5593/* XXX: not implemented on 440 ? */
05332d70 5594GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5595{
5596#if defined(CONFIG_USER_ONLY)
e1833e1f 5597 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5598#else
5599 if (unlikely(!ctx->supervisor)) {
e1833e1f 5600 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5601 return;
5602 }
5603 /* Restore CPU state */
a42bd6cc 5604 gen_op_rfdi();
e1833e1f 5605 GEN_SYNC(ctx);
76a66253
JM		 5606#endif
5607}
5608
2662a059 5609/* XXX: not implemented on 440 ? */
a750fc0b 5610GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5611{
5612#if defined(CONFIG_USER_ONLY)
e1833e1f 5613 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5614#else
5615 if (unlikely(!ctx->supervisor)) {
e1833e1f 5616 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5617 return;
5618 }
5619 /* Restore CPU state */
5620 gen_op_rfmci();
e1833e1f 5621 GEN_SYNC(ctx);
a42bd6cc
JM		 5622#endif
5623}
5eb7995e 5624
d9bce9d9 5625/* TLB management - PowerPC 405 implementation */
76a66253 5626/* tlbre */
c7697e1f 5627GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5628{
5629#if defined(CONFIG_USER_ONLY)
e1833e1f 5630 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5631#else
5632 if (unlikely(!ctx->supervisor)) {
e1833e1f 5633 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5634 return;
5635 }
5636 switch (rB(ctx->opcode)) {
5637 case 0:
f78fb44e 5638 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5639 gen_op_4xx_tlbre_hi();
f78fb44e 5640 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5641 break;
5642 case 1:
f78fb44e 5643 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5644 gen_op_4xx_tlbre_lo();
f78fb44e 5645 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5646 break;
5647 default:
e1833e1f 5648 GEN_EXCP_INVAL(ctx);
76a66253 5649 break;
9a64fbe4 5650 }
76a66253
JM		 5651#endif
5652}
5653
d9bce9d9 5654/* tlbsx - tlbsx. */
c7697e1f 5655GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5656{
5657#if defined(CONFIG_USER_ONLY)
e1833e1f 5658 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5659#else
5660 if (unlikely(!ctx->supervisor)) {
e1833e1f 5661 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5662 return;
5663 }
e2be8d8d 5664 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5665 gen_op_4xx_tlbsx();
76a66253 5666 if (Rc(ctx->opcode))
daf4f96e 5667 gen_op_4xx_tlbsx_check();
f78fb44e 5668 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5669#endif
79aceca5
FB		 5670}
5671
76a66253 5672/* tlbwe */
c7697e1f 5673GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5674{
76a66253 5675#if defined(CONFIG_USER_ONLY)
e1833e1f 5676 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5677#else
5678 if (unlikely(!ctx->supervisor)) {
e1833e1f 5679 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5680 return;
5681 }
5682 switch (rB(ctx->opcode)) {
5683 case 0:
f78fb44e
AJ		 5684 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5685 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5686 gen_op_4xx_tlbwe_hi();
5687 break;
5688 case 1:
f78fb44e
AJ		 5689 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5690 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5691 gen_op_4xx_tlbwe_lo();
5692 break;
5693 default:
e1833e1f 5694 GEN_EXCP_INVAL(ctx);
76a66253 5695 break;
9a64fbe4 5696 }
76a66253
JM		 5697#endif
5698}
5699
a4bb6c3e 5700/* TLB management - PowerPC 440 implementation */
5eb7995e 5701/* tlbre */
c7697e1f 5702GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5703{
5704#if defined(CONFIG_USER_ONLY)
e1833e1f 5705 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5706#else
5707 if (unlikely(!ctx->supervisor)) {
e1833e1f 5708 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5709 return;
5710 }
5711 switch (rB(ctx->opcode)) {
5712 case 0:
5eb7995e 5713 case 1:
5eb7995e 5714 case 2:
f78fb44e 5715 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5716 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5717 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5718 break;
5719 default:
e1833e1f 5720 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5721 break;
5722 }
5723#endif
5724}
5725
5726/* tlbsx - tlbsx. */
c7697e1f 5727GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5728{
5729#if defined(CONFIG_USER_ONLY)
e1833e1f 5730 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5731#else
5732 if (unlikely(!ctx->supervisor)) {
e1833e1f 5733 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5734 return;
5735 }
e2be8d8d 5736 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5737 gen_op_440_tlbsx();
5eb7995e 5738 if (Rc(ctx->opcode))
daf4f96e 5739 gen_op_4xx_tlbsx_check();
f78fb44e 5740 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5741#endif
5742}
5743
5744/* tlbwe */
c7697e1f 5745GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5746{
5747#if defined(CONFIG_USER_ONLY)
e1833e1f 5748 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5749#else
5750 if (unlikely(!ctx->supervisor)) {
e1833e1f 5751 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5752 return;
5753 }
5754 switch (rB(ctx->opcode)) {
5755 case 0:
5eb7995e 5756 case 1:
5eb7995e 5757 case 2:
f78fb44e
AJ		 5758 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5759 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5760 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5761 break;
5762 default:
e1833e1f 5763 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5764 break;
5765 }
5766#endif
5767}
5768
76a66253 5769/* wrtee */
05332d70 5770GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5771{
5772#if defined(CONFIG_USER_ONLY)
e1833e1f 5773 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5774#else
5775 if (unlikely(!ctx->supervisor)) {
e1833e1f 5776 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5777 return;
5778 }
f78fb44e 5779 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5780 gen_op_wrte();
dee96f6c
JM		 5781 /* Stop translation to have a chance to raise an exception
5782 * if we just set msr_ee to 1
5783 */
e1833e1f 5784 GEN_STOP(ctx);
76a66253
JM		 5785#endif
5786}
5787
5788/* wrteei */
05332d70 5789GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5790{
5791#if defined(CONFIG_USER_ONLY)
e1833e1f 5792 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5793#else
5794 if (unlikely(!ctx->supervisor)) {
e1833e1f 5795 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5796 return;
5797 }
86c581dc 5798 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5799 gen_op_wrte();
dee96f6c
JM		 5800 /* Stop translation to have a chance to raise an exception
5801 * if we just set msr_ee to 1
5802 */
e1833e1f 5803 GEN_STOP(ctx);
76a66253
JM		 5804#endif
5805}
5806
08e46e54 5807/* PowerPC 440 specific instructions */
76a66253
JM		 5808/* dlmzb */
5809GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5810{
f78fb44e
AJ		 5811 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5812 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5813 gen_op_440_dlmzb();
f78fb44e 5814 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5815 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5816 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5817 if (Rc(ctx->opcode)) {
5818 gen_op_440_dlmzb_update_Rc();
a7812ae4
PB		 5819 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_T[0]);
5820 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 0xf);
76a66253
JM		 5821 }
5822}
5823
5824/* mbar replaces eieio on 440 */
5825GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5826{
5827 /* interpreted as no-op */
5828}
5829
5830/* msync replaces sync on 440 */
0db1b20e 5831GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5832{
5833 /* interpreted as no-op */
5834}
5835
5836/* icbt */
c7697e1f 5837GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5838{
5839 /* interpreted as no-op */
5840 /* XXX: specification say this is treated as a load by the MMU
5841 * but does not generate any exception
5842 */
79aceca5
FB		 5843}
5844
a9d9eb8f
JM		 5845/*** Altivec vector extension ***/
5846/* Altivec registers moves */
a9d9eb8f 5847
1d542695
AJ		 5848static always_inline void gen_load_avr(int t, int reg) {
5849 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5850 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5851}
5852
5853static always_inline void gen_store_avr(int reg, int t) {
5854 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5855 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5856}
a9d9eb8f
JM		 5857
5858#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5859#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5860static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5861 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5862};
5863#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5864static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5865 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5866};
a9d9eb8f
JM		 5867
5868#define GEN_VR_LDX(name, opc2, opc3) \
5869GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5870{ \
5871 if (unlikely(!ctx->altivec_enabled)) { \
5872 GEN_EXCP_NO_VR(ctx); \
5873 return; \
5874 } \
e2be8d8d 5875 gen_addr_reg_index(cpu_T[0], ctx); \
a9d9eb8f 5876 op_vr_ldst(vr_l##name); \
1d542695 5877 gen_store_avr(rD(ctx->opcode), 0); \
a9d9eb8f
JM		 5878}
5879
5880#define GEN_VR_STX(name, opc2, opc3) \
5881GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5882{ \
5883 if (unlikely(!ctx->altivec_enabled)) { \
5884 GEN_EXCP_NO_VR(ctx); \
5885 return; \
5886 } \
e2be8d8d 5887 gen_addr_reg_index(cpu_T[0], ctx); \
1d542695 5888 gen_load_avr(0, rS(ctx->opcode)); \
a9d9eb8f
JM		 5889 op_vr_ldst(vr_st##name); \
5890}
5891
5892OP_VR_LD_TABLE(vx);
5893GEN_VR_LDX(vx, 0x07, 0x03);
5894/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5895#define gen_op_vr_lvxl gen_op_vr_lvx
5896GEN_VR_LDX(vxl, 0x07, 0x0B);
5897
5898OP_VR_ST_TABLE(vx);
5899GEN_VR_STX(vx, 0x07, 0x07);
5900/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5901#define gen_op_vr_stvxl gen_op_vr_stvx
5902GEN_VR_STX(vxl, 0x07, 0x0F);
5903
0487d6a8 5904/*** SPE extension ***/
0487d6a8 5905/* Register moves */
3cd7d1dd 5906
a7812ae4 5907static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 5908#if defined(TARGET_PPC64)
5909 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5910#else
36aa55dc 5911 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5912#endif
f78fb44e 5913}
3cd7d1dd 5914
a7812ae4 5915static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 5916#if defined(TARGET_PPC64)
5917 tcg_gen_mov_i64(cpu_gpr[reg], t);
5918#else
a7812ae4 5919 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 5920 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 5921 tcg_gen_shri_i64(tmp, t, 32);
5922 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 5923 tcg_temp_free_i64(tmp);
3cd7d1dd 5924#endif
f78fb44e 5925}
3cd7d1dd 5926
0487d6a8
JM		 5927#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5928GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5929{ \
5930 if (Rc(ctx->opcode)) \
5931 gen_##name1(ctx); \
5932 else \
5933 gen_##name0(ctx); \
5934}
5935
5936/* Handler for undefined SPE opcodes */
b068d6a7 5937static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5938{
e1833e1f 5939 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5940}
5941
5942/* SPE load and stores */
f0aabd1a 5943static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
0487d6a8
JM		 5944{
5945 target_long simm = rB(ctx->opcode);
5946
f0aabd1a
AJ		 5947 if (rA(ctx->opcode) == 0)
5948 tcg_gen_movi_tl(EA, simm << sh);
5949 else if (likely(simm != 0))
5950 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5951 else
5952 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
0487d6a8
JM		 5953}
5954
5955#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5956#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5957static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5958 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5959};
5960#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5961static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5962 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5963};
0487d6a8
JM		 5964
5965#define GEN_SPE_LD(name, sh) \
b068d6a7 5966static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5967{ \
5968 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5969 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5970 return; \
5971 } \
f0aabd1a 5972 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
0487d6a8 5973 op_spe_ldst(spe_l##name); \
f78fb44e 5974 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5975}
5976
5977#define GEN_SPE_LDX(name) \
b068d6a7 5978static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 5979{ \
5980 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5981 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5982 return; \
5983 } \
e2be8d8d 5984 gen_addr_reg_index(cpu_T[0], ctx); \
0487d6a8 5985 op_spe_ldst(spe_l##name); \
f78fb44e 5986 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5987}
5988
5989#define GEN_SPEOP_LD(name, sh) \
5990OP_SPE_LD_TABLE(name); \
5991GEN_SPE_LD(name, sh); \
5992GEN_SPE_LDX(name)
5993
5994#define GEN_SPE_ST(name, sh) \
b068d6a7 5995static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 5996{ \
5997 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5998 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5999 return; \
6000 } \
f0aabd1a 6001 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
f78fb44e 6002 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 6003 op_spe_ldst(spe_st##name); \
6004}
6005
6006#define GEN_SPE_STX(name) \
b068d6a7 6007static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 6008{ \
6009 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6010 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6011 return; \
6012 } \
e2be8d8d 6013 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 6014 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 6015 op_spe_ldst(spe_st##name); \
6016}
6017
6018#define GEN_SPEOP_ST(name, sh) \
6019OP_SPE_ST_TABLE(name); \
6020GEN_SPE_ST(name, sh); \
6021GEN_SPE_STX(name)
6022
6023#define GEN_SPEOP_LDST(name, sh) \
6024GEN_SPEOP_LD(name, sh); \
6025GEN_SPEOP_ST(name, sh)
6026
57951c27
AJ		 6027/* SPE logic */
6028#if defined(TARGET_PPC64)
6029#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6030static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6031{ \
6032 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6033 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6034 return; \
6035 } \
57951c27
AJ		 6036 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6037 cpu_gpr[rB(ctx->opcode)]); \
6038}
6039#else
6040#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6041static always_inline void gen_##name (DisasContext *ctx) \
6042{ \
6043 if (unlikely(!ctx->spe_enabled)) { \
6044 GEN_EXCP_NO_AP(ctx); \
6045 return; \
6046 } \
6047 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6048 cpu_gpr[rB(ctx->opcode)]); \
6049 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6050 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6051}
57951c27
AJ		 6052#endif
6053
6054GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6055GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6056GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6057GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6058GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6059GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6060GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6061GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6062
57951c27
AJ		 6063/* SPE logic immediate */
6064#if defined(TARGET_PPC64)
6065#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6066static always_inline void gen_##name (DisasContext *ctx) \
6067{ \
6068 if (unlikely(!ctx->spe_enabled)) { \
6069 GEN_EXCP_NO_AP(ctx); \
6070 return; \
6071 } \
a7812ae4
PB		 6072 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6073 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6074 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6075 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6076 tcg_opi(t0, t0, rB(ctx->opcode)); \
6077 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6078 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6079 tcg_temp_free_i64(t2); \
57951c27
AJ		 6080 tcg_opi(t1, t1, rB(ctx->opcode)); \
6081 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6082 tcg_temp_free_i32(t0); \
6083 tcg_temp_free_i32(t1); \
3d3a6a0a 6084}
57951c27
AJ		 6085#else
6086#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6087static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6088{ \
6089 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6090 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6091 return; \
6092 } \
57951c27
AJ		 6093 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6094 rB(ctx->opcode)); \
6095 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6096 rB(ctx->opcode)); \
0487d6a8 6097}
57951c27
AJ		 6098#endif
6099GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6100GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6101GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6102GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6103
57951c27
AJ		 6104/* SPE arithmetic */
6105#if defined(TARGET_PPC64)
6106#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6107static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6108{ \
6109 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6110 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6111 return; \
6112 } \
a7812ae4
PB		 6113 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6114 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6115 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6116 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6117 tcg_op(t0, t0); \
6118 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6119 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6120 tcg_temp_free_i64(t2); \
57951c27
AJ		 6121 tcg_op(t1, t1); \
6122 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6123 tcg_temp_free_i32(t0); \
6124 tcg_temp_free_i32(t1); \
0487d6a8 6125}
57951c27 6126#else
a7812ae4 6127#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6128static always_inline void gen_##name (DisasContext *ctx) \
6129{ \
6130 if (unlikely(!ctx->spe_enabled)) { \
6131 GEN_EXCP_NO_AP(ctx); \
6132 return; \
6133 } \
6134 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6135 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6136}
6137#endif
0487d6a8 6138
a7812ae4 6139static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6140{
6141 int l1 = gen_new_label();
6142 int l2 = gen_new_label();
0487d6a8 6143
57951c27
AJ		 6144 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6145 tcg_gen_neg_i32(ret, arg1);
6146 tcg_gen_br(l2);
6147 gen_set_label(l1);
a7812ae4 6148 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6149 gen_set_label(l2);
6150}
6151GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6152GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6153GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6154GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6155static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6156{
57951c27
AJ		 6157 tcg_gen_addi_i32(ret, arg1, 0x8000);
6158 tcg_gen_ext16u_i32(ret, ret);
6159}
6160GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6161GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6162GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6163
57951c27
AJ		 6164#if defined(TARGET_PPC64)
6165#define GEN_SPEOP_ARITH2(name, tcg_op) \
6166static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6167{ \
6168 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6169 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6170 return; \
6171 } \
a7812ae4
PB		 6172 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6173 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6174 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6175 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
57951c27
AJ		 6176 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6177 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6178 tcg_op(t0, t0, t2); \
6179 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6180 tcg_gen_trunc_i64_i32(t1, t3); \
6181 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6182 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6183 tcg_temp_free_i64(t3); \
57951c27 6184 tcg_op(t1, t1, t2); \
a7812ae4 6185 tcg_temp_free_i32(t2); \
57951c27 6186 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6187 tcg_temp_free_i32(t0); \
6188 tcg_temp_free_i32(t1); \
0487d6a8 6189}
57951c27
AJ		 6190#else
6191#define GEN_SPEOP_ARITH2(name, tcg_op) \
6192static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6193{ \
6194 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6195 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6196 return; \
6197 } \
57951c27
AJ		 6198 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6199 cpu_gpr[rB(ctx->opcode)]); \
6200 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6201 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6202}
57951c27 6203#endif
0487d6a8 6204
a7812ae4 6205static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6206{
a7812ae4 6207 TCGv_i32 t0;
57951c27 6208 int l1, l2;
0487d6a8 6209
57951c27
AJ		 6210 l1 = gen_new_label();
6211 l2 = gen_new_label();
a7812ae4 6212 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6213 /* No error here: 6 bits are used */
6214 tcg_gen_andi_i32(t0, arg2, 0x3F);
6215 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6216 tcg_gen_shr_i32(ret, arg1, t0);
6217 tcg_gen_br(l2);
6218 gen_set_label(l1);
6219 tcg_gen_movi_i32(ret, 0);
6220 tcg_gen_br(l2);
a7812ae4 6221 tcg_temp_free_i32(t0);
57951c27
AJ		 6222}
6223GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6224static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6225{
a7812ae4 6226 TCGv_i32 t0;
57951c27
AJ		 6227 int l1, l2;
6228
6229 l1 = gen_new_label();
6230 l2 = gen_new_label();
a7812ae4 6231 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6232 /* No error here: 6 bits are used */
6233 tcg_gen_andi_i32(t0, arg2, 0x3F);
6234 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6235 tcg_gen_sar_i32(ret, arg1, t0);
6236 tcg_gen_br(l2);
6237 gen_set_label(l1);
6238 tcg_gen_movi_i32(ret, 0);
6239 tcg_gen_br(l2);
a7812ae4 6240 tcg_temp_free_i32(t0);
57951c27
AJ		 6241}
6242GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6243static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6244{
a7812ae4 6245 TCGv_i32 t0;
57951c27
AJ		 6246 int l1, l2;
6247
6248 l1 = gen_new_label();
6249 l2 = gen_new_label();
a7812ae4 6250 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6251 /* No error here: 6 bits are used */
6252 tcg_gen_andi_i32(t0, arg2, 0x3F);
6253 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6254 tcg_gen_shl_i32(ret, arg1, t0);
6255 tcg_gen_br(l2);
6256 gen_set_label(l1);
6257 tcg_gen_movi_i32(ret, 0);
6258 tcg_gen_br(l2);
a7812ae4 6259 tcg_temp_free_i32(t0);
57951c27
AJ		 6260}
6261GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6262static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6263{
a7812ae4 6264 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6265 tcg_gen_andi_i32(t0, arg2, 0x1F);
6266 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6267 tcg_temp_free_i32(t0);
57951c27
AJ		 6268}
6269GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6270static always_inline void gen_evmergehi (DisasContext *ctx)
6271{
6272 if (unlikely(!ctx->spe_enabled)) {
6273 GEN_EXCP_NO_AP(ctx);
6274 return;
6275 }
6276#if defined(TARGET_PPC64)
a7812ae4
PB		 6277 TCGv t0 = tcg_temp_new();
6278 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6279 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6280 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6281 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6282 tcg_temp_free(t0);
6283 tcg_temp_free(t1);
6284#else
6285 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6286 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6287#endif
6288}
6289GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6290static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6291{
57951c27
AJ		 6292 tcg_gen_sub_i32(ret, arg2, arg1);
6293}
6294GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6295
57951c27
AJ		 6296/* SPE arithmetic immediate */
6297#if defined(TARGET_PPC64)
6298#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6299static always_inline void gen_##name (DisasContext *ctx) \
6300{ \
6301 if (unlikely(!ctx->spe_enabled)) { \
6302 GEN_EXCP_NO_AP(ctx); \
6303 return; \
6304 } \
a7812ae4
PB		 6305 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6306 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6307 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6308 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6309 tcg_op(t0, t0, rA(ctx->opcode)); \
6310 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6311 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6312 tcg_temp_free_i64(t2); \
57951c27
AJ		 6313 tcg_op(t1, t1, rA(ctx->opcode)); \
6314 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6315 tcg_temp_free_i32(t0); \
6316 tcg_temp_free_i32(t1); \
57951c27
AJ		 6317}
6318#else
6319#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6320static always_inline void gen_##name (DisasContext *ctx) \
6321{ \
6322 if (unlikely(!ctx->spe_enabled)) { \
6323 GEN_EXCP_NO_AP(ctx); \
6324 return; \
6325 } \
6326 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6327 rA(ctx->opcode)); \
6328 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6329 rA(ctx->opcode)); \
6330}
6331#endif
6332GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6333GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6334
6335/* SPE comparison */
6336#if defined(TARGET_PPC64)
6337#define GEN_SPEOP_COMP(name, tcg_cond) \
6338static always_inline void gen_##name (DisasContext *ctx) \
6339{ \
6340 if (unlikely(!ctx->spe_enabled)) { \
6341 GEN_EXCP_NO_AP(ctx); \
6342 return; \
6343 } \
6344 int l1 = gen_new_label(); \
6345 int l2 = gen_new_label(); \
6346 int l3 = gen_new_label(); \
6347 int l4 = gen_new_label(); \
a7812ae4
PB		 6348 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6349 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6350 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6351 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6352 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6353 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6354 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6355 tcg_gen_br(l2); \
6356 gen_set_label(l1); \
6357 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6358 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6359 gen_set_label(l2); \
6360 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6361 tcg_gen_trunc_i64_i32(t0, t2); \
6362 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6363 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6364 tcg_temp_free_i64(t2); \
57951c27
AJ		 6365 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6366 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6367 ~(CRF_CH | CRF_CH_AND_CL)); \
6368 tcg_gen_br(l4); \
6369 gen_set_label(l3); \
6370 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6371 CRF_CH | CRF_CH_OR_CL); \
6372 gen_set_label(l4); \
a7812ae4
PB		 6373 tcg_temp_free_i32(t0); \
6374 tcg_temp_free_i32(t1); \
57951c27
AJ		 6375}
6376#else
6377#define GEN_SPEOP_COMP(name, tcg_cond) \
6378static always_inline void gen_##name (DisasContext *ctx) \
6379{ \
6380 if (unlikely(!ctx->spe_enabled)) { \
6381 GEN_EXCP_NO_AP(ctx); \
6382 return; \
6383 } \
6384 int l1 = gen_new_label(); \
6385 int l2 = gen_new_label(); \
6386 int l3 = gen_new_label(); \
6387 int l4 = gen_new_label(); \
6388 \
6389 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6390 cpu_gpr[rB(ctx->opcode)], l1); \
6391 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6392 tcg_gen_br(l2); \
6393 gen_set_label(l1); \
6394 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6395 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6396 gen_set_label(l2); \
6397 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6398 cpu_gprh[rB(ctx->opcode)], l3); \
6399 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6400 ~(CRF_CH | CRF_CH_AND_CL)); \
6401 tcg_gen_br(l4); \
6402 gen_set_label(l3); \
6403 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6404 CRF_CH | CRF_CH_OR_CL); \
6405 gen_set_label(l4); \
6406}
6407#endif
6408GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6409GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6410GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6411GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6412GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6413
6414/* SPE misc */
6415static always_inline void gen_brinc (DisasContext *ctx)
6416{
6417 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6418 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6419 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6420}
57951c27
AJ		 6421static always_inline void gen_evmergelo (DisasContext *ctx)
6422{
6423 if (unlikely(!ctx->spe_enabled)) {
6424 GEN_EXCP_NO_AP(ctx);
6425 return;
6426 }
6427#if defined(TARGET_PPC64)
a7812ae4
PB		 6428 TCGv t0 = tcg_temp_new();
6429 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6430 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6431 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6432 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6433 tcg_temp_free(t0);
6434 tcg_temp_free(t1);
6435#else
6436 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6437 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6438#endif
6439}
6440static always_inline void gen_evmergehilo (DisasContext *ctx)
6441{
6442 if (unlikely(!ctx->spe_enabled)) {
6443 GEN_EXCP_NO_AP(ctx);
6444 return;
6445 }
6446#if defined(TARGET_PPC64)
a7812ae4
PB		 6447 TCGv t0 = tcg_temp_new();
6448 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6449 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6450 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6451 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6452 tcg_temp_free(t0);
6453 tcg_temp_free(t1);
6454#else
6455 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6456 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6457#endif
6458}
6459static always_inline void gen_evmergelohi (DisasContext *ctx)
6460{
6461 if (unlikely(!ctx->spe_enabled)) {
6462 GEN_EXCP_NO_AP(ctx);
6463 return;
6464 }
6465#if defined(TARGET_PPC64)
a7812ae4
PB		 6466 TCGv t0 = tcg_temp_new();
6467 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6468 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6469 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6470 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6471 tcg_temp_free(t0);
6472 tcg_temp_free(t1);
6473#else
6474 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6475 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6476#endif
6477}
6478static always_inline void gen_evsplati (DisasContext *ctx)
6479{
6480 int32_t imm = (int32_t)(rA(ctx->opcode) << 11) >> 27;
0487d6a8 6481
57951c27 6482#if defined(TARGET_PPC64)
a7812ae4
PB		 6483 TCGv t0 = tcg_temp_new();
6484 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6485 tcg_gen_movi_tl(t0, imm);
6486 tcg_gen_shri_tl(t1, t0, 32);
6487 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6488 tcg_temp_free(t0);
6489 tcg_temp_free(t1);
6490#else
6491 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6492 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6493#endif
6494}
b068d6a7 6495static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 6496{
57951c27 6497 uint32_t imm = rA(ctx->opcode) << 11;
0487d6a8 6498
57951c27 6499#if defined(TARGET_PPC64)
a7812ae4
PB		 6500 TCGv t0 = tcg_temp_new();
6501 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6502 tcg_gen_movi_tl(t0, imm);
6503 tcg_gen_shri_tl(t1, t0, 32);
6504 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6505 tcg_temp_free(t0);
6506 tcg_temp_free(t1);
6507#else
6508 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6509 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6510#endif
0487d6a8
JM		 6511}
6512
57951c27
AJ		 6513static always_inline void gen_evsel (DisasContext *ctx)
6514{
6515 int l1 = gen_new_label();
6516 int l2 = gen_new_label();
6517 int l3 = gen_new_label();
6518 int l4 = gen_new_label();
a7812ae4 6519 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 6520#if defined(TARGET_PPC64)
a7812ae4
PB		 6521 TCGv t1 = tcg_temp_local_new();
6522 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 6523#endif
6524 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6525 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6526#if defined(TARGET_PPC64)
6527 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6528#else
6529 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6530#endif
6531 tcg_gen_br(l2);
6532 gen_set_label(l1);
6533#if defined(TARGET_PPC64)
6534 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6535#else
6536 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6537#endif
6538 gen_set_label(l2);
6539 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6540 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6541#if defined(TARGET_PPC64)
6542 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6543#else
6544 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6545#endif
6546 tcg_gen_br(l4);
6547 gen_set_label(l3);
6548#if defined(TARGET_PPC64)
6549 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6550#else
6551 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6552#endif
6553 gen_set_label(l4);
a7812ae4 6554 tcg_temp_free_i32(t0);
57951c27
AJ		 6555#if defined(TARGET_PPC64)
6556 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6557 tcg_temp_free(t1);
6558 tcg_temp_free(t2);
6559#endif
6560}
6561GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6562{
6563 gen_evsel(ctx);
6564}
6565GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6566{
6567 gen_evsel(ctx);
6568}
6569GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6570{
6571 gen_evsel(ctx);
6572}
6573GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6574{
6575 gen_evsel(ctx);
6576}
0487d6a8
JM		 6577
6578GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6579GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6580GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6581GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6582GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6583GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6584GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6585GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6586GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6587GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6588GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6589GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6590GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6591GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6592GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6593GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6594GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6595GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6596GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6597GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6598GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6599GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6600GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6601GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6602GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6603
0487d6a8 6604/* Load and stores */
0487d6a8
JM		 6605GEN_SPEOP_LDST(dd, 3);
6606GEN_SPEOP_LDST(dw, 3);
6607GEN_SPEOP_LDST(dh, 3);
6608GEN_SPEOP_LDST(whe, 2);
6609GEN_SPEOP_LD(whou, 2);
6610GEN_SPEOP_LD(whos, 2);
6611GEN_SPEOP_ST(who, 2);
6612
0487d6a8 6613#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 6614static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 6615{ \
6616 gen_op_srli32_T1_64(); \
6617 gen_op_spe_stwwo_##suffix(); \
6618}
6619#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 6620static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 6621{ \
6622 gen_op_srli32_T1_64(); \
6623 gen_op_spe_stwwo_le_##suffix(); \
6624}
6625#if defined(TARGET_PPC64)
6626#define GEN_OP_SPE_STWWE(suffix) \
6627_GEN_OP_SPE_STWWE(suffix); \
6628_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 6629static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 6630{ \
6631 gen_op_srli32_T1_64(); \
6632 gen_op_spe_stwwo_64_##suffix(); \
6633} \
b068d6a7 6634static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 6635{ \
6636 gen_op_srli32_T1_64(); \
6637 gen_op_spe_stwwo_le_64_##suffix(); \
6638}
6639#else
6640#define GEN_OP_SPE_STWWE(suffix) \
6641_GEN_OP_SPE_STWWE(suffix); \
6642_GEN_OP_SPE_STWWE_LE(suffix)
6643#endif
6644#if defined(CONFIG_USER_ONLY)
6645GEN_OP_SPE_STWWE(raw);
6646#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 6647GEN_OP_SPE_STWWE(user);
7863667f
JM		 6648GEN_OP_SPE_STWWE(kernel);
6649GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 6650#endif /* defined(CONFIG_USER_ONLY) */
6651GEN_SPEOP_ST(wwe, 2);
6652GEN_SPEOP_ST(wwo, 2);
6653
6654#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 6655static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 6656{ \
6657 gen_op_##op##_##suffix(); \
6658 gen_op_splatw_T1_64(); \
6659}
6660
6661#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 6662static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 6663{ \
6664 gen_op_spe_lh_##suffix(); \
6665 gen_op_sli16_T1_64(); \
6666}
6667
6668#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 6669static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 6670{ \
6671 gen_op_spe_lh_##suffix(); \
6672 gen_op_extsh_T1_64(); \
6673}
6674
6675#if defined(CONFIG_USER_ONLY)
6676GEN_OP_SPE_LHE(raw);
6677GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6678GEN_OP_SPE_LHE(le_raw);
6679GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6680GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6681GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6682GEN_OP_SPE_LHX(raw);
6683GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6684GEN_OP_SPE_LHX(le_raw);
6685GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6686#if defined(TARGET_PPC64)
6687GEN_OP_SPE_LHE(64_raw);
6688GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6689GEN_OP_SPE_LHE(le_64_raw);
6690GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6691GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6692GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6693GEN_OP_SPE_LHX(64_raw);
6694GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6695GEN_OP_SPE_LHX(le_64_raw);
6696GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6697#endif
6698#else
0487d6a8 6699GEN_OP_SPE_LHE(user);
7863667f
JM		 6700GEN_OP_SPE_LHE(kernel);
6701GEN_OP_SPE_LHE(hypv);
0487d6a8 6702GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 6703GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6704GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 6705GEN_OP_SPE_LHE(le_user);
7863667f
JM		 6706GEN_OP_SPE_LHE(le_kernel);
6707GEN_OP_SPE_LHE(le_hypv);
0487d6a8 6708GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 6709GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6710GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 6711GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 6712GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6713GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 6714GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 6715GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6716GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 6717GEN_OP_SPE_LHX(user);
7863667f
JM		 6718GEN_OP_SPE_LHX(kernel);
6719GEN_OP_SPE_LHX(hypv);
0487d6a8 6720GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 6721GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6722GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 6723GEN_OP_SPE_LHX(le_user);
7863667f
JM		 6724GEN_OP_SPE_LHX(le_kernel);
6725GEN_OP_SPE_LHX(le_hypv);
0487d6a8 6726GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 6727GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6728GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 6729#if defined(TARGET_PPC64)
0487d6a8 6730GEN_OP_SPE_LHE(64_user);
7863667f
JM		 6731GEN_OP_SPE_LHE(64_kernel);
6732GEN_OP_SPE_LHE(64_hypv);
0487d6a8 6733GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 6734GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6735GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 6736GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 6737GEN_OP_SPE_LHE(le_64_kernel);
6738GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 6739GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 6740GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6741GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 6742GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 6743GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6744GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 6745GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 6746GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6747GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 6748GEN_OP_SPE_LHX(64_user);
7863667f
JM		 6749GEN_OP_SPE_LHX(64_kernel);
6750GEN_OP_SPE_LHX(64_hypv);
0487d6a8 6751GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 6752GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6753GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 6754GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 6755GEN_OP_SPE_LHX(le_64_kernel);
6756GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 6757GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 6758GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6759GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 6760#endif
6761#endif
6762GEN_SPEOP_LD(hhesplat, 1);
6763GEN_SPEOP_LD(hhousplat, 1);
6764GEN_SPEOP_LD(hhossplat, 1);
6765GEN_SPEOP_LD(wwsplat, 2);
6766GEN_SPEOP_LD(whsplat, 2);
6767
6768GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6769GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6770GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6771GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6772GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6773GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6774GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6775GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6776GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6777GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6778GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6779GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6780GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6781GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6782GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6783GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6784GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6785GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6786
6787/* Multiply and add - TODO */
6788#if 0
6789GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6790GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6791GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6792GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6793GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6794GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6795GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6796GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6797GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6798GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6799GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6800GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6801
6802GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6803GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6804GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6805GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6806GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6807GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6808GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6809GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6810GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6811GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6812GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6813GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6814GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6815GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6816
6817GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6818GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6819GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6820GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6821GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6822GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6823
6824GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6825GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6826GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6827GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6828GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6829GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6830GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6831GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6832GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6833GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6834GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6835GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6836
6837GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6838GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6839GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6840GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6841GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6842
6843GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6844GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6845GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6846GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6847GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6848GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6849GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6850GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6851GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6852GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6853GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6854GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6855
6856GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6857GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6858GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6859GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6860GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6861#endif
6862
6863/*** SPE floating-point extension ***/
1c97856d
AJ		 6864#if defined(TARGET_PPC64)
6865#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 6866static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6867{ \
1c97856d
AJ		 6868 TCGv_i32 t0; \
6869 TCGv t1; \
6870 t0 = tcg_temp_new_i32(); \
6871 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6872 gen_helper_##name(t0, t0); \
6873 t1 = tcg_temp_new(); \
6874 tcg_gen_extu_i32_tl(t1, t0); \
6875 tcg_temp_free_i32(t0); \
6876 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6877 0xFFFFFFFF00000000ULL); \
6878 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6879 tcg_temp_free(t1); \
0487d6a8 6880}
1c97856d
AJ		 6881#define GEN_SPEFPUOP_CONV_32_64(name) \
6882static always_inline void gen_##name (DisasContext *ctx) \
6883{ \
6884 TCGv_i32 t0; \
6885 TCGv t1; \
6886 t0 = tcg_temp_new_i32(); \
6887 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
6888 t1 = tcg_temp_new(); \
6889 tcg_gen_extu_i32_tl(t1, t0); \
6890 tcg_temp_free_i32(t0); \
6891 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6892 0xFFFFFFFF00000000ULL); \
6893 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6894 tcg_temp_free(t1); \
6895}
6896#define GEN_SPEFPUOP_CONV_64_32(name) \
6897static always_inline void gen_##name (DisasContext *ctx) \
6898{ \
6899 TCGv_i32 t0 = tcg_temp_new_i32(); \
6900 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6901 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
6902 tcg_temp_free_i32(t0); \
6903}
6904#define GEN_SPEFPUOP_CONV_64_64(name) \
6905static always_inline void gen_##name (DisasContext *ctx) \
6906{ \
6907 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6908}
6909#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 6910static always_inline void gen_##name (DisasContext *ctx) \
6911{ \
1c97856d
AJ		 6912 TCGv_i32 t0, t1; \
6913 TCGv_i64 t2; \
57951c27
AJ		 6914 if (unlikely(!ctx->spe_enabled)) { \
6915 GEN_EXCP_NO_AP(ctx); \
6916 return; \
6917 } \
1c97856d
AJ		 6918 t0 = tcg_temp_new_i32(); \
6919 t1 = tcg_temp_new_i32(); \
6920 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6921 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6922 gen_helper_##name(t0, t0, t1); \
6923 tcg_temp_free_i32(t1); \
6924 t2 = tcg_temp_new(); \
6925 tcg_gen_extu_i32_tl(t2, t0); \
6926 tcg_temp_free_i32(t0); \
6927 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6928 0xFFFFFFFF00000000ULL); \
6929 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
6930 tcg_temp_free(t2); \
57951c27 6931}
1c97856d 6932#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 6933static always_inline void gen_##name (DisasContext *ctx) \
6934{ \
6935 if (unlikely(!ctx->spe_enabled)) { \
6936 GEN_EXCP_NO_AP(ctx); \
6937 return; \
6938 } \
1c97856d
AJ		 6939 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6940 cpu_gpr[rB(ctx->opcode)]); \
57951c27 6941}
1c97856d 6942#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 6943static always_inline void gen_##name (DisasContext *ctx) \
6944{ \
1c97856d 6945 TCGv_i32 t0, t1; \
57951c27
AJ		 6946 if (unlikely(!ctx->spe_enabled)) { \
6947 GEN_EXCP_NO_AP(ctx); \
6948 return; \
6949 } \
1c97856d
AJ		 6950 t0 = tcg_temp_new_i32(); \
6951 t1 = tcg_temp_new_i32(); \
6952 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6953 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6954 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
6955 tcg_temp_free_i32(t0); \
6956 tcg_temp_free_i32(t1); \
6957}
6958#define GEN_SPEFPUOP_COMP_64(name) \
6959static always_inline void gen_##name (DisasContext *ctx) \
6960{ \
6961 if (unlikely(!ctx->spe_enabled)) { \
6962 GEN_EXCP_NO_AP(ctx); \
6963 return; \
6964 } \
6965 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
6966 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6967}
6968#else
6969#define GEN_SPEFPUOP_CONV_32_32(name) \
6970static always_inline void gen_##name (DisasContext *ctx) \
6971{ \
6972 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 6973}
1c97856d
AJ		 6974#define GEN_SPEFPUOP_CONV_32_64(name) \
6975static always_inline void gen_##name (DisasContext *ctx) \
6976{ \
6977 TCGv_i64 t0 = tcg_temp_new_i64(); \
6978 gen_load_gpr64(t0, rB(ctx->opcode)); \
6979 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
6980 tcg_temp_free_i64(t0); \
6981}
6982#define GEN_SPEFPUOP_CONV_64_32(name) \
6983static always_inline void gen_##name (DisasContext *ctx) \
6984{ \
6985 TCGv_i64 t0 = tcg_temp_new_i64(); \
6986 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
6987 gen_store_gpr64(rD(ctx->opcode), t0); \
6988 tcg_temp_free_i64(t0); \
6989}
6990#define GEN_SPEFPUOP_CONV_64_64(name) \
6991static always_inline void gen_##name (DisasContext *ctx) \
6992{ \
6993 TCGv_i64 t0 = tcg_temp_new_i64(); \
6994 gen_load_gpr64(t0, rB(ctx->opcode)); \
6995 gen_helper_##name(t0, t0); \
6996 gen_store_gpr64(rD(ctx->opcode), t0); \
6997 tcg_temp_free_i64(t0); \
6998}
6999#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7000static always_inline void gen_##name (DisasContext *ctx) \
7001{ \
7002 if (unlikely(!ctx->spe_enabled)) { \
7003 GEN_EXCP_NO_AP(ctx); \
7004 return; \
7005 } \
7006 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7007 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7008}
7009#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7010static always_inline void gen_##name (DisasContext *ctx) \
7011{ \
7012 TCGv_i64 t0, t1; \
7013 if (unlikely(!ctx->spe_enabled)) { \
7014 GEN_EXCP_NO_AP(ctx); \
7015 return; \
7016 } \
7017 t0 = tcg_temp_new_i64(); \
7018 t1 = tcg_temp_new_i64(); \
7019 gen_load_gpr64(t0, rA(ctx->opcode)); \
7020 gen_load_gpr64(t1, rB(ctx->opcode)); \
7021 gen_helper_##name(t0, t0, t1); \
7022 gen_store_gpr64(rD(ctx->opcode), t0); \
7023 tcg_temp_free_i64(t0); \
7024 tcg_temp_free_i64(t1); \
7025}
7026#define GEN_SPEFPUOP_COMP_32(name) \
7027static always_inline void gen_##name (DisasContext *ctx) \
7028{ \
7029 if (unlikely(!ctx->spe_enabled)) { \
7030 GEN_EXCP_NO_AP(ctx); \
7031 return; \
7032 } \
7033 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7034 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7035}
7036#define GEN_SPEFPUOP_COMP_64(name) \
7037static always_inline void gen_##name (DisasContext *ctx) \
7038{ \
7039 TCGv_i64 t0, t1; \
7040 if (unlikely(!ctx->spe_enabled)) { \
7041 GEN_EXCP_NO_AP(ctx); \
7042 return; \
7043 } \
7044 t0 = tcg_temp_new_i64(); \
7045 t1 = tcg_temp_new_i64(); \
7046 gen_load_gpr64(t0, rA(ctx->opcode)); \
7047 gen_load_gpr64(t1, rB(ctx->opcode)); \
7048 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7049 tcg_temp_free_i64(t0); \
7050 tcg_temp_free_i64(t1); \
7051}
7052#endif
57951c27 7053
0487d6a8
JM		 7054/* Single precision floating-point vectors operations */
7055/* Arithmetic */
1c97856d
AJ		 7056GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7057GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7058GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7059GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7060static always_inline void gen_evfsabs (DisasContext *ctx)
7061{
7062 if (unlikely(!ctx->spe_enabled)) {
7063 GEN_EXCP_NO_AP(ctx);
7064 return;
7065 }
7066#if defined(TARGET_PPC64)
7067 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7068#else
7069 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7070 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7071#endif
7072}
7073static always_inline void gen_evfsnabs (DisasContext *ctx)
7074{
7075 if (unlikely(!ctx->spe_enabled)) {
7076 GEN_EXCP_NO_AP(ctx);
7077 return;
7078 }
7079#if defined(TARGET_PPC64)
7080 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7081#else
7082 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7083 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7084#endif
7085}
7086static always_inline void gen_evfsneg (DisasContext *ctx)
7087{
7088 if (unlikely(!ctx->spe_enabled)) {
7089 GEN_EXCP_NO_AP(ctx);
7090 return;
7091 }
7092#if defined(TARGET_PPC64)
7093 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7094#else
7095 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7096 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7097#endif
7098}
7099
0487d6a8 7100/* Conversion */
1c97856d
AJ		 7101GEN_SPEFPUOP_CONV_64_64(evfscfui);
7102GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7103GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7104GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7105GEN_SPEFPUOP_CONV_64_64(evfsctui);
7106GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7107GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7108GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7109GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7110GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7111
0487d6a8 7112/* Comparison */
1c97856d
AJ		 7113GEN_SPEFPUOP_COMP_64(evfscmpgt);
7114GEN_SPEFPUOP_COMP_64(evfscmplt);
7115GEN_SPEFPUOP_COMP_64(evfscmpeq);
7116GEN_SPEFPUOP_COMP_64(evfststgt);
7117GEN_SPEFPUOP_COMP_64(evfststlt);
7118GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7119
7120/* Opcodes definitions */
7121GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7122GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7123GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7124GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7125GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7126GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7127GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7128GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7129GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7130GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7131GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7132GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7133GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7134GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7135
7136/* Single precision floating-point operations */
7137/* Arithmetic */
1c97856d
AJ		 7138GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7139GEN_SPEFPUOP_ARITH2_32_32(efssub);
7140GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7141GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7142static always_inline void gen_efsabs (DisasContext *ctx)
7143{
7144 if (unlikely(!ctx->spe_enabled)) {
7145 GEN_EXCP_NO_AP(ctx);
7146 return;
7147 }
7148 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7149}
7150static always_inline void gen_efsnabs (DisasContext *ctx)
7151{
7152 if (unlikely(!ctx->spe_enabled)) {
7153 GEN_EXCP_NO_AP(ctx);
7154 return;
7155 }
7156 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7157}
7158static always_inline void gen_efsneg (DisasContext *ctx)
7159{
7160 if (unlikely(!ctx->spe_enabled)) {
7161 GEN_EXCP_NO_AP(ctx);
7162 return;
7163 }
7164 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7165}
7166
0487d6a8 7167/* Conversion */
1c97856d
AJ		 7168GEN_SPEFPUOP_CONV_32_32(efscfui);
7169GEN_SPEFPUOP_CONV_32_32(efscfsi);
7170GEN_SPEFPUOP_CONV_32_32(efscfuf);
7171GEN_SPEFPUOP_CONV_32_32(efscfsf);
7172GEN_SPEFPUOP_CONV_32_32(efsctui);
7173GEN_SPEFPUOP_CONV_32_32(efsctsi);
7174GEN_SPEFPUOP_CONV_32_32(efsctuf);
7175GEN_SPEFPUOP_CONV_32_32(efsctsf);
7176GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7177GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7178GEN_SPEFPUOP_CONV_32_64(efscfd);
7179
0487d6a8 7180/* Comparison */
1c97856d
AJ		 7181GEN_SPEFPUOP_COMP_32(efscmpgt);
7182GEN_SPEFPUOP_COMP_32(efscmplt);
7183GEN_SPEFPUOP_COMP_32(efscmpeq);
7184GEN_SPEFPUOP_COMP_32(efststgt);
7185GEN_SPEFPUOP_COMP_32(efststlt);
7186GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7187
7188/* Opcodes definitions */
05332d70 7189GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7190GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7191GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7192GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7193GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7194GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7195GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7196GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7197GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7198GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7199GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7200GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7201GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7202GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7203
7204/* Double precision floating-point operations */
7205/* Arithmetic */
1c97856d
AJ		 7206GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7207GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7208GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7209GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7210static always_inline void gen_efdabs (DisasContext *ctx)
7211{
7212 if (unlikely(!ctx->spe_enabled)) {
7213 GEN_EXCP_NO_AP(ctx);
7214 return;
7215 }
7216#if defined(TARGET_PPC64)
7217 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7218#else
7219 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7220#endif
7221}
7222static always_inline void gen_efdnabs (DisasContext *ctx)
7223{
7224 if (unlikely(!ctx->spe_enabled)) {
7225 GEN_EXCP_NO_AP(ctx);
7226 return;
7227 }
7228#if defined(TARGET_PPC64)
7229 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7230#else
7231 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7232#endif
7233}
7234static always_inline void gen_efdneg (DisasContext *ctx)
7235{
7236 if (unlikely(!ctx->spe_enabled)) {
7237 GEN_EXCP_NO_AP(ctx);
7238 return;
7239 }
7240#if defined(TARGET_PPC64)
7241 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7242#else
7243 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7244#endif
7245}
7246
0487d6a8 7247/* Conversion */
1c97856d
AJ		 7248GEN_SPEFPUOP_CONV_64_32(efdcfui);
7249GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7250GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7251GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7252GEN_SPEFPUOP_CONV_32_64(efdctui);
7253GEN_SPEFPUOP_CONV_32_64(efdctsi);
7254GEN_SPEFPUOP_CONV_32_64(efdctuf);
7255GEN_SPEFPUOP_CONV_32_64(efdctsf);
7256GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7257GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7258GEN_SPEFPUOP_CONV_64_32(efdcfs);
7259GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7260GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7261GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7262GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 7263
0487d6a8 7264/* Comparison */
1c97856d
AJ		 7265GEN_SPEFPUOP_COMP_64(efdcmpgt);
7266GEN_SPEFPUOP_COMP_64(efdcmplt);
7267GEN_SPEFPUOP_COMP_64(efdcmpeq);
7268GEN_SPEFPUOP_COMP_64(efdtstgt);
7269GEN_SPEFPUOP_COMP_64(efdtstlt);
7270GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 7271
7272/* Opcodes definitions */
7273GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7274GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7275GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7276GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7277GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7278GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7279GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7280GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7281GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7282GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7283GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7284GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7285GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7286GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7287GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7288GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 7289
79aceca5
FB		 7290/* End opcode list */
7291GEN_OPCODE_MARK(end);
7292
3fc6c082 7293#include "translate_init.c"
0411a972 7294#include "helper_regs.h"
79aceca5 7295
9a64fbe4 7296/*****************************************************************************/
3fc6c082 7297/* Misc PowerPC helpers */
36081602
JM		 7298void cpu_dump_state (CPUState *env, FILE *f,
7299 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7300 int flags)
79aceca5 7301{
3fc6c082
FB		 7302#define RGPL 4
7303#define RFPL 4
3fc6c082 7304
79aceca5
FB		 7305 int i;
7306
077fc206 7307 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 7308 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 7309 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7310 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 7311#if !defined(NO_TIMER_DUMP)
077fc206 7312 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 7313#if !defined(CONFIG_USER_ONLY)
7314 "DECR %08x"
7315#endif
7316 "\n",
077fc206 7317 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 7318#if !defined(CONFIG_USER_ONLY)
7319 , cpu_ppc_load_decr(env)
7320#endif
7321 );
077fc206 7322#endif
76a66253 7323 for (i = 0; i < 32; i++) {
3fc6c082
FB		 7324 if ((i & (RGPL - 1)) == 0)
7325 cpu_fprintf(f, "GPR%02d", i);
6b542af7 7326 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 7327 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 7328 cpu_fprintf(f, "\n");
76a66253 7329 }
3fc6c082 7330 cpu_fprintf(f, "CR ");
76a66253 7331 for (i = 0; i < 8; i++)
7fe48483
FB		 7332 cpu_fprintf(f, "%01x", env->crf[i]);
7333 cpu_fprintf(f, " [");
76a66253
JM		 7334 for (i = 0; i < 8; i++) {
7335 char a = '-';
7336 if (env->crf[i] & 0x08)
7337 a = 'L';
7338 else if (env->crf[i] & 0x04)
7339 a = 'G';
7340 else if (env->crf[i] & 0x02)
7341 a = 'E';
7fe48483 7342 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 7343 }
6b542af7 7344 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 7345 for (i = 0; i < 32; i++) {
7346 if ((i & (RFPL - 1)) == 0)
7347 cpu_fprintf(f, "FPR%02d", i);
26a76461 7348 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 7349 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 7350 cpu_fprintf(f, "\n");
79aceca5 7351 }
f2e63a42 7352#if !defined(CONFIG_USER_ONLY)
6b542af7 7353 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 7354 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 7355#endif
79aceca5 7356
3fc6c082
FB		 7357#undef RGPL
7358#undef RFPL
79aceca5
FB		 7359}
7360
76a66253
JM		 7361void cpu_dump_statistics (CPUState *env, FILE*f,
7362 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7363 int flags)
7364{
7365#if defined(DO_PPC_STATISTICS)
7366 opc_handler_t **t1, **t2, **t3, *handler;
7367 int op1, op2, op3;
7368
7369 t1 = env->opcodes;
7370 for (op1 = 0; op1 < 64; op1++) {
7371 handler = t1[op1];
7372 if (is_indirect_opcode(handler)) {
7373 t2 = ind_table(handler);
7374 for (op2 = 0; op2 < 32; op2++) {
7375 handler = t2[op2];
7376 if (is_indirect_opcode(handler)) {
7377 t3 = ind_table(handler);
7378 for (op3 = 0; op3 < 32; op3++) {
7379 handler = t3[op3];
7380 if (handler->count == 0)
7381 continue;
7382 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7383 "%016llx %lld\n",
7384 op1, op2, op3, op1, (op3 << 5) | op2,
7385 handler->oname,
7386 handler->count, handler->count);
7387 }
7388 } else {
7389 if (handler->count == 0)
7390 continue;
7391 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7392 "%016llx %lld\n",
7393 op1, op2, op1, op2, handler->oname,
7394 handler->count, handler->count);
7395 }
7396 }
7397 } else {
7398 if (handler->count == 0)
7399 continue;
7400 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7401 op1, op1, handler->oname,
7402 handler->count, handler->count);
7403 }
7404 }
7405#endif
7406}
7407
9a64fbe4 7408/*****************************************************************************/
2cfc5f17
TS		 7409static always_inline void gen_intermediate_code_internal (CPUState *env,
7410 TranslationBlock *tb,
7411 int search_pc)
79aceca5 7412{
9fddaa0c 7413 DisasContext ctx, *ctxp = &ctx;
79aceca5 7414 opc_handler_t **table, *handler;
0fa85d43 7415 target_ulong pc_start;
79aceca5 7416 uint16_t *gen_opc_end;
056401ea 7417 int supervisor, little_endian;
a1d1bb31 7418 CPUBreakpoint *bp;
79aceca5 7419 int j, lj = -1;
2e70f6ef
PB		 7420 int num_insns;
7421 int max_insns;
79aceca5
FB		 7422
7423 pc_start = tb->pc;
79aceca5 7424 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 7425#if defined(OPTIMIZE_FPRF_UPDATE)
7426 gen_fprf_ptr = gen_fprf_buf;
7427#endif
046d6672 7428 ctx.nip = pc_start;
79aceca5 7429 ctx.tb = tb;
e1833e1f 7430 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 7431 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 7432 supervisor = env->mmu_idx;
7433#if !defined(CONFIG_USER_ONLY)
2857068e 7434 ctx.supervisor = supervisor;
d9bce9d9 7435#endif
056401ea 7436 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 7437#if defined(TARGET_PPC64)
7438 ctx.sf_mode = msr_sf;
056401ea 7439 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 7440#else
056401ea 7441 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 7442#endif
d63001d1 7443 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 7444 ctx.fpu_enabled = msr_fp;
a9d9eb8f 7445 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 7446 ctx.spe_enabled = msr_spe;
7447 else
7448 ctx.spe_enabled = 0;
a9d9eb8f
JM		 7449 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7450 ctx.altivec_enabled = msr_vr;
7451 else
7452 ctx.altivec_enabled = 0;
d26bfc9a 7453 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 7454 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 7455 else
8cbcb4fa 7456 ctx.singlestep_enabled = 0;
d26bfc9a 7457 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 7458 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7459 if (unlikely(env->singlestep_enabled))
7460 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 7461#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 7462 /* Single step trace mode */
7463 msr_se = 1;
7464#endif
2e70f6ef
PB		 7465 num_insns = 0;
7466 max_insns = tb->cflags & CF_COUNT_MASK;
7467 if (max_insns == 0)
7468 max_insns = CF_COUNT_MASK;
7469
7470 gen_icount_start();
9a64fbe4 7471 /* Set env in case of segfault during code fetch */
e1833e1f 7472 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
a1d1bb31
AL		 7473 if (unlikely(env->breakpoints)) {
7474 for (bp = env->breakpoints; bp != NULL; bp = bp->next) {
7475 if (bp->pc == ctx.nip) {
5fafdf24 7476 gen_update_nip(&ctx, ctx.nip);
64adab3f 7477 gen_helper_raise_debug();
ea4e754f
FB		 7478 break;
7479 }
7480 }
7481 }
76a66253 7482 if (unlikely(search_pc)) {
79aceca5
FB		 7483 j = gen_opc_ptr - gen_opc_buf;
7484 if (lj < j) {
7485 lj++;
7486 while (lj < j)
7487 gen_opc_instr_start[lj++] = 0;
046d6672 7488 gen_opc_pc[lj] = ctx.nip;
79aceca5 7489 gen_opc_instr_start[lj] = 1;
2e70f6ef 7490 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 7491 }
7492 }
9fddaa0c
FB		 7493#if defined PPC_DEBUG_DISAS
7494 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 7495 fprintf(logfile, "----------------\n");
1b9eb036 7496 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 7497 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 7498 }
7499#endif
2e70f6ef
PB		 7500 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7501 gen_io_start();
056401ea
JM		 7502 if (unlikely(little_endian)) {
7503 ctx.opcode = bswap32(ldl_code(ctx.nip));
7504 } else {
7505 ctx.opcode = ldl_code(ctx.nip);
111bfab3 7506 }
9fddaa0c
FB		 7507#if defined PPC_DEBUG_DISAS
7508 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 7509 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 7510 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 7511 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 7512 }
7513#endif
046d6672 7514 ctx.nip += 4;
3fc6c082 7515 table = env->opcodes;
2e70f6ef 7516 num_insns++;
79aceca5
FB		 7517 handler = table[opc1(ctx.opcode)];
7518 if (is_indirect_opcode(handler)) {
7519 table = ind_table(handler);
7520 handler = table[opc2(ctx.opcode)];
7521 if (is_indirect_opcode(handler)) {
7522 table = ind_table(handler);
7523 handler = table[opc3(ctx.opcode)];
7524 }
7525 }
7526 /* Is opcode *REALLY* valid ? */
76a66253 7527 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7528 if (loglevel != 0) {
76a66253 7529 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 7530 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 7531 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7532 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7533 } else {
7534 printf("invalid/unsupported opcode: "
6b542af7 7535 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 7536 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7537 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7538 }
76a66253
JM		 7539 } else {
7540 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7541 if (loglevel != 0) {
79aceca5 7542 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 7543 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 7544 ctx.opcode & handler->inval, opc1(ctx.opcode),
7545 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7546 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7547 } else {
7548 printf("invalid bits: %08x for opcode: "
6b542af7 7549 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 7550 ctx.opcode & handler->inval, opc1(ctx.opcode),
7551 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7552 ctx.opcode, ctx.nip - 4);
76a66253 7553 }
e1833e1f 7554 GEN_EXCP_INVAL(ctxp);
4b3686fa 7555 break;
79aceca5 7556 }
79aceca5 7557 }
4b3686fa 7558 (*(handler->handler))(&ctx);
76a66253
JM		 7559#if defined(DO_PPC_STATISTICS)
7560 handler->count++;
7561#endif
9a64fbe4 7562 /* Check trace mode exceptions */
8cbcb4fa
AJ		 7563 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7564 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7565 ctx.exception != POWERPC_SYSCALL &&
7566 ctx.exception != POWERPC_EXCP_TRAP &&
7567 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 7568 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 7569 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 7570 (env->singlestep_enabled) ||
7571 num_insns >= max_insns)) {
d26bfc9a
JM		 7572 /* if we reach a page boundary or are single stepping, stop
7573 * generation
7574 */
8dd4983c 7575 break;
76a66253 7576 }
3fc6c082
FB		 7577#if defined (DO_SINGLE_STEP)
7578 break;
7579#endif
7580 }
2e70f6ef
PB		 7581 if (tb->cflags & CF_LAST_IO)
7582 gen_io_end();
e1833e1f 7583 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7584 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7585 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 7586 if (unlikely(env->singlestep_enabled)) {
7587 gen_update_nip(&ctx, ctx.nip);
64adab3f 7588 gen_helper_raise_debug();
8cbcb4fa 7589 }
76a66253 7590 /* Generate the return instruction */
57fec1fe 7591 tcg_gen_exit_tb(0);
9a64fbe4 7592 }
2e70f6ef 7593 gen_icount_end(tb, num_insns);
79aceca5 7594 *gen_opc_ptr = INDEX_op_end;
76a66253 7595 if (unlikely(search_pc)) {
9a64fbe4
FB		 7596 j = gen_opc_ptr - gen_opc_buf;
7597 lj++;
7598 while (lj <= j)
7599 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7600 } else {
046d6672 7601 tb->size = ctx.nip - pc_start;
2e70f6ef 7602 tb->icount = num_insns;
9a64fbe4 7603 }
d9bce9d9 7604#if defined(DEBUG_DISAS)
9fddaa0c 7605 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7606 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7607 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7608 }
7609 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7610 int flags;
237c0af0 7611 flags = env->bfd_mach;
056401ea 7612 flags |= little_endian << 16;
0fa85d43 7613 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7614 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7615 fprintf(logfile, "\n");
9fddaa0c 7616 }
79aceca5 7617#endif
79aceca5
FB		 7618}
7619
2cfc5f17 7620void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 7621{
2cfc5f17 7622 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 7623}
7624
2cfc5f17 7625void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7626{
2cfc5f17 7627 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7628}
d2856f1a
AJ		 7629
7630void gen_pc_load(CPUState *env, TranslationBlock *tb,
7631 unsigned long searched_pc, int pc_pos, void *puc)
7632{
7633 int type, c;
7634 /* for PPC, we need to look at the micro operation to get the
7635 * access type */
7636 env->nip = gen_opc_pc[pc_pos];
7637 c = gen_opc_buf[pc_pos];
7638 switch(c) {
7639#if defined(CONFIG_USER_ONLY)
7640#define CASE3(op)\
7641 case INDEX_op_ ## op ## _raw
7642#else
7643#define CASE3(op)\
7644 case INDEX_op_ ## op ## _user:\
7645 case INDEX_op_ ## op ## _kernel:\
7646 case INDEX_op_ ## op ## _hypv
7647#endif
7648
7649 CASE3(stfd):
7650 CASE3(stfs):
7651 CASE3(lfd):
7652 CASE3(lfs):
7653 type = ACCESS_FLOAT;
7654 break;
7655 CASE3(lwarx):
7656 type = ACCESS_RES;
7657 break;
7658 CASE3(stwcx):
7659 type = ACCESS_RES;
7660 break;
7661 CASE3(eciwx):
7662 CASE3(ecowx):
7663 type = ACCESS_EXT;
7664 break;
7665 default:
7666 type = ACCESS_INT;
7667 break;
7668 }
7669 env->access_type = type;
7670}
Qemu copy for testing