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Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSP
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5
FB		 28#include "disas.h"
29
a750fc0b 30/* Include definitions for instructions classes and implementations flags */
79aceca5 31//#define DO_SINGLE_STEP
9fddaa0c 32//#define PPC_DEBUG_DISAS
a496775f 33//#define DEBUG_MEMORY_ACCESSES
76a66253 34//#define DO_PPC_STATISTICS
7c58044c 35//#define OPTIMIZE_FPRF_UPDATE
79aceca5 36
a750fc0b
JM		 37/*****************************************************************************/
38/* Code translation helpers */
d9bce9d9 39#if defined(USE_DIRECT_JUMP)
c53be334
FB		 40#define TBPARAM(x)
41#else
42#define TBPARAM(x) (long)(x)
43#endif
44
79aceca5
FB		 45enum {
46#define DEF(s, n, copy_size) INDEX_op_ ## s,
47#include "opc.h"
48#undef DEF
49 NB_OPS,
50};
51
52static uint16_t *gen_opc_ptr;
53static uint32_t *gen_opparam_ptr;
7c58044c
JM		 54#if defined(OPTIMIZE_FPRF_UPDATE)
55static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
56static uint16_t **gen_fprf_ptr;
57#endif
79aceca5
FB		 58
59#include "gen-op.h"
28b6751f 60
b068d6a7 61static always_inline void gen_set_T0 (target_ulong val)
d9bce9d9
JM		 62{
63#if defined(TARGET_PPC64)
64 if (val >> 32)
65 gen_op_set_T0_64(val >> 32, val);
66 else
67#endif
68 gen_op_set_T0(val);
69}
70
b068d6a7 71static always_inline void gen_set_T1 (target_ulong val)
d9bce9d9
JM		 72{
73#if defined(TARGET_PPC64)
74 if (val >> 32)
75 gen_op_set_T1_64(val >> 32, val);
76 else
77#endif
78 gen_op_set_T1(val);
79}
80
81#define GEN8(func, NAME) \
9a64fbe4
FB		 82static GenOpFunc *NAME ## _table [8] = { \
83NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
84NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
85}; \
b068d6a7 86static always_inline void func (int n) \
9a64fbe4
FB		 87{ \
88 NAME ## _table[n](); \
89}
90
91#define GEN16(func, NAME) \
92static GenOpFunc *NAME ## _table [16] = { \
93NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
94NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
95NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
96NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
97}; \
b068d6a7 98static always_inline void func (int n) \
9a64fbe4
FB		 99{ \
100 NAME ## _table[n](); \
28b6751f
FB		 101}
102
d9bce9d9 103#define GEN32(func, NAME) \
9a64fbe4
FB		 104static GenOpFunc *NAME ## _table [32] = { \
105NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
106NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
107NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
108NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
109NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
110NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
111NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
112NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
113}; \
b068d6a7 114static always_inline void func (int n) \
9a64fbe4
FB		 115{ \
116 NAME ## _table[n](); \
117}
118
119/* Condition register moves */
120GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
121GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
122GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
fc0d441e 123#if 0 // Unused
9a64fbe4 124GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
fc0d441e 125#endif
28b6751f 126
9a64fbe4
FB		 127/* General purpose registers moves */
128GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
129GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
130GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
131
132GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
133GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
76a66253 134#if 0 // unused
9a64fbe4 135GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
76a66253 136#endif
28b6751f 137
fb0eaffc
FB		 138/* floating point registers moves */
139GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
140GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
141GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
142GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
143GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
76a66253 144#if 0 // unused
fb0eaffc 145GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
76a66253 146#endif
79aceca5
FB		 147
148/* internal defines */
149typedef struct DisasContext {
150 struct TranslationBlock *tb;
0fa85d43 151 target_ulong nip;
79aceca5 152 uint32_t opcode;
9a64fbe4 153 uint32_t exception;
3cc62370
FB		 154 /* Routine used to access memory */
155 int mem_idx;
156 /* Translation flags */
9a64fbe4 157#if !defined(CONFIG_USER_ONLY)
79aceca5 158 int supervisor;
d9bce9d9
JM		 159#endif
160#if defined(TARGET_PPC64)
161 int sf_mode;
9a64fbe4 162#endif
3cc62370 163 int fpu_enabled;
a9d9eb8f 164 int altivec_enabled;
0487d6a8 165 int spe_enabled;
3fc6c082 166 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 167 int singlestep_enabled;
d63001d1 168 int dcache_line_size;
79aceca5
FB		 169} DisasContext;
170
3fc6c082 171struct opc_handler_t {
79aceca5
FB		 172 /* invalid bits */
173 uint32_t inval;
9a64fbe4 174 /* instruction type */
0487d6a8 175 uint64_t type;
79aceca5
FB		 176 /* handler */
177 void (*handler)(DisasContext *ctx);
a750fc0b 178#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
76a66253 179 const unsigned char *oname;
a750fc0b
JM		 180#endif
181#if defined(DO_PPC_STATISTICS)
76a66253
JM		 182 uint64_t count;
183#endif
3fc6c082 184};
79aceca5 185
b068d6a7 186static always_inline void gen_set_Rc0 (DisasContext *ctx)
76a66253 187{
d9bce9d9
JM		 188#if defined(TARGET_PPC64)
189 if (ctx->sf_mode)
190 gen_op_cmpi_64(0);
191 else
192#endif
193 gen_op_cmpi(0);
76a66253
JM		 194 gen_op_set_Rc0();
195}
196
7c58044c
JM		 197static always_inline void gen_reset_fpstatus (void)
198{
199#ifdef CONFIG_SOFTFLOAT
200 gen_op_reset_fpstatus();
201#endif
202}
203
204static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
205{
206 if (set_fprf != 0) {
207 /* This case might be optimized later */
208#if defined(OPTIMIZE_FPRF_UPDATE)
209 *gen_fprf_ptr++ = gen_opc_ptr;
210#endif
211 gen_op_compute_fprf(1);
212 if (unlikely(set_rc))
213 gen_op_store_T0_crf(1);
214 gen_op_float_check_status();
215 } else if (unlikely(set_rc)) {
216 /* We always need to compute fpcc */
217 gen_op_compute_fprf(0);
218 gen_op_store_T0_crf(1);
219 if (set_fprf)
220 gen_op_float_check_status();
221 }
222}
223
224static always_inline void gen_optimize_fprf (void)
225{
226#if defined(OPTIMIZE_FPRF_UPDATE)
227 uint16_t **ptr;
228
229 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
230 *ptr = INDEX_op_nop1;
231 gen_fprf_ptr = gen_fprf_buf;
232#endif
233}
234
b068d6a7 235static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 236{
237#if defined(TARGET_PPC64)
238 if (ctx->sf_mode)
239 gen_op_update_nip_64(nip >> 32, nip);
240 else
241#endif
242 gen_op_update_nip(nip);
243}
244
e1833e1f 245#define GEN_EXCP(ctx, excp, error) \
79aceca5 246do { \
e1833e1f 247 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 248 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 249 } \
250 gen_op_raise_exception_err((excp), (error)); \
251 ctx->exception = (excp); \
79aceca5
FB		 252} while (0)
253
e1833e1f
JM		 254#define GEN_EXCP_INVAL(ctx) \
255GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
256 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 257
e1833e1f
JM		 258#define GEN_EXCP_PRIVOPC(ctx) \
259GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
260 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 261
e1833e1f
JM		 262#define GEN_EXCP_PRIVREG(ctx) \
263GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
264 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
265
266#define GEN_EXCP_NO_FP(ctx) \
267GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
268
269#define GEN_EXCP_NO_AP(ctx) \
270GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 271
a9d9eb8f
JM		 272#define GEN_EXCP_NO_VR(ctx) \
273GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
274
f24e5695 275/* Stop translation */
b068d6a7 276static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 277{
d9bce9d9 278 gen_update_nip(ctx, ctx->nip);
e1833e1f 279 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 280}
281
f24e5695 282/* No need to update nip here, as execution flow will change */
b068d6a7 283static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 284{
e1833e1f 285 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 286}
287
79aceca5
FB		 288#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
289static void gen_##name (DisasContext *ctx); \
290GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
291static void gen_##name (DisasContext *ctx)
292
c7697e1f
JM		 293#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
294static void gen_##name (DisasContext *ctx); \
295GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
296static void gen_##name (DisasContext *ctx)
297
79aceca5
FB		 298typedef struct opcode_t {
299 unsigned char opc1, opc2, opc3;
18fba28c
FB		 300#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
301 unsigned char pad[5];
302#else
303 unsigned char pad[1];
304#endif
79aceca5 305 opc_handler_t handler;
3fc6c082 306 const unsigned char *oname;
79aceca5
FB		 307} opcode_t;
308
a750fc0b 309/*****************************************************************************/
79aceca5
FB		 310/*** Instruction decoding ***/
311#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 312static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 313{ \
314 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
315}
316
317#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 318static always_inline int32_t name (uint32_t opcode) \
79aceca5 319{ \
18fba28c 320 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 321}
322
323/* Opcode part 1 */
324EXTRACT_HELPER(opc1, 26, 6);
325/* Opcode part 2 */
326EXTRACT_HELPER(opc2, 1, 5);
327/* Opcode part 3 */
328EXTRACT_HELPER(opc3, 6, 5);
329/* Update Cr0 flags */
330EXTRACT_HELPER(Rc, 0, 1);
331/* Destination */
332EXTRACT_HELPER(rD, 21, 5);
333/* Source */
334EXTRACT_HELPER(rS, 21, 5);
335/* First operand */
336EXTRACT_HELPER(rA, 16, 5);
337/* Second operand */
338EXTRACT_HELPER(rB, 11, 5);
339/* Third operand */
340EXTRACT_HELPER(rC, 6, 5);
341/*** Get CRn ***/
342EXTRACT_HELPER(crfD, 23, 3);
343EXTRACT_HELPER(crfS, 18, 3);
344EXTRACT_HELPER(crbD, 21, 5);
345EXTRACT_HELPER(crbA, 16, 5);
346EXTRACT_HELPER(crbB, 11, 5);
347/* SPR / TBL */
3fc6c082 348EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 349static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 350{
351 uint32_t sprn = _SPR(opcode);
352
353 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
354}
79aceca5
FB		 355/*** Get constants ***/
356EXTRACT_HELPER(IMM, 12, 8);
357/* 16 bits signed immediate value */
358EXTRACT_SHELPER(SIMM, 0, 16);
359/* 16 bits unsigned immediate value */
360EXTRACT_HELPER(UIMM, 0, 16);
361/* Bit count */
362EXTRACT_HELPER(NB, 11, 5);
363/* Shift count */
364EXTRACT_HELPER(SH, 11, 5);
365/* Mask start */
366EXTRACT_HELPER(MB, 6, 5);
367/* Mask end */
368EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 369/* Trap operand */
370EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 371
372EXTRACT_HELPER(CRM, 12, 8);
373EXTRACT_HELPER(FM, 17, 8);
374EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 375EXTRACT_HELPER(FPIMM, 20, 4);
376
79aceca5
FB		 377/*** Jump target decoding ***/
378/* Displacement */
379EXTRACT_SHELPER(d, 0, 16);
380/* Immediate address */
b068d6a7 381static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 382{
383 return (opcode >> 0) & 0x03FFFFFC;
384}
385
b068d6a7 386static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 387{
388 return (opcode >> 0) & 0xFFFC;
389}
390
391EXTRACT_HELPER(BO, 21, 5);
392EXTRACT_HELPER(BI, 16, 5);
393/* Absolute/relative address */
394EXTRACT_HELPER(AA, 1, 1);
395/* Link */
396EXTRACT_HELPER(LK, 0, 1);
397
398/* Create a mask between <start> and <end> bits */
b068d6a7 399static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 400{
76a66253 401 target_ulong ret;
79aceca5 402
76a66253
JM		 403#if defined(TARGET_PPC64)
404 if (likely(start == 0)) {
6f2d8978 405 ret = UINT64_MAX << (63 - end);
76a66253 406 } else if (likely(end == 63)) {
6f2d8978 407 ret = UINT64_MAX >> start;
76a66253
JM		 408 }
409#else
410 if (likely(start == 0)) {
6f2d8978 411 ret = UINT32_MAX << (31 - end);
76a66253 412 } else if (likely(end == 31)) {
6f2d8978 413 ret = UINT32_MAX >> start;
76a66253
JM		 414 }
415#endif
416 else {
417 ret = (((target_ulong)(-1ULL)) >> (start)) ^
418 (((target_ulong)(-1ULL) >> (end)) >> 1);
419 if (unlikely(start > end))
420 return ~ret;
421 }
79aceca5
FB		 422
423 return ret;
424}
425
a750fc0b
JM		 426/*****************************************************************************/
427/* PowerPC Instructions types definitions */
428enum {
1b413d55 429 PPC_NONE = 0x0000000000000000ULL,
12de9a39 430 /* PowerPC base instructions set */
1b413d55
JM		 431 PPC_INSNS_BASE = 0x0000000000000001ULL,
432 /* integer operations instructions */
a750fc0b 433#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 434 /* flow control instructions */
a750fc0b 435#define PPC_FLOW PPC_INSNS_BASE
1b413d55 436 /* virtual memory instructions */
a750fc0b 437#define PPC_MEM PPC_INSNS_BASE
1b413d55 438 /* ld/st with reservation instructions */
a750fc0b 439#define PPC_RES PPC_INSNS_BASE
1b413d55 440 /* spr/msr access instructions */
a750fc0b 441#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 442 /* Deprecated instruction sets */
443 /* Original POWER instruction set */
444 PPC_POWER = 0x0000000000000001ULL,
445 /* POWER2 instruction set extension */
446 PPC_POWER2 = 0x0000000000000002ULL,
447 /* Power RTC support */
448 PPC_POWER_RTC = 0x0000000000000004ULL,
449 /* Power-to-PowerPC bridge (601) */
450 PPC_POWER_BR = 0x0000000000000008ULL,
451 /* 64 bits PowerPC instruction set */
452 PPC_64B = 0x0000000000000010ULL,
453 /* New 64 bits extensions (PowerPC 2.0x) */
454 PPC_64BX = 0x0000000000000020ULL,
455 /* 64 bits hypervisor extensions */
456 PPC_64H = 0x0000000000000040ULL,
457 /* New wait instruction (PowerPC 2.0x) */
458 PPC_WAIT = 0x0000000000000080ULL,
459 /* Time base mftb instruction */
460 PPC_MFTB = 0x0000000000000100ULL,
461
462 /* Fixed-point unit extensions */
463 /* PowerPC 602 specific */
464 PPC_602_SPEC = 0x0000000000000200ULL,
465 /* PowerPC 2.03 specification extensions */
466 PPC_203 = 0x0000000000000400ULL,
467
468 /* Floating-point unit extensions */
469 /* Optional floating point instructions */
470 PPC_FLOAT = 0x0000000000010000ULL,
471 /* New floating-point extensions (PowerPC 2.0x) */
472 PPC_FLOAT_EXT = 0x0000000000020000ULL,
473 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
474 PPC_FLOAT_FRES = 0x0000000000080000ULL,
475 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
476 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
477 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
478 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
479
480 /* Vector/SIMD extensions */
481 /* Altivec support */
482 PPC_ALTIVEC = 0x0000000001000000ULL,
483 /* e500 vector instructions */
484 PPC_E500_VECTOR = 0x0000000002000000ULL,
485 /* PowerPC 2.03 SPE extension */
486 PPC_SPE = 0x0000000004000000ULL,
487 /* PowerPC 2.03 SPE floating-point extension */
488 PPC_SPEFPU = 0x0000000008000000ULL,
489
12de9a39 490 /* Optional memory control instructions */
1b413d55
JM		 491 PPC_MEM_TLBIA = 0x0000000010000000ULL,
492 PPC_MEM_TLBIE = 0x0000000020000000ULL,
493 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
494 /* sync instruction */
495 PPC_MEM_SYNC = 0x0000000080000000ULL,
496 /* eieio instruction */
497 PPC_MEM_EIEIO = 0x0000000100000000ULL,
498
499 /* Cache control instructions */
500 PPC_CACHE = 0x0000001000000000ULL,
501 /* icbi instruction */
502 PPC_CACHE_ICBI = 0x0000002000000000ULL,
503 /* dcbz instruction with fixed cache line size */
504 PPC_CACHE_DCBZ = 0x0000004000000000ULL,
505 /* dcbz instruction with tunable cache line size */
506 PPC_CACHE_DCBZT = 0x0000008000000000ULL,
507 /* dcba instruction */
508 PPC_CACHE_DCBA = 0x0000010000000000ULL,
509
510 /* MMU related extensions */
511 /* external control instructions */
512 PPC_EXTERN = 0x0000100000000000ULL,
513 /* segment register access instructions */
514 PPC_SEGMENT = 0x0000200000000000ULL,
515 /* PowerPC 6xx TLB management instructions */
516 PPC_6xx_TLB = 0x0000400000000000ULL,
517 /* PowerPC 74xx TLB management instructions */
518 PPC_74xx_TLB = 0x0000800000000000ULL,
519 /* PowerPC 40x TLB management instructions */
520 PPC_40x_TLB = 0x0001000000000000ULL,
521 /* segment register access instructions for PowerPC 64 "bridge" */
522 PPC_SEGMENT_64B = 0x0002000000000000ULL,
523 /* SLB management */
524 PPC_SLBI = 0x0004000000000000ULL,
525
12de9a39 526 /* Embedded PowerPC dedicated instructions */
1b413d55 527 PPC_EMB_COMMON = 0x0010000000000000ULL,
12de9a39 528 /* PowerPC 40x exception model */
1b413d55 529 PPC_40x_EXCP = 0x0020000000000000ULL,
12de9a39 530 /* PowerPC 405 Mac instructions */
1b413d55 531 PPC_405_MAC = 0x0040000000000000ULL,
12de9a39 532 /* PowerPC 440 specific instructions */
1b413d55 533 PPC_440_SPEC = 0x0080000000000000ULL,
12de9a39 534 /* BookE (embedded) PowerPC specification */
1b413d55
JM		 535 PPC_BOOKE = 0x0100000000000000ULL,
536 /* More BookE (embedded) instructions... */
537 PPC_BOOKE_EXT = 0x0200000000000000ULL,
12de9a39 538 /* PowerPC 4xx dedicated instructions */
1b413d55 539 PPC_4xx_COMMON = 0x0400000000000000ULL,
12de9a39 540 /* PowerPC 40x ibct instructions */
1b413d55 541 PPC_40x_ICBT = 0x0800000000000000ULL,
12de9a39 542 /* rfmci is not implemented in all BookE PowerPC */
1b413d55 543 PPC_RFMCI = 0x1000000000000000ULL,
12de9a39 544 /* user-mode DCR access, implemented in PowerPC 460 */
1b413d55 545 PPC_DCRUX = 0x2000000000000000ULL,
a750fc0b
JM		 546};
547
548/*****************************************************************************/
549/* PowerPC instructions table */
3fc6c082
FB		 550#if HOST_LONG_BITS == 64
551#define OPC_ALIGN 8
552#else
553#define OPC_ALIGN 4
554#endif
1b039c09 555#if defined(__APPLE__)
d9bce9d9 556#define OPCODES_SECTION \
3fc6c082 557 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 558#else
d9bce9d9 559#define OPCODES_SECTION \
3fc6c082 560 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 561#endif
562
76a66253 563#if defined(DO_PPC_STATISTICS)
79aceca5 564#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 565OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 566 .opc1 = op1, \
567 .opc2 = op2, \
568 .opc3 = op3, \
18fba28c 569 .pad = { 0, }, \
79aceca5
FB		 570 .handler = { \
571 .inval = invl, \
9a64fbe4 572 .type = _typ, \
79aceca5 573 .handler = &gen_##name, \
76a66253 574 .oname = stringify(name), \
79aceca5 575 }, \
3fc6c082 576 .oname = stringify(name), \
79aceca5 577}
c7697e1f
JM		 578#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
579OPCODES_SECTION opcode_t opc_##name = { \
580 .opc1 = op1, \
581 .opc2 = op2, \
582 .opc3 = op3, \
583 .pad = { 0, }, \
584 .handler = { \
585 .inval = invl, \
586 .type = _typ, \
587 .handler = &gen_##name, \
588 .oname = onam, \
589 }, \
590 .oname = onam, \
591}
76a66253
JM		 592#else
593#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
594OPCODES_SECTION opcode_t opc_##name = { \
595 .opc1 = op1, \
596 .opc2 = op2, \
597 .opc3 = op3, \
598 .pad = { 0, }, \
599 .handler = { \
600 .inval = invl, \
601 .type = _typ, \
602 .handler = &gen_##name, \
603 }, \
604 .oname = stringify(name), \
605}
c7697e1f
JM		 606#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
607OPCODES_SECTION opcode_t opc_##name = { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .pad = { 0, }, \
612 .handler = { \
613 .inval = invl, \
614 .type = _typ, \
615 .handler = &gen_##name, \
616 }, \
617 .oname = onam, \
618}
76a66253 619#endif
79aceca5
FB		 620
621#define GEN_OPCODE_MARK(name) \
18fba28c 622OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 623 .opc1 = 0xFF, \
624 .opc2 = 0xFF, \
625 .opc3 = 0xFF, \
18fba28c 626 .pad = { 0, }, \
79aceca5
FB		 627 .handler = { \
628 .inval = 0x00000000, \
9a64fbe4 629 .type = 0x00, \
79aceca5
FB		 630 .handler = NULL, \
631 }, \
3fc6c082 632 .oname = stringify(name), \
79aceca5
FB		 633}
634
635/* Start opcode list */
636GEN_OPCODE_MARK(start);
637
638/* Invalid instruction */
9a64fbe4
FB		 639GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
640{
e1833e1f 641 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 642}
643
79aceca5
FB		 644static opc_handler_t invalid_handler = {
645 .inval = 0xFFFFFFFF,
9a64fbe4 646 .type = PPC_NONE,
79aceca5
FB		 647 .handler = gen_invalid,
648};
649
650/*** Integer arithmetic ***/
d9bce9d9
JM		 651#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
652GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5
FB		 653{ \
654 gen_op_load_gpr_T0(rA(ctx->opcode)); \
655 gen_op_load_gpr_T1(rB(ctx->opcode)); \
656 gen_op_##name(); \
79aceca5 657 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 658 if (unlikely(Rc(ctx->opcode) != 0)) \
659 gen_set_Rc0(ctx); \
79aceca5
FB		 660}
661
d9bce9d9
JM		 662#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
663GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5
FB		 664{ \
665 gen_op_load_gpr_T0(rA(ctx->opcode)); \
666 gen_op_load_gpr_T1(rB(ctx->opcode)); \
667 gen_op_##name(); \
79aceca5 668 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 669 if (unlikely(Rc(ctx->opcode) != 0)) \
670 gen_set_Rc0(ctx); \
79aceca5
FB		 671}
672
d9bce9d9
JM		 673#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
674GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5
FB		 675{ \
676 gen_op_load_gpr_T0(rA(ctx->opcode)); \
677 gen_op_##name(); \
79aceca5 678 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 679 if (unlikely(Rc(ctx->opcode) != 0)) \
680 gen_set_Rc0(ctx); \
79aceca5 681}
d9bce9d9
JM		 682#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
683GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5
FB		 684{ \
685 gen_op_load_gpr_T0(rA(ctx->opcode)); \
686 gen_op_##name(); \
79aceca5 687 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 688 if (unlikely(Rc(ctx->opcode) != 0)) \
689 gen_set_Rc0(ctx); \
79aceca5
FB		 690}
691
692/* Two operands arithmetic functions */
d9bce9d9
JM		 693#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
694__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
695__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
696
697/* Two operands arithmetic functions with no overflow allowed */
698#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
699__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
700
701/* One operand arithmetic functions */
702#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
703__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
704__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
705
706#if defined(TARGET_PPC64)
707#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
708GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
709{ \
710 gen_op_load_gpr_T0(rA(ctx->opcode)); \
711 gen_op_load_gpr_T1(rB(ctx->opcode)); \
712 if (ctx->sf_mode) \
713 gen_op_##name##_64(); \
714 else \
715 gen_op_##name(); \
716 gen_op_store_T0_gpr(rD(ctx->opcode)); \
717 if (unlikely(Rc(ctx->opcode) != 0)) \
718 gen_set_Rc0(ctx); \
719}
720
721#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
722GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
723{ \
724 gen_op_load_gpr_T0(rA(ctx->opcode)); \
725 gen_op_load_gpr_T1(rB(ctx->opcode)); \
726 if (ctx->sf_mode) \
727 gen_op_##name##_64(); \
728 else \
729 gen_op_##name(); \
730 gen_op_store_T0_gpr(rD(ctx->opcode)); \
731 if (unlikely(Rc(ctx->opcode) != 0)) \
732 gen_set_Rc0(ctx); \
733}
734
735#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
736GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
737{ \
738 gen_op_load_gpr_T0(rA(ctx->opcode)); \
739 if (ctx->sf_mode) \
740 gen_op_##name##_64(); \
741 else \
742 gen_op_##name(); \
743 gen_op_store_T0_gpr(rD(ctx->opcode)); \
744 if (unlikely(Rc(ctx->opcode) != 0)) \
745 gen_set_Rc0(ctx); \
746}
747#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
748GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
749{ \
750 gen_op_load_gpr_T0(rA(ctx->opcode)); \
751 if (ctx->sf_mode) \
752 gen_op_##name##_64(); \
753 else \
754 gen_op_##name(); \
755 gen_op_store_T0_gpr(rD(ctx->opcode)); \
756 if (unlikely(Rc(ctx->opcode) != 0)) \
757 gen_set_Rc0(ctx); \
758}
759
760/* Two operands arithmetic functions */
761#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
762__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
763__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 764
765/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 766#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
767__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 768
769/* One operand arithmetic functions */
d9bce9d9
JM		 770#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
771__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
772__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
773#else
774#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
775#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
776#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
777#endif
79aceca5
FB		 778
779/* add add. addo addo. */
b068d6a7 780static always_inline void gen_op_addo (void)
d9bce9d9
JM		 781{
782 gen_op_move_T2_T0();
783 gen_op_add();
784 gen_op_check_addo();
785}
786#if defined(TARGET_PPC64)
787#define gen_op_add_64 gen_op_add
b068d6a7 788static always_inline void gen_op_addo_64 (void)
d9bce9d9
JM		 789{
790 gen_op_move_T2_T0();
791 gen_op_add();
792 gen_op_check_addo_64();
793}
794#endif
795GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 796/* addc addc. addco addco. */
b068d6a7 797static always_inline void gen_op_addc (void)
d9bce9d9
JM		 798{
799 gen_op_move_T2_T0();
800 gen_op_add();
801 gen_op_check_addc();
802}
b068d6a7 803static always_inline void gen_op_addco (void)
d9bce9d9
JM		 804{
805 gen_op_move_T2_T0();
806 gen_op_add();
807 gen_op_check_addc();
808 gen_op_check_addo();
809}
810#if defined(TARGET_PPC64)
b068d6a7 811static always_inline void gen_op_addc_64 (void)
d9bce9d9
JM		 812{
813 gen_op_move_T2_T0();
814 gen_op_add();
815 gen_op_check_addc_64();
816}
b068d6a7 817static always_inline void gen_op_addco_64 (void)
d9bce9d9
JM		 818{
819 gen_op_move_T2_T0();
820 gen_op_add();
821 gen_op_check_addc_64();
822 gen_op_check_addo_64();
823}
824#endif
825GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 826/* adde adde. addeo addeo. */
b068d6a7 827static always_inline void gen_op_addeo (void)
d9bce9d9
JM		 828{
829 gen_op_move_T2_T0();
830 gen_op_adde();
831 gen_op_check_addo();
832}
833#if defined(TARGET_PPC64)
b068d6a7 834static always_inline void gen_op_addeo_64 (void)
d9bce9d9
JM		 835{
836 gen_op_move_T2_T0();
837 gen_op_adde_64();
838 gen_op_check_addo_64();
839}
840#endif
841GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 842/* addme addme. addmeo addmeo. */
b068d6a7 843static always_inline void gen_op_addme (void)
d9bce9d9
JM		 844{
845 gen_op_move_T1_T0();
846 gen_op_add_me();
847}
848#if defined(TARGET_PPC64)
b068d6a7 849static always_inline void gen_op_addme_64 (void)
d9bce9d9
JM		 850{
851 gen_op_move_T1_T0();
852 gen_op_add_me_64();
853}
854#endif
855GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 856/* addze addze. addzeo addzeo. */
b068d6a7 857static always_inline void gen_op_addze (void)
d9bce9d9
JM		 858{
859 gen_op_move_T2_T0();
860 gen_op_add_ze();
861 gen_op_check_addc();
862}
b068d6a7 863static always_inline void gen_op_addzeo (void)
d9bce9d9
JM		 864{
865 gen_op_move_T2_T0();
866 gen_op_add_ze();
867 gen_op_check_addc();
868 gen_op_check_addo();
869}
870#if defined(TARGET_PPC64)
b068d6a7 871static always_inline void gen_op_addze_64 (void)
d9bce9d9
JM		 872{
873 gen_op_move_T2_T0();
874 gen_op_add_ze();
875 gen_op_check_addc_64();
876}
b068d6a7 877static always_inline void gen_op_addzeo_64 (void)
d9bce9d9
JM		 878{
879 gen_op_move_T2_T0();
880 gen_op_add_ze();
881 gen_op_check_addc_64();
882 gen_op_check_addo_64();
883}
884#endif
885GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 886/* divw divw. divwo divwo. */
d9bce9d9 887GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 888/* divwu divwu. divwuo divwuo. */
d9bce9d9 889GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 890/* mulhw mulhw. */
d9bce9d9 891GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 892/* mulhwu mulhwu. */
d9bce9d9 893GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 894/* mullw mullw. mullwo mullwo. */
d9bce9d9 895GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 896/* neg neg. nego nego. */
d9bce9d9 897GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 898/* subf subf. subfo subfo. */
b068d6a7 899static always_inline void gen_op_subfo (void)
d9bce9d9 900{
c3e10c7b 901 gen_op_moven_T2_T0();
d9bce9d9 902 gen_op_subf();
c3e10c7b 903 gen_op_check_addo();
d9bce9d9
JM		 904}
905#if defined(TARGET_PPC64)
906#define gen_op_subf_64 gen_op_subf
b068d6a7 907static always_inline void gen_op_subfo_64 (void)
d9bce9d9 908{
c3e10c7b 909 gen_op_moven_T2_T0();
d9bce9d9 910 gen_op_subf();
c3e10c7b 911 gen_op_check_addo_64();
d9bce9d9
JM		 912}
913#endif
914GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 915/* subfc subfc. subfco subfco. */
b068d6a7 916static always_inline void gen_op_subfc (void)
d9bce9d9
JM		 917{
918 gen_op_subf();
919 gen_op_check_subfc();
920}
b068d6a7 921static always_inline void gen_op_subfco (void)
d9bce9d9 922{
c3e10c7b 923 gen_op_moven_T2_T0();
d9bce9d9
JM		 924 gen_op_subf();
925 gen_op_check_subfc();
c3e10c7b 926 gen_op_check_addo();
d9bce9d9
JM		 927}
928#if defined(TARGET_PPC64)
b068d6a7 929static always_inline void gen_op_subfc_64 (void)
d9bce9d9
JM		 930{
931 gen_op_subf();
932 gen_op_check_subfc_64();
933}
b068d6a7 934static always_inline void gen_op_subfco_64 (void)
d9bce9d9 935{
c3e10c7b 936 gen_op_moven_T2_T0();
d9bce9d9
JM		 937 gen_op_subf();
938 gen_op_check_subfc_64();
c3e10c7b 939 gen_op_check_addo_64();
d9bce9d9
JM		 940}
941#endif
942GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 943/* subfe subfe. subfeo subfeo. */
b068d6a7 944static always_inline void gen_op_subfeo (void)
d9bce9d9 945{
c3e10c7b 946 gen_op_moven_T2_T0();
d9bce9d9 947 gen_op_subfe();
c3e10c7b 948 gen_op_check_addo();
d9bce9d9
JM		 949}
950#if defined(TARGET_PPC64)
951#define gen_op_subfe_64 gen_op_subfe
b068d6a7 952static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 953{
c3e10c7b 954 gen_op_moven_T2_T0();
d9bce9d9 955 gen_op_subfe_64();
c3e10c7b 956 gen_op_check_addo_64();
d9bce9d9
JM		 957}
958#endif
959GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 960/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 961GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 962/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 963GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 964/* addi */
965GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
966{
76a66253 967 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 968
969 if (rA(ctx->opcode) == 0) {
76a66253 970 /* li case */
d9bce9d9 971 gen_set_T0(simm);
79aceca5
FB		 972 } else {
973 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 974 if (likely(simm != 0))
975 gen_op_addi(simm);
79aceca5
FB		 976 }
977 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 978}
979/* addic */
980GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
981{
76a66253
JM		 982 target_long simm = SIMM(ctx->opcode);
983
79aceca5 984 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 985 if (likely(simm != 0)) {
986 gen_op_move_T2_T0();
987 gen_op_addi(simm);
988#if defined(TARGET_PPC64)
989 if (ctx->sf_mode)
990 gen_op_check_addc_64();
991 else
992#endif
993 gen_op_check_addc();
e864cabd
JM		 994 } else {
995 gen_op_clear_xer_ca();
d9bce9d9 996 }
79aceca5 997 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 998}
999/* addic. */
c7697e1f 1000GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1001{
76a66253
JM		 1002 target_long simm = SIMM(ctx->opcode);
1003
79aceca5 1004 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 1005 if (likely(simm != 0)) {
1006 gen_op_move_T2_T0();
1007 gen_op_addi(simm);
1008#if defined(TARGET_PPC64)
1009 if (ctx->sf_mode)
1010 gen_op_check_addc_64();
1011 else
1012#endif
1013 gen_op_check_addc();
966439a6
JM		 1014 } else {
1015 gen_op_clear_xer_ca();
d9bce9d9 1016 }
79aceca5 1017 gen_op_store_T0_gpr(rD(ctx->opcode));
76a66253 1018 gen_set_Rc0(ctx);
79aceca5
FB		 1019}
1020/* addis */
1021GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1022{
76a66253 1023 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1024
1025 if (rA(ctx->opcode) == 0) {
76a66253 1026 /* lis case */
d9bce9d9 1027 gen_set_T0(simm << 16);
79aceca5
FB		 1028 } else {
1029 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 1030 if (likely(simm != 0))
1031 gen_op_addi(simm << 16);
79aceca5
FB		 1032 }
1033 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1034}
1035/* mulli */
1036GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1037{
1038 gen_op_load_gpr_T0(rA(ctx->opcode));
1039 gen_op_mulli(SIMM(ctx->opcode));
1040 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1041}
1042/* subfic */
1043GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1044{
1045 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 1046#if defined(TARGET_PPC64)
1047 if (ctx->sf_mode)
1048 gen_op_subfic_64(SIMM(ctx->opcode));
1049 else
1050#endif
1051 gen_op_subfic(SIMM(ctx->opcode));
79aceca5 1052 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1053}
1054
d9bce9d9
JM		 1055#if defined(TARGET_PPC64)
1056/* mulhd mulhd. */
a750fc0b 1057GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1058/* mulhdu mulhdu. */
a750fc0b 1059GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1060/* mulld mulld. mulldo mulldo. */
a750fc0b 1061GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1062/* divd divd. divdo divdo. */
a750fc0b 1063GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1064/* divdu divdu. divduo divduo. */
a750fc0b 1065GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1066#endif
1067
79aceca5 1068/*** Integer comparison ***/
d9bce9d9
JM		 1069#if defined(TARGET_PPC64)
1070#define GEN_CMP(name, opc, type) \
1071GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1072{ \
1073 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1074 gen_op_load_gpr_T1(rB(ctx->opcode)); \
e3878283 1075 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
d9bce9d9
JM		 1076 gen_op_##name##_64(); \
1077 else \
1078 gen_op_##name(); \
1079 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1080}
1081#else
1082#define GEN_CMP(name, opc, type) \
1083GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
79aceca5
FB		 1084{ \
1085 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1086 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1087 gen_op_##name(); \
1088 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5 1089}
d9bce9d9 1090#endif
79aceca5
FB		 1091
1092/* cmp */
d9bce9d9 1093GEN_CMP(cmp, 0x00, PPC_INTEGER);
79aceca5
FB		 1094/* cmpi */
1095GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1096{
1097 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9 1098#if defined(TARGET_PPC64)
e3878283 1099 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1100 gen_op_cmpi_64(SIMM(ctx->opcode));
1101 else
1102#endif
1103 gen_op_cmpi(SIMM(ctx->opcode));
79aceca5 1104 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1105}
1106/* cmpl */
d9bce9d9 1107GEN_CMP(cmpl, 0x01, PPC_INTEGER);
79aceca5
FB		 1108/* cmpli */
1109GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1110{
1111 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9 1112#if defined(TARGET_PPC64)
e3878283 1113 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1114 gen_op_cmpli_64(UIMM(ctx->opcode));
1115 else
1116#endif
1117 gen_op_cmpli(UIMM(ctx->opcode));
79aceca5 1118 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1119}
1120
d9bce9d9
JM		 1121/* isel (PowerPC 2.03 specification) */
1122GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1123{
1124 uint32_t bi = rC(ctx->opcode);
1125 uint32_t mask;
1126
1127 if (rA(ctx->opcode) == 0) {
1128 gen_set_T0(0);
1129 } else {
1130 gen_op_load_gpr_T1(rA(ctx->opcode));
1131 }
1132 gen_op_load_gpr_T2(rB(ctx->opcode));
1133 mask = 1 << (3 - (bi & 0x03));
1134 gen_op_load_crf_T0(bi >> 2);
1135 gen_op_test_true(mask);
1136 gen_op_isel();
1137 gen_op_store_T0_gpr(rD(ctx->opcode));
1138}
1139
79aceca5 1140/*** Integer logical ***/
d9bce9d9
JM		 1141#define __GEN_LOGICAL2(name, opc2, opc3, type) \
1142GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
79aceca5
FB		 1143{ \
1144 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1145 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1146 gen_op_##name(); \
79aceca5 1147 gen_op_store_T0_gpr(rA(ctx->opcode)); \
76a66253
JM		 1148 if (unlikely(Rc(ctx->opcode) != 0)) \
1149 gen_set_Rc0(ctx); \
79aceca5 1150}
d9bce9d9
JM		 1151#define GEN_LOGICAL2(name, opc, type) \
1152__GEN_LOGICAL2(name, 0x1C, opc, type)
79aceca5 1153
d9bce9d9
JM		 1154#define GEN_LOGICAL1(name, opc, type) \
1155GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5
FB		 1156{ \
1157 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1158 gen_op_##name(); \
79aceca5 1159 gen_op_store_T0_gpr(rA(ctx->opcode)); \
76a66253
JM		 1160 if (unlikely(Rc(ctx->opcode) != 0)) \
1161 gen_set_Rc0(ctx); \
79aceca5
FB		 1162}
1163
1164/* and & and. */
d9bce9d9 1165GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
79aceca5 1166/* andc & andc. */
d9bce9d9 1167GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
79aceca5 1168/* andi. */
c7697e1f 1169GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5
FB		 1170{
1171 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253 1172 gen_op_andi_T0(UIMM(ctx->opcode));
79aceca5 1173 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253 1174 gen_set_Rc0(ctx);
79aceca5
FB		 1175}
1176/* andis. */
c7697e1f 1177GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5
FB		 1178{
1179 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253 1180 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
79aceca5 1181 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253 1182 gen_set_Rc0(ctx);
79aceca5
FB		 1183}
1184
1185/* cntlzw */
d9bce9d9 1186GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
79aceca5 1187/* eqv & eqv. */
d9bce9d9 1188GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
79aceca5 1189/* extsb & extsb. */
d9bce9d9 1190GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
79aceca5 1191/* extsh & extsh. */
d9bce9d9 1192GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
79aceca5 1193/* nand & nand. */
d9bce9d9 1194GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
79aceca5 1195/* nor & nor. */
d9bce9d9 1196GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
9a64fbe4 1197
79aceca5 1198/* or & or. */
9a64fbe4
FB		 1199GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1200{
76a66253
JM		 1201 int rs, ra, rb;
1202
1203 rs = rS(ctx->opcode);
1204 ra = rA(ctx->opcode);
1205 rb = rB(ctx->opcode);
1206 /* Optimisation for mr. ri case */
1207 if (rs != ra || rs != rb) {
1208 gen_op_load_gpr_T0(rs);
1209 if (rs != rb) {
1210 gen_op_load_gpr_T1(rb);
1211 gen_op_or();
1212 }
1213 gen_op_store_T0_gpr(ra);
1214 if (unlikely(Rc(ctx->opcode) != 0))
1215 gen_set_Rc0(ctx);
1216 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1217 gen_op_load_gpr_T0(rs);
1218 gen_set_Rc0(ctx);
c80f84e3
JM		 1219#if defined(TARGET_PPC64)
1220 } else {
1221 switch (rs) {
1222 case 1:
1223 /* Set process priority to low */
1224 gen_op_store_pri(2);
1225 break;
1226 case 6:
1227 /* Set process priority to medium-low */
1228 gen_op_store_pri(3);
1229 break;
1230 case 2:
1231 /* Set process priority to normal */
1232 gen_op_store_pri(4);
1233 break;
be147d08
JM		 1234#if !defined(CONFIG_USER_ONLY)
1235 case 31:
1236 if (ctx->supervisor > 0) {
1237 /* Set process priority to very low */
1238 gen_op_store_pri(1);
1239 }
1240 break;
1241 case 5:
1242 if (ctx->supervisor > 0) {
1243 /* Set process priority to medium-hight */
1244 gen_op_store_pri(5);
1245 }
1246 break;
1247 case 3:
1248 if (ctx->supervisor > 0) {
1249 /* Set process priority to high */
1250 gen_op_store_pri(6);
1251 }
1252 break;
1253#if defined(TARGET_PPC64H)
1254 case 7:
1255 if (ctx->supervisor > 1) {
1256 /* Set process priority to very high */
1257 gen_op_store_pri(7);
1258 }
1259 break;
1260#endif
1261#endif
c80f84e3
JM		 1262 default:
1263 /* nop */
1264 break;
1265 }
1266#endif
9a64fbe4 1267 }
9a64fbe4
FB		 1268}
1269
79aceca5 1270/* orc & orc. */
d9bce9d9 1271GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
79aceca5 1272/* xor & xor. */
9a64fbe4
FB		 1273GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1274{
1275 gen_op_load_gpr_T0(rS(ctx->opcode));
1276 /* Optimisation for "set to zero" case */
1277 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1278 gen_op_load_gpr_T1(rB(ctx->opcode));
1279 gen_op_xor();
1280 } else {
76a66253 1281 gen_op_reset_T0();
9a64fbe4 1282 }
9a64fbe4 1283 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1284 if (unlikely(Rc(ctx->opcode) != 0))
1285 gen_set_Rc0(ctx);
9a64fbe4 1286}
79aceca5
FB		 1287/* ori */
1288GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1289{
76a66253 1290 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1291
9a64fbe4
FB		 1292 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1293 /* NOP */
76a66253 1294 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1295 return;
76a66253
JM		 1296 }
1297 gen_op_load_gpr_T0(rS(ctx->opcode));
1298 if (likely(uimm != 0))
79aceca5 1299 gen_op_ori(uimm);
76a66253 1300 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1301}
1302/* oris */
1303GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1304{
76a66253 1305 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1306
9a64fbe4
FB		 1307 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1308 /* NOP */
1309 return;
76a66253
JM		 1310 }
1311 gen_op_load_gpr_T0(rS(ctx->opcode));
1312 if (likely(uimm != 0))
79aceca5 1313 gen_op_ori(uimm << 16);
76a66253 1314 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1315}
1316/* xori */
1317GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1318{
76a66253 1319 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1320
1321 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1322 /* NOP */
1323 return;
1324 }
79aceca5 1325 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1326 if (likely(uimm != 0))
1327 gen_op_xori(uimm);
79aceca5 1328 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1329}
1330
1331/* xoris */
1332GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1333{
76a66253 1334 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1335
1336 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1337 /* NOP */
1338 return;
1339 }
79aceca5 1340 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1341 if (likely(uimm != 0))
1342 gen_op_xori(uimm << 16);
79aceca5 1343 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1344}
1345
d9bce9d9
JM		 1346/* popcntb : PowerPC 2.03 specification */
1347GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1348{
1349 gen_op_load_gpr_T0(rS(ctx->opcode));
1350#if defined(TARGET_PPC64)
1351 if (ctx->sf_mode)
1352 gen_op_popcntb_64();
1353 else
1354#endif
1355 gen_op_popcntb();
1356 gen_op_store_T0_gpr(rA(ctx->opcode));
1357}
1358
1359#if defined(TARGET_PPC64)
1360/* extsw & extsw. */
1361GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1362/* cntlzd */
1363GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1364#endif
1365
79aceca5
FB		 1366/*** Integer rotate ***/
1367/* rlwimi & rlwimi. */
1368GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1369{
76a66253
JM		 1370 target_ulong mask;
1371 uint32_t mb, me, sh;
79aceca5
FB		 1372
1373 mb = MB(ctx->opcode);
1374 me = ME(ctx->opcode);
76a66253 1375 sh = SH(ctx->opcode);
76a66253
JM		 1376 if (likely(sh == 0)) {
1377 if (likely(mb == 0 && me == 31)) {
1378 gen_op_load_gpr_T0(rS(ctx->opcode));
1379 goto do_store;
1380 } else if (likely(mb == 31 && me == 0)) {
1381 gen_op_load_gpr_T0(rA(ctx->opcode));
1382 goto do_store;
1383 }
1384 gen_op_load_gpr_T0(rS(ctx->opcode));
1385 gen_op_load_gpr_T1(rA(ctx->opcode));
1386 goto do_mask;
1387 }
79aceca5 1388 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 1389 gen_op_load_gpr_T1(rA(ctx->opcode));
76a66253
JM		 1390 gen_op_rotli32_T0(SH(ctx->opcode));
1391 do_mask:
1392#if defined(TARGET_PPC64)
1393 mb += 32;
1394 me += 32;
1395#endif
1396 mask = MASK(mb, me);
1397 gen_op_andi_T0(mask);
1398 gen_op_andi_T1(~mask);
1399 gen_op_or();
1400 do_store:
79aceca5 1401 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1402 if (unlikely(Rc(ctx->opcode) != 0))
1403 gen_set_Rc0(ctx);
79aceca5
FB		 1404}
1405/* rlwinm & rlwinm. */
1406GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1407{
1408 uint32_t mb, me, sh;
3b46e624 1409
79aceca5
FB		 1410 sh = SH(ctx->opcode);
1411 mb = MB(ctx->opcode);
1412 me = ME(ctx->opcode);
1413 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1414 if (likely(sh == 0)) {
1415 goto do_mask;
1416 }
1417 if (likely(mb == 0)) {
1418 if (likely(me == 31)) {
1419 gen_op_rotli32_T0(sh);
1420 goto do_store;
1421 } else if (likely(me == (31 - sh))) {
1422 gen_op_sli_T0(sh);
1423 goto do_store;
79aceca5 1424 }
76a66253
JM		 1425 } else if (likely(me == 31)) {
1426 if (likely(sh == (32 - mb))) {
1427 gen_op_srli_T0(mb);
1428 goto do_store;
79aceca5
FB		 1429 }
1430 }
76a66253
JM		 1431 gen_op_rotli32_T0(sh);
1432 do_mask:
1433#if defined(TARGET_PPC64)
1434 mb += 32;
1435 me += 32;
1436#endif
1437 gen_op_andi_T0(MASK(mb, me));
1438 do_store:
79aceca5 1439 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1440 if (unlikely(Rc(ctx->opcode) != 0))
1441 gen_set_Rc0(ctx);
79aceca5
FB		 1442}
1443/* rlwnm & rlwnm. */
1444GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1445{
1446 uint32_t mb, me;
1447
1448 mb = MB(ctx->opcode);
1449 me = ME(ctx->opcode);
1450 gen_op_load_gpr_T0(rS(ctx->opcode));
1451 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 1452 gen_op_rotl32_T0_T1();
1453 if (unlikely(mb != 0 || me != 31)) {
1454#if defined(TARGET_PPC64)
1455 mb += 32;
1456 me += 32;
1457#endif
1458 gen_op_andi_T0(MASK(mb, me));
79aceca5 1459 }
79aceca5 1460 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1461 if (unlikely(Rc(ctx->opcode) != 0))
1462 gen_set_Rc0(ctx);
79aceca5
FB		 1463}
1464
d9bce9d9
JM		 1465#if defined(TARGET_PPC64)
1466#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1467GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1468{ \
1469 gen_##name(ctx, 0); \
1470} \
c7697e1f
JM		 1471GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1472 PPC_64B) \
d9bce9d9
JM		 1473{ \
1474 gen_##name(ctx, 1); \
1475}
1476#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1477GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1478{ \
1479 gen_##name(ctx, 0, 0); \
1480} \
c7697e1f
JM		 1481GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1482 PPC_64B) \
d9bce9d9
JM		 1483{ \
1484 gen_##name(ctx, 0, 1); \
1485} \
c7697e1f
JM		 1486GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1487 PPC_64B) \
d9bce9d9
JM		 1488{ \
1489 gen_##name(ctx, 1, 0); \
1490} \
c7697e1f
JM		 1491GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1492 PPC_64B) \
d9bce9d9
JM		 1493{ \
1494 gen_##name(ctx, 1, 1); \
1495}
51789c41 1496
b068d6a7 1497static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
40d0591e
JM		 1498{
1499 if (mask >> 32)
1500 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1501 else
1502 gen_op_andi_T0(mask);
1503}
1504
b068d6a7 1505static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
40d0591e
JM		 1506{
1507 if (mask >> 32)
1508 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1509 else
1510 gen_op_andi_T1(mask);
1511}
1512
b068d6a7
JM		 1513static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1514 uint32_t me, uint32_t sh)
51789c41
JM		 1515{
1516 gen_op_load_gpr_T0(rS(ctx->opcode));
1517 if (likely(sh == 0)) {
1518 goto do_mask;
1519 }
1520 if (likely(mb == 0)) {
1521 if (likely(me == 63)) {
40d0591e 1522 gen_op_rotli64_T0(sh);
51789c41
JM		 1523 goto do_store;
1524 } else if (likely(me == (63 - sh))) {
1525 gen_op_sli_T0(sh);
1526 goto do_store;
1527 }
1528 } else if (likely(me == 63)) {
1529 if (likely(sh == (64 - mb))) {
40d0591e 1530 gen_op_srli_T0_64(mb);
51789c41
JM		 1531 goto do_store;
1532 }
1533 }
1534 gen_op_rotli64_T0(sh);
1535 do_mask:
40d0591e 1536 gen_andi_T0_64(ctx, MASK(mb, me));
51789c41
JM		 1537 do_store:
1538 gen_op_store_T0_gpr(rA(ctx->opcode));
1539 if (unlikely(Rc(ctx->opcode) != 0))
1540 gen_set_Rc0(ctx);
1541}
d9bce9d9 1542/* rldicl - rldicl. */
b068d6a7 1543static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1544{
51789c41 1545 uint32_t sh, mb;
d9bce9d9 1546
9d53c753
JM		 1547 sh = SH(ctx->opcode) | (shn << 5);
1548 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1549 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1550}
51789c41 1551GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1552/* rldicr - rldicr. */
b068d6a7 1553static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1554{
51789c41 1555 uint32_t sh, me;
d9bce9d9 1556
9d53c753
JM		 1557 sh = SH(ctx->opcode) | (shn << 5);
1558 me = MB(ctx->opcode) | (men << 5);
51789c41 1559 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1560}
51789c41 1561GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1562/* rldic - rldic. */
b068d6a7 1563static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1564{
51789c41 1565 uint32_t sh, mb;
d9bce9d9 1566
9d53c753
JM		 1567 sh = SH(ctx->opcode) | (shn << 5);
1568 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1569 gen_rldinm(ctx, mb, 63 - sh, sh);
1570}
1571GEN_PPC64_R4(rldic, 0x1E, 0x04);
1572
b068d6a7
JM		 1573static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1574 uint32_t me)
51789c41
JM		 1575{
1576 gen_op_load_gpr_T0(rS(ctx->opcode));
1577 gen_op_load_gpr_T1(rB(ctx->opcode));
1578 gen_op_rotl64_T0_T1();
1579 if (unlikely(mb != 0 || me != 63)) {
40d0591e 1580 gen_andi_T0_64(ctx, MASK(mb, me));
51789c41
JM		 1581 }
1582 gen_op_store_T0_gpr(rA(ctx->opcode));
1583 if (unlikely(Rc(ctx->opcode) != 0))
1584 gen_set_Rc0(ctx);
d9bce9d9 1585}
51789c41 1586
d9bce9d9 1587/* rldcl - rldcl. */
b068d6a7 1588static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1589{
51789c41 1590 uint32_t mb;
d9bce9d9 1591
9d53c753 1592 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1593 gen_rldnm(ctx, mb, 63);
d9bce9d9 1594}
36081602 1595GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1596/* rldcr - rldcr. */
b068d6a7 1597static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1598{
51789c41 1599 uint32_t me;
d9bce9d9 1600
9d53c753 1601 me = MB(ctx->opcode) | (men << 5);
51789c41 1602 gen_rldnm(ctx, 0, me);
d9bce9d9 1603}
36081602 1604GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1605/* rldimi - rldimi. */
b068d6a7 1606static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1607{
51789c41
JM		 1608 uint64_t mask;
1609 uint32_t sh, mb;
d9bce9d9 1610
9d53c753
JM		 1611 sh = SH(ctx->opcode) | (shn << 5);
1612 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1613 if (likely(sh == 0)) {
1614 if (likely(mb == 0)) {
1615 gen_op_load_gpr_T0(rS(ctx->opcode));
1616 goto do_store;
1617 } else if (likely(mb == 63)) {
1618 gen_op_load_gpr_T0(rA(ctx->opcode));
1619 goto do_store;
1620 }
1621 gen_op_load_gpr_T0(rS(ctx->opcode));
1622 gen_op_load_gpr_T1(rA(ctx->opcode));
1623 goto do_mask;
1624 }
1625 gen_op_load_gpr_T0(rS(ctx->opcode));
1626 gen_op_load_gpr_T1(rA(ctx->opcode));
40d0591e 1627 gen_op_rotli64_T0(sh);
51789c41
JM		 1628 do_mask:
1629 mask = MASK(mb, 63 - sh);
40d0591e
JM		 1630 gen_andi_T0_64(ctx, mask);
1631 gen_andi_T1_64(ctx, ~mask);
51789c41
JM		 1632 gen_op_or();
1633 do_store:
1634 gen_op_store_T0_gpr(rA(ctx->opcode));
1635 if (unlikely(Rc(ctx->opcode) != 0))
1636 gen_set_Rc0(ctx);
d9bce9d9 1637}
36081602 1638GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1639#endif
1640
79aceca5
FB		 1641/*** Integer shift ***/
1642/* slw & slw. */
d9bce9d9 1643__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
79aceca5 1644/* sraw & sraw. */
d9bce9d9 1645__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
79aceca5
FB		 1646/* srawi & srawi. */
1647GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1648{
d9bce9d9 1649 int mb, me;
79aceca5 1650 gen_op_load_gpr_T0(rS(ctx->opcode));
d9bce9d9
JM		 1651 if (SH(ctx->opcode) != 0) {
1652 gen_op_move_T1_T0();
1653 mb = 32 - SH(ctx->opcode);
1654 me = 31;
1655#if defined(TARGET_PPC64)
1656 mb += 32;
1657 me += 32;
1658#endif
1659 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1660 }
79aceca5 1661 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1662 if (unlikely(Rc(ctx->opcode) != 0))
1663 gen_set_Rc0(ctx);
79aceca5
FB		 1664}
1665/* srw & srw. */
d9bce9d9
JM		 1666__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1667
1668#if defined(TARGET_PPC64)
1669/* sld & sld. */
1670__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1671/* srad & srad. */
1672__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1673/* sradi & sradi. */
b068d6a7 1674static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9
JM		 1675{
1676 uint64_t mask;
1677 int sh, mb, me;
1678
1679 gen_op_load_gpr_T0(rS(ctx->opcode));
1680 sh = SH(ctx->opcode) + (n << 5);
1681 if (sh != 0) {
1682 gen_op_move_T1_T0();
1683 mb = 64 - SH(ctx->opcode);
1684 me = 63;
1685 mask = MASK(mb, me);
1686 gen_op_sradi(sh, mask >> 32, mask);
1687 }
1688 gen_op_store_T0_gpr(rA(ctx->opcode));
1689 if (unlikely(Rc(ctx->opcode) != 0))
1690 gen_set_Rc0(ctx);
1691}
c7697e1f 1692GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1693{
1694 gen_sradi(ctx, 0);
1695}
c7697e1f 1696GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1697{
1698 gen_sradi(ctx, 1);
1699}
1700/* srd & srd. */
1701__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1702#endif
79aceca5
FB		 1703
1704/*** Floating-Point arithmetic ***/
7c58044c 1705#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1706GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1707{ \
76a66253 1708 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1709 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1710 return; \
1711 } \
9a64fbe4
FB		 1712 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1713 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1714 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
7c58044c 1715 gen_reset_fpstatus(); \
4ecc3190
FB		 1716 gen_op_f##op(); \
1717 if (isfloat) { \
1718 gen_op_frsp(); \
1719 } \
9a64fbe4 1720 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1721 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1722}
1723
7c58044c
JM		 1724#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1725_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1726_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1727
7c58044c
JM		 1728#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1729GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1730{ \
76a66253 1731 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1732 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1733 return; \
1734 } \
9a64fbe4
FB		 1735 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1736 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
7c58044c 1737 gen_reset_fpstatus(); \
4ecc3190
FB		 1738 gen_op_f##op(); \
1739 if (isfloat) { \
1740 gen_op_frsp(); \
1741 } \
9a64fbe4 1742 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1743 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1744}
7c58044c
JM		 1745#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1746_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1747_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1748
7c58044c
JM		 1749#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1750GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1751{ \
76a66253 1752 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1753 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1754 return; \
1755 } \
9a64fbe4
FB		 1756 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1757 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
7c58044c 1758 gen_reset_fpstatus(); \
4ecc3190
FB		 1759 gen_op_f##op(); \
1760 if (isfloat) { \
1761 gen_op_frsp(); \
1762 } \
9a64fbe4 1763 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1764 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1765}
7c58044c
JM		 1766#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1767_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1768_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1769
7c58044c 1770#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 1771GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 1772{ \
76a66253 1773 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1774 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1775 return; \
1776 } \
9a64fbe4 1777 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
7c58044c 1778 gen_reset_fpstatus(); \
9a64fbe4
FB		 1779 gen_op_f##name(); \
1780 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1781 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1782}
1783
7c58044c 1784#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 1785GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 1786{ \
76a66253 1787 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1788 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1789 return; \
1790 } \
9a64fbe4 1791 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
7c58044c 1792 gen_reset_fpstatus(); \
9a64fbe4
FB		 1793 gen_op_f##name(); \
1794 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1795 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1796}
1797
9a64fbe4 1798/* fadd - fadds */
7c58044c 1799GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1800/* fdiv - fdivs */
7c58044c 1801GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1802/* fmul - fmuls */
7c58044c 1803GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 1804
d7e4b87e 1805/* fre */
7c58044c 1806GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 1807
a750fc0b 1808/* fres */
7c58044c 1809GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 1810
a750fc0b 1811/* frsqrte */
7c58044c
JM		 1812GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1813
1814/* frsqrtes */
1815static always_inline void gen_op_frsqrtes (void)
1816{
1817 gen_op_frsqrte();
1818 gen_op_frsp();
1819}
1b413d55 1820GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 1821
a750fc0b 1822/* fsel */
7c58044c 1823_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 1824/* fsub - fsubs */
7c58044c 1825GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 1826/* Optional: */
1827/* fsqrt */
a750fc0b 1828GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 1829{
76a66253 1830 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1831 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 1832 return;
1833 }
c7d344af 1834 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 1835 gen_reset_fpstatus();
c7d344af
FB		 1836 gen_op_fsqrt();
1837 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1838 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 1839}
79aceca5 1840
a750fc0b 1841GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 1842{
76a66253 1843 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1844 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1845 return;
1846 }
9a64fbe4 1847 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 1848 gen_reset_fpstatus();
4ecc3190
FB		 1849 gen_op_fsqrt();
1850 gen_op_frsp();
9a64fbe4 1851 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1852 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 1853}
1854
1855/*** Floating-Point multiply-and-add ***/
4ecc3190 1856/* fmadd - fmadds */
7c58044c 1857GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 1858/* fmsub - fmsubs */
7c58044c 1859GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 1860/* fnmadd - fnmadds */
7c58044c 1861GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 1862/* fnmsub - fnmsubs */
7c58044c 1863GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 1864
1865/*** Floating-Point round & convert ***/
1866/* fctiw */
7c58044c 1867GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 1868/* fctiwz */
7c58044c 1869GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 1870/* frsp */
7c58044c 1871GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 1872#if defined(TARGET_PPC64)
1873/* fcfid */
7c58044c 1874GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 1875/* fctid */
7c58044c 1876GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 1877/* fctidz */
7c58044c 1878GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 1879#endif
79aceca5 1880
d7e4b87e 1881/* frin */
7c58044c 1882GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 1883/* friz */
7c58044c 1884GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 1885/* frip */
7c58044c 1886GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 1887/* frim */
7c58044c 1888GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 1889
79aceca5
FB		 1890/*** Floating-Point compare ***/
1891/* fcmpo */
76a66253 1892GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 1893{
76a66253 1894 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1895 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1896 return;
1897 }
9a64fbe4
FB		 1898 gen_op_load_fpr_FT0(rA(ctx->opcode));
1899 gen_op_load_fpr_FT1(rB(ctx->opcode));
7c58044c 1900 gen_reset_fpstatus();
9a64fbe4
FB		 1901 gen_op_fcmpo();
1902 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1903 gen_op_float_check_status();
79aceca5
FB		 1904}
1905
1906/* fcmpu */
76a66253 1907GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 1908{
76a66253 1909 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1910 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1911 return;
1912 }
9a64fbe4
FB		 1913 gen_op_load_fpr_FT0(rA(ctx->opcode));
1914 gen_op_load_fpr_FT1(rB(ctx->opcode));
7c58044c 1915 gen_reset_fpstatus();
9a64fbe4
FB		 1916 gen_op_fcmpu();
1917 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1918 gen_op_float_check_status();
79aceca5
FB		 1919}
1920
9a64fbe4
FB		 1921/*** Floating-point move ***/
1922/* fabs */
7c58044c
JM		 1923/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1924GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 1925
1926/* fmr - fmr. */
7c58044c 1927/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 1928GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1929{
76a66253 1930 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1931 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1932 return;
1933 }
9a64fbe4
FB		 1934 gen_op_load_fpr_FT0(rB(ctx->opcode));
1935 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1936 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 1937}
1938
1939/* fnabs */
7c58044c
JM		 1940/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1941GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 1942/* fneg */
7c58044c
JM		 1943/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1944GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 1945
79aceca5
FB		 1946/*** Floating-Point status & ctrl register ***/
1947/* mcrfs */
1948GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1949{
7c58044c
JM		 1950 int bfa;
1951
76a66253 1952 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1953 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1954 return;
1955 }
7c58044c
JM		 1956 gen_optimize_fprf();
1957 bfa = 4 * (7 - crfS(ctx->opcode));
1958 gen_op_load_fpscr_T0(bfa);
fb0eaffc 1959 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1960 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 1961}
1962
1963/* mffs */
1964GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1965{
76a66253 1966 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1967 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1968 return;
1969 }
7c58044c
JM		 1970 gen_optimize_fprf();
1971 gen_reset_fpstatus();
1972 gen_op_load_fpscr_FT0();
fb0eaffc 1973 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1974 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 1975}
1976
1977/* mtfsb0 */
1978GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1979{
fb0eaffc 1980 uint8_t crb;
3b46e624 1981
76a66253 1982 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1983 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1984 return;
1985 }
7c58044c
JM		 1986 crb = 32 - (crbD(ctx->opcode) >> 2);
1987 gen_optimize_fprf();
1988 gen_reset_fpstatus();
1989 if (likely(crb != 30 && crb != 29))
1990 gen_op_fpscr_resetbit(~(1 << crb));
1991 if (unlikely(Rc(ctx->opcode) != 0)) {
1992 gen_op_load_fpcc();
1993 gen_op_set_Rc0();
1994 }
79aceca5
FB		 1995}
1996
1997/* mtfsb1 */
1998GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1999{
fb0eaffc 2000 uint8_t crb;
3b46e624 2001
76a66253 2002 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2003 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2004 return;
2005 }
7c58044c
JM		 2006 crb = 32 - (crbD(ctx->opcode) >> 2);
2007 gen_optimize_fprf();
2008 gen_reset_fpstatus();
2009 /* XXX: we pretend we can only do IEEE floating-point computations */
2010 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2011 gen_op_fpscr_setbit(crb);
2012 if (unlikely(Rc(ctx->opcode) != 0)) {
2013 gen_op_load_fpcc();
2014 gen_op_set_Rc0();
2015 }
2016 /* We can raise a differed exception */
2017 gen_op_float_check_status();
79aceca5
FB		 2018}
2019
2020/* mtfsf */
2021GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2022{
76a66253 2023 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2024 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2025 return;
2026 }
7c58044c 2027 gen_optimize_fprf();
fb0eaffc 2028 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 2029 gen_reset_fpstatus();
28b6751f 2030 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c
JM		 2031 if (unlikely(Rc(ctx->opcode) != 0)) {
2032 gen_op_load_fpcc();
2033 gen_op_set_Rc0();
2034 }
2035 /* We can raise a differed exception */
2036 gen_op_float_check_status();
79aceca5
FB		 2037}
2038
2039/* mtfsfi */
2040GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2041{
7c58044c
JM		 2042 int bf, sh;
2043
76a66253 2044 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2045 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2046 return;
2047 }
7c58044c
JM		 2048 bf = crbD(ctx->opcode) >> 2;
2049 sh = 7 - bf;
2050 gen_optimize_fprf();
2051 gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2052 gen_reset_fpstatus();
2053 gen_op_store_fpscr(1 << sh);
2054 if (unlikely(Rc(ctx->opcode) != 0)) {
2055 gen_op_load_fpcc();
2056 gen_op_set_Rc0();
2057 }
2058 /* We can raise a differed exception */
2059 gen_op_float_check_status();
79aceca5
FB		 2060}
2061
76a66253
JM		 2062/*** Addressing modes ***/
2063/* Register indirect with immediate index : EA = (rA|0) + SIMM */
b068d6a7
JM		 2064static always_inline void gen_addr_imm_index (DisasContext *ctx,
2065 target_long maskl)
76a66253
JM		 2066{
2067 target_long simm = SIMM(ctx->opcode);
2068
be147d08 2069 simm &= ~maskl;
76a66253 2070 if (rA(ctx->opcode) == 0) {
d9bce9d9 2071 gen_set_T0(simm);
76a66253
JM		 2072 } else {
2073 gen_op_load_gpr_T0(rA(ctx->opcode));
2074 if (likely(simm != 0))
2075 gen_op_addi(simm);
2076 }
a496775f
JM		 2077#ifdef DEBUG_MEMORY_ACCESSES
2078 gen_op_print_mem_EA();
2079#endif
76a66253
JM		 2080}
2081
b068d6a7 2082static always_inline void gen_addr_reg_index (DisasContext *ctx)
76a66253
JM		 2083{
2084 if (rA(ctx->opcode) == 0) {
2085 gen_op_load_gpr_T0(rB(ctx->opcode));
2086 } else {
2087 gen_op_load_gpr_T0(rA(ctx->opcode));
2088 gen_op_load_gpr_T1(rB(ctx->opcode));
2089 gen_op_add();
2090 }
a496775f
JM		 2091#ifdef DEBUG_MEMORY_ACCESSES
2092 gen_op_print_mem_EA();
2093#endif
76a66253
JM		 2094}
2095
b068d6a7 2096static always_inline void gen_addr_register (DisasContext *ctx)
76a66253
JM		 2097{
2098 if (rA(ctx->opcode) == 0) {
2099 gen_op_reset_T0();
2100 } else {
2101 gen_op_load_gpr_T0(rA(ctx->opcode));
2102 }
a496775f
JM		 2103#ifdef DEBUG_MEMORY_ACCESSES
2104 gen_op_print_mem_EA();
2105#endif
76a66253
JM		 2106}
2107
79aceca5 2108/*** Integer load ***/
111bfab3 2109#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
9a64fbe4 2110#if defined(CONFIG_USER_ONLY)
d9bce9d9 2111#if defined(TARGET_PPC64)
2857068e 2112/* User mode only - 64 bits */
111bfab3
FB		 2113#define OP_LD_TABLE(width) \
2114static GenOpFunc *gen_op_l##width[] = { \
2115 &gen_op_l##width##_raw, \
2116 &gen_op_l##width##_le_raw, \
d9bce9d9
JM		 2117 &gen_op_l##width##_64_raw, \
2118 &gen_op_l##width##_le_64_raw, \
111bfab3
FB		 2119};
2120#define OP_ST_TABLE(width) \
2121static GenOpFunc *gen_op_st##width[] = { \
2122 &gen_op_st##width##_raw, \
2123 &gen_op_st##width##_le_raw, \
d9bce9d9
JM		 2124 &gen_op_st##width##_64_raw, \
2125 &gen_op_st##width##_le_64_raw, \
111bfab3
FB		 2126};
2127/* Byte access routine are endian safe */
d9bce9d9
JM		 2128#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2129#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2130#else
2857068e 2131/* User mode only - 32 bits */
d9bce9d9
JM		 2132#define OP_LD_TABLE(width) \
2133static GenOpFunc *gen_op_l##width[] = { \
2134 &gen_op_l##width##_raw, \
2135 &gen_op_l##width##_le_raw, \
2136};
2137#define OP_ST_TABLE(width) \
2138static GenOpFunc *gen_op_st##width[] = { \
2139 &gen_op_st##width##_raw, \
2140 &gen_op_st##width##_le_raw, \
2141};
2142#endif
2143/* Byte access routine are endian safe */
111bfab3
FB		 2144#define gen_op_stb_le_raw gen_op_stb_raw
2145#define gen_op_lbz_le_raw gen_op_lbz_raw
9a64fbe4 2146#else
d9bce9d9 2147#if defined(TARGET_PPC64)
2857068e
JM		 2148#if defined(TARGET_PPC64H)
2149/* Full system - 64 bits with hypervisor mode */
9a64fbe4
FB		 2150#define OP_LD_TABLE(width) \
2151static GenOpFunc *gen_op_l##width[] = { \
2152 &gen_op_l##width##_user, \
111bfab3 2153 &gen_op_l##width##_le_user, \
d9bce9d9
JM		 2154 &gen_op_l##width##_64_user, \
2155 &gen_op_l##width##_le_64_user, \
2857068e
JM		 2156 &gen_op_l##width##_kernel, \
2157 &gen_op_l##width##_le_kernel, \
d9bce9d9
JM		 2158 &gen_op_l##width##_64_kernel, \
2159 &gen_op_l##width##_le_64_kernel, \
2857068e
JM		 2160 &gen_op_l##width##_hypv, \
2161 &gen_op_l##width##_le_hypv, \
2162 &gen_op_l##width##_64_hypv, \
2163 &gen_op_l##width##_le_64_hypv, \
111bfab3 2164};
9a64fbe4
FB		 2165#define OP_ST_TABLE(width) \
2166static GenOpFunc *gen_op_st##width[] = { \
2167 &gen_op_st##width##_user, \
111bfab3 2168 &gen_op_st##width##_le_user, \
2857068e
JM		 2169 &gen_op_st##width##_64_user, \
2170 &gen_op_st##width##_le_64_user, \
9a64fbe4 2171 &gen_op_st##width##_kernel, \
111bfab3 2172 &gen_op_st##width##_le_kernel, \
2857068e
JM		 2173 &gen_op_st##width##_64_kernel, \
2174 &gen_op_st##width##_le_64_kernel, \
2175 &gen_op_st##width##_hypv, \
2176 &gen_op_st##width##_le_hypv, \
2177 &gen_op_st##width##_64_hypv, \
2178 &gen_op_st##width##_le_64_hypv, \
2179};
2180/* Byte access routine are endian safe */
2181#define gen_op_stb_le_hypv gen_op_stb_64_hypv
2182#define gen_op_lbz_le_hypv gen_op_lbz_64_hypv
2183#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2184#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2185#else
2186/* Full system - 64 bits */
2187#define OP_LD_TABLE(width) \
2188static GenOpFunc *gen_op_l##width[] = { \
2189 &gen_op_l##width##_user, \
2190 &gen_op_l##width##_le_user, \
2191 &gen_op_l##width##_64_user, \
2192 &gen_op_l##width##_le_64_user, \
2193 &gen_op_l##width##_kernel, \
2194 &gen_op_l##width##_le_kernel, \
2195 &gen_op_l##width##_64_kernel, \
2196 &gen_op_l##width##_le_64_kernel, \
2197};
2198#define OP_ST_TABLE(width) \
2199static GenOpFunc *gen_op_st##width[] = { \
2200 &gen_op_st##width##_user, \
2201 &gen_op_st##width##_le_user, \
d9bce9d9
JM		 2202 &gen_op_st##width##_64_user, \
2203 &gen_op_st##width##_le_64_user, \
2857068e
JM		 2204 &gen_op_st##width##_kernel, \
2205 &gen_op_st##width##_le_kernel, \
d9bce9d9
JM		 2206 &gen_op_st##width##_64_kernel, \
2207 &gen_op_st##width##_le_64_kernel, \
111bfab3 2208};
2857068e 2209#endif
111bfab3 2210/* Byte access routine are endian safe */
2857068e
JM		 2211#define gen_op_stb_le_64_user gen_op_stb_64_user
2212#define gen_op_lbz_le_64_user gen_op_lbz_64_user
d9bce9d9
JM		 2213#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2214#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2215#else
2857068e 2216/* Full system - 32 bits */
d9bce9d9
JM		 2217#define OP_LD_TABLE(width) \
2218static GenOpFunc *gen_op_l##width[] = { \
2219 &gen_op_l##width##_user, \
2220 &gen_op_l##width##_le_user, \
2221 &gen_op_l##width##_kernel, \
2222 &gen_op_l##width##_le_kernel, \
2223};
2224#define OP_ST_TABLE(width) \
2225static GenOpFunc *gen_op_st##width[] = { \
2226 &gen_op_st##width##_user, \
2227 &gen_op_st##width##_le_user, \
2228 &gen_op_st##width##_kernel, \
2229 &gen_op_st##width##_le_kernel, \
2230};
2231#endif
2232/* Byte access routine are endian safe */
2857068e
JM		 2233#define gen_op_stb_le_user gen_op_stb_user
2234#define gen_op_lbz_le_user gen_op_lbz_user
111bfab3
FB		 2235#define gen_op_stb_le_kernel gen_op_stb_kernel
2236#define gen_op_lbz_le_kernel gen_op_lbz_kernel
9a64fbe4
FB		 2237#endif
2238
d9bce9d9
JM		 2239#define GEN_LD(width, opc, type) \
2240GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2241{ \
9d53c753 2242 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2243 op_ldst(l##width); \
79aceca5 2244 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 2245}
2246
d9bce9d9
JM		 2247#define GEN_LDU(width, opc, type) \
2248GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2249{ \
76a66253
JM		 2250 if (unlikely(rA(ctx->opcode) == 0 || \
2251 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2252 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2253 return; \
9a64fbe4 2254 } \
9d53c753 2255 if (type == PPC_64B) \
be147d08 2256 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2257 else \
2258 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2259 op_ldst(l##width); \
79aceca5
FB		 2260 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2261 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2262}
2263
d9bce9d9
JM		 2264#define GEN_LDUX(width, opc2, opc3, type) \
2265GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2266{ \
76a66253
JM		 2267 if (unlikely(rA(ctx->opcode) == 0 || \
2268 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2269 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2270 return; \
9a64fbe4 2271 } \
76a66253 2272 gen_addr_reg_index(ctx); \
9a64fbe4 2273 op_ldst(l##width); \
79aceca5
FB		 2274 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2275 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2276}
2277
d9bce9d9
JM		 2278#define GEN_LDX(width, opc2, opc3, type) \
2279GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2280{ \
76a66253 2281 gen_addr_reg_index(ctx); \
9a64fbe4 2282 op_ldst(l##width); \
79aceca5 2283 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 2284}
2285
d9bce9d9 2286#define GEN_LDS(width, op, type) \
9a64fbe4 2287OP_LD_TABLE(width); \
d9bce9d9
JM		 2288GEN_LD(width, op | 0x20, type); \
2289GEN_LDU(width, op | 0x21, type); \
2290GEN_LDUX(width, 0x17, op | 0x01, type); \
2291GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2292
2293/* lbz lbzu lbzux lbzx */
d9bce9d9 2294GEN_LDS(bz, 0x02, PPC_INTEGER);
79aceca5 2295/* lha lhau lhaux lhax */
d9bce9d9 2296GEN_LDS(ha, 0x0A, PPC_INTEGER);
79aceca5 2297/* lhz lhzu lhzux lhzx */
d9bce9d9 2298GEN_LDS(hz, 0x08, PPC_INTEGER);
79aceca5 2299/* lwz lwzu lwzux lwzx */
d9bce9d9
JM		 2300GEN_LDS(wz, 0x00, PPC_INTEGER);
2301#if defined(TARGET_PPC64)
2302OP_LD_TABLE(wa);
2303OP_LD_TABLE(d);
2304/* lwaux */
2305GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2306/* lwax */
2307GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2308/* ldux */
2309GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2310/* ldx */
2311GEN_LDX(d, 0x15, 0x00, PPC_64B);
2312GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2313{
2314 if (Rc(ctx->opcode)) {
2315 if (unlikely(rA(ctx->opcode) == 0 ||
2316 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2317 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2318 return;
2319 }
2320 }
be147d08 2321 gen_addr_imm_index(ctx, 0x03);
d9bce9d9
JM		 2322 if (ctx->opcode & 0x02) {
2323 /* lwa (lwau is undefined) */
2324 op_ldst(lwa);
2325 } else {
2326 /* ld - ldu */
2327 op_ldst(ld);
2328 }
2329 gen_op_store_T1_gpr(rD(ctx->opcode));
2330 if (Rc(ctx->opcode))
2331 gen_op_store_T0_gpr(rA(ctx->opcode));
2332}
be147d08
JM		 2333/* lq */
2334GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2335{
2336#if defined(CONFIG_USER_ONLY)
2337 GEN_EXCP_PRIVOPC(ctx);
2338#else
2339 int ra, rd;
2340
2341 /* Restore CPU state */
2342 if (unlikely(ctx->supervisor == 0)) {
2343 GEN_EXCP_PRIVOPC(ctx);
2344 return;
2345 }
2346 ra = rA(ctx->opcode);
2347 rd = rD(ctx->opcode);
2348 if (unlikely((rd & 1) || rd == ra)) {
2349 GEN_EXCP_INVAL(ctx);
2350 return;
2351 }
2352 if (unlikely(ctx->mem_idx & 1)) {
2353 /* Little-endian mode is not handled */
2354 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2355 return;
2356 }
2357 gen_addr_imm_index(ctx, 0x0F);
2358 op_ldst(ld);
2359 gen_op_store_T1_gpr(rd);
2360 gen_op_addi(8);
2361 op_ldst(ld);
2362 gen_op_store_T1_gpr(rd + 1);
2363#endif
2364}
d9bce9d9 2365#endif
79aceca5
FB		 2366
2367/*** Integer store ***/
d9bce9d9
JM		 2368#define GEN_ST(width, opc, type) \
2369GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2370{ \
9d53c753 2371 gen_addr_imm_index(ctx, 0); \
9a64fbe4
FB		 2372 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2373 op_ldst(st##width); \
79aceca5
FB		 2374}
2375
d9bce9d9
JM		 2376#define GEN_STU(width, opc, type) \
2377GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2378{ \
76a66253 2379 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2380 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2381 return; \
9a64fbe4 2382 } \
9d53c753 2383 if (type == PPC_64B) \
be147d08 2384 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2385 else \
2386 gen_addr_imm_index(ctx, 0); \
79aceca5 2387 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 2388 op_ldst(st##width); \
79aceca5 2389 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2390}
2391
d9bce9d9
JM		 2392#define GEN_STUX(width, opc2, opc3, type) \
2393GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2394{ \
76a66253 2395 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2396 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2397 return; \
9a64fbe4 2398 } \
76a66253 2399 gen_addr_reg_index(ctx); \
9a64fbe4
FB		 2400 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2401 op_ldst(st##width); \
79aceca5 2402 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2403}
2404
d9bce9d9
JM		 2405#define GEN_STX(width, opc2, opc3, type) \
2406GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2407{ \
76a66253 2408 gen_addr_reg_index(ctx); \
9a64fbe4
FB		 2409 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2410 op_ldst(st##width); \
79aceca5
FB		 2411}
2412
d9bce9d9 2413#define GEN_STS(width, op, type) \
9a64fbe4 2414OP_ST_TABLE(width); \
d9bce9d9
JM		 2415GEN_ST(width, op | 0x20, type); \
2416GEN_STU(width, op | 0x21, type); \
2417GEN_STUX(width, 0x17, op | 0x01, type); \
2418GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2419
2420/* stb stbu stbux stbx */
d9bce9d9 2421GEN_STS(b, 0x06, PPC_INTEGER);
79aceca5 2422/* sth sthu sthux sthx */
d9bce9d9 2423GEN_STS(h, 0x0C, PPC_INTEGER);
79aceca5 2424/* stw stwu stwux stwx */
d9bce9d9
JM		 2425GEN_STS(w, 0x04, PPC_INTEGER);
2426#if defined(TARGET_PPC64)
2427OP_ST_TABLE(d);
426613db
JM		 2428GEN_STUX(d, 0x15, 0x05, PPC_64B);
2429GEN_STX(d, 0x15, 0x04, PPC_64B);
be147d08 2430GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2431{
be147d08
JM		 2432 int rs;
2433
2434 rs = rS(ctx->opcode);
2435 if ((ctx->opcode & 0x3) == 0x2) {
2436#if defined(CONFIG_USER_ONLY)
2437 GEN_EXCP_PRIVOPC(ctx);
2438#else
2439 /* stq */
2440 if (unlikely(ctx->supervisor == 0)) {
2441 GEN_EXCP_PRIVOPC(ctx);
2442 return;
2443 }
2444 if (unlikely(rs & 1)) {
e1833e1f 2445 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2446 return;
2447 }
be147d08
JM		 2448 if (unlikely(ctx->mem_idx & 1)) {
2449 /* Little-endian mode is not handled */
2450 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2451 return;
2452 }
2453 gen_addr_imm_index(ctx, 0x03);
2454 gen_op_load_gpr_T1(rs);
2455 op_ldst(std);
2456 gen_op_addi(8);
2457 gen_op_load_gpr_T1(rs + 1);
2458 op_ldst(std);
2459#endif
2460 } else {
2461 /* std / stdu */
2462 if (Rc(ctx->opcode)) {
2463 if (unlikely(rA(ctx->opcode) == 0)) {
2464 GEN_EXCP_INVAL(ctx);
2465 return;
2466 }
2467 }
2468 gen_addr_imm_index(ctx, 0x03);
2469 gen_op_load_gpr_T1(rs);
2470 op_ldst(std);
2471 if (Rc(ctx->opcode))
2472 gen_op_store_T0_gpr(rA(ctx->opcode));
d9bce9d9 2473 }
d9bce9d9
JM		 2474}
2475#endif
79aceca5
FB		 2476/*** Integer load and store with byte reverse ***/
2477/* lhbrx */
9a64fbe4 2478OP_LD_TABLE(hbr);
d9bce9d9 2479GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
79aceca5 2480/* lwbrx */
9a64fbe4 2481OP_LD_TABLE(wbr);
d9bce9d9 2482GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
79aceca5 2483/* sthbrx */
9a64fbe4 2484OP_ST_TABLE(hbr);
d9bce9d9 2485GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
79aceca5 2486/* stwbrx */
9a64fbe4 2487OP_ST_TABLE(wbr);
d9bce9d9 2488GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2489
2490/*** Integer load and store multiple ***/
111bfab3 2491#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
d9bce9d9 2492#if defined(CONFIG_USER_ONLY)
2857068e 2493/* User-mode only */
d9bce9d9
JM		 2494static GenOpFunc1 *gen_op_lmw[] = {
2495 &gen_op_lmw_raw,
2496 &gen_op_lmw_le_raw,
2857068e 2497#if defined(TARGET_PPC64)
d9bce9d9
JM		 2498 &gen_op_lmw_64_raw,
2499 &gen_op_lmw_le_64_raw,
2857068e 2500#endif
d9bce9d9
JM		 2501};
2502static GenOpFunc1 *gen_op_stmw[] = {
2857068e
JM		 2503 &gen_op_stmw_raw,
2504 &gen_op_stmw_le_raw,
2505#if defined(TARGET_PPC64)
d9bce9d9
JM		 2506 &gen_op_stmw_64_raw,
2507 &gen_op_stmw_le_64_raw,
2857068e 2508#endif
d9bce9d9
JM		 2509};
2510#else
2857068e
JM		 2511#if defined(TARGET_PPC64)
2512/* Full system - 64 bits mode */
d9bce9d9
JM		 2513static GenOpFunc1 *gen_op_lmw[] = {
2514 &gen_op_lmw_user,
2515 &gen_op_lmw_le_user,
d9bce9d9
JM		 2516 &gen_op_lmw_64_user,
2517 &gen_op_lmw_le_64_user,
2857068e
JM		 2518 &gen_op_lmw_kernel,
2519 &gen_op_lmw_le_kernel,
d9bce9d9
JM		 2520 &gen_op_lmw_64_kernel,
2521 &gen_op_lmw_le_64_kernel,
2857068e
JM		 2522#if defined(TARGET_PPC64H)
2523 &gen_op_lmw_hypv,
2524 &gen_op_lmw_le_hypv,
2525 &gen_op_lmw_64_hypv,
2526 &gen_op_lmw_le_64_hypv,
2527#endif
d9bce9d9
JM		 2528};
2529static GenOpFunc1 *gen_op_stmw[] = {
2530 &gen_op_stmw_user,
2531 &gen_op_stmw_le_user,
d9bce9d9
JM		 2532 &gen_op_stmw_64_user,
2533 &gen_op_stmw_le_64_user,
2857068e
JM		 2534 &gen_op_stmw_kernel,
2535 &gen_op_stmw_le_kernel,
d9bce9d9
JM		 2536 &gen_op_stmw_64_kernel,
2537 &gen_op_stmw_le_64_kernel,
2857068e
JM		 2538#if defined(TARGET_PPC64H)
2539 &gen_op_stmw_hypv,
2540 &gen_op_stmw_le_hypv,
2541 &gen_op_stmw_64_hypv,
2542 &gen_op_stmw_le_64_hypv,
d9bce9d9 2543#endif
111bfab3 2544};
9a64fbe4 2545#else
2857068e 2546/* Full system - 32 bits mode */
9a64fbe4
FB		 2547static GenOpFunc1 *gen_op_lmw[] = {
2548 &gen_op_lmw_user,
111bfab3 2549 &gen_op_lmw_le_user,
9a64fbe4 2550 &gen_op_lmw_kernel,
111bfab3 2551 &gen_op_lmw_le_kernel,
9a64fbe4
FB		 2552};
2553static GenOpFunc1 *gen_op_stmw[] = {
2554 &gen_op_stmw_user,
111bfab3 2555 &gen_op_stmw_le_user,
9a64fbe4 2556 &gen_op_stmw_kernel,
111bfab3 2557 &gen_op_stmw_le_kernel,
9a64fbe4
FB		 2558};
2559#endif
d9bce9d9 2560#endif
9a64fbe4 2561
79aceca5
FB		 2562/* lmw */
2563GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2564{
76a66253 2565 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2566 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2567 gen_addr_imm_index(ctx, 0);
9a64fbe4 2568 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2569}
2570
2571/* stmw */
2572GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2573{
76a66253 2574 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2575 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2576 gen_addr_imm_index(ctx, 0);
9a64fbe4 2577 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2578}
2579
2580/*** Integer load and store strings ***/
9a64fbe4
FB		 2581#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2582#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
d9bce9d9 2583#if defined(CONFIG_USER_ONLY)
2857068e 2584/* User-mode only */
d9bce9d9
JM		 2585static GenOpFunc1 *gen_op_lswi[] = {
2586 &gen_op_lswi_raw,
2587 &gen_op_lswi_le_raw,
2857068e 2588#if defined(TARGET_PPC64)
d9bce9d9
JM		 2589 &gen_op_lswi_64_raw,
2590 &gen_op_lswi_le_64_raw,
2857068e 2591#endif
d9bce9d9
JM		 2592};
2593static GenOpFunc3 *gen_op_lswx[] = {
2594 &gen_op_lswx_raw,
2595 &gen_op_lswx_le_raw,
2857068e 2596#if defined(TARGET_PPC64)
d9bce9d9
JM		 2597 &gen_op_lswx_64_raw,
2598 &gen_op_lswx_le_64_raw,
2857068e 2599#endif
d9bce9d9
JM		 2600};
2601static GenOpFunc1 *gen_op_stsw[] = {
2602 &gen_op_stsw_raw,
2603 &gen_op_stsw_le_raw,
2857068e 2604#if defined(TARGET_PPC64)
d9bce9d9
JM		 2605 &gen_op_stsw_64_raw,
2606 &gen_op_stsw_le_64_raw,
2857068e 2607#endif
d9bce9d9
JM		 2608};
2609#else
2857068e
JM		 2610#if defined(TARGET_PPC64)
2611/* Full system - 64 bits mode */
d9bce9d9
JM		 2612static GenOpFunc1 *gen_op_lswi[] = {
2613 &gen_op_lswi_user,
2614 &gen_op_lswi_le_user,
d9bce9d9
JM		 2615 &gen_op_lswi_64_user,
2616 &gen_op_lswi_le_64_user,
2857068e
JM		 2617 &gen_op_lswi_kernel,
2618 &gen_op_lswi_le_kernel,
d9bce9d9
JM		 2619 &gen_op_lswi_64_kernel,
2620 &gen_op_lswi_le_64_kernel,
2857068e
JM		 2621#if defined(TARGET_PPC64H)
2622 &gen_op_lswi_hypv,
2623 &gen_op_lswi_le_hypv,
2624 &gen_op_lswi_64_hypv,
2625 &gen_op_lswi_le_64_hypv,
2626#endif
d9bce9d9
JM		 2627};
2628static GenOpFunc3 *gen_op_lswx[] = {
2629 &gen_op_lswx_user,
2630 &gen_op_lswx_le_user,
d9bce9d9
JM		 2631 &gen_op_lswx_64_user,
2632 &gen_op_lswx_le_64_user,
2857068e
JM		 2633 &gen_op_lswx_kernel,
2634 &gen_op_lswx_le_kernel,
d9bce9d9
JM		 2635 &gen_op_lswx_64_kernel,
2636 &gen_op_lswx_le_64_kernel,
2857068e
JM		 2637#if defined(TARGET_PPC64H)
2638 &gen_op_lswx_hypv,
2639 &gen_op_lswx_le_hypv,
2640 &gen_op_lswx_64_hypv,
2641 &gen_op_lswx_le_64_hypv,
2642#endif
d9bce9d9
JM		 2643};
2644static GenOpFunc1 *gen_op_stsw[] = {
2645 &gen_op_stsw_user,
2646 &gen_op_stsw_le_user,
d9bce9d9
JM		 2647 &gen_op_stsw_64_user,
2648 &gen_op_stsw_le_64_user,
2857068e
JM		 2649 &gen_op_stsw_kernel,
2650 &gen_op_stsw_le_kernel,
d9bce9d9
JM		 2651 &gen_op_stsw_64_kernel,
2652 &gen_op_stsw_le_64_kernel,
2857068e
JM		 2653#if defined(TARGET_PPC64H)
2654 &gen_op_stsw_hypv,
2655 &gen_op_stsw_le_hypv,
2656 &gen_op_stsw_64_hypv,
2657 &gen_op_stsw_le_64_hypv,
d9bce9d9 2658#endif
111bfab3
FB		 2659};
2660#else
2857068e 2661/* Full system - 32 bits mode */
9a64fbe4
FB		 2662static GenOpFunc1 *gen_op_lswi[] = {
2663 &gen_op_lswi_user,
111bfab3 2664 &gen_op_lswi_le_user,
9a64fbe4 2665 &gen_op_lswi_kernel,
111bfab3 2666 &gen_op_lswi_le_kernel,
9a64fbe4
FB		 2667};
2668static GenOpFunc3 *gen_op_lswx[] = {
2669 &gen_op_lswx_user,
111bfab3 2670 &gen_op_lswx_le_user,
9a64fbe4 2671 &gen_op_lswx_kernel,
111bfab3 2672 &gen_op_lswx_le_kernel,
9a64fbe4
FB		 2673};
2674static GenOpFunc1 *gen_op_stsw[] = {
2675 &gen_op_stsw_user,
111bfab3 2676 &gen_op_stsw_le_user,
9a64fbe4 2677 &gen_op_stsw_kernel,
111bfab3 2678 &gen_op_stsw_le_kernel,
9a64fbe4
FB		 2679};
2680#endif
d9bce9d9 2681#endif
9a64fbe4 2682
79aceca5 2683/* lswi */
3fc6c082 2684/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2685 * rA is in the range of registers to be loaded.
2686 * In an other hand, IBM says this is valid, but rA won't be loaded.
2687 * For now, I'll follow the spec...
2688 */
79aceca5
FB		 2689GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2690{
2691 int nb = NB(ctx->opcode);
2692 int start = rD(ctx->opcode);
9a64fbe4 2693 int ra = rA(ctx->opcode);
79aceca5
FB		 2694 int nr;
2695
2696 if (nb == 0)
2697 nb = 32;
2698 nr = nb / 4;
76a66253
JM		 2699 if (unlikely(((start + nr) > 32 &&
2700 start <= ra && (start + nr - 32) > ra) ||
2701 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 2702 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2703 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2704 return;
297d8e62 2705 }
8dd4983c 2706 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2707 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 2708 gen_addr_register(ctx);
2709 gen_op_set_T1(nb);
9a64fbe4 2710 op_ldsts(lswi, start);
79aceca5
FB		 2711}
2712
2713/* lswx */
2714GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2715{
9a64fbe4
FB		 2716 int ra = rA(ctx->opcode);
2717 int rb = rB(ctx->opcode);
2718
76a66253 2719 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2720 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2721 gen_addr_reg_index(ctx);
9a64fbe4 2722 if (ra == 0) {
9a64fbe4 2723 ra = rb;
79aceca5 2724 }
9a64fbe4
FB		 2725 gen_op_load_xer_bc();
2726 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 2727}
2728
2729/* stswi */
2730GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2731{
4b3686fa
FB		 2732 int nb = NB(ctx->opcode);
2733
76a66253 2734 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2735 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2736 gen_addr_register(ctx);
4b3686fa
FB		 2737 if (nb == 0)
2738 nb = 32;
2739 gen_op_set_T1(nb);
9a64fbe4 2740 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2741}
2742
2743/* stswx */
2744GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2745{
8dd4983c 2746 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 2747 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 2748 gen_addr_reg_index(ctx);
2749 gen_op_load_xer_bc();
9a64fbe4 2750 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2751}
2752
2753/*** Memory synchronisation ***/
2754/* eieio */
0db1b20e 2755GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 2756{
79aceca5
FB		 2757}
2758
2759/* isync */
0db1b20e 2760GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 2761{
e1833e1f 2762 GEN_STOP(ctx);
79aceca5
FB		 2763}
2764
111bfab3
FB		 2765#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2766#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
9a64fbe4 2767#if defined(CONFIG_USER_ONLY)
2857068e 2768/* User-mode only */
111bfab3
FB		 2769static GenOpFunc *gen_op_lwarx[] = {
2770 &gen_op_lwarx_raw,
2771 &gen_op_lwarx_le_raw,
2857068e 2772#if defined(TARGET_PPC64)
d9bce9d9
JM		 2773 &gen_op_lwarx_64_raw,
2774 &gen_op_lwarx_le_64_raw,
2857068e 2775#endif
111bfab3
FB		 2776};
2777static GenOpFunc *gen_op_stwcx[] = {
2778 &gen_op_stwcx_raw,
2779 &gen_op_stwcx_le_raw,
2857068e 2780#if defined(TARGET_PPC64)
d9bce9d9
JM		 2781 &gen_op_stwcx_64_raw,
2782 &gen_op_stwcx_le_64_raw,
2857068e 2783#endif
111bfab3 2784};
9a64fbe4 2785#else
2857068e
JM		 2786#if defined(TARGET_PPC64)
2787/* Full system - 64 bits mode */
985a19d6
FB		 2788static GenOpFunc *gen_op_lwarx[] = {
2789 &gen_op_lwarx_user,
111bfab3 2790 &gen_op_lwarx_le_user,
d9bce9d9
JM		 2791 &gen_op_lwarx_64_user,
2792 &gen_op_lwarx_le_64_user,
2857068e
JM		 2793 &gen_op_lwarx_kernel,
2794 &gen_op_lwarx_le_kernel,
d9bce9d9
JM		 2795 &gen_op_lwarx_64_kernel,
2796 &gen_op_lwarx_le_64_kernel,
2857068e
JM		 2797#if defined(TARGET_PPC64H)
2798 &gen_op_lwarx_hypv,
2799 &gen_op_lwarx_le_hypv,
2800 &gen_op_lwarx_64_hypv,
2801 &gen_op_lwarx_le_64_hypv,
2802#endif
985a19d6 2803};
9a64fbe4
FB		 2804static GenOpFunc *gen_op_stwcx[] = {
2805 &gen_op_stwcx_user,
111bfab3 2806 &gen_op_stwcx_le_user,
d9bce9d9
JM		 2807 &gen_op_stwcx_64_user,
2808 &gen_op_stwcx_le_64_user,
2857068e
JM		 2809 &gen_op_stwcx_kernel,
2810 &gen_op_stwcx_le_kernel,
d9bce9d9
JM		 2811 &gen_op_stwcx_64_kernel,
2812 &gen_op_stwcx_le_64_kernel,
2857068e
JM		 2813#if defined(TARGET_PPC64H)
2814 &gen_op_stwcx_hypv,
2815 &gen_op_stwcx_le_hypv,
2816 &gen_op_stwcx_64_hypv,
2817 &gen_op_stwcx_le_64_hypv,
9a64fbe4 2818#endif
d9bce9d9
JM		 2819};
2820#else
2857068e 2821/* Full system - 32 bits mode */
d9bce9d9
JM		 2822static GenOpFunc *gen_op_lwarx[] = {
2823 &gen_op_lwarx_user,
2824 &gen_op_lwarx_le_user,
2825 &gen_op_lwarx_kernel,
2826 &gen_op_lwarx_le_kernel,
2827};
2828static GenOpFunc *gen_op_stwcx[] = {
2829 &gen_op_stwcx_user,
2830 &gen_op_stwcx_le_user,
2831 &gen_op_stwcx_kernel,
2832 &gen_op_stwcx_le_kernel,
2833};
2834#endif
2835#endif
9a64fbe4 2836
111bfab3 2837/* lwarx */
76a66253 2838GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 2839{
30032c94
JM		 2840 /* NIP cannot be restored if the memory exception comes from an helper */
2841 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2842 gen_addr_reg_index(ctx);
985a19d6 2843 op_lwarx();
79aceca5 2844 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 2845}
2846
2847/* stwcx. */
c7697e1f 2848GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 2849{
30032c94
JM		 2850 /* NIP cannot be restored if the memory exception comes from an helper */
2851 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2852 gen_addr_reg_index(ctx);
9a64fbe4
FB		 2853 gen_op_load_gpr_T1(rS(ctx->opcode));
2854 op_stwcx();
79aceca5
FB		 2855}
2856
426613db
JM		 2857#if defined(TARGET_PPC64)
2858#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2859#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2860#if defined(CONFIG_USER_ONLY)
2857068e 2861/* User-mode only */
426613db
JM		 2862static GenOpFunc *gen_op_ldarx[] = {
2863 &gen_op_ldarx_raw,
2864 &gen_op_ldarx_le_raw,
2865 &gen_op_ldarx_64_raw,
2866 &gen_op_ldarx_le_64_raw,
2867};
2868static GenOpFunc *gen_op_stdcx[] = {
2869 &gen_op_stdcx_raw,
2870 &gen_op_stdcx_le_raw,
2871 &gen_op_stdcx_64_raw,
2872 &gen_op_stdcx_le_64_raw,
2873};
2874#else
2857068e 2875/* Full system */
426613db
JM		 2876static GenOpFunc *gen_op_ldarx[] = {
2877 &gen_op_ldarx_user,
2878 &gen_op_ldarx_le_user,
426613db
JM		 2879 &gen_op_ldarx_64_user,
2880 &gen_op_ldarx_le_64_user,
2857068e
JM		 2881 &gen_op_ldarx_kernel,
2882 &gen_op_ldarx_le_kernel,
426613db
JM		 2883 &gen_op_ldarx_64_kernel,
2884 &gen_op_ldarx_le_64_kernel,
2857068e
JM		 2885#if defined(TARGET_PPC64H)
2886 &gen_op_ldarx_hypv,
2887 &gen_op_ldarx_le_hypv,
2888 &gen_op_ldarx_64_hypv,
2889 &gen_op_ldarx_le_64_hypv,
2890#endif
426613db
JM		 2891};
2892static GenOpFunc *gen_op_stdcx[] = {
2893 &gen_op_stdcx_user,
2894 &gen_op_stdcx_le_user,
426613db
JM		 2895 &gen_op_stdcx_64_user,
2896 &gen_op_stdcx_le_64_user,
2857068e
JM		 2897 &gen_op_stdcx_kernel,
2898 &gen_op_stdcx_le_kernel,
426613db
JM		 2899 &gen_op_stdcx_64_kernel,
2900 &gen_op_stdcx_le_64_kernel,
2857068e
JM		 2901#if defined(TARGET_PPC64H)
2902 &gen_op_stdcx_hypv,
2903 &gen_op_stdcx_le_hypv,
2904 &gen_op_stdcx_64_hypv,
2905 &gen_op_stdcx_le_64_hypv,
2906#endif
426613db
JM		 2907};
2908#endif
2909
2910/* ldarx */
a750fc0b 2911GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 2912{
30032c94
JM		 2913 /* NIP cannot be restored if the memory exception comes from an helper */
2914 gen_update_nip(ctx, ctx->nip - 4);
426613db
JM		 2915 gen_addr_reg_index(ctx);
2916 op_ldarx();
2917 gen_op_store_T1_gpr(rD(ctx->opcode));
2918}
2919
2920/* stdcx. */
c7697e1f 2921GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 2922{
30032c94
JM		 2923 /* NIP cannot be restored if the memory exception comes from an helper */
2924 gen_update_nip(ctx, ctx->nip - 4);
426613db
JM		 2925 gen_addr_reg_index(ctx);
2926 gen_op_load_gpr_T1(rS(ctx->opcode));
2927 op_stdcx();
2928}
2929#endif /* defined(TARGET_PPC64) */
2930
79aceca5 2931/* sync */
a902d886 2932GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 2933{
79aceca5
FB		 2934}
2935
0db1b20e
JM		 2936/* wait */
2937GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2938{
2939 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 2940 gen_op_wait();
2941 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 2942}
2943
79aceca5 2944/*** Floating-point load ***/
477023a6
JM		 2945#define GEN_LDF(width, opc, type) \
2946GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2947{ \
76a66253 2948 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2949 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2950 return; \
2951 } \
9d53c753 2952 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2953 op_ldst(l##width); \
76a66253 2954 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5
FB		 2955}
2956
477023a6
JM		 2957#define GEN_LDUF(width, opc, type) \
2958GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2959{ \
76a66253 2960 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2961 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2962 return; \
2963 } \
76a66253 2964 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2965 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2966 return; \
9a64fbe4 2967 } \
9d53c753 2968 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2969 op_ldst(l##width); \
76a66253 2970 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5 2971 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2972}
2973
477023a6
JM		 2974#define GEN_LDUXF(width, opc, type) \
2975GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2976{ \
76a66253 2977 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2978 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2979 return; \
2980 } \
76a66253 2981 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2982 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2983 return; \
9a64fbe4 2984 } \
76a66253 2985 gen_addr_reg_index(ctx); \
9a64fbe4 2986 op_ldst(l##width); \
76a66253 2987 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5 2988 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2989}
2990
477023a6
JM		 2991#define GEN_LDXF(width, opc2, opc3, type) \
2992GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2993{ \
76a66253 2994 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2995 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2996 return; \
2997 } \
76a66253 2998 gen_addr_reg_index(ctx); \
9a64fbe4 2999 op_ldst(l##width); \
76a66253 3000 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5
FB		 3001}
3002
477023a6 3003#define GEN_LDFS(width, op, type) \
9a64fbe4 3004OP_LD_TABLE(width); \
477023a6
JM		 3005GEN_LDF(width, op | 0x20, type); \
3006GEN_LDUF(width, op | 0x21, type); \
3007GEN_LDUXF(width, op | 0x01, type); \
3008GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3009
3010/* lfd lfdu lfdux lfdx */
477023a6 3011GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 3012/* lfs lfsu lfsux lfsx */
477023a6 3013GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3014
3015/*** Floating-point store ***/
477023a6
JM		 3016#define GEN_STF(width, opc, type) \
3017GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3018{ \
76a66253 3019 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3020 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3021 return; \
3022 } \
9d53c753 3023 gen_addr_imm_index(ctx, 0); \
76a66253 3024 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 3025 op_ldst(st##width); \
79aceca5
FB		 3026}
3027
477023a6
JM		 3028#define GEN_STUF(width, opc, type) \
3029GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3030{ \
76a66253 3031 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3032 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3033 return; \
3034 } \
76a66253 3035 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3036 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3037 return; \
9a64fbe4 3038 } \
9d53c753 3039 gen_addr_imm_index(ctx, 0); \
76a66253 3040 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 3041 op_ldst(st##width); \
79aceca5 3042 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 3043}
3044
477023a6
JM		 3045#define GEN_STUXF(width, opc, type) \
3046GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3047{ \
76a66253 3048 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3049 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3050 return; \
3051 } \
76a66253 3052 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3053 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3054 return; \
9a64fbe4 3055 } \
76a66253
JM		 3056 gen_addr_reg_index(ctx); \
3057 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 3058 op_ldst(st##width); \
79aceca5 3059 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 3060}
3061
477023a6
JM		 3062#define GEN_STXF(width, opc2, opc3, type) \
3063GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3064{ \
76a66253 3065 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3066 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3067 return; \
3068 } \
76a66253
JM		 3069 gen_addr_reg_index(ctx); \
3070 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 3071 op_ldst(st##width); \
79aceca5
FB		 3072}
3073
477023a6 3074#define GEN_STFS(width, op, type) \
9a64fbe4 3075OP_ST_TABLE(width); \
477023a6
JM		 3076GEN_STF(width, op | 0x20, type); \
3077GEN_STUF(width, op | 0x21, type); \
3078GEN_STUXF(width, op | 0x01, type); \
3079GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3080
3081/* stfd stfdu stfdux stfdx */
477023a6 3082GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 3083/* stfs stfsu stfsux stfsx */
477023a6 3084GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3085
3086/* Optional: */
3087/* stfiwx */
477023a6
JM		 3088OP_ST_TABLE(fiwx);
3089GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3090
3091/*** Branch ***/
b068d6a7
JM		 3092static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3093 target_ulong dest)
c1942362
FB		 3094{
3095 TranslationBlock *tb;
3096 tb = ctx->tb;
3097 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3098 if (n == 0)
3099 gen_op_goto_tb0(TBPARAM(tb));
3100 else
3101 gen_op_goto_tb1(TBPARAM(tb));
d9bce9d9
JM		 3102 gen_set_T1(dest);
3103#if defined(TARGET_PPC64)
3104 if (ctx->sf_mode)
3105 gen_op_b_T1_64();
3106 else
3107#endif
3108 gen_op_b_T1();
c1942362 3109 gen_op_set_T0((long)tb + n);
ea4e754f
FB		 3110 if (ctx->singlestep_enabled)
3111 gen_op_debug();
c1942362
FB		 3112 gen_op_exit_tb();
3113 } else {
d9bce9d9
JM		 3114 gen_set_T1(dest);
3115#if defined(TARGET_PPC64)
3116 if (ctx->sf_mode)
3117 gen_op_b_T1_64();
3118 else
3119#endif
3120 gen_op_b_T1();
76a66253 3121 gen_op_reset_T0();
ea4e754f
FB		 3122 if (ctx->singlestep_enabled)
3123 gen_op_debug();
c1942362
FB		 3124 gen_op_exit_tb();
3125 }
c53be334
FB		 3126}
3127
b068d6a7 3128static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3129{
3130#if defined(TARGET_PPC64)
3131 if (ctx->sf_mode != 0 && (nip >> 32))
3132 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3133 else
3134#endif
3135 gen_op_setlr(ctx->nip);
3136}
3137
79aceca5
FB		 3138/* b ba bl bla */
3139GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3140{
76a66253 3141 target_ulong li, target;
38a64f9d
FB		 3142
3143 /* sign extend LI */
76a66253 3144#if defined(TARGET_PPC64)
d9bce9d9
JM		 3145 if (ctx->sf_mode)
3146 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3147 else
76a66253 3148#endif
d9bce9d9 3149 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3150 if (likely(AA(ctx->opcode) == 0))
046d6672 3151 target = ctx->nip + li - 4;
79aceca5 3152 else
9a64fbe4 3153 target = li;
d9bce9d9 3154#if defined(TARGET_PPC64)
e1833e1f
JM		 3155 if (!ctx->sf_mode)
3156 target = (uint32_t)target;
d9bce9d9 3157#endif
e1833e1f
JM		 3158 if (LK(ctx->opcode))
3159 gen_setlr(ctx, ctx->nip);
c1942362 3160 gen_goto_tb(ctx, 0, target);
e1833e1f 3161 ctx->exception = POWERPC_EXCP_BRANCH;
79aceca5
FB		 3162}
3163
e98a6e40
FB		 3164#define BCOND_IM 0
3165#define BCOND_LR 1
3166#define BCOND_CTR 2
3167
b068d6a7 3168static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3169{
76a66253
JM		 3170 target_ulong target = 0;
3171 target_ulong li;
d9bce9d9
JM		 3172 uint32_t bo = BO(ctx->opcode);
3173 uint32_t bi = BI(ctx->opcode);
3174 uint32_t mask;
e98a6e40 3175
e98a6e40 3176 if ((bo & 0x4) == 0)
d9bce9d9 3177 gen_op_dec_ctr();
e98a6e40
FB		 3178 switch(type) {
3179 case BCOND_IM:
76a66253
JM		 3180 li = (target_long)((int16_t)(BD(ctx->opcode)));
3181 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3182 target = ctx->nip + li - 4;
e98a6e40
FB		 3183 } else {
3184 target = li;
3185 }
e1833e1f
JM		 3186#if defined(TARGET_PPC64)
3187 if (!ctx->sf_mode)
3188 target = (uint32_t)target;
3189#endif
e98a6e40
FB		 3190 break;
3191 case BCOND_CTR:
3192 gen_op_movl_T1_ctr();
3193 break;
3194 default:
3195 case BCOND_LR:
3196 gen_op_movl_T1_lr();
3197 break;
3198 }
e1833e1f
JM		 3199 if (LK(ctx->opcode))
3200 gen_setlr(ctx, ctx->nip);
e98a6e40 3201 if (bo & 0x10) {
d9bce9d9
JM		 3202 /* No CR condition */
3203 switch (bo & 0x6) {
3204 case 0:
3205#if defined(TARGET_PPC64)
3206 if (ctx->sf_mode)
3207 gen_op_test_ctr_64();
3208 else
3209#endif
3210 gen_op_test_ctr();
3211 break;
3212 case 2:
3213#if defined(TARGET_PPC64)
3214 if (ctx->sf_mode)
3215 gen_op_test_ctrz_64();
3216 else
3217#endif
3218 gen_op_test_ctrz();
e98a6e40 3219 break;
e98a6e40 3220 default:
d9bce9d9
JM		 3221 case 4:
3222 case 6:
e98a6e40 3223 if (type == BCOND_IM) {
c1942362 3224 gen_goto_tb(ctx, 0, target);
056b05f8 3225 goto out;
e98a6e40 3226 } else {
d9bce9d9
JM		 3227#if defined(TARGET_PPC64)
3228 if (ctx->sf_mode)
3229 gen_op_b_T1_64();
3230 else
3231#endif
3232 gen_op_b_T1();
76a66253 3233 gen_op_reset_T0();
056b05f8 3234 goto no_test;
e98a6e40 3235 }
056b05f8 3236 break;
e98a6e40 3237 }
d9bce9d9
JM		 3238 } else {
3239 mask = 1 << (3 - (bi & 0x03));
3240 gen_op_load_crf_T0(bi >> 2);
3241 if (bo & 0x8) {
3242 switch (bo & 0x6) {
3243 case 0:
3244#if defined(TARGET_PPC64)
3245 if (ctx->sf_mode)
3246 gen_op_test_ctr_true_64(mask);
3247 else
3248#endif
3249 gen_op_test_ctr_true(mask);
3250 break;
3251 case 2:
3252#if defined(TARGET_PPC64)
3253 if (ctx->sf_mode)
3254 gen_op_test_ctrz_true_64(mask);
3255 else
3256#endif
3257 gen_op_test_ctrz_true(mask);
3258 break;
3259 default:
3260 case 4:
3261 case 6:
e98a6e40 3262 gen_op_test_true(mask);
d9bce9d9
JM		 3263 break;
3264 }
3265 } else {
3266 switch (bo & 0x6) {
3267 case 0:
3268#if defined(TARGET_PPC64)
3269 if (ctx->sf_mode)
3270 gen_op_test_ctr_false_64(mask);
3271 else
3272#endif
3273 gen_op_test_ctr_false(mask);
3b46e624 3274 break;
d9bce9d9
JM		 3275 case 2:
3276#if defined(TARGET_PPC64)
3277 if (ctx->sf_mode)
3278 gen_op_test_ctrz_false_64(mask);
3279 else
3280#endif
3281 gen_op_test_ctrz_false(mask);
3282 break;
e98a6e40 3283 default:
d9bce9d9
JM		 3284 case 4:
3285 case 6:
e98a6e40 3286 gen_op_test_false(mask);
d9bce9d9
JM		 3287 break;
3288 }
3289 }
3290 }
e98a6e40 3291 if (type == BCOND_IM) {
c53be334
FB		 3292 int l1 = gen_new_label();
3293 gen_op_jz_T0(l1);
c1942362 3294 gen_goto_tb(ctx, 0, target);
c53be334 3295 gen_set_label(l1);
c1942362 3296 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3297 } else {
d9bce9d9
JM		 3298#if defined(TARGET_PPC64)
3299 if (ctx->sf_mode)
3300 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3301 else
3302#endif
3303 gen_op_btest_T1(ctx->nip);
76a66253 3304 gen_op_reset_T0();
36081602 3305 no_test:
08e46e54
JM		 3306 if (ctx->singlestep_enabled)
3307 gen_op_debug();
3308 gen_op_exit_tb();
3309 }
056b05f8 3310 out:
e1833e1f 3311 ctx->exception = POWERPC_EXCP_BRANCH;
e98a6e40
FB		 3312}
3313
3314GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3315{
e98a6e40
FB		 3316 gen_bcond(ctx, BCOND_IM);
3317}
3318
3319GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3320{
e98a6e40
FB		 3321 gen_bcond(ctx, BCOND_CTR);
3322}
3323
3324GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3325{
e98a6e40
FB		 3326 gen_bcond(ctx, BCOND_LR);
3327}
79aceca5
FB		 3328
3329/*** Condition register logical ***/
3330#define GEN_CRLOGIC(op, opc) \
3331GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3332{ \
fc0d441e
JM		 3333 uint8_t bitmask; \
3334 int sh; \
79aceca5 3335 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
fc0d441e
JM		 3336 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3337 if (sh > 0) \
3338 gen_op_srli_T0(sh); \
3339 else if (sh < 0) \
3340 gen_op_sli_T0(-sh); \
79aceca5 3341 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
fc0d441e
JM		 3342 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3343 if (sh > 0) \
3344 gen_op_srli_T1(sh); \
3345 else if (sh < 0) \
3346 gen_op_sli_T1(-sh); \
79aceca5 3347 gen_op_##op(); \
fc0d441e
JM		 3348 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3349 gen_op_andi_T0(bitmask); \
79aceca5 3350 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
fc0d441e
JM		 3351 gen_op_andi_T1(~bitmask); \
3352 gen_op_or(); \
3353 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 3354}
3355
3356/* crand */
76a66253 3357GEN_CRLOGIC(and, 0x08);
79aceca5 3358/* crandc */
76a66253 3359GEN_CRLOGIC(andc, 0x04);
79aceca5 3360/* creqv */
76a66253 3361GEN_CRLOGIC(eqv, 0x09);
79aceca5 3362/* crnand */
76a66253 3363GEN_CRLOGIC(nand, 0x07);
79aceca5 3364/* crnor */
76a66253 3365GEN_CRLOGIC(nor, 0x01);
79aceca5 3366/* cror */
76a66253 3367GEN_CRLOGIC(or, 0x0E);
79aceca5 3368/* crorc */
76a66253 3369GEN_CRLOGIC(orc, 0x0D);
79aceca5 3370/* crxor */
76a66253 3371GEN_CRLOGIC(xor, 0x06);
79aceca5
FB		 3372/* mcrf */
3373GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3374{
3375 gen_op_load_crf_T0(crfS(ctx->opcode));
3376 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 3377}
3378
3379/*** System linkage ***/
3380/* rfi (supervisor only) */
76a66253 3381GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3382{
9a64fbe4 3383#if defined(CONFIG_USER_ONLY)
e1833e1f 3384 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3385#else
3386 /* Restore CPU state */
76a66253 3387 if (unlikely(!ctx->supervisor)) {
e1833e1f 3388 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3389 return;
9a64fbe4 3390 }
a42bd6cc 3391 gen_op_rfi();
e1833e1f 3392 GEN_SYNC(ctx);
9a64fbe4 3393#endif
79aceca5
FB		 3394}
3395
426613db 3396#if defined(TARGET_PPC64)
a750fc0b 3397GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3398{
3399#if defined(CONFIG_USER_ONLY)
e1833e1f 3400 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3401#else
3402 /* Restore CPU state */
3403 if (unlikely(!ctx->supervisor)) {
e1833e1f 3404 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3405 return;
3406 }
a42bd6cc 3407 gen_op_rfid();
e1833e1f 3408 GEN_SYNC(ctx);
426613db
JM		 3409#endif
3410}
3411#endif
3412
be147d08
JM		 3413#if defined(TARGET_PPC64H)
3414GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3415{
3416#if defined(CONFIG_USER_ONLY)
3417 GEN_EXCP_PRIVOPC(ctx);
3418#else
3419 /* Restore CPU state */
3420 if (unlikely(ctx->supervisor <= 1)) {
3421 GEN_EXCP_PRIVOPC(ctx);
3422 return;
3423 }
3424 gen_op_hrfid();
3425 GEN_SYNC(ctx);
3426#endif
3427}
3428#endif
3429
79aceca5 3430/* sc */
417bf010
JM		 3431#if defined(CONFIG_USER_ONLY)
3432#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3433#else
3434#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3435#endif
e1833e1f 3436GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3437{
e1833e1f
JM		 3438 uint32_t lev;
3439
3440 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3441 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3442}
3443
3444/*** Trap ***/
3445/* tw */
76a66253 3446GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3447{
9a64fbe4
FB		 3448 gen_op_load_gpr_T0(rA(ctx->opcode));
3449 gen_op_load_gpr_T1(rB(ctx->opcode));
a0ae05aa 3450 /* Update the nip since this might generate a trap exception */
d9bce9d9 3451 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3452 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3453}
3454
3455/* twi */
3456GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3457{
9a64fbe4 3458 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 3459 gen_set_T1(SIMM(ctx->opcode));
3460 /* Update the nip since this might generate a trap exception */
3461 gen_update_nip(ctx, ctx->nip);
76a66253 3462 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3463}
3464
d9bce9d9
JM		 3465#if defined(TARGET_PPC64)
3466/* td */
3467GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3468{
3469 gen_op_load_gpr_T0(rA(ctx->opcode));
3470 gen_op_load_gpr_T1(rB(ctx->opcode));
3471 /* Update the nip since this might generate a trap exception */
3472 gen_update_nip(ctx, ctx->nip);
3473 gen_op_td(TO(ctx->opcode));
3474}
3475
3476/* tdi */
3477GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3478{
3479 gen_op_load_gpr_T0(rA(ctx->opcode));
3480 gen_set_T1(SIMM(ctx->opcode));
3481 /* Update the nip since this might generate a trap exception */
3482 gen_update_nip(ctx, ctx->nip);
3483 gen_op_td(TO(ctx->opcode));
3484}
3485#endif
3486
79aceca5 3487/*** Processor control ***/
79aceca5
FB		 3488/* mcrxr */
3489GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3490{
3491 gen_op_load_xer_cr();
3492 gen_op_store_T0_crf(crfD(ctx->opcode));
e864cabd
JM		 3493 gen_op_clear_xer_ov();
3494 gen_op_clear_xer_ca();
79aceca5
FB		 3495}
3496
3497/* mfcr */
76a66253 3498GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3499{
76a66253 3500 uint32_t crm, crn;
3b46e624 3501
76a66253
JM		 3502 if (likely(ctx->opcode & 0x00100000)) {
3503 crm = CRM(ctx->opcode);
3504 if (likely((crm ^ (crm - 1)) == 0)) {
3505 crn = ffs(crm);
3506 gen_op_load_cro(7 - crn);
3507 }
d9bce9d9
JM		 3508 } else {
3509 gen_op_load_cr();
3510 }
79aceca5 3511 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 3512}
3513
3514/* mfmsr */
3515GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3516{
9a64fbe4 3517#if defined(CONFIG_USER_ONLY)
e1833e1f 3518 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3519#else
76a66253 3520 if (unlikely(!ctx->supervisor)) {
e1833e1f 3521 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3522 return;
9a64fbe4 3523 }
79aceca5
FB		 3524 gen_op_load_msr();
3525 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 3526#endif
79aceca5
FB		 3527}
3528
a11b8151 3529#if 1
6f2d8978 3530#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3531#else
3532static void spr_noaccess (void *opaque, int sprn)
3533{
3534 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3535 printf("ERROR: try to access SPR %d !\n", sprn);
3536}
3537#define SPR_NOACCESS (&spr_noaccess)
3538#endif
3539
79aceca5 3540/* mfspr */
b068d6a7 3541static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3542{
3fc6c082 3543 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3544 uint32_t sprn = SPR(ctx->opcode);
3545
3fc6c082 3546#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3547#if defined(TARGET_PPC64H)
3548 if (ctx->supervisor == 2)
3549 read_cb = ctx->spr_cb[sprn].hea_read;
3550 else
3551#endif
3fc6c082
FB		 3552 if (ctx->supervisor)
3553 read_cb = ctx->spr_cb[sprn].oea_read;
3554 else
9a64fbe4 3555#endif
3fc6c082 3556 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3557 if (likely(read_cb != NULL)) {
3558 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082
FB		 3559 (*read_cb)(ctx, sprn);
3560 gen_op_store_T0_gpr(rD(ctx->opcode));
3561 } else {
3562 /* Privilege exception */
9fceefa7
JM		 3563 /* This is a hack to avoid warnings when running Linux:
3564 * this OS breaks the PowerPC virtualisation model,
3565 * allowing userland application to read the PVR
3566 */
3567 if (sprn != SPR_PVR) {
3568 if (loglevel != 0) {
077fc206
JM		 3569 fprintf(logfile, "Trying to read privileged spr %d %03x at"
3570 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3571 }
077fc206
JM		 3572 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3573 sprn, sprn, ctx->nip);
f24e5695 3574 }
e1833e1f 3575 GEN_EXCP_PRIVREG(ctx);
79aceca5 3576 }
3fc6c082
FB		 3577 } else {
3578 /* Not defined */
4a057712 3579 if (loglevel != 0) {
077fc206
JM		 3580 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3581 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3582 }
077fc206
JM		 3583 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3584 sprn, sprn, ctx->nip);
e1833e1f
JM		 3585 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3586 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3587 }
79aceca5
FB		 3588}
3589
3fc6c082 3590GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3591{
3fc6c082 3592 gen_op_mfspr(ctx);
76a66253 3593}
3fc6c082
FB		 3594
3595/* mftb */
a750fc0b 3596GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3597{
3598 gen_op_mfspr(ctx);
79aceca5
FB		 3599}
3600
3601/* mtcrf */
8dd4983c 3602GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3603{
76a66253 3604 uint32_t crm, crn;
3b46e624 3605
79aceca5 3606 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 3607 crm = CRM(ctx->opcode);
3608 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3609 crn = ffs(crm);
3610 gen_op_srli_T0(crn * 4);
3611 gen_op_andi_T0(0xF);
3612 gen_op_store_cro(7 - crn);
3613 } else {
3614 gen_op_store_cr(crm);
3615 }
79aceca5
FB		 3616}
3617
3618/* mtmsr */
426613db 3619#if defined(TARGET_PPC64)
be147d08 3620GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3621{
3622#if defined(CONFIG_USER_ONLY)
e1833e1f 3623 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3624#else
3625 if (unlikely(!ctx->supervisor)) {
e1833e1f 3626 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3627 return;
3628 }
426613db 3629 gen_op_load_gpr_T0(rS(ctx->opcode));
be147d08
JM		 3630 if (ctx->opcode & 0x00010000) {
3631 /* Special form that does not need any synchronisation */
3632 gen_op_update_riee();
3633 } else {
056b05f8
JM		 3634 /* XXX: we need to update nip before the store
3635 * if we enter power saving mode, we will exit the loop
3636 * directly from ppc_store_msr
3637 */
be147d08
JM		 3638 gen_update_nip(ctx, ctx->nip);
3639 gen_op_store_msr();
3640 /* Must stop the translation as machine state (may have) changed */
3641 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3642 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3643 }
426613db
JM		 3644#endif
3645}
3646#endif
3647
79aceca5
FB		 3648GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3649{
9a64fbe4 3650#if defined(CONFIG_USER_ONLY)
e1833e1f 3651 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3652#else
76a66253 3653 if (unlikely(!ctx->supervisor)) {
e1833e1f 3654 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3655 return;
9a64fbe4 3656 }
79aceca5 3657 gen_op_load_gpr_T0(rS(ctx->opcode));
be147d08
JM		 3658 if (ctx->opcode & 0x00010000) {
3659 /* Special form that does not need any synchronisation */
3660 gen_op_update_riee();
3661 } else {
056b05f8
JM		 3662 /* XXX: we need to update nip before the store
3663 * if we enter power saving mode, we will exit the loop
3664 * directly from ppc_store_msr
3665 */
be147d08 3666 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3667#if defined(TARGET_PPC64)
be147d08
JM		 3668 if (!ctx->sf_mode)
3669 gen_op_store_msr_32();
3670 else
d9bce9d9 3671#endif
be147d08
JM		 3672 gen_op_store_msr();
3673 /* Must stop the translation as machine state (may have) changed */
3674 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3675 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3676 }
9a64fbe4 3677#endif
79aceca5
FB		 3678}
3679
3680/* mtspr */
3681GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3682{
3fc6c082 3683 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3684 uint32_t sprn = SPR(ctx->opcode);
3685
3fc6c082 3686#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3687#if defined(TARGET_PPC64H)
3688 if (ctx->supervisor == 2)
3689 write_cb = ctx->spr_cb[sprn].hea_write;
3690 else
3691#endif
3fc6c082
FB		 3692 if (ctx->supervisor)
3693 write_cb = ctx->spr_cb[sprn].oea_write;
3694 else
9a64fbe4 3695#endif
3fc6c082 3696 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3697 if (likely(write_cb != NULL)) {
3698 if (likely(write_cb != SPR_NOACCESS)) {
3fc6c082
FB		 3699 gen_op_load_gpr_T0(rS(ctx->opcode));
3700 (*write_cb)(ctx, sprn);
3701 } else {
3702 /* Privilege exception */
4a057712 3703 if (loglevel != 0) {
077fc206
JM		 3704 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3705 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3706 }
077fc206
JM		 3707 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3708 sprn, sprn, ctx->nip);
e1833e1f 3709 GEN_EXCP_PRIVREG(ctx);
76a66253 3710 }
3fc6c082
FB		 3711 } else {
3712 /* Not defined */
4a057712 3713 if (loglevel != 0) {
077fc206
JM		 3714 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3715 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3716 }
077fc206
JM		 3717 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3718 sprn, sprn, ctx->nip);
e1833e1f
JM		 3719 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3720 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3721 }
79aceca5
FB		 3722}
3723
3724/*** Cache management ***/
79aceca5 3725/* dcbf */
0db1b20e 3726GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3727{
dac454af 3728 /* XXX: specification says this is treated as a load by the MMU */
76a66253 3729 gen_addr_reg_index(ctx);
a541f297 3730 op_ldst(lbz);
79aceca5
FB		 3731}
3732
3733/* dcbi (Supervisor only) */
9a64fbe4 3734GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3735{
a541f297 3736#if defined(CONFIG_USER_ONLY)
e1833e1f 3737 GEN_EXCP_PRIVOPC(ctx);
a541f297 3738#else
76a66253 3739 if (unlikely(!ctx->supervisor)) {
e1833e1f 3740 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3741 return;
9a64fbe4 3742 }
76a66253
JM		 3743 gen_addr_reg_index(ctx);
3744 /* XXX: specification says this should be treated as a store by the MMU */
dac454af 3745 op_ldst(lbz);
a541f297
FB		 3746 op_ldst(stb);
3747#endif
79aceca5
FB		 3748}
3749
3750/* dcdst */
9a64fbe4 3751GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3752{
76a66253
JM		 3753 /* XXX: specification say this is treated as a load by the MMU */
3754 gen_addr_reg_index(ctx);
a541f297 3755 op_ldst(lbz);
79aceca5
FB		 3756}
3757
3758/* dcbt */
0db1b20e 3759GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3760{
0db1b20e 3761 /* interpreted as no-op */
76a66253
JM		 3762 /* XXX: specification say this is treated as a load by the MMU
3763 * but does not generate any exception
3764 */
79aceca5
FB		 3765}
3766
3767/* dcbtst */
0db1b20e 3768GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3769{
0db1b20e 3770 /* interpreted as no-op */
76a66253
JM		 3771 /* XXX: specification say this is treated as a load by the MMU
3772 * but does not generate any exception
3773 */
79aceca5
FB		 3774}
3775
3776/* dcbz */
d63001d1 3777#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
d9bce9d9 3778#if defined(CONFIG_USER_ONLY)
2857068e 3779/* User-mode only */
d63001d1
JM		 3780static GenOpFunc *gen_op_dcbz[4][4] = {
3781 {
3782 &gen_op_dcbz_l32_raw,
3783 &gen_op_dcbz_l32_raw,
2857068e 3784#if defined(TARGET_PPC64)
d63001d1
JM		 3785 &gen_op_dcbz_l32_64_raw,
3786 &gen_op_dcbz_l32_64_raw,
2857068e 3787#endif
d63001d1
JM		 3788 },
3789 {
3790 &gen_op_dcbz_l64_raw,
3791 &gen_op_dcbz_l64_raw,
3792#if defined(TARGET_PPC64)
3793 &gen_op_dcbz_l64_64_raw,
3794 &gen_op_dcbz_l64_64_raw,
3795#endif
3796 },
3797 {
3798 &gen_op_dcbz_l128_raw,
3799 &gen_op_dcbz_l128_raw,
3800#if defined(TARGET_PPC64)
3801 &gen_op_dcbz_l128_64_raw,
3802 &gen_op_dcbz_l128_64_raw,
3803#endif
3804 },
3805 {
3806 &gen_op_dcbz_raw,
3807 &gen_op_dcbz_raw,
3808#if defined(TARGET_PPC64)
3809 &gen_op_dcbz_64_raw,
3810 &gen_op_dcbz_64_raw,
3811#endif
3812 },
d9bce9d9
JM		 3813};
3814#else
2857068e
JM		 3815#if defined(TARGET_PPC64)
3816/* Full system - 64 bits mode */
d63001d1
JM		 3817static GenOpFunc *gen_op_dcbz[4][12] = {
3818 {
3819 &gen_op_dcbz_l32_user,
3820 &gen_op_dcbz_l32_user,
3821 &gen_op_dcbz_l32_64_user,
3822 &gen_op_dcbz_l32_64_user,
3823 &gen_op_dcbz_l32_kernel,
3824 &gen_op_dcbz_l32_kernel,
3825 &gen_op_dcbz_l32_64_kernel,
3826 &gen_op_dcbz_l32_64_kernel,
3827#if defined(TARGET_PPC64H)
3828 &gen_op_dcbz_l32_hypv,
3829 &gen_op_dcbz_l32_hypv,
3830 &gen_op_dcbz_l32_64_hypv,
3831 &gen_op_dcbz_l32_64_hypv,
3832#endif
3833 },
3834 {
3835 &gen_op_dcbz_l64_user,
3836 &gen_op_dcbz_l64_user,
3837 &gen_op_dcbz_l64_64_user,
3838 &gen_op_dcbz_l64_64_user,
3839 &gen_op_dcbz_l64_kernel,
3840 &gen_op_dcbz_l64_kernel,
3841 &gen_op_dcbz_l64_64_kernel,
3842 &gen_op_dcbz_l64_64_kernel,
2857068e 3843#if defined(TARGET_PPC64H)
d63001d1
JM		 3844 &gen_op_dcbz_l64_hypv,
3845 &gen_op_dcbz_l64_hypv,
3846 &gen_op_dcbz_l64_64_hypv,
3847 &gen_op_dcbz_l64_64_hypv,
3848#endif
3849 },
3850 {
3851 &gen_op_dcbz_l128_user,
3852 &gen_op_dcbz_l128_user,
3853 &gen_op_dcbz_l128_64_user,
3854 &gen_op_dcbz_l128_64_user,
3855 &gen_op_dcbz_l128_kernel,
3856 &gen_op_dcbz_l128_kernel,
3857 &gen_op_dcbz_l128_64_kernel,
3858 &gen_op_dcbz_l128_64_kernel,
3859#if defined(TARGET_PPC64H)
3860 &gen_op_dcbz_l128_hypv,
3861 &gen_op_dcbz_l128_hypv,
3862 &gen_op_dcbz_l128_64_hypv,
3863 &gen_op_dcbz_l128_64_hypv,
3864#endif
3865 },
3866 {
3867 &gen_op_dcbz_user,
3868 &gen_op_dcbz_user,
3869 &gen_op_dcbz_64_user,
3870 &gen_op_dcbz_64_user,
3871 &gen_op_dcbz_kernel,
3872 &gen_op_dcbz_kernel,
3873 &gen_op_dcbz_64_kernel,
3874 &gen_op_dcbz_64_kernel,
3875#if defined(TARGET_PPC64H)
3876 &gen_op_dcbz_hypv,
3877 &gen_op_dcbz_hypv,
3878 &gen_op_dcbz_64_hypv,
3879 &gen_op_dcbz_64_hypv,
d9bce9d9 3880#endif
d63001d1 3881 },
76a66253 3882};
9a64fbe4 3883#else
2857068e 3884/* Full system - 32 bits mode */
d63001d1
JM		 3885static GenOpFunc *gen_op_dcbz[4][4] = {
3886 {
3887 &gen_op_dcbz_l32_user,
3888 &gen_op_dcbz_l32_user,
3889 &gen_op_dcbz_l32_kernel,
3890 &gen_op_dcbz_l32_kernel,
3891 },
3892 {
3893 &gen_op_dcbz_l64_user,
3894 &gen_op_dcbz_l64_user,
3895 &gen_op_dcbz_l64_kernel,
3896 &gen_op_dcbz_l64_kernel,
3897 },
3898 {
3899 &gen_op_dcbz_l128_user,
3900 &gen_op_dcbz_l128_user,
3901 &gen_op_dcbz_l128_kernel,
3902 &gen_op_dcbz_l128_kernel,
3903 },
3904 {
3905 &gen_op_dcbz_user,
3906 &gen_op_dcbz_user,
3907 &gen_op_dcbz_kernel,
3908 &gen_op_dcbz_kernel,
3909 },
9a64fbe4
FB		 3910};
3911#endif
d9bce9d9 3912#endif
9a64fbe4 3913
b068d6a7
JM		 3914static always_inline void handler_dcbz (DisasContext *ctx,
3915 int dcache_line_size)
d63001d1
JM		 3916{
3917 int n;
3918
3919 switch (dcache_line_size) {
3920 case 32:
3921 n = 0;
3922 break;
3923 case 64:
3924 n = 1;
3925 break;
3926 case 128:
3927 n = 2;
3928 break;
3929 default:
3930 n = 3;
3931 break;
3932 }
3933 op_dcbz(n);
3934}
3935
3936GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 3937{
76a66253 3938 gen_addr_reg_index(ctx);
d63001d1
JM		 3939 handler_dcbz(ctx, ctx->dcache_line_size);
3940 gen_op_check_reservation();
3941}
3942
c7697e1f 3943GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1
JM		 3944{
3945 gen_addr_reg_index(ctx);
3946 if (ctx->opcode & 0x00200000)
3947 handler_dcbz(ctx, ctx->dcache_line_size);
3948 else
3949 handler_dcbz(ctx, -1);
4b3686fa 3950 gen_op_check_reservation();
79aceca5
FB		 3951}
3952
3953/* icbi */
36f69651 3954#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
36f69651 3955#if defined(CONFIG_USER_ONLY)
2857068e 3956/* User-mode only */
36f69651
JM		 3957static GenOpFunc *gen_op_icbi[] = {
3958 &gen_op_icbi_raw,
3959 &gen_op_icbi_raw,
2857068e 3960#if defined(TARGET_PPC64)
36f69651
JM		 3961 &gen_op_icbi_64_raw,
3962 &gen_op_icbi_64_raw,
2857068e 3963#endif
36f69651
JM		 3964};
3965#else
2857068e
JM		 3966/* Full system - 64 bits mode */
3967#if defined(TARGET_PPC64)
36f69651
JM		 3968static GenOpFunc *gen_op_icbi[] = {
3969 &gen_op_icbi_user,
3970 &gen_op_icbi_user,
36f69651
JM		 3971 &gen_op_icbi_64_user,
3972 &gen_op_icbi_64_user,
2857068e
JM		 3973 &gen_op_icbi_kernel,
3974 &gen_op_icbi_kernel,
36f69651
JM		 3975 &gen_op_icbi_64_kernel,
3976 &gen_op_icbi_64_kernel,
2857068e
JM		 3977#if defined(TARGET_PPC64H)
3978 &gen_op_icbi_hypv,
3979 &gen_op_icbi_hypv,
3980 &gen_op_icbi_64_hypv,
3981 &gen_op_icbi_64_hypv,
36f69651 3982#endif
36f69651
JM		 3983};
3984#else
2857068e 3985/* Full system - 32 bits mode */
36f69651
JM		 3986static GenOpFunc *gen_op_icbi[] = {
3987 &gen_op_icbi_user,
3988 &gen_op_icbi_user,
3989 &gen_op_icbi_kernel,
3990 &gen_op_icbi_kernel,
3991};
3992#endif
3993#endif
e1833e1f 3994
1b413d55 3995GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 3996{
30032c94
JM		 3997 /* NIP cannot be restored if the memory exception comes from an helper */
3998 gen_update_nip(ctx, ctx->nip - 4);
76a66253 3999 gen_addr_reg_index(ctx);
36f69651 4000 op_icbi();
79aceca5
FB		 4001}
4002
4003/* Optional: */
4004/* dcba */
a750fc0b 4005GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4006{
0db1b20e
JM		 4007 /* interpreted as no-op */
4008 /* XXX: specification say this is treated as a store by the MMU
4009 * but does not generate any exception
4010 */
79aceca5
FB		 4011}
4012
4013/*** Segment register manipulation ***/
4014/* Supervisor only: */
4015/* mfsr */
4016GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4017{
9a64fbe4 4018#if defined(CONFIG_USER_ONLY)
e1833e1f 4019 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4020#else
76a66253 4021 if (unlikely(!ctx->supervisor)) {
e1833e1f 4022 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4023 return;
9a64fbe4 4024 }
76a66253
JM		 4025 gen_op_set_T1(SR(ctx->opcode));
4026 gen_op_load_sr();
9a64fbe4
FB		 4027 gen_op_store_T0_gpr(rD(ctx->opcode));
4028#endif
79aceca5
FB		 4029}
4030
4031/* mfsrin */
9a64fbe4 4032GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4033{
9a64fbe4 4034#if defined(CONFIG_USER_ONLY)
e1833e1f 4035 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4036#else
76a66253 4037 if (unlikely(!ctx->supervisor)) {
e1833e1f 4038 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4039 return;
9a64fbe4
FB		 4040 }
4041 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 4042 gen_op_srli_T1(28);
4043 gen_op_load_sr();
9a64fbe4
FB		 4044 gen_op_store_T0_gpr(rD(ctx->opcode));
4045#endif
79aceca5
FB		 4046}
4047
4048/* mtsr */
e63c59cb 4049GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4050{
9a64fbe4 4051#if defined(CONFIG_USER_ONLY)
e1833e1f 4052 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4053#else
76a66253 4054 if (unlikely(!ctx->supervisor)) {
e1833e1f 4055 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4056 return;
9a64fbe4
FB		 4057 }
4058 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 4059 gen_op_set_T1(SR(ctx->opcode));
4060 gen_op_store_sr();
9a64fbe4 4061#endif
79aceca5
FB		 4062}
4063
4064/* mtsrin */
9a64fbe4 4065GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4066{
9a64fbe4 4067#if defined(CONFIG_USER_ONLY)
e1833e1f 4068 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4069#else
76a66253 4070 if (unlikely(!ctx->supervisor)) {
e1833e1f 4071 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4072 return;
9a64fbe4
FB		 4073 }
4074 gen_op_load_gpr_T0(rS(ctx->opcode));
4075 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 4076 gen_op_srli_T1(28);
4077 gen_op_store_sr();
9a64fbe4 4078#endif
79aceca5
FB		 4079}
4080
12de9a39
JM		 4081#if defined(TARGET_PPC64)
4082/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4083/* mfsr */
c7697e1f 4084GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4085{
4086#if defined(CONFIG_USER_ONLY)
4087 GEN_EXCP_PRIVREG(ctx);
4088#else
4089 if (unlikely(!ctx->supervisor)) {
4090 GEN_EXCP_PRIVREG(ctx);
4091 return;
4092 }
4093 gen_op_set_T1(SR(ctx->opcode));
4094 gen_op_load_slb();
4095 gen_op_store_T0_gpr(rD(ctx->opcode));
4096#endif
4097}
4098
4099/* mfsrin */
c7697e1f
JM		 4100GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4101 PPC_SEGMENT_64B)
12de9a39
JM		 4102{
4103#if defined(CONFIG_USER_ONLY)
4104 GEN_EXCP_PRIVREG(ctx);
4105#else
4106 if (unlikely(!ctx->supervisor)) {
4107 GEN_EXCP_PRIVREG(ctx);
4108 return;
4109 }
4110 gen_op_load_gpr_T1(rB(ctx->opcode));
4111 gen_op_srli_T1(28);
4112 gen_op_load_slb();
4113 gen_op_store_T0_gpr(rD(ctx->opcode));
4114#endif
4115}
4116
4117/* mtsr */
c7697e1f 4118GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4119{
4120#if defined(CONFIG_USER_ONLY)
4121 GEN_EXCP_PRIVREG(ctx);
4122#else
4123 if (unlikely(!ctx->supervisor)) {
4124 GEN_EXCP_PRIVREG(ctx);
4125 return;
4126 }
4127 gen_op_load_gpr_T0(rS(ctx->opcode));
4128 gen_op_set_T1(SR(ctx->opcode));
4129 gen_op_store_slb();
4130#endif
4131}
4132
4133/* mtsrin */
c7697e1f
JM		 4134GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4135 PPC_SEGMENT_64B)
12de9a39
JM		 4136{
4137#if defined(CONFIG_USER_ONLY)
4138 GEN_EXCP_PRIVREG(ctx);
4139#else
4140 if (unlikely(!ctx->supervisor)) {
4141 GEN_EXCP_PRIVREG(ctx);
4142 return;
4143 }
4144 gen_op_load_gpr_T0(rS(ctx->opcode));
4145 gen_op_load_gpr_T1(rB(ctx->opcode));
4146 gen_op_srli_T1(28);
4147 gen_op_store_slb();
4148#endif
4149}
4150#endif /* defined(TARGET_PPC64) */
4151
79aceca5
FB		 4152/*** Lookaside buffer management ***/
4153/* Optional & supervisor only: */
4154/* tlbia */
3fc6c082 4155GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4156{
9a64fbe4 4157#if defined(CONFIG_USER_ONLY)
e1833e1f 4158 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4159#else
76a66253 4160 if (unlikely(!ctx->supervisor)) {
4a057712 4161 if (loglevel != 0)
9fddaa0c 4162 fprintf(logfile, "%s: ! supervisor\n", __func__);
e1833e1f 4163 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4164 return;
9a64fbe4
FB		 4165 }
4166 gen_op_tlbia();
4167#endif
79aceca5
FB		 4168}
4169
4170/* tlbie */
76a66253 4171GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4172{
9a64fbe4 4173#if defined(CONFIG_USER_ONLY)
e1833e1f 4174 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4175#else
76a66253 4176 if (unlikely(!ctx->supervisor)) {
e1833e1f 4177 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4178 return;
9a64fbe4
FB		 4179 }
4180 gen_op_load_gpr_T0(rB(ctx->opcode));
d9bce9d9
JM		 4181#if defined(TARGET_PPC64)
4182 if (ctx->sf_mode)
4183 gen_op_tlbie_64();
4184 else
4185#endif
4186 gen_op_tlbie();
9a64fbe4 4187#endif
79aceca5
FB		 4188}
4189
4190/* tlbsync */
76a66253 4191GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4192{
9a64fbe4 4193#if defined(CONFIG_USER_ONLY)
e1833e1f 4194 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4195#else
76a66253 4196 if (unlikely(!ctx->supervisor)) {
e1833e1f 4197 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4198 return;
9a64fbe4
FB		 4199 }
4200 /* This has no effect: it should ensure that all previous
4201 * tlbie have completed
4202 */
e1833e1f 4203 GEN_STOP(ctx);
9a64fbe4 4204#endif
79aceca5
FB		 4205}
4206
426613db
JM		 4207#if defined(TARGET_PPC64)
4208/* slbia */
4209GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4210{
4211#if defined(CONFIG_USER_ONLY)
e1833e1f 4212 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4213#else
4214 if (unlikely(!ctx->supervisor)) {
4a057712 4215 if (loglevel != 0)
426613db 4216 fprintf(logfile, "%s: ! supervisor\n", __func__);
e1833e1f 4217 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4218 return;
4219 }
4220 gen_op_slbia();
426613db
JM		 4221#endif
4222}
4223
4224/* slbie */
4225GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4226{
4227#if defined(CONFIG_USER_ONLY)
e1833e1f 4228 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4229#else
4230 if (unlikely(!ctx->supervisor)) {
e1833e1f 4231 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4232 return;
4233 }
4234 gen_op_load_gpr_T0(rB(ctx->opcode));
4235 gen_op_slbie();
426613db
JM		 4236#endif
4237}
4238#endif
4239
79aceca5
FB		 4240/*** External control ***/
4241/* Optional: */
9a64fbe4
FB		 4242#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4243#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
111bfab3 4244#if defined(CONFIG_USER_ONLY)
2857068e 4245/* User-mode only */
111bfab3
FB		 4246static GenOpFunc *gen_op_eciwx[] = {
4247 &gen_op_eciwx_raw,
4248 &gen_op_eciwx_le_raw,
2857068e 4249#if defined(TARGET_PPC64)
d9bce9d9
JM		 4250 &gen_op_eciwx_64_raw,
4251 &gen_op_eciwx_le_64_raw,
2857068e 4252#endif
111bfab3
FB		 4253};
4254static GenOpFunc *gen_op_ecowx[] = {
4255 &gen_op_ecowx_raw,
4256 &gen_op_ecowx_le_raw,
2857068e 4257#if defined(TARGET_PPC64)
d9bce9d9
JM		 4258 &gen_op_ecowx_64_raw,
4259 &gen_op_ecowx_le_64_raw,
2857068e 4260#endif
111bfab3
FB		 4261};
4262#else
2857068e
JM		 4263#if defined(TARGET_PPC64)
4264/* Full system - 64 bits mode */
9a64fbe4
FB		 4265static GenOpFunc *gen_op_eciwx[] = {
4266 &gen_op_eciwx_user,
111bfab3 4267 &gen_op_eciwx_le_user,
d9bce9d9
JM		 4268 &gen_op_eciwx_64_user,
4269 &gen_op_eciwx_le_64_user,
2857068e
JM		 4270 &gen_op_eciwx_kernel,
4271 &gen_op_eciwx_le_kernel,
d9bce9d9
JM		 4272 &gen_op_eciwx_64_kernel,
4273 &gen_op_eciwx_le_64_kernel,
2857068e
JM		 4274#if defined(TARGET_PPC64H)
4275 &gen_op_eciwx_hypv,
4276 &gen_op_eciwx_le_hypv,
4277 &gen_op_eciwx_64_hypv,
4278 &gen_op_eciwx_le_64_hypv,
4279#endif
9a64fbe4
FB		 4280};
4281static GenOpFunc *gen_op_ecowx[] = {
4282 &gen_op_ecowx_user,
111bfab3 4283 &gen_op_ecowx_le_user,
d9bce9d9
JM		 4284 &gen_op_ecowx_64_user,
4285 &gen_op_ecowx_le_64_user,
2857068e
JM		 4286 &gen_op_ecowx_kernel,
4287 &gen_op_ecowx_le_kernel,
d9bce9d9
JM		 4288 &gen_op_ecowx_64_kernel,
4289 &gen_op_ecowx_le_64_kernel,
2857068e
JM		 4290#if defined(TARGET_PPC64H)
4291 &gen_op_ecowx_hypv,
4292 &gen_op_ecowx_le_hypv,
4293 &gen_op_ecowx_64_hypv,
4294 &gen_op_ecowx_le_64_hypv,
9a64fbe4 4295#endif
d9bce9d9
JM		 4296};
4297#else
2857068e 4298/* Full system - 32 bits mode */
d9bce9d9
JM		 4299static GenOpFunc *gen_op_eciwx[] = {
4300 &gen_op_eciwx_user,
4301 &gen_op_eciwx_le_user,
4302 &gen_op_eciwx_kernel,
4303 &gen_op_eciwx_le_kernel,
4304};
4305static GenOpFunc *gen_op_ecowx[] = {
4306 &gen_op_ecowx_user,
4307 &gen_op_ecowx_le_user,
4308 &gen_op_ecowx_kernel,
4309 &gen_op_ecowx_le_kernel,
4310};
4311#endif
4312#endif
9a64fbe4 4313
111bfab3 4314/* eciwx */
79aceca5
FB		 4315GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4316{
9a64fbe4 4317 /* Should check EAR[E] & alignment ! */
76a66253
JM		 4318 gen_addr_reg_index(ctx);
4319 op_eciwx();
4320 gen_op_store_T0_gpr(rD(ctx->opcode));
4321}
4322
4323/* ecowx */
4324GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4325{
4326 /* Should check EAR[E] & alignment ! */
4327 gen_addr_reg_index(ctx);
4328 gen_op_load_gpr_T1(rS(ctx->opcode));
4329 op_ecowx();
4330}
4331
4332/* PowerPC 601 specific instructions */
4333/* abs - abs. */
4334GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4335{
4336 gen_op_load_gpr_T0(rA(ctx->opcode));
4337 gen_op_POWER_abs();
4338 gen_op_store_T0_gpr(rD(ctx->opcode));
4339 if (unlikely(Rc(ctx->opcode) != 0))
4340 gen_set_Rc0(ctx);
4341}
4342
4343/* abso - abso. */
4344GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4345{
4346 gen_op_load_gpr_T0(rA(ctx->opcode));
4347 gen_op_POWER_abso();
4348 gen_op_store_T0_gpr(rD(ctx->opcode));
4349 if (unlikely(Rc(ctx->opcode) != 0))
4350 gen_set_Rc0(ctx);
4351}
4352
4353/* clcs */
a750fc0b 4354GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253
JM		 4355{
4356 gen_op_load_gpr_T0(rA(ctx->opcode));
4357 gen_op_POWER_clcs();
c7697e1f 4358 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4359 gen_op_store_T0_gpr(rD(ctx->opcode));
4360}
4361
4362/* div - div. */
4363GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4364{
4365 gen_op_load_gpr_T0(rA(ctx->opcode));
4366 gen_op_load_gpr_T1(rB(ctx->opcode));
4367 gen_op_POWER_div();
4368 gen_op_store_T0_gpr(rD(ctx->opcode));
4369 if (unlikely(Rc(ctx->opcode) != 0))
4370 gen_set_Rc0(ctx);
4371}
4372
4373/* divo - divo. */
4374GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4375{
4376 gen_op_load_gpr_T0(rA(ctx->opcode));
4377 gen_op_load_gpr_T1(rB(ctx->opcode));
4378 gen_op_POWER_divo();
4379 gen_op_store_T0_gpr(rD(ctx->opcode));
4380 if (unlikely(Rc(ctx->opcode) != 0))
4381 gen_set_Rc0(ctx);
4382}
4383
4384/* divs - divs. */
4385GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4386{
4387 gen_op_load_gpr_T0(rA(ctx->opcode));
4388 gen_op_load_gpr_T1(rB(ctx->opcode));
4389 gen_op_POWER_divs();
4390 gen_op_store_T0_gpr(rD(ctx->opcode));
4391 if (unlikely(Rc(ctx->opcode) != 0))
4392 gen_set_Rc0(ctx);
4393}
4394
4395/* divso - divso. */
4396GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4397{
4398 gen_op_load_gpr_T0(rA(ctx->opcode));
4399 gen_op_load_gpr_T1(rB(ctx->opcode));
4400 gen_op_POWER_divso();
4401 gen_op_store_T0_gpr(rD(ctx->opcode));
4402 if (unlikely(Rc(ctx->opcode) != 0))
4403 gen_set_Rc0(ctx);
4404}
4405
4406/* doz - doz. */
4407GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4408{
4409 gen_op_load_gpr_T0(rA(ctx->opcode));
4410 gen_op_load_gpr_T1(rB(ctx->opcode));
4411 gen_op_POWER_doz();
4412 gen_op_store_T0_gpr(rD(ctx->opcode));
4413 if (unlikely(Rc(ctx->opcode) != 0))
4414 gen_set_Rc0(ctx);
4415}
4416
4417/* dozo - dozo. */
4418GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4419{
4420 gen_op_load_gpr_T0(rA(ctx->opcode));
4421 gen_op_load_gpr_T1(rB(ctx->opcode));
4422 gen_op_POWER_dozo();
4423 gen_op_store_T0_gpr(rD(ctx->opcode));
4424 if (unlikely(Rc(ctx->opcode) != 0))
4425 gen_set_Rc0(ctx);
4426}
4427
4428/* dozi */
4429GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4430{
4431 gen_op_load_gpr_T0(rA(ctx->opcode));
4432 gen_op_set_T1(SIMM(ctx->opcode));
4433 gen_op_POWER_doz();
4434 gen_op_store_T0_gpr(rD(ctx->opcode));
4435}
4436
4437/* As lscbx load from memory byte after byte, it's always endian safe */
2857068e 4438#define op_POWER_lscbx(start, ra, rb) \
76a66253
JM		 4439(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4440#if defined(CONFIG_USER_ONLY)
4441static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4442 &gen_op_POWER_lscbx_raw,
4443 &gen_op_POWER_lscbx_raw,
4444};
4445#else
4446static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4447 &gen_op_POWER_lscbx_user,
4448 &gen_op_POWER_lscbx_user,
4449 &gen_op_POWER_lscbx_kernel,
4450 &gen_op_POWER_lscbx_kernel,
4451};
4452#endif
4453
4454/* lscbx - lscbx. */
4455GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4456{
4457 int ra = rA(ctx->opcode);
4458 int rb = rB(ctx->opcode);
4459
4460 gen_addr_reg_index(ctx);
4461 if (ra == 0) {
4462 ra = rb;
4463 }
4464 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4465 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4466 gen_op_load_xer_bc();
4467 gen_op_load_xer_cmp();
4468 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4469 gen_op_store_xer_bc();
4470 if (unlikely(Rc(ctx->opcode) != 0))
4471 gen_set_Rc0(ctx);
4472}
4473
4474/* maskg - maskg. */
4475GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4476{
4477 gen_op_load_gpr_T0(rS(ctx->opcode));
4478 gen_op_load_gpr_T1(rB(ctx->opcode));
4479 gen_op_POWER_maskg();
4480 gen_op_store_T0_gpr(rA(ctx->opcode));
4481 if (unlikely(Rc(ctx->opcode) != 0))
4482 gen_set_Rc0(ctx);
4483}
4484
4485/* maskir - maskir. */
4486GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4487{
4488 gen_op_load_gpr_T0(rA(ctx->opcode));
4489 gen_op_load_gpr_T1(rS(ctx->opcode));
4490 gen_op_load_gpr_T2(rB(ctx->opcode));
4491 gen_op_POWER_maskir();
4492 gen_op_store_T0_gpr(rA(ctx->opcode));
4493 if (unlikely(Rc(ctx->opcode) != 0))
4494 gen_set_Rc0(ctx);
4495}
4496
4497/* mul - mul. */
4498GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4499{
4500 gen_op_load_gpr_T0(rA(ctx->opcode));
4501 gen_op_load_gpr_T1(rB(ctx->opcode));
4502 gen_op_POWER_mul();
4503 gen_op_store_T0_gpr(rD(ctx->opcode));
4504 if (unlikely(Rc(ctx->opcode) != 0))
4505 gen_set_Rc0(ctx);
4506}
4507
4508/* mulo - mulo. */
4509GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4510{
4511 gen_op_load_gpr_T0(rA(ctx->opcode));
4512 gen_op_load_gpr_T1(rB(ctx->opcode));
4513 gen_op_POWER_mulo();
4514 gen_op_store_T0_gpr(rD(ctx->opcode));
4515 if (unlikely(Rc(ctx->opcode) != 0))
4516 gen_set_Rc0(ctx);
4517}
4518
4519/* nabs - nabs. */
4520GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4521{
4522 gen_op_load_gpr_T0(rA(ctx->opcode));
4523 gen_op_POWER_nabs();
4524 gen_op_store_T0_gpr(rD(ctx->opcode));
4525 if (unlikely(Rc(ctx->opcode) != 0))
4526 gen_set_Rc0(ctx);
4527}
4528
4529/* nabso - nabso. */
4530GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4531{
4532 gen_op_load_gpr_T0(rA(ctx->opcode));
4533 gen_op_POWER_nabso();
4534 gen_op_store_T0_gpr(rD(ctx->opcode));
4535 if (unlikely(Rc(ctx->opcode) != 0))
4536 gen_set_Rc0(ctx);
4537}
4538
4539/* rlmi - rlmi. */
4540GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4541{
4542 uint32_t mb, me;
4543
4544 mb = MB(ctx->opcode);
4545 me = ME(ctx->opcode);
4546 gen_op_load_gpr_T0(rS(ctx->opcode));
4547 gen_op_load_gpr_T1(rA(ctx->opcode));
4548 gen_op_load_gpr_T2(rB(ctx->opcode));
4549 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4550 gen_op_store_T0_gpr(rA(ctx->opcode));
4551 if (unlikely(Rc(ctx->opcode) != 0))
4552 gen_set_Rc0(ctx);
4553}
4554
4555/* rrib - rrib. */
4556GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4557{
4558 gen_op_load_gpr_T0(rS(ctx->opcode));
4559 gen_op_load_gpr_T1(rA(ctx->opcode));
4560 gen_op_load_gpr_T2(rB(ctx->opcode));
4561 gen_op_POWER_rrib();
4562 gen_op_store_T0_gpr(rA(ctx->opcode));
4563 if (unlikely(Rc(ctx->opcode) != 0))
4564 gen_set_Rc0(ctx);
4565}
4566
4567/* sle - sle. */
4568GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4569{
4570 gen_op_load_gpr_T0(rS(ctx->opcode));
4571 gen_op_load_gpr_T1(rB(ctx->opcode));
4572 gen_op_POWER_sle();
4573 gen_op_store_T0_gpr(rA(ctx->opcode));
4574 if (unlikely(Rc(ctx->opcode) != 0))
4575 gen_set_Rc0(ctx);
4576}
4577
4578/* sleq - sleq. */
4579GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4580{
4581 gen_op_load_gpr_T0(rS(ctx->opcode));
4582 gen_op_load_gpr_T1(rB(ctx->opcode));
4583 gen_op_POWER_sleq();
4584 gen_op_store_T0_gpr(rA(ctx->opcode));
4585 if (unlikely(Rc(ctx->opcode) != 0))
4586 gen_set_Rc0(ctx);
4587}
4588
4589/* sliq - sliq. */
4590GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4591{
4592 gen_op_load_gpr_T0(rS(ctx->opcode));
4593 gen_op_set_T1(SH(ctx->opcode));
4594 gen_op_POWER_sle();
4595 gen_op_store_T0_gpr(rA(ctx->opcode));
4596 if (unlikely(Rc(ctx->opcode) != 0))
4597 gen_set_Rc0(ctx);
4598}
4599
4600/* slliq - slliq. */
4601GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4602{
4603 gen_op_load_gpr_T0(rS(ctx->opcode));
4604 gen_op_set_T1(SH(ctx->opcode));
4605 gen_op_POWER_sleq();
4606 gen_op_store_T0_gpr(rA(ctx->opcode));
4607 if (unlikely(Rc(ctx->opcode) != 0))
4608 gen_set_Rc0(ctx);
4609}
4610
4611/* sllq - sllq. */
4612GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4613{
4614 gen_op_load_gpr_T0(rS(ctx->opcode));
4615 gen_op_load_gpr_T1(rB(ctx->opcode));
4616 gen_op_POWER_sllq();
4617 gen_op_store_T0_gpr(rA(ctx->opcode));
4618 if (unlikely(Rc(ctx->opcode) != 0))
4619 gen_set_Rc0(ctx);
4620}
4621
4622/* slq - slq. */
4623GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4624{
4625 gen_op_load_gpr_T0(rS(ctx->opcode));
4626 gen_op_load_gpr_T1(rB(ctx->opcode));
4627 gen_op_POWER_slq();
4628 gen_op_store_T0_gpr(rA(ctx->opcode));
4629 if (unlikely(Rc(ctx->opcode) != 0))
4630 gen_set_Rc0(ctx);
4631}
4632
d9bce9d9 4633/* sraiq - sraiq. */
76a66253
JM		 4634GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4635{
4636 gen_op_load_gpr_T0(rS(ctx->opcode));
4637 gen_op_set_T1(SH(ctx->opcode));
4638 gen_op_POWER_sraq();
4639 gen_op_store_T0_gpr(rA(ctx->opcode));
4640 if (unlikely(Rc(ctx->opcode) != 0))
4641 gen_set_Rc0(ctx);
4642}
4643
4644/* sraq - sraq. */
4645GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4646{
4647 gen_op_load_gpr_T0(rS(ctx->opcode));
4648 gen_op_load_gpr_T1(rB(ctx->opcode));
4649 gen_op_POWER_sraq();
4650 gen_op_store_T0_gpr(rA(ctx->opcode));
4651 if (unlikely(Rc(ctx->opcode) != 0))
4652 gen_set_Rc0(ctx);
4653}
4654
4655/* sre - sre. */
4656GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4657{
4658 gen_op_load_gpr_T0(rS(ctx->opcode));
4659 gen_op_load_gpr_T1(rB(ctx->opcode));
4660 gen_op_POWER_sre();
4661 gen_op_store_T0_gpr(rA(ctx->opcode));
4662 if (unlikely(Rc(ctx->opcode) != 0))
4663 gen_set_Rc0(ctx);
4664}
4665
4666/* srea - srea. */
4667GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4668{
4669 gen_op_load_gpr_T0(rS(ctx->opcode));
4670 gen_op_load_gpr_T1(rB(ctx->opcode));
4671 gen_op_POWER_srea();
4672 gen_op_store_T0_gpr(rA(ctx->opcode));
4673 if (unlikely(Rc(ctx->opcode) != 0))
4674 gen_set_Rc0(ctx);
4675}
4676
4677/* sreq */
4678GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4679{
4680 gen_op_load_gpr_T0(rS(ctx->opcode));
4681 gen_op_load_gpr_T1(rB(ctx->opcode));
4682 gen_op_POWER_sreq();
4683 gen_op_store_T0_gpr(rA(ctx->opcode));
4684 if (unlikely(Rc(ctx->opcode) != 0))
4685 gen_set_Rc0(ctx);
4686}
4687
4688/* sriq */
4689GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4690{
4691 gen_op_load_gpr_T0(rS(ctx->opcode));
4692 gen_op_set_T1(SH(ctx->opcode));
4693 gen_op_POWER_srq();
4694 gen_op_store_T0_gpr(rA(ctx->opcode));
4695 if (unlikely(Rc(ctx->opcode) != 0))
4696 gen_set_Rc0(ctx);
4697}
4698
4699/* srliq */
4700GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4701{
4702 gen_op_load_gpr_T0(rS(ctx->opcode));
4703 gen_op_load_gpr_T1(rB(ctx->opcode));
4704 gen_op_set_T1(SH(ctx->opcode));
4705 gen_op_POWER_srlq();
4706 gen_op_store_T0_gpr(rA(ctx->opcode));
4707 if (unlikely(Rc(ctx->opcode) != 0))
4708 gen_set_Rc0(ctx);
4709}
4710
4711/* srlq */
4712GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4713{
4714 gen_op_load_gpr_T0(rS(ctx->opcode));
4715 gen_op_load_gpr_T1(rB(ctx->opcode));
4716 gen_op_POWER_srlq();
4717 gen_op_store_T0_gpr(rA(ctx->opcode));
4718 if (unlikely(Rc(ctx->opcode) != 0))
4719 gen_set_Rc0(ctx);
4720}
4721
4722/* srq */
4723GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4724{
4725 gen_op_load_gpr_T0(rS(ctx->opcode));
4726 gen_op_load_gpr_T1(rB(ctx->opcode));
4727 gen_op_POWER_srq();
4728 gen_op_store_T0_gpr(rA(ctx->opcode));
4729 if (unlikely(Rc(ctx->opcode) != 0))
4730 gen_set_Rc0(ctx);
4731}
4732
4733/* PowerPC 602 specific instructions */
4734/* dsa */
4735GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4736{
4737 /* XXX: TODO */
e1833e1f 4738 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4739}
4740
4741/* esa */
4742GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4743{
4744 /* XXX: TODO */
e1833e1f 4745 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4746}
4747
4748/* mfrom */
4749GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4750{
4751#if defined(CONFIG_USER_ONLY)
e1833e1f 4752 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4753#else
4754 if (unlikely(!ctx->supervisor)) {
e1833e1f 4755 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4756 return;
4757 }
4758 gen_op_load_gpr_T0(rA(ctx->opcode));
4759 gen_op_602_mfrom();
4760 gen_op_store_T0_gpr(rD(ctx->opcode));
4761#endif
4762}
4763
4764/* 602 - 603 - G2 TLB management */
4765/* tlbld */
c7697e1f 4766GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4767{
4768#if defined(CONFIG_USER_ONLY)
e1833e1f 4769 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4770#else
4771 if (unlikely(!ctx->supervisor)) {
e1833e1f 4772 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4773 return;
4774 }
4775 gen_op_load_gpr_T0(rB(ctx->opcode));
4776 gen_op_6xx_tlbld();
76a66253
JM		 4777#endif
4778}
4779
4780/* tlbli */
c7697e1f 4781GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4782{
4783#if defined(CONFIG_USER_ONLY)
e1833e1f 4784 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4785#else
4786 if (unlikely(!ctx->supervisor)) {
e1833e1f 4787 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4788 return;
4789 }
4790 gen_op_load_gpr_T0(rB(ctx->opcode));
4791 gen_op_6xx_tlbli();
76a66253
JM		 4792#endif
4793}
4794
7dbe11ac
JM		 4795/* 74xx TLB management */
4796/* tlbld */
c7697e1f 4797GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4798{
4799#if defined(CONFIG_USER_ONLY)
4800 GEN_EXCP_PRIVOPC(ctx);
4801#else
4802 if (unlikely(!ctx->supervisor)) {
4803 GEN_EXCP_PRIVOPC(ctx);
4804 return;
4805 }
4806 gen_op_load_gpr_T0(rB(ctx->opcode));
4807 gen_op_74xx_tlbld();
4808#endif
4809}
4810
4811/* tlbli */
c7697e1f 4812GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4813{
4814#if defined(CONFIG_USER_ONLY)
4815 GEN_EXCP_PRIVOPC(ctx);
4816#else
4817 if (unlikely(!ctx->supervisor)) {
4818 GEN_EXCP_PRIVOPC(ctx);
4819 return;
4820 }
4821 gen_op_load_gpr_T0(rB(ctx->opcode));
4822 gen_op_74xx_tlbli();
4823#endif
4824}
4825
76a66253
JM		 4826/* POWER instructions not in PowerPC 601 */
4827/* clf */
4828GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4829{
4830 /* Cache line flush: implemented as no-op */
4831}
4832
4833/* cli */
4834GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4835{
7f75ffd3 4836 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4837#if defined(CONFIG_USER_ONLY)
e1833e1f 4838 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4839#else
4840 if (unlikely(!ctx->supervisor)) {
e1833e1f 4841 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4842 return;
4843 }
4844#endif
4845}
4846
4847/* dclst */
4848GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4849{
4850 /* Data cache line store: treated as no-op */
4851}
4852
4853GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4854{
4855#if defined(CONFIG_USER_ONLY)
e1833e1f 4856 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4857#else
4858 if (unlikely(!ctx->supervisor)) {
e1833e1f 4859 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4860 return;
4861 }
4862 int ra = rA(ctx->opcode);
4863 int rd = rD(ctx->opcode);
4864
4865 gen_addr_reg_index(ctx);
4866 gen_op_POWER_mfsri();
4867 gen_op_store_T0_gpr(rd);
4868 if (ra != 0 && ra != rd)
4869 gen_op_store_T1_gpr(ra);
4870#endif
4871}
4872
4873GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4874{
4875#if defined(CONFIG_USER_ONLY)
e1833e1f 4876 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4877#else
4878 if (unlikely(!ctx->supervisor)) {
e1833e1f 4879 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4880 return;
4881 }
4882 gen_addr_reg_index(ctx);
4883 gen_op_POWER_rac();
4884 gen_op_store_T0_gpr(rD(ctx->opcode));
4885#endif
4886}
4887
4888GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4889{
4890#if defined(CONFIG_USER_ONLY)
e1833e1f 4891 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4892#else
4893 if (unlikely(!ctx->supervisor)) {
e1833e1f 4894 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4895 return;
4896 }
4897 gen_op_POWER_rfsvc();
e1833e1f 4898 GEN_SYNC(ctx);
76a66253
JM		 4899#endif
4900}
4901
4902/* svc is not implemented for now */
4903
4904/* POWER2 specific instructions */
4905/* Quad manipulation (load/store two floats at a time) */
4906#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4907#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4908#if defined(CONFIG_USER_ONLY)
4909static GenOpFunc *gen_op_POWER2_lfq[] = {
4910 &gen_op_POWER2_lfq_le_raw,
4911 &gen_op_POWER2_lfq_raw,
4912};
4913static GenOpFunc *gen_op_POWER2_stfq[] = {
4914 &gen_op_POWER2_stfq_le_raw,
4915 &gen_op_POWER2_stfq_raw,
4916};
4917#else
4918static GenOpFunc *gen_op_POWER2_lfq[] = {
4919 &gen_op_POWER2_lfq_le_user,
4920 &gen_op_POWER2_lfq_user,
4921 &gen_op_POWER2_lfq_le_kernel,
4922 &gen_op_POWER2_lfq_kernel,
4923};
4924static GenOpFunc *gen_op_POWER2_stfq[] = {
4925 &gen_op_POWER2_stfq_le_user,
4926 &gen_op_POWER2_stfq_user,
4927 &gen_op_POWER2_stfq_le_kernel,
4928 &gen_op_POWER2_stfq_kernel,
4929};
4930#endif
4931
4932/* lfq */
4933GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4934{
4935 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4936 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4937 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4938 op_POWER2_lfq();
4939 gen_op_store_FT0_fpr(rD(ctx->opcode));
4940 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4941}
4942
4943/* lfqu */
4944GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4945{
4946 int ra = rA(ctx->opcode);
4947
4948 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4949 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4950 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4951 op_POWER2_lfq();
4952 gen_op_store_FT0_fpr(rD(ctx->opcode));
4953 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4954 if (ra != 0)
4955 gen_op_store_T0_gpr(ra);
4956}
4957
4958/* lfqux */
4959GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4960{
4961 int ra = rA(ctx->opcode);
4962
4963 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4964 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4965 gen_addr_reg_index(ctx);
4966 op_POWER2_lfq();
4967 gen_op_store_FT0_fpr(rD(ctx->opcode));
4968 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4969 if (ra != 0)
4970 gen_op_store_T0_gpr(ra);
4971}
4972
4973/* lfqx */
4974GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4975{
4976 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4977 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4978 gen_addr_reg_index(ctx);
4979 op_POWER2_lfq();
4980 gen_op_store_FT0_fpr(rD(ctx->opcode));
4981 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4982}
4983
4984/* stfq */
4985GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4986{
4987 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4988 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4989 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4990 gen_op_load_fpr_FT0(rS(ctx->opcode));
4991 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4992 op_POWER2_stfq();
4993}
4994
4995/* stfqu */
4996GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4997{
4998 int ra = rA(ctx->opcode);
4999
5000 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5001 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 5002 gen_addr_imm_index(ctx, 0);
76a66253
JM		 5003 gen_op_load_fpr_FT0(rS(ctx->opcode));
5004 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5005 op_POWER2_stfq();
5006 if (ra != 0)
5007 gen_op_store_T0_gpr(ra);
5008}
5009
5010/* stfqux */
5011GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5012{
5013 int ra = rA(ctx->opcode);
5014
5015 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5016 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 5017 gen_addr_reg_index(ctx);
5018 gen_op_load_fpr_FT0(rS(ctx->opcode));
5019 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5020 op_POWER2_stfq();
5021 if (ra != 0)
5022 gen_op_store_T0_gpr(ra);
5023}
5024
5025/* stfqx */
5026GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5027{
5028 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5029 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 5030 gen_addr_reg_index(ctx);
5031 gen_op_load_fpr_FT0(rS(ctx->opcode));
5032 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5033 op_POWER2_stfq();
5034}
5035
5036/* BookE specific instructions */
2662a059 5037/* XXX: not implemented on 440 ? */
a750fc0b 5038GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
76a66253
JM		 5039{
5040 /* XXX: TODO */
e1833e1f 5041 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5042}
5043
2662a059 5044/* XXX: not implemented on 440 ? */
a750fc0b 5045GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
76a66253
JM		 5046{
5047#if defined(CONFIG_USER_ONLY)
e1833e1f 5048 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5049#else
5050 if (unlikely(!ctx->supervisor)) {
e1833e1f 5051 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5052 return;
5053 }
5054 gen_addr_reg_index(ctx);
5055 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5056#if defined(TARGET_PPC64)
5057 if (ctx->sf_mode)
5058 gen_op_tlbie_64();
5059 else
5060#endif
5061 gen_op_tlbie();
76a66253
JM		 5062#endif
5063}
5064
5065/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5066static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5067 int opc2, int opc3,
5068 int ra, int rb, int rt, int Rc)
76a66253
JM		 5069{
5070 gen_op_load_gpr_T0(ra);
5071 gen_op_load_gpr_T1(rb);
5072 switch (opc3 & 0x0D) {
5073 case 0x05:
5074 /* macchw - macchw. - macchwo - macchwo. */
5075 /* macchws - macchws. - macchwso - macchwso. */
5076 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5077 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5078 /* mulchw - mulchw. */
5079 gen_op_405_mulchw();
5080 break;
5081 case 0x04:
5082 /* macchwu - macchwu. - macchwuo - macchwuo. */
5083 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5084 /* mulchwu - mulchwu. */
5085 gen_op_405_mulchwu();
5086 break;
5087 case 0x01:
5088 /* machhw - machhw. - machhwo - machhwo. */
5089 /* machhws - machhws. - machhwso - machhwso. */
5090 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5091 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5092 /* mulhhw - mulhhw. */
5093 gen_op_405_mulhhw();
5094 break;
5095 case 0x00:
5096 /* machhwu - machhwu. - machhwuo - machhwuo. */
5097 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5098 /* mulhhwu - mulhhwu. */
5099 gen_op_405_mulhhwu();
5100 break;
5101 case 0x0D:
5102 /* maclhw - maclhw. - maclhwo - maclhwo. */
5103 /* maclhws - maclhws. - maclhwso - maclhwso. */
5104 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5105 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5106 /* mullhw - mullhw. */
5107 gen_op_405_mullhw();
5108 break;
5109 case 0x0C:
5110 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5111 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5112 /* mullhwu - mullhwu. */
5113 gen_op_405_mullhwu();
5114 break;
5115 }
5116 if (opc2 & 0x02) {
5117 /* nmultiply-and-accumulate (0x0E) */
5118 gen_op_neg();
5119 }
5120 if (opc2 & 0x04) {
5121 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
5122 gen_op_load_gpr_T2(rt);
5123 gen_op_move_T1_T0();
5124 gen_op_405_add_T0_T2();
5125 }
5126 if (opc3 & 0x10) {
5127 /* Check overflow */
5128 if (opc3 & 0x01)
c3e10c7b 5129 gen_op_check_addo();
76a66253
JM		 5130 else
5131 gen_op_405_check_ovu();
5132 }
5133 if (opc3 & 0x02) {
5134 /* Saturate */
5135 if (opc3 & 0x01)
5136 gen_op_405_check_sat();
5137 else
5138 gen_op_405_check_satu();
5139 }
5140 gen_op_store_T0_gpr(rt);
5141 if (unlikely(Rc) != 0) {
5142 /* Update Rc0 */
5143 gen_set_Rc0(ctx);
5144 }
5145}
5146
a750fc0b
JM		 5147#define GEN_MAC_HANDLER(name, opc2, opc3) \
5148GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5149{ \
5150 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5151 rD(ctx->opcode), Rc(ctx->opcode)); \
5152}
5153
5154/* macchw - macchw. */
a750fc0b 5155GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5156/* macchwo - macchwo. */
a750fc0b 5157GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5158/* macchws - macchws. */
a750fc0b 5159GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5160/* macchwso - macchwso. */
a750fc0b 5161GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5162/* macchwsu - macchwsu. */
a750fc0b 5163GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5164/* macchwsuo - macchwsuo. */
a750fc0b 5165GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5166/* macchwu - macchwu. */
a750fc0b 5167GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5168/* macchwuo - macchwuo. */
a750fc0b 5169GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5170/* machhw - machhw. */
a750fc0b 5171GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5172/* machhwo - machhwo. */
a750fc0b 5173GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5174/* machhws - machhws. */
a750fc0b 5175GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5176/* machhwso - machhwso. */
a750fc0b 5177GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5178/* machhwsu - machhwsu. */
a750fc0b 5179GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5180/* machhwsuo - machhwsuo. */
a750fc0b 5181GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5182/* machhwu - machhwu. */
a750fc0b 5183GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5184/* machhwuo - machhwuo. */
a750fc0b 5185GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5186/* maclhw - maclhw. */
a750fc0b 5187GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5188/* maclhwo - maclhwo. */
a750fc0b 5189GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5190/* maclhws - maclhws. */
a750fc0b 5191GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5192/* maclhwso - maclhwso. */
a750fc0b 5193GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5194/* maclhwu - maclhwu. */
a750fc0b 5195GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5196/* maclhwuo - maclhwuo. */
a750fc0b 5197GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5198/* maclhwsu - maclhwsu. */
a750fc0b 5199GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5200/* maclhwsuo - maclhwsuo. */
a750fc0b 5201GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5202/* nmacchw - nmacchw. */
a750fc0b 5203GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5204/* nmacchwo - nmacchwo. */
a750fc0b 5205GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5206/* nmacchws - nmacchws. */
a750fc0b 5207GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5208/* nmacchwso - nmacchwso. */
a750fc0b 5209GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5210/* nmachhw - nmachhw. */
a750fc0b 5211GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5212/* nmachhwo - nmachhwo. */
a750fc0b 5213GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5214/* nmachhws - nmachhws. */
a750fc0b 5215GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5216/* nmachhwso - nmachhwso. */
a750fc0b 5217GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5218/* nmaclhw - nmaclhw. */
a750fc0b 5219GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5220/* nmaclhwo - nmaclhwo. */
a750fc0b 5221GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5222/* nmaclhws - nmaclhws. */
a750fc0b 5223GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5224/* nmaclhwso - nmaclhwso. */
a750fc0b 5225GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5226
5227/* mulchw - mulchw. */
a750fc0b 5228GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5229/* mulchwu - mulchwu. */
a750fc0b 5230GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5231/* mulhhw - mulhhw. */
a750fc0b 5232GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5233/* mulhhwu - mulhhwu. */
a750fc0b 5234GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5235/* mullhw - mullhw. */
a750fc0b 5236GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5237/* mullhwu - mullhwu. */
a750fc0b 5238GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5239
5240/* mfdcr */
5241GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
5242{
5243#if defined(CONFIG_USER_ONLY)
e1833e1f 5244 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5245#else
5246 uint32_t dcrn = SPR(ctx->opcode);
5247
5248 if (unlikely(!ctx->supervisor)) {
e1833e1f 5249 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5250 return;
5251 }
a42bd6cc
JM		 5252 gen_op_set_T0(dcrn);
5253 gen_op_load_dcr();
76a66253
JM		 5254 gen_op_store_T0_gpr(rD(ctx->opcode));
5255#endif
5256}
5257
5258/* mtdcr */
5259GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
5260{
5261#if defined(CONFIG_USER_ONLY)
e1833e1f 5262 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5263#else
5264 uint32_t dcrn = SPR(ctx->opcode);
5265
5266 if (unlikely(!ctx->supervisor)) {
e1833e1f 5267 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5268 return;
5269 }
a42bd6cc
JM		 5270 gen_op_set_T0(dcrn);
5271 gen_op_load_gpr_T1(rS(ctx->opcode));
5272 gen_op_store_dcr();
5273#endif
5274}
5275
5276/* mfdcrx */
2662a059 5277/* XXX: not implemented on 440 ? */
a750fc0b 5278GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
a42bd6cc
JM		 5279{
5280#if defined(CONFIG_USER_ONLY)
e1833e1f 5281 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5282#else
5283 if (unlikely(!ctx->supervisor)) {
e1833e1f 5284 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5285 return;
5286 }
5287 gen_op_load_gpr_T0(rA(ctx->opcode));
5288 gen_op_load_dcr();
5289 gen_op_store_T0_gpr(rD(ctx->opcode));
a750fc0b 5290 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5291#endif
5292}
5293
5294/* mtdcrx */
2662a059 5295/* XXX: not implemented on 440 ? */
a750fc0b 5296GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
a42bd6cc
JM		 5297{
5298#if defined(CONFIG_USER_ONLY)
e1833e1f 5299 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5300#else
5301 if (unlikely(!ctx->supervisor)) {
e1833e1f 5302 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5303 return;
5304 }
5305 gen_op_load_gpr_T0(rA(ctx->opcode));
5306 gen_op_load_gpr_T1(rS(ctx->opcode));
5307 gen_op_store_dcr();
a750fc0b 5308 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5309#endif
5310}
5311
a750fc0b
JM		 5312/* mfdcrux (PPC 460) : user-mode access to DCR */
5313GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5314{
5315 gen_op_load_gpr_T0(rA(ctx->opcode));
5316 gen_op_load_dcr();
5317 gen_op_store_T0_gpr(rD(ctx->opcode));
5318 /* Note: Rc update flag set leads to undefined state of Rc0 */
5319}
5320
5321/* mtdcrux (PPC 460) : user-mode access to DCR */
5322GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5323{
5324 gen_op_load_gpr_T0(rA(ctx->opcode));
5325 gen_op_load_gpr_T1(rS(ctx->opcode));
5326 gen_op_store_dcr();
5327 /* Note: Rc update flag set leads to undefined state of Rc0 */
5328}
5329
76a66253
JM		 5330/* dccci */
5331GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5332{
5333#if defined(CONFIG_USER_ONLY)
e1833e1f 5334 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5335#else
5336 if (unlikely(!ctx->supervisor)) {
e1833e1f 5337 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5338 return;
5339 }
5340 /* interpreted as no-op */
5341#endif
5342}
5343
5344/* dcread */
5345GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5346{
5347#if defined(CONFIG_USER_ONLY)
e1833e1f 5348 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5349#else
5350 if (unlikely(!ctx->supervisor)) {
e1833e1f 5351 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5352 return;
5353 }
5354 gen_addr_reg_index(ctx);
5355 op_ldst(lwz);
5356 gen_op_store_T0_gpr(rD(ctx->opcode));
5357#endif
5358}
5359
5360/* icbt */
c7697e1f 5361GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5362{
5363 /* interpreted as no-op */
5364 /* XXX: specification say this is treated as a load by the MMU
5365 * but does not generate any exception
5366 */
5367}
5368
5369/* iccci */
5370GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5371{
5372#if defined(CONFIG_USER_ONLY)
e1833e1f 5373 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5374#else
5375 if (unlikely(!ctx->supervisor)) {
e1833e1f 5376 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5377 return;
5378 }
5379 /* interpreted as no-op */
5380#endif
5381}
5382
5383/* icread */
5384GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5385{
5386#if defined(CONFIG_USER_ONLY)
e1833e1f 5387 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5388#else
5389 if (unlikely(!ctx->supervisor)) {
e1833e1f 5390 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5391 return;
5392 }
5393 /* interpreted as no-op */
5394#endif
5395}
5396
5397/* rfci (supervisor only) */
c7697e1f 5398GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5399{
5400#if defined(CONFIG_USER_ONLY)
e1833e1f 5401 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5402#else
5403 if (unlikely(!ctx->supervisor)) {
e1833e1f 5404 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5405 return;
5406 }
5407 /* Restore CPU state */
5408 gen_op_40x_rfci();
e1833e1f 5409 GEN_SYNC(ctx);
a42bd6cc
JM		 5410#endif
5411}
5412
5413GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5414{
5415#if defined(CONFIG_USER_ONLY)
e1833e1f 5416 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5417#else
5418 if (unlikely(!ctx->supervisor)) {
e1833e1f 5419 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5420 return;
5421 }
5422 /* Restore CPU state */
5423 gen_op_rfci();
e1833e1f 5424 GEN_SYNC(ctx);
a42bd6cc
JM		 5425#endif
5426}
5427
5428/* BookE specific */
2662a059 5429/* XXX: not implemented on 440 ? */
a750fc0b 5430GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
76a66253
JM		 5431{
5432#if defined(CONFIG_USER_ONLY)
e1833e1f 5433 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5434#else
5435 if (unlikely(!ctx->supervisor)) {
e1833e1f 5436 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5437 return;
5438 }
5439 /* Restore CPU state */
a42bd6cc 5440 gen_op_rfdi();
e1833e1f 5441 GEN_SYNC(ctx);
76a66253
JM		 5442#endif
5443}
5444
2662a059 5445/* XXX: not implemented on 440 ? */
a750fc0b 5446GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5447{
5448#if defined(CONFIG_USER_ONLY)
e1833e1f 5449 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5450#else
5451 if (unlikely(!ctx->supervisor)) {
e1833e1f 5452 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5453 return;
5454 }
5455 /* Restore CPU state */
5456 gen_op_rfmci();
e1833e1f 5457 GEN_SYNC(ctx);
a42bd6cc
JM		 5458#endif
5459}
5eb7995e 5460
d9bce9d9 5461/* TLB management - PowerPC 405 implementation */
76a66253 5462/* tlbre */
c7697e1f 5463GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5464{
5465#if defined(CONFIG_USER_ONLY)
e1833e1f 5466 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5467#else
5468 if (unlikely(!ctx->supervisor)) {
e1833e1f 5469 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5470 return;
5471 }
5472 switch (rB(ctx->opcode)) {
5473 case 0:
9a64fbe4 5474 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 5475 gen_op_4xx_tlbre_hi();
5476 gen_op_store_T0_gpr(rD(ctx->opcode));
5477 break;
5478 case 1:
5479 gen_op_load_gpr_T0(rA(ctx->opcode));
5480 gen_op_4xx_tlbre_lo();
5481 gen_op_store_T0_gpr(rD(ctx->opcode));
5482 break;
5483 default:
e1833e1f 5484 GEN_EXCP_INVAL(ctx);
76a66253 5485 break;
9a64fbe4 5486 }
76a66253
JM		 5487#endif
5488}
5489
d9bce9d9 5490/* tlbsx - tlbsx. */
c7697e1f 5491GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5492{
5493#if defined(CONFIG_USER_ONLY)
e1833e1f 5494 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5495#else
5496 if (unlikely(!ctx->supervisor)) {
e1833e1f 5497 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5498 return;
5499 }
5500 gen_addr_reg_index(ctx);
daf4f96e 5501 gen_op_4xx_tlbsx();
76a66253 5502 if (Rc(ctx->opcode))
daf4f96e 5503 gen_op_4xx_tlbsx_check();
9a64fbe4 5504 gen_op_store_T0_gpr(rD(ctx->opcode));
76a66253 5505#endif
79aceca5
FB		 5506}
5507
76a66253 5508/* tlbwe */
c7697e1f 5509GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5510{
76a66253 5511#if defined(CONFIG_USER_ONLY)
e1833e1f 5512 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5513#else
5514 if (unlikely(!ctx->supervisor)) {
e1833e1f 5515 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5516 return;
5517 }
5518 switch (rB(ctx->opcode)) {
5519 case 0:
9a64fbe4 5520 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 5521 gen_op_load_gpr_T1(rS(ctx->opcode));
5522 gen_op_4xx_tlbwe_hi();
5523 break;
5524 case 1:
5525 gen_op_load_gpr_T0(rA(ctx->opcode));
5526 gen_op_load_gpr_T1(rS(ctx->opcode));
5527 gen_op_4xx_tlbwe_lo();
5528 break;
5529 default:
e1833e1f 5530 GEN_EXCP_INVAL(ctx);
76a66253 5531 break;
9a64fbe4 5532 }
76a66253
JM		 5533#endif
5534}
5535
a4bb6c3e 5536/* TLB management - PowerPC 440 implementation */
5eb7995e 5537/* tlbre */
c7697e1f 5538GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5539{
5540#if defined(CONFIG_USER_ONLY)
e1833e1f 5541 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5542#else
5543 if (unlikely(!ctx->supervisor)) {
e1833e1f 5544 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5545 return;
5546 }
5547 switch (rB(ctx->opcode)) {
5548 case 0:
5eb7995e 5549 case 1:
5eb7995e
JM		 5550 case 2:
5551 gen_op_load_gpr_T0(rA(ctx->opcode));
a4bb6c3e 5552 gen_op_440_tlbre(rB(ctx->opcode));
5eb7995e
JM		 5553 gen_op_store_T0_gpr(rD(ctx->opcode));
5554 break;
5555 default:
e1833e1f 5556 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5557 break;
5558 }
5559#endif
5560}
5561
5562/* tlbsx - tlbsx. */
c7697e1f 5563GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5564{
5565#if defined(CONFIG_USER_ONLY)
e1833e1f 5566 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5567#else
5568 if (unlikely(!ctx->supervisor)) {
e1833e1f 5569 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5570 return;
5571 }
5572 gen_addr_reg_index(ctx);
daf4f96e 5573 gen_op_440_tlbsx();
5eb7995e 5574 if (Rc(ctx->opcode))
daf4f96e 5575 gen_op_4xx_tlbsx_check();
5eb7995e
JM		 5576 gen_op_store_T0_gpr(rD(ctx->opcode));
5577#endif
5578}
5579
5580/* tlbwe */
c7697e1f 5581GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5582{
5583#if defined(CONFIG_USER_ONLY)
e1833e1f 5584 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5585#else
5586 if (unlikely(!ctx->supervisor)) {
e1833e1f 5587 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5588 return;
5589 }
5590 switch (rB(ctx->opcode)) {
5591 case 0:
5eb7995e 5592 case 1:
5eb7995e
JM		 5593 case 2:
5594 gen_op_load_gpr_T0(rA(ctx->opcode));
5595 gen_op_load_gpr_T1(rS(ctx->opcode));
a4bb6c3e 5596 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5597 break;
5598 default:
e1833e1f 5599 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5600 break;
5601 }
5602#endif
5603}
5604
76a66253
JM		 5605/* wrtee */
5606GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
5607{
5608#if defined(CONFIG_USER_ONLY)
e1833e1f 5609 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5610#else
5611 if (unlikely(!ctx->supervisor)) {
e1833e1f 5612 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5613 return;
5614 }
5615 gen_op_load_gpr_T0(rD(ctx->opcode));
a42bd6cc 5616 gen_op_wrte();
dee96f6c
JM		 5617 /* Stop translation to have a chance to raise an exception
5618 * if we just set msr_ee to 1
5619 */
e1833e1f 5620 GEN_STOP(ctx);
76a66253
JM		 5621#endif
5622}
5623
5624/* wrteei */
5625GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
5626{
5627#if defined(CONFIG_USER_ONLY)
e1833e1f 5628 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5629#else
5630 if (unlikely(!ctx->supervisor)) {
e1833e1f 5631 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5632 return;
5633 }
5634 gen_op_set_T0(ctx->opcode & 0x00010000);
a42bd6cc 5635 gen_op_wrte();
dee96f6c
JM		 5636 /* Stop translation to have a chance to raise an exception
5637 * if we just set msr_ee to 1
5638 */
e1833e1f 5639 GEN_STOP(ctx);
76a66253
JM		 5640#endif
5641}
5642
08e46e54 5643/* PowerPC 440 specific instructions */
76a66253
JM		 5644/* dlmzb */
5645GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5646{
5647 gen_op_load_gpr_T0(rS(ctx->opcode));
5648 gen_op_load_gpr_T1(rB(ctx->opcode));
5649 gen_op_440_dlmzb();
5650 gen_op_store_T0_gpr(rA(ctx->opcode));
5651 gen_op_store_xer_bc();
5652 if (Rc(ctx->opcode)) {
5653 gen_op_440_dlmzb_update_Rc();
5654 gen_op_store_T0_crf(0);
5655 }
5656}
5657
5658/* mbar replaces eieio on 440 */
5659GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5660{
5661 /* interpreted as no-op */
5662}
5663
5664/* msync replaces sync on 440 */
0db1b20e 5665GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5666{
5667 /* interpreted as no-op */
5668}
5669
5670/* icbt */
c7697e1f 5671GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5672{
5673 /* interpreted as no-op */
5674 /* XXX: specification say this is treated as a load by the MMU
5675 * but does not generate any exception
5676 */
79aceca5
FB		 5677}
5678
a9d9eb8f
JM		 5679/*** Altivec vector extension ***/
5680/* Altivec registers moves */
5681GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5682GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5683GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5684
5685GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5686GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5687#if 0 // unused
5688GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5689#endif
5690
5691#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5692#if defined(CONFIG_USER_ONLY)
5693#if defined(TARGET_PPC64)
5694/* User-mode only - 64 bits mode */
5695#define OP_VR_LD_TABLE(name) \
5696static GenOpFunc *gen_op_vr_l##name[] = { \
5697 &gen_op_vr_l##name##_raw, \
5698 &gen_op_vr_l##name##_le_raw, \
5699 &gen_op_vr_l##name##_64_raw, \
5700 &gen_op_vr_l##name##_le_64_raw, \
5701};
5702#define OP_VR_ST_TABLE(name) \
5703static GenOpFunc *gen_op_vr_st##name[] = { \
5704 &gen_op_vr_st##name##_raw, \
5705 &gen_op_vr_st##name##_le_raw, \
5706 &gen_op_vr_st##name##_64_raw, \
5707 &gen_op_vr_st##name##_le_64_raw, \
5708};
5709#else /* defined(TARGET_PPC64) */
5710/* User-mode only - 32 bits mode */
5711#define OP_VR_LD_TABLE(name) \
5712static GenOpFunc *gen_op_vr_l##name[] = { \
5713 &gen_op_vr_l##name##_raw, \
5714 &gen_op_vr_l##name##_le_raw, \
5715};
5716#define OP_VR_ST_TABLE(name) \
5717static GenOpFunc *gen_op_vr_st##name[] = { \
5718 &gen_op_vr_st##name##_raw, \
5719 &gen_op_vr_st##name##_le_raw, \
5720};
5721#endif /* defined(TARGET_PPC64) */
5722#else /* defined(CONFIG_USER_ONLY) */
5723#if defined(TARGET_PPC64H)
5724/* Full system with hypervisor mode */
5725#define OP_VR_LD_TABLE(name) \
5726static GenOpFunc *gen_op_vr_l##name[] = { \
5727 &gen_op_vr_l##name##_user, \
5728 &gen_op_vr_l##name##_le_user, \
5729 &gen_op_vr_l##name##_64_user, \
5730 &gen_op_vr_l##name##_le_64_user, \
5731 &gen_op_vr_l##name##_kernel, \
5732 &gen_op_vr_l##name##_le_kernel, \
5733 &gen_op_vr_l##name##_64_kernel, \
5734 &gen_op_vr_l##name##_le_64_kernel, \
5735 &gen_op_vr_l##name##_hypv, \
5736 &gen_op_vr_l##name##_le_hypv, \
5737 &gen_op_vr_l##name##_64_hypv, \
5738 &gen_op_vr_l##name##_le_64_hypv, \
5739};
5740#define OP_VR_ST_TABLE(name) \
5741static GenOpFunc *gen_op_vr_st##name[] = { \
5742 &gen_op_vr_st##name##_user, \
5743 &gen_op_vr_st##name##_le_user, \
5744 &gen_op_vr_st##name##_64_user, \
5745 &gen_op_vr_st##name##_le_64_user, \
5746 &gen_op_vr_st##name##_kernel, \
5747 &gen_op_vr_st##name##_le_kernel, \
5748 &gen_op_vr_st##name##_64_kernel, \
5749 &gen_op_vr_st##name##_le_64_kernel, \
5750 &gen_op_vr_st##name##_hypv, \
5751 &gen_op_vr_st##name##_le_hypv, \
5752 &gen_op_vr_st##name##_64_hypv, \
5753 &gen_op_vr_st##name##_le_64_hypv, \
5754};
5755#elif defined(TARGET_PPC64)
5756/* Full system - 64 bits mode */
5757#define OP_VR_LD_TABLE(name) \
5758static GenOpFunc *gen_op_vr_l##name[] = { \
5759 &gen_op_vr_l##name##_user, \
5760 &gen_op_vr_l##name##_le_user, \
5761 &gen_op_vr_l##name##_64_user, \
5762 &gen_op_vr_l##name##_le_64_user, \
5763 &gen_op_vr_l##name##_kernel, \
5764 &gen_op_vr_l##name##_le_kernel, \
5765 &gen_op_vr_l##name##_64_kernel, \
5766 &gen_op_vr_l##name##_le_64_kernel, \
5767};
5768#define OP_VR_ST_TABLE(name) \
5769static GenOpFunc *gen_op_vr_st##name[] = { \
5770 &gen_op_vr_st##name##_user, \
5771 &gen_op_vr_st##name##_le_user, \
5772 &gen_op_vr_st##name##_64_user, \
5773 &gen_op_vr_st##name##_le_64_user, \
5774 &gen_op_vr_st##name##_kernel, \
5775 &gen_op_vr_st##name##_le_kernel, \
5776 &gen_op_vr_st##name##_64_kernel, \
5777 &gen_op_vr_st##name##_le_64_kernel, \
5778};
5779#else /* defined(TARGET_PPC64) */
5780/* Full system - 32 bits mode */
5781#define OP_VR_LD_TABLE(name) \
5782static GenOpFunc *gen_op_vr_l##name[] = { \
5783 &gen_op_vr_l##name##_user, \
5784 &gen_op_vr_l##name##_le_user, \
5785 &gen_op_vr_l##name##_kernel, \
5786 &gen_op_vr_l##name##_le_kernel, \
5787};
5788#define OP_VR_ST_TABLE(name) \
5789static GenOpFunc *gen_op_vr_st##name[] = { \
5790 &gen_op_vr_st##name##_user, \
5791 &gen_op_vr_st##name##_le_user, \
5792 &gen_op_vr_st##name##_kernel, \
5793 &gen_op_vr_st##name##_le_kernel, \
5794};
5795#endif /* defined(TARGET_PPC64) */
5796#endif /* defined(CONFIG_USER_ONLY) */
5797
5798#define GEN_VR_LDX(name, opc2, opc3) \
5799GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5800{ \
5801 if (unlikely(!ctx->altivec_enabled)) { \
5802 GEN_EXCP_NO_VR(ctx); \
5803 return; \
5804 } \
5805 gen_addr_reg_index(ctx); \
5806 op_vr_ldst(vr_l##name); \
5807 gen_op_store_A0_avr(rD(ctx->opcode)); \
5808}
5809
5810#define GEN_VR_STX(name, opc2, opc3) \
5811GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5812{ \
5813 if (unlikely(!ctx->altivec_enabled)) { \
5814 GEN_EXCP_NO_VR(ctx); \
5815 return; \
5816 } \
5817 gen_addr_reg_index(ctx); \
5818 gen_op_load_avr_A0(rS(ctx->opcode)); \
5819 op_vr_ldst(vr_st##name); \
5820}
5821
5822OP_VR_LD_TABLE(vx);
5823GEN_VR_LDX(vx, 0x07, 0x03);
5824/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5825#define gen_op_vr_lvxl gen_op_vr_lvx
5826GEN_VR_LDX(vxl, 0x07, 0x0B);
5827
5828OP_VR_ST_TABLE(vx);
5829GEN_VR_STX(vx, 0x07, 0x07);
5830/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5831#define gen_op_vr_stvxl gen_op_vr_stvx
5832GEN_VR_STX(vxl, 0x07, 0x0F);
5833
0487d6a8
JM		 5834/*** SPE extension ***/
5835
5836/* Register moves */
65d6c0f3 5837#if !defined(TARGET_PPC64)
3cd7d1dd 5838
0487d6a8
JM		 5839GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5840GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5841#if 0 // unused
5842GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5843#endif
5844
5845GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5846GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5847#if 0 // unused
5848GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5849#endif
5850
65d6c0f3 5851#else /* !defined(TARGET_PPC64) */
3cd7d1dd
JM		 5852
5853/* No specific load/store functions: GPRs are already 64 bits */
5854#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
5855#define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
5856#if 0 // unused
5857#define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
5858#endif
5859
5860#define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
5861#define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
5862#if 0 // unused
5863#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
5864#endif
5865
65d6c0f3 5866#endif /* !defined(TARGET_PPC64) */
3cd7d1dd 5867
0487d6a8
JM		 5868#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5869GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5870{ \
5871 if (Rc(ctx->opcode)) \
5872 gen_##name1(ctx); \
5873 else \
5874 gen_##name0(ctx); \
5875}
5876
5877/* Handler for undefined SPE opcodes */
b068d6a7 5878static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5879{
e1833e1f 5880 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5881}
5882
5883/* SPE load and stores */
b068d6a7 5884static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
0487d6a8
JM		 5885{
5886 target_long simm = rB(ctx->opcode);
5887
5888 if (rA(ctx->opcode) == 0) {
5889 gen_set_T0(simm << sh);
5890 } else {
5891 gen_op_load_gpr_T0(rA(ctx->opcode));
5892 if (likely(simm != 0))
5893 gen_op_addi(simm << sh);
5894 }
5895}
5896
5897#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5898#if defined(CONFIG_USER_ONLY)
5899#if defined(TARGET_PPC64)
2857068e 5900/* User-mode only - 64 bits mode */
0487d6a8
JM		 5901#define OP_SPE_LD_TABLE(name) \
5902static GenOpFunc *gen_op_spe_l##name[] = { \
5903 &gen_op_spe_l##name##_raw, \
5904 &gen_op_spe_l##name##_le_raw, \
5905 &gen_op_spe_l##name##_64_raw, \
5906 &gen_op_spe_l##name##_le_64_raw, \
5907};
5908#define OP_SPE_ST_TABLE(name) \
5909static GenOpFunc *gen_op_spe_st##name[] = { \
5910 &gen_op_spe_st##name##_raw, \
5911 &gen_op_spe_st##name##_le_raw, \
5912 &gen_op_spe_st##name##_64_raw, \
5913 &gen_op_spe_st##name##_le_64_raw, \
5914};
5915#else /* defined(TARGET_PPC64) */
2857068e 5916/* User-mode only - 32 bits mode */
0487d6a8
JM		 5917#define OP_SPE_LD_TABLE(name) \
5918static GenOpFunc *gen_op_spe_l##name[] = { \
5919 &gen_op_spe_l##name##_raw, \
5920 &gen_op_spe_l##name##_le_raw, \
5921};
5922#define OP_SPE_ST_TABLE(name) \
5923static GenOpFunc *gen_op_spe_st##name[] = { \
5924 &gen_op_spe_st##name##_raw, \
5925 &gen_op_spe_st##name##_le_raw, \
5926};
5927#endif /* defined(TARGET_PPC64) */
5928#else /* defined(CONFIG_USER_ONLY) */
2857068e
JM		 5929#if defined(TARGET_PPC64H)
5930/* Full system with hypervisor mode */
0487d6a8
JM		 5931#define OP_SPE_LD_TABLE(name) \
5932static GenOpFunc *gen_op_spe_l##name[] = { \
5933 &gen_op_spe_l##name##_user, \
5934 &gen_op_spe_l##name##_le_user, \
0487d6a8
JM		 5935 &gen_op_spe_l##name##_64_user, \
5936 &gen_op_spe_l##name##_le_64_user, \
2857068e
JM		 5937 &gen_op_spe_l##name##_kernel, \
5938 &gen_op_spe_l##name##_le_kernel, \
0487d6a8
JM		 5939 &gen_op_spe_l##name##_64_kernel, \
5940 &gen_op_spe_l##name##_le_64_kernel, \
2857068e
JM		 5941 &gen_op_spe_l##name##_hypv, \
5942 &gen_op_spe_l##name##_le_hypv, \
5943 &gen_op_spe_l##name##_64_hypv, \
5944 &gen_op_spe_l##name##_le_64_hypv, \
0487d6a8
JM		 5945};
5946#define OP_SPE_ST_TABLE(name) \
5947static GenOpFunc *gen_op_spe_st##name[] = { \
5948 &gen_op_spe_st##name##_user, \
5949 &gen_op_spe_st##name##_le_user, \
2857068e
JM		 5950 &gen_op_spe_st##name##_64_user, \
5951 &gen_op_spe_st##name##_le_64_user, \
0487d6a8
JM		 5952 &gen_op_spe_st##name##_kernel, \
5953 &gen_op_spe_st##name##_le_kernel, \
2857068e
JM		 5954 &gen_op_spe_st##name##_64_kernel, \
5955 &gen_op_spe_st##name##_le_64_kernel, \
5956 &gen_op_spe_st##name##_hypv, \
5957 &gen_op_spe_st##name##_le_hypv, \
5958 &gen_op_spe_st##name##_64_hypv, \
5959 &gen_op_spe_st##name##_le_64_hypv, \
5960};
5961#elif defined(TARGET_PPC64)
5962/* Full system - 64 bits mode */
5963#define OP_SPE_LD_TABLE(name) \
5964static GenOpFunc *gen_op_spe_l##name[] = { \
5965 &gen_op_spe_l##name##_user, \
5966 &gen_op_spe_l##name##_le_user, \
5967 &gen_op_spe_l##name##_64_user, \
5968 &gen_op_spe_l##name##_le_64_user, \
5969 &gen_op_spe_l##name##_kernel, \
5970 &gen_op_spe_l##name##_le_kernel, \
5971 &gen_op_spe_l##name##_64_kernel, \
5972 &gen_op_spe_l##name##_le_64_kernel, \
5973};
5974#define OP_SPE_ST_TABLE(name) \
5975static GenOpFunc *gen_op_spe_st##name[] = { \
5976 &gen_op_spe_st##name##_user, \
5977 &gen_op_spe_st##name##_le_user, \
0487d6a8
JM		 5978 &gen_op_spe_st##name##_64_user, \
5979 &gen_op_spe_st##name##_le_64_user, \
2857068e
JM		 5980 &gen_op_spe_st##name##_kernel, \
5981 &gen_op_spe_st##name##_le_kernel, \
0487d6a8
JM		 5982 &gen_op_spe_st##name##_64_kernel, \
5983 &gen_op_spe_st##name##_le_64_kernel, \
5984};
5985#else /* defined(TARGET_PPC64) */
2857068e 5986/* Full system - 32 bits mode */
0487d6a8
JM		 5987#define OP_SPE_LD_TABLE(name) \
5988static GenOpFunc *gen_op_spe_l##name[] = { \
5989 &gen_op_spe_l##name##_user, \
5990 &gen_op_spe_l##name##_le_user, \
5991 &gen_op_spe_l##name##_kernel, \
5992 &gen_op_spe_l##name##_le_kernel, \
5993};
5994#define OP_SPE_ST_TABLE(name) \
5995static GenOpFunc *gen_op_spe_st##name[] = { \
5996 &gen_op_spe_st##name##_user, \
5997 &gen_op_spe_st##name##_le_user, \
5998 &gen_op_spe_st##name##_kernel, \
5999 &gen_op_spe_st##name##_le_kernel, \
6000};
6001#endif /* defined(TARGET_PPC64) */
6002#endif /* defined(CONFIG_USER_ONLY) */
6003
6004#define GEN_SPE_LD(name, sh) \
b068d6a7 6005static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 6006{ \
6007 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6008 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6009 return; \
6010 } \
6011 gen_addr_spe_imm_index(ctx, sh); \
6012 op_spe_ldst(spe_l##name); \
6013 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
6014}
6015
6016#define GEN_SPE_LDX(name) \
b068d6a7 6017static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 6018{ \
6019 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6020 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6021 return; \
6022 } \
6023 gen_addr_reg_index(ctx); \
6024 op_spe_ldst(spe_l##name); \
6025 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
6026}
6027
6028#define GEN_SPEOP_LD(name, sh) \
6029OP_SPE_LD_TABLE(name); \
6030GEN_SPE_LD(name, sh); \
6031GEN_SPE_LDX(name)
6032
6033#define GEN_SPE_ST(name, sh) \
b068d6a7 6034static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 6035{ \
6036 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6037 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6038 return; \
6039 } \
6040 gen_addr_spe_imm_index(ctx, sh); \
6041 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6042 op_spe_ldst(spe_st##name); \
6043}
6044
6045#define GEN_SPE_STX(name) \
b068d6a7 6046static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 6047{ \
6048 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6049 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6050 return; \
6051 } \
6052 gen_addr_reg_index(ctx); \
6053 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6054 op_spe_ldst(spe_st##name); \
6055}
6056
6057#define GEN_SPEOP_ST(name, sh) \
6058OP_SPE_ST_TABLE(name); \
6059GEN_SPE_ST(name, sh); \
6060GEN_SPE_STX(name)
6061
6062#define GEN_SPEOP_LDST(name, sh) \
6063GEN_SPEOP_LD(name, sh); \
6064GEN_SPEOP_ST(name, sh)
6065
6066/* SPE arithmetic and logic */
6067#define GEN_SPEOP_ARITH2(name) \
b068d6a7 6068static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6069{ \
6070 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6071 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6072 return; \
6073 } \
6074 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6075 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6076 gen_op_##name(); \
6077 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6078}
6079
6080#define GEN_SPEOP_ARITH1(name) \
b068d6a7 6081static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6082{ \
6083 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6084 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6085 return; \
6086 } \
6087 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6088 gen_op_##name(); \
6089 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6090}
6091
6092#define GEN_SPEOP_COMP(name) \
b068d6a7 6093static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6094{ \
6095 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6096 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6097 return; \
6098 } \
6099 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6100 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6101 gen_op_##name(); \
6102 gen_op_store_T0_crf(crfD(ctx->opcode)); \
6103}
6104
6105/* Logical */
6106GEN_SPEOP_ARITH2(evand);
6107GEN_SPEOP_ARITH2(evandc);
6108GEN_SPEOP_ARITH2(evxor);
6109GEN_SPEOP_ARITH2(evor);
6110GEN_SPEOP_ARITH2(evnor);
6111GEN_SPEOP_ARITH2(eveqv);
6112GEN_SPEOP_ARITH2(evorc);
6113GEN_SPEOP_ARITH2(evnand);
6114GEN_SPEOP_ARITH2(evsrwu);
6115GEN_SPEOP_ARITH2(evsrws);
6116GEN_SPEOP_ARITH2(evslw);
6117GEN_SPEOP_ARITH2(evrlw);
6118GEN_SPEOP_ARITH2(evmergehi);
6119GEN_SPEOP_ARITH2(evmergelo);
6120GEN_SPEOP_ARITH2(evmergehilo);
6121GEN_SPEOP_ARITH2(evmergelohi);
6122
6123/* Arithmetic */
6124GEN_SPEOP_ARITH2(evaddw);
6125GEN_SPEOP_ARITH2(evsubfw);
6126GEN_SPEOP_ARITH1(evabs);
6127GEN_SPEOP_ARITH1(evneg);
6128GEN_SPEOP_ARITH1(evextsb);
6129GEN_SPEOP_ARITH1(evextsh);
6130GEN_SPEOP_ARITH1(evrndw);
6131GEN_SPEOP_ARITH1(evcntlzw);
6132GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 6133static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 6134{
6135 /* Note: brinc is usable even if SPE is disabled */
3cd7d1dd
JM		 6136 gen_op_load_gpr_T0(rA(ctx->opcode));
6137 gen_op_load_gpr_T1(rB(ctx->opcode));
0487d6a8 6138 gen_op_brinc();
3cd7d1dd 6139 gen_op_store_T0_gpr(rD(ctx->opcode));
0487d6a8
JM		 6140}
6141
6142#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 6143static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 6144{ \
6145 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6146 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6147 return; \
6148 } \
6149 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6150 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
6151 gen_op_##name(); \
6152 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6153}
6154
6155#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 6156static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 6157{ \
6158 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6159 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6160 return; \
6161 } \
6162 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6163 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6164 gen_op_##name(); \
6165 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6166}
6167
6168GEN_SPEOP_ARITH_IMM2(evaddw);
6169#define gen_evaddiw gen_evaddwi
6170GEN_SPEOP_ARITH_IMM2(evsubfw);
6171#define gen_evsubifw gen_evsubfwi
6172GEN_SPEOP_LOGIC_IMM2(evslw);
6173GEN_SPEOP_LOGIC_IMM2(evsrwu);
6174#define gen_evsrwis gen_evsrwsi
6175GEN_SPEOP_LOGIC_IMM2(evsrws);
6176#define gen_evsrwiu gen_evsrwui
6177GEN_SPEOP_LOGIC_IMM2(evrlw);
6178
b068d6a7 6179static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 6180{
6181 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
6182
6183 gen_op_splatwi_T0_64(imm);
6184 gen_op_store_T0_gpr64(rD(ctx->opcode));
6185}
6186
b068d6a7 6187static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 6188{
6189 uint32_t imm = rA(ctx->opcode) << 27;
6190
6191 gen_op_splatwi_T0_64(imm);
6192 gen_op_store_T0_gpr64(rD(ctx->opcode));
6193}
6194
6195/* Comparison */
6196GEN_SPEOP_COMP(evcmpgtu);
6197GEN_SPEOP_COMP(evcmpgts);
6198GEN_SPEOP_COMP(evcmpltu);
6199GEN_SPEOP_COMP(evcmplts);
6200GEN_SPEOP_COMP(evcmpeq);
6201
6202GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6203GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6204GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6205GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6206GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6207GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6208GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6209GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6210GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6211GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6212GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6213GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6214GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6215GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6216GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6217GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6218GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6219GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6220GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6221GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6222GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6223GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6224GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6225GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6226GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6227
b068d6a7 6228static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 6229{
6230 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 6231 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 6232 return;
6233 }
6234 gen_op_load_crf_T0(ctx->opcode & 0x7);
6235 gen_op_load_gpr64_T0(rA(ctx->opcode));
6236 gen_op_load_gpr64_T1(rB(ctx->opcode));
6237 gen_op_evsel();
6238 gen_op_store_T0_gpr64(rD(ctx->opcode));
6239}
6240
c7697e1f 6241GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6242{
6243 gen_evsel(ctx);
6244}
c7697e1f 6245GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6246{
6247 gen_evsel(ctx);
6248}
c7697e1f 6249GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6250{
6251 gen_evsel(ctx);
6252}
c7697e1f 6253GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6254{
6255 gen_evsel(ctx);
6256}
6257
6258/* Load and stores */
6259#if defined(TARGET_PPC64)
6260/* In that case, we already have 64 bits load & stores
6261 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
6262 */
6263#if defined(CONFIG_USER_ONLY)
6264#define gen_op_spe_ldd_raw gen_op_ld_raw
6265#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
6266#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
6267#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
6268#define gen_op_spe_stdd_raw gen_op_ld_raw
6269#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
6270#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
6271#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
6272#else /* defined(CONFIG_USER_ONLY) */
3cd7d1dd
JM		 6273#if defined(TARGET_PPC64H)
6274#define gen_op_spe_ldd_hypv gen_op_ld_hypv
6275#define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
6276#define gen_op_spe_ldd_le_hypv gen_op_ld_hypv
6277#define gen_op_spe_ldd_le_64_hypv gen_op_ld_64_hypv
6278#endif
0487d6a8
JM		 6279#define gen_op_spe_ldd_kernel gen_op_ld_kernel
6280#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
6281#define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
6282#define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
6283#define gen_op_spe_ldd_user gen_op_ld_user
6284#define gen_op_spe_ldd_64_user gen_op_ld_64_user
6285#define gen_op_spe_ldd_le_user gen_op_ld_le_user
6286#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
3cd7d1dd
JM		 6287#if defined(TARGET_PPC64H)
6288#define gen_op_spe_stdd_hypv gen_op_std_hypv
6289#define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
6290#define gen_op_spe_stdd_le_hypv gen_op_std_hypv
6291#define gen_op_spe_stdd_le_64_hypv gen_op_std_64_hypv
6292#endif
0487d6a8
JM		 6293#define gen_op_spe_stdd_kernel gen_op_std_kernel
6294#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
6295#define gen_op_spe_stdd_le_kernel gen_op_std_kernel
6296#define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
6297#define gen_op_spe_stdd_user gen_op_std_user
6298#define gen_op_spe_stdd_64_user gen_op_std_64_user
6299#define gen_op_spe_stdd_le_user gen_op_std_le_user
6300#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
6301#endif /* defined(CONFIG_USER_ONLY) */
6302#endif /* defined(TARGET_PPC64) */
6303GEN_SPEOP_LDST(dd, 3);
6304GEN_SPEOP_LDST(dw, 3);
6305GEN_SPEOP_LDST(dh, 3);
6306GEN_SPEOP_LDST(whe, 2);
6307GEN_SPEOP_LD(whou, 2);
6308GEN_SPEOP_LD(whos, 2);
6309GEN_SPEOP_ST(who, 2);
6310
6311#if defined(TARGET_PPC64)
6312/* In that case, spe_stwwo is equivalent to stw */
6313#if defined(CONFIG_USER_ONLY)
6314#define gen_op_spe_stwwo_raw gen_op_stw_raw
6315#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
6316#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
6317#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
6318#else
6319#define gen_op_spe_stwwo_user gen_op_stw_user
6320#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
6321#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
6322#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
6323#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
6324#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
6325#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
6326#define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
3cd7d1dd
JM		 6327#if defined(TARGET_PPC64H)
6328#define gen_op_spe_stwwo_hypv gen_op_stw_hypv
6329#define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
6330#define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
6331#define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
6332#endif
0487d6a8
JM		 6333#endif
6334#endif
6335#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 6336static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 6337{ \
6338 gen_op_srli32_T1_64(); \
6339 gen_op_spe_stwwo_##suffix(); \
6340}
6341#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 6342static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 6343{ \
6344 gen_op_srli32_T1_64(); \
6345 gen_op_spe_stwwo_le_##suffix(); \
6346}
6347#if defined(TARGET_PPC64)
6348#define GEN_OP_SPE_STWWE(suffix) \
6349_GEN_OP_SPE_STWWE(suffix); \
6350_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 6351static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 6352{ \
6353 gen_op_srli32_T1_64(); \
6354 gen_op_spe_stwwo_64_##suffix(); \
6355} \
b068d6a7 6356static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 6357{ \
6358 gen_op_srli32_T1_64(); \
6359 gen_op_spe_stwwo_le_64_##suffix(); \
6360}
6361#else
6362#define GEN_OP_SPE_STWWE(suffix) \
6363_GEN_OP_SPE_STWWE(suffix); \
6364_GEN_OP_SPE_STWWE_LE(suffix)
6365#endif
6366#if defined(CONFIG_USER_ONLY)
6367GEN_OP_SPE_STWWE(raw);
6368#else /* defined(CONFIG_USER_ONLY) */
3cd7d1dd
JM		 6369#if defined(TARGET_PPC64H)
6370GEN_OP_SPE_STWWE(hypv);
6371#endif
0487d6a8
JM		 6372GEN_OP_SPE_STWWE(kernel);
6373GEN_OP_SPE_STWWE(user);
6374#endif /* defined(CONFIG_USER_ONLY) */
6375GEN_SPEOP_ST(wwe, 2);
6376GEN_SPEOP_ST(wwo, 2);
6377
6378#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 6379static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 6380{ \
6381 gen_op_##op##_##suffix(); \
6382 gen_op_splatw_T1_64(); \
6383}
6384
6385#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 6386static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 6387{ \
6388 gen_op_spe_lh_##suffix(); \
6389 gen_op_sli16_T1_64(); \
6390}
6391
6392#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 6393static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 6394{ \
6395 gen_op_spe_lh_##suffix(); \
6396 gen_op_extsh_T1_64(); \
6397}
6398
6399#if defined(CONFIG_USER_ONLY)
6400GEN_OP_SPE_LHE(raw);
6401GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6402GEN_OP_SPE_LHE(le_raw);
6403GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6404GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6405GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6406GEN_OP_SPE_LHX(raw);
6407GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6408GEN_OP_SPE_LHX(le_raw);
6409GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6410#if defined(TARGET_PPC64)
6411GEN_OP_SPE_LHE(64_raw);
6412GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6413GEN_OP_SPE_LHE(le_64_raw);
6414GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6415GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6416GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6417GEN_OP_SPE_LHX(64_raw);
6418GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6419GEN_OP_SPE_LHX(le_64_raw);
6420GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6421#endif
6422#else
3cd7d1dd
JM		 6423#if defined(TARGET_PPC64H)
6424GEN_OP_SPE_LHE(hypv);
6425#endif
0487d6a8
JM		 6426GEN_OP_SPE_LHE(kernel);
6427GEN_OP_SPE_LHE(user);
3cd7d1dd
JM		 6428#if defined(TARGET_PPC64H)
6429GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
6430#endif
0487d6a8
JM		 6431GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6432GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
3cd7d1dd
JM		 6433#if defined(TARGET_PPC64H)
6434GEN_OP_SPE_LHE(le_hypv);
6435#endif
0487d6a8
JM		 6436GEN_OP_SPE_LHE(le_kernel);
6437GEN_OP_SPE_LHE(le_user);
3cd7d1dd
JM		 6438#if defined(TARGET_PPC64H)
6439GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
6440#endif
0487d6a8
JM		 6441GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6442GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
3cd7d1dd
JM		 6443#if defined(TARGET_PPC64H)
6444GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
6445#endif
0487d6a8
JM		 6446GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6447GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
3cd7d1dd
JM		 6448#if defined(TARGET_PPC64H)
6449GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
6450#endif
0487d6a8
JM		 6451GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6452GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
3cd7d1dd
JM		 6453#if defined(TARGET_PPC64H)
6454GEN_OP_SPE_LHX(hypv);
6455#endif
0487d6a8
JM		 6456GEN_OP_SPE_LHX(kernel);
6457GEN_OP_SPE_LHX(user);
3cd7d1dd
JM		 6458#if defined(TARGET_PPC64H)
6459GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
6460#endif
0487d6a8
JM		 6461GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6462GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
3cd7d1dd
JM		 6463#if defined(TARGET_PPC64H)
6464GEN_OP_SPE_LHX(le_hypv);
6465#endif
0487d6a8
JM		 6466GEN_OP_SPE_LHX(le_kernel);
6467GEN_OP_SPE_LHX(le_user);
3cd7d1dd
JM		 6468#if defined(TARGET_PPC64H)
6469GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
6470#endif
0487d6a8
JM		 6471GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6472GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
6473#if defined(TARGET_PPC64)
3cd7d1dd
JM		 6474#if defined(TARGET_PPC64H)
6475GEN_OP_SPE_LHE(64_hypv);
6476#endif
0487d6a8
JM		 6477GEN_OP_SPE_LHE(64_kernel);
6478GEN_OP_SPE_LHE(64_user);
3cd7d1dd
JM		 6479#if defined(TARGET_PPC64H)
6480GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
6481#endif
0487d6a8
JM		 6482GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6483GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
3cd7d1dd
JM		 6484#if defined(TARGET_PPC64H)
6485GEN_OP_SPE_LHE(le_64_hypv);
6486#endif
0487d6a8
JM		 6487GEN_OP_SPE_LHE(le_64_kernel);
6488GEN_OP_SPE_LHE(le_64_user);
3cd7d1dd
JM		 6489#if defined(TARGET_PPC64H)
6490GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
6491#endif
0487d6a8
JM		 6492GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6493GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
3cd7d1dd
JM		 6494#if defined(TARGET_PPC64H)
6495GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
6496#endif
0487d6a8
JM		 6497GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6498GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
3cd7d1dd
JM		 6499#if defined(TARGET_PPC64H)
6500GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
6501#endif
0487d6a8
JM		 6502GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6503GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
3cd7d1dd
JM		 6504#if defined(TARGET_PPC64H)
6505GEN_OP_SPE_LHX(64_hypv);
6506#endif
0487d6a8
JM		 6507GEN_OP_SPE_LHX(64_kernel);
6508GEN_OP_SPE_LHX(64_user);
3cd7d1dd
JM		 6509#if defined(TARGET_PPC64H)
6510GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
6511#endif
0487d6a8
JM		 6512GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6513GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
3cd7d1dd
JM		 6514#if defined(TARGET_PPC64H)
6515GEN_OP_SPE_LHX(le_64_hypv);
6516#endif
0487d6a8
JM		 6517GEN_OP_SPE_LHX(le_64_kernel);
6518GEN_OP_SPE_LHX(le_64_user);
3cd7d1dd
JM		 6519#if defined(TARGET_PPC64H)
6520GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
6521#endif
0487d6a8
JM		 6522GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6523GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
6524#endif
6525#endif
6526GEN_SPEOP_LD(hhesplat, 1);
6527GEN_SPEOP_LD(hhousplat, 1);
6528GEN_SPEOP_LD(hhossplat, 1);
6529GEN_SPEOP_LD(wwsplat, 2);
6530GEN_SPEOP_LD(whsplat, 2);
6531
6532GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6533GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6534GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6535GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6536GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6537GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6538GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6539GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6540GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6541GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6542GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6543GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6544GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6545GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6546GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6547GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6548GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6549GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6550
6551/* Multiply and add - TODO */
6552#if 0
6553GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6554GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6555GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6556GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6557GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6558GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6559GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6560GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6561GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6562GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6563GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6564GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6565
6566GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6567GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6568GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6569GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6570GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6571GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6572GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6573GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6574GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6575GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6576GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6577GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6578GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6579GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6580
6581GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6582GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6583GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6584GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6585GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6586GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6587
6588GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6589GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6590GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6591GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6592GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6593GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6594GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6595GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6596GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6597GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6598GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6599GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6600
6601GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6602GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6603GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6604GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6605GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6606
6607GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6608GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6609GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6610GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6611GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6612GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6613GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6614GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6615GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6616GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6617GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6618GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6619
6620GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6621GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6622GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6623GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6624GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6625#endif
6626
6627/*** SPE floating-point extension ***/
6628#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 6629static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6630{ \
6631 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6632 gen_op_##name(); \
6633 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6634}
6635
6636/* Single precision floating-point vectors operations */
6637/* Arithmetic */
6638GEN_SPEOP_ARITH2(evfsadd);
6639GEN_SPEOP_ARITH2(evfssub);
6640GEN_SPEOP_ARITH2(evfsmul);
6641GEN_SPEOP_ARITH2(evfsdiv);
6642GEN_SPEOP_ARITH1(evfsabs);
6643GEN_SPEOP_ARITH1(evfsnabs);
6644GEN_SPEOP_ARITH1(evfsneg);
6645/* Conversion */
6646GEN_SPEFPUOP_CONV(evfscfui);
6647GEN_SPEFPUOP_CONV(evfscfsi);
6648GEN_SPEFPUOP_CONV(evfscfuf);
6649GEN_SPEFPUOP_CONV(evfscfsf);
6650GEN_SPEFPUOP_CONV(evfsctui);
6651GEN_SPEFPUOP_CONV(evfsctsi);
6652GEN_SPEFPUOP_CONV(evfsctuf);
6653GEN_SPEFPUOP_CONV(evfsctsf);
6654GEN_SPEFPUOP_CONV(evfsctuiz);
6655GEN_SPEFPUOP_CONV(evfsctsiz);
6656/* Comparison */
6657GEN_SPEOP_COMP(evfscmpgt);
6658GEN_SPEOP_COMP(evfscmplt);
6659GEN_SPEOP_COMP(evfscmpeq);
6660GEN_SPEOP_COMP(evfststgt);
6661GEN_SPEOP_COMP(evfststlt);
6662GEN_SPEOP_COMP(evfststeq);
6663
6664/* Opcodes definitions */
6665GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6666GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6667GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6668GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6669GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6670GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6671GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6672GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6673GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6674GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6675GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6676GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6677GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6678GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6679
6680/* Single precision floating-point operations */
6681/* Arithmetic */
6682GEN_SPEOP_ARITH2(efsadd);
6683GEN_SPEOP_ARITH2(efssub);
6684GEN_SPEOP_ARITH2(efsmul);
6685GEN_SPEOP_ARITH2(efsdiv);
6686GEN_SPEOP_ARITH1(efsabs);
6687GEN_SPEOP_ARITH1(efsnabs);
6688GEN_SPEOP_ARITH1(efsneg);
6689/* Conversion */
6690GEN_SPEFPUOP_CONV(efscfui);
6691GEN_SPEFPUOP_CONV(efscfsi);
6692GEN_SPEFPUOP_CONV(efscfuf);
6693GEN_SPEFPUOP_CONV(efscfsf);
6694GEN_SPEFPUOP_CONV(efsctui);
6695GEN_SPEFPUOP_CONV(efsctsi);
6696GEN_SPEFPUOP_CONV(efsctuf);
6697GEN_SPEFPUOP_CONV(efsctsf);
6698GEN_SPEFPUOP_CONV(efsctuiz);
6699GEN_SPEFPUOP_CONV(efsctsiz);
6700GEN_SPEFPUOP_CONV(efscfd);
6701/* Comparison */
6702GEN_SPEOP_COMP(efscmpgt);
6703GEN_SPEOP_COMP(efscmplt);
6704GEN_SPEOP_COMP(efscmpeq);
6705GEN_SPEOP_COMP(efststgt);
6706GEN_SPEOP_COMP(efststlt);
6707GEN_SPEOP_COMP(efststeq);
6708
6709/* Opcodes definitions */
6710GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6711GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6712GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6713GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6714GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6715GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6716GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6717GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6718GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6719GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
6720GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6721GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6722GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6723
6724/* Double precision floating-point operations */
6725/* Arithmetic */
6726GEN_SPEOP_ARITH2(efdadd);
6727GEN_SPEOP_ARITH2(efdsub);
6728GEN_SPEOP_ARITH2(efdmul);
6729GEN_SPEOP_ARITH2(efddiv);
6730GEN_SPEOP_ARITH1(efdabs);
6731GEN_SPEOP_ARITH1(efdnabs);
6732GEN_SPEOP_ARITH1(efdneg);
6733/* Conversion */
6734
6735GEN_SPEFPUOP_CONV(efdcfui);
6736GEN_SPEFPUOP_CONV(efdcfsi);
6737GEN_SPEFPUOP_CONV(efdcfuf);
6738GEN_SPEFPUOP_CONV(efdcfsf);
6739GEN_SPEFPUOP_CONV(efdctui);
6740GEN_SPEFPUOP_CONV(efdctsi);
6741GEN_SPEFPUOP_CONV(efdctuf);
6742GEN_SPEFPUOP_CONV(efdctsf);
6743GEN_SPEFPUOP_CONV(efdctuiz);
6744GEN_SPEFPUOP_CONV(efdctsiz);
6745GEN_SPEFPUOP_CONV(efdcfs);
6746GEN_SPEFPUOP_CONV(efdcfuid);
6747GEN_SPEFPUOP_CONV(efdcfsid);
6748GEN_SPEFPUOP_CONV(efdctuidz);
6749GEN_SPEFPUOP_CONV(efdctsidz);
6750/* Comparison */
6751GEN_SPEOP_COMP(efdcmpgt);
6752GEN_SPEOP_COMP(efdcmplt);
6753GEN_SPEOP_COMP(efdcmpeq);
6754GEN_SPEOP_COMP(efdtstgt);
6755GEN_SPEOP_COMP(efdtstlt);
6756GEN_SPEOP_COMP(efdtsteq);
6757
6758/* Opcodes definitions */
6759GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6760GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6761GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6762GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6763GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6764GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6765GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6766GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6767GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6768GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6769GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6770GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6771GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6772GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6773GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6774GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6775
79aceca5
FB		 6776/* End opcode list */
6777GEN_OPCODE_MARK(end);
6778
3fc6c082 6779#include "translate_init.c"
0411a972 6780#include "helper_regs.h"
79aceca5 6781
9a64fbe4 6782/*****************************************************************************/
3fc6c082 6783/* Misc PowerPC helpers */
36081602
JM		 6784void cpu_dump_state (CPUState *env, FILE *f,
6785 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6786 int flags)
79aceca5 6787{
3fc6c082
FB		 6788#if defined(TARGET_PPC64) || 1
6789#define FILL ""
3fc6c082
FB		 6790#define RGPL 4
6791#define RFPL 4
6792#else
6793#define FILL " "
3fc6c082
FB		 6794#define RGPL 8
6795#define RFPL 4
6796#endif
6797
79aceca5
FB		 6798 int i;
6799
077fc206
JM		 6800 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6801 env->nip, env->lr, env->ctr, hreg_load_xer(env));
6802 cpu_fprintf(f, "MSR " REGX FILL " HID0 " REGX FILL " HF " REGX FILL
6803 " idx %d\n",
6804 env->msr, env->hflags, env->spr[SPR_HID0], env->mmu_idx);
d9bce9d9 6805#if !defined(NO_TIMER_DUMP)
077fc206 6806 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6807#if !defined(CONFIG_USER_ONLY)
6808 "DECR %08x"
6809#endif
6810 "\n",
077fc206 6811 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6812#if !defined(CONFIG_USER_ONLY)
6813 , cpu_ppc_load_decr(env)
6814#endif
6815 );
077fc206 6816#endif
76a66253 6817 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6818 if ((i & (RGPL - 1)) == 0)
6819 cpu_fprintf(f, "GPR%02d", i);
a750fc0b 6820 cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
3fc6c082 6821 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6822 cpu_fprintf(f, "\n");
76a66253 6823 }
3fc6c082 6824 cpu_fprintf(f, "CR ");
76a66253 6825 for (i = 0; i < 8; i++)
7fe48483
FB		 6826 cpu_fprintf(f, "%01x", env->crf[i]);
6827 cpu_fprintf(f, " [");
76a66253
JM		 6828 for (i = 0; i < 8; i++) {
6829 char a = '-';
6830 if (env->crf[i] & 0x08)
6831 a = 'L';
6832 else if (env->crf[i] & 0x04)
6833 a = 'G';
6834 else if (env->crf[i] & 0x02)
6835 a = 'E';
7fe48483 6836 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6837 }
3fc6c082
FB		 6838 cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
6839 for (i = 0; i < 32; i++) {
6840 if ((i & (RFPL - 1)) == 0)
6841 cpu_fprintf(f, "FPR%02d", i);
26a76461 6842 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6843 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6844 cpu_fprintf(f, "\n");
79aceca5 6845 }
f2e63a42 6846#if !defined(CONFIG_USER_ONLY)
077fc206 6847 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " SDR1 " REGX "\n",
3fc6c082 6848 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6849#endif
79aceca5 6850
3fc6c082
FB		 6851#undef RGPL
6852#undef RFPL
6853#undef FILL
79aceca5
FB		 6854}
6855
76a66253
JM		 6856void cpu_dump_statistics (CPUState *env, FILE*f,
6857 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6858 int flags)
6859{
6860#if defined(DO_PPC_STATISTICS)
6861 opc_handler_t **t1, **t2, **t3, *handler;
6862 int op1, op2, op3;
6863
6864 t1 = env->opcodes;
6865 for (op1 = 0; op1 < 64; op1++) {
6866 handler = t1[op1];
6867 if (is_indirect_opcode(handler)) {
6868 t2 = ind_table(handler);
6869 for (op2 = 0; op2 < 32; op2++) {
6870 handler = t2[op2];
6871 if (is_indirect_opcode(handler)) {
6872 t3 = ind_table(handler);
6873 for (op3 = 0; op3 < 32; op3++) {
6874 handler = t3[op3];
6875 if (handler->count == 0)
6876 continue;
6877 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6878 "%016llx %lld\n",
6879 op1, op2, op3, op1, (op3 << 5) | op2,
6880 handler->oname,
6881 handler->count, handler->count);
6882 }
6883 } else {
6884 if (handler->count == 0)
6885 continue;
6886 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6887 "%016llx %lld\n",
6888 op1, op2, op1, op2, handler->oname,
6889 handler->count, handler->count);
6890 }
6891 }
6892 } else {
6893 if (handler->count == 0)
6894 continue;
6895 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6896 op1, op1, handler->oname,
6897 handler->count, handler->count);
6898 }
6899 }
6900#endif
6901}
6902
9a64fbe4 6903/*****************************************************************************/
b068d6a7
JM		 6904static always_inline int gen_intermediate_code_internal (CPUState *env,
6905 TranslationBlock *tb,
6906 int search_pc)
79aceca5 6907{
9fddaa0c 6908 DisasContext ctx, *ctxp = &ctx;
79aceca5 6909 opc_handler_t **table, *handler;
0fa85d43 6910 target_ulong pc_start;
79aceca5 6911 uint16_t *gen_opc_end;
056401ea 6912 int supervisor, little_endian;
d26bfc9a 6913 int single_step, branch_step;
79aceca5 6914 int j, lj = -1;
79aceca5
FB		 6915
6916 pc_start = tb->pc;
6917 gen_opc_ptr = gen_opc_buf;
6918 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6919 gen_opparam_ptr = gen_opparam_buf;
7c58044c
JM		 6920#if defined(OPTIMIZE_FPRF_UPDATE)
6921 gen_fprf_ptr = gen_fprf_buf;
6922#endif
c53be334 6923 nb_gen_labels = 0;
046d6672 6924 ctx.nip = pc_start;
79aceca5 6925 ctx.tb = tb;
e1833e1f 6926 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6927 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6928 supervisor = env->mmu_idx;
6929#if !defined(CONFIG_USER_ONLY)
2857068e 6930 ctx.supervisor = supervisor;
d9bce9d9 6931#endif
056401ea 6932 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6933#if defined(TARGET_PPC64)
6934 ctx.sf_mode = msr_sf;
056401ea 6935 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6936#else
056401ea 6937 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6938#endif
d63001d1 6939 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6940 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6941 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6942 ctx.spe_enabled = msr_spe;
6943 else
6944 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6945 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6946 ctx.altivec_enabled = msr_vr;
6947 else
6948 ctx.altivec_enabled = 0;
d26bfc9a
JM		 6949 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6950 single_step = 1;
6951 else
6952 single_step = 0;
6953 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6954 branch_step = 1;
6955 else
6956 branch_step = 0;
b33c17e1 6957 ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;
3fc6c082 6958#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6959 /* Single step trace mode */
6960 msr_se = 1;
6961#endif
6962 /* Set env in case of segfault during code fetch */
e1833e1f 6963 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6964 if (unlikely(env->nb_breakpoints > 0)) {
6965 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6966 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6967 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6968 gen_op_debug();
6969 break;
6970 }
6971 }
6972 }
76a66253 6973 if (unlikely(search_pc)) {
79aceca5
FB		 6974 j = gen_opc_ptr - gen_opc_buf;
6975 if (lj < j) {
6976 lj++;
6977 while (lj < j)
6978 gen_opc_instr_start[lj++] = 0;
046d6672 6979 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 6980 gen_opc_instr_start[lj] = 1;
6981 }
6982 }
9fddaa0c
FB		 6983#if defined PPC_DEBUG_DISAS
6984 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6985 fprintf(logfile, "----------------\n");
1b9eb036 6986 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6987 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6988 }
6989#endif
056401ea
JM		 6990 if (unlikely(little_endian)) {
6991 ctx.opcode = bswap32(ldl_code(ctx.nip));
6992 } else {
6993 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6994 }
9fddaa0c
FB		 6995#if defined PPC_DEBUG_DISAS
6996 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6997 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6998 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6999 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 7000 }
7001#endif
046d6672 7002 ctx.nip += 4;
3fc6c082 7003 table = env->opcodes;
79aceca5
FB		 7004 handler = table[opc1(ctx.opcode)];
7005 if (is_indirect_opcode(handler)) {
7006 table = ind_table(handler);
7007 handler = table[opc2(ctx.opcode)];
7008 if (is_indirect_opcode(handler)) {
7009 table = ind_table(handler);
7010 handler = table[opc3(ctx.opcode)];
7011 }
7012 }
7013 /* Is opcode *REALLY* valid ? */
76a66253 7014 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7015 if (loglevel != 0) {
76a66253 7016 fprintf(logfile, "invalid/unsupported opcode: "
1b9eb036 7017 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
76a66253 7018 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7019 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7020 } else {
7021 printf("invalid/unsupported opcode: "
1b9eb036 7022 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
4b3686fa 7023 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7024 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7025 }
76a66253
JM		 7026 } else {
7027 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7028 if (loglevel != 0) {
79aceca5 7029 fprintf(logfile, "invalid bits: %08x for opcode: "
e1833e1f 7030 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
79aceca5
FB		 7031 ctx.opcode & handler->inval, opc1(ctx.opcode),
7032 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7033 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7034 } else {
7035 printf("invalid bits: %08x for opcode: "
e1833e1f 7036 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
76a66253
JM		 7037 ctx.opcode & handler->inval, opc1(ctx.opcode),
7038 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7039 ctx.opcode, ctx.nip - 4);
76a66253 7040 }
e1833e1f 7041 GEN_EXCP_INVAL(ctxp);
4b3686fa 7042 break;
79aceca5 7043 }
79aceca5 7044 }
4b3686fa 7045 (*(handler->handler))(&ctx);
76a66253
JM		 7046#if defined(DO_PPC_STATISTICS)
7047 handler->count++;
7048#endif
9a64fbe4 7049 /* Check trace mode exceptions */
d26bfc9a
JM		 7050 if (unlikely(branch_step != 0 &&
7051 ctx.exception == POWERPC_EXCP_BRANCH)) {
7052 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
7053 } else if (unlikely(single_step != 0 &&
7054 (ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
7055 (ctx.nip & 0xFC) != 0x04) &&
417bf010 7056 ctx.exception != POWERPC_SYSCALL &&
d26bfc9a 7057 ctx.exception != POWERPC_EXCP_TRAP)) {
e1833e1f 7058 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a
JM		 7059 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7060 (env->singlestep_enabled))) {
7061 /* if we reach a page boundary or are single stepping, stop
7062 * generation
7063 */
8dd4983c 7064 break;
76a66253 7065 }
3fc6c082
FB		 7066#if defined (DO_SINGLE_STEP)
7067 break;
7068#endif
7069 }
e1833e1f 7070 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7071 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7072 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
76a66253
JM		 7073 gen_op_reset_T0();
7074 /* Generate the return instruction */
7075 gen_op_exit_tb();
9a64fbe4 7076 }
79aceca5 7077 *gen_opc_ptr = INDEX_op_end;
76a66253 7078 if (unlikely(search_pc)) {
9a64fbe4
FB		 7079 j = gen_opc_ptr - gen_opc_buf;
7080 lj++;
7081 while (lj <= j)
7082 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7083 } else {
046d6672 7084 tb->size = ctx.nip - pc_start;
9a64fbe4 7085 }
d9bce9d9 7086#if defined(DEBUG_DISAS)
9fddaa0c 7087 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7088 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7089 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7090 }
7091 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7092 int flags;
237c0af0 7093 flags = env->bfd_mach;
056401ea 7094 flags |= little_endian << 16;
0fa85d43 7095 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7096 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7097 fprintf(logfile, "\n");
9fddaa0c
FB		 7098 }
7099 if (loglevel & CPU_LOG_TB_OP) {
79aceca5
FB		 7100 fprintf(logfile, "OP:\n");
7101 dump_ops(gen_opc_buf, gen_opparam_buf);
7102 fprintf(logfile, "\n");
7103 }
7104#endif
79aceca5
FB		 7105 return 0;
7106}
7107
9a64fbe4 7108int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 7109{
7110 return gen_intermediate_code_internal(env, tb, 0);
7111}
7112
9a64fbe4 7113int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 7114{
7115 return gen_intermediate_code_internal(env, tb, 1);
7116}
Qemu copy for testing