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PowerPC merge (Jocelyn Mayer)
[qemu.git] / target-ppc / translate.c
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79aceca5
FB		 1/*
2 * PPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include "dyngen-exec.h"
21#include "cpu.h"
22#include "exec.h"
23#include "disas.h"
24
25//#define DO_SINGLE_STEP
26//#define DO_STEP_FLUSH
9a64fbe4 27//#define DEBUG_DISAS
79aceca5
FB		 28
29enum {
30#define DEF(s, n, copy_size) INDEX_op_ ## s,
31#include "opc.h"
32#undef DEF
33 NB_OPS,
34};
35
36static uint16_t *gen_opc_ptr;
37static uint32_t *gen_opparam_ptr;
38
39#include "gen-op.h"
28b6751f 40
28b6751f 41#define GEN8(func, NAME) \
9a64fbe4
FB		 42static GenOpFunc *NAME ## _table [8] = { \
43NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
44NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
45}; \
46static inline void func(int n) \
47{ \
48 NAME ## _table[n](); \
49}
50
51#define GEN16(func, NAME) \
52static GenOpFunc *NAME ## _table [16] = { \
53NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
54NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
55NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
56NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
57}; \
58static inline void func(int n) \
59{ \
60 NAME ## _table[n](); \
28b6751f
FB		 61}
62
63#define GEN32(func, NAME) \
9a64fbe4
FB		 64static GenOpFunc *NAME ## _table [32] = { \
65NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
66NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
67NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
68NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
69NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
70NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
71NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
72NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
73}; \
74static inline void func(int n) \
75{ \
76 NAME ## _table[n](); \
77}
78
79/* Condition register moves */
80GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
81GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
82GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
83GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
28b6751f 84
fb0eaffc
FB		 85/* Floating point condition and status register moves */
86GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
87GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
88GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
89static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
90 &gen_op_store_T0_fpscri_fpscr0,
91 &gen_op_store_T0_fpscri_fpscr1,
92 &gen_op_store_T0_fpscri_fpscr2,
93 &gen_op_store_T0_fpscri_fpscr3,
94 &gen_op_store_T0_fpscri_fpscr4,
95 &gen_op_store_T0_fpscri_fpscr5,
96 &gen_op_store_T0_fpscri_fpscr6,
97 &gen_op_store_T0_fpscri_fpscr7,
98};
99static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
100{
101 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
102}
103
9a64fbe4
FB		 104/* Segment register moves */
105GEN16(gen_op_load_sr, gen_op_load_sr);
106GEN16(gen_op_store_sr, gen_op_store_sr);
28b6751f 107
9a64fbe4
FB		 108/* General purpose registers moves */
109GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
110GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
111GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
112
113GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
114GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
115GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
28b6751f 116
fb0eaffc
FB		 117/* floating point registers moves */
118GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
119GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
120GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
121GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
122GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
123GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
79aceca5
FB		 124
125static uint8_t spr_access[1024 / 2];
126
127/* internal defines */
128typedef struct DisasContext {
129 struct TranslationBlock *tb;
130 uint32_t *nip;
131 uint32_t opcode;
9a64fbe4
FB		 132 uint32_t exception;
133 /* Time base offset */
79aceca5 134 uint32_t tb_offset;
9a64fbe4
FB		 135 /* Decrementer offset */
136 uint32_t decr_offset;
137 /* Execution mode */
138#if !defined(CONFIG_USER_ONLY)
79aceca5 139 int supervisor;
9a64fbe4
FB		 140#endif
141 /* Routine used to access memory */
142 int mem_idx;
79aceca5
FB		 143} DisasContext;
144
145typedef struct opc_handler_t {
146 /* invalid bits */
147 uint32_t inval;
9a64fbe4
FB		 148 /* instruction type */
149 uint32_t type;
79aceca5
FB		 150 /* handler */
151 void (*handler)(DisasContext *ctx);
152} opc_handler_t;
153
9a64fbe4 154#define RET_EXCP(excp, error) \
79aceca5 155do { \
9a64fbe4
FB		 156 gen_op_queue_exception_err(excp, error); \
157 ctx->exception = excp; \
79aceca5
FB		 158 return; \
159} while (0)
160
9a64fbe4
FB		 161#define RET_INVAL() \
162RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
163
164#define RET_PRIVOPC() \
165RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
166
167#define RET_PRIVREG() \
168RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
79aceca5
FB		 169
170#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
171static void gen_##name (DisasContext *ctx); \
172GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
173static void gen_##name (DisasContext *ctx)
174
79aceca5
FB		 175typedef struct opcode_t {
176 unsigned char opc1, opc2, opc3;
79aceca5
FB		 177 opc_handler_t handler;
178} opcode_t;
179
180/* XXX: move that elsewhere */
181extern FILE *logfile;
182extern int loglevel;
183
79aceca5
FB		 184/*** Instruction decoding ***/
185#define EXTRACT_HELPER(name, shift, nb) \
186static inline uint32_t name (uint32_t opcode) \
187{ \
188 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
189}
190
191#define EXTRACT_SHELPER(name, shift, nb) \
192static inline int32_t name (uint32_t opcode) \
193{ \
194 return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \
195}
196
197/* Opcode part 1 */
198EXTRACT_HELPER(opc1, 26, 6);
199/* Opcode part 2 */
200EXTRACT_HELPER(opc2, 1, 5);
201/* Opcode part 3 */
202EXTRACT_HELPER(opc3, 6, 5);
203/* Update Cr0 flags */
204EXTRACT_HELPER(Rc, 0, 1);
205/* Destination */
206EXTRACT_HELPER(rD, 21, 5);
207/* Source */
208EXTRACT_HELPER(rS, 21, 5);
209/* First operand */
210EXTRACT_HELPER(rA, 16, 5);
211/* Second operand */
212EXTRACT_HELPER(rB, 11, 5);
213/* Third operand */
214EXTRACT_HELPER(rC, 6, 5);
215/*** Get CRn ***/
216EXTRACT_HELPER(crfD, 23, 3);
217EXTRACT_HELPER(crfS, 18, 3);
218EXTRACT_HELPER(crbD, 21, 5);
219EXTRACT_HELPER(crbA, 16, 5);
220EXTRACT_HELPER(crbB, 11, 5);
221/* SPR / TBL */
222EXTRACT_HELPER(SPR, 11, 10);
223/*** Get constants ***/
224EXTRACT_HELPER(IMM, 12, 8);
225/* 16 bits signed immediate value */
226EXTRACT_SHELPER(SIMM, 0, 16);
227/* 16 bits unsigned immediate value */
228EXTRACT_HELPER(UIMM, 0, 16);
229/* Bit count */
230EXTRACT_HELPER(NB, 11, 5);
231/* Shift count */
232EXTRACT_HELPER(SH, 11, 5);
233/* Mask start */
234EXTRACT_HELPER(MB, 6, 5);
235/* Mask end */
236EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 237/* Trap operand */
238EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 239
240EXTRACT_HELPER(CRM, 12, 8);
241EXTRACT_HELPER(FM, 17, 8);
242EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 243EXTRACT_HELPER(FPIMM, 20, 4);
244
79aceca5
FB		 245/*** Jump target decoding ***/
246/* Displacement */
247EXTRACT_SHELPER(d, 0, 16);
248/* Immediate address */
249static inline uint32_t LI (uint32_t opcode)
250{
251 return (opcode >> 0) & 0x03FFFFFC;
252}
253
254static inline uint32_t BD (uint32_t opcode)
255{
256 return (opcode >> 0) & 0xFFFC;
257}
258
259EXTRACT_HELPER(BO, 21, 5);
260EXTRACT_HELPER(BI, 16, 5);
261/* Absolute/relative address */
262EXTRACT_HELPER(AA, 1, 1);
263/* Link */
264EXTRACT_HELPER(LK, 0, 1);
265
266/* Create a mask between <start> and <end> bits */
267static inline uint32_t MASK (uint32_t start, uint32_t end)
268{
269 uint32_t ret;
270
271 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
272 if (start > end)
273 return ~ret;
274
275 return ret;
276}
277
278#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
279__attribute__ ((section(".opcodes"), unused)) \
280static opcode_t opc_##name = { \
281 .opc1 = op1, \
282 .opc2 = op2, \
283 .opc3 = op3, \
79aceca5
FB		 284 .handler = { \
285 .inval = invl, \
9a64fbe4 286 .type = _typ, \
79aceca5
FB		 287 .handler = &gen_##name, \
288 }, \
289}
290
291#define GEN_OPCODE_MARK(name) \
292__attribute__ ((section(".opcodes"), unused)) \
293static opcode_t opc_##name = { \
294 .opc1 = 0xFF, \
295 .opc2 = 0xFF, \
296 .opc3 = 0xFF, \
79aceca5
FB		 297 .handler = { \
298 .inval = 0x00000000, \
9a64fbe4 299 .type = 0x00, \
79aceca5
FB		 300 .handler = NULL, \
301 }, \
302}
303
304/* Start opcode list */
305GEN_OPCODE_MARK(start);
306
307/* Invalid instruction */
9a64fbe4
FB		 308GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
309{
310 RET_INVAL();
311}
312
313/* Special opcode to stop emulation */
314GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
79aceca5 315{
9a64fbe4
FB		 316 gen_op_queue_exception(EXCP_HLT);
317 ctx->exception = EXCP_HLT;
318}
319
320/* Special opcode to call open-firmware */
321GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
322{
323 gen_op_queue_exception(EXCP_OFCALL);
324 ctx->exception = EXCP_OFCALL;
325}
326
327/* Special opcode to call RTAS */
328GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
329{
330 printf("RTAS entry point !\n");
331 gen_op_queue_exception(EXCP_RTASCALL);
332 ctx->exception = EXCP_RTASCALL;
79aceca5
FB		 333}
334
335static opc_handler_t invalid_handler = {
336 .inval = 0xFFFFFFFF,
9a64fbe4 337 .type = PPC_NONE,
79aceca5
FB		 338 .handler = gen_invalid,
339};
340
341/*** Integer arithmetic ***/
342#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
343GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
344{ \
345 gen_op_load_gpr_T0(rA(ctx->opcode)); \
346 gen_op_load_gpr_T1(rB(ctx->opcode)); \
347 gen_op_##name(); \
348 if (Rc(ctx->opcode) != 0) \
349 gen_op_set_Rc0(); \
350 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 351}
352
353#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
354GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
355{ \
356 gen_op_load_gpr_T0(rA(ctx->opcode)); \
357 gen_op_load_gpr_T1(rB(ctx->opcode)); \
358 gen_op_##name(); \
359 if (Rc(ctx->opcode) != 0) \
360 gen_op_set_Rc0_ov(); \
361 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 362}
363
364#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
365GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
366{ \
367 gen_op_load_gpr_T0(rA(ctx->opcode)); \
368 gen_op_##name(); \
369 if (Rc(ctx->opcode) != 0) \
370 gen_op_set_Rc0(); \
371 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 372}
373#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
374GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
375{ \
376 gen_op_load_gpr_T0(rA(ctx->opcode)); \
377 gen_op_##name(); \
378 if (Rc(ctx->opcode) != 0) \
379 gen_op_set_Rc0_ov(); \
380 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 381}
382
383/* Two operands arithmetic functions */
384#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
385__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
386__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
387
388/* Two operands arithmetic functions with no overflow allowed */
389#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
390__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
391
392/* One operand arithmetic functions */
393#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
394__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
395__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
396
397/* add add. addo addo. */
398GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
399/* addc addc. addco addco. */
400GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
401/* adde adde. addeo addeo. */
402GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
403/* addme addme. addmeo addmeo. */
404GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
405/* addze addze. addzeo addzeo. */
406GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
407/* divw divw. divwo divwo. */
408GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
409/* divwu divwu. divwuo divwuo. */
410GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
411/* mulhw mulhw. */
412GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
413/* mulhwu mulhwu. */
414GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
415/* mullw mullw. mullwo mullwo. */
416GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
417/* neg neg. nego nego. */
418GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
419/* subf subf. subfo subfo. */
420GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
421/* subfc subfc. subfco subfco. */
422GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
423/* subfe subfe. subfeo subfeo. */
424GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
425/* subfme subfme. subfmeo subfmeo. */
426GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
427/* subfze subfze. subfzeo subfzeo. */
428GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
429/* addi */
430GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
431{
432 int32_t simm = SIMM(ctx->opcode);
433
434 if (rA(ctx->opcode) == 0) {
435 gen_op_set_T0(simm);
436 } else {
437 gen_op_load_gpr_T0(rA(ctx->opcode));
438 gen_op_addi(simm);
439 }
440 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 441}
442/* addic */
443GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
444{
445 gen_op_load_gpr_T0(rA(ctx->opcode));
446 gen_op_addic(SIMM(ctx->opcode));
447 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 448}
449/* addic. */
450GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
451{
452 gen_op_load_gpr_T0(rA(ctx->opcode));
453 gen_op_addic(SIMM(ctx->opcode));
454 gen_op_set_Rc0();
455 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 456}
457/* addis */
458GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
459{
460 int32_t simm = SIMM(ctx->opcode);
461
462 if (rA(ctx->opcode) == 0) {
463 gen_op_set_T0(simm << 16);
464 } else {
465 gen_op_load_gpr_T0(rA(ctx->opcode));
466 gen_op_addi(simm << 16);
467 }
468 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 469}
470/* mulli */
471GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
472{
473 gen_op_load_gpr_T0(rA(ctx->opcode));
474 gen_op_mulli(SIMM(ctx->opcode));
475 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 476}
477/* subfic */
478GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
479{
480 gen_op_load_gpr_T0(rA(ctx->opcode));
481 gen_op_subfic(SIMM(ctx->opcode));
482 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 483}
484
485/*** Integer comparison ***/
486#define GEN_CMP(name, opc) \
487GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
488{ \
489 gen_op_load_gpr_T0(rA(ctx->opcode)); \
490 gen_op_load_gpr_T1(rB(ctx->opcode)); \
491 gen_op_##name(); \
492 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5
FB		 493}
494
495/* cmp */
496GEN_CMP(cmp, 0x00);
497/* cmpi */
498GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
499{
500 gen_op_load_gpr_T0(rA(ctx->opcode));
501 gen_op_cmpi(SIMM(ctx->opcode));
502 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 503}
504/* cmpl */
505GEN_CMP(cmpl, 0x01);
506/* cmpli */
507GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
508{
509 gen_op_load_gpr_T0(rA(ctx->opcode));
510 gen_op_cmpli(UIMM(ctx->opcode));
511 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 512}
513
514/*** Integer logical ***/
515#define __GEN_LOGICAL2(name, opc2, opc3) \
516GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
517{ \
518 gen_op_load_gpr_T0(rS(ctx->opcode)); \
519 gen_op_load_gpr_T1(rB(ctx->opcode)); \
520 gen_op_##name(); \
521 if (Rc(ctx->opcode) != 0) \
522 gen_op_set_Rc0(); \
523 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 524}
525#define GEN_LOGICAL2(name, opc) \
526__GEN_LOGICAL2(name, 0x1C, opc)
527
528#define GEN_LOGICAL1(name, opc) \
529GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
530{ \
531 gen_op_load_gpr_T0(rS(ctx->opcode)); \
532 gen_op_##name(); \
533 if (Rc(ctx->opcode) != 0) \
534 gen_op_set_Rc0(); \
535 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 536}
537
538/* and & and. */
539GEN_LOGICAL2(and, 0x00);
540/* andc & andc. */
541GEN_LOGICAL2(andc, 0x01);
542/* andi. */
543GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
544{
545 gen_op_load_gpr_T0(rS(ctx->opcode));
546 gen_op_andi_(UIMM(ctx->opcode));
547 gen_op_set_Rc0();
548 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 549}
550/* andis. */
551GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
552{
553 gen_op_load_gpr_T0(rS(ctx->opcode));
554 gen_op_andi_(UIMM(ctx->opcode) << 16);
555 gen_op_set_Rc0();
556 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 557}
558
559/* cntlzw */
560GEN_LOGICAL1(cntlzw, 0x00);
561/* eqv & eqv. */
562GEN_LOGICAL2(eqv, 0x08);
563/* extsb & extsb. */
564GEN_LOGICAL1(extsb, 0x1D);
565/* extsh & extsh. */
566GEN_LOGICAL1(extsh, 0x1C);
567/* nand & nand. */
568GEN_LOGICAL2(nand, 0x0E);
569/* nor & nor. */
570GEN_LOGICAL2(nor, 0x03);
9a64fbe4 571
79aceca5 572/* or & or. */
9a64fbe4
FB		 573GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
574{
575 gen_op_load_gpr_T0(rS(ctx->opcode));
576 /* Optimisation for mr case */
577 if (rS(ctx->opcode) != rB(ctx->opcode)) {
578 gen_op_load_gpr_T1(rB(ctx->opcode));
579 gen_op_or();
580 }
581 if (Rc(ctx->opcode) != 0)
582 gen_op_set_Rc0();
583 gen_op_store_T0_gpr(rA(ctx->opcode));
584}
585
79aceca5
FB		 586/* orc & orc. */
587GEN_LOGICAL2(orc, 0x0C);
588/* xor & xor. */
9a64fbe4
FB		 589GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
590{
591 gen_op_load_gpr_T0(rS(ctx->opcode));
592 /* Optimisation for "set to zero" case */
593 if (rS(ctx->opcode) != rB(ctx->opcode)) {
594 gen_op_load_gpr_T1(rB(ctx->opcode));
595 gen_op_xor();
596 } else {
597 gen_op_set_T0(0);
598 }
599 if (Rc(ctx->opcode) != 0)
600 gen_op_set_Rc0();
601 gen_op_store_T0_gpr(rA(ctx->opcode));
602}
79aceca5
FB		 603/* ori */
604GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
605{
606 uint32_t uimm = UIMM(ctx->opcode);
607
9a64fbe4
FB		 608 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
609 /* NOP */
610 return;
79aceca5 611 }
79aceca5 612 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 613 if (uimm != 0)
79aceca5
FB		 614 gen_op_ori(uimm);
615 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 616}
617/* oris */
618GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
619{
620 uint32_t uimm = UIMM(ctx->opcode);
621
9a64fbe4
FB		 622 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
623 /* NOP */
624 return;
79aceca5 625 }
79aceca5 626 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 627 if (uimm != 0)
79aceca5
FB		 628 gen_op_ori(uimm << 16);
629 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 630}
631/* xori */
632GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
633{
9a64fbe4
FB		 634 uint32_t uimm = UIMM(ctx->opcode);
635
636 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
637 /* NOP */
638 return;
639 }
79aceca5 640 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 641 if (uimm != 0)
79aceca5
FB		 642 gen_op_xori(UIMM(ctx->opcode));
643 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 644}
645
646/* xoris */
647GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
648{
9a64fbe4
FB		 649 uint32_t uimm = UIMM(ctx->opcode);
650
651 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
652 /* NOP */
653 return;
654 }
79aceca5 655 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 656 if (uimm != 0)
79aceca5
FB		 657 gen_op_xori(UIMM(ctx->opcode) << 16);
658 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 659}
660
661/*** Integer rotate ***/
662/* rlwimi & rlwimi. */
663GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
664{
665 uint32_t mb, me;
666
667 mb = MB(ctx->opcode);
668 me = ME(ctx->opcode);
669 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 670 gen_op_load_gpr_T1(rA(ctx->opcode));
79aceca5
FB		 671 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
672 if (Rc(ctx->opcode) != 0)
673 gen_op_set_Rc0();
674 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 675}
676/* rlwinm & rlwinm. */
677GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
678{
679 uint32_t mb, me, sh;
680
681 sh = SH(ctx->opcode);
682 mb = MB(ctx->opcode);
683 me = ME(ctx->opcode);
684 gen_op_load_gpr_T0(rS(ctx->opcode));
79aceca5
FB		 685 if (mb == 0) {
686 if (me == 31) {
687 gen_op_rotlwi(sh);
688 goto store;
689 } else if (me == (31 - sh)) {
690 gen_op_slwi(sh);
691 goto store;
692 } else if (sh == 0) {
693 gen_op_andi_(MASK(0, me));
694 goto store;
695 }
696 } else if (me == 31) {
697 if (sh == (32 - mb)) {
698 gen_op_srwi(mb);
699 goto store;
700 } else if (sh == 0) {
701 gen_op_andi_(MASK(mb, 31));
702 goto store;
703 }
704 }
705 gen_op_rlwinm(sh, MASK(mb, me));
706store:
707 if (Rc(ctx->opcode) != 0)
708 gen_op_set_Rc0();
709 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 710}
711/* rlwnm & rlwnm. */
712GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
713{
714 uint32_t mb, me;
715
716 mb = MB(ctx->opcode);
717 me = ME(ctx->opcode);
718 gen_op_load_gpr_T0(rS(ctx->opcode));
719 gen_op_load_gpr_T1(rB(ctx->opcode));
720 if (mb == 0 && me == 31) {
721 gen_op_rotl();
722 } else
723 {
724 gen_op_rlwnm(MASK(mb, me));
725 }
726 if (Rc(ctx->opcode) != 0)
727 gen_op_set_Rc0();
728 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 729}
730
731/*** Integer shift ***/
732/* slw & slw. */
733__GEN_LOGICAL2(slw, 0x18, 0x00);
734/* sraw & sraw. */
735__GEN_LOGICAL2(sraw, 0x18, 0x18);
736/* srawi & srawi. */
737GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
738{
739 gen_op_load_gpr_T0(rS(ctx->opcode));
740 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
741 if (Rc(ctx->opcode) != 0)
742 gen_op_set_Rc0();
743 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 744}
745/* srw & srw. */
746__GEN_LOGICAL2(srw, 0x18, 0x10);
747
748/*** Floating-Point arithmetic ***/
9a64fbe4
FB		 749#define _GEN_FLOAT_ACB(name, op1, op2) \
750GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
751{ \
752 gen_op_reset_scrfx(); \
753 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
754 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
755 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
756 gen_op_f##name(); \
757 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
758 if (Rc(ctx->opcode)) \
759 gen_op_set_Rc1(); \
760}
761
762#define GEN_FLOAT_ACB(name, op2) \
763_GEN_FLOAT_ACB(name, 0x3F, op2); \
764_GEN_FLOAT_ACB(name##s, 0x3B, op2);
765
766#define _GEN_FLOAT_AB(name, op1, op2, inval) \
767GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
768{ \
769 gen_op_reset_scrfx(); \
770 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
771 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
772 gen_op_f##name(); \
773 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
774 if (Rc(ctx->opcode)) \
775 gen_op_set_Rc1(); \
776}
777#define GEN_FLOAT_AB(name, op2, inval) \
778_GEN_FLOAT_AB(name, 0x3F, op2, inval); \
779_GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
780
781#define _GEN_FLOAT_AC(name, op1, op2, inval) \
782GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
783{ \
784 gen_op_reset_scrfx(); \
785 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
786 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
787 gen_op_f##name(); \
788 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
789 if (Rc(ctx->opcode)) \
790 gen_op_set_Rc1(); \
791}
792#define GEN_FLOAT_AC(name, op2, inval) \
793_GEN_FLOAT_AC(name, 0x3F, op2, inval); \
794_GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
795
796#define GEN_FLOAT_B(name, op2, op3) \
797GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
798{ \
799 gen_op_reset_scrfx(); \
800 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
801 gen_op_f##name(); \
802 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
803 if (Rc(ctx->opcode)) \
804 gen_op_set_Rc1(); \
79aceca5
FB		 805}
806
9a64fbe4
FB		 807#define GEN_FLOAT_BS(name, op2) \
808GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
809{ \
810 gen_op_reset_scrfx(); \
811 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
812 gen_op_f##name(); \
813 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
814 if (Rc(ctx->opcode)) \
815 gen_op_set_Rc1(); \
79aceca5
FB		 816}
817
9a64fbe4
FB		 818/* fadd - fadds */
819GEN_FLOAT_AB(add, 0x15, 0x000007C0);
79aceca5 820/* fdiv */
9a64fbe4 821GEN_FLOAT_AB(div, 0x12, 0x000007C0);
79aceca5 822/* fmul */
9a64fbe4 823GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
79aceca5
FB		 824
825/* fres */
9a64fbe4 826GEN_FLOAT_BS(res, 0x18);
79aceca5
FB		 827
828/* frsqrte */
9a64fbe4 829GEN_FLOAT_BS(rsqrte, 0x1A);
79aceca5
FB		 830
831/* fsel */
9a64fbe4 832_GEN_FLOAT_ACB(sel, 0x3F, 0x17);
79aceca5 833/* fsub */
9a64fbe4 834GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
79aceca5
FB		 835/* Optional: */
836/* fsqrt */
9a64fbe4 837GEN_FLOAT_BS(sqrt, 0x16);
79aceca5 838
9a64fbe4 839GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
79aceca5 840{
9a64fbe4
FB		 841 gen_op_reset_scrfx();
842 gen_op_load_fpr_FT0(rB(ctx->opcode));
843 gen_op_fsqrts();
844 gen_op_store_FT0_fpr(rD(ctx->opcode));
845 if (Rc(ctx->opcode))
846 gen_op_set_Rc1();
79aceca5
FB		 847}
848
849/*** Floating-Point multiply-and-add ***/
850/* fmadd */
9a64fbe4 851GEN_FLOAT_ACB(madd, 0x1D);
79aceca5 852/* fmsub */
9a64fbe4 853GEN_FLOAT_ACB(msub, 0x1C);
79aceca5 854/* fnmadd */
9a64fbe4 855GEN_FLOAT_ACB(nmadd, 0x1F);
79aceca5 856/* fnmsub */
9a64fbe4 857GEN_FLOAT_ACB(nmsub, 0x1E);
79aceca5
FB		 858
859/*** Floating-Point round & convert ***/
860/* fctiw */
9a64fbe4 861GEN_FLOAT_B(ctiw, 0x0E, 0x00);
79aceca5 862/* fctiwz */
9a64fbe4 863GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
79aceca5 864/* frsp */
9a64fbe4 865GEN_FLOAT_B(rsp, 0x0C, 0x00);
79aceca5
FB		 866
867/*** Floating-Point compare ***/
868/* fcmpo */
869GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
870{
9a64fbe4
FB		 871 gen_op_reset_scrfx();
872 gen_op_load_fpr_FT0(rA(ctx->opcode));
873 gen_op_load_fpr_FT1(rB(ctx->opcode));
874 gen_op_fcmpo();
875 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 876}
877
878/* fcmpu */
879GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
880{
9a64fbe4
FB		 881 gen_op_reset_scrfx();
882 gen_op_load_fpr_FT0(rA(ctx->opcode));
883 gen_op_load_fpr_FT1(rB(ctx->opcode));
884 gen_op_fcmpu();
885 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 886}
887
9a64fbe4
FB		 888/*** Floating-point move ***/
889/* fabs */
890GEN_FLOAT_B(abs, 0x08, 0x08);
891
892/* fmr - fmr. */
893GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
894{
895 gen_op_reset_scrfx();
896 gen_op_load_fpr_FT0(rB(ctx->opcode));
897 gen_op_store_FT0_fpr(rD(ctx->opcode));
898 if (Rc(ctx->opcode))
899 gen_op_set_Rc1();
900}
901
902/* fnabs */
903GEN_FLOAT_B(nabs, 0x08, 0x04);
904/* fneg */
905GEN_FLOAT_B(neg, 0x08, 0x01);
906
79aceca5
FB		 907/*** Floating-Point status & ctrl register ***/
908/* mcrfs */
909GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
910{
fb0eaffc
FB		 911 gen_op_load_fpscr_T0(crfS(ctx->opcode));
912 gen_op_store_T0_crf(crfD(ctx->opcode));
913 gen_op_clear_fpscr(crfS(ctx->opcode));
79aceca5
FB		 914}
915
916/* mffs */
917GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
918{
28b6751f 919 gen_op_load_fpscr();
fb0eaffc
FB		 920 gen_op_store_FT0_fpr(rD(ctx->opcode));
921 if (Rc(ctx->opcode))
922 gen_op_set_Rc1();
79aceca5
FB		 923}
924
925/* mtfsb0 */
926GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
927{
fb0eaffc
FB		 928 uint8_t crb;
929
930 crb = crbD(ctx->opcode) >> 2;
931 gen_op_load_fpscr_T0(crb);
932 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
933 gen_op_store_T0_fpscr(crb);
934 if (Rc(ctx->opcode))
935 gen_op_set_Rc1();
79aceca5
FB		 936}
937
938/* mtfsb1 */
939GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
940{
fb0eaffc
FB		 941 uint8_t crb;
942
943 crb = crbD(ctx->opcode) >> 2;
944 gen_op_load_fpscr_T0(crb);
945 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
946 gen_op_store_T0_fpscr(crb);
947 if (Rc(ctx->opcode))
948 gen_op_set_Rc1();
79aceca5
FB		 949}
950
951/* mtfsf */
952GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
953{
fb0eaffc 954 gen_op_load_fpr_FT0(rB(ctx->opcode));
28b6751f 955 gen_op_store_fpscr(FM(ctx->opcode));
fb0eaffc
FB		 956 if (Rc(ctx->opcode))
957 gen_op_set_Rc1();
79aceca5
FB		 958}
959
960/* mtfsfi */
961GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
962{
fb0eaffc
FB		 963 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
964 if (Rc(ctx->opcode))
965 gen_op_set_Rc1();
79aceca5
FB		 966}
967
968/*** Integer load ***/
9a64fbe4
FB		 969#if defined(CONFIG_USER_ONLY)
970#define op_ldst(name) gen_op_##name##_raw()
971#define OP_LD_TABLE(width)
972#define OP_ST_TABLE(width)
973#else
974#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
975#define OP_LD_TABLE(width) \
976static GenOpFunc *gen_op_l##width[] = { \
977 &gen_op_l##width##_user, \
978 &gen_op_l##width##_kernel, \
979}
980#define OP_ST_TABLE(width) \
981static GenOpFunc *gen_op_st##width[] = { \
982 &gen_op_st##width##_user, \
983 &gen_op_st##width##_kernel, \
984}
985#endif
986
987#define GEN_LD(width, opc) \
79aceca5
FB		 988GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
989{ \
990 uint32_t simm = SIMM(ctx->opcode); \
991 if (rA(ctx->opcode) == 0) { \
9a64fbe4 992 gen_op_set_T0(simm); \
79aceca5
FB		 993 } else { \
994 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 995 if (simm != 0) \
996 gen_op_addi(simm); \
79aceca5 997 } \
9a64fbe4 998 op_ldst(l##width); \
79aceca5 999 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1000}
1001
9a64fbe4 1002#define GEN_LDU(width, opc) \
79aceca5
FB		 1003GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1004{ \
9a64fbe4 1005 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1006 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1007 rA(ctx->opcode) == rD(ctx->opcode)) { \
1008 RET_INVAL(); \
1009 } \
79aceca5 1010 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1011 if (simm != 0) \
1012 gen_op_addi(simm); \
1013 op_ldst(l##width); \
79aceca5
FB		 1014 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1015 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1016}
1017
9a64fbe4 1018#define GEN_LDUX(width, opc) \
79aceca5
FB		 1019GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1020{ \
1021 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1022 rA(ctx->opcode) == rD(ctx->opcode)) { \
1023 RET_INVAL(); \
1024 } \
79aceca5
FB		 1025 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1026 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1027 gen_op_add(); \
1028 op_ldst(l##width); \
79aceca5
FB		 1029 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1030 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1031}
1032
9a64fbe4 1033#define GEN_LDX(width, opc2, opc3) \
79aceca5
FB		 1034GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1035{ \
1036 if (rA(ctx->opcode) == 0) { \
1037 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1038 } else { \
1039 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1040 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1041 gen_op_add(); \
79aceca5 1042 } \
9a64fbe4 1043 op_ldst(l##width); \
79aceca5 1044 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1045}
1046
9a64fbe4
FB		 1047#define GEN_LDS(width, op) \
1048OP_LD_TABLE(width); \
1049GEN_LD(width, op | 0x20); \
1050GEN_LDU(width, op | 0x21); \
1051GEN_LDUX(width, op | 0x01); \
1052GEN_LDX(width, 0x17, op | 0x00)
79aceca5
FB		 1053
1054/* lbz lbzu lbzux lbzx */
9a64fbe4 1055GEN_LDS(bz, 0x02);
79aceca5 1056/* lha lhau lhaux lhax */
9a64fbe4 1057GEN_LDS(ha, 0x0A);
79aceca5 1058/* lhz lhzu lhzux lhzx */
9a64fbe4 1059GEN_LDS(hz, 0x08);
79aceca5 1060/* lwz lwzu lwzux lwzx */
9a64fbe4 1061GEN_LDS(wz, 0x00);
79aceca5
FB		 1062
1063/*** Integer store ***/
9a64fbe4 1064#define GEN_ST(width, opc) \
79aceca5
FB		 1065GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1066{ \
1067 uint32_t simm = SIMM(ctx->opcode); \
1068 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1069 gen_op_set_T0(simm); \
79aceca5
FB		 1070 } else { \
1071 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1072 if (simm != 0) \
1073 gen_op_addi(simm); \
79aceca5 1074 } \
9a64fbe4
FB		 1075 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1076 op_ldst(st##width); \
79aceca5
FB		 1077}
1078
9a64fbe4 1079#define GEN_STU(width, opc) \
79aceca5
FB		 1080GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1081{ \
9a64fbe4
FB		 1082 uint32_t simm = SIMM(ctx->opcode); \
1083 if (rA(ctx->opcode) == 0) { \
1084 RET_INVAL(); \
1085 } \
79aceca5 1086 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1087 if (simm != 0) \
1088 gen_op_addi(simm); \
79aceca5 1089 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 1090 op_ldst(st##width); \
79aceca5 1091 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1092}
1093
9a64fbe4 1094#define GEN_STUX(width, opc) \
79aceca5
FB		 1095GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1096{ \
9a64fbe4
FB		 1097 if (rA(ctx->opcode) == 0) { \
1098 RET_INVAL(); \
1099 } \
79aceca5
FB		 1100 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1101 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1102 gen_op_add(); \
1103 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1104 op_ldst(st##width); \
79aceca5 1105 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1106}
1107
9a64fbe4 1108#define GEN_STX(width, opc2, opc3) \
79aceca5
FB		 1109GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1110{ \
1111 if (rA(ctx->opcode) == 0) { \
1112 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1113 } else { \
1114 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1115 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1116 gen_op_add(); \
79aceca5 1117 } \
9a64fbe4
FB		 1118 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1119 op_ldst(st##width); \
79aceca5
FB		 1120}
1121
9a64fbe4
FB		 1122#define GEN_STS(width, op) \
1123OP_ST_TABLE(width); \
1124GEN_ST(width, op | 0x20); \
1125GEN_STU(width, op | 0x21); \
1126GEN_STUX(width, op | 0x01); \
1127GEN_STX(width, 0x17, op | 0x00)
79aceca5
FB		 1128
1129/* stb stbu stbux stbx */
9a64fbe4 1130GEN_STS(b, 0x06);
79aceca5 1131/* sth sthu sthux sthx */
9a64fbe4 1132GEN_STS(h, 0x0C);
79aceca5 1133/* stw stwu stwux stwx */
9a64fbe4 1134GEN_STS(w, 0x04);
79aceca5
FB		 1135
1136/*** Integer load and store with byte reverse ***/
1137/* lhbrx */
9a64fbe4
FB		 1138OP_LD_TABLE(hbr);
1139GEN_LDX(hbr, 0x16, 0x18);
79aceca5 1140/* lwbrx */
9a64fbe4
FB		 1141OP_LD_TABLE(wbr);
1142GEN_LDX(wbr, 0x16, 0x10);
79aceca5 1143/* sthbrx */
9a64fbe4
FB		 1144OP_ST_TABLE(hbr);
1145GEN_STX(hbr, 0x16, 0x1C);
79aceca5 1146/* stwbrx */
9a64fbe4
FB		 1147OP_ST_TABLE(wbr);
1148GEN_STX(wbr, 0x16, 0x14);
79aceca5
FB		 1149
1150/*** Integer load and store multiple ***/
9a64fbe4
FB		 1151#if defined(CONFIG_USER_ONLY)
1152#define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1153#else
1154#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1155static GenOpFunc1 *gen_op_lmw[] = {
1156 &gen_op_lmw_user,
1157 &gen_op_lmw_kernel,
1158};
1159static GenOpFunc1 *gen_op_stmw[] = {
1160 &gen_op_stmw_user,
1161 &gen_op_stmw_kernel,
1162};
1163#endif
1164
79aceca5
FB		 1165/* lmw */
1166GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1167{
9a64fbe4
FB		 1168 int simm = SIMM(ctx->opcode);
1169
79aceca5 1170 if (rA(ctx->opcode) == 0) {
9a64fbe4 1171 gen_op_set_T0(simm);
79aceca5
FB		 1172 } else {
1173 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1174 if (simm != 0)
1175 gen_op_addi(simm);
79aceca5 1176 }
9a64fbe4 1177 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 1178}
1179
1180/* stmw */
1181GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1182{
9a64fbe4
FB		 1183 int simm = SIMM(ctx->opcode);
1184
79aceca5 1185 if (rA(ctx->opcode) == 0) {
9a64fbe4 1186 gen_op_set_T0(simm);
79aceca5
FB		 1187 } else {
1188 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1189 if (simm != 0)
1190 gen_op_addi(simm);
79aceca5 1191 }
9a64fbe4 1192 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 1193}
1194
1195/*** Integer load and store strings ***/
9a64fbe4
FB		 1196#if defined(CONFIG_USER_ONLY)
1197#define op_ldsts(name, start) gen_op_##name##_raw(start)
1198#define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1199#else
1200#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1201#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1202static GenOpFunc1 *gen_op_lswi[] = {
1203 &gen_op_lswi_user,
1204 &gen_op_lswi_kernel,
1205};
1206static GenOpFunc3 *gen_op_lswx[] = {
1207 &gen_op_lswx_user,
1208 &gen_op_lswx_kernel,
1209};
1210static GenOpFunc1 *gen_op_stsw[] = {
1211 &gen_op_stsw_user,
1212 &gen_op_stsw_kernel,
1213};
1214#endif
1215
79aceca5 1216/* lswi */
9a64fbe4
FB		 1217/* PPC32 specification says we must generate an exception if
1218 * rA is in the range of registers to be loaded.
1219 * In an other hand, IBM says this is valid, but rA won't be loaded.
1220 * For now, I'll follow the spec...
1221 */
79aceca5
FB		 1222GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1223{
1224 int nb = NB(ctx->opcode);
1225 int start = rD(ctx->opcode);
9a64fbe4 1226 int ra = rA(ctx->opcode);
79aceca5
FB		 1227 int nr;
1228
1229 if (nb == 0)
1230 nb = 32;
1231 nr = nb / 4;
9a64fbe4
FB		 1232 if (((start + nr) > 32 && start <= ra && (start + nr - 32) >= ra) ||
1233 ((start + nr) <= 32 && start <= ra && (start + nr) >= ra)) {
1234 RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
79aceca5 1235 }
9a64fbe4 1236 if (ra == 0) {
79aceca5
FB		 1237 gen_op_set_T0(0);
1238 } else {
9a64fbe4 1239 gen_op_load_gpr_T0(ra);
79aceca5 1240 }
9a64fbe4
FB		 1241 gen_op_set_T1(nb);
1242 op_ldsts(lswi, start);
79aceca5
FB		 1243}
1244
1245/* lswx */
1246GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1247{
9a64fbe4
FB		 1248 int ra = rA(ctx->opcode);
1249 int rb = rB(ctx->opcode);
1250
1251 if (ra == 0) {
1252 gen_op_load_gpr_T0(rb);
1253 ra = rb;
79aceca5 1254 } else {
9a64fbe4
FB		 1255 gen_op_load_gpr_T0(ra);
1256 gen_op_load_gpr_T1(rb);
1257 gen_op_add();
79aceca5 1258 }
9a64fbe4
FB		 1259 gen_op_load_xer_bc();
1260 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 1261}
1262
1263/* stswi */
1264GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1265{
79aceca5
FB		 1266 if (rA(ctx->opcode) == 0) {
1267 gen_op_set_T0(0);
1268 } else {
1269 gen_op_load_gpr_T0(rA(ctx->opcode));
1270 }
9a64fbe4
FB		 1271 gen_op_set_T1(NB(ctx->opcode));
1272 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1273}
1274
1275/* stswx */
1276GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1277{
9a64fbe4
FB		 1278 int ra = rA(ctx->opcode);
1279
1280 if (ra == 0) {
1281 gen_op_load_gpr_T0(rB(ctx->opcode));
1282 ra = rB(ctx->opcode);
79aceca5 1283 } else {
9a64fbe4
FB		 1284 gen_op_load_gpr_T0(ra);
1285 gen_op_load_gpr_T1(rB(ctx->opcode));
1286 gen_op_add();
79aceca5 1287 }
9a64fbe4
FB		 1288 gen_op_load_xer_bc();
1289 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1290}
1291
1292/*** Memory synchronisation ***/
1293/* eieio */
1294GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1295{
79aceca5
FB		 1296}
1297
1298/* isync */
1299GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1300{
79aceca5
FB		 1301}
1302
1303/* lwarx */
9a64fbe4
FB		 1304#if defined(CONFIG_USER_ONLY)
1305#define op_stwcx() gen_op_stwcx_raw()
1306#else
1307#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1308static GenOpFunc *gen_op_stwcx[] = {
1309 &gen_op_stwcx_user,
1310 &gen_op_stwcx_kernel,
1311};
1312#endif
1313
1314GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
79aceca5 1315{
79aceca5
FB		 1316 if (rA(ctx->opcode) == 0) {
1317 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1318 } else {
1319 gen_op_load_gpr_T0(rA(ctx->opcode));
1320 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1321 gen_op_add();
79aceca5 1322 }
9a64fbe4 1323 op_ldst(lwz);
79aceca5 1324 gen_op_store_T1_gpr(rD(ctx->opcode));
9a64fbe4 1325 gen_op_set_reservation();
79aceca5
FB		 1326}
1327
1328/* stwcx. */
9a64fbe4 1329GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 1330{
79aceca5
FB		 1331 if (rA(ctx->opcode) == 0) {
1332 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1333 } else {
1334 gen_op_load_gpr_T0(rA(ctx->opcode));
1335 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1336 gen_op_add();
79aceca5 1337 }
9a64fbe4
FB		 1338 gen_op_load_gpr_T1(rS(ctx->opcode));
1339 op_stwcx();
79aceca5
FB		 1340}
1341
1342/* sync */
1343GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1344{
79aceca5
FB		 1345}
1346
1347/*** Floating-point load ***/
9a64fbe4
FB		 1348#define GEN_LDF(width, opc) \
1349GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1350{ \
1351 uint32_t simm = SIMM(ctx->opcode); \
1352 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1353 gen_op_set_T0(simm); \
79aceca5
FB		 1354 } else { \
1355 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1356 if (simm != 0) \
1357 gen_op_addi(simm); \
79aceca5 1358 } \
9a64fbe4
FB		 1359 op_ldst(l##width); \
1360 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1361}
1362
9a64fbe4
FB		 1363#define GEN_LDUF(width, opc) \
1364GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1365{ \
9a64fbe4 1366 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1367 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1368 rA(ctx->opcode) == rD(ctx->opcode)) { \
1369 RET_INVAL(); \
1370 } \
79aceca5 1371 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1372 if (simm != 0) \
1373 gen_op_addi(simm); \
1374 op_ldst(l##width); \
1375 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1376 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1377}
1378
9a64fbe4
FB		 1379#define GEN_LDUXF(width, opc) \
1380GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1381{ \
1382 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1383 rA(ctx->opcode) == rD(ctx->opcode)) { \
1384 RET_INVAL(); \
1385 } \
79aceca5
FB		 1386 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1387 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1388 gen_op_add(); \
1389 op_ldst(l##width); \
1390 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1391 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1392}
1393
9a64fbe4
FB		 1394#define GEN_LDXF(width, opc2, opc3) \
1395GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1396{ \
1397 if (rA(ctx->opcode) == 0) { \
1398 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1399 } else { \
1400 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1401 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1402 gen_op_add(); \
79aceca5 1403 } \
9a64fbe4
FB		 1404 op_ldst(l##width); \
1405 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1406}
1407
9a64fbe4
FB		 1408#define GEN_LDFS(width, op) \
1409OP_LD_TABLE(width); \
1410GEN_LDF(width, op | 0x20); \
1411GEN_LDUF(width, op | 0x21); \
1412GEN_LDUXF(width, op | 0x01); \
1413GEN_LDXF(width, 0x17, op | 0x00)
79aceca5
FB		 1414
1415/* lfd lfdu lfdux lfdx */
9a64fbe4 1416GEN_LDFS(fd, 0x12);
79aceca5 1417/* lfs lfsu lfsux lfsx */
9a64fbe4 1418GEN_LDFS(fs, 0x10);
79aceca5
FB		 1419
1420/*** Floating-point store ***/
1421#define GEN_STF(width, opc) \
9a64fbe4 1422GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1423{ \
1424 uint32_t simm = SIMM(ctx->opcode); \
1425 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1426 gen_op_set_T0(simm); \
79aceca5
FB		 1427 } else { \
1428 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1429 if (simm != 0) \
1430 gen_op_addi(simm); \
79aceca5 1431 } \
9a64fbe4
FB		 1432 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1433 op_ldst(st##width); \
79aceca5
FB		 1434}
1435
9a64fbe4
FB		 1436#define GEN_STUF(width, opc) \
1437GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1438{ \
9a64fbe4
FB		 1439 uint32_t simm = SIMM(ctx->opcode); \
1440 if (rA(ctx->opcode) == 0) { \
1441 RET_INVAL(); \
1442 } \
79aceca5 1443 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1444 if (simm != 0) \
1445 gen_op_addi(simm); \
1446 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1447 op_ldst(st##width); \
79aceca5 1448 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1449}
1450
9a64fbe4
FB		 1451#define GEN_STUXF(width, opc) \
1452GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5 1453{ \
9a64fbe4
FB		 1454 if (rA(ctx->opcode) == 0) { \
1455 RET_INVAL(); \
1456 } \
79aceca5
FB		 1457 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1458 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1459 gen_op_add(); \
1460 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1461 op_ldst(st##width); \
79aceca5 1462 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1463}
1464
9a64fbe4
FB		 1465#define GEN_STXF(width, opc2, opc3) \
1466GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1467{ \
1468 if (rA(ctx->opcode) == 0) { \
1469 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1470 } else { \
1471 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1472 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1473 gen_op_add(); \
79aceca5 1474 } \
9a64fbe4
FB		 1475 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1476 op_ldst(st##width); \
79aceca5
FB		 1477}
1478
9a64fbe4
FB		 1479#define GEN_STFS(width, op) \
1480OP_ST_TABLE(width); \
1481GEN_STF(width, op | 0x20); \
1482GEN_STUF(width, op | 0x21); \
1483GEN_STUXF(width, op | 0x01); \
1484GEN_STXF(width, 0x17, op | 0x00)
79aceca5
FB		 1485
1486/* stfd stfdu stfdux stfdx */
9a64fbe4 1487GEN_STFS(fd, 0x16);
79aceca5 1488/* stfs stfsu stfsux stfsx */
9a64fbe4 1489GEN_STFS(fs, 0x14);
79aceca5
FB		 1490
1491/* Optional: */
1492/* stfiwx */
1493GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1494{
9a64fbe4 1495 RET_INVAL();
79aceca5
FB		 1496}
1497
1498/*** Branch ***/
1499#define GEN_BCOND(name, opc1, opc2, opc3, prologue, \
9a64fbe4 1500 bl_ctr, b_ctr, bl_ctrz, b_ctrz, b, bl, \
79aceca5
FB		 1501 bl_ctr_true, b_ctr_true, bl_ctrz_true, b_ctrz_true, bl_true, b_true, \
1502 bl_ctr_false, b_ctr_false, bl_ctrz_false, b_ctrz_false, bl_false, b_false) \
1503GEN_HANDLER(name, opc1, opc2, opc3, 0x00000000, PPC_FLOW) \
1504{ \
1505 __attribute__ ((unused)) uint32_t target; \
1506 uint32_t bo = BO(ctx->opcode); \
1507 uint32_t bi = BI(ctx->opcode); \
1508 uint32_t mask; \
9a64fbe4
FB		 1509 gen_op_update_tb(ctx->tb_offset); \
1510 gen_op_update_decr(ctx->decr_offset); \
1511 gen_op_process_exceptions((uint32_t)ctx->nip - 4); \
79aceca5 1512 prologue; \
9a64fbe4 1513/* gen_op_set_T1((uint32_t)ctx->tb);*/ \
79aceca5
FB		 1514 if ((bo & 0x4) == 0) \
1515 gen_op_dec_ctr(); \
1516 if (bo & 0x10) { \
1517 /* No CR condition */ \
1518 switch (bo & 0x6) { \
1519 case 0: \
1520 if (LK(ctx->opcode)) { \
1521 bl_ctr; \
1522 } else { \
1523 b_ctr; \
1524 } \
1525 break; \
1526 case 2: \
1527 if (LK(ctx->opcode)) { \
1528 bl_ctrz; \
1529 } else { \
1530 b_ctrz; \
1531 } \
1532 break; \
1533 case 4: \
1534 case 6: \
9a64fbe4
FB		 1535 if (LK(ctx->opcode)) { \
1536 bl; \
1537 } else { \
79aceca5 1538 b; \
9a64fbe4 1539 } \
79aceca5
FB		 1540 break; \
1541 default: \
1542 printf("ERROR: %s: unhandled ba case (%d)\n", __func__, bo); \
9a64fbe4 1543 RET_INVAL(); \
79aceca5
FB		 1544 break; \
1545 } \
1546 } else { \
1547 mask = 1 << (3 - (bi & 0x03)); \
1548 gen_op_load_crf_T0(bi >> 2); \
1549 if (bo & 0x8) { \
1550 switch (bo & 0x6) { \
1551 case 0: \
1552 if (LK(ctx->opcode)) { \
1553 bl_ctr_true; \
1554 } else { \
1555 b_ctr_true; \
1556 } \
1557 break; \
1558 case 2: \
1559 if (LK(ctx->opcode)) { \
1560 bl_ctrz_true; \
1561 } else { \
1562 b_ctrz_true; \
1563 } \
1564 break; \
1565 case 4: \
1566 case 6: \
1567 if (LK(ctx->opcode)) { \
1568 bl_true; \
1569 } else { \
1570 b_true; \
1571 } \
1572 break; \
1573 default: \
1574 printf("ERROR: %s: unhandled b case (%d)\n", __func__, bo); \
9a64fbe4 1575 RET_INVAL(); \
79aceca5
FB		 1576 break; \
1577 } \
1578 } else { \
1579 switch (bo & 0x6) { \
1580 case 0: \
1581 if (LK(ctx->opcode)) { \
1582 bl_ctr_false; \
1583 } else { \
1584 b_ctr_false; \
1585 } \
1586 break; \
1587 case 2: \
1588 if (LK(ctx->opcode)) { \
1589 bl_ctrz_false; \
1590 } else { \
1591 b_ctrz_false; \
1592 } \
1593 break; \
1594 case 4: \
1595 case 6: \
1596 if (LK(ctx->opcode)) { \
1597 bl_false; \
1598 } else { \
1599 b_false; \
1600 } \
1601 break; \
1602 default: \
1603 printf("ERROR: %s: unhandled bn case (%d)\n", __func__, bo); \
9a64fbe4 1604 RET_INVAL(); \
79aceca5
FB		 1605 break; \
1606 } \
1607 } \
1608 } \
9a64fbe4 1609 ctx->exception = EXCP_BRANCH; \
79aceca5
FB		 1610}
1611
1612/* b ba bl bla */
1613GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1614{
1615 uint32_t li = s_ext24(LI(ctx->opcode)), target;
1616
9a64fbe4
FB		 1617 gen_op_update_tb(ctx->tb_offset);
1618 gen_op_update_decr(ctx->decr_offset);
1619 gen_op_process_exceptions((uint32_t)ctx->nip - 4);
79aceca5
FB		 1620 if (AA(ctx->opcode) == 0)
1621 target = (uint32_t)ctx->nip + li - 4;
1622 else
9a64fbe4
FB		 1623 target = li;
1624// gen_op_set_T1((uint32_t)ctx->tb);
1625 if (LK(ctx->opcode)) {
1626 gen_op_bl(target, (uint32_t)ctx->nip);
1627 } else {
79aceca5 1628 gen_op_b(target);
9a64fbe4
FB		 1629 }
1630 ctx->exception = EXCP_BRANCH;
79aceca5
FB		 1631}
1632
1633/* bc bca bcl bcla */
1634GEN_BCOND(bc, 0x10, 0xFF, 0xFF,
1635 do {
1636 uint32_t li = s_ext16(BD(ctx->opcode));
1637 if (AA(ctx->opcode) == 0) {
1638 target = (uint32_t)ctx->nip + li - 4;
1639 } else {
1640 target = li;
1641 }
1642 } while (0),
1643 gen_op_bl_ctr((uint32_t)ctx->nip, target),
1644 gen_op_b_ctr((uint32_t)ctx->nip, target),
1645 gen_op_bl_ctrz((uint32_t)ctx->nip, target),
1646 gen_op_b_ctrz((uint32_t)ctx->nip, target),
1647 gen_op_b(target),
9a64fbe4 1648 gen_op_bl(target, (uint32_t)ctx->nip),
79aceca5
FB		 1649 gen_op_bl_ctr_true((uint32_t)ctx->nip, target, mask),
1650 gen_op_b_ctr_true((uint32_t)ctx->nip, target, mask),
1651 gen_op_bl_ctrz_true((uint32_t)ctx->nip, target, mask),
1652 gen_op_b_ctrz_true((uint32_t)ctx->nip, target, mask),
1653 gen_op_bl_true((uint32_t)ctx->nip, target, mask),
1654 gen_op_b_true((uint32_t)ctx->nip, target, mask),
1655 gen_op_bl_ctr_false((uint32_t)ctx->nip, target, mask),
1656 gen_op_b_ctr_false((uint32_t)ctx->nip, target, mask),
1657 gen_op_bl_ctrz_false((uint32_t)ctx->nip, target, mask),
1658 gen_op_b_ctrz_false((uint32_t)ctx->nip, target, mask),
1659 gen_op_bl_false((uint32_t)ctx->nip, target, mask),
1660 gen_op_b_false((uint32_t)ctx->nip, target, mask));
1661
1662/* bcctr bcctrl */
1663GEN_BCOND(bcctr, 0x13, 0x10, 0x10, do { } while (0),
1664 gen_op_bctrl_ctr((uint32_t)ctx->nip),
1665 gen_op_bctr_ctr((uint32_t)ctx->nip),
1666 gen_op_bctrl_ctrz((uint32_t)ctx->nip),
1667 gen_op_bctr_ctrz((uint32_t)ctx->nip),
1668 gen_op_bctr(),
9a64fbe4 1669 gen_op_bctrl((uint32_t)ctx->nip),
79aceca5
FB		 1670 gen_op_bctrl_ctr_true((uint32_t)ctx->nip, mask),
1671 gen_op_bctr_ctr_true((uint32_t)ctx->nip, mask),
1672 gen_op_bctrl_ctrz_true((uint32_t)ctx->nip, mask),
1673 gen_op_bctr_ctrz_true((uint32_t)ctx->nip, mask),
1674 gen_op_bctrl_true((uint32_t)ctx->nip, mask),
1675 gen_op_bctr_true((uint32_t)ctx->nip, mask),
1676 gen_op_bctrl_ctr_false((uint32_t)ctx->nip, mask),
1677 gen_op_bctr_ctr_false((uint32_t)ctx->nip, mask),
1678 gen_op_bctrl_ctrz_false((uint32_t)ctx->nip, mask),
1679 gen_op_bctr_ctrz_false((uint32_t)ctx->nip, mask),
1680 gen_op_bctrl_false((uint32_t)ctx->nip, mask),
1681 gen_op_bctr_false((uint32_t)ctx->nip, mask))
1682
1683/* bclr bclrl */
1684GEN_BCOND(bclr, 0x13, 0x10, 0x00, do { } while (0),
1685 gen_op_blrl_ctr((uint32_t)ctx->nip),
1686 gen_op_blr_ctr((uint32_t)ctx->nip),
1687 gen_op_blrl_ctrz((uint32_t)ctx->nip),
1688 gen_op_blr_ctrz((uint32_t)ctx->nip),
1689 gen_op_blr(),
9a64fbe4 1690 gen_op_blrl((uint32_t)ctx->nip),
79aceca5
FB		 1691 gen_op_blrl_ctr_true((uint32_t)ctx->nip, mask),
1692 gen_op_blr_ctr_true((uint32_t)ctx->nip, mask),
1693 gen_op_blrl_ctrz_true((uint32_t)ctx->nip, mask),
1694 gen_op_blr_ctrz_true((uint32_t)ctx->nip, mask),
1695 gen_op_blrl_true((uint32_t)ctx->nip, mask),
1696 gen_op_blr_true((uint32_t)ctx->nip, mask),
1697 gen_op_blrl_ctr_false((uint32_t)ctx->nip, mask),
1698 gen_op_blr_ctr_false((uint32_t)ctx->nip, mask),
1699 gen_op_blrl_ctrz_false((uint32_t)ctx->nip, mask),
1700 gen_op_blr_ctrz_false((uint32_t)ctx->nip, mask),
1701 gen_op_blrl_false((uint32_t)ctx->nip, mask),
1702 gen_op_blr_false((uint32_t)ctx->nip, mask))
1703
1704/*** Condition register logical ***/
1705#define GEN_CRLOGIC(op, opc) \
1706GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1707{ \
1708 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1709 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1710 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1711 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1712 gen_op_##op(); \
1713 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1714 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1715 3 - (crbD(ctx->opcode) & 0x03)); \
1716 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 1717}
1718
1719/* crand */
1720GEN_CRLOGIC(and, 0x08)
1721/* crandc */
1722GEN_CRLOGIC(andc, 0x04)
1723/* creqv */
1724GEN_CRLOGIC(eqv, 0x09)
1725/* crnand */
1726GEN_CRLOGIC(nand, 0x07)
1727/* crnor */
1728GEN_CRLOGIC(nor, 0x01)
1729/* cror */
1730GEN_CRLOGIC(or, 0x0E)
1731/* crorc */
1732GEN_CRLOGIC(orc, 0x0D)
1733/* crxor */
1734GEN_CRLOGIC(xor, 0x06)
1735/* mcrf */
1736GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1737{
1738 gen_op_load_crf_T0(crfS(ctx->opcode));
1739 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1740}
1741
1742/*** System linkage ***/
1743/* rfi (supervisor only) */
1744GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1745{
9a64fbe4
FB		 1746#if defined(CONFIG_USER_ONLY)
1747 RET_PRIVOPC();
1748#else
1749 /* Restore CPU state */
1750 if (!ctx->supervisor) {
1751 RET_PRIVOPC();
1752 }
1753 gen_op_rfi();
1754 ctx->exception = EXCP_RFI;
1755#endif
79aceca5
FB		 1756}
1757
1758/* sc */
1759GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1760{
9a64fbe4
FB		 1761#if defined(CONFIG_USER_ONLY)
1762 gen_op_queue_exception(EXCP_SYSCALL_USER);
1763#else
1764 gen_op_queue_exception(EXCP_SYSCALL);
1765#endif
1766 ctx->exception = EXCP_SYSCALL;
79aceca5
FB		 1767}
1768
1769/*** Trap ***/
1770/* tw */
1771GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1772{
9a64fbe4
FB		 1773 gen_op_load_gpr_T0(rA(ctx->opcode));
1774 gen_op_load_gpr_T1(rB(ctx->opcode));
1775 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 1776}
1777
1778/* twi */
1779GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1780{
9a64fbe4
FB		 1781 gen_op_load_gpr_T0(rA(ctx->opcode));
1782#if 0
1783 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1784 SIMM(ctx->opcode), TO(ctx->opcode));
1785#endif
1786 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
79aceca5
FB		 1787}
1788
1789/*** Processor control ***/
1790static inline int check_spr_access (int spr, int rw, int supervisor)
1791{
1792 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1793
9a64fbe4
FB		 1794#if 0
1795 if (spr != LR && spr != CTR) {
1796 if (loglevel > 0) {
1797 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1798 SPR_ENCODE(spr), supervisor, rw, rights,
1799 (rights >> ((2 * supervisor) + rw)) & 1);
1800 } else {
1801 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1802 SPR_ENCODE(spr), supervisor, rw, rights,
1803 (rights >> ((2 * supervisor) + rw)) & 1);
1804 }
1805 }
1806#endif
1807 if (rights == 0)
1808 return -1;
79aceca5
FB		 1809 rights = rights >> (2 * supervisor);
1810 rights = rights >> rw;
1811
1812 return rights & 1;
1813}
1814
1815/* mcrxr */
1816GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1817{
1818 gen_op_load_xer_cr();
1819 gen_op_store_T0_crf(crfD(ctx->opcode));
1820 gen_op_clear_xer_cr();
79aceca5
FB		 1821}
1822
1823/* mfcr */
1824GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1825{
1826 gen_op_load_cr();
1827 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1828}
1829
1830/* mfmsr */
1831GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1832{
9a64fbe4
FB		 1833#if defined(CONFIG_USER_ONLY)
1834 RET_PRIVREG();
1835#else
1836 if (!ctx->supervisor) {
1837 RET_PRIVREG();
1838 }
79aceca5
FB		 1839 gen_op_load_msr();
1840 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 1841#endif
79aceca5
FB		 1842}
1843
1844/* mfspr */
1845GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1846{
1847 uint32_t sprn = SPR(ctx->opcode);
1848
9a64fbe4
FB		 1849#if defined(CONFIG_USER_ONLY)
1850 switch (check_spr_access(sprn, 0, 0))
1851#else
1852 switch (check_spr_access(sprn, 0, ctx->supervisor))
1853#endif
1854 {
1855 case -1:
1856 RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1857 break;
1858 case 0:
1859 RET_PRIVREG();
1860 break;
1861 default:
1862 break;
79aceca5 1863 }
9a64fbe4
FB		 1864 switch (sprn) {
1865 case XER:
79aceca5
FB		 1866 gen_op_load_xer();
1867 break;
9a64fbe4
FB		 1868 case LR:
1869 gen_op_load_lr();
1870 break;
1871 case CTR:
1872 gen_op_load_ctr();
1873 break;
1874 case IBAT0U:
1875 gen_op_load_ibat(0, 0);
1876 break;
1877 case IBAT1U:
1878 gen_op_load_ibat(0, 1);
1879 break;
1880 case IBAT2U:
1881 gen_op_load_ibat(0, 2);
1882 break;
1883 case IBAT3U:
1884 gen_op_load_ibat(0, 3);
1885 break;
1886 case IBAT4U:
1887 gen_op_load_ibat(0, 4);
1888 break;
1889 case IBAT5U:
1890 gen_op_load_ibat(0, 5);
1891 break;
1892 case IBAT6U:
1893 gen_op_load_ibat(0, 6);
1894 break;
1895 case IBAT7U:
1896 gen_op_load_ibat(0, 7);
1897 break;
1898 case IBAT0L:
1899 gen_op_load_ibat(1, 0);
1900 break;
1901 case IBAT1L:
1902 gen_op_load_ibat(1, 1);
1903 break;
1904 case IBAT2L:
1905 gen_op_load_ibat(1, 2);
1906 break;
1907 case IBAT3L:
1908 gen_op_load_ibat(1, 3);
1909 break;
1910 case IBAT4L:
1911 gen_op_load_ibat(1, 4);
1912 break;
1913 case IBAT5L:
1914 gen_op_load_ibat(1, 5);
1915 break;
1916 case IBAT6L:
1917 gen_op_load_ibat(1, 6);
1918 break;
1919 case IBAT7L:
1920 gen_op_load_ibat(1, 7);
1921 break;
1922 case DBAT0U:
1923 gen_op_load_dbat(0, 0);
1924 break;
1925 case DBAT1U:
1926 gen_op_load_dbat(0, 1);
1927 break;
1928 case DBAT2U:
1929 gen_op_load_dbat(0, 2);
1930 break;
1931 case DBAT3U:
1932 gen_op_load_dbat(0, 3);
1933 break;
1934 case DBAT4U:
1935 gen_op_load_dbat(0, 4);
1936 break;
1937 case DBAT5U:
1938 gen_op_load_dbat(0, 5);
1939 break;
1940 case DBAT6U:
1941 gen_op_load_dbat(0, 6);
1942 break;
1943 case DBAT7U:
1944 gen_op_load_dbat(0, 7);
1945 break;
1946 case DBAT0L:
1947 gen_op_load_dbat(1, 0);
1948 break;
1949 case DBAT1L:
1950 gen_op_load_dbat(1, 1);
1951 break;
1952 case DBAT2L:
1953 gen_op_load_dbat(1, 2);
1954 break;
1955 case DBAT3L:
1956 gen_op_load_dbat(1, 3);
1957 break;
1958 case DBAT4L:
1959 gen_op_load_dbat(1, 4);
1960 break;
1961 case DBAT5L:
1962 gen_op_load_dbat(1, 5);
1963 break;
1964 case DBAT6L:
1965 gen_op_load_dbat(1, 6);
1966 break;
1967 case DBAT7L:
1968 gen_op_load_dbat(1, 7);
1969 break;
1970 case SDR1:
1971 gen_op_load_sdr1();
1972 break;
1973 case V_TBL:
79aceca5
FB		 1974 gen_op_update_tb(ctx->tb_offset);
1975 ctx->tb_offset = 0;
9a64fbe4 1976 /* TBL is still in T0 */
79aceca5 1977 break;
9a64fbe4 1978 case V_TBU:
79aceca5
FB		 1979 gen_op_update_tb(ctx->tb_offset);
1980 ctx->tb_offset = 0;
9a64fbe4
FB		 1981 gen_op_load_tb(1);
1982 break;
1983 case DECR:
1984 gen_op_update_decr(ctx->decr_offset);
1985 ctx->decr_offset = 0;
1986 /* decr is still in T0 */
79aceca5
FB		 1987 break;
1988 default:
1989 gen_op_load_spr(sprn);
1990 break;
1991 }
9a64fbe4 1992 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1993}
1994
1995/* mftb */
1996GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
1997{
1998 uint32_t sprn = SPR(ctx->opcode);
1999
79aceca5 2000 /* We need to update the time base before reading it */
9a64fbe4
FB		 2001 switch (sprn) {
2002 case V_TBL:
79aceca5 2003 gen_op_update_tb(ctx->tb_offset);
9a64fbe4 2004 /* TBL is still in T0 */
79aceca5 2005 break;
9a64fbe4 2006 case V_TBU:
79aceca5 2007 gen_op_update_tb(ctx->tb_offset);
9a64fbe4 2008 gen_op_load_tb(1);
79aceca5
FB		 2009 break;
2010 default:
9a64fbe4 2011 RET_INVAL();
79aceca5
FB		 2012 break;
2013 }
9a64fbe4
FB		 2014 ctx->tb_offset = 0;
2015 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2016}
2017
2018/* mtcrf */
2019GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
2020{
2021 gen_op_load_gpr_T0(rS(ctx->opcode));
2022 gen_op_store_cr(CRM(ctx->opcode));
79aceca5
FB		 2023}
2024
2025/* mtmsr */
2026GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2027{
9a64fbe4
FB		 2028#if defined(CONFIG_USER_ONLY)
2029 RET_PRIVREG();
2030#else
2031 if (!ctx->supervisor) {
2032 RET_PRIVREG();
2033 }
79aceca5
FB		 2034 gen_op_load_gpr_T0(rS(ctx->opcode));
2035 gen_op_store_msr();
2036 /* Must stop the translation as machine state (may have) changed */
9a64fbe4
FB		 2037 ctx->exception = EXCP_MTMSR;
2038#endif
79aceca5
FB		 2039}
2040
2041/* mtspr */
2042GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2043{
2044 uint32_t sprn = SPR(ctx->opcode);
2045
9a64fbe4
FB		 2046#if 0
2047 if (loglevel > 0) {
2048 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
2049 rS(ctx->opcode), sprn);
2050 }
2051#endif
2052#if defined(CONFIG_USER_ONLY)
2053 switch (check_spr_access(sprn, 1, 0))
2054#else
2055 switch (check_spr_access(sprn, 1, ctx->supervisor))
2056#endif
2057 {
2058 case -1:
2059 RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2060 break;
2061 case 0:
2062 RET_PRIVREG();
2063 break;
2064 default:
2065 break;
2066 }
79aceca5 2067 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4
FB		 2068 switch (sprn) {
2069 case XER:
79aceca5 2070 gen_op_store_xer();
9a64fbe4
FB		 2071 break;
2072 case LR:
2073 gen_op_andi_(~0x03);
2074 gen_op_store_lr();
2075 break;
2076 case CTR:
2077 gen_op_store_ctr();
2078 break;
2079 case IBAT0U:
2080 gen_op_store_ibat(0, 0);
2081 gen_op_tlbia();
2082 break;
2083 case IBAT1U:
2084 gen_op_store_ibat(0, 1);
2085 gen_op_tlbia();
2086 break;
2087 case IBAT2U:
2088 gen_op_store_ibat(0, 2);
2089 gen_op_tlbia();
2090 break;
2091 case IBAT3U:
2092 gen_op_store_ibat(0, 3);
2093 gen_op_tlbia();
2094 break;
2095 case IBAT4U:
2096 gen_op_store_ibat(0, 4);
2097 gen_op_tlbia();
2098 break;
2099 case IBAT5U:
2100 gen_op_store_ibat(0, 5);
2101 gen_op_tlbia();
2102 break;
2103 case IBAT6U:
2104 gen_op_store_ibat(0, 6);
2105 gen_op_tlbia();
2106 break;
2107 case IBAT7U:
2108 gen_op_store_ibat(0, 7);
2109 gen_op_tlbia();
2110 break;
2111 case IBAT0L:
2112 gen_op_store_ibat(1, 0);
2113 gen_op_tlbia();
2114 break;
2115 case IBAT1L:
2116 gen_op_store_ibat(1, 1);
2117 gen_op_tlbia();
2118 break;
2119 case IBAT2L:
2120 gen_op_store_ibat(1, 2);
2121 gen_op_tlbia();
2122 break;
2123 case IBAT3L:
2124 gen_op_store_ibat(1, 3);
2125 gen_op_tlbia();
2126 break;
2127 case IBAT4L:
2128 gen_op_store_ibat(1, 4);
2129 gen_op_tlbia();
2130 break;
2131 case IBAT5L:
2132 gen_op_store_ibat(1, 5);
2133 gen_op_tlbia();
2134 break;
2135 case IBAT6L:
2136 gen_op_store_ibat(1, 6);
2137 gen_op_tlbia();
2138 break;
2139 case IBAT7L:
2140 gen_op_store_ibat(1, 7);
2141 gen_op_tlbia();
2142 break;
2143 case DBAT0U:
2144 gen_op_store_dbat(0, 0);
2145 gen_op_tlbia();
2146 break;
2147 case DBAT1U:
2148 gen_op_store_dbat(0, 1);
2149 gen_op_tlbia();
2150 break;
2151 case DBAT2U:
2152 gen_op_store_dbat(0, 2);
2153 gen_op_tlbia();
2154 break;
2155 case DBAT3U:
2156 gen_op_store_dbat(0, 3);
2157 gen_op_tlbia();
2158 break;
2159 case DBAT4U:
2160 gen_op_store_dbat(0, 4);
2161 gen_op_tlbia();
2162 break;
2163 case DBAT5U:
2164 gen_op_store_dbat(0, 5);
2165 gen_op_tlbia();
2166 break;
2167 case DBAT6U:
2168 gen_op_store_dbat(0, 6);
2169 gen_op_tlbia();
2170 break;
2171 case DBAT7U:
2172 gen_op_store_dbat(0, 7);
2173 gen_op_tlbia();
2174 break;
2175 case DBAT0L:
2176 gen_op_store_dbat(1, 0);
2177 gen_op_tlbia();
2178 break;
2179 case DBAT1L:
2180 gen_op_store_dbat(1, 1);
2181 gen_op_tlbia();
2182 break;
2183 case DBAT2L:
2184 gen_op_store_dbat(1, 2);
2185 gen_op_tlbia();
2186 break;
2187 case DBAT3L:
2188 gen_op_store_dbat(1, 3);
2189 gen_op_tlbia();
2190 break;
2191 case DBAT4L:
2192 gen_op_store_dbat(1, 4);
2193 gen_op_tlbia();
2194 break;
2195 case DBAT5L:
2196 gen_op_store_dbat(1, 5);
2197 gen_op_tlbia();
2198 break;
2199 case DBAT6L:
2200 gen_op_store_dbat(1, 6);
2201 gen_op_tlbia();
2202 break;
2203 case DBAT7L:
2204 gen_op_store_dbat(1, 7);
2205 gen_op_tlbia();
2206 break;
2207 case SDR1:
2208 gen_op_store_sdr1();
2209 gen_op_tlbia();
2210 break;
2211 case O_TBL:
2212 gen_op_store_tb(0);
2213 ctx->tb_offset = 0;
2214 break;
2215 case O_TBU:
2216 gen_op_store_tb(1);
2217 ctx->tb_offset = 0;
2218 break;
2219 case DECR:
2220 gen_op_store_decr();
2221 ctx->decr_offset = 0;
2222 break;
2223 default:
79aceca5 2224 gen_op_store_spr(sprn);
9a64fbe4 2225 break;
79aceca5 2226 }
79aceca5
FB		 2227}
2228
2229/*** Cache management ***/
2230/* For now, all those will be implemented as nop:
2231 * this is valid, regarding the PowerPC specs...
9a64fbe4 2232 * We just have to flush tb while invalidating instruction cache lines...
79aceca5
FB		 2233 */
2234/* dcbf */
9a64fbe4 2235GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
79aceca5 2236{
79aceca5
FB		 2237}
2238
2239/* dcbi (Supervisor only) */
9a64fbe4 2240GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 2241{
9a64fbe4
FB		 2242#if !defined(CONFIG_USER_ONLY)
2243 if (!ctx->supervisor)
2244#endif
2245 {
2246 RET_PRIVOPC();
2247 }
79aceca5
FB		 2248}
2249
2250/* dcdst */
9a64fbe4 2251GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 2252{
79aceca5
FB		 2253}
2254
2255/* dcbt */
9a64fbe4 2256GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
79aceca5 2257{
79aceca5
FB		 2258}
2259
2260/* dcbtst */
9a64fbe4 2261GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
79aceca5 2262{
79aceca5
FB		 2263}
2264
2265/* dcbz */
9a64fbe4
FB		 2266#if defined(CONFIG_USER_ONLY)
2267#define op_dcbz() gen_op_dcbz_raw()
2268#else
2269#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2270static GenOpFunc *gen_op_dcbz[] = {
2271 &gen_op_dcbz_user,
2272 &gen_op_dcbz_kernel,
2273};
2274#endif
2275
2276GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
79aceca5 2277{
fb0eaffc
FB		 2278 if (rA(ctx->opcode) == 0) {
2279 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2280 } else {
2281 gen_op_load_gpr_T0(rA(ctx->opcode));
2282 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2283 gen_op_add();
fb0eaffc 2284 }
9a64fbe4 2285 op_dcbz();
79aceca5
FB		 2286}
2287
2288/* icbi */
9a64fbe4 2289GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
79aceca5 2290{
fb0eaffc
FB		 2291 if (rA(ctx->opcode) == 0) {
2292 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2293 } else {
2294 gen_op_load_gpr_T0(rA(ctx->opcode));
2295 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2296 gen_op_add();
fb0eaffc 2297 }
9a64fbe4 2298 gen_op_icbi();
79aceca5
FB		 2299}
2300
2301/* Optional: */
2302/* dcba */
9a64fbe4 2303GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
79aceca5 2304{
79aceca5
FB		 2305}
2306
2307/*** Segment register manipulation ***/
2308/* Supervisor only: */
2309/* mfsr */
2310GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2311{
9a64fbe4
FB		 2312#if defined(CONFIG_USER_ONLY)
2313 RET_PRIVREG();
2314#else
2315 if (!ctx->supervisor) {
2316 RET_PRIVREG();
2317 }
2318 gen_op_load_sr(SR(ctx->opcode));
2319 gen_op_store_T0_gpr(rD(ctx->opcode));
2320#endif
79aceca5
FB		 2321}
2322
2323/* mfsrin */
9a64fbe4 2324GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 2325{
9a64fbe4
FB		 2326#if defined(CONFIG_USER_ONLY)
2327 RET_PRIVREG();
2328#else
2329 if (!ctx->supervisor) {
2330 RET_PRIVREG();
2331 }
2332 gen_op_load_gpr_T1(rB(ctx->opcode));
2333 gen_op_load_srin();
2334 gen_op_store_T0_gpr(rD(ctx->opcode));
2335#endif
79aceca5
FB		 2336}
2337
2338/* mtsr */
2339GEN_HANDLER(mtsr, 0x1F, 0x12, 0x02, 0x0010F801, PPC_SEGMENT)
2340{
9a64fbe4
FB		 2341#if defined(CONFIG_USER_ONLY)
2342 RET_PRIVREG();
2343#else
2344 if (!ctx->supervisor) {
2345 RET_PRIVREG();
2346 }
2347 gen_op_load_gpr_T0(rS(ctx->opcode));
2348 gen_op_store_sr(SR(ctx->opcode));
2349 gen_op_tlbia();
2350#endif
79aceca5
FB		 2351}
2352
2353/* mtsrin */
9a64fbe4 2354GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 2355{
9a64fbe4
FB		 2356#if defined(CONFIG_USER_ONLY)
2357 RET_PRIVREG();
2358#else
2359 if (!ctx->supervisor) {
2360 RET_PRIVREG();
2361 }
2362 gen_op_load_gpr_T0(rS(ctx->opcode));
2363 gen_op_load_gpr_T1(rB(ctx->opcode));
2364 gen_op_store_srin();
2365 gen_op_tlbia();
2366#endif
79aceca5
FB		 2367}
2368
2369/*** Lookaside buffer management ***/
2370/* Optional & supervisor only: */
2371/* tlbia */
9a64fbe4 2372GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
79aceca5 2373{
9a64fbe4
FB		 2374#if defined(CONFIG_USER_ONLY)
2375 RET_PRIVOPC();
2376#else
2377 if (!ctx->supervisor) {
2378 RET_PRIVOPC();
2379 }
2380 gen_op_tlbia();
2381#endif
79aceca5
FB		 2382}
2383
2384/* tlbie */
9a64fbe4 2385GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
79aceca5 2386{
9a64fbe4
FB		 2387#if defined(CONFIG_USER_ONLY)
2388 RET_PRIVOPC();
2389#else
2390 if (!ctx->supervisor) {
2391 RET_PRIVOPC();
2392 }
2393 gen_op_load_gpr_T0(rB(ctx->opcode));
2394 gen_op_tlbie();
2395#endif
79aceca5
FB		 2396}
2397
2398/* tlbsync */
2399GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFFC01, PPC_MEM)
2400{
9a64fbe4
FB		 2401#if defined(CONFIG_USER_ONLY)
2402 RET_PRIVOPC();
2403#else
2404 if (!ctx->supervisor) {
2405 RET_PRIVOPC();
2406 }
2407 /* This has no effect: it should ensure that all previous
2408 * tlbie have completed
2409 */
2410#endif
79aceca5
FB		 2411}
2412
2413/*** External control ***/
2414/* Optional: */
2415/* eciwx */
9a64fbe4
FB		 2416#if defined(CONFIG_USER_ONLY)
2417#define op_eciwx() gen_op_eciwx_raw()
2418#define op_ecowx() gen_op_ecowx_raw()
2419#else
2420#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2421#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2422static GenOpFunc *gen_op_eciwx[] = {
2423 &gen_op_eciwx_user,
2424 &gen_op_eciwx_kernel,
2425};
2426static GenOpFunc *gen_op_ecowx[] = {
2427 &gen_op_ecowx_user,
2428 &gen_op_ecowx_kernel,
2429};
2430#endif
2431
79aceca5
FB		 2432GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2433{
9a64fbe4
FB		 2434 /* Should check EAR[E] & alignment ! */
2435 if (rA(ctx->opcode) == 0) {
2436 gen_op_load_gpr_T0(rB(ctx->opcode));
2437 } else {
2438 gen_op_load_gpr_T0(rA(ctx->opcode));
2439 gen_op_load_gpr_T1(rB(ctx->opcode));
2440 gen_op_add();
2441 }
2442 op_eciwx();
2443 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2444}
2445
2446/* ecowx */
2447GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2448{
9a64fbe4
FB		 2449 /* Should check EAR[E] & alignment ! */
2450 if (rA(ctx->opcode) == 0) {
2451 gen_op_load_gpr_T0(rB(ctx->opcode));
2452 } else {
2453 gen_op_load_gpr_T0(rA(ctx->opcode));
2454 gen_op_load_gpr_T1(rB(ctx->opcode));
2455 gen_op_add();
2456 }
2457 gen_op_load_gpr_T2(rS(ctx->opcode));
2458 op_ecowx();
79aceca5
FB		 2459}
2460
2461/* End opcode list */
2462GEN_OPCODE_MARK(end);
2463
2464/*****************************************************************************/
9a64fbe4 2465#include <stdlib.h>
79aceca5 2466#include <string.h>
9a64fbe4
FB		 2467
2468int fflush (FILE *stream);
79aceca5
FB		 2469
2470/* Main ppc opcodes table:
2471 * at init, all opcodes are invalids
2472 */
2473static opc_handler_t *ppc_opcodes[0x40];
2474
2475/* Opcode types */
2476enum {
2477 PPC_DIRECT = 0, /* Opcode routine */
2478 PPC_INDIRECT = 1, /* Indirect opcode table */
2479};
2480
2481static inline int is_indirect_opcode (void *handler)
2482{
2483 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2484}
2485
2486static inline opc_handler_t **ind_table(void *handler)
2487{
2488 return (opc_handler_t **)((unsigned long)handler & ~3);
2489}
2490
9a64fbe4 2491/* Instruction table creation */
79aceca5
FB		 2492/* Opcodes tables creation */
2493static void fill_new_table (opc_handler_t **table, int len)
2494{
2495 int i;
2496
2497 for (i = 0; i < len; i++)
2498 table[i] = &invalid_handler;
2499}
2500
2501static int create_new_table (opc_handler_t **table, unsigned char idx)
2502{
2503 opc_handler_t **tmp;
2504
2505 tmp = malloc(0x20 * sizeof(opc_handler_t));
2506 if (tmp == NULL)
2507 return -1;
2508 fill_new_table(tmp, 0x20);
2509 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2510
2511 return 0;
2512}
2513
2514static int insert_in_table (opc_handler_t **table, unsigned char idx,
2515 opc_handler_t *handler)
2516{
2517 if (table[idx] != &invalid_handler)
2518 return -1;
2519 table[idx] = handler;
2520
2521 return 0;
2522}
2523
9a64fbe4
FB		 2524static int register_direct_insn (opc_handler_t **ppc_opcodes,
2525 unsigned char idx, opc_handler_t *handler)
79aceca5
FB		 2526{
2527 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9a64fbe4 2528 printf("*** ERROR: opcode %02x already assigned in main "
79aceca5
FB		 2529 "opcode table\n", idx);
2530 return -1;
2531 }
2532
2533 return 0;
2534}
2535
2536static int register_ind_in_table (opc_handler_t **table,
2537 unsigned char idx1, unsigned char idx2,
2538 opc_handler_t *handler)
2539{
2540 if (table[idx1] == &invalid_handler) {
2541 if (create_new_table(table, idx1) < 0) {
9a64fbe4 2542 printf("*** ERROR: unable to create indirect table "
79aceca5
FB		 2543 "idx=%02x\n", idx1);
2544 return -1;
2545 }
2546 } else {
2547 if (!is_indirect_opcode(table[idx1])) {
9a64fbe4 2548 printf("*** ERROR: idx %02x already assigned to a direct "
79aceca5
FB		 2549 "opcode\n", idx1);
2550 return -1;
2551 }
2552 }
2553 if (handler != NULL &&
2554 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9a64fbe4 2555 printf("*** ERROR: opcode %02x already assigned in "
79aceca5
FB		 2556 "opcode table %02x\n", idx2, idx1);
2557 return -1;
2558 }
2559
2560 return 0;
2561}
2562
9a64fbe4
FB		 2563static int register_ind_insn (opc_handler_t **ppc_opcodes,
2564 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2565 opc_handler_t *handler)
2566{
2567 int ret;
2568
2569 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2570
2571 return ret;
2572}
2573
9a64fbe4
FB		 2574static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2575 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2576 unsigned char idx3, opc_handler_t *handler)
2577{
2578 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9a64fbe4 2579 printf("*** ERROR: unable to join indirect table idx "
79aceca5
FB		 2580 "[%02x-%02x]\n", idx1, idx2);
2581 return -1;
2582 }
2583 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2584 handler) < 0) {
9a64fbe4 2585 printf("*** ERROR: unable to insert opcode "
79aceca5
FB		 2586 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2587 return -1;
2588 }
2589
2590 return 0;
2591}
2592
9a64fbe4 2593static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
79aceca5
FB		 2594{
2595 if (insn->opc2 != 0xFF) {
2596 if (insn->opc3 != 0xFF) {
9a64fbe4
FB		 2597 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2598 insn->opc3, &insn->handler) < 0)
79aceca5
FB		 2599 return -1;
2600 } else {
9a64fbe4
FB		 2601 if (register_ind_insn(ppc_opcodes, insn->opc1,
2602 insn->opc2, &insn->handler) < 0)
79aceca5
FB		 2603 return -1;
2604 }
2605 } else {
9a64fbe4 2606 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
79aceca5
FB		 2607 return -1;
2608 }
2609
2610 return 0;
2611}
2612
2613static int test_opcode_table (opc_handler_t **table, int len)
2614{
2615 int i, count, tmp;
2616
2617 for (i = 0, count = 0; i < len; i++) {
2618 /* Consistency fixup */
2619 if (table[i] == NULL)
2620 table[i] = &invalid_handler;
2621 if (table[i] != &invalid_handler) {
2622 if (is_indirect_opcode(table[i])) {
2623 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2624 if (tmp == 0) {
2625 free(table[i]);
2626 table[i] = &invalid_handler;
2627 } else {
2628 count++;
2629 }
2630 } else {
2631 count++;
2632 }
2633 }
2634 }
2635
2636 return count;
2637}
2638
9a64fbe4 2639static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
79aceca5
FB		 2640{
2641 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9a64fbe4 2642 printf("*** WARNING: no opcode defined !\n");
79aceca5
FB		 2643}
2644
9a64fbe4 2645#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
79aceca5
FB		 2646#define SPR_UR SPR_RIGHTS(0, 0)
2647#define SPR_UW SPR_RIGHTS(1, 0)
2648#define SPR_SR SPR_RIGHTS(0, 1)
2649#define SPR_SW SPR_RIGHTS(1, 1)
2650
2651#define spr_set_rights(spr, rights) \
2652do { \
2653 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2654} while (0)
2655
9a64fbe4 2656static void init_spr_rights (uint32_t pvr)
79aceca5
FB		 2657{
2658 /* XER (SPR 1) */
9a64fbe4 2659 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2660 /* LR (SPR 8) */
9a64fbe4 2661 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2662 /* CTR (SPR 9) */
9a64fbe4 2663 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2664 /* TBL (SPR 268) */
9a64fbe4 2665 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
79aceca5 2666 /* TBU (SPR 269) */
9a64fbe4 2667 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
79aceca5 2668 /* DSISR (SPR 18) */
9a64fbe4 2669 spr_set_rights(DSISR, SPR_SR | SPR_SW);
79aceca5 2670 /* DAR (SPR 19) */
9a64fbe4 2671 spr_set_rights(DAR, SPR_SR | SPR_SW);
79aceca5 2672 /* DEC (SPR 22) */
9a64fbe4 2673 spr_set_rights(DECR, SPR_SR | SPR_SW);
79aceca5 2674 /* SDR1 (SPR 25) */
9a64fbe4
FB		 2675 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2676 /* SRR0 (SPR 26) */
2677 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2678 /* SRR1 (SPR 27) */
2679 spr_set_rights(SRR1, SPR_SR | SPR_SW);
79aceca5 2680 /* SPRG0 (SPR 272) */
9a64fbe4 2681 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
79aceca5 2682 /* SPRG1 (SPR 273) */
9a64fbe4 2683 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
79aceca5 2684 /* SPRG2 (SPR 274) */
9a64fbe4 2685 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
79aceca5 2686 /* SPRG3 (SPR 275) */
9a64fbe4 2687 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
79aceca5 2688 /* ASR (SPR 280) */
9a64fbe4 2689 spr_set_rights(ASR, SPR_SR | SPR_SW);
79aceca5 2690 /* EAR (SPR 282) */
9a64fbe4
FB		 2691 spr_set_rights(EAR, SPR_SR | SPR_SW);
2692 /* TBL (SPR 284) */
2693 spr_set_rights(O_TBL, SPR_SW);
2694 /* TBU (SPR 285) */
2695 spr_set_rights(O_TBU, SPR_SW);
2696 /* PVR (SPR 287) */
2697 spr_set_rights(PVR, SPR_SR);
79aceca5 2698 /* IBAT0U (SPR 528) */
9a64fbe4 2699 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
79aceca5 2700 /* IBAT0L (SPR 529) */
9a64fbe4 2701 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
79aceca5 2702 /* IBAT1U (SPR 530) */
9a64fbe4 2703 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
79aceca5 2704 /* IBAT1L (SPR 531) */
9a64fbe4 2705 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
79aceca5 2706 /* IBAT2U (SPR 532) */
9a64fbe4 2707 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
79aceca5 2708 /* IBAT2L (SPR 533) */
9a64fbe4 2709 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
79aceca5 2710 /* IBAT3U (SPR 534) */
9a64fbe4 2711 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
79aceca5 2712 /* IBAT3L (SPR 535) */
9a64fbe4 2713 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
79aceca5 2714 /* DBAT0U (SPR 536) */
9a64fbe4 2715 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
79aceca5 2716 /* DBAT0L (SPR 537) */
9a64fbe4 2717 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
79aceca5 2718 /* DBAT1U (SPR 538) */
9a64fbe4 2719 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
79aceca5 2720 /* DBAT1L (SPR 539) */
9a64fbe4 2721 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
79aceca5 2722 /* DBAT2U (SPR 540) */
9a64fbe4 2723 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
79aceca5 2724 /* DBAT2L (SPR 541) */
9a64fbe4 2725 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
79aceca5 2726 /* DBAT3U (SPR 542) */
9a64fbe4 2727 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
79aceca5 2728 /* DBAT3L (SPR 543) */
9a64fbe4 2729 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
79aceca5 2730 /* DABR (SPR 1013) */
9a64fbe4 2731 spr_set_rights(DABR, SPR_SR | SPR_SW);
79aceca5 2732 /* FPECR (SPR 1022) */
9a64fbe4 2733 spr_set_rights(FPECR, SPR_SR | SPR_SW);
79aceca5 2734 /* PIR (SPR 1023) */
9a64fbe4
FB		 2735 spr_set_rights(PIR, SPR_SR | SPR_SW);
2736 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2737 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2738 (pvr & 0xFFFF0000) == 0x70000000) {
2739 /* HID0 */
2740 spr_set_rights(SPR_ENCODE(1008), SPR_SR | SPR_SW);
2741 /* HID1 */
2742 spr_set_rights(SPR_ENCODE(1009), SPR_SR | SPR_SW);
2743 /* IABR */
2744 spr_set_rights(SPR_ENCODE(1010), SPR_SR | SPR_SW);
2745 /* ICTC */
2746 spr_set_rights(SPR_ENCODE(1019), SPR_SR | SPR_SW);
2747 /* L2CR */
2748 spr_set_rights(SPR_ENCODE(1017), SPR_SR | SPR_SW);
2749 /* MMCR0 */
2750 spr_set_rights(SPR_ENCODE(952), SPR_SR | SPR_SW);
2751 /* MMCR1 */
2752 spr_set_rights(SPR_ENCODE(956), SPR_SR | SPR_SW);
2753 /* PMC1 */
2754 spr_set_rights(SPR_ENCODE(953), SPR_SR | SPR_SW);
2755 /* PMC2 */
2756 spr_set_rights(SPR_ENCODE(954), SPR_SR | SPR_SW);
2757 /* PMC3 */
2758 spr_set_rights(SPR_ENCODE(957), SPR_SR | SPR_SW);
2759 /* PMC4 */
2760 spr_set_rights(SPR_ENCODE(958), SPR_SR | SPR_SW);
2761 /* SIA */
2762 spr_set_rights(SPR_ENCODE(955), SPR_SR | SPR_SW);
2763 /* THRM1 */
2764 spr_set_rights(SPR_ENCODE(1020), SPR_SR | SPR_SW);
2765 /* THRM2 */
2766 spr_set_rights(SPR_ENCODE(1021), SPR_SR | SPR_SW);
2767 /* THRM3 */
2768 spr_set_rights(SPR_ENCODE(1022), SPR_SR | SPR_SW);
2769 /* UMMCR0 */
2770 spr_set_rights(SPR_ENCODE(936), SPR_UR | SPR_UW);
2771 /* UMMCR1 */
2772 spr_set_rights(SPR_ENCODE(940), SPR_UR | SPR_UW);
2773 /* UPMC1 */
2774 spr_set_rights(SPR_ENCODE(937), SPR_UR | SPR_UW);
2775 /* UPMC2 */
2776 spr_set_rights(SPR_ENCODE(938), SPR_UR | SPR_UW);
2777 /* UPMC3 */
2778 spr_set_rights(SPR_ENCODE(941), SPR_UR | SPR_UW);
2779 /* UPMC4 */
2780 spr_set_rights(SPR_ENCODE(942), SPR_UR | SPR_UW);
2781 /* USIA */
2782 spr_set_rights(SPR_ENCODE(939), SPR_UR | SPR_UW);
2783 }
2784 /* MPC755 has special registers */
2785 if (pvr == 0x00083100) {
2786 /* SPRG4 */
2787 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2788 /* SPRG5 */
2789 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2790 /* SPRG6 */
2791 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2792 /* SPRG7 */
2793 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2794 /* IBAT4U */
2795 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2796 /* IBAT4L */
2797 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2798 /* IBAT5U */
2799 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2800 /* IBAT5L */
2801 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2802 /* IBAT6U */
2803 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2804 /* IBAT6L */
2805 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2806 /* IBAT7U */
2807 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2808 /* IBAT7L */
2809 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2810 /* DBAT4U */
2811 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2812 /* DBAT4L */
2813 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2814 /* DBAT5U */
2815 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2816 /* DBAT5L */
2817 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2818 /* DBAT6U */
2819 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2820 /* DBAT6L */
2821 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2822 /* DBAT7U */
2823 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2824 /* DBAT7L */
2825 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2826 /* DMISS */
2827 spr_set_rights(SPR_ENCODE(976), SPR_SR | SPR_SW);
2828 /* DCMP */
2829 spr_set_rights(SPR_ENCODE(977), SPR_SR | SPR_SW);
2830 /* DHASH1 */
2831 spr_set_rights(SPR_ENCODE(978), SPR_SR | SPR_SW);
2832 /* DHASH2 */
2833 spr_set_rights(SPR_ENCODE(979), SPR_SR | SPR_SW);
2834 /* IMISS */
2835 spr_set_rights(SPR_ENCODE(980), SPR_SR | SPR_SW);
2836 /* ICMP */
2837 spr_set_rights(SPR_ENCODE(981), SPR_SR | SPR_SW);
2838 /* RPA */
2839 spr_set_rights(SPR_ENCODE(982), SPR_SR | SPR_SW);
2840 /* HID2 */
2841 spr_set_rights(SPR_ENCODE(1011), SPR_SR | SPR_SW);
2842 /* L2PM */
2843 spr_set_rights(SPR_ENCODE(1016), SPR_SR | SPR_SW);
2844 }
79aceca5
FB		 2845}
2846
9a64fbe4
FB		 2847/*****************************************************************************/
2848/* PPC "main stream" common instructions (no optional ones) */
79aceca5
FB		 2849
2850typedef struct ppc_proc_t {
2851 int flags;
2852 void *specific;
2853} ppc_proc_t;
2854
2855typedef struct ppc_def_t {
2856 unsigned long pvr;
2857 unsigned long pvr_mask;
2858 ppc_proc_t *proc;
2859} ppc_def_t;
2860
2861static ppc_proc_t ppc_proc_common = {
2862 .flags = PPC_COMMON,
2863 .specific = NULL,
2864};
2865
9a64fbe4
FB		 2866static ppc_proc_t ppc_proc_G3 = {
2867 .flags = PPC_750,
2868 .specific = NULL,
2869};
2870
79aceca5
FB		 2871static ppc_def_t ppc_defs[] =
2872{
9a64fbe4
FB		 2873 /* MPC740/745/750/755 (G3) */
2874 {
2875 .pvr = 0x00080000,
2876 .pvr_mask = 0xFFFF0000,
2877 .proc = &ppc_proc_G3,
2878 },
2879 /* IBM 750FX (G3 embedded) */
2880 {
2881 .pvr = 0x70000000,
2882 .pvr_mask = 0xFFFF0000,
2883 .proc = &ppc_proc_G3,
2884 },
2885 /* Fallback (generic PPC) */
79aceca5
FB		 2886 {
2887 .pvr = 0x00000000,
2888 .pvr_mask = 0x00000000,
2889 .proc = &ppc_proc_common,
2890 },
2891};
2892
9a64fbe4 2893static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
79aceca5
FB		 2894{
2895 opcode_t *opc;
2896 int i, flags;
2897
2898 fill_new_table(ppc_opcodes, 0x40);
2899 for (i = 0; ; i++) {
2900 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2901 (pvr & ppc_defs[i].pvr_mask)) {
2902 flags = ppc_defs[i].proc->flags;
2903 break;
2904 }
2905 }
2906
2907 for (opc = &opc_start + 1; opc != &opc_end; opc++) {
9a64fbe4
FB		 2908 if ((opc->handler.type & flags) != 0)
2909 if (register_insn(ppc_opcodes, opc) < 0) {
2910 printf("*** ERROR initializing PPC instruction "
79aceca5
FB		 2911 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2912 opc->opc3);
2913 return -1;
2914 }
2915 }
9a64fbe4 2916 fix_opcode_tables(ppc_opcodes);
79aceca5
FB		 2917
2918 return 0;
2919}
2920
9a64fbe4 2921
79aceca5 2922/*****************************************************************************/
9a64fbe4
FB		 2923/* Misc PPC helpers */
2924FILE *stdout;
79aceca5
FB		 2925
2926void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags)
2927{
2928 int i;
2929
9a64fbe4
FB		 2930 fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
2931 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
2932 _load_xer(), _load_msr());
79aceca5
FB		 2933 for (i = 0; i < 32; i++) {
2934 if ((i & 7) == 0)
9a64fbe4
FB		 2935 fprintf(f, "GPR%02d:", i);
2936 fprintf(f, " %08x", env->gpr[i]);
79aceca5 2937 if ((i & 7) == 7)
9a64fbe4 2938 fprintf(f, "\n");
79aceca5 2939 }
9a64fbe4 2940 fprintf(f, "CR: 0x");
79aceca5 2941 for (i = 0; i < 8; i++)
9a64fbe4
FB		 2942 fprintf(f, "%01x", env->crf[i]);
2943 fprintf(f, " [");
79aceca5
FB		 2944 for (i = 0; i < 8; i++) {
2945 char a = '-';
79aceca5
FB		 2946 if (env->crf[i] & 0x08)
2947 a = 'L';
2948 else if (env->crf[i] & 0x04)
2949 a = 'G';
2950 else if (env->crf[i] & 0x02)
2951 a = 'E';
9a64fbe4 2952 fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
79aceca5 2953 }
9a64fbe4
FB		 2954 fprintf(f, " ] ");
2955 fprintf(f, "TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
79aceca5
FB		 2956 for (i = 0; i < 16; i++) {
2957 if ((i & 3) == 0)
9a64fbe4
FB		 2958 fprintf(f, "FPR%02d:", i);
2959 fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
79aceca5 2960 if ((i & 3) == 3)
9a64fbe4 2961 fprintf(f, "\n");
79aceca5 2962 }
9a64fbe4
FB		 2963 fprintf(f, "SRR0 0x%08x SRR1 0x%08x\n",
2964 env->spr[SRR0], env->spr[SRR1]);
2965 fprintf(f, "reservation 0x%08x\n", env->reserve);
2966 fflush(f);
79aceca5
FB		 2967}
2968
9a64fbe4
FB		 2969#if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
2970int setup_machine (CPUPPCState *env, uint32_t mid);
2971#endif
2972
79aceca5
FB		 2973CPUPPCState *cpu_ppc_init(void)
2974{
2975 CPUPPCState *env;
2976
2977 cpu_exec_init();
2978
2979 env = malloc(sizeof(CPUPPCState));
2980 if (!env)
2981 return NULL;
2982 memset(env, 0, sizeof(CPUPPCState));
9a64fbe4
FB		 2983#if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
2984 setup_machine(env, 0);
2985#else
2986// env->spr[PVR] = 0; /* Basic PPC */
2987 env->spr[PVR] = 0x00080100; /* G3 CPU */
2988// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
2989// env->spr[PVR] = 0x00070100; /* IBM 750FX */
2990#endif
2991 env->decr = 0xFFFFFFFF;
2992 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
79aceca5 2993 return NULL;
9a64fbe4
FB		 2994 init_spr_rights(env->spr[PVR]);
2995 tlb_flush(env);
2996#if defined (DO_SINGLE_STEP)
2997 /* Single step trace mode */
2998 msr_se = 1;
2999#endif
3000#if defined(CONFIG_USER_ONLY)
3001 msr_pr = 1;
3002#endif
79aceca5
FB		 3003
3004 return env;
3005}
3006
3007void cpu_ppc_close(CPUPPCState *env)
3008{
3009 /* Should also remove all opcode tables... */
3010 free(env);
3011}
3012
9a64fbe4
FB		 3013/*****************************************************************************/
3014void raise_exception_err (int exception_index, int error_code);
3015int print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr,
3016 int dialect);
3017
79aceca5
FB		 3018int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3019 int search_pc)
3020{
3021 DisasContext ctx;
3022 opc_handler_t **table, *handler;
3023 uint32_t pc_start;
3024 uint16_t *gen_opc_end;
3025 int j, lj = -1;
79aceca5
FB		 3026
3027 pc_start = tb->pc;
3028 gen_opc_ptr = gen_opc_buf;
3029 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3030 gen_opparam_ptr = gen_opparam_buf;
3031 ctx.nip = (uint32_t *)pc_start;
3032 ctx.tb_offset = 0;
9a64fbe4 3033 ctx.decr_offset = 0;
79aceca5 3034 ctx.tb = tb;
9a64fbe4
FB		 3035 ctx.exception = EXCP_NONE;
3036#if defined(CONFIG_USER_ONLY)
3037 ctx.mem_idx = 0;
3038#else
3039 ctx.supervisor = 1 - msr_pr;
3040 ctx.mem_idx = (1 - msr_pr);
3041#endif
3042#if defined (DO_SINGLE_STEP)
3043 /* Single step trace mode */
3044 msr_se = 1;
3045#endif
3046 /* Set env in case of segfault during code fetch */
3047 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
79aceca5
FB		 3048 if (search_pc) {
3049 if (loglevel > 0)
3050 fprintf(logfile, "Search PC...\n");
3051 j = gen_opc_ptr - gen_opc_buf;
3052 if (lj < j) {
3053 lj++;
3054 while (lj < j)
3055 gen_opc_instr_start[lj++] = 0;
3056 gen_opc_pc[lj] = (uint32_t)ctx.nip;
3057 gen_opc_instr_start[lj] = 1;
3058 }
3059 }
9a64fbe4 3060#if defined DEBUG_DISAS
79aceca5
FB		 3061 if (loglevel > 0) {
3062 fprintf(logfile, "----------------\n");
9a64fbe4
FB		 3063 fprintf(logfile, "nip=%p super=%d ir=%d\n",
3064 ctx.nip, 1 - msr_pr, msr_ir);
3065 }
3066#endif
3067 ctx.opcode = ldl_code(ctx.nip);
3068#if defined DEBUG_DISAS
3069 if (loglevel > 0) {
3070 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3071 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3072 opc3(ctx.opcode));
79aceca5
FB		 3073 }
3074#endif
3075 ctx.nip++;
9a64fbe4
FB		 3076 ctx.tb_offset++;
3077 /* Check decrementer exception */
3078 if (++ctx.decr_offset == env->decr + 1)
3079 ctx.exception = EXCP_DECR;
79aceca5
FB		 3080 table = ppc_opcodes;
3081 handler = table[opc1(ctx.opcode)];
3082 if (is_indirect_opcode(handler)) {
3083 table = ind_table(handler);
3084 handler = table[opc2(ctx.opcode)];
3085 if (is_indirect_opcode(handler)) {
3086 table = ind_table(handler);
3087 handler = table[opc3(ctx.opcode)];
3088 }
3089 }
3090 /* Is opcode *REALLY* valid ? */
3091 if ((ctx.opcode & handler->inval) != 0) {
3092 if (loglevel > 0) {
3093 if (handler->handler == &gen_invalid) {
3094 fprintf(logfile, "invalid/unsupported opcode: "
9a64fbe4
FB		 3095 "%02x -%02x - %02x (%08x) %p\n",
3096 opc1(ctx.opcode), opc2(ctx.opcode),
3097 opc3(ctx.opcode), ctx.opcode, ctx.nip - 1);
79aceca5
FB		 3098 } else {
3099 fprintf(logfile, "invalid bits: %08x for opcode: "
9a64fbe4 3100 "%02x -%02x - %02x (0x%08x) (%p)\n",
79aceca5
FB		 3101 ctx.opcode & handler->inval, opc1(ctx.opcode),
3102 opc2(ctx.opcode), opc3(ctx.opcode),
9a64fbe4 3103 ctx.opcode, ctx.nip - 1);
79aceca5 3104 }
9a64fbe4
FB		 3105 } else {
3106 if (handler->handler == &gen_invalid) {
3107 printf("invalid/unsupported opcode: "
3108 "%02x -%02x - %02x (%08x) %p\n",
3109 opc1(ctx.opcode), opc2(ctx.opcode),
3110 opc3(ctx.opcode), ctx.opcode, ctx.nip - 1);
3111 } else {
3112 printf("invalid bits: %08x for opcode: "
3113 "%02x -%02x - %02x (0x%08x) (%p)\n",
3114 ctx.opcode & handler->inval, opc1(ctx.opcode),
3115 opc2(ctx.opcode), opc3(ctx.opcode),
3116 ctx.opcode, ctx.nip - 1);
3117 }
79aceca5 3118 }
9a64fbe4 3119 (*gen_invalid)(&ctx);
79aceca5 3120 } else {
9a64fbe4 3121 (*(handler->handler))(&ctx);
79aceca5 3122 }
9a64fbe4
FB		 3123 /* Check trace mode exceptions */
3124 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3125 /* Check in single step trace mode
3126 * we need to stop except if:
3127 * - rfi, trap or syscall
3128 * - first instruction of an exception handler
3129 */
3130 (msr_se && ((uint32_t)ctx.nip < 0x100 ||
3131 (uint32_t)ctx.nip > 0xF00 ||
3132 ((uint32_t)ctx.nip & 0xFC) != 0x04) &&
3133 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3134 ctx.exception != EXCP_TRAP)) {
3135#if !defined(CONFIG_USER_ONLY)
3136 gen_op_queue_exception(EXCP_TRACE);
79aceca5 3137#endif
9a64fbe4
FB		 3138 if (ctx.exception == EXCP_NONE) {
3139 ctx.exception = EXCP_TRACE;
79aceca5 3140 }
9a64fbe4
FB		 3141 }
3142 /* if too long translation, stop generation too */
3143 if (gen_opc_ptr >= gen_opc_end ||
3144 ((uint32_t)ctx.nip - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
3145 if (ctx.exception == EXCP_NONE) {
79aceca5 3146 gen_op_b((uint32_t)ctx.nip);
9a64fbe4 3147 ctx.exception = EXCP_BRANCH;
79aceca5 3148 }
79aceca5 3149 }
9a64fbe4
FB		 3150 }
3151 /* In case of branch, this has already been done *BEFORE* the branch */
3152 if (ctx.exception != EXCP_BRANCH && ctx.exception != EXCP_RFI) {
3153 gen_op_update_tb(ctx.tb_offset);
3154 gen_op_update_decr(ctx.decr_offset);
3155 gen_op_process_exceptions((uint32_t)ctx.nip);
3156 }
3157#if 1
79aceca5
FB		 3158 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3159 * do bad business and then qemu crashes !
3160 */
3161 gen_op_set_T0(0);
9a64fbe4 3162#endif
79aceca5
FB		 3163 /* Generate the return instruction */
3164 gen_op_exit_tb();
3165 *gen_opc_ptr = INDEX_op_end;
9a64fbe4
FB		 3166 if (search_pc) {
3167 j = gen_opc_ptr - gen_opc_buf;
3168 lj++;
3169 while (lj <= j)
3170 gen_opc_instr_start[lj++] = 0;
79aceca5 3171 tb->size = 0;
9a64fbe4
FB		 3172 if (loglevel > 0) {
3173 page_dump(logfile);
3174 }
3175 } else {
3176 tb->size = (uint32_t)ctx.nip - pc_start;
3177 }
79aceca5
FB		 3178#ifdef DEBUG_DISAS
3179 if (loglevel > 0) {
9a64fbe4
FB		 3180 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
3181 cpu_ppc_dump_state(env, logfile, 0);
79aceca5
FB		 3182 fprintf(logfile, "IN: %s\n", lookup_symbol((void *)pc_start));
3183 disas(logfile, (void *)pc_start, (uint32_t)ctx.nip - pc_start, 0, 0);
3184 fprintf(logfile, "\n");
3185
3186 fprintf(logfile, "OP:\n");
3187 dump_ops(gen_opc_buf, gen_opparam_buf);
3188 fprintf(logfile, "\n");
3189 }
3190#endif
3191
3192 return 0;
3193}
3194
9a64fbe4 3195int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3196{
3197 return gen_intermediate_code_internal(env, tb, 0);
3198}
3199
9a64fbe4 3200int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3201{
3202 return gen_intermediate_code_internal(env, tb, 1);
3203}
Qemu copy for testing