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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
79aceca5 19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
0cfe11ea 31#include "host-utils.h"
79aceca5 32
a7812ae4
PB		 33#include "helper.h"
34#define GEN_HELPER 1
35#include "helper.h"
36
8cbcb4fa
AJ		 37#define CPU_SINGLE_STEP 0x1
38#define CPU_BRANCH_STEP 0x2
39#define GDBSTUB_SINGLE_STEP 0x4
40
a750fc0b 41/* Include definitions for instructions classes and implementations flags */
e8fc4fa7 42//#define DO_SINGLE_STEP
9fddaa0c 43//#define PPC_DEBUG_DISAS
76a66253 44//#define DO_PPC_STATISTICS
79aceca5 45
d12d51d5 46#ifdef PPC_DEBUG_DISAS
93fcfe39 47# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 48#else
49# define LOG_DISAS(...) do { } while (0)
50#endif
a750fc0b
JM		 51/*****************************************************************************/
52/* Code translation helpers */
c53be334 53
f78fb44e 54/* global register indexes */
a7812ae4 55static TCGv_ptr cpu_env;
1d542695 56static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 57#if !defined(TARGET_PPC64)
1d542695 58 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 59#endif
a5e26afa 60 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 61 + 2*(10*6 + 22*7) /* AVRh, AVRl */
62 + 8*5 /* CRF */];
f78fb44e
AJ		 63static TCGv cpu_gpr[32];
64#if !defined(TARGET_PPC64)
65static TCGv cpu_gprh[32];
66#endif
a7812ae4
PB		 67static TCGv_i64 cpu_fpr[32];
68static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
69static TCGv_i32 cpu_crf[8];
bd568f18 70static TCGv cpu_nip;
6527f6ea 71static TCGv cpu_msr;
cfdcd37a
AJ		 72static TCGv cpu_ctr;
73static TCGv cpu_lr;
3d7b417e 74static TCGv cpu_xer;
cf360a32 75static TCGv cpu_reserve;
a7812ae4 76static TCGv_i32 cpu_fpscr;
a7859e89 77static TCGv_i32 cpu_access_type;
f78fb44e 78
2e70f6ef
PB		 79#include "gen-icount.h"
80
81void ppc_translate_init(void)
82{
f78fb44e
AJ		 83 int i;
84 char* p;
b2437bf2 85 static int done_init = 0;
f78fb44e 86
2e70f6ef
PB		 87 if (done_init)
88 return;
f78fb44e 89
a7812ae4 90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 91
f78fb44e 92 p = cpu_reg_names;
47e4661c
AJ		 93
94 for (i = 0; i < 8; i++) {
95 sprintf(p, "crf%d", i);
a7812ae4
PB		 96 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
97 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 98 p += 5;
99 }
100
f78fb44e
AJ		 101 for (i = 0; i < 32; i++) {
102 sprintf(p, "r%d", i);
a7812ae4 103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 104 offsetof(CPUState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106#if !defined(TARGET_PPC64)
107 sprintf(p, "r%dH", i);
a7812ae4
PB		 108 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
109 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 110 p += (i < 10) ? 4 : 5;
111#endif
1d542695 112
a5e26afa 113 sprintf(p, "fp%d", i);
a7812ae4
PB		 114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUState, fpr[i]), p);
ec1ac72d 116 p += (i < 10) ? 4 : 5;
a5e26afa 117
1d542695 118 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 119#ifdef WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUState, avr[i].u64[0]), p);
122#else
a7812ae4 123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 124 offsetof(CPUState, avr[i].u64[1]), p);
125#endif
1d542695 126 p += (i < 10) ? 6 : 7;
ec1ac72d 127
1d542695 128 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 129#ifdef WORDS_BIGENDIAN
130 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
131 offsetof(CPUState, avr[i].u64[1]), p);
132#else
a7812ae4 133 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 134 offsetof(CPUState, avr[i].u64[0]), p);
135#endif
1d542695 136 p += (i < 10) ? 6 : 7;
f78fb44e 137 }
f10dc08e 138
a7812ae4 139 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 140 offsetof(CPUState, nip), "nip");
141
6527f6ea
AJ		 142 cpu_msr = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUState, msr), "msr");
144
a7812ae4 145 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 146 offsetof(CPUState, ctr), "ctr");
147
a7812ae4 148 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 149 offsetof(CPUState, lr), "lr");
150
a7812ae4 151 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 152 offsetof(CPUState, xer), "xer");
153
cf360a32
AJ		 154 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, reserve), "reserve");
156
a7812ae4
PB		 157 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
158 offsetof(CPUState, fpscr), "fpscr");
e1571908 159
a7859e89
AJ		 160 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
161 offsetof(CPUState, access_type), "access_type");
162
f10dc08e 163 /* register helpers */
a7812ae4 164#define GEN_HELPER 2
f10dc08e
AJ		 165#include "helper.h"
166
2e70f6ef
PB		 167 done_init = 1;
168}
169
79aceca5
FB		 170/* internal defines */
171typedef struct DisasContext {
172 struct TranslationBlock *tb;
0fa85d43 173 target_ulong nip;
79aceca5 174 uint32_t opcode;
9a64fbe4 175 uint32_t exception;
3cc62370
FB		 176 /* Routine used to access memory */
177 int mem_idx;
76db3ba4 178 int access_type;
3cc62370 179 /* Translation flags */
76db3ba4 180 int le_mode;
d9bce9d9
JM		 181#if defined(TARGET_PPC64)
182 int sf_mode;
9a64fbe4 183#endif
3cc62370 184 int fpu_enabled;
a9d9eb8f 185 int altivec_enabled;
0487d6a8 186 int spe_enabled;
3fc6c082 187 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 188 int singlestep_enabled;
79aceca5
FB		 189} DisasContext;
190
3fc6c082 191struct opc_handler_t {
79aceca5
FB		 192 /* invalid bits */
193 uint32_t inval;
9a64fbe4 194 /* instruction type */
0487d6a8 195 uint64_t type;
79aceca5
FB		 196 /* handler */
197 void (*handler)(DisasContext *ctx);
a750fc0b 198#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 199 const char *oname;
a750fc0b
JM		 200#endif
201#if defined(DO_PPC_STATISTICS)
76a66253
JM		 202 uint64_t count;
203#endif
3fc6c082 204};
79aceca5 205
7c58044c
JM		 206static always_inline void gen_reset_fpstatus (void)
207{
208#ifdef CONFIG_SOFTFLOAT
a44d2ce1 209 gen_helper_reset_fpstatus();
7c58044c
JM		 210#endif
211}
212
0f2f39c2 213static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 214{
0f2f39c2 215 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 216
7c58044c
JM		 217 if (set_fprf != 0) {
218 /* This case might be optimized later */
0f2f39c2 219 tcg_gen_movi_i32(t0, 1);
af12906f 220 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 221 if (unlikely(set_rc)) {
0f2f39c2 222 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 223 }
af12906f 224 gen_helper_float_check_status();
7c58044c
JM		 225 } else if (unlikely(set_rc)) {
226 /* We always need to compute fpcc */
0f2f39c2 227 tcg_gen_movi_i32(t0, 0);
af12906f 228 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 229 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 230 }
af12906f 231
0f2f39c2 232 tcg_temp_free_i32(t0);
7c58044c
JM		 233}
234
76db3ba4 235static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
a7859e89 236{
76db3ba4
AJ		 237 if (ctx->access_type != access_type) {
238 tcg_gen_movi_i32(cpu_access_type, access_type);
239 ctx->access_type = access_type;
240 }
a7859e89
AJ		 241}
242
b068d6a7 243static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 244{
245#if defined(TARGET_PPC64)
246 if (ctx->sf_mode)
bd568f18 247 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 248 else
249#endif
bd568f18 250 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 251}
252
e06fcd75
AJ		 253static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
254{
255 TCGv_i32 t0, t1;
256 if (ctx->exception == POWERPC_EXCP_NONE) {
257 gen_update_nip(ctx, ctx->nip);
258 }
259 t0 = tcg_const_i32(excp);
260 t1 = tcg_const_i32(error);
261 gen_helper_raise_exception_err(t0, t1);
262 tcg_temp_free_i32(t0);
263 tcg_temp_free_i32(t1);
264 ctx->exception = (excp);
265}
e1833e1f 266
e06fcd75
AJ		 267static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
268{
269 TCGv_i32 t0;
270 if (ctx->exception == POWERPC_EXCP_NONE) {
271 gen_update_nip(ctx, ctx->nip);
272 }
273 t0 = tcg_const_i32(excp);
274 gen_helper_raise_exception(t0);
275 tcg_temp_free_i32(t0);
276 ctx->exception = (excp);
277}
e1833e1f 278
e06fcd75
AJ		 279static always_inline void gen_debug_exception (DisasContext *ctx)
280{
281 TCGv_i32 t0;
5518f3a6
BS		 282
283 if (ctx->exception != POWERPC_EXCP_BRANCH)
284 gen_update_nip(ctx, ctx->nip);
e06fcd75
AJ		 285 t0 = tcg_const_i32(EXCP_DEBUG);
286 gen_helper_raise_exception(t0);
287 tcg_temp_free_i32(t0);
288}
9a64fbe4 289
e06fcd75
AJ		 290static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
291{
292 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
293}
a9d9eb8f 294
f24e5695 295/* Stop translation */
e06fcd75 296static always_inline void gen_stop_exception (DisasContext *ctx)
3fc6c082 297{
d9bce9d9 298 gen_update_nip(ctx, ctx->nip);
e1833e1f 299 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 300}
301
f24e5695 302/* No need to update nip here, as execution flow will change */
e06fcd75 303static always_inline void gen_sync_exception (DisasContext *ctx)
2be0071f 304{
e1833e1f 305 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 306}
307
79aceca5
FB		 308#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
309static void gen_##name (DisasContext *ctx); \
310GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
311static void gen_##name (DisasContext *ctx)
312
c7697e1f
JM		 313#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
314static void gen_##name (DisasContext *ctx); \
315GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
316static void gen_##name (DisasContext *ctx)
317
79aceca5
FB		 318typedef struct opcode_t {
319 unsigned char opc1, opc2, opc3;
1235fc06 320#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 321 unsigned char pad[5];
322#else
323 unsigned char pad[1];
324#endif
79aceca5 325 opc_handler_t handler;
b55266b5 326 const char *oname;
79aceca5
FB		 327} opcode_t;
328
a750fc0b 329/*****************************************************************************/
79aceca5
FB		 330/*** Instruction decoding ***/
331#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 332static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 333{ \
334 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
335}
336
337#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 338static always_inline int32_t name (uint32_t opcode) \
79aceca5 339{ \
18fba28c 340 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 341}
342
343/* Opcode part 1 */
344EXTRACT_HELPER(opc1, 26, 6);
345/* Opcode part 2 */
346EXTRACT_HELPER(opc2, 1, 5);
347/* Opcode part 3 */
348EXTRACT_HELPER(opc3, 6, 5);
349/* Update Cr0 flags */
350EXTRACT_HELPER(Rc, 0, 1);
351/* Destination */
352EXTRACT_HELPER(rD, 21, 5);
353/* Source */
354EXTRACT_HELPER(rS, 21, 5);
355/* First operand */
356EXTRACT_HELPER(rA, 16, 5);
357/* Second operand */
358EXTRACT_HELPER(rB, 11, 5);
359/* Third operand */
360EXTRACT_HELPER(rC, 6, 5);
361/*** Get CRn ***/
362EXTRACT_HELPER(crfD, 23, 3);
363EXTRACT_HELPER(crfS, 18, 3);
364EXTRACT_HELPER(crbD, 21, 5);
365EXTRACT_HELPER(crbA, 16, 5);
366EXTRACT_HELPER(crbB, 11, 5);
367/* SPR / TBL */
3fc6c082 368EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 369static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 370{
371 uint32_t sprn = _SPR(opcode);
372
373 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
374}
79aceca5
FB		 375/*** Get constants ***/
376EXTRACT_HELPER(IMM, 12, 8);
377/* 16 bits signed immediate value */
378EXTRACT_SHELPER(SIMM, 0, 16);
379/* 16 bits unsigned immediate value */
380EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 381/* 5 bits signed immediate value */
382EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 383/* 5 bits signed immediate value */
384EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 385/* Bit count */
386EXTRACT_HELPER(NB, 11, 5);
387/* Shift count */
388EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 389/* Vector shift count */
390EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 391/* Mask start */
392EXTRACT_HELPER(MB, 6, 5);
393/* Mask end */
394EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 395/* Trap operand */
396EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 397
398EXTRACT_HELPER(CRM, 12, 8);
399EXTRACT_HELPER(FM, 17, 8);
400EXTRACT_HELPER(SR, 16, 4);
e4bb997e 401EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 402
79aceca5
FB		 403/*** Jump target decoding ***/
404/* Displacement */
405EXTRACT_SHELPER(d, 0, 16);
406/* Immediate address */
b068d6a7 407static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 408{
409 return (opcode >> 0) & 0x03FFFFFC;
410}
411
b068d6a7 412static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 413{
414 return (opcode >> 0) & 0xFFFC;
415}
416
417EXTRACT_HELPER(BO, 21, 5);
418EXTRACT_HELPER(BI, 16, 5);
419/* Absolute/relative address */
420EXTRACT_HELPER(AA, 1, 1);
421/* Link */
422EXTRACT_HELPER(LK, 0, 1);
423
424/* Create a mask between <start> and <end> bits */
b068d6a7 425static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 426{
76a66253 427 target_ulong ret;
79aceca5 428
76a66253
JM		 429#if defined(TARGET_PPC64)
430 if (likely(start == 0)) {
6f2d8978 431 ret = UINT64_MAX << (63 - end);
76a66253 432 } else if (likely(end == 63)) {
6f2d8978 433 ret = UINT64_MAX >> start;
76a66253
JM		 434 }
435#else
436 if (likely(start == 0)) {
6f2d8978 437 ret = UINT32_MAX << (31 - end);
76a66253 438 } else if (likely(end == 31)) {
6f2d8978 439 ret = UINT32_MAX >> start;
76a66253
JM		 440 }
441#endif
442 else {
443 ret = (((target_ulong)(-1ULL)) >> (start)) ^
444 (((target_ulong)(-1ULL) >> (end)) >> 1);
445 if (unlikely(start > end))
446 return ~ret;
447 }
79aceca5
FB		 448
449 return ret;
450}
451
a750fc0b
JM		 452/*****************************************************************************/
453/* PowerPC Instructions types definitions */
454enum {
1b413d55 455 PPC_NONE = 0x0000000000000000ULL,
12de9a39 456 /* PowerPC base instructions set */
1b413d55
JM		 457 PPC_INSNS_BASE = 0x0000000000000001ULL,
458 /* integer operations instructions */
a750fc0b 459#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 460 /* flow control instructions */
a750fc0b 461#define PPC_FLOW PPC_INSNS_BASE
1b413d55 462 /* virtual memory instructions */
a750fc0b 463#define PPC_MEM PPC_INSNS_BASE
1b413d55 464 /* ld/st with reservation instructions */
a750fc0b 465#define PPC_RES PPC_INSNS_BASE
1b413d55 466 /* spr/msr access instructions */
a750fc0b 467#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 468 /* Deprecated instruction sets */
469 /* Original POWER instruction set */
f610349f 470 PPC_POWER = 0x0000000000000002ULL,
1b413d55 471 /* POWER2 instruction set extension */
f610349f 472 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 473 /* Power RTC support */
f610349f 474 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 475 /* Power-to-PowerPC bridge (601) */
f610349f 476 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 477 /* 64 bits PowerPC instruction set */
f610349f 478 PPC_64B = 0x0000000000000020ULL,
1b413d55 479 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 480 PPC_64BX = 0x0000000000000040ULL,
1b413d55 481 /* 64 bits hypervisor extensions */
f610349f 482 PPC_64H = 0x0000000000000080ULL,
1b413d55 483 /* New wait instruction (PowerPC 2.0x) */
f610349f 484 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 485 /* Time base mftb instruction */
f610349f 486 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 487
488 /* Fixed-point unit extensions */
489 /* PowerPC 602 specific */
f610349f 490 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 491 /* isel instruction */
492 PPC_ISEL = 0x0000000000000800ULL,
493 /* popcntb instruction */
494 PPC_POPCNTB = 0x0000000000001000ULL,
495 /* string load / store */
496 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 497
498 /* Floating-point unit extensions */
499 /* Optional floating point instructions */
500 PPC_FLOAT = 0x0000000000010000ULL,
501 /* New floating-point extensions (PowerPC 2.0x) */
502 PPC_FLOAT_EXT = 0x0000000000020000ULL,
503 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
504 PPC_FLOAT_FRES = 0x0000000000080000ULL,
505 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
506 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
507 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
508 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
509
510 /* Vector/SIMD extensions */
511 /* Altivec support */
512 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 513 /* PowerPC 2.03 SPE extension */
05332d70 514 PPC_SPE = 0x0000000002000000ULL,
40569b7e
AJ		 515 /* PowerPC 2.03 SPE single-precision floating-point extension */
516 PPC_SPE_SINGLE = 0x0000000004000000ULL,
517 /* PowerPC 2.03 SPE double-precision floating-point extension */
518 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1b413d55 519
12de9a39 520 /* Optional memory control instructions */
1b413d55
JM		 521 PPC_MEM_TLBIA = 0x0000000010000000ULL,
522 PPC_MEM_TLBIE = 0x0000000020000000ULL,
523 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
524 /* sync instruction */
525 PPC_MEM_SYNC = 0x0000000080000000ULL,
526 /* eieio instruction */
527 PPC_MEM_EIEIO = 0x0000000100000000ULL,
528
529 /* Cache control instructions */
c8623f2e 530 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 531 /* icbi instruction */
05332d70 532 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 533 /* dcbz instruction with fixed cache line size */
05332d70 534 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 535 /* dcbz instruction with tunable cache line size */
05332d70 536 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 537 /* dcba instruction */
05332d70
JM		 538 PPC_CACHE_DCBA = 0x0000002000000000ULL,
539 /* Freescale cache locking instructions */
540 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 541
542 /* MMU related extensions */
543 /* external control instructions */
05332d70 544 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 545 /* segment register access instructions */
05332d70 546 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 547 /* PowerPC 6xx TLB management instructions */
05332d70 548 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 549 /* PowerPC 74xx TLB management instructions */
05332d70 550 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 551 /* PowerPC 40x TLB management instructions */
05332d70 552 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 553 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 554 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 555 /* SLB management */
05332d70 556 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 557
12de9a39 558 /* Embedded PowerPC dedicated instructions */
05332d70 559 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 560 /* PowerPC 40x exception model */
05332d70 561 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 562 /* PowerPC 405 Mac instructions */
05332d70 563 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 564 /* PowerPC 440 specific instructions */
05332d70 565 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 566 /* BookE (embedded) PowerPC specification */
05332d70
JM		 567 PPC_BOOKE = 0x0010000000000000ULL,
568 /* mfapidi instruction */
569 PPC_MFAPIDI = 0x0020000000000000ULL,
570 /* tlbiva instruction */
571 PPC_TLBIVA = 0x0040000000000000ULL,
572 /* tlbivax instruction */
573 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 574 /* PowerPC 4xx dedicated instructions */
05332d70 575 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 576 /* PowerPC 40x ibct instructions */
05332d70 577 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 578 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 579 PPC_RFMCI = 0x0400000000000000ULL,
580 /* rfdi instruction */
581 PPC_RFDI = 0x0800000000000000ULL,
582 /* DCR accesses */
583 PPC_DCR = 0x1000000000000000ULL,
584 /* DCR extended accesse */
585 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 586 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 587 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 588};
589
590/*****************************************************************************/
591/* PowerPC instructions table */
3fc6c082
FB		 592#if HOST_LONG_BITS == 64
593#define OPC_ALIGN 8
594#else
595#define OPC_ALIGN 4
596#endif
1b039c09 597#if defined(__APPLE__)
d9bce9d9 598#define OPCODES_SECTION \
3fc6c082 599 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 600#else
d9bce9d9 601#define OPCODES_SECTION \
3fc6c082 602 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 603#endif
604
76a66253 605#if defined(DO_PPC_STATISTICS)
79aceca5 606#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
50773fd2 607extern opcode_t opc_##name; \
18fba28c 608OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 609 .opc1 = op1, \
610 .opc2 = op2, \
611 .opc3 = op3, \
18fba28c 612 .pad = { 0, }, \
79aceca5
FB		 613 .handler = { \
614 .inval = invl, \
9a64fbe4 615 .type = _typ, \
79aceca5 616 .handler = &gen_##name, \
76a66253 617 .oname = stringify(name), \
79aceca5 618 }, \
3fc6c082 619 .oname = stringify(name), \
79aceca5 620}
c7697e1f
JM		 621#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
622OPCODES_SECTION opcode_t opc_##name = { \
623 .opc1 = op1, \
624 .opc2 = op2, \
625 .opc3 = op3, \
626 .pad = { 0, }, \
627 .handler = { \
628 .inval = invl, \
629 .type = _typ, \
630 .handler = &gen_##name, \
631 .oname = onam, \
632 }, \
633 .oname = onam, \
634}
76a66253
JM		 635#else
636#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
50773fd2 637extern opcode_t opc_##name; \
76a66253
JM		 638OPCODES_SECTION opcode_t opc_##name = { \
639 .opc1 = op1, \
640 .opc2 = op2, \
641 .opc3 = op3, \
642 .pad = { 0, }, \
643 .handler = { \
644 .inval = invl, \
645 .type = _typ, \
646 .handler = &gen_##name, \
647 }, \
648 .oname = stringify(name), \
649}
c7697e1f 650#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
50773fd2 651extern opcode_t opc_##name; \
c7697e1f
JM		 652OPCODES_SECTION opcode_t opc_##name = { \
653 .opc1 = op1, \
654 .opc2 = op2, \
655 .opc3 = op3, \
656 .pad = { 0, }, \
657 .handler = { \
658 .inval = invl, \
659 .type = _typ, \
660 .handler = &gen_##name, \
661 }, \
662 .oname = onam, \
663}
76a66253 664#endif
79aceca5
FB		 665
666#define GEN_OPCODE_MARK(name) \
50773fd2 667extern opcode_t opc_##name; \
18fba28c 668OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 669 .opc1 = 0xFF, \
670 .opc2 = 0xFF, \
671 .opc3 = 0xFF, \
18fba28c 672 .pad = { 0, }, \
79aceca5
FB		 673 .handler = { \
674 .inval = 0x00000000, \
9a64fbe4 675 .type = 0x00, \
79aceca5
FB		 676 .handler = NULL, \
677 }, \
3fc6c082 678 .oname = stringify(name), \
79aceca5
FB		 679}
680
54cdcae6
AJ		 681/* SPR load/store helpers */
682static always_inline void gen_load_spr(TCGv t, int reg)
683{
684 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
685}
686
687static always_inline void gen_store_spr(int reg, TCGv t)
688{
689 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
690}
691
79aceca5
FB		 692/* Start opcode list */
693GEN_OPCODE_MARK(start);
694
695/* Invalid instruction */
9a64fbe4
FB		 696GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
697{
e06fcd75 698 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 699}
700
79aceca5
FB		 701static opc_handler_t invalid_handler = {
702 .inval = 0xFFFFFFFF,
9a64fbe4 703 .type = PPC_NONE,
79aceca5
FB		 704 .handler = gen_invalid,
705};
706
e1571908
AJ		 707/*** Integer comparison ***/
708
ea363694 709static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 710{
711 int l1, l2, l3;
712
269f3e95
AJ		 713 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
714 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 715 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
716
717 l1 = gen_new_label();
718 l2 = gen_new_label();
719 l3 = gen_new_label();
720 if (s) {
ea363694
AJ		 721 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 723 } else {
ea363694
AJ		 724 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
725 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 726 }
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
728 tcg_gen_br(l3);
729 gen_set_label(l1);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
731 tcg_gen_br(l3);
732 gen_set_label(l2);
733 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
734 gen_set_label(l3);
735}
736
ea363694 737static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 738{
ea363694
AJ		 739 TCGv t0 = tcg_const_local_tl(arg1);
740 gen_op_cmp(arg0, t0, s, crf);
741 tcg_temp_free(t0);
e1571908
AJ		 742}
743
744#if defined(TARGET_PPC64)
ea363694 745static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 746{
ea363694 747 TCGv t0, t1;
a7812ae4
PB		 748 t0 = tcg_temp_local_new();
749 t1 = tcg_temp_local_new();
e1571908 750 if (s) {
ea363694
AJ		 751 tcg_gen_ext32s_tl(t0, arg0);
752 tcg_gen_ext32s_tl(t1, arg1);
e1571908 753 } else {
ea363694
AJ		 754 tcg_gen_ext32u_tl(t0, arg0);
755 tcg_gen_ext32u_tl(t1, arg1);
e1571908 756 }
ea363694
AJ		 757 gen_op_cmp(t0, t1, s, crf);
758 tcg_temp_free(t1);
759 tcg_temp_free(t0);
e1571908
AJ		 760}
761
ea363694 762static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 763{
ea363694
AJ		 764 TCGv t0 = tcg_const_local_tl(arg1);
765 gen_op_cmp32(arg0, t0, s, crf);
766 tcg_temp_free(t0);
e1571908
AJ		 767}
768#endif
769
770static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
771{
772#if defined(TARGET_PPC64)
773 if (!(ctx->sf_mode))
774 gen_op_cmpi32(reg, 0, 1, 0);
775 else
776#endif
777 gen_op_cmpi(reg, 0, 1, 0);
778}
779
780/* cmp */
781GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
782{
783#if defined(TARGET_PPC64)
784 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
785 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787 else
788#endif
789 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
790 1, crfD(ctx->opcode));
791}
792
793/* cmpi */
794GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
795{
796#if defined(TARGET_PPC64)
797 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
798 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800 else
801#endif
802 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
803 1, crfD(ctx->opcode));
804}
805
806/* cmpl */
807GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
808{
809#if defined(TARGET_PPC64)
810 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
811 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813 else
814#endif
815 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
816 0, crfD(ctx->opcode));
817}
818
819/* cmpli */
820GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
821{
822#if defined(TARGET_PPC64)
823 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
824 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826 else
827#endif
828 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
829 0, crfD(ctx->opcode));
830}
831
832/* isel (PowerPC 2.03 specification) */
833GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
834{
835 int l1, l2;
836 uint32_t bi = rC(ctx->opcode);
837 uint32_t mask;
a7812ae4 838 TCGv_i32 t0;
e1571908
AJ		 839
840 l1 = gen_new_label();
841 l2 = gen_new_label();
842
843 mask = 1 << (3 - (bi & 0x03));
a7812ae4 844 t0 = tcg_temp_new_i32();
fea0c503
AJ		 845 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
846 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 847 if (rA(ctx->opcode) == 0)
848 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
849 else
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
851 tcg_gen_br(l2);
852 gen_set_label(l1);
853 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
854 gen_set_label(l2);
a7812ae4 855 tcg_temp_free_i32(t0);
e1571908
AJ		 856}
857
79aceca5 858/*** Integer arithmetic ***/
79aceca5 859
74637406
AJ		 860static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
861{
862 int l1;
863 TCGv t0;
79aceca5 864
74637406
AJ		 865 l1 = gen_new_label();
866 /* Start with XER OV disabled, the most likely case */
867 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 868 t0 = tcg_temp_local_new();
74637406
AJ		 869 tcg_gen_xor_tl(t0, arg0, arg1);
870#if defined(TARGET_PPC64)
871 if (!ctx->sf_mode)
872 tcg_gen_ext32s_tl(t0, t0);
873#endif
874 if (sub)
875 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
876 else
877 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
878 tcg_gen_xor_tl(t0, arg1, arg2);
879#if defined(TARGET_PPC64)
880 if (!ctx->sf_mode)
881 tcg_gen_ext32s_tl(t0, t0);
882#endif
883 if (sub)
884 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
885 else
886 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
887 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
888 gen_set_label(l1);
889 tcg_temp_free(t0);
79aceca5
FB		 890}
891
74637406
AJ		 892static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
893{
894 int l1 = gen_new_label();
d9bce9d9
JM		 895
896#if defined(TARGET_PPC64)
74637406
AJ		 897 if (!(ctx->sf_mode)) {
898 TCGv t0, t1;
a7812ae4
PB		 899 t0 = tcg_temp_new();
900 t1 = tcg_temp_new();
d9bce9d9 901
74637406
AJ		 902 tcg_gen_ext32u_tl(t0, arg1);
903 tcg_gen_ext32u_tl(t1, arg2);
904 if (sub) {
905 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 906 } else {
74637406
AJ		 907 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
908 }
a9730017
AJ		 909 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
910 gen_set_label(l1);
911 tcg_temp_free(t0);
912 tcg_temp_free(t1);
74637406
AJ		 913 } else
914#endif
a9730017
AJ		 915 {
916 if (sub) {
917 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
918 } else {
919 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
920 }
921 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
922 gen_set_label(l1);
74637406 923 }
d9bce9d9
JM		 924}
925
74637406
AJ		 926/* Common add function */
927static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
928 int add_ca, int compute_ca, int compute_ov)
929{
930 TCGv t0, t1;
d9bce9d9 931
74637406 932 if ((!compute_ca && !compute_ov) ||
a7812ae4 933 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 934 t0 = ret;
935 } else {
a7812ae4 936 t0 = tcg_temp_local_new();
74637406 937 }
79aceca5 938
74637406 939 if (add_ca) {
a7812ae4 940 t1 = tcg_temp_local_new();
74637406
AJ		 941 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
942 tcg_gen_shri_tl(t1, t1, XER_CA);
943 }
79aceca5 944
74637406
AJ		 945 if (compute_ca && compute_ov) {
946 /* Start with XER CA and OV disabled, the most likely case */
947 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
948 } else if (compute_ca) {
949 /* Start with XER CA disabled, the most likely case */
950 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
951 } else if (compute_ov) {
952 /* Start with XER OV disabled, the most likely case */
953 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
954 }
79aceca5 955
74637406
AJ		 956 tcg_gen_add_tl(t0, arg1, arg2);
957
958 if (compute_ca) {
959 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
960 }
961 if (add_ca) {
962 tcg_gen_add_tl(t0, t0, t1);
963 gen_op_arith_compute_ca(ctx, t0, t1, 0);
964 tcg_temp_free(t1);
965 }
966 if (compute_ov) {
967 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
968 }
969
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, t0);
972
a7812ae4 973 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 974 tcg_gen_mov_tl(ret, t0);
975 tcg_temp_free(t0);
976 }
39dd32ee 977}
74637406
AJ		 978/* Add functions with two operands */
979#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
980GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
981{ \
982 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 add_ca, compute_ca, compute_ov); \
985}
986/* Add functions with one operand and one immediate */
987#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
988 add_ca, compute_ca, compute_ov) \
989GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
990{ \
991 TCGv t0 = tcg_const_local_tl(const_val); \
992 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], t0, \
994 add_ca, compute_ca, compute_ov); \
995 tcg_temp_free(t0); \
996}
997
998/* add add. addo addo. */
999GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1000GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1001/* addc addc. addco addco. */
1002GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1003GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1004/* adde adde. addeo addeo. */
1005GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1006GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1007/* addme addme. addmeo addmeo. */
1008GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1009GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1010/* addze addze. addzeo addzeo.*/
1011GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1012GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1013/* addi */
1014GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1015{
74637406
AJ		 1016 target_long simm = SIMM(ctx->opcode);
1017
1018 if (rA(ctx->opcode) == 0) {
1019 /* li case */
1020 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1021 } else {
1022 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1023 }
d9bce9d9 1024}
74637406
AJ		 1025/* addic addic.*/
1026static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1027 int compute_Rc0)
d9bce9d9 1028{
74637406
AJ		 1029 target_long simm = SIMM(ctx->opcode);
1030
1031 /* Start with XER CA and OV disabled, the most likely case */
1032 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1033
1034 if (likely(simm != 0)) {
a7812ae4 1035 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1036 tcg_gen_addi_tl(t0, arg1, simm);
1037 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1038 tcg_gen_mov_tl(ret, t0);
1039 tcg_temp_free(t0);
1040 } else {
1041 tcg_gen_mov_tl(ret, arg1);
1042 }
1043 if (compute_Rc0) {
1044 gen_set_Rc0(ctx, ret);
1045 }
d9bce9d9 1046}
74637406 1047GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1048{
74637406 1049 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1050}
74637406 1051GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1052{
74637406 1053 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1054}
74637406
AJ		 1055/* addis */
1056GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1057{
74637406
AJ		 1058 target_long simm = SIMM(ctx->opcode);
1059
1060 if (rA(ctx->opcode) == 0) {
1061 /* lis case */
1062 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1063 } else {
1064 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1065 }
d9bce9d9 1066}
74637406
AJ		 1067
1068static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1069 int sign, int compute_ov)
d9bce9d9 1070{
2ef1b120
AJ		 1071 int l1 = gen_new_label();
1072 int l2 = gen_new_label();
a7812ae4
PB		 1073 TCGv_i32 t0 = tcg_temp_local_new_i32();
1074 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1075
2ef1b120
AJ		 1076 tcg_gen_trunc_tl_i32(t0, arg1);
1077 tcg_gen_trunc_tl_i32(t1, arg2);
1078 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1079 if (sign) {
2ef1b120
AJ		 1080 int l3 = gen_new_label();
1081 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1082 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1083 gen_set_label(l3);
2ef1b120 1084 tcg_gen_div_i32(t0, t0, t1);
74637406 1085 } else {
2ef1b120 1086 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1087 }
1088 if (compute_ov) {
1089 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1090 }
1091 tcg_gen_br(l2);
1092 gen_set_label(l1);
1093 if (sign) {
2ef1b120 1094 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1095 } else {
1096 tcg_gen_movi_i32(t0, 0);
1097 }
1098 if (compute_ov) {
1099 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1100 }
1101 gen_set_label(l2);
2ef1b120 1102 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1103 tcg_temp_free_i32(t0);
1104 tcg_temp_free_i32(t1);
74637406
AJ		 1105 if (unlikely(Rc(ctx->opcode) != 0))
1106 gen_set_Rc0(ctx, ret);
d9bce9d9 1107}
74637406
AJ		 1108/* Div functions */
1109#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1110GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1111{ \
1112 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1114 sign, compute_ov); \
1115}
1116/* divwu divwu. divwuo divwuo. */
1117GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1118GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1119/* divw divw. divwo divwo. */
1120GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1121GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1122#if defined(TARGET_PPC64)
2ef1b120
AJ		 1123static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1124 int sign, int compute_ov)
d9bce9d9 1125{
2ef1b120
AJ		 1126 int l1 = gen_new_label();
1127 int l2 = gen_new_label();
74637406
AJ		 1128
1129 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1130 if (sign) {
2ef1b120 1131 int l3 = gen_new_label();
74637406
AJ		 1132 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1133 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1134 gen_set_label(l3);
74637406
AJ		 1135 tcg_gen_div_i64(ret, arg1, arg2);
1136 } else {
1137 tcg_gen_divu_i64(ret, arg1, arg2);
1138 }
1139 if (compute_ov) {
1140 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1141 }
1142 tcg_gen_br(l2);
1143 gen_set_label(l1);
1144 if (sign) {
1145 tcg_gen_sari_i64(ret, arg1, 63);
1146 } else {
1147 tcg_gen_movi_i64(ret, 0);
1148 }
1149 if (compute_ov) {
1150 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1151 }
1152 gen_set_label(l2);
1153 if (unlikely(Rc(ctx->opcode) != 0))
1154 gen_set_Rc0(ctx, ret);
d9bce9d9 1155}
74637406
AJ		 1156#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1157GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1158{ \
2ef1b120
AJ		 1159 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 sign, compute_ov); \
74637406
AJ		 1162}
1163/* divwu divwu. divwuo divwuo. */
1164GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1165GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1166/* divw divw. divwo divwo. */
1167GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1168GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1169#endif
74637406
AJ		 1170
1171/* mulhw mulhw. */
1172GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1173{
a7812ae4 1174 TCGv_i64 t0, t1;
74637406 1175
a7812ae4
PB		 1176 t0 = tcg_temp_new_i64();
1177 t1 = tcg_temp_new_i64();
74637406
AJ		 1178#if defined(TARGET_PPC64)
1179 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1183#else
1184 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1185 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1186 tcg_gen_mul_i64(t0, t0, t1);
1187 tcg_gen_shri_i64(t0, t0, 32);
1188 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1189#endif
a7812ae4
PB		 1190 tcg_temp_free_i64(t0);
1191 tcg_temp_free_i64(t1);
74637406
AJ		 1192 if (unlikely(Rc(ctx->opcode) != 0))
1193 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1194}
74637406
AJ		 1195/* mulhwu mulhwu. */
1196GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1197{
a7812ae4 1198 TCGv_i64 t0, t1;
74637406 1199
a7812ae4
PB		 1200 t0 = tcg_temp_new_i64();
1201 t1 = tcg_temp_new_i64();
d9bce9d9 1202#if defined(TARGET_PPC64)
74637406
AJ		 1203 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1207#else
1208 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1209 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1210 tcg_gen_mul_i64(t0, t0, t1);
1211 tcg_gen_shri_i64(t0, t0, 32);
1212 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1213#endif
a7812ae4
PB		 1214 tcg_temp_free_i64(t0);
1215 tcg_temp_free_i64(t1);
74637406
AJ		 1216 if (unlikely(Rc(ctx->opcode) != 0))
1217 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1218}
74637406
AJ		 1219/* mullw mullw. */
1220GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1221{
74637406
AJ		 1222 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1223 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1224 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1227}
74637406
AJ		 1228/* mullwo mullwo. */
1229GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1230{
74637406 1231 int l1;
a7812ae4 1232 TCGv_i64 t0, t1;
74637406 1233
a7812ae4
PB		 1234 t0 = tcg_temp_new_i64();
1235 t1 = tcg_temp_new_i64();
74637406
AJ		 1236 l1 = gen_new_label();
1237 /* Start with XER OV disabled, the most likely case */
1238 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1239#if defined(TARGET_PPC64)
1240 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1241 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1242#else
1243 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1244 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1245#endif
74637406
AJ		 1246 tcg_gen_mul_i64(t0, t0, t1);
1247#if defined(TARGET_PPC64)
1248 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1249 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1250#else
1251 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1252 tcg_gen_ext32s_i64(t1, t0);
1253 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1254#endif
1255 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1256 gen_set_label(l1);
a7812ae4
PB		 1257 tcg_temp_free_i64(t0);
1258 tcg_temp_free_i64(t1);
74637406
AJ		 1259 if (unlikely(Rc(ctx->opcode) != 0))
1260 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1261}
74637406
AJ		 1262/* mulli */
1263GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1264{
74637406
AJ		 1265 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1266 SIMM(ctx->opcode));
d9bce9d9
JM		 1267}
1268#if defined(TARGET_PPC64)
74637406
AJ		 1269#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1270GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1271{ \
a7812ae4 1272 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1274 if (unlikely(Rc(ctx->opcode) != 0)) \
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1276}
74637406
AJ		 1277/* mulhd mulhd. */
1278GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1279/* mulhdu mulhdu. */
1280GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1281/* mulld mulld. */
1282GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1283{
74637406
AJ		 1284 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1285 cpu_gpr[rB(ctx->opcode)]);
1286 if (unlikely(Rc(ctx->opcode) != 0))
1287 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1288}
74637406
AJ		 1289/* mulldo mulldo. */
1290GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1291#endif
74637406
AJ		 1292
1293/* neg neg. nego nego. */
ec6469a3 1294static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1295{
ec6469a3
AJ		 1296 int l1 = gen_new_label();
1297 int l2 = gen_new_label();
a7812ae4 1298 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1299#if defined(TARGET_PPC64)
74637406 1300 if (ctx->sf_mode) {
741a7444 1301 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1303 } else
1304#endif
1305 {
1306 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1307 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1308 }
74637406
AJ		 1309 tcg_gen_neg_tl(ret, arg1);
1310 if (ov_check) {
1311 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1312 }
1313 tcg_gen_br(l2);
1314 gen_set_label(l1);
ec6469a3 1315 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1316 if (ov_check) {
1317 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1318 }
1319 gen_set_label(l2);
ec6469a3 1320 tcg_temp_free(t0);
74637406
AJ		 1321 if (unlikely(Rc(ctx->opcode) != 0))
1322 gen_set_Rc0(ctx, ret);
1323}
1324GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1325{
ec6469a3 1326 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1327}
74637406 1328GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1329{
ec6469a3 1330 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1331}
74637406
AJ		 1332
1333/* Common subf function */
1334static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1335 int add_ca, int compute_ca, int compute_ov)
79aceca5 1336{
74637406 1337 TCGv t0, t1;
76a66253 1338
74637406 1339 if ((!compute_ca && !compute_ov) ||
a7812ae4 1340 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1341 t0 = ret;
e864cabd 1342 } else {
a7812ae4 1343 t0 = tcg_temp_local_new();
d9bce9d9 1344 }
76a66253 1345
74637406 1346 if (add_ca) {
a7812ae4 1347 t1 = tcg_temp_local_new();
74637406
AJ		 1348 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1349 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1350 }
79aceca5 1351
74637406
AJ		 1352 if (compute_ca && compute_ov) {
1353 /* Start with XER CA and OV disabled, the most likely case */
1354 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1355 } else if (compute_ca) {
1356 /* Start with XER CA disabled, the most likely case */
1357 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1358 } else if (compute_ov) {
1359 /* Start with XER OV disabled, the most likely case */
1360 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1361 }
1362
1363 if (add_ca) {
1364 tcg_gen_not_tl(t0, arg1);
1365 tcg_gen_add_tl(t0, t0, arg2);
1366 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1367 tcg_gen_add_tl(t0, t0, t1);
1368 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1369 tcg_temp_free(t1);
79aceca5 1370 } else {
74637406
AJ		 1371 tcg_gen_sub_tl(t0, arg2, arg1);
1372 if (compute_ca) {
1373 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1374 }
1375 }
1376 if (compute_ov) {
1377 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1378 }
1379
1380 if (unlikely(Rc(ctx->opcode) != 0))
1381 gen_set_Rc0(ctx, t0);
1382
a7812ae4 1383 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1384 tcg_gen_mov_tl(ret, t0);
1385 tcg_temp_free(t0);
79aceca5 1386 }
79aceca5 1387}
74637406
AJ		 1388/* Sub functions with Two operands functions */
1389#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1390GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1391{ \
1392 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1393 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1394 add_ca, compute_ca, compute_ov); \
1395}
1396/* Sub functions with one operand and one immediate */
1397#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1398 add_ca, compute_ca, compute_ov) \
1399GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1400{ \
1401 TCGv t0 = tcg_const_local_tl(const_val); \
1402 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1403 cpu_gpr[rA(ctx->opcode)], t0, \
1404 add_ca, compute_ca, compute_ov); \
1405 tcg_temp_free(t0); \
1406}
1407/* subf subf. subfo subfo. */
1408GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1409GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1410/* subfc subfc. subfco subfco. */
1411GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1412GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1413/* subfe subfe. subfeo subfo. */
1414GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1415GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1416/* subfme subfme. subfmeo subfmeo. */
1417GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1418GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1419/* subfze subfze. subfzeo subfzeo.*/
1420GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1421GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1422/* subfic */
1423GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1424{
74637406
AJ		 1425 /* Start with XER CA and OV disabled, the most likely case */
1426 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1427 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1428 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1429 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1430 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1431 tcg_temp_free(t1);
1432 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1433 tcg_temp_free(t0);
79aceca5
FB		 1434}
1435
79aceca5 1436/*** Integer logical ***/
26d67362
AJ		 1437#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1438GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1439{ \
26d67362
AJ		 1440 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1441 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1442 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1443 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1444}
79aceca5 1445
26d67362 1446#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1447GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1448{ \
26d67362 1449 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1450 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1451 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1452}
1453
1454/* and & and. */
26d67362 1455GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1456/* andc & andc. */
26d67362 1457GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1458/* andi. */
c7697e1f 1459GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1460{
26d67362
AJ		 1461 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1463}
1464/* andis. */
c7697e1f 1465GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1466{
26d67362
AJ		 1467 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1469}
79aceca5 1470/* cntlzw */
26d67362
AJ		 1471GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1472{
a7812ae4 1473 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1474 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1475 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1476}
79aceca5 1477/* eqv & eqv. */
26d67362 1478GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1479/* extsb & extsb. */
26d67362 1480GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1481/* extsh & extsh. */
26d67362 1482GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1483/* nand & nand. */
26d67362 1484GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1485/* nor & nor. */
26d67362 1486GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1487/* or & or. */
9a64fbe4
FB		 1488GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1489{
76a66253
JM		 1490 int rs, ra, rb;
1491
1492 rs = rS(ctx->opcode);
1493 ra = rA(ctx->opcode);
1494 rb = rB(ctx->opcode);
1495 /* Optimisation for mr. ri case */
1496 if (rs != ra || rs != rb) {
26d67362
AJ		 1497 if (rs != rb)
1498 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1499 else
1500 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1501 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1502 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1503 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1504 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1505#if defined(TARGET_PPC64)
1506 } else {
26d67362
AJ		 1507 int prio = 0;
1508
c80f84e3
JM		 1509 switch (rs) {
1510 case 1:
1511 /* Set process priority to low */
26d67362 1512 prio = 2;
c80f84e3
JM		 1513 break;
1514 case 6:
1515 /* Set process priority to medium-low */
26d67362 1516 prio = 3;
c80f84e3
JM		 1517 break;
1518 case 2:
1519 /* Set process priority to normal */
26d67362 1520 prio = 4;
c80f84e3 1521 break;
be147d08
JM		 1522#if !defined(CONFIG_USER_ONLY)
1523 case 31:
76db3ba4 1524 if (ctx->mem_idx > 0) {
be147d08 1525 /* Set process priority to very low */
26d67362 1526 prio = 1;
be147d08
JM		 1527 }
1528 break;
1529 case 5:
76db3ba4 1530 if (ctx->mem_idx > 0) {
be147d08 1531 /* Set process priority to medium-hight */
26d67362 1532 prio = 5;
be147d08
JM		 1533 }
1534 break;
1535 case 3:
76db3ba4 1536 if (ctx->mem_idx > 0) {
be147d08 1537 /* Set process priority to high */
26d67362 1538 prio = 6;
be147d08
JM		 1539 }
1540 break;
be147d08 1541 case 7:
76db3ba4 1542 if (ctx->mem_idx > 1) {
be147d08 1543 /* Set process priority to very high */
26d67362 1544 prio = 7;
be147d08
JM		 1545 }
1546 break;
be147d08 1547#endif
c80f84e3
JM		 1548 default:
1549 /* nop */
1550 break;
1551 }
26d67362 1552 if (prio) {
a7812ae4 1553 TCGv t0 = tcg_temp_new();
54cdcae6 1554 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1555 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1556 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1557 gen_store_spr(SPR_PPR, t0);
ea363694 1558 tcg_temp_free(t0);
26d67362 1559 }
c80f84e3 1560#endif
9a64fbe4 1561 }
9a64fbe4 1562}
79aceca5 1563/* orc & orc. */
26d67362 1564GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1565/* xor & xor. */
9a64fbe4
FB		 1566GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1567{
9a64fbe4 1568 /* Optimisation for "set to zero" case */
26d67362 1569 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1570 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1571 else
1572 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1573 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1575}
79aceca5
FB		 1576/* ori */
1577GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1578{
76a66253 1579 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1580
9a64fbe4
FB		 1581 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1582 /* NOP */
76a66253 1583 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1584 return;
76a66253 1585 }
26d67362 1586 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1587}
1588/* oris */
1589GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1590{
76a66253 1591 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1592
9a64fbe4
FB		 1593 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1594 /* NOP */
1595 return;
76a66253 1596 }
26d67362 1597 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1598}
1599/* xori */
1600GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1601{
76a66253 1602 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1603
1604 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1605 /* NOP */
1606 return;
1607 }
26d67362 1608 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1609}
79aceca5
FB		 1610/* xoris */
1611GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1612{
76a66253 1613 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1614
1615 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1616 /* NOP */
1617 return;
1618 }
26d67362 1619 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1620}
d9bce9d9 1621/* popcntb : PowerPC 2.03 specification */
05332d70 1622GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1623{
d9bce9d9
JM		 1624#if defined(TARGET_PPC64)
1625 if (ctx->sf_mode)
a7812ae4 1626 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1627 else
1628#endif
a7812ae4 1629 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1630}
1631
1632#if defined(TARGET_PPC64)
1633/* extsw & extsw. */
26d67362 1634GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1635/* cntlzd */
26d67362
AJ		 1636GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1637{
a7812ae4 1638 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1639 if (unlikely(Rc(ctx->opcode) != 0))
1640 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1641}
d9bce9d9
JM		 1642#endif
1643
79aceca5
FB		 1644/*** Integer rotate ***/
1645/* rlwimi & rlwimi. */
1646GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1647{
76a66253 1648 uint32_t mb, me, sh;
79aceca5
FB		 1649
1650 mb = MB(ctx->opcode);
1651 me = ME(ctx->opcode);
76a66253 1652 sh = SH(ctx->opcode);
d03ef511
AJ		 1653 if (likely(sh == 0 && mb == 0 && me == 31)) {
1654 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1655 } else {
d03ef511 1656 target_ulong mask;
a7812ae4
PB		 1657 TCGv t1;
1658 TCGv t0 = tcg_temp_new();
54843a58 1659#if defined(TARGET_PPC64)
a7812ae4
PB		 1660 TCGv_i32 t2 = tcg_temp_new_i32();
1661 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1662 tcg_gen_rotli_i32(t2, t2, sh);
1663 tcg_gen_extu_i32_i64(t0, t2);
1664 tcg_temp_free_i32(t2);
54843a58
AJ		 1665#else
1666 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1667#endif
76a66253 1668#if defined(TARGET_PPC64)
d03ef511
AJ		 1669 mb += 32;
1670 me += 32;
76a66253 1671#endif
d03ef511 1672 mask = MASK(mb, me);
a7812ae4 1673 t1 = tcg_temp_new();
d03ef511
AJ		 1674 tcg_gen_andi_tl(t0, t0, mask);
1675 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1676 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1677 tcg_temp_free(t0);
1678 tcg_temp_free(t1);
1679 }
76a66253 1680 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1681 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1682}
1683/* rlwinm & rlwinm. */
1684GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1685{
1686 uint32_t mb, me, sh;
3b46e624 1687
79aceca5
FB		 1688 sh = SH(ctx->opcode);
1689 mb = MB(ctx->opcode);
1690 me = ME(ctx->opcode);
d03ef511
AJ		 1691
1692 if (likely(mb == 0 && me == (31 - sh))) {
1693 if (likely(sh == 0)) {
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1695 } else {
a7812ae4 1696 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1697 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1698 tcg_gen_shli_tl(t0, t0, sh);
1699 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1700 tcg_temp_free(t0);
79aceca5 1701 }
d03ef511 1702 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1703 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1704 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1705 tcg_gen_shri_tl(t0, t0, mb);
1706 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1707 tcg_temp_free(t0);
1708 } else {
a7812ae4 1709 TCGv t0 = tcg_temp_new();
54843a58 1710#if defined(TARGET_PPC64)
a7812ae4 1711 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1712 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1713 tcg_gen_rotli_i32(t1, t1, sh);
1714 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1715 tcg_temp_free_i32(t1);
54843a58
AJ		 1716#else
1717 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1718#endif
76a66253 1719#if defined(TARGET_PPC64)
d03ef511
AJ		 1720 mb += 32;
1721 me += 32;
76a66253 1722#endif
d03ef511
AJ		 1723 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1724 tcg_temp_free(t0);
1725 }
76a66253 1726 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1727 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1728}
1729/* rlwnm & rlwnm. */
1730GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1731{
1732 uint32_t mb, me;
54843a58
AJ		 1733 TCGv t0;
1734#if defined(TARGET_PPC64)
a7812ae4 1735 TCGv_i32 t1, t2;
54843a58 1736#endif
79aceca5
FB		 1737
1738 mb = MB(ctx->opcode);
1739 me = ME(ctx->opcode);
a7812ae4 1740 t0 = tcg_temp_new();
d03ef511 1741 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1742#if defined(TARGET_PPC64)
a7812ae4
PB		 1743 t1 = tcg_temp_new_i32();
1744 t2 = tcg_temp_new_i32();
54843a58
AJ		 1745 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1746 tcg_gen_trunc_i64_i32(t2, t0);
1747 tcg_gen_rotl_i32(t1, t1, t2);
1748 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1749 tcg_temp_free_i32(t1);
1750 tcg_temp_free_i32(t2);
54843a58
AJ		 1751#else
1752 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1753#endif
76a66253
JM		 1754 if (unlikely(mb != 0 || me != 31)) {
1755#if defined(TARGET_PPC64)
1756 mb += 32;
1757 me += 32;
1758#endif
54843a58 1759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1760 } else {
54843a58 1761 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1762 }
54843a58 1763 tcg_temp_free(t0);
76a66253 1764 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1765 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1766}
1767
d9bce9d9
JM		 1768#if defined(TARGET_PPC64)
1769#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1770GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1771{ \
1772 gen_##name(ctx, 0); \
1773} \
c7697e1f
JM		 1774GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1775 PPC_64B) \
d9bce9d9
JM		 1776{ \
1777 gen_##name(ctx, 1); \
1778}
1779#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1780GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1781{ \
1782 gen_##name(ctx, 0, 0); \
1783} \
c7697e1f
JM		 1784GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1785 PPC_64B) \
d9bce9d9
JM		 1786{ \
1787 gen_##name(ctx, 0, 1); \
1788} \
c7697e1f
JM		 1789GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1790 PPC_64B) \
d9bce9d9
JM		 1791{ \
1792 gen_##name(ctx, 1, 0); \
1793} \
c7697e1f
JM		 1794GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1795 PPC_64B) \
d9bce9d9
JM		 1796{ \
1797 gen_##name(ctx, 1, 1); \
1798}
51789c41 1799
b068d6a7
JM		 1800static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1801 uint32_t me, uint32_t sh)
51789c41 1802{
d03ef511
AJ		 1803 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1804 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1805 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1806 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1807 } else {
a7812ae4 1808 TCGv t0 = tcg_temp_new();
54843a58 1809 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1810 if (likely(mb == 0 && me == 63)) {
54843a58 1811 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1812 } else {
1813 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1814 }
d03ef511 1815 tcg_temp_free(t0);
51789c41 1816 }
51789c41 1817 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1819}
d9bce9d9 1820/* rldicl - rldicl. */
b068d6a7 1821static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1822{
51789c41 1823 uint32_t sh, mb;
d9bce9d9 1824
9d53c753
JM		 1825 sh = SH(ctx->opcode) | (shn << 5);
1826 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1827 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1828}
51789c41 1829GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1830/* rldicr - rldicr. */
b068d6a7 1831static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1832{
51789c41 1833 uint32_t sh, me;
d9bce9d9 1834
9d53c753
JM		 1835 sh = SH(ctx->opcode) | (shn << 5);
1836 me = MB(ctx->opcode) | (men << 5);
51789c41 1837 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1838}
51789c41 1839GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1840/* rldic - rldic. */
b068d6a7 1841static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1842{
51789c41 1843 uint32_t sh, mb;
d9bce9d9 1844
9d53c753
JM		 1845 sh = SH(ctx->opcode) | (shn << 5);
1846 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1847 gen_rldinm(ctx, mb, 63 - sh, sh);
1848}
1849GEN_PPC64_R4(rldic, 0x1E, 0x04);
1850
b068d6a7
JM		 1851static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1852 uint32_t me)
51789c41 1853{
54843a58 1854 TCGv t0;
d03ef511
AJ		 1855
1856 mb = MB(ctx->opcode);
1857 me = ME(ctx->opcode);
a7812ae4 1858 t0 = tcg_temp_new();
d03ef511 1859 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1860 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1861 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1862 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1863 } else {
1864 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1865 }
1866 tcg_temp_free(t0);
51789c41 1867 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1869}
51789c41 1870
d9bce9d9 1871/* rldcl - rldcl. */
b068d6a7 1872static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1873{
51789c41 1874 uint32_t mb;
d9bce9d9 1875
9d53c753 1876 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1877 gen_rldnm(ctx, mb, 63);
d9bce9d9 1878}
36081602 1879GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1880/* rldcr - rldcr. */
b068d6a7 1881static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1882{
51789c41 1883 uint32_t me;
d9bce9d9 1884
9d53c753 1885 me = MB(ctx->opcode) | (men << 5);
51789c41 1886 gen_rldnm(ctx, 0, me);
d9bce9d9 1887}
36081602 1888GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1889/* rldimi - rldimi. */
b068d6a7 1890static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1891{
271a916e 1892 uint32_t sh, mb, me;
d9bce9d9 1893
9d53c753
JM		 1894 sh = SH(ctx->opcode) | (shn << 5);
1895 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1896 me = 63 - sh;
d03ef511
AJ		 1897 if (unlikely(sh == 0 && mb == 0)) {
1898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1899 } else {
1900 TCGv t0, t1;
1901 target_ulong mask;
1902
a7812ae4 1903 t0 = tcg_temp_new();
54843a58 1904 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1905 t1 = tcg_temp_new();
d03ef511
AJ		 1906 mask = MASK(mb, me);
1907 tcg_gen_andi_tl(t0, t0, mask);
1908 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1909 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1910 tcg_temp_free(t0);
1911 tcg_temp_free(t1);
51789c41 1912 }
51789c41 1913 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1915}
36081602 1916GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1917#endif
1918
79aceca5
FB		 1919/*** Integer shift ***/
1920/* slw & slw. */
26d67362
AJ		 1921GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1922{
fea0c503 1923 TCGv t0;
26d67362
AJ		 1924 int l1, l2;
1925 l1 = gen_new_label();
1926 l2 = gen_new_label();
1927
a7812ae4 1928 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1929 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1930 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1931 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1932 tcg_gen_br(l2);
1933 gen_set_label(l1);
fea0c503 1934 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1935 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1936 gen_set_label(l2);
fea0c503 1937 tcg_temp_free(t0);
26d67362
AJ		 1938 if (unlikely(Rc(ctx->opcode) != 0))
1939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1940}
79aceca5 1941/* sraw & sraw. */
26d67362
AJ		 1942GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1943{
a7812ae4
PB		 1944 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1945 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1946 if (unlikely(Rc(ctx->opcode) != 0))
1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1948}
79aceca5
FB		 1949/* srawi & srawi. */
1950GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1951{
26d67362
AJ		 1952 int sh = SH(ctx->opcode);
1953 if (sh != 0) {
1954 int l1, l2;
fea0c503 1955 TCGv t0;
26d67362
AJ		 1956 l1 = gen_new_label();
1957 l2 = gen_new_label();
a7812ae4 1958 t0 = tcg_temp_local_new();
fea0c503
AJ		 1959 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1960 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1961 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1962 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1963 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1964 tcg_gen_br(l2);
1965 gen_set_label(l1);
269f3e95 1966 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1967 gen_set_label(l2);
fea0c503
AJ		 1968 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1969 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1970 tcg_temp_free(t0);
26d67362
AJ		 1971 } else {
1972 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1973 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1974 }
76a66253 1975 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1977}
1978/* srw & srw. */
26d67362
AJ		 1979GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1980{
fea0c503 1981 TCGv t0, t1;
26d67362
AJ		 1982 int l1, l2;
1983 l1 = gen_new_label();
1984 l2 = gen_new_label();
d9bce9d9 1985
a7812ae4 1986 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1987 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1988 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1989 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1990 tcg_gen_br(l2);
1991 gen_set_label(l1);
a7812ae4 1992 t1 = tcg_temp_new();
fea0c503
AJ		 1993 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1994 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1995 tcg_temp_free(t1);
26d67362 1996 gen_set_label(l2);
fea0c503 1997 tcg_temp_free(t0);
26d67362
AJ		 1998 if (unlikely(Rc(ctx->opcode) != 0))
1999 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2000}
d9bce9d9
JM		 2001#if defined(TARGET_PPC64)
2002/* sld & sld. */
26d67362
AJ		 2003GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2004{
fea0c503 2005 TCGv t0;
26d67362
AJ		 2006 int l1, l2;
2007 l1 = gen_new_label();
2008 l2 = gen_new_label();
2009
a7812ae4 2010 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2011 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2012 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2013 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2014 tcg_gen_br(l2);
2015 gen_set_label(l1);
fea0c503 2016 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2017 gen_set_label(l2);
fea0c503 2018 tcg_temp_free(t0);
26d67362
AJ		 2019 if (unlikely(Rc(ctx->opcode) != 0))
2020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2021}
d9bce9d9 2022/* srad & srad. */
26d67362
AJ		 2023GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2024{
a7812ae4
PB		 2025 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2026 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029}
d9bce9d9 2030/* sradi & sradi. */
b068d6a7 2031static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2032{
26d67362 2033 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2034 if (sh != 0) {
26d67362 2035 int l1, l2;
fea0c503 2036 TCGv t0;
26d67362
AJ		 2037 l1 = gen_new_label();
2038 l2 = gen_new_label();
a7812ae4 2039 t0 = tcg_temp_local_new();
26d67362 2040 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2041 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2042 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2043 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2044 tcg_gen_br(l2);
2045 gen_set_label(l1);
269f3e95 2046 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2047 gen_set_label(l2);
a9730017 2048 tcg_temp_free(t0);
26d67362
AJ		 2049 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2050 } else {
2051 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2052 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2053 }
d9bce9d9 2054 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2056}
c7697e1f 2057GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2058{
2059 gen_sradi(ctx, 0);
2060}
c7697e1f 2061GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2062{
2063 gen_sradi(ctx, 1);
2064}
2065/* srd & srd. */
26d67362
AJ		 2066GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2067{
fea0c503 2068 TCGv t0;
26d67362
AJ		 2069 int l1, l2;
2070 l1 = gen_new_label();
2071 l2 = gen_new_label();
2072
a7812ae4 2073 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2074 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2075 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2076 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2077 tcg_gen_br(l2);
2078 gen_set_label(l1);
fea0c503 2079 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2080 gen_set_label(l2);
fea0c503 2081 tcg_temp_free(t0);
26d67362
AJ		 2082 if (unlikely(Rc(ctx->opcode) != 0))
2083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2084}
d9bce9d9 2085#endif
79aceca5
FB		 2086
2087/*** Floating-Point arithmetic ***/
7c58044c 2088#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2089GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2090{ \
76a66253 2091 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2092 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2093 return; \
2094 } \
eb44b959
AJ		 2095 /* NIP cannot be restored if the memory exception comes from an helper */ \
2096 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2097 gen_reset_fpstatus(); \
af12906f
AJ		 2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2100 if (isfloat) { \
af12906f 2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2102 } \
af12906f
AJ		 2103 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2104 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2105}
2106
7c58044c
JM		 2107#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2108_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2109_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2110
7c58044c
JM		 2111#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2112GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2113{ \
76a66253 2114 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2115 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2116 return; \
2117 } \
eb44b959
AJ		 2118 /* NIP cannot be restored if the memory exception comes from an helper */ \
2119 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2120 gen_reset_fpstatus(); \
af12906f
AJ		 2121 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2122 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2123 if (isfloat) { \
af12906f 2124 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2125 } \
af12906f
AJ		 2126 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2127 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2128}
7c58044c
JM		 2129#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2130_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2131_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2132
7c58044c
JM		 2133#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2134GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2135{ \
76a66253 2136 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2137 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2138 return; \
2139 } \
eb44b959
AJ		 2140 /* NIP cannot be restored if the memory exception comes from an helper */ \
2141 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2142 gen_reset_fpstatus(); \
af12906f
AJ		 2143 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2144 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2145 if (isfloat) { \
af12906f 2146 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2147 } \
af12906f
AJ		 2148 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2149 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2150}
7c58044c
JM		 2151#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2152_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2153_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2154
7c58044c 2155#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2156GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2157{ \
76a66253 2158 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2159 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2160 return; \
2161 } \
eb44b959
AJ		 2162 /* NIP cannot be restored if the memory exception comes from an helper */ \
2163 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2164 gen_reset_fpstatus(); \
af12906f
AJ		 2165 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2167 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2168}
2169
7c58044c 2170#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2171GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2172{ \
76a66253 2173 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2174 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2175 return; \
2176 } \
eb44b959
AJ		 2177 /* NIP cannot be restored if the memory exception comes from an helper */ \
2178 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2179 gen_reset_fpstatus(); \
af12906f
AJ		 2180 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2181 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2182 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2183}
2184
9a64fbe4 2185/* fadd - fadds */
7c58044c 2186GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2187/* fdiv - fdivs */
7c58044c 2188GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2189/* fmul - fmuls */
7c58044c 2190GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2191
d7e4b87e 2192/* fre */
7c58044c 2193GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2194
a750fc0b 2195/* fres */
7c58044c 2196GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2197
a750fc0b 2198/* frsqrte */
7c58044c
JM		 2199GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2200
2201/* frsqrtes */
af12906f 2202GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2203{
af12906f 2204 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2205 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2206 return;
2207 }
eb44b959
AJ		 2208 /* NIP cannot be restored if the memory exception comes from an helper */
2209 gen_update_nip(ctx, ctx->nip - 4);
af12906f
AJ		 2210 gen_reset_fpstatus();
2211 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2212 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2214}
79aceca5 2215
a750fc0b 2216/* fsel */
7c58044c 2217_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2218/* fsub - fsubs */
7c58044c 2219GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2220/* Optional: */
2221/* fsqrt */
a750fc0b 2222GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2223{
76a66253 2224 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2225 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2226 return;
2227 }
eb44b959
AJ		 2228 /* NIP cannot be restored if the memory exception comes from an helper */
2229 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2230 gen_reset_fpstatus();
af12906f
AJ		 2231 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2233}
79aceca5 2234
a750fc0b 2235GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2236{
76a66253 2237 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2238 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2239 return;
2240 }
eb44b959
AJ		 2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2243 gen_reset_fpstatus();
af12906f
AJ		 2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2245 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2247}
2248
2249/*** Floating-Point multiply-and-add ***/
4ecc3190 2250/* fmadd - fmadds */
7c58044c 2251GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2252/* fmsub - fmsubs */
7c58044c 2253GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2254/* fnmadd - fnmadds */
7c58044c 2255GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2256/* fnmsub - fnmsubs */
7c58044c 2257GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2258
2259/*** Floating-Point round & convert ***/
2260/* fctiw */
7c58044c 2261GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2262/* fctiwz */
7c58044c 2263GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2264/* frsp */
7c58044c 2265GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2266#if defined(TARGET_PPC64)
2267/* fcfid */
7c58044c 2268GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2269/* fctid */
7c58044c 2270GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2271/* fctidz */
7c58044c 2272GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2273#endif
79aceca5 2274
d7e4b87e 2275/* frin */
7c58044c 2276GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2277/* friz */
7c58044c 2278GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2279/* frip */
7c58044c 2280GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2281/* frim */
7c58044c 2282GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2283
79aceca5
FB		 2284/*** Floating-Point compare ***/
2285/* fcmpo */
76a66253 2286GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2287{
330c483b 2288 TCGv_i32 crf;
76a66253 2289 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2290 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2291 return;
2292 }
eb44b959
AJ		 2293 /* NIP cannot be restored if the memory exception comes from an helper */
2294 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2295 gen_reset_fpstatus();
9a819377
AJ		 2296 crf = tcg_const_i32(crfD(ctx->opcode));
2297 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2298 tcg_temp_free_i32(crf);
af12906f 2299 gen_helper_float_check_status();
79aceca5
FB		 2300}
2301
2302/* fcmpu */
76a66253 2303GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2304{
330c483b 2305 TCGv_i32 crf;
76a66253 2306 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2307 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2308 return;
2309 }
eb44b959
AJ		 2310 /* NIP cannot be restored if the memory exception comes from an helper */
2311 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2312 gen_reset_fpstatus();
9a819377
AJ		 2313 crf = tcg_const_i32(crfD(ctx->opcode));
2314 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2315 tcg_temp_free_i32(crf);
af12906f 2316 gen_helper_float_check_status();
79aceca5
FB		 2317}
2318
9a64fbe4
FB		 2319/*** Floating-point move ***/
2320/* fabs */
7c58044c
JM		 2321/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2322GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2323
2324/* fmr - fmr. */
7c58044c 2325/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2326GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2327{
76a66253 2328 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2329 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2330 return;
2331 }
af12906f
AJ		 2332 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2333 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2334}
2335
2336/* fnabs */
7c58044c
JM		 2337/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2338GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2339/* fneg */
7c58044c
JM		 2340/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2341GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2342
79aceca5
FB		 2343/*** Floating-Point status & ctrl register ***/
2344/* mcrfs */
2345GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2346{
7c58044c
JM		 2347 int bfa;
2348
76a66253 2349 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2350 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2351 return;
2352 }
7c58044c 2353 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2354 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2355 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2356 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2357}
2358
2359/* mffs */
2360GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2361{
76a66253 2362 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2363 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2364 return;
2365 }
7c58044c 2366 gen_reset_fpstatus();
af12906f
AJ		 2367 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2368 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2369}
2370
2371/* mtfsb0 */
2372GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2373{
fb0eaffc 2374 uint8_t crb;
3b46e624 2375
76a66253 2376 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2377 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2378 return;
2379 }
6e35d524 2380 crb = 31 - crbD(ctx->opcode);
7c58044c 2381 gen_reset_fpstatus();
6e35d524 2382 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2383 TCGv_i32 t0;
2384 /* NIP cannot be restored if the memory exception comes from an helper */
2385 gen_update_nip(ctx, ctx->nip - 4);
2386 t0 = tcg_const_i32(crb);
6e35d524
AJ		 2387 gen_helper_fpscr_clrbit(t0);
2388 tcg_temp_free_i32(t0);
2389 }
7c58044c 2390 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2391 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2392 }
79aceca5
FB		 2393}
2394
2395/* mtfsb1 */
2396GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2397{
fb0eaffc 2398 uint8_t crb;
3b46e624 2399
76a66253 2400 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2401 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2402 return;
2403 }
6e35d524 2404 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2405 gen_reset_fpstatus();
2406 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2407 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2408 TCGv_i32 t0;
2409 /* NIP cannot be restored if the memory exception comes from an helper */
2410 gen_update_nip(ctx, ctx->nip - 4);
2411 t0 = tcg_const_i32(crb);
af12906f 2412 gen_helper_fpscr_setbit(t0);
0f2f39c2 2413 tcg_temp_free_i32(t0);
af12906f 2414 }
7c58044c 2415 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2416 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2417 }
2418 /* We can raise a differed exception */
af12906f 2419 gen_helper_float_check_status();
79aceca5
FB		 2420}
2421
2422/* mtfsf */
2423GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2424{
0f2f39c2 2425 TCGv_i32 t0;
af12906f 2426
76a66253 2427 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2428 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2429 return;
2430 }
eb44b959
AJ		 2431 /* NIP cannot be restored if the memory exception comes from an helper */
2432 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2433 gen_reset_fpstatus();
af12906f
AJ		 2434 t0 = tcg_const_i32(FM(ctx->opcode));
2435 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2436 tcg_temp_free_i32(t0);
7c58044c 2437 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2438 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2439 }
2440 /* We can raise a differed exception */
af12906f 2441 gen_helper_float_check_status();
79aceca5
FB		 2442}
2443
2444/* mtfsfi */
2445GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2446{
7c58044c 2447 int bf, sh;
0f2f39c2
AJ		 2448 TCGv_i64 t0;
2449 TCGv_i32 t1;
7c58044c 2450
76a66253 2451 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2452 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2453 return;
2454 }
7c58044c
JM		 2455 bf = crbD(ctx->opcode) >> 2;
2456 sh = 7 - bf;
eb44b959
AJ		 2457 /* NIP cannot be restored if the memory exception comes from an helper */
2458 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2459 gen_reset_fpstatus();
0f2f39c2 2460 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2461 t1 = tcg_const_i32(1 << sh);
2462 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2463 tcg_temp_free_i64(t0);
2464 tcg_temp_free_i32(t1);
7c58044c 2465 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2466 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2467 }
2468 /* We can raise a differed exception */
af12906f 2469 gen_helper_float_check_status();
79aceca5
FB		 2470}
2471
76a66253
JM		 2472/*** Addressing modes ***/
2473/* Register indirect with immediate index : EA = (rA|0) + SIMM */
76db3ba4 2474static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
76a66253
JM		 2475{
2476 target_long simm = SIMM(ctx->opcode);
2477
be147d08 2478 simm &= ~maskl;
76db3ba4
AJ		 2479 if (rA(ctx->opcode) == 0) {
2480#if defined(TARGET_PPC64)
2481 if (!ctx->sf_mode) {
2482 tcg_gen_movi_tl(EA, (uint32_t)simm);
2483 } else
2484#endif
e2be8d8d 2485 tcg_gen_movi_tl(EA, simm);
76db3ba4 2486 } else if (likely(simm != 0)) {
e2be8d8d 2487 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
76db3ba4
AJ		 2488#if defined(TARGET_PPC64)
2489 if (!ctx->sf_mode) {
2490 tcg_gen_ext32u_tl(EA, EA);
2491 }
2492#endif
2493 } else {
2494#if defined(TARGET_PPC64)
2495 if (!ctx->sf_mode) {
2496 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2497 } else
2498#endif
e2be8d8d 2499 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2500 }
76a66253
JM		 2501}
2502
76db3ba4 2503static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
76a66253 2504{
76db3ba4
AJ		 2505 if (rA(ctx->opcode) == 0) {
2506#if defined(TARGET_PPC64)
2507 if (!ctx->sf_mode) {
2508 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2509 } else
2510#endif
e2be8d8d 2511 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
76db3ba4 2512 } else {
e2be8d8d 2513 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76db3ba4
AJ		 2514#if defined(TARGET_PPC64)
2515 if (!ctx->sf_mode) {
2516 tcg_gen_ext32u_tl(EA, EA);
2517 }
2518#endif
2519 }
76a66253
JM		 2520}
2521
76db3ba4 2522static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
76a66253 2523{
76db3ba4 2524 if (rA(ctx->opcode) == 0) {
e2be8d8d 2525 tcg_gen_movi_tl(EA, 0);
76db3ba4
AJ		 2526 } else {
2527#if defined(TARGET_PPC64)
2528 if (!ctx->sf_mode) {
2529 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2530 } else
2531#endif
2532 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2533 }
2534}
2535
2536static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2537{
2538 tcg_gen_addi_tl(ret, arg1, val);
2539#if defined(TARGET_PPC64)
2540 if (!ctx->sf_mode) {
2541 tcg_gen_ext32u_tl(ret, ret);
2542 }
2543#endif
76a66253
JM		 2544}
2545
cf360a32
AJ		 2546static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2547{
2548 int l1 = gen_new_label();
2549 TCGv t0 = tcg_temp_new();
2550 TCGv_i32 t1, t2;
2551 /* NIP cannot be restored if the memory exception comes from an helper */
2552 gen_update_nip(ctx, ctx->nip - 4);
2553 tcg_gen_andi_tl(t0, EA, mask);
2554 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2555 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2556 t2 = tcg_const_i32(0);
2557 gen_helper_raise_exception_err(t1, t2);
2558 tcg_temp_free_i32(t1);
2559 tcg_temp_free_i32(t2);
2560 gen_set_label(l1);
2561 tcg_temp_free(t0);
2562}
2563
7863667f 2564/*** Integer load ***/
76db3ba4
AJ		 2565static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2566{
2567 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2568}
2569
2570static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2571{
2572 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2573}
2574
2575static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2576{
2577 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2578 if (unlikely(ctx->le_mode)) {
b61f2753 2579#if defined(TARGET_PPC64)
76db3ba4
AJ		 2580 TCGv_i32 t0 = tcg_temp_new_i32();
2581 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2582 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2583 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2584 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2585#else
2586 tcg_gen_bswap16_i32(arg1, arg1);
2587#endif
2588 }
b61f2753
AJ		 2589}
2590
76db3ba4 2591static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2592{
76db3ba4
AJ		 2593 if (unlikely(ctx->le_mode)) {
2594#if defined(TARGET_PPC64)
a7812ae4 2595 TCGv_i32 t0;
76db3ba4 2596 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
a7812ae4 2597 t0 = tcg_temp_new_i32();
76db3ba4 2598 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2599 tcg_gen_bswap16_i32(t0, t0);
76db3ba4
AJ		 2600 tcg_gen_extu_i32_tl(arg1, t0);
2601 tcg_gen_ext16s_tl(arg1, arg1);
a7812ae4 2602 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2603#else
2604 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2605 tcg_gen_bswap16_i32(arg1, arg1);
2606 tcg_gen_ext16s_i32(arg1, arg1);
2607#endif
2608 } else {
2609 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2610 }
b61f2753
AJ		 2611}
2612
76db3ba4 2613static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2614{
76db3ba4
AJ		 2615 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2616 if (unlikely(ctx->le_mode)) {
2617#if defined(TARGET_PPC64)
2618 TCGv_i32 t0 = tcg_temp_new_i32();
2619 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2620 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2621 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2622 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2623#else
2624 tcg_gen_bswap_i32(arg1, arg1);
2625#endif
2626 }
b61f2753
AJ		 2627}
2628
76db3ba4
AJ		 2629#if defined(TARGET_PPC64)
2630static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2631{
a457e7ee 2632 if (unlikely(ctx->le_mode)) {
a7812ae4 2633 TCGv_i32 t0;
76db3ba4 2634 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
a7812ae4 2635 t0 = tcg_temp_new_i32();
76db3ba4 2636 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2637 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2638 tcg_gen_ext_i32_tl(arg1, t0);
a7812ae4 2639 tcg_temp_free_i32(t0);
b61f2753 2640 } else
76db3ba4 2641 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753 2642}
76db3ba4 2643#endif
b61f2753 2644
76db3ba4 2645static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2646{
76db3ba4
AJ		 2647 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2648 if (unlikely(ctx->le_mode)) {
2649 tcg_gen_bswap_i64(arg1, arg1);
2650 }
b61f2753
AJ		 2651}
2652
76db3ba4 2653static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2654{
76db3ba4 2655 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2656}
2657
76db3ba4 2658static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2659{
76db3ba4
AJ		 2660 if (unlikely(ctx->le_mode)) {
2661#if defined(TARGET_PPC64)
a7812ae4 2662 TCGv_i32 t0;
76db3ba4 2663 TCGv t1;
a7812ae4 2664 t0 = tcg_temp_new_i32();
76db3ba4 2665 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694
AJ		 2666 tcg_gen_ext16u_i32(t0, t0);
2667 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2668 t1 = tcg_temp_new();
ea363694 2669 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2670 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2671 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2672 tcg_temp_free(t1);
2673#else
2674 TCGv t0 = tcg_temp_new();
2675 tcg_gen_ext16u_tl(t0, arg1);
2676 tcg_gen_bswap16_i32(t0, t0);
2677 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2678 tcg_temp_free(t0);
2679#endif
2680 } else {
2681 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2682 }
b61f2753
AJ		 2683}
2684
76db3ba4 2685static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2686{
76db3ba4
AJ		 2687 if (unlikely(ctx->le_mode)) {
2688#if defined(TARGET_PPC64)
a7812ae4 2689 TCGv_i32 t0;
76db3ba4 2690 TCGv t1;
a7812ae4 2691 t0 = tcg_temp_new_i32();
76db3ba4 2692 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2693 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2694 t1 = tcg_temp_new();
ea363694 2695 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2696 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2697 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2698 tcg_temp_free(t1);
2699#else
2700 TCGv t0 = tcg_temp_new_i32();
2701 tcg_gen_bswap_i32(t0, arg1);
2702 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2703 tcg_temp_free(t0);
2704#endif
2705 } else {
2706 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2707 }
b61f2753
AJ		 2708}
2709
76db3ba4 2710static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2711{
76db3ba4 2712 if (unlikely(ctx->le_mode)) {
a7812ae4 2713 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4
AJ		 2714 tcg_gen_bswap_i64(t0, arg1);
2715 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2716 tcg_temp_free_i64(t0);
b61f2753 2717 } else
76db3ba4 2718 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2719}
2720
0c8aacd4
AJ		 2721#define GEN_LD(name, ldop, opc, type) \
2722GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2723{ \
76db3ba4
AJ		 2724 TCGv EA; \
2725 gen_set_access_type(ctx, ACCESS_INT); \
2726 EA = tcg_temp_new(); \
2727 gen_addr_imm_index(ctx, EA, 0); \
2728 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2729 tcg_temp_free(EA); \
79aceca5
FB		 2730}
2731
0c8aacd4
AJ		 2732#define GEN_LDU(name, ldop, opc, type) \
2733GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2734{ \
b61f2753 2735 TCGv EA; \
76a66253
JM		 2736 if (unlikely(rA(ctx->opcode) == 0 || \
2737 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2738 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2739 return; \
9a64fbe4 2740 } \
76db3ba4 2741 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2742 EA = tcg_temp_new(); \
9d53c753 2743 if (type == PPC_64B) \
76db3ba4 2744 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2745 else \
76db3ba4
AJ		 2746 gen_addr_imm_index(ctx, EA, 0); \
2747 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2748 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2749 tcg_temp_free(EA); \
79aceca5
FB		 2750}
2751
0c8aacd4
AJ		 2752#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2753GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2754{ \
b61f2753 2755 TCGv EA; \
76a66253
JM		 2756 if (unlikely(rA(ctx->opcode) == 0 || \
2757 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2758 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2759 return; \
9a64fbe4 2760 } \
76db3ba4 2761 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2762 EA = tcg_temp_new(); \
76db3ba4
AJ		 2763 gen_addr_reg_index(ctx, EA); \
2764 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2765 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2766 tcg_temp_free(EA); \
79aceca5
FB		 2767}
2768
0c8aacd4
AJ		 2769#define GEN_LDX(name, ldop, opc2, opc3, type) \
2770GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2771{ \
76db3ba4
AJ		 2772 TCGv EA; \
2773 gen_set_access_type(ctx, ACCESS_INT); \
2774 EA = tcg_temp_new(); \
2775 gen_addr_reg_index(ctx, EA); \
2776 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2777 tcg_temp_free(EA); \
79aceca5
FB		 2778}
2779
0c8aacd4
AJ		 2780#define GEN_LDS(name, ldop, op, type) \
2781GEN_LD(name, ldop, op | 0x20, type); \
2782GEN_LDU(name, ldop, op | 0x21, type); \
2783GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2784GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2785
2786/* lbz lbzu lbzux lbzx */
0c8aacd4 2787GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2788/* lha lhau lhaux lhax */
0c8aacd4 2789GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2790/* lhz lhzu lhzux lhzx */
0c8aacd4 2791GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2792/* lwz lwzu lwzux lwzx */
0c8aacd4 2793GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2794#if defined(TARGET_PPC64)
d9bce9d9 2795/* lwaux */
0c8aacd4 2796GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2797/* lwax */
0c8aacd4 2798GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2799/* ldux */
0c8aacd4 2800GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2801/* ldx */
0c8aacd4 2802GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2803GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2804{
b61f2753 2805 TCGv EA;
d9bce9d9
JM		 2806 if (Rc(ctx->opcode)) {
2807 if (unlikely(rA(ctx->opcode) == 0 ||
2808 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2809 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2810 return;
2811 }
2812 }
76db3ba4 2813 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2814 EA = tcg_temp_new();
76db3ba4 2815 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2816 if (ctx->opcode & 0x02) {
2817 /* lwa (lwau is undefined) */
76db3ba4 2818 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2819 } else {
2820 /* ld - ldu */
76db3ba4 2821 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2822 }
d9bce9d9 2823 if (Rc(ctx->opcode))
b61f2753
AJ		 2824 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2825 tcg_temp_free(EA);
d9bce9d9 2826}
be147d08
JM		 2827/* lq */
2828GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2829{
2830#if defined(CONFIG_USER_ONLY)
e06fcd75 2831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2832#else
2833 int ra, rd;
b61f2753 2834 TCGv EA;
be147d08
JM		 2835
2836 /* Restore CPU state */
76db3ba4 2837 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2839 return;
2840 }
2841 ra = rA(ctx->opcode);
2842 rd = rD(ctx->opcode);
2843 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2844 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2845 return;
2846 }
76db3ba4 2847 if (unlikely(ctx->le_mode)) {
be147d08 2848 /* Little-endian mode is not handled */
e06fcd75 2849 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2850 return;
2851 }
76db3ba4 2852 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2853 EA = tcg_temp_new();
76db3ba4
AJ		 2854 gen_addr_imm_index(ctx, EA, 0x0F);
2855 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2856 gen_addr_add(ctx, EA, EA, 8);
2857 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
b61f2753 2858 tcg_temp_free(EA);
be147d08
JM		 2859#endif
2860}
d9bce9d9 2861#endif
79aceca5
FB		 2862
2863/*** Integer store ***/
0c8aacd4
AJ		 2864#define GEN_ST(name, stop, opc, type) \
2865GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2866{ \
76db3ba4
AJ		 2867 TCGv EA; \
2868 gen_set_access_type(ctx, ACCESS_INT); \
2869 EA = tcg_temp_new(); \
2870 gen_addr_imm_index(ctx, EA, 0); \
2871 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2872 tcg_temp_free(EA); \
79aceca5
FB		 2873}
2874
0c8aacd4
AJ		 2875#define GEN_STU(name, stop, opc, type) \
2876GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2877{ \
b61f2753 2878 TCGv EA; \
76a66253 2879 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2880 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2881 return; \
9a64fbe4 2882 } \
76db3ba4 2883 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2884 EA = tcg_temp_new(); \
9d53c753 2885 if (type == PPC_64B) \
76db3ba4 2886 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2887 else \
76db3ba4
AJ		 2888 gen_addr_imm_index(ctx, EA, 0); \
2889 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2890 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2891 tcg_temp_free(EA); \
79aceca5
FB		 2892}
2893
0c8aacd4
AJ		 2894#define GEN_STUX(name, stop, opc2, opc3, type) \
2895GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2896{ \
b61f2753 2897 TCGv EA; \
76a66253 2898 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2899 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2900 return; \
9a64fbe4 2901 } \
76db3ba4 2902 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2903 EA = tcg_temp_new(); \
76db3ba4
AJ		 2904 gen_addr_reg_index(ctx, EA); \
2905 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2906 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2907 tcg_temp_free(EA); \
79aceca5
FB		 2908}
2909
0c8aacd4
AJ		 2910#define GEN_STX(name, stop, opc2, opc3, type) \
2911GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2912{ \
76db3ba4
AJ		 2913 TCGv EA; \
2914 gen_set_access_type(ctx, ACCESS_INT); \
2915 EA = tcg_temp_new(); \
2916 gen_addr_reg_index(ctx, EA); \
2917 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2918 tcg_temp_free(EA); \
79aceca5
FB		 2919}
2920
0c8aacd4
AJ		 2921#define GEN_STS(name, stop, op, type) \
2922GEN_ST(name, stop, op | 0x20, type); \
2923GEN_STU(name, stop, op | 0x21, type); \
2924GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2925GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2926
2927/* stb stbu stbux stbx */
0c8aacd4 2928GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2929/* sth sthu sthux sthx */
0c8aacd4 2930GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2931/* stw stwu stwux stwx */
0c8aacd4 2932GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2933#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2934GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2935GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2936GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2937{
be147d08 2938 int rs;
b61f2753 2939 TCGv EA;
be147d08
JM		 2940
2941 rs = rS(ctx->opcode);
2942 if ((ctx->opcode & 0x3) == 0x2) {
2943#if defined(CONFIG_USER_ONLY)
e06fcd75 2944 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2945#else
2946 /* stq */
76db3ba4 2947 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2949 return;
2950 }
2951 if (unlikely(rs & 1)) {
e06fcd75 2952 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2953 return;
2954 }
76db3ba4 2955 if (unlikely(ctx->le_mode)) {
be147d08 2956 /* Little-endian mode is not handled */
e06fcd75 2957 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2958 return;
2959 }
76db3ba4 2960 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2961 EA = tcg_temp_new();
76db3ba4
AJ		 2962 gen_addr_imm_index(ctx, EA, 0x03);
2963 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2964 gen_addr_add(ctx, EA, EA, 8);
2965 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
b61f2753 2966 tcg_temp_free(EA);
be147d08
JM		 2967#endif
2968 } else {
2969 /* std / stdu */
2970 if (Rc(ctx->opcode)) {
2971 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2972 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2973 return;
2974 }
2975 }
76db3ba4 2976 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2977 EA = tcg_temp_new();
76db3ba4
AJ		 2978 gen_addr_imm_index(ctx, EA, 0x03);
2979 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 2980 if (Rc(ctx->opcode))
b61f2753
AJ		 2981 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2982 tcg_temp_free(EA);
d9bce9d9 2983 }
d9bce9d9
JM		 2984}
2985#endif
79aceca5
FB		 2986/*** Integer load and store with byte reverse ***/
2987/* lhbrx */
76db3ba4 2988static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2989{
76db3ba4
AJ		 2990 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2991 if (likely(!ctx->le_mode)) {
2992#if defined(TARGET_PPC64)
2993 TCGv_i32 t0 = tcg_temp_new_i32();
2994 tcg_gen_trunc_tl_i32(t0, arg1);
2995 tcg_gen_bswap16_i32(t0, t0);
2996 tcg_gen_extu_i32_tl(arg1, t0);
2997 tcg_temp_free_i32(t0);
2998#else
2999 tcg_gen_bswap16_i32(arg1, arg1);
3000#endif
3001 }
b61f2753 3002}
0c8aacd4 3003GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3004
79aceca5 3005/* lwbrx */
76db3ba4 3006static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3007{
76db3ba4
AJ		 3008 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3009 if (likely(!ctx->le_mode)) {
3010#if defined(TARGET_PPC64)
3011 TCGv_i32 t0 = tcg_temp_new_i32();
3012 tcg_gen_trunc_tl_i32(t0, arg1);
3013 tcg_gen_bswap_i32(t0, t0);
3014 tcg_gen_extu_i32_tl(arg1, t0);
3015 tcg_temp_free_i32(t0);
3016#else
3017 tcg_gen_bswap_i32(arg1, arg1);
3018#endif
3019 }
b61f2753 3020}
0c8aacd4 3021GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3022
79aceca5 3023/* sthbrx */
76db3ba4 3024static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3025{
76db3ba4
AJ		 3026 if (likely(!ctx->le_mode)) {
3027#if defined(TARGET_PPC64)
3028 TCGv_i32 t0;
3029 TCGv t1;
3030 t0 = tcg_temp_new_i32();
3031 tcg_gen_trunc_tl_i32(t0, arg1);
3032 tcg_gen_ext16u_i32(t0, t0);
3033 tcg_gen_bswap16_i32(t0, t0);
3034 t1 = tcg_temp_new();
3035 tcg_gen_extu_i32_tl(t1, t0);
3036 tcg_temp_free_i32(t0);
3037 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3038 tcg_temp_free(t1);
3039#else
3040 TCGv t0 = tcg_temp_new();
3041 tcg_gen_ext16u_tl(t0, arg1);
3042 tcg_gen_bswap16_i32(t0, t0);
3043 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3044 tcg_temp_free(t0);
3045#endif
3046 } else {
3047 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3048 }
b61f2753 3049}
0c8aacd4 3050GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3051
79aceca5 3052/* stwbrx */
76db3ba4 3053static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3054{
76db3ba4
AJ		 3055 if (likely(!ctx->le_mode)) {
3056#if defined(TARGET_PPC64)
3057 TCGv_i32 t0;
3058 TCGv t1;
3059 t0 = tcg_temp_new_i32();
3060 tcg_gen_trunc_tl_i32(t0, arg1);
3061 tcg_gen_bswap_i32(t0, t0);
3062 t1 = tcg_temp_new();
3063 tcg_gen_extu_i32_tl(t1, t0);
3064 tcg_temp_free_i32(t0);
3065 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3066 tcg_temp_free(t1);
3067#else
3068 TCGv t0 = tcg_temp_new_i32();
3069 tcg_gen_bswap_i32(t0, arg1);
3070 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3071 tcg_temp_free(t0);
3072#endif
3073 } else {
3074 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3075 }
b61f2753 3076}
0c8aacd4 3077GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3078
3079/*** Integer load and store multiple ***/
3080/* lmw */
3081GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3082{
76db3ba4
AJ		 3083 TCGv t0;
3084 TCGv_i32 t1;
3085 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3086 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3087 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3088 t0 = tcg_temp_new();
3089 t1 = tcg_const_i32(rD(ctx->opcode));
3090 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3091 gen_helper_lmw(t0, t1);
3092 tcg_temp_free(t0);
3093 tcg_temp_free_i32(t1);
79aceca5
FB		 3094}
3095
3096/* stmw */
3097GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3098{
76db3ba4
AJ		 3099 TCGv t0;
3100 TCGv_i32 t1;
3101 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3102 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3103 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3104 t0 = tcg_temp_new();
3105 t1 = tcg_const_i32(rS(ctx->opcode));
3106 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3107 gen_helper_stmw(t0, t1);
3108 tcg_temp_free(t0);
3109 tcg_temp_free_i32(t1);
79aceca5
FB		 3110}
3111
3112/*** Integer load and store strings ***/
3113/* lswi */
3fc6c082 3114/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3115 * rA is in the range of registers to be loaded.
3116 * In an other hand, IBM says this is valid, but rA won't be loaded.
3117 * For now, I'll follow the spec...
3118 */
05332d70 3119GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3120{
dfbc799d
AJ		 3121 TCGv t0;
3122 TCGv_i32 t1, t2;
79aceca5
FB		 3123 int nb = NB(ctx->opcode);
3124 int start = rD(ctx->opcode);
9a64fbe4 3125 int ra = rA(ctx->opcode);
79aceca5
FB		 3126 int nr;
3127
3128 if (nb == 0)
3129 nb = 32;
3130 nr = nb / 4;
76a66253
JM		 3131 if (unlikely(((start + nr) > 32 &&
3132 start <= ra && (start + nr - 32) > ra) ||
3133 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3134 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3135 return;
297d8e62 3136 }
76db3ba4 3137 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3138 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3139 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3140 t0 = tcg_temp_new();
76db3ba4 3141 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3142 t1 = tcg_const_i32(nb);
3143 t2 = tcg_const_i32(start);
3144 gen_helper_lsw(t0, t1, t2);
3145 tcg_temp_free(t0);
3146 tcg_temp_free_i32(t1);
3147 tcg_temp_free_i32(t2);
79aceca5
FB		 3148}
3149
3150/* lswx */
05332d70 3151GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3152{
76db3ba4
AJ		 3153 TCGv t0;
3154 TCGv_i32 t1, t2, t3;
3155 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3156 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3157 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3158 t0 = tcg_temp_new();
3159 gen_addr_reg_index(ctx, t0);
3160 t1 = tcg_const_i32(rD(ctx->opcode));
3161 t2 = tcg_const_i32(rA(ctx->opcode));
3162 t3 = tcg_const_i32(rB(ctx->opcode));
dfbc799d
AJ		 3163 gen_helper_lswx(t0, t1, t2, t3);
3164 tcg_temp_free(t0);
3165 tcg_temp_free_i32(t1);
3166 tcg_temp_free_i32(t2);
3167 tcg_temp_free_i32(t3);
79aceca5
FB		 3168}
3169
3170/* stswi */
05332d70 3171GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3172{
76db3ba4
AJ		 3173 TCGv t0;
3174 TCGv_i32 t1, t2;
4b3686fa 3175 int nb = NB(ctx->opcode);
76db3ba4 3176 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3177 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3178 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3179 t0 = tcg_temp_new();
3180 gen_addr_register(ctx, t0);
4b3686fa
FB		 3181 if (nb == 0)
3182 nb = 32;
dfbc799d 3183 t1 = tcg_const_i32(nb);
76db3ba4 3184 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3185 gen_helper_stsw(t0, t1, t2);
3186 tcg_temp_free(t0);
3187 tcg_temp_free_i32(t1);
3188 tcg_temp_free_i32(t2);
79aceca5
FB		 3189}
3190
3191/* stswx */
05332d70 3192GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3193{
76db3ba4
AJ		 3194 TCGv t0;
3195 TCGv_i32 t1, t2;
3196 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3197 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3198 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3199 t0 = tcg_temp_new();
3200 gen_addr_reg_index(ctx, t0);
3201 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3202 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3203 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3204 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3205 gen_helper_stsw(t0, t1, t2);
3206 tcg_temp_free(t0);
3207 tcg_temp_free_i32(t1);
3208 tcg_temp_free_i32(t2);
79aceca5
FB		 3209}
3210
3211/*** Memory synchronisation ***/
3212/* eieio */
0db1b20e 3213GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3214{
79aceca5
FB		 3215}
3216
3217/* isync */
0db1b20e 3218GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3219{
e06fcd75 3220 gen_stop_exception(ctx);
79aceca5
FB		 3221}
3222
111bfab3 3223/* lwarx */
76a66253 3224GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3225{
76db3ba4
AJ		 3226 TCGv t0;
3227 gen_set_access_type(ctx, ACCESS_RES);
3228 t0 = tcg_temp_local_new();
3229 gen_addr_reg_index(ctx, t0);
cf360a32 3230 gen_check_align(ctx, t0, 0x03);
76db3ba4 3231 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3232 tcg_gen_mov_tl(cpu_reserve, t0);
3233 tcg_temp_free(t0);
79aceca5
FB		 3234}
3235
3236/* stwcx. */
c7697e1f 3237GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3238{
76db3ba4
AJ		 3239 int l1;
3240 TCGv t0;
3241 gen_set_access_type(ctx, ACCESS_RES);
3242 t0 = tcg_temp_local_new();
3243 gen_addr_reg_index(ctx, t0);
cf360a32 3244 gen_check_align(ctx, t0, 0x03);
cf360a32
AJ		 3245 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3246 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3247 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3248 l1 = gen_new_label();
cf360a32
AJ		 3249 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3250 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3251 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3252 gen_set_label(l1);
3253 tcg_gen_movi_tl(cpu_reserve, -1);
3254 tcg_temp_free(t0);
79aceca5
FB		 3255}
3256
426613db 3257#if defined(TARGET_PPC64)
426613db 3258/* ldarx */
a750fc0b 3259GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3260{
76db3ba4
AJ		 3261 TCGv t0;
3262 gen_set_access_type(ctx, ACCESS_RES);
3263 t0 = tcg_temp_local_new();
3264 gen_addr_reg_index(ctx, t0);
cf360a32 3265 gen_check_align(ctx, t0, 0x07);
76db3ba4 3266 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3267 tcg_gen_mov_tl(cpu_reserve, t0);
3268 tcg_temp_free(t0);
426613db
JM		 3269}
3270
3271/* stdcx. */
c7697e1f 3272GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3273{
76db3ba4
AJ		 3274 int l1;
3275 TCGv t0;
3276 gen_set_access_type(ctx, ACCESS_RES);
3277 t0 = tcg_temp_local_new();
3278 gen_addr_reg_index(ctx, t0);
cf360a32 3279 gen_check_align(ctx, t0, 0x07);
cf360a32
AJ		 3280 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3281 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3282 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3283 l1 = gen_new_label();
cf360a32
AJ		 3284 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3285 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3286 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3287 gen_set_label(l1);
3288 tcg_gen_movi_tl(cpu_reserve, -1);
3289 tcg_temp_free(t0);
426613db
JM		 3290}
3291#endif /* defined(TARGET_PPC64) */
3292
79aceca5 3293/* sync */
a902d886 3294GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3295{
79aceca5
FB		 3296}
3297
0db1b20e
JM		 3298/* wait */
3299GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3300{
931ff272
AJ		 3301 TCGv_i32 t0 = tcg_temp_new_i32();
3302 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3303 tcg_temp_free_i32(t0);
0db1b20e 3304 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3305 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3306}
3307
79aceca5 3308/*** Floating-point load ***/
a0d7d5a7
AJ		 3309#define GEN_LDF(name, ldop, opc, type) \
3310GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3311{ \
a0d7d5a7 3312 TCGv EA; \
76a66253 3313 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3314 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3315 return; \
3316 } \
76db3ba4 3317 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3318 EA = tcg_temp_new(); \
76db3ba4
AJ		 3319 gen_addr_imm_index(ctx, EA, 0); \
3320 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3321 tcg_temp_free(EA); \
79aceca5
FB		 3322}
3323
a0d7d5a7
AJ		 3324#define GEN_LDUF(name, ldop, opc, type) \
3325GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3326{ \
a0d7d5a7 3327 TCGv EA; \
76a66253 3328 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3329 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3330 return; \
3331 } \
76a66253 3332 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3333 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3334 return; \
9a64fbe4 3335 } \
76db3ba4 3336 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3337 EA = tcg_temp_new(); \
76db3ba4
AJ		 3338 gen_addr_imm_index(ctx, EA, 0); \
3339 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3340 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3341 tcg_temp_free(EA); \
79aceca5
FB		 3342}
3343
a0d7d5a7
AJ		 3344#define GEN_LDUXF(name, ldop, opc, type) \
3345GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3346{ \
a0d7d5a7 3347 TCGv EA; \
76a66253 3348 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3349 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3350 return; \
3351 } \
76a66253 3352 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3353 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3354 return; \
9a64fbe4 3355 } \
76db3ba4 3356 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3357 EA = tcg_temp_new(); \
76db3ba4
AJ		 3358 gen_addr_reg_index(ctx, EA); \
3359 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3360 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3361 tcg_temp_free(EA); \
79aceca5
FB		 3362}
3363
a0d7d5a7
AJ		 3364#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3365GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3366{ \
a0d7d5a7 3367 TCGv EA; \
76a66253 3368 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3369 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3370 return; \
3371 } \
76db3ba4 3372 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3373 EA = tcg_temp_new(); \
76db3ba4
AJ		 3374 gen_addr_reg_index(ctx, EA); \
3375 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3376 tcg_temp_free(EA); \
79aceca5
FB		 3377}
3378
a0d7d5a7
AJ		 3379#define GEN_LDFS(name, ldop, op, type) \
3380GEN_LDF(name, ldop, op | 0x20, type); \
3381GEN_LDUF(name, ldop, op | 0x21, type); \
3382GEN_LDUXF(name, ldop, op | 0x01, type); \
3383GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3384
76db3ba4 3385static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3386{
3387 TCGv t0 = tcg_temp_new();
3388 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3389 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3390 tcg_gen_trunc_tl_i32(t1, t0);
3391 tcg_temp_free(t0);
3392 gen_helper_float32_to_float64(arg1, t1);
3393 tcg_temp_free_i32(t1);
3394}
79aceca5 3395
a0d7d5a7
AJ		 3396 /* lfd lfdu lfdux lfdx */
3397GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3398 /* lfs lfsu lfsux lfsx */
3399GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3400
3401/*** Floating-point store ***/
a0d7d5a7
AJ		 3402#define GEN_STF(name, stop, opc, type) \
3403GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3404{ \
a0d7d5a7 3405 TCGv EA; \
76a66253 3406 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3407 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3408 return; \
3409 } \
76db3ba4 3410 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3411 EA = tcg_temp_new(); \
76db3ba4
AJ		 3412 gen_addr_imm_index(ctx, EA, 0); \
3413 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3414 tcg_temp_free(EA); \
79aceca5
FB		 3415}
3416
a0d7d5a7
AJ		 3417#define GEN_STUF(name, stop, opc, type) \
3418GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3419{ \
a0d7d5a7 3420 TCGv EA; \
76a66253 3421 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3422 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3423 return; \
3424 } \
76a66253 3425 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3426 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3427 return; \
9a64fbe4 3428 } \
76db3ba4 3429 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3430 EA = tcg_temp_new(); \
76db3ba4
AJ		 3431 gen_addr_imm_index(ctx, EA, 0); \
3432 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3433 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3434 tcg_temp_free(EA); \
79aceca5
FB		 3435}
3436
a0d7d5a7
AJ		 3437#define GEN_STUXF(name, stop, opc, type) \
3438GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3439{ \
a0d7d5a7 3440 TCGv EA; \
76a66253 3441 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3442 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3443 return; \
3444 } \
76a66253 3445 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3446 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3447 return; \
9a64fbe4 3448 } \
76db3ba4 3449 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3450 EA = tcg_temp_new(); \
76db3ba4
AJ		 3451 gen_addr_reg_index(ctx, EA); \
3452 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3453 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3454 tcg_temp_free(EA); \
79aceca5
FB		 3455}
3456
a0d7d5a7
AJ		 3457#define GEN_STXF(name, stop, opc2, opc3, type) \
3458GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3459{ \
a0d7d5a7 3460 TCGv EA; \
76a66253 3461 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3462 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3463 return; \
3464 } \
76db3ba4 3465 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3466 EA = tcg_temp_new(); \
76db3ba4
AJ		 3467 gen_addr_reg_index(ctx, EA); \
3468 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3469 tcg_temp_free(EA); \
79aceca5
FB		 3470}
3471
a0d7d5a7
AJ		 3472#define GEN_STFS(name, stop, op, type) \
3473GEN_STF(name, stop, op | 0x20, type); \
3474GEN_STUF(name, stop, op | 0x21, type); \
3475GEN_STUXF(name, stop, op | 0x01, type); \
3476GEN_STXF(name, stop, 0x17, op | 0x00, type)
3477
76db3ba4 3478static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3479{
3480 TCGv_i32 t0 = tcg_temp_new_i32();
3481 TCGv t1 = tcg_temp_new();
3482 gen_helper_float64_to_float32(t0, arg1);
3483 tcg_gen_extu_i32_tl(t1, t0);
3484 tcg_temp_free_i32(t0);
76db3ba4 3485 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3486 tcg_temp_free(t1);
3487}
79aceca5
FB		 3488
3489/* stfd stfdu stfdux stfdx */
a0d7d5a7 3490GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3491/* stfs stfsu stfsux stfsx */
a0d7d5a7 3492GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3493
3494/* Optional: */
76db3ba4 3495static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3496{
3497 TCGv t0 = tcg_temp_new();
3498 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3499 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3500 tcg_temp_free(t0);
3501}
79aceca5 3502/* stfiwx */
a0d7d5a7 3503GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3504
3505/*** Branch ***/
b068d6a7
JM		 3506static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3507 target_ulong dest)
c1942362
FB		 3508{
3509 TranslationBlock *tb;
3510 tb = ctx->tb;
a2ffb812
AJ		 3511#if defined(TARGET_PPC64)
3512 if (!ctx->sf_mode)
3513 dest = (uint32_t) dest;
3514#endif
57fec1fe 3515 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3516 likely(!ctx->singlestep_enabled)) {
57fec1fe 3517 tcg_gen_goto_tb(n);
a2ffb812 3518 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3519 tcg_gen_exit_tb((long)tb + n);
c1942362 3520 } else {
a2ffb812 3521 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3522 if (unlikely(ctx->singlestep_enabled)) {
3523 if ((ctx->singlestep_enabled &
bdc4e053 3524 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3525 ctx->exception == POWERPC_EXCP_BRANCH) {
3526 target_ulong tmp = ctx->nip;
3527 ctx->nip = dest;
e06fcd75 3528 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3529 ctx->nip = tmp;
3530 }
3531 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3532 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3533 }
3534 }
57fec1fe 3535 tcg_gen_exit_tb(0);
c1942362 3536 }
c53be334
FB		 3537}
3538
b068d6a7 3539static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3540{
3541#if defined(TARGET_PPC64)
a2ffb812
AJ		 3542 if (ctx->sf_mode == 0)
3543 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3544 else
3545#endif
a2ffb812 3546 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3547}
3548
79aceca5
FB		 3549/* b ba bl bla */
3550GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3551{
76a66253 3552 target_ulong li, target;
38a64f9d 3553
8cbcb4fa 3554 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3555 /* sign extend LI */
76a66253 3556#if defined(TARGET_PPC64)
d9bce9d9
JM		 3557 if (ctx->sf_mode)
3558 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3559 else
76a66253 3560#endif
d9bce9d9 3561 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3562 if (likely(AA(ctx->opcode) == 0))
046d6672 3563 target = ctx->nip + li - 4;
79aceca5 3564 else
9a64fbe4 3565 target = li;
e1833e1f
JM		 3566 if (LK(ctx->opcode))
3567 gen_setlr(ctx, ctx->nip);
c1942362 3568 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3569}
3570
e98a6e40
FB		 3571#define BCOND_IM 0
3572#define BCOND_LR 1
3573#define BCOND_CTR 2
3574
b068d6a7 3575static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3576{
d9bce9d9 3577 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3578 int l1 = gen_new_label();
3579 TCGv target;
e98a6e40 3580
8cbcb4fa 3581 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3582 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3583 target = tcg_temp_local_new();
a2ffb812
AJ		 3584 if (type == BCOND_CTR)
3585 tcg_gen_mov_tl(target, cpu_ctr);
3586 else
3587 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3588 }
e1833e1f
JM		 3589 if (LK(ctx->opcode))
3590 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3591 l1 = gen_new_label();
3592 if ((bo & 0x4) == 0) {
3593 /* Decrement and test CTR */
a7812ae4 3594 TCGv temp = tcg_temp_new();
a2ffb812 3595 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3596 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3597 return;
3598 }
3599 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3600#if defined(TARGET_PPC64)
a2ffb812
AJ		 3601 if (!ctx->sf_mode)
3602 tcg_gen_ext32u_tl(temp, cpu_ctr);
3603 else
d9bce9d9 3604#endif
a2ffb812
AJ		 3605 tcg_gen_mov_tl(temp, cpu_ctr);
3606 if (bo & 0x2) {
3607 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3608 } else {
3609 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3610 }
a7812ae4 3611 tcg_temp_free(temp);
a2ffb812
AJ		 3612 }
3613 if ((bo & 0x10) == 0) {
3614 /* Test CR */
3615 uint32_t bi = BI(ctx->opcode);
3616 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3617 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3618
d9bce9d9 3619 if (bo & 0x8) {
a2ffb812
AJ		 3620 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3621 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3622 } else {
a2ffb812
AJ		 3623 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3624 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3625 }
a7812ae4 3626 tcg_temp_free_i32(temp);
d9bce9d9 3627 }
e98a6e40 3628 if (type == BCOND_IM) {
a2ffb812
AJ		 3629 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3630 if (likely(AA(ctx->opcode) == 0)) {
3631 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3632 } else {
3633 gen_goto_tb(ctx, 0, li);
3634 }
c53be334 3635 gen_set_label(l1);
c1942362 3636 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3637 } else {
d9bce9d9 3638#if defined(TARGET_PPC64)
a2ffb812
AJ		 3639 if (!(ctx->sf_mode))
3640 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3641 else
3642#endif
3643 tcg_gen_andi_tl(cpu_nip, target, ~3);
3644 tcg_gen_exit_tb(0);
3645 gen_set_label(l1);
3646#if defined(TARGET_PPC64)
3647 if (!(ctx->sf_mode))
3648 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3649 else
3650#endif
a2ffb812 3651 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3652 tcg_gen_exit_tb(0);
08e46e54 3653 }
e98a6e40
FB		 3654}
3655
3656GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3657{
e98a6e40
FB		 3658 gen_bcond(ctx, BCOND_IM);
3659}
3660
3661GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3662{
e98a6e40
FB		 3663 gen_bcond(ctx, BCOND_CTR);
3664}
3665
3666GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3667{
e98a6e40
FB		 3668 gen_bcond(ctx, BCOND_LR);
3669}
79aceca5
FB		 3670
3671/*** Condition register logical ***/
e1571908
AJ		 3672#define GEN_CRLOGIC(name, tcg_op, opc) \
3673GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3674{ \
fc0d441e
JM		 3675 uint8_t bitmask; \
3676 int sh; \
a7812ae4 3677 TCGv_i32 t0, t1; \
fc0d441e 3678 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3679 t0 = tcg_temp_new_i32(); \
fc0d441e 3680 if (sh > 0) \
fea0c503 3681 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3682 else if (sh < 0) \
fea0c503 3683 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3684 else \
fea0c503 3685 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3686 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3687 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3688 if (sh > 0) \
fea0c503 3689 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3690 else if (sh < 0) \
fea0c503 3691 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3692 else \
fea0c503
AJ		 3693 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3694 tcg_op(t0, t0, t1); \
fc0d441e 3695 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3696 tcg_gen_andi_i32(t0, t0, bitmask); \
3697 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3698 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3699 tcg_temp_free_i32(t0); \
3700 tcg_temp_free_i32(t1); \
79aceca5
FB		 3701}
3702
3703/* crand */
e1571908 3704GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3705/* crandc */
e1571908 3706GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3707/* creqv */
e1571908 3708GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3709/* crnand */
e1571908 3710GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3711/* crnor */
e1571908 3712GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3713/* cror */
e1571908 3714GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3715/* crorc */
e1571908 3716GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3717/* crxor */
e1571908 3718GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3719/* mcrf */
3720GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3721{
47e4661c 3722 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3723}
3724
3725/*** System linkage ***/
76db3ba4 3726/* rfi (mem_idx only) */
76a66253 3727GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3728{
9a64fbe4 3729#if defined(CONFIG_USER_ONLY)
e06fcd75 3730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 3731#else
3732 /* Restore CPU state */
76db3ba4 3733 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 3735 return;
9a64fbe4 3736 }
d72a19f7 3737 gen_helper_rfi();
e06fcd75 3738 gen_sync_exception(ctx);
9a64fbe4 3739#endif
79aceca5
FB		 3740}
3741
426613db 3742#if defined(TARGET_PPC64)
a750fc0b 3743GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3744{
3745#if defined(CONFIG_USER_ONLY)
e06fcd75 3746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3747#else
3748 /* Restore CPU state */
76db3ba4 3749 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3751 return;
3752 }
d72a19f7 3753 gen_helper_rfid();
e06fcd75 3754 gen_sync_exception(ctx);
426613db
JM		 3755#endif
3756}
426613db 3757
5b8105fa 3758GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3759{
3760#if defined(CONFIG_USER_ONLY)
e06fcd75 3761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3762#else
3763 /* Restore CPU state */
76db3ba4 3764 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 3765 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3766 return;
3767 }
d72a19f7 3768 gen_helper_hrfid();
e06fcd75 3769 gen_sync_exception(ctx);
be147d08
JM		 3770#endif
3771}
3772#endif
3773
79aceca5 3774/* sc */
417bf010
JM		 3775#if defined(CONFIG_USER_ONLY)
3776#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3777#else
3778#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3779#endif
e1833e1f 3780GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3781{
e1833e1f
JM		 3782 uint32_t lev;
3783
3784 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3785 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3786}
3787
3788/*** Trap ***/
3789/* tw */
76a66253 3790GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3791{
cab3bee2 3792 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3793 /* Update the nip since this might generate a trap exception */
d9bce9d9 3794 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3795 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3796 tcg_temp_free_i32(t0);
79aceca5
FB		 3797}
3798
3799/* twi */
3800GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3801{
cab3bee2
AJ		 3802 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3803 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3804 /* Update the nip since this might generate a trap exception */
3805 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3806 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3807 tcg_temp_free(t0);
3808 tcg_temp_free_i32(t1);
79aceca5
FB		 3809}
3810
d9bce9d9
JM		 3811#if defined(TARGET_PPC64)
3812/* td */
3813GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3814{
cab3bee2 3815 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3816 /* Update the nip since this might generate a trap exception */
3817 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3818 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3819 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3820}
3821
3822/* tdi */
3823GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3824{
cab3bee2
AJ		 3825 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3826 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3827 /* Update the nip since this might generate a trap exception */
3828 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3829 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3830 tcg_temp_free(t0);
3831 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3832}
3833#endif
3834
79aceca5 3835/*** Processor control ***/
79aceca5
FB		 3836/* mcrxr */
3837GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3838{
3d7b417e
AJ		 3839 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3840 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3841 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3842}
3843
0cfe11ea 3844/* mfcr mfocrf */
76a66253 3845GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3846{
76a66253 3847 uint32_t crm, crn;
3b46e624 3848
76a66253
JM		 3849 if (likely(ctx->opcode & 0x00100000)) {
3850 crm = CRM(ctx->opcode);
8dd640e4 3851 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 3852 crn = ctz32 (crm);
e1571908 3853 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
8dd640e4 3854 tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)],
3855 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 3856 }
d9bce9d9 3857 } else {
a7812ae4 3858 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3859 }
79aceca5
FB		 3860}
3861
3862/* mfmsr */
3863GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3864{
9a64fbe4 3865#if defined(CONFIG_USER_ONLY)
e06fcd75 3866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3867#else
76db3ba4 3868 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3870 return;
9a64fbe4 3871 }
6527f6ea 3872 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3873#endif
79aceca5
FB		 3874}
3875
a11b8151 3876#if 1
6f2d8978 3877#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3878#else
3879static void spr_noaccess (void *opaque, int sprn)
3880{
3881 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3882 printf("ERROR: try to access SPR %d !\n", sprn);
3883}
3884#define SPR_NOACCESS (&spr_noaccess)
3885#endif
3886
79aceca5 3887/* mfspr */
b068d6a7 3888static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3889{
45d827d2 3890 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3891 uint32_t sprn = SPR(ctx->opcode);
3892
3fc6c082 3893#if !defined(CONFIG_USER_ONLY)
76db3ba4 3894 if (ctx->mem_idx == 2)
be147d08 3895 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 3896 else if (ctx->mem_idx)
3fc6c082
FB		 3897 read_cb = ctx->spr_cb[sprn].oea_read;
3898 else
9a64fbe4 3899#endif
3fc6c082 3900 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3901 if (likely(read_cb != NULL)) {
3902 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3903 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3904 } else {
3905 /* Privilege exception */
9fceefa7
JM		 3906 /* This is a hack to avoid warnings when running Linux:
3907 * this OS breaks the PowerPC virtualisation model,
3908 * allowing userland application to read the PVR
3909 */
3910 if (sprn != SPR_PVR) {
93fcfe39 3911 qemu_log("Trying to read privileged spr %d %03x at "
077fc206 3912 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3913 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3914 sprn, sprn, ctx->nip);
f24e5695 3915 }
e06fcd75 3916 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3917 }
3fc6c082
FB		 3918 } else {
3919 /* Not defined */
93fcfe39 3920 qemu_log("Trying to read invalid spr %d %03x at "
077fc206 3921 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3922 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3923 sprn, sprn, ctx->nip);
e06fcd75 3924 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3925 }
79aceca5
FB		 3926}
3927
3fc6c082 3928GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3929{
3fc6c082 3930 gen_op_mfspr(ctx);
76a66253 3931}
3fc6c082
FB		 3932
3933/* mftb */
a750fc0b 3934GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3935{
3936 gen_op_mfspr(ctx);
79aceca5
FB		 3937}
3938
0cfe11ea 3939/* mtcrf mtocrf*/
8dd4983c 3940GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3941{
76a66253 3942 uint32_t crm, crn;
3b46e624 3943
76a66253 3944 crm = CRM(ctx->opcode);
8dd640e4 3945 if (likely((ctx->opcode & 0x00100000))) {
3946 if (crm && ((crm & (crm - 1)) == 0)) {
3947 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 3948 crn = ctz32 (crm);
8dd640e4 3949 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 3950 tcg_gen_shri_i32(temp, temp, crn * 4);
3951 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 3952 tcg_temp_free_i32(temp);
3953 }
76a66253 3954 } else {
a7812ae4
PB		 3955 TCGv_i32 temp = tcg_const_i32(crm);
3956 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3957 tcg_temp_free_i32(temp);
76a66253 3958 }
79aceca5
FB		 3959}
3960
3961/* mtmsr */
426613db 3962#if defined(TARGET_PPC64)
be147d08 3963GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3964{
3965#if defined(CONFIG_USER_ONLY)
e06fcd75 3966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 3967#else
76db3ba4 3968 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 3970 return;
3971 }
be147d08
JM		 3972 if (ctx->opcode & 0x00010000) {
3973 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3974 TCGv t0 = tcg_temp_new();
3975 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3976 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3977 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3978 tcg_temp_free(t0);
be147d08 3979 } else {
056b05f8
JM		 3980 /* XXX: we need to update nip before the store
3981 * if we enter power saving mode, we will exit the loop
3982 * directly from ppc_store_msr
3983 */
be147d08 3984 gen_update_nip(ctx, ctx->nip);
6527f6ea 3985 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3986 /* Must stop the translation as machine state (may have) changed */
3987 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3988 gen_stop_exception(ctx);
be147d08 3989 }
426613db
JM		 3990#endif
3991}
3992#endif
3993
79aceca5
FB		 3994GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3995{
9a64fbe4 3996#if defined(CONFIG_USER_ONLY)
e06fcd75 3997 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3998#else
76db3ba4 3999 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4000 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4001 return;
9a64fbe4 4002 }
be147d08
JM		 4003 if (ctx->opcode & 0x00010000) {
4004 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4005 TCGv t0 = tcg_temp_new();
4006 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4007 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4008 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4009 tcg_temp_free(t0);
be147d08 4010 } else {
056b05f8
JM		 4011 /* XXX: we need to update nip before the store
4012 * if we enter power saving mode, we will exit the loop
4013 * directly from ppc_store_msr
4014 */
be147d08 4015 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4016#if defined(TARGET_PPC64)
6527f6ea
AJ		 4017 if (!ctx->sf_mode) {
4018 TCGv t0 = tcg_temp_new();
4019 TCGv t1 = tcg_temp_new();
4020 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4021 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4022 tcg_gen_or_tl(t0, t0, t1);
4023 tcg_temp_free(t1);
4024 gen_helper_store_msr(t0);
4025 tcg_temp_free(t0);
4026 } else
d9bce9d9 4027#endif
6527f6ea 4028 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 4029 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4030 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4031 gen_stop_exception(ctx);
be147d08 4032 }
9a64fbe4 4033#endif
79aceca5
FB		 4034}
4035
4036/* mtspr */
4037GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4038{
45d827d2 4039 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4040 uint32_t sprn = SPR(ctx->opcode);
4041
3fc6c082 4042#if !defined(CONFIG_USER_ONLY)
76db3ba4 4043 if (ctx->mem_idx == 2)
be147d08 4044 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 4045 else if (ctx->mem_idx)
3fc6c082
FB		 4046 write_cb = ctx->spr_cb[sprn].oea_write;
4047 else
9a64fbe4 4048#endif
3fc6c082 4049 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4050 if (likely(write_cb != NULL)) {
4051 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4052 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4053 } else {
4054 /* Privilege exception */
93fcfe39 4055 qemu_log("Trying to write privileged spr %d %03x at "
077fc206 4056 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 4057 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4058 sprn, sprn, ctx->nip);
e06fcd75 4059 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4060 }
3fc6c082
FB		 4061 } else {
4062 /* Not defined */
93fcfe39 4063 qemu_log("Trying to write invalid spr %d %03x at "
077fc206 4064 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 4065 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4066 sprn, sprn, ctx->nip);
e06fcd75 4067 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4068 }
79aceca5
FB		 4069}
4070
4071/*** Cache management ***/
79aceca5 4072/* dcbf */
0db1b20e 4073GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4074{
dac454af 4075 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4076 TCGv t0;
4077 gen_set_access_type(ctx, ACCESS_CACHE);
4078 t0 = tcg_temp_new();
4079 gen_addr_reg_index(ctx, t0);
4080 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4081 tcg_temp_free(t0);
79aceca5
FB		 4082}
4083
4084/* dcbi (Supervisor only) */
9a64fbe4 4085GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4086{
a541f297 4087#if defined(CONFIG_USER_ONLY)
e06fcd75 4088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4089#else
b61f2753 4090 TCGv EA, val;
76db3ba4 4091 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4093 return;
9a64fbe4 4094 }
a7812ae4 4095 EA = tcg_temp_new();
76db3ba4
AJ		 4096 gen_set_access_type(ctx, ACCESS_CACHE);
4097 gen_addr_reg_index(ctx, EA);
a7812ae4 4098 val = tcg_temp_new();
76a66253 4099 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4100 gen_qemu_ld8u(ctx, val, EA);
4101 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4102 tcg_temp_free(val);
4103 tcg_temp_free(EA);
a541f297 4104#endif
79aceca5
FB		 4105}
4106
4107/* dcdst */
9a64fbe4 4108GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4109{
76a66253 4110 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4111 TCGv t0;
4112 gen_set_access_type(ctx, ACCESS_CACHE);
4113 t0 = tcg_temp_new();
4114 gen_addr_reg_index(ctx, t0);
4115 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4116 tcg_temp_free(t0);
79aceca5
FB		 4117}
4118
4119/* dcbt */
0db1b20e 4120GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4121{
0db1b20e 4122 /* interpreted as no-op */
76a66253
JM		 4123 /* XXX: specification say this is treated as a load by the MMU
4124 * but does not generate any exception
4125 */
79aceca5
FB		 4126}
4127
4128/* dcbtst */
0db1b20e 4129GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4130{
0db1b20e 4131 /* interpreted as no-op */
76a66253
JM		 4132 /* XXX: specification say this is treated as a load by the MMU
4133 * but does not generate any exception
4134 */
79aceca5
FB		 4135}
4136
4137/* dcbz */
d63001d1 4138GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4139{
76db3ba4
AJ		 4140 TCGv t0;
4141 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4142 /* NIP cannot be restored if the memory exception comes from an helper */
4143 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4144 t0 = tcg_temp_new();
4145 gen_addr_reg_index(ctx, t0);
799a8c8d
AJ		 4146 gen_helper_dcbz(t0);
4147 tcg_temp_free(t0);
d63001d1
JM		 4148}
4149
c7697e1f 4150GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4151{
76db3ba4
AJ		 4152 TCGv t0;
4153 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4154 /* NIP cannot be restored if the memory exception comes from an helper */
4155 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4156 t0 = tcg_temp_new();
4157 gen_addr_reg_index(ctx, t0);
d63001d1 4158 if (ctx->opcode & 0x00200000)
799a8c8d 4159 gen_helper_dcbz(t0);
d63001d1 4160 else
799a8c8d
AJ		 4161 gen_helper_dcbz_970(t0);
4162 tcg_temp_free(t0);
79aceca5
FB		 4163}
4164
ae1c1a3d
AJ		 4165/* dst / dstt */
4166GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4167{
4168 if (rA(ctx->opcode) == 0) {
4169 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4170 } else {
4171 /* interpreted as no-op */
4172 }
4173}
4174
4175/* dstst /dststt */
4176GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4177{
4178 if (rA(ctx->opcode) == 0) {
4179 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4180 } else {
4181 /* interpreted as no-op */
4182 }
4183
4184}
4185
4186/* dss / dssall */
4187GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4188{
4189 /* interpreted as no-op */
4190}
4191
79aceca5 4192/* icbi */
1b413d55 4193GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4194{
76db3ba4
AJ		 4195 TCGv t0;
4196 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4197 /* NIP cannot be restored if the memory exception comes from an helper */
4198 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4199 t0 = tcg_temp_new();
4200 gen_addr_reg_index(ctx, t0);
37d269df
AJ		 4201 gen_helper_icbi(t0);
4202 tcg_temp_free(t0);
79aceca5
FB		 4203}
4204
4205/* Optional: */
4206/* dcba */
a750fc0b 4207GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4208{
0db1b20e
JM		 4209 /* interpreted as no-op */
4210 /* XXX: specification say this is treated as a store by the MMU
4211 * but does not generate any exception
4212 */
79aceca5
FB		 4213}
4214
4215/*** Segment register manipulation ***/
4216/* Supervisor only: */
4217/* mfsr */
4218GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4219{
9a64fbe4 4220#if defined(CONFIG_USER_ONLY)
e06fcd75 4221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4222#else
74d37793 4223 TCGv t0;
76db3ba4 4224 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4226 return;
9a64fbe4 4227 }
74d37793
AJ		 4228 t0 = tcg_const_tl(SR(ctx->opcode));
4229 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4230 tcg_temp_free(t0);
9a64fbe4 4231#endif
79aceca5
FB		 4232}
4233
4234/* mfsrin */
9a64fbe4 4235GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4236{
9a64fbe4 4237#if defined(CONFIG_USER_ONLY)
e06fcd75 4238 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4239#else
74d37793 4240 TCGv t0;
76db3ba4 4241 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4243 return;
9a64fbe4 4244 }
74d37793
AJ		 4245 t0 = tcg_temp_new();
4246 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4247 tcg_gen_andi_tl(t0, t0, 0xF);
4248 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4249 tcg_temp_free(t0);
9a64fbe4 4250#endif
79aceca5
FB		 4251}
4252
4253/* mtsr */
e63c59cb 4254GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4255{
9a64fbe4 4256#if defined(CONFIG_USER_ONLY)
e06fcd75 4257 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4258#else
74d37793 4259 TCGv t0;
76db3ba4 4260 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4262 return;
9a64fbe4 4263 }
74d37793
AJ		 4264 t0 = tcg_const_tl(SR(ctx->opcode));
4265 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4266 tcg_temp_free(t0);
9a64fbe4 4267#endif
79aceca5
FB		 4268}
4269
4270/* mtsrin */
9a64fbe4 4271GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4272{
9a64fbe4 4273#if defined(CONFIG_USER_ONLY)
e06fcd75 4274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4275#else
74d37793 4276 TCGv t0;
76db3ba4 4277 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4279 return;
9a64fbe4 4280 }
74d37793
AJ		 4281 t0 = tcg_temp_new();
4282 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4283 tcg_gen_andi_tl(t0, t0, 0xF);
4284 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4285 tcg_temp_free(t0);
9a64fbe4 4286#endif
79aceca5
FB		 4287}
4288
12de9a39
JM		 4289#if defined(TARGET_PPC64)
4290/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4291/* mfsr */
c7697e1f 4292GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4293{
4294#if defined(CONFIG_USER_ONLY)
e06fcd75 4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4296#else
74d37793 4297 TCGv t0;
76db3ba4 4298 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4300 return;
4301 }
74d37793 4302 t0 = tcg_const_tl(SR(ctx->opcode));
f6b868fc 4303 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
74d37793 4304 tcg_temp_free(t0);
12de9a39
JM		 4305#endif
4306}
4307
4308/* mfsrin */
c7697e1f
JM		 4309GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4310 PPC_SEGMENT_64B)
12de9a39
JM		 4311{
4312#if defined(CONFIG_USER_ONLY)
e06fcd75 4313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4314#else
74d37793 4315 TCGv t0;
76db3ba4 4316 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4318 return;
4319 }
74d37793
AJ		 4320 t0 = tcg_temp_new();
4321 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4322 tcg_gen_andi_tl(t0, t0, 0xF);
f6b868fc 4323 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
74d37793 4324 tcg_temp_free(t0);
12de9a39
JM		 4325#endif
4326}
4327
4328/* mtsr */
c7697e1f 4329GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4330{
4331#if defined(CONFIG_USER_ONLY)
e06fcd75 4332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4333#else
74d37793 4334 TCGv t0;
76db3ba4 4335 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4337 return;
4338 }
74d37793 4339 t0 = tcg_const_tl(SR(ctx->opcode));
f6b868fc 4340 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4341 tcg_temp_free(t0);
12de9a39
JM		 4342#endif
4343}
4344
4345/* mtsrin */
c7697e1f
JM		 4346GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4347 PPC_SEGMENT_64B)
12de9a39
JM		 4348{
4349#if defined(CONFIG_USER_ONLY)
e06fcd75 4350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4351#else
74d37793 4352 TCGv t0;
76db3ba4 4353 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4355 return;
4356 }
74d37793
AJ		 4357 t0 = tcg_temp_new();
4358 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4359 tcg_gen_andi_tl(t0, t0, 0xF);
f6b868fc 4360 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4361 tcg_temp_free(t0);
12de9a39
JM		 4362#endif
4363}
f6b868fc
BS		 4364
4365/* slbmte */
4366GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B)
4367{
4368#if defined(CONFIG_USER_ONLY)
4369 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4370#else
4371 if (unlikely(!ctx->mem_idx)) {
4372 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4373 return;
4374 }
4375 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4376#endif
4377}
4378
12de9a39
JM		 4379#endif /* defined(TARGET_PPC64) */
4380
79aceca5 4381/*** Lookaside buffer management ***/
76db3ba4 4382/* Optional & mem_idx only: */
79aceca5 4383/* tlbia */
3fc6c082 4384GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4385{
9a64fbe4 4386#if defined(CONFIG_USER_ONLY)
e06fcd75 4387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4388#else
76db3ba4 4389 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4390 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4391 return;
9a64fbe4 4392 }
74d37793 4393 gen_helper_tlbia();
9a64fbe4 4394#endif
79aceca5
FB		 4395}
4396
4397/* tlbie */
76a66253 4398GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4399{
9a64fbe4 4400#if defined(CONFIG_USER_ONLY)
e06fcd75 4401 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4402#else
76db3ba4 4403 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4404 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4405 return;
9a64fbe4 4406 }
d9bce9d9 4407#if defined(TARGET_PPC64)
74d37793
AJ		 4408 if (!ctx->sf_mode) {
4409 TCGv t0 = tcg_temp_new();
4410 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4411 gen_helper_tlbie(t0);
4412 tcg_temp_free(t0);
4413 } else
d9bce9d9 4414#endif
74d37793 4415 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4416#endif
79aceca5
FB		 4417}
4418
4419/* tlbsync */
76a66253 4420GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4421{
9a64fbe4 4422#if defined(CONFIG_USER_ONLY)
e06fcd75 4423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4424#else
76db3ba4 4425 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4426 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4427 return;
9a64fbe4
FB		 4428 }
4429 /* This has no effect: it should ensure that all previous
4430 * tlbie have completed
4431 */
e06fcd75 4432 gen_stop_exception(ctx);
9a64fbe4 4433#endif
79aceca5
FB		 4434}
4435
426613db
JM		 4436#if defined(TARGET_PPC64)
4437/* slbia */
4438GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4439{
4440#if defined(CONFIG_USER_ONLY)
e06fcd75 4441 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4442#else
76db3ba4 4443 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4444 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4445 return;
4446 }
74d37793 4447 gen_helper_slbia();
426613db
JM		 4448#endif
4449}
4450
4451/* slbie */
4452GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4453{
4454#if defined(CONFIG_USER_ONLY)
e06fcd75 4455 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4456#else
76db3ba4 4457 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4458 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4459 return;
4460 }
74d37793 4461 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4462#endif
4463}
4464#endif
4465
79aceca5
FB		 4466/*** External control ***/
4467/* Optional: */
111bfab3 4468/* eciwx */
79aceca5
FB		 4469GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4470{
76db3ba4 4471 TCGv t0;
fa407c03 4472 /* Should check EAR[E] ! */
76db3ba4
AJ		 4473 gen_set_access_type(ctx, ACCESS_EXT);
4474 t0 = tcg_temp_new();
4475 gen_addr_reg_index(ctx, t0);
fa407c03 4476 gen_check_align(ctx, t0, 0x03);
76db3ba4 4477 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4478 tcg_temp_free(t0);
76a66253
JM		 4479}
4480
4481/* ecowx */
4482GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4483{
76db3ba4 4484 TCGv t0;
fa407c03 4485 /* Should check EAR[E] ! */
76db3ba4
AJ		 4486 gen_set_access_type(ctx, ACCESS_EXT);
4487 t0 = tcg_temp_new();
4488 gen_addr_reg_index(ctx, t0);
fa407c03 4489 gen_check_align(ctx, t0, 0x03);
76db3ba4 4490 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4491 tcg_temp_free(t0);
76a66253
JM		 4492}
4493
4494/* PowerPC 601 specific instructions */
4495/* abs - abs. */
4496GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4497{
22e0e173
AJ		 4498 int l1 = gen_new_label();
4499 int l2 = gen_new_label();
4500 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4501 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4502 tcg_gen_br(l2);
4503 gen_set_label(l1);
4504 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4505 gen_set_label(l2);
76a66253 4506 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4507 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4508}
4509
4510/* abso - abso. */
4511GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4512{
22e0e173
AJ		 4513 int l1 = gen_new_label();
4514 int l2 = gen_new_label();
4515 int l3 = gen_new_label();
4516 /* Start with XER OV disabled, the most likely case */
4517 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4518 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4519 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4520 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4521 tcg_gen_br(l2);
4522 gen_set_label(l1);
4523 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4524 tcg_gen_br(l3);
4525 gen_set_label(l2);
4526 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4527 gen_set_label(l3);
76a66253 4528 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4529 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4530}
4531
4532/* clcs */
a750fc0b 4533GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4534{
22e0e173
AJ		 4535 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4536 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4537 tcg_temp_free_i32(t0);
c7697e1f 4538 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4539}
4540
4541/* div - div. */
4542GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4543{
22e0e173 4544 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4545 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4546 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4547}
4548
4549/* divo - divo. */
4550GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4551{
22e0e173 4552 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4553 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4554 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4555}
4556
4557/* divs - divs. */
4558GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4559{
22e0e173 4560 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4561 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4562 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4563}
4564
4565/* divso - divso. */
4566GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4567{
22e0e173 4568 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4569 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4570 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4571}
4572
4573/* doz - doz. */
4574GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4575{
22e0e173
AJ		 4576 int l1 = gen_new_label();
4577 int l2 = gen_new_label();
4578 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4579 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4580 tcg_gen_br(l2);
4581 gen_set_label(l1);
4582 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4583 gen_set_label(l2);
76a66253 4584 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4585 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4586}
4587
4588/* dozo - dozo. */
4589GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4590{
22e0e173
AJ		 4591 int l1 = gen_new_label();
4592 int l2 = gen_new_label();
4593 TCGv t0 = tcg_temp_new();
4594 TCGv t1 = tcg_temp_new();
4595 TCGv t2 = tcg_temp_new();
4596 /* Start with XER OV disabled, the most likely case */
4597 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4598 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4599 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4600 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4601 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4602 tcg_gen_andc_tl(t1, t1, t2);
4603 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4604 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4605 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4606 tcg_gen_br(l2);
4607 gen_set_label(l1);
4608 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4609 gen_set_label(l2);
4610 tcg_temp_free(t0);
4611 tcg_temp_free(t1);
4612 tcg_temp_free(t2);
76a66253 4613 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4614 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4615}
4616
4617/* dozi */
4618GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4619{
22e0e173
AJ		 4620 target_long simm = SIMM(ctx->opcode);
4621 int l1 = gen_new_label();
4622 int l2 = gen_new_label();
4623 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4624 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4625 tcg_gen_br(l2);
4626 gen_set_label(l1);
4627 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4628 gen_set_label(l2);
4629 if (unlikely(Rc(ctx->opcode) != 0))
4630 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4631}
4632
76a66253
JM		 4633/* lscbx - lscbx. */
4634GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4635{
bdb4b689
AJ		 4636 TCGv t0 = tcg_temp_new();
4637 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4638 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4639 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4640
76db3ba4 4641 gen_addr_reg_index(ctx, t0);
76a66253 4642 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4643 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4644 gen_helper_lscbx(t0, t0, t1, t2, t3);
4645 tcg_temp_free_i32(t1);
4646 tcg_temp_free_i32(t2);
4647 tcg_temp_free_i32(t3);
3d7b417e 4648 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4649 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4650 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4651 gen_set_Rc0(ctx, t0);
4652 tcg_temp_free(t0);
76a66253
JM		 4653}
4654
4655/* maskg - maskg. */
4656GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4657{
22e0e173
AJ		 4658 int l1 = gen_new_label();
4659 TCGv t0 = tcg_temp_new();
4660 TCGv t1 = tcg_temp_new();
4661 TCGv t2 = tcg_temp_new();
4662 TCGv t3 = tcg_temp_new();
4663 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4664 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4665 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4666 tcg_gen_addi_tl(t2, t0, 1);
4667 tcg_gen_shr_tl(t2, t3, t2);
4668 tcg_gen_shr_tl(t3, t3, t1);
4669 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4670 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4671 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4672 gen_set_label(l1);
4673 tcg_temp_free(t0);
4674 tcg_temp_free(t1);
4675 tcg_temp_free(t2);
4676 tcg_temp_free(t3);
76a66253 4677 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4678 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4679}
4680
4681/* maskir - maskir. */
4682GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4683{
22e0e173
AJ		 4684 TCGv t0 = tcg_temp_new();
4685 TCGv t1 = tcg_temp_new();
4686 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4687 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4688 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4689 tcg_temp_free(t0);
4690 tcg_temp_free(t1);
76a66253 4691 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4692 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4693}
4694
4695/* mul - mul. */
4696GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4697{
22e0e173
AJ		 4698 TCGv_i64 t0 = tcg_temp_new_i64();
4699 TCGv_i64 t1 = tcg_temp_new_i64();
4700 TCGv t2 = tcg_temp_new();
4701 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4702 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4703 tcg_gen_mul_i64(t0, t0, t1);
4704 tcg_gen_trunc_i64_tl(t2, t0);
4705 gen_store_spr(SPR_MQ, t2);
4706 tcg_gen_shri_i64(t1, t0, 32);
4707 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4708 tcg_temp_free_i64(t0);
4709 tcg_temp_free_i64(t1);
4710 tcg_temp_free(t2);
76a66253 4711 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4712 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4713}
4714
4715/* mulo - mulo. */
4716GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4717{
22e0e173
AJ		 4718 int l1 = gen_new_label();
4719 TCGv_i64 t0 = tcg_temp_new_i64();
4720 TCGv_i64 t1 = tcg_temp_new_i64();
4721 TCGv t2 = tcg_temp_new();
4722 /* Start with XER OV disabled, the most likely case */
4723 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4724 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4725 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4726 tcg_gen_mul_i64(t0, t0, t1);
4727 tcg_gen_trunc_i64_tl(t2, t0);
4728 gen_store_spr(SPR_MQ, t2);
4729 tcg_gen_shri_i64(t1, t0, 32);
4730 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4731 tcg_gen_ext32s_i64(t1, t0);
4732 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4733 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4734 gen_set_label(l1);
4735 tcg_temp_free_i64(t0);
4736 tcg_temp_free_i64(t1);
4737 tcg_temp_free(t2);
76a66253 4738 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4739 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4740}
4741
4742/* nabs - nabs. */
4743GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4744{
22e0e173
AJ		 4745 int l1 = gen_new_label();
4746 int l2 = gen_new_label();
4747 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4748 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4749 tcg_gen_br(l2);
4750 gen_set_label(l1);
4751 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4752 gen_set_label(l2);
76a66253 4753 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4754 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4755}
4756
4757/* nabso - nabso. */
4758GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4759{
22e0e173
AJ		 4760 int l1 = gen_new_label();
4761 int l2 = gen_new_label();
4762 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4763 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4764 tcg_gen_br(l2);
4765 gen_set_label(l1);
4766 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4767 gen_set_label(l2);
4768 /* nabs never overflows */
4769 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4770 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4771 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4772}
4773
4774/* rlmi - rlmi. */
4775GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4776{
7487953d
AJ		 4777 uint32_t mb = MB(ctx->opcode);
4778 uint32_t me = ME(ctx->opcode);
4779 TCGv t0 = tcg_temp_new();
4780 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4781 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4782 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4783 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4784 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4785 tcg_temp_free(t0);
76a66253 4786 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4787 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4788}
4789
4790/* rrib - rrib. */
4791GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4792{
7487953d
AJ		 4793 TCGv t0 = tcg_temp_new();
4794 TCGv t1 = tcg_temp_new();
4795 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4796 tcg_gen_movi_tl(t1, 0x80000000);
4797 tcg_gen_shr_tl(t1, t1, t0);
4798 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4799 tcg_gen_and_tl(t0, t0, t1);
4800 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4801 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4802 tcg_temp_free(t0);
4803 tcg_temp_free(t1);
76a66253 4804 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4806}
4807
4808/* sle - sle. */
4809GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4810{
7487953d
AJ		 4811 TCGv t0 = tcg_temp_new();
4812 TCGv t1 = tcg_temp_new();
4813 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4814 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4815 tcg_gen_subfi_tl(t1, 32, t1);
4816 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4817 tcg_gen_or_tl(t1, t0, t1);
4818 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4819 gen_store_spr(SPR_MQ, t1);
4820 tcg_temp_free(t0);
4821 tcg_temp_free(t1);
76a66253 4822 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4823 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4824}
4825
4826/* sleq - sleq. */
4827GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4828{
7487953d
AJ		 4829 TCGv t0 = tcg_temp_new();
4830 TCGv t1 = tcg_temp_new();
4831 TCGv t2 = tcg_temp_new();
4832 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4833 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4834 tcg_gen_shl_tl(t2, t2, t0);
4835 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4836 gen_load_spr(t1, SPR_MQ);
4837 gen_store_spr(SPR_MQ, t0);
4838 tcg_gen_and_tl(t0, t0, t2);
4839 tcg_gen_andc_tl(t1, t1, t2);
4840 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4841 tcg_temp_free(t0);
4842 tcg_temp_free(t1);
4843 tcg_temp_free(t2);
76a66253 4844 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4845 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4846}
4847
4848/* sliq - sliq. */
4849GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4850{
7487953d
AJ		 4851 int sh = SH(ctx->opcode);
4852 TCGv t0 = tcg_temp_new();
4853 TCGv t1 = tcg_temp_new();
4854 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4855 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4856 tcg_gen_or_tl(t1, t0, t1);
4857 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4858 gen_store_spr(SPR_MQ, t1);
4859 tcg_temp_free(t0);
4860 tcg_temp_free(t1);
76a66253 4861 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4862 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4863}
4864
4865/* slliq - slliq. */
4866GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4867{
7487953d
AJ		 4868 int sh = SH(ctx->opcode);
4869 TCGv t0 = tcg_temp_new();
4870 TCGv t1 = tcg_temp_new();
4871 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4872 gen_load_spr(t1, SPR_MQ);
4873 gen_store_spr(SPR_MQ, t0);
4874 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4875 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4876 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4877 tcg_temp_free(t0);
4878 tcg_temp_free(t1);
76a66253 4879 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4881}
4882
4883/* sllq - sllq. */
4884GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4885{
7487953d
AJ		 4886 int l1 = gen_new_label();
4887 int l2 = gen_new_label();
4888 TCGv t0 = tcg_temp_local_new();
4889 TCGv t1 = tcg_temp_local_new();
4890 TCGv t2 = tcg_temp_local_new();
4891 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4892 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4893 tcg_gen_shl_tl(t1, t1, t2);
4894 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4895 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4896 gen_load_spr(t0, SPR_MQ);
4897 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4898 tcg_gen_br(l2);
4899 gen_set_label(l1);
4900 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4901 gen_load_spr(t2, SPR_MQ);
4902 tcg_gen_andc_tl(t1, t2, t1);
4903 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4904 gen_set_label(l2);
4905 tcg_temp_free(t0);
4906 tcg_temp_free(t1);
4907 tcg_temp_free(t2);
76a66253 4908 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4910}
4911
4912/* slq - slq. */
4913GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4914{
7487953d
AJ		 4915 int l1 = gen_new_label();
4916 TCGv t0 = tcg_temp_new();
4917 TCGv t1 = tcg_temp_new();
4918 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4919 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4920 tcg_gen_subfi_tl(t1, 32, t1);
4921 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4922 tcg_gen_or_tl(t1, t0, t1);
4923 gen_store_spr(SPR_MQ, t1);
4924 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4925 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4926 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4927 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4928 gen_set_label(l1);
4929 tcg_temp_free(t0);
4930 tcg_temp_free(t1);
76a66253 4931 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4932 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4933}
4934
d9bce9d9 4935/* sraiq - sraiq. */
76a66253
JM		 4936GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4937{
7487953d
AJ		 4938 int sh = SH(ctx->opcode);
4939 int l1 = gen_new_label();
4940 TCGv t0 = tcg_temp_new();
4941 TCGv t1 = tcg_temp_new();
4942 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4943 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4944 tcg_gen_or_tl(t0, t0, t1);
4945 gen_store_spr(SPR_MQ, t0);
4946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4947 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4948 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4949 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4950 gen_set_label(l1);
4951 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4952 tcg_temp_free(t0);
4953 tcg_temp_free(t1);
76a66253 4954 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4955 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4956}
4957
4958/* sraq - sraq. */
4959GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4960{
7487953d
AJ		 4961 int l1 = gen_new_label();
4962 int l2 = gen_new_label();
4963 TCGv t0 = tcg_temp_new();
4964 TCGv t1 = tcg_temp_local_new();
4965 TCGv t2 = tcg_temp_local_new();
4966 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4967 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4968 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4969 tcg_gen_subfi_tl(t2, 32, t2);
4970 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4971 tcg_gen_or_tl(t0, t0, t2);
4972 gen_store_spr(SPR_MQ, t0);
4973 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4974 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4975 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4976 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4977 gen_set_label(l1);
4978 tcg_temp_free(t0);
4979 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4980 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4981 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4982 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4983 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4984 gen_set_label(l2);
4985 tcg_temp_free(t1);
4986 tcg_temp_free(t2);
76a66253 4987 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4988 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4989}
4990
4991/* sre - sre. */
4992GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4993{
7487953d
AJ		 4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4997 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4998 tcg_gen_subfi_tl(t1, 32, t1);
4999 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5000 tcg_gen_or_tl(t1, t0, t1);
5001 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5002 gen_store_spr(SPR_MQ, t1);
5003 tcg_temp_free(t0);
5004 tcg_temp_free(t1);
76a66253 5005 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5006 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5007}
5008
5009/* srea - srea. */
5010GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
5011{
7487953d
AJ		 5012 TCGv t0 = tcg_temp_new();
5013 TCGv t1 = tcg_temp_new();
5014 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5015 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5016 gen_store_spr(SPR_MQ, t0);
5017 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5018 tcg_temp_free(t0);
5019 tcg_temp_free(t1);
76a66253 5020 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5021 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5022}
5023
5024/* sreq */
5025GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
5026{
7487953d
AJ		 5027 TCGv t0 = tcg_temp_new();
5028 TCGv t1 = tcg_temp_new();
5029 TCGv t2 = tcg_temp_new();
5030 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5031 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5032 tcg_gen_shr_tl(t1, t1, t0);
5033 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5034 gen_load_spr(t2, SPR_MQ);
5035 gen_store_spr(SPR_MQ, t0);
5036 tcg_gen_and_tl(t0, t0, t1);
5037 tcg_gen_andc_tl(t2, t2, t1);
5038 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5039 tcg_temp_free(t0);
5040 tcg_temp_free(t1);
5041 tcg_temp_free(t2);
76a66253 5042 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5043 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5044}
5045
5046/* sriq */
5047GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5048{
7487953d
AJ		 5049 int sh = SH(ctx->opcode);
5050 TCGv t0 = tcg_temp_new();
5051 TCGv t1 = tcg_temp_new();
5052 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5053 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5054 tcg_gen_or_tl(t1, t0, t1);
5055 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5056 gen_store_spr(SPR_MQ, t1);
5057 tcg_temp_free(t0);
5058 tcg_temp_free(t1);
76a66253 5059 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5060 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5061}
5062
5063/* srliq */
5064GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5065{
7487953d
AJ		 5066 int sh = SH(ctx->opcode);
5067 TCGv t0 = tcg_temp_new();
5068 TCGv t1 = tcg_temp_new();
5069 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5070 gen_load_spr(t1, SPR_MQ);
5071 gen_store_spr(SPR_MQ, t0);
5072 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5073 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5074 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5075 tcg_temp_free(t0);
5076 tcg_temp_free(t1);
76a66253 5077 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5079}
5080
5081/* srlq */
5082GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5083{
7487953d
AJ		 5084 int l1 = gen_new_label();
5085 int l2 = gen_new_label();
5086 TCGv t0 = tcg_temp_local_new();
5087 TCGv t1 = tcg_temp_local_new();
5088 TCGv t2 = tcg_temp_local_new();
5089 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5090 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5091 tcg_gen_shr_tl(t2, t1, t2);
5092 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5093 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5094 gen_load_spr(t0, SPR_MQ);
5095 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5096 tcg_gen_br(l2);
5097 gen_set_label(l1);
5098 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5099 tcg_gen_and_tl(t0, t0, t2);
5100 gen_load_spr(t1, SPR_MQ);
5101 tcg_gen_andc_tl(t1, t1, t2);
5102 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5103 gen_set_label(l2);
5104 tcg_temp_free(t0);
5105 tcg_temp_free(t1);
5106 tcg_temp_free(t2);
76a66253 5107 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5108 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5109}
5110
5111/* srq */
5112GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5113{
7487953d
AJ		 5114 int l1 = gen_new_label();
5115 TCGv t0 = tcg_temp_new();
5116 TCGv t1 = tcg_temp_new();
5117 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5118 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5119 tcg_gen_subfi_tl(t1, 32, t1);
5120 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5121 tcg_gen_or_tl(t1, t0, t1);
5122 gen_store_spr(SPR_MQ, t1);
5123 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5124 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5125 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5126 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5127 gen_set_label(l1);
5128 tcg_temp_free(t0);
5129 tcg_temp_free(t1);
76a66253 5130 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5131 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5132}
5133
5134/* PowerPC 602 specific instructions */
5135/* dsa */
5136GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5137{
5138 /* XXX: TODO */
e06fcd75 5139 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5140}
5141
5142/* esa */
5143GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5144{
5145 /* XXX: TODO */
e06fcd75 5146 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5147}
5148
5149/* mfrom */
5150GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5151{
5152#if defined(CONFIG_USER_ONLY)
e06fcd75 5153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5154#else
76db3ba4 5155 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5156 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5157 return;
5158 }
cf02a65c 5159 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5160#endif
5161}
5162
5163/* 602 - 603 - G2 TLB management */
5164/* tlbld */
c7697e1f 5165GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5166{
5167#if defined(CONFIG_USER_ONLY)
e06fcd75 5168 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5169#else
76db3ba4 5170 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5172 return;
5173 }
74d37793 5174 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5175#endif
5176}
5177
5178/* tlbli */
c7697e1f 5179GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5180{
5181#if defined(CONFIG_USER_ONLY)
e06fcd75 5182 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5183#else
76db3ba4 5184 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5186 return;
5187 }
74d37793 5188 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5189#endif
5190}
5191
7dbe11ac
JM		 5192/* 74xx TLB management */
5193/* tlbld */
c7697e1f 5194GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5195{
5196#if defined(CONFIG_USER_ONLY)
e06fcd75 5197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5198#else
76db3ba4 5199 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5201 return;
5202 }
74d37793 5203 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5204#endif
5205}
5206
5207/* tlbli */
c7697e1f 5208GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5209{
5210#if defined(CONFIG_USER_ONLY)
e06fcd75 5211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5212#else
76db3ba4 5213 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5215 return;
5216 }
74d37793 5217 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5218#endif
5219}
5220
76a66253
JM		 5221/* POWER instructions not in PowerPC 601 */
5222/* clf */
5223GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5224{
5225 /* Cache line flush: implemented as no-op */
5226}
5227
5228/* cli */
5229GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5230{
7f75ffd3 5231 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5232#if defined(CONFIG_USER_ONLY)
e06fcd75 5233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5234#else
76db3ba4 5235 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5237 return;
5238 }
5239#endif
5240}
5241
5242/* dclst */
5243GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5244{
5245 /* Data cache line store: treated as no-op */
5246}
5247
5248GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5249{
5250#if defined(CONFIG_USER_ONLY)
e06fcd75 5251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5252#else
74d37793
AJ		 5253 int ra = rA(ctx->opcode);
5254 int rd = rD(ctx->opcode);
5255 TCGv t0;
76db3ba4 5256 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5257 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5258 return;
5259 }
74d37793 5260 t0 = tcg_temp_new();
76db3ba4 5261 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5262 tcg_gen_shri_tl(t0, t0, 28);
5263 tcg_gen_andi_tl(t0, t0, 0xF);
5264 gen_helper_load_sr(cpu_gpr[rd], t0);
5265 tcg_temp_free(t0);
76a66253 5266 if (ra != 0 && ra != rd)
74d37793 5267 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5268#endif
5269}
5270
5271GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5272{
5273#if defined(CONFIG_USER_ONLY)
e06fcd75 5274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5275#else
22e0e173 5276 TCGv t0;
76db3ba4 5277 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5279 return;
5280 }
22e0e173 5281 t0 = tcg_temp_new();
76db3ba4 5282 gen_addr_reg_index(ctx, t0);
22e0e173
AJ		 5283 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5284 tcg_temp_free(t0);
76a66253
JM		 5285#endif
5286}
5287
5288GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5289{
5290#if defined(CONFIG_USER_ONLY)
e06fcd75 5291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5292#else
76db3ba4 5293 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5295 return;
5296 }
d72a19f7 5297 gen_helper_rfsvc();
e06fcd75 5298 gen_sync_exception(ctx);
76a66253
JM		 5299#endif
5300}
5301
5302/* svc is not implemented for now */
5303
5304/* POWER2 specific instructions */
5305/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5306
5307/* lfq */
5308GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5309{
01a4afeb 5310 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5311 TCGv t0;
5312 gen_set_access_type(ctx, ACCESS_FLOAT);
5313 t0 = tcg_temp_new();
5314 gen_addr_imm_index(ctx, t0, 0);
5315 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5316 gen_addr_add(ctx, t0, t0, 8);
5317 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5318 tcg_temp_free(t0);
76a66253
JM		 5319}
5320
5321/* lfqu */
5322GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5323{
5324 int ra = rA(ctx->opcode);
01a4afeb 5325 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5326 TCGv t0, t1;
5327 gen_set_access_type(ctx, ACCESS_FLOAT);
5328 t0 = tcg_temp_new();
5329 t1 = tcg_temp_new();
5330 gen_addr_imm_index(ctx, t0, 0);
5331 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5332 gen_addr_add(ctx, t1, t0, 8);
5333 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5334 if (ra != 0)
01a4afeb
AJ		 5335 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5336 tcg_temp_free(t0);
5337 tcg_temp_free(t1);
76a66253
JM		 5338}
5339
5340/* lfqux */
5341GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5342{
5343 int ra = rA(ctx->opcode);
01a4afeb 5344 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5345 gen_set_access_type(ctx, ACCESS_FLOAT);
5346 TCGv t0, t1;
5347 t0 = tcg_temp_new();
5348 gen_addr_reg_index(ctx, t0);
5349 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5350 t1 = tcg_temp_new();
5351 gen_addr_add(ctx, t1, t0, 8);
5352 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5353 tcg_temp_free(t1);
76a66253 5354 if (ra != 0)
01a4afeb
AJ		 5355 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5356 tcg_temp_free(t0);
76a66253
JM		 5357}
5358
5359/* lfqx */
5360GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5361{
01a4afeb 5362 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5363 TCGv t0;
5364 gen_set_access_type(ctx, ACCESS_FLOAT);
5365 t0 = tcg_temp_new();
5366 gen_addr_reg_index(ctx, t0);
5367 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5368 gen_addr_add(ctx, t0, t0, 8);
5369 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5370 tcg_temp_free(t0);
76a66253
JM		 5371}
5372
5373/* stfq */
5374GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5375{
01a4afeb 5376 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5377 TCGv t0;
5378 gen_set_access_type(ctx, ACCESS_FLOAT);
5379 t0 = tcg_temp_new();
5380 gen_addr_imm_index(ctx, t0, 0);
5381 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5382 gen_addr_add(ctx, t0, t0, 8);
5383 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5384 tcg_temp_free(t0);
76a66253
JM		 5385}
5386
5387/* stfqu */
5388GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5389{
5390 int ra = rA(ctx->opcode);
01a4afeb 5391 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5392 TCGv t0, t1;
5393 gen_set_access_type(ctx, ACCESS_FLOAT);
5394 t0 = tcg_temp_new();
5395 gen_addr_imm_index(ctx, t0, 0);
5396 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5397 t1 = tcg_temp_new();
5398 gen_addr_add(ctx, t1, t0, 8);
5399 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5400 tcg_temp_free(t1);
76a66253 5401 if (ra != 0)
01a4afeb
AJ		 5402 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5403 tcg_temp_free(t0);
76a66253
JM		 5404}
5405
5406/* stfqux */
5407GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5408{
5409 int ra = rA(ctx->opcode);
01a4afeb 5410 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5411 TCGv t0, t1;
5412 gen_set_access_type(ctx, ACCESS_FLOAT);
5413 t0 = tcg_temp_new();
5414 gen_addr_reg_index(ctx, t0);
5415 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5416 t1 = tcg_temp_new();
5417 gen_addr_add(ctx, t1, t0, 8);
5418 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5419 tcg_temp_free(t1);
76a66253 5420 if (ra != 0)
01a4afeb
AJ		 5421 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5422 tcg_temp_free(t0);
76a66253
JM		 5423}
5424
5425/* stfqx */
5426GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5427{
01a4afeb 5428 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5429 TCGv t0;
5430 gen_set_access_type(ctx, ACCESS_FLOAT);
5431 t0 = tcg_temp_new();
5432 gen_addr_reg_index(ctx, t0);
5433 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5434 gen_addr_add(ctx, t0, t0, 8);
5435 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5436 tcg_temp_free(t0);
76a66253
JM		 5437}
5438
5439/* BookE specific instructions */
2662a059 5440/* XXX: not implemented on 440 ? */
05332d70 5441GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5442{
5443 /* XXX: TODO */
e06fcd75 5444 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5445}
5446
2662a059 5447/* XXX: not implemented on 440 ? */
05332d70 5448GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5449{
5450#if defined(CONFIG_USER_ONLY)
e06fcd75 5451 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5452#else
74d37793 5453 TCGv t0;
76db3ba4 5454 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5455 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5456 return;
5457 }
ec72e276 5458 t0 = tcg_temp_new();
76db3ba4 5459 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5460 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5461 tcg_temp_free(t0);
76a66253
JM		 5462#endif
5463}
5464
5465/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5466static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5467 int opc2, int opc3,
5468 int ra, int rb, int rt, int Rc)
76a66253 5469{
182608d4
AJ		 5470 TCGv t0, t1;
5471
a7812ae4
PB		 5472 t0 = tcg_temp_local_new();
5473 t1 = tcg_temp_local_new();
182608d4 5474
76a66253
JM		 5475 switch (opc3 & 0x0D) {
5476 case 0x05:
5477 /* macchw - macchw. - macchwo - macchwo. */
5478 /* macchws - macchws. - macchwso - macchwso. */
5479 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5480 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5481 /* mulchw - mulchw. */
182608d4
AJ		 5482 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5483 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5484 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5485 break;
5486 case 0x04:
5487 /* macchwu - macchwu. - macchwuo - macchwuo. */
5488 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5489 /* mulchwu - mulchwu. */
182608d4
AJ		 5490 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5491 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5492 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5493 break;
5494 case 0x01:
5495 /* machhw - machhw. - machhwo - machhwo. */
5496 /* machhws - machhws. - machhwso - machhwso. */
5497 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5498 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5499 /* mulhhw - mulhhw. */
182608d4
AJ		 5500 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5501 tcg_gen_ext16s_tl(t0, t0);
5502 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5503 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5504 break;
5505 case 0x00:
5506 /* machhwu - machhwu. - machhwuo - machhwuo. */
5507 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5508 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5509 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5510 tcg_gen_ext16u_tl(t0, t0);
5511 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5512 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5513 break;
5514 case 0x0D:
5515 /* maclhw - maclhw. - maclhwo - maclhwo. */
5516 /* maclhws - maclhws. - maclhwso - maclhwso. */
5517 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5518 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5519 /* mullhw - mullhw. */
182608d4
AJ		 5520 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5521 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5522 break;
5523 case 0x0C:
5524 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5525 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5526 /* mullhwu - mullhwu. */
182608d4
AJ		 5527 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5528 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5529 break;
5530 }
76a66253 5531 if (opc2 & 0x04) {
182608d4
AJ		 5532 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5533 tcg_gen_mul_tl(t1, t0, t1);
5534 if (opc2 & 0x02) {
5535 /* nmultiply-and-accumulate (0x0E) */
5536 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5537 } else {
5538 /* multiply-and-accumulate (0x0C) */
5539 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5540 }
5541
5542 if (opc3 & 0x12) {
5543 /* Check overflow and/or saturate */
5544 int l1 = gen_new_label();
5545
5546 if (opc3 & 0x10) {
5547 /* Start with XER OV disabled, the most likely case */
5548 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5549 }
5550 if (opc3 & 0x01) {
5551 /* Signed */
5552 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5553 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5554 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5555 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5556 if (opc3 & 0x02) {
182608d4
AJ		 5557 /* Saturate */
5558 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5559 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5560 }
5561 } else {
5562 /* Unsigned */
5563 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5564 if (opc3 & 0x02) {
182608d4
AJ		 5565 /* Saturate */
5566 tcg_gen_movi_tl(t0, UINT32_MAX);
5567 }
5568 }
5569 if (opc3 & 0x10) {
5570 /* Check overflow */
5571 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5572 }
5573 gen_set_label(l1);
5574 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5575 }
5576 } else {
5577 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5578 }
182608d4
AJ		 5579 tcg_temp_free(t0);
5580 tcg_temp_free(t1);
76a66253
JM		 5581 if (unlikely(Rc) != 0) {
5582 /* Update Rc0 */
182608d4 5583 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5584 }
5585}
5586
a750fc0b
JM		 5587#define GEN_MAC_HANDLER(name, opc2, opc3) \
5588GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5589{ \
5590 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5591 rD(ctx->opcode), Rc(ctx->opcode)); \
5592}
5593
5594/* macchw - macchw. */
a750fc0b 5595GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5596/* macchwo - macchwo. */
a750fc0b 5597GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5598/* macchws - macchws. */
a750fc0b 5599GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5600/* macchwso - macchwso. */
a750fc0b 5601GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5602/* macchwsu - macchwsu. */
a750fc0b 5603GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5604/* macchwsuo - macchwsuo. */
a750fc0b 5605GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5606/* macchwu - macchwu. */
a750fc0b 5607GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5608/* macchwuo - macchwuo. */
a750fc0b 5609GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5610/* machhw - machhw. */
a750fc0b 5611GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5612/* machhwo - machhwo. */
a750fc0b 5613GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5614/* machhws - machhws. */
a750fc0b 5615GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5616/* machhwso - machhwso. */
a750fc0b 5617GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5618/* machhwsu - machhwsu. */
a750fc0b 5619GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5620/* machhwsuo - machhwsuo. */
a750fc0b 5621GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5622/* machhwu - machhwu. */
a750fc0b 5623GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5624/* machhwuo - machhwuo. */
a750fc0b 5625GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5626/* maclhw - maclhw. */
a750fc0b 5627GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5628/* maclhwo - maclhwo. */
a750fc0b 5629GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5630/* maclhws - maclhws. */
a750fc0b 5631GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5632/* maclhwso - maclhwso. */
a750fc0b 5633GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5634/* maclhwu - maclhwu. */
a750fc0b 5635GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5636/* maclhwuo - maclhwuo. */
a750fc0b 5637GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5638/* maclhwsu - maclhwsu. */
a750fc0b 5639GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5640/* maclhwsuo - maclhwsuo. */
a750fc0b 5641GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5642/* nmacchw - nmacchw. */
a750fc0b 5643GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5644/* nmacchwo - nmacchwo. */
a750fc0b 5645GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5646/* nmacchws - nmacchws. */
a750fc0b 5647GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5648/* nmacchwso - nmacchwso. */
a750fc0b 5649GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5650/* nmachhw - nmachhw. */
a750fc0b 5651GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5652/* nmachhwo - nmachhwo. */
a750fc0b 5653GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5654/* nmachhws - nmachhws. */
a750fc0b 5655GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5656/* nmachhwso - nmachhwso. */
a750fc0b 5657GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5658/* nmaclhw - nmaclhw. */
a750fc0b 5659GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5660/* nmaclhwo - nmaclhwo. */
a750fc0b 5661GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5662/* nmaclhws - nmaclhws. */
a750fc0b 5663GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5664/* nmaclhwso - nmaclhwso. */
a750fc0b 5665GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5666
5667/* mulchw - mulchw. */
a750fc0b 5668GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5669/* mulchwu - mulchwu. */
a750fc0b 5670GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5671/* mulhhw - mulhhw. */
a750fc0b 5672GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5673/* mulhhwu - mulhhwu. */
a750fc0b 5674GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5675/* mullhw - mullhw. */
a750fc0b 5676GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5677/* mullhwu - mullhwu. */
a750fc0b 5678GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5679
5680/* mfdcr */
05332d70 5681GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5682{
5683#if defined(CONFIG_USER_ONLY)
e06fcd75 5684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5685#else
06dca6a7 5686 TCGv dcrn;
76db3ba4 5687 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5689 return;
5690 }
06dca6a7
AJ		 5691 /* NIP cannot be restored if the memory exception comes from an helper */
5692 gen_update_nip(ctx, ctx->nip - 4);
5693 dcrn = tcg_const_tl(SPR(ctx->opcode));
5694 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5695 tcg_temp_free(dcrn);
76a66253
JM		 5696#endif
5697}
5698
5699/* mtdcr */
05332d70 5700GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5701{
5702#if defined(CONFIG_USER_ONLY)
e06fcd75 5703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5704#else
06dca6a7 5705 TCGv dcrn;
76db3ba4 5706 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5707 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5708 return;
5709 }
06dca6a7
AJ		 5710 /* NIP cannot be restored if the memory exception comes from an helper */
5711 gen_update_nip(ctx, ctx->nip - 4);
5712 dcrn = tcg_const_tl(SPR(ctx->opcode));
5713 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5714 tcg_temp_free(dcrn);
a42bd6cc
JM		 5715#endif
5716}
5717
5718/* mfdcrx */
2662a059 5719/* XXX: not implemented on 440 ? */
05332d70 5720GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5721{
5722#if defined(CONFIG_USER_ONLY)
e06fcd75 5723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5724#else
76db3ba4 5725 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5727 return;
5728 }
06dca6a7
AJ		 5729 /* NIP cannot be restored if the memory exception comes from an helper */
5730 gen_update_nip(ctx, ctx->nip - 4);
5731 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5732 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5733#endif
5734}
5735
5736/* mtdcrx */
2662a059 5737/* XXX: not implemented on 440 ? */
05332d70 5738GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5739{
5740#if defined(CONFIG_USER_ONLY)
e06fcd75 5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5742#else
76db3ba4 5743 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5745 return;
5746 }
06dca6a7
AJ		 5747 /* NIP cannot be restored if the memory exception comes from an helper */
5748 gen_update_nip(ctx, ctx->nip - 4);
5749 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5750 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5751#endif
5752}
5753
a750fc0b
JM		 5754/* mfdcrux (PPC 460) : user-mode access to DCR */
5755GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5756{
06dca6a7
AJ		 5757 /* NIP cannot be restored if the memory exception comes from an helper */
5758 gen_update_nip(ctx, ctx->nip - 4);
5759 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5760 /* Note: Rc update flag set leads to undefined state of Rc0 */
5761}
5762
5763/* mtdcrux (PPC 460) : user-mode access to DCR */
5764GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5765{
06dca6a7
AJ		 5766 /* NIP cannot be restored if the memory exception comes from an helper */
5767 gen_update_nip(ctx, ctx->nip - 4);
5768 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5769 /* Note: Rc update flag set leads to undefined state of Rc0 */
5770}
5771
76a66253
JM		 5772/* dccci */
5773GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5774{
5775#if defined(CONFIG_USER_ONLY)
e06fcd75 5776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5777#else
76db3ba4 5778 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5780 return;
5781 }
5782 /* interpreted as no-op */
5783#endif
5784}
5785
5786/* dcread */
5787GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5788{
5789#if defined(CONFIG_USER_ONLY)
e06fcd75 5790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5791#else
b61f2753 5792 TCGv EA, val;
76db3ba4 5793 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5795 return;
5796 }
76db3ba4 5797 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5798 EA = tcg_temp_new();
76db3ba4 5799 gen_addr_reg_index(ctx, EA);
a7812ae4 5800 val = tcg_temp_new();
76db3ba4 5801 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5802 tcg_temp_free(val);
5803 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5804 tcg_temp_free(EA);
76a66253
JM		 5805#endif
5806}
5807
5808/* icbt */
c7697e1f 5809GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5810{
5811 /* interpreted as no-op */
5812 /* XXX: specification say this is treated as a load by the MMU
5813 * but does not generate any exception
5814 */
5815}
5816
5817/* iccci */
5818GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5819{
5820#if defined(CONFIG_USER_ONLY)
e06fcd75 5821 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5822#else
76db3ba4 5823 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5825 return;
5826 }
5827 /* interpreted as no-op */
5828#endif
5829}
5830
5831/* icread */
5832GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5833{
5834#if defined(CONFIG_USER_ONLY)
e06fcd75 5835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5836#else
76db3ba4 5837 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5839 return;
5840 }
5841 /* interpreted as no-op */
5842#endif
5843}
5844
76db3ba4 5845/* rfci (mem_idx only) */
c7697e1f 5846GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5847{
5848#if defined(CONFIG_USER_ONLY)
e06fcd75 5849 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5850#else
76db3ba4 5851 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5852 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5853 return;
5854 }
5855 /* Restore CPU state */
d72a19f7 5856 gen_helper_40x_rfci();
e06fcd75 5857 gen_sync_exception(ctx);
a42bd6cc
JM		 5858#endif
5859}
5860
5861GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5862{
5863#if defined(CONFIG_USER_ONLY)
e06fcd75 5864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5865#else
76db3ba4 5866 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5867 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5868 return;
5869 }
5870 /* Restore CPU state */
d72a19f7 5871 gen_helper_rfci();
e06fcd75 5872 gen_sync_exception(ctx);
a42bd6cc
JM		 5873#endif
5874}
5875
5876/* BookE specific */
2662a059 5877/* XXX: not implemented on 440 ? */
05332d70 5878GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5879{
5880#if defined(CONFIG_USER_ONLY)
e06fcd75 5881 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5882#else
76db3ba4 5883 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5884 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5885 return;
5886 }
5887 /* Restore CPU state */
d72a19f7 5888 gen_helper_rfdi();
e06fcd75 5889 gen_sync_exception(ctx);
76a66253
JM		 5890#endif
5891}
5892
2662a059 5893/* XXX: not implemented on 440 ? */
a750fc0b 5894GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5895{
5896#if defined(CONFIG_USER_ONLY)
e06fcd75 5897 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5898#else
76db3ba4 5899 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5900 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5901 return;
5902 }
5903 /* Restore CPU state */
d72a19f7 5904 gen_helper_rfmci();
e06fcd75 5905 gen_sync_exception(ctx);
a42bd6cc
JM		 5906#endif
5907}
5eb7995e 5908
d9bce9d9 5909/* TLB management - PowerPC 405 implementation */
76a66253 5910/* tlbre */
c7697e1f 5911GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5912{
5913#if defined(CONFIG_USER_ONLY)
e06fcd75 5914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5915#else
76db3ba4 5916 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5918 return;
5919 }
5920 switch (rB(ctx->opcode)) {
5921 case 0:
74d37793 5922 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5923 break;
5924 case 1:
74d37793 5925 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5926 break;
5927 default:
e06fcd75 5928 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5929 break;
9a64fbe4 5930 }
76a66253
JM		 5931#endif
5932}
5933
d9bce9d9 5934/* tlbsx - tlbsx. */
c7697e1f 5935GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5936{
5937#if defined(CONFIG_USER_ONLY)
e06fcd75 5938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5939#else
74d37793 5940 TCGv t0;
76db3ba4 5941 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5942 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5943 return;
5944 }
74d37793 5945 t0 = tcg_temp_new();
76db3ba4 5946 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5947 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5948 tcg_temp_free(t0);
5949 if (Rc(ctx->opcode)) {
5950 int l1 = gen_new_label();
5951 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5952 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5953 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5954 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5955 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5956 gen_set_label(l1);
5957 }
76a66253 5958#endif
79aceca5
FB		 5959}
5960
76a66253 5961/* tlbwe */
c7697e1f 5962GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5963{
76a66253 5964#if defined(CONFIG_USER_ONLY)
e06fcd75 5965 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5966#else
76db3ba4 5967 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5968 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5969 return;
5970 }
5971 switch (rB(ctx->opcode)) {
5972 case 0:
74d37793 5973 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5974 break;
5975 case 1:
74d37793 5976 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5977 break;
5978 default:
e06fcd75 5979 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5980 break;
9a64fbe4 5981 }
76a66253
JM		 5982#endif
5983}
5984
a4bb6c3e 5985/* TLB management - PowerPC 440 implementation */
5eb7995e 5986/* tlbre */
c7697e1f 5987GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5988{
5989#if defined(CONFIG_USER_ONLY)
e06fcd75 5990 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5991#else
76db3ba4 5992 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5993 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5994 return;
5995 }
5996 switch (rB(ctx->opcode)) {
5997 case 0:
5eb7995e 5998 case 1:
5eb7995e 5999 case 2:
74d37793
AJ		 6000 {
6001 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6002 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6003 tcg_temp_free_i32(t0);
6004 }
5eb7995e
JM		 6005 break;
6006 default:
e06fcd75 6007 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6008 break;
6009 }
6010#endif
6011}
6012
6013/* tlbsx - tlbsx. */
c7697e1f 6014GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 6015{
6016#if defined(CONFIG_USER_ONLY)
e06fcd75 6017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6018#else
74d37793 6019 TCGv t0;
76db3ba4 6020 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6021 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6022 return;
6023 }
74d37793 6024 t0 = tcg_temp_new();
76db3ba4 6025 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 6026 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6027 tcg_temp_free(t0);
6028 if (Rc(ctx->opcode)) {
6029 int l1 = gen_new_label();
6030 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6031 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6032 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6033 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6034 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6035 gen_set_label(l1);
6036 }
5eb7995e
JM		 6037#endif
6038}
6039
6040/* tlbwe */
c7697e1f 6041GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 6042{
6043#if defined(CONFIG_USER_ONLY)
e06fcd75 6044 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6045#else
76db3ba4 6046 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6048 return;
6049 }
6050 switch (rB(ctx->opcode)) {
6051 case 0:
5eb7995e 6052 case 1:
5eb7995e 6053 case 2:
74d37793
AJ		 6054 {
6055 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6056 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6057 tcg_temp_free_i32(t0);
6058 }
5eb7995e
JM		 6059 break;
6060 default:
e06fcd75 6061 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6062 break;
6063 }
6064#endif
6065}
6066
76a66253 6067/* wrtee */
05332d70 6068GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6069{
6070#if defined(CONFIG_USER_ONLY)
e06fcd75 6071 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6072#else
6527f6ea 6073 TCGv t0;
76db3ba4 6074 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6075 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6076 return;
6077 }
6527f6ea
AJ		 6078 t0 = tcg_temp_new();
6079 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6080 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6081 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6082 tcg_temp_free(t0);
dee96f6c
JM		 6083 /* Stop translation to have a chance to raise an exception
6084 * if we just set msr_ee to 1
6085 */
e06fcd75 6086 gen_stop_exception(ctx);
76a66253
JM		 6087#endif
6088}
6089
6090/* wrteei */
05332d70 6091GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6092{
6093#if defined(CONFIG_USER_ONLY)
e06fcd75 6094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6095#else
76db3ba4 6096 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6098 return;
6099 }
6527f6ea
AJ		 6100 if (ctx->opcode & 0x00010000) {
6101 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6102 /* Stop translation to have a chance to raise an exception */
e06fcd75 6103 gen_stop_exception(ctx);
6527f6ea 6104 } else {
1b6e5f99 6105 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6106 }
76a66253
JM		 6107#endif
6108}
6109
08e46e54 6110/* PowerPC 440 specific instructions */
76a66253
JM		 6111/* dlmzb */
6112GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6113{
ef0d51af
AJ		 6114 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6115 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6116 cpu_gpr[rB(ctx->opcode)], t0);
6117 tcg_temp_free_i32(t0);
76a66253
JM		 6118}
6119
6120/* mbar replaces eieio on 440 */
26370046 6121GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
76a66253
JM		 6122{
6123 /* interpreted as no-op */
6124}
6125
6126/* msync replaces sync on 440 */
0db1b20e 6127GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6128{
6129 /* interpreted as no-op */
6130}
6131
6132/* icbt */
c7697e1f 6133GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6134{
6135 /* interpreted as no-op */
6136 /* XXX: specification say this is treated as a load by the MMU
6137 * but does not generate any exception
6138 */
79aceca5
FB		 6139}
6140
a9d9eb8f
JM		 6141/*** Altivec vector extension ***/
6142/* Altivec registers moves */
a9d9eb8f 6143
564e571a
AJ		 6144static always_inline TCGv_ptr gen_avr_ptr(int reg)
6145{
e4704b3b 6146 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6147 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6148 return r;
6149}
6150
a9d9eb8f 6151#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6152GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6153{ \
fe1e5c53 6154 TCGv EA; \
a9d9eb8f 6155 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6156 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6157 return; \
6158 } \
76db3ba4 6159 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6160 EA = tcg_temp_new(); \
76db3ba4 6161 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6162 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6163 if (ctx->le_mode) { \
6164 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6165 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6166 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6167 } else { \
76db3ba4 6168 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6169 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6170 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6171 } \
6172 tcg_temp_free(EA); \
a9d9eb8f
JM		 6173}
6174
6175#define GEN_VR_STX(name, opc2, opc3) \
6176GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6177{ \
fe1e5c53 6178 TCGv EA; \
a9d9eb8f 6179 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6180 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6181 return; \
6182 } \
76db3ba4 6183 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6184 EA = tcg_temp_new(); \
76db3ba4 6185 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6186 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6187 if (ctx->le_mode) { \
6188 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6189 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6190 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6191 } else { \
76db3ba4 6192 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6193 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6194 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6195 } \
6196 tcg_temp_free(EA); \
a9d9eb8f
JM		 6197}
6198
cbfb6ae9
AJ		 6199#define GEN_VR_LVE(name, opc2, opc3) \
6200 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6201 { \
6202 TCGv EA; \
6203 TCGv_ptr rs; \
6204 if (unlikely(!ctx->altivec_enabled)) { \
6205 gen_exception(ctx, POWERPC_EXCP_VPU); \
6206 return; \
6207 } \
6208 gen_set_access_type(ctx, ACCESS_INT); \
6209 EA = tcg_temp_new(); \
6210 gen_addr_reg_index(ctx, EA); \
6211 rs = gen_avr_ptr(rS(ctx->opcode)); \
6212 gen_helper_lve##name (rs, EA); \
6213 tcg_temp_free(EA); \
6214 tcg_temp_free_ptr(rs); \
6215 }
6216
6217#define GEN_VR_STVE(name, opc2, opc3) \
6218 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6219 { \
6220 TCGv EA; \
6221 TCGv_ptr rs; \
6222 if (unlikely(!ctx->altivec_enabled)) { \
6223 gen_exception(ctx, POWERPC_EXCP_VPU); \
6224 return; \
6225 } \
6226 gen_set_access_type(ctx, ACCESS_INT); \
6227 EA = tcg_temp_new(); \
6228 gen_addr_reg_index(ctx, EA); \
6229 rs = gen_avr_ptr(rS(ctx->opcode)); \
6230 gen_helper_stve##name (rs, EA); \
6231 tcg_temp_free(EA); \
6232 tcg_temp_free_ptr(rs); \
6233 }
6234
fe1e5c53 6235GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6236/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6237GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6238
cbfb6ae9
AJ		 6239GEN_VR_LVE(bx, 0x07, 0x00);
6240GEN_VR_LVE(hx, 0x07, 0x01);
6241GEN_VR_LVE(wx, 0x07, 0x02);
6242
fe1e5c53 6243GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6244/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6245GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6246
cbfb6ae9
AJ		 6247GEN_VR_STVE(bx, 0x07, 0x04);
6248GEN_VR_STVE(hx, 0x07, 0x05);
6249GEN_VR_STVE(wx, 0x07, 0x06);
6250
bf8d8ded
AJ		 6251GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6252{
6253 TCGv_ptr rd;
6254 TCGv EA;
6255 if (unlikely(!ctx->altivec_enabled)) {
6256 gen_exception(ctx, POWERPC_EXCP_VPU);
6257 return;
6258 }
6259 EA = tcg_temp_new();
6260 gen_addr_reg_index(ctx, EA);
6261 rd = gen_avr_ptr(rD(ctx->opcode));
6262 gen_helper_lvsl(rd, EA);
6263 tcg_temp_free(EA);
6264 tcg_temp_free_ptr(rd);
6265}
6266
6267GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6268{
6269 TCGv_ptr rd;
6270 TCGv EA;
6271 if (unlikely(!ctx->altivec_enabled)) {
6272 gen_exception(ctx, POWERPC_EXCP_VPU);
6273 return;
6274 }
6275 EA = tcg_temp_new();
6276 gen_addr_reg_index(ctx, EA);
6277 rd = gen_avr_ptr(rD(ctx->opcode));
6278 gen_helper_lvsr(rd, EA);
6279 tcg_temp_free(EA);
6280 tcg_temp_free_ptr(rd);
6281}
6282
785f451b
AJ		 6283GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6284{
6285 TCGv_i32 t;
6286 if (unlikely(!ctx->altivec_enabled)) {
6287 gen_exception(ctx, POWERPC_EXCP_VPU);
6288 return;
6289 }
6290 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6291 t = tcg_temp_new_i32();
6292 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6293 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6294 tcg_temp_free_i32(t);
785f451b
AJ		 6295}
6296
6297GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6298{
6e87b7c7 6299 TCGv_ptr p;
785f451b
AJ		 6300 if (unlikely(!ctx->altivec_enabled)) {
6301 gen_exception(ctx, POWERPC_EXCP_VPU);
6302 return;
6303 }
6e87b7c7
AJ		 6304 p = gen_avr_ptr(rD(ctx->opcode));
6305 gen_helper_mtvscr(p);
6306 tcg_temp_free_ptr(p);
785f451b
AJ		 6307}
6308
7a9b96cf
AJ		 6309/* Logical operations */
6310#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6311GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6312{ \
6313 if (unlikely(!ctx->altivec_enabled)) { \
6314 gen_exception(ctx, POWERPC_EXCP_VPU); \
6315 return; \
6316 } \
6317 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6318 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6319}
6320
6321GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6322GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6323GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6324GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6325GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6326
8e27dd6f
AJ		 6327#define GEN_VXFORM(name, opc2, opc3) \
6328GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6329{ \
6330 TCGv_ptr ra, rb, rd; \
6331 if (unlikely(!ctx->altivec_enabled)) { \
6332 gen_exception(ctx, POWERPC_EXCP_VPU); \
6333 return; \
6334 } \
6335 ra = gen_avr_ptr(rA(ctx->opcode)); \
6336 rb = gen_avr_ptr(rB(ctx->opcode)); \
6337 rd = gen_avr_ptr(rD(ctx->opcode)); \
6338 gen_helper_##name (rd, ra, rb); \
6339 tcg_temp_free_ptr(ra); \
6340 tcg_temp_free_ptr(rb); \
6341 tcg_temp_free_ptr(rd); \
6342}
6343
7872c51c
AJ		 6344GEN_VXFORM(vaddubm, 0, 0);
6345GEN_VXFORM(vadduhm, 0, 1);
6346GEN_VXFORM(vadduwm, 0, 2);
6347GEN_VXFORM(vsububm, 0, 16);
6348GEN_VXFORM(vsubuhm, 0, 17);
6349GEN_VXFORM(vsubuwm, 0, 18);
e4039339
AJ		 6350GEN_VXFORM(vmaxub, 1, 0);
6351GEN_VXFORM(vmaxuh, 1, 1);
6352GEN_VXFORM(vmaxuw, 1, 2);
6353GEN_VXFORM(vmaxsb, 1, 4);
6354GEN_VXFORM(vmaxsh, 1, 5);
6355GEN_VXFORM(vmaxsw, 1, 6);
6356GEN_VXFORM(vminub, 1, 8);
6357GEN_VXFORM(vminuh, 1, 9);
6358GEN_VXFORM(vminuw, 1, 10);
6359GEN_VXFORM(vminsb, 1, 12);
6360GEN_VXFORM(vminsh, 1, 13);
6361GEN_VXFORM(vminsw, 1, 14);
fab3cbe9
AJ		 6362GEN_VXFORM(vavgub, 1, 16);
6363GEN_VXFORM(vavguh, 1, 17);
6364GEN_VXFORM(vavguw, 1, 18);
6365GEN_VXFORM(vavgsb, 1, 20);
6366GEN_VXFORM(vavgsh, 1, 21);
6367GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 6368GEN_VXFORM(vmrghb, 6, 0);
6369GEN_VXFORM(vmrghh, 6, 1);
6370GEN_VXFORM(vmrghw, 6, 2);
6371GEN_VXFORM(vmrglb, 6, 4);
6372GEN_VXFORM(vmrglh, 6, 5);
6373GEN_VXFORM(vmrglw, 6, 6);
2c277908
AJ		 6374GEN_VXFORM(vmuloub, 4, 0);
6375GEN_VXFORM(vmulouh, 4, 1);
6376GEN_VXFORM(vmulosb, 4, 4);
6377GEN_VXFORM(vmulosh, 4, 5);
6378GEN_VXFORM(vmuleub, 4, 8);
6379GEN_VXFORM(vmuleuh, 4, 9);
6380GEN_VXFORM(vmulesb, 4, 12);
6381GEN_VXFORM(vmulesh, 4, 13);
d79f0809
AJ		 6382GEN_VXFORM(vslb, 2, 4);
6383GEN_VXFORM(vslh, 2, 5);
6384GEN_VXFORM(vslw, 2, 6);
07ef34c3
AJ		 6385GEN_VXFORM(vsrb, 2, 8);
6386GEN_VXFORM(vsrh, 2, 9);
6387GEN_VXFORM(vsrw, 2, 10);
6388GEN_VXFORM(vsrab, 2, 12);
6389GEN_VXFORM(vsrah, 2, 13);
6390GEN_VXFORM(vsraw, 2, 14);
7b239bec
AJ		 6391GEN_VXFORM(vslo, 6, 16);
6392GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 6393GEN_VXFORM(vaddcuw, 0, 6);
6394GEN_VXFORM(vsubcuw, 0, 22);
5ab09f33
AJ		 6395GEN_VXFORM(vaddubs, 0, 8);
6396GEN_VXFORM(vadduhs, 0, 9);
6397GEN_VXFORM(vadduws, 0, 10);
6398GEN_VXFORM(vaddsbs, 0, 12);
6399GEN_VXFORM(vaddshs, 0, 13);
6400GEN_VXFORM(vaddsws, 0, 14);
6401GEN_VXFORM(vsububs, 0, 24);
6402GEN_VXFORM(vsubuhs, 0, 25);
6403GEN_VXFORM(vsubuws, 0, 26);
6404GEN_VXFORM(vsubsbs, 0, 28);
6405GEN_VXFORM(vsubshs, 0, 29);
6406GEN_VXFORM(vsubsws, 0, 30);
5e1d0985
AJ		 6407GEN_VXFORM(vrlb, 2, 0);
6408GEN_VXFORM(vrlh, 2, 1);
6409GEN_VXFORM(vrlw, 2, 2);
d9430add
AJ		 6410GEN_VXFORM(vsl, 2, 7);
6411GEN_VXFORM(vsr, 2, 11);
5335a145
AJ		 6412GEN_VXFORM(vpkuhum, 7, 0);
6413GEN_VXFORM(vpkuwum, 7, 1);
6414GEN_VXFORM(vpkuhus, 7, 2);
6415GEN_VXFORM(vpkuwus, 7, 3);
6416GEN_VXFORM(vpkshus, 7, 4);
6417GEN_VXFORM(vpkswus, 7, 5);
6418GEN_VXFORM(vpkshss, 7, 6);
6419GEN_VXFORM(vpkswss, 7, 7);
1dd9ffb9 6420GEN_VXFORM(vpkpx, 7, 12);
8142cddd
AJ		 6421GEN_VXFORM(vsum4ubs, 4, 24);
6422GEN_VXFORM(vsum4sbs, 4, 28);
6423GEN_VXFORM(vsum4shs, 4, 25);
6424GEN_VXFORM(vsum2sws, 4, 26);
6425GEN_VXFORM(vsumsws, 4, 30);
56fdd213
AJ		 6426GEN_VXFORM(vaddfp, 5, 0);
6427GEN_VXFORM(vsubfp, 5, 1);
1536ff64
AJ		 6428GEN_VXFORM(vmaxfp, 5, 16);
6429GEN_VXFORM(vminfp, 5, 17);
fab3cbe9 6430
0cbcd906
AJ		 6431#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6432 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6433 { \
6434 TCGv_ptr ra, rb, rd; \
6435 if (unlikely(!ctx->altivec_enabled)) { \
6436 gen_exception(ctx, POWERPC_EXCP_VPU); \
6437 return; \
6438 } \
6439 ra = gen_avr_ptr(rA(ctx->opcode)); \
6440 rb = gen_avr_ptr(rB(ctx->opcode)); \
6441 rd = gen_avr_ptr(rD(ctx->opcode)); \
6442 gen_helper_##opname (rd, ra, rb); \
6443 tcg_temp_free_ptr(ra); \
6444 tcg_temp_free_ptr(rb); \
6445 tcg_temp_free_ptr(rd); \
6446 }
6447
6448#define GEN_VXRFORM(name, opc2, opc3) \
6449 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6450 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6451
1add6e23
AJ		 6452GEN_VXRFORM(vcmpequb, 3, 0)
6453GEN_VXRFORM(vcmpequh, 3, 1)
6454GEN_VXRFORM(vcmpequw, 3, 2)
6455GEN_VXRFORM(vcmpgtsb, 3, 12)
6456GEN_VXRFORM(vcmpgtsh, 3, 13)
6457GEN_VXRFORM(vcmpgtsw, 3, 14)
6458GEN_VXRFORM(vcmpgtub, 3, 8)
6459GEN_VXRFORM(vcmpgtuh, 3, 9)
6460GEN_VXRFORM(vcmpgtuw, 3, 10)
819ca121
AJ		 6461GEN_VXRFORM(vcmpeqfp, 3, 3)
6462GEN_VXRFORM(vcmpgefp, 3, 7)
6463GEN_VXRFORM(vcmpgtfp, 3, 11)
6464GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 6465
c026766b
AJ		 6466#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6467 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6468 { \
6469 TCGv_ptr rd; \
6470 TCGv_i32 simm; \
6471 if (unlikely(!ctx->altivec_enabled)) { \
6472 gen_exception(ctx, POWERPC_EXCP_VPU); \
6473 return; \
6474 } \
6475 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6476 rd = gen_avr_ptr(rD(ctx->opcode)); \
6477 gen_helper_##name (rd, simm); \
6478 tcg_temp_free_i32(simm); \
6479 tcg_temp_free_ptr(rd); \
6480 }
6481
6482GEN_VXFORM_SIMM(vspltisb, 6, 12);
6483GEN_VXFORM_SIMM(vspltish, 6, 13);
6484GEN_VXFORM_SIMM(vspltisw, 6, 14);
6485
de5f2484
AJ		 6486#define GEN_VXFORM_NOA(name, opc2, opc3) \
6487 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6488 { \
6489 TCGv_ptr rb, rd; \
6490 if (unlikely(!ctx->altivec_enabled)) { \
6491 gen_exception(ctx, POWERPC_EXCP_VPU); \
6492 return; \
6493 } \
6494 rb = gen_avr_ptr(rB(ctx->opcode)); \
6495 rd = gen_avr_ptr(rD(ctx->opcode)); \
6496 gen_helper_##name (rd, rb); \
6497 tcg_temp_free_ptr(rb); \
6498 tcg_temp_free_ptr(rd); \
6499 }
6500
6cf1c6e5
AJ		 6501GEN_VXFORM_NOA(vupkhsb, 7, 8);
6502GEN_VXFORM_NOA(vupkhsh, 7, 9);
6503GEN_VXFORM_NOA(vupklsb, 7, 10);
6504GEN_VXFORM_NOA(vupklsh, 7, 11);
79f85c3a
AJ		 6505GEN_VXFORM_NOA(vupkhpx, 7, 13);
6506GEN_VXFORM_NOA(vupklpx, 7, 15);
bdfbac35 6507GEN_VXFORM_NOA(vrefp, 5, 4);
071fc3b1 6508GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
b580763f 6509GEN_VXFORM_NOA(vlogefp, 5, 7);
f6b19645
AJ		 6510GEN_VXFORM_NOA(vrfim, 5, 8);
6511GEN_VXFORM_NOA(vrfin, 5, 9);
6512GEN_VXFORM_NOA(vrfip, 5, 10);
6513GEN_VXFORM_NOA(vrfiz, 5, 11);
79f85c3a 6514
21d21583
AJ		 6515#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6516 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6517 { \
6518 TCGv_ptr rd; \
6519 TCGv_i32 simm; \
6520 if (unlikely(!ctx->altivec_enabled)) { \
6521 gen_exception(ctx, POWERPC_EXCP_VPU); \
6522 return; \
6523 } \
6524 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6525 rd = gen_avr_ptr(rD(ctx->opcode)); \
6526 gen_helper_##name (rd, simm); \
6527 tcg_temp_free_i32(simm); \
6528 tcg_temp_free_ptr(rd); \
6529 }
6530
27a4edb3
AJ		 6531#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6532 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6533 { \
6534 TCGv_ptr rb, rd; \
6535 TCGv_i32 uimm; \
6536 if (unlikely(!ctx->altivec_enabled)) { \
6537 gen_exception(ctx, POWERPC_EXCP_VPU); \
6538 return; \
6539 } \
6540 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6541 rb = gen_avr_ptr(rB(ctx->opcode)); \
6542 rd = gen_avr_ptr(rD(ctx->opcode)); \
6543 gen_helper_##name (rd, rb, uimm); \
6544 tcg_temp_free_i32(uimm); \
6545 tcg_temp_free_ptr(rb); \
6546 tcg_temp_free_ptr(rd); \
6547 }
6548
e4e6bee7
AJ		 6549GEN_VXFORM_UIMM(vspltb, 6, 8);
6550GEN_VXFORM_UIMM(vsplth, 6, 9);
6551GEN_VXFORM_UIMM(vspltw, 6, 10);
e140632e
AJ		 6552GEN_VXFORM_UIMM(vcfux, 5, 12);
6553GEN_VXFORM_UIMM(vcfsx, 5, 13);
875b31db
AJ		 6554GEN_VXFORM_UIMM(vctuxs, 5, 14);
6555GEN_VXFORM_UIMM(vctsxs, 5, 15);
e4e6bee7 6556
cd633b10
AJ		 6557GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6558{
6559 TCGv_ptr ra, rb, rd;
fce5ecb7 6560 TCGv_i32 sh;
cd633b10
AJ		 6561 if (unlikely(!ctx->altivec_enabled)) {
6562 gen_exception(ctx, POWERPC_EXCP_VPU);
6563 return;
6564 }
6565 ra = gen_avr_ptr(rA(ctx->opcode));
6566 rb = gen_avr_ptr(rB(ctx->opcode));
6567 rd = gen_avr_ptr(rD(ctx->opcode));
6568 sh = tcg_const_i32(VSH(ctx->opcode));
6569 gen_helper_vsldoi (rd, ra, rb, sh);
6570 tcg_temp_free_ptr(ra);
6571 tcg_temp_free_ptr(rb);
6572 tcg_temp_free_ptr(rd);
fce5ecb7 6573 tcg_temp_free_i32(sh);
cd633b10
AJ		 6574}
6575
707cec33
AJ		 6576#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6577 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6578 { \
6579 TCGv_ptr ra, rb, rc, rd; \
6580 if (unlikely(!ctx->altivec_enabled)) { \
6581 gen_exception(ctx, POWERPC_EXCP_VPU); \
6582 return; \
6583 } \
6584 ra = gen_avr_ptr(rA(ctx->opcode)); \
6585 rb = gen_avr_ptr(rB(ctx->opcode)); \
6586 rc = gen_avr_ptr(rC(ctx->opcode)); \
6587 rd = gen_avr_ptr(rD(ctx->opcode)); \
6588 if (Rc(ctx->opcode)) { \
6589 gen_helper_##name1 (rd, ra, rb, rc); \
6590 } else { \
6591 gen_helper_##name0 (rd, ra, rb, rc); \
6592 } \
6593 tcg_temp_free_ptr(ra); \
6594 tcg_temp_free_ptr(rb); \
6595 tcg_temp_free_ptr(rc); \
6596 tcg_temp_free_ptr(rd); \
6597 }
6598
b161ae27
AJ		 6599GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6600
bcd2ee23
AJ		 6601GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6602{
6603 TCGv_ptr ra, rb, rc, rd;
6604 if (unlikely(!ctx->altivec_enabled)) {
6605 gen_exception(ctx, POWERPC_EXCP_VPU);
6606 return;
6607 }
6608 ra = gen_avr_ptr(rA(ctx->opcode));
6609 rb = gen_avr_ptr(rB(ctx->opcode));
6610 rc = gen_avr_ptr(rC(ctx->opcode));
6611 rd = gen_avr_ptr(rD(ctx->opcode));
6612 gen_helper_vmladduhm(rd, ra, rb, rc);
6613 tcg_temp_free_ptr(ra);
6614 tcg_temp_free_ptr(rb);
6615 tcg_temp_free_ptr(rc);
6616 tcg_temp_free_ptr(rd);
6617}
6618
b04ae981 6619GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 6620GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 6621GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 6622GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 6623GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 6624
0487d6a8 6625/*** SPE extension ***/
0487d6a8 6626/* Register moves */
3cd7d1dd 6627
a7812ae4 6628static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6629#if defined(TARGET_PPC64)
6630 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6631#else
36aa55dc 6632 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6633#endif
f78fb44e 6634}
3cd7d1dd 6635
a7812ae4 6636static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6637#if defined(TARGET_PPC64)
6638 tcg_gen_mov_i64(cpu_gpr[reg], t);
6639#else
a7812ae4 6640 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6641 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6642 tcg_gen_shri_i64(tmp, t, 32);
6643 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6644 tcg_temp_free_i64(tmp);
3cd7d1dd 6645#endif
f78fb44e 6646}
3cd7d1dd 6647
0487d6a8
JM		 6648#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6649GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6650{ \
6651 if (Rc(ctx->opcode)) \
6652 gen_##name1(ctx); \
6653 else \
6654 gen_##name0(ctx); \
6655}
6656
6657/* Handler for undefined SPE opcodes */
b068d6a7 6658static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6659{
e06fcd75 6660 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 6661}
6662
57951c27
AJ		 6663/* SPE logic */
6664#if defined(TARGET_PPC64)
6665#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6666static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6667{ \
6668 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6669 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6670 return; \
6671 } \
57951c27
AJ		 6672 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6673 cpu_gpr[rB(ctx->opcode)]); \
6674}
6675#else
6676#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6677static always_inline void gen_##name (DisasContext *ctx) \
6678{ \
6679 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6680 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6681 return; \
6682 } \
6683 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6684 cpu_gpr[rB(ctx->opcode)]); \
6685 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6686 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6687}
57951c27
AJ		 6688#endif
6689
6690GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6691GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6692GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6693GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6694GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6695GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6696GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6697GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6698
57951c27
AJ		 6699/* SPE logic immediate */
6700#if defined(TARGET_PPC64)
6701#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6702static always_inline void gen_##name (DisasContext *ctx) \
6703{ \
6704 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6705 gen_exception(ctx, POWERPC_EXCP_APU); \
3d3a6a0a
AJ		 6706 return; \
6707 } \
a7812ae4
PB		 6708 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6709 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6710 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6711 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6712 tcg_opi(t0, t0, rB(ctx->opcode)); \
6713 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6714 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6715 tcg_temp_free_i64(t2); \
57951c27
AJ		 6716 tcg_opi(t1, t1, rB(ctx->opcode)); \
6717 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6718 tcg_temp_free_i32(t0); \
6719 tcg_temp_free_i32(t1); \
3d3a6a0a 6720}
57951c27
AJ		 6721#else
6722#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6723static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6724{ \
6725 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6726 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6727 return; \
6728 } \
57951c27
AJ		 6729 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6730 rB(ctx->opcode)); \
6731 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6732 rB(ctx->opcode)); \
0487d6a8 6733}
57951c27
AJ		 6734#endif
6735GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6736GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6737GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6738GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6739
57951c27
AJ		 6740/* SPE arithmetic */
6741#if defined(TARGET_PPC64)
6742#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6743static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6744{ \
6745 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6746 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6747 return; \
6748 } \
a7812ae4
PB		 6749 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6750 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6751 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6752 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6753 tcg_op(t0, t0); \
6754 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6755 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6756 tcg_temp_free_i64(t2); \
57951c27
AJ		 6757 tcg_op(t1, t1); \
6758 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6759 tcg_temp_free_i32(t0); \
6760 tcg_temp_free_i32(t1); \
0487d6a8 6761}
57951c27 6762#else
a7812ae4 6763#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6764static always_inline void gen_##name (DisasContext *ctx) \
6765{ \
6766 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6767 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6768 return; \
6769 } \
6770 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6771 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6772}
6773#endif
0487d6a8 6774
a7812ae4 6775static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6776{
6777 int l1 = gen_new_label();
6778 int l2 = gen_new_label();
0487d6a8 6779
57951c27
AJ		 6780 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6781 tcg_gen_neg_i32(ret, arg1);
6782 tcg_gen_br(l2);
6783 gen_set_label(l1);
a7812ae4 6784 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6785 gen_set_label(l2);
6786}
6787GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6788GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6789GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6790GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6791static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6792{
57951c27
AJ		 6793 tcg_gen_addi_i32(ret, arg1, 0x8000);
6794 tcg_gen_ext16u_i32(ret, ret);
6795}
6796GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6797GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6798GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6799
57951c27
AJ		 6800#if defined(TARGET_PPC64)
6801#define GEN_SPEOP_ARITH2(name, tcg_op) \
6802static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6803{ \
6804 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6805 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6806 return; \
6807 } \
a7812ae4
PB		 6808 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6809 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6810 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
501e23c4 6811 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6812 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6813 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6814 tcg_op(t0, t0, t2); \
6815 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6816 tcg_gen_trunc_i64_i32(t1, t3); \
6817 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6818 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6819 tcg_temp_free_i64(t3); \
57951c27 6820 tcg_op(t1, t1, t2); \
a7812ae4 6821 tcg_temp_free_i32(t2); \
57951c27 6822 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6823 tcg_temp_free_i32(t0); \
6824 tcg_temp_free_i32(t1); \
0487d6a8 6825}
57951c27
AJ		 6826#else
6827#define GEN_SPEOP_ARITH2(name, tcg_op) \
6828static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6829{ \
6830 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6831 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6832 return; \
6833 } \
57951c27
AJ		 6834 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6835 cpu_gpr[rB(ctx->opcode)]); \
6836 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6837 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6838}
57951c27 6839#endif
0487d6a8 6840
a7812ae4 6841static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6842{
a7812ae4 6843 TCGv_i32 t0;
57951c27 6844 int l1, l2;
0487d6a8 6845
57951c27
AJ		 6846 l1 = gen_new_label();
6847 l2 = gen_new_label();
a7812ae4 6848 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6849 /* No error here: 6 bits are used */
6850 tcg_gen_andi_i32(t0, arg2, 0x3F);
6851 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6852 tcg_gen_shr_i32(ret, arg1, t0);
6853 tcg_gen_br(l2);
6854 gen_set_label(l1);
6855 tcg_gen_movi_i32(ret, 0);
6856 tcg_gen_br(l2);
a7812ae4 6857 tcg_temp_free_i32(t0);
57951c27
AJ		 6858}
6859GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6860static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6861{
a7812ae4 6862 TCGv_i32 t0;
57951c27
AJ		 6863 int l1, l2;
6864
6865 l1 = gen_new_label();
6866 l2 = gen_new_label();
a7812ae4 6867 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6868 /* No error here: 6 bits are used */
6869 tcg_gen_andi_i32(t0, arg2, 0x3F);
6870 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6871 tcg_gen_sar_i32(ret, arg1, t0);
6872 tcg_gen_br(l2);
6873 gen_set_label(l1);
6874 tcg_gen_movi_i32(ret, 0);
6875 tcg_gen_br(l2);
a7812ae4 6876 tcg_temp_free_i32(t0);
57951c27
AJ		 6877}
6878GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6879static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6880{
a7812ae4 6881 TCGv_i32 t0;
57951c27
AJ		 6882 int l1, l2;
6883
6884 l1 = gen_new_label();
6885 l2 = gen_new_label();
a7812ae4 6886 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6887 /* No error here: 6 bits are used */
6888 tcg_gen_andi_i32(t0, arg2, 0x3F);
6889 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6890 tcg_gen_shl_i32(ret, arg1, t0);
6891 tcg_gen_br(l2);
6892 gen_set_label(l1);
6893 tcg_gen_movi_i32(ret, 0);
6894 tcg_gen_br(l2);
a7812ae4 6895 tcg_temp_free_i32(t0);
57951c27
AJ		 6896}
6897GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6898static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6899{
a7812ae4 6900 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6901 tcg_gen_andi_i32(t0, arg2, 0x1F);
6902 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6903 tcg_temp_free_i32(t0);
57951c27
AJ		 6904}
6905GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6906static always_inline void gen_evmergehi (DisasContext *ctx)
6907{
6908 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6909 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6910 return;
6911 }
6912#if defined(TARGET_PPC64)
a7812ae4
PB		 6913 TCGv t0 = tcg_temp_new();
6914 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6915 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6916 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6917 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6918 tcg_temp_free(t0);
6919 tcg_temp_free(t1);
6920#else
6921 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6922 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6923#endif
6924}
6925GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6926static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6927{
57951c27
AJ		 6928 tcg_gen_sub_i32(ret, arg2, arg1);
6929}
6930GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6931
57951c27
AJ		 6932/* SPE arithmetic immediate */
6933#if defined(TARGET_PPC64)
6934#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6935static always_inline void gen_##name (DisasContext *ctx) \
6936{ \
6937 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6938 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6939 return; \
6940 } \
a7812ae4
PB		 6941 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6942 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6943 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6944 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6945 tcg_op(t0, t0, rA(ctx->opcode)); \
6946 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6947 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 6948 tcg_temp_free_i64(t2); \
57951c27
AJ		 6949 tcg_op(t1, t1, rA(ctx->opcode)); \
6950 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6951 tcg_temp_free_i32(t0); \
6952 tcg_temp_free_i32(t1); \
57951c27
AJ		 6953}
6954#else
6955#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6956static always_inline void gen_##name (DisasContext *ctx) \
6957{ \
6958 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6959 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6960 return; \
6961 } \
6962 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6963 rA(ctx->opcode)); \
6964 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6965 rA(ctx->opcode)); \
6966}
6967#endif
6968GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6969GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6970
6971/* SPE comparison */
6972#if defined(TARGET_PPC64)
6973#define GEN_SPEOP_COMP(name, tcg_cond) \
6974static always_inline void gen_##name (DisasContext *ctx) \
6975{ \
6976 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6977 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6978 return; \
6979 } \
6980 int l1 = gen_new_label(); \
6981 int l2 = gen_new_label(); \
6982 int l3 = gen_new_label(); \
6983 int l4 = gen_new_label(); \
a7812ae4
PB		 6984 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6985 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6986 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6987 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6988 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6989 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6990 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6991 tcg_gen_br(l2); \
6992 gen_set_label(l1); \
6993 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6994 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6995 gen_set_label(l2); \
6996 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6997 tcg_gen_trunc_i64_i32(t0, t2); \
6998 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6999 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 7000 tcg_temp_free_i64(t2); \
57951c27
AJ		 7001 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7002 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7003 ~(CRF_CH | CRF_CH_AND_CL)); \
7004 tcg_gen_br(l4); \
7005 gen_set_label(l3); \
7006 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7007 CRF_CH | CRF_CH_OR_CL); \
7008 gen_set_label(l4); \
a7812ae4
PB		 7009 tcg_temp_free_i32(t0); \
7010 tcg_temp_free_i32(t1); \
57951c27
AJ		 7011}
7012#else
7013#define GEN_SPEOP_COMP(name, tcg_cond) \
7014static always_inline void gen_##name (DisasContext *ctx) \
7015{ \
7016 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7017 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7018 return; \
7019 } \
7020 int l1 = gen_new_label(); \
7021 int l2 = gen_new_label(); \
7022 int l3 = gen_new_label(); \
7023 int l4 = gen_new_label(); \
7024 \
7025 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7026 cpu_gpr[rB(ctx->opcode)], l1); \
7027 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7028 tcg_gen_br(l2); \
7029 gen_set_label(l1); \
7030 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7031 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7032 gen_set_label(l2); \
7033 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7034 cpu_gprh[rB(ctx->opcode)], l3); \
7035 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7036 ~(CRF_CH | CRF_CH_AND_CL)); \
7037 tcg_gen_br(l4); \
7038 gen_set_label(l3); \
7039 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7040 CRF_CH | CRF_CH_OR_CL); \
7041 gen_set_label(l4); \
7042}
7043#endif
7044GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7045GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7046GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7047GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7048GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7049
7050/* SPE misc */
7051static always_inline void gen_brinc (DisasContext *ctx)
7052{
7053 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 7054 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7055 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 7056}
57951c27
AJ		 7057static always_inline void gen_evmergelo (DisasContext *ctx)
7058{
7059 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7060 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7061 return;
7062 }
7063#if defined(TARGET_PPC64)
a7812ae4
PB		 7064 TCGv t0 = tcg_temp_new();
7065 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7066 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7067 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7068 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7069 tcg_temp_free(t0);
7070 tcg_temp_free(t1);
7071#else
7072 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7073 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7074#endif
7075}
7076static always_inline void gen_evmergehilo (DisasContext *ctx)
7077{
7078 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7079 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7080 return;
7081 }
7082#if defined(TARGET_PPC64)
a7812ae4
PB		 7083 TCGv t0 = tcg_temp_new();
7084 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7085 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7086 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7087 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7088 tcg_temp_free(t0);
7089 tcg_temp_free(t1);
7090#else
7091 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7092 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7093#endif
7094}
7095static always_inline void gen_evmergelohi (DisasContext *ctx)
7096{
7097 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7098 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7099 return;
7100 }
7101#if defined(TARGET_PPC64)
a7812ae4
PB		 7102 TCGv t0 = tcg_temp_new();
7103 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7104 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7105 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7106 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7107 tcg_temp_free(t0);
7108 tcg_temp_free(t1);
7109#else
7110 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7111 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7112#endif
7113}
7114static always_inline void gen_evsplati (DisasContext *ctx)
7115{
38d14952 7116 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 7117
57951c27 7118#if defined(TARGET_PPC64)
38d14952 7119 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7120#else
7121 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7122 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7123#endif
7124}
b068d6a7 7125static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 7126{
38d14952 7127 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 7128
57951c27 7129#if defined(TARGET_PPC64)
38d14952 7130 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7131#else
7132 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7133 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7134#endif
0487d6a8
JM		 7135}
7136
57951c27
AJ		 7137static always_inline void gen_evsel (DisasContext *ctx)
7138{
7139 int l1 = gen_new_label();
7140 int l2 = gen_new_label();
7141 int l3 = gen_new_label();
7142 int l4 = gen_new_label();
a7812ae4 7143 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 7144#if defined(TARGET_PPC64)
a7812ae4
PB		 7145 TCGv t1 = tcg_temp_local_new();
7146 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 7147#endif
7148 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7149 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7150#if defined(TARGET_PPC64)
7151 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7152#else
7153 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7154#endif
7155 tcg_gen_br(l2);
7156 gen_set_label(l1);
7157#if defined(TARGET_PPC64)
7158 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7159#else
7160 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7161#endif
7162 gen_set_label(l2);
7163 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7164 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7165#if defined(TARGET_PPC64)
7166 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7167#else
7168 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7169#endif
7170 tcg_gen_br(l4);
7171 gen_set_label(l3);
7172#if defined(TARGET_PPC64)
7173 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7174#else
7175 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7176#endif
7177 gen_set_label(l4);
a7812ae4 7178 tcg_temp_free_i32(t0);
57951c27
AJ		 7179#if defined(TARGET_PPC64)
7180 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7181 tcg_temp_free(t1);
7182 tcg_temp_free(t2);
7183#endif
7184}
7185GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7186{
7187 gen_evsel(ctx);
7188}
7189GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7190{
7191 gen_evsel(ctx);
7192}
7193GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7194{
7195 gen_evsel(ctx);
7196}
7197GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7198{
7199 gen_evsel(ctx);
7200}
0487d6a8
JM		 7201
7202GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7203GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7204GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7205GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7206GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7207GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7208GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7209GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7210GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7211GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7212GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7213GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7214GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7215GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7216GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7217GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7218GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7219GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7220GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7221GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7222GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7223GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7224GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7225GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7226GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7227
6a6ae23f 7228/* SPE load and stores */
76db3ba4 7229static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 7230{
7231 target_ulong uimm = rB(ctx->opcode);
7232
76db3ba4 7233 if (rA(ctx->opcode) == 0) {
6a6ae23f 7234 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 7235 } else {
6a6ae23f 7236 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
76db3ba4
AJ		 7237#if defined(TARGET_PPC64)
7238 if (!ctx->sf_mode) {
7239 tcg_gen_ext32u_tl(EA, EA);
7240 }
7241#endif
7242 }
0487d6a8 7243}
6a6ae23f
AJ		 7244
7245static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7246{
7247#if defined(TARGET_PPC64)
76db3ba4 7248 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7249#else
7250 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 7251 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 7252 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7253 tcg_gen_shri_i64(t0, t0, 32);
7254 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7255 tcg_temp_free_i64(t0);
7256#endif
0487d6a8 7257}
6a6ae23f
AJ		 7258
7259static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7260{
0487d6a8 7261#if defined(TARGET_PPC64)
6a6ae23f 7262 TCGv t0 = tcg_temp_new();
76db3ba4 7263 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 7264 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 7265 gen_addr_add(ctx, addr, addr, 4);
7266 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 7267 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7268 tcg_temp_free(t0);
7269#else
76db3ba4
AJ		 7270 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7271 gen_addr_add(ctx, addr, addr, 4);
7272 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 7273#endif
0487d6a8 7274}
6a6ae23f
AJ		 7275
7276static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7277{
7278 TCGv t0 = tcg_temp_new();
7279#if defined(TARGET_PPC64)
76db3ba4 7280 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7281 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7282 gen_addr_add(ctx, addr, addr, 2);
7283 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7284 tcg_gen_shli_tl(t0, t0, 32);
7285 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7286 gen_addr_add(ctx, addr, addr, 2);
7287 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7288 tcg_gen_shli_tl(t0, t0, 16);
7289 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7290 gen_addr_add(ctx, addr, addr, 2);
7291 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7292 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7293#else
76db3ba4 7294 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7295 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7296 gen_addr_add(ctx, addr, addr, 2);
7297 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7298 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7299 gen_addr_add(ctx, addr, addr, 2);
7300 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7301 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7302 gen_addr_add(ctx, addr, addr, 2);
7303 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7304 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7305#endif
6a6ae23f 7306 tcg_temp_free(t0);
0487d6a8
JM		 7307}
7308
6a6ae23f
AJ		 7309static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7310{
7311 TCGv t0 = tcg_temp_new();
76db3ba4 7312 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7313#if defined(TARGET_PPC64)
7314 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7315 tcg_gen_shli_tl(t0, t0, 16);
7316 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7317#else
7318 tcg_gen_shli_tl(t0, t0, 16);
7319 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7320 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7321#endif
7322 tcg_temp_free(t0);
0487d6a8
JM		 7323}
7324
6a6ae23f
AJ		 7325static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7326{
7327 TCGv t0 = tcg_temp_new();
76db3ba4 7328 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7329#if defined(TARGET_PPC64)
7330 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7331 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7332#else
7333 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7334 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7335#endif
7336 tcg_temp_free(t0);
0487d6a8
JM		 7337}
7338
6a6ae23f
AJ		 7339static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7340{
7341 TCGv t0 = tcg_temp_new();
76db3ba4 7342 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7343#if defined(TARGET_PPC64)
7344 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7345 tcg_gen_ext32u_tl(t0, t0);
7346 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7347#else
7348 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7349 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7350#endif
7351 tcg_temp_free(t0);
7352}
7353
7354static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7355{
7356 TCGv t0 = tcg_temp_new();
7357#if defined(TARGET_PPC64)
76db3ba4 7358 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7359 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7360 gen_addr_add(ctx, addr, addr, 2);
7361 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7362 tcg_gen_shli_tl(t0, t0, 16);
7363 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7364#else
76db3ba4 7365 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7366 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7367 gen_addr_add(ctx, addr, addr, 2);
7368 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7369 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7370#endif
7371 tcg_temp_free(t0);
7372}
7373
7374static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7375{
7376#if defined(TARGET_PPC64)
7377 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 7378 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7379 gen_addr_add(ctx, addr, addr, 2);
7380 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7381 tcg_gen_shli_tl(t0, t0, 32);
7382 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7383 tcg_temp_free(t0);
7384#else
76db3ba4
AJ		 7385 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7386 gen_addr_add(ctx, addr, addr, 2);
7387 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7388#endif
7389}
7390
7391static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7392{
7393#if defined(TARGET_PPC64)
7394 TCGv t0 = tcg_temp_new();
76db3ba4 7395 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 7396 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7397 gen_addr_add(ctx, addr, addr, 2);
7398 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7399 tcg_gen_shli_tl(t0, t0, 32);
7400 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7401 tcg_temp_free(t0);
7402#else
76db3ba4
AJ		 7403 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7404 gen_addr_add(ctx, addr, addr, 2);
7405 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7406#endif
7407}
7408
7409static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7410{
7411 TCGv t0 = tcg_temp_new();
76db3ba4 7412 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 7413#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7414 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7415 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7416#else
7417 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7418 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7419#endif
7420 tcg_temp_free(t0);
7421}
7422
7423static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7424{
7425 TCGv t0 = tcg_temp_new();
7426#if defined(TARGET_PPC64)
76db3ba4 7427 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7428 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7429 tcg_gen_shli_tl(t0, t0, 32);
7430 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7431 gen_addr_add(ctx, addr, addr, 2);
7432 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7433 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7434 tcg_gen_shli_tl(t0, t0, 16);
7435 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7436#else
76db3ba4 7437 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7438 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7439 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7440 gen_addr_add(ctx, addr, addr, 2);
7441 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7442 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7443 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 7444#endif
6a6ae23f
AJ		 7445 tcg_temp_free(t0);
7446}
7447
7448static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7449{
7450#if defined(TARGET_PPC64)
76db3ba4 7451 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 7452#else
6a6ae23f
AJ		 7453 TCGv_i64 t0 = tcg_temp_new_i64();
7454 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 7455 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 7456 tcg_temp_free_i64(t0);
7457#endif
7458}
7459
7460static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7461{
0487d6a8 7462#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7463 TCGv t0 = tcg_temp_new();
7464 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7465 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7466 tcg_temp_free(t0);
7467#else
76db3ba4 7468 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7469#endif
76db3ba4
AJ		 7470 gen_addr_add(ctx, addr, addr, 4);
7471 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7472}
7473
7474static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7475{
7476 TCGv t0 = tcg_temp_new();
7477#if defined(TARGET_PPC64)
7478 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7479#else
7480 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7481#endif
76db3ba4
AJ		 7482 gen_qemu_st16(ctx, t0, addr);
7483 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 7484#if defined(TARGET_PPC64)
7485 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7486 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7487#else
76db3ba4 7488 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7489#endif
76db3ba4 7490 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7491 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7492 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7493 tcg_temp_free(t0);
76db3ba4
AJ		 7494 gen_addr_add(ctx, addr, addr, 2);
7495 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7496}
7497
7498static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7499{
7500 TCGv t0 = tcg_temp_new();
7501#if defined(TARGET_PPC64)
7502 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7503#else
7504 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7505#endif
76db3ba4
AJ		 7506 gen_qemu_st16(ctx, t0, addr);
7507 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7508 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7509 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7510 tcg_temp_free(t0);
7511}
7512
7513static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7514{
7515#if defined(TARGET_PPC64)
7516 TCGv t0 = tcg_temp_new();
7517 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7518 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7519 tcg_temp_free(t0);
7520#else
76db3ba4 7521 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7522#endif
76db3ba4
AJ		 7523 gen_addr_add(ctx, addr, addr, 2);
7524 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7525}
7526
7527static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7528{
7529#if defined(TARGET_PPC64)
7530 TCGv t0 = tcg_temp_new();
7531 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7532 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7533 tcg_temp_free(t0);
7534#else
76db3ba4 7535 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7536#endif
7537}
7538
7539static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7540{
76db3ba4 7541 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7542}
7543
7544#define GEN_SPEOP_LDST(name, opc2, sh) \
76db3ba4 7545GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6a6ae23f
AJ		 7546{ \
7547 TCGv t0; \
7548 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7549 gen_exception(ctx, POWERPC_EXCP_APU); \
6a6ae23f
AJ		 7550 return; \
7551 } \
76db3ba4 7552 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 7553 t0 = tcg_temp_new(); \
7554 if (Rc(ctx->opcode)) { \
76db3ba4 7555 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 7556 } else { \
76db3ba4 7557 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 7558 } \
7559 gen_op_##name(ctx, t0); \
7560 tcg_temp_free(t0); \
7561}
7562
7563GEN_SPEOP_LDST(evldd, 0x00, 3);
7564GEN_SPEOP_LDST(evldw, 0x01, 3);
7565GEN_SPEOP_LDST(evldh, 0x02, 3);
7566GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7567GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7568GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7569GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7570GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7571GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7572GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7573GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7574
7575GEN_SPEOP_LDST(evstdd, 0x10, 3);
7576GEN_SPEOP_LDST(evstdw, 0x11, 3);
7577GEN_SPEOP_LDST(evstdh, 0x12, 3);
7578GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7579GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7580GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7581GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7582
7583/* Multiply and add - TODO */
7584#if 0
7585GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7586GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7587GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7588GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7589GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7590GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7591GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7592GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7593GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7594GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7595GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7596GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7597
7598GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7599GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7600GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7601GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7602GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7603GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7604GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7605GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7606GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7607GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7608GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7609GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7610GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7611GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7612
7613GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7614GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7615GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7616GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7617GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7618GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7619
7620GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7621GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7622GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7623GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7624GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7625GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7626GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7627GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7628GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7629GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7630GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7631GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7632
7633GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7634GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7635GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7636GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7637GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7638
7639GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7640GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7641GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7642GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7643GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7644GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7645GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7646GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7647GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7648GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7649GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7650GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7651
7652GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7653GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7654GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7655GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7656GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7657#endif
7658
7659/*** SPE floating-point extension ***/
1c97856d
AJ		 7660#if defined(TARGET_PPC64)
7661#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7662static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7663{ \
1c97856d
AJ		 7664 TCGv_i32 t0; \
7665 TCGv t1; \
7666 t0 = tcg_temp_new_i32(); \
7667 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7668 gen_helper_##name(t0, t0); \
7669 t1 = tcg_temp_new(); \
7670 tcg_gen_extu_i32_tl(t1, t0); \
7671 tcg_temp_free_i32(t0); \
7672 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7673 0xFFFFFFFF00000000ULL); \
7674 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7675 tcg_temp_free(t1); \
0487d6a8 7676}
1c97856d
AJ		 7677#define GEN_SPEFPUOP_CONV_32_64(name) \
7678static always_inline void gen_##name (DisasContext *ctx) \
7679{ \
7680 TCGv_i32 t0; \
7681 TCGv t1; \
7682 t0 = tcg_temp_new_i32(); \
7683 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7684 t1 = tcg_temp_new(); \
7685 tcg_gen_extu_i32_tl(t1, t0); \
7686 tcg_temp_free_i32(t0); \
7687 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7688 0xFFFFFFFF00000000ULL); \
7689 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7690 tcg_temp_free(t1); \
7691}
7692#define GEN_SPEFPUOP_CONV_64_32(name) \
7693static always_inline void gen_##name (DisasContext *ctx) \
7694{ \
7695 TCGv_i32 t0 = tcg_temp_new_i32(); \
7696 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7697 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7698 tcg_temp_free_i32(t0); \
7699}
7700#define GEN_SPEFPUOP_CONV_64_64(name) \
7701static always_inline void gen_##name (DisasContext *ctx) \
7702{ \
7703 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7704}
7705#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7706static always_inline void gen_##name (DisasContext *ctx) \
7707{ \
1c97856d
AJ		 7708 TCGv_i32 t0, t1; \
7709 TCGv_i64 t2; \
57951c27 7710 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7711 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7712 return; \
7713 } \
1c97856d
AJ		 7714 t0 = tcg_temp_new_i32(); \
7715 t1 = tcg_temp_new_i32(); \
7716 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7717 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7718 gen_helper_##name(t0, t0, t1); \
7719 tcg_temp_free_i32(t1); \
7720 t2 = tcg_temp_new(); \
7721 tcg_gen_extu_i32_tl(t2, t0); \
7722 tcg_temp_free_i32(t0); \
7723 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7724 0xFFFFFFFF00000000ULL); \
7725 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7726 tcg_temp_free(t2); \
57951c27 7727}
1c97856d 7728#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7729static always_inline void gen_##name (DisasContext *ctx) \
7730{ \
7731 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7732 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7733 return; \
7734 } \
1c97856d
AJ		 7735 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7736 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7737}
1c97856d 7738#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7739static always_inline void gen_##name (DisasContext *ctx) \
7740{ \
1c97856d 7741 TCGv_i32 t0, t1; \
57951c27 7742 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7743 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7744 return; \
7745 } \
1c97856d
AJ		 7746 t0 = tcg_temp_new_i32(); \
7747 t1 = tcg_temp_new_i32(); \
7748 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7749 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7750 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7751 tcg_temp_free_i32(t0); \
7752 tcg_temp_free_i32(t1); \
7753}
7754#define GEN_SPEFPUOP_COMP_64(name) \
7755static always_inline void gen_##name (DisasContext *ctx) \
7756{ \
7757 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7758 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7759 return; \
7760 } \
7761 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7762 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7763}
7764#else
7765#define GEN_SPEFPUOP_CONV_32_32(name) \
7766static always_inline void gen_##name (DisasContext *ctx) \
7767{ \
7768 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7769}
1c97856d
AJ		 7770#define GEN_SPEFPUOP_CONV_32_64(name) \
7771static always_inline void gen_##name (DisasContext *ctx) \
7772{ \
7773 TCGv_i64 t0 = tcg_temp_new_i64(); \
7774 gen_load_gpr64(t0, rB(ctx->opcode)); \
7775 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7776 tcg_temp_free_i64(t0); \
7777}
7778#define GEN_SPEFPUOP_CONV_64_32(name) \
7779static always_inline void gen_##name (DisasContext *ctx) \
7780{ \
7781 TCGv_i64 t0 = tcg_temp_new_i64(); \
7782 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7783 gen_store_gpr64(rD(ctx->opcode), t0); \
7784 tcg_temp_free_i64(t0); \
7785}
7786#define GEN_SPEFPUOP_CONV_64_64(name) \
7787static always_inline void gen_##name (DisasContext *ctx) \
7788{ \
7789 TCGv_i64 t0 = tcg_temp_new_i64(); \
7790 gen_load_gpr64(t0, rB(ctx->opcode)); \
7791 gen_helper_##name(t0, t0); \
7792 gen_store_gpr64(rD(ctx->opcode), t0); \
7793 tcg_temp_free_i64(t0); \
7794}
7795#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7796static always_inline void gen_##name (DisasContext *ctx) \
7797{ \
7798 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7799 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7800 return; \
7801 } \
7802 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7803 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7804}
7805#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7806static always_inline void gen_##name (DisasContext *ctx) \
7807{ \
7808 TCGv_i64 t0, t1; \
7809 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7810 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7811 return; \
7812 } \
7813 t0 = tcg_temp_new_i64(); \
7814 t1 = tcg_temp_new_i64(); \
7815 gen_load_gpr64(t0, rA(ctx->opcode)); \
7816 gen_load_gpr64(t1, rB(ctx->opcode)); \
7817 gen_helper_##name(t0, t0, t1); \
7818 gen_store_gpr64(rD(ctx->opcode), t0); \
7819 tcg_temp_free_i64(t0); \
7820 tcg_temp_free_i64(t1); \
7821}
7822#define GEN_SPEFPUOP_COMP_32(name) \
7823static always_inline void gen_##name (DisasContext *ctx) \
7824{ \
7825 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7826 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7827 return; \
7828 } \
7829 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7830 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7831}
7832#define GEN_SPEFPUOP_COMP_64(name) \
7833static always_inline void gen_##name (DisasContext *ctx) \
7834{ \
7835 TCGv_i64 t0, t1; \
7836 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7837 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7838 return; \
7839 } \
7840 t0 = tcg_temp_new_i64(); \
7841 t1 = tcg_temp_new_i64(); \
7842 gen_load_gpr64(t0, rA(ctx->opcode)); \
7843 gen_load_gpr64(t1, rB(ctx->opcode)); \
7844 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7845 tcg_temp_free_i64(t0); \
7846 tcg_temp_free_i64(t1); \
7847}
7848#endif
57951c27 7849
0487d6a8
JM		 7850/* Single precision floating-point vectors operations */
7851/* Arithmetic */
1c97856d
AJ		 7852GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7853GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7854GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7855GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7856static always_inline void gen_evfsabs (DisasContext *ctx)
7857{
7858 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7859 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7860 return;
7861 }
7862#if defined(TARGET_PPC64)
7863 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7864#else
7865 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7866 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7867#endif
7868}
7869static always_inline void gen_evfsnabs (DisasContext *ctx)
7870{
7871 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7872 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7873 return;
7874 }
7875#if defined(TARGET_PPC64)
7876 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7877#else
7878 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7879 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7880#endif
7881}
7882static always_inline void gen_evfsneg (DisasContext *ctx)
7883{
7884 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7885 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7886 return;
7887 }
7888#if defined(TARGET_PPC64)
7889 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7890#else
7891 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7892 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7893#endif
7894}
7895
0487d6a8 7896/* Conversion */
1c97856d
AJ		 7897GEN_SPEFPUOP_CONV_64_64(evfscfui);
7898GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7899GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7900GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7901GEN_SPEFPUOP_CONV_64_64(evfsctui);
7902GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7903GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7904GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7905GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7906GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7907
0487d6a8 7908/* Comparison */
1c97856d
AJ		 7909GEN_SPEFPUOP_COMP_64(evfscmpgt);
7910GEN_SPEFPUOP_COMP_64(evfscmplt);
7911GEN_SPEFPUOP_COMP_64(evfscmpeq);
7912GEN_SPEFPUOP_COMP_64(evfststgt);
7913GEN_SPEFPUOP_COMP_64(evfststlt);
7914GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7915
7916/* Opcodes definitions */
40569b7e
AJ		 7917GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7918GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7919GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7920GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7921GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7922GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7923GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7924GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7925GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7926GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7927GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7928GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7929GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7930GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 7931
7932/* Single precision floating-point operations */
7933/* Arithmetic */
1c97856d
AJ		 7934GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7935GEN_SPEFPUOP_ARITH2_32_32(efssub);
7936GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7937GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7938static always_inline void gen_efsabs (DisasContext *ctx)
7939{
7940 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7941 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7942 return;
7943 }
7944 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7945}
7946static always_inline void gen_efsnabs (DisasContext *ctx)
7947{
7948 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7949 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7950 return;
7951 }
7952 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7953}
7954static always_inline void gen_efsneg (DisasContext *ctx)
7955{
7956 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7957 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7958 return;
7959 }
7960 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7961}
7962
0487d6a8 7963/* Conversion */
1c97856d
AJ		 7964GEN_SPEFPUOP_CONV_32_32(efscfui);
7965GEN_SPEFPUOP_CONV_32_32(efscfsi);
7966GEN_SPEFPUOP_CONV_32_32(efscfuf);
7967GEN_SPEFPUOP_CONV_32_32(efscfsf);
7968GEN_SPEFPUOP_CONV_32_32(efsctui);
7969GEN_SPEFPUOP_CONV_32_32(efsctsi);
7970GEN_SPEFPUOP_CONV_32_32(efsctuf);
7971GEN_SPEFPUOP_CONV_32_32(efsctsf);
7972GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7973GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7974GEN_SPEFPUOP_CONV_32_64(efscfd);
7975
0487d6a8 7976/* Comparison */
1c97856d
AJ		 7977GEN_SPEFPUOP_COMP_32(efscmpgt);
7978GEN_SPEFPUOP_COMP_32(efscmplt);
7979GEN_SPEFPUOP_COMP_32(efscmpeq);
7980GEN_SPEFPUOP_COMP_32(efststgt);
7981GEN_SPEFPUOP_COMP_32(efststlt);
7982GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7983
7984/* Opcodes definitions */
40569b7e
AJ		 7985GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7986GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7987GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7988GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7989GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7990GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7991GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7992GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7993GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7994GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7995GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7996GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7997GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7998GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 7999
8000/* Double precision floating-point operations */
8001/* Arithmetic */
1c97856d
AJ		 8002GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8003GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8004GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8005GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8006static always_inline void gen_efdabs (DisasContext *ctx)
8007{
8008 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 8009 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 8010 return;
8011 }
8012#if defined(TARGET_PPC64)
8013 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8014#else
8015 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8016#endif
8017}
8018static always_inline void gen_efdnabs (DisasContext *ctx)
8019{
8020 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 8021 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 8022 return;
8023 }
8024#if defined(TARGET_PPC64)
8025 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8026#else
8027 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8028#endif
8029}
8030static always_inline void gen_efdneg (DisasContext *ctx)
8031{
8032 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 8033 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 8034 return;
8035 }
8036#if defined(TARGET_PPC64)
8037 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8038#else
8039 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8040#endif
8041}
8042
0487d6a8 8043/* Conversion */
1c97856d
AJ		 8044GEN_SPEFPUOP_CONV_64_32(efdcfui);
8045GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8046GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8047GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8048GEN_SPEFPUOP_CONV_32_64(efdctui);
8049GEN_SPEFPUOP_CONV_32_64(efdctsi);
8050GEN_SPEFPUOP_CONV_32_64(efdctuf);
8051GEN_SPEFPUOP_CONV_32_64(efdctsf);
8052GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8053GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8054GEN_SPEFPUOP_CONV_64_32(efdcfs);
8055GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8056GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8057GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8058GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 8059
0487d6a8 8060/* Comparison */
1c97856d
AJ		 8061GEN_SPEFPUOP_COMP_64(efdcmpgt);
8062GEN_SPEFPUOP_COMP_64(efdcmplt);
8063GEN_SPEFPUOP_COMP_64(efdcmpeq);
8064GEN_SPEFPUOP_COMP_64(efdtstgt);
8065GEN_SPEFPUOP_COMP_64(efdtstlt);
8066GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 8067
8068/* Opcodes definitions */
40569b7e
AJ		 8069GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8070GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8071GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8072GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8073GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8074GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8075GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8076GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8077GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8078GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8079GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8080GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8081GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8082GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8083GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8084GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
0487d6a8 8085
79aceca5
FB		 8086/* End opcode list */
8087GEN_OPCODE_MARK(end);
8088
3fc6c082 8089#include "translate_init.c"
0411a972 8090#include "helper_regs.h"
79aceca5 8091
9a64fbe4 8092/*****************************************************************************/
3fc6c082 8093/* Misc PowerPC helpers */
36081602
JM		 8094void cpu_dump_state (CPUState *env, FILE *f,
8095 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8096 int flags)
79aceca5 8097{
3fc6c082
FB		 8098#define RGPL 4
8099#define RFPL 4
3fc6c082 8100
79aceca5
FB		 8101 int i;
8102
077fc206 8103 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 8104 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 8105 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8106 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 8107#if !defined(NO_TIMER_DUMP)
077fc206 8108 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 8109#if !defined(CONFIG_USER_ONLY)
8110 "DECR %08x"
8111#endif
8112 "\n",
077fc206 8113 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 8114#if !defined(CONFIG_USER_ONLY)
8115 , cpu_ppc_load_decr(env)
8116#endif
8117 );
077fc206 8118#endif
76a66253 8119 for (i = 0; i < 32; i++) {
3fc6c082
FB		 8120 if ((i & (RGPL - 1)) == 0)
8121 cpu_fprintf(f, "GPR%02d", i);
6b542af7 8122 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 8123 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 8124 cpu_fprintf(f, "\n");
76a66253 8125 }
3fc6c082 8126 cpu_fprintf(f, "CR ");
76a66253 8127 for (i = 0; i < 8; i++)
7fe48483
FB		 8128 cpu_fprintf(f, "%01x", env->crf[i]);
8129 cpu_fprintf(f, " [");
76a66253
JM		 8130 for (i = 0; i < 8; i++) {
8131 char a = '-';
8132 if (env->crf[i] & 0x08)
8133 a = 'L';
8134 else if (env->crf[i] & 0x04)
8135 a = 'G';
8136 else if (env->crf[i] & 0x02)
8137 a = 'E';
7fe48483 8138 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 8139 }
6b542af7 8140 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 8141 for (i = 0; i < 32; i++) {
8142 if ((i & (RFPL - 1)) == 0)
8143 cpu_fprintf(f, "FPR%02d", i);
26a76461 8144 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 8145 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 8146 cpu_fprintf(f, "\n");
79aceca5 8147 }
7889270a 8148 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
f2e63a42 8149#if !defined(CONFIG_USER_ONLY)
6b542af7 8150 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 8151 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 8152#endif
79aceca5 8153
3fc6c082
FB		 8154#undef RGPL
8155#undef RFPL
79aceca5
FB		 8156}
8157
76a66253
JM		 8158void cpu_dump_statistics (CPUState *env, FILE*f,
8159 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8160 int flags)
8161{
8162#if defined(DO_PPC_STATISTICS)
8163 opc_handler_t **t1, **t2, **t3, *handler;
8164 int op1, op2, op3;
8165
8166 t1 = env->opcodes;
8167 for (op1 = 0; op1 < 64; op1++) {
8168 handler = t1[op1];
8169 if (is_indirect_opcode(handler)) {
8170 t2 = ind_table(handler);
8171 for (op2 = 0; op2 < 32; op2++) {
8172 handler = t2[op2];
8173 if (is_indirect_opcode(handler)) {
8174 t3 = ind_table(handler);
8175 for (op3 = 0; op3 < 32; op3++) {
8176 handler = t3[op3];
8177 if (handler->count == 0)
8178 continue;
8179 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8180 "%016llx %lld\n",
8181 op1, op2, op3, op1, (op3 << 5) | op2,
8182 handler->oname,
8183 handler->count, handler->count);
8184 }
8185 } else {
8186 if (handler->count == 0)
8187 continue;
8188 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8189 "%016llx %lld\n",
8190 op1, op2, op1, op2, handler->oname,
8191 handler->count, handler->count);
8192 }
8193 }
8194 } else {
8195 if (handler->count == 0)
8196 continue;
8197 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8198 op1, op1, handler->oname,
8199 handler->count, handler->count);
8200 }
8201 }
8202#endif
8203}
8204
9a64fbe4 8205/*****************************************************************************/
2cfc5f17
TS		 8206static always_inline void gen_intermediate_code_internal (CPUState *env,
8207 TranslationBlock *tb,
8208 int search_pc)
79aceca5 8209{
9fddaa0c 8210 DisasContext ctx, *ctxp = &ctx;
79aceca5 8211 opc_handler_t **table, *handler;
0fa85d43 8212 target_ulong pc_start;
79aceca5 8213 uint16_t *gen_opc_end;
a1d1bb31 8214 CPUBreakpoint *bp;
79aceca5 8215 int j, lj = -1;
2e70f6ef
PB		 8216 int num_insns;
8217 int max_insns;
79aceca5
FB		 8218
8219 pc_start = tb->pc;
79aceca5 8220 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
046d6672 8221 ctx.nip = pc_start;
79aceca5 8222 ctx.tb = tb;
e1833e1f 8223 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 8224 ctx.spr_cb = env->spr_cb;
76db3ba4
AJ		 8225 ctx.mem_idx = env->mmu_idx;
8226 ctx.access_type = -1;
8227 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 8228#if defined(TARGET_PPC64)
8229 ctx.sf_mode = msr_sf;
9a64fbe4 8230#endif
3cc62370 8231 ctx.fpu_enabled = msr_fp;
a9d9eb8f 8232 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 8233 ctx.spe_enabled = msr_spe;
8234 else
8235 ctx.spe_enabled = 0;
a9d9eb8f
JM		 8236 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8237 ctx.altivec_enabled = msr_vr;
8238 else
8239 ctx.altivec_enabled = 0;
d26bfc9a 8240 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 8241 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 8242 else
8cbcb4fa 8243 ctx.singlestep_enabled = 0;
d26bfc9a 8244 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 8245 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8246 if (unlikely(env->singlestep_enabled))
8247 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 8248#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 8249 /* Single step trace mode */
8250 msr_se = 1;
8251#endif
2e70f6ef
PB		 8252 num_insns = 0;
8253 max_insns = tb->cflags & CF_COUNT_MASK;
8254 if (max_insns == 0)
8255 max_insns = CF_COUNT_MASK;
8256
8257 gen_icount_start();
9a64fbe4 8258 /* Set env in case of segfault during code fetch */
e1833e1f 8259 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 8260 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8261 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 8262 if (bp->pc == ctx.nip) {
e06fcd75 8263 gen_debug_exception(ctxp);
ea4e754f
FB		 8264 break;
8265 }
8266 }
8267 }
76a66253 8268 if (unlikely(search_pc)) {
79aceca5
FB		 8269 j = gen_opc_ptr - gen_opc_buf;
8270 if (lj < j) {
8271 lj++;
8272 while (lj < j)
8273 gen_opc_instr_start[lj++] = 0;
046d6672 8274 gen_opc_pc[lj] = ctx.nip;
79aceca5 8275 gen_opc_instr_start[lj] = 1;
2e70f6ef 8276 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 8277 }
8278 }
d12d51d5
AL		 8279 LOG_DISAS("----------------\n");
8280 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8281 ctx.nip, ctx.mem_idx, (int)msr_ir);
2e70f6ef
PB		 8282 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8283 gen_io_start();
76db3ba4 8284 if (unlikely(ctx.le_mode)) {
056401ea
JM		 8285 ctx.opcode = bswap32(ldl_code(ctx.nip));
8286 } else {
8287 ctx.opcode = ldl_code(ctx.nip);
111bfab3 8288 }
d12d51d5 8289 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 8290 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 8291 opc3(ctx.opcode), little_endian ? "little" : "big");
046d6672 8292 ctx.nip += 4;
3fc6c082 8293 table = env->opcodes;
2e70f6ef 8294 num_insns++;
79aceca5
FB		 8295 handler = table[opc1(ctx.opcode)];
8296 if (is_indirect_opcode(handler)) {
8297 table = ind_table(handler);
8298 handler = table[opc2(ctx.opcode)];
8299 if (is_indirect_opcode(handler)) {
8300 table = ind_table(handler);
8301 handler = table[opc3(ctx.opcode)];
8302 }
8303 }
8304 /* Is opcode *REALLY* valid ? */
76a66253 8305 if (unlikely(handler->handler == &gen_invalid)) {
93fcfe39
AL		 8306 if (qemu_log_enabled()) {
8307 qemu_log("invalid/unsupported opcode: "
8308 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8309 opc1(ctx.opcode), opc2(ctx.opcode),
8310 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 8311 } else {
8312 printf("invalid/unsupported opcode: "
6b542af7 8313 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 8314 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8315 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 8316 }
76a66253
JM		 8317 } else {
8318 if (unlikely((ctx.opcode & handler->inval) != 0)) {
93fcfe39
AL		 8319 if (qemu_log_enabled()) {
8320 qemu_log("invalid bits: %08x for opcode: "
8321 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8322 ctx.opcode & handler->inval, opc1(ctx.opcode),
8323 opc2(ctx.opcode), opc3(ctx.opcode),
8324 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 8325 } else {
8326 printf("invalid bits: %08x for opcode: "
6b542af7 8327 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 8328 ctx.opcode & handler->inval, opc1(ctx.opcode),
8329 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8330 ctx.opcode, ctx.nip - 4);
76a66253 8331 }
e06fcd75 8332 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 8333 break;
79aceca5 8334 }
79aceca5 8335 }
4b3686fa 8336 (*(handler->handler))(&ctx);
76a66253
JM		 8337#if defined(DO_PPC_STATISTICS)
8338 handler->count++;
8339#endif
9a64fbe4 8340 /* Check trace mode exceptions */
8cbcb4fa
AJ		 8341 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8342 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8343 ctx.exception != POWERPC_SYSCALL &&
8344 ctx.exception != POWERPC_EXCP_TRAP &&
8345 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 8346 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 8347 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 8348 (env->singlestep_enabled) ||
8349 num_insns >= max_insns)) {
d26bfc9a
JM		 8350 /* if we reach a page boundary or are single stepping, stop
8351 * generation
8352 */
8dd4983c 8353 break;
76a66253 8354 }
3fc6c082
FB		 8355#if defined (DO_SINGLE_STEP)
8356 break;
8357#endif
8358 }
2e70f6ef
PB		 8359 if (tb->cflags & CF_LAST_IO)
8360 gen_io_end();
e1833e1f 8361 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 8362 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 8363 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa 8364 if (unlikely(env->singlestep_enabled)) {
e06fcd75 8365 gen_debug_exception(ctxp);
8cbcb4fa 8366 }
76a66253 8367 /* Generate the return instruction */
57fec1fe 8368 tcg_gen_exit_tb(0);
9a64fbe4 8369 }
2e70f6ef 8370 gen_icount_end(tb, num_insns);
79aceca5 8371 *gen_opc_ptr = INDEX_op_end;
76a66253 8372 if (unlikely(search_pc)) {
9a64fbe4
FB		 8373 j = gen_opc_ptr - gen_opc_buf;
8374 lj++;
8375 while (lj <= j)
8376 gen_opc_instr_start[lj++] = 0;
9a64fbe4 8377 } else {
046d6672 8378 tb->size = ctx.nip - pc_start;
2e70f6ef 8379 tb->icount = num_insns;
9a64fbe4 8380 }
d9bce9d9 8381#if defined(DEBUG_DISAS)
93fcfe39
AL		 8382 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8383 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8fec2b8c 8384 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 8385 int flags;
237c0af0 8386 flags = env->bfd_mach;
76db3ba4 8387 flags |= ctx.le_mode << 16;
93fcfe39
AL		 8388 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8389 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8390 qemu_log("\n");
9fddaa0c 8391 }
79aceca5 8392#endif
79aceca5
FB		 8393}
8394
2cfc5f17 8395void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 8396{
2cfc5f17 8397 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 8398}
8399
2cfc5f17 8400void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 8401{
2cfc5f17 8402 gen_intermediate_code_internal(env, tb, 1);
79aceca5 8403}
d2856f1a
AJ		 8404
8405void gen_pc_load(CPUState *env, TranslationBlock *tb,
8406 unsigned long searched_pc, int pc_pos, void *puc)
8407{
d2856f1a 8408 env->nip = gen_opc_pc[pc_pos];
d2856f1a 8409}
Qemu copy for testing