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SH: Implement MOVCO.L and MOVLI.L
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
79aceca5 19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
e8fc4fa7 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
79aceca5 44
d12d51d5 45#ifdef PPC_DEBUG_DISAS
93fcfe39 46# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 47#else
48# define LOG_DISAS(...) do { } while (0)
49#endif
a750fc0b
JM		 50/*****************************************************************************/
51/* Code translation helpers */
c53be334 52
f78fb44e 53/* global register indexes */
a7812ae4 54static TCGv_ptr cpu_env;
1d542695 55static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 56#if !defined(TARGET_PPC64)
1d542695 57 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 58#endif
a5e26afa 59 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 60 + 2*(10*6 + 22*7) /* AVRh, AVRl */
61 + 8*5 /* CRF */];
f78fb44e
AJ		 62static TCGv cpu_gpr[32];
63#if !defined(TARGET_PPC64)
64static TCGv cpu_gprh[32];
65#endif
a7812ae4
PB		 66static TCGv_i64 cpu_fpr[32];
67static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
68static TCGv_i32 cpu_crf[8];
bd568f18 69static TCGv cpu_nip;
6527f6ea 70static TCGv cpu_msr;
cfdcd37a
AJ		 71static TCGv cpu_ctr;
72static TCGv cpu_lr;
3d7b417e 73static TCGv cpu_xer;
cf360a32 74static TCGv cpu_reserve;
a7812ae4 75static TCGv_i32 cpu_fpscr;
a7859e89 76static TCGv_i32 cpu_access_type;
f78fb44e 77
2e70f6ef
PB		 78#include "gen-icount.h"
79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
b2437bf2 84 static int done_init = 0;
f78fb44e 85
2e70f6ef
PB		 86 if (done_init)
87 return;
f78fb44e 88
a7812ae4 89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 90
f78fb44e 91 p = cpu_reg_names;
47e4661c
AJ		 92
93 for (i = 0; i < 8; i++) {
94 sprintf(p, "crf%d", i);
a7812ae4
PB		 95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 97 p += 5;
98 }
99
f78fb44e
AJ		 100 for (i = 0; i < 32; i++) {
101 sprintf(p, "r%d", i);
a7812ae4 102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 103 offsetof(CPUState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105#if !defined(TARGET_PPC64)
106 sprintf(p, "r%dH", i);
a7812ae4
PB		 107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 109 p += (i < 10) ? 4 : 5;
110#endif
1d542695 111
a5e26afa 112 sprintf(p, "fp%d", i);
a7812ae4
PB		 113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUState, fpr[i]), p);
ec1ac72d 115 p += (i < 10) ? 4 : 5;
a5e26afa 116
1d542695 117 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 118#ifdef WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
120 offsetof(CPUState, avr[i].u64[0]), p);
121#else
a7812ae4 122 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 123 offsetof(CPUState, avr[i].u64[1]), p);
124#endif
1d542695 125 p += (i < 10) ? 6 : 7;
ec1ac72d 126
1d542695 127 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 128#ifdef WORDS_BIGENDIAN
129 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
130 offsetof(CPUState, avr[i].u64[1]), p);
131#else
a7812ae4 132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 133 offsetof(CPUState, avr[i].u64[0]), p);
134#endif
1d542695 135 p += (i < 10) ? 6 : 7;
f78fb44e 136 }
f10dc08e 137
a7812ae4 138 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 139 offsetof(CPUState, nip), "nip");
140
6527f6ea
AJ		 141 cpu_msr = tcg_global_mem_new(TCG_AREG0,
142 offsetof(CPUState, msr), "msr");
143
a7812ae4 144 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 145 offsetof(CPUState, ctr), "ctr");
146
a7812ae4 147 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 148 offsetof(CPUState, lr), "lr");
149
a7812ae4 150 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 151 offsetof(CPUState, xer), "xer");
152
cf360a32
AJ		 153 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
154 offsetof(CPUState, reserve), "reserve");
155
a7812ae4
PB		 156 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
157 offsetof(CPUState, fpscr), "fpscr");
e1571908 158
a7859e89
AJ		 159 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
160 offsetof(CPUState, access_type), "access_type");
161
f10dc08e 162 /* register helpers */
a7812ae4 163#define GEN_HELPER 2
f10dc08e
AJ		 164#include "helper.h"
165
2e70f6ef
PB		 166 done_init = 1;
167}
168
79aceca5
FB		 169/* internal defines */
170typedef struct DisasContext {
171 struct TranslationBlock *tb;
0fa85d43 172 target_ulong nip;
79aceca5 173 uint32_t opcode;
9a64fbe4 174 uint32_t exception;
3cc62370
FB		 175 /* Routine used to access memory */
176 int mem_idx;
76db3ba4 177 int access_type;
3cc62370 178 /* Translation flags */
76db3ba4 179 int le_mode;
d9bce9d9
JM		 180#if defined(TARGET_PPC64)
181 int sf_mode;
9a64fbe4 182#endif
3cc62370 183 int fpu_enabled;
a9d9eb8f 184 int altivec_enabled;
0487d6a8 185 int spe_enabled;
3fc6c082 186 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 187 int singlestep_enabled;
79aceca5
FB		 188} DisasContext;
189
3fc6c082 190struct opc_handler_t {
79aceca5
FB		 191 /* invalid bits */
192 uint32_t inval;
9a64fbe4 193 /* instruction type */
0487d6a8 194 uint64_t type;
79aceca5
FB		 195 /* handler */
196 void (*handler)(DisasContext *ctx);
a750fc0b 197#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 198 const char *oname;
a750fc0b
JM		 199#endif
200#if defined(DO_PPC_STATISTICS)
76a66253
JM		 201 uint64_t count;
202#endif
3fc6c082 203};
79aceca5 204
7c58044c
JM		 205static always_inline void gen_reset_fpstatus (void)
206{
207#ifdef CONFIG_SOFTFLOAT
a44d2ce1 208 gen_helper_reset_fpstatus();
7c58044c
JM		 209#endif
210}
211
0f2f39c2 212static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 213{
0f2f39c2 214 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 215
7c58044c
JM		 216 if (set_fprf != 0) {
217 /* This case might be optimized later */
0f2f39c2 218 tcg_gen_movi_i32(t0, 1);
af12906f 219 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 220 if (unlikely(set_rc)) {
0f2f39c2 221 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 222 }
af12906f 223 gen_helper_float_check_status();
7c58044c
JM		 224 } else if (unlikely(set_rc)) {
225 /* We always need to compute fpcc */
0f2f39c2 226 tcg_gen_movi_i32(t0, 0);
af12906f 227 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 228 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 229 }
af12906f 230
0f2f39c2 231 tcg_temp_free_i32(t0);
7c58044c
JM		 232}
233
76db3ba4 234static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
a7859e89 235{
76db3ba4
AJ		 236 if (ctx->access_type != access_type) {
237 tcg_gen_movi_i32(cpu_access_type, access_type);
238 ctx->access_type = access_type;
239 }
a7859e89
AJ		 240}
241
b068d6a7 242static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 243{
244#if defined(TARGET_PPC64)
245 if (ctx->sf_mode)
bd568f18 246 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 247 else
248#endif
bd568f18 249 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 250}
251
e06fcd75
AJ		 252static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
253{
254 TCGv_i32 t0, t1;
255 if (ctx->exception == POWERPC_EXCP_NONE) {
256 gen_update_nip(ctx, ctx->nip);
257 }
258 t0 = tcg_const_i32(excp);
259 t1 = tcg_const_i32(error);
260 gen_helper_raise_exception_err(t0, t1);
261 tcg_temp_free_i32(t0);
262 tcg_temp_free_i32(t1);
263 ctx->exception = (excp);
264}
e1833e1f 265
e06fcd75
AJ		 266static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
267{
268 TCGv_i32 t0;
269 if (ctx->exception == POWERPC_EXCP_NONE) {
270 gen_update_nip(ctx, ctx->nip);
271 }
272 t0 = tcg_const_i32(excp);
273 gen_helper_raise_exception(t0);
274 tcg_temp_free_i32(t0);
275 ctx->exception = (excp);
276}
e1833e1f 277
e06fcd75
AJ		 278static always_inline void gen_debug_exception (DisasContext *ctx)
279{
280 TCGv_i32 t0;
5518f3a6
BS		 281
282 if (ctx->exception != POWERPC_EXCP_BRANCH)
283 gen_update_nip(ctx, ctx->nip);
e06fcd75
AJ		 284 t0 = tcg_const_i32(EXCP_DEBUG);
285 gen_helper_raise_exception(t0);
286 tcg_temp_free_i32(t0);
287}
9a64fbe4 288
e06fcd75
AJ		 289static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
290{
291 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
292}
a9d9eb8f 293
f24e5695 294/* Stop translation */
e06fcd75 295static always_inline void gen_stop_exception (DisasContext *ctx)
3fc6c082 296{
d9bce9d9 297 gen_update_nip(ctx, ctx->nip);
e1833e1f 298 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 299}
300
f24e5695 301/* No need to update nip here, as execution flow will change */
e06fcd75 302static always_inline void gen_sync_exception (DisasContext *ctx)
2be0071f 303{
e1833e1f 304 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 305}
306
79aceca5
FB		 307#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
308static void gen_##name (DisasContext *ctx); \
309GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
310static void gen_##name (DisasContext *ctx)
311
c7697e1f
JM		 312#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
313static void gen_##name (DisasContext *ctx); \
314GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
315static void gen_##name (DisasContext *ctx)
316
79aceca5
FB		 317typedef struct opcode_t {
318 unsigned char opc1, opc2, opc3;
1235fc06 319#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 320 unsigned char pad[5];
321#else
322 unsigned char pad[1];
323#endif
79aceca5 324 opc_handler_t handler;
b55266b5 325 const char *oname;
79aceca5
FB		 326} opcode_t;
327
a750fc0b 328/*****************************************************************************/
79aceca5
FB		 329/*** Instruction decoding ***/
330#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 331static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 332{ \
333 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
334}
335
336#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 337static always_inline int32_t name (uint32_t opcode) \
79aceca5 338{ \
18fba28c 339 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 340}
341
342/* Opcode part 1 */
343EXTRACT_HELPER(opc1, 26, 6);
344/* Opcode part 2 */
345EXTRACT_HELPER(opc2, 1, 5);
346/* Opcode part 3 */
347EXTRACT_HELPER(opc3, 6, 5);
348/* Update Cr0 flags */
349EXTRACT_HELPER(Rc, 0, 1);
350/* Destination */
351EXTRACT_HELPER(rD, 21, 5);
352/* Source */
353EXTRACT_HELPER(rS, 21, 5);
354/* First operand */
355EXTRACT_HELPER(rA, 16, 5);
356/* Second operand */
357EXTRACT_HELPER(rB, 11, 5);
358/* Third operand */
359EXTRACT_HELPER(rC, 6, 5);
360/*** Get CRn ***/
361EXTRACT_HELPER(crfD, 23, 3);
362EXTRACT_HELPER(crfS, 18, 3);
363EXTRACT_HELPER(crbD, 21, 5);
364EXTRACT_HELPER(crbA, 16, 5);
365EXTRACT_HELPER(crbB, 11, 5);
366/* SPR / TBL */
3fc6c082 367EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 368static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 369{
370 uint32_t sprn = _SPR(opcode);
371
372 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
373}
79aceca5
FB		 374/*** Get constants ***/
375EXTRACT_HELPER(IMM, 12, 8);
376/* 16 bits signed immediate value */
377EXTRACT_SHELPER(SIMM, 0, 16);
378/* 16 bits unsigned immediate value */
379EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 380/* 5 bits signed immediate value */
381EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 382/* 5 bits signed immediate value */
383EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 384/* Bit count */
385EXTRACT_HELPER(NB, 11, 5);
386/* Shift count */
387EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 388/* Vector shift count */
389EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 390/* Mask start */
391EXTRACT_HELPER(MB, 6, 5);
392/* Mask end */
393EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 394/* Trap operand */
395EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 396
397EXTRACT_HELPER(CRM, 12, 8);
398EXTRACT_HELPER(FM, 17, 8);
399EXTRACT_HELPER(SR, 16, 4);
e4bb997e 400EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 401
79aceca5
FB		 402/*** Jump target decoding ***/
403/* Displacement */
404EXTRACT_SHELPER(d, 0, 16);
405/* Immediate address */
b068d6a7 406static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 407{
408 return (opcode >> 0) & 0x03FFFFFC;
409}
410
b068d6a7 411static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 412{
413 return (opcode >> 0) & 0xFFFC;
414}
415
416EXTRACT_HELPER(BO, 21, 5);
417EXTRACT_HELPER(BI, 16, 5);
418/* Absolute/relative address */
419EXTRACT_HELPER(AA, 1, 1);
420/* Link */
421EXTRACT_HELPER(LK, 0, 1);
422
423/* Create a mask between <start> and <end> bits */
b068d6a7 424static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 425{
76a66253 426 target_ulong ret;
79aceca5 427
76a66253
JM		 428#if defined(TARGET_PPC64)
429 if (likely(start == 0)) {
6f2d8978 430 ret = UINT64_MAX << (63 - end);
76a66253 431 } else if (likely(end == 63)) {
6f2d8978 432 ret = UINT64_MAX >> start;
76a66253
JM		 433 }
434#else
435 if (likely(start == 0)) {
6f2d8978 436 ret = UINT32_MAX << (31 - end);
76a66253 437 } else if (likely(end == 31)) {
6f2d8978 438 ret = UINT32_MAX >> start;
76a66253
JM		 439 }
440#endif
441 else {
442 ret = (((target_ulong)(-1ULL)) >> (start)) ^
443 (((target_ulong)(-1ULL) >> (end)) >> 1);
444 if (unlikely(start > end))
445 return ~ret;
446 }
79aceca5
FB		 447
448 return ret;
449}
450
a750fc0b
JM		 451/*****************************************************************************/
452/* PowerPC Instructions types definitions */
453enum {
1b413d55 454 PPC_NONE = 0x0000000000000000ULL,
12de9a39 455 /* PowerPC base instructions set */
1b413d55
JM		 456 PPC_INSNS_BASE = 0x0000000000000001ULL,
457 /* integer operations instructions */
a750fc0b 458#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 459 /* flow control instructions */
a750fc0b 460#define PPC_FLOW PPC_INSNS_BASE
1b413d55 461 /* virtual memory instructions */
a750fc0b 462#define PPC_MEM PPC_INSNS_BASE
1b413d55 463 /* ld/st with reservation instructions */
a750fc0b 464#define PPC_RES PPC_INSNS_BASE
1b413d55 465 /* spr/msr access instructions */
a750fc0b 466#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 467 /* Deprecated instruction sets */
468 /* Original POWER instruction set */
f610349f 469 PPC_POWER = 0x0000000000000002ULL,
1b413d55 470 /* POWER2 instruction set extension */
f610349f 471 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 472 /* Power RTC support */
f610349f 473 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 474 /* Power-to-PowerPC bridge (601) */
f610349f 475 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 476 /* 64 bits PowerPC instruction set */
f610349f 477 PPC_64B = 0x0000000000000020ULL,
1b413d55 478 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 479 PPC_64BX = 0x0000000000000040ULL,
1b413d55 480 /* 64 bits hypervisor extensions */
f610349f 481 PPC_64H = 0x0000000000000080ULL,
1b413d55 482 /* New wait instruction (PowerPC 2.0x) */
f610349f 483 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 484 /* Time base mftb instruction */
f610349f 485 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 486
487 /* Fixed-point unit extensions */
488 /* PowerPC 602 specific */
f610349f 489 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 490 /* isel instruction */
491 PPC_ISEL = 0x0000000000000800ULL,
492 /* popcntb instruction */
493 PPC_POPCNTB = 0x0000000000001000ULL,
494 /* string load / store */
495 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 496
497 /* Floating-point unit extensions */
498 /* Optional floating point instructions */
499 PPC_FLOAT = 0x0000000000010000ULL,
500 /* New floating-point extensions (PowerPC 2.0x) */
501 PPC_FLOAT_EXT = 0x0000000000020000ULL,
502 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
503 PPC_FLOAT_FRES = 0x0000000000080000ULL,
504 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
505 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
506 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
507 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
508
509 /* Vector/SIMD extensions */
510 /* Altivec support */
511 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 512 /* PowerPC 2.03 SPE extension */
05332d70 513 PPC_SPE = 0x0000000002000000ULL,
40569b7e
AJ		 514 /* PowerPC 2.03 SPE single-precision floating-point extension */
515 PPC_SPE_SINGLE = 0x0000000004000000ULL,
516 /* PowerPC 2.03 SPE double-precision floating-point extension */
517 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1b413d55 518
12de9a39 519 /* Optional memory control instructions */
1b413d55
JM		 520 PPC_MEM_TLBIA = 0x0000000010000000ULL,
521 PPC_MEM_TLBIE = 0x0000000020000000ULL,
522 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
523 /* sync instruction */
524 PPC_MEM_SYNC = 0x0000000080000000ULL,
525 /* eieio instruction */
526 PPC_MEM_EIEIO = 0x0000000100000000ULL,
527
528 /* Cache control instructions */
c8623f2e 529 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 530 /* icbi instruction */
05332d70 531 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 532 /* dcbz instruction with fixed cache line size */
05332d70 533 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 534 /* dcbz instruction with tunable cache line size */
05332d70 535 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 536 /* dcba instruction */
05332d70
JM		 537 PPC_CACHE_DCBA = 0x0000002000000000ULL,
538 /* Freescale cache locking instructions */
539 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 540
541 /* MMU related extensions */
542 /* external control instructions */
05332d70 543 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 544 /* segment register access instructions */
05332d70 545 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 546 /* PowerPC 6xx TLB management instructions */
05332d70 547 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 548 /* PowerPC 74xx TLB management instructions */
05332d70 549 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 550 /* PowerPC 40x TLB management instructions */
05332d70 551 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 552 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 553 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 554 /* SLB management */
05332d70 555 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 556
12de9a39 557 /* Embedded PowerPC dedicated instructions */
05332d70 558 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 559 /* PowerPC 40x exception model */
05332d70 560 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 561 /* PowerPC 405 Mac instructions */
05332d70 562 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 563 /* PowerPC 440 specific instructions */
05332d70 564 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 565 /* BookE (embedded) PowerPC specification */
05332d70
JM		 566 PPC_BOOKE = 0x0010000000000000ULL,
567 /* mfapidi instruction */
568 PPC_MFAPIDI = 0x0020000000000000ULL,
569 /* tlbiva instruction */
570 PPC_TLBIVA = 0x0040000000000000ULL,
571 /* tlbivax instruction */
572 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 573 /* PowerPC 4xx dedicated instructions */
05332d70 574 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 575 /* PowerPC 40x ibct instructions */
05332d70 576 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 577 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 578 PPC_RFMCI = 0x0400000000000000ULL,
579 /* rfdi instruction */
580 PPC_RFDI = 0x0800000000000000ULL,
581 /* DCR accesses */
582 PPC_DCR = 0x1000000000000000ULL,
583 /* DCR extended accesse */
584 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 585 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 586 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 587};
588
589/*****************************************************************************/
590/* PowerPC instructions table */
3fc6c082
FB		 591#if HOST_LONG_BITS == 64
592#define OPC_ALIGN 8
593#else
594#define OPC_ALIGN 4
595#endif
1b039c09 596#if defined(__APPLE__)
d9bce9d9 597#define OPCODES_SECTION \
3fc6c082 598 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 599#else
d9bce9d9 600#define OPCODES_SECTION \
3fc6c082 601 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 602#endif
603
76a66253 604#if defined(DO_PPC_STATISTICS)
79aceca5 605#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 606OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 607 .opc1 = op1, \
608 .opc2 = op2, \
609 .opc3 = op3, \
18fba28c 610 .pad = { 0, }, \
79aceca5
FB		 611 .handler = { \
612 .inval = invl, \
9a64fbe4 613 .type = _typ, \
79aceca5 614 .handler = &gen_##name, \
76a66253 615 .oname = stringify(name), \
79aceca5 616 }, \
3fc6c082 617 .oname = stringify(name), \
79aceca5 618}
c7697e1f
JM		 619#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
620OPCODES_SECTION opcode_t opc_##name = { \
621 .opc1 = op1, \
622 .opc2 = op2, \
623 .opc3 = op3, \
624 .pad = { 0, }, \
625 .handler = { \
626 .inval = invl, \
627 .type = _typ, \
628 .handler = &gen_##name, \
629 .oname = onam, \
630 }, \
631 .oname = onam, \
632}
76a66253
JM		 633#else
634#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
635OPCODES_SECTION opcode_t opc_##name = { \
636 .opc1 = op1, \
637 .opc2 = op2, \
638 .opc3 = op3, \
639 .pad = { 0, }, \
640 .handler = { \
641 .inval = invl, \
642 .type = _typ, \
643 .handler = &gen_##name, \
644 }, \
645 .oname = stringify(name), \
646}
c7697e1f
JM		 647#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
648OPCODES_SECTION opcode_t opc_##name = { \
649 .opc1 = op1, \
650 .opc2 = op2, \
651 .opc3 = op3, \
652 .pad = { 0, }, \
653 .handler = { \
654 .inval = invl, \
655 .type = _typ, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = onam, \
659}
76a66253 660#endif
79aceca5
FB		 661
662#define GEN_OPCODE_MARK(name) \
18fba28c 663OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 664 .opc1 = 0xFF, \
665 .opc2 = 0xFF, \
666 .opc3 = 0xFF, \
18fba28c 667 .pad = { 0, }, \
79aceca5
FB		 668 .handler = { \
669 .inval = 0x00000000, \
9a64fbe4 670 .type = 0x00, \
79aceca5
FB		 671 .handler = NULL, \
672 }, \
3fc6c082 673 .oname = stringify(name), \
79aceca5
FB		 674}
675
54cdcae6
AJ		 676/* SPR load/store helpers */
677static always_inline void gen_load_spr(TCGv t, int reg)
678{
679 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
680}
681
682static always_inline void gen_store_spr(int reg, TCGv t)
683{
684 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
685}
686
79aceca5
FB		 687/* Start opcode list */
688GEN_OPCODE_MARK(start);
689
690/* Invalid instruction */
9a64fbe4
FB		 691GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
692{
e06fcd75 693 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 694}
695
79aceca5
FB		 696static opc_handler_t invalid_handler = {
697 .inval = 0xFFFFFFFF,
9a64fbe4 698 .type = PPC_NONE,
79aceca5
FB		 699 .handler = gen_invalid,
700};
701
e1571908
AJ		 702/*** Integer comparison ***/
703
ea363694 704static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 705{
706 int l1, l2, l3;
707
269f3e95
AJ		 708 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
709 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 710 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
711
712 l1 = gen_new_label();
713 l2 = gen_new_label();
714 l3 = gen_new_label();
715 if (s) {
ea363694
AJ		 716 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
717 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 718 } else {
ea363694
AJ		 719 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
720 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 721 }
722 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
723 tcg_gen_br(l3);
724 gen_set_label(l1);
725 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
726 tcg_gen_br(l3);
727 gen_set_label(l2);
728 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
729 gen_set_label(l3);
730}
731
ea363694 732static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 733{
ea363694
AJ		 734 TCGv t0 = tcg_const_local_tl(arg1);
735 gen_op_cmp(arg0, t0, s, crf);
736 tcg_temp_free(t0);
e1571908
AJ		 737}
738
739#if defined(TARGET_PPC64)
ea363694 740static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 741{
ea363694 742 TCGv t0, t1;
a7812ae4
PB		 743 t0 = tcg_temp_local_new();
744 t1 = tcg_temp_local_new();
e1571908 745 if (s) {
ea363694
AJ		 746 tcg_gen_ext32s_tl(t0, arg0);
747 tcg_gen_ext32s_tl(t1, arg1);
e1571908 748 } else {
ea363694
AJ		 749 tcg_gen_ext32u_tl(t0, arg0);
750 tcg_gen_ext32u_tl(t1, arg1);
e1571908 751 }
ea363694
AJ		 752 gen_op_cmp(t0, t1, s, crf);
753 tcg_temp_free(t1);
754 tcg_temp_free(t0);
e1571908
AJ		 755}
756
ea363694 757static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 758{
ea363694
AJ		 759 TCGv t0 = tcg_const_local_tl(arg1);
760 gen_op_cmp32(arg0, t0, s, crf);
761 tcg_temp_free(t0);
e1571908
AJ		 762}
763#endif
764
765static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
766{
767#if defined(TARGET_PPC64)
768 if (!(ctx->sf_mode))
769 gen_op_cmpi32(reg, 0, 1, 0);
770 else
771#endif
772 gen_op_cmpi(reg, 0, 1, 0);
773}
774
775/* cmp */
776GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
777{
778#if defined(TARGET_PPC64)
779 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
780 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
781 1, crfD(ctx->opcode));
782 else
783#endif
784 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
785 1, crfD(ctx->opcode));
786}
787
788/* cmpi */
789GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
790{
791#if defined(TARGET_PPC64)
792 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
793 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
794 1, crfD(ctx->opcode));
795 else
796#endif
797 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
798 1, crfD(ctx->opcode));
799}
800
801/* cmpl */
802GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
803{
804#if defined(TARGET_PPC64)
805 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
806 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
807 0, crfD(ctx->opcode));
808 else
809#endif
810 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
811 0, crfD(ctx->opcode));
812}
813
814/* cmpli */
815GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
816{
817#if defined(TARGET_PPC64)
818 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
819 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
820 0, crfD(ctx->opcode));
821 else
822#endif
823 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
824 0, crfD(ctx->opcode));
825}
826
827/* isel (PowerPC 2.03 specification) */
828GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
829{
830 int l1, l2;
831 uint32_t bi = rC(ctx->opcode);
832 uint32_t mask;
a7812ae4 833 TCGv_i32 t0;
e1571908
AJ		 834
835 l1 = gen_new_label();
836 l2 = gen_new_label();
837
838 mask = 1 << (3 - (bi & 0x03));
a7812ae4 839 t0 = tcg_temp_new_i32();
fea0c503
AJ		 840 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
841 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 842 if (rA(ctx->opcode) == 0)
843 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
844 else
845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
846 tcg_gen_br(l2);
847 gen_set_label(l1);
848 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
849 gen_set_label(l2);
a7812ae4 850 tcg_temp_free_i32(t0);
e1571908
AJ		 851}
852
79aceca5 853/*** Integer arithmetic ***/
79aceca5 854
74637406
AJ		 855static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
856{
857 int l1;
858 TCGv t0;
79aceca5 859
74637406
AJ		 860 l1 = gen_new_label();
861 /* Start with XER OV disabled, the most likely case */
862 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 863 t0 = tcg_temp_local_new();
74637406
AJ		 864 tcg_gen_xor_tl(t0, arg0, arg1);
865#if defined(TARGET_PPC64)
866 if (!ctx->sf_mode)
867 tcg_gen_ext32s_tl(t0, t0);
868#endif
869 if (sub)
870 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
871 else
872 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
873 tcg_gen_xor_tl(t0, arg1, arg2);
874#if defined(TARGET_PPC64)
875 if (!ctx->sf_mode)
876 tcg_gen_ext32s_tl(t0, t0);
877#endif
878 if (sub)
879 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
880 else
881 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
882 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
883 gen_set_label(l1);
884 tcg_temp_free(t0);
79aceca5
FB		 885}
886
74637406
AJ		 887static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
888{
889 int l1 = gen_new_label();
d9bce9d9
JM		 890
891#if defined(TARGET_PPC64)
74637406
AJ		 892 if (!(ctx->sf_mode)) {
893 TCGv t0, t1;
a7812ae4
PB		 894 t0 = tcg_temp_new();
895 t1 = tcg_temp_new();
d9bce9d9 896
74637406
AJ		 897 tcg_gen_ext32u_tl(t0, arg1);
898 tcg_gen_ext32u_tl(t1, arg2);
899 if (sub) {
900 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 901 } else {
74637406
AJ		 902 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
903 }
a9730017
AJ		 904 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
905 gen_set_label(l1);
906 tcg_temp_free(t0);
907 tcg_temp_free(t1);
74637406
AJ		 908 } else
909#endif
a9730017
AJ		 910 {
911 if (sub) {
912 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
913 } else {
914 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
915 }
916 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
917 gen_set_label(l1);
74637406 918 }
d9bce9d9
JM		 919}
920
74637406
AJ		 921/* Common add function */
922static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
923 int add_ca, int compute_ca, int compute_ov)
924{
925 TCGv t0, t1;
d9bce9d9 926
74637406 927 if ((!compute_ca && !compute_ov) ||
a7812ae4 928 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 929 t0 = ret;
930 } else {
a7812ae4 931 t0 = tcg_temp_local_new();
74637406 932 }
79aceca5 933
74637406 934 if (add_ca) {
a7812ae4 935 t1 = tcg_temp_local_new();
74637406
AJ		 936 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
937 tcg_gen_shri_tl(t1, t1, XER_CA);
938 }
79aceca5 939
74637406
AJ		 940 if (compute_ca && compute_ov) {
941 /* Start with XER CA and OV disabled, the most likely case */
942 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
943 } else if (compute_ca) {
944 /* Start with XER CA disabled, the most likely case */
945 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
946 } else if (compute_ov) {
947 /* Start with XER OV disabled, the most likely case */
948 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
949 }
79aceca5 950
74637406
AJ		 951 tcg_gen_add_tl(t0, arg1, arg2);
952
953 if (compute_ca) {
954 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
955 }
956 if (add_ca) {
957 tcg_gen_add_tl(t0, t0, t1);
958 gen_op_arith_compute_ca(ctx, t0, t1, 0);
959 tcg_temp_free(t1);
960 }
961 if (compute_ov) {
962 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
963 }
964
965 if (unlikely(Rc(ctx->opcode) != 0))
966 gen_set_Rc0(ctx, t0);
967
a7812ae4 968 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 969 tcg_gen_mov_tl(ret, t0);
970 tcg_temp_free(t0);
971 }
39dd32ee 972}
74637406
AJ		 973/* Add functions with two operands */
974#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
975GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
976{ \
977 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 add_ca, compute_ca, compute_ov); \
980}
981/* Add functions with one operand and one immediate */
982#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
983 add_ca, compute_ca, compute_ov) \
984GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
985{ \
986 TCGv t0 = tcg_const_local_tl(const_val); \
987 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
988 cpu_gpr[rA(ctx->opcode)], t0, \
989 add_ca, compute_ca, compute_ov); \
990 tcg_temp_free(t0); \
991}
992
993/* add add. addo addo. */
994GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
995GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
996/* addc addc. addco addco. */
997GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
998GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
999/* adde adde. addeo addeo. */
1000GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1001GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1002/* addme addme. addmeo addmeo. */
1003GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1004GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1005/* addze addze. addzeo addzeo.*/
1006GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1007GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1008/* addi */
1009GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1010{
74637406
AJ		 1011 target_long simm = SIMM(ctx->opcode);
1012
1013 if (rA(ctx->opcode) == 0) {
1014 /* li case */
1015 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1016 } else {
1017 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1018 }
d9bce9d9 1019}
74637406
AJ		 1020/* addic addic.*/
1021static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1022 int compute_Rc0)
d9bce9d9 1023{
74637406
AJ		 1024 target_long simm = SIMM(ctx->opcode);
1025
1026 /* Start with XER CA and OV disabled, the most likely case */
1027 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1028
1029 if (likely(simm != 0)) {
a7812ae4 1030 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1031 tcg_gen_addi_tl(t0, arg1, simm);
1032 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1033 tcg_gen_mov_tl(ret, t0);
1034 tcg_temp_free(t0);
1035 } else {
1036 tcg_gen_mov_tl(ret, arg1);
1037 }
1038 if (compute_Rc0) {
1039 gen_set_Rc0(ctx, ret);
1040 }
d9bce9d9 1041}
74637406 1042GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1043{
74637406 1044 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1045}
74637406 1046GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1047{
74637406 1048 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1049}
74637406
AJ		 1050/* addis */
1051GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1052{
74637406
AJ		 1053 target_long simm = SIMM(ctx->opcode);
1054
1055 if (rA(ctx->opcode) == 0) {
1056 /* lis case */
1057 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1058 } else {
1059 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1060 }
d9bce9d9 1061}
74637406
AJ		 1062
1063static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1064 int sign, int compute_ov)
d9bce9d9 1065{
2ef1b120
AJ		 1066 int l1 = gen_new_label();
1067 int l2 = gen_new_label();
a7812ae4
PB		 1068 TCGv_i32 t0 = tcg_temp_local_new_i32();
1069 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1070
2ef1b120
AJ		 1071 tcg_gen_trunc_tl_i32(t0, arg1);
1072 tcg_gen_trunc_tl_i32(t1, arg2);
1073 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1074 if (sign) {
2ef1b120
AJ		 1075 int l3 = gen_new_label();
1076 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1078 gen_set_label(l3);
2ef1b120 1079 tcg_gen_div_i32(t0, t0, t1);
74637406 1080 } else {
2ef1b120 1081 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1082 }
1083 if (compute_ov) {
1084 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1085 }
1086 tcg_gen_br(l2);
1087 gen_set_label(l1);
1088 if (sign) {
2ef1b120 1089 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1090 } else {
1091 tcg_gen_movi_i32(t0, 0);
1092 }
1093 if (compute_ov) {
1094 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1095 }
1096 gen_set_label(l2);
2ef1b120 1097 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1098 tcg_temp_free_i32(t0);
1099 tcg_temp_free_i32(t1);
74637406
AJ		 1100 if (unlikely(Rc(ctx->opcode) != 0))
1101 gen_set_Rc0(ctx, ret);
d9bce9d9 1102}
74637406
AJ		 1103/* Div functions */
1104#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1105GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1106{ \
1107 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1108 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1109 sign, compute_ov); \
1110}
1111/* divwu divwu. divwuo divwuo. */
1112GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1113GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1114/* divw divw. divwo divwo. */
1115GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1116GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1117#if defined(TARGET_PPC64)
2ef1b120
AJ		 1118static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1119 int sign, int compute_ov)
d9bce9d9 1120{
2ef1b120
AJ		 1121 int l1 = gen_new_label();
1122 int l2 = gen_new_label();
74637406
AJ		 1123
1124 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1125 if (sign) {
2ef1b120 1126 int l3 = gen_new_label();
74637406
AJ		 1127 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1128 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1129 gen_set_label(l3);
74637406
AJ		 1130 tcg_gen_div_i64(ret, arg1, arg2);
1131 } else {
1132 tcg_gen_divu_i64(ret, arg1, arg2);
1133 }
1134 if (compute_ov) {
1135 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1136 }
1137 tcg_gen_br(l2);
1138 gen_set_label(l1);
1139 if (sign) {
1140 tcg_gen_sari_i64(ret, arg1, 63);
1141 } else {
1142 tcg_gen_movi_i64(ret, 0);
1143 }
1144 if (compute_ov) {
1145 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1146 }
1147 gen_set_label(l2);
1148 if (unlikely(Rc(ctx->opcode) != 0))
1149 gen_set_Rc0(ctx, ret);
d9bce9d9 1150}
74637406
AJ		 1151#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1152GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1153{ \
2ef1b120
AJ		 1154 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1155 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1156 sign, compute_ov); \
74637406
AJ		 1157}
1158/* divwu divwu. divwuo divwuo. */
1159GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1160GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1161/* divw divw. divwo divwo. */
1162GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1163GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1164#endif
74637406
AJ		 1165
1166/* mulhw mulhw. */
1167GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1168{
a7812ae4 1169 TCGv_i64 t0, t1;
74637406 1170
a7812ae4
PB		 1171 t0 = tcg_temp_new_i64();
1172 t1 = tcg_temp_new_i64();
74637406
AJ		 1173#if defined(TARGET_PPC64)
1174 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1175 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1176 tcg_gen_mul_i64(t0, t0, t1);
1177 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1178#else
1179 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(t0, t0, 32);
1183 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1184#endif
a7812ae4
PB		 1185 tcg_temp_free_i64(t0);
1186 tcg_temp_free_i64(t1);
74637406
AJ		 1187 if (unlikely(Rc(ctx->opcode) != 0))
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1189}
74637406
AJ		 1190/* mulhwu mulhwu. */
1191GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1192{
a7812ae4 1193 TCGv_i64 t0, t1;
74637406 1194
a7812ae4
PB		 1195 t0 = tcg_temp_new_i64();
1196 t1 = tcg_temp_new_i64();
d9bce9d9 1197#if defined(TARGET_PPC64)
74637406
AJ		 1198 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1199 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1200 tcg_gen_mul_i64(t0, t0, t1);
1201 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1202#else
1203 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(t0, t0, 32);
1207 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1208#endif
a7812ae4
PB		 1209 tcg_temp_free_i64(t0);
1210 tcg_temp_free_i64(t1);
74637406
AJ		 1211 if (unlikely(Rc(ctx->opcode) != 0))
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1213}
74637406
AJ		 1214/* mullw mullw. */
1215GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1216{
74637406
AJ		 1217 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1218 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1219 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1220 if (unlikely(Rc(ctx->opcode) != 0))
1221 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1222}
74637406
AJ		 1223/* mullwo mullwo. */
1224GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1225{
74637406 1226 int l1;
a7812ae4 1227 TCGv_i64 t0, t1;
74637406 1228
a7812ae4
PB		 1229 t0 = tcg_temp_new_i64();
1230 t1 = tcg_temp_new_i64();
74637406
AJ		 1231 l1 = gen_new_label();
1232 /* Start with XER OV disabled, the most likely case */
1233 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1234#if defined(TARGET_PPC64)
1235 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1236 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1237#else
1238 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1239 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1240#endif
74637406
AJ		 1241 tcg_gen_mul_i64(t0, t0, t1);
1242#if defined(TARGET_PPC64)
1243 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1244 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1245#else
1246 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1247 tcg_gen_ext32s_i64(t1, t0);
1248 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1249#endif
1250 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1251 gen_set_label(l1);
a7812ae4
PB		 1252 tcg_temp_free_i64(t0);
1253 tcg_temp_free_i64(t1);
74637406
AJ		 1254 if (unlikely(Rc(ctx->opcode) != 0))
1255 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1256}
74637406
AJ		 1257/* mulli */
1258GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1259{
74637406
AJ		 1260 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1261 SIMM(ctx->opcode));
d9bce9d9
JM		 1262}
1263#if defined(TARGET_PPC64)
74637406
AJ		 1264#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1265GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1266{ \
a7812ae4 1267 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1268 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1269 if (unlikely(Rc(ctx->opcode) != 0)) \
1270 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1271}
74637406
AJ		 1272/* mulhd mulhd. */
1273GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1274/* mulhdu mulhdu. */
1275GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1276/* mulld mulld. */
1277GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1278{
74637406
AJ		 1279 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1280 cpu_gpr[rB(ctx->opcode)]);
1281 if (unlikely(Rc(ctx->opcode) != 0))
1282 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1283}
74637406
AJ		 1284/* mulldo mulldo. */
1285GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1286#endif
74637406
AJ		 1287
1288/* neg neg. nego nego. */
ec6469a3 1289static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1290{
ec6469a3
AJ		 1291 int l1 = gen_new_label();
1292 int l2 = gen_new_label();
a7812ae4 1293 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1294#if defined(TARGET_PPC64)
74637406 1295 if (ctx->sf_mode) {
741a7444 1296 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1297 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1298 } else
1299#endif
1300 {
1301 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1303 }
74637406
AJ		 1304 tcg_gen_neg_tl(ret, arg1);
1305 if (ov_check) {
1306 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1307 }
1308 tcg_gen_br(l2);
1309 gen_set_label(l1);
ec6469a3 1310 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1311 if (ov_check) {
1312 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1313 }
1314 gen_set_label(l2);
ec6469a3 1315 tcg_temp_free(t0);
74637406
AJ		 1316 if (unlikely(Rc(ctx->opcode) != 0))
1317 gen_set_Rc0(ctx, ret);
1318}
1319GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1320{
ec6469a3 1321 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1322}
74637406 1323GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1324{
ec6469a3 1325 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1326}
74637406
AJ		 1327
1328/* Common subf function */
1329static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1330 int add_ca, int compute_ca, int compute_ov)
79aceca5 1331{
74637406 1332 TCGv t0, t1;
76a66253 1333
74637406 1334 if ((!compute_ca && !compute_ov) ||
a7812ae4 1335 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1336 t0 = ret;
e864cabd 1337 } else {
a7812ae4 1338 t0 = tcg_temp_local_new();
d9bce9d9 1339 }
76a66253 1340
74637406 1341 if (add_ca) {
a7812ae4 1342 t1 = tcg_temp_local_new();
74637406
AJ		 1343 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1344 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1345 }
79aceca5 1346
74637406
AJ		 1347 if (compute_ca && compute_ov) {
1348 /* Start with XER CA and OV disabled, the most likely case */
1349 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1350 } else if (compute_ca) {
1351 /* Start with XER CA disabled, the most likely case */
1352 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1353 } else if (compute_ov) {
1354 /* Start with XER OV disabled, the most likely case */
1355 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1356 }
1357
1358 if (add_ca) {
1359 tcg_gen_not_tl(t0, arg1);
1360 tcg_gen_add_tl(t0, t0, arg2);
1361 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1362 tcg_gen_add_tl(t0, t0, t1);
1363 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1364 tcg_temp_free(t1);
79aceca5 1365 } else {
74637406
AJ		 1366 tcg_gen_sub_tl(t0, arg2, arg1);
1367 if (compute_ca) {
1368 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1369 }
1370 }
1371 if (compute_ov) {
1372 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1373 }
1374
1375 if (unlikely(Rc(ctx->opcode) != 0))
1376 gen_set_Rc0(ctx, t0);
1377
a7812ae4 1378 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1379 tcg_gen_mov_tl(ret, t0);
1380 tcg_temp_free(t0);
79aceca5 1381 }
79aceca5 1382}
74637406
AJ		 1383/* Sub functions with Two operands functions */
1384#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1385GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1386{ \
1387 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1388 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1389 add_ca, compute_ca, compute_ov); \
1390}
1391/* Sub functions with one operand and one immediate */
1392#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1393 add_ca, compute_ca, compute_ov) \
1394GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1395{ \
1396 TCGv t0 = tcg_const_local_tl(const_val); \
1397 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1398 cpu_gpr[rA(ctx->opcode)], t0, \
1399 add_ca, compute_ca, compute_ov); \
1400 tcg_temp_free(t0); \
1401}
1402/* subf subf. subfo subfo. */
1403GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1404GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1405/* subfc subfc. subfco subfco. */
1406GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1407GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1408/* subfe subfe. subfeo subfo. */
1409GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1410GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1411/* subfme subfme. subfmeo subfmeo. */
1412GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1413GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1414/* subfze subfze. subfzeo subfzeo.*/
1415GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1416GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1417/* subfic */
1418GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1419{
74637406
AJ		 1420 /* Start with XER CA and OV disabled, the most likely case */
1421 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1422 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1423 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1424 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1425 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1426 tcg_temp_free(t1);
1427 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1428 tcg_temp_free(t0);
79aceca5
FB		 1429}
1430
79aceca5 1431/*** Integer logical ***/
26d67362
AJ		 1432#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1433GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1434{ \
26d67362
AJ		 1435 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1436 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1437 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1438 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1439}
79aceca5 1440
26d67362 1441#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1442GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1443{ \
26d67362 1444 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1445 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1446 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1447}
1448
1449/* and & and. */
26d67362 1450GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1451/* andc & andc. */
26d67362 1452GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1453/* andi. */
c7697e1f 1454GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1455{
26d67362
AJ		 1456 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1457 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1458}
1459/* andis. */
c7697e1f 1460GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1461{
26d67362
AJ		 1462 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1463 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1464}
79aceca5 1465/* cntlzw */
26d67362
AJ		 1466GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1467{
a7812ae4 1468 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1469 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1470 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1471}
79aceca5 1472/* eqv & eqv. */
26d67362 1473GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1474/* extsb & extsb. */
26d67362 1475GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1476/* extsh & extsh. */
26d67362 1477GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1478/* nand & nand. */
26d67362 1479GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1480/* nor & nor. */
26d67362 1481GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1482/* or & or. */
9a64fbe4
FB		 1483GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1484{
76a66253
JM		 1485 int rs, ra, rb;
1486
1487 rs = rS(ctx->opcode);
1488 ra = rA(ctx->opcode);
1489 rb = rB(ctx->opcode);
1490 /* Optimisation for mr. ri case */
1491 if (rs != ra || rs != rb) {
26d67362
AJ		 1492 if (rs != rb)
1493 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1494 else
1495 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1496 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1497 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1498 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1499 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1500#if defined(TARGET_PPC64)
1501 } else {
26d67362
AJ		 1502 int prio = 0;
1503
c80f84e3
JM		 1504 switch (rs) {
1505 case 1:
1506 /* Set process priority to low */
26d67362 1507 prio = 2;
c80f84e3
JM		 1508 break;
1509 case 6:
1510 /* Set process priority to medium-low */
26d67362 1511 prio = 3;
c80f84e3
JM		 1512 break;
1513 case 2:
1514 /* Set process priority to normal */
26d67362 1515 prio = 4;
c80f84e3 1516 break;
be147d08
JM		 1517#if !defined(CONFIG_USER_ONLY)
1518 case 31:
76db3ba4 1519 if (ctx->mem_idx > 0) {
be147d08 1520 /* Set process priority to very low */
26d67362 1521 prio = 1;
be147d08
JM		 1522 }
1523 break;
1524 case 5:
76db3ba4 1525 if (ctx->mem_idx > 0) {
be147d08 1526 /* Set process priority to medium-hight */
26d67362 1527 prio = 5;
be147d08
JM		 1528 }
1529 break;
1530 case 3:
76db3ba4 1531 if (ctx->mem_idx > 0) {
be147d08 1532 /* Set process priority to high */
26d67362 1533 prio = 6;
be147d08
JM		 1534 }
1535 break;
be147d08 1536 case 7:
76db3ba4 1537 if (ctx->mem_idx > 1) {
be147d08 1538 /* Set process priority to very high */
26d67362 1539 prio = 7;
be147d08
JM		 1540 }
1541 break;
be147d08 1542#endif
c80f84e3
JM		 1543 default:
1544 /* nop */
1545 break;
1546 }
26d67362 1547 if (prio) {
a7812ae4 1548 TCGv t0 = tcg_temp_new();
54cdcae6 1549 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1550 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1551 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1552 gen_store_spr(SPR_PPR, t0);
ea363694 1553 tcg_temp_free(t0);
26d67362 1554 }
c80f84e3 1555#endif
9a64fbe4 1556 }
9a64fbe4 1557}
79aceca5 1558/* orc & orc. */
26d67362 1559GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1560/* xor & xor. */
9a64fbe4
FB		 1561GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1562{
9a64fbe4 1563 /* Optimisation for "set to zero" case */
26d67362 1564 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1565 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1566 else
1567 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1568 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1570}
79aceca5
FB		 1571/* ori */
1572GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1573{
76a66253 1574 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1575
9a64fbe4
FB		 1576 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1577 /* NOP */
76a66253 1578 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1579 return;
76a66253 1580 }
26d67362 1581 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1582}
1583/* oris */
1584GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1585{
76a66253 1586 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1587
9a64fbe4
FB		 1588 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1589 /* NOP */
1590 return;
76a66253 1591 }
26d67362 1592 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1593}
1594/* xori */
1595GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1596{
76a66253 1597 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1598
1599 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1600 /* NOP */
1601 return;
1602 }
26d67362 1603 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1604}
79aceca5
FB		 1605/* xoris */
1606GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1607{
76a66253 1608 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1609
1610 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1611 /* NOP */
1612 return;
1613 }
26d67362 1614 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1615}
d9bce9d9 1616/* popcntb : PowerPC 2.03 specification */
05332d70 1617GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1618{
d9bce9d9
JM		 1619#if defined(TARGET_PPC64)
1620 if (ctx->sf_mode)
a7812ae4 1621 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1622 else
1623#endif
a7812ae4 1624 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1625}
1626
1627#if defined(TARGET_PPC64)
1628/* extsw & extsw. */
26d67362 1629GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1630/* cntlzd */
26d67362
AJ		 1631GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1632{
a7812ae4 1633 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1634 if (unlikely(Rc(ctx->opcode) != 0))
1635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1636}
d9bce9d9
JM		 1637#endif
1638
79aceca5
FB		 1639/*** Integer rotate ***/
1640/* rlwimi & rlwimi. */
1641GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1642{
76a66253 1643 uint32_t mb, me, sh;
79aceca5
FB		 1644
1645 mb = MB(ctx->opcode);
1646 me = ME(ctx->opcode);
76a66253 1647 sh = SH(ctx->opcode);
d03ef511
AJ		 1648 if (likely(sh == 0 && mb == 0 && me == 31)) {
1649 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1650 } else {
d03ef511 1651 target_ulong mask;
a7812ae4
PB		 1652 TCGv t1;
1653 TCGv t0 = tcg_temp_new();
54843a58 1654#if defined(TARGET_PPC64)
a7812ae4
PB		 1655 TCGv_i32 t2 = tcg_temp_new_i32();
1656 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1657 tcg_gen_rotli_i32(t2, t2, sh);
1658 tcg_gen_extu_i32_i64(t0, t2);
1659 tcg_temp_free_i32(t2);
54843a58
AJ		 1660#else
1661 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1662#endif
76a66253 1663#if defined(TARGET_PPC64)
d03ef511
AJ		 1664 mb += 32;
1665 me += 32;
76a66253 1666#endif
d03ef511 1667 mask = MASK(mb, me);
a7812ae4 1668 t1 = tcg_temp_new();
d03ef511
AJ		 1669 tcg_gen_andi_tl(t0, t0, mask);
1670 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1671 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1672 tcg_temp_free(t0);
1673 tcg_temp_free(t1);
1674 }
76a66253 1675 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1676 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1677}
1678/* rlwinm & rlwinm. */
1679GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1680{
1681 uint32_t mb, me, sh;
3b46e624 1682
79aceca5
FB		 1683 sh = SH(ctx->opcode);
1684 mb = MB(ctx->opcode);
1685 me = ME(ctx->opcode);
d03ef511
AJ		 1686
1687 if (likely(mb == 0 && me == (31 - sh))) {
1688 if (likely(sh == 0)) {
1689 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1690 } else {
a7812ae4 1691 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1692 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1693 tcg_gen_shli_tl(t0, t0, sh);
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1695 tcg_temp_free(t0);
79aceca5 1696 }
d03ef511 1697 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1698 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1699 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1700 tcg_gen_shri_tl(t0, t0, mb);
1701 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1702 tcg_temp_free(t0);
1703 } else {
a7812ae4 1704 TCGv t0 = tcg_temp_new();
54843a58 1705#if defined(TARGET_PPC64)
a7812ae4 1706 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1707 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1708 tcg_gen_rotli_i32(t1, t1, sh);
1709 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1710 tcg_temp_free_i32(t1);
54843a58
AJ		 1711#else
1712 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1713#endif
76a66253 1714#if defined(TARGET_PPC64)
d03ef511
AJ		 1715 mb += 32;
1716 me += 32;
76a66253 1717#endif
d03ef511
AJ		 1718 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1719 tcg_temp_free(t0);
1720 }
76a66253 1721 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1722 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1723}
1724/* rlwnm & rlwnm. */
1725GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1726{
1727 uint32_t mb, me;
54843a58
AJ		 1728 TCGv t0;
1729#if defined(TARGET_PPC64)
a7812ae4 1730 TCGv_i32 t1, t2;
54843a58 1731#endif
79aceca5
FB		 1732
1733 mb = MB(ctx->opcode);
1734 me = ME(ctx->opcode);
a7812ae4 1735 t0 = tcg_temp_new();
d03ef511 1736 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1737#if defined(TARGET_PPC64)
a7812ae4
PB		 1738 t1 = tcg_temp_new_i32();
1739 t2 = tcg_temp_new_i32();
54843a58
AJ		 1740 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1741 tcg_gen_trunc_i64_i32(t2, t0);
1742 tcg_gen_rotl_i32(t1, t1, t2);
1743 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1744 tcg_temp_free_i32(t1);
1745 tcg_temp_free_i32(t2);
54843a58
AJ		 1746#else
1747 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1748#endif
76a66253
JM		 1749 if (unlikely(mb != 0 || me != 31)) {
1750#if defined(TARGET_PPC64)
1751 mb += 32;
1752 me += 32;
1753#endif
54843a58 1754 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1755 } else {
54843a58 1756 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1757 }
54843a58 1758 tcg_temp_free(t0);
76a66253 1759 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1760 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1761}
1762
d9bce9d9
JM		 1763#if defined(TARGET_PPC64)
1764#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1765GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1766{ \
1767 gen_##name(ctx, 0); \
1768} \
c7697e1f
JM		 1769GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1770 PPC_64B) \
d9bce9d9
JM		 1771{ \
1772 gen_##name(ctx, 1); \
1773}
1774#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1775GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1776{ \
1777 gen_##name(ctx, 0, 0); \
1778} \
c7697e1f
JM		 1779GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1780 PPC_64B) \
d9bce9d9
JM		 1781{ \
1782 gen_##name(ctx, 0, 1); \
1783} \
c7697e1f
JM		 1784GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1785 PPC_64B) \
d9bce9d9
JM		 1786{ \
1787 gen_##name(ctx, 1, 0); \
1788} \
c7697e1f
JM		 1789GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1790 PPC_64B) \
d9bce9d9
JM		 1791{ \
1792 gen_##name(ctx, 1, 1); \
1793}
51789c41 1794
b068d6a7
JM		 1795static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1796 uint32_t me, uint32_t sh)
51789c41 1797{
d03ef511
AJ		 1798 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1799 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1800 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1801 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1802 } else {
a7812ae4 1803 TCGv t0 = tcg_temp_new();
54843a58 1804 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1805 if (likely(mb == 0 && me == 63)) {
54843a58 1806 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1807 } else {
1808 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1809 }
d03ef511 1810 tcg_temp_free(t0);
51789c41 1811 }
51789c41 1812 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1814}
d9bce9d9 1815/* rldicl - rldicl. */
b068d6a7 1816static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1817{
51789c41 1818 uint32_t sh, mb;
d9bce9d9 1819
9d53c753
JM		 1820 sh = SH(ctx->opcode) | (shn << 5);
1821 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1822 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1823}
51789c41 1824GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1825/* rldicr - rldicr. */
b068d6a7 1826static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1827{
51789c41 1828 uint32_t sh, me;
d9bce9d9 1829
9d53c753
JM		 1830 sh = SH(ctx->opcode) | (shn << 5);
1831 me = MB(ctx->opcode) | (men << 5);
51789c41 1832 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1833}
51789c41 1834GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1835/* rldic - rldic. */
b068d6a7 1836static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1837{
51789c41 1838 uint32_t sh, mb;
d9bce9d9 1839
9d53c753
JM		 1840 sh = SH(ctx->opcode) | (shn << 5);
1841 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1842 gen_rldinm(ctx, mb, 63 - sh, sh);
1843}
1844GEN_PPC64_R4(rldic, 0x1E, 0x04);
1845
b068d6a7
JM		 1846static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1847 uint32_t me)
51789c41 1848{
54843a58 1849 TCGv t0;
d03ef511
AJ		 1850
1851 mb = MB(ctx->opcode);
1852 me = ME(ctx->opcode);
a7812ae4 1853 t0 = tcg_temp_new();
d03ef511 1854 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1855 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1856 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1857 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1858 } else {
1859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1860 }
1861 tcg_temp_free(t0);
51789c41 1862 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1863 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1864}
51789c41 1865
d9bce9d9 1866/* rldcl - rldcl. */
b068d6a7 1867static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1868{
51789c41 1869 uint32_t mb;
d9bce9d9 1870
9d53c753 1871 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1872 gen_rldnm(ctx, mb, 63);
d9bce9d9 1873}
36081602 1874GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1875/* rldcr - rldcr. */
b068d6a7 1876static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1877{
51789c41 1878 uint32_t me;
d9bce9d9 1879
9d53c753 1880 me = MB(ctx->opcode) | (men << 5);
51789c41 1881 gen_rldnm(ctx, 0, me);
d9bce9d9 1882}
36081602 1883GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1884/* rldimi - rldimi. */
b068d6a7 1885static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1886{
271a916e 1887 uint32_t sh, mb, me;
d9bce9d9 1888
9d53c753
JM		 1889 sh = SH(ctx->opcode) | (shn << 5);
1890 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1891 me = 63 - sh;
d03ef511
AJ		 1892 if (unlikely(sh == 0 && mb == 0)) {
1893 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1894 } else {
1895 TCGv t0, t1;
1896 target_ulong mask;
1897
a7812ae4 1898 t0 = tcg_temp_new();
54843a58 1899 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1900 t1 = tcg_temp_new();
d03ef511
AJ		 1901 mask = MASK(mb, me);
1902 tcg_gen_andi_tl(t0, t0, mask);
1903 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1904 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1905 tcg_temp_free(t0);
1906 tcg_temp_free(t1);
51789c41 1907 }
51789c41 1908 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1910}
36081602 1911GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1912#endif
1913
79aceca5
FB		 1914/*** Integer shift ***/
1915/* slw & slw. */
26d67362
AJ		 1916GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1917{
fea0c503 1918 TCGv t0;
26d67362
AJ		 1919 int l1, l2;
1920 l1 = gen_new_label();
1921 l2 = gen_new_label();
1922
a7812ae4 1923 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1924 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1925 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1926 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1927 tcg_gen_br(l2);
1928 gen_set_label(l1);
fea0c503 1929 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1930 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1931 gen_set_label(l2);
fea0c503 1932 tcg_temp_free(t0);
26d67362
AJ		 1933 if (unlikely(Rc(ctx->opcode) != 0))
1934 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1935}
79aceca5 1936/* sraw & sraw. */
26d67362
AJ		 1937GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1938{
a7812ae4
PB		 1939 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1940 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1941 if (unlikely(Rc(ctx->opcode) != 0))
1942 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1943}
79aceca5
FB		 1944/* srawi & srawi. */
1945GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1946{
26d67362
AJ		 1947 int sh = SH(ctx->opcode);
1948 if (sh != 0) {
1949 int l1, l2;
fea0c503 1950 TCGv t0;
26d67362
AJ		 1951 l1 = gen_new_label();
1952 l2 = gen_new_label();
a7812ae4 1953 t0 = tcg_temp_local_new();
fea0c503
AJ		 1954 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1955 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1956 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1957 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1958 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1959 tcg_gen_br(l2);
1960 gen_set_label(l1);
269f3e95 1961 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1962 gen_set_label(l2);
fea0c503
AJ		 1963 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1964 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1965 tcg_temp_free(t0);
26d67362
AJ		 1966 } else {
1967 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1968 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1969 }
76a66253 1970 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1972}
1973/* srw & srw. */
26d67362
AJ		 1974GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1975{
fea0c503 1976 TCGv t0, t1;
26d67362
AJ		 1977 int l1, l2;
1978 l1 = gen_new_label();
1979 l2 = gen_new_label();
d9bce9d9 1980
a7812ae4 1981 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1982 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1983 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1984 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1985 tcg_gen_br(l2);
1986 gen_set_label(l1);
a7812ae4 1987 t1 = tcg_temp_new();
fea0c503
AJ		 1988 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1989 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1990 tcg_temp_free(t1);
26d67362 1991 gen_set_label(l2);
fea0c503 1992 tcg_temp_free(t0);
26d67362
AJ		 1993 if (unlikely(Rc(ctx->opcode) != 0))
1994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1995}
d9bce9d9
JM		 1996#if defined(TARGET_PPC64)
1997/* sld & sld. */
26d67362
AJ		 1998GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1999{
fea0c503 2000 TCGv t0;
26d67362
AJ		 2001 int l1, l2;
2002 l1 = gen_new_label();
2003 l2 = gen_new_label();
2004
a7812ae4 2005 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2006 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2007 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2008 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2009 tcg_gen_br(l2);
2010 gen_set_label(l1);
fea0c503 2011 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2012 gen_set_label(l2);
fea0c503 2013 tcg_temp_free(t0);
26d67362
AJ		 2014 if (unlikely(Rc(ctx->opcode) != 0))
2015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2016}
d9bce9d9 2017/* srad & srad. */
26d67362
AJ		 2018GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2019{
a7812ae4
PB		 2020 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2021 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2022 if (unlikely(Rc(ctx->opcode) != 0))
2023 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2024}
d9bce9d9 2025/* sradi & sradi. */
b068d6a7 2026static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2027{
26d67362 2028 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2029 if (sh != 0) {
26d67362 2030 int l1, l2;
fea0c503 2031 TCGv t0;
26d67362
AJ		 2032 l1 = gen_new_label();
2033 l2 = gen_new_label();
a7812ae4 2034 t0 = tcg_temp_local_new();
26d67362 2035 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2036 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2037 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2038 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2039 tcg_gen_br(l2);
2040 gen_set_label(l1);
269f3e95 2041 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2042 gen_set_label(l2);
a9730017 2043 tcg_temp_free(t0);
26d67362
AJ		 2044 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2045 } else {
2046 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2047 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2048 }
d9bce9d9 2049 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2050 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2051}
c7697e1f 2052GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2053{
2054 gen_sradi(ctx, 0);
2055}
c7697e1f 2056GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2057{
2058 gen_sradi(ctx, 1);
2059}
2060/* srd & srd. */
26d67362
AJ		 2061GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2062{
fea0c503 2063 TCGv t0;
26d67362
AJ		 2064 int l1, l2;
2065 l1 = gen_new_label();
2066 l2 = gen_new_label();
2067
a7812ae4 2068 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2069 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2070 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2071 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2072 tcg_gen_br(l2);
2073 gen_set_label(l1);
fea0c503 2074 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2075 gen_set_label(l2);
fea0c503 2076 tcg_temp_free(t0);
26d67362
AJ		 2077 if (unlikely(Rc(ctx->opcode) != 0))
2078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2079}
d9bce9d9 2080#endif
79aceca5
FB		 2081
2082/*** Floating-Point arithmetic ***/
7c58044c 2083#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2084GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2085{ \
76a66253 2086 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2087 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2088 return; \
2089 } \
eb44b959
AJ		 2090 /* NIP cannot be restored if the memory exception comes from an helper */ \
2091 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2092 gen_reset_fpstatus(); \
af12906f
AJ		 2093 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2094 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2095 if (isfloat) { \
af12906f 2096 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2097 } \
af12906f
AJ		 2098 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2099 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2100}
2101
7c58044c
JM		 2102#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2103_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2104_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2105
7c58044c
JM		 2106#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2107GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2108{ \
76a66253 2109 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2110 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2111 return; \
2112 } \
eb44b959
AJ		 2113 /* NIP cannot be restored if the memory exception comes from an helper */ \
2114 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2115 gen_reset_fpstatus(); \
af12906f
AJ		 2116 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2117 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2118 if (isfloat) { \
af12906f 2119 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2120 } \
af12906f
AJ		 2121 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2122 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2123}
7c58044c
JM		 2124#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2125_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2126_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2127
7c58044c
JM		 2128#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2129GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2130{ \
76a66253 2131 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2132 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2133 return; \
2134 } \
eb44b959
AJ		 2135 /* NIP cannot be restored if the memory exception comes from an helper */ \
2136 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2137 gen_reset_fpstatus(); \
af12906f
AJ		 2138 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2139 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2140 if (isfloat) { \
af12906f 2141 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2142 } \
af12906f
AJ		 2143 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2144 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2145}
7c58044c
JM		 2146#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2147_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2148_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2149
7c58044c 2150#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2151GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2152{ \
76a66253 2153 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2154 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2155 return; \
2156 } \
eb44b959
AJ		 2157 /* NIP cannot be restored if the memory exception comes from an helper */ \
2158 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2159 gen_reset_fpstatus(); \
af12906f
AJ		 2160 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2161 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2162 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2163}
2164
7c58044c 2165#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2166GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2167{ \
76a66253 2168 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2169 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2170 return; \
2171 } \
eb44b959
AJ		 2172 /* NIP cannot be restored if the memory exception comes from an helper */ \
2173 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2174 gen_reset_fpstatus(); \
af12906f
AJ		 2175 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2176 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2177 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2178}
2179
9a64fbe4 2180/* fadd - fadds */
7c58044c 2181GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2182/* fdiv - fdivs */
7c58044c 2183GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2184/* fmul - fmuls */
7c58044c 2185GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2186
d7e4b87e 2187/* fre */
7c58044c 2188GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2189
a750fc0b 2190/* fres */
7c58044c 2191GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2192
a750fc0b 2193/* frsqrte */
7c58044c
JM		 2194GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2195
2196/* frsqrtes */
af12906f 2197GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2198{
af12906f 2199 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2200 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2201 return;
2202 }
eb44b959
AJ		 2203 /* NIP cannot be restored if the memory exception comes from an helper */
2204 gen_update_nip(ctx, ctx->nip - 4);
af12906f
AJ		 2205 gen_reset_fpstatus();
2206 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2207 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2208 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2209}
79aceca5 2210
a750fc0b 2211/* fsel */
7c58044c 2212_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2213/* fsub - fsubs */
7c58044c 2214GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2215/* Optional: */
2216/* fsqrt */
a750fc0b 2217GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2218{
76a66253 2219 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2220 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2221 return;
2222 }
eb44b959
AJ		 2223 /* NIP cannot be restored if the memory exception comes from an helper */
2224 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2225 gen_reset_fpstatus();
af12906f
AJ		 2226 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2227 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2228}
79aceca5 2229
a750fc0b 2230GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2231{
76a66253 2232 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2233 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2234 return;
2235 }
eb44b959
AJ		 2236 /* NIP cannot be restored if the memory exception comes from an helper */
2237 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2238 gen_reset_fpstatus();
af12906f
AJ		 2239 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2240 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2241 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2242}
2243
2244/*** Floating-Point multiply-and-add ***/
4ecc3190 2245/* fmadd - fmadds */
7c58044c 2246GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2247/* fmsub - fmsubs */
7c58044c 2248GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2249/* fnmadd - fnmadds */
7c58044c 2250GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2251/* fnmsub - fnmsubs */
7c58044c 2252GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2253
2254/*** Floating-Point round & convert ***/
2255/* fctiw */
7c58044c 2256GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2257/* fctiwz */
7c58044c 2258GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2259/* frsp */
7c58044c 2260GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2261#if defined(TARGET_PPC64)
2262/* fcfid */
7c58044c 2263GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2264/* fctid */
7c58044c 2265GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2266/* fctidz */
7c58044c 2267GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2268#endif
79aceca5 2269
d7e4b87e 2270/* frin */
7c58044c 2271GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2272/* friz */
7c58044c 2273GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2274/* frip */
7c58044c 2275GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2276/* frim */
7c58044c 2277GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2278
79aceca5
FB		 2279/*** Floating-Point compare ***/
2280/* fcmpo */
76a66253 2281GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2282{
330c483b 2283 TCGv_i32 crf;
76a66253 2284 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2285 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2286 return;
2287 }
eb44b959
AJ		 2288 /* NIP cannot be restored if the memory exception comes from an helper */
2289 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2290 gen_reset_fpstatus();
9a819377
AJ		 2291 crf = tcg_const_i32(crfD(ctx->opcode));
2292 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2293 tcg_temp_free_i32(crf);
af12906f 2294 gen_helper_float_check_status();
79aceca5
FB		 2295}
2296
2297/* fcmpu */
76a66253 2298GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2299{
330c483b 2300 TCGv_i32 crf;
76a66253 2301 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2302 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2303 return;
2304 }
eb44b959
AJ		 2305 /* NIP cannot be restored if the memory exception comes from an helper */
2306 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2307 gen_reset_fpstatus();
9a819377
AJ		 2308 crf = tcg_const_i32(crfD(ctx->opcode));
2309 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2310 tcg_temp_free_i32(crf);
af12906f 2311 gen_helper_float_check_status();
79aceca5
FB		 2312}
2313
9a64fbe4
FB		 2314/*** Floating-point move ***/
2315/* fabs */
7c58044c
JM		 2316/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2317GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2318
2319/* fmr - fmr. */
7c58044c 2320/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2321GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2322{
76a66253 2323 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2324 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2325 return;
2326 }
af12906f
AJ		 2327 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2328 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2329}
2330
2331/* fnabs */
7c58044c
JM		 2332/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2333GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2334/* fneg */
7c58044c
JM		 2335/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2336GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2337
79aceca5
FB		 2338/*** Floating-Point status & ctrl register ***/
2339/* mcrfs */
2340GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2341{
7c58044c
JM		 2342 int bfa;
2343
76a66253 2344 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2345 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2346 return;
2347 }
7c58044c 2348 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2349 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2350 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2351 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2352}
2353
2354/* mffs */
2355GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2356{
76a66253 2357 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2358 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2359 return;
2360 }
7c58044c 2361 gen_reset_fpstatus();
af12906f
AJ		 2362 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2363 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2364}
2365
2366/* mtfsb0 */
2367GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2368{
fb0eaffc 2369 uint8_t crb;
3b46e624 2370
76a66253 2371 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2372 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2373 return;
2374 }
6e35d524 2375 crb = 31 - crbD(ctx->opcode);
7c58044c 2376 gen_reset_fpstatus();
6e35d524 2377 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2378 TCGv_i32 t0;
2379 /* NIP cannot be restored if the memory exception comes from an helper */
2380 gen_update_nip(ctx, ctx->nip - 4);
2381 t0 = tcg_const_i32(crb);
6e35d524
AJ		 2382 gen_helper_fpscr_clrbit(t0);
2383 tcg_temp_free_i32(t0);
2384 }
7c58044c 2385 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2386 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2387 }
79aceca5
FB		 2388}
2389
2390/* mtfsb1 */
2391GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2392{
fb0eaffc 2393 uint8_t crb;
3b46e624 2394
76a66253 2395 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2396 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2397 return;
2398 }
6e35d524 2399 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2400 gen_reset_fpstatus();
2401 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2402 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2403 TCGv_i32 t0;
2404 /* NIP cannot be restored if the memory exception comes from an helper */
2405 gen_update_nip(ctx, ctx->nip - 4);
2406 t0 = tcg_const_i32(crb);
af12906f 2407 gen_helper_fpscr_setbit(t0);
0f2f39c2 2408 tcg_temp_free_i32(t0);
af12906f 2409 }
7c58044c 2410 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2411 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2412 }
2413 /* We can raise a differed exception */
af12906f 2414 gen_helper_float_check_status();
79aceca5
FB		 2415}
2416
2417/* mtfsf */
2418GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2419{
0f2f39c2 2420 TCGv_i32 t0;
af12906f 2421
76a66253 2422 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2423 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2424 return;
2425 }
eb44b959
AJ		 2426 /* NIP cannot be restored if the memory exception comes from an helper */
2427 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2428 gen_reset_fpstatus();
af12906f
AJ		 2429 t0 = tcg_const_i32(FM(ctx->opcode));
2430 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2431 tcg_temp_free_i32(t0);
7c58044c 2432 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2433 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2434 }
2435 /* We can raise a differed exception */
af12906f 2436 gen_helper_float_check_status();
79aceca5
FB		 2437}
2438
2439/* mtfsfi */
2440GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2441{
7c58044c 2442 int bf, sh;
0f2f39c2
AJ		 2443 TCGv_i64 t0;
2444 TCGv_i32 t1;
7c58044c 2445
76a66253 2446 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2447 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2448 return;
2449 }
7c58044c
JM		 2450 bf = crbD(ctx->opcode) >> 2;
2451 sh = 7 - bf;
eb44b959
AJ		 2452 /* NIP cannot be restored if the memory exception comes from an helper */
2453 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2454 gen_reset_fpstatus();
0f2f39c2 2455 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2456 t1 = tcg_const_i32(1 << sh);
2457 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2458 tcg_temp_free_i64(t0);
2459 tcg_temp_free_i32(t1);
7c58044c 2460 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2461 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2462 }
2463 /* We can raise a differed exception */
af12906f 2464 gen_helper_float_check_status();
79aceca5
FB		 2465}
2466
76a66253
JM		 2467/*** Addressing modes ***/
2468/* Register indirect with immediate index : EA = (rA|0) + SIMM */
76db3ba4 2469static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
76a66253
JM		 2470{
2471 target_long simm = SIMM(ctx->opcode);
2472
be147d08 2473 simm &= ~maskl;
76db3ba4
AJ		 2474 if (rA(ctx->opcode) == 0) {
2475#if defined(TARGET_PPC64)
2476 if (!ctx->sf_mode) {
2477 tcg_gen_movi_tl(EA, (uint32_t)simm);
2478 } else
2479#endif
e2be8d8d 2480 tcg_gen_movi_tl(EA, simm);
76db3ba4 2481 } else if (likely(simm != 0)) {
e2be8d8d 2482 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
76db3ba4
AJ		 2483#if defined(TARGET_PPC64)
2484 if (!ctx->sf_mode) {
2485 tcg_gen_ext32u_tl(EA, EA);
2486 }
2487#endif
2488 } else {
2489#if defined(TARGET_PPC64)
2490 if (!ctx->sf_mode) {
2491 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2492 } else
2493#endif
e2be8d8d 2494 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2495 }
76a66253
JM		 2496}
2497
76db3ba4 2498static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
76a66253 2499{
76db3ba4
AJ		 2500 if (rA(ctx->opcode) == 0) {
2501#if defined(TARGET_PPC64)
2502 if (!ctx->sf_mode) {
2503 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2504 } else
2505#endif
e2be8d8d 2506 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
76db3ba4 2507 } else {
e2be8d8d 2508 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76db3ba4
AJ		 2509#if defined(TARGET_PPC64)
2510 if (!ctx->sf_mode) {
2511 tcg_gen_ext32u_tl(EA, EA);
2512 }
2513#endif
2514 }
76a66253
JM		 2515}
2516
76db3ba4 2517static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
76a66253 2518{
76db3ba4 2519 if (rA(ctx->opcode) == 0) {
e2be8d8d 2520 tcg_gen_movi_tl(EA, 0);
76db3ba4
AJ		 2521 } else {
2522#if defined(TARGET_PPC64)
2523 if (!ctx->sf_mode) {
2524 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2525 } else
2526#endif
2527 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2528 }
2529}
2530
2531static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2532{
2533 tcg_gen_addi_tl(ret, arg1, val);
2534#if defined(TARGET_PPC64)
2535 if (!ctx->sf_mode) {
2536 tcg_gen_ext32u_tl(ret, ret);
2537 }
2538#endif
76a66253
JM		 2539}
2540
cf360a32
AJ		 2541static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2542{
2543 int l1 = gen_new_label();
2544 TCGv t0 = tcg_temp_new();
2545 TCGv_i32 t1, t2;
2546 /* NIP cannot be restored if the memory exception comes from an helper */
2547 gen_update_nip(ctx, ctx->nip - 4);
2548 tcg_gen_andi_tl(t0, EA, mask);
2549 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2550 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2551 t2 = tcg_const_i32(0);
2552 gen_helper_raise_exception_err(t1, t2);
2553 tcg_temp_free_i32(t1);
2554 tcg_temp_free_i32(t2);
2555 gen_set_label(l1);
2556 tcg_temp_free(t0);
2557}
2558
7863667f 2559/*** Integer load ***/
76db3ba4
AJ		 2560static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2561{
2562 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2563}
2564
2565static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2566{
2567 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2568}
2569
2570static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2571{
2572 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2573 if (unlikely(ctx->le_mode)) {
b61f2753 2574#if defined(TARGET_PPC64)
76db3ba4
AJ		 2575 TCGv_i32 t0 = tcg_temp_new_i32();
2576 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2577 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2578 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2579 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2580#else
2581 tcg_gen_bswap16_i32(arg1, arg1);
2582#endif
2583 }
b61f2753
AJ		 2584}
2585
76db3ba4 2586static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2587{
76db3ba4
AJ		 2588 if (unlikely(ctx->le_mode)) {
2589#if defined(TARGET_PPC64)
a7812ae4 2590 TCGv_i32 t0;
76db3ba4 2591 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
a7812ae4 2592 t0 = tcg_temp_new_i32();
76db3ba4 2593 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2594 tcg_gen_bswap16_i32(t0, t0);
76db3ba4
AJ		 2595 tcg_gen_extu_i32_tl(arg1, t0);
2596 tcg_gen_ext16s_tl(arg1, arg1);
a7812ae4 2597 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2598#else
2599 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2600 tcg_gen_bswap16_i32(arg1, arg1);
2601 tcg_gen_ext16s_i32(arg1, arg1);
2602#endif
2603 } else {
2604 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2605 }
b61f2753
AJ		 2606}
2607
76db3ba4 2608static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2609{
76db3ba4
AJ		 2610 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2611 if (unlikely(ctx->le_mode)) {
2612#if defined(TARGET_PPC64)
2613 TCGv_i32 t0 = tcg_temp_new_i32();
2614 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2615 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2616 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2617 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2618#else
2619 tcg_gen_bswap_i32(arg1, arg1);
2620#endif
2621 }
b61f2753
AJ		 2622}
2623
76db3ba4
AJ		 2624#if defined(TARGET_PPC64)
2625static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2626{
a457e7ee 2627 if (unlikely(ctx->le_mode)) {
a7812ae4 2628 TCGv_i32 t0;
76db3ba4 2629 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
a7812ae4 2630 t0 = tcg_temp_new_i32();
76db3ba4 2631 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2632 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2633 tcg_gen_ext_i32_tl(arg1, t0);
a7812ae4 2634 tcg_temp_free_i32(t0);
b61f2753 2635 } else
76db3ba4 2636 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753 2637}
76db3ba4 2638#endif
b61f2753 2639
76db3ba4 2640static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2641{
76db3ba4
AJ		 2642 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2643 if (unlikely(ctx->le_mode)) {
2644 tcg_gen_bswap_i64(arg1, arg1);
2645 }
b61f2753
AJ		 2646}
2647
76db3ba4 2648static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2649{
76db3ba4 2650 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2651}
2652
76db3ba4 2653static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2654{
76db3ba4
AJ		 2655 if (unlikely(ctx->le_mode)) {
2656#if defined(TARGET_PPC64)
a7812ae4 2657 TCGv_i32 t0;
76db3ba4 2658 TCGv t1;
a7812ae4 2659 t0 = tcg_temp_new_i32();
76db3ba4 2660 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694
AJ		 2661 tcg_gen_ext16u_i32(t0, t0);
2662 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2663 t1 = tcg_temp_new();
ea363694 2664 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2665 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2666 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2667 tcg_temp_free(t1);
2668#else
2669 TCGv t0 = tcg_temp_new();
2670 tcg_gen_ext16u_tl(t0, arg1);
2671 tcg_gen_bswap16_i32(t0, t0);
2672 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2673 tcg_temp_free(t0);
2674#endif
2675 } else {
2676 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2677 }
b61f2753
AJ		 2678}
2679
76db3ba4 2680static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2681{
76db3ba4
AJ		 2682 if (unlikely(ctx->le_mode)) {
2683#if defined(TARGET_PPC64)
a7812ae4 2684 TCGv_i32 t0;
76db3ba4 2685 TCGv t1;
a7812ae4 2686 t0 = tcg_temp_new_i32();
76db3ba4 2687 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2688 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2689 t1 = tcg_temp_new();
ea363694 2690 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2691 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2692 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2693 tcg_temp_free(t1);
2694#else
2695 TCGv t0 = tcg_temp_new_i32();
2696 tcg_gen_bswap_i32(t0, arg1);
2697 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2698 tcg_temp_free(t0);
2699#endif
2700 } else {
2701 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2702 }
b61f2753
AJ		 2703}
2704
76db3ba4 2705static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2706{
76db3ba4 2707 if (unlikely(ctx->le_mode)) {
a7812ae4 2708 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4
AJ		 2709 tcg_gen_bswap_i64(t0, arg1);
2710 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2711 tcg_temp_free_i64(t0);
b61f2753 2712 } else
76db3ba4 2713 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2714}
2715
0c8aacd4
AJ		 2716#define GEN_LD(name, ldop, opc, type) \
2717GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2718{ \
76db3ba4
AJ		 2719 TCGv EA; \
2720 gen_set_access_type(ctx, ACCESS_INT); \
2721 EA = tcg_temp_new(); \
2722 gen_addr_imm_index(ctx, EA, 0); \
2723 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2724 tcg_temp_free(EA); \
79aceca5
FB		 2725}
2726
0c8aacd4
AJ		 2727#define GEN_LDU(name, ldop, opc, type) \
2728GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2729{ \
b61f2753 2730 TCGv EA; \
76a66253
JM		 2731 if (unlikely(rA(ctx->opcode) == 0 || \
2732 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2733 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2734 return; \
9a64fbe4 2735 } \
76db3ba4 2736 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2737 EA = tcg_temp_new(); \
9d53c753 2738 if (type == PPC_64B) \
76db3ba4 2739 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2740 else \
76db3ba4
AJ		 2741 gen_addr_imm_index(ctx, EA, 0); \
2742 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2744 tcg_temp_free(EA); \
79aceca5
FB		 2745}
2746
0c8aacd4
AJ		 2747#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2748GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2749{ \
b61f2753 2750 TCGv EA; \
76a66253
JM		 2751 if (unlikely(rA(ctx->opcode) == 0 || \
2752 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2753 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2754 return; \
9a64fbe4 2755 } \
76db3ba4 2756 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2757 EA = tcg_temp_new(); \
76db3ba4
AJ		 2758 gen_addr_reg_index(ctx, EA); \
2759 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2761 tcg_temp_free(EA); \
79aceca5
FB		 2762}
2763
0c8aacd4
AJ		 2764#define GEN_LDX(name, ldop, opc2, opc3, type) \
2765GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2766{ \
76db3ba4
AJ		 2767 TCGv EA; \
2768 gen_set_access_type(ctx, ACCESS_INT); \
2769 EA = tcg_temp_new(); \
2770 gen_addr_reg_index(ctx, EA); \
2771 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2772 tcg_temp_free(EA); \
79aceca5
FB		 2773}
2774
0c8aacd4
AJ		 2775#define GEN_LDS(name, ldop, op, type) \
2776GEN_LD(name, ldop, op | 0x20, type); \
2777GEN_LDU(name, ldop, op | 0x21, type); \
2778GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2779GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2780
2781/* lbz lbzu lbzux lbzx */
0c8aacd4 2782GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2783/* lha lhau lhaux lhax */
0c8aacd4 2784GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2785/* lhz lhzu lhzux lhzx */
0c8aacd4 2786GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2787/* lwz lwzu lwzux lwzx */
0c8aacd4 2788GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2789#if defined(TARGET_PPC64)
d9bce9d9 2790/* lwaux */
0c8aacd4 2791GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2792/* lwax */
0c8aacd4 2793GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2794/* ldux */
0c8aacd4 2795GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2796/* ldx */
0c8aacd4 2797GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2798GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2799{
b61f2753 2800 TCGv EA;
d9bce9d9
JM		 2801 if (Rc(ctx->opcode)) {
2802 if (unlikely(rA(ctx->opcode) == 0 ||
2803 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2804 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2805 return;
2806 }
2807 }
76db3ba4 2808 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2809 EA = tcg_temp_new();
76db3ba4 2810 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2811 if (ctx->opcode & 0x02) {
2812 /* lwa (lwau is undefined) */
76db3ba4 2813 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2814 } else {
2815 /* ld - ldu */
76db3ba4 2816 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2817 }
d9bce9d9 2818 if (Rc(ctx->opcode))
b61f2753
AJ		 2819 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2820 tcg_temp_free(EA);
d9bce9d9 2821}
be147d08
JM		 2822/* lq */
2823GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2824{
2825#if defined(CONFIG_USER_ONLY)
e06fcd75 2826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2827#else
2828 int ra, rd;
b61f2753 2829 TCGv EA;
be147d08
JM		 2830
2831 /* Restore CPU state */
76db3ba4 2832 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2834 return;
2835 }
2836 ra = rA(ctx->opcode);
2837 rd = rD(ctx->opcode);
2838 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2839 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2840 return;
2841 }
76db3ba4 2842 if (unlikely(ctx->le_mode)) {
be147d08 2843 /* Little-endian mode is not handled */
e06fcd75 2844 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2845 return;
2846 }
76db3ba4 2847 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2848 EA = tcg_temp_new();
76db3ba4
AJ		 2849 gen_addr_imm_index(ctx, EA, 0x0F);
2850 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2851 gen_addr_add(ctx, EA, EA, 8);
2852 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
b61f2753 2853 tcg_temp_free(EA);
be147d08
JM		 2854#endif
2855}
d9bce9d9 2856#endif
79aceca5
FB		 2857
2858/*** Integer store ***/
0c8aacd4
AJ		 2859#define GEN_ST(name, stop, opc, type) \
2860GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2861{ \
76db3ba4
AJ		 2862 TCGv EA; \
2863 gen_set_access_type(ctx, ACCESS_INT); \
2864 EA = tcg_temp_new(); \
2865 gen_addr_imm_index(ctx, EA, 0); \
2866 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2867 tcg_temp_free(EA); \
79aceca5
FB		 2868}
2869
0c8aacd4
AJ		 2870#define GEN_STU(name, stop, opc, type) \
2871GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2872{ \
b61f2753 2873 TCGv EA; \
76a66253 2874 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2875 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2876 return; \
9a64fbe4 2877 } \
76db3ba4 2878 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2879 EA = tcg_temp_new(); \
9d53c753 2880 if (type == PPC_64B) \
76db3ba4 2881 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2882 else \
76db3ba4
AJ		 2883 gen_addr_imm_index(ctx, EA, 0); \
2884 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2885 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2886 tcg_temp_free(EA); \
79aceca5
FB		 2887}
2888
0c8aacd4
AJ		 2889#define GEN_STUX(name, stop, opc2, opc3, type) \
2890GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2891{ \
b61f2753 2892 TCGv EA; \
76a66253 2893 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2894 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2895 return; \
9a64fbe4 2896 } \
76db3ba4 2897 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2898 EA = tcg_temp_new(); \
76db3ba4
AJ		 2899 gen_addr_reg_index(ctx, EA); \
2900 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2902 tcg_temp_free(EA); \
79aceca5
FB		 2903}
2904
0c8aacd4
AJ		 2905#define GEN_STX(name, stop, opc2, opc3, type) \
2906GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2907{ \
76db3ba4
AJ		 2908 TCGv EA; \
2909 gen_set_access_type(ctx, ACCESS_INT); \
2910 EA = tcg_temp_new(); \
2911 gen_addr_reg_index(ctx, EA); \
2912 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2913 tcg_temp_free(EA); \
79aceca5
FB		 2914}
2915
0c8aacd4
AJ		 2916#define GEN_STS(name, stop, op, type) \
2917GEN_ST(name, stop, op | 0x20, type); \
2918GEN_STU(name, stop, op | 0x21, type); \
2919GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2920GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2921
2922/* stb stbu stbux stbx */
0c8aacd4 2923GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2924/* sth sthu sthux sthx */
0c8aacd4 2925GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2926/* stw stwu stwux stwx */
0c8aacd4 2927GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2928#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2929GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2930GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2931GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2932{
be147d08 2933 int rs;
b61f2753 2934 TCGv EA;
be147d08
JM		 2935
2936 rs = rS(ctx->opcode);
2937 if ((ctx->opcode & 0x3) == 0x2) {
2938#if defined(CONFIG_USER_ONLY)
e06fcd75 2939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2940#else
2941 /* stq */
76db3ba4 2942 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2943 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2944 return;
2945 }
2946 if (unlikely(rs & 1)) {
e06fcd75 2947 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2948 return;
2949 }
76db3ba4 2950 if (unlikely(ctx->le_mode)) {
be147d08 2951 /* Little-endian mode is not handled */
e06fcd75 2952 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2953 return;
2954 }
76db3ba4 2955 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2956 EA = tcg_temp_new();
76db3ba4
AJ		 2957 gen_addr_imm_index(ctx, EA, 0x03);
2958 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2959 gen_addr_add(ctx, EA, EA, 8);
2960 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
b61f2753 2961 tcg_temp_free(EA);
be147d08
JM		 2962#endif
2963 } else {
2964 /* std / stdu */
2965 if (Rc(ctx->opcode)) {
2966 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2967 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2968 return;
2969 }
2970 }
76db3ba4 2971 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2972 EA = tcg_temp_new();
76db3ba4
AJ		 2973 gen_addr_imm_index(ctx, EA, 0x03);
2974 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 2975 if (Rc(ctx->opcode))
b61f2753
AJ		 2976 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2977 tcg_temp_free(EA);
d9bce9d9 2978 }
d9bce9d9
JM		 2979}
2980#endif
79aceca5
FB		 2981/*** Integer load and store with byte reverse ***/
2982/* lhbrx */
76db3ba4 2983static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2984{
76db3ba4
AJ		 2985 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2986 if (likely(!ctx->le_mode)) {
2987#if defined(TARGET_PPC64)
2988 TCGv_i32 t0 = tcg_temp_new_i32();
2989 tcg_gen_trunc_tl_i32(t0, arg1);
2990 tcg_gen_bswap16_i32(t0, t0);
2991 tcg_gen_extu_i32_tl(arg1, t0);
2992 tcg_temp_free_i32(t0);
2993#else
2994 tcg_gen_bswap16_i32(arg1, arg1);
2995#endif
2996 }
b61f2753 2997}
0c8aacd4 2998GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 2999
79aceca5 3000/* lwbrx */
76db3ba4 3001static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3002{
76db3ba4
AJ		 3003 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3004 if (likely(!ctx->le_mode)) {
3005#if defined(TARGET_PPC64)
3006 TCGv_i32 t0 = tcg_temp_new_i32();
3007 tcg_gen_trunc_tl_i32(t0, arg1);
3008 tcg_gen_bswap_i32(t0, t0);
3009 tcg_gen_extu_i32_tl(arg1, t0);
3010 tcg_temp_free_i32(t0);
3011#else
3012 tcg_gen_bswap_i32(arg1, arg1);
3013#endif
3014 }
b61f2753 3015}
0c8aacd4 3016GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3017
79aceca5 3018/* sthbrx */
76db3ba4 3019static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3020{
76db3ba4
AJ		 3021 if (likely(!ctx->le_mode)) {
3022#if defined(TARGET_PPC64)
3023 TCGv_i32 t0;
3024 TCGv t1;
3025 t0 = tcg_temp_new_i32();
3026 tcg_gen_trunc_tl_i32(t0, arg1);
3027 tcg_gen_ext16u_i32(t0, t0);
3028 tcg_gen_bswap16_i32(t0, t0);
3029 t1 = tcg_temp_new();
3030 tcg_gen_extu_i32_tl(t1, t0);
3031 tcg_temp_free_i32(t0);
3032 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3033 tcg_temp_free(t1);
3034#else
3035 TCGv t0 = tcg_temp_new();
3036 tcg_gen_ext16u_tl(t0, arg1);
3037 tcg_gen_bswap16_i32(t0, t0);
3038 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3039 tcg_temp_free(t0);
3040#endif
3041 } else {
3042 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3043 }
b61f2753 3044}
0c8aacd4 3045GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3046
79aceca5 3047/* stwbrx */
76db3ba4 3048static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3049{
76db3ba4
AJ		 3050 if (likely(!ctx->le_mode)) {
3051#if defined(TARGET_PPC64)
3052 TCGv_i32 t0;
3053 TCGv t1;
3054 t0 = tcg_temp_new_i32();
3055 tcg_gen_trunc_tl_i32(t0, arg1);
3056 tcg_gen_bswap_i32(t0, t0);
3057 t1 = tcg_temp_new();
3058 tcg_gen_extu_i32_tl(t1, t0);
3059 tcg_temp_free_i32(t0);
3060 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3061 tcg_temp_free(t1);
3062#else
3063 TCGv t0 = tcg_temp_new_i32();
3064 tcg_gen_bswap_i32(t0, arg1);
3065 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3066 tcg_temp_free(t0);
3067#endif
3068 } else {
3069 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3070 }
b61f2753 3071}
0c8aacd4 3072GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3073
3074/*** Integer load and store multiple ***/
3075/* lmw */
3076GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3077{
76db3ba4
AJ		 3078 TCGv t0;
3079 TCGv_i32 t1;
3080 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3081 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3082 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3083 t0 = tcg_temp_new();
3084 t1 = tcg_const_i32(rD(ctx->opcode));
3085 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3086 gen_helper_lmw(t0, t1);
3087 tcg_temp_free(t0);
3088 tcg_temp_free_i32(t1);
79aceca5
FB		 3089}
3090
3091/* stmw */
3092GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3093{
76db3ba4
AJ		 3094 TCGv t0;
3095 TCGv_i32 t1;
3096 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3097 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3098 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3099 t0 = tcg_temp_new();
3100 t1 = tcg_const_i32(rS(ctx->opcode));
3101 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3102 gen_helper_stmw(t0, t1);
3103 tcg_temp_free(t0);
3104 tcg_temp_free_i32(t1);
79aceca5
FB		 3105}
3106
3107/*** Integer load and store strings ***/
3108/* lswi */
3fc6c082 3109/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3110 * rA is in the range of registers to be loaded.
3111 * In an other hand, IBM says this is valid, but rA won't be loaded.
3112 * For now, I'll follow the spec...
3113 */
05332d70 3114GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3115{
dfbc799d
AJ		 3116 TCGv t0;
3117 TCGv_i32 t1, t2;
79aceca5
FB		 3118 int nb = NB(ctx->opcode);
3119 int start = rD(ctx->opcode);
9a64fbe4 3120 int ra = rA(ctx->opcode);
79aceca5
FB		 3121 int nr;
3122
3123 if (nb == 0)
3124 nb = 32;
3125 nr = nb / 4;
76a66253
JM		 3126 if (unlikely(((start + nr) > 32 &&
3127 start <= ra && (start + nr - 32) > ra) ||
3128 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3129 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3130 return;
297d8e62 3131 }
76db3ba4 3132 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3133 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3134 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3135 t0 = tcg_temp_new();
76db3ba4 3136 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3137 t1 = tcg_const_i32(nb);
3138 t2 = tcg_const_i32(start);
3139 gen_helper_lsw(t0, t1, t2);
3140 tcg_temp_free(t0);
3141 tcg_temp_free_i32(t1);
3142 tcg_temp_free_i32(t2);
79aceca5
FB		 3143}
3144
3145/* lswx */
05332d70 3146GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3147{
76db3ba4
AJ		 3148 TCGv t0;
3149 TCGv_i32 t1, t2, t3;
3150 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3151 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3152 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3153 t0 = tcg_temp_new();
3154 gen_addr_reg_index(ctx, t0);
3155 t1 = tcg_const_i32(rD(ctx->opcode));
3156 t2 = tcg_const_i32(rA(ctx->opcode));
3157 t3 = tcg_const_i32(rB(ctx->opcode));
dfbc799d
AJ		 3158 gen_helper_lswx(t0, t1, t2, t3);
3159 tcg_temp_free(t0);
3160 tcg_temp_free_i32(t1);
3161 tcg_temp_free_i32(t2);
3162 tcg_temp_free_i32(t3);
79aceca5
FB		 3163}
3164
3165/* stswi */
05332d70 3166GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3167{
76db3ba4
AJ		 3168 TCGv t0;
3169 TCGv_i32 t1, t2;
4b3686fa 3170 int nb = NB(ctx->opcode);
76db3ba4 3171 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3172 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3173 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3174 t0 = tcg_temp_new();
3175 gen_addr_register(ctx, t0);
4b3686fa
FB		 3176 if (nb == 0)
3177 nb = 32;
dfbc799d 3178 t1 = tcg_const_i32(nb);
76db3ba4 3179 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3180 gen_helper_stsw(t0, t1, t2);
3181 tcg_temp_free(t0);
3182 tcg_temp_free_i32(t1);
3183 tcg_temp_free_i32(t2);
79aceca5
FB		 3184}
3185
3186/* stswx */
05332d70 3187GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3188{
76db3ba4
AJ		 3189 TCGv t0;
3190 TCGv_i32 t1, t2;
3191 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3192 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3193 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3194 t0 = tcg_temp_new();
3195 gen_addr_reg_index(ctx, t0);
3196 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3197 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3198 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3199 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3200 gen_helper_stsw(t0, t1, t2);
3201 tcg_temp_free(t0);
3202 tcg_temp_free_i32(t1);
3203 tcg_temp_free_i32(t2);
79aceca5
FB		 3204}
3205
3206/*** Memory synchronisation ***/
3207/* eieio */
0db1b20e 3208GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3209{
79aceca5
FB		 3210}
3211
3212/* isync */
0db1b20e 3213GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3214{
e06fcd75 3215 gen_stop_exception(ctx);
79aceca5
FB		 3216}
3217
111bfab3 3218/* lwarx */
76a66253 3219GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3220{
76db3ba4
AJ		 3221 TCGv t0;
3222 gen_set_access_type(ctx, ACCESS_RES);
3223 t0 = tcg_temp_local_new();
3224 gen_addr_reg_index(ctx, t0);
cf360a32 3225 gen_check_align(ctx, t0, 0x03);
76db3ba4 3226 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3227 tcg_gen_mov_tl(cpu_reserve, t0);
3228 tcg_temp_free(t0);
79aceca5
FB		 3229}
3230
3231/* stwcx. */
c7697e1f 3232GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3233{
76db3ba4
AJ		 3234 int l1;
3235 TCGv t0;
3236 gen_set_access_type(ctx, ACCESS_RES);
3237 t0 = tcg_temp_local_new();
3238 gen_addr_reg_index(ctx, t0);
cf360a32 3239 gen_check_align(ctx, t0, 0x03);
cf360a32
AJ		 3240 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3241 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3242 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3243 l1 = gen_new_label();
cf360a32
AJ		 3244 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3245 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3246 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3247 gen_set_label(l1);
3248 tcg_gen_movi_tl(cpu_reserve, -1);
3249 tcg_temp_free(t0);
79aceca5
FB		 3250}
3251
426613db 3252#if defined(TARGET_PPC64)
426613db 3253/* ldarx */
a750fc0b 3254GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3255{
76db3ba4
AJ		 3256 TCGv t0;
3257 gen_set_access_type(ctx, ACCESS_RES);
3258 t0 = tcg_temp_local_new();
3259 gen_addr_reg_index(ctx, t0);
cf360a32 3260 gen_check_align(ctx, t0, 0x07);
76db3ba4 3261 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3262 tcg_gen_mov_tl(cpu_reserve, t0);
3263 tcg_temp_free(t0);
426613db
JM		 3264}
3265
3266/* stdcx. */
c7697e1f 3267GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3268{
76db3ba4
AJ		 3269 int l1;
3270 TCGv t0;
3271 gen_set_access_type(ctx, ACCESS_RES);
3272 t0 = tcg_temp_local_new();
3273 gen_addr_reg_index(ctx, t0);
cf360a32 3274 gen_check_align(ctx, t0, 0x07);
cf360a32
AJ		 3275 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3276 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3277 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3278 l1 = gen_new_label();
cf360a32
AJ		 3279 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3280 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3281 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3282 gen_set_label(l1);
3283 tcg_gen_movi_tl(cpu_reserve, -1);
3284 tcg_temp_free(t0);
426613db
JM		 3285}
3286#endif /* defined(TARGET_PPC64) */
3287
79aceca5 3288/* sync */
a902d886 3289GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3290{
79aceca5
FB		 3291}
3292
0db1b20e
JM		 3293/* wait */
3294GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3295{
931ff272
AJ		 3296 TCGv_i32 t0 = tcg_temp_new_i32();
3297 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3298 tcg_temp_free_i32(t0);
0db1b20e 3299 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3300 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3301}
3302
79aceca5 3303/*** Floating-point load ***/
a0d7d5a7
AJ		 3304#define GEN_LDF(name, ldop, opc, type) \
3305GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3306{ \
a0d7d5a7 3307 TCGv EA; \
76a66253 3308 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3309 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3310 return; \
3311 } \
76db3ba4 3312 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3313 EA = tcg_temp_new(); \
76db3ba4
AJ		 3314 gen_addr_imm_index(ctx, EA, 0); \
3315 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3316 tcg_temp_free(EA); \
79aceca5
FB		 3317}
3318
a0d7d5a7
AJ		 3319#define GEN_LDUF(name, ldop, opc, type) \
3320GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3321{ \
a0d7d5a7 3322 TCGv EA; \
76a66253 3323 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3324 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3325 return; \
3326 } \
76a66253 3327 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3328 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3329 return; \
9a64fbe4 3330 } \
76db3ba4 3331 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3332 EA = tcg_temp_new(); \
76db3ba4
AJ		 3333 gen_addr_imm_index(ctx, EA, 0); \
3334 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3335 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3336 tcg_temp_free(EA); \
79aceca5
FB		 3337}
3338
a0d7d5a7
AJ		 3339#define GEN_LDUXF(name, ldop, opc, type) \
3340GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3341{ \
a0d7d5a7 3342 TCGv EA; \
76a66253 3343 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3344 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3345 return; \
3346 } \
76a66253 3347 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3348 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3349 return; \
9a64fbe4 3350 } \
76db3ba4 3351 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3352 EA = tcg_temp_new(); \
76db3ba4
AJ		 3353 gen_addr_reg_index(ctx, EA); \
3354 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3355 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3356 tcg_temp_free(EA); \
79aceca5
FB		 3357}
3358
a0d7d5a7
AJ		 3359#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3360GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3361{ \
a0d7d5a7 3362 TCGv EA; \
76a66253 3363 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3364 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3365 return; \
3366 } \
76db3ba4 3367 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3368 EA = tcg_temp_new(); \
76db3ba4
AJ		 3369 gen_addr_reg_index(ctx, EA); \
3370 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3371 tcg_temp_free(EA); \
79aceca5
FB		 3372}
3373
a0d7d5a7
AJ		 3374#define GEN_LDFS(name, ldop, op, type) \
3375GEN_LDF(name, ldop, op | 0x20, type); \
3376GEN_LDUF(name, ldop, op | 0x21, type); \
3377GEN_LDUXF(name, ldop, op | 0x01, type); \
3378GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3379
76db3ba4 3380static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3381{
3382 TCGv t0 = tcg_temp_new();
3383 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3384 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3385 tcg_gen_trunc_tl_i32(t1, t0);
3386 tcg_temp_free(t0);
3387 gen_helper_float32_to_float64(arg1, t1);
3388 tcg_temp_free_i32(t1);
3389}
79aceca5 3390
a0d7d5a7
AJ		 3391 /* lfd lfdu lfdux lfdx */
3392GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3393 /* lfs lfsu lfsux lfsx */
3394GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3395
3396/*** Floating-point store ***/
a0d7d5a7
AJ		 3397#define GEN_STF(name, stop, opc, type) \
3398GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3399{ \
a0d7d5a7 3400 TCGv EA; \
76a66253 3401 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3402 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3403 return; \
3404 } \
76db3ba4 3405 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3406 EA = tcg_temp_new(); \
76db3ba4
AJ		 3407 gen_addr_imm_index(ctx, EA, 0); \
3408 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3409 tcg_temp_free(EA); \
79aceca5
FB		 3410}
3411
a0d7d5a7
AJ		 3412#define GEN_STUF(name, stop, opc, type) \
3413GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3414{ \
a0d7d5a7 3415 TCGv EA; \
76a66253 3416 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3417 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3418 return; \
3419 } \
76a66253 3420 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3421 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3422 return; \
9a64fbe4 3423 } \
76db3ba4 3424 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3425 EA = tcg_temp_new(); \
76db3ba4
AJ		 3426 gen_addr_imm_index(ctx, EA, 0); \
3427 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3428 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3429 tcg_temp_free(EA); \
79aceca5
FB		 3430}
3431
a0d7d5a7
AJ		 3432#define GEN_STUXF(name, stop, opc, type) \
3433GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3434{ \
a0d7d5a7 3435 TCGv EA; \
76a66253 3436 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3437 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3438 return; \
3439 } \
76a66253 3440 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3441 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3442 return; \
9a64fbe4 3443 } \
76db3ba4 3444 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3445 EA = tcg_temp_new(); \
76db3ba4
AJ		 3446 gen_addr_reg_index(ctx, EA); \
3447 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3448 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3449 tcg_temp_free(EA); \
79aceca5
FB		 3450}
3451
a0d7d5a7
AJ		 3452#define GEN_STXF(name, stop, opc2, opc3, type) \
3453GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3454{ \
a0d7d5a7 3455 TCGv EA; \
76a66253 3456 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3457 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3458 return; \
3459 } \
76db3ba4 3460 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3461 EA = tcg_temp_new(); \
76db3ba4
AJ		 3462 gen_addr_reg_index(ctx, EA); \
3463 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3464 tcg_temp_free(EA); \
79aceca5
FB		 3465}
3466
a0d7d5a7
AJ		 3467#define GEN_STFS(name, stop, op, type) \
3468GEN_STF(name, stop, op | 0x20, type); \
3469GEN_STUF(name, stop, op | 0x21, type); \
3470GEN_STUXF(name, stop, op | 0x01, type); \
3471GEN_STXF(name, stop, 0x17, op | 0x00, type)
3472
76db3ba4 3473static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3474{
3475 TCGv_i32 t0 = tcg_temp_new_i32();
3476 TCGv t1 = tcg_temp_new();
3477 gen_helper_float64_to_float32(t0, arg1);
3478 tcg_gen_extu_i32_tl(t1, t0);
3479 tcg_temp_free_i32(t0);
76db3ba4 3480 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3481 tcg_temp_free(t1);
3482}
79aceca5
FB		 3483
3484/* stfd stfdu stfdux stfdx */
a0d7d5a7 3485GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3486/* stfs stfsu stfsux stfsx */
a0d7d5a7 3487GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3488
3489/* Optional: */
76db3ba4 3490static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3491{
3492 TCGv t0 = tcg_temp_new();
3493 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3494 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3495 tcg_temp_free(t0);
3496}
79aceca5 3497/* stfiwx */
a0d7d5a7 3498GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3499
3500/*** Branch ***/
b068d6a7
JM		 3501static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3502 target_ulong dest)
c1942362
FB		 3503{
3504 TranslationBlock *tb;
3505 tb = ctx->tb;
a2ffb812
AJ		 3506#if defined(TARGET_PPC64)
3507 if (!ctx->sf_mode)
3508 dest = (uint32_t) dest;
3509#endif
57fec1fe 3510 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3511 likely(!ctx->singlestep_enabled)) {
57fec1fe 3512 tcg_gen_goto_tb(n);
a2ffb812 3513 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3514 tcg_gen_exit_tb((long)tb + n);
c1942362 3515 } else {
a2ffb812 3516 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3517 if (unlikely(ctx->singlestep_enabled)) {
3518 if ((ctx->singlestep_enabled &
bdc4e053 3519 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3520 ctx->exception == POWERPC_EXCP_BRANCH) {
3521 target_ulong tmp = ctx->nip;
3522 ctx->nip = dest;
e06fcd75 3523 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3524 ctx->nip = tmp;
3525 }
3526 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3527 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3528 }
3529 }
57fec1fe 3530 tcg_gen_exit_tb(0);
c1942362 3531 }
c53be334
FB		 3532}
3533
b068d6a7 3534static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3535{
3536#if defined(TARGET_PPC64)
a2ffb812
AJ		 3537 if (ctx->sf_mode == 0)
3538 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3539 else
3540#endif
a2ffb812 3541 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3542}
3543
79aceca5
FB		 3544/* b ba bl bla */
3545GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3546{
76a66253 3547 target_ulong li, target;
38a64f9d 3548
8cbcb4fa 3549 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3550 /* sign extend LI */
76a66253 3551#if defined(TARGET_PPC64)
d9bce9d9
JM		 3552 if (ctx->sf_mode)
3553 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3554 else
76a66253 3555#endif
d9bce9d9 3556 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3557 if (likely(AA(ctx->opcode) == 0))
046d6672 3558 target = ctx->nip + li - 4;
79aceca5 3559 else
9a64fbe4 3560 target = li;
e1833e1f
JM		 3561 if (LK(ctx->opcode))
3562 gen_setlr(ctx, ctx->nip);
c1942362 3563 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3564}
3565
e98a6e40
FB		 3566#define BCOND_IM 0
3567#define BCOND_LR 1
3568#define BCOND_CTR 2
3569
b068d6a7 3570static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3571{
d9bce9d9 3572 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3573 int l1 = gen_new_label();
3574 TCGv target;
e98a6e40 3575
8cbcb4fa 3576 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3577 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3578 target = tcg_temp_local_new();
a2ffb812
AJ		 3579 if (type == BCOND_CTR)
3580 tcg_gen_mov_tl(target, cpu_ctr);
3581 else
3582 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3583 }
e1833e1f
JM		 3584 if (LK(ctx->opcode))
3585 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3586 l1 = gen_new_label();
3587 if ((bo & 0x4) == 0) {
3588 /* Decrement and test CTR */
a7812ae4 3589 TCGv temp = tcg_temp_new();
a2ffb812 3590 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3591 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3592 return;
3593 }
3594 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3595#if defined(TARGET_PPC64)
a2ffb812
AJ		 3596 if (!ctx->sf_mode)
3597 tcg_gen_ext32u_tl(temp, cpu_ctr);
3598 else
d9bce9d9 3599#endif
a2ffb812
AJ		 3600 tcg_gen_mov_tl(temp, cpu_ctr);
3601 if (bo & 0x2) {
3602 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3603 } else {
3604 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3605 }
a7812ae4 3606 tcg_temp_free(temp);
a2ffb812
AJ		 3607 }
3608 if ((bo & 0x10) == 0) {
3609 /* Test CR */
3610 uint32_t bi = BI(ctx->opcode);
3611 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3612 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3613
d9bce9d9 3614 if (bo & 0x8) {
a2ffb812
AJ		 3615 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3616 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3617 } else {
a2ffb812
AJ		 3618 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3619 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3620 }
a7812ae4 3621 tcg_temp_free_i32(temp);
d9bce9d9 3622 }
e98a6e40 3623 if (type == BCOND_IM) {
a2ffb812
AJ		 3624 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3625 if (likely(AA(ctx->opcode) == 0)) {
3626 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3627 } else {
3628 gen_goto_tb(ctx, 0, li);
3629 }
c53be334 3630 gen_set_label(l1);
c1942362 3631 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3632 } else {
d9bce9d9 3633#if defined(TARGET_PPC64)
a2ffb812
AJ		 3634 if (!(ctx->sf_mode))
3635 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3636 else
3637#endif
3638 tcg_gen_andi_tl(cpu_nip, target, ~3);
3639 tcg_gen_exit_tb(0);
3640 gen_set_label(l1);
3641#if defined(TARGET_PPC64)
3642 if (!(ctx->sf_mode))
3643 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3644 else
3645#endif
a2ffb812 3646 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3647 tcg_gen_exit_tb(0);
08e46e54 3648 }
e98a6e40
FB		 3649}
3650
3651GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3652{
e98a6e40
FB		 3653 gen_bcond(ctx, BCOND_IM);
3654}
3655
3656GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3657{
e98a6e40
FB		 3658 gen_bcond(ctx, BCOND_CTR);
3659}
3660
3661GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3662{
e98a6e40
FB		 3663 gen_bcond(ctx, BCOND_LR);
3664}
79aceca5
FB		 3665
3666/*** Condition register logical ***/
e1571908
AJ		 3667#define GEN_CRLOGIC(name, tcg_op, opc) \
3668GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3669{ \
fc0d441e
JM		 3670 uint8_t bitmask; \
3671 int sh; \
a7812ae4 3672 TCGv_i32 t0, t1; \
fc0d441e 3673 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3674 t0 = tcg_temp_new_i32(); \
fc0d441e 3675 if (sh > 0) \
fea0c503 3676 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3677 else if (sh < 0) \
fea0c503 3678 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3679 else \
fea0c503 3680 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3681 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3682 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3683 if (sh > 0) \
fea0c503 3684 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3685 else if (sh < 0) \
fea0c503 3686 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3687 else \
fea0c503
AJ		 3688 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3689 tcg_op(t0, t0, t1); \
fc0d441e 3690 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3691 tcg_gen_andi_i32(t0, t0, bitmask); \
3692 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3693 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3694 tcg_temp_free_i32(t0); \
3695 tcg_temp_free_i32(t1); \
79aceca5
FB		 3696}
3697
3698/* crand */
e1571908 3699GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3700/* crandc */
e1571908 3701GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3702/* creqv */
e1571908 3703GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3704/* crnand */
e1571908 3705GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3706/* crnor */
e1571908 3707GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3708/* cror */
e1571908 3709GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3710/* crorc */
e1571908 3711GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3712/* crxor */
e1571908 3713GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3714/* mcrf */
3715GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3716{
47e4661c 3717 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3718}
3719
3720/*** System linkage ***/
76db3ba4 3721/* rfi (mem_idx only) */
76a66253 3722GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3723{
9a64fbe4 3724#if defined(CONFIG_USER_ONLY)
e06fcd75 3725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 3726#else
3727 /* Restore CPU state */
76db3ba4 3728 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 3730 return;
9a64fbe4 3731 }
d72a19f7 3732 gen_helper_rfi();
e06fcd75 3733 gen_sync_exception(ctx);
9a64fbe4 3734#endif
79aceca5
FB		 3735}
3736
426613db 3737#if defined(TARGET_PPC64)
a750fc0b 3738GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3739{
3740#if defined(CONFIG_USER_ONLY)
e06fcd75 3741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3742#else
3743 /* Restore CPU state */
76db3ba4 3744 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3746 return;
3747 }
d72a19f7 3748 gen_helper_rfid();
e06fcd75 3749 gen_sync_exception(ctx);
426613db
JM		 3750#endif
3751}
426613db 3752
5b8105fa 3753GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3754{
3755#if defined(CONFIG_USER_ONLY)
e06fcd75 3756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3757#else
3758 /* Restore CPU state */
76db3ba4 3759 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 3760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3761 return;
3762 }
d72a19f7 3763 gen_helper_hrfid();
e06fcd75 3764 gen_sync_exception(ctx);
be147d08
JM		 3765#endif
3766}
3767#endif
3768
79aceca5 3769/* sc */
417bf010
JM		 3770#if defined(CONFIG_USER_ONLY)
3771#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3772#else
3773#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3774#endif
e1833e1f 3775GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3776{
e1833e1f
JM		 3777 uint32_t lev;
3778
3779 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3780 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3781}
3782
3783/*** Trap ***/
3784/* tw */
76a66253 3785GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3786{
cab3bee2 3787 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3788 /* Update the nip since this might generate a trap exception */
d9bce9d9 3789 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3790 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3791 tcg_temp_free_i32(t0);
79aceca5
FB		 3792}
3793
3794/* twi */
3795GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3796{
cab3bee2
AJ		 3797 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3798 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3799 /* Update the nip since this might generate a trap exception */
3800 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3801 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3802 tcg_temp_free(t0);
3803 tcg_temp_free_i32(t1);
79aceca5
FB		 3804}
3805
d9bce9d9
JM		 3806#if defined(TARGET_PPC64)
3807/* td */
3808GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3809{
cab3bee2 3810 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3811 /* Update the nip since this might generate a trap exception */
3812 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3813 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3814 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3815}
3816
3817/* tdi */
3818GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3819{
cab3bee2
AJ		 3820 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3821 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3822 /* Update the nip since this might generate a trap exception */
3823 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3824 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3825 tcg_temp_free(t0);
3826 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3827}
3828#endif
3829
79aceca5 3830/*** Processor control ***/
79aceca5
FB		 3831/* mcrxr */
3832GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3833{
3d7b417e
AJ		 3834 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3835 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3836 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3837}
3838
3839/* mfcr */
76a66253 3840GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3841{
76a66253 3842 uint32_t crm, crn;
3b46e624 3843
76a66253
JM		 3844 if (likely(ctx->opcode & 0x00100000)) {
3845 crm = CRM(ctx->opcode);
3846 if (likely((crm ^ (crm - 1)) == 0)) {
3847 crn = ffs(crm);
e1571908 3848 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3849 }
d9bce9d9 3850 } else {
a7812ae4 3851 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3852 }
79aceca5
FB		 3853}
3854
3855/* mfmsr */
3856GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3857{
9a64fbe4 3858#if defined(CONFIG_USER_ONLY)
e06fcd75 3859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3860#else
76db3ba4 3861 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3863 return;
9a64fbe4 3864 }
6527f6ea 3865 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3866#endif
79aceca5
FB		 3867}
3868
a11b8151 3869#if 1
6f2d8978 3870#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3871#else
3872static void spr_noaccess (void *opaque, int sprn)
3873{
3874 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3875 printf("ERROR: try to access SPR %d !\n", sprn);
3876}
3877#define SPR_NOACCESS (&spr_noaccess)
3878#endif
3879
79aceca5 3880/* mfspr */
b068d6a7 3881static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3882{
45d827d2 3883 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3884 uint32_t sprn = SPR(ctx->opcode);
3885
3fc6c082 3886#if !defined(CONFIG_USER_ONLY)
76db3ba4 3887 if (ctx->mem_idx == 2)
be147d08 3888 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 3889 else if (ctx->mem_idx)
3fc6c082
FB		 3890 read_cb = ctx->spr_cb[sprn].oea_read;
3891 else
9a64fbe4 3892#endif
3fc6c082 3893 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3894 if (likely(read_cb != NULL)) {
3895 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3896 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3897 } else {
3898 /* Privilege exception */
9fceefa7
JM		 3899 /* This is a hack to avoid warnings when running Linux:
3900 * this OS breaks the PowerPC virtualisation model,
3901 * allowing userland application to read the PVR
3902 */
3903 if (sprn != SPR_PVR) {
93fcfe39 3904 qemu_log("Trying to read privileged spr %d %03x at "
077fc206 3905 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3906 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3907 sprn, sprn, ctx->nip);
f24e5695 3908 }
e06fcd75 3909 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3910 }
3fc6c082
FB		 3911 } else {
3912 /* Not defined */
93fcfe39 3913 qemu_log("Trying to read invalid spr %d %03x at "
077fc206 3914 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3915 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3916 sprn, sprn, ctx->nip);
e06fcd75 3917 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3918 }
79aceca5
FB		 3919}
3920
3fc6c082 3921GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3922{
3fc6c082 3923 gen_op_mfspr(ctx);
76a66253 3924}
3fc6c082
FB		 3925
3926/* mftb */
a750fc0b 3927GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3928{
3929 gen_op_mfspr(ctx);
79aceca5
FB		 3930}
3931
3932/* mtcrf */
8dd4983c 3933GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3934{
76a66253 3935 uint32_t crm, crn;
3b46e624 3936
76a66253
JM		 3937 crm = CRM(ctx->opcode);
3938 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3939 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3940 crn = ffs(crm);
a7812ae4
PB		 3941 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3942 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3943 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3944 tcg_temp_free_i32(temp);
76a66253 3945 } else {
a7812ae4
PB		 3946 TCGv_i32 temp = tcg_const_i32(crm);
3947 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3948 tcg_temp_free_i32(temp);
76a66253 3949 }
79aceca5
FB		 3950}
3951
3952/* mtmsr */
426613db 3953#if defined(TARGET_PPC64)
be147d08 3954GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3955{
3956#if defined(CONFIG_USER_ONLY)
e06fcd75 3957 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 3958#else
76db3ba4 3959 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3960 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 3961 return;
3962 }
be147d08
JM		 3963 if (ctx->opcode & 0x00010000) {
3964 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3965 TCGv t0 = tcg_temp_new();
3966 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3967 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3968 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3969 tcg_temp_free(t0);
be147d08 3970 } else {
056b05f8
JM		 3971 /* XXX: we need to update nip before the store
3972 * if we enter power saving mode, we will exit the loop
3973 * directly from ppc_store_msr
3974 */
be147d08 3975 gen_update_nip(ctx, ctx->nip);
6527f6ea 3976 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3977 /* Must stop the translation as machine state (may have) changed */
3978 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3979 gen_stop_exception(ctx);
be147d08 3980 }
426613db
JM		 3981#endif
3982}
3983#endif
3984
79aceca5
FB		 3985GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3986{
9a64fbe4 3987#if defined(CONFIG_USER_ONLY)
e06fcd75 3988 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3989#else
76db3ba4 3990 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3991 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3992 return;
9a64fbe4 3993 }
be147d08
JM		 3994 if (ctx->opcode & 0x00010000) {
3995 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3996 TCGv t0 = tcg_temp_new();
3997 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3998 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3999 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4000 tcg_temp_free(t0);
be147d08 4001 } else {
056b05f8
JM		 4002 /* XXX: we need to update nip before the store
4003 * if we enter power saving mode, we will exit the loop
4004 * directly from ppc_store_msr
4005 */
be147d08 4006 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4007#if defined(TARGET_PPC64)
6527f6ea
AJ		 4008 if (!ctx->sf_mode) {
4009 TCGv t0 = tcg_temp_new();
4010 TCGv t1 = tcg_temp_new();
4011 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4012 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4013 tcg_gen_or_tl(t0, t0, t1);
4014 tcg_temp_free(t1);
4015 gen_helper_store_msr(t0);
4016 tcg_temp_free(t0);
4017 } else
d9bce9d9 4018#endif
6527f6ea 4019 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 4020 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4021 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4022 gen_stop_exception(ctx);
be147d08 4023 }
9a64fbe4 4024#endif
79aceca5
FB		 4025}
4026
4027/* mtspr */
4028GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4029{
45d827d2 4030 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4031 uint32_t sprn = SPR(ctx->opcode);
4032
3fc6c082 4033#if !defined(CONFIG_USER_ONLY)
76db3ba4 4034 if (ctx->mem_idx == 2)
be147d08 4035 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 4036 else if (ctx->mem_idx)
3fc6c082
FB		 4037 write_cb = ctx->spr_cb[sprn].oea_write;
4038 else
9a64fbe4 4039#endif
3fc6c082 4040 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4041 if (likely(write_cb != NULL)) {
4042 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4043 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4044 } else {
4045 /* Privilege exception */
93fcfe39 4046 qemu_log("Trying to write privileged spr %d %03x at "
077fc206 4047 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 4048 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4049 sprn, sprn, ctx->nip);
e06fcd75 4050 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4051 }
3fc6c082
FB		 4052 } else {
4053 /* Not defined */
93fcfe39 4054 qemu_log("Trying to write invalid spr %d %03x at "
077fc206 4055 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 4056 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4057 sprn, sprn, ctx->nip);
e06fcd75 4058 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4059 }
79aceca5
FB		 4060}
4061
4062/*** Cache management ***/
79aceca5 4063/* dcbf */
0db1b20e 4064GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4065{
dac454af 4066 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4067 TCGv t0;
4068 gen_set_access_type(ctx, ACCESS_CACHE);
4069 t0 = tcg_temp_new();
4070 gen_addr_reg_index(ctx, t0);
4071 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4072 tcg_temp_free(t0);
79aceca5
FB		 4073}
4074
4075/* dcbi (Supervisor only) */
9a64fbe4 4076GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4077{
a541f297 4078#if defined(CONFIG_USER_ONLY)
e06fcd75 4079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4080#else
b61f2753 4081 TCGv EA, val;
76db3ba4 4082 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4083 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4084 return;
9a64fbe4 4085 }
a7812ae4 4086 EA = tcg_temp_new();
76db3ba4
AJ		 4087 gen_set_access_type(ctx, ACCESS_CACHE);
4088 gen_addr_reg_index(ctx, EA);
a7812ae4 4089 val = tcg_temp_new();
76a66253 4090 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4091 gen_qemu_ld8u(ctx, val, EA);
4092 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4093 tcg_temp_free(val);
4094 tcg_temp_free(EA);
a541f297 4095#endif
79aceca5
FB		 4096}
4097
4098/* dcdst */
9a64fbe4 4099GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4100{
76a66253 4101 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4102 TCGv t0;
4103 gen_set_access_type(ctx, ACCESS_CACHE);
4104 t0 = tcg_temp_new();
4105 gen_addr_reg_index(ctx, t0);
4106 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4107 tcg_temp_free(t0);
79aceca5
FB		 4108}
4109
4110/* dcbt */
0db1b20e 4111GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4112{
0db1b20e 4113 /* interpreted as no-op */
76a66253
JM		 4114 /* XXX: specification say this is treated as a load by the MMU
4115 * but does not generate any exception
4116 */
79aceca5
FB		 4117}
4118
4119/* dcbtst */
0db1b20e 4120GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4121{
0db1b20e 4122 /* interpreted as no-op */
76a66253
JM		 4123 /* XXX: specification say this is treated as a load by the MMU
4124 * but does not generate any exception
4125 */
79aceca5
FB		 4126}
4127
4128/* dcbz */
d63001d1 4129GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4130{
76db3ba4
AJ		 4131 TCGv t0;
4132 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4133 /* NIP cannot be restored if the memory exception comes from an helper */
4134 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4135 t0 = tcg_temp_new();
4136 gen_addr_reg_index(ctx, t0);
799a8c8d
AJ		 4137 gen_helper_dcbz(t0);
4138 tcg_temp_free(t0);
d63001d1
JM		 4139}
4140
c7697e1f 4141GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4142{
76db3ba4
AJ		 4143 TCGv t0;
4144 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4145 /* NIP cannot be restored if the memory exception comes from an helper */
4146 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4147 t0 = tcg_temp_new();
4148 gen_addr_reg_index(ctx, t0);
d63001d1 4149 if (ctx->opcode & 0x00200000)
799a8c8d 4150 gen_helper_dcbz(t0);
d63001d1 4151 else
799a8c8d
AJ		 4152 gen_helper_dcbz_970(t0);
4153 tcg_temp_free(t0);
79aceca5
FB		 4154}
4155
ae1c1a3d
AJ		 4156/* dst / dstt */
4157GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4158{
4159 if (rA(ctx->opcode) == 0) {
4160 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4161 } else {
4162 /* interpreted as no-op */
4163 }
4164}
4165
4166/* dstst /dststt */
4167GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4168{
4169 if (rA(ctx->opcode) == 0) {
4170 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4171 } else {
4172 /* interpreted as no-op */
4173 }
4174
4175}
4176
4177/* dss / dssall */
4178GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4179{
4180 /* interpreted as no-op */
4181}
4182
79aceca5 4183/* icbi */
1b413d55 4184GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4185{
76db3ba4
AJ		 4186 TCGv t0;
4187 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4188 /* NIP cannot be restored if the memory exception comes from an helper */
4189 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4190 t0 = tcg_temp_new();
4191 gen_addr_reg_index(ctx, t0);
37d269df
AJ		 4192 gen_helper_icbi(t0);
4193 tcg_temp_free(t0);
79aceca5
FB		 4194}
4195
4196/* Optional: */
4197/* dcba */
a750fc0b 4198GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4199{
0db1b20e
JM		 4200 /* interpreted as no-op */
4201 /* XXX: specification say this is treated as a store by the MMU
4202 * but does not generate any exception
4203 */
79aceca5
FB		 4204}
4205
4206/*** Segment register manipulation ***/
4207/* Supervisor only: */
4208/* mfsr */
4209GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4210{
9a64fbe4 4211#if defined(CONFIG_USER_ONLY)
e06fcd75 4212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4213#else
74d37793 4214 TCGv t0;
76db3ba4 4215 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4217 return;
9a64fbe4 4218 }
74d37793
AJ		 4219 t0 = tcg_const_tl(SR(ctx->opcode));
4220 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4221 tcg_temp_free(t0);
9a64fbe4 4222#endif
79aceca5
FB		 4223}
4224
4225/* mfsrin */
9a64fbe4 4226GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4227{
9a64fbe4 4228#if defined(CONFIG_USER_ONLY)
e06fcd75 4229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4230#else
74d37793 4231 TCGv t0;
76db3ba4 4232 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4234 return;
9a64fbe4 4235 }
74d37793
AJ		 4236 t0 = tcg_temp_new();
4237 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4238 tcg_gen_andi_tl(t0, t0, 0xF);
4239 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4240 tcg_temp_free(t0);
9a64fbe4 4241#endif
79aceca5
FB		 4242}
4243
4244/* mtsr */
e63c59cb 4245GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4246{
9a64fbe4 4247#if defined(CONFIG_USER_ONLY)
e06fcd75 4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4249#else
74d37793 4250 TCGv t0;
76db3ba4 4251 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4253 return;
9a64fbe4 4254 }
74d37793
AJ		 4255 t0 = tcg_const_tl(SR(ctx->opcode));
4256 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4257 tcg_temp_free(t0);
9a64fbe4 4258#endif
79aceca5
FB		 4259}
4260
4261/* mtsrin */
9a64fbe4 4262GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4263{
9a64fbe4 4264#if defined(CONFIG_USER_ONLY)
e06fcd75 4265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4266#else
74d37793 4267 TCGv t0;
76db3ba4 4268 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4270 return;
9a64fbe4 4271 }
74d37793
AJ		 4272 t0 = tcg_temp_new();
4273 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4274 tcg_gen_andi_tl(t0, t0, 0xF);
4275 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4276 tcg_temp_free(t0);
9a64fbe4 4277#endif
79aceca5
FB		 4278}
4279
12de9a39
JM		 4280#if defined(TARGET_PPC64)
4281/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4282/* mfsr */
c7697e1f 4283GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4284{
4285#if defined(CONFIG_USER_ONLY)
e06fcd75 4286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4287#else
74d37793 4288 TCGv t0;
76db3ba4 4289 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4291 return;
4292 }
74d37793
AJ		 4293 t0 = tcg_const_tl(SR(ctx->opcode));
4294 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4295 tcg_temp_free(t0);
12de9a39
JM		 4296#endif
4297}
4298
4299/* mfsrin */
c7697e1f
JM		 4300GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4301 PPC_SEGMENT_64B)
12de9a39
JM		 4302{
4303#if defined(CONFIG_USER_ONLY)
e06fcd75 4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4305#else
74d37793 4306 TCGv t0;
76db3ba4 4307 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4309 return;
4310 }
74d37793
AJ		 4311 t0 = tcg_temp_new();
4312 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4313 tcg_gen_andi_tl(t0, t0, 0xF);
4314 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4315 tcg_temp_free(t0);
12de9a39
JM		 4316#endif
4317}
4318
4319/* mtsr */
c7697e1f 4320GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4321{
4322#if defined(CONFIG_USER_ONLY)
e06fcd75 4323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4324#else
74d37793 4325 TCGv t0;
76db3ba4 4326 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4327 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4328 return;
4329 }
74d37793
AJ		 4330 t0 = tcg_const_tl(SR(ctx->opcode));
4331 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4332 tcg_temp_free(t0);
12de9a39
JM		 4333#endif
4334}
4335
4336/* mtsrin */
c7697e1f
JM		 4337GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4338 PPC_SEGMENT_64B)
12de9a39
JM		 4339{
4340#if defined(CONFIG_USER_ONLY)
e06fcd75 4341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4342#else
74d37793 4343 TCGv t0;
76db3ba4 4344 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4346 return;
4347 }
74d37793
AJ		 4348 t0 = tcg_temp_new();
4349 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4350 tcg_gen_andi_tl(t0, t0, 0xF);
4351 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4352 tcg_temp_free(t0);
12de9a39
JM		 4353#endif
4354}
4355#endif /* defined(TARGET_PPC64) */
4356
79aceca5 4357/*** Lookaside buffer management ***/
76db3ba4 4358/* Optional & mem_idx only: */
79aceca5 4359/* tlbia */
3fc6c082 4360GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4361{
9a64fbe4 4362#if defined(CONFIG_USER_ONLY)
e06fcd75 4363 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4364#else
76db3ba4 4365 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4366 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4367 return;
9a64fbe4 4368 }
74d37793 4369 gen_helper_tlbia();
9a64fbe4 4370#endif
79aceca5
FB		 4371}
4372
4373/* tlbie */
76a66253 4374GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4375{
9a64fbe4 4376#if defined(CONFIG_USER_ONLY)
e06fcd75 4377 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4378#else
76db3ba4 4379 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4381 return;
9a64fbe4 4382 }
d9bce9d9 4383#if defined(TARGET_PPC64)
74d37793
AJ		 4384 if (!ctx->sf_mode) {
4385 TCGv t0 = tcg_temp_new();
4386 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4387 gen_helper_tlbie(t0);
4388 tcg_temp_free(t0);
4389 } else
d9bce9d9 4390#endif
74d37793 4391 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4392#endif
79aceca5
FB		 4393}
4394
4395/* tlbsync */
76a66253 4396GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4397{
9a64fbe4 4398#if defined(CONFIG_USER_ONLY)
e06fcd75 4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4400#else
76db3ba4 4401 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4403 return;
9a64fbe4
FB		 4404 }
4405 /* This has no effect: it should ensure that all previous
4406 * tlbie have completed
4407 */
e06fcd75 4408 gen_stop_exception(ctx);
9a64fbe4 4409#endif
79aceca5
FB		 4410}
4411
426613db
JM		 4412#if defined(TARGET_PPC64)
4413/* slbia */
4414GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4415{
4416#if defined(CONFIG_USER_ONLY)
e06fcd75 4417 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4418#else
76db3ba4 4419 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4421 return;
4422 }
74d37793 4423 gen_helper_slbia();
426613db
JM		 4424#endif
4425}
4426
4427/* slbie */
4428GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4429{
4430#if defined(CONFIG_USER_ONLY)
e06fcd75 4431 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4432#else
76db3ba4 4433 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4434 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4435 return;
4436 }
74d37793 4437 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4438#endif
4439}
4440#endif
4441
79aceca5
FB		 4442/*** External control ***/
4443/* Optional: */
111bfab3 4444/* eciwx */
79aceca5
FB		 4445GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4446{
76db3ba4 4447 TCGv t0;
fa407c03 4448 /* Should check EAR[E] ! */
76db3ba4
AJ		 4449 gen_set_access_type(ctx, ACCESS_EXT);
4450 t0 = tcg_temp_new();
4451 gen_addr_reg_index(ctx, t0);
fa407c03 4452 gen_check_align(ctx, t0, 0x03);
76db3ba4 4453 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4454 tcg_temp_free(t0);
76a66253
JM		 4455}
4456
4457/* ecowx */
4458GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4459{
76db3ba4 4460 TCGv t0;
fa407c03 4461 /* Should check EAR[E] ! */
76db3ba4
AJ		 4462 gen_set_access_type(ctx, ACCESS_EXT);
4463 t0 = tcg_temp_new();
4464 gen_addr_reg_index(ctx, t0);
fa407c03 4465 gen_check_align(ctx, t0, 0x03);
76db3ba4 4466 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4467 tcg_temp_free(t0);
76a66253
JM		 4468}
4469
4470/* PowerPC 601 specific instructions */
4471/* abs - abs. */
4472GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4473{
22e0e173
AJ		 4474 int l1 = gen_new_label();
4475 int l2 = gen_new_label();
4476 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4477 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4478 tcg_gen_br(l2);
4479 gen_set_label(l1);
4480 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4481 gen_set_label(l2);
76a66253 4482 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4483 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4484}
4485
4486/* abso - abso. */
4487GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4488{
22e0e173
AJ		 4489 int l1 = gen_new_label();
4490 int l2 = gen_new_label();
4491 int l3 = gen_new_label();
4492 /* Start with XER OV disabled, the most likely case */
4493 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4494 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4495 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4496 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4497 tcg_gen_br(l2);
4498 gen_set_label(l1);
4499 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4500 tcg_gen_br(l3);
4501 gen_set_label(l2);
4502 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4503 gen_set_label(l3);
76a66253 4504 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4505 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4506}
4507
4508/* clcs */
a750fc0b 4509GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4510{
22e0e173
AJ		 4511 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4512 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4513 tcg_temp_free_i32(t0);
c7697e1f 4514 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4515}
4516
4517/* div - div. */
4518GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4519{
22e0e173 4520 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4521 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4522 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4523}
4524
4525/* divo - divo. */
4526GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4527{
22e0e173 4528 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4529 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4530 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4531}
4532
4533/* divs - divs. */
4534GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4535{
22e0e173 4536 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4537 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4538 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4539}
4540
4541/* divso - divso. */
4542GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4543{
22e0e173 4544 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4545 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4546 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4547}
4548
4549/* doz - doz. */
4550GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4551{
22e0e173
AJ		 4552 int l1 = gen_new_label();
4553 int l2 = gen_new_label();
4554 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4555 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4556 tcg_gen_br(l2);
4557 gen_set_label(l1);
4558 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4559 gen_set_label(l2);
76a66253 4560 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4561 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4562}
4563
4564/* dozo - dozo. */
4565GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4566{
22e0e173
AJ		 4567 int l1 = gen_new_label();
4568 int l2 = gen_new_label();
4569 TCGv t0 = tcg_temp_new();
4570 TCGv t1 = tcg_temp_new();
4571 TCGv t2 = tcg_temp_new();
4572 /* Start with XER OV disabled, the most likely case */
4573 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4574 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4575 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4576 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4577 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4578 tcg_gen_andc_tl(t1, t1, t2);
4579 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4580 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4581 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4582 tcg_gen_br(l2);
4583 gen_set_label(l1);
4584 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4585 gen_set_label(l2);
4586 tcg_temp_free(t0);
4587 tcg_temp_free(t1);
4588 tcg_temp_free(t2);
76a66253 4589 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4590 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4591}
4592
4593/* dozi */
4594GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4595{
22e0e173
AJ		 4596 target_long simm = SIMM(ctx->opcode);
4597 int l1 = gen_new_label();
4598 int l2 = gen_new_label();
4599 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4600 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4601 tcg_gen_br(l2);
4602 gen_set_label(l1);
4603 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4604 gen_set_label(l2);
4605 if (unlikely(Rc(ctx->opcode) != 0))
4606 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4607}
4608
76a66253
JM		 4609/* lscbx - lscbx. */
4610GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4611{
bdb4b689
AJ		 4612 TCGv t0 = tcg_temp_new();
4613 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4614 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4615 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4616
76db3ba4 4617 gen_addr_reg_index(ctx, t0);
76a66253 4618 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4619 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4620 gen_helper_lscbx(t0, t0, t1, t2, t3);
4621 tcg_temp_free_i32(t1);
4622 tcg_temp_free_i32(t2);
4623 tcg_temp_free_i32(t3);
3d7b417e 4624 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4625 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4626 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4627 gen_set_Rc0(ctx, t0);
4628 tcg_temp_free(t0);
76a66253
JM		 4629}
4630
4631/* maskg - maskg. */
4632GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4633{
22e0e173
AJ		 4634 int l1 = gen_new_label();
4635 TCGv t0 = tcg_temp_new();
4636 TCGv t1 = tcg_temp_new();
4637 TCGv t2 = tcg_temp_new();
4638 TCGv t3 = tcg_temp_new();
4639 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4640 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4641 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4642 tcg_gen_addi_tl(t2, t0, 1);
4643 tcg_gen_shr_tl(t2, t3, t2);
4644 tcg_gen_shr_tl(t3, t3, t1);
4645 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4646 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4647 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4648 gen_set_label(l1);
4649 tcg_temp_free(t0);
4650 tcg_temp_free(t1);
4651 tcg_temp_free(t2);
4652 tcg_temp_free(t3);
76a66253 4653 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4654 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4655}
4656
4657/* maskir - maskir. */
4658GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4659{
22e0e173
AJ		 4660 TCGv t0 = tcg_temp_new();
4661 TCGv t1 = tcg_temp_new();
4662 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4663 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4664 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4665 tcg_temp_free(t0);
4666 tcg_temp_free(t1);
76a66253 4667 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4668 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4669}
4670
4671/* mul - mul. */
4672GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4673{
22e0e173
AJ		 4674 TCGv_i64 t0 = tcg_temp_new_i64();
4675 TCGv_i64 t1 = tcg_temp_new_i64();
4676 TCGv t2 = tcg_temp_new();
4677 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4678 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4679 tcg_gen_mul_i64(t0, t0, t1);
4680 tcg_gen_trunc_i64_tl(t2, t0);
4681 gen_store_spr(SPR_MQ, t2);
4682 tcg_gen_shri_i64(t1, t0, 32);
4683 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4684 tcg_temp_free_i64(t0);
4685 tcg_temp_free_i64(t1);
4686 tcg_temp_free(t2);
76a66253 4687 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4688 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4689}
4690
4691/* mulo - mulo. */
4692GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4693{
22e0e173
AJ		 4694 int l1 = gen_new_label();
4695 TCGv_i64 t0 = tcg_temp_new_i64();
4696 TCGv_i64 t1 = tcg_temp_new_i64();
4697 TCGv t2 = tcg_temp_new();
4698 /* Start with XER OV disabled, the most likely case */
4699 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4700 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4701 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4702 tcg_gen_mul_i64(t0, t0, t1);
4703 tcg_gen_trunc_i64_tl(t2, t0);
4704 gen_store_spr(SPR_MQ, t2);
4705 tcg_gen_shri_i64(t1, t0, 32);
4706 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4707 tcg_gen_ext32s_i64(t1, t0);
4708 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4709 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4710 gen_set_label(l1);
4711 tcg_temp_free_i64(t0);
4712 tcg_temp_free_i64(t1);
4713 tcg_temp_free(t2);
76a66253 4714 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4715 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4716}
4717
4718/* nabs - nabs. */
4719GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4720{
22e0e173
AJ		 4721 int l1 = gen_new_label();
4722 int l2 = gen_new_label();
4723 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4724 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4725 tcg_gen_br(l2);
4726 gen_set_label(l1);
4727 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4728 gen_set_label(l2);
76a66253 4729 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4730 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4731}
4732
4733/* nabso - nabso. */
4734GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4735{
22e0e173
AJ		 4736 int l1 = gen_new_label();
4737 int l2 = gen_new_label();
4738 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4740 tcg_gen_br(l2);
4741 gen_set_label(l1);
4742 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4743 gen_set_label(l2);
4744 /* nabs never overflows */
4745 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4746 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4747 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4748}
4749
4750/* rlmi - rlmi. */
4751GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4752{
7487953d
AJ		 4753 uint32_t mb = MB(ctx->opcode);
4754 uint32_t me = ME(ctx->opcode);
4755 TCGv t0 = tcg_temp_new();
4756 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4757 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4758 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4760 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4761 tcg_temp_free(t0);
76a66253 4762 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4763 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4764}
4765
4766/* rrib - rrib. */
4767GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4768{
7487953d
AJ		 4769 TCGv t0 = tcg_temp_new();
4770 TCGv t1 = tcg_temp_new();
4771 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4772 tcg_gen_movi_tl(t1, 0x80000000);
4773 tcg_gen_shr_tl(t1, t1, t0);
4774 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4775 tcg_gen_and_tl(t0, t0, t1);
4776 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4777 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4778 tcg_temp_free(t0);
4779 tcg_temp_free(t1);
76a66253 4780 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4781 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4782}
4783
4784/* sle - sle. */
4785GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4786{
7487953d
AJ		 4787 TCGv t0 = tcg_temp_new();
4788 TCGv t1 = tcg_temp_new();
4789 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4790 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4791 tcg_gen_subfi_tl(t1, 32, t1);
4792 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4793 tcg_gen_or_tl(t1, t0, t1);
4794 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4795 gen_store_spr(SPR_MQ, t1);
4796 tcg_temp_free(t0);
4797 tcg_temp_free(t1);
76a66253 4798 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4799 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4800}
4801
4802/* sleq - sleq. */
4803GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4804{
7487953d
AJ		 4805 TCGv t0 = tcg_temp_new();
4806 TCGv t1 = tcg_temp_new();
4807 TCGv t2 = tcg_temp_new();
4808 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4809 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4810 tcg_gen_shl_tl(t2, t2, t0);
4811 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4812 gen_load_spr(t1, SPR_MQ);
4813 gen_store_spr(SPR_MQ, t0);
4814 tcg_gen_and_tl(t0, t0, t2);
4815 tcg_gen_andc_tl(t1, t1, t2);
4816 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4817 tcg_temp_free(t0);
4818 tcg_temp_free(t1);
4819 tcg_temp_free(t2);
76a66253 4820 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4822}
4823
4824/* sliq - sliq. */
4825GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4826{
7487953d
AJ		 4827 int sh = SH(ctx->opcode);
4828 TCGv t0 = tcg_temp_new();
4829 TCGv t1 = tcg_temp_new();
4830 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4831 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4832 tcg_gen_or_tl(t1, t0, t1);
4833 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4834 gen_store_spr(SPR_MQ, t1);
4835 tcg_temp_free(t0);
4836 tcg_temp_free(t1);
76a66253 4837 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4838 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4839}
4840
4841/* slliq - slliq. */
4842GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4843{
7487953d
AJ		 4844 int sh = SH(ctx->opcode);
4845 TCGv t0 = tcg_temp_new();
4846 TCGv t1 = tcg_temp_new();
4847 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4848 gen_load_spr(t1, SPR_MQ);
4849 gen_store_spr(SPR_MQ, t0);
4850 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4851 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4852 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4853 tcg_temp_free(t0);
4854 tcg_temp_free(t1);
76a66253 4855 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4857}
4858
4859/* sllq - sllq. */
4860GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4861{
7487953d
AJ		 4862 int l1 = gen_new_label();
4863 int l2 = gen_new_label();
4864 TCGv t0 = tcg_temp_local_new();
4865 TCGv t1 = tcg_temp_local_new();
4866 TCGv t2 = tcg_temp_local_new();
4867 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4868 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4869 tcg_gen_shl_tl(t1, t1, t2);
4870 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4871 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4872 gen_load_spr(t0, SPR_MQ);
4873 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4874 tcg_gen_br(l2);
4875 gen_set_label(l1);
4876 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4877 gen_load_spr(t2, SPR_MQ);
4878 tcg_gen_andc_tl(t1, t2, t1);
4879 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4880 gen_set_label(l2);
4881 tcg_temp_free(t0);
4882 tcg_temp_free(t1);
4883 tcg_temp_free(t2);
76a66253 4884 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4885 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4886}
4887
4888/* slq - slq. */
4889GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4890{
7487953d
AJ		 4891 int l1 = gen_new_label();
4892 TCGv t0 = tcg_temp_new();
4893 TCGv t1 = tcg_temp_new();
4894 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4895 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4896 tcg_gen_subfi_tl(t1, 32, t1);
4897 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4898 tcg_gen_or_tl(t1, t0, t1);
4899 gen_store_spr(SPR_MQ, t1);
4900 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4902 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4903 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4904 gen_set_label(l1);
4905 tcg_temp_free(t0);
4906 tcg_temp_free(t1);
76a66253 4907 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4909}
4910
d9bce9d9 4911/* sraiq - sraiq. */
76a66253
JM		 4912GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4913{
7487953d
AJ		 4914 int sh = SH(ctx->opcode);
4915 int l1 = gen_new_label();
4916 TCGv t0 = tcg_temp_new();
4917 TCGv t1 = tcg_temp_new();
4918 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4919 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4920 tcg_gen_or_tl(t0, t0, t1);
4921 gen_store_spr(SPR_MQ, t0);
4922 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4923 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4924 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4925 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4926 gen_set_label(l1);
4927 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4928 tcg_temp_free(t0);
4929 tcg_temp_free(t1);
76a66253 4930 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4931 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4932}
4933
4934/* sraq - sraq. */
4935GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4936{
7487953d
AJ		 4937 int l1 = gen_new_label();
4938 int l2 = gen_new_label();
4939 TCGv t0 = tcg_temp_new();
4940 TCGv t1 = tcg_temp_local_new();
4941 TCGv t2 = tcg_temp_local_new();
4942 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4943 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4944 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4945 tcg_gen_subfi_tl(t2, 32, t2);
4946 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4947 tcg_gen_or_tl(t0, t0, t2);
4948 gen_store_spr(SPR_MQ, t0);
4949 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4950 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4951 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4952 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4953 gen_set_label(l1);
4954 tcg_temp_free(t0);
4955 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4956 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4957 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4958 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4959 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4960 gen_set_label(l2);
4961 tcg_temp_free(t1);
4962 tcg_temp_free(t2);
76a66253 4963 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4964 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4965}
4966
4967/* sre - sre. */
4968GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4969{
7487953d
AJ		 4970 TCGv t0 = tcg_temp_new();
4971 TCGv t1 = tcg_temp_new();
4972 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4973 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4974 tcg_gen_subfi_tl(t1, 32, t1);
4975 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4976 tcg_gen_or_tl(t1, t0, t1);
4977 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4978 gen_store_spr(SPR_MQ, t1);
4979 tcg_temp_free(t0);
4980 tcg_temp_free(t1);
76a66253 4981 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4982 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4983}
4984
4985/* srea - srea. */
4986GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4987{
7487953d
AJ		 4988 TCGv t0 = tcg_temp_new();
4989 TCGv t1 = tcg_temp_new();
4990 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4991 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4992 gen_store_spr(SPR_MQ, t0);
4993 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4994 tcg_temp_free(t0);
4995 tcg_temp_free(t1);
76a66253 4996 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4997 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4998}
4999
5000/* sreq */
5001GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
5002{
7487953d
AJ		 5003 TCGv t0 = tcg_temp_new();
5004 TCGv t1 = tcg_temp_new();
5005 TCGv t2 = tcg_temp_new();
5006 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5007 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5008 tcg_gen_shr_tl(t1, t1, t0);
5009 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5010 gen_load_spr(t2, SPR_MQ);
5011 gen_store_spr(SPR_MQ, t0);
5012 tcg_gen_and_tl(t0, t0, t1);
5013 tcg_gen_andc_tl(t2, t2, t1);
5014 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5015 tcg_temp_free(t0);
5016 tcg_temp_free(t1);
5017 tcg_temp_free(t2);
76a66253 5018 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5020}
5021
5022/* sriq */
5023GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5024{
7487953d
AJ		 5025 int sh = SH(ctx->opcode);
5026 TCGv t0 = tcg_temp_new();
5027 TCGv t1 = tcg_temp_new();
5028 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5029 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5030 tcg_gen_or_tl(t1, t0, t1);
5031 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5032 gen_store_spr(SPR_MQ, t1);
5033 tcg_temp_free(t0);
5034 tcg_temp_free(t1);
76a66253 5035 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5036 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5037}
5038
5039/* srliq */
5040GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5041{
7487953d
AJ		 5042 int sh = SH(ctx->opcode);
5043 TCGv t0 = tcg_temp_new();
5044 TCGv t1 = tcg_temp_new();
5045 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5046 gen_load_spr(t1, SPR_MQ);
5047 gen_store_spr(SPR_MQ, t0);
5048 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5049 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5050 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5051 tcg_temp_free(t0);
5052 tcg_temp_free(t1);
76a66253 5053 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5054 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5055}
5056
5057/* srlq */
5058GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5059{
7487953d
AJ		 5060 int l1 = gen_new_label();
5061 int l2 = gen_new_label();
5062 TCGv t0 = tcg_temp_local_new();
5063 TCGv t1 = tcg_temp_local_new();
5064 TCGv t2 = tcg_temp_local_new();
5065 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5066 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5067 tcg_gen_shr_tl(t2, t1, t2);
5068 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5069 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5070 gen_load_spr(t0, SPR_MQ);
5071 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5072 tcg_gen_br(l2);
5073 gen_set_label(l1);
5074 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5075 tcg_gen_and_tl(t0, t0, t2);
5076 gen_load_spr(t1, SPR_MQ);
5077 tcg_gen_andc_tl(t1, t1, t2);
5078 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5079 gen_set_label(l2);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 tcg_temp_free(t2);
76a66253 5083 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5084 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5085}
5086
5087/* srq */
5088GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5089{
7487953d
AJ		 5090 int l1 = gen_new_label();
5091 TCGv t0 = tcg_temp_new();
5092 TCGv t1 = tcg_temp_new();
5093 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5094 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5095 tcg_gen_subfi_tl(t1, 32, t1);
5096 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5097 tcg_gen_or_tl(t1, t0, t1);
5098 gen_store_spr(SPR_MQ, t1);
5099 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5100 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5101 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5102 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5103 gen_set_label(l1);
5104 tcg_temp_free(t0);
5105 tcg_temp_free(t1);
76a66253 5106 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5107 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5108}
5109
5110/* PowerPC 602 specific instructions */
5111/* dsa */
5112GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5113{
5114 /* XXX: TODO */
e06fcd75 5115 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5116}
5117
5118/* esa */
5119GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5120{
5121 /* XXX: TODO */
e06fcd75 5122 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5123}
5124
5125/* mfrom */
5126GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5127{
5128#if defined(CONFIG_USER_ONLY)
e06fcd75 5129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5130#else
76db3ba4 5131 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5132 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5133 return;
5134 }
cf02a65c 5135 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5136#endif
5137}
5138
5139/* 602 - 603 - G2 TLB management */
5140/* tlbld */
c7697e1f 5141GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5142{
5143#if defined(CONFIG_USER_ONLY)
e06fcd75 5144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5145#else
76db3ba4 5146 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5148 return;
5149 }
74d37793 5150 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5151#endif
5152}
5153
5154/* tlbli */
c7697e1f 5155GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5156{
5157#if defined(CONFIG_USER_ONLY)
e06fcd75 5158 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5159#else
76db3ba4 5160 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5162 return;
5163 }
74d37793 5164 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5165#endif
5166}
5167
7dbe11ac
JM		 5168/* 74xx TLB management */
5169/* tlbld */
c7697e1f 5170GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5171{
5172#if defined(CONFIG_USER_ONLY)
e06fcd75 5173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5174#else
76db3ba4 5175 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5176 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5177 return;
5178 }
74d37793 5179 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5180#endif
5181}
5182
5183/* tlbli */
c7697e1f 5184GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5185{
5186#if defined(CONFIG_USER_ONLY)
e06fcd75 5187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5188#else
76db3ba4 5189 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5191 return;
5192 }
74d37793 5193 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5194#endif
5195}
5196
76a66253
JM		 5197/* POWER instructions not in PowerPC 601 */
5198/* clf */
5199GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5200{
5201 /* Cache line flush: implemented as no-op */
5202}
5203
5204/* cli */
5205GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5206{
7f75ffd3 5207 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5208#if defined(CONFIG_USER_ONLY)
e06fcd75 5209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5210#else
76db3ba4 5211 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5213 return;
5214 }
5215#endif
5216}
5217
5218/* dclst */
5219GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5220{
5221 /* Data cache line store: treated as no-op */
5222}
5223
5224GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5225{
5226#if defined(CONFIG_USER_ONLY)
e06fcd75 5227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5228#else
74d37793
AJ		 5229 int ra = rA(ctx->opcode);
5230 int rd = rD(ctx->opcode);
5231 TCGv t0;
76db3ba4 5232 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5234 return;
5235 }
74d37793 5236 t0 = tcg_temp_new();
76db3ba4 5237 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5238 tcg_gen_shri_tl(t0, t0, 28);
5239 tcg_gen_andi_tl(t0, t0, 0xF);
5240 gen_helper_load_sr(cpu_gpr[rd], t0);
5241 tcg_temp_free(t0);
76a66253 5242 if (ra != 0 && ra != rd)
74d37793 5243 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5244#endif
5245}
5246
5247GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5248{
5249#if defined(CONFIG_USER_ONLY)
e06fcd75 5250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5251#else
22e0e173 5252 TCGv t0;
76db3ba4 5253 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5255 return;
5256 }
22e0e173 5257 t0 = tcg_temp_new();
76db3ba4 5258 gen_addr_reg_index(ctx, t0);
22e0e173
AJ		 5259 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5260 tcg_temp_free(t0);
76a66253
JM		 5261#endif
5262}
5263
5264GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5265{
5266#if defined(CONFIG_USER_ONLY)
e06fcd75 5267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5268#else
76db3ba4 5269 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5271 return;
5272 }
d72a19f7 5273 gen_helper_rfsvc();
e06fcd75 5274 gen_sync_exception(ctx);
76a66253
JM		 5275#endif
5276}
5277
5278/* svc is not implemented for now */
5279
5280/* POWER2 specific instructions */
5281/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5282
5283/* lfq */
5284GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5285{
01a4afeb 5286 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5287 TCGv t0;
5288 gen_set_access_type(ctx, ACCESS_FLOAT);
5289 t0 = tcg_temp_new();
5290 gen_addr_imm_index(ctx, t0, 0);
5291 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5292 gen_addr_add(ctx, t0, t0, 8);
5293 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5294 tcg_temp_free(t0);
76a66253
JM		 5295}
5296
5297/* lfqu */
5298GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5299{
5300 int ra = rA(ctx->opcode);
01a4afeb 5301 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5302 TCGv t0, t1;
5303 gen_set_access_type(ctx, ACCESS_FLOAT);
5304 t0 = tcg_temp_new();
5305 t1 = tcg_temp_new();
5306 gen_addr_imm_index(ctx, t0, 0);
5307 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5308 gen_addr_add(ctx, t1, t0, 8);
5309 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5310 if (ra != 0)
01a4afeb
AJ		 5311 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5312 tcg_temp_free(t0);
5313 tcg_temp_free(t1);
76a66253
JM		 5314}
5315
5316/* lfqux */
5317GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5318{
5319 int ra = rA(ctx->opcode);
01a4afeb 5320 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5321 gen_set_access_type(ctx, ACCESS_FLOAT);
5322 TCGv t0, t1;
5323 t0 = tcg_temp_new();
5324 gen_addr_reg_index(ctx, t0);
5325 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5326 t1 = tcg_temp_new();
5327 gen_addr_add(ctx, t1, t0, 8);
5328 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5329 tcg_temp_free(t1);
76a66253 5330 if (ra != 0)
01a4afeb
AJ		 5331 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5332 tcg_temp_free(t0);
76a66253
JM		 5333}
5334
5335/* lfqx */
5336GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5337{
01a4afeb 5338 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5339 TCGv t0;
5340 gen_set_access_type(ctx, ACCESS_FLOAT);
5341 t0 = tcg_temp_new();
5342 gen_addr_reg_index(ctx, t0);
5343 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5344 gen_addr_add(ctx, t0, t0, 8);
5345 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5346 tcg_temp_free(t0);
76a66253
JM		 5347}
5348
5349/* stfq */
5350GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5351{
01a4afeb 5352 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5353 TCGv t0;
5354 gen_set_access_type(ctx, ACCESS_FLOAT);
5355 t0 = tcg_temp_new();
5356 gen_addr_imm_index(ctx, t0, 0);
5357 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5358 gen_addr_add(ctx, t0, t0, 8);
5359 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5360 tcg_temp_free(t0);
76a66253
JM		 5361}
5362
5363/* stfqu */
5364GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5365{
5366 int ra = rA(ctx->opcode);
01a4afeb 5367 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5368 TCGv t0, t1;
5369 gen_set_access_type(ctx, ACCESS_FLOAT);
5370 t0 = tcg_temp_new();
5371 gen_addr_imm_index(ctx, t0, 0);
5372 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5373 t1 = tcg_temp_new();
5374 gen_addr_add(ctx, t1, t0, 8);
5375 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5376 tcg_temp_free(t1);
76a66253 5377 if (ra != 0)
01a4afeb
AJ		 5378 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5379 tcg_temp_free(t0);
76a66253
JM		 5380}
5381
5382/* stfqux */
5383GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5384{
5385 int ra = rA(ctx->opcode);
01a4afeb 5386 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5387 TCGv t0, t1;
5388 gen_set_access_type(ctx, ACCESS_FLOAT);
5389 t0 = tcg_temp_new();
5390 gen_addr_reg_index(ctx, t0);
5391 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5392 t1 = tcg_temp_new();
5393 gen_addr_add(ctx, t1, t0, 8);
5394 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5395 tcg_temp_free(t1);
76a66253 5396 if (ra != 0)
01a4afeb
AJ		 5397 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5398 tcg_temp_free(t0);
76a66253
JM		 5399}
5400
5401/* stfqx */
5402GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5403{
01a4afeb 5404 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5405 TCGv t0;
5406 gen_set_access_type(ctx, ACCESS_FLOAT);
5407 t0 = tcg_temp_new();
5408 gen_addr_reg_index(ctx, t0);
5409 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5410 gen_addr_add(ctx, t0, t0, 8);
5411 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5412 tcg_temp_free(t0);
76a66253
JM		 5413}
5414
5415/* BookE specific instructions */
2662a059 5416/* XXX: not implemented on 440 ? */
05332d70 5417GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5418{
5419 /* XXX: TODO */
e06fcd75 5420 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5421}
5422
2662a059 5423/* XXX: not implemented on 440 ? */
05332d70 5424GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5425{
5426#if defined(CONFIG_USER_ONLY)
e06fcd75 5427 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5428#else
74d37793 5429 TCGv t0;
76db3ba4 5430 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5431 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5432 return;
5433 }
ec72e276 5434 t0 = tcg_temp_new();
76db3ba4 5435 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5436 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5437 tcg_temp_free(t0);
76a66253
JM		 5438#endif
5439}
5440
5441/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5442static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5443 int opc2, int opc3,
5444 int ra, int rb, int rt, int Rc)
76a66253 5445{
182608d4
AJ		 5446 TCGv t0, t1;
5447
a7812ae4
PB		 5448 t0 = tcg_temp_local_new();
5449 t1 = tcg_temp_local_new();
182608d4 5450
76a66253
JM		 5451 switch (opc3 & 0x0D) {
5452 case 0x05:
5453 /* macchw - macchw. - macchwo - macchwo. */
5454 /* macchws - macchws. - macchwso - macchwso. */
5455 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5456 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5457 /* mulchw - mulchw. */
182608d4
AJ		 5458 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5459 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5460 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5461 break;
5462 case 0x04:
5463 /* macchwu - macchwu. - macchwuo - macchwuo. */
5464 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5465 /* mulchwu - mulchwu. */
182608d4
AJ		 5466 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5467 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5468 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5469 break;
5470 case 0x01:
5471 /* machhw - machhw. - machhwo - machhwo. */
5472 /* machhws - machhws. - machhwso - machhwso. */
5473 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5474 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5475 /* mulhhw - mulhhw. */
182608d4
AJ		 5476 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5477 tcg_gen_ext16s_tl(t0, t0);
5478 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5479 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5480 break;
5481 case 0x00:
5482 /* machhwu - machhwu. - machhwuo - machhwuo. */
5483 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5484 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5485 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5486 tcg_gen_ext16u_tl(t0, t0);
5487 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5488 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5489 break;
5490 case 0x0D:
5491 /* maclhw - maclhw. - maclhwo - maclhwo. */
5492 /* maclhws - maclhws. - maclhwso - maclhwso. */
5493 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5494 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5495 /* mullhw - mullhw. */
182608d4
AJ		 5496 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5497 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5498 break;
5499 case 0x0C:
5500 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5501 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5502 /* mullhwu - mullhwu. */
182608d4
AJ		 5503 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5504 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5505 break;
5506 }
76a66253 5507 if (opc2 & 0x04) {
182608d4
AJ		 5508 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5509 tcg_gen_mul_tl(t1, t0, t1);
5510 if (opc2 & 0x02) {
5511 /* nmultiply-and-accumulate (0x0E) */
5512 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5513 } else {
5514 /* multiply-and-accumulate (0x0C) */
5515 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5516 }
5517
5518 if (opc3 & 0x12) {
5519 /* Check overflow and/or saturate */
5520 int l1 = gen_new_label();
5521
5522 if (opc3 & 0x10) {
5523 /* Start with XER OV disabled, the most likely case */
5524 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5525 }
5526 if (opc3 & 0x01) {
5527 /* Signed */
5528 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5529 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5530 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5531 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5532 if (opc3 & 0x02) {
182608d4
AJ		 5533 /* Saturate */
5534 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5535 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5536 }
5537 } else {
5538 /* Unsigned */
5539 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5540 if (opc3 & 0x02) {
182608d4
AJ		 5541 /* Saturate */
5542 tcg_gen_movi_tl(t0, UINT32_MAX);
5543 }
5544 }
5545 if (opc3 & 0x10) {
5546 /* Check overflow */
5547 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5548 }
5549 gen_set_label(l1);
5550 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5551 }
5552 } else {
5553 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5554 }
182608d4
AJ		 5555 tcg_temp_free(t0);
5556 tcg_temp_free(t1);
76a66253
JM		 5557 if (unlikely(Rc) != 0) {
5558 /* Update Rc0 */
182608d4 5559 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5560 }
5561}
5562
a750fc0b
JM		 5563#define GEN_MAC_HANDLER(name, opc2, opc3) \
5564GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5565{ \
5566 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5567 rD(ctx->opcode), Rc(ctx->opcode)); \
5568}
5569
5570/* macchw - macchw. */
a750fc0b 5571GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5572/* macchwo - macchwo. */
a750fc0b 5573GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5574/* macchws - macchws. */
a750fc0b 5575GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5576/* macchwso - macchwso. */
a750fc0b 5577GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5578/* macchwsu - macchwsu. */
a750fc0b 5579GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5580/* macchwsuo - macchwsuo. */
a750fc0b 5581GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5582/* macchwu - macchwu. */
a750fc0b 5583GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5584/* macchwuo - macchwuo. */
a750fc0b 5585GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5586/* machhw - machhw. */
a750fc0b 5587GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5588/* machhwo - machhwo. */
a750fc0b 5589GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5590/* machhws - machhws. */
a750fc0b 5591GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5592/* machhwso - machhwso. */
a750fc0b 5593GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5594/* machhwsu - machhwsu. */
a750fc0b 5595GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5596/* machhwsuo - machhwsuo. */
a750fc0b 5597GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5598/* machhwu - machhwu. */
a750fc0b 5599GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5600/* machhwuo - machhwuo. */
a750fc0b 5601GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5602/* maclhw - maclhw. */
a750fc0b 5603GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5604/* maclhwo - maclhwo. */
a750fc0b 5605GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5606/* maclhws - maclhws. */
a750fc0b 5607GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5608/* maclhwso - maclhwso. */
a750fc0b 5609GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5610/* maclhwu - maclhwu. */
a750fc0b 5611GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5612/* maclhwuo - maclhwuo. */
a750fc0b 5613GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5614/* maclhwsu - maclhwsu. */
a750fc0b 5615GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5616/* maclhwsuo - maclhwsuo. */
a750fc0b 5617GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5618/* nmacchw - nmacchw. */
a750fc0b 5619GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5620/* nmacchwo - nmacchwo. */
a750fc0b 5621GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5622/* nmacchws - nmacchws. */
a750fc0b 5623GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5624/* nmacchwso - nmacchwso. */
a750fc0b 5625GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5626/* nmachhw - nmachhw. */
a750fc0b 5627GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5628/* nmachhwo - nmachhwo. */
a750fc0b 5629GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5630/* nmachhws - nmachhws. */
a750fc0b 5631GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5632/* nmachhwso - nmachhwso. */
a750fc0b 5633GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5634/* nmaclhw - nmaclhw. */
a750fc0b 5635GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5636/* nmaclhwo - nmaclhwo. */
a750fc0b 5637GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5638/* nmaclhws - nmaclhws. */
a750fc0b 5639GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5640/* nmaclhwso - nmaclhwso. */
a750fc0b 5641GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5642
5643/* mulchw - mulchw. */
a750fc0b 5644GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5645/* mulchwu - mulchwu. */
a750fc0b 5646GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5647/* mulhhw - mulhhw. */
a750fc0b 5648GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5649/* mulhhwu - mulhhwu. */
a750fc0b 5650GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5651/* mullhw - mullhw. */
a750fc0b 5652GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5653/* mullhwu - mullhwu. */
a750fc0b 5654GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5655
5656/* mfdcr */
05332d70 5657GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5658{
5659#if defined(CONFIG_USER_ONLY)
e06fcd75 5660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5661#else
06dca6a7 5662 TCGv dcrn;
76db3ba4 5663 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5665 return;
5666 }
06dca6a7
AJ		 5667 /* NIP cannot be restored if the memory exception comes from an helper */
5668 gen_update_nip(ctx, ctx->nip - 4);
5669 dcrn = tcg_const_tl(SPR(ctx->opcode));
5670 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5671 tcg_temp_free(dcrn);
76a66253
JM		 5672#endif
5673}
5674
5675/* mtdcr */
05332d70 5676GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5677{
5678#if defined(CONFIG_USER_ONLY)
e06fcd75 5679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5680#else
06dca6a7 5681 TCGv dcrn;
76db3ba4 5682 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5684 return;
5685 }
06dca6a7
AJ		 5686 /* NIP cannot be restored if the memory exception comes from an helper */
5687 gen_update_nip(ctx, ctx->nip - 4);
5688 dcrn = tcg_const_tl(SPR(ctx->opcode));
5689 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5690 tcg_temp_free(dcrn);
a42bd6cc
JM		 5691#endif
5692}
5693
5694/* mfdcrx */
2662a059 5695/* XXX: not implemented on 440 ? */
05332d70 5696GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5697{
5698#if defined(CONFIG_USER_ONLY)
e06fcd75 5699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5700#else
76db3ba4 5701 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5702 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5703 return;
5704 }
06dca6a7
AJ		 5705 /* NIP cannot be restored if the memory exception comes from an helper */
5706 gen_update_nip(ctx, ctx->nip - 4);
5707 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5708 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5709#endif
5710}
5711
5712/* mtdcrx */
2662a059 5713/* XXX: not implemented on 440 ? */
05332d70 5714GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5715{
5716#if defined(CONFIG_USER_ONLY)
e06fcd75 5717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5718#else
76db3ba4 5719 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5721 return;
5722 }
06dca6a7
AJ		 5723 /* NIP cannot be restored if the memory exception comes from an helper */
5724 gen_update_nip(ctx, ctx->nip - 4);
5725 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5726 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5727#endif
5728}
5729
a750fc0b
JM		 5730/* mfdcrux (PPC 460) : user-mode access to DCR */
5731GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5732{
06dca6a7
AJ		 5733 /* NIP cannot be restored if the memory exception comes from an helper */
5734 gen_update_nip(ctx, ctx->nip - 4);
5735 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5736 /* Note: Rc update flag set leads to undefined state of Rc0 */
5737}
5738
5739/* mtdcrux (PPC 460) : user-mode access to DCR */
5740GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5741{
06dca6a7
AJ		 5742 /* NIP cannot be restored if the memory exception comes from an helper */
5743 gen_update_nip(ctx, ctx->nip - 4);
5744 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5745 /* Note: Rc update flag set leads to undefined state of Rc0 */
5746}
5747
76a66253
JM		 5748/* dccci */
5749GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5750{
5751#if defined(CONFIG_USER_ONLY)
e06fcd75 5752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5753#else
76db3ba4 5754 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5756 return;
5757 }
5758 /* interpreted as no-op */
5759#endif
5760}
5761
5762/* dcread */
5763GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5764{
5765#if defined(CONFIG_USER_ONLY)
e06fcd75 5766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5767#else
b61f2753 5768 TCGv EA, val;
76db3ba4 5769 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5771 return;
5772 }
76db3ba4 5773 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5774 EA = tcg_temp_new();
76db3ba4 5775 gen_addr_reg_index(ctx, EA);
a7812ae4 5776 val = tcg_temp_new();
76db3ba4 5777 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5778 tcg_temp_free(val);
5779 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5780 tcg_temp_free(EA);
76a66253
JM		 5781#endif
5782}
5783
5784/* icbt */
c7697e1f 5785GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5786{
5787 /* interpreted as no-op */
5788 /* XXX: specification say this is treated as a load by the MMU
5789 * but does not generate any exception
5790 */
5791}
5792
5793/* iccci */
5794GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5795{
5796#if defined(CONFIG_USER_ONLY)
e06fcd75 5797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5798#else
76db3ba4 5799 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5801 return;
5802 }
5803 /* interpreted as no-op */
5804#endif
5805}
5806
5807/* icread */
5808GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5809{
5810#if defined(CONFIG_USER_ONLY)
e06fcd75 5811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5812#else
76db3ba4 5813 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5815 return;
5816 }
5817 /* interpreted as no-op */
5818#endif
5819}
5820
76db3ba4 5821/* rfci (mem_idx only) */
c7697e1f 5822GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5823{
5824#if defined(CONFIG_USER_ONLY)
e06fcd75 5825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5826#else
76db3ba4 5827 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5828 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5829 return;
5830 }
5831 /* Restore CPU state */
d72a19f7 5832 gen_helper_40x_rfci();
e06fcd75 5833 gen_sync_exception(ctx);
a42bd6cc
JM		 5834#endif
5835}
5836
5837GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5838{
5839#if defined(CONFIG_USER_ONLY)
e06fcd75 5840 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5841#else
76db3ba4 5842 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5843 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5844 return;
5845 }
5846 /* Restore CPU state */
d72a19f7 5847 gen_helper_rfci();
e06fcd75 5848 gen_sync_exception(ctx);
a42bd6cc
JM		 5849#endif
5850}
5851
5852/* BookE specific */
2662a059 5853/* XXX: not implemented on 440 ? */
05332d70 5854GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5855{
5856#if defined(CONFIG_USER_ONLY)
e06fcd75 5857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5858#else
76db3ba4 5859 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5860 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5861 return;
5862 }
5863 /* Restore CPU state */
d72a19f7 5864 gen_helper_rfdi();
e06fcd75 5865 gen_sync_exception(ctx);
76a66253
JM		 5866#endif
5867}
5868
2662a059 5869/* XXX: not implemented on 440 ? */
a750fc0b 5870GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5871{
5872#if defined(CONFIG_USER_ONLY)
e06fcd75 5873 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5874#else
76db3ba4 5875 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5877 return;
5878 }
5879 /* Restore CPU state */
d72a19f7 5880 gen_helper_rfmci();
e06fcd75 5881 gen_sync_exception(ctx);
a42bd6cc
JM		 5882#endif
5883}
5eb7995e 5884
d9bce9d9 5885/* TLB management - PowerPC 405 implementation */
76a66253 5886/* tlbre */
c7697e1f 5887GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5888{
5889#if defined(CONFIG_USER_ONLY)
e06fcd75 5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5891#else
76db3ba4 5892 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5894 return;
5895 }
5896 switch (rB(ctx->opcode)) {
5897 case 0:
74d37793 5898 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5899 break;
5900 case 1:
74d37793 5901 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5902 break;
5903 default:
e06fcd75 5904 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5905 break;
9a64fbe4 5906 }
76a66253
JM		 5907#endif
5908}
5909
d9bce9d9 5910/* tlbsx - tlbsx. */
c7697e1f 5911GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5912{
5913#if defined(CONFIG_USER_ONLY)
e06fcd75 5914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5915#else
74d37793 5916 TCGv t0;
76db3ba4 5917 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5918 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5919 return;
5920 }
74d37793 5921 t0 = tcg_temp_new();
76db3ba4 5922 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5923 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5924 tcg_temp_free(t0);
5925 if (Rc(ctx->opcode)) {
5926 int l1 = gen_new_label();
5927 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5928 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5929 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5930 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5931 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5932 gen_set_label(l1);
5933 }
76a66253 5934#endif
79aceca5
FB		 5935}
5936
76a66253 5937/* tlbwe */
c7697e1f 5938GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5939{
76a66253 5940#if defined(CONFIG_USER_ONLY)
e06fcd75 5941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5942#else
76db3ba4 5943 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5944 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5945 return;
5946 }
5947 switch (rB(ctx->opcode)) {
5948 case 0:
74d37793 5949 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5950 break;
5951 case 1:
74d37793 5952 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5953 break;
5954 default:
e06fcd75 5955 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5956 break;
9a64fbe4 5957 }
76a66253
JM		 5958#endif
5959}
5960
a4bb6c3e 5961/* TLB management - PowerPC 440 implementation */
5eb7995e 5962/* tlbre */
c7697e1f 5963GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5964{
5965#if defined(CONFIG_USER_ONLY)
e06fcd75 5966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5967#else
76db3ba4 5968 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5970 return;
5971 }
5972 switch (rB(ctx->opcode)) {
5973 case 0:
5eb7995e 5974 case 1:
5eb7995e 5975 case 2:
74d37793
AJ		 5976 {
5977 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5978 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5979 tcg_temp_free_i32(t0);
5980 }
5eb7995e
JM		 5981 break;
5982 default:
e06fcd75 5983 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 5984 break;
5985 }
5986#endif
5987}
5988
5989/* tlbsx - tlbsx. */
c7697e1f 5990GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5991{
5992#if defined(CONFIG_USER_ONLY)
e06fcd75 5993 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5994#else
74d37793 5995 TCGv t0;
76db3ba4 5996 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5997 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5998 return;
5999 }
74d37793 6000 t0 = tcg_temp_new();
76db3ba4 6001 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 6002 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6003 tcg_temp_free(t0);
6004 if (Rc(ctx->opcode)) {
6005 int l1 = gen_new_label();
6006 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6007 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6008 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6009 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6010 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6011 gen_set_label(l1);
6012 }
5eb7995e
JM		 6013#endif
6014}
6015
6016/* tlbwe */
c7697e1f 6017GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 6018{
6019#if defined(CONFIG_USER_ONLY)
e06fcd75 6020 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6021#else
76db3ba4 6022 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6023 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6024 return;
6025 }
6026 switch (rB(ctx->opcode)) {
6027 case 0:
5eb7995e 6028 case 1:
5eb7995e 6029 case 2:
74d37793
AJ		 6030 {
6031 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6032 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6033 tcg_temp_free_i32(t0);
6034 }
5eb7995e
JM		 6035 break;
6036 default:
e06fcd75 6037 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6038 break;
6039 }
6040#endif
6041}
6042
76a66253 6043/* wrtee */
05332d70 6044GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6045{
6046#if defined(CONFIG_USER_ONLY)
e06fcd75 6047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6048#else
6527f6ea 6049 TCGv t0;
76db3ba4 6050 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6051 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6052 return;
6053 }
6527f6ea
AJ		 6054 t0 = tcg_temp_new();
6055 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6056 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6057 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6058 tcg_temp_free(t0);
dee96f6c
JM		 6059 /* Stop translation to have a chance to raise an exception
6060 * if we just set msr_ee to 1
6061 */
e06fcd75 6062 gen_stop_exception(ctx);
76a66253
JM		 6063#endif
6064}
6065
6066/* wrteei */
05332d70 6067GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6068{
6069#if defined(CONFIG_USER_ONLY)
e06fcd75 6070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6071#else
76db3ba4 6072 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6073 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6074 return;
6075 }
6527f6ea
AJ		 6076 if (ctx->opcode & 0x00010000) {
6077 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6078 /* Stop translation to have a chance to raise an exception */
e06fcd75 6079 gen_stop_exception(ctx);
6527f6ea 6080 } else {
1b6e5f99 6081 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6082 }
76a66253
JM		 6083#endif
6084}
6085
08e46e54 6086/* PowerPC 440 specific instructions */
76a66253
JM		 6087/* dlmzb */
6088GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6089{
ef0d51af
AJ		 6090 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6091 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6092 cpu_gpr[rB(ctx->opcode)], t0);
6093 tcg_temp_free_i32(t0);
76a66253
JM		 6094}
6095
6096/* mbar replaces eieio on 440 */
26370046 6097GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
76a66253
JM		 6098{
6099 /* interpreted as no-op */
6100}
6101
6102/* msync replaces sync on 440 */
0db1b20e 6103GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6104{
6105 /* interpreted as no-op */
6106}
6107
6108/* icbt */
c7697e1f 6109GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6110{
6111 /* interpreted as no-op */
6112 /* XXX: specification say this is treated as a load by the MMU
6113 * but does not generate any exception
6114 */
79aceca5
FB		 6115}
6116
a9d9eb8f
JM		 6117/*** Altivec vector extension ***/
6118/* Altivec registers moves */
a9d9eb8f 6119
564e571a
AJ		 6120static always_inline TCGv_ptr gen_avr_ptr(int reg)
6121{
e4704b3b 6122 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6123 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6124 return r;
6125}
6126
a9d9eb8f 6127#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6128GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6129{ \
fe1e5c53 6130 TCGv EA; \
a9d9eb8f 6131 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6132 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6133 return; \
6134 } \
76db3ba4 6135 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6136 EA = tcg_temp_new(); \
76db3ba4 6137 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6138 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6139 if (ctx->le_mode) { \
6140 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6141 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6142 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6143 } else { \
76db3ba4 6144 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6145 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6146 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6147 } \
6148 tcg_temp_free(EA); \
a9d9eb8f
JM		 6149}
6150
6151#define GEN_VR_STX(name, opc2, opc3) \
6152GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6153{ \
fe1e5c53 6154 TCGv EA; \
a9d9eb8f 6155 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6156 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6157 return; \
6158 } \
76db3ba4 6159 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6160 EA = tcg_temp_new(); \
76db3ba4 6161 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6162 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6163 if (ctx->le_mode) { \
6164 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6165 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6166 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6167 } else { \
76db3ba4 6168 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6169 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6170 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6171 } \
6172 tcg_temp_free(EA); \
a9d9eb8f
JM		 6173}
6174
cbfb6ae9
AJ		 6175#define GEN_VR_LVE(name, opc2, opc3) \
6176 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6177 { \
6178 TCGv EA; \
6179 TCGv_ptr rs; \
6180 if (unlikely(!ctx->altivec_enabled)) { \
6181 gen_exception(ctx, POWERPC_EXCP_VPU); \
6182 return; \
6183 } \
6184 gen_set_access_type(ctx, ACCESS_INT); \
6185 EA = tcg_temp_new(); \
6186 gen_addr_reg_index(ctx, EA); \
6187 rs = gen_avr_ptr(rS(ctx->opcode)); \
6188 gen_helper_lve##name (rs, EA); \
6189 tcg_temp_free(EA); \
6190 tcg_temp_free_ptr(rs); \
6191 }
6192
6193#define GEN_VR_STVE(name, opc2, opc3) \
6194 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6195 { \
6196 TCGv EA; \
6197 TCGv_ptr rs; \
6198 if (unlikely(!ctx->altivec_enabled)) { \
6199 gen_exception(ctx, POWERPC_EXCP_VPU); \
6200 return; \
6201 } \
6202 gen_set_access_type(ctx, ACCESS_INT); \
6203 EA = tcg_temp_new(); \
6204 gen_addr_reg_index(ctx, EA); \
6205 rs = gen_avr_ptr(rS(ctx->opcode)); \
6206 gen_helper_stve##name (rs, EA); \
6207 tcg_temp_free(EA); \
6208 tcg_temp_free_ptr(rs); \
6209 }
6210
fe1e5c53 6211GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6212/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6213GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6214
cbfb6ae9
AJ		 6215GEN_VR_LVE(bx, 0x07, 0x00);
6216GEN_VR_LVE(hx, 0x07, 0x01);
6217GEN_VR_LVE(wx, 0x07, 0x02);
6218
fe1e5c53 6219GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6220/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6221GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6222
cbfb6ae9
AJ		 6223GEN_VR_STVE(bx, 0x07, 0x04);
6224GEN_VR_STVE(hx, 0x07, 0x05);
6225GEN_VR_STVE(wx, 0x07, 0x06);
6226
bf8d8ded
AJ		 6227GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6228{
6229 TCGv_ptr rd;
6230 TCGv EA;
6231 if (unlikely(!ctx->altivec_enabled)) {
6232 gen_exception(ctx, POWERPC_EXCP_VPU);
6233 return;
6234 }
6235 EA = tcg_temp_new();
6236 gen_addr_reg_index(ctx, EA);
6237 rd = gen_avr_ptr(rD(ctx->opcode));
6238 gen_helper_lvsl(rd, EA);
6239 tcg_temp_free(EA);
6240 tcg_temp_free_ptr(rd);
6241}
6242
6243GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6244{
6245 TCGv_ptr rd;
6246 TCGv EA;
6247 if (unlikely(!ctx->altivec_enabled)) {
6248 gen_exception(ctx, POWERPC_EXCP_VPU);
6249 return;
6250 }
6251 EA = tcg_temp_new();
6252 gen_addr_reg_index(ctx, EA);
6253 rd = gen_avr_ptr(rD(ctx->opcode));
6254 gen_helper_lvsr(rd, EA);
6255 tcg_temp_free(EA);
6256 tcg_temp_free_ptr(rd);
6257}
6258
785f451b
AJ		 6259GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6260{
6261 TCGv_i32 t;
6262 if (unlikely(!ctx->altivec_enabled)) {
6263 gen_exception(ctx, POWERPC_EXCP_VPU);
6264 return;
6265 }
6266 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6267 t = tcg_temp_new_i32();
6268 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6269 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6270 tcg_temp_free_i32(t);
785f451b
AJ		 6271}
6272
6273GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6274{
6e87b7c7 6275 TCGv_ptr p;
785f451b
AJ		 6276 if (unlikely(!ctx->altivec_enabled)) {
6277 gen_exception(ctx, POWERPC_EXCP_VPU);
6278 return;
6279 }
6e87b7c7
AJ		 6280 p = gen_avr_ptr(rD(ctx->opcode));
6281 gen_helper_mtvscr(p);
6282 tcg_temp_free_ptr(p);
785f451b
AJ		 6283}
6284
7a9b96cf
AJ		 6285/* Logical operations */
6286#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6287GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6288{ \
6289 if (unlikely(!ctx->altivec_enabled)) { \
6290 gen_exception(ctx, POWERPC_EXCP_VPU); \
6291 return; \
6292 } \
6293 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6294 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6295}
6296
6297GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6298GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6299GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6300GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6301GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6302
8e27dd6f
AJ		 6303#define GEN_VXFORM(name, opc2, opc3) \
6304GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6305{ \
6306 TCGv_ptr ra, rb, rd; \
6307 if (unlikely(!ctx->altivec_enabled)) { \
6308 gen_exception(ctx, POWERPC_EXCP_VPU); \
6309 return; \
6310 } \
6311 ra = gen_avr_ptr(rA(ctx->opcode)); \
6312 rb = gen_avr_ptr(rB(ctx->opcode)); \
6313 rd = gen_avr_ptr(rD(ctx->opcode)); \
6314 gen_helper_##name (rd, ra, rb); \
6315 tcg_temp_free_ptr(ra); \
6316 tcg_temp_free_ptr(rb); \
6317 tcg_temp_free_ptr(rd); \
6318}
6319
7872c51c
AJ		 6320GEN_VXFORM(vaddubm, 0, 0);
6321GEN_VXFORM(vadduhm, 0, 1);
6322GEN_VXFORM(vadduwm, 0, 2);
6323GEN_VXFORM(vsububm, 0, 16);
6324GEN_VXFORM(vsubuhm, 0, 17);
6325GEN_VXFORM(vsubuwm, 0, 18);
e4039339
AJ		 6326GEN_VXFORM(vmaxub, 1, 0);
6327GEN_VXFORM(vmaxuh, 1, 1);
6328GEN_VXFORM(vmaxuw, 1, 2);
6329GEN_VXFORM(vmaxsb, 1, 4);
6330GEN_VXFORM(vmaxsh, 1, 5);
6331GEN_VXFORM(vmaxsw, 1, 6);
6332GEN_VXFORM(vminub, 1, 8);
6333GEN_VXFORM(vminuh, 1, 9);
6334GEN_VXFORM(vminuw, 1, 10);
6335GEN_VXFORM(vminsb, 1, 12);
6336GEN_VXFORM(vminsh, 1, 13);
6337GEN_VXFORM(vminsw, 1, 14);
fab3cbe9
AJ		 6338GEN_VXFORM(vavgub, 1, 16);
6339GEN_VXFORM(vavguh, 1, 17);
6340GEN_VXFORM(vavguw, 1, 18);
6341GEN_VXFORM(vavgsb, 1, 20);
6342GEN_VXFORM(vavgsh, 1, 21);
6343GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 6344GEN_VXFORM(vmrghb, 6, 0);
6345GEN_VXFORM(vmrghh, 6, 1);
6346GEN_VXFORM(vmrghw, 6, 2);
6347GEN_VXFORM(vmrglb, 6, 4);
6348GEN_VXFORM(vmrglh, 6, 5);
6349GEN_VXFORM(vmrglw, 6, 6);
2c277908
AJ		 6350GEN_VXFORM(vmuloub, 4, 0);
6351GEN_VXFORM(vmulouh, 4, 1);
6352GEN_VXFORM(vmulosb, 4, 4);
6353GEN_VXFORM(vmulosh, 4, 5);
6354GEN_VXFORM(vmuleub, 4, 8);
6355GEN_VXFORM(vmuleuh, 4, 9);
6356GEN_VXFORM(vmulesb, 4, 12);
6357GEN_VXFORM(vmulesh, 4, 13);
d79f0809
AJ		 6358GEN_VXFORM(vslb, 2, 4);
6359GEN_VXFORM(vslh, 2, 5);
6360GEN_VXFORM(vslw, 2, 6);
07ef34c3
AJ		 6361GEN_VXFORM(vsrb, 2, 8);
6362GEN_VXFORM(vsrh, 2, 9);
6363GEN_VXFORM(vsrw, 2, 10);
6364GEN_VXFORM(vsrab, 2, 12);
6365GEN_VXFORM(vsrah, 2, 13);
6366GEN_VXFORM(vsraw, 2, 14);
7b239bec
AJ		 6367GEN_VXFORM(vslo, 6, 16);
6368GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 6369GEN_VXFORM(vaddcuw, 0, 6);
6370GEN_VXFORM(vsubcuw, 0, 22);
5ab09f33
AJ		 6371GEN_VXFORM(vaddubs, 0, 8);
6372GEN_VXFORM(vadduhs, 0, 9);
6373GEN_VXFORM(vadduws, 0, 10);
6374GEN_VXFORM(vaddsbs, 0, 12);
6375GEN_VXFORM(vaddshs, 0, 13);
6376GEN_VXFORM(vaddsws, 0, 14);
6377GEN_VXFORM(vsububs, 0, 24);
6378GEN_VXFORM(vsubuhs, 0, 25);
6379GEN_VXFORM(vsubuws, 0, 26);
6380GEN_VXFORM(vsubsbs, 0, 28);
6381GEN_VXFORM(vsubshs, 0, 29);
6382GEN_VXFORM(vsubsws, 0, 30);
5e1d0985
AJ		 6383GEN_VXFORM(vrlb, 2, 0);
6384GEN_VXFORM(vrlh, 2, 1);
6385GEN_VXFORM(vrlw, 2, 2);
d9430add
AJ		 6386GEN_VXFORM(vsl, 2, 7);
6387GEN_VXFORM(vsr, 2, 11);
5335a145
AJ		 6388GEN_VXFORM(vpkuhum, 7, 0);
6389GEN_VXFORM(vpkuwum, 7, 1);
6390GEN_VXFORM(vpkuhus, 7, 2);
6391GEN_VXFORM(vpkuwus, 7, 3);
6392GEN_VXFORM(vpkshus, 7, 4);
6393GEN_VXFORM(vpkswus, 7, 5);
6394GEN_VXFORM(vpkshss, 7, 6);
6395GEN_VXFORM(vpkswss, 7, 7);
1dd9ffb9 6396GEN_VXFORM(vpkpx, 7, 12);
8142cddd
AJ		 6397GEN_VXFORM(vsum4ubs, 4, 24);
6398GEN_VXFORM(vsum4sbs, 4, 28);
6399GEN_VXFORM(vsum4shs, 4, 25);
6400GEN_VXFORM(vsum2sws, 4, 26);
6401GEN_VXFORM(vsumsws, 4, 30);
56fdd213
AJ		 6402GEN_VXFORM(vaddfp, 5, 0);
6403GEN_VXFORM(vsubfp, 5, 1);
1536ff64
AJ		 6404GEN_VXFORM(vmaxfp, 5, 16);
6405GEN_VXFORM(vminfp, 5, 17);
fab3cbe9 6406
0cbcd906
AJ		 6407#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6408 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6409 { \
6410 TCGv_ptr ra, rb, rd; \
6411 if (unlikely(!ctx->altivec_enabled)) { \
6412 gen_exception(ctx, POWERPC_EXCP_VPU); \
6413 return; \
6414 } \
6415 ra = gen_avr_ptr(rA(ctx->opcode)); \
6416 rb = gen_avr_ptr(rB(ctx->opcode)); \
6417 rd = gen_avr_ptr(rD(ctx->opcode)); \
6418 gen_helper_##opname (rd, ra, rb); \
6419 tcg_temp_free_ptr(ra); \
6420 tcg_temp_free_ptr(rb); \
6421 tcg_temp_free_ptr(rd); \
6422 }
6423
6424#define GEN_VXRFORM(name, opc2, opc3) \
6425 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6426 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6427
1add6e23
AJ		 6428GEN_VXRFORM(vcmpequb, 3, 0)
6429GEN_VXRFORM(vcmpequh, 3, 1)
6430GEN_VXRFORM(vcmpequw, 3, 2)
6431GEN_VXRFORM(vcmpgtsb, 3, 12)
6432GEN_VXRFORM(vcmpgtsh, 3, 13)
6433GEN_VXRFORM(vcmpgtsw, 3, 14)
6434GEN_VXRFORM(vcmpgtub, 3, 8)
6435GEN_VXRFORM(vcmpgtuh, 3, 9)
6436GEN_VXRFORM(vcmpgtuw, 3, 10)
819ca121
AJ		 6437GEN_VXRFORM(vcmpeqfp, 3, 3)
6438GEN_VXRFORM(vcmpgefp, 3, 7)
6439GEN_VXRFORM(vcmpgtfp, 3, 11)
6440GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 6441
c026766b
AJ		 6442#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6443 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6444 { \
6445 TCGv_ptr rd; \
6446 TCGv_i32 simm; \
6447 if (unlikely(!ctx->altivec_enabled)) { \
6448 gen_exception(ctx, POWERPC_EXCP_VPU); \
6449 return; \
6450 } \
6451 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6452 rd = gen_avr_ptr(rD(ctx->opcode)); \
6453 gen_helper_##name (rd, simm); \
6454 tcg_temp_free_i32(simm); \
6455 tcg_temp_free_ptr(rd); \
6456 }
6457
6458GEN_VXFORM_SIMM(vspltisb, 6, 12);
6459GEN_VXFORM_SIMM(vspltish, 6, 13);
6460GEN_VXFORM_SIMM(vspltisw, 6, 14);
6461
de5f2484
AJ		 6462#define GEN_VXFORM_NOA(name, opc2, opc3) \
6463 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6464 { \
6465 TCGv_ptr rb, rd; \
6466 if (unlikely(!ctx->altivec_enabled)) { \
6467 gen_exception(ctx, POWERPC_EXCP_VPU); \
6468 return; \
6469 } \
6470 rb = gen_avr_ptr(rB(ctx->opcode)); \
6471 rd = gen_avr_ptr(rD(ctx->opcode)); \
6472 gen_helper_##name (rd, rb); \
6473 tcg_temp_free_ptr(rb); \
6474 tcg_temp_free_ptr(rd); \
6475 }
6476
6cf1c6e5
AJ		 6477GEN_VXFORM_NOA(vupkhsb, 7, 8);
6478GEN_VXFORM_NOA(vupkhsh, 7, 9);
6479GEN_VXFORM_NOA(vupklsb, 7, 10);
6480GEN_VXFORM_NOA(vupklsh, 7, 11);
79f85c3a
AJ		 6481GEN_VXFORM_NOA(vupkhpx, 7, 13);
6482GEN_VXFORM_NOA(vupklpx, 7, 15);
bdfbac35 6483GEN_VXFORM_NOA(vrefp, 5, 4);
071fc3b1 6484GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
b580763f 6485GEN_VXFORM_NOA(vlogefp, 5, 7);
f6b19645
AJ		 6486GEN_VXFORM_NOA(vrfim, 5, 8);
6487GEN_VXFORM_NOA(vrfin, 5, 9);
6488GEN_VXFORM_NOA(vrfip, 5, 10);
6489GEN_VXFORM_NOA(vrfiz, 5, 11);
79f85c3a 6490
21d21583
AJ		 6491#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6492 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6493 { \
6494 TCGv_ptr rd; \
6495 TCGv_i32 simm; \
6496 if (unlikely(!ctx->altivec_enabled)) { \
6497 gen_exception(ctx, POWERPC_EXCP_VPU); \
6498 return; \
6499 } \
6500 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6501 rd = gen_avr_ptr(rD(ctx->opcode)); \
6502 gen_helper_##name (rd, simm); \
6503 tcg_temp_free_i32(simm); \
6504 tcg_temp_free_ptr(rd); \
6505 }
6506
27a4edb3
AJ		 6507#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6508 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6509 { \
6510 TCGv_ptr rb, rd; \
6511 TCGv_i32 uimm; \
6512 if (unlikely(!ctx->altivec_enabled)) { \
6513 gen_exception(ctx, POWERPC_EXCP_VPU); \
6514 return; \
6515 } \
6516 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6517 rb = gen_avr_ptr(rB(ctx->opcode)); \
6518 rd = gen_avr_ptr(rD(ctx->opcode)); \
6519 gen_helper_##name (rd, rb, uimm); \
6520 tcg_temp_free_i32(uimm); \
6521 tcg_temp_free_ptr(rb); \
6522 tcg_temp_free_ptr(rd); \
6523 }
6524
e4e6bee7
AJ		 6525GEN_VXFORM_UIMM(vspltb, 6, 8);
6526GEN_VXFORM_UIMM(vsplth, 6, 9);
6527GEN_VXFORM_UIMM(vspltw, 6, 10);
e140632e
AJ		 6528GEN_VXFORM_UIMM(vcfux, 5, 12);
6529GEN_VXFORM_UIMM(vcfsx, 5, 13);
875b31db
AJ		 6530GEN_VXFORM_UIMM(vctuxs, 5, 14);
6531GEN_VXFORM_UIMM(vctsxs, 5, 15);
e4e6bee7 6532
cd633b10
AJ		 6533GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6534{
6535 TCGv_ptr ra, rb, rd;
fce5ecb7 6536 TCGv_i32 sh;
cd633b10
AJ		 6537 if (unlikely(!ctx->altivec_enabled)) {
6538 gen_exception(ctx, POWERPC_EXCP_VPU);
6539 return;
6540 }
6541 ra = gen_avr_ptr(rA(ctx->opcode));
6542 rb = gen_avr_ptr(rB(ctx->opcode));
6543 rd = gen_avr_ptr(rD(ctx->opcode));
6544 sh = tcg_const_i32(VSH(ctx->opcode));
6545 gen_helper_vsldoi (rd, ra, rb, sh);
6546 tcg_temp_free_ptr(ra);
6547 tcg_temp_free_ptr(rb);
6548 tcg_temp_free_ptr(rd);
fce5ecb7 6549 tcg_temp_free_i32(sh);
cd633b10
AJ		 6550}
6551
707cec33
AJ		 6552#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6553 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6554 { \
6555 TCGv_ptr ra, rb, rc, rd; \
6556 if (unlikely(!ctx->altivec_enabled)) { \
6557 gen_exception(ctx, POWERPC_EXCP_VPU); \
6558 return; \
6559 } \
6560 ra = gen_avr_ptr(rA(ctx->opcode)); \
6561 rb = gen_avr_ptr(rB(ctx->opcode)); \
6562 rc = gen_avr_ptr(rC(ctx->opcode)); \
6563 rd = gen_avr_ptr(rD(ctx->opcode)); \
6564 if (Rc(ctx->opcode)) { \
6565 gen_helper_##name1 (rd, ra, rb, rc); \
6566 } else { \
6567 gen_helper_##name0 (rd, ra, rb, rc); \
6568 } \
6569 tcg_temp_free_ptr(ra); \
6570 tcg_temp_free_ptr(rb); \
6571 tcg_temp_free_ptr(rc); \
6572 tcg_temp_free_ptr(rd); \
6573 }
6574
b161ae27
AJ		 6575GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6576
bcd2ee23
AJ		 6577GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6578{
6579 TCGv_ptr ra, rb, rc, rd;
6580 if (unlikely(!ctx->altivec_enabled)) {
6581 gen_exception(ctx, POWERPC_EXCP_VPU);
6582 return;
6583 }
6584 ra = gen_avr_ptr(rA(ctx->opcode));
6585 rb = gen_avr_ptr(rB(ctx->opcode));
6586 rc = gen_avr_ptr(rC(ctx->opcode));
6587 rd = gen_avr_ptr(rD(ctx->opcode));
6588 gen_helper_vmladduhm(rd, ra, rb, rc);
6589 tcg_temp_free_ptr(ra);
6590 tcg_temp_free_ptr(rb);
6591 tcg_temp_free_ptr(rc);
6592 tcg_temp_free_ptr(rd);
6593}
6594
b04ae981 6595GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 6596GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 6597GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 6598GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 6599GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 6600
0487d6a8 6601/*** SPE extension ***/
0487d6a8 6602/* Register moves */
3cd7d1dd 6603
a7812ae4 6604static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6605#if defined(TARGET_PPC64)
6606 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6607#else
36aa55dc 6608 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6609#endif
f78fb44e 6610}
3cd7d1dd 6611
a7812ae4 6612static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6613#if defined(TARGET_PPC64)
6614 tcg_gen_mov_i64(cpu_gpr[reg], t);
6615#else
a7812ae4 6616 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6617 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6618 tcg_gen_shri_i64(tmp, t, 32);
6619 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6620 tcg_temp_free_i64(tmp);
3cd7d1dd 6621#endif
f78fb44e 6622}
3cd7d1dd 6623
0487d6a8
JM		 6624#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6625GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6626{ \
6627 if (Rc(ctx->opcode)) \
6628 gen_##name1(ctx); \
6629 else \
6630 gen_##name0(ctx); \
6631}
6632
6633/* Handler for undefined SPE opcodes */
b068d6a7 6634static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6635{
e06fcd75 6636 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 6637}
6638
57951c27
AJ		 6639/* SPE logic */
6640#if defined(TARGET_PPC64)
6641#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6642static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6643{ \
6644 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6645 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6646 return; \
6647 } \
57951c27
AJ		 6648 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6649 cpu_gpr[rB(ctx->opcode)]); \
6650}
6651#else
6652#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6653static always_inline void gen_##name (DisasContext *ctx) \
6654{ \
6655 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6656 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6657 return; \
6658 } \
6659 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6660 cpu_gpr[rB(ctx->opcode)]); \
6661 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6662 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6663}
57951c27
AJ		 6664#endif
6665
6666GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6667GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6668GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6669GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6670GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6671GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6672GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6673GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6674
57951c27
AJ		 6675/* SPE logic immediate */
6676#if defined(TARGET_PPC64)
6677#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6678static always_inline void gen_##name (DisasContext *ctx) \
6679{ \
6680 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6681 gen_exception(ctx, POWERPC_EXCP_APU); \
3d3a6a0a
AJ		 6682 return; \
6683 } \
a7812ae4
PB		 6684 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6685 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6686 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6687 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6688 tcg_opi(t0, t0, rB(ctx->opcode)); \
6689 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6690 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6691 tcg_temp_free_i64(t2); \
57951c27
AJ		 6692 tcg_opi(t1, t1, rB(ctx->opcode)); \
6693 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6694 tcg_temp_free_i32(t0); \
6695 tcg_temp_free_i32(t1); \
3d3a6a0a 6696}
57951c27
AJ		 6697#else
6698#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6699static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6700{ \
6701 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6702 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6703 return; \
6704 } \
57951c27
AJ		 6705 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6706 rB(ctx->opcode)); \
6707 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6708 rB(ctx->opcode)); \
0487d6a8 6709}
57951c27
AJ		 6710#endif
6711GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6712GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6713GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6714GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6715
57951c27
AJ		 6716/* SPE arithmetic */
6717#if defined(TARGET_PPC64)
6718#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6719static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6720{ \
6721 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6722 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6723 return; \
6724 } \
a7812ae4
PB		 6725 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6726 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6727 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6728 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6729 tcg_op(t0, t0); \
6730 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6731 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6732 tcg_temp_free_i64(t2); \
57951c27
AJ		 6733 tcg_op(t1, t1); \
6734 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6735 tcg_temp_free_i32(t0); \
6736 tcg_temp_free_i32(t1); \
0487d6a8 6737}
57951c27 6738#else
a7812ae4 6739#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6740static always_inline void gen_##name (DisasContext *ctx) \
6741{ \
6742 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6743 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6744 return; \
6745 } \
6746 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6747 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6748}
6749#endif
0487d6a8 6750
a7812ae4 6751static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6752{
6753 int l1 = gen_new_label();
6754 int l2 = gen_new_label();
0487d6a8 6755
57951c27
AJ		 6756 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6757 tcg_gen_neg_i32(ret, arg1);
6758 tcg_gen_br(l2);
6759 gen_set_label(l1);
a7812ae4 6760 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6761 gen_set_label(l2);
6762}
6763GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6764GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6765GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6766GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6767static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6768{
57951c27
AJ		 6769 tcg_gen_addi_i32(ret, arg1, 0x8000);
6770 tcg_gen_ext16u_i32(ret, ret);
6771}
6772GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6773GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6774GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6775
57951c27
AJ		 6776#if defined(TARGET_PPC64)
6777#define GEN_SPEOP_ARITH2(name, tcg_op) \
6778static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6779{ \
6780 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6781 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6782 return; \
6783 } \
a7812ae4
PB		 6784 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6785 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6786 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
501e23c4 6787 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6788 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6789 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6790 tcg_op(t0, t0, t2); \
6791 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6792 tcg_gen_trunc_i64_i32(t1, t3); \
6793 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6794 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6795 tcg_temp_free_i64(t3); \
57951c27 6796 tcg_op(t1, t1, t2); \
a7812ae4 6797 tcg_temp_free_i32(t2); \
57951c27 6798 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6799 tcg_temp_free_i32(t0); \
6800 tcg_temp_free_i32(t1); \
0487d6a8 6801}
57951c27
AJ		 6802#else
6803#define GEN_SPEOP_ARITH2(name, tcg_op) \
6804static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6805{ \
6806 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6807 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6808 return; \
6809 } \
57951c27
AJ		 6810 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6811 cpu_gpr[rB(ctx->opcode)]); \
6812 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6813 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6814}
57951c27 6815#endif
0487d6a8 6816
a7812ae4 6817static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6818{
a7812ae4 6819 TCGv_i32 t0;
57951c27 6820 int l1, l2;
0487d6a8 6821
57951c27
AJ		 6822 l1 = gen_new_label();
6823 l2 = gen_new_label();
a7812ae4 6824 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6825 /* No error here: 6 bits are used */
6826 tcg_gen_andi_i32(t0, arg2, 0x3F);
6827 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6828 tcg_gen_shr_i32(ret, arg1, t0);
6829 tcg_gen_br(l2);
6830 gen_set_label(l1);
6831 tcg_gen_movi_i32(ret, 0);
6832 tcg_gen_br(l2);
a7812ae4 6833 tcg_temp_free_i32(t0);
57951c27
AJ		 6834}
6835GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6836static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6837{
a7812ae4 6838 TCGv_i32 t0;
57951c27
AJ		 6839 int l1, l2;
6840
6841 l1 = gen_new_label();
6842 l2 = gen_new_label();
a7812ae4 6843 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6844 /* No error here: 6 bits are used */
6845 tcg_gen_andi_i32(t0, arg2, 0x3F);
6846 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6847 tcg_gen_sar_i32(ret, arg1, t0);
6848 tcg_gen_br(l2);
6849 gen_set_label(l1);
6850 tcg_gen_movi_i32(ret, 0);
6851 tcg_gen_br(l2);
a7812ae4 6852 tcg_temp_free_i32(t0);
57951c27
AJ		 6853}
6854GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6855static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6856{
a7812ae4 6857 TCGv_i32 t0;
57951c27
AJ		 6858 int l1, l2;
6859
6860 l1 = gen_new_label();
6861 l2 = gen_new_label();
a7812ae4 6862 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6863 /* No error here: 6 bits are used */
6864 tcg_gen_andi_i32(t0, arg2, 0x3F);
6865 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6866 tcg_gen_shl_i32(ret, arg1, t0);
6867 tcg_gen_br(l2);
6868 gen_set_label(l1);
6869 tcg_gen_movi_i32(ret, 0);
6870 tcg_gen_br(l2);
a7812ae4 6871 tcg_temp_free_i32(t0);
57951c27
AJ		 6872}
6873GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6874static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6875{
a7812ae4 6876 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6877 tcg_gen_andi_i32(t0, arg2, 0x1F);
6878 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6879 tcg_temp_free_i32(t0);
57951c27
AJ		 6880}
6881GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6882static always_inline void gen_evmergehi (DisasContext *ctx)
6883{
6884 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6885 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6886 return;
6887 }
6888#if defined(TARGET_PPC64)
a7812ae4
PB		 6889 TCGv t0 = tcg_temp_new();
6890 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6891 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6892 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6893 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6894 tcg_temp_free(t0);
6895 tcg_temp_free(t1);
6896#else
6897 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6898 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6899#endif
6900}
6901GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6902static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6903{
57951c27
AJ		 6904 tcg_gen_sub_i32(ret, arg2, arg1);
6905}
6906GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6907
57951c27
AJ		 6908/* SPE arithmetic immediate */
6909#if defined(TARGET_PPC64)
6910#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6911static always_inline void gen_##name (DisasContext *ctx) \
6912{ \
6913 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6914 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6915 return; \
6916 } \
a7812ae4
PB		 6917 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6918 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6919 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6920 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6921 tcg_op(t0, t0, rA(ctx->opcode)); \
6922 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6923 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 6924 tcg_temp_free_i64(t2); \
57951c27
AJ		 6925 tcg_op(t1, t1, rA(ctx->opcode)); \
6926 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6927 tcg_temp_free_i32(t0); \
6928 tcg_temp_free_i32(t1); \
57951c27
AJ		 6929}
6930#else
6931#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6932static always_inline void gen_##name (DisasContext *ctx) \
6933{ \
6934 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6935 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6936 return; \
6937 } \
6938 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6939 rA(ctx->opcode)); \
6940 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6941 rA(ctx->opcode)); \
6942}
6943#endif
6944GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6945GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6946
6947/* SPE comparison */
6948#if defined(TARGET_PPC64)
6949#define GEN_SPEOP_COMP(name, tcg_cond) \
6950static always_inline void gen_##name (DisasContext *ctx) \
6951{ \
6952 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6953 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6954 return; \
6955 } \
6956 int l1 = gen_new_label(); \
6957 int l2 = gen_new_label(); \
6958 int l3 = gen_new_label(); \
6959 int l4 = gen_new_label(); \
a7812ae4
PB		 6960 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6961 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6962 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6963 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6964 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6965 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6966 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6967 tcg_gen_br(l2); \
6968 gen_set_label(l1); \
6969 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6970 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6971 gen_set_label(l2); \
6972 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6973 tcg_gen_trunc_i64_i32(t0, t2); \
6974 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6975 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6976 tcg_temp_free_i64(t2); \
57951c27
AJ		 6977 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6978 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6979 ~(CRF_CH | CRF_CH_AND_CL)); \
6980 tcg_gen_br(l4); \
6981 gen_set_label(l3); \
6982 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6983 CRF_CH | CRF_CH_OR_CL); \
6984 gen_set_label(l4); \
a7812ae4
PB		 6985 tcg_temp_free_i32(t0); \
6986 tcg_temp_free_i32(t1); \
57951c27
AJ		 6987}
6988#else
6989#define GEN_SPEOP_COMP(name, tcg_cond) \
6990static always_inline void gen_##name (DisasContext *ctx) \
6991{ \
6992 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6993 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6994 return; \
6995 } \
6996 int l1 = gen_new_label(); \
6997 int l2 = gen_new_label(); \
6998 int l3 = gen_new_label(); \
6999 int l4 = gen_new_label(); \
7000 \
7001 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7002 cpu_gpr[rB(ctx->opcode)], l1); \
7003 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7004 tcg_gen_br(l2); \
7005 gen_set_label(l1); \
7006 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7007 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7008 gen_set_label(l2); \
7009 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7010 cpu_gprh[rB(ctx->opcode)], l3); \
7011 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7012 ~(CRF_CH | CRF_CH_AND_CL)); \
7013 tcg_gen_br(l4); \
7014 gen_set_label(l3); \
7015 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7016 CRF_CH | CRF_CH_OR_CL); \
7017 gen_set_label(l4); \
7018}
7019#endif
7020GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7021GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7022GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7023GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7024GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7025
7026/* SPE misc */
7027static always_inline void gen_brinc (DisasContext *ctx)
7028{
7029 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 7030 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7031 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 7032}
57951c27
AJ		 7033static always_inline void gen_evmergelo (DisasContext *ctx)
7034{
7035 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7036 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7037 return;
7038 }
7039#if defined(TARGET_PPC64)
a7812ae4
PB		 7040 TCGv t0 = tcg_temp_new();
7041 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7042 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7043 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7044 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7045 tcg_temp_free(t0);
7046 tcg_temp_free(t1);
7047#else
7048 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7049 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7050#endif
7051}
7052static always_inline void gen_evmergehilo (DisasContext *ctx)
7053{
7054 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7055 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7056 return;
7057 }
7058#if defined(TARGET_PPC64)
a7812ae4
PB		 7059 TCGv t0 = tcg_temp_new();
7060 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7061 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7062 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7063 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7064 tcg_temp_free(t0);
7065 tcg_temp_free(t1);
7066#else
7067 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7068 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7069#endif
7070}
7071static always_inline void gen_evmergelohi (DisasContext *ctx)
7072{
7073 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7074 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7075 return;
7076 }
7077#if defined(TARGET_PPC64)
a7812ae4
PB		 7078 TCGv t0 = tcg_temp_new();
7079 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7080 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7081 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7082 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7083 tcg_temp_free(t0);
7084 tcg_temp_free(t1);
7085#else
7086 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7087 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7088#endif
7089}
7090static always_inline void gen_evsplati (DisasContext *ctx)
7091{
38d14952 7092 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 7093
57951c27 7094#if defined(TARGET_PPC64)
38d14952 7095 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7096#else
7097 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7098 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7099#endif
7100}
b068d6a7 7101static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 7102{
38d14952 7103 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 7104
57951c27 7105#if defined(TARGET_PPC64)
38d14952 7106 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7107#else
7108 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7109 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7110#endif
0487d6a8
JM		 7111}
7112
57951c27
AJ		 7113static always_inline void gen_evsel (DisasContext *ctx)
7114{
7115 int l1 = gen_new_label();
7116 int l2 = gen_new_label();
7117 int l3 = gen_new_label();
7118 int l4 = gen_new_label();
a7812ae4 7119 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 7120#if defined(TARGET_PPC64)
a7812ae4
PB		 7121 TCGv t1 = tcg_temp_local_new();
7122 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 7123#endif
7124 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7125 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7126#if defined(TARGET_PPC64)
7127 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7128#else
7129 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7130#endif
7131 tcg_gen_br(l2);
7132 gen_set_label(l1);
7133#if defined(TARGET_PPC64)
7134 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7135#else
7136 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7137#endif
7138 gen_set_label(l2);
7139 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7140 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7141#if defined(TARGET_PPC64)
7142 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7143#else
7144 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7145#endif
7146 tcg_gen_br(l4);
7147 gen_set_label(l3);
7148#if defined(TARGET_PPC64)
7149 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7150#else
7151 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7152#endif
7153 gen_set_label(l4);
a7812ae4 7154 tcg_temp_free_i32(t0);
57951c27
AJ		 7155#if defined(TARGET_PPC64)
7156 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7157 tcg_temp_free(t1);
7158 tcg_temp_free(t2);
7159#endif
7160}
7161GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7162{
7163 gen_evsel(ctx);
7164}
7165GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7166{
7167 gen_evsel(ctx);
7168}
7169GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7170{
7171 gen_evsel(ctx);
7172}
7173GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7174{
7175 gen_evsel(ctx);
7176}
0487d6a8
JM		 7177
7178GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7179GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7180GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7181GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7182GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7183GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7184GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7185GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7186GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7187GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7188GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7189GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7190GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7191GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7192GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7193GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7194GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7195GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7196GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7197GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7198GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7199GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7200GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7201GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7202GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7203
6a6ae23f 7204/* SPE load and stores */
76db3ba4 7205static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 7206{
7207 target_ulong uimm = rB(ctx->opcode);
7208
76db3ba4 7209 if (rA(ctx->opcode) == 0) {
6a6ae23f 7210 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 7211 } else {
6a6ae23f 7212 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
76db3ba4
AJ		 7213#if defined(TARGET_PPC64)
7214 if (!ctx->sf_mode) {
7215 tcg_gen_ext32u_tl(EA, EA);
7216 }
7217#endif
7218 }
0487d6a8 7219}
6a6ae23f
AJ		 7220
7221static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7222{
7223#if defined(TARGET_PPC64)
76db3ba4 7224 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7225#else
7226 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 7227 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 7228 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7229 tcg_gen_shri_i64(t0, t0, 32);
7230 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7231 tcg_temp_free_i64(t0);
7232#endif
0487d6a8 7233}
6a6ae23f
AJ		 7234
7235static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7236{
0487d6a8 7237#if defined(TARGET_PPC64)
6a6ae23f 7238 TCGv t0 = tcg_temp_new();
76db3ba4 7239 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 7240 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 7241 gen_addr_add(ctx, addr, addr, 4);
7242 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 7243 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7244 tcg_temp_free(t0);
7245#else
76db3ba4
AJ		 7246 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7247 gen_addr_add(ctx, addr, addr, 4);
7248 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 7249#endif
0487d6a8 7250}
6a6ae23f
AJ		 7251
7252static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7253{
7254 TCGv t0 = tcg_temp_new();
7255#if defined(TARGET_PPC64)
76db3ba4 7256 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7257 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7258 gen_addr_add(ctx, addr, addr, 2);
7259 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7260 tcg_gen_shli_tl(t0, t0, 32);
7261 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7262 gen_addr_add(ctx, addr, addr, 2);
7263 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7264 tcg_gen_shli_tl(t0, t0, 16);
7265 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7266 gen_addr_add(ctx, addr, addr, 2);
7267 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7268 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7269#else
76db3ba4 7270 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7271 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7272 gen_addr_add(ctx, addr, addr, 2);
7273 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7274 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7275 gen_addr_add(ctx, addr, addr, 2);
7276 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7277 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7278 gen_addr_add(ctx, addr, addr, 2);
7279 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7280 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7281#endif
6a6ae23f 7282 tcg_temp_free(t0);
0487d6a8
JM		 7283}
7284
6a6ae23f
AJ		 7285static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7286{
7287 TCGv t0 = tcg_temp_new();
76db3ba4 7288 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7289#if defined(TARGET_PPC64)
7290 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7291 tcg_gen_shli_tl(t0, t0, 16);
7292 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7293#else
7294 tcg_gen_shli_tl(t0, t0, 16);
7295 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7296 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7297#endif
7298 tcg_temp_free(t0);
0487d6a8
JM		 7299}
7300
6a6ae23f
AJ		 7301static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7302{
7303 TCGv t0 = tcg_temp_new();
76db3ba4 7304 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7305#if defined(TARGET_PPC64)
7306 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7307 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7308#else
7309 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7310 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7311#endif
7312 tcg_temp_free(t0);
0487d6a8
JM		 7313}
7314
6a6ae23f
AJ		 7315static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7316{
7317 TCGv t0 = tcg_temp_new();
76db3ba4 7318 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7319#if defined(TARGET_PPC64)
7320 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7321 tcg_gen_ext32u_tl(t0, t0);
7322 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7323#else
7324 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7325 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7326#endif
7327 tcg_temp_free(t0);
7328}
7329
7330static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7331{
7332 TCGv t0 = tcg_temp_new();
7333#if defined(TARGET_PPC64)
76db3ba4 7334 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7335 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7336 gen_addr_add(ctx, addr, addr, 2);
7337 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7338 tcg_gen_shli_tl(t0, t0, 16);
7339 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7340#else
76db3ba4 7341 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7342 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7343 gen_addr_add(ctx, addr, addr, 2);
7344 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7345 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7346#endif
7347 tcg_temp_free(t0);
7348}
7349
7350static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7351{
7352#if defined(TARGET_PPC64)
7353 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 7354 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7355 gen_addr_add(ctx, addr, addr, 2);
7356 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7357 tcg_gen_shli_tl(t0, t0, 32);
7358 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7359 tcg_temp_free(t0);
7360#else
76db3ba4
AJ		 7361 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7362 gen_addr_add(ctx, addr, addr, 2);
7363 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7364#endif
7365}
7366
7367static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7368{
7369#if defined(TARGET_PPC64)
7370 TCGv t0 = tcg_temp_new();
76db3ba4 7371 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 7372 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7373 gen_addr_add(ctx, addr, addr, 2);
7374 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7375 tcg_gen_shli_tl(t0, t0, 32);
7376 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7377 tcg_temp_free(t0);
7378#else
76db3ba4
AJ		 7379 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7380 gen_addr_add(ctx, addr, addr, 2);
7381 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7382#endif
7383}
7384
7385static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7386{
7387 TCGv t0 = tcg_temp_new();
76db3ba4 7388 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 7389#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7390 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7391 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7392#else
7393 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7394 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7395#endif
7396 tcg_temp_free(t0);
7397}
7398
7399static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7400{
7401 TCGv t0 = tcg_temp_new();
7402#if defined(TARGET_PPC64)
76db3ba4 7403 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7404 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7405 tcg_gen_shli_tl(t0, t0, 32);
7406 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7407 gen_addr_add(ctx, addr, addr, 2);
7408 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7409 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7410 tcg_gen_shli_tl(t0, t0, 16);
7411 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7412#else
76db3ba4 7413 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7414 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7415 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7416 gen_addr_add(ctx, addr, addr, 2);
7417 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7418 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7419 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 7420#endif
6a6ae23f
AJ		 7421 tcg_temp_free(t0);
7422}
7423
7424static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7425{
7426#if defined(TARGET_PPC64)
76db3ba4 7427 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 7428#else
6a6ae23f
AJ		 7429 TCGv_i64 t0 = tcg_temp_new_i64();
7430 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 7431 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 7432 tcg_temp_free_i64(t0);
7433#endif
7434}
7435
7436static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7437{
0487d6a8 7438#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7439 TCGv t0 = tcg_temp_new();
7440 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7441 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7442 tcg_temp_free(t0);
7443#else
76db3ba4 7444 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7445#endif
76db3ba4
AJ		 7446 gen_addr_add(ctx, addr, addr, 4);
7447 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7448}
7449
7450static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7451{
7452 TCGv t0 = tcg_temp_new();
7453#if defined(TARGET_PPC64)
7454 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7455#else
7456 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7457#endif
76db3ba4
AJ		 7458 gen_qemu_st16(ctx, t0, addr);
7459 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 7460#if defined(TARGET_PPC64)
7461 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7462 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7463#else
76db3ba4 7464 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7465#endif
76db3ba4 7466 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7467 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7468 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7469 tcg_temp_free(t0);
76db3ba4
AJ		 7470 gen_addr_add(ctx, addr, addr, 2);
7471 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7472}
7473
7474static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7475{
7476 TCGv t0 = tcg_temp_new();
7477#if defined(TARGET_PPC64)
7478 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7479#else
7480 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7481#endif
76db3ba4
AJ		 7482 gen_qemu_st16(ctx, t0, addr);
7483 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7484 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7485 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7486 tcg_temp_free(t0);
7487}
7488
7489static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7490{
7491#if defined(TARGET_PPC64)
7492 TCGv t0 = tcg_temp_new();
7493 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7494 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7495 tcg_temp_free(t0);
7496#else
76db3ba4 7497 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7498#endif
76db3ba4
AJ		 7499 gen_addr_add(ctx, addr, addr, 2);
7500 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7501}
7502
7503static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7504{
7505#if defined(TARGET_PPC64)
7506 TCGv t0 = tcg_temp_new();
7507 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7508 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7509 tcg_temp_free(t0);
7510#else
76db3ba4 7511 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7512#endif
7513}
7514
7515static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7516{
76db3ba4 7517 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7518}
7519
7520#define GEN_SPEOP_LDST(name, opc2, sh) \
76db3ba4 7521GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6a6ae23f
AJ		 7522{ \
7523 TCGv t0; \
7524 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7525 gen_exception(ctx, POWERPC_EXCP_APU); \
6a6ae23f
AJ		 7526 return; \
7527 } \
76db3ba4 7528 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 7529 t0 = tcg_temp_new(); \
7530 if (Rc(ctx->opcode)) { \
76db3ba4 7531 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 7532 } else { \
76db3ba4 7533 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 7534 } \
7535 gen_op_##name(ctx, t0); \
7536 tcg_temp_free(t0); \
7537}
7538
7539GEN_SPEOP_LDST(evldd, 0x00, 3);
7540GEN_SPEOP_LDST(evldw, 0x01, 3);
7541GEN_SPEOP_LDST(evldh, 0x02, 3);
7542GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7543GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7544GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7545GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7546GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7547GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7548GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7549GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7550
7551GEN_SPEOP_LDST(evstdd, 0x10, 3);
7552GEN_SPEOP_LDST(evstdw, 0x11, 3);
7553GEN_SPEOP_LDST(evstdh, 0x12, 3);
7554GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7555GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7556GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7557GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7558
7559/* Multiply and add - TODO */
7560#if 0
7561GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7562GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7563GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7564GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7565GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7566GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7567GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7568GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7569GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7570GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7571GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7572GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7573
7574GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7575GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7576GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7577GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7578GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7579GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7580GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7581GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7582GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7583GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7584GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7585GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7586GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7587GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7588
7589GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7590GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7591GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7592GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7593GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7594GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7595
7596GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7597GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7598GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7599GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7600GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7601GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7602GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7603GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7604GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7605GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7606GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7607GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7608
7609GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7610GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7611GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7612GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7613GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7614
7615GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7616GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7617GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7618GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7619GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7620GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7621GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7622GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7623GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7624GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7625GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7626GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7627
7628GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7629GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7630GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7631GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7632GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7633#endif
7634
7635/*** SPE floating-point extension ***/
1c97856d
AJ		 7636#if defined(TARGET_PPC64)
7637#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7638static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7639{ \
1c97856d
AJ		 7640 TCGv_i32 t0; \
7641 TCGv t1; \
7642 t0 = tcg_temp_new_i32(); \
7643 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7644 gen_helper_##name(t0, t0); \
7645 t1 = tcg_temp_new(); \
7646 tcg_gen_extu_i32_tl(t1, t0); \
7647 tcg_temp_free_i32(t0); \
7648 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7649 0xFFFFFFFF00000000ULL); \
7650 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7651 tcg_temp_free(t1); \
0487d6a8 7652}
1c97856d
AJ		 7653#define GEN_SPEFPUOP_CONV_32_64(name) \
7654static always_inline void gen_##name (DisasContext *ctx) \
7655{ \
7656 TCGv_i32 t0; \
7657 TCGv t1; \
7658 t0 = tcg_temp_new_i32(); \
7659 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7660 t1 = tcg_temp_new(); \
7661 tcg_gen_extu_i32_tl(t1, t0); \
7662 tcg_temp_free_i32(t0); \
7663 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7664 0xFFFFFFFF00000000ULL); \
7665 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7666 tcg_temp_free(t1); \
7667}
7668#define GEN_SPEFPUOP_CONV_64_32(name) \
7669static always_inline void gen_##name (DisasContext *ctx) \
7670{ \
7671 TCGv_i32 t0 = tcg_temp_new_i32(); \
7672 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7673 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7674 tcg_temp_free_i32(t0); \
7675}
7676#define GEN_SPEFPUOP_CONV_64_64(name) \
7677static always_inline void gen_##name (DisasContext *ctx) \
7678{ \
7679 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7680}
7681#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7682static always_inline void gen_##name (DisasContext *ctx) \
7683{ \
1c97856d
AJ		 7684 TCGv_i32 t0, t1; \
7685 TCGv_i64 t2; \
57951c27 7686 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7687 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7688 return; \
7689 } \
1c97856d
AJ		 7690 t0 = tcg_temp_new_i32(); \
7691 t1 = tcg_temp_new_i32(); \
7692 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7693 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7694 gen_helper_##name(t0, t0, t1); \
7695 tcg_temp_free_i32(t1); \
7696 t2 = tcg_temp_new(); \
7697 tcg_gen_extu_i32_tl(t2, t0); \
7698 tcg_temp_free_i32(t0); \
7699 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7700 0xFFFFFFFF00000000ULL); \
7701 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7702 tcg_temp_free(t2); \
57951c27 7703}
1c97856d 7704#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7705static always_inline void gen_##name (DisasContext *ctx) \
7706{ \
7707 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7708 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7709 return; \
7710 } \
1c97856d
AJ		 7711 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7712 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7713}
1c97856d 7714#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7715static always_inline void gen_##name (DisasContext *ctx) \
7716{ \
1c97856d 7717 TCGv_i32 t0, t1; \
57951c27 7718 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7719 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7720 return; \
7721 } \
1c97856d
AJ		 7722 t0 = tcg_temp_new_i32(); \
7723 t1 = tcg_temp_new_i32(); \
7724 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7725 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7726 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7727 tcg_temp_free_i32(t0); \
7728 tcg_temp_free_i32(t1); \
7729}
7730#define GEN_SPEFPUOP_COMP_64(name) \
7731static always_inline void gen_##name (DisasContext *ctx) \
7732{ \
7733 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7734 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7735 return; \
7736 } \
7737 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7738 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7739}
7740#else
7741#define GEN_SPEFPUOP_CONV_32_32(name) \
7742static always_inline void gen_##name (DisasContext *ctx) \
7743{ \
7744 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7745}
1c97856d
AJ		 7746#define GEN_SPEFPUOP_CONV_32_64(name) \
7747static always_inline void gen_##name (DisasContext *ctx) \
7748{ \
7749 TCGv_i64 t0 = tcg_temp_new_i64(); \
7750 gen_load_gpr64(t0, rB(ctx->opcode)); \
7751 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7752 tcg_temp_free_i64(t0); \
7753}
7754#define GEN_SPEFPUOP_CONV_64_32(name) \
7755static always_inline void gen_##name (DisasContext *ctx) \
7756{ \
7757 TCGv_i64 t0 = tcg_temp_new_i64(); \
7758 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7759 gen_store_gpr64(rD(ctx->opcode), t0); \
7760 tcg_temp_free_i64(t0); \
7761}
7762#define GEN_SPEFPUOP_CONV_64_64(name) \
7763static always_inline void gen_##name (DisasContext *ctx) \
7764{ \
7765 TCGv_i64 t0 = tcg_temp_new_i64(); \
7766 gen_load_gpr64(t0, rB(ctx->opcode)); \
7767 gen_helper_##name(t0, t0); \
7768 gen_store_gpr64(rD(ctx->opcode), t0); \
7769 tcg_temp_free_i64(t0); \
7770}
7771#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7772static always_inline void gen_##name (DisasContext *ctx) \
7773{ \
7774 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7775 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7776 return; \
7777 } \
7778 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7779 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7780}
7781#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7782static always_inline void gen_##name (DisasContext *ctx) \
7783{ \
7784 TCGv_i64 t0, t1; \
7785 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7786 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7787 return; \
7788 } \
7789 t0 = tcg_temp_new_i64(); \
7790 t1 = tcg_temp_new_i64(); \
7791 gen_load_gpr64(t0, rA(ctx->opcode)); \
7792 gen_load_gpr64(t1, rB(ctx->opcode)); \
7793 gen_helper_##name(t0, t0, t1); \
7794 gen_store_gpr64(rD(ctx->opcode), t0); \
7795 tcg_temp_free_i64(t0); \
7796 tcg_temp_free_i64(t1); \
7797}
7798#define GEN_SPEFPUOP_COMP_32(name) \
7799static always_inline void gen_##name (DisasContext *ctx) \
7800{ \
7801 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7802 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7803 return; \
7804 } \
7805 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7806 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7807}
7808#define GEN_SPEFPUOP_COMP_64(name) \
7809static always_inline void gen_##name (DisasContext *ctx) \
7810{ \
7811 TCGv_i64 t0, t1; \
7812 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7813 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7814 return; \
7815 } \
7816 t0 = tcg_temp_new_i64(); \
7817 t1 = tcg_temp_new_i64(); \
7818 gen_load_gpr64(t0, rA(ctx->opcode)); \
7819 gen_load_gpr64(t1, rB(ctx->opcode)); \
7820 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7821 tcg_temp_free_i64(t0); \
7822 tcg_temp_free_i64(t1); \
7823}
7824#endif
57951c27 7825
0487d6a8
JM		 7826/* Single precision floating-point vectors operations */
7827/* Arithmetic */
1c97856d
AJ		 7828GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7829GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7830GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7831GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7832static always_inline void gen_evfsabs (DisasContext *ctx)
7833{
7834 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7835 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7836 return;
7837 }
7838#if defined(TARGET_PPC64)
7839 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7840#else
7841 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7842 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7843#endif
7844}
7845static always_inline void gen_evfsnabs (DisasContext *ctx)
7846{
7847 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7848 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7849 return;
7850 }
7851#if defined(TARGET_PPC64)
7852 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7853#else
7854 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7855 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7856#endif
7857}
7858static always_inline void gen_evfsneg (DisasContext *ctx)
7859{
7860 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7861 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7862 return;
7863 }
7864#if defined(TARGET_PPC64)
7865 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7866#else
7867 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7868 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7869#endif
7870}
7871
0487d6a8 7872/* Conversion */
1c97856d
AJ		 7873GEN_SPEFPUOP_CONV_64_64(evfscfui);
7874GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7875GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7876GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7877GEN_SPEFPUOP_CONV_64_64(evfsctui);
7878GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7879GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7880GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7881GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7882GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7883
0487d6a8 7884/* Comparison */
1c97856d
AJ		 7885GEN_SPEFPUOP_COMP_64(evfscmpgt);
7886GEN_SPEFPUOP_COMP_64(evfscmplt);
7887GEN_SPEFPUOP_COMP_64(evfscmpeq);
7888GEN_SPEFPUOP_COMP_64(evfststgt);
7889GEN_SPEFPUOP_COMP_64(evfststlt);
7890GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7891
7892/* Opcodes definitions */
40569b7e
AJ		 7893GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7894GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7895GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7896GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7897GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7898GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7899GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7900GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7901GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7902GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7903GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7904GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7905GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7906GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 7907
7908/* Single precision floating-point operations */
7909/* Arithmetic */
1c97856d
AJ		 7910GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7911GEN_SPEFPUOP_ARITH2_32_32(efssub);
7912GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7913GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7914static always_inline void gen_efsabs (DisasContext *ctx)
7915{
7916 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7917 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7918 return;
7919 }
7920 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7921}
7922static always_inline void gen_efsnabs (DisasContext *ctx)
7923{
7924 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7925 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7926 return;
7927 }
7928 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7929}
7930static always_inline void gen_efsneg (DisasContext *ctx)
7931{
7932 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7933 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7934 return;
7935 }
7936 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7937}
7938
0487d6a8 7939/* Conversion */
1c97856d
AJ		 7940GEN_SPEFPUOP_CONV_32_32(efscfui);
7941GEN_SPEFPUOP_CONV_32_32(efscfsi);
7942GEN_SPEFPUOP_CONV_32_32(efscfuf);
7943GEN_SPEFPUOP_CONV_32_32(efscfsf);
7944GEN_SPEFPUOP_CONV_32_32(efsctui);
7945GEN_SPEFPUOP_CONV_32_32(efsctsi);
7946GEN_SPEFPUOP_CONV_32_32(efsctuf);
7947GEN_SPEFPUOP_CONV_32_32(efsctsf);
7948GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7949GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7950GEN_SPEFPUOP_CONV_32_64(efscfd);
7951
0487d6a8 7952/* Comparison */
1c97856d
AJ		 7953GEN_SPEFPUOP_COMP_32(efscmpgt);
7954GEN_SPEFPUOP_COMP_32(efscmplt);
7955GEN_SPEFPUOP_COMP_32(efscmpeq);
7956GEN_SPEFPUOP_COMP_32(efststgt);
7957GEN_SPEFPUOP_COMP_32(efststlt);
7958GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7959
7960/* Opcodes definitions */
40569b7e
AJ		 7961GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7962GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7963GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7964GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7965GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7966GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7967GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7968GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7969GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7970GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7971GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7972GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7973GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7974GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 7975
7976/* Double precision floating-point operations */
7977/* Arithmetic */
1c97856d
AJ		 7978GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7979GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7980GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7981GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7982static always_inline void gen_efdabs (DisasContext *ctx)
7983{
7984 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7985 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7986 return;
7987 }
7988#if defined(TARGET_PPC64)
7989 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7990#else
7991 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7992#endif
7993}
7994static always_inline void gen_efdnabs (DisasContext *ctx)
7995{
7996 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7997 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7998 return;
7999 }
8000#if defined(TARGET_PPC64)
8001 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8002#else
8003 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8004#endif
8005}
8006static always_inline void gen_efdneg (DisasContext *ctx)
8007{
8008 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 8009 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 8010 return;
8011 }
8012#if defined(TARGET_PPC64)
8013 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8014#else
8015 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8016#endif
8017}
8018
0487d6a8 8019/* Conversion */
1c97856d
AJ		 8020GEN_SPEFPUOP_CONV_64_32(efdcfui);
8021GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8022GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8023GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8024GEN_SPEFPUOP_CONV_32_64(efdctui);
8025GEN_SPEFPUOP_CONV_32_64(efdctsi);
8026GEN_SPEFPUOP_CONV_32_64(efdctuf);
8027GEN_SPEFPUOP_CONV_32_64(efdctsf);
8028GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8029GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8030GEN_SPEFPUOP_CONV_64_32(efdcfs);
8031GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8032GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8033GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8034GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 8035
0487d6a8 8036/* Comparison */
1c97856d
AJ		 8037GEN_SPEFPUOP_COMP_64(efdcmpgt);
8038GEN_SPEFPUOP_COMP_64(efdcmplt);
8039GEN_SPEFPUOP_COMP_64(efdcmpeq);
8040GEN_SPEFPUOP_COMP_64(efdtstgt);
8041GEN_SPEFPUOP_COMP_64(efdtstlt);
8042GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 8043
8044/* Opcodes definitions */
40569b7e
AJ		 8045GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8046GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8047GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8048GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8049GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8050GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8051GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8052GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8053GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8054GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8055GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8056GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8057GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8058GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8059GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8060GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
0487d6a8 8061
79aceca5
FB		 8062/* End opcode list */
8063GEN_OPCODE_MARK(end);
8064
3fc6c082 8065#include "translate_init.c"
0411a972 8066#include "helper_regs.h"
79aceca5 8067
9a64fbe4 8068/*****************************************************************************/
3fc6c082 8069/* Misc PowerPC helpers */
36081602
JM		 8070void cpu_dump_state (CPUState *env, FILE *f,
8071 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8072 int flags)
79aceca5 8073{
3fc6c082
FB		 8074#define RGPL 4
8075#define RFPL 4
3fc6c082 8076
79aceca5
FB		 8077 int i;
8078
077fc206 8079 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 8080 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 8081 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8082 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 8083#if !defined(NO_TIMER_DUMP)
077fc206 8084 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 8085#if !defined(CONFIG_USER_ONLY)
8086 "DECR %08x"
8087#endif
8088 "\n",
077fc206 8089 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 8090#if !defined(CONFIG_USER_ONLY)
8091 , cpu_ppc_load_decr(env)
8092#endif
8093 );
077fc206 8094#endif
76a66253 8095 for (i = 0; i < 32; i++) {
3fc6c082
FB		 8096 if ((i & (RGPL - 1)) == 0)
8097 cpu_fprintf(f, "GPR%02d", i);
6b542af7 8098 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 8099 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 8100 cpu_fprintf(f, "\n");
76a66253 8101 }
3fc6c082 8102 cpu_fprintf(f, "CR ");
76a66253 8103 for (i = 0; i < 8; i++)
7fe48483
FB		 8104 cpu_fprintf(f, "%01x", env->crf[i]);
8105 cpu_fprintf(f, " [");
76a66253
JM		 8106 for (i = 0; i < 8; i++) {
8107 char a = '-';
8108 if (env->crf[i] & 0x08)
8109 a = 'L';
8110 else if (env->crf[i] & 0x04)
8111 a = 'G';
8112 else if (env->crf[i] & 0x02)
8113 a = 'E';
7fe48483 8114 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 8115 }
6b542af7 8116 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 8117 for (i = 0; i < 32; i++) {
8118 if ((i & (RFPL - 1)) == 0)
8119 cpu_fprintf(f, "FPR%02d", i);
26a76461 8120 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 8121 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 8122 cpu_fprintf(f, "\n");
79aceca5 8123 }
7889270a 8124 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
f2e63a42 8125#if !defined(CONFIG_USER_ONLY)
6b542af7 8126 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 8127 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 8128#endif
79aceca5 8129
3fc6c082
FB		 8130#undef RGPL
8131#undef RFPL
79aceca5
FB		 8132}
8133
76a66253
JM		 8134void cpu_dump_statistics (CPUState *env, FILE*f,
8135 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8136 int flags)
8137{
8138#if defined(DO_PPC_STATISTICS)
8139 opc_handler_t **t1, **t2, **t3, *handler;
8140 int op1, op2, op3;
8141
8142 t1 = env->opcodes;
8143 for (op1 = 0; op1 < 64; op1++) {
8144 handler = t1[op1];
8145 if (is_indirect_opcode(handler)) {
8146 t2 = ind_table(handler);
8147 for (op2 = 0; op2 < 32; op2++) {
8148 handler = t2[op2];
8149 if (is_indirect_opcode(handler)) {
8150 t3 = ind_table(handler);
8151 for (op3 = 0; op3 < 32; op3++) {
8152 handler = t3[op3];
8153 if (handler->count == 0)
8154 continue;
8155 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8156 "%016llx %lld\n",
8157 op1, op2, op3, op1, (op3 << 5) | op2,
8158 handler->oname,
8159 handler->count, handler->count);
8160 }
8161 } else {
8162 if (handler->count == 0)
8163 continue;
8164 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8165 "%016llx %lld\n",
8166 op1, op2, op1, op2, handler->oname,
8167 handler->count, handler->count);
8168 }
8169 }
8170 } else {
8171 if (handler->count == 0)
8172 continue;
8173 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8174 op1, op1, handler->oname,
8175 handler->count, handler->count);
8176 }
8177 }
8178#endif
8179}
8180
9a64fbe4 8181/*****************************************************************************/
2cfc5f17
TS		 8182static always_inline void gen_intermediate_code_internal (CPUState *env,
8183 TranslationBlock *tb,
8184 int search_pc)
79aceca5 8185{
9fddaa0c 8186 DisasContext ctx, *ctxp = &ctx;
79aceca5 8187 opc_handler_t **table, *handler;
0fa85d43 8188 target_ulong pc_start;
79aceca5 8189 uint16_t *gen_opc_end;
a1d1bb31 8190 CPUBreakpoint *bp;
79aceca5 8191 int j, lj = -1;
2e70f6ef
PB		 8192 int num_insns;
8193 int max_insns;
79aceca5
FB		 8194
8195 pc_start = tb->pc;
79aceca5 8196 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
046d6672 8197 ctx.nip = pc_start;
79aceca5 8198 ctx.tb = tb;
e1833e1f 8199 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 8200 ctx.spr_cb = env->spr_cb;
76db3ba4
AJ		 8201 ctx.mem_idx = env->mmu_idx;
8202 ctx.access_type = -1;
8203 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 8204#if defined(TARGET_PPC64)
8205 ctx.sf_mode = msr_sf;
9a64fbe4 8206#endif
3cc62370 8207 ctx.fpu_enabled = msr_fp;
a9d9eb8f 8208 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 8209 ctx.spe_enabled = msr_spe;
8210 else
8211 ctx.spe_enabled = 0;
a9d9eb8f
JM		 8212 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8213 ctx.altivec_enabled = msr_vr;
8214 else
8215 ctx.altivec_enabled = 0;
d26bfc9a 8216 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 8217 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 8218 else
8cbcb4fa 8219 ctx.singlestep_enabled = 0;
d26bfc9a 8220 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 8221 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8222 if (unlikely(env->singlestep_enabled))
8223 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 8224#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 8225 /* Single step trace mode */
8226 msr_se = 1;
8227#endif
2e70f6ef
PB		 8228 num_insns = 0;
8229 max_insns = tb->cflags & CF_COUNT_MASK;
8230 if (max_insns == 0)
8231 max_insns = CF_COUNT_MASK;
8232
8233 gen_icount_start();
9a64fbe4 8234 /* Set env in case of segfault during code fetch */
e1833e1f 8235 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 8236 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8237 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 8238 if (bp->pc == ctx.nip) {
e06fcd75 8239 gen_debug_exception(ctxp);
ea4e754f
FB		 8240 break;
8241 }
8242 }
8243 }
76a66253 8244 if (unlikely(search_pc)) {
79aceca5
FB		 8245 j = gen_opc_ptr - gen_opc_buf;
8246 if (lj < j) {
8247 lj++;
8248 while (lj < j)
8249 gen_opc_instr_start[lj++] = 0;
046d6672 8250 gen_opc_pc[lj] = ctx.nip;
79aceca5 8251 gen_opc_instr_start[lj] = 1;
2e70f6ef 8252 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 8253 }
8254 }
d12d51d5
AL		 8255 LOG_DISAS("----------------\n");
8256 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8257 ctx.nip, ctx.mem_idx, (int)msr_ir);
2e70f6ef
PB		 8258 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8259 gen_io_start();
76db3ba4 8260 if (unlikely(ctx.le_mode)) {
056401ea
JM		 8261 ctx.opcode = bswap32(ldl_code(ctx.nip));
8262 } else {
8263 ctx.opcode = ldl_code(ctx.nip);
111bfab3 8264 }
d12d51d5 8265 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 8266 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 8267 opc3(ctx.opcode), little_endian ? "little" : "big");
046d6672 8268 ctx.nip += 4;
3fc6c082 8269 table = env->opcodes;
2e70f6ef 8270 num_insns++;
79aceca5
FB		 8271 handler = table[opc1(ctx.opcode)];
8272 if (is_indirect_opcode(handler)) {
8273 table = ind_table(handler);
8274 handler = table[opc2(ctx.opcode)];
8275 if (is_indirect_opcode(handler)) {
8276 table = ind_table(handler);
8277 handler = table[opc3(ctx.opcode)];
8278 }
8279 }
8280 /* Is opcode *REALLY* valid ? */
76a66253 8281 if (unlikely(handler->handler == &gen_invalid)) {
93fcfe39
AL		 8282 if (qemu_log_enabled()) {
8283 qemu_log("invalid/unsupported opcode: "
8284 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8285 opc1(ctx.opcode), opc2(ctx.opcode),
8286 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 8287 } else {
8288 printf("invalid/unsupported opcode: "
6b542af7 8289 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 8290 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8291 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 8292 }
76a66253
JM		 8293 } else {
8294 if (unlikely((ctx.opcode & handler->inval) != 0)) {
93fcfe39
AL		 8295 if (qemu_log_enabled()) {
8296 qemu_log("invalid bits: %08x for opcode: "
8297 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8298 ctx.opcode & handler->inval, opc1(ctx.opcode),
8299 opc2(ctx.opcode), opc3(ctx.opcode),
8300 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 8301 } else {
8302 printf("invalid bits: %08x for opcode: "
6b542af7 8303 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 8304 ctx.opcode & handler->inval, opc1(ctx.opcode),
8305 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8306 ctx.opcode, ctx.nip - 4);
76a66253 8307 }
e06fcd75 8308 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 8309 break;
79aceca5 8310 }
79aceca5 8311 }
4b3686fa 8312 (*(handler->handler))(&ctx);
76a66253
JM		 8313#if defined(DO_PPC_STATISTICS)
8314 handler->count++;
8315#endif
9a64fbe4 8316 /* Check trace mode exceptions */
8cbcb4fa
AJ		 8317 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8318 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8319 ctx.exception != POWERPC_SYSCALL &&
8320 ctx.exception != POWERPC_EXCP_TRAP &&
8321 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 8322 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 8323 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 8324 (env->singlestep_enabled) ||
8325 num_insns >= max_insns)) {
d26bfc9a
JM		 8326 /* if we reach a page boundary or are single stepping, stop
8327 * generation
8328 */
8dd4983c 8329 break;
76a66253 8330 }
3fc6c082
FB		 8331#if defined (DO_SINGLE_STEP)
8332 break;
8333#endif
8334 }
2e70f6ef
PB		 8335 if (tb->cflags & CF_LAST_IO)
8336 gen_io_end();
e1833e1f 8337 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 8338 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 8339 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa 8340 if (unlikely(env->singlestep_enabled)) {
e06fcd75 8341 gen_debug_exception(ctxp);
8cbcb4fa 8342 }
76a66253 8343 /* Generate the return instruction */
57fec1fe 8344 tcg_gen_exit_tb(0);
9a64fbe4 8345 }
2e70f6ef 8346 gen_icount_end(tb, num_insns);
79aceca5 8347 *gen_opc_ptr = INDEX_op_end;
76a66253 8348 if (unlikely(search_pc)) {
9a64fbe4
FB		 8349 j = gen_opc_ptr - gen_opc_buf;
8350 lj++;
8351 while (lj <= j)
8352 gen_opc_instr_start[lj++] = 0;
9a64fbe4 8353 } else {
046d6672 8354 tb->size = ctx.nip - pc_start;
2e70f6ef 8355 tb->icount = num_insns;
9a64fbe4 8356 }
d9bce9d9 8357#if defined(DEBUG_DISAS)
93fcfe39
AL		 8358 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8359 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8fec2b8c 8360 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 8361 int flags;
237c0af0 8362 flags = env->bfd_mach;
76db3ba4 8363 flags |= ctx.le_mode << 16;
93fcfe39
AL		 8364 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8365 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8366 qemu_log("\n");
9fddaa0c 8367 }
79aceca5 8368#endif
79aceca5
FB		 8369}
8370
2cfc5f17 8371void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 8372{
2cfc5f17 8373 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 8374}
8375
2cfc5f17 8376void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 8377{
2cfc5f17 8378 gen_intermediate_code_internal(env, tb, 1);
79aceca5 8379}
d2856f1a
AJ		 8380
8381void gen_pc_load(CPUState *env, TranslationBlock *tb,
8382 unsigned long searched_pc, int pc_pos, void *puc)
8383{
d2856f1a 8384 env->nip = gen_opc_pc[pc_pos];
d2856f1a 8385}
Qemu copy for testing