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exploiting the new interface in vnc.c (Stefano Stabellini)
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
79aceca5 19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
e8fc4fa7 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
79aceca5 44
d12d51d5
AL		 45#ifdef PPC_DEBUG_DISAS
46# define LOG_DISAS(...) do { \
47 if (loglevel & CPU_LOG_TB_IN_ASM) \
48 fprintf(logfile, ## __VA_ARGS__); \
49 } while (0)
50#else
51# define LOG_DISAS(...) do { } while (0)
52#endif
a750fc0b
JM		 53/*****************************************************************************/
54/* Code translation helpers */
c53be334 55
f78fb44e 56/* global register indexes */
a7812ae4 57static TCGv_ptr cpu_env;
1d542695 58static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 59#if !defined(TARGET_PPC64)
1d542695 60 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 61#endif
a5e26afa 62 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 63 + 2*(10*6 + 22*7) /* AVRh, AVRl */
64 + 8*5 /* CRF */];
f78fb44e
AJ		 65static TCGv cpu_gpr[32];
66#if !defined(TARGET_PPC64)
67static TCGv cpu_gprh[32];
68#endif
a7812ae4
PB		 69static TCGv_i64 cpu_fpr[32];
70static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
71static TCGv_i32 cpu_crf[8];
bd568f18 72static TCGv cpu_nip;
6527f6ea 73static TCGv cpu_msr;
cfdcd37a
AJ		 74static TCGv cpu_ctr;
75static TCGv cpu_lr;
3d7b417e 76static TCGv cpu_xer;
cf360a32 77static TCGv cpu_reserve;
a7812ae4 78static TCGv_i32 cpu_fpscr;
a7859e89 79static TCGv_i32 cpu_access_type;
f78fb44e 80
2e70f6ef
PB		 81#include "gen-icount.h"
82
83void ppc_translate_init(void)
84{
f78fb44e
AJ		 85 int i;
86 char* p;
b2437bf2 87 static int done_init = 0;
f78fb44e 88
2e70f6ef
PB		 89 if (done_init)
90 return;
f78fb44e 91
a7812ae4 92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 93
f78fb44e 94 p = cpu_reg_names;
47e4661c
AJ		 95
96 for (i = 0; i < 8; i++) {
97 sprintf(p, "crf%d", i);
a7812ae4
PB		 98 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
99 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 100 p += 5;
101 }
102
f78fb44e
AJ		 103 for (i = 0; i < 32; i++) {
104 sprintf(p, "r%d", i);
a7812ae4 105 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 106 offsetof(CPUState, gpr[i]), p);
107 p += (i < 10) ? 3 : 4;
108#if !defined(TARGET_PPC64)
109 sprintf(p, "r%dH", i);
a7812ae4
PB		 110 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 112 p += (i < 10) ? 4 : 5;
113#endif
1d542695 114
a5e26afa 115 sprintf(p, "fp%d", i);
a7812ae4
PB		 116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUState, fpr[i]), p);
ec1ac72d 118 p += (i < 10) ? 4 : 5;
a5e26afa 119
1d542695 120 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 121#ifdef WORDS_BIGENDIAN
122 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
123 offsetof(CPUState, avr[i].u64[0]), p);
124#else
a7812ae4 125 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 126 offsetof(CPUState, avr[i].u64[1]), p);
127#endif
1d542695 128 p += (i < 10) ? 6 : 7;
ec1ac72d 129
1d542695 130 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 131#ifdef WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUState, avr[i].u64[1]), p);
134#else
a7812ae4 135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 136 offsetof(CPUState, avr[i].u64[0]), p);
137#endif
1d542695 138 p += (i < 10) ? 6 : 7;
f78fb44e 139 }
f10dc08e 140
a7812ae4 141 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 142 offsetof(CPUState, nip), "nip");
143
6527f6ea
AJ		 144 cpu_msr = tcg_global_mem_new(TCG_AREG0,
145 offsetof(CPUState, msr), "msr");
146
a7812ae4 147 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 148 offsetof(CPUState, ctr), "ctr");
149
a7812ae4 150 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 151 offsetof(CPUState, lr), "lr");
152
a7812ae4 153 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 154 offsetof(CPUState, xer), "xer");
155
cf360a32
AJ		 156 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
157 offsetof(CPUState, reserve), "reserve");
158
a7812ae4
PB		 159 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
160 offsetof(CPUState, fpscr), "fpscr");
e1571908 161
a7859e89
AJ		 162 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
163 offsetof(CPUState, access_type), "access_type");
164
f10dc08e 165 /* register helpers */
a7812ae4 166#define GEN_HELPER 2
f10dc08e
AJ		 167#include "helper.h"
168
2e70f6ef
PB		 169 done_init = 1;
170}
171
79aceca5
FB		 172/* internal defines */
173typedef struct DisasContext {
174 struct TranslationBlock *tb;
0fa85d43 175 target_ulong nip;
79aceca5 176 uint32_t opcode;
9a64fbe4 177 uint32_t exception;
3cc62370
FB		 178 /* Routine used to access memory */
179 int mem_idx;
76db3ba4 180 int access_type;
3cc62370 181 /* Translation flags */
76db3ba4 182 int le_mode;
d9bce9d9
JM		 183#if defined(TARGET_PPC64)
184 int sf_mode;
9a64fbe4 185#endif
3cc62370 186 int fpu_enabled;
a9d9eb8f 187 int altivec_enabled;
0487d6a8 188 int spe_enabled;
3fc6c082 189 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 190 int singlestep_enabled;
79aceca5
FB		 191} DisasContext;
192
3fc6c082 193struct opc_handler_t {
79aceca5
FB		 194 /* invalid bits */
195 uint32_t inval;
9a64fbe4 196 /* instruction type */
0487d6a8 197 uint64_t type;
79aceca5
FB		 198 /* handler */
199 void (*handler)(DisasContext *ctx);
a750fc0b 200#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 201 const char *oname;
a750fc0b
JM		 202#endif
203#if defined(DO_PPC_STATISTICS)
76a66253
JM		 204 uint64_t count;
205#endif
3fc6c082 206};
79aceca5 207
7c58044c
JM		 208static always_inline void gen_reset_fpstatus (void)
209{
210#ifdef CONFIG_SOFTFLOAT
a44d2ce1 211 gen_helper_reset_fpstatus();
7c58044c
JM		 212#endif
213}
214
0f2f39c2 215static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 216{
0f2f39c2 217 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 218
7c58044c
JM		 219 if (set_fprf != 0) {
220 /* This case might be optimized later */
0f2f39c2 221 tcg_gen_movi_i32(t0, 1);
af12906f 222 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 223 if (unlikely(set_rc)) {
0f2f39c2 224 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 225 }
af12906f 226 gen_helper_float_check_status();
7c58044c
JM		 227 } else if (unlikely(set_rc)) {
228 /* We always need to compute fpcc */
0f2f39c2 229 tcg_gen_movi_i32(t0, 0);
af12906f 230 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 231 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 232 }
af12906f 233
0f2f39c2 234 tcg_temp_free_i32(t0);
7c58044c
JM		 235}
236
76db3ba4 237static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
a7859e89 238{
76db3ba4
AJ		 239 if (ctx->access_type != access_type) {
240 tcg_gen_movi_i32(cpu_access_type, access_type);
241 ctx->access_type = access_type;
242 }
a7859e89
AJ		 243}
244
b068d6a7 245static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 246{
247#if defined(TARGET_PPC64)
248 if (ctx->sf_mode)
bd568f18 249 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 250 else
251#endif
bd568f18 252 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 253}
254
e06fcd75
AJ		 255static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
256{
257 TCGv_i32 t0, t1;
258 if (ctx->exception == POWERPC_EXCP_NONE) {
259 gen_update_nip(ctx, ctx->nip);
260 }
261 t0 = tcg_const_i32(excp);
262 t1 = tcg_const_i32(error);
263 gen_helper_raise_exception_err(t0, t1);
264 tcg_temp_free_i32(t0);
265 tcg_temp_free_i32(t1);
266 ctx->exception = (excp);
267}
e1833e1f 268
e06fcd75
AJ		 269static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
270{
271 TCGv_i32 t0;
272 if (ctx->exception == POWERPC_EXCP_NONE) {
273 gen_update_nip(ctx, ctx->nip);
274 }
275 t0 = tcg_const_i32(excp);
276 gen_helper_raise_exception(t0);
277 tcg_temp_free_i32(t0);
278 ctx->exception = (excp);
279}
e1833e1f 280
e06fcd75
AJ		 281static always_inline void gen_debug_exception (DisasContext *ctx)
282{
283 TCGv_i32 t0;
284 gen_update_nip(ctx, ctx->nip);
285 t0 = tcg_const_i32(EXCP_DEBUG);
286 gen_helper_raise_exception(t0);
287 tcg_temp_free_i32(t0);
288}
9a64fbe4 289
e06fcd75
AJ		 290static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
291{
292 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
293}
a9d9eb8f 294
f24e5695 295/* Stop translation */
e06fcd75 296static always_inline void gen_stop_exception (DisasContext *ctx)
3fc6c082 297{
d9bce9d9 298 gen_update_nip(ctx, ctx->nip);
e1833e1f 299 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 300}
301
f24e5695 302/* No need to update nip here, as execution flow will change */
e06fcd75 303static always_inline void gen_sync_exception (DisasContext *ctx)
2be0071f 304{
e1833e1f 305 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 306}
307
79aceca5
FB		 308#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
309static void gen_##name (DisasContext *ctx); \
310GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
311static void gen_##name (DisasContext *ctx)
312
c7697e1f
JM		 313#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
314static void gen_##name (DisasContext *ctx); \
315GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
316static void gen_##name (DisasContext *ctx)
317
79aceca5
FB		 318typedef struct opcode_t {
319 unsigned char opc1, opc2, opc3;
1235fc06 320#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 321 unsigned char pad[5];
322#else
323 unsigned char pad[1];
324#endif
79aceca5 325 opc_handler_t handler;
b55266b5 326 const char *oname;
79aceca5
FB		 327} opcode_t;
328
a750fc0b 329/*****************************************************************************/
79aceca5
FB		 330/*** Instruction decoding ***/
331#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 332static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 333{ \
334 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
335}
336
337#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 338static always_inline int32_t name (uint32_t opcode) \
79aceca5 339{ \
18fba28c 340 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 341}
342
343/* Opcode part 1 */
344EXTRACT_HELPER(opc1, 26, 6);
345/* Opcode part 2 */
346EXTRACT_HELPER(opc2, 1, 5);
347/* Opcode part 3 */
348EXTRACT_HELPER(opc3, 6, 5);
349/* Update Cr0 flags */
350EXTRACT_HELPER(Rc, 0, 1);
351/* Destination */
352EXTRACT_HELPER(rD, 21, 5);
353/* Source */
354EXTRACT_HELPER(rS, 21, 5);
355/* First operand */
356EXTRACT_HELPER(rA, 16, 5);
357/* Second operand */
358EXTRACT_HELPER(rB, 11, 5);
359/* Third operand */
360EXTRACT_HELPER(rC, 6, 5);
361/*** Get CRn ***/
362EXTRACT_HELPER(crfD, 23, 3);
363EXTRACT_HELPER(crfS, 18, 3);
364EXTRACT_HELPER(crbD, 21, 5);
365EXTRACT_HELPER(crbA, 16, 5);
366EXTRACT_HELPER(crbB, 11, 5);
367/* SPR / TBL */
3fc6c082 368EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 369static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 370{
371 uint32_t sprn = _SPR(opcode);
372
373 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
374}
79aceca5
FB		 375/*** Get constants ***/
376EXTRACT_HELPER(IMM, 12, 8);
377/* 16 bits signed immediate value */
378EXTRACT_SHELPER(SIMM, 0, 16);
379/* 16 bits unsigned immediate value */
380EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 381/* 5 bits signed immediate value */
382EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 383/* 5 bits signed immediate value */
384EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 385/* Bit count */
386EXTRACT_HELPER(NB, 11, 5);
387/* Shift count */
388EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 389/* Vector shift count */
390EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 391/* Mask start */
392EXTRACT_HELPER(MB, 6, 5);
393/* Mask end */
394EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 395/* Trap operand */
396EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 397
398EXTRACT_HELPER(CRM, 12, 8);
399EXTRACT_HELPER(FM, 17, 8);
400EXTRACT_HELPER(SR, 16, 4);
e4bb997e 401EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 402
79aceca5
FB		 403/*** Jump target decoding ***/
404/* Displacement */
405EXTRACT_SHELPER(d, 0, 16);
406/* Immediate address */
b068d6a7 407static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 408{
409 return (opcode >> 0) & 0x03FFFFFC;
410}
411
b068d6a7 412static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 413{
414 return (opcode >> 0) & 0xFFFC;
415}
416
417EXTRACT_HELPER(BO, 21, 5);
418EXTRACT_HELPER(BI, 16, 5);
419/* Absolute/relative address */
420EXTRACT_HELPER(AA, 1, 1);
421/* Link */
422EXTRACT_HELPER(LK, 0, 1);
423
424/* Create a mask between <start> and <end> bits */
b068d6a7 425static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 426{
76a66253 427 target_ulong ret;
79aceca5 428
76a66253
JM		 429#if defined(TARGET_PPC64)
430 if (likely(start == 0)) {
6f2d8978 431 ret = UINT64_MAX << (63 - end);
76a66253 432 } else if (likely(end == 63)) {
6f2d8978 433 ret = UINT64_MAX >> start;
76a66253
JM		 434 }
435#else
436 if (likely(start == 0)) {
6f2d8978 437 ret = UINT32_MAX << (31 - end);
76a66253 438 } else if (likely(end == 31)) {
6f2d8978 439 ret = UINT32_MAX >> start;
76a66253
JM		 440 }
441#endif
442 else {
443 ret = (((target_ulong)(-1ULL)) >> (start)) ^
444 (((target_ulong)(-1ULL) >> (end)) >> 1);
445 if (unlikely(start > end))
446 return ~ret;
447 }
79aceca5
FB		 448
449 return ret;
450}
451
a750fc0b
JM		 452/*****************************************************************************/
453/* PowerPC Instructions types definitions */
454enum {
1b413d55 455 PPC_NONE = 0x0000000000000000ULL,
12de9a39 456 /* PowerPC base instructions set */
1b413d55
JM		 457 PPC_INSNS_BASE = 0x0000000000000001ULL,
458 /* integer operations instructions */
a750fc0b 459#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 460 /* flow control instructions */
a750fc0b 461#define PPC_FLOW PPC_INSNS_BASE
1b413d55 462 /* virtual memory instructions */
a750fc0b 463#define PPC_MEM PPC_INSNS_BASE
1b413d55 464 /* ld/st with reservation instructions */
a750fc0b 465#define PPC_RES PPC_INSNS_BASE
1b413d55 466 /* spr/msr access instructions */
a750fc0b 467#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 468 /* Deprecated instruction sets */
469 /* Original POWER instruction set */
f610349f 470 PPC_POWER = 0x0000000000000002ULL,
1b413d55 471 /* POWER2 instruction set extension */
f610349f 472 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 473 /* Power RTC support */
f610349f 474 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 475 /* Power-to-PowerPC bridge (601) */
f610349f 476 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 477 /* 64 bits PowerPC instruction set */
f610349f 478 PPC_64B = 0x0000000000000020ULL,
1b413d55 479 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 480 PPC_64BX = 0x0000000000000040ULL,
1b413d55 481 /* 64 bits hypervisor extensions */
f610349f 482 PPC_64H = 0x0000000000000080ULL,
1b413d55 483 /* New wait instruction (PowerPC 2.0x) */
f610349f 484 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 485 /* Time base mftb instruction */
f610349f 486 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 487
488 /* Fixed-point unit extensions */
489 /* PowerPC 602 specific */
f610349f 490 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 491 /* isel instruction */
492 PPC_ISEL = 0x0000000000000800ULL,
493 /* popcntb instruction */
494 PPC_POPCNTB = 0x0000000000001000ULL,
495 /* string load / store */
496 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 497
498 /* Floating-point unit extensions */
499 /* Optional floating point instructions */
500 PPC_FLOAT = 0x0000000000010000ULL,
501 /* New floating-point extensions (PowerPC 2.0x) */
502 PPC_FLOAT_EXT = 0x0000000000020000ULL,
503 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
504 PPC_FLOAT_FRES = 0x0000000000080000ULL,
505 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
506 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
507 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
508 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
509
510 /* Vector/SIMD extensions */
511 /* Altivec support */
512 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 513 /* PowerPC 2.03 SPE extension */
05332d70 514 PPC_SPE = 0x0000000002000000ULL,
1b413d55 515 /* PowerPC 2.03 SPE floating-point extension */
05332d70 516 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 517
12de9a39 518 /* Optional memory control instructions */
1b413d55
JM		 519 PPC_MEM_TLBIA = 0x0000000010000000ULL,
520 PPC_MEM_TLBIE = 0x0000000020000000ULL,
521 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
522 /* sync instruction */
523 PPC_MEM_SYNC = 0x0000000080000000ULL,
524 /* eieio instruction */
525 PPC_MEM_EIEIO = 0x0000000100000000ULL,
526
527 /* Cache control instructions */
c8623f2e 528 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 529 /* icbi instruction */
05332d70 530 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 531 /* dcbz instruction with fixed cache line size */
05332d70 532 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 533 /* dcbz instruction with tunable cache line size */
05332d70 534 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 535 /* dcba instruction */
05332d70
JM		 536 PPC_CACHE_DCBA = 0x0000002000000000ULL,
537 /* Freescale cache locking instructions */
538 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 539
540 /* MMU related extensions */
541 /* external control instructions */
05332d70 542 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 543 /* segment register access instructions */
05332d70 544 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 545 /* PowerPC 6xx TLB management instructions */
05332d70 546 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 547 /* PowerPC 74xx TLB management instructions */
05332d70 548 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 549 /* PowerPC 40x TLB management instructions */
05332d70 550 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 551 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 552 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 553 /* SLB management */
05332d70 554 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 555
12de9a39 556 /* Embedded PowerPC dedicated instructions */
05332d70 557 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 558 /* PowerPC 40x exception model */
05332d70 559 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 560 /* PowerPC 405 Mac instructions */
05332d70 561 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 562 /* PowerPC 440 specific instructions */
05332d70 563 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 564 /* BookE (embedded) PowerPC specification */
05332d70
JM		 565 PPC_BOOKE = 0x0010000000000000ULL,
566 /* mfapidi instruction */
567 PPC_MFAPIDI = 0x0020000000000000ULL,
568 /* tlbiva instruction */
569 PPC_TLBIVA = 0x0040000000000000ULL,
570 /* tlbivax instruction */
571 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 572 /* PowerPC 4xx dedicated instructions */
05332d70 573 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 574 /* PowerPC 40x ibct instructions */
05332d70 575 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 576 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 577 PPC_RFMCI = 0x0400000000000000ULL,
578 /* rfdi instruction */
579 PPC_RFDI = 0x0800000000000000ULL,
580 /* DCR accesses */
581 PPC_DCR = 0x1000000000000000ULL,
582 /* DCR extended accesse */
583 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 584 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 585 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 586};
587
588/*****************************************************************************/
589/* PowerPC instructions table */
3fc6c082
FB		 590#if HOST_LONG_BITS == 64
591#define OPC_ALIGN 8
592#else
593#define OPC_ALIGN 4
594#endif
1b039c09 595#if defined(__APPLE__)
d9bce9d9 596#define OPCODES_SECTION \
3fc6c082 597 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 598#else
d9bce9d9 599#define OPCODES_SECTION \
3fc6c082 600 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 601#endif
602
76a66253 603#if defined(DO_PPC_STATISTICS)
79aceca5 604#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 605OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 606 .opc1 = op1, \
607 .opc2 = op2, \
608 .opc3 = op3, \
18fba28c 609 .pad = { 0, }, \
79aceca5
FB		 610 .handler = { \
611 .inval = invl, \
9a64fbe4 612 .type = _typ, \
79aceca5 613 .handler = &gen_##name, \
76a66253 614 .oname = stringify(name), \
79aceca5 615 }, \
3fc6c082 616 .oname = stringify(name), \
79aceca5 617}
c7697e1f
JM		 618#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
619OPCODES_SECTION opcode_t opc_##name = { \
620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
623 .pad = { 0, }, \
624 .handler = { \
625 .inval = invl, \
626 .type = _typ, \
627 .handler = &gen_##name, \
628 .oname = onam, \
629 }, \
630 .oname = onam, \
631}
76a66253
JM		 632#else
633#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
634OPCODES_SECTION opcode_t opc_##name = { \
635 .opc1 = op1, \
636 .opc2 = op2, \
637 .opc3 = op3, \
638 .pad = { 0, }, \
639 .handler = { \
640 .inval = invl, \
641 .type = _typ, \
642 .handler = &gen_##name, \
643 }, \
644 .oname = stringify(name), \
645}
c7697e1f
JM		 646#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
647OPCODES_SECTION opcode_t opc_##name = { \
648 .opc1 = op1, \
649 .opc2 = op2, \
650 .opc3 = op3, \
651 .pad = { 0, }, \
652 .handler = { \
653 .inval = invl, \
654 .type = _typ, \
655 .handler = &gen_##name, \
656 }, \
657 .oname = onam, \
658}
76a66253 659#endif
79aceca5
FB		 660
661#define GEN_OPCODE_MARK(name) \
18fba28c 662OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 663 .opc1 = 0xFF, \
664 .opc2 = 0xFF, \
665 .opc3 = 0xFF, \
18fba28c 666 .pad = { 0, }, \
79aceca5
FB		 667 .handler = { \
668 .inval = 0x00000000, \
9a64fbe4 669 .type = 0x00, \
79aceca5
FB		 670 .handler = NULL, \
671 }, \
3fc6c082 672 .oname = stringify(name), \
79aceca5
FB		 673}
674
54cdcae6
AJ		 675/* SPR load/store helpers */
676static always_inline void gen_load_spr(TCGv t, int reg)
677{
678 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
679}
680
681static always_inline void gen_store_spr(int reg, TCGv t)
682{
683 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
684}
685
79aceca5
FB		 686/* Start opcode list */
687GEN_OPCODE_MARK(start);
688
689/* Invalid instruction */
9a64fbe4
FB		 690GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
691{
e06fcd75 692 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 693}
694
79aceca5
FB		 695static opc_handler_t invalid_handler = {
696 .inval = 0xFFFFFFFF,
9a64fbe4 697 .type = PPC_NONE,
79aceca5
FB		 698 .handler = gen_invalid,
699};
700
e1571908
AJ		 701/*** Integer comparison ***/
702
ea363694 703static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 704{
705 int l1, l2, l3;
706
269f3e95
AJ		 707 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
708 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 709 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
710
711 l1 = gen_new_label();
712 l2 = gen_new_label();
713 l3 = gen_new_label();
714 if (s) {
ea363694
AJ		 715 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
716 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 717 } else {
ea363694
AJ		 718 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
719 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 720 }
721 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
722 tcg_gen_br(l3);
723 gen_set_label(l1);
724 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
725 tcg_gen_br(l3);
726 gen_set_label(l2);
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
728 gen_set_label(l3);
729}
730
ea363694 731static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 732{
ea363694
AJ		 733 TCGv t0 = tcg_const_local_tl(arg1);
734 gen_op_cmp(arg0, t0, s, crf);
735 tcg_temp_free(t0);
e1571908
AJ		 736}
737
738#if defined(TARGET_PPC64)
ea363694 739static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 740{
ea363694 741 TCGv t0, t1;
a7812ae4
PB		 742 t0 = tcg_temp_local_new();
743 t1 = tcg_temp_local_new();
e1571908 744 if (s) {
ea363694
AJ		 745 tcg_gen_ext32s_tl(t0, arg0);
746 tcg_gen_ext32s_tl(t1, arg1);
e1571908 747 } else {
ea363694
AJ		 748 tcg_gen_ext32u_tl(t0, arg0);
749 tcg_gen_ext32u_tl(t1, arg1);
e1571908 750 }
ea363694
AJ		 751 gen_op_cmp(t0, t1, s, crf);
752 tcg_temp_free(t1);
753 tcg_temp_free(t0);
e1571908
AJ		 754}
755
ea363694 756static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 757{
ea363694
AJ		 758 TCGv t0 = tcg_const_local_tl(arg1);
759 gen_op_cmp32(arg0, t0, s, crf);
760 tcg_temp_free(t0);
e1571908
AJ		 761}
762#endif
763
764static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
765{
766#if defined(TARGET_PPC64)
767 if (!(ctx->sf_mode))
768 gen_op_cmpi32(reg, 0, 1, 0);
769 else
770#endif
771 gen_op_cmpi(reg, 0, 1, 0);
772}
773
774/* cmp */
775GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
776{
777#if defined(TARGET_PPC64)
778 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
779 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
780 1, crfD(ctx->opcode));
781 else
782#endif
783 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
784 1, crfD(ctx->opcode));
785}
786
787/* cmpi */
788GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
789{
790#if defined(TARGET_PPC64)
791 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
792 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
793 1, crfD(ctx->opcode));
794 else
795#endif
796 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
797 1, crfD(ctx->opcode));
798}
799
800/* cmpl */
801GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
802{
803#if defined(TARGET_PPC64)
804 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
805 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
806 0, crfD(ctx->opcode));
807 else
808#endif
809 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
810 0, crfD(ctx->opcode));
811}
812
813/* cmpli */
814GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
815{
816#if defined(TARGET_PPC64)
817 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
818 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
819 0, crfD(ctx->opcode));
820 else
821#endif
822 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
823 0, crfD(ctx->opcode));
824}
825
826/* isel (PowerPC 2.03 specification) */
827GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
828{
829 int l1, l2;
830 uint32_t bi = rC(ctx->opcode);
831 uint32_t mask;
a7812ae4 832 TCGv_i32 t0;
e1571908
AJ		 833
834 l1 = gen_new_label();
835 l2 = gen_new_label();
836
837 mask = 1 << (3 - (bi & 0x03));
a7812ae4 838 t0 = tcg_temp_new_i32();
fea0c503
AJ		 839 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
840 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 841 if (rA(ctx->opcode) == 0)
842 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
843 else
844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
845 tcg_gen_br(l2);
846 gen_set_label(l1);
847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
848 gen_set_label(l2);
a7812ae4 849 tcg_temp_free_i32(t0);
e1571908
AJ		 850}
851
79aceca5 852/*** Integer arithmetic ***/
79aceca5 853
74637406
AJ		 854static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
855{
856 int l1;
857 TCGv t0;
79aceca5 858
74637406
AJ		 859 l1 = gen_new_label();
860 /* Start with XER OV disabled, the most likely case */
861 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 862 t0 = tcg_temp_local_new();
74637406
AJ		 863 tcg_gen_xor_tl(t0, arg0, arg1);
864#if defined(TARGET_PPC64)
865 if (!ctx->sf_mode)
866 tcg_gen_ext32s_tl(t0, t0);
867#endif
868 if (sub)
869 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
870 else
871 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
872 tcg_gen_xor_tl(t0, arg1, arg2);
873#if defined(TARGET_PPC64)
874 if (!ctx->sf_mode)
875 tcg_gen_ext32s_tl(t0, t0);
876#endif
877 if (sub)
878 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
879 else
880 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
881 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
882 gen_set_label(l1);
883 tcg_temp_free(t0);
79aceca5
FB		 884}
885
74637406
AJ		 886static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
887{
888 int l1 = gen_new_label();
d9bce9d9
JM		 889
890#if defined(TARGET_PPC64)
74637406
AJ		 891 if (!(ctx->sf_mode)) {
892 TCGv t0, t1;
a7812ae4
PB		 893 t0 = tcg_temp_new();
894 t1 = tcg_temp_new();
d9bce9d9 895
74637406
AJ		 896 tcg_gen_ext32u_tl(t0, arg1);
897 tcg_gen_ext32u_tl(t1, arg2);
898 if (sub) {
899 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 900 } else {
74637406
AJ		 901 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
902 }
a9730017
AJ		 903 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
904 gen_set_label(l1);
905 tcg_temp_free(t0);
906 tcg_temp_free(t1);
74637406
AJ		 907 } else
908#endif
a9730017
AJ		 909 {
910 if (sub) {
911 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
912 } else {
913 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
914 }
915 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
916 gen_set_label(l1);
74637406 917 }
d9bce9d9
JM		 918}
919
74637406
AJ		 920/* Common add function */
921static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
922 int add_ca, int compute_ca, int compute_ov)
923{
924 TCGv t0, t1;
d9bce9d9 925
74637406 926 if ((!compute_ca && !compute_ov) ||
a7812ae4 927 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 928 t0 = ret;
929 } else {
a7812ae4 930 t0 = tcg_temp_local_new();
74637406 931 }
79aceca5 932
74637406 933 if (add_ca) {
a7812ae4 934 t1 = tcg_temp_local_new();
74637406
AJ		 935 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
936 tcg_gen_shri_tl(t1, t1, XER_CA);
937 }
79aceca5 938
74637406
AJ		 939 if (compute_ca && compute_ov) {
940 /* Start with XER CA and OV disabled, the most likely case */
941 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
942 } else if (compute_ca) {
943 /* Start with XER CA disabled, the most likely case */
944 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
945 } else if (compute_ov) {
946 /* Start with XER OV disabled, the most likely case */
947 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
948 }
79aceca5 949
74637406
AJ		 950 tcg_gen_add_tl(t0, arg1, arg2);
951
952 if (compute_ca) {
953 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
954 }
955 if (add_ca) {
956 tcg_gen_add_tl(t0, t0, t1);
957 gen_op_arith_compute_ca(ctx, t0, t1, 0);
958 tcg_temp_free(t1);
959 }
960 if (compute_ov) {
961 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
962 }
963
964 if (unlikely(Rc(ctx->opcode) != 0))
965 gen_set_Rc0(ctx, t0);
966
a7812ae4 967 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 968 tcg_gen_mov_tl(ret, t0);
969 tcg_temp_free(t0);
970 }
39dd32ee 971}
74637406
AJ		 972/* Add functions with two operands */
973#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
974GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
975{ \
976 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
977 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
978 add_ca, compute_ca, compute_ov); \
979}
980/* Add functions with one operand and one immediate */
981#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
982 add_ca, compute_ca, compute_ov) \
983GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
984{ \
985 TCGv t0 = tcg_const_local_tl(const_val); \
986 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
987 cpu_gpr[rA(ctx->opcode)], t0, \
988 add_ca, compute_ca, compute_ov); \
989 tcg_temp_free(t0); \
990}
991
992/* add add. addo addo. */
993GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
994GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
995/* addc addc. addco addco. */
996GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
997GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
998/* adde adde. addeo addeo. */
999GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1000GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1001/* addme addme. addmeo addmeo. */
1002GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1003GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1004/* addze addze. addzeo addzeo.*/
1005GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1006GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1007/* addi */
1008GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1009{
74637406
AJ		 1010 target_long simm = SIMM(ctx->opcode);
1011
1012 if (rA(ctx->opcode) == 0) {
1013 /* li case */
1014 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1015 } else {
1016 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1017 }
d9bce9d9 1018}
74637406
AJ		 1019/* addic addic.*/
1020static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1021 int compute_Rc0)
d9bce9d9 1022{
74637406
AJ		 1023 target_long simm = SIMM(ctx->opcode);
1024
1025 /* Start with XER CA and OV disabled, the most likely case */
1026 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1027
1028 if (likely(simm != 0)) {
a7812ae4 1029 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1030 tcg_gen_addi_tl(t0, arg1, simm);
1031 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1032 tcg_gen_mov_tl(ret, t0);
1033 tcg_temp_free(t0);
1034 } else {
1035 tcg_gen_mov_tl(ret, arg1);
1036 }
1037 if (compute_Rc0) {
1038 gen_set_Rc0(ctx, ret);
1039 }
d9bce9d9 1040}
74637406 1041GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1042{
74637406 1043 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1044}
74637406 1045GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1046{
74637406 1047 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1048}
74637406
AJ		 1049/* addis */
1050GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1051{
74637406
AJ		 1052 target_long simm = SIMM(ctx->opcode);
1053
1054 if (rA(ctx->opcode) == 0) {
1055 /* lis case */
1056 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1057 } else {
1058 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1059 }
d9bce9d9 1060}
74637406
AJ		 1061
1062static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1063 int sign, int compute_ov)
d9bce9d9 1064{
2ef1b120
AJ		 1065 int l1 = gen_new_label();
1066 int l2 = gen_new_label();
a7812ae4
PB		 1067 TCGv_i32 t0 = tcg_temp_local_new_i32();
1068 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1069
2ef1b120
AJ		 1070 tcg_gen_trunc_tl_i32(t0, arg1);
1071 tcg_gen_trunc_tl_i32(t1, arg2);
1072 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1073 if (sign) {
2ef1b120
AJ		 1074 int l3 = gen_new_label();
1075 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1076 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1077 gen_set_label(l3);
2ef1b120 1078 tcg_gen_div_i32(t0, t0, t1);
74637406 1079 } else {
2ef1b120 1080 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1081 }
1082 if (compute_ov) {
1083 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1084 }
1085 tcg_gen_br(l2);
1086 gen_set_label(l1);
1087 if (sign) {
2ef1b120 1088 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1089 } else {
1090 tcg_gen_movi_i32(t0, 0);
1091 }
1092 if (compute_ov) {
1093 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1094 }
1095 gen_set_label(l2);
2ef1b120 1096 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1097 tcg_temp_free_i32(t0);
1098 tcg_temp_free_i32(t1);
74637406
AJ		 1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, ret);
d9bce9d9 1101}
74637406
AJ		 1102/* Div functions */
1103#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1104GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1105{ \
1106 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1107 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1108 sign, compute_ov); \
1109}
1110/* divwu divwu. divwuo divwuo. */
1111GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1112GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1113/* divw divw. divwo divwo. */
1114GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1115GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1116#if defined(TARGET_PPC64)
2ef1b120
AJ		 1117static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1118 int sign, int compute_ov)
d9bce9d9 1119{
2ef1b120
AJ		 1120 int l1 = gen_new_label();
1121 int l2 = gen_new_label();
74637406
AJ		 1122
1123 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1124 if (sign) {
2ef1b120 1125 int l3 = gen_new_label();
74637406
AJ		 1126 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1127 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1128 gen_set_label(l3);
74637406
AJ		 1129 tcg_gen_div_i64(ret, arg1, arg2);
1130 } else {
1131 tcg_gen_divu_i64(ret, arg1, arg2);
1132 }
1133 if (compute_ov) {
1134 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1135 }
1136 tcg_gen_br(l2);
1137 gen_set_label(l1);
1138 if (sign) {
1139 tcg_gen_sari_i64(ret, arg1, 63);
1140 } else {
1141 tcg_gen_movi_i64(ret, 0);
1142 }
1143 if (compute_ov) {
1144 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1145 }
1146 gen_set_label(l2);
1147 if (unlikely(Rc(ctx->opcode) != 0))
1148 gen_set_Rc0(ctx, ret);
d9bce9d9 1149}
74637406
AJ		 1150#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1151GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1152{ \
2ef1b120
AJ		 1153 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1154 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1155 sign, compute_ov); \
74637406
AJ		 1156}
1157/* divwu divwu. divwuo divwuo. */
1158GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1159GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1160/* divw divw. divwo divwo. */
1161GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1162GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1163#endif
74637406
AJ		 1164
1165/* mulhw mulhw. */
1166GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1167{
a7812ae4 1168 TCGv_i64 t0, t1;
74637406 1169
a7812ae4
PB		 1170 t0 = tcg_temp_new_i64();
1171 t1 = tcg_temp_new_i64();
74637406
AJ		 1172#if defined(TARGET_PPC64)
1173 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1174 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1175 tcg_gen_mul_i64(t0, t0, t1);
1176 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1177#else
1178 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1179 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1180 tcg_gen_mul_i64(t0, t0, t1);
1181 tcg_gen_shri_i64(t0, t0, 32);
1182 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1183#endif
a7812ae4
PB		 1184 tcg_temp_free_i64(t0);
1185 tcg_temp_free_i64(t1);
74637406
AJ		 1186 if (unlikely(Rc(ctx->opcode) != 0))
1187 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1188}
74637406
AJ		 1189/* mulhwu mulhwu. */
1190GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1191{
a7812ae4 1192 TCGv_i64 t0, t1;
74637406 1193
a7812ae4
PB		 1194 t0 = tcg_temp_new_i64();
1195 t1 = tcg_temp_new_i64();
d9bce9d9 1196#if defined(TARGET_PPC64)
74637406
AJ		 1197 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1198 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1199 tcg_gen_mul_i64(t0, t0, t1);
1200 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1201#else
1202 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1203 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1204 tcg_gen_mul_i64(t0, t0, t1);
1205 tcg_gen_shri_i64(t0, t0, 32);
1206 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1207#endif
a7812ae4
PB		 1208 tcg_temp_free_i64(t0);
1209 tcg_temp_free_i64(t1);
74637406
AJ		 1210 if (unlikely(Rc(ctx->opcode) != 0))
1211 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1212}
74637406
AJ		 1213/* mullw mullw. */
1214GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1215{
74637406
AJ		 1216 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1217 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1218 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1219 if (unlikely(Rc(ctx->opcode) != 0))
1220 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1221}
74637406
AJ		 1222/* mullwo mullwo. */
1223GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1224{
74637406 1225 int l1;
a7812ae4 1226 TCGv_i64 t0, t1;
74637406 1227
a7812ae4
PB		 1228 t0 = tcg_temp_new_i64();
1229 t1 = tcg_temp_new_i64();
74637406
AJ		 1230 l1 = gen_new_label();
1231 /* Start with XER OV disabled, the most likely case */
1232 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1233#if defined(TARGET_PPC64)
1234 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1235 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1236#else
1237 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1238 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1239#endif
74637406
AJ		 1240 tcg_gen_mul_i64(t0, t0, t1);
1241#if defined(TARGET_PPC64)
1242 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1243 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1244#else
1245 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1246 tcg_gen_ext32s_i64(t1, t0);
1247 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1248#endif
1249 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1250 gen_set_label(l1);
a7812ae4
PB		 1251 tcg_temp_free_i64(t0);
1252 tcg_temp_free_i64(t1);
74637406
AJ		 1253 if (unlikely(Rc(ctx->opcode) != 0))
1254 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1255}
74637406
AJ		 1256/* mulli */
1257GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1258{
74637406
AJ		 1259 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1260 SIMM(ctx->opcode));
d9bce9d9
JM		 1261}
1262#if defined(TARGET_PPC64)
74637406
AJ		 1263#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1264GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1265{ \
a7812ae4 1266 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1267 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1268 if (unlikely(Rc(ctx->opcode) != 0)) \
1269 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1270}
74637406
AJ		 1271/* mulhd mulhd. */
1272GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1273/* mulhdu mulhdu. */
1274GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1275/* mulld mulld. */
1276GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1277{
74637406
AJ		 1278 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1279 cpu_gpr[rB(ctx->opcode)]);
1280 if (unlikely(Rc(ctx->opcode) != 0))
1281 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1282}
74637406
AJ		 1283/* mulldo mulldo. */
1284GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1285#endif
74637406
AJ		 1286
1287/* neg neg. nego nego. */
ec6469a3 1288static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1289{
ec6469a3
AJ		 1290 int l1 = gen_new_label();
1291 int l2 = gen_new_label();
a7812ae4 1292 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1293#if defined(TARGET_PPC64)
74637406 1294 if (ctx->sf_mode) {
741a7444 1295 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1296 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1297 } else
1298#endif
1299 {
1300 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1301 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1302 }
74637406
AJ		 1303 tcg_gen_neg_tl(ret, arg1);
1304 if (ov_check) {
1305 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1306 }
1307 tcg_gen_br(l2);
1308 gen_set_label(l1);
ec6469a3 1309 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1310 if (ov_check) {
1311 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1312 }
1313 gen_set_label(l2);
ec6469a3 1314 tcg_temp_free(t0);
74637406
AJ		 1315 if (unlikely(Rc(ctx->opcode) != 0))
1316 gen_set_Rc0(ctx, ret);
1317}
1318GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1319{
ec6469a3 1320 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1321}
74637406 1322GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1323{
ec6469a3 1324 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1325}
74637406
AJ		 1326
1327/* Common subf function */
1328static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1329 int add_ca, int compute_ca, int compute_ov)
79aceca5 1330{
74637406 1331 TCGv t0, t1;
76a66253 1332
74637406 1333 if ((!compute_ca && !compute_ov) ||
a7812ae4 1334 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1335 t0 = ret;
e864cabd 1336 } else {
a7812ae4 1337 t0 = tcg_temp_local_new();
d9bce9d9 1338 }
76a66253 1339
74637406 1340 if (add_ca) {
a7812ae4 1341 t1 = tcg_temp_local_new();
74637406
AJ		 1342 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1343 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1344 }
79aceca5 1345
74637406
AJ		 1346 if (compute_ca && compute_ov) {
1347 /* Start with XER CA and OV disabled, the most likely case */
1348 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1349 } else if (compute_ca) {
1350 /* Start with XER CA disabled, the most likely case */
1351 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1352 } else if (compute_ov) {
1353 /* Start with XER OV disabled, the most likely case */
1354 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1355 }
1356
1357 if (add_ca) {
1358 tcg_gen_not_tl(t0, arg1);
1359 tcg_gen_add_tl(t0, t0, arg2);
1360 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1361 tcg_gen_add_tl(t0, t0, t1);
1362 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1363 tcg_temp_free(t1);
79aceca5 1364 } else {
74637406
AJ		 1365 tcg_gen_sub_tl(t0, arg2, arg1);
1366 if (compute_ca) {
1367 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1368 }
1369 }
1370 if (compute_ov) {
1371 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1372 }
1373
1374 if (unlikely(Rc(ctx->opcode) != 0))
1375 gen_set_Rc0(ctx, t0);
1376
a7812ae4 1377 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1378 tcg_gen_mov_tl(ret, t0);
1379 tcg_temp_free(t0);
79aceca5 1380 }
79aceca5 1381}
74637406
AJ		 1382/* Sub functions with Two operands functions */
1383#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1384GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1385{ \
1386 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1387 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1388 add_ca, compute_ca, compute_ov); \
1389}
1390/* Sub functions with one operand and one immediate */
1391#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1392 add_ca, compute_ca, compute_ov) \
1393GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1394{ \
1395 TCGv t0 = tcg_const_local_tl(const_val); \
1396 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1397 cpu_gpr[rA(ctx->opcode)], t0, \
1398 add_ca, compute_ca, compute_ov); \
1399 tcg_temp_free(t0); \
1400}
1401/* subf subf. subfo subfo. */
1402GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1403GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1404/* subfc subfc. subfco subfco. */
1405GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1406GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1407/* subfe subfe. subfeo subfo. */
1408GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1409GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1410/* subfme subfme. subfmeo subfmeo. */
1411GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1412GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1413/* subfze subfze. subfzeo subfzeo.*/
1414GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1415GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1416/* subfic */
1417GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1418{
74637406
AJ		 1419 /* Start with XER CA and OV disabled, the most likely case */
1420 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1421 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1422 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1423 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1424 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1425 tcg_temp_free(t1);
1426 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1427 tcg_temp_free(t0);
79aceca5
FB		 1428}
1429
79aceca5 1430/*** Integer logical ***/
26d67362
AJ		 1431#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1432GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1433{ \
26d67362
AJ		 1434 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1435 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1436 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1437 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1438}
79aceca5 1439
26d67362 1440#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1441GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1442{ \
26d67362 1443 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1444 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1445 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1446}
1447
1448/* and & and. */
26d67362 1449GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1450/* andc & andc. */
26d67362 1451GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1452/* andi. */
c7697e1f 1453GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1454{
26d67362
AJ		 1455 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1456 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1457}
1458/* andis. */
c7697e1f 1459GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1460{
26d67362
AJ		 1461 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1463}
79aceca5 1464/* cntlzw */
26d67362
AJ		 1465GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1466{
a7812ae4 1467 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1468 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1469 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1470}
79aceca5 1471/* eqv & eqv. */
26d67362 1472GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1473/* extsb & extsb. */
26d67362 1474GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1475/* extsh & extsh. */
26d67362 1476GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1477/* nand & nand. */
26d67362 1478GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1479/* nor & nor. */
26d67362 1480GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1481/* or & or. */
9a64fbe4
FB		 1482GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1483{
76a66253
JM		 1484 int rs, ra, rb;
1485
1486 rs = rS(ctx->opcode);
1487 ra = rA(ctx->opcode);
1488 rb = rB(ctx->opcode);
1489 /* Optimisation for mr. ri case */
1490 if (rs != ra || rs != rb) {
26d67362
AJ		 1491 if (rs != rb)
1492 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1493 else
1494 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1495 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1496 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1497 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1498 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1499#if defined(TARGET_PPC64)
1500 } else {
26d67362
AJ		 1501 int prio = 0;
1502
c80f84e3
JM		 1503 switch (rs) {
1504 case 1:
1505 /* Set process priority to low */
26d67362 1506 prio = 2;
c80f84e3
JM		 1507 break;
1508 case 6:
1509 /* Set process priority to medium-low */
26d67362 1510 prio = 3;
c80f84e3
JM		 1511 break;
1512 case 2:
1513 /* Set process priority to normal */
26d67362 1514 prio = 4;
c80f84e3 1515 break;
be147d08
JM		 1516#if !defined(CONFIG_USER_ONLY)
1517 case 31:
76db3ba4 1518 if (ctx->mem_idx > 0) {
be147d08 1519 /* Set process priority to very low */
26d67362 1520 prio = 1;
be147d08
JM		 1521 }
1522 break;
1523 case 5:
76db3ba4 1524 if (ctx->mem_idx > 0) {
be147d08 1525 /* Set process priority to medium-hight */
26d67362 1526 prio = 5;
be147d08
JM		 1527 }
1528 break;
1529 case 3:
76db3ba4 1530 if (ctx->mem_idx > 0) {
be147d08 1531 /* Set process priority to high */
26d67362 1532 prio = 6;
be147d08
JM		 1533 }
1534 break;
be147d08 1535 case 7:
76db3ba4 1536 if (ctx->mem_idx > 1) {
be147d08 1537 /* Set process priority to very high */
26d67362 1538 prio = 7;
be147d08
JM		 1539 }
1540 break;
be147d08 1541#endif
c80f84e3
JM		 1542 default:
1543 /* nop */
1544 break;
1545 }
26d67362 1546 if (prio) {
a7812ae4 1547 TCGv t0 = tcg_temp_new();
54cdcae6 1548 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1549 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1550 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1551 gen_store_spr(SPR_PPR, t0);
ea363694 1552 tcg_temp_free(t0);
26d67362 1553 }
c80f84e3 1554#endif
9a64fbe4 1555 }
9a64fbe4 1556}
79aceca5 1557/* orc & orc. */
26d67362 1558GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1559/* xor & xor. */
9a64fbe4
FB		 1560GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1561{
9a64fbe4 1562 /* Optimisation for "set to zero" case */
26d67362 1563 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1564 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1565 else
1566 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1567 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1568 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1569}
79aceca5
FB		 1570/* ori */
1571GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1572{
76a66253 1573 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1574
9a64fbe4
FB		 1575 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1576 /* NOP */
76a66253 1577 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1578 return;
76a66253 1579 }
26d67362 1580 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1581}
1582/* oris */
1583GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1584{
76a66253 1585 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1586
9a64fbe4
FB		 1587 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1588 /* NOP */
1589 return;
76a66253 1590 }
26d67362 1591 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1592}
1593/* xori */
1594GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1595{
76a66253 1596 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1597
1598 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1599 /* NOP */
1600 return;
1601 }
26d67362 1602 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1603}
79aceca5
FB		 1604/* xoris */
1605GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1606{
76a66253 1607 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1608
1609 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1610 /* NOP */
1611 return;
1612 }
26d67362 1613 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1614}
d9bce9d9 1615/* popcntb : PowerPC 2.03 specification */
05332d70 1616GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1617{
d9bce9d9
JM		 1618#if defined(TARGET_PPC64)
1619 if (ctx->sf_mode)
a7812ae4 1620 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1621 else
1622#endif
a7812ae4 1623 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1624}
1625
1626#if defined(TARGET_PPC64)
1627/* extsw & extsw. */
26d67362 1628GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1629/* cntlzd */
26d67362
AJ		 1630GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1631{
a7812ae4 1632 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1633 if (unlikely(Rc(ctx->opcode) != 0))
1634 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1635}
d9bce9d9
JM		 1636#endif
1637
79aceca5
FB		 1638/*** Integer rotate ***/
1639/* rlwimi & rlwimi. */
1640GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1641{
76a66253 1642 uint32_t mb, me, sh;
79aceca5
FB		 1643
1644 mb = MB(ctx->opcode);
1645 me = ME(ctx->opcode);
76a66253 1646 sh = SH(ctx->opcode);
d03ef511
AJ		 1647 if (likely(sh == 0 && mb == 0 && me == 31)) {
1648 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1649 } else {
d03ef511 1650 target_ulong mask;
a7812ae4
PB		 1651 TCGv t1;
1652 TCGv t0 = tcg_temp_new();
54843a58 1653#if defined(TARGET_PPC64)
a7812ae4
PB		 1654 TCGv_i32 t2 = tcg_temp_new_i32();
1655 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1656 tcg_gen_rotli_i32(t2, t2, sh);
1657 tcg_gen_extu_i32_i64(t0, t2);
1658 tcg_temp_free_i32(t2);
54843a58
AJ		 1659#else
1660 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1661#endif
76a66253 1662#if defined(TARGET_PPC64)
d03ef511
AJ		 1663 mb += 32;
1664 me += 32;
76a66253 1665#endif
d03ef511 1666 mask = MASK(mb, me);
a7812ae4 1667 t1 = tcg_temp_new();
d03ef511
AJ		 1668 tcg_gen_andi_tl(t0, t0, mask);
1669 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1670 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1671 tcg_temp_free(t0);
1672 tcg_temp_free(t1);
1673 }
76a66253 1674 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1675 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1676}
1677/* rlwinm & rlwinm. */
1678GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1679{
1680 uint32_t mb, me, sh;
3b46e624 1681
79aceca5
FB		 1682 sh = SH(ctx->opcode);
1683 mb = MB(ctx->opcode);
1684 me = ME(ctx->opcode);
d03ef511
AJ		 1685
1686 if (likely(mb == 0 && me == (31 - sh))) {
1687 if (likely(sh == 0)) {
1688 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1689 } else {
a7812ae4 1690 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1691 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1692 tcg_gen_shli_tl(t0, t0, sh);
1693 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1694 tcg_temp_free(t0);
79aceca5 1695 }
d03ef511 1696 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1697 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1698 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1699 tcg_gen_shri_tl(t0, t0, mb);
1700 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1701 tcg_temp_free(t0);
1702 } else {
a7812ae4 1703 TCGv t0 = tcg_temp_new();
54843a58 1704#if defined(TARGET_PPC64)
a7812ae4 1705 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1706 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1707 tcg_gen_rotli_i32(t1, t1, sh);
1708 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1709 tcg_temp_free_i32(t1);
54843a58
AJ		 1710#else
1711 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1712#endif
76a66253 1713#if defined(TARGET_PPC64)
d03ef511
AJ		 1714 mb += 32;
1715 me += 32;
76a66253 1716#endif
d03ef511
AJ		 1717 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1718 tcg_temp_free(t0);
1719 }
76a66253 1720 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1721 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1722}
1723/* rlwnm & rlwnm. */
1724GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1725{
1726 uint32_t mb, me;
54843a58
AJ		 1727 TCGv t0;
1728#if defined(TARGET_PPC64)
a7812ae4 1729 TCGv_i32 t1, t2;
54843a58 1730#endif
79aceca5
FB		 1731
1732 mb = MB(ctx->opcode);
1733 me = ME(ctx->opcode);
a7812ae4 1734 t0 = tcg_temp_new();
d03ef511 1735 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1736#if defined(TARGET_PPC64)
a7812ae4
PB		 1737 t1 = tcg_temp_new_i32();
1738 t2 = tcg_temp_new_i32();
54843a58
AJ		 1739 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1740 tcg_gen_trunc_i64_i32(t2, t0);
1741 tcg_gen_rotl_i32(t1, t1, t2);
1742 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1743 tcg_temp_free_i32(t1);
1744 tcg_temp_free_i32(t2);
54843a58
AJ		 1745#else
1746 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1747#endif
76a66253
JM		 1748 if (unlikely(mb != 0 || me != 31)) {
1749#if defined(TARGET_PPC64)
1750 mb += 32;
1751 me += 32;
1752#endif
54843a58 1753 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1754 } else {
54843a58 1755 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1756 }
54843a58 1757 tcg_temp_free(t0);
76a66253 1758 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1759 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1760}
1761
d9bce9d9
JM		 1762#if defined(TARGET_PPC64)
1763#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1764GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1765{ \
1766 gen_##name(ctx, 0); \
1767} \
c7697e1f
JM		 1768GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1769 PPC_64B) \
d9bce9d9
JM		 1770{ \
1771 gen_##name(ctx, 1); \
1772}
1773#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1774GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1775{ \
1776 gen_##name(ctx, 0, 0); \
1777} \
c7697e1f
JM		 1778GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1779 PPC_64B) \
d9bce9d9
JM		 1780{ \
1781 gen_##name(ctx, 0, 1); \
1782} \
c7697e1f
JM		 1783GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1784 PPC_64B) \
d9bce9d9
JM		 1785{ \
1786 gen_##name(ctx, 1, 0); \
1787} \
c7697e1f
JM		 1788GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1789 PPC_64B) \
d9bce9d9
JM		 1790{ \
1791 gen_##name(ctx, 1, 1); \
1792}
51789c41 1793
b068d6a7
JM		 1794static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1795 uint32_t me, uint32_t sh)
51789c41 1796{
d03ef511
AJ		 1797 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1798 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1799 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1800 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1801 } else {
a7812ae4 1802 TCGv t0 = tcg_temp_new();
54843a58 1803 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1804 if (likely(mb == 0 && me == 63)) {
54843a58 1805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1806 } else {
1807 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1808 }
d03ef511 1809 tcg_temp_free(t0);
51789c41 1810 }
51789c41 1811 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1812 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1813}
d9bce9d9 1814/* rldicl - rldicl. */
b068d6a7 1815static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1816{
51789c41 1817 uint32_t sh, mb;
d9bce9d9 1818
9d53c753
JM		 1819 sh = SH(ctx->opcode) | (shn << 5);
1820 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1821 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1822}
51789c41 1823GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1824/* rldicr - rldicr. */
b068d6a7 1825static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1826{
51789c41 1827 uint32_t sh, me;
d9bce9d9 1828
9d53c753
JM		 1829 sh = SH(ctx->opcode) | (shn << 5);
1830 me = MB(ctx->opcode) | (men << 5);
51789c41 1831 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1832}
51789c41 1833GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1834/* rldic - rldic. */
b068d6a7 1835static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1836{
51789c41 1837 uint32_t sh, mb;
d9bce9d9 1838
9d53c753
JM		 1839 sh = SH(ctx->opcode) | (shn << 5);
1840 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1841 gen_rldinm(ctx, mb, 63 - sh, sh);
1842}
1843GEN_PPC64_R4(rldic, 0x1E, 0x04);
1844
b068d6a7
JM		 1845static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1846 uint32_t me)
51789c41 1847{
54843a58 1848 TCGv t0;
d03ef511
AJ		 1849
1850 mb = MB(ctx->opcode);
1851 me = ME(ctx->opcode);
a7812ae4 1852 t0 = tcg_temp_new();
d03ef511 1853 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1854 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1855 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1856 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1857 } else {
1858 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1859 }
1860 tcg_temp_free(t0);
51789c41 1861 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1862 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1863}
51789c41 1864
d9bce9d9 1865/* rldcl - rldcl. */
b068d6a7 1866static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1867{
51789c41 1868 uint32_t mb;
d9bce9d9 1869
9d53c753 1870 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1871 gen_rldnm(ctx, mb, 63);
d9bce9d9 1872}
36081602 1873GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1874/* rldcr - rldcr. */
b068d6a7 1875static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1876{
51789c41 1877 uint32_t me;
d9bce9d9 1878
9d53c753 1879 me = MB(ctx->opcode) | (men << 5);
51789c41 1880 gen_rldnm(ctx, 0, me);
d9bce9d9 1881}
36081602 1882GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1883/* rldimi - rldimi. */
b068d6a7 1884static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1885{
271a916e 1886 uint32_t sh, mb, me;
d9bce9d9 1887
9d53c753
JM		 1888 sh = SH(ctx->opcode) | (shn << 5);
1889 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1890 me = 63 - sh;
d03ef511
AJ		 1891 if (unlikely(sh == 0 && mb == 0)) {
1892 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1893 } else {
1894 TCGv t0, t1;
1895 target_ulong mask;
1896
a7812ae4 1897 t0 = tcg_temp_new();
54843a58 1898 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1899 t1 = tcg_temp_new();
d03ef511
AJ		 1900 mask = MASK(mb, me);
1901 tcg_gen_andi_tl(t0, t0, mask);
1902 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1903 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1904 tcg_temp_free(t0);
1905 tcg_temp_free(t1);
51789c41 1906 }
51789c41 1907 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1909}
36081602 1910GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1911#endif
1912
79aceca5
FB		 1913/*** Integer shift ***/
1914/* slw & slw. */
26d67362
AJ		 1915GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1916{
fea0c503 1917 TCGv t0;
26d67362
AJ		 1918 int l1, l2;
1919 l1 = gen_new_label();
1920 l2 = gen_new_label();
1921
a7812ae4 1922 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1923 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1924 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1925 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1926 tcg_gen_br(l2);
1927 gen_set_label(l1);
fea0c503 1928 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1929 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1930 gen_set_label(l2);
fea0c503 1931 tcg_temp_free(t0);
26d67362
AJ		 1932 if (unlikely(Rc(ctx->opcode) != 0))
1933 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1934}
79aceca5 1935/* sraw & sraw. */
26d67362
AJ		 1936GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1937{
a7812ae4
PB		 1938 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1939 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1940 if (unlikely(Rc(ctx->opcode) != 0))
1941 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1942}
79aceca5
FB		 1943/* srawi & srawi. */
1944GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1945{
26d67362
AJ		 1946 int sh = SH(ctx->opcode);
1947 if (sh != 0) {
1948 int l1, l2;
fea0c503 1949 TCGv t0;
26d67362
AJ		 1950 l1 = gen_new_label();
1951 l2 = gen_new_label();
a7812ae4 1952 t0 = tcg_temp_local_new();
fea0c503
AJ		 1953 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1954 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1955 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1956 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1957 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1958 tcg_gen_br(l2);
1959 gen_set_label(l1);
269f3e95 1960 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1961 gen_set_label(l2);
fea0c503
AJ		 1962 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1963 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1964 tcg_temp_free(t0);
26d67362
AJ		 1965 } else {
1966 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1967 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1968 }
76a66253 1969 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1971}
1972/* srw & srw. */
26d67362
AJ		 1973GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1974{
fea0c503 1975 TCGv t0, t1;
26d67362
AJ		 1976 int l1, l2;
1977 l1 = gen_new_label();
1978 l2 = gen_new_label();
d9bce9d9 1979
a7812ae4 1980 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1981 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1982 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1983 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1984 tcg_gen_br(l2);
1985 gen_set_label(l1);
a7812ae4 1986 t1 = tcg_temp_new();
fea0c503
AJ		 1987 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1988 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1989 tcg_temp_free(t1);
26d67362 1990 gen_set_label(l2);
fea0c503 1991 tcg_temp_free(t0);
26d67362
AJ		 1992 if (unlikely(Rc(ctx->opcode) != 0))
1993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1994}
d9bce9d9
JM		 1995#if defined(TARGET_PPC64)
1996/* sld & sld. */
26d67362
AJ		 1997GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1998{
fea0c503 1999 TCGv t0;
26d67362
AJ		 2000 int l1, l2;
2001 l1 = gen_new_label();
2002 l2 = gen_new_label();
2003
a7812ae4 2004 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2005 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2006 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2007 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2008 tcg_gen_br(l2);
2009 gen_set_label(l1);
fea0c503 2010 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2011 gen_set_label(l2);
fea0c503 2012 tcg_temp_free(t0);
26d67362
AJ		 2013 if (unlikely(Rc(ctx->opcode) != 0))
2014 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2015}
d9bce9d9 2016/* srad & srad. */
26d67362
AJ		 2017GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2018{
a7812ae4
PB		 2019 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2020 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2021 if (unlikely(Rc(ctx->opcode) != 0))
2022 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2023}
d9bce9d9 2024/* sradi & sradi. */
b068d6a7 2025static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2026{
26d67362 2027 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2028 if (sh != 0) {
26d67362 2029 int l1, l2;
fea0c503 2030 TCGv t0;
26d67362
AJ		 2031 l1 = gen_new_label();
2032 l2 = gen_new_label();
a7812ae4 2033 t0 = tcg_temp_local_new();
26d67362 2034 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2035 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2036 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2037 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2038 tcg_gen_br(l2);
2039 gen_set_label(l1);
269f3e95 2040 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2041 gen_set_label(l2);
a9730017 2042 tcg_temp_free(t0);
26d67362
AJ		 2043 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2044 } else {
2045 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2046 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2047 }
d9bce9d9 2048 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2049 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2050}
c7697e1f 2051GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2052{
2053 gen_sradi(ctx, 0);
2054}
c7697e1f 2055GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2056{
2057 gen_sradi(ctx, 1);
2058}
2059/* srd & srd. */
26d67362
AJ		 2060GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2061{
fea0c503 2062 TCGv t0;
26d67362
AJ		 2063 int l1, l2;
2064 l1 = gen_new_label();
2065 l2 = gen_new_label();
2066
a7812ae4 2067 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2068 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2069 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2070 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2071 tcg_gen_br(l2);
2072 gen_set_label(l1);
fea0c503 2073 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2074 gen_set_label(l2);
fea0c503 2075 tcg_temp_free(t0);
26d67362
AJ		 2076 if (unlikely(Rc(ctx->opcode) != 0))
2077 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2078}
d9bce9d9 2079#endif
79aceca5
FB		 2080
2081/*** Floating-Point arithmetic ***/
7c58044c 2082#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2083GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2084{ \
76a66253 2085 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2086 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2087 return; \
2088 } \
eb44b959
AJ		 2089 /* NIP cannot be restored if the memory exception comes from an helper */ \
2090 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2091 gen_reset_fpstatus(); \
af12906f
AJ		 2092 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2093 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2094 if (isfloat) { \
af12906f 2095 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2096 } \
af12906f
AJ		 2097 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2098 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2099}
2100
7c58044c
JM		 2101#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2102_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2103_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2104
7c58044c
JM		 2105#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2106GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2107{ \
76a66253 2108 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2109 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2110 return; \
2111 } \
eb44b959
AJ		 2112 /* NIP cannot be restored if the memory exception comes from an helper */ \
2113 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2114 gen_reset_fpstatus(); \
af12906f
AJ		 2115 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2116 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2117 if (isfloat) { \
af12906f 2118 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2119 } \
af12906f
AJ		 2120 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2121 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2122}
7c58044c
JM		 2123#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2124_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2125_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2126
7c58044c
JM		 2127#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2128GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2129{ \
76a66253 2130 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2131 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2132 return; \
2133 } \
eb44b959
AJ		 2134 /* NIP cannot be restored if the memory exception comes from an helper */ \
2135 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2136 gen_reset_fpstatus(); \
af12906f
AJ		 2137 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2138 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2139 if (isfloat) { \
af12906f 2140 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2141 } \
af12906f
AJ		 2142 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2143 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2144}
7c58044c
JM		 2145#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2146_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2147_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2148
7c58044c 2149#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2150GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2151{ \
76a66253 2152 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2153 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2154 return; \
2155 } \
eb44b959
AJ		 2156 /* NIP cannot be restored if the memory exception comes from an helper */ \
2157 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2158 gen_reset_fpstatus(); \
af12906f
AJ		 2159 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2160 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2161 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2162}
2163
7c58044c 2164#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2165GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2166{ \
76a66253 2167 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2168 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2169 return; \
2170 } \
eb44b959
AJ		 2171 /* NIP cannot be restored if the memory exception comes from an helper */ \
2172 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2173 gen_reset_fpstatus(); \
af12906f
AJ		 2174 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2175 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2176 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2177}
2178
9a64fbe4 2179/* fadd - fadds */
7c58044c 2180GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2181/* fdiv - fdivs */
7c58044c 2182GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2183/* fmul - fmuls */
7c58044c 2184GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2185
d7e4b87e 2186/* fre */
7c58044c 2187GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2188
a750fc0b 2189/* fres */
7c58044c 2190GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2191
a750fc0b 2192/* frsqrte */
7c58044c
JM		 2193GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2194
2195/* frsqrtes */
af12906f 2196GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2197{
af12906f 2198 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2199 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2200 return;
2201 }
eb44b959
AJ		 2202 /* NIP cannot be restored if the memory exception comes from an helper */
2203 gen_update_nip(ctx, ctx->nip - 4);
af12906f
AJ		 2204 gen_reset_fpstatus();
2205 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2206 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2207 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2208}
79aceca5 2209
a750fc0b 2210/* fsel */
7c58044c 2211_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2212/* fsub - fsubs */
7c58044c 2213GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2214/* Optional: */
2215/* fsqrt */
a750fc0b 2216GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2217{
76a66253 2218 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2219 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2220 return;
2221 }
eb44b959
AJ		 2222 /* NIP cannot be restored if the memory exception comes from an helper */
2223 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2224 gen_reset_fpstatus();
af12906f
AJ		 2225 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2226 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2227}
79aceca5 2228
a750fc0b 2229GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2230{
76a66253 2231 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2232 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2233 return;
2234 }
eb44b959
AJ		 2235 /* NIP cannot be restored if the memory exception comes from an helper */
2236 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2237 gen_reset_fpstatus();
af12906f
AJ		 2238 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2239 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2240 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2241}
2242
2243/*** Floating-Point multiply-and-add ***/
4ecc3190 2244/* fmadd - fmadds */
7c58044c 2245GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2246/* fmsub - fmsubs */
7c58044c 2247GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2248/* fnmadd - fnmadds */
7c58044c 2249GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2250/* fnmsub - fnmsubs */
7c58044c 2251GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2252
2253/*** Floating-Point round & convert ***/
2254/* fctiw */
7c58044c 2255GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2256/* fctiwz */
7c58044c 2257GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2258/* frsp */
7c58044c 2259GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2260#if defined(TARGET_PPC64)
2261/* fcfid */
7c58044c 2262GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2263/* fctid */
7c58044c 2264GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2265/* fctidz */
7c58044c 2266GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2267#endif
79aceca5 2268
d7e4b87e 2269/* frin */
7c58044c 2270GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2271/* friz */
7c58044c 2272GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2273/* frip */
7c58044c 2274GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2275/* frim */
7c58044c 2276GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2277
79aceca5
FB		 2278/*** Floating-Point compare ***/
2279/* fcmpo */
76a66253 2280GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2281{
330c483b 2282 TCGv_i32 crf;
76a66253 2283 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2284 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2285 return;
2286 }
eb44b959
AJ		 2287 /* NIP cannot be restored if the memory exception comes from an helper */
2288 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2289 gen_reset_fpstatus();
9a819377
AJ		 2290 crf = tcg_const_i32(crfD(ctx->opcode));
2291 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2292 tcg_temp_free_i32(crf);
af12906f 2293 gen_helper_float_check_status();
79aceca5
FB		 2294}
2295
2296/* fcmpu */
76a66253 2297GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2298{
330c483b 2299 TCGv_i32 crf;
76a66253 2300 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2301 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2302 return;
2303 }
eb44b959
AJ		 2304 /* NIP cannot be restored if the memory exception comes from an helper */
2305 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2306 gen_reset_fpstatus();
9a819377
AJ		 2307 crf = tcg_const_i32(crfD(ctx->opcode));
2308 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2309 tcg_temp_free_i32(crf);
af12906f 2310 gen_helper_float_check_status();
79aceca5
FB		 2311}
2312
9a64fbe4
FB		 2313/*** Floating-point move ***/
2314/* fabs */
7c58044c
JM		 2315/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2316GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2317
2318/* fmr - fmr. */
7c58044c 2319/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2320GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2321{
76a66253 2322 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2323 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2324 return;
2325 }
af12906f
AJ		 2326 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2327 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2328}
2329
2330/* fnabs */
7c58044c
JM		 2331/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2332GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2333/* fneg */
7c58044c
JM		 2334/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2335GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2336
79aceca5
FB		 2337/*** Floating-Point status & ctrl register ***/
2338/* mcrfs */
2339GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2340{
7c58044c
JM		 2341 int bfa;
2342
76a66253 2343 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2344 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2345 return;
2346 }
7c58044c 2347 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2348 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2349 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2350 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2351}
2352
2353/* mffs */
2354GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2355{
76a66253 2356 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2357 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2358 return;
2359 }
7c58044c 2360 gen_reset_fpstatus();
af12906f
AJ		 2361 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2362 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2363}
2364
2365/* mtfsb0 */
2366GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2367{
fb0eaffc 2368 uint8_t crb;
3b46e624 2369
76a66253 2370 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2371 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2372 return;
2373 }
6e35d524 2374 crb = 31 - crbD(ctx->opcode);
7c58044c 2375 gen_reset_fpstatus();
6e35d524 2376 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2377 TCGv_i32 t0;
2378 /* NIP cannot be restored if the memory exception comes from an helper */
2379 gen_update_nip(ctx, ctx->nip - 4);
2380 t0 = tcg_const_i32(crb);
6e35d524
AJ		 2381 gen_helper_fpscr_clrbit(t0);
2382 tcg_temp_free_i32(t0);
2383 }
7c58044c 2384 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2385 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2386 }
79aceca5
FB		 2387}
2388
2389/* mtfsb1 */
2390GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2391{
fb0eaffc 2392 uint8_t crb;
3b46e624 2393
76a66253 2394 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2395 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2396 return;
2397 }
6e35d524 2398 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2399 gen_reset_fpstatus();
2400 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2401 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2402 TCGv_i32 t0;
2403 /* NIP cannot be restored if the memory exception comes from an helper */
2404 gen_update_nip(ctx, ctx->nip - 4);
2405 t0 = tcg_const_i32(crb);
af12906f 2406 gen_helper_fpscr_setbit(t0);
0f2f39c2 2407 tcg_temp_free_i32(t0);
af12906f 2408 }
7c58044c 2409 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2410 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2411 }
2412 /* We can raise a differed exception */
af12906f 2413 gen_helper_float_check_status();
79aceca5
FB		 2414}
2415
2416/* mtfsf */
2417GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2418{
0f2f39c2 2419 TCGv_i32 t0;
af12906f 2420
76a66253 2421 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2422 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2423 return;
2424 }
eb44b959
AJ		 2425 /* NIP cannot be restored if the memory exception comes from an helper */
2426 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2427 gen_reset_fpstatus();
af12906f
AJ		 2428 t0 = tcg_const_i32(FM(ctx->opcode));
2429 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2430 tcg_temp_free_i32(t0);
7c58044c 2431 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2432 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2433 }
2434 /* We can raise a differed exception */
af12906f 2435 gen_helper_float_check_status();
79aceca5
FB		 2436}
2437
2438/* mtfsfi */
2439GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2440{
7c58044c 2441 int bf, sh;
0f2f39c2
AJ		 2442 TCGv_i64 t0;
2443 TCGv_i32 t1;
7c58044c 2444
76a66253 2445 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2446 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2447 return;
2448 }
7c58044c
JM		 2449 bf = crbD(ctx->opcode) >> 2;
2450 sh = 7 - bf;
eb44b959
AJ		 2451 /* NIP cannot be restored if the memory exception comes from an helper */
2452 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2453 gen_reset_fpstatus();
0f2f39c2 2454 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2455 t1 = tcg_const_i32(1 << sh);
2456 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2457 tcg_temp_free_i64(t0);
2458 tcg_temp_free_i32(t1);
7c58044c 2459 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2460 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2461 }
2462 /* We can raise a differed exception */
af12906f 2463 gen_helper_float_check_status();
79aceca5
FB		 2464}
2465
76a66253
JM		 2466/*** Addressing modes ***/
2467/* Register indirect with immediate index : EA = (rA|0) + SIMM */
76db3ba4 2468static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
76a66253
JM		 2469{
2470 target_long simm = SIMM(ctx->opcode);
2471
be147d08 2472 simm &= ~maskl;
76db3ba4
AJ		 2473 if (rA(ctx->opcode) == 0) {
2474#if defined(TARGET_PPC64)
2475 if (!ctx->sf_mode) {
2476 tcg_gen_movi_tl(EA, (uint32_t)simm);
2477 } else
2478#endif
e2be8d8d 2479 tcg_gen_movi_tl(EA, simm);
76db3ba4 2480 } else if (likely(simm != 0)) {
e2be8d8d 2481 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
76db3ba4
AJ		 2482#if defined(TARGET_PPC64)
2483 if (!ctx->sf_mode) {
2484 tcg_gen_ext32u_tl(EA, EA);
2485 }
2486#endif
2487 } else {
2488#if defined(TARGET_PPC64)
2489 if (!ctx->sf_mode) {
2490 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2491 } else
2492#endif
e2be8d8d 2493 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2494 }
76a66253
JM		 2495}
2496
76db3ba4 2497static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
76a66253 2498{
76db3ba4
AJ		 2499 if (rA(ctx->opcode) == 0) {
2500#if defined(TARGET_PPC64)
2501 if (!ctx->sf_mode) {
2502 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2503 } else
2504#endif
e2be8d8d 2505 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
76db3ba4 2506 } else {
e2be8d8d 2507 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76db3ba4
AJ		 2508#if defined(TARGET_PPC64)
2509 if (!ctx->sf_mode) {
2510 tcg_gen_ext32u_tl(EA, EA);
2511 }
2512#endif
2513 }
76a66253
JM		 2514}
2515
76db3ba4 2516static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
76a66253 2517{
76db3ba4 2518 if (rA(ctx->opcode) == 0) {
e2be8d8d 2519 tcg_gen_movi_tl(EA, 0);
76db3ba4
AJ		 2520 } else {
2521#if defined(TARGET_PPC64)
2522 if (!ctx->sf_mode) {
2523 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2524 } else
2525#endif
2526 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2527 }
2528}
2529
2530static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2531{
2532 tcg_gen_addi_tl(ret, arg1, val);
2533#if defined(TARGET_PPC64)
2534 if (!ctx->sf_mode) {
2535 tcg_gen_ext32u_tl(ret, ret);
2536 }
2537#endif
76a66253
JM		 2538}
2539
cf360a32
AJ		 2540static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2541{
2542 int l1 = gen_new_label();
2543 TCGv t0 = tcg_temp_new();
2544 TCGv_i32 t1, t2;
2545 /* NIP cannot be restored if the memory exception comes from an helper */
2546 gen_update_nip(ctx, ctx->nip - 4);
2547 tcg_gen_andi_tl(t0, EA, mask);
2548 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2549 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2550 t2 = tcg_const_i32(0);
2551 gen_helper_raise_exception_err(t1, t2);
2552 tcg_temp_free_i32(t1);
2553 tcg_temp_free_i32(t2);
2554 gen_set_label(l1);
2555 tcg_temp_free(t0);
2556}
2557
7863667f 2558/*** Integer load ***/
76db3ba4
AJ		 2559static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2560{
2561 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2562}
2563
2564static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2565{
2566 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2567}
2568
2569static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2570{
2571 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2572 if (unlikely(ctx->le_mode)) {
b61f2753 2573#if defined(TARGET_PPC64)
76db3ba4
AJ		 2574 TCGv_i32 t0 = tcg_temp_new_i32();
2575 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2576 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2577 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2578 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2579#else
2580 tcg_gen_bswap16_i32(arg1, arg1);
2581#endif
2582 }
b61f2753
AJ		 2583}
2584
76db3ba4 2585static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2586{
76db3ba4
AJ		 2587 if (unlikely(ctx->le_mode)) {
2588#if defined(TARGET_PPC64)
a7812ae4 2589 TCGv_i32 t0;
76db3ba4 2590 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
a7812ae4 2591 t0 = tcg_temp_new_i32();
76db3ba4 2592 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2593 tcg_gen_bswap16_i32(t0, t0);
76db3ba4
AJ		 2594 tcg_gen_extu_i32_tl(arg1, t0);
2595 tcg_gen_ext16s_tl(arg1, arg1);
a7812ae4 2596 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2597#else
2598 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2599 tcg_gen_bswap16_i32(arg1, arg1);
2600 tcg_gen_ext16s_i32(arg1, arg1);
2601#endif
2602 } else {
2603 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2604 }
b61f2753
AJ		 2605}
2606
76db3ba4 2607static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2608{
76db3ba4
AJ		 2609 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2610 if (unlikely(ctx->le_mode)) {
2611#if defined(TARGET_PPC64)
2612 TCGv_i32 t0 = tcg_temp_new_i32();
2613 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2614 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2615 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2616 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2617#else
2618 tcg_gen_bswap_i32(arg1, arg1);
2619#endif
2620 }
b61f2753
AJ		 2621}
2622
76db3ba4
AJ		 2623#if defined(TARGET_PPC64)
2624static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2625{
76db3ba4 2626 if (unlikely(ctx->mem_idx)) {
a7812ae4 2627 TCGv_i32 t0;
76db3ba4 2628 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
a7812ae4 2629 t0 = tcg_temp_new_i32();
76db3ba4 2630 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2631 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2632 tcg_gen_ext_i32_tl(arg1, t0);
a7812ae4 2633 tcg_temp_free_i32(t0);
b61f2753 2634 } else
76db3ba4 2635 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753 2636}
76db3ba4 2637#endif
b61f2753 2638
76db3ba4 2639static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2640{
76db3ba4
AJ		 2641 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2642 if (unlikely(ctx->le_mode)) {
2643 tcg_gen_bswap_i64(arg1, arg1);
2644 }
b61f2753
AJ		 2645}
2646
76db3ba4 2647static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2648{
76db3ba4 2649 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2650}
2651
76db3ba4 2652static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2653{
76db3ba4
AJ		 2654 if (unlikely(ctx->le_mode)) {
2655#if defined(TARGET_PPC64)
a7812ae4 2656 TCGv_i32 t0;
76db3ba4 2657 TCGv t1;
a7812ae4 2658 t0 = tcg_temp_new_i32();
76db3ba4 2659 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694
AJ		 2660 tcg_gen_ext16u_i32(t0, t0);
2661 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2662 t1 = tcg_temp_new();
ea363694 2663 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2664 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2665 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2666 tcg_temp_free(t1);
2667#else
2668 TCGv t0 = tcg_temp_new();
2669 tcg_gen_ext16u_tl(t0, arg1);
2670 tcg_gen_bswap16_i32(t0, t0);
2671 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2672 tcg_temp_free(t0);
2673#endif
2674 } else {
2675 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2676 }
b61f2753
AJ		 2677}
2678
76db3ba4 2679static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2680{
76db3ba4
AJ		 2681 if (unlikely(ctx->le_mode)) {
2682#if defined(TARGET_PPC64)
a7812ae4 2683 TCGv_i32 t0;
76db3ba4 2684 TCGv t1;
a7812ae4 2685 t0 = tcg_temp_new_i32();
76db3ba4 2686 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2687 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2688 t1 = tcg_temp_new();
ea363694 2689 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2690 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2691 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2692 tcg_temp_free(t1);
2693#else
2694 TCGv t0 = tcg_temp_new_i32();
2695 tcg_gen_bswap_i32(t0, arg1);
2696 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2697 tcg_temp_free(t0);
2698#endif
2699 } else {
2700 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2701 }
b61f2753
AJ		 2702}
2703
76db3ba4 2704static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2705{
76db3ba4 2706 if (unlikely(ctx->le_mode)) {
a7812ae4 2707 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4
AJ		 2708 tcg_gen_bswap_i64(t0, arg1);
2709 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2710 tcg_temp_free_i64(t0);
b61f2753 2711 } else
76db3ba4 2712 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2713}
2714
0c8aacd4
AJ		 2715#define GEN_LD(name, ldop, opc, type) \
2716GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2717{ \
76db3ba4
AJ		 2718 TCGv EA; \
2719 gen_set_access_type(ctx, ACCESS_INT); \
2720 EA = tcg_temp_new(); \
2721 gen_addr_imm_index(ctx, EA, 0); \
2722 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2723 tcg_temp_free(EA); \
79aceca5
FB		 2724}
2725
0c8aacd4
AJ		 2726#define GEN_LDU(name, ldop, opc, type) \
2727GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2728{ \
b61f2753 2729 TCGv EA; \
76a66253
JM		 2730 if (unlikely(rA(ctx->opcode) == 0 || \
2731 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2732 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2733 return; \
9a64fbe4 2734 } \
76db3ba4 2735 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2736 EA = tcg_temp_new(); \
9d53c753 2737 if (type == PPC_64B) \
76db3ba4 2738 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2739 else \
76db3ba4
AJ		 2740 gen_addr_imm_index(ctx, EA, 0); \
2741 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2742 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2743 tcg_temp_free(EA); \
79aceca5
FB		 2744}
2745
0c8aacd4
AJ		 2746#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2747GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2748{ \
b61f2753 2749 TCGv EA; \
76a66253
JM		 2750 if (unlikely(rA(ctx->opcode) == 0 || \
2751 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2752 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2753 return; \
9a64fbe4 2754 } \
76db3ba4 2755 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2756 EA = tcg_temp_new(); \
76db3ba4
AJ		 2757 gen_addr_reg_index(ctx, EA); \
2758 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2760 tcg_temp_free(EA); \
79aceca5
FB		 2761}
2762
0c8aacd4
AJ		 2763#define GEN_LDX(name, ldop, opc2, opc3, type) \
2764GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2765{ \
76db3ba4
AJ		 2766 TCGv EA; \
2767 gen_set_access_type(ctx, ACCESS_INT); \
2768 EA = tcg_temp_new(); \
2769 gen_addr_reg_index(ctx, EA); \
2770 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2771 tcg_temp_free(EA); \
79aceca5
FB		 2772}
2773
0c8aacd4
AJ		 2774#define GEN_LDS(name, ldop, op, type) \
2775GEN_LD(name, ldop, op | 0x20, type); \
2776GEN_LDU(name, ldop, op | 0x21, type); \
2777GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2778GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2779
2780/* lbz lbzu lbzux lbzx */
0c8aacd4 2781GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2782/* lha lhau lhaux lhax */
0c8aacd4 2783GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2784/* lhz lhzu lhzux lhzx */
0c8aacd4 2785GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2786/* lwz lwzu lwzux lwzx */
0c8aacd4 2787GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2788#if defined(TARGET_PPC64)
d9bce9d9 2789/* lwaux */
0c8aacd4 2790GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2791/* lwax */
0c8aacd4 2792GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2793/* ldux */
0c8aacd4 2794GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2795/* ldx */
0c8aacd4 2796GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2797GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2798{
b61f2753 2799 TCGv EA;
d9bce9d9
JM		 2800 if (Rc(ctx->opcode)) {
2801 if (unlikely(rA(ctx->opcode) == 0 ||
2802 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2803 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2804 return;
2805 }
2806 }
76db3ba4 2807 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2808 EA = tcg_temp_new();
76db3ba4 2809 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2810 if (ctx->opcode & 0x02) {
2811 /* lwa (lwau is undefined) */
76db3ba4 2812 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2813 } else {
2814 /* ld - ldu */
76db3ba4 2815 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2816 }
d9bce9d9 2817 if (Rc(ctx->opcode))
b61f2753
AJ		 2818 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2819 tcg_temp_free(EA);
d9bce9d9 2820}
be147d08
JM		 2821/* lq */
2822GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2823{
2824#if defined(CONFIG_USER_ONLY)
e06fcd75 2825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2826#else
2827 int ra, rd;
b61f2753 2828 TCGv EA;
be147d08
JM		 2829
2830 /* Restore CPU state */
76db3ba4 2831 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2833 return;
2834 }
2835 ra = rA(ctx->opcode);
2836 rd = rD(ctx->opcode);
2837 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2838 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2839 return;
2840 }
76db3ba4 2841 if (unlikely(ctx->le_mode)) {
be147d08 2842 /* Little-endian mode is not handled */
e06fcd75 2843 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2844 return;
2845 }
76db3ba4 2846 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2847 EA = tcg_temp_new();
76db3ba4
AJ		 2848 gen_addr_imm_index(ctx, EA, 0x0F);
2849 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2850 gen_addr_add(ctx, EA, EA, 8);
2851 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
b61f2753 2852 tcg_temp_free(EA);
be147d08
JM		 2853#endif
2854}
d9bce9d9 2855#endif
79aceca5
FB		 2856
2857/*** Integer store ***/
0c8aacd4
AJ		 2858#define GEN_ST(name, stop, opc, type) \
2859GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2860{ \
76db3ba4
AJ		 2861 TCGv EA; \
2862 gen_set_access_type(ctx, ACCESS_INT); \
2863 EA = tcg_temp_new(); \
2864 gen_addr_imm_index(ctx, EA, 0); \
2865 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2866 tcg_temp_free(EA); \
79aceca5
FB		 2867}
2868
0c8aacd4
AJ		 2869#define GEN_STU(name, stop, opc, type) \
2870GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2871{ \
b61f2753 2872 TCGv EA; \
76a66253 2873 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2874 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2875 return; \
9a64fbe4 2876 } \
76db3ba4 2877 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2878 EA = tcg_temp_new(); \
9d53c753 2879 if (type == PPC_64B) \
76db3ba4 2880 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2881 else \
76db3ba4
AJ		 2882 gen_addr_imm_index(ctx, EA, 0); \
2883 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2884 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2885 tcg_temp_free(EA); \
79aceca5
FB		 2886}
2887
0c8aacd4
AJ		 2888#define GEN_STUX(name, stop, opc2, opc3, type) \
2889GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2890{ \
b61f2753 2891 TCGv EA; \
76a66253 2892 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2893 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2894 return; \
9a64fbe4 2895 } \
76db3ba4 2896 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2897 EA = tcg_temp_new(); \
76db3ba4
AJ		 2898 gen_addr_reg_index(ctx, EA); \
2899 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2900 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2901 tcg_temp_free(EA); \
79aceca5
FB		 2902}
2903
0c8aacd4
AJ		 2904#define GEN_STX(name, stop, opc2, opc3, type) \
2905GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2906{ \
76db3ba4
AJ		 2907 TCGv EA; \
2908 gen_set_access_type(ctx, ACCESS_INT); \
2909 EA = tcg_temp_new(); \
2910 gen_addr_reg_index(ctx, EA); \
2911 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2912 tcg_temp_free(EA); \
79aceca5
FB		 2913}
2914
0c8aacd4
AJ		 2915#define GEN_STS(name, stop, op, type) \
2916GEN_ST(name, stop, op | 0x20, type); \
2917GEN_STU(name, stop, op | 0x21, type); \
2918GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2919GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2920
2921/* stb stbu stbux stbx */
0c8aacd4 2922GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2923/* sth sthu sthux sthx */
0c8aacd4 2924GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2925/* stw stwu stwux stwx */
0c8aacd4 2926GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2927#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2928GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2929GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2930GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2931{
be147d08 2932 int rs;
b61f2753 2933 TCGv EA;
be147d08
JM		 2934
2935 rs = rS(ctx->opcode);
2936 if ((ctx->opcode & 0x3) == 0x2) {
2937#if defined(CONFIG_USER_ONLY)
e06fcd75 2938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2939#else
2940 /* stq */
76db3ba4 2941 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2942 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2943 return;
2944 }
2945 if (unlikely(rs & 1)) {
e06fcd75 2946 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2947 return;
2948 }
76db3ba4 2949 if (unlikely(ctx->le_mode)) {
be147d08 2950 /* Little-endian mode is not handled */
e06fcd75 2951 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2952 return;
2953 }
76db3ba4 2954 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2955 EA = tcg_temp_new();
76db3ba4
AJ		 2956 gen_addr_imm_index(ctx, EA, 0x03);
2957 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2958 gen_addr_add(ctx, EA, EA, 8);
2959 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
b61f2753 2960 tcg_temp_free(EA);
be147d08
JM		 2961#endif
2962 } else {
2963 /* std / stdu */
2964 if (Rc(ctx->opcode)) {
2965 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2966 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2967 return;
2968 }
2969 }
76db3ba4 2970 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2971 EA = tcg_temp_new();
76db3ba4
AJ		 2972 gen_addr_imm_index(ctx, EA, 0x03);
2973 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 2974 if (Rc(ctx->opcode))
b61f2753
AJ		 2975 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2976 tcg_temp_free(EA);
d9bce9d9 2977 }
d9bce9d9
JM		 2978}
2979#endif
79aceca5
FB		 2980/*** Integer load and store with byte reverse ***/
2981/* lhbrx */
76db3ba4 2982static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2983{
76db3ba4
AJ		 2984 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2985 if (likely(!ctx->le_mode)) {
2986#if defined(TARGET_PPC64)
2987 TCGv_i32 t0 = tcg_temp_new_i32();
2988 tcg_gen_trunc_tl_i32(t0, arg1);
2989 tcg_gen_bswap16_i32(t0, t0);
2990 tcg_gen_extu_i32_tl(arg1, t0);
2991 tcg_temp_free_i32(t0);
2992#else
2993 tcg_gen_bswap16_i32(arg1, arg1);
2994#endif
2995 }
b61f2753 2996}
0c8aacd4 2997GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 2998
79aceca5 2999/* lwbrx */
76db3ba4 3000static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3001{
76db3ba4
AJ		 3002 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3003 if (likely(!ctx->le_mode)) {
3004#if defined(TARGET_PPC64)
3005 TCGv_i32 t0 = tcg_temp_new_i32();
3006 tcg_gen_trunc_tl_i32(t0, arg1);
3007 tcg_gen_bswap_i32(t0, t0);
3008 tcg_gen_extu_i32_tl(arg1, t0);
3009 tcg_temp_free_i32(t0);
3010#else
3011 tcg_gen_bswap_i32(arg1, arg1);
3012#endif
3013 }
b61f2753 3014}
0c8aacd4 3015GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3016
79aceca5 3017/* sthbrx */
76db3ba4 3018static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3019{
76db3ba4
AJ		 3020 if (likely(!ctx->le_mode)) {
3021#if defined(TARGET_PPC64)
3022 TCGv_i32 t0;
3023 TCGv t1;
3024 t0 = tcg_temp_new_i32();
3025 tcg_gen_trunc_tl_i32(t0, arg1);
3026 tcg_gen_ext16u_i32(t0, t0);
3027 tcg_gen_bswap16_i32(t0, t0);
3028 t1 = tcg_temp_new();
3029 tcg_gen_extu_i32_tl(t1, t0);
3030 tcg_temp_free_i32(t0);
3031 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3032 tcg_temp_free(t1);
3033#else
3034 TCGv t0 = tcg_temp_new();
3035 tcg_gen_ext16u_tl(t0, arg1);
3036 tcg_gen_bswap16_i32(t0, t0);
3037 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3038 tcg_temp_free(t0);
3039#endif
3040 } else {
3041 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3042 }
b61f2753 3043}
0c8aacd4 3044GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3045
79aceca5 3046/* stwbrx */
76db3ba4 3047static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3048{
76db3ba4
AJ		 3049 if (likely(!ctx->le_mode)) {
3050#if defined(TARGET_PPC64)
3051 TCGv_i32 t0;
3052 TCGv t1;
3053 t0 = tcg_temp_new_i32();
3054 tcg_gen_trunc_tl_i32(t0, arg1);
3055 tcg_gen_bswap_i32(t0, t0);
3056 t1 = tcg_temp_new();
3057 tcg_gen_extu_i32_tl(t1, t0);
3058 tcg_temp_free_i32(t0);
3059 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3060 tcg_temp_free(t1);
3061#else
3062 TCGv t0 = tcg_temp_new_i32();
3063 tcg_gen_bswap_i32(t0, arg1);
3064 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3065 tcg_temp_free(t0);
3066#endif
3067 } else {
3068 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3069 }
b61f2753 3070}
0c8aacd4 3071GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3072
3073/*** Integer load and store multiple ***/
3074/* lmw */
3075GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3076{
76db3ba4
AJ		 3077 TCGv t0;
3078 TCGv_i32 t1;
3079 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3080 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3081 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3082 t0 = tcg_temp_new();
3083 t1 = tcg_const_i32(rD(ctx->opcode));
3084 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3085 gen_helper_lmw(t0, t1);
3086 tcg_temp_free(t0);
3087 tcg_temp_free_i32(t1);
79aceca5
FB		 3088}
3089
3090/* stmw */
3091GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3092{
76db3ba4
AJ		 3093 TCGv t0;
3094 TCGv_i32 t1;
3095 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3096 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3097 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3098 t0 = tcg_temp_new();
3099 t1 = tcg_const_i32(rS(ctx->opcode));
3100 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3101 gen_helper_stmw(t0, t1);
3102 tcg_temp_free(t0);
3103 tcg_temp_free_i32(t1);
79aceca5
FB		 3104}
3105
3106/*** Integer load and store strings ***/
3107/* lswi */
3fc6c082 3108/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3109 * rA is in the range of registers to be loaded.
3110 * In an other hand, IBM says this is valid, but rA won't be loaded.
3111 * For now, I'll follow the spec...
3112 */
05332d70 3113GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3114{
dfbc799d
AJ		 3115 TCGv t0;
3116 TCGv_i32 t1, t2;
79aceca5
FB		 3117 int nb = NB(ctx->opcode);
3118 int start = rD(ctx->opcode);
9a64fbe4 3119 int ra = rA(ctx->opcode);
79aceca5
FB		 3120 int nr;
3121
3122 if (nb == 0)
3123 nb = 32;
3124 nr = nb / 4;
76a66253
JM		 3125 if (unlikely(((start + nr) > 32 &&
3126 start <= ra && (start + nr - 32) > ra) ||
3127 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3128 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3129 return;
297d8e62 3130 }
76db3ba4 3131 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3132 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3133 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3134 t0 = tcg_temp_new();
76db3ba4 3135 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3136 t1 = tcg_const_i32(nb);
3137 t2 = tcg_const_i32(start);
3138 gen_helper_lsw(t0, t1, t2);
3139 tcg_temp_free(t0);
3140 tcg_temp_free_i32(t1);
3141 tcg_temp_free_i32(t2);
79aceca5
FB		 3142}
3143
3144/* lswx */
05332d70 3145GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3146{
76db3ba4
AJ		 3147 TCGv t0;
3148 TCGv_i32 t1, t2, t3;
3149 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3150 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3151 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3152 t0 = tcg_temp_new();
3153 gen_addr_reg_index(ctx, t0);
3154 t1 = tcg_const_i32(rD(ctx->opcode));
3155 t2 = tcg_const_i32(rA(ctx->opcode));
3156 t3 = tcg_const_i32(rB(ctx->opcode));
dfbc799d
AJ		 3157 gen_helper_lswx(t0, t1, t2, t3);
3158 tcg_temp_free(t0);
3159 tcg_temp_free_i32(t1);
3160 tcg_temp_free_i32(t2);
3161 tcg_temp_free_i32(t3);
79aceca5
FB		 3162}
3163
3164/* stswi */
05332d70 3165GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3166{
76db3ba4
AJ		 3167 TCGv t0;
3168 TCGv_i32 t1, t2;
4b3686fa 3169 int nb = NB(ctx->opcode);
76db3ba4 3170 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3171 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3172 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3173 t0 = tcg_temp_new();
3174 gen_addr_register(ctx, t0);
4b3686fa
FB		 3175 if (nb == 0)
3176 nb = 32;
dfbc799d 3177 t1 = tcg_const_i32(nb);
76db3ba4 3178 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3179 gen_helper_stsw(t0, t1, t2);
3180 tcg_temp_free(t0);
3181 tcg_temp_free_i32(t1);
3182 tcg_temp_free_i32(t2);
79aceca5
FB		 3183}
3184
3185/* stswx */
05332d70 3186GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3187{
76db3ba4
AJ		 3188 TCGv t0;
3189 TCGv_i32 t1, t2;
3190 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3191 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3192 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3193 t0 = tcg_temp_new();
3194 gen_addr_reg_index(ctx, t0);
3195 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3196 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3197 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3198 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3199 gen_helper_stsw(t0, t1, t2);
3200 tcg_temp_free(t0);
3201 tcg_temp_free_i32(t1);
3202 tcg_temp_free_i32(t2);
79aceca5
FB		 3203}
3204
3205/*** Memory synchronisation ***/
3206/* eieio */
0db1b20e 3207GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3208{
79aceca5
FB		 3209}
3210
3211/* isync */
0db1b20e 3212GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3213{
e06fcd75 3214 gen_stop_exception(ctx);
79aceca5
FB		 3215}
3216
111bfab3 3217/* lwarx */
76a66253 3218GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3219{
76db3ba4
AJ		 3220 TCGv t0;
3221 gen_set_access_type(ctx, ACCESS_RES);
3222 t0 = tcg_temp_local_new();
3223 gen_addr_reg_index(ctx, t0);
cf360a32 3224 gen_check_align(ctx, t0, 0x03);
76db3ba4 3225 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3226 tcg_gen_mov_tl(cpu_reserve, t0);
3227 tcg_temp_free(t0);
79aceca5
FB		 3228}
3229
3230/* stwcx. */
c7697e1f 3231GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3232{
76db3ba4
AJ		 3233 int l1;
3234 TCGv t0;
3235 gen_set_access_type(ctx, ACCESS_RES);
3236 t0 = tcg_temp_local_new();
3237 gen_addr_reg_index(ctx, t0);
cf360a32 3238 gen_check_align(ctx, t0, 0x03);
cf360a32
AJ		 3239 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3240 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3241 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3242 l1 = gen_new_label();
cf360a32
AJ		 3243 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3244 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3245 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3246 gen_set_label(l1);
3247 tcg_gen_movi_tl(cpu_reserve, -1);
3248 tcg_temp_free(t0);
79aceca5
FB		 3249}
3250
426613db 3251#if defined(TARGET_PPC64)
426613db 3252/* ldarx */
a750fc0b 3253GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3254{
76db3ba4
AJ		 3255 TCGv t0;
3256 gen_set_access_type(ctx, ACCESS_RES);
3257 t0 = tcg_temp_local_new();
3258 gen_addr_reg_index(ctx, t0);
cf360a32 3259 gen_check_align(ctx, t0, 0x07);
76db3ba4 3260 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3261 tcg_gen_mov_tl(cpu_reserve, t0);
3262 tcg_temp_free(t0);
426613db
JM		 3263}
3264
3265/* stdcx. */
c7697e1f 3266GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3267{
76db3ba4
AJ		 3268 int l1;
3269 TCGv t0;
3270 gen_set_access_type(ctx, ACCESS_RES);
3271 t0 = tcg_temp_local_new();
3272 gen_addr_reg_index(ctx, t0);
cf360a32 3273 gen_check_align(ctx, t0, 0x07);
cf360a32
AJ		 3274 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3275 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3276 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3277 l1 = gen_new_label();
cf360a32
AJ		 3278 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3279 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3280 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3281 gen_set_label(l1);
3282 tcg_gen_movi_tl(cpu_reserve, -1);
3283 tcg_temp_free(t0);
426613db
JM		 3284}
3285#endif /* defined(TARGET_PPC64) */
3286
79aceca5 3287/* sync */
a902d886 3288GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3289{
79aceca5
FB		 3290}
3291
0db1b20e
JM		 3292/* wait */
3293GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3294{
931ff272
AJ		 3295 TCGv_i32 t0 = tcg_temp_new_i32();
3296 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3297 tcg_temp_free_i32(t0);
0db1b20e 3298 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3299 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3300}
3301
79aceca5 3302/*** Floating-point load ***/
a0d7d5a7
AJ		 3303#define GEN_LDF(name, ldop, opc, type) \
3304GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3305{ \
a0d7d5a7 3306 TCGv EA; \
76a66253 3307 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3308 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3309 return; \
3310 } \
76db3ba4 3311 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3312 EA = tcg_temp_new(); \
76db3ba4
AJ		 3313 gen_addr_imm_index(ctx, EA, 0); \
3314 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3315 tcg_temp_free(EA); \
79aceca5
FB		 3316}
3317
a0d7d5a7
AJ		 3318#define GEN_LDUF(name, ldop, opc, type) \
3319GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3320{ \
a0d7d5a7 3321 TCGv EA; \
76a66253 3322 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3323 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3324 return; \
3325 } \
76a66253 3326 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3327 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3328 return; \
9a64fbe4 3329 } \
76db3ba4 3330 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3331 EA = tcg_temp_new(); \
76db3ba4
AJ		 3332 gen_addr_imm_index(ctx, EA, 0); \
3333 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3334 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3335 tcg_temp_free(EA); \
79aceca5
FB		 3336}
3337
a0d7d5a7
AJ		 3338#define GEN_LDUXF(name, ldop, opc, type) \
3339GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3340{ \
a0d7d5a7 3341 TCGv EA; \
76a66253 3342 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3343 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3344 return; \
3345 } \
76a66253 3346 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3347 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3348 return; \
9a64fbe4 3349 } \
76db3ba4 3350 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3351 EA = tcg_temp_new(); \
76db3ba4
AJ		 3352 gen_addr_reg_index(ctx, EA); \
3353 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3354 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3355 tcg_temp_free(EA); \
79aceca5
FB		 3356}
3357
a0d7d5a7
AJ		 3358#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3359GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3360{ \
a0d7d5a7 3361 TCGv EA; \
76a66253 3362 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3363 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3364 return; \
3365 } \
76db3ba4 3366 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3367 EA = tcg_temp_new(); \
76db3ba4
AJ		 3368 gen_addr_reg_index(ctx, EA); \
3369 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3370 tcg_temp_free(EA); \
79aceca5
FB		 3371}
3372
a0d7d5a7
AJ		 3373#define GEN_LDFS(name, ldop, op, type) \
3374GEN_LDF(name, ldop, op | 0x20, type); \
3375GEN_LDUF(name, ldop, op | 0x21, type); \
3376GEN_LDUXF(name, ldop, op | 0x01, type); \
3377GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3378
76db3ba4 3379static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3380{
3381 TCGv t0 = tcg_temp_new();
3382 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3383 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3384 tcg_gen_trunc_tl_i32(t1, t0);
3385 tcg_temp_free(t0);
3386 gen_helper_float32_to_float64(arg1, t1);
3387 tcg_temp_free_i32(t1);
3388}
79aceca5 3389
a0d7d5a7
AJ		 3390 /* lfd lfdu lfdux lfdx */
3391GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3392 /* lfs lfsu lfsux lfsx */
3393GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3394
3395/*** Floating-point store ***/
a0d7d5a7
AJ		 3396#define GEN_STF(name, stop, opc, type) \
3397GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3398{ \
a0d7d5a7 3399 TCGv EA; \
76a66253 3400 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3401 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3402 return; \
3403 } \
76db3ba4 3404 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3405 EA = tcg_temp_new(); \
76db3ba4
AJ		 3406 gen_addr_imm_index(ctx, EA, 0); \
3407 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3408 tcg_temp_free(EA); \
79aceca5
FB		 3409}
3410
a0d7d5a7
AJ		 3411#define GEN_STUF(name, stop, opc, type) \
3412GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3413{ \
a0d7d5a7 3414 TCGv EA; \
76a66253 3415 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3416 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3417 return; \
3418 } \
76a66253 3419 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3420 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3421 return; \
9a64fbe4 3422 } \
76db3ba4 3423 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3424 EA = tcg_temp_new(); \
76db3ba4
AJ		 3425 gen_addr_imm_index(ctx, EA, 0); \
3426 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3427 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3428 tcg_temp_free(EA); \
79aceca5
FB		 3429}
3430
a0d7d5a7
AJ		 3431#define GEN_STUXF(name, stop, opc, type) \
3432GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3433{ \
a0d7d5a7 3434 TCGv EA; \
76a66253 3435 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3436 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3437 return; \
3438 } \
76a66253 3439 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3440 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3441 return; \
9a64fbe4 3442 } \
76db3ba4 3443 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3444 EA = tcg_temp_new(); \
76db3ba4
AJ		 3445 gen_addr_reg_index(ctx, EA); \
3446 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3447 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3448 tcg_temp_free(EA); \
79aceca5
FB		 3449}
3450
a0d7d5a7
AJ		 3451#define GEN_STXF(name, stop, opc2, opc3, type) \
3452GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3453{ \
a0d7d5a7 3454 TCGv EA; \
76a66253 3455 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3456 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3457 return; \
3458 } \
76db3ba4 3459 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3460 EA = tcg_temp_new(); \
76db3ba4
AJ		 3461 gen_addr_reg_index(ctx, EA); \
3462 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3463 tcg_temp_free(EA); \
79aceca5
FB		 3464}
3465
a0d7d5a7
AJ		 3466#define GEN_STFS(name, stop, op, type) \
3467GEN_STF(name, stop, op | 0x20, type); \
3468GEN_STUF(name, stop, op | 0x21, type); \
3469GEN_STUXF(name, stop, op | 0x01, type); \
3470GEN_STXF(name, stop, 0x17, op | 0x00, type)
3471
76db3ba4 3472static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3473{
3474 TCGv_i32 t0 = tcg_temp_new_i32();
3475 TCGv t1 = tcg_temp_new();
3476 gen_helper_float64_to_float32(t0, arg1);
3477 tcg_gen_extu_i32_tl(t1, t0);
3478 tcg_temp_free_i32(t0);
76db3ba4 3479 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3480 tcg_temp_free(t1);
3481}
79aceca5
FB		 3482
3483/* stfd stfdu stfdux stfdx */
a0d7d5a7 3484GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3485/* stfs stfsu stfsux stfsx */
a0d7d5a7 3486GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3487
3488/* Optional: */
76db3ba4 3489static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3490{
3491 TCGv t0 = tcg_temp_new();
3492 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3493 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3494 tcg_temp_free(t0);
3495}
79aceca5 3496/* stfiwx */
a0d7d5a7 3497GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3498
3499/*** Branch ***/
b068d6a7
JM		 3500static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3501 target_ulong dest)
c1942362
FB		 3502{
3503 TranslationBlock *tb;
3504 tb = ctx->tb;
a2ffb812
AJ		 3505#if defined(TARGET_PPC64)
3506 if (!ctx->sf_mode)
3507 dest = (uint32_t) dest;
3508#endif
57fec1fe 3509 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3510 likely(!ctx->singlestep_enabled)) {
57fec1fe 3511 tcg_gen_goto_tb(n);
a2ffb812 3512 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3513 tcg_gen_exit_tb((long)tb + n);
c1942362 3514 } else {
a2ffb812 3515 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3516 if (unlikely(ctx->singlestep_enabled)) {
3517 if ((ctx->singlestep_enabled &
bdc4e053 3518 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3519 ctx->exception == POWERPC_EXCP_BRANCH) {
3520 target_ulong tmp = ctx->nip;
3521 ctx->nip = dest;
e06fcd75 3522 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3523 ctx->nip = tmp;
3524 }
3525 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3526 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3527 }
3528 }
57fec1fe 3529 tcg_gen_exit_tb(0);
c1942362 3530 }
c53be334
FB		 3531}
3532
b068d6a7 3533static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3534{
3535#if defined(TARGET_PPC64)
a2ffb812
AJ		 3536 if (ctx->sf_mode == 0)
3537 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3538 else
3539#endif
a2ffb812 3540 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3541}
3542
79aceca5
FB		 3543/* b ba bl bla */
3544GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3545{
76a66253 3546 target_ulong li, target;
38a64f9d 3547
8cbcb4fa 3548 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3549 /* sign extend LI */
76a66253 3550#if defined(TARGET_PPC64)
d9bce9d9
JM		 3551 if (ctx->sf_mode)
3552 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3553 else
76a66253 3554#endif
d9bce9d9 3555 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3556 if (likely(AA(ctx->opcode) == 0))
046d6672 3557 target = ctx->nip + li - 4;
79aceca5 3558 else
9a64fbe4 3559 target = li;
e1833e1f
JM		 3560 if (LK(ctx->opcode))
3561 gen_setlr(ctx, ctx->nip);
c1942362 3562 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3563}
3564
e98a6e40
FB		 3565#define BCOND_IM 0
3566#define BCOND_LR 1
3567#define BCOND_CTR 2
3568
b068d6a7 3569static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3570{
d9bce9d9 3571 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3572 int l1 = gen_new_label();
3573 TCGv target;
e98a6e40 3574
8cbcb4fa 3575 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3576 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3577 target = tcg_temp_local_new();
a2ffb812
AJ		 3578 if (type == BCOND_CTR)
3579 tcg_gen_mov_tl(target, cpu_ctr);
3580 else
3581 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3582 }
e1833e1f
JM		 3583 if (LK(ctx->opcode))
3584 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3585 l1 = gen_new_label();
3586 if ((bo & 0x4) == 0) {
3587 /* Decrement and test CTR */
a7812ae4 3588 TCGv temp = tcg_temp_new();
a2ffb812 3589 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3590 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3591 return;
3592 }
3593 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3594#if defined(TARGET_PPC64)
a2ffb812
AJ		 3595 if (!ctx->sf_mode)
3596 tcg_gen_ext32u_tl(temp, cpu_ctr);
3597 else
d9bce9d9 3598#endif
a2ffb812
AJ		 3599 tcg_gen_mov_tl(temp, cpu_ctr);
3600 if (bo & 0x2) {
3601 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3602 } else {
3603 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3604 }
a7812ae4 3605 tcg_temp_free(temp);
a2ffb812
AJ		 3606 }
3607 if ((bo & 0x10) == 0) {
3608 /* Test CR */
3609 uint32_t bi = BI(ctx->opcode);
3610 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3611 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3612
d9bce9d9 3613 if (bo & 0x8) {
a2ffb812
AJ		 3614 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3615 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3616 } else {
a2ffb812
AJ		 3617 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3618 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3619 }
a7812ae4 3620 tcg_temp_free_i32(temp);
d9bce9d9 3621 }
e98a6e40 3622 if (type == BCOND_IM) {
a2ffb812
AJ		 3623 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3624 if (likely(AA(ctx->opcode) == 0)) {
3625 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3626 } else {
3627 gen_goto_tb(ctx, 0, li);
3628 }
c53be334 3629 gen_set_label(l1);
c1942362 3630 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3631 } else {
d9bce9d9 3632#if defined(TARGET_PPC64)
a2ffb812
AJ		 3633 if (!(ctx->sf_mode))
3634 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3635 else
3636#endif
3637 tcg_gen_andi_tl(cpu_nip, target, ~3);
3638 tcg_gen_exit_tb(0);
3639 gen_set_label(l1);
3640#if defined(TARGET_PPC64)
3641 if (!(ctx->sf_mode))
3642 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3643 else
3644#endif
a2ffb812 3645 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3646 tcg_gen_exit_tb(0);
08e46e54 3647 }
e98a6e40
FB		 3648}
3649
3650GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3651{
e98a6e40
FB		 3652 gen_bcond(ctx, BCOND_IM);
3653}
3654
3655GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3656{
e98a6e40
FB		 3657 gen_bcond(ctx, BCOND_CTR);
3658}
3659
3660GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3661{
e98a6e40
FB		 3662 gen_bcond(ctx, BCOND_LR);
3663}
79aceca5
FB		 3664
3665/*** Condition register logical ***/
e1571908
AJ		 3666#define GEN_CRLOGIC(name, tcg_op, opc) \
3667GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3668{ \
fc0d441e
JM		 3669 uint8_t bitmask; \
3670 int sh; \
a7812ae4 3671 TCGv_i32 t0, t1; \
fc0d441e 3672 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3673 t0 = tcg_temp_new_i32(); \
fc0d441e 3674 if (sh > 0) \
fea0c503 3675 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3676 else if (sh < 0) \
fea0c503 3677 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3678 else \
fea0c503 3679 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3680 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3681 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3682 if (sh > 0) \
fea0c503 3683 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3684 else if (sh < 0) \
fea0c503 3685 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3686 else \
fea0c503
AJ		 3687 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3688 tcg_op(t0, t0, t1); \
fc0d441e 3689 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3690 tcg_gen_andi_i32(t0, t0, bitmask); \
3691 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3692 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3693 tcg_temp_free_i32(t0); \
3694 tcg_temp_free_i32(t1); \
79aceca5
FB		 3695}
3696
3697/* crand */
e1571908 3698GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3699/* crandc */
e1571908 3700GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3701/* creqv */
e1571908 3702GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3703/* crnand */
e1571908 3704GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3705/* crnor */
e1571908 3706GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3707/* cror */
e1571908 3708GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3709/* crorc */
e1571908 3710GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3711/* crxor */
e1571908 3712GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3713/* mcrf */
3714GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3715{
47e4661c 3716 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3717}
3718
3719/*** System linkage ***/
76db3ba4 3720/* rfi (mem_idx only) */
76a66253 3721GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3722{
9a64fbe4 3723#if defined(CONFIG_USER_ONLY)
e06fcd75 3724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 3725#else
3726 /* Restore CPU state */
76db3ba4 3727 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 3729 return;
9a64fbe4 3730 }
d72a19f7 3731 gen_helper_rfi();
e06fcd75 3732 gen_sync_exception(ctx);
9a64fbe4 3733#endif
79aceca5
FB		 3734}
3735
426613db 3736#if defined(TARGET_PPC64)
a750fc0b 3737GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3738{
3739#if defined(CONFIG_USER_ONLY)
e06fcd75 3740 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3741#else
3742 /* Restore CPU state */
76db3ba4 3743 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3745 return;
3746 }
d72a19f7 3747 gen_helper_rfid();
e06fcd75 3748 gen_sync_exception(ctx);
426613db
JM		 3749#endif
3750}
426613db 3751
5b8105fa 3752GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3753{
3754#if defined(CONFIG_USER_ONLY)
e06fcd75 3755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3756#else
3757 /* Restore CPU state */
76db3ba4 3758 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 3759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3760 return;
3761 }
d72a19f7 3762 gen_helper_hrfid();
e06fcd75 3763 gen_sync_exception(ctx);
be147d08
JM		 3764#endif
3765}
3766#endif
3767
79aceca5 3768/* sc */
417bf010
JM		 3769#if defined(CONFIG_USER_ONLY)
3770#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3771#else
3772#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3773#endif
e1833e1f 3774GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3775{
e1833e1f
JM		 3776 uint32_t lev;
3777
3778 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3779 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3780}
3781
3782/*** Trap ***/
3783/* tw */
76a66253 3784GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3785{
cab3bee2 3786 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3787 /* Update the nip since this might generate a trap exception */
d9bce9d9 3788 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3789 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3790 tcg_temp_free_i32(t0);
79aceca5
FB		 3791}
3792
3793/* twi */
3794GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3795{
cab3bee2
AJ		 3796 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3797 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3798 /* Update the nip since this might generate a trap exception */
3799 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3800 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3801 tcg_temp_free(t0);
3802 tcg_temp_free_i32(t1);
79aceca5
FB		 3803}
3804
d9bce9d9
JM		 3805#if defined(TARGET_PPC64)
3806/* td */
3807GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3808{
cab3bee2 3809 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3810 /* Update the nip since this might generate a trap exception */
3811 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3812 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3813 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3814}
3815
3816/* tdi */
3817GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3818{
cab3bee2
AJ		 3819 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3820 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3821 /* Update the nip since this might generate a trap exception */
3822 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3823 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3824 tcg_temp_free(t0);
3825 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3826}
3827#endif
3828
79aceca5 3829/*** Processor control ***/
79aceca5
FB		 3830/* mcrxr */
3831GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3832{
3d7b417e
AJ		 3833 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3834 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3835 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3836}
3837
3838/* mfcr */
76a66253 3839GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3840{
76a66253 3841 uint32_t crm, crn;
3b46e624 3842
76a66253
JM		 3843 if (likely(ctx->opcode & 0x00100000)) {
3844 crm = CRM(ctx->opcode);
3845 if (likely((crm ^ (crm - 1)) == 0)) {
3846 crn = ffs(crm);
e1571908 3847 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3848 }
d9bce9d9 3849 } else {
a7812ae4 3850 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3851 }
79aceca5
FB		 3852}
3853
3854/* mfmsr */
3855GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3856{
9a64fbe4 3857#if defined(CONFIG_USER_ONLY)
e06fcd75 3858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3859#else
76db3ba4 3860 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3862 return;
9a64fbe4 3863 }
6527f6ea 3864 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3865#endif
79aceca5
FB		 3866}
3867
a11b8151 3868#if 1
6f2d8978 3869#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3870#else
3871static void spr_noaccess (void *opaque, int sprn)
3872{
3873 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3874 printf("ERROR: try to access SPR %d !\n", sprn);
3875}
3876#define SPR_NOACCESS (&spr_noaccess)
3877#endif
3878
79aceca5 3879/* mfspr */
b068d6a7 3880static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3881{
45d827d2 3882 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3883 uint32_t sprn = SPR(ctx->opcode);
3884
3fc6c082 3885#if !defined(CONFIG_USER_ONLY)
76db3ba4 3886 if (ctx->mem_idx == 2)
be147d08 3887 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 3888 else if (ctx->mem_idx)
3fc6c082
FB		 3889 read_cb = ctx->spr_cb[sprn].oea_read;
3890 else
9a64fbe4 3891#endif
3fc6c082 3892 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3893 if (likely(read_cb != NULL)) {
3894 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3895 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3896 } else {
3897 /* Privilege exception */
9fceefa7
JM		 3898 /* This is a hack to avoid warnings when running Linux:
3899 * this OS breaks the PowerPC virtualisation model,
3900 * allowing userland application to read the PVR
3901 */
3902 if (sprn != SPR_PVR) {
3903 if (loglevel != 0) {
6b542af7 3904 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3905 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3906 }
077fc206
JM		 3907 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3908 sprn, sprn, ctx->nip);
f24e5695 3909 }
e06fcd75 3910 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3911 }
3fc6c082
FB		 3912 } else {
3913 /* Not defined */
4a057712 3914 if (loglevel != 0) {
077fc206
JM		 3915 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3916 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3917 }
077fc206
JM		 3918 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3919 sprn, sprn, ctx->nip);
e06fcd75 3920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3921 }
79aceca5
FB		 3922}
3923
3fc6c082 3924GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3925{
3fc6c082 3926 gen_op_mfspr(ctx);
76a66253 3927}
3fc6c082
FB		 3928
3929/* mftb */
a750fc0b 3930GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3931{
3932 gen_op_mfspr(ctx);
79aceca5
FB		 3933}
3934
3935/* mtcrf */
8dd4983c 3936GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3937{
76a66253 3938 uint32_t crm, crn;
3b46e624 3939
76a66253
JM		 3940 crm = CRM(ctx->opcode);
3941 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3942 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3943 crn = ffs(crm);
a7812ae4
PB		 3944 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3945 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3946 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3947 tcg_temp_free_i32(temp);
76a66253 3948 } else {
a7812ae4
PB		 3949 TCGv_i32 temp = tcg_const_i32(crm);
3950 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3951 tcg_temp_free_i32(temp);
76a66253 3952 }
79aceca5
FB		 3953}
3954
3955/* mtmsr */
426613db 3956#if defined(TARGET_PPC64)
be147d08 3957GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3958{
3959#if defined(CONFIG_USER_ONLY)
e06fcd75 3960 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 3961#else
76db3ba4 3962 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3963 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 3964 return;
3965 }
be147d08
JM		 3966 if (ctx->opcode & 0x00010000) {
3967 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3968 TCGv t0 = tcg_temp_new();
3969 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3970 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3971 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3972 tcg_temp_free(t0);
be147d08 3973 } else {
056b05f8
JM		 3974 /* XXX: we need to update nip before the store
3975 * if we enter power saving mode, we will exit the loop
3976 * directly from ppc_store_msr
3977 */
be147d08 3978 gen_update_nip(ctx, ctx->nip);
6527f6ea 3979 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3980 /* Must stop the translation as machine state (may have) changed */
3981 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3982 gen_stop_exception(ctx);
be147d08 3983 }
426613db
JM		 3984#endif
3985}
3986#endif
3987
79aceca5
FB		 3988GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3989{
9a64fbe4 3990#if defined(CONFIG_USER_ONLY)
e06fcd75 3991 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3992#else
76db3ba4 3993 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3994 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3995 return;
9a64fbe4 3996 }
be147d08
JM		 3997 if (ctx->opcode & 0x00010000) {
3998 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3999 TCGv t0 = tcg_temp_new();
4000 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4001 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4002 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4003 tcg_temp_free(t0);
be147d08 4004 } else {
056b05f8
JM		 4005 /* XXX: we need to update nip before the store
4006 * if we enter power saving mode, we will exit the loop
4007 * directly from ppc_store_msr
4008 */
be147d08 4009 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4010#if defined(TARGET_PPC64)
6527f6ea
AJ		 4011 if (!ctx->sf_mode) {
4012 TCGv t0 = tcg_temp_new();
4013 TCGv t1 = tcg_temp_new();
4014 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4015 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4016 tcg_gen_or_tl(t0, t0, t1);
4017 tcg_temp_free(t1);
4018 gen_helper_store_msr(t0);
4019 tcg_temp_free(t0);
4020 } else
d9bce9d9 4021#endif
6527f6ea 4022 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 4023 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4024 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4025 gen_stop_exception(ctx);
be147d08 4026 }
9a64fbe4 4027#endif
79aceca5
FB		 4028}
4029
4030/* mtspr */
4031GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4032{
45d827d2 4033 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4034 uint32_t sprn = SPR(ctx->opcode);
4035
3fc6c082 4036#if !defined(CONFIG_USER_ONLY)
76db3ba4 4037 if (ctx->mem_idx == 2)
be147d08 4038 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 4039 else if (ctx->mem_idx)
3fc6c082
FB		 4040 write_cb = ctx->spr_cb[sprn].oea_write;
4041 else
9a64fbe4 4042#endif
3fc6c082 4043 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4044 if (likely(write_cb != NULL)) {
4045 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4046 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4047 } else {
4048 /* Privilege exception */
4a057712 4049 if (loglevel != 0) {
077fc206
JM		 4050 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4051 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4052 }
077fc206
JM		 4053 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4054 sprn, sprn, ctx->nip);
e06fcd75 4055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4056 }
3fc6c082
FB		 4057 } else {
4058 /* Not defined */
4a057712 4059 if (loglevel != 0) {
077fc206
JM		 4060 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4061 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4062 }
077fc206
JM		 4063 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4064 sprn, sprn, ctx->nip);
e06fcd75 4065 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4066 }
79aceca5
FB		 4067}
4068
4069/*** Cache management ***/
79aceca5 4070/* dcbf */
0db1b20e 4071GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4072{
dac454af 4073 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4074 TCGv t0;
4075 gen_set_access_type(ctx, ACCESS_CACHE);
4076 t0 = tcg_temp_new();
4077 gen_addr_reg_index(ctx, t0);
4078 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4079 tcg_temp_free(t0);
79aceca5
FB		 4080}
4081
4082/* dcbi (Supervisor only) */
9a64fbe4 4083GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4084{
a541f297 4085#if defined(CONFIG_USER_ONLY)
e06fcd75 4086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4087#else
b61f2753 4088 TCGv EA, val;
76db3ba4 4089 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4091 return;
9a64fbe4 4092 }
a7812ae4 4093 EA = tcg_temp_new();
76db3ba4
AJ		 4094 gen_set_access_type(ctx, ACCESS_CACHE);
4095 gen_addr_reg_index(ctx, EA);
a7812ae4 4096 val = tcg_temp_new();
76a66253 4097 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4098 gen_qemu_ld8u(ctx, val, EA);
4099 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4100 tcg_temp_free(val);
4101 tcg_temp_free(EA);
a541f297 4102#endif
79aceca5
FB		 4103}
4104
4105/* dcdst */
9a64fbe4 4106GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4107{
76a66253 4108 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4109 TCGv t0;
4110 gen_set_access_type(ctx, ACCESS_CACHE);
4111 t0 = tcg_temp_new();
4112 gen_addr_reg_index(ctx, t0);
4113 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4114 tcg_temp_free(t0);
79aceca5
FB		 4115}
4116
4117/* dcbt */
0db1b20e 4118GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4119{
0db1b20e 4120 /* interpreted as no-op */
76a66253
JM		 4121 /* XXX: specification say this is treated as a load by the MMU
4122 * but does not generate any exception
4123 */
79aceca5
FB		 4124}
4125
4126/* dcbtst */
0db1b20e 4127GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4128{
0db1b20e 4129 /* interpreted as no-op */
76a66253
JM		 4130 /* XXX: specification say this is treated as a load by the MMU
4131 * but does not generate any exception
4132 */
79aceca5
FB		 4133}
4134
4135/* dcbz */
d63001d1 4136GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4137{
76db3ba4
AJ		 4138 TCGv t0;
4139 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4140 /* NIP cannot be restored if the memory exception comes from an helper */
4141 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4142 t0 = tcg_temp_new();
4143 gen_addr_reg_index(ctx, t0);
799a8c8d
AJ		 4144 gen_helper_dcbz(t0);
4145 tcg_temp_free(t0);
d63001d1
JM		 4146}
4147
c7697e1f 4148GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4149{
76db3ba4
AJ		 4150 TCGv t0;
4151 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4152 /* NIP cannot be restored if the memory exception comes from an helper */
4153 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4154 t0 = tcg_temp_new();
4155 gen_addr_reg_index(ctx, t0);
d63001d1 4156 if (ctx->opcode & 0x00200000)
799a8c8d 4157 gen_helper_dcbz(t0);
d63001d1 4158 else
799a8c8d
AJ		 4159 gen_helper_dcbz_970(t0);
4160 tcg_temp_free(t0);
79aceca5
FB		 4161}
4162
ae1c1a3d
AJ		 4163/* dst / dstt */
4164GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4165{
4166 if (rA(ctx->opcode) == 0) {
4167 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4168 } else {
4169 /* interpreted as no-op */
4170 }
4171}
4172
4173/* dstst /dststt */
4174GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4175{
4176 if (rA(ctx->opcode) == 0) {
4177 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4178 } else {
4179 /* interpreted as no-op */
4180 }
4181
4182}
4183
4184/* dss / dssall */
4185GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4186{
4187 /* interpreted as no-op */
4188}
4189
79aceca5 4190/* icbi */
1b413d55 4191GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4192{
76db3ba4
AJ		 4193 TCGv t0;
4194 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4195 /* NIP cannot be restored if the memory exception comes from an helper */
4196 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4197 t0 = tcg_temp_new();
4198 gen_addr_reg_index(ctx, t0);
37d269df
AJ		 4199 gen_helper_icbi(t0);
4200 tcg_temp_free(t0);
79aceca5
FB		 4201}
4202
4203/* Optional: */
4204/* dcba */
a750fc0b 4205GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4206{
0db1b20e
JM		 4207 /* interpreted as no-op */
4208 /* XXX: specification say this is treated as a store by the MMU
4209 * but does not generate any exception
4210 */
79aceca5
FB		 4211}
4212
4213/*** Segment register manipulation ***/
4214/* Supervisor only: */
4215/* mfsr */
4216GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4217{
9a64fbe4 4218#if defined(CONFIG_USER_ONLY)
e06fcd75 4219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4220#else
74d37793 4221 TCGv t0;
76db3ba4 4222 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4224 return;
9a64fbe4 4225 }
74d37793
AJ		 4226 t0 = tcg_const_tl(SR(ctx->opcode));
4227 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4228 tcg_temp_free(t0);
9a64fbe4 4229#endif
79aceca5
FB		 4230}
4231
4232/* mfsrin */
9a64fbe4 4233GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4234{
9a64fbe4 4235#if defined(CONFIG_USER_ONLY)
e06fcd75 4236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4237#else
74d37793 4238 TCGv t0;
76db3ba4 4239 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4241 return;
9a64fbe4 4242 }
74d37793
AJ		 4243 t0 = tcg_temp_new();
4244 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4245 tcg_gen_andi_tl(t0, t0, 0xF);
4246 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4247 tcg_temp_free(t0);
9a64fbe4 4248#endif
79aceca5
FB		 4249}
4250
4251/* mtsr */
e63c59cb 4252GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4253{
9a64fbe4 4254#if defined(CONFIG_USER_ONLY)
e06fcd75 4255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4256#else
74d37793 4257 TCGv t0;
76db3ba4 4258 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4260 return;
9a64fbe4 4261 }
74d37793
AJ		 4262 t0 = tcg_const_tl(SR(ctx->opcode));
4263 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4264 tcg_temp_free(t0);
9a64fbe4 4265#endif
79aceca5
FB		 4266}
4267
4268/* mtsrin */
9a64fbe4 4269GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4270{
9a64fbe4 4271#if defined(CONFIG_USER_ONLY)
e06fcd75 4272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4273#else
74d37793 4274 TCGv t0;
76db3ba4 4275 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4277 return;
9a64fbe4 4278 }
74d37793
AJ		 4279 t0 = tcg_temp_new();
4280 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4281 tcg_gen_andi_tl(t0, t0, 0xF);
4282 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4283 tcg_temp_free(t0);
9a64fbe4 4284#endif
79aceca5
FB		 4285}
4286
12de9a39
JM		 4287#if defined(TARGET_PPC64)
4288/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4289/* mfsr */
c7697e1f 4290GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4291{
4292#if defined(CONFIG_USER_ONLY)
e06fcd75 4293 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4294#else
74d37793 4295 TCGv t0;
76db3ba4 4296 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4297 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4298 return;
4299 }
74d37793
AJ		 4300 t0 = tcg_const_tl(SR(ctx->opcode));
4301 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4302 tcg_temp_free(t0);
12de9a39
JM		 4303#endif
4304}
4305
4306/* mfsrin */
c7697e1f
JM		 4307GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4308 PPC_SEGMENT_64B)
12de9a39
JM		 4309{
4310#if defined(CONFIG_USER_ONLY)
e06fcd75 4311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4312#else
74d37793 4313 TCGv t0;
76db3ba4 4314 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4316 return;
4317 }
74d37793
AJ		 4318 t0 = tcg_temp_new();
4319 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4320 tcg_gen_andi_tl(t0, t0, 0xF);
4321 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4322 tcg_temp_free(t0);
12de9a39
JM		 4323#endif
4324}
4325
4326/* mtsr */
c7697e1f 4327GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4328{
4329#if defined(CONFIG_USER_ONLY)
e06fcd75 4330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4331#else
74d37793 4332 TCGv t0;
76db3ba4 4333 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4334 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4335 return;
4336 }
74d37793
AJ		 4337 t0 = tcg_const_tl(SR(ctx->opcode));
4338 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4339 tcg_temp_free(t0);
12de9a39
JM		 4340#endif
4341}
4342
4343/* mtsrin */
c7697e1f
JM		 4344GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4345 PPC_SEGMENT_64B)
12de9a39
JM		 4346{
4347#if defined(CONFIG_USER_ONLY)
e06fcd75 4348 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4349#else
74d37793 4350 TCGv t0;
76db3ba4 4351 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4353 return;
4354 }
74d37793
AJ		 4355 t0 = tcg_temp_new();
4356 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4357 tcg_gen_andi_tl(t0, t0, 0xF);
4358 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4359 tcg_temp_free(t0);
12de9a39
JM		 4360#endif
4361}
4362#endif /* defined(TARGET_PPC64) */
4363
79aceca5 4364/*** Lookaside buffer management ***/
76db3ba4 4365/* Optional & mem_idx only: */
79aceca5 4366/* tlbia */
3fc6c082 4367GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4368{
9a64fbe4 4369#if defined(CONFIG_USER_ONLY)
e06fcd75 4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4371#else
76db3ba4 4372 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4374 return;
9a64fbe4 4375 }
74d37793 4376 gen_helper_tlbia();
9a64fbe4 4377#endif
79aceca5
FB		 4378}
4379
4380/* tlbie */
76a66253 4381GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4382{
9a64fbe4 4383#if defined(CONFIG_USER_ONLY)
e06fcd75 4384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4385#else
76db3ba4 4386 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4388 return;
9a64fbe4 4389 }
d9bce9d9 4390#if defined(TARGET_PPC64)
74d37793
AJ		 4391 if (!ctx->sf_mode) {
4392 TCGv t0 = tcg_temp_new();
4393 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4394 gen_helper_tlbie(t0);
4395 tcg_temp_free(t0);
4396 } else
d9bce9d9 4397#endif
74d37793 4398 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4399#endif
79aceca5
FB		 4400}
4401
4402/* tlbsync */
76a66253 4403GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4404{
9a64fbe4 4405#if defined(CONFIG_USER_ONLY)
e06fcd75 4406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4407#else
76db3ba4 4408 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4409 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4410 return;
9a64fbe4
FB		 4411 }
4412 /* This has no effect: it should ensure that all previous
4413 * tlbie have completed
4414 */
e06fcd75 4415 gen_stop_exception(ctx);
9a64fbe4 4416#endif
79aceca5
FB		 4417}
4418
426613db
JM		 4419#if defined(TARGET_PPC64)
4420/* slbia */
4421GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4422{
4423#if defined(CONFIG_USER_ONLY)
e06fcd75 4424 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4425#else
76db3ba4 4426 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4427 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4428 return;
4429 }
74d37793 4430 gen_helper_slbia();
426613db
JM		 4431#endif
4432}
4433
4434/* slbie */
4435GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4436{
4437#if defined(CONFIG_USER_ONLY)
e06fcd75 4438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4439#else
76db3ba4 4440 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4441 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4442 return;
4443 }
74d37793 4444 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4445#endif
4446}
4447#endif
4448
79aceca5
FB		 4449/*** External control ***/
4450/* Optional: */
111bfab3 4451/* eciwx */
79aceca5
FB		 4452GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4453{
76db3ba4 4454 TCGv t0;
fa407c03 4455 /* Should check EAR[E] ! */
76db3ba4
AJ		 4456 gen_set_access_type(ctx, ACCESS_EXT);
4457 t0 = tcg_temp_new();
4458 gen_addr_reg_index(ctx, t0);
fa407c03 4459 gen_check_align(ctx, t0, 0x03);
76db3ba4 4460 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4461 tcg_temp_free(t0);
76a66253
JM		 4462}
4463
4464/* ecowx */
4465GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4466{
76db3ba4 4467 TCGv t0;
fa407c03 4468 /* Should check EAR[E] ! */
76db3ba4
AJ		 4469 gen_set_access_type(ctx, ACCESS_EXT);
4470 t0 = tcg_temp_new();
4471 gen_addr_reg_index(ctx, t0);
fa407c03 4472 gen_check_align(ctx, t0, 0x03);
76db3ba4 4473 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4474 tcg_temp_free(t0);
76a66253
JM		 4475}
4476
4477/* PowerPC 601 specific instructions */
4478/* abs - abs. */
4479GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4480{
22e0e173
AJ		 4481 int l1 = gen_new_label();
4482 int l2 = gen_new_label();
4483 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4484 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4485 tcg_gen_br(l2);
4486 gen_set_label(l1);
4487 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4488 gen_set_label(l2);
76a66253 4489 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4490 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4491}
4492
4493/* abso - abso. */
4494GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4495{
22e0e173
AJ		 4496 int l1 = gen_new_label();
4497 int l2 = gen_new_label();
4498 int l3 = gen_new_label();
4499 /* Start with XER OV disabled, the most likely case */
4500 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4501 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4502 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4503 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4504 tcg_gen_br(l2);
4505 gen_set_label(l1);
4506 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4507 tcg_gen_br(l3);
4508 gen_set_label(l2);
4509 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4510 gen_set_label(l3);
76a66253 4511 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4512 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4513}
4514
4515/* clcs */
a750fc0b 4516GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4517{
22e0e173
AJ		 4518 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4519 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4520 tcg_temp_free_i32(t0);
c7697e1f 4521 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4522}
4523
4524/* div - div. */
4525GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4526{
22e0e173 4527 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4528 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4529 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4530}
4531
4532/* divo - divo. */
4533GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4534{
22e0e173 4535 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4536 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4537 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4538}
4539
4540/* divs - divs. */
4541GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4542{
22e0e173 4543 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4544 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4545 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4546}
4547
4548/* divso - divso. */
4549GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4550{
22e0e173 4551 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4552 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4553 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4554}
4555
4556/* doz - doz. */
4557GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4558{
22e0e173
AJ		 4559 int l1 = gen_new_label();
4560 int l2 = gen_new_label();
4561 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4562 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4563 tcg_gen_br(l2);
4564 gen_set_label(l1);
4565 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4566 gen_set_label(l2);
76a66253 4567 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4568 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4569}
4570
4571/* dozo - dozo. */
4572GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4573{
22e0e173
AJ		 4574 int l1 = gen_new_label();
4575 int l2 = gen_new_label();
4576 TCGv t0 = tcg_temp_new();
4577 TCGv t1 = tcg_temp_new();
4578 TCGv t2 = tcg_temp_new();
4579 /* Start with XER OV disabled, the most likely case */
4580 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4581 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4582 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4583 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4584 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4585 tcg_gen_andc_tl(t1, t1, t2);
4586 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4587 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4588 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4589 tcg_gen_br(l2);
4590 gen_set_label(l1);
4591 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4592 gen_set_label(l2);
4593 tcg_temp_free(t0);
4594 tcg_temp_free(t1);
4595 tcg_temp_free(t2);
76a66253 4596 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4597 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4598}
4599
4600/* dozi */
4601GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4602{
22e0e173
AJ		 4603 target_long simm = SIMM(ctx->opcode);
4604 int l1 = gen_new_label();
4605 int l2 = gen_new_label();
4606 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4607 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4608 tcg_gen_br(l2);
4609 gen_set_label(l1);
4610 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4611 gen_set_label(l2);
4612 if (unlikely(Rc(ctx->opcode) != 0))
4613 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4614}
4615
76a66253
JM		 4616/* lscbx - lscbx. */
4617GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4618{
bdb4b689
AJ		 4619 TCGv t0 = tcg_temp_new();
4620 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4621 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4622 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4623
76db3ba4 4624 gen_addr_reg_index(ctx, t0);
76a66253 4625 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4626 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4627 gen_helper_lscbx(t0, t0, t1, t2, t3);
4628 tcg_temp_free_i32(t1);
4629 tcg_temp_free_i32(t2);
4630 tcg_temp_free_i32(t3);
3d7b417e 4631 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4632 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4633 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4634 gen_set_Rc0(ctx, t0);
4635 tcg_temp_free(t0);
76a66253
JM		 4636}
4637
4638/* maskg - maskg. */
4639GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4640{
22e0e173
AJ		 4641 int l1 = gen_new_label();
4642 TCGv t0 = tcg_temp_new();
4643 TCGv t1 = tcg_temp_new();
4644 TCGv t2 = tcg_temp_new();
4645 TCGv t3 = tcg_temp_new();
4646 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4647 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4648 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4649 tcg_gen_addi_tl(t2, t0, 1);
4650 tcg_gen_shr_tl(t2, t3, t2);
4651 tcg_gen_shr_tl(t3, t3, t1);
4652 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4653 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4654 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4655 gen_set_label(l1);
4656 tcg_temp_free(t0);
4657 tcg_temp_free(t1);
4658 tcg_temp_free(t2);
4659 tcg_temp_free(t3);
76a66253 4660 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4661 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4662}
4663
4664/* maskir - maskir. */
4665GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4666{
22e0e173
AJ		 4667 TCGv t0 = tcg_temp_new();
4668 TCGv t1 = tcg_temp_new();
4669 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4670 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4671 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4672 tcg_temp_free(t0);
4673 tcg_temp_free(t1);
76a66253 4674 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4675 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4676}
4677
4678/* mul - mul. */
4679GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4680{
22e0e173
AJ		 4681 TCGv_i64 t0 = tcg_temp_new_i64();
4682 TCGv_i64 t1 = tcg_temp_new_i64();
4683 TCGv t2 = tcg_temp_new();
4684 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4685 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4686 tcg_gen_mul_i64(t0, t0, t1);
4687 tcg_gen_trunc_i64_tl(t2, t0);
4688 gen_store_spr(SPR_MQ, t2);
4689 tcg_gen_shri_i64(t1, t0, 32);
4690 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4691 tcg_temp_free_i64(t0);
4692 tcg_temp_free_i64(t1);
4693 tcg_temp_free(t2);
76a66253 4694 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4695 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4696}
4697
4698/* mulo - mulo. */
4699GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4700{
22e0e173
AJ		 4701 int l1 = gen_new_label();
4702 TCGv_i64 t0 = tcg_temp_new_i64();
4703 TCGv_i64 t1 = tcg_temp_new_i64();
4704 TCGv t2 = tcg_temp_new();
4705 /* Start with XER OV disabled, the most likely case */
4706 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4707 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4708 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4709 tcg_gen_mul_i64(t0, t0, t1);
4710 tcg_gen_trunc_i64_tl(t2, t0);
4711 gen_store_spr(SPR_MQ, t2);
4712 tcg_gen_shri_i64(t1, t0, 32);
4713 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4714 tcg_gen_ext32s_i64(t1, t0);
4715 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4716 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4717 gen_set_label(l1);
4718 tcg_temp_free_i64(t0);
4719 tcg_temp_free_i64(t1);
4720 tcg_temp_free(t2);
76a66253 4721 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4722 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4723}
4724
4725/* nabs - nabs. */
4726GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4727{
22e0e173
AJ		 4728 int l1 = gen_new_label();
4729 int l2 = gen_new_label();
4730 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4731 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4732 tcg_gen_br(l2);
4733 gen_set_label(l1);
4734 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4735 gen_set_label(l2);
76a66253 4736 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4737 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4738}
4739
4740/* nabso - nabso. */
4741GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4742{
22e0e173
AJ		 4743 int l1 = gen_new_label();
4744 int l2 = gen_new_label();
4745 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4746 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4747 tcg_gen_br(l2);
4748 gen_set_label(l1);
4749 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4750 gen_set_label(l2);
4751 /* nabs never overflows */
4752 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4753 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4754 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4755}
4756
4757/* rlmi - rlmi. */
4758GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4759{
7487953d
AJ		 4760 uint32_t mb = MB(ctx->opcode);
4761 uint32_t me = ME(ctx->opcode);
4762 TCGv t0 = tcg_temp_new();
4763 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4764 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4765 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4766 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4767 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4768 tcg_temp_free(t0);
76a66253 4769 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4770 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4771}
4772
4773/* rrib - rrib. */
4774GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4775{
7487953d
AJ		 4776 TCGv t0 = tcg_temp_new();
4777 TCGv t1 = tcg_temp_new();
4778 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4779 tcg_gen_movi_tl(t1, 0x80000000);
4780 tcg_gen_shr_tl(t1, t1, t0);
4781 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4782 tcg_gen_and_tl(t0, t0, t1);
4783 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4784 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4785 tcg_temp_free(t0);
4786 tcg_temp_free(t1);
76a66253 4787 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4788 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4789}
4790
4791/* sle - sle. */
4792GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4793{
7487953d
AJ		 4794 TCGv t0 = tcg_temp_new();
4795 TCGv t1 = tcg_temp_new();
4796 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4797 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4798 tcg_gen_subfi_tl(t1, 32, t1);
4799 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4800 tcg_gen_or_tl(t1, t0, t1);
4801 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4802 gen_store_spr(SPR_MQ, t1);
4803 tcg_temp_free(t0);
4804 tcg_temp_free(t1);
76a66253 4805 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4806 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4807}
4808
4809/* sleq - sleq. */
4810GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4811{
7487953d
AJ		 4812 TCGv t0 = tcg_temp_new();
4813 TCGv t1 = tcg_temp_new();
4814 TCGv t2 = tcg_temp_new();
4815 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4816 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4817 tcg_gen_shl_tl(t2, t2, t0);
4818 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4819 gen_load_spr(t1, SPR_MQ);
4820 gen_store_spr(SPR_MQ, t0);
4821 tcg_gen_and_tl(t0, t0, t2);
4822 tcg_gen_andc_tl(t1, t1, t2);
4823 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4824 tcg_temp_free(t0);
4825 tcg_temp_free(t1);
4826 tcg_temp_free(t2);
76a66253 4827 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4829}
4830
4831/* sliq - sliq. */
4832GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4833{
7487953d
AJ		 4834 int sh = SH(ctx->opcode);
4835 TCGv t0 = tcg_temp_new();
4836 TCGv t1 = tcg_temp_new();
4837 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4838 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4839 tcg_gen_or_tl(t1, t0, t1);
4840 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4841 gen_store_spr(SPR_MQ, t1);
4842 tcg_temp_free(t0);
4843 tcg_temp_free(t1);
76a66253 4844 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4845 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4846}
4847
4848/* slliq - slliq. */
4849GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4850{
7487953d
AJ		 4851 int sh = SH(ctx->opcode);
4852 TCGv t0 = tcg_temp_new();
4853 TCGv t1 = tcg_temp_new();
4854 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4855 gen_load_spr(t1, SPR_MQ);
4856 gen_store_spr(SPR_MQ, t0);
4857 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4858 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4859 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4860 tcg_temp_free(t0);
4861 tcg_temp_free(t1);
76a66253 4862 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4863 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4864}
4865
4866/* sllq - sllq. */
4867GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4868{
7487953d
AJ		 4869 int l1 = gen_new_label();
4870 int l2 = gen_new_label();
4871 TCGv t0 = tcg_temp_local_new();
4872 TCGv t1 = tcg_temp_local_new();
4873 TCGv t2 = tcg_temp_local_new();
4874 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4875 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4876 tcg_gen_shl_tl(t1, t1, t2);
4877 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4878 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4879 gen_load_spr(t0, SPR_MQ);
4880 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4881 tcg_gen_br(l2);
4882 gen_set_label(l1);
4883 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4884 gen_load_spr(t2, SPR_MQ);
4885 tcg_gen_andc_tl(t1, t2, t1);
4886 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4887 gen_set_label(l2);
4888 tcg_temp_free(t0);
4889 tcg_temp_free(t1);
4890 tcg_temp_free(t2);
76a66253 4891 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4892 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4893}
4894
4895/* slq - slq. */
4896GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4897{
7487953d
AJ		 4898 int l1 = gen_new_label();
4899 TCGv t0 = tcg_temp_new();
4900 TCGv t1 = tcg_temp_new();
4901 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4902 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4903 tcg_gen_subfi_tl(t1, 32, t1);
4904 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4905 tcg_gen_or_tl(t1, t0, t1);
4906 gen_store_spr(SPR_MQ, t1);
4907 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4908 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4909 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4910 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4911 gen_set_label(l1);
4912 tcg_temp_free(t0);
4913 tcg_temp_free(t1);
76a66253 4914 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4915 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4916}
4917
d9bce9d9 4918/* sraiq - sraiq. */
76a66253
JM		 4919GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4920{
7487953d
AJ		 4921 int sh = SH(ctx->opcode);
4922 int l1 = gen_new_label();
4923 TCGv t0 = tcg_temp_new();
4924 TCGv t1 = tcg_temp_new();
4925 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4926 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4927 tcg_gen_or_tl(t0, t0, t1);
4928 gen_store_spr(SPR_MQ, t0);
4929 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4930 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4931 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4932 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4933 gen_set_label(l1);
4934 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4935 tcg_temp_free(t0);
4936 tcg_temp_free(t1);
76a66253 4937 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4939}
4940
4941/* sraq - sraq. */
4942GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4943{
7487953d
AJ		 4944 int l1 = gen_new_label();
4945 int l2 = gen_new_label();
4946 TCGv t0 = tcg_temp_new();
4947 TCGv t1 = tcg_temp_local_new();
4948 TCGv t2 = tcg_temp_local_new();
4949 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4950 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4951 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4952 tcg_gen_subfi_tl(t2, 32, t2);
4953 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4954 tcg_gen_or_tl(t0, t0, t2);
4955 gen_store_spr(SPR_MQ, t0);
4956 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4957 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4958 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4959 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4960 gen_set_label(l1);
4961 tcg_temp_free(t0);
4962 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4963 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4964 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4965 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4966 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4967 gen_set_label(l2);
4968 tcg_temp_free(t1);
4969 tcg_temp_free(t2);
76a66253 4970 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4972}
4973
4974/* sre - sre. */
4975GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4976{
7487953d
AJ		 4977 TCGv t0 = tcg_temp_new();
4978 TCGv t1 = tcg_temp_new();
4979 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4980 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4981 tcg_gen_subfi_tl(t1, 32, t1);
4982 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4983 tcg_gen_or_tl(t1, t0, t1);
4984 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4985 gen_store_spr(SPR_MQ, t1);
4986 tcg_temp_free(t0);
4987 tcg_temp_free(t1);
76a66253 4988 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4989 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4990}
4991
4992/* srea - srea. */
4993GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4994{
7487953d
AJ		 4995 TCGv t0 = tcg_temp_new();
4996 TCGv t1 = tcg_temp_new();
4997 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4998 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4999 gen_store_spr(SPR_MQ, t0);
5000 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5001 tcg_temp_free(t0);
5002 tcg_temp_free(t1);
76a66253 5003 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5004 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5005}
5006
5007/* sreq */
5008GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
5009{
7487953d
AJ		 5010 TCGv t0 = tcg_temp_new();
5011 TCGv t1 = tcg_temp_new();
5012 TCGv t2 = tcg_temp_new();
5013 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5014 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5015 tcg_gen_shr_tl(t1, t1, t0);
5016 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5017 gen_load_spr(t2, SPR_MQ);
5018 gen_store_spr(SPR_MQ, t0);
5019 tcg_gen_and_tl(t0, t0, t1);
5020 tcg_gen_andc_tl(t2, t2, t1);
5021 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5022 tcg_temp_free(t0);
5023 tcg_temp_free(t1);
5024 tcg_temp_free(t2);
76a66253 5025 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5026 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5027}
5028
5029/* sriq */
5030GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5031{
7487953d
AJ		 5032 int sh = SH(ctx->opcode);
5033 TCGv t0 = tcg_temp_new();
5034 TCGv t1 = tcg_temp_new();
5035 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5036 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5037 tcg_gen_or_tl(t1, t0, t1);
5038 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5039 gen_store_spr(SPR_MQ, t1);
5040 tcg_temp_free(t0);
5041 tcg_temp_free(t1);
76a66253 5042 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5043 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5044}
5045
5046/* srliq */
5047GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5048{
7487953d
AJ		 5049 int sh = SH(ctx->opcode);
5050 TCGv t0 = tcg_temp_new();
5051 TCGv t1 = tcg_temp_new();
5052 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5053 gen_load_spr(t1, SPR_MQ);
5054 gen_store_spr(SPR_MQ, t0);
5055 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5056 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5057 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5058 tcg_temp_free(t0);
5059 tcg_temp_free(t1);
76a66253 5060 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5061 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5062}
5063
5064/* srlq */
5065GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5066{
7487953d
AJ		 5067 int l1 = gen_new_label();
5068 int l2 = gen_new_label();
5069 TCGv t0 = tcg_temp_local_new();
5070 TCGv t1 = tcg_temp_local_new();
5071 TCGv t2 = tcg_temp_local_new();
5072 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5073 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5074 tcg_gen_shr_tl(t2, t1, t2);
5075 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5076 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5077 gen_load_spr(t0, SPR_MQ);
5078 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5079 tcg_gen_br(l2);
5080 gen_set_label(l1);
5081 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5082 tcg_gen_and_tl(t0, t0, t2);
5083 gen_load_spr(t1, SPR_MQ);
5084 tcg_gen_andc_tl(t1, t1, t2);
5085 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5086 gen_set_label(l2);
5087 tcg_temp_free(t0);
5088 tcg_temp_free(t1);
5089 tcg_temp_free(t2);
76a66253 5090 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5091 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5092}
5093
5094/* srq */
5095GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5096{
7487953d
AJ		 5097 int l1 = gen_new_label();
5098 TCGv t0 = tcg_temp_new();
5099 TCGv t1 = tcg_temp_new();
5100 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5101 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5102 tcg_gen_subfi_tl(t1, 32, t1);
5103 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5104 tcg_gen_or_tl(t1, t0, t1);
5105 gen_store_spr(SPR_MQ, t1);
5106 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5107 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5108 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5109 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5110 gen_set_label(l1);
5111 tcg_temp_free(t0);
5112 tcg_temp_free(t1);
76a66253 5113 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5114 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5115}
5116
5117/* PowerPC 602 specific instructions */
5118/* dsa */
5119GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5120{
5121 /* XXX: TODO */
e06fcd75 5122 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5123}
5124
5125/* esa */
5126GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5127{
5128 /* XXX: TODO */
e06fcd75 5129 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5130}
5131
5132/* mfrom */
5133GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5134{
5135#if defined(CONFIG_USER_ONLY)
e06fcd75 5136 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5137#else
76db3ba4 5138 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5140 return;
5141 }
cf02a65c 5142 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5143#endif
5144}
5145
5146/* 602 - 603 - G2 TLB management */
5147/* tlbld */
c7697e1f 5148GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5149{
5150#if defined(CONFIG_USER_ONLY)
e06fcd75 5151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5152#else
76db3ba4 5153 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5154 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5155 return;
5156 }
74d37793 5157 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5158#endif
5159}
5160
5161/* tlbli */
c7697e1f 5162GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5163{
5164#if defined(CONFIG_USER_ONLY)
e06fcd75 5165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5166#else
76db3ba4 5167 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5168 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5169 return;
5170 }
74d37793 5171 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5172#endif
5173}
5174
7dbe11ac
JM		 5175/* 74xx TLB management */
5176/* tlbld */
c7697e1f 5177GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5178{
5179#if defined(CONFIG_USER_ONLY)
e06fcd75 5180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5181#else
76db3ba4 5182 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5184 return;
5185 }
74d37793 5186 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5187#endif
5188}
5189
5190/* tlbli */
c7697e1f 5191GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5192{
5193#if defined(CONFIG_USER_ONLY)
e06fcd75 5194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5195#else
76db3ba4 5196 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5198 return;
5199 }
74d37793 5200 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5201#endif
5202}
5203
76a66253
JM		 5204/* POWER instructions not in PowerPC 601 */
5205/* clf */
5206GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5207{
5208 /* Cache line flush: implemented as no-op */
5209}
5210
5211/* cli */
5212GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5213{
7f75ffd3 5214 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5215#if defined(CONFIG_USER_ONLY)
e06fcd75 5216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5217#else
76db3ba4 5218 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5220 return;
5221 }
5222#endif
5223}
5224
5225/* dclst */
5226GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5227{
5228 /* Data cache line store: treated as no-op */
5229}
5230
5231GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5232{
5233#if defined(CONFIG_USER_ONLY)
e06fcd75 5234 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5235#else
74d37793
AJ		 5236 int ra = rA(ctx->opcode);
5237 int rd = rD(ctx->opcode);
5238 TCGv t0;
76db3ba4 5239 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5241 return;
5242 }
74d37793 5243 t0 = tcg_temp_new();
76db3ba4 5244 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5245 tcg_gen_shri_tl(t0, t0, 28);
5246 tcg_gen_andi_tl(t0, t0, 0xF);
5247 gen_helper_load_sr(cpu_gpr[rd], t0);
5248 tcg_temp_free(t0);
76a66253 5249 if (ra != 0 && ra != rd)
74d37793 5250 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5251#endif
5252}
5253
5254GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5255{
5256#if defined(CONFIG_USER_ONLY)
e06fcd75 5257 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5258#else
22e0e173 5259 TCGv t0;
76db3ba4 5260 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5262 return;
5263 }
22e0e173 5264 t0 = tcg_temp_new();
76db3ba4 5265 gen_addr_reg_index(ctx, t0);
22e0e173
AJ		 5266 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5267 tcg_temp_free(t0);
76a66253
JM		 5268#endif
5269}
5270
5271GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5272{
5273#if defined(CONFIG_USER_ONLY)
e06fcd75 5274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5275#else
76db3ba4 5276 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5278 return;
5279 }
d72a19f7 5280 gen_helper_rfsvc();
e06fcd75 5281 gen_sync_exception(ctx);
76a66253
JM		 5282#endif
5283}
5284
5285/* svc is not implemented for now */
5286
5287/* POWER2 specific instructions */
5288/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5289
5290/* lfq */
5291GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5292{
01a4afeb 5293 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5294 TCGv t0;
5295 gen_set_access_type(ctx, ACCESS_FLOAT);
5296 t0 = tcg_temp_new();
5297 gen_addr_imm_index(ctx, t0, 0);
5298 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5299 gen_addr_add(ctx, t0, t0, 8);
5300 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5301 tcg_temp_free(t0);
76a66253
JM		 5302}
5303
5304/* lfqu */
5305GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5306{
5307 int ra = rA(ctx->opcode);
01a4afeb 5308 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5309 TCGv t0, t1;
5310 gen_set_access_type(ctx, ACCESS_FLOAT);
5311 t0 = tcg_temp_new();
5312 t1 = tcg_temp_new();
5313 gen_addr_imm_index(ctx, t0, 0);
5314 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5315 gen_addr_add(ctx, t1, t0, 8);
5316 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5317 if (ra != 0)
01a4afeb
AJ		 5318 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5319 tcg_temp_free(t0);
5320 tcg_temp_free(t1);
76a66253
JM		 5321}
5322
5323/* lfqux */
5324GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5325{
5326 int ra = rA(ctx->opcode);
01a4afeb 5327 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5328 gen_set_access_type(ctx, ACCESS_FLOAT);
5329 TCGv t0, t1;
5330 t0 = tcg_temp_new();
5331 gen_addr_reg_index(ctx, t0);
5332 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5333 t1 = tcg_temp_new();
5334 gen_addr_add(ctx, t1, t0, 8);
5335 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5336 tcg_temp_free(t1);
76a66253 5337 if (ra != 0)
01a4afeb
AJ		 5338 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5339 tcg_temp_free(t0);
76a66253
JM		 5340}
5341
5342/* lfqx */
5343GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5344{
01a4afeb 5345 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5346 TCGv t0;
5347 gen_set_access_type(ctx, ACCESS_FLOAT);
5348 t0 = tcg_temp_new();
5349 gen_addr_reg_index(ctx, t0);
5350 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5351 gen_addr_add(ctx, t0, t0, 8);
5352 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5353 tcg_temp_free(t0);
76a66253
JM		 5354}
5355
5356/* stfq */
5357GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5358{
01a4afeb 5359 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5360 TCGv t0;
5361 gen_set_access_type(ctx, ACCESS_FLOAT);
5362 t0 = tcg_temp_new();
5363 gen_addr_imm_index(ctx, t0, 0);
5364 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5365 gen_addr_add(ctx, t0, t0, 8);
5366 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5367 tcg_temp_free(t0);
76a66253
JM		 5368}
5369
5370/* stfqu */
5371GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5372{
5373 int ra = rA(ctx->opcode);
01a4afeb 5374 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5375 TCGv t0, t1;
5376 gen_set_access_type(ctx, ACCESS_FLOAT);
5377 t0 = tcg_temp_new();
5378 gen_addr_imm_index(ctx, t0, 0);
5379 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5380 t1 = tcg_temp_new();
5381 gen_addr_add(ctx, t1, t0, 8);
5382 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5383 tcg_temp_free(t1);
76a66253 5384 if (ra != 0)
01a4afeb
AJ		 5385 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5386 tcg_temp_free(t0);
76a66253
JM		 5387}
5388
5389/* stfqux */
5390GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5391{
5392 int ra = rA(ctx->opcode);
01a4afeb 5393 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5394 TCGv t0, t1;
5395 gen_set_access_type(ctx, ACCESS_FLOAT);
5396 t0 = tcg_temp_new();
5397 gen_addr_reg_index(ctx, t0);
5398 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5399 t1 = tcg_temp_new();
5400 gen_addr_add(ctx, t1, t0, 8);
5401 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5402 tcg_temp_free(t1);
76a66253 5403 if (ra != 0)
01a4afeb
AJ		 5404 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5405 tcg_temp_free(t0);
76a66253
JM		 5406}
5407
5408/* stfqx */
5409GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5410{
01a4afeb 5411 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5412 TCGv t0;
5413 gen_set_access_type(ctx, ACCESS_FLOAT);
5414 t0 = tcg_temp_new();
5415 gen_addr_reg_index(ctx, t0);
5416 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5417 gen_addr_add(ctx, t0, t0, 8);
5418 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5419 tcg_temp_free(t0);
76a66253
JM		 5420}
5421
5422/* BookE specific instructions */
2662a059 5423/* XXX: not implemented on 440 ? */
05332d70 5424GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5425{
5426 /* XXX: TODO */
e06fcd75 5427 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5428}
5429
2662a059 5430/* XXX: not implemented on 440 ? */
05332d70 5431GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5432{
5433#if defined(CONFIG_USER_ONLY)
e06fcd75 5434 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5435#else
74d37793 5436 TCGv t0;
76db3ba4 5437 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5439 return;
5440 }
ec72e276 5441 t0 = tcg_temp_new();
76db3ba4 5442 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5443 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5444 tcg_temp_free(t0);
76a66253
JM		 5445#endif
5446}
5447
5448/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5449static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5450 int opc2, int opc3,
5451 int ra, int rb, int rt, int Rc)
76a66253 5452{
182608d4
AJ		 5453 TCGv t0, t1;
5454
a7812ae4
PB		 5455 t0 = tcg_temp_local_new();
5456 t1 = tcg_temp_local_new();
182608d4 5457
76a66253
JM		 5458 switch (opc3 & 0x0D) {
5459 case 0x05:
5460 /* macchw - macchw. - macchwo - macchwo. */
5461 /* macchws - macchws. - macchwso - macchwso. */
5462 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5463 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5464 /* mulchw - mulchw. */
182608d4
AJ		 5465 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5466 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5467 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5468 break;
5469 case 0x04:
5470 /* macchwu - macchwu. - macchwuo - macchwuo. */
5471 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5472 /* mulchwu - mulchwu. */
182608d4
AJ		 5473 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5474 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5475 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5476 break;
5477 case 0x01:
5478 /* machhw - machhw. - machhwo - machhwo. */
5479 /* machhws - machhws. - machhwso - machhwso. */
5480 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5481 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5482 /* mulhhw - mulhhw. */
182608d4
AJ		 5483 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5484 tcg_gen_ext16s_tl(t0, t0);
5485 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5486 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5487 break;
5488 case 0x00:
5489 /* machhwu - machhwu. - machhwuo - machhwuo. */
5490 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5491 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5492 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5493 tcg_gen_ext16u_tl(t0, t0);
5494 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5495 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5496 break;
5497 case 0x0D:
5498 /* maclhw - maclhw. - maclhwo - maclhwo. */
5499 /* maclhws - maclhws. - maclhwso - maclhwso. */
5500 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5501 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5502 /* mullhw - mullhw. */
182608d4
AJ		 5503 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5504 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5505 break;
5506 case 0x0C:
5507 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5508 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5509 /* mullhwu - mullhwu. */
182608d4
AJ		 5510 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5511 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5512 break;
5513 }
76a66253 5514 if (opc2 & 0x04) {
182608d4
AJ		 5515 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5516 tcg_gen_mul_tl(t1, t0, t1);
5517 if (opc2 & 0x02) {
5518 /* nmultiply-and-accumulate (0x0E) */
5519 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5520 } else {
5521 /* multiply-and-accumulate (0x0C) */
5522 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5523 }
5524
5525 if (opc3 & 0x12) {
5526 /* Check overflow and/or saturate */
5527 int l1 = gen_new_label();
5528
5529 if (opc3 & 0x10) {
5530 /* Start with XER OV disabled, the most likely case */
5531 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5532 }
5533 if (opc3 & 0x01) {
5534 /* Signed */
5535 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5536 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5537 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5538 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5539 if (opc3 & 0x02) {
182608d4
AJ		 5540 /* Saturate */
5541 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5542 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5543 }
5544 } else {
5545 /* Unsigned */
5546 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5547 if (opc3 & 0x02) {
182608d4
AJ		 5548 /* Saturate */
5549 tcg_gen_movi_tl(t0, UINT32_MAX);
5550 }
5551 }
5552 if (opc3 & 0x10) {
5553 /* Check overflow */
5554 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5555 }
5556 gen_set_label(l1);
5557 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5558 }
5559 } else {
5560 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5561 }
182608d4
AJ		 5562 tcg_temp_free(t0);
5563 tcg_temp_free(t1);
76a66253
JM		 5564 if (unlikely(Rc) != 0) {
5565 /* Update Rc0 */
182608d4 5566 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5567 }
5568}
5569
a750fc0b
JM		 5570#define GEN_MAC_HANDLER(name, opc2, opc3) \
5571GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5572{ \
5573 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5574 rD(ctx->opcode), Rc(ctx->opcode)); \
5575}
5576
5577/* macchw - macchw. */
a750fc0b 5578GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5579/* macchwo - macchwo. */
a750fc0b 5580GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5581/* macchws - macchws. */
a750fc0b 5582GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5583/* macchwso - macchwso. */
a750fc0b 5584GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5585/* macchwsu - macchwsu. */
a750fc0b 5586GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5587/* macchwsuo - macchwsuo. */
a750fc0b 5588GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5589/* macchwu - macchwu. */
a750fc0b 5590GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5591/* macchwuo - macchwuo. */
a750fc0b 5592GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5593/* machhw - machhw. */
a750fc0b 5594GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5595/* machhwo - machhwo. */
a750fc0b 5596GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5597/* machhws - machhws. */
a750fc0b 5598GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5599/* machhwso - machhwso. */
a750fc0b 5600GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5601/* machhwsu - machhwsu. */
a750fc0b 5602GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5603/* machhwsuo - machhwsuo. */
a750fc0b 5604GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5605/* machhwu - machhwu. */
a750fc0b 5606GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5607/* machhwuo - machhwuo. */
a750fc0b 5608GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5609/* maclhw - maclhw. */
a750fc0b 5610GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5611/* maclhwo - maclhwo. */
a750fc0b 5612GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5613/* maclhws - maclhws. */
a750fc0b 5614GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5615/* maclhwso - maclhwso. */
a750fc0b 5616GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5617/* maclhwu - maclhwu. */
a750fc0b 5618GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5619/* maclhwuo - maclhwuo. */
a750fc0b 5620GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5621/* maclhwsu - maclhwsu. */
a750fc0b 5622GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5623/* maclhwsuo - maclhwsuo. */
a750fc0b 5624GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5625/* nmacchw - nmacchw. */
a750fc0b 5626GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5627/* nmacchwo - nmacchwo. */
a750fc0b 5628GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5629/* nmacchws - nmacchws. */
a750fc0b 5630GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5631/* nmacchwso - nmacchwso. */
a750fc0b 5632GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5633/* nmachhw - nmachhw. */
a750fc0b 5634GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5635/* nmachhwo - nmachhwo. */
a750fc0b 5636GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5637/* nmachhws - nmachhws. */
a750fc0b 5638GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5639/* nmachhwso - nmachhwso. */
a750fc0b 5640GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5641/* nmaclhw - nmaclhw. */
a750fc0b 5642GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5643/* nmaclhwo - nmaclhwo. */
a750fc0b 5644GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5645/* nmaclhws - nmaclhws. */
a750fc0b 5646GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5647/* nmaclhwso - nmaclhwso. */
a750fc0b 5648GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5649
5650/* mulchw - mulchw. */
a750fc0b 5651GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5652/* mulchwu - mulchwu. */
a750fc0b 5653GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5654/* mulhhw - mulhhw. */
a750fc0b 5655GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5656/* mulhhwu - mulhhwu. */
a750fc0b 5657GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5658/* mullhw - mullhw. */
a750fc0b 5659GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5660/* mullhwu - mullhwu. */
a750fc0b 5661GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5662
5663/* mfdcr */
05332d70 5664GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5665{
5666#if defined(CONFIG_USER_ONLY)
e06fcd75 5667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5668#else
06dca6a7 5669 TCGv dcrn;
76db3ba4 5670 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5672 return;
5673 }
06dca6a7
AJ		 5674 /* NIP cannot be restored if the memory exception comes from an helper */
5675 gen_update_nip(ctx, ctx->nip - 4);
5676 dcrn = tcg_const_tl(SPR(ctx->opcode));
5677 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5678 tcg_temp_free(dcrn);
76a66253
JM		 5679#endif
5680}
5681
5682/* mtdcr */
05332d70 5683GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5684{
5685#if defined(CONFIG_USER_ONLY)
e06fcd75 5686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5687#else
06dca6a7 5688 TCGv dcrn;
76db3ba4 5689 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5691 return;
5692 }
06dca6a7
AJ		 5693 /* NIP cannot be restored if the memory exception comes from an helper */
5694 gen_update_nip(ctx, ctx->nip - 4);
5695 dcrn = tcg_const_tl(SPR(ctx->opcode));
5696 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5697 tcg_temp_free(dcrn);
a42bd6cc
JM		 5698#endif
5699}
5700
5701/* mfdcrx */
2662a059 5702/* XXX: not implemented on 440 ? */
05332d70 5703GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5704{
5705#if defined(CONFIG_USER_ONLY)
e06fcd75 5706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5707#else
76db3ba4 5708 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5710 return;
5711 }
06dca6a7
AJ		 5712 /* NIP cannot be restored if the memory exception comes from an helper */
5713 gen_update_nip(ctx, ctx->nip - 4);
5714 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5715 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5716#endif
5717}
5718
5719/* mtdcrx */
2662a059 5720/* XXX: not implemented on 440 ? */
05332d70 5721GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5722{
5723#if defined(CONFIG_USER_ONLY)
e06fcd75 5724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5725#else
76db3ba4 5726 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5728 return;
5729 }
06dca6a7
AJ		 5730 /* NIP cannot be restored if the memory exception comes from an helper */
5731 gen_update_nip(ctx, ctx->nip - 4);
5732 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5733 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5734#endif
5735}
5736
a750fc0b
JM		 5737/* mfdcrux (PPC 460) : user-mode access to DCR */
5738GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5739{
06dca6a7
AJ		 5740 /* NIP cannot be restored if the memory exception comes from an helper */
5741 gen_update_nip(ctx, ctx->nip - 4);
5742 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5743 /* Note: Rc update flag set leads to undefined state of Rc0 */
5744}
5745
5746/* mtdcrux (PPC 460) : user-mode access to DCR */
5747GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5748{
06dca6a7
AJ		 5749 /* NIP cannot be restored if the memory exception comes from an helper */
5750 gen_update_nip(ctx, ctx->nip - 4);
5751 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5752 /* Note: Rc update flag set leads to undefined state of Rc0 */
5753}
5754
76a66253
JM		 5755/* dccci */
5756GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5757{
5758#if defined(CONFIG_USER_ONLY)
e06fcd75 5759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5760#else
76db3ba4 5761 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5763 return;
5764 }
5765 /* interpreted as no-op */
5766#endif
5767}
5768
5769/* dcread */
5770GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5771{
5772#if defined(CONFIG_USER_ONLY)
e06fcd75 5773 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5774#else
b61f2753 5775 TCGv EA, val;
76db3ba4 5776 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5778 return;
5779 }
76db3ba4 5780 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5781 EA = tcg_temp_new();
76db3ba4 5782 gen_addr_reg_index(ctx, EA);
a7812ae4 5783 val = tcg_temp_new();
76db3ba4 5784 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5785 tcg_temp_free(val);
5786 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5787 tcg_temp_free(EA);
76a66253
JM		 5788#endif
5789}
5790
5791/* icbt */
c7697e1f 5792GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5793{
5794 /* interpreted as no-op */
5795 /* XXX: specification say this is treated as a load by the MMU
5796 * but does not generate any exception
5797 */
5798}
5799
5800/* iccci */
5801GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5802{
5803#if defined(CONFIG_USER_ONLY)
e06fcd75 5804 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5805#else
76db3ba4 5806 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5807 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5808 return;
5809 }
5810 /* interpreted as no-op */
5811#endif
5812}
5813
5814/* icread */
5815GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5816{
5817#if defined(CONFIG_USER_ONLY)
e06fcd75 5818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5819#else
76db3ba4 5820 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5821 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5822 return;
5823 }
5824 /* interpreted as no-op */
5825#endif
5826}
5827
76db3ba4 5828/* rfci (mem_idx only) */
c7697e1f 5829GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5830{
5831#if defined(CONFIG_USER_ONLY)
e06fcd75 5832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5833#else
76db3ba4 5834 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5836 return;
5837 }
5838 /* Restore CPU state */
d72a19f7 5839 gen_helper_40x_rfci();
e06fcd75 5840 gen_sync_exception(ctx);
a42bd6cc
JM		 5841#endif
5842}
5843
5844GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5845{
5846#if defined(CONFIG_USER_ONLY)
e06fcd75 5847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5848#else
76db3ba4 5849 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5851 return;
5852 }
5853 /* Restore CPU state */
d72a19f7 5854 gen_helper_rfci();
e06fcd75 5855 gen_sync_exception(ctx);
a42bd6cc
JM		 5856#endif
5857}
5858
5859/* BookE specific */
2662a059 5860/* XXX: not implemented on 440 ? */
05332d70 5861GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5862{
5863#if defined(CONFIG_USER_ONLY)
e06fcd75 5864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5865#else
76db3ba4 5866 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5867 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5868 return;
5869 }
5870 /* Restore CPU state */
d72a19f7 5871 gen_helper_rfdi();
e06fcd75 5872 gen_sync_exception(ctx);
76a66253
JM		 5873#endif
5874}
5875
2662a059 5876/* XXX: not implemented on 440 ? */
a750fc0b 5877GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5878{
5879#if defined(CONFIG_USER_ONLY)
e06fcd75 5880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5881#else
76db3ba4 5882 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5884 return;
5885 }
5886 /* Restore CPU state */
d72a19f7 5887 gen_helper_rfmci();
e06fcd75 5888 gen_sync_exception(ctx);
a42bd6cc
JM		 5889#endif
5890}
5eb7995e 5891
d9bce9d9 5892/* TLB management - PowerPC 405 implementation */
76a66253 5893/* tlbre */
c7697e1f 5894GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5895{
5896#if defined(CONFIG_USER_ONLY)
e06fcd75 5897 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5898#else
76db3ba4 5899 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5900 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5901 return;
5902 }
5903 switch (rB(ctx->opcode)) {
5904 case 0:
74d37793 5905 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5906 break;
5907 case 1:
74d37793 5908 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5909 break;
5910 default:
e06fcd75 5911 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5912 break;
9a64fbe4 5913 }
76a66253
JM		 5914#endif
5915}
5916
d9bce9d9 5917/* tlbsx - tlbsx. */
c7697e1f 5918GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5919{
5920#if defined(CONFIG_USER_ONLY)
e06fcd75 5921 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5922#else
74d37793 5923 TCGv t0;
76db3ba4 5924 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5925 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5926 return;
5927 }
74d37793 5928 t0 = tcg_temp_new();
76db3ba4 5929 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5930 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5931 tcg_temp_free(t0);
5932 if (Rc(ctx->opcode)) {
5933 int l1 = gen_new_label();
5934 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5935 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5936 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5937 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5938 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5939 gen_set_label(l1);
5940 }
76a66253 5941#endif
79aceca5
FB		 5942}
5943
76a66253 5944/* tlbwe */
c7697e1f 5945GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5946{
76a66253 5947#if defined(CONFIG_USER_ONLY)
e06fcd75 5948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5949#else
76db3ba4 5950 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5952 return;
5953 }
5954 switch (rB(ctx->opcode)) {
5955 case 0:
74d37793 5956 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5957 break;
5958 case 1:
74d37793 5959 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5960 break;
5961 default:
e06fcd75 5962 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5963 break;
9a64fbe4 5964 }
76a66253
JM		 5965#endif
5966}
5967
a4bb6c3e 5968/* TLB management - PowerPC 440 implementation */
5eb7995e 5969/* tlbre */
c7697e1f 5970GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5971{
5972#if defined(CONFIG_USER_ONLY)
e06fcd75 5973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5974#else
76db3ba4 5975 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5976 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5977 return;
5978 }
5979 switch (rB(ctx->opcode)) {
5980 case 0:
5eb7995e 5981 case 1:
5eb7995e 5982 case 2:
74d37793
AJ		 5983 {
5984 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5985 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5986 tcg_temp_free_i32(t0);
5987 }
5eb7995e
JM		 5988 break;
5989 default:
e06fcd75 5990 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 5991 break;
5992 }
5993#endif
5994}
5995
5996/* tlbsx - tlbsx. */
c7697e1f 5997GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5998{
5999#if defined(CONFIG_USER_ONLY)
e06fcd75 6000 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6001#else
74d37793 6002 TCGv t0;
76db3ba4 6003 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6004 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6005 return;
6006 }
74d37793 6007 t0 = tcg_temp_new();
76db3ba4 6008 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 6009 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6010 tcg_temp_free(t0);
6011 if (Rc(ctx->opcode)) {
6012 int l1 = gen_new_label();
6013 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6014 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6015 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6016 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6017 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6018 gen_set_label(l1);
6019 }
5eb7995e
JM		 6020#endif
6021}
6022
6023/* tlbwe */
c7697e1f 6024GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 6025{
6026#if defined(CONFIG_USER_ONLY)
e06fcd75 6027 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6028#else
76db3ba4 6029 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6030 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6031 return;
6032 }
6033 switch (rB(ctx->opcode)) {
6034 case 0:
5eb7995e 6035 case 1:
5eb7995e 6036 case 2:
74d37793
AJ		 6037 {
6038 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6039 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6040 tcg_temp_free_i32(t0);
6041 }
5eb7995e
JM		 6042 break;
6043 default:
e06fcd75 6044 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6045 break;
6046 }
6047#endif
6048}
6049
76a66253 6050/* wrtee */
05332d70 6051GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6052{
6053#if defined(CONFIG_USER_ONLY)
e06fcd75 6054 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6055#else
6527f6ea 6056 TCGv t0;
76db3ba4 6057 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6059 return;
6060 }
6527f6ea
AJ		 6061 t0 = tcg_temp_new();
6062 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6063 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6064 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6065 tcg_temp_free(t0);
dee96f6c
JM		 6066 /* Stop translation to have a chance to raise an exception
6067 * if we just set msr_ee to 1
6068 */
e06fcd75 6069 gen_stop_exception(ctx);
76a66253
JM		 6070#endif
6071}
6072
6073/* wrteei */
05332d70 6074GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6075{
6076#if defined(CONFIG_USER_ONLY)
e06fcd75 6077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6078#else
76db3ba4 6079 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6080 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6081 return;
6082 }
6527f6ea
AJ		 6083 if (ctx->opcode & 0x00010000) {
6084 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6085 /* Stop translation to have a chance to raise an exception */
e06fcd75 6086 gen_stop_exception(ctx);
6527f6ea 6087 } else {
1b6e5f99 6088 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6089 }
76a66253
JM		 6090#endif
6091}
6092
08e46e54 6093/* PowerPC 440 specific instructions */
76a66253
JM		 6094/* dlmzb */
6095GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6096{
ef0d51af
AJ		 6097 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6098 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6099 cpu_gpr[rB(ctx->opcode)], t0);
6100 tcg_temp_free_i32(t0);
76a66253
JM		 6101}
6102
6103/* mbar replaces eieio on 440 */
26370046 6104GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
76a66253
JM		 6105{
6106 /* interpreted as no-op */
6107}
6108
6109/* msync replaces sync on 440 */
0db1b20e 6110GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6111{
6112 /* interpreted as no-op */
6113}
6114
6115/* icbt */
c7697e1f 6116GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6117{
6118 /* interpreted as no-op */
6119 /* XXX: specification say this is treated as a load by the MMU
6120 * but does not generate any exception
6121 */
79aceca5
FB		 6122}
6123
a9d9eb8f
JM		 6124/*** Altivec vector extension ***/
6125/* Altivec registers moves */
a9d9eb8f 6126
564e571a
AJ		 6127static always_inline TCGv_ptr gen_avr_ptr(int reg)
6128{
e4704b3b 6129 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6130 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6131 return r;
6132}
6133
a9d9eb8f 6134#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6135GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6136{ \
fe1e5c53 6137 TCGv EA; \
a9d9eb8f 6138 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6139 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6140 return; \
6141 } \
76db3ba4 6142 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6143 EA = tcg_temp_new(); \
76db3ba4 6144 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6145 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6146 if (ctx->le_mode) { \
6147 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6148 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6149 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6150 } else { \
76db3ba4 6151 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6152 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6153 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6154 } \
6155 tcg_temp_free(EA); \
a9d9eb8f
JM		 6156}
6157
6158#define GEN_VR_STX(name, opc2, opc3) \
6159GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6160{ \
fe1e5c53 6161 TCGv EA; \
a9d9eb8f 6162 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6163 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6164 return; \
6165 } \
76db3ba4 6166 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6167 EA = tcg_temp_new(); \
76db3ba4 6168 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6169 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6170 if (ctx->le_mode) { \
6171 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6172 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6173 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6174 } else { \
76db3ba4 6175 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6176 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6177 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6178 } \
6179 tcg_temp_free(EA); \
a9d9eb8f
JM		 6180}
6181
cbfb6ae9
AJ		 6182#define GEN_VR_LVE(name, opc2, opc3) \
6183 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6184 { \
6185 TCGv EA; \
6186 TCGv_ptr rs; \
6187 if (unlikely(!ctx->altivec_enabled)) { \
6188 gen_exception(ctx, POWERPC_EXCP_VPU); \
6189 return; \
6190 } \
6191 gen_set_access_type(ctx, ACCESS_INT); \
6192 EA = tcg_temp_new(); \
6193 gen_addr_reg_index(ctx, EA); \
6194 rs = gen_avr_ptr(rS(ctx->opcode)); \
6195 gen_helper_lve##name (rs, EA); \
6196 tcg_temp_free(EA); \
6197 tcg_temp_free_ptr(rs); \
6198 }
6199
6200#define GEN_VR_STVE(name, opc2, opc3) \
6201 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6202 { \
6203 TCGv EA; \
6204 TCGv_ptr rs; \
6205 if (unlikely(!ctx->altivec_enabled)) { \
6206 gen_exception(ctx, POWERPC_EXCP_VPU); \
6207 return; \
6208 } \
6209 gen_set_access_type(ctx, ACCESS_INT); \
6210 EA = tcg_temp_new(); \
6211 gen_addr_reg_index(ctx, EA); \
6212 rs = gen_avr_ptr(rS(ctx->opcode)); \
6213 gen_helper_stve##name (rs, EA); \
6214 tcg_temp_free(EA); \
6215 tcg_temp_free_ptr(rs); \
6216 }
6217
fe1e5c53 6218GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6219/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6220GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6221
cbfb6ae9
AJ		 6222GEN_VR_LVE(bx, 0x07, 0x00);
6223GEN_VR_LVE(hx, 0x07, 0x01);
6224GEN_VR_LVE(wx, 0x07, 0x02);
6225
fe1e5c53 6226GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6227/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6228GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6229
cbfb6ae9
AJ		 6230GEN_VR_STVE(bx, 0x07, 0x04);
6231GEN_VR_STVE(hx, 0x07, 0x05);
6232GEN_VR_STVE(wx, 0x07, 0x06);
6233
bf8d8ded
AJ		 6234GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6235{
6236 TCGv_ptr rd;
6237 TCGv EA;
6238 if (unlikely(!ctx->altivec_enabled)) {
6239 gen_exception(ctx, POWERPC_EXCP_VPU);
6240 return;
6241 }
6242 EA = tcg_temp_new();
6243 gen_addr_reg_index(ctx, EA);
6244 rd = gen_avr_ptr(rD(ctx->opcode));
6245 gen_helper_lvsl(rd, EA);
6246 tcg_temp_free(EA);
6247 tcg_temp_free_ptr(rd);
6248}
6249
6250GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6251{
6252 TCGv_ptr rd;
6253 TCGv EA;
6254 if (unlikely(!ctx->altivec_enabled)) {
6255 gen_exception(ctx, POWERPC_EXCP_VPU);
6256 return;
6257 }
6258 EA = tcg_temp_new();
6259 gen_addr_reg_index(ctx, EA);
6260 rd = gen_avr_ptr(rD(ctx->opcode));
6261 gen_helper_lvsr(rd, EA);
6262 tcg_temp_free(EA);
6263 tcg_temp_free_ptr(rd);
6264}
6265
785f451b
AJ		 6266GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6267{
6268 TCGv_i32 t;
6269 if (unlikely(!ctx->altivec_enabled)) {
6270 gen_exception(ctx, POWERPC_EXCP_VPU);
6271 return;
6272 }
6273 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6274 t = tcg_temp_new_i32();
6275 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6276 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6277 tcg_temp_free(t);
6278}
6279
6280GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6281{
6282 TCGv_i32 t;
6283 if (unlikely(!ctx->altivec_enabled)) {
6284 gen_exception(ctx, POWERPC_EXCP_VPU);
6285 return;
6286 }
6287 t = tcg_temp_new_i32();
6288 tcg_gen_trunc_i64_i32(t, cpu_avrl[rD(ctx->opcode)]);
6289 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
6290 tcg_temp_free_i32(t);
6291}
6292
7a9b96cf
AJ		 6293/* Logical operations */
6294#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6295GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6296{ \
6297 if (unlikely(!ctx->altivec_enabled)) { \
6298 gen_exception(ctx, POWERPC_EXCP_VPU); \
6299 return; \
6300 } \
6301 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6302 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6303}
6304
6305GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6306GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6307GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6308GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6309GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6310
8e27dd6f
AJ		 6311#define GEN_VXFORM(name, opc2, opc3) \
6312GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6313{ \
6314 TCGv_ptr ra, rb, rd; \
6315 if (unlikely(!ctx->altivec_enabled)) { \
6316 gen_exception(ctx, POWERPC_EXCP_VPU); \
6317 return; \
6318 } \
6319 ra = gen_avr_ptr(rA(ctx->opcode)); \
6320 rb = gen_avr_ptr(rB(ctx->opcode)); \
6321 rd = gen_avr_ptr(rD(ctx->opcode)); \
6322 gen_helper_##name (rd, ra, rb); \
6323 tcg_temp_free_ptr(ra); \
6324 tcg_temp_free_ptr(rb); \
6325 tcg_temp_free_ptr(rd); \
6326}
6327
7872c51c
AJ		 6328GEN_VXFORM(vaddubm, 0, 0);
6329GEN_VXFORM(vadduhm, 0, 1);
6330GEN_VXFORM(vadduwm, 0, 2);
6331GEN_VXFORM(vsububm, 0, 16);
6332GEN_VXFORM(vsubuhm, 0, 17);
6333GEN_VXFORM(vsubuwm, 0, 18);
e4039339
AJ		 6334GEN_VXFORM(vmaxub, 1, 0);
6335GEN_VXFORM(vmaxuh, 1, 1);
6336GEN_VXFORM(vmaxuw, 1, 2);
6337GEN_VXFORM(vmaxsb, 1, 4);
6338GEN_VXFORM(vmaxsh, 1, 5);
6339GEN_VXFORM(vmaxsw, 1, 6);
6340GEN_VXFORM(vminub, 1, 8);
6341GEN_VXFORM(vminuh, 1, 9);
6342GEN_VXFORM(vminuw, 1, 10);
6343GEN_VXFORM(vminsb, 1, 12);
6344GEN_VXFORM(vminsh, 1, 13);
6345GEN_VXFORM(vminsw, 1, 14);
fab3cbe9
AJ		 6346GEN_VXFORM(vavgub, 1, 16);
6347GEN_VXFORM(vavguh, 1, 17);
6348GEN_VXFORM(vavguw, 1, 18);
6349GEN_VXFORM(vavgsb, 1, 20);
6350GEN_VXFORM(vavgsh, 1, 21);
6351GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 6352GEN_VXFORM(vmrghb, 6, 0);
6353GEN_VXFORM(vmrghh, 6, 1);
6354GEN_VXFORM(vmrghw, 6, 2);
6355GEN_VXFORM(vmrglb, 6, 4);
6356GEN_VXFORM(vmrglh, 6, 5);
6357GEN_VXFORM(vmrglw, 6, 6);
2c277908
AJ		 6358GEN_VXFORM(vmuloub, 4, 0);
6359GEN_VXFORM(vmulouh, 4, 1);
6360GEN_VXFORM(vmulosb, 4, 4);
6361GEN_VXFORM(vmulosh, 4, 5);
6362GEN_VXFORM(vmuleub, 4, 8);
6363GEN_VXFORM(vmuleuh, 4, 9);
6364GEN_VXFORM(vmulesb, 4, 12);
6365GEN_VXFORM(vmulesh, 4, 13);
d79f0809
AJ		 6366GEN_VXFORM(vslb, 2, 4);
6367GEN_VXFORM(vslh, 2, 5);
6368GEN_VXFORM(vslw, 2, 6);
07ef34c3
AJ		 6369GEN_VXFORM(vsrb, 2, 8);
6370GEN_VXFORM(vsrh, 2, 9);
6371GEN_VXFORM(vsrw, 2, 10);
6372GEN_VXFORM(vsrab, 2, 12);
6373GEN_VXFORM(vsrah, 2, 13);
6374GEN_VXFORM(vsraw, 2, 14);
7b239bec
AJ		 6375GEN_VXFORM(vslo, 6, 16);
6376GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 6377GEN_VXFORM(vaddcuw, 0, 6);
6378GEN_VXFORM(vsubcuw, 0, 22);
5ab09f33
AJ		 6379GEN_VXFORM(vaddubs, 0, 8);
6380GEN_VXFORM(vadduhs, 0, 9);
6381GEN_VXFORM(vadduws, 0, 10);
6382GEN_VXFORM(vaddsbs, 0, 12);
6383GEN_VXFORM(vaddshs, 0, 13);
6384GEN_VXFORM(vaddsws, 0, 14);
6385GEN_VXFORM(vsububs, 0, 24);
6386GEN_VXFORM(vsubuhs, 0, 25);
6387GEN_VXFORM(vsubuws, 0, 26);
6388GEN_VXFORM(vsubsbs, 0, 28);
6389GEN_VXFORM(vsubshs, 0, 29);
6390GEN_VXFORM(vsubsws, 0, 30);
5e1d0985
AJ		 6391GEN_VXFORM(vrlb, 2, 0);
6392GEN_VXFORM(vrlh, 2, 1);
6393GEN_VXFORM(vrlw, 2, 2);
d9430add
AJ		 6394GEN_VXFORM(vsl, 2, 7);
6395GEN_VXFORM(vsr, 2, 11);
5335a145
AJ		 6396GEN_VXFORM(vpkuhum, 7, 0);
6397GEN_VXFORM(vpkuwum, 7, 1);
6398GEN_VXFORM(vpkuhus, 7, 2);
6399GEN_VXFORM(vpkuwus, 7, 3);
6400GEN_VXFORM(vpkshus, 7, 4);
6401GEN_VXFORM(vpkswus, 7, 5);
6402GEN_VXFORM(vpkshss, 7, 6);
6403GEN_VXFORM(vpkswss, 7, 7);
1dd9ffb9 6404GEN_VXFORM(vpkpx, 7, 12);
8142cddd
AJ		 6405GEN_VXFORM(vsum4ubs, 4, 24);
6406GEN_VXFORM(vsum4sbs, 4, 28);
6407GEN_VXFORM(vsum4shs, 4, 25);
6408GEN_VXFORM(vsum2sws, 4, 26);
6409GEN_VXFORM(vsumsws, 4, 30);
fab3cbe9 6410
0cbcd906
AJ		 6411#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6412 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6413 { \
6414 TCGv_ptr ra, rb, rd; \
6415 if (unlikely(!ctx->altivec_enabled)) { \
6416 gen_exception(ctx, POWERPC_EXCP_VPU); \
6417 return; \
6418 } \
6419 ra = gen_avr_ptr(rA(ctx->opcode)); \
6420 rb = gen_avr_ptr(rB(ctx->opcode)); \
6421 rd = gen_avr_ptr(rD(ctx->opcode)); \
6422 gen_helper_##opname (rd, ra, rb); \
6423 tcg_temp_free_ptr(ra); \
6424 tcg_temp_free_ptr(rb); \
6425 tcg_temp_free_ptr(rd); \
6426 }
6427
6428#define GEN_VXRFORM(name, opc2, opc3) \
6429 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6430 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6431
1add6e23
AJ		 6432GEN_VXRFORM(vcmpequb, 3, 0)
6433GEN_VXRFORM(vcmpequh, 3, 1)
6434GEN_VXRFORM(vcmpequw, 3, 2)
6435GEN_VXRFORM(vcmpgtsb, 3, 12)
6436GEN_VXRFORM(vcmpgtsh, 3, 13)
6437GEN_VXRFORM(vcmpgtsw, 3, 14)
6438GEN_VXRFORM(vcmpgtub, 3, 8)
6439GEN_VXRFORM(vcmpgtuh, 3, 9)
6440GEN_VXRFORM(vcmpgtuw, 3, 10)
6441
c026766b
AJ		 6442#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6443 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6444 { \
6445 TCGv_ptr rd; \
6446 TCGv_i32 simm; \
6447 if (unlikely(!ctx->altivec_enabled)) { \
6448 gen_exception(ctx, POWERPC_EXCP_VPU); \
6449 return; \
6450 } \
6451 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6452 rd = gen_avr_ptr(rD(ctx->opcode)); \
6453 gen_helper_##name (rd, simm); \
6454 tcg_temp_free_i32(simm); \
6455 tcg_temp_free_ptr(rd); \
6456 }
6457
6458GEN_VXFORM_SIMM(vspltisb, 6, 12);
6459GEN_VXFORM_SIMM(vspltish, 6, 13);
6460GEN_VXFORM_SIMM(vspltisw, 6, 14);
6461
de5f2484
AJ		 6462#define GEN_VXFORM_NOA(name, opc2, opc3) \
6463 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6464 { \
6465 TCGv_ptr rb, rd; \
6466 if (unlikely(!ctx->altivec_enabled)) { \
6467 gen_exception(ctx, POWERPC_EXCP_VPU); \
6468 return; \
6469 } \
6470 rb = gen_avr_ptr(rB(ctx->opcode)); \
6471 rd = gen_avr_ptr(rD(ctx->opcode)); \
6472 gen_helper_##name (rd, rb); \
6473 tcg_temp_free_ptr(rb); \
6474 tcg_temp_free_ptr(rd); \
6475 }
6476
6cf1c6e5
AJ		 6477GEN_VXFORM_NOA(vupkhsb, 7, 8);
6478GEN_VXFORM_NOA(vupkhsh, 7, 9);
6479GEN_VXFORM_NOA(vupklsb, 7, 10);
6480GEN_VXFORM_NOA(vupklsh, 7, 11);
79f85c3a
AJ		 6481GEN_VXFORM_NOA(vupkhpx, 7, 13);
6482GEN_VXFORM_NOA(vupklpx, 7, 15);
6483
21d21583
AJ		 6484#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6485 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6486 { \
6487 TCGv_ptr rd; \
6488 TCGv_i32 simm; \
6489 if (unlikely(!ctx->altivec_enabled)) { \
6490 gen_exception(ctx, POWERPC_EXCP_VPU); \
6491 return; \
6492 } \
6493 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6494 rd = gen_avr_ptr(rD(ctx->opcode)); \
6495 gen_helper_##name (rd, simm); \
6496 tcg_temp_free_i32(simm); \
6497 tcg_temp_free_ptr(rd); \
6498 }
6499
27a4edb3
AJ		 6500#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6501 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6502 { \
6503 TCGv_ptr rb, rd; \
6504 TCGv_i32 uimm; \
6505 if (unlikely(!ctx->altivec_enabled)) { \
6506 gen_exception(ctx, POWERPC_EXCP_VPU); \
6507 return; \
6508 } \
6509 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6510 rb = gen_avr_ptr(rB(ctx->opcode)); \
6511 rd = gen_avr_ptr(rD(ctx->opcode)); \
6512 gen_helper_##name (rd, rb, uimm); \
6513 tcg_temp_free_i32(uimm); \
6514 tcg_temp_free_ptr(rb); \
6515 tcg_temp_free_ptr(rd); \
6516 }
6517
e4e6bee7
AJ		 6518GEN_VXFORM_UIMM(vspltb, 6, 8);
6519GEN_VXFORM_UIMM(vsplth, 6, 9);
6520GEN_VXFORM_UIMM(vspltw, 6, 10);
6521
cd633b10
AJ		 6522GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6523{
6524 TCGv_ptr ra, rb, rd;
6525 TCGv sh;
6526 if (unlikely(!ctx->altivec_enabled)) {
6527 gen_exception(ctx, POWERPC_EXCP_VPU);
6528 return;
6529 }
6530 ra = gen_avr_ptr(rA(ctx->opcode));
6531 rb = gen_avr_ptr(rB(ctx->opcode));
6532 rd = gen_avr_ptr(rD(ctx->opcode));
6533 sh = tcg_const_i32(VSH(ctx->opcode));
6534 gen_helper_vsldoi (rd, ra, rb, sh);
6535 tcg_temp_free_ptr(ra);
6536 tcg_temp_free_ptr(rb);
6537 tcg_temp_free_ptr(rd);
6538 tcg_temp_free(sh);
6539}
6540
707cec33
AJ		 6541#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6542 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6543 { \
6544 TCGv_ptr ra, rb, rc, rd; \
6545 if (unlikely(!ctx->altivec_enabled)) { \
6546 gen_exception(ctx, POWERPC_EXCP_VPU); \
6547 return; \
6548 } \
6549 ra = gen_avr_ptr(rA(ctx->opcode)); \
6550 rb = gen_avr_ptr(rB(ctx->opcode)); \
6551 rc = gen_avr_ptr(rC(ctx->opcode)); \
6552 rd = gen_avr_ptr(rD(ctx->opcode)); \
6553 if (Rc(ctx->opcode)) { \
6554 gen_helper_##name1 (rd, ra, rb, rc); \
6555 } else { \
6556 gen_helper_##name0 (rd, ra, rb, rc); \
6557 } \
6558 tcg_temp_free_ptr(ra); \
6559 tcg_temp_free_ptr(rb); \
6560 tcg_temp_free_ptr(rc); \
6561 tcg_temp_free_ptr(rd); \
6562 }
6563
b161ae27
AJ		 6564GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6565
bcd2ee23
AJ		 6566GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6567{
6568 TCGv_ptr ra, rb, rc, rd;
6569 if (unlikely(!ctx->altivec_enabled)) {
6570 gen_exception(ctx, POWERPC_EXCP_VPU);
6571 return;
6572 }
6573 ra = gen_avr_ptr(rA(ctx->opcode));
6574 rb = gen_avr_ptr(rB(ctx->opcode));
6575 rc = gen_avr_ptr(rC(ctx->opcode));
6576 rd = gen_avr_ptr(rD(ctx->opcode));
6577 gen_helper_vmladduhm(rd, ra, rb, rc);
6578 tcg_temp_free_ptr(ra);
6579 tcg_temp_free_ptr(rb);
6580 tcg_temp_free_ptr(rc);
6581 tcg_temp_free_ptr(rd);
6582}
6583
b04ae981 6584GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 6585GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 6586GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 6587GEN_VAFORM_PAIRED(vsel, vperm, 21)
b04ae981 6588
0487d6a8 6589/*** SPE extension ***/
0487d6a8 6590/* Register moves */
3cd7d1dd 6591
a7812ae4 6592static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6593#if defined(TARGET_PPC64)
6594 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6595#else
36aa55dc 6596 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6597#endif
f78fb44e 6598}
3cd7d1dd 6599
a7812ae4 6600static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6601#if defined(TARGET_PPC64)
6602 tcg_gen_mov_i64(cpu_gpr[reg], t);
6603#else
a7812ae4 6604 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6605 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6606 tcg_gen_shri_i64(tmp, t, 32);
6607 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6608 tcg_temp_free_i64(tmp);
3cd7d1dd 6609#endif
f78fb44e 6610}
3cd7d1dd 6611
0487d6a8
JM		 6612#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6613GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6614{ \
6615 if (Rc(ctx->opcode)) \
6616 gen_##name1(ctx); \
6617 else \
6618 gen_##name0(ctx); \
6619}
6620
6621/* Handler for undefined SPE opcodes */
b068d6a7 6622static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6623{
e06fcd75 6624 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 6625}
6626
57951c27
AJ		 6627/* SPE logic */
6628#if defined(TARGET_PPC64)
6629#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6630static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6631{ \
6632 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6633 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6634 return; \
6635 } \
57951c27
AJ		 6636 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6637 cpu_gpr[rB(ctx->opcode)]); \
6638}
6639#else
6640#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6641static always_inline void gen_##name (DisasContext *ctx) \
6642{ \
6643 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6644 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6645 return; \
6646 } \
6647 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6648 cpu_gpr[rB(ctx->opcode)]); \
6649 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6650 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6651}
57951c27
AJ		 6652#endif
6653
6654GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6655GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6656GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6657GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6658GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6659GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6660GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6661GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6662
57951c27
AJ		 6663/* SPE logic immediate */
6664#if defined(TARGET_PPC64)
6665#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6666static always_inline void gen_##name (DisasContext *ctx) \
6667{ \
6668 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6669 gen_exception(ctx, POWERPC_EXCP_APU); \
3d3a6a0a
AJ		 6670 return; \
6671 } \
a7812ae4
PB		 6672 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6673 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6674 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6675 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6676 tcg_opi(t0, t0, rB(ctx->opcode)); \
6677 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6678 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6679 tcg_temp_free_i64(t2); \
57951c27
AJ		 6680 tcg_opi(t1, t1, rB(ctx->opcode)); \
6681 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6682 tcg_temp_free_i32(t0); \
6683 tcg_temp_free_i32(t1); \
3d3a6a0a 6684}
57951c27
AJ		 6685#else
6686#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6687static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6688{ \
6689 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6690 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6691 return; \
6692 } \
57951c27
AJ		 6693 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6694 rB(ctx->opcode)); \
6695 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6696 rB(ctx->opcode)); \
0487d6a8 6697}
57951c27
AJ		 6698#endif
6699GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6700GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6701GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6702GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6703
57951c27
AJ		 6704/* SPE arithmetic */
6705#if defined(TARGET_PPC64)
6706#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6707static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6708{ \
6709 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6710 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6711 return; \
6712 } \
a7812ae4
PB		 6713 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6714 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6715 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6716 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6717 tcg_op(t0, t0); \
6718 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6719 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6720 tcg_temp_free_i64(t2); \
57951c27
AJ		 6721 tcg_op(t1, t1); \
6722 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6723 tcg_temp_free_i32(t0); \
6724 tcg_temp_free_i32(t1); \
0487d6a8 6725}
57951c27 6726#else
a7812ae4 6727#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6728static always_inline void gen_##name (DisasContext *ctx) \
6729{ \
6730 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6731 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6732 return; \
6733 } \
6734 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6735 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6736}
6737#endif
0487d6a8 6738
a7812ae4 6739static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6740{
6741 int l1 = gen_new_label();
6742 int l2 = gen_new_label();
0487d6a8 6743
57951c27
AJ		 6744 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6745 tcg_gen_neg_i32(ret, arg1);
6746 tcg_gen_br(l2);
6747 gen_set_label(l1);
a7812ae4 6748 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6749 gen_set_label(l2);
6750}
6751GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6752GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6753GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6754GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6755static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6756{
57951c27
AJ		 6757 tcg_gen_addi_i32(ret, arg1, 0x8000);
6758 tcg_gen_ext16u_i32(ret, ret);
6759}
6760GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6761GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6762GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6763
57951c27
AJ		 6764#if defined(TARGET_PPC64)
6765#define GEN_SPEOP_ARITH2(name, tcg_op) \
6766static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6767{ \
6768 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6769 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6770 return; \
6771 } \
a7812ae4
PB		 6772 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6773 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6774 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
501e23c4 6775 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6776 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6777 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6778 tcg_op(t0, t0, t2); \
6779 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6780 tcg_gen_trunc_i64_i32(t1, t3); \
6781 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6782 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6783 tcg_temp_free_i64(t3); \
57951c27 6784 tcg_op(t1, t1, t2); \
a7812ae4 6785 tcg_temp_free_i32(t2); \
57951c27 6786 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6787 tcg_temp_free_i32(t0); \
6788 tcg_temp_free_i32(t1); \
0487d6a8 6789}
57951c27
AJ		 6790#else
6791#define GEN_SPEOP_ARITH2(name, tcg_op) \
6792static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6793{ \
6794 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6795 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6796 return; \
6797 } \
57951c27
AJ		 6798 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6799 cpu_gpr[rB(ctx->opcode)]); \
6800 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6801 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6802}
57951c27 6803#endif
0487d6a8 6804
a7812ae4 6805static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6806{
a7812ae4 6807 TCGv_i32 t0;
57951c27 6808 int l1, l2;
0487d6a8 6809
57951c27
AJ		 6810 l1 = gen_new_label();
6811 l2 = gen_new_label();
a7812ae4 6812 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6813 /* No error here: 6 bits are used */
6814 tcg_gen_andi_i32(t0, arg2, 0x3F);
6815 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6816 tcg_gen_shr_i32(ret, arg1, t0);
6817 tcg_gen_br(l2);
6818 gen_set_label(l1);
6819 tcg_gen_movi_i32(ret, 0);
6820 tcg_gen_br(l2);
a7812ae4 6821 tcg_temp_free_i32(t0);
57951c27
AJ		 6822}
6823GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6824static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6825{
a7812ae4 6826 TCGv_i32 t0;
57951c27
AJ		 6827 int l1, l2;
6828
6829 l1 = gen_new_label();
6830 l2 = gen_new_label();
a7812ae4 6831 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6832 /* No error here: 6 bits are used */
6833 tcg_gen_andi_i32(t0, arg2, 0x3F);
6834 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6835 tcg_gen_sar_i32(ret, arg1, t0);
6836 tcg_gen_br(l2);
6837 gen_set_label(l1);
6838 tcg_gen_movi_i32(ret, 0);
6839 tcg_gen_br(l2);
a7812ae4 6840 tcg_temp_free_i32(t0);
57951c27
AJ		 6841}
6842GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6843static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6844{
a7812ae4 6845 TCGv_i32 t0;
57951c27
AJ		 6846 int l1, l2;
6847
6848 l1 = gen_new_label();
6849 l2 = gen_new_label();
a7812ae4 6850 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6851 /* No error here: 6 bits are used */
6852 tcg_gen_andi_i32(t0, arg2, 0x3F);
6853 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6854 tcg_gen_shl_i32(ret, arg1, t0);
6855 tcg_gen_br(l2);
6856 gen_set_label(l1);
6857 tcg_gen_movi_i32(ret, 0);
6858 tcg_gen_br(l2);
a7812ae4 6859 tcg_temp_free_i32(t0);
57951c27
AJ		 6860}
6861GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6862static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6863{
a7812ae4 6864 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6865 tcg_gen_andi_i32(t0, arg2, 0x1F);
6866 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6867 tcg_temp_free_i32(t0);
57951c27
AJ		 6868}
6869GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6870static always_inline void gen_evmergehi (DisasContext *ctx)
6871{
6872 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6873 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6874 return;
6875 }
6876#if defined(TARGET_PPC64)
a7812ae4
PB		 6877 TCGv t0 = tcg_temp_new();
6878 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6879 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6880 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6881 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6882 tcg_temp_free(t0);
6883 tcg_temp_free(t1);
6884#else
6885 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6886 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6887#endif
6888}
6889GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6890static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6891{
57951c27
AJ		 6892 tcg_gen_sub_i32(ret, arg2, arg1);
6893}
6894GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6895
57951c27
AJ		 6896/* SPE arithmetic immediate */
6897#if defined(TARGET_PPC64)
6898#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6899static always_inline void gen_##name (DisasContext *ctx) \
6900{ \
6901 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6902 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6903 return; \
6904 } \
a7812ae4
PB		 6905 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6906 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6907 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6908 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6909 tcg_op(t0, t0, rA(ctx->opcode)); \
6910 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6911 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 6912 tcg_temp_free_i64(t2); \
57951c27
AJ		 6913 tcg_op(t1, t1, rA(ctx->opcode)); \
6914 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6915 tcg_temp_free_i32(t0); \
6916 tcg_temp_free_i32(t1); \
57951c27
AJ		 6917}
6918#else
6919#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6920static always_inline void gen_##name (DisasContext *ctx) \
6921{ \
6922 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6923 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6924 return; \
6925 } \
6926 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6927 rA(ctx->opcode)); \
6928 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6929 rA(ctx->opcode)); \
6930}
6931#endif
6932GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6933GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6934
6935/* SPE comparison */
6936#if defined(TARGET_PPC64)
6937#define GEN_SPEOP_COMP(name, tcg_cond) \
6938static always_inline void gen_##name (DisasContext *ctx) \
6939{ \
6940 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6941 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6942 return; \
6943 } \
6944 int l1 = gen_new_label(); \
6945 int l2 = gen_new_label(); \
6946 int l3 = gen_new_label(); \
6947 int l4 = gen_new_label(); \
a7812ae4
PB		 6948 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6949 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6950 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6951 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6952 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6953 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6954 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6955 tcg_gen_br(l2); \
6956 gen_set_label(l1); \
6957 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6958 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6959 gen_set_label(l2); \
6960 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6961 tcg_gen_trunc_i64_i32(t0, t2); \
6962 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6963 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6964 tcg_temp_free_i64(t2); \
57951c27
AJ		 6965 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6966 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6967 ~(CRF_CH | CRF_CH_AND_CL)); \
6968 tcg_gen_br(l4); \
6969 gen_set_label(l3); \
6970 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6971 CRF_CH | CRF_CH_OR_CL); \
6972 gen_set_label(l4); \
a7812ae4
PB		 6973 tcg_temp_free_i32(t0); \
6974 tcg_temp_free_i32(t1); \
57951c27
AJ		 6975}
6976#else
6977#define GEN_SPEOP_COMP(name, tcg_cond) \
6978static always_inline void gen_##name (DisasContext *ctx) \
6979{ \
6980 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6981 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6982 return; \
6983 } \
6984 int l1 = gen_new_label(); \
6985 int l2 = gen_new_label(); \
6986 int l3 = gen_new_label(); \
6987 int l4 = gen_new_label(); \
6988 \
6989 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6990 cpu_gpr[rB(ctx->opcode)], l1); \
6991 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6992 tcg_gen_br(l2); \
6993 gen_set_label(l1); \
6994 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6995 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6996 gen_set_label(l2); \
6997 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6998 cpu_gprh[rB(ctx->opcode)], l3); \
6999 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7000 ~(CRF_CH | CRF_CH_AND_CL)); \
7001 tcg_gen_br(l4); \
7002 gen_set_label(l3); \
7003 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7004 CRF_CH | CRF_CH_OR_CL); \
7005 gen_set_label(l4); \
7006}
7007#endif
7008GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7009GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7010GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7011GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7012GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7013
7014/* SPE misc */
7015static always_inline void gen_brinc (DisasContext *ctx)
7016{
7017 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 7018 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7019 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 7020}
57951c27
AJ		 7021static always_inline void gen_evmergelo (DisasContext *ctx)
7022{
7023 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7024 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7025 return;
7026 }
7027#if defined(TARGET_PPC64)
a7812ae4
PB		 7028 TCGv t0 = tcg_temp_new();
7029 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7030 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7031 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7032 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7033 tcg_temp_free(t0);
7034 tcg_temp_free(t1);
7035#else
7036 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7037 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7038#endif
7039}
7040static always_inline void gen_evmergehilo (DisasContext *ctx)
7041{
7042 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7043 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7044 return;
7045 }
7046#if defined(TARGET_PPC64)
a7812ae4
PB		 7047 TCGv t0 = tcg_temp_new();
7048 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7049 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7050 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7051 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7052 tcg_temp_free(t0);
7053 tcg_temp_free(t1);
7054#else
7055 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7056 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7057#endif
7058}
7059static always_inline void gen_evmergelohi (DisasContext *ctx)
7060{
7061 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7062 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7063 return;
7064 }
7065#if defined(TARGET_PPC64)
a7812ae4
PB		 7066 TCGv t0 = tcg_temp_new();
7067 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7068 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7069 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7070 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7071 tcg_temp_free(t0);
7072 tcg_temp_free(t1);
7073#else
7074 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7075 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7076#endif
7077}
7078static always_inline void gen_evsplati (DisasContext *ctx)
7079{
38d14952 7080 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 7081
57951c27 7082#if defined(TARGET_PPC64)
38d14952 7083 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7084#else
7085 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7086 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7087#endif
7088}
b068d6a7 7089static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 7090{
38d14952 7091 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 7092
57951c27 7093#if defined(TARGET_PPC64)
38d14952 7094 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7095#else
7096 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7097 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7098#endif
0487d6a8
JM		 7099}
7100
57951c27
AJ		 7101static always_inline void gen_evsel (DisasContext *ctx)
7102{
7103 int l1 = gen_new_label();
7104 int l2 = gen_new_label();
7105 int l3 = gen_new_label();
7106 int l4 = gen_new_label();
a7812ae4 7107 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 7108#if defined(TARGET_PPC64)
a7812ae4
PB		 7109 TCGv t1 = tcg_temp_local_new();
7110 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 7111#endif
7112 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7113 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7114#if defined(TARGET_PPC64)
7115 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7116#else
7117 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7118#endif
7119 tcg_gen_br(l2);
7120 gen_set_label(l1);
7121#if defined(TARGET_PPC64)
7122 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7123#else
7124 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7125#endif
7126 gen_set_label(l2);
7127 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7128 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7129#if defined(TARGET_PPC64)
7130 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7131#else
7132 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7133#endif
7134 tcg_gen_br(l4);
7135 gen_set_label(l3);
7136#if defined(TARGET_PPC64)
7137 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7138#else
7139 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7140#endif
7141 gen_set_label(l4);
a7812ae4 7142 tcg_temp_free_i32(t0);
57951c27
AJ		 7143#if defined(TARGET_PPC64)
7144 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7145 tcg_temp_free(t1);
7146 tcg_temp_free(t2);
7147#endif
7148}
7149GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7150{
7151 gen_evsel(ctx);
7152}
7153GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7154{
7155 gen_evsel(ctx);
7156}
7157GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7158{
7159 gen_evsel(ctx);
7160}
7161GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7162{
7163 gen_evsel(ctx);
7164}
0487d6a8
JM		 7165
7166GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7167GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7168GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7169GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7170GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7171GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7172GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7173GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7174GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7175GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7176GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7177GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7178GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7179GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7180GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7181GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7182GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7183GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7184GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7185GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7186GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7187GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7188GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7189GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7190GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7191
6a6ae23f 7192/* SPE load and stores */
76db3ba4 7193static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 7194{
7195 target_ulong uimm = rB(ctx->opcode);
7196
76db3ba4 7197 if (rA(ctx->opcode) == 0) {
6a6ae23f 7198 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 7199 } else {
6a6ae23f 7200 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
76db3ba4
AJ		 7201#if defined(TARGET_PPC64)
7202 if (!ctx->sf_mode) {
7203 tcg_gen_ext32u_tl(EA, EA);
7204 }
7205#endif
7206 }
0487d6a8 7207}
6a6ae23f
AJ		 7208
7209static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7210{
7211#if defined(TARGET_PPC64)
76db3ba4 7212 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7213#else
7214 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 7215 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 7216 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7217 tcg_gen_shri_i64(t0, t0, 32);
7218 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7219 tcg_temp_free_i64(t0);
7220#endif
0487d6a8 7221}
6a6ae23f
AJ		 7222
7223static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7224{
0487d6a8 7225#if defined(TARGET_PPC64)
6a6ae23f 7226 TCGv t0 = tcg_temp_new();
76db3ba4 7227 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 7228 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 7229 gen_addr_add(ctx, addr, addr, 4);
7230 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 7231 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7232 tcg_temp_free(t0);
7233#else
76db3ba4
AJ		 7234 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7235 gen_addr_add(ctx, addr, addr, 4);
7236 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 7237#endif
0487d6a8 7238}
6a6ae23f
AJ		 7239
7240static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7241{
7242 TCGv t0 = tcg_temp_new();
7243#if defined(TARGET_PPC64)
76db3ba4 7244 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7245 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7246 gen_addr_add(ctx, addr, addr, 2);
7247 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7248 tcg_gen_shli_tl(t0, t0, 32);
7249 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7250 gen_addr_add(ctx, addr, addr, 2);
7251 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7252 tcg_gen_shli_tl(t0, t0, 16);
7253 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7254 gen_addr_add(ctx, addr, addr, 2);
7255 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7256 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7257#else
76db3ba4 7258 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7259 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7260 gen_addr_add(ctx, addr, addr, 2);
7261 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7262 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7263 gen_addr_add(ctx, addr, addr, 2);
7264 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7265 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7266 gen_addr_add(ctx, addr, addr, 2);
7267 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7268 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7269#endif
6a6ae23f 7270 tcg_temp_free(t0);
0487d6a8
JM		 7271}
7272
6a6ae23f
AJ		 7273static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7274{
7275 TCGv t0 = tcg_temp_new();
76db3ba4 7276 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7277#if defined(TARGET_PPC64)
7278 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7279 tcg_gen_shli_tl(t0, t0, 16);
7280 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7281#else
7282 tcg_gen_shli_tl(t0, t0, 16);
7283 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7284 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7285#endif
7286 tcg_temp_free(t0);
0487d6a8
JM		 7287}
7288
6a6ae23f
AJ		 7289static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7290{
7291 TCGv t0 = tcg_temp_new();
76db3ba4 7292 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7293#if defined(TARGET_PPC64)
7294 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7295 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7296#else
7297 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7298 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7299#endif
7300 tcg_temp_free(t0);
0487d6a8
JM		 7301}
7302
6a6ae23f
AJ		 7303static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7304{
7305 TCGv t0 = tcg_temp_new();
76db3ba4 7306 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7307#if defined(TARGET_PPC64)
7308 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7309 tcg_gen_ext32u_tl(t0, t0);
7310 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7311#else
7312 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7313 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7314#endif
7315 tcg_temp_free(t0);
7316}
7317
7318static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7319{
7320 TCGv t0 = tcg_temp_new();
7321#if defined(TARGET_PPC64)
76db3ba4 7322 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7323 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7324 gen_addr_add(ctx, addr, addr, 2);
7325 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7326 tcg_gen_shli_tl(t0, t0, 16);
7327 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7328#else
76db3ba4 7329 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7330 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7331 gen_addr_add(ctx, addr, addr, 2);
7332 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7333 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7334#endif
7335 tcg_temp_free(t0);
7336}
7337
7338static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7339{
7340#if defined(TARGET_PPC64)
7341 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 7342 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7343 gen_addr_add(ctx, addr, addr, 2);
7344 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7345 tcg_gen_shli_tl(t0, t0, 32);
7346 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7347 tcg_temp_free(t0);
7348#else
76db3ba4
AJ		 7349 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7350 gen_addr_add(ctx, addr, addr, 2);
7351 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7352#endif
7353}
7354
7355static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7356{
7357#if defined(TARGET_PPC64)
7358 TCGv t0 = tcg_temp_new();
76db3ba4 7359 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 7360 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7361 gen_addr_add(ctx, addr, addr, 2);
7362 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7363 tcg_gen_shli_tl(t0, t0, 32);
7364 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7365 tcg_temp_free(t0);
7366#else
76db3ba4
AJ		 7367 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7368 gen_addr_add(ctx, addr, addr, 2);
7369 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7370#endif
7371}
7372
7373static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7374{
7375 TCGv t0 = tcg_temp_new();
76db3ba4 7376 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 7377#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7378 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7379 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7380#else
7381 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7382 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7383#endif
7384 tcg_temp_free(t0);
7385}
7386
7387static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7388{
7389 TCGv t0 = tcg_temp_new();
7390#if defined(TARGET_PPC64)
76db3ba4 7391 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7392 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7393 tcg_gen_shli_tl(t0, t0, 32);
7394 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7395 gen_addr_add(ctx, addr, addr, 2);
7396 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7397 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7398 tcg_gen_shli_tl(t0, t0, 16);
7399 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7400#else
76db3ba4 7401 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7402 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7403 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7404 gen_addr_add(ctx, addr, addr, 2);
7405 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7406 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7407 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 7408#endif
6a6ae23f
AJ		 7409 tcg_temp_free(t0);
7410}
7411
7412static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7413{
7414#if defined(TARGET_PPC64)
76db3ba4 7415 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 7416#else
6a6ae23f
AJ		 7417 TCGv_i64 t0 = tcg_temp_new_i64();
7418 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 7419 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 7420 tcg_temp_free_i64(t0);
7421#endif
7422}
7423
7424static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7425{
0487d6a8 7426#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7427 TCGv t0 = tcg_temp_new();
7428 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7429 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7430 tcg_temp_free(t0);
7431#else
76db3ba4 7432 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7433#endif
76db3ba4
AJ		 7434 gen_addr_add(ctx, addr, addr, 4);
7435 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7436}
7437
7438static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7439{
7440 TCGv t0 = tcg_temp_new();
7441#if defined(TARGET_PPC64)
7442 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7443#else
7444 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7445#endif
76db3ba4
AJ		 7446 gen_qemu_st16(ctx, t0, addr);
7447 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 7448#if defined(TARGET_PPC64)
7449 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7450 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7451#else
76db3ba4 7452 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7453#endif
76db3ba4 7454 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7455 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7456 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7457 tcg_temp_free(t0);
76db3ba4
AJ		 7458 gen_addr_add(ctx, addr, addr, 2);
7459 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7460}
7461
7462static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7463{
7464 TCGv t0 = tcg_temp_new();
7465#if defined(TARGET_PPC64)
7466 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7467#else
7468 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7469#endif
76db3ba4
AJ		 7470 gen_qemu_st16(ctx, t0, addr);
7471 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7472 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7473 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7474 tcg_temp_free(t0);
7475}
7476
7477static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7478{
7479#if defined(TARGET_PPC64)
7480 TCGv t0 = tcg_temp_new();
7481 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7482 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7483 tcg_temp_free(t0);
7484#else
76db3ba4 7485 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7486#endif
76db3ba4
AJ		 7487 gen_addr_add(ctx, addr, addr, 2);
7488 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7489}
7490
7491static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7492{
7493#if defined(TARGET_PPC64)
7494 TCGv t0 = tcg_temp_new();
7495 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7496 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7497 tcg_temp_free(t0);
7498#else
76db3ba4 7499 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7500#endif
7501}
7502
7503static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7504{
76db3ba4 7505 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7506}
7507
7508#define GEN_SPEOP_LDST(name, opc2, sh) \
76db3ba4 7509GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6a6ae23f
AJ		 7510{ \
7511 TCGv t0; \
7512 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7513 gen_exception(ctx, POWERPC_EXCP_APU); \
6a6ae23f
AJ		 7514 return; \
7515 } \
76db3ba4 7516 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 7517 t0 = tcg_temp_new(); \
7518 if (Rc(ctx->opcode)) { \
76db3ba4 7519 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 7520 } else { \
76db3ba4 7521 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 7522 } \
7523 gen_op_##name(ctx, t0); \
7524 tcg_temp_free(t0); \
7525}
7526
7527GEN_SPEOP_LDST(evldd, 0x00, 3);
7528GEN_SPEOP_LDST(evldw, 0x01, 3);
7529GEN_SPEOP_LDST(evldh, 0x02, 3);
7530GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7531GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7532GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7533GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7534GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7535GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7536GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7537GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7538
7539GEN_SPEOP_LDST(evstdd, 0x10, 3);
7540GEN_SPEOP_LDST(evstdw, 0x11, 3);
7541GEN_SPEOP_LDST(evstdh, 0x12, 3);
7542GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7543GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7544GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7545GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7546
7547/* Multiply and add - TODO */
7548#if 0
7549GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7550GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7551GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7552GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7553GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7554GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7555GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7556GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7557GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7558GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7559GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7560GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7561
7562GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7563GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7564GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7565GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7566GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7567GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7568GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7569GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7570GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7571GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7572GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7573GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7574GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7575GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7576
7577GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7578GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7579GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7580GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7581GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7582GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7583
7584GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7585GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7586GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7587GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7588GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7589GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7590GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7591GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7592GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7593GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7594GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7595GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7596
7597GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7598GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7599GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7600GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7601GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7602
7603GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7604GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7605GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7606GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7607GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7608GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7609GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7610GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7611GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7612GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7613GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7614GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7615
7616GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7617GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7618GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7619GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7620GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7621#endif
7622
7623/*** SPE floating-point extension ***/
1c97856d
AJ		 7624#if defined(TARGET_PPC64)
7625#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7626static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7627{ \
1c97856d
AJ		 7628 TCGv_i32 t0; \
7629 TCGv t1; \
7630 t0 = tcg_temp_new_i32(); \
7631 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7632 gen_helper_##name(t0, t0); \
7633 t1 = tcg_temp_new(); \
7634 tcg_gen_extu_i32_tl(t1, t0); \
7635 tcg_temp_free_i32(t0); \
7636 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7637 0xFFFFFFFF00000000ULL); \
7638 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7639 tcg_temp_free(t1); \
0487d6a8 7640}
1c97856d
AJ		 7641#define GEN_SPEFPUOP_CONV_32_64(name) \
7642static always_inline void gen_##name (DisasContext *ctx) \
7643{ \
7644 TCGv_i32 t0; \
7645 TCGv t1; \
7646 t0 = tcg_temp_new_i32(); \
7647 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7648 t1 = tcg_temp_new(); \
7649 tcg_gen_extu_i32_tl(t1, t0); \
7650 tcg_temp_free_i32(t0); \
7651 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7652 0xFFFFFFFF00000000ULL); \
7653 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7654 tcg_temp_free(t1); \
7655}
7656#define GEN_SPEFPUOP_CONV_64_32(name) \
7657static always_inline void gen_##name (DisasContext *ctx) \
7658{ \
7659 TCGv_i32 t0 = tcg_temp_new_i32(); \
7660 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7661 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7662 tcg_temp_free_i32(t0); \
7663}
7664#define GEN_SPEFPUOP_CONV_64_64(name) \
7665static always_inline void gen_##name (DisasContext *ctx) \
7666{ \
7667 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7668}
7669#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7670static always_inline void gen_##name (DisasContext *ctx) \
7671{ \
1c97856d
AJ		 7672 TCGv_i32 t0, t1; \
7673 TCGv_i64 t2; \
57951c27 7674 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7675 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7676 return; \
7677 } \
1c97856d
AJ		 7678 t0 = tcg_temp_new_i32(); \
7679 t1 = tcg_temp_new_i32(); \
7680 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7681 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7682 gen_helper_##name(t0, t0, t1); \
7683 tcg_temp_free_i32(t1); \
7684 t2 = tcg_temp_new(); \
7685 tcg_gen_extu_i32_tl(t2, t0); \
7686 tcg_temp_free_i32(t0); \
7687 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7688 0xFFFFFFFF00000000ULL); \
7689 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7690 tcg_temp_free(t2); \
57951c27 7691}
1c97856d 7692#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7693static always_inline void gen_##name (DisasContext *ctx) \
7694{ \
7695 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7696 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7697 return; \
7698 } \
1c97856d
AJ		 7699 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7700 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7701}
1c97856d 7702#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7703static always_inline void gen_##name (DisasContext *ctx) \
7704{ \
1c97856d 7705 TCGv_i32 t0, t1; \
57951c27 7706 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7707 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7708 return; \
7709 } \
1c97856d
AJ		 7710 t0 = tcg_temp_new_i32(); \
7711 t1 = tcg_temp_new_i32(); \
7712 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7713 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7714 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7715 tcg_temp_free_i32(t0); \
7716 tcg_temp_free_i32(t1); \
7717}
7718#define GEN_SPEFPUOP_COMP_64(name) \
7719static always_inline void gen_##name (DisasContext *ctx) \
7720{ \
7721 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7722 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7723 return; \
7724 } \
7725 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7726 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7727}
7728#else
7729#define GEN_SPEFPUOP_CONV_32_32(name) \
7730static always_inline void gen_##name (DisasContext *ctx) \
7731{ \
7732 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7733}
1c97856d
AJ		 7734#define GEN_SPEFPUOP_CONV_32_64(name) \
7735static always_inline void gen_##name (DisasContext *ctx) \
7736{ \
7737 TCGv_i64 t0 = tcg_temp_new_i64(); \
7738 gen_load_gpr64(t0, rB(ctx->opcode)); \
7739 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7740 tcg_temp_free_i64(t0); \
7741}
7742#define GEN_SPEFPUOP_CONV_64_32(name) \
7743static always_inline void gen_##name (DisasContext *ctx) \
7744{ \
7745 TCGv_i64 t0 = tcg_temp_new_i64(); \
7746 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7747 gen_store_gpr64(rD(ctx->opcode), t0); \
7748 tcg_temp_free_i64(t0); \
7749}
7750#define GEN_SPEFPUOP_CONV_64_64(name) \
7751static always_inline void gen_##name (DisasContext *ctx) \
7752{ \
7753 TCGv_i64 t0 = tcg_temp_new_i64(); \
7754 gen_load_gpr64(t0, rB(ctx->opcode)); \
7755 gen_helper_##name(t0, t0); \
7756 gen_store_gpr64(rD(ctx->opcode), t0); \
7757 tcg_temp_free_i64(t0); \
7758}
7759#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7760static always_inline void gen_##name (DisasContext *ctx) \
7761{ \
7762 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7763 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7764 return; \
7765 } \
7766 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7767 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7768}
7769#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7770static always_inline void gen_##name (DisasContext *ctx) \
7771{ \
7772 TCGv_i64 t0, t1; \
7773 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7774 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7775 return; \
7776 } \
7777 t0 = tcg_temp_new_i64(); \
7778 t1 = tcg_temp_new_i64(); \
7779 gen_load_gpr64(t0, rA(ctx->opcode)); \
7780 gen_load_gpr64(t1, rB(ctx->opcode)); \
7781 gen_helper_##name(t0, t0, t1); \
7782 gen_store_gpr64(rD(ctx->opcode), t0); \
7783 tcg_temp_free_i64(t0); \
7784 tcg_temp_free_i64(t1); \
7785}
7786#define GEN_SPEFPUOP_COMP_32(name) \
7787static always_inline void gen_##name (DisasContext *ctx) \
7788{ \
7789 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7790 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7791 return; \
7792 } \
7793 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7794 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7795}
7796#define GEN_SPEFPUOP_COMP_64(name) \
7797static always_inline void gen_##name (DisasContext *ctx) \
7798{ \
7799 TCGv_i64 t0, t1; \
7800 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7801 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7802 return; \
7803 } \
7804 t0 = tcg_temp_new_i64(); \
7805 t1 = tcg_temp_new_i64(); \
7806 gen_load_gpr64(t0, rA(ctx->opcode)); \
7807 gen_load_gpr64(t1, rB(ctx->opcode)); \
7808 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7809 tcg_temp_free_i64(t0); \
7810 tcg_temp_free_i64(t1); \
7811}
7812#endif
57951c27 7813
0487d6a8
JM		 7814/* Single precision floating-point vectors operations */
7815/* Arithmetic */
1c97856d
AJ		 7816GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7817GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7818GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7819GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7820static always_inline void gen_evfsabs (DisasContext *ctx)
7821{
7822 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7823 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7824 return;
7825 }
7826#if defined(TARGET_PPC64)
7827 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7828#else
7829 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7830 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7831#endif
7832}
7833static always_inline void gen_evfsnabs (DisasContext *ctx)
7834{
7835 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7836 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7837 return;
7838 }
7839#if defined(TARGET_PPC64)
7840 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7841#else
7842 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7843 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7844#endif
7845}
7846static always_inline void gen_evfsneg (DisasContext *ctx)
7847{
7848 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7849 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7850 return;
7851 }
7852#if defined(TARGET_PPC64)
7853 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7854#else
7855 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7856 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7857#endif
7858}
7859
0487d6a8 7860/* Conversion */
1c97856d
AJ		 7861GEN_SPEFPUOP_CONV_64_64(evfscfui);
7862GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7863GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7864GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7865GEN_SPEFPUOP_CONV_64_64(evfsctui);
7866GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7867GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7868GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7869GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7870GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7871
0487d6a8 7872/* Comparison */
1c97856d
AJ		 7873GEN_SPEFPUOP_COMP_64(evfscmpgt);
7874GEN_SPEFPUOP_COMP_64(evfscmplt);
7875GEN_SPEFPUOP_COMP_64(evfscmpeq);
7876GEN_SPEFPUOP_COMP_64(evfststgt);
7877GEN_SPEFPUOP_COMP_64(evfststlt);
7878GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7879
7880/* Opcodes definitions */
7881GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7882GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7883GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7884GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7885GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7886GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7887GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7888GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7889GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7890GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7891GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7892GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7893GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7894GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7895
7896/* Single precision floating-point operations */
7897/* Arithmetic */
1c97856d
AJ		 7898GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7899GEN_SPEFPUOP_ARITH2_32_32(efssub);
7900GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7901GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7902static always_inline void gen_efsabs (DisasContext *ctx)
7903{
7904 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7905 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7906 return;
7907 }
7908 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7909}
7910static always_inline void gen_efsnabs (DisasContext *ctx)
7911{
7912 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7913 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7914 return;
7915 }
7916 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7917}
7918static always_inline void gen_efsneg (DisasContext *ctx)
7919{
7920 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7921 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7922 return;
7923 }
7924 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7925}
7926
0487d6a8 7927/* Conversion */
1c97856d
AJ		 7928GEN_SPEFPUOP_CONV_32_32(efscfui);
7929GEN_SPEFPUOP_CONV_32_32(efscfsi);
7930GEN_SPEFPUOP_CONV_32_32(efscfuf);
7931GEN_SPEFPUOP_CONV_32_32(efscfsf);
7932GEN_SPEFPUOP_CONV_32_32(efsctui);
7933GEN_SPEFPUOP_CONV_32_32(efsctsi);
7934GEN_SPEFPUOP_CONV_32_32(efsctuf);
7935GEN_SPEFPUOP_CONV_32_32(efsctsf);
7936GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7937GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7938GEN_SPEFPUOP_CONV_32_64(efscfd);
7939
0487d6a8 7940/* Comparison */
1c97856d
AJ		 7941GEN_SPEFPUOP_COMP_32(efscmpgt);
7942GEN_SPEFPUOP_COMP_32(efscmplt);
7943GEN_SPEFPUOP_COMP_32(efscmpeq);
7944GEN_SPEFPUOP_COMP_32(efststgt);
7945GEN_SPEFPUOP_COMP_32(efststlt);
7946GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7947
7948/* Opcodes definitions */
05332d70 7949GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7950GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7951GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7952GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7953GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7954GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7955GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7956GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7957GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7958GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7959GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7960GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7961GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7962GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7963
7964/* Double precision floating-point operations */
7965/* Arithmetic */
1c97856d
AJ		 7966GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7967GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7968GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7969GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7970static always_inline void gen_efdabs (DisasContext *ctx)
7971{
7972 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7973 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7974 return;
7975 }
7976#if defined(TARGET_PPC64)
7977 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7978#else
7979 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7980#endif
7981}
7982static always_inline void gen_efdnabs (DisasContext *ctx)
7983{
7984 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7985 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7986 return;
7987 }
7988#if defined(TARGET_PPC64)
7989 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7990#else
7991 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7992#endif
7993}
7994static always_inline void gen_efdneg (DisasContext *ctx)
7995{
7996 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7997 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7998 return;
7999 }
8000#if defined(TARGET_PPC64)
8001 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8002#else
8003 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8004#endif
8005}
8006
0487d6a8 8007/* Conversion */
1c97856d
AJ		 8008GEN_SPEFPUOP_CONV_64_32(efdcfui);
8009GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8010GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8011GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8012GEN_SPEFPUOP_CONV_32_64(efdctui);
8013GEN_SPEFPUOP_CONV_32_64(efdctsi);
8014GEN_SPEFPUOP_CONV_32_64(efdctuf);
8015GEN_SPEFPUOP_CONV_32_64(efdctsf);
8016GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8017GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8018GEN_SPEFPUOP_CONV_64_32(efdcfs);
8019GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8020GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8021GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8022GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 8023
0487d6a8 8024/* Comparison */
1c97856d
AJ		 8025GEN_SPEFPUOP_COMP_64(efdcmpgt);
8026GEN_SPEFPUOP_COMP_64(efdcmplt);
8027GEN_SPEFPUOP_COMP_64(efdcmpeq);
8028GEN_SPEFPUOP_COMP_64(efdtstgt);
8029GEN_SPEFPUOP_COMP_64(efdtstlt);
8030GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 8031
8032/* Opcodes definitions */
8033GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
8034GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
8035GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
8036GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
8037GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
8038GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
8039GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
8040GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
8041GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
8042GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
8043GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
8044GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
8045GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
8046GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
8047GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
8048GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 8049
79aceca5
FB		 8050/* End opcode list */
8051GEN_OPCODE_MARK(end);
8052
3fc6c082 8053#include "translate_init.c"
0411a972 8054#include "helper_regs.h"
79aceca5 8055
9a64fbe4 8056/*****************************************************************************/
3fc6c082 8057/* Misc PowerPC helpers */
36081602
JM		 8058void cpu_dump_state (CPUState *env, FILE *f,
8059 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8060 int flags)
79aceca5 8061{
3fc6c082
FB		 8062#define RGPL 4
8063#define RFPL 4
3fc6c082 8064
79aceca5
FB		 8065 int i;
8066
077fc206 8067 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 8068 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 8069 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8070 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 8071#if !defined(NO_TIMER_DUMP)
077fc206 8072 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 8073#if !defined(CONFIG_USER_ONLY)
8074 "DECR %08x"
8075#endif
8076 "\n",
077fc206 8077 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 8078#if !defined(CONFIG_USER_ONLY)
8079 , cpu_ppc_load_decr(env)
8080#endif
8081 );
077fc206 8082#endif
76a66253 8083 for (i = 0; i < 32; i++) {
3fc6c082
FB		 8084 if ((i & (RGPL - 1)) == 0)
8085 cpu_fprintf(f, "GPR%02d", i);
6b542af7 8086 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 8087 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 8088 cpu_fprintf(f, "\n");
76a66253 8089 }
3fc6c082 8090 cpu_fprintf(f, "CR ");
76a66253 8091 for (i = 0; i < 8; i++)
7fe48483
FB		 8092 cpu_fprintf(f, "%01x", env->crf[i]);
8093 cpu_fprintf(f, " [");
76a66253
JM		 8094 for (i = 0; i < 8; i++) {
8095 char a = '-';
8096 if (env->crf[i] & 0x08)
8097 a = 'L';
8098 else if (env->crf[i] & 0x04)
8099 a = 'G';
8100 else if (env->crf[i] & 0x02)
8101 a = 'E';
7fe48483 8102 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 8103 }
6b542af7 8104 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 8105 for (i = 0; i < 32; i++) {
8106 if ((i & (RFPL - 1)) == 0)
8107 cpu_fprintf(f, "FPR%02d", i);
26a76461 8108 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 8109 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 8110 cpu_fprintf(f, "\n");
79aceca5 8111 }
7889270a 8112 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
f2e63a42 8113#if !defined(CONFIG_USER_ONLY)
6b542af7 8114 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 8115 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 8116#endif
79aceca5 8117
3fc6c082
FB		 8118#undef RGPL
8119#undef RFPL
79aceca5
FB		 8120}
8121
76a66253
JM		 8122void cpu_dump_statistics (CPUState *env, FILE*f,
8123 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8124 int flags)
8125{
8126#if defined(DO_PPC_STATISTICS)
8127 opc_handler_t **t1, **t2, **t3, *handler;
8128 int op1, op2, op3;
8129
8130 t1 = env->opcodes;
8131 for (op1 = 0; op1 < 64; op1++) {
8132 handler = t1[op1];
8133 if (is_indirect_opcode(handler)) {
8134 t2 = ind_table(handler);
8135 for (op2 = 0; op2 < 32; op2++) {
8136 handler = t2[op2];
8137 if (is_indirect_opcode(handler)) {
8138 t3 = ind_table(handler);
8139 for (op3 = 0; op3 < 32; op3++) {
8140 handler = t3[op3];
8141 if (handler->count == 0)
8142 continue;
8143 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8144 "%016llx %lld\n",
8145 op1, op2, op3, op1, (op3 << 5) | op2,
8146 handler->oname,
8147 handler->count, handler->count);
8148 }
8149 } else {
8150 if (handler->count == 0)
8151 continue;
8152 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8153 "%016llx %lld\n",
8154 op1, op2, op1, op2, handler->oname,
8155 handler->count, handler->count);
8156 }
8157 }
8158 } else {
8159 if (handler->count == 0)
8160 continue;
8161 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8162 op1, op1, handler->oname,
8163 handler->count, handler->count);
8164 }
8165 }
8166#endif
8167}
8168
9a64fbe4 8169/*****************************************************************************/
2cfc5f17
TS		 8170static always_inline void gen_intermediate_code_internal (CPUState *env,
8171 TranslationBlock *tb,
8172 int search_pc)
79aceca5 8173{
9fddaa0c 8174 DisasContext ctx, *ctxp = &ctx;
79aceca5 8175 opc_handler_t **table, *handler;
0fa85d43 8176 target_ulong pc_start;
79aceca5 8177 uint16_t *gen_opc_end;
a1d1bb31 8178 CPUBreakpoint *bp;
79aceca5 8179 int j, lj = -1;
2e70f6ef
PB		 8180 int num_insns;
8181 int max_insns;
79aceca5
FB		 8182
8183 pc_start = tb->pc;
79aceca5 8184 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
046d6672 8185 ctx.nip = pc_start;
79aceca5 8186 ctx.tb = tb;
e1833e1f 8187 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 8188 ctx.spr_cb = env->spr_cb;
76db3ba4
AJ		 8189 ctx.mem_idx = env->mmu_idx;
8190 ctx.access_type = -1;
8191 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 8192#if defined(TARGET_PPC64)
8193 ctx.sf_mode = msr_sf;
9a64fbe4 8194#endif
3cc62370 8195 ctx.fpu_enabled = msr_fp;
a9d9eb8f 8196 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 8197 ctx.spe_enabled = msr_spe;
8198 else
8199 ctx.spe_enabled = 0;
a9d9eb8f
JM		 8200 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8201 ctx.altivec_enabled = msr_vr;
8202 else
8203 ctx.altivec_enabled = 0;
d26bfc9a 8204 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 8205 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 8206 else
8cbcb4fa 8207 ctx.singlestep_enabled = 0;
d26bfc9a 8208 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 8209 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8210 if (unlikely(env->singlestep_enabled))
8211 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 8212#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 8213 /* Single step trace mode */
8214 msr_se = 1;
8215#endif
2e70f6ef
PB		 8216 num_insns = 0;
8217 max_insns = tb->cflags & CF_COUNT_MASK;
8218 if (max_insns == 0)
8219 max_insns = CF_COUNT_MASK;
8220
8221 gen_icount_start();
9a64fbe4 8222 /* Set env in case of segfault during code fetch */
e1833e1f 8223 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 8224 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8225 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 8226 if (bp->pc == ctx.nip) {
e06fcd75 8227 gen_debug_exception(ctxp);
ea4e754f
FB		 8228 break;
8229 }
8230 }
8231 }
76a66253 8232 if (unlikely(search_pc)) {
79aceca5
FB		 8233 j = gen_opc_ptr - gen_opc_buf;
8234 if (lj < j) {
8235 lj++;
8236 while (lj < j)
8237 gen_opc_instr_start[lj++] = 0;
046d6672 8238 gen_opc_pc[lj] = ctx.nip;
79aceca5 8239 gen_opc_instr_start[lj] = 1;
2e70f6ef 8240 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 8241 }
8242 }
d12d51d5
AL		 8243 LOG_DISAS("----------------\n");
8244 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8245 ctx.nip, ctx.mem_idx, (int)msr_ir);
2e70f6ef
PB		 8246 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8247 gen_io_start();
76db3ba4 8248 if (unlikely(ctx.le_mode)) {
056401ea
JM		 8249 ctx.opcode = bswap32(ldl_code(ctx.nip));
8250 } else {
8251 ctx.opcode = ldl_code(ctx.nip);
111bfab3 8252 }
d12d51d5 8253 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 8254 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 8255 opc3(ctx.opcode), little_endian ? "little" : "big");
046d6672 8256 ctx.nip += 4;
3fc6c082 8257 table = env->opcodes;
2e70f6ef 8258 num_insns++;
79aceca5
FB		 8259 handler = table[opc1(ctx.opcode)];
8260 if (is_indirect_opcode(handler)) {
8261 table = ind_table(handler);
8262 handler = table[opc2(ctx.opcode)];
8263 if (is_indirect_opcode(handler)) {
8264 table = ind_table(handler);
8265 handler = table[opc3(ctx.opcode)];
8266 }
8267 }
8268 /* Is opcode *REALLY* valid ? */
76a66253 8269 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 8270 if (loglevel != 0) {
76a66253 8271 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 8272 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 8273 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8274 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 8275 } else {
8276 printf("invalid/unsupported opcode: "
6b542af7 8277 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 8278 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8279 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 8280 }
76a66253
JM		 8281 } else {
8282 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 8283 if (loglevel != 0) {
79aceca5 8284 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 8285 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 8286 ctx.opcode & handler->inval, opc1(ctx.opcode),
8287 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8288 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 8289 } else {
8290 printf("invalid bits: %08x for opcode: "
6b542af7 8291 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 8292 ctx.opcode & handler->inval, opc1(ctx.opcode),
8293 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8294 ctx.opcode, ctx.nip - 4);
76a66253 8295 }
e06fcd75 8296 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 8297 break;
79aceca5 8298 }
79aceca5 8299 }
4b3686fa 8300 (*(handler->handler))(&ctx);
76a66253
JM		 8301#if defined(DO_PPC_STATISTICS)
8302 handler->count++;
8303#endif
9a64fbe4 8304 /* Check trace mode exceptions */
8cbcb4fa
AJ		 8305 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8306 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8307 ctx.exception != POWERPC_SYSCALL &&
8308 ctx.exception != POWERPC_EXCP_TRAP &&
8309 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 8310 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 8311 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 8312 (env->singlestep_enabled) ||
8313 num_insns >= max_insns)) {
d26bfc9a
JM		 8314 /* if we reach a page boundary or are single stepping, stop
8315 * generation
8316 */
8dd4983c 8317 break;
76a66253 8318 }
3fc6c082
FB		 8319#if defined (DO_SINGLE_STEP)
8320 break;
8321#endif
8322 }
2e70f6ef
PB		 8323 if (tb->cflags & CF_LAST_IO)
8324 gen_io_end();
e1833e1f 8325 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 8326 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 8327 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa 8328 if (unlikely(env->singlestep_enabled)) {
e06fcd75 8329 gen_debug_exception(ctxp);
8cbcb4fa 8330 }
76a66253 8331 /* Generate the return instruction */
57fec1fe 8332 tcg_gen_exit_tb(0);
9a64fbe4 8333 }
2e70f6ef 8334 gen_icount_end(tb, num_insns);
79aceca5 8335 *gen_opc_ptr = INDEX_op_end;
76a66253 8336 if (unlikely(search_pc)) {
9a64fbe4
FB		 8337 j = gen_opc_ptr - gen_opc_buf;
8338 lj++;
8339 while (lj <= j)
8340 gen_opc_instr_start[lj++] = 0;
9a64fbe4 8341 } else {
046d6672 8342 tb->size = ctx.nip - pc_start;
2e70f6ef 8343 tb->icount = num_insns;
9a64fbe4 8344 }
d9bce9d9 8345#if defined(DEBUG_DISAS)
9fddaa0c 8346 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 8347 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 8348 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 8349 }
8350 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 8351 int flags;
237c0af0 8352 flags = env->bfd_mach;
76db3ba4 8353 flags |= ctx.le_mode << 16;
0fa85d43 8354 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 8355 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 8356 fprintf(logfile, "\n");
9fddaa0c 8357 }
79aceca5 8358#endif
79aceca5
FB		 8359}
8360
2cfc5f17 8361void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 8362{
2cfc5f17 8363 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 8364}
8365
2cfc5f17 8366void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 8367{
2cfc5f17 8368 gen_intermediate_code_internal(env, tb, 1);
79aceca5 8369}
d2856f1a
AJ		 8370
8371void gen_pc_load(CPUState *env, TranslationBlock *tb,
8372 unsigned long searched_pc, int pc_pos, void *puc)
8373{
d2856f1a 8374 env->nip = gen_opc_pc[pc_pos];
d2856f1a 8375}
Qemu copy for testing