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Revert "target-ppc: use -Werror to make sure no new warning is added"
[qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
e8fc4fa7 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
7c58044c 44//#define OPTIMIZE_FPRF_UPDATE
79aceca5 45
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 52#if !defined(TARGET_PPC64)
1d542695 53 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 54#endif
a5e26afa 55 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
f78fb44e
AJ		 58static TCGv cpu_gpr[32];
59#if !defined(TARGET_PPC64)
60static TCGv cpu_gprh[32];
61#endif
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64static TCGv_i32 cpu_crf[8];
bd568f18 65static TCGv cpu_nip;
6527f6ea 66static TCGv cpu_msr;
cfdcd37a
AJ		 67static TCGv cpu_ctr;
68static TCGv cpu_lr;
3d7b417e 69static TCGv cpu_xer;
cf360a32 70static TCGv cpu_reserve;
a7812ae4 71static TCGv_i32 cpu_fpscr;
a7859e89 72static TCGv_i32 cpu_access_type;
f78fb44e 73
2e70f6ef
PB		 74#include "gen-icount.h"
75
76void ppc_translate_init(void)
77{
f78fb44e
AJ		 78 int i;
79 char* p;
b2437bf2 80 static int done_init = 0;
f78fb44e 81
2e70f6ef
PB		 82 if (done_init)
83 return;
f78fb44e 84
a7812ae4 85 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 86
f78fb44e 87 p = cpu_reg_names;
47e4661c
AJ		 88
89 for (i = 0; i < 8; i++) {
90 sprintf(p, "crf%d", i);
a7812ae4
PB		 91 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
92 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 93 p += 5;
94 }
95
f78fb44e
AJ		 96 for (i = 0; i < 32; i++) {
97 sprintf(p, "r%d", i);
a7812ae4 98 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 99 offsetof(CPUState, gpr[i]), p);
100 p += (i < 10) ? 3 : 4;
101#if !defined(TARGET_PPC64)
102 sprintf(p, "r%dH", i);
a7812ae4
PB		 103 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
104 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 105 p += (i < 10) ? 4 : 5;
106#endif
1d542695 107
a5e26afa 108 sprintf(p, "fp%d", i);
a7812ae4
PB		 109 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
110 offsetof(CPUState, fpr[i]), p);
ec1ac72d 111 p += (i < 10) ? 4 : 5;
a5e26afa 112
1d542695 113 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 114#ifdef WORDS_BIGENDIAN
115 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
116 offsetof(CPUState, avr[i].u64[0]), p);
117#else
a7812ae4 118 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 119 offsetof(CPUState, avr[i].u64[1]), p);
120#endif
1d542695 121 p += (i < 10) ? 6 : 7;
ec1ac72d 122
1d542695 123 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 124#ifdef WORDS_BIGENDIAN
125 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
126 offsetof(CPUState, avr[i].u64[1]), p);
127#else
a7812ae4 128 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 129 offsetof(CPUState, avr[i].u64[0]), p);
130#endif
1d542695 131 p += (i < 10) ? 6 : 7;
f78fb44e 132 }
f10dc08e 133
a7812ae4 134 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 135 offsetof(CPUState, nip), "nip");
136
6527f6ea
AJ		 137 cpu_msr = tcg_global_mem_new(TCG_AREG0,
138 offsetof(CPUState, msr), "msr");
139
a7812ae4 140 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 141 offsetof(CPUState, ctr), "ctr");
142
a7812ae4 143 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 144 offsetof(CPUState, lr), "lr");
145
a7812ae4 146 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 147 offsetof(CPUState, xer), "xer");
148
cf360a32
AJ		 149 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUState, reserve), "reserve");
151
a7812ae4
PB		 152 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
153 offsetof(CPUState, fpscr), "fpscr");
e1571908 154
a7859e89
AJ		 155 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
156 offsetof(CPUState, access_type), "access_type");
157
f10dc08e 158 /* register helpers */
a7812ae4 159#define GEN_HELPER 2
f10dc08e
AJ		 160#include "helper.h"
161
2e70f6ef
PB		 162 done_init = 1;
163}
164
7c58044c
JM		 165#if defined(OPTIMIZE_FPRF_UPDATE)
166static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
167static uint16_t **gen_fprf_ptr;
168#endif
79aceca5 169
79aceca5
FB		 170/* internal defines */
171typedef struct DisasContext {
172 struct TranslationBlock *tb;
0fa85d43 173 target_ulong nip;
79aceca5 174 uint32_t opcode;
9a64fbe4 175 uint32_t exception;
3cc62370
FB		 176 /* Routine used to access memory */
177 int mem_idx;
76db3ba4 178 int access_type;
3cc62370 179 /* Translation flags */
76db3ba4 180 int le_mode;
d9bce9d9
JM		 181#if defined(TARGET_PPC64)
182 int sf_mode;
9a64fbe4 183#endif
3cc62370 184 int fpu_enabled;
a9d9eb8f 185 int altivec_enabled;
0487d6a8 186 int spe_enabled;
3fc6c082 187 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 188 int singlestep_enabled;
79aceca5
FB		 189} DisasContext;
190
3fc6c082 191struct opc_handler_t {
79aceca5
FB		 192 /* invalid bits */
193 uint32_t inval;
9a64fbe4 194 /* instruction type */
0487d6a8 195 uint64_t type;
79aceca5
FB		 196 /* handler */
197 void (*handler)(DisasContext *ctx);
a750fc0b 198#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 199 const char *oname;
a750fc0b
JM		 200#endif
201#if defined(DO_PPC_STATISTICS)
76a66253
JM		 202 uint64_t count;
203#endif
3fc6c082 204};
79aceca5 205
7c58044c
JM		 206static always_inline void gen_reset_fpstatus (void)
207{
208#ifdef CONFIG_SOFTFLOAT
a44d2ce1 209 gen_helper_reset_fpstatus();
7c58044c
JM		 210#endif
211}
212
0f2f39c2 213static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 214{
0f2f39c2 215 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 216
7c58044c
JM		 217 if (set_fprf != 0) {
218 /* This case might be optimized later */
219#if defined(OPTIMIZE_FPRF_UPDATE)
220 *gen_fprf_ptr++ = gen_opc_ptr;
221#endif
0f2f39c2 222 tcg_gen_movi_i32(t0, 1);
af12906f 223 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 224 if (unlikely(set_rc)) {
0f2f39c2 225 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 226 }
af12906f 227 gen_helper_float_check_status();
7c58044c
JM		 228 } else if (unlikely(set_rc)) {
229 /* We always need to compute fpcc */
0f2f39c2 230 tcg_gen_movi_i32(t0, 0);
af12906f 231 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 232 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 233 }
af12906f 234
0f2f39c2 235 tcg_temp_free_i32(t0);
7c58044c
JM		 236}
237
238static always_inline void gen_optimize_fprf (void)
239{
240#if defined(OPTIMIZE_FPRF_UPDATE)
241 uint16_t **ptr;
242
243 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
244 *ptr = INDEX_op_nop1;
245 gen_fprf_ptr = gen_fprf_buf;
246#endif
247}
248
76db3ba4 249static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
a7859e89 250{
76db3ba4
AJ		 251 if (ctx->access_type != access_type) {
252 tcg_gen_movi_i32(cpu_access_type, access_type);
253 ctx->access_type = access_type;
254 }
a7859e89
AJ		 255}
256
b068d6a7 257static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 258{
259#if defined(TARGET_PPC64)
260 if (ctx->sf_mode)
bd568f18 261 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 262 else
263#endif
bd568f18 264 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 265}
266
e06fcd75
AJ		 267static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
268{
269 TCGv_i32 t0, t1;
270 if (ctx->exception == POWERPC_EXCP_NONE) {
271 gen_update_nip(ctx, ctx->nip);
272 }
273 t0 = tcg_const_i32(excp);
274 t1 = tcg_const_i32(error);
275 gen_helper_raise_exception_err(t0, t1);
276 tcg_temp_free_i32(t0);
277 tcg_temp_free_i32(t1);
278 ctx->exception = (excp);
279}
e1833e1f 280
e06fcd75
AJ		 281static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
282{
283 TCGv_i32 t0;
284 if (ctx->exception == POWERPC_EXCP_NONE) {
285 gen_update_nip(ctx, ctx->nip);
286 }
287 t0 = tcg_const_i32(excp);
288 gen_helper_raise_exception(t0);
289 tcg_temp_free_i32(t0);
290 ctx->exception = (excp);
291}
e1833e1f 292
e06fcd75
AJ		 293static always_inline void gen_debug_exception (DisasContext *ctx)
294{
295 TCGv_i32 t0;
296 gen_update_nip(ctx, ctx->nip);
297 t0 = tcg_const_i32(EXCP_DEBUG);
298 gen_helper_raise_exception(t0);
299 tcg_temp_free_i32(t0);
300}
9a64fbe4 301
e06fcd75
AJ		 302static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
303{
304 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
305}
a9d9eb8f 306
f24e5695 307/* Stop translation */
e06fcd75 308static always_inline void gen_stop_exception (DisasContext *ctx)
3fc6c082 309{
d9bce9d9 310 gen_update_nip(ctx, ctx->nip);
e1833e1f 311 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 312}
313
f24e5695 314/* No need to update nip here, as execution flow will change */
e06fcd75 315static always_inline void gen_sync_exception (DisasContext *ctx)
2be0071f 316{
e1833e1f 317 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 318}
319
79aceca5
FB		 320#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
321static void gen_##name (DisasContext *ctx); \
322GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
323static void gen_##name (DisasContext *ctx)
324
c7697e1f
JM		 325#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
326static void gen_##name (DisasContext *ctx); \
327GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
328static void gen_##name (DisasContext *ctx)
329
79aceca5
FB		 330typedef struct opcode_t {
331 unsigned char opc1, opc2, opc3;
1235fc06 332#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 333 unsigned char pad[5];
334#else
335 unsigned char pad[1];
336#endif
79aceca5 337 opc_handler_t handler;
b55266b5 338 const char *oname;
79aceca5
FB		 339} opcode_t;
340
a750fc0b 341/*****************************************************************************/
79aceca5
FB		 342/*** Instruction decoding ***/
343#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 344static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 345{ \
346 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
347}
348
349#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 350static always_inline int32_t name (uint32_t opcode) \
79aceca5 351{ \
18fba28c 352 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 353}
354
355/* Opcode part 1 */
356EXTRACT_HELPER(opc1, 26, 6);
357/* Opcode part 2 */
358EXTRACT_HELPER(opc2, 1, 5);
359/* Opcode part 3 */
360EXTRACT_HELPER(opc3, 6, 5);
361/* Update Cr0 flags */
362EXTRACT_HELPER(Rc, 0, 1);
363/* Destination */
364EXTRACT_HELPER(rD, 21, 5);
365/* Source */
366EXTRACT_HELPER(rS, 21, 5);
367/* First operand */
368EXTRACT_HELPER(rA, 16, 5);
369/* Second operand */
370EXTRACT_HELPER(rB, 11, 5);
371/* Third operand */
372EXTRACT_HELPER(rC, 6, 5);
373/*** Get CRn ***/
374EXTRACT_HELPER(crfD, 23, 3);
375EXTRACT_HELPER(crfS, 18, 3);
376EXTRACT_HELPER(crbD, 21, 5);
377EXTRACT_HELPER(crbA, 16, 5);
378EXTRACT_HELPER(crbB, 11, 5);
379/* SPR / TBL */
3fc6c082 380EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 381static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 382{
383 uint32_t sprn = _SPR(opcode);
384
385 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
386}
79aceca5
FB		 387/*** Get constants ***/
388EXTRACT_HELPER(IMM, 12, 8);
389/* 16 bits signed immediate value */
390EXTRACT_SHELPER(SIMM, 0, 16);
391/* 16 bits unsigned immediate value */
392EXTRACT_HELPER(UIMM, 0, 16);
393/* Bit count */
394EXTRACT_HELPER(NB, 11, 5);
395/* Shift count */
396EXTRACT_HELPER(SH, 11, 5);
397/* Mask start */
398EXTRACT_HELPER(MB, 6, 5);
399/* Mask end */
400EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 401/* Trap operand */
402EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 403
404EXTRACT_HELPER(CRM, 12, 8);
405EXTRACT_HELPER(FM, 17, 8);
406EXTRACT_HELPER(SR, 16, 4);
e4bb997e 407EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 408
79aceca5
FB		 409/*** Jump target decoding ***/
410/* Displacement */
411EXTRACT_SHELPER(d, 0, 16);
412/* Immediate address */
b068d6a7 413static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 414{
415 return (opcode >> 0) & 0x03FFFFFC;
416}
417
b068d6a7 418static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 419{
420 return (opcode >> 0) & 0xFFFC;
421}
422
423EXTRACT_HELPER(BO, 21, 5);
424EXTRACT_HELPER(BI, 16, 5);
425/* Absolute/relative address */
426EXTRACT_HELPER(AA, 1, 1);
427/* Link */
428EXTRACT_HELPER(LK, 0, 1);
429
430/* Create a mask between <start> and <end> bits */
b068d6a7 431static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 432{
76a66253 433 target_ulong ret;
79aceca5 434
76a66253
JM		 435#if defined(TARGET_PPC64)
436 if (likely(start == 0)) {
6f2d8978 437 ret = UINT64_MAX << (63 - end);
76a66253 438 } else if (likely(end == 63)) {
6f2d8978 439 ret = UINT64_MAX >> start;
76a66253
JM		 440 }
441#else
442 if (likely(start == 0)) {
6f2d8978 443 ret = UINT32_MAX << (31 - end);
76a66253 444 } else if (likely(end == 31)) {
6f2d8978 445 ret = UINT32_MAX >> start;
76a66253
JM		 446 }
447#endif
448 else {
449 ret = (((target_ulong)(-1ULL)) >> (start)) ^
450 (((target_ulong)(-1ULL) >> (end)) >> 1);
451 if (unlikely(start > end))
452 return ~ret;
453 }
79aceca5
FB		 454
455 return ret;
456}
457
a750fc0b
JM		 458/*****************************************************************************/
459/* PowerPC Instructions types definitions */
460enum {
1b413d55 461 PPC_NONE = 0x0000000000000000ULL,
12de9a39 462 /* PowerPC base instructions set */
1b413d55
JM		 463 PPC_INSNS_BASE = 0x0000000000000001ULL,
464 /* integer operations instructions */
a750fc0b 465#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 466 /* flow control instructions */
a750fc0b 467#define PPC_FLOW PPC_INSNS_BASE
1b413d55 468 /* virtual memory instructions */
a750fc0b 469#define PPC_MEM PPC_INSNS_BASE
1b413d55 470 /* ld/st with reservation instructions */
a750fc0b 471#define PPC_RES PPC_INSNS_BASE
1b413d55 472 /* spr/msr access instructions */
a750fc0b 473#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 474 /* Deprecated instruction sets */
475 /* Original POWER instruction set */
f610349f 476 PPC_POWER = 0x0000000000000002ULL,
1b413d55 477 /* POWER2 instruction set extension */
f610349f 478 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 479 /* Power RTC support */
f610349f 480 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 481 /* Power-to-PowerPC bridge (601) */
f610349f 482 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 483 /* 64 bits PowerPC instruction set */
f610349f 484 PPC_64B = 0x0000000000000020ULL,
1b413d55 485 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 486 PPC_64BX = 0x0000000000000040ULL,
1b413d55 487 /* 64 bits hypervisor extensions */
f610349f 488 PPC_64H = 0x0000000000000080ULL,
1b413d55 489 /* New wait instruction (PowerPC 2.0x) */
f610349f 490 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 491 /* Time base mftb instruction */
f610349f 492 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 493
494 /* Fixed-point unit extensions */
495 /* PowerPC 602 specific */
f610349f 496 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 497 /* isel instruction */
498 PPC_ISEL = 0x0000000000000800ULL,
499 /* popcntb instruction */
500 PPC_POPCNTB = 0x0000000000001000ULL,
501 /* string load / store */
502 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 503
504 /* Floating-point unit extensions */
505 /* Optional floating point instructions */
506 PPC_FLOAT = 0x0000000000010000ULL,
507 /* New floating-point extensions (PowerPC 2.0x) */
508 PPC_FLOAT_EXT = 0x0000000000020000ULL,
509 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
510 PPC_FLOAT_FRES = 0x0000000000080000ULL,
511 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
512 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
513 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
514 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
515
516 /* Vector/SIMD extensions */
517 /* Altivec support */
518 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 519 /* PowerPC 2.03 SPE extension */
05332d70 520 PPC_SPE = 0x0000000002000000ULL,
1b413d55 521 /* PowerPC 2.03 SPE floating-point extension */
05332d70 522 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 523
12de9a39 524 /* Optional memory control instructions */
1b413d55
JM		 525 PPC_MEM_TLBIA = 0x0000000010000000ULL,
526 PPC_MEM_TLBIE = 0x0000000020000000ULL,
527 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
528 /* sync instruction */
529 PPC_MEM_SYNC = 0x0000000080000000ULL,
530 /* eieio instruction */
531 PPC_MEM_EIEIO = 0x0000000100000000ULL,
532
533 /* Cache control instructions */
c8623f2e 534 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 535 /* icbi instruction */
05332d70 536 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 537 /* dcbz instruction with fixed cache line size */
05332d70 538 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 539 /* dcbz instruction with tunable cache line size */
05332d70 540 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 541 /* dcba instruction */
05332d70
JM		 542 PPC_CACHE_DCBA = 0x0000002000000000ULL,
543 /* Freescale cache locking instructions */
544 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 545
546 /* MMU related extensions */
547 /* external control instructions */
05332d70 548 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 549 /* segment register access instructions */
05332d70 550 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 551 /* PowerPC 6xx TLB management instructions */
05332d70 552 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 553 /* PowerPC 74xx TLB management instructions */
05332d70 554 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 555 /* PowerPC 40x TLB management instructions */
05332d70 556 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 557 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 558 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 559 /* SLB management */
05332d70 560 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 561
12de9a39 562 /* Embedded PowerPC dedicated instructions */
05332d70 563 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 564 /* PowerPC 40x exception model */
05332d70 565 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 566 /* PowerPC 405 Mac instructions */
05332d70 567 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 568 /* PowerPC 440 specific instructions */
05332d70 569 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 570 /* BookE (embedded) PowerPC specification */
05332d70
JM		 571 PPC_BOOKE = 0x0010000000000000ULL,
572 /* mfapidi instruction */
573 PPC_MFAPIDI = 0x0020000000000000ULL,
574 /* tlbiva instruction */
575 PPC_TLBIVA = 0x0040000000000000ULL,
576 /* tlbivax instruction */
577 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 578 /* PowerPC 4xx dedicated instructions */
05332d70 579 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 580 /* PowerPC 40x ibct instructions */
05332d70 581 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 582 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 583 PPC_RFMCI = 0x0400000000000000ULL,
584 /* rfdi instruction */
585 PPC_RFDI = 0x0800000000000000ULL,
586 /* DCR accesses */
587 PPC_DCR = 0x1000000000000000ULL,
588 /* DCR extended accesse */
589 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 590 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 591 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 592};
593
594/*****************************************************************************/
595/* PowerPC instructions table */
3fc6c082
FB		 596#if HOST_LONG_BITS == 64
597#define OPC_ALIGN 8
598#else
599#define OPC_ALIGN 4
600#endif
1b039c09 601#if defined(__APPLE__)
d9bce9d9 602#define OPCODES_SECTION \
3fc6c082 603 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 604#else
d9bce9d9 605#define OPCODES_SECTION \
3fc6c082 606 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 607#endif
608
76a66253 609#if defined(DO_PPC_STATISTICS)
79aceca5 610#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 611OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 612 .opc1 = op1, \
613 .opc2 = op2, \
614 .opc3 = op3, \
18fba28c 615 .pad = { 0, }, \
79aceca5
FB		 616 .handler = { \
617 .inval = invl, \
9a64fbe4 618 .type = _typ, \
79aceca5 619 .handler = &gen_##name, \
76a66253 620 .oname = stringify(name), \
79aceca5 621 }, \
3fc6c082 622 .oname = stringify(name), \
79aceca5 623}
c7697e1f
JM		 624#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
625OPCODES_SECTION opcode_t opc_##name = { \
626 .opc1 = op1, \
627 .opc2 = op2, \
628 .opc3 = op3, \
629 .pad = { 0, }, \
630 .handler = { \
631 .inval = invl, \
632 .type = _typ, \
633 .handler = &gen_##name, \
634 .oname = onam, \
635 }, \
636 .oname = onam, \
637}
76a66253
JM		 638#else
639#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
640OPCODES_SECTION opcode_t opc_##name = { \
641 .opc1 = op1, \
642 .opc2 = op2, \
643 .opc3 = op3, \
644 .pad = { 0, }, \
645 .handler = { \
646 .inval = invl, \
647 .type = _typ, \
648 .handler = &gen_##name, \
649 }, \
650 .oname = stringify(name), \
651}
c7697e1f
JM		 652#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
653OPCODES_SECTION opcode_t opc_##name = { \
654 .opc1 = op1, \
655 .opc2 = op2, \
656 .opc3 = op3, \
657 .pad = { 0, }, \
658 .handler = { \
659 .inval = invl, \
660 .type = _typ, \
661 .handler = &gen_##name, \
662 }, \
663 .oname = onam, \
664}
76a66253 665#endif
79aceca5
FB		 666
667#define GEN_OPCODE_MARK(name) \
18fba28c 668OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 669 .opc1 = 0xFF, \
670 .opc2 = 0xFF, \
671 .opc3 = 0xFF, \
18fba28c 672 .pad = { 0, }, \
79aceca5
FB		 673 .handler = { \
674 .inval = 0x00000000, \
9a64fbe4 675 .type = 0x00, \
79aceca5
FB		 676 .handler = NULL, \
677 }, \
3fc6c082 678 .oname = stringify(name), \
79aceca5
FB		 679}
680
54cdcae6
AJ		 681/* SPR load/store helpers */
682static always_inline void gen_load_spr(TCGv t, int reg)
683{
684 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
685}
686
687static always_inline void gen_store_spr(int reg, TCGv t)
688{
689 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
690}
691
79aceca5
FB		 692/* Start opcode list */
693GEN_OPCODE_MARK(start);
694
695/* Invalid instruction */
9a64fbe4
FB		 696GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
697{
e06fcd75 698 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 699}
700
79aceca5
FB		 701static opc_handler_t invalid_handler = {
702 .inval = 0xFFFFFFFF,
9a64fbe4 703 .type = PPC_NONE,
79aceca5
FB		 704 .handler = gen_invalid,
705};
706
e1571908
AJ		 707/*** Integer comparison ***/
708
ea363694 709static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 710{
711 int l1, l2, l3;
712
269f3e95
AJ		 713 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
714 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 715 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
716
717 l1 = gen_new_label();
718 l2 = gen_new_label();
719 l3 = gen_new_label();
720 if (s) {
ea363694
AJ		 721 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 723 } else {
ea363694
AJ		 724 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
725 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 726 }
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
728 tcg_gen_br(l3);
729 gen_set_label(l1);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
731 tcg_gen_br(l3);
732 gen_set_label(l2);
733 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
734 gen_set_label(l3);
735}
736
ea363694 737static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 738{
ea363694
AJ		 739 TCGv t0 = tcg_const_local_tl(arg1);
740 gen_op_cmp(arg0, t0, s, crf);
741 tcg_temp_free(t0);
e1571908
AJ		 742}
743
744#if defined(TARGET_PPC64)
ea363694 745static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 746{
ea363694 747 TCGv t0, t1;
a7812ae4
PB		 748 t0 = tcg_temp_local_new();
749 t1 = tcg_temp_local_new();
e1571908 750 if (s) {
ea363694
AJ		 751 tcg_gen_ext32s_tl(t0, arg0);
752 tcg_gen_ext32s_tl(t1, arg1);
e1571908 753 } else {
ea363694
AJ		 754 tcg_gen_ext32u_tl(t0, arg0);
755 tcg_gen_ext32u_tl(t1, arg1);
e1571908 756 }
ea363694
AJ		 757 gen_op_cmp(t0, t1, s, crf);
758 tcg_temp_free(t1);
759 tcg_temp_free(t0);
e1571908
AJ		 760}
761
ea363694 762static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 763{
ea363694
AJ		 764 TCGv t0 = tcg_const_local_tl(arg1);
765 gen_op_cmp32(arg0, t0, s, crf);
766 tcg_temp_free(t0);
e1571908
AJ		 767}
768#endif
769
770static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
771{
772#if defined(TARGET_PPC64)
773 if (!(ctx->sf_mode))
774 gen_op_cmpi32(reg, 0, 1, 0);
775 else
776#endif
777 gen_op_cmpi(reg, 0, 1, 0);
778}
779
780/* cmp */
781GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
782{
783#if defined(TARGET_PPC64)
784 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
785 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787 else
788#endif
789 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
790 1, crfD(ctx->opcode));
791}
792
793/* cmpi */
794GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
795{
796#if defined(TARGET_PPC64)
797 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
798 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800 else
801#endif
802 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
803 1, crfD(ctx->opcode));
804}
805
806/* cmpl */
807GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
808{
809#if defined(TARGET_PPC64)
810 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
811 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813 else
814#endif
815 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
816 0, crfD(ctx->opcode));
817}
818
819/* cmpli */
820GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
821{
822#if defined(TARGET_PPC64)
823 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
824 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826 else
827#endif
828 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
829 0, crfD(ctx->opcode));
830}
831
832/* isel (PowerPC 2.03 specification) */
833GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
834{
835 int l1, l2;
836 uint32_t bi = rC(ctx->opcode);
837 uint32_t mask;
a7812ae4 838 TCGv_i32 t0;
e1571908
AJ		 839
840 l1 = gen_new_label();
841 l2 = gen_new_label();
842
843 mask = 1 << (3 - (bi & 0x03));
a7812ae4 844 t0 = tcg_temp_new_i32();
fea0c503
AJ		 845 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
846 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 847 if (rA(ctx->opcode) == 0)
848 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
849 else
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
851 tcg_gen_br(l2);
852 gen_set_label(l1);
853 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
854 gen_set_label(l2);
a7812ae4 855 tcg_temp_free_i32(t0);
e1571908
AJ		 856}
857
79aceca5 858/*** Integer arithmetic ***/
79aceca5 859
74637406
AJ		 860static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
861{
862 int l1;
863 TCGv t0;
79aceca5 864
74637406
AJ		 865 l1 = gen_new_label();
866 /* Start with XER OV disabled, the most likely case */
867 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 868 t0 = tcg_temp_local_new();
74637406
AJ		 869 tcg_gen_xor_tl(t0, arg0, arg1);
870#if defined(TARGET_PPC64)
871 if (!ctx->sf_mode)
872 tcg_gen_ext32s_tl(t0, t0);
873#endif
874 if (sub)
875 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
876 else
877 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
878 tcg_gen_xor_tl(t0, arg1, arg2);
879#if defined(TARGET_PPC64)
880 if (!ctx->sf_mode)
881 tcg_gen_ext32s_tl(t0, t0);
882#endif
883 if (sub)
884 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
885 else
886 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
887 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
888 gen_set_label(l1);
889 tcg_temp_free(t0);
79aceca5
FB		 890}
891
74637406
AJ		 892static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
893{
894 int l1 = gen_new_label();
d9bce9d9
JM		 895
896#if defined(TARGET_PPC64)
74637406
AJ		 897 if (!(ctx->sf_mode)) {
898 TCGv t0, t1;
a7812ae4
PB		 899 t0 = tcg_temp_new();
900 t1 = tcg_temp_new();
d9bce9d9 901
74637406
AJ		 902 tcg_gen_ext32u_tl(t0, arg1);
903 tcg_gen_ext32u_tl(t1, arg2);
904 if (sub) {
905 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 906 } else {
74637406
AJ		 907 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
908 }
a9730017
AJ		 909 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
910 gen_set_label(l1);
911 tcg_temp_free(t0);
912 tcg_temp_free(t1);
74637406
AJ		 913 } else
914#endif
a9730017
AJ		 915 {
916 if (sub) {
917 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
918 } else {
919 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
920 }
921 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
922 gen_set_label(l1);
74637406 923 }
d9bce9d9
JM		 924}
925
74637406
AJ		 926/* Common add function */
927static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
928 int add_ca, int compute_ca, int compute_ov)
929{
930 TCGv t0, t1;
d9bce9d9 931
74637406 932 if ((!compute_ca && !compute_ov) ||
a7812ae4 933 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 934 t0 = ret;
935 } else {
a7812ae4 936 t0 = tcg_temp_local_new();
74637406 937 }
79aceca5 938
74637406 939 if (add_ca) {
a7812ae4 940 t1 = tcg_temp_local_new();
74637406
AJ		 941 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
942 tcg_gen_shri_tl(t1, t1, XER_CA);
943 }
79aceca5 944
74637406
AJ		 945 if (compute_ca && compute_ov) {
946 /* Start with XER CA and OV disabled, the most likely case */
947 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
948 } else if (compute_ca) {
949 /* Start with XER CA disabled, the most likely case */
950 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
951 } else if (compute_ov) {
952 /* Start with XER OV disabled, the most likely case */
953 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
954 }
79aceca5 955
74637406
AJ		 956 tcg_gen_add_tl(t0, arg1, arg2);
957
958 if (compute_ca) {
959 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
960 }
961 if (add_ca) {
962 tcg_gen_add_tl(t0, t0, t1);
963 gen_op_arith_compute_ca(ctx, t0, t1, 0);
964 tcg_temp_free(t1);
965 }
966 if (compute_ov) {
967 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
968 }
969
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, t0);
972
a7812ae4 973 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 974 tcg_gen_mov_tl(ret, t0);
975 tcg_temp_free(t0);
976 }
39dd32ee 977}
74637406
AJ		 978/* Add functions with two operands */
979#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
980GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
981{ \
982 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 add_ca, compute_ca, compute_ov); \
985}
986/* Add functions with one operand and one immediate */
987#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
988 add_ca, compute_ca, compute_ov) \
989GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
990{ \
991 TCGv t0 = tcg_const_local_tl(const_val); \
992 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], t0, \
994 add_ca, compute_ca, compute_ov); \
995 tcg_temp_free(t0); \
996}
997
998/* add add. addo addo. */
999GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1000GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1001/* addc addc. addco addco. */
1002GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1003GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1004/* adde adde. addeo addeo. */
1005GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1006GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1007/* addme addme. addmeo addmeo. */
1008GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1009GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1010/* addze addze. addzeo addzeo.*/
1011GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1012GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1013/* addi */
1014GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1015{
74637406
AJ		 1016 target_long simm = SIMM(ctx->opcode);
1017
1018 if (rA(ctx->opcode) == 0) {
1019 /* li case */
1020 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1021 } else {
1022 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1023 }
d9bce9d9 1024}
74637406
AJ		 1025/* addic addic.*/
1026static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1027 int compute_Rc0)
d9bce9d9 1028{
74637406
AJ		 1029 target_long simm = SIMM(ctx->opcode);
1030
1031 /* Start with XER CA and OV disabled, the most likely case */
1032 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1033
1034 if (likely(simm != 0)) {
a7812ae4 1035 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1036 tcg_gen_addi_tl(t0, arg1, simm);
1037 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1038 tcg_gen_mov_tl(ret, t0);
1039 tcg_temp_free(t0);
1040 } else {
1041 tcg_gen_mov_tl(ret, arg1);
1042 }
1043 if (compute_Rc0) {
1044 gen_set_Rc0(ctx, ret);
1045 }
d9bce9d9 1046}
74637406 1047GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1048{
74637406 1049 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1050}
74637406 1051GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1052{
74637406 1053 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1054}
74637406
AJ		 1055/* addis */
1056GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1057{
74637406
AJ		 1058 target_long simm = SIMM(ctx->opcode);
1059
1060 if (rA(ctx->opcode) == 0) {
1061 /* lis case */
1062 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1063 } else {
1064 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1065 }
d9bce9d9 1066}
74637406
AJ		 1067
1068static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1069 int sign, int compute_ov)
d9bce9d9 1070{
2ef1b120
AJ		 1071 int l1 = gen_new_label();
1072 int l2 = gen_new_label();
a7812ae4
PB		 1073 TCGv_i32 t0 = tcg_temp_local_new_i32();
1074 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1075
2ef1b120
AJ		 1076 tcg_gen_trunc_tl_i32(t0, arg1);
1077 tcg_gen_trunc_tl_i32(t1, arg2);
1078 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1079 if (sign) {
2ef1b120
AJ		 1080 int l3 = gen_new_label();
1081 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1082 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1083 gen_set_label(l3);
2ef1b120 1084 tcg_gen_div_i32(t0, t0, t1);
74637406 1085 } else {
2ef1b120 1086 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1087 }
1088 if (compute_ov) {
1089 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1090 }
1091 tcg_gen_br(l2);
1092 gen_set_label(l1);
1093 if (sign) {
2ef1b120 1094 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1095 } else {
1096 tcg_gen_movi_i32(t0, 0);
1097 }
1098 if (compute_ov) {
1099 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1100 }
1101 gen_set_label(l2);
2ef1b120 1102 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1103 tcg_temp_free_i32(t0);
1104 tcg_temp_free_i32(t1);
74637406
AJ		 1105 if (unlikely(Rc(ctx->opcode) != 0))
1106 gen_set_Rc0(ctx, ret);
d9bce9d9 1107}
74637406
AJ		 1108/* Div functions */
1109#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1110GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1111{ \
1112 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1114 sign, compute_ov); \
1115}
1116/* divwu divwu. divwuo divwuo. */
1117GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1118GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1119/* divw divw. divwo divwo. */
1120GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1121GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1122#if defined(TARGET_PPC64)
2ef1b120
AJ		 1123static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1124 int sign, int compute_ov)
d9bce9d9 1125{
2ef1b120
AJ		 1126 int l1 = gen_new_label();
1127 int l2 = gen_new_label();
74637406
AJ		 1128
1129 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1130 if (sign) {
2ef1b120 1131 int l3 = gen_new_label();
74637406
AJ		 1132 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1133 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1134 gen_set_label(l3);
74637406
AJ		 1135 tcg_gen_div_i64(ret, arg1, arg2);
1136 } else {
1137 tcg_gen_divu_i64(ret, arg1, arg2);
1138 }
1139 if (compute_ov) {
1140 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1141 }
1142 tcg_gen_br(l2);
1143 gen_set_label(l1);
1144 if (sign) {
1145 tcg_gen_sari_i64(ret, arg1, 63);
1146 } else {
1147 tcg_gen_movi_i64(ret, 0);
1148 }
1149 if (compute_ov) {
1150 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1151 }
1152 gen_set_label(l2);
1153 if (unlikely(Rc(ctx->opcode) != 0))
1154 gen_set_Rc0(ctx, ret);
d9bce9d9 1155}
74637406
AJ		 1156#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1157GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1158{ \
2ef1b120
AJ		 1159 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 sign, compute_ov); \
74637406
AJ		 1162}
1163/* divwu divwu. divwuo divwuo. */
1164GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1165GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1166/* divw divw. divwo divwo. */
1167GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1168GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1169#endif
74637406
AJ		 1170
1171/* mulhw mulhw. */
1172GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1173{
a7812ae4 1174 TCGv_i64 t0, t1;
74637406 1175
a7812ae4
PB		 1176 t0 = tcg_temp_new_i64();
1177 t1 = tcg_temp_new_i64();
74637406
AJ		 1178#if defined(TARGET_PPC64)
1179 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1183#else
1184 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1185 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1186 tcg_gen_mul_i64(t0, t0, t1);
1187 tcg_gen_shri_i64(t0, t0, 32);
1188 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1189#endif
a7812ae4
PB		 1190 tcg_temp_free_i64(t0);
1191 tcg_temp_free_i64(t1);
74637406
AJ		 1192 if (unlikely(Rc(ctx->opcode) != 0))
1193 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1194}
74637406
AJ		 1195/* mulhwu mulhwu. */
1196GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1197{
a7812ae4 1198 TCGv_i64 t0, t1;
74637406 1199
a7812ae4
PB		 1200 t0 = tcg_temp_new_i64();
1201 t1 = tcg_temp_new_i64();
d9bce9d9 1202#if defined(TARGET_PPC64)
74637406
AJ		 1203 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1207#else
1208 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1209 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1210 tcg_gen_mul_i64(t0, t0, t1);
1211 tcg_gen_shri_i64(t0, t0, 32);
1212 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1213#endif
a7812ae4
PB		 1214 tcg_temp_free_i64(t0);
1215 tcg_temp_free_i64(t1);
74637406
AJ		 1216 if (unlikely(Rc(ctx->opcode) != 0))
1217 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1218}
74637406
AJ		 1219/* mullw mullw. */
1220GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1221{
74637406
AJ		 1222 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1223 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1224 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1227}
74637406
AJ		 1228/* mullwo mullwo. */
1229GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1230{
74637406 1231 int l1;
a7812ae4 1232 TCGv_i64 t0, t1;
74637406 1233
a7812ae4
PB		 1234 t0 = tcg_temp_new_i64();
1235 t1 = tcg_temp_new_i64();
74637406
AJ		 1236 l1 = gen_new_label();
1237 /* Start with XER OV disabled, the most likely case */
1238 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1239#if defined(TARGET_PPC64)
1240 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1241 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1242#else
1243 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1244 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1245#endif
74637406
AJ		 1246 tcg_gen_mul_i64(t0, t0, t1);
1247#if defined(TARGET_PPC64)
1248 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1249 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1250#else
1251 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1252 tcg_gen_ext32s_i64(t1, t0);
1253 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1254#endif
1255 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1256 gen_set_label(l1);
a7812ae4
PB		 1257 tcg_temp_free_i64(t0);
1258 tcg_temp_free_i64(t1);
74637406
AJ		 1259 if (unlikely(Rc(ctx->opcode) != 0))
1260 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1261}
74637406
AJ		 1262/* mulli */
1263GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1264{
74637406
AJ		 1265 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1266 SIMM(ctx->opcode));
d9bce9d9
JM		 1267}
1268#if defined(TARGET_PPC64)
74637406
AJ		 1269#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1270GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1271{ \
a7812ae4 1272 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1274 if (unlikely(Rc(ctx->opcode) != 0)) \
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1276}
74637406
AJ		 1277/* mulhd mulhd. */
1278GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1279/* mulhdu mulhdu. */
1280GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1281/* mulld mulld. */
1282GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1283{
74637406
AJ		 1284 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1285 cpu_gpr[rB(ctx->opcode)]);
1286 if (unlikely(Rc(ctx->opcode) != 0))
1287 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1288}
74637406
AJ		 1289/* mulldo mulldo. */
1290GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1291#endif
74637406
AJ		 1292
1293/* neg neg. nego nego. */
ec6469a3 1294static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1295{
ec6469a3
AJ		 1296 int l1 = gen_new_label();
1297 int l2 = gen_new_label();
a7812ae4 1298 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1299#if defined(TARGET_PPC64)
74637406 1300 if (ctx->sf_mode) {
741a7444 1301 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1303 } else
1304#endif
1305 {
1306 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1307 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1308 }
74637406
AJ		 1309 tcg_gen_neg_tl(ret, arg1);
1310 if (ov_check) {
1311 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1312 }
1313 tcg_gen_br(l2);
1314 gen_set_label(l1);
ec6469a3 1315 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1316 if (ov_check) {
1317 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1318 }
1319 gen_set_label(l2);
ec6469a3 1320 tcg_temp_free(t0);
74637406
AJ		 1321 if (unlikely(Rc(ctx->opcode) != 0))
1322 gen_set_Rc0(ctx, ret);
1323}
1324GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1325{
ec6469a3 1326 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1327}
74637406 1328GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1329{
ec6469a3 1330 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1331}
74637406
AJ		 1332
1333/* Common subf function */
1334static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1335 int add_ca, int compute_ca, int compute_ov)
79aceca5 1336{
74637406 1337 TCGv t0, t1;
76a66253 1338
74637406 1339 if ((!compute_ca && !compute_ov) ||
a7812ae4 1340 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1341 t0 = ret;
e864cabd 1342 } else {
a7812ae4 1343 t0 = tcg_temp_local_new();
d9bce9d9 1344 }
76a66253 1345
74637406 1346 if (add_ca) {
a7812ae4 1347 t1 = tcg_temp_local_new();
74637406
AJ		 1348 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1349 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1350 }
79aceca5 1351
74637406
AJ		 1352 if (compute_ca && compute_ov) {
1353 /* Start with XER CA and OV disabled, the most likely case */
1354 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1355 } else if (compute_ca) {
1356 /* Start with XER CA disabled, the most likely case */
1357 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1358 } else if (compute_ov) {
1359 /* Start with XER OV disabled, the most likely case */
1360 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1361 }
1362
1363 if (add_ca) {
1364 tcg_gen_not_tl(t0, arg1);
1365 tcg_gen_add_tl(t0, t0, arg2);
1366 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1367 tcg_gen_add_tl(t0, t0, t1);
1368 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1369 tcg_temp_free(t1);
79aceca5 1370 } else {
74637406
AJ		 1371 tcg_gen_sub_tl(t0, arg2, arg1);
1372 if (compute_ca) {
1373 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1374 }
1375 }
1376 if (compute_ov) {
1377 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1378 }
1379
1380 if (unlikely(Rc(ctx->opcode) != 0))
1381 gen_set_Rc0(ctx, t0);
1382
a7812ae4 1383 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1384 tcg_gen_mov_tl(ret, t0);
1385 tcg_temp_free(t0);
79aceca5 1386 }
79aceca5 1387}
74637406
AJ		 1388/* Sub functions with Two operands functions */
1389#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1390GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1391{ \
1392 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1393 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1394 add_ca, compute_ca, compute_ov); \
1395}
1396/* Sub functions with one operand and one immediate */
1397#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1398 add_ca, compute_ca, compute_ov) \
1399GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1400{ \
1401 TCGv t0 = tcg_const_local_tl(const_val); \
1402 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1403 cpu_gpr[rA(ctx->opcode)], t0, \
1404 add_ca, compute_ca, compute_ov); \
1405 tcg_temp_free(t0); \
1406}
1407/* subf subf. subfo subfo. */
1408GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1409GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1410/* subfc subfc. subfco subfco. */
1411GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1412GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1413/* subfe subfe. subfeo subfo. */
1414GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1415GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1416/* subfme subfme. subfmeo subfmeo. */
1417GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1418GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1419/* subfze subfze. subfzeo subfzeo.*/
1420GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1421GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1422/* subfic */
1423GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1424{
74637406
AJ		 1425 /* Start with XER CA and OV disabled, the most likely case */
1426 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1427 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1428 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1429 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1430 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1431 tcg_temp_free(t1);
1432 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1433 tcg_temp_free(t0);
79aceca5
FB		 1434}
1435
79aceca5 1436/*** Integer logical ***/
26d67362
AJ		 1437#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1438GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1439{ \
26d67362
AJ		 1440 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1441 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1442 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1443 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1444}
79aceca5 1445
26d67362 1446#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1447GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1448{ \
26d67362 1449 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1450 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1451 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1452}
1453
1454/* and & and. */
26d67362 1455GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1456/* andc & andc. */
26d67362 1457GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1458/* andi. */
c7697e1f 1459GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1460{
26d67362
AJ		 1461 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1463}
1464/* andis. */
c7697e1f 1465GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1466{
26d67362
AJ		 1467 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1469}
79aceca5 1470/* cntlzw */
26d67362
AJ		 1471GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1472{
a7812ae4 1473 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1474 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1475 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1476}
79aceca5 1477/* eqv & eqv. */
26d67362 1478GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1479/* extsb & extsb. */
26d67362 1480GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1481/* extsh & extsh. */
26d67362 1482GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1483/* nand & nand. */
26d67362 1484GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1485/* nor & nor. */
26d67362 1486GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1487/* or & or. */
9a64fbe4
FB		 1488GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1489{
76a66253
JM		 1490 int rs, ra, rb;
1491
1492 rs = rS(ctx->opcode);
1493 ra = rA(ctx->opcode);
1494 rb = rB(ctx->opcode);
1495 /* Optimisation for mr. ri case */
1496 if (rs != ra || rs != rb) {
26d67362
AJ		 1497 if (rs != rb)
1498 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1499 else
1500 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1501 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1502 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1503 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1504 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1505#if defined(TARGET_PPC64)
1506 } else {
26d67362
AJ		 1507 int prio = 0;
1508
c80f84e3
JM		 1509 switch (rs) {
1510 case 1:
1511 /* Set process priority to low */
26d67362 1512 prio = 2;
c80f84e3
JM		 1513 break;
1514 case 6:
1515 /* Set process priority to medium-low */
26d67362 1516 prio = 3;
c80f84e3
JM		 1517 break;
1518 case 2:
1519 /* Set process priority to normal */
26d67362 1520 prio = 4;
c80f84e3 1521 break;
be147d08
JM		 1522#if !defined(CONFIG_USER_ONLY)
1523 case 31:
76db3ba4 1524 if (ctx->mem_idx > 0) {
be147d08 1525 /* Set process priority to very low */
26d67362 1526 prio = 1;
be147d08
JM		 1527 }
1528 break;
1529 case 5:
76db3ba4 1530 if (ctx->mem_idx > 0) {
be147d08 1531 /* Set process priority to medium-hight */
26d67362 1532 prio = 5;
be147d08
JM		 1533 }
1534 break;
1535 case 3:
76db3ba4 1536 if (ctx->mem_idx > 0) {
be147d08 1537 /* Set process priority to high */
26d67362 1538 prio = 6;
be147d08
JM		 1539 }
1540 break;
be147d08 1541 case 7:
76db3ba4 1542 if (ctx->mem_idx > 1) {
be147d08 1543 /* Set process priority to very high */
26d67362 1544 prio = 7;
be147d08
JM		 1545 }
1546 break;
be147d08 1547#endif
c80f84e3
JM		 1548 default:
1549 /* nop */
1550 break;
1551 }
26d67362 1552 if (prio) {
a7812ae4 1553 TCGv t0 = tcg_temp_new();
54cdcae6 1554 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1555 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1556 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1557 gen_store_spr(SPR_PPR, t0);
ea363694 1558 tcg_temp_free(t0);
26d67362 1559 }
c80f84e3 1560#endif
9a64fbe4 1561 }
9a64fbe4 1562}
79aceca5 1563/* orc & orc. */
26d67362 1564GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1565/* xor & xor. */
9a64fbe4
FB		 1566GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1567{
9a64fbe4 1568 /* Optimisation for "set to zero" case */
26d67362 1569 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1570 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1571 else
1572 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1573 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1575}
79aceca5
FB		 1576/* ori */
1577GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1578{
76a66253 1579 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1580
9a64fbe4
FB		 1581 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1582 /* NOP */
76a66253 1583 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1584 return;
76a66253 1585 }
26d67362 1586 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1587}
1588/* oris */
1589GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1590{
76a66253 1591 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1592
9a64fbe4
FB		 1593 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1594 /* NOP */
1595 return;
76a66253 1596 }
26d67362 1597 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1598}
1599/* xori */
1600GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1601{
76a66253 1602 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1603
1604 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1605 /* NOP */
1606 return;
1607 }
26d67362 1608 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1609}
79aceca5
FB		 1610/* xoris */
1611GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1612{
76a66253 1613 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1614
1615 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1616 /* NOP */
1617 return;
1618 }
26d67362 1619 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1620}
d9bce9d9 1621/* popcntb : PowerPC 2.03 specification */
05332d70 1622GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1623{
d9bce9d9
JM		 1624#if defined(TARGET_PPC64)
1625 if (ctx->sf_mode)
a7812ae4 1626 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1627 else
1628#endif
a7812ae4 1629 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1630}
1631
1632#if defined(TARGET_PPC64)
1633/* extsw & extsw. */
26d67362 1634GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1635/* cntlzd */
26d67362
AJ		 1636GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1637{
a7812ae4 1638 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1639 if (unlikely(Rc(ctx->opcode) != 0))
1640 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1641}
d9bce9d9
JM		 1642#endif
1643
79aceca5
FB		 1644/*** Integer rotate ***/
1645/* rlwimi & rlwimi. */
1646GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1647{
76a66253 1648 uint32_t mb, me, sh;
79aceca5
FB		 1649
1650 mb = MB(ctx->opcode);
1651 me = ME(ctx->opcode);
76a66253 1652 sh = SH(ctx->opcode);
d03ef511
AJ		 1653 if (likely(sh == 0 && mb == 0 && me == 31)) {
1654 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1655 } else {
d03ef511 1656 target_ulong mask;
a7812ae4
PB		 1657 TCGv t1;
1658 TCGv t0 = tcg_temp_new();
54843a58 1659#if defined(TARGET_PPC64)
a7812ae4
PB		 1660 TCGv_i32 t2 = tcg_temp_new_i32();
1661 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1662 tcg_gen_rotli_i32(t2, t2, sh);
1663 tcg_gen_extu_i32_i64(t0, t2);
1664 tcg_temp_free_i32(t2);
54843a58
AJ		 1665#else
1666 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1667#endif
76a66253 1668#if defined(TARGET_PPC64)
d03ef511
AJ		 1669 mb += 32;
1670 me += 32;
76a66253 1671#endif
d03ef511 1672 mask = MASK(mb, me);
a7812ae4 1673 t1 = tcg_temp_new();
d03ef511
AJ		 1674 tcg_gen_andi_tl(t0, t0, mask);
1675 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1676 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1677 tcg_temp_free(t0);
1678 tcg_temp_free(t1);
1679 }
76a66253 1680 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1681 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1682}
1683/* rlwinm & rlwinm. */
1684GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1685{
1686 uint32_t mb, me, sh;
3b46e624 1687
79aceca5
FB		 1688 sh = SH(ctx->opcode);
1689 mb = MB(ctx->opcode);
1690 me = ME(ctx->opcode);
d03ef511
AJ		 1691
1692 if (likely(mb == 0 && me == (31 - sh))) {
1693 if (likely(sh == 0)) {
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1695 } else {
a7812ae4 1696 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1697 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1698 tcg_gen_shli_tl(t0, t0, sh);
1699 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1700 tcg_temp_free(t0);
79aceca5 1701 }
d03ef511 1702 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1703 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1704 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1705 tcg_gen_shri_tl(t0, t0, mb);
1706 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1707 tcg_temp_free(t0);
1708 } else {
a7812ae4 1709 TCGv t0 = tcg_temp_new();
54843a58 1710#if defined(TARGET_PPC64)
a7812ae4 1711 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1712 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1713 tcg_gen_rotli_i32(t1, t1, sh);
1714 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1715 tcg_temp_free_i32(t1);
54843a58
AJ		 1716#else
1717 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1718#endif
76a66253 1719#if defined(TARGET_PPC64)
d03ef511
AJ		 1720 mb += 32;
1721 me += 32;
76a66253 1722#endif
d03ef511
AJ		 1723 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1724 tcg_temp_free(t0);
1725 }
76a66253 1726 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1727 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1728}
1729/* rlwnm & rlwnm. */
1730GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1731{
1732 uint32_t mb, me;
54843a58
AJ		 1733 TCGv t0;
1734#if defined(TARGET_PPC64)
a7812ae4 1735 TCGv_i32 t1, t2;
54843a58 1736#endif
79aceca5
FB		 1737
1738 mb = MB(ctx->opcode);
1739 me = ME(ctx->opcode);
a7812ae4 1740 t0 = tcg_temp_new();
d03ef511 1741 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1742#if defined(TARGET_PPC64)
a7812ae4
PB		 1743 t1 = tcg_temp_new_i32();
1744 t2 = tcg_temp_new_i32();
54843a58
AJ		 1745 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1746 tcg_gen_trunc_i64_i32(t2, t0);
1747 tcg_gen_rotl_i32(t1, t1, t2);
1748 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1749 tcg_temp_free_i32(t1);
1750 tcg_temp_free_i32(t2);
54843a58
AJ		 1751#else
1752 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1753#endif
76a66253
JM		 1754 if (unlikely(mb != 0 || me != 31)) {
1755#if defined(TARGET_PPC64)
1756 mb += 32;
1757 me += 32;
1758#endif
54843a58 1759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1760 } else {
54843a58 1761 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1762 }
54843a58 1763 tcg_temp_free(t0);
76a66253 1764 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1765 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1766}
1767
d9bce9d9
JM		 1768#if defined(TARGET_PPC64)
1769#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1770GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1771{ \
1772 gen_##name(ctx, 0); \
1773} \
c7697e1f
JM		 1774GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1775 PPC_64B) \
d9bce9d9
JM		 1776{ \
1777 gen_##name(ctx, 1); \
1778}
1779#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1780GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1781{ \
1782 gen_##name(ctx, 0, 0); \
1783} \
c7697e1f
JM		 1784GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1785 PPC_64B) \
d9bce9d9
JM		 1786{ \
1787 gen_##name(ctx, 0, 1); \
1788} \
c7697e1f
JM		 1789GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1790 PPC_64B) \
d9bce9d9
JM		 1791{ \
1792 gen_##name(ctx, 1, 0); \
1793} \
c7697e1f
JM		 1794GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1795 PPC_64B) \
d9bce9d9
JM		 1796{ \
1797 gen_##name(ctx, 1, 1); \
1798}
51789c41 1799
b068d6a7
JM		 1800static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1801 uint32_t me, uint32_t sh)
51789c41 1802{
d03ef511
AJ		 1803 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1804 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1805 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1806 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1807 } else {
a7812ae4 1808 TCGv t0 = tcg_temp_new();
54843a58 1809 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1810 if (likely(mb == 0 && me == 63)) {
54843a58 1811 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1812 } else {
1813 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1814 }
d03ef511 1815 tcg_temp_free(t0);
51789c41 1816 }
51789c41 1817 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1819}
d9bce9d9 1820/* rldicl - rldicl. */
b068d6a7 1821static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1822{
51789c41 1823 uint32_t sh, mb;
d9bce9d9 1824
9d53c753
JM		 1825 sh = SH(ctx->opcode) | (shn << 5);
1826 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1827 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1828}
51789c41 1829GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1830/* rldicr - rldicr. */
b068d6a7 1831static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1832{
51789c41 1833 uint32_t sh, me;
d9bce9d9 1834
9d53c753
JM		 1835 sh = SH(ctx->opcode) | (shn << 5);
1836 me = MB(ctx->opcode) | (men << 5);
51789c41 1837 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1838}
51789c41 1839GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1840/* rldic - rldic. */
b068d6a7 1841static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1842{
51789c41 1843 uint32_t sh, mb;
d9bce9d9 1844
9d53c753
JM		 1845 sh = SH(ctx->opcode) | (shn << 5);
1846 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1847 gen_rldinm(ctx, mb, 63 - sh, sh);
1848}
1849GEN_PPC64_R4(rldic, 0x1E, 0x04);
1850
b068d6a7
JM		 1851static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1852 uint32_t me)
51789c41 1853{
54843a58 1854 TCGv t0;
d03ef511
AJ		 1855
1856 mb = MB(ctx->opcode);
1857 me = ME(ctx->opcode);
a7812ae4 1858 t0 = tcg_temp_new();
d03ef511 1859 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1860 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1861 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1862 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1863 } else {
1864 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1865 }
1866 tcg_temp_free(t0);
51789c41 1867 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1869}
51789c41 1870
d9bce9d9 1871/* rldcl - rldcl. */
b068d6a7 1872static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1873{
51789c41 1874 uint32_t mb;
d9bce9d9 1875
9d53c753 1876 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1877 gen_rldnm(ctx, mb, 63);
d9bce9d9 1878}
36081602 1879GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1880/* rldcr - rldcr. */
b068d6a7 1881static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1882{
51789c41 1883 uint32_t me;
d9bce9d9 1884
9d53c753 1885 me = MB(ctx->opcode) | (men << 5);
51789c41 1886 gen_rldnm(ctx, 0, me);
d9bce9d9 1887}
36081602 1888GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1889/* rldimi - rldimi. */
b068d6a7 1890static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1891{
271a916e 1892 uint32_t sh, mb, me;
d9bce9d9 1893
9d53c753
JM		 1894 sh = SH(ctx->opcode) | (shn << 5);
1895 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1896 me = 63 - sh;
d03ef511
AJ		 1897 if (unlikely(sh == 0 && mb == 0)) {
1898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1899 } else {
1900 TCGv t0, t1;
1901 target_ulong mask;
1902
a7812ae4 1903 t0 = tcg_temp_new();
54843a58 1904 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1905 t1 = tcg_temp_new();
d03ef511
AJ		 1906 mask = MASK(mb, me);
1907 tcg_gen_andi_tl(t0, t0, mask);
1908 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1909 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1910 tcg_temp_free(t0);
1911 tcg_temp_free(t1);
51789c41 1912 }
51789c41 1913 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1915}
36081602 1916GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1917#endif
1918
79aceca5
FB		 1919/*** Integer shift ***/
1920/* slw & slw. */
26d67362
AJ		 1921GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1922{
fea0c503 1923 TCGv t0;
26d67362
AJ		 1924 int l1, l2;
1925 l1 = gen_new_label();
1926 l2 = gen_new_label();
1927
a7812ae4 1928 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1929 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1930 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1931 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1932 tcg_gen_br(l2);
1933 gen_set_label(l1);
fea0c503 1934 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1935 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1936 gen_set_label(l2);
fea0c503 1937 tcg_temp_free(t0);
26d67362
AJ		 1938 if (unlikely(Rc(ctx->opcode) != 0))
1939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1940}
79aceca5 1941/* sraw & sraw. */
26d67362
AJ		 1942GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1943{
a7812ae4
PB		 1944 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1945 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1946 if (unlikely(Rc(ctx->opcode) != 0))
1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1948}
79aceca5
FB		 1949/* srawi & srawi. */
1950GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1951{
26d67362
AJ		 1952 int sh = SH(ctx->opcode);
1953 if (sh != 0) {
1954 int l1, l2;
fea0c503 1955 TCGv t0;
26d67362
AJ		 1956 l1 = gen_new_label();
1957 l2 = gen_new_label();
a7812ae4 1958 t0 = tcg_temp_local_new();
fea0c503
AJ		 1959 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1960 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1961 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1962 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1963 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1964 tcg_gen_br(l2);
1965 gen_set_label(l1);
269f3e95 1966 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1967 gen_set_label(l2);
fea0c503
AJ		 1968 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1969 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1970 tcg_temp_free(t0);
26d67362
AJ		 1971 } else {
1972 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1973 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1974 }
76a66253 1975 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1977}
1978/* srw & srw. */
26d67362
AJ		 1979GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1980{
fea0c503 1981 TCGv t0, t1;
26d67362
AJ		 1982 int l1, l2;
1983 l1 = gen_new_label();
1984 l2 = gen_new_label();
d9bce9d9 1985
a7812ae4 1986 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1987 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1988 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1989 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1990 tcg_gen_br(l2);
1991 gen_set_label(l1);
a7812ae4 1992 t1 = tcg_temp_new();
fea0c503
AJ		 1993 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1994 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1995 tcg_temp_free(t1);
26d67362 1996 gen_set_label(l2);
fea0c503 1997 tcg_temp_free(t0);
26d67362
AJ		 1998 if (unlikely(Rc(ctx->opcode) != 0))
1999 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2000}
d9bce9d9
JM		 2001#if defined(TARGET_PPC64)
2002/* sld & sld. */
26d67362
AJ		 2003GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2004{
fea0c503 2005 TCGv t0;
26d67362
AJ		 2006 int l1, l2;
2007 l1 = gen_new_label();
2008 l2 = gen_new_label();
2009
a7812ae4 2010 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2011 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2012 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2013 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2014 tcg_gen_br(l2);
2015 gen_set_label(l1);
fea0c503 2016 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2017 gen_set_label(l2);
fea0c503 2018 tcg_temp_free(t0);
26d67362
AJ		 2019 if (unlikely(Rc(ctx->opcode) != 0))
2020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2021}
d9bce9d9 2022/* srad & srad. */
26d67362
AJ		 2023GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2024{
a7812ae4
PB		 2025 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2026 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029}
d9bce9d9 2030/* sradi & sradi. */
b068d6a7 2031static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2032{
26d67362 2033 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2034 if (sh != 0) {
26d67362 2035 int l1, l2;
fea0c503 2036 TCGv t0;
26d67362
AJ		 2037 l1 = gen_new_label();
2038 l2 = gen_new_label();
a7812ae4 2039 t0 = tcg_temp_local_new();
26d67362 2040 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2041 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2042 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2043 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2044 tcg_gen_br(l2);
2045 gen_set_label(l1);
269f3e95 2046 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2047 gen_set_label(l2);
a9730017 2048 tcg_temp_free(t0);
26d67362
AJ		 2049 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2050 } else {
2051 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2052 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2053 }
d9bce9d9 2054 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2056}
c7697e1f 2057GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2058{
2059 gen_sradi(ctx, 0);
2060}
c7697e1f 2061GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2062{
2063 gen_sradi(ctx, 1);
2064}
2065/* srd & srd. */
26d67362
AJ		 2066GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2067{
fea0c503 2068 TCGv t0;
26d67362
AJ		 2069 int l1, l2;
2070 l1 = gen_new_label();
2071 l2 = gen_new_label();
2072
a7812ae4 2073 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2074 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2075 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2076 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2077 tcg_gen_br(l2);
2078 gen_set_label(l1);
fea0c503 2079 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2080 gen_set_label(l2);
fea0c503 2081 tcg_temp_free(t0);
26d67362
AJ		 2082 if (unlikely(Rc(ctx->opcode) != 0))
2083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2084}
d9bce9d9 2085#endif
79aceca5
FB		 2086
2087/*** Floating-Point arithmetic ***/
7c58044c 2088#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2089GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2090{ \
76a66253 2091 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2092 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2093 return; \
2094 } \
7c58044c 2095 gen_reset_fpstatus(); \
af12906f
AJ		 2096 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2097 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2098 if (isfloat) { \
af12906f 2099 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2100 } \
af12906f
AJ		 2101 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2102 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2103}
2104
7c58044c
JM		 2105#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2106_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2107_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2108
7c58044c
JM		 2109#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2110GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2111{ \
76a66253 2112 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2113 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2114 return; \
2115 } \
7c58044c 2116 gen_reset_fpstatus(); \
af12906f
AJ		 2117 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2118 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2119 if (isfloat) { \
af12906f 2120 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2121 } \
af12906f
AJ		 2122 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2123 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2124}
7c58044c
JM		 2125#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2126_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2127_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2128
7c58044c
JM		 2129#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2130GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2131{ \
76a66253 2132 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2133 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2134 return; \
2135 } \
7c58044c 2136 gen_reset_fpstatus(); \
af12906f
AJ		 2137 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2138 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2139 if (isfloat) { \
af12906f 2140 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2141 } \
af12906f
AJ		 2142 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2143 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2144}
7c58044c
JM		 2145#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2146_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2147_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2148
7c58044c 2149#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2150GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2151{ \
76a66253 2152 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2153 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2154 return; \
2155 } \
7c58044c 2156 gen_reset_fpstatus(); \
af12906f
AJ		 2157 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2158 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2159 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2160}
2161
7c58044c 2162#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2163GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2164{ \
76a66253 2165 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2166 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2167 return; \
2168 } \
7c58044c 2169 gen_reset_fpstatus(); \
af12906f
AJ		 2170 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2171 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2172 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2173}
2174
9a64fbe4 2175/* fadd - fadds */
7c58044c 2176GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2177/* fdiv - fdivs */
7c58044c 2178GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2179/* fmul - fmuls */
7c58044c 2180GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2181
d7e4b87e 2182/* fre */
7c58044c 2183GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2184
a750fc0b 2185/* fres */
7c58044c 2186GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2187
a750fc0b 2188/* frsqrte */
7c58044c
JM		 2189GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2190
2191/* frsqrtes */
af12906f 2192GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2193{
af12906f 2194 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2195 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2196 return;
2197 }
2198 gen_reset_fpstatus();
2199 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2200 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2201 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2202}
79aceca5 2203
a750fc0b 2204/* fsel */
7c58044c 2205_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2206/* fsub - fsubs */
7c58044c 2207GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2208/* Optional: */
2209/* fsqrt */
a750fc0b 2210GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2211{
76a66253 2212 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2213 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2214 return;
2215 }
7c58044c 2216 gen_reset_fpstatus();
af12906f
AJ		 2217 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2218 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2219}
79aceca5 2220
a750fc0b 2221GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2222{
76a66253 2223 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2224 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2225 return;
2226 }
7c58044c 2227 gen_reset_fpstatus();
af12906f
AJ		 2228 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2229 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2230 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2231}
2232
2233/*** Floating-Point multiply-and-add ***/
4ecc3190 2234/* fmadd - fmadds */
7c58044c 2235GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2236/* fmsub - fmsubs */
7c58044c 2237GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2238/* fnmadd - fnmadds */
7c58044c 2239GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2240/* fnmsub - fnmsubs */
7c58044c 2241GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2242
2243/*** Floating-Point round & convert ***/
2244/* fctiw */
7c58044c 2245GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2246/* fctiwz */
7c58044c 2247GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2248/* frsp */
7c58044c 2249GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2250#if defined(TARGET_PPC64)
2251/* fcfid */
7c58044c 2252GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2253/* fctid */
7c58044c 2254GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2255/* fctidz */
7c58044c 2256GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2257#endif
79aceca5 2258
d7e4b87e 2259/* frin */
7c58044c 2260GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2261/* friz */
7c58044c 2262GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2263/* frip */
7c58044c 2264GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2265/* frim */
7c58044c 2266GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2267
79aceca5
FB		 2268/*** Floating-Point compare ***/
2269/* fcmpo */
76a66253 2270GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2271{
76a66253 2272 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2273 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2274 return;
2275 }
7c58044c 2276 gen_reset_fpstatus();
af12906f
AJ		 2277 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2278 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2279 gen_helper_float_check_status();
79aceca5
FB		 2280}
2281
2282/* fcmpu */
76a66253 2283GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2284{
76a66253 2285 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2286 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2287 return;
2288 }
7c58044c 2289 gen_reset_fpstatus();
af12906f
AJ		 2290 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2291 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2292 gen_helper_float_check_status();
79aceca5
FB		 2293}
2294
9a64fbe4
FB		 2295/*** Floating-point move ***/
2296/* fabs */
7c58044c
JM		 2297/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2298GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2299
2300/* fmr - fmr. */
7c58044c 2301/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2302GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2303{
76a66253 2304 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2305 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2306 return;
2307 }
af12906f
AJ		 2308 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2309 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2310}
2311
2312/* fnabs */
7c58044c
JM		 2313/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2314GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2315/* fneg */
7c58044c
JM		 2316/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2317GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2318
79aceca5
FB		 2319/*** Floating-Point status & ctrl register ***/
2320/* mcrfs */
2321GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2322{
7c58044c
JM		 2323 int bfa;
2324
76a66253 2325 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2326 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2327 return;
2328 }
7c58044c
JM		 2329 gen_optimize_fprf();
2330 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2331 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2332 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2333 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2334}
2335
2336/* mffs */
2337GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2338{
76a66253 2339 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2340 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2341 return;
2342 }
7c58044c
JM		 2343 gen_optimize_fprf();
2344 gen_reset_fpstatus();
af12906f
AJ		 2345 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2346 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2347}
2348
2349/* mtfsb0 */
2350GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2351{
fb0eaffc 2352 uint8_t crb;
3b46e624 2353
76a66253 2354 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2355 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2356 return;
2357 }
7c58044c
JM		 2358 crb = 32 - (crbD(ctx->opcode) >> 2);
2359 gen_optimize_fprf();
2360 gen_reset_fpstatus();
2361 if (likely(crb != 30 && crb != 29))
af12906f 2362 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
7c58044c 2363 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2364 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2365 }
79aceca5
FB		 2366}
2367
2368/* mtfsb1 */
2369GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2370{
fb0eaffc 2371 uint8_t crb;
3b46e624 2372
76a66253 2373 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2374 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2375 return;
2376 }
7c58044c
JM		 2377 crb = 32 - (crbD(ctx->opcode) >> 2);
2378 gen_optimize_fprf();
2379 gen_reset_fpstatus();
2380 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2381 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
0f2f39c2 2382 TCGv_i32 t0 = tcg_const_i32(crb);
af12906f 2383 gen_helper_fpscr_setbit(t0);
0f2f39c2 2384 tcg_temp_free_i32(t0);
af12906f 2385 }
7c58044c 2386 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2387 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2388 }
2389 /* We can raise a differed exception */
af12906f 2390 gen_helper_float_check_status();
79aceca5
FB		 2391}
2392
2393/* mtfsf */
2394GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2395{
0f2f39c2 2396 TCGv_i32 t0;
af12906f 2397
76a66253 2398 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2399 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2400 return;
2401 }
7c58044c 2402 gen_optimize_fprf();
7c58044c 2403 gen_reset_fpstatus();
af12906f
AJ		 2404 t0 = tcg_const_i32(FM(ctx->opcode));
2405 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2406 tcg_temp_free_i32(t0);
7c58044c 2407 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2408 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2409 }
2410 /* We can raise a differed exception */
af12906f 2411 gen_helper_float_check_status();
79aceca5
FB		 2412}
2413
2414/* mtfsfi */
2415GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2416{
7c58044c 2417 int bf, sh;
0f2f39c2
AJ		 2418 TCGv_i64 t0;
2419 TCGv_i32 t1;
7c58044c 2420
76a66253 2421 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2422 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2423 return;
2424 }
7c58044c
JM		 2425 bf = crbD(ctx->opcode) >> 2;
2426 sh = 7 - bf;
2427 gen_optimize_fprf();
7c58044c 2428 gen_reset_fpstatus();
0f2f39c2 2429 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2430 t1 = tcg_const_i32(1 << sh);
2431 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2432 tcg_temp_free_i64(t0);
2433 tcg_temp_free_i32(t1);
7c58044c 2434 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2435 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2436 }
2437 /* We can raise a differed exception */
af12906f 2438 gen_helper_float_check_status();
79aceca5
FB		 2439}
2440
76a66253
JM		 2441/*** Addressing modes ***/
2442/* Register indirect with immediate index : EA = (rA|0) + SIMM */
76db3ba4 2443static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
76a66253
JM		 2444{
2445 target_long simm = SIMM(ctx->opcode);
2446
be147d08 2447 simm &= ~maskl;
76db3ba4
AJ		 2448 if (rA(ctx->opcode) == 0) {
2449#if defined(TARGET_PPC64)
2450 if (!ctx->sf_mode) {
2451 tcg_gen_movi_tl(EA, (uint32_t)simm);
2452 } else
2453#endif
e2be8d8d 2454 tcg_gen_movi_tl(EA, simm);
76db3ba4 2455 } else if (likely(simm != 0)) {
e2be8d8d 2456 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
76db3ba4
AJ		 2457#if defined(TARGET_PPC64)
2458 if (!ctx->sf_mode) {
2459 tcg_gen_ext32u_tl(EA, EA);
2460 }
2461#endif
2462 } else {
2463#if defined(TARGET_PPC64)
2464 if (!ctx->sf_mode) {
2465 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2466 } else
2467#endif
e2be8d8d 2468 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2469 }
76a66253
JM		 2470}
2471
76db3ba4 2472static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
76a66253 2473{
76db3ba4
AJ		 2474 if (rA(ctx->opcode) == 0) {
2475#if defined(TARGET_PPC64)
2476 if (!ctx->sf_mode) {
2477 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2478 } else
2479#endif
e2be8d8d 2480 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
76db3ba4 2481 } else {
e2be8d8d 2482 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76db3ba4
AJ		 2483#if defined(TARGET_PPC64)
2484 if (!ctx->sf_mode) {
2485 tcg_gen_ext32u_tl(EA, EA);
2486 }
2487#endif
2488 }
76a66253
JM		 2489}
2490
76db3ba4 2491static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
76a66253 2492{
76db3ba4 2493 if (rA(ctx->opcode) == 0) {
e2be8d8d 2494 tcg_gen_movi_tl(EA, 0);
76db3ba4
AJ		 2495 } else {
2496#if defined(TARGET_PPC64)
2497 if (!ctx->sf_mode) {
2498 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2499 } else
2500#endif
2501 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2502 }
2503}
2504
2505static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2506{
2507 tcg_gen_addi_tl(ret, arg1, val);
2508#if defined(TARGET_PPC64)
2509 if (!ctx->sf_mode) {
2510 tcg_gen_ext32u_tl(ret, ret);
2511 }
2512#endif
76a66253
JM		 2513}
2514
cf360a32
AJ		 2515static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2516{
2517 int l1 = gen_new_label();
2518 TCGv t0 = tcg_temp_new();
2519 TCGv_i32 t1, t2;
2520 /* NIP cannot be restored if the memory exception comes from an helper */
2521 gen_update_nip(ctx, ctx->nip - 4);
2522 tcg_gen_andi_tl(t0, EA, mask);
2523 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2524 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2525 t2 = tcg_const_i32(0);
2526 gen_helper_raise_exception_err(t1, t2);
2527 tcg_temp_free_i32(t1);
2528 tcg_temp_free_i32(t2);
2529 gen_set_label(l1);
2530 tcg_temp_free(t0);
2531}
2532
7863667f 2533/*** Integer load ***/
76db3ba4
AJ		 2534static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2535{
2536 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2537}
2538
2539static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2540{
2541 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2542}
2543
2544static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2545{
2546 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2547 if (unlikely(ctx->le_mode)) {
b61f2753 2548#if defined(TARGET_PPC64)
76db3ba4
AJ		 2549 TCGv_i32 t0 = tcg_temp_new_i32();
2550 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2551 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2552 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2553 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2554#else
2555 tcg_gen_bswap16_i32(arg1, arg1);
2556#endif
2557 }
b61f2753
AJ		 2558}
2559
76db3ba4 2560static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2561{
76db3ba4
AJ		 2562 if (unlikely(ctx->le_mode)) {
2563#if defined(TARGET_PPC64)
a7812ae4 2564 TCGv_i32 t0;
76db3ba4 2565 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
a7812ae4 2566 t0 = tcg_temp_new_i32();
76db3ba4 2567 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2568 tcg_gen_bswap16_i32(t0, t0);
76db3ba4
AJ		 2569 tcg_gen_extu_i32_tl(arg1, t0);
2570 tcg_gen_ext16s_tl(arg1, arg1);
a7812ae4 2571 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2572#else
2573 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2574 tcg_gen_bswap16_i32(arg1, arg1);
2575 tcg_gen_ext16s_i32(arg1, arg1);
2576#endif
2577 } else {
2578 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2579 }
b61f2753
AJ		 2580}
2581
76db3ba4 2582static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2583{
76db3ba4
AJ		 2584 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2585 if (unlikely(ctx->le_mode)) {
2586#if defined(TARGET_PPC64)
2587 TCGv_i32 t0 = tcg_temp_new_i32();
2588 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2589 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2590 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2591 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2592#else
2593 tcg_gen_bswap_i32(arg1, arg1);
2594#endif
2595 }
b61f2753
AJ		 2596}
2597
76db3ba4
AJ		 2598#if defined(TARGET_PPC64)
2599static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2600{
76db3ba4 2601 if (unlikely(ctx->mem_idx)) {
a7812ae4 2602 TCGv_i32 t0;
76db3ba4 2603 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
a7812ae4 2604 t0 = tcg_temp_new_i32();
76db3ba4 2605 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2606 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2607 tcg_gen_ext_i32_tl(arg1, t0);
a7812ae4 2608 tcg_temp_free_i32(t0);
b61f2753 2609 } else
76db3ba4 2610 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753 2611}
76db3ba4 2612#endif
b61f2753 2613
76db3ba4 2614static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2615{
76db3ba4
AJ		 2616 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2617 if (unlikely(ctx->le_mode)) {
2618 tcg_gen_bswap_i64(arg1, arg1);
2619 }
b61f2753
AJ		 2620}
2621
76db3ba4 2622static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2623{
76db3ba4 2624 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2625}
2626
76db3ba4 2627static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2628{
76db3ba4
AJ		 2629 if (unlikely(ctx->le_mode)) {
2630#if defined(TARGET_PPC64)
a7812ae4 2631 TCGv_i32 t0;
76db3ba4 2632 TCGv t1;
a7812ae4 2633 t0 = tcg_temp_new_i32();
76db3ba4 2634 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694
AJ		 2635 tcg_gen_ext16u_i32(t0, t0);
2636 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2637 t1 = tcg_temp_new();
ea363694 2638 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2639 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2640 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2641 tcg_temp_free(t1);
2642#else
2643 TCGv t0 = tcg_temp_new();
2644 tcg_gen_ext16u_tl(t0, arg1);
2645 tcg_gen_bswap16_i32(t0, t0);
2646 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2647 tcg_temp_free(t0);
2648#endif
2649 } else {
2650 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2651 }
b61f2753
AJ		 2652}
2653
76db3ba4 2654static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2655{
76db3ba4
AJ		 2656 if (unlikely(ctx->le_mode)) {
2657#if defined(TARGET_PPC64)
a7812ae4 2658 TCGv_i32 t0;
76db3ba4 2659 TCGv t1;
a7812ae4 2660 t0 = tcg_temp_new_i32();
76db3ba4 2661 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2662 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2663 t1 = tcg_temp_new();
ea363694 2664 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2665 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2666 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2667 tcg_temp_free(t1);
2668#else
2669 TCGv t0 = tcg_temp_new_i32();
2670 tcg_gen_bswap_i32(t0, arg1);
2671 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2672 tcg_temp_free(t0);
2673#endif
2674 } else {
2675 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2676 }
b61f2753
AJ		 2677}
2678
76db3ba4 2679static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2680{
76db3ba4 2681 if (unlikely(ctx->le_mode)) {
a7812ae4 2682 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4
AJ		 2683 tcg_gen_bswap_i64(t0, arg1);
2684 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2685 tcg_temp_free_i64(t0);
b61f2753 2686 } else
76db3ba4 2687 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2688}
2689
0c8aacd4
AJ		 2690#define GEN_LD(name, ldop, opc, type) \
2691GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2692{ \
76db3ba4
AJ		 2693 TCGv EA; \
2694 gen_set_access_type(ctx, ACCESS_INT); \
2695 EA = tcg_temp_new(); \
2696 gen_addr_imm_index(ctx, EA, 0); \
2697 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2698 tcg_temp_free(EA); \
79aceca5
FB		 2699}
2700
0c8aacd4
AJ		 2701#define GEN_LDU(name, ldop, opc, type) \
2702GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2703{ \
b61f2753 2704 TCGv EA; \
76a66253
JM		 2705 if (unlikely(rA(ctx->opcode) == 0 || \
2706 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2707 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2708 return; \
9a64fbe4 2709 } \
76db3ba4 2710 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2711 EA = tcg_temp_new(); \
9d53c753 2712 if (type == PPC_64B) \
76db3ba4 2713 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2714 else \
76db3ba4
AJ		 2715 gen_addr_imm_index(ctx, EA, 0); \
2716 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2717 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2718 tcg_temp_free(EA); \
79aceca5
FB		 2719}
2720
0c8aacd4
AJ		 2721#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2722GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2723{ \
b61f2753 2724 TCGv EA; \
76a66253
JM		 2725 if (unlikely(rA(ctx->opcode) == 0 || \
2726 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2727 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2728 return; \
9a64fbe4 2729 } \
76db3ba4 2730 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2731 EA = tcg_temp_new(); \
76db3ba4
AJ		 2732 gen_addr_reg_index(ctx, EA); \
2733 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2734 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2735 tcg_temp_free(EA); \
79aceca5
FB		 2736}
2737
0c8aacd4
AJ		 2738#define GEN_LDX(name, ldop, opc2, opc3, type) \
2739GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2740{ \
76db3ba4
AJ		 2741 TCGv EA; \
2742 gen_set_access_type(ctx, ACCESS_INT); \
2743 EA = tcg_temp_new(); \
2744 gen_addr_reg_index(ctx, EA); \
2745 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2746 tcg_temp_free(EA); \
79aceca5
FB		 2747}
2748
0c8aacd4
AJ		 2749#define GEN_LDS(name, ldop, op, type) \
2750GEN_LD(name, ldop, op | 0x20, type); \
2751GEN_LDU(name, ldop, op | 0x21, type); \
2752GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2753GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2754
2755/* lbz lbzu lbzux lbzx */
0c8aacd4 2756GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2757/* lha lhau lhaux lhax */
0c8aacd4 2758GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2759/* lhz lhzu lhzux lhzx */
0c8aacd4 2760GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2761/* lwz lwzu lwzux lwzx */
0c8aacd4 2762GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2763#if defined(TARGET_PPC64)
d9bce9d9 2764/* lwaux */
0c8aacd4 2765GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2766/* lwax */
0c8aacd4 2767GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2768/* ldux */
0c8aacd4 2769GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2770/* ldx */
0c8aacd4 2771GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2772GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2773{
b61f2753 2774 TCGv EA;
d9bce9d9
JM		 2775 if (Rc(ctx->opcode)) {
2776 if (unlikely(rA(ctx->opcode) == 0 ||
2777 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2778 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2779 return;
2780 }
2781 }
76db3ba4 2782 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2783 EA = tcg_temp_new();
76db3ba4 2784 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2785 if (ctx->opcode & 0x02) {
2786 /* lwa (lwau is undefined) */
76db3ba4 2787 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2788 } else {
2789 /* ld - ldu */
76db3ba4 2790 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2791 }
d9bce9d9 2792 if (Rc(ctx->opcode))
b61f2753
AJ		 2793 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2794 tcg_temp_free(EA);
d9bce9d9 2795}
be147d08
JM		 2796/* lq */
2797GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2798{
2799#if defined(CONFIG_USER_ONLY)
e06fcd75 2800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2801#else
2802 int ra, rd;
b61f2753 2803 TCGv EA;
be147d08
JM		 2804
2805 /* Restore CPU state */
76db3ba4 2806 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2807 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2808 return;
2809 }
2810 ra = rA(ctx->opcode);
2811 rd = rD(ctx->opcode);
2812 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2813 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2814 return;
2815 }
76db3ba4 2816 if (unlikely(ctx->le_mode)) {
be147d08 2817 /* Little-endian mode is not handled */
e06fcd75 2818 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2819 return;
2820 }
76db3ba4 2821 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2822 EA = tcg_temp_new();
76db3ba4
AJ		 2823 gen_addr_imm_index(ctx, EA, 0x0F);
2824 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2825 gen_addr_add(ctx, EA, EA, 8);
2826 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
b61f2753 2827 tcg_temp_free(EA);
be147d08
JM		 2828#endif
2829}
d9bce9d9 2830#endif
79aceca5
FB		 2831
2832/*** Integer store ***/
0c8aacd4
AJ		 2833#define GEN_ST(name, stop, opc, type) \
2834GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2835{ \
76db3ba4
AJ		 2836 TCGv EA; \
2837 gen_set_access_type(ctx, ACCESS_INT); \
2838 EA = tcg_temp_new(); \
2839 gen_addr_imm_index(ctx, EA, 0); \
2840 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2841 tcg_temp_free(EA); \
79aceca5
FB		 2842}
2843
0c8aacd4
AJ		 2844#define GEN_STU(name, stop, opc, type) \
2845GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2846{ \
b61f2753 2847 TCGv EA; \
76a66253 2848 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2850 return; \
9a64fbe4 2851 } \
76db3ba4 2852 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2853 EA = tcg_temp_new(); \
9d53c753 2854 if (type == PPC_64B) \
76db3ba4 2855 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2856 else \
76db3ba4
AJ		 2857 gen_addr_imm_index(ctx, EA, 0); \
2858 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2860 tcg_temp_free(EA); \
79aceca5
FB		 2861}
2862
0c8aacd4
AJ		 2863#define GEN_STUX(name, stop, opc2, opc3, type) \
2864GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2865{ \
b61f2753 2866 TCGv EA; \
76a66253 2867 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2868 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2869 return; \
9a64fbe4 2870 } \
76db3ba4 2871 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2872 EA = tcg_temp_new(); \
76db3ba4
AJ		 2873 gen_addr_reg_index(ctx, EA); \
2874 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2875 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2876 tcg_temp_free(EA); \
79aceca5
FB		 2877}
2878
0c8aacd4
AJ		 2879#define GEN_STX(name, stop, opc2, opc3, type) \
2880GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2881{ \
76db3ba4
AJ		 2882 TCGv EA; \
2883 gen_set_access_type(ctx, ACCESS_INT); \
2884 EA = tcg_temp_new(); \
2885 gen_addr_reg_index(ctx, EA); \
2886 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2887 tcg_temp_free(EA); \
79aceca5
FB		 2888}
2889
0c8aacd4
AJ		 2890#define GEN_STS(name, stop, op, type) \
2891GEN_ST(name, stop, op | 0x20, type); \
2892GEN_STU(name, stop, op | 0x21, type); \
2893GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2894GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2895
2896/* stb stbu stbux stbx */
0c8aacd4 2897GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2898/* sth sthu sthux sthx */
0c8aacd4 2899GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2900/* stw stwu stwux stwx */
0c8aacd4 2901GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2902#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2903GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2904GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2905GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2906{
be147d08 2907 int rs;
b61f2753 2908 TCGv EA;
be147d08
JM		 2909
2910 rs = rS(ctx->opcode);
2911 if ((ctx->opcode & 0x3) == 0x2) {
2912#if defined(CONFIG_USER_ONLY)
e06fcd75 2913 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2914#else
2915 /* stq */
76db3ba4 2916 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2918 return;
2919 }
2920 if (unlikely(rs & 1)) {
e06fcd75 2921 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2922 return;
2923 }
76db3ba4 2924 if (unlikely(ctx->le_mode)) {
be147d08 2925 /* Little-endian mode is not handled */
e06fcd75 2926 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2927 return;
2928 }
76db3ba4 2929 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2930 EA = tcg_temp_new();
76db3ba4
AJ		 2931 gen_addr_imm_index(ctx, EA, 0x03);
2932 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2933 gen_addr_add(ctx, EA, EA, 8);
2934 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
b61f2753 2935 tcg_temp_free(EA);
be147d08
JM		 2936#endif
2937 } else {
2938 /* std / stdu */
2939 if (Rc(ctx->opcode)) {
2940 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2941 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2942 return;
2943 }
2944 }
76db3ba4 2945 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2946 EA = tcg_temp_new();
76db3ba4
AJ		 2947 gen_addr_imm_index(ctx, EA, 0x03);
2948 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 2949 if (Rc(ctx->opcode))
b61f2753
AJ		 2950 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2951 tcg_temp_free(EA);
d9bce9d9 2952 }
d9bce9d9
JM		 2953}
2954#endif
79aceca5
FB		 2955/*** Integer load and store with byte reverse ***/
2956/* lhbrx */
76db3ba4 2957static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2958{
76db3ba4
AJ		 2959 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2960 if (likely(!ctx->le_mode)) {
2961#if defined(TARGET_PPC64)
2962 TCGv_i32 t0 = tcg_temp_new_i32();
2963 tcg_gen_trunc_tl_i32(t0, arg1);
2964 tcg_gen_bswap16_i32(t0, t0);
2965 tcg_gen_extu_i32_tl(arg1, t0);
2966 tcg_temp_free_i32(t0);
2967#else
2968 tcg_gen_bswap16_i32(arg1, arg1);
2969#endif
2970 }
b61f2753 2971}
0c8aacd4 2972GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 2973
79aceca5 2974/* lwbrx */
76db3ba4 2975static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2976{
76db3ba4
AJ		 2977 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2978 if (likely(!ctx->le_mode)) {
2979#if defined(TARGET_PPC64)
2980 TCGv_i32 t0 = tcg_temp_new_i32();
2981 tcg_gen_trunc_tl_i32(t0, arg1);
2982 tcg_gen_bswap_i32(t0, t0);
2983 tcg_gen_extu_i32_tl(arg1, t0);
2984 tcg_temp_free_i32(t0);
2985#else
2986 tcg_gen_bswap_i32(arg1, arg1);
2987#endif
2988 }
b61f2753 2989}
0c8aacd4 2990GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 2991
79aceca5 2992/* sthbrx */
76db3ba4 2993static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2994{
76db3ba4
AJ		 2995 if (likely(!ctx->le_mode)) {
2996#if defined(TARGET_PPC64)
2997 TCGv_i32 t0;
2998 TCGv t1;
2999 t0 = tcg_temp_new_i32();
3000 tcg_gen_trunc_tl_i32(t0, arg1);
3001 tcg_gen_ext16u_i32(t0, t0);
3002 tcg_gen_bswap16_i32(t0, t0);
3003 t1 = tcg_temp_new();
3004 tcg_gen_extu_i32_tl(t1, t0);
3005 tcg_temp_free_i32(t0);
3006 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3007 tcg_temp_free(t1);
3008#else
3009 TCGv t0 = tcg_temp_new();
3010 tcg_gen_ext16u_tl(t0, arg1);
3011 tcg_gen_bswap16_i32(t0, t0);
3012 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3013 tcg_temp_free(t0);
3014#endif
3015 } else {
3016 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3017 }
b61f2753 3018}
0c8aacd4 3019GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3020
79aceca5 3021/* stwbrx */
76db3ba4 3022static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3023{
76db3ba4
AJ		 3024 if (likely(!ctx->le_mode)) {
3025#if defined(TARGET_PPC64)
3026 TCGv_i32 t0;
3027 TCGv t1;
3028 t0 = tcg_temp_new_i32();
3029 tcg_gen_trunc_tl_i32(t0, arg1);
3030 tcg_gen_bswap_i32(t0, t0);
3031 t1 = tcg_temp_new();
3032 tcg_gen_extu_i32_tl(t1, t0);
3033 tcg_temp_free_i32(t0);
3034 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3035 tcg_temp_free(t1);
3036#else
3037 TCGv t0 = tcg_temp_new_i32();
3038 tcg_gen_bswap_i32(t0, arg1);
3039 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3040 tcg_temp_free(t0);
3041#endif
3042 } else {
3043 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3044 }
b61f2753 3045}
0c8aacd4 3046GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3047
3048/*** Integer load and store multiple ***/
3049/* lmw */
3050GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3051{
76db3ba4
AJ		 3052 TCGv t0;
3053 TCGv_i32 t1;
3054 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3055 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3056 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3057 t0 = tcg_temp_new();
3058 t1 = tcg_const_i32(rD(ctx->opcode));
3059 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3060 gen_helper_lmw(t0, t1);
3061 tcg_temp_free(t0);
3062 tcg_temp_free_i32(t1);
79aceca5
FB		 3063}
3064
3065/* stmw */
3066GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3067{
76db3ba4
AJ		 3068 TCGv t0;
3069 TCGv_i32 t1;
3070 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3071 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3072 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3073 t0 = tcg_temp_new();
3074 t1 = tcg_const_i32(rS(ctx->opcode));
3075 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3076 gen_helper_stmw(t0, t1);
3077 tcg_temp_free(t0);
3078 tcg_temp_free_i32(t1);
79aceca5
FB		 3079}
3080
3081/*** Integer load and store strings ***/
3082/* lswi */
3fc6c082 3083/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3084 * rA is in the range of registers to be loaded.
3085 * In an other hand, IBM says this is valid, but rA won't be loaded.
3086 * For now, I'll follow the spec...
3087 */
05332d70 3088GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3089{
dfbc799d
AJ		 3090 TCGv t0;
3091 TCGv_i32 t1, t2;
79aceca5
FB		 3092 int nb = NB(ctx->opcode);
3093 int start = rD(ctx->opcode);
9a64fbe4 3094 int ra = rA(ctx->opcode);
79aceca5
FB		 3095 int nr;
3096
3097 if (nb == 0)
3098 nb = 32;
3099 nr = nb / 4;
76a66253
JM		 3100 if (unlikely(((start + nr) > 32 &&
3101 start <= ra && (start + nr - 32) > ra) ||
3102 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3103 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3104 return;
297d8e62 3105 }
76db3ba4 3106 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3107 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3108 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3109 t0 = tcg_temp_new();
76db3ba4 3110 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3111 t1 = tcg_const_i32(nb);
3112 t2 = tcg_const_i32(start);
3113 gen_helper_lsw(t0, t1, t2);
3114 tcg_temp_free(t0);
3115 tcg_temp_free_i32(t1);
3116 tcg_temp_free_i32(t2);
79aceca5
FB		 3117}
3118
3119/* lswx */
05332d70 3120GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3121{
76db3ba4
AJ		 3122 TCGv t0;
3123 TCGv_i32 t1, t2, t3;
3124 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3125 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3126 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3127 t0 = tcg_temp_new();
3128 gen_addr_reg_index(ctx, t0);
3129 t1 = tcg_const_i32(rD(ctx->opcode));
3130 t2 = tcg_const_i32(rA(ctx->opcode));
3131 t3 = tcg_const_i32(rB(ctx->opcode));
dfbc799d
AJ		 3132 gen_helper_lswx(t0, t1, t2, t3);
3133 tcg_temp_free(t0);
3134 tcg_temp_free_i32(t1);
3135 tcg_temp_free_i32(t2);
3136 tcg_temp_free_i32(t3);
79aceca5
FB		 3137}
3138
3139/* stswi */
05332d70 3140GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3141{
76db3ba4
AJ		 3142 TCGv t0;
3143 TCGv_i32 t1, t2;
4b3686fa 3144 int nb = NB(ctx->opcode);
76db3ba4 3145 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3146 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3147 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3148 t0 = tcg_temp_new();
3149 gen_addr_register(ctx, t0);
4b3686fa
FB		 3150 if (nb == 0)
3151 nb = 32;
dfbc799d 3152 t1 = tcg_const_i32(nb);
76db3ba4 3153 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3154 gen_helper_stsw(t0, t1, t2);
3155 tcg_temp_free(t0);
3156 tcg_temp_free_i32(t1);
3157 tcg_temp_free_i32(t2);
79aceca5
FB		 3158}
3159
3160/* stswx */
05332d70 3161GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3162{
76db3ba4
AJ		 3163 TCGv t0;
3164 TCGv_i32 t1, t2;
3165 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3166 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3167 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3168 t0 = tcg_temp_new();
3169 gen_addr_reg_index(ctx, t0);
3170 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3171 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3172 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3173 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3174 gen_helper_stsw(t0, t1, t2);
3175 tcg_temp_free(t0);
3176 tcg_temp_free_i32(t1);
3177 tcg_temp_free_i32(t2);
79aceca5
FB		 3178}
3179
3180/*** Memory synchronisation ***/
3181/* eieio */
0db1b20e 3182GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3183{
79aceca5
FB		 3184}
3185
3186/* isync */
0db1b20e 3187GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3188{
e06fcd75 3189 gen_stop_exception(ctx);
79aceca5
FB		 3190}
3191
111bfab3 3192/* lwarx */
76a66253 3193GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3194{
76db3ba4
AJ		 3195 TCGv t0;
3196 gen_set_access_type(ctx, ACCESS_RES);
3197 t0 = tcg_temp_local_new();
3198 gen_addr_reg_index(ctx, t0);
cf360a32 3199 gen_check_align(ctx, t0, 0x03);
76db3ba4 3200 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3201 tcg_gen_mov_tl(cpu_reserve, t0);
3202 tcg_temp_free(t0);
79aceca5
FB		 3203}
3204
3205/* stwcx. */
c7697e1f 3206GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3207{
76db3ba4
AJ		 3208 int l1;
3209 TCGv t0;
3210 gen_set_access_type(ctx, ACCESS_RES);
3211 t0 = tcg_temp_local_new();
3212 gen_addr_reg_index(ctx, t0);
cf360a32 3213 gen_check_align(ctx, t0, 0x03);
cf360a32
AJ		 3214 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3215 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3216 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3217 l1 = gen_new_label();
cf360a32
AJ		 3218 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3219 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3220 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3221 gen_set_label(l1);
3222 tcg_gen_movi_tl(cpu_reserve, -1);
3223 tcg_temp_free(t0);
79aceca5
FB		 3224}
3225
426613db 3226#if defined(TARGET_PPC64)
426613db 3227/* ldarx */
a750fc0b 3228GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3229{
76db3ba4
AJ		 3230 TCGv t0;
3231 gen_set_access_type(ctx, ACCESS_RES);
3232 t0 = tcg_temp_local_new();
3233 gen_addr_reg_index(ctx, t0);
cf360a32 3234 gen_check_align(ctx, t0, 0x07);
76db3ba4 3235 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3236 tcg_gen_mov_tl(cpu_reserve, t0);
3237 tcg_temp_free(t0);
426613db
JM		 3238}
3239
3240/* stdcx. */
c7697e1f 3241GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3242{
76db3ba4
AJ		 3243 int l1;
3244 TCGv t0;
3245 gen_set_access_type(ctx, ACCESS_RES);
3246 t0 = tcg_temp_local_new();
3247 gen_addr_reg_index(ctx, t0);
cf360a32 3248 gen_check_align(ctx, t0, 0x07);
cf360a32
AJ		 3249 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3250 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3251 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3252 l1 = gen_new_label();
cf360a32
AJ		 3253 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3254 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3255 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3256 gen_set_label(l1);
3257 tcg_gen_movi_tl(cpu_reserve, -1);
3258 tcg_temp_free(t0);
426613db
JM		 3259}
3260#endif /* defined(TARGET_PPC64) */
3261
79aceca5 3262/* sync */
a902d886 3263GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3264{
79aceca5
FB		 3265}
3266
0db1b20e
JM		 3267/* wait */
3268GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3269{
931ff272
AJ		 3270 TCGv_i32 t0 = tcg_temp_new_i32();
3271 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3272 tcg_temp_free_i32(t0);
0db1b20e 3273 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3274 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3275}
3276
79aceca5 3277/*** Floating-point load ***/
a0d7d5a7
AJ		 3278#define GEN_LDF(name, ldop, opc, type) \
3279GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3280{ \
a0d7d5a7 3281 TCGv EA; \
76a66253 3282 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3283 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3284 return; \
3285 } \
76db3ba4 3286 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3287 EA = tcg_temp_new(); \
76db3ba4
AJ		 3288 gen_addr_imm_index(ctx, EA, 0); \
3289 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3290 tcg_temp_free(EA); \
79aceca5
FB		 3291}
3292
a0d7d5a7
AJ		 3293#define GEN_LDUF(name, ldop, opc, type) \
3294GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3295{ \
a0d7d5a7 3296 TCGv EA; \
76a66253 3297 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3298 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3299 return; \
3300 } \
76a66253 3301 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3302 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3303 return; \
9a64fbe4 3304 } \
76db3ba4 3305 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3306 EA = tcg_temp_new(); \
76db3ba4
AJ		 3307 gen_addr_imm_index(ctx, EA, 0); \
3308 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3309 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3310 tcg_temp_free(EA); \
79aceca5
FB		 3311}
3312
a0d7d5a7
AJ		 3313#define GEN_LDUXF(name, ldop, opc, type) \
3314GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3315{ \
a0d7d5a7 3316 TCGv EA; \
76a66253 3317 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3318 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3319 return; \
3320 } \
76a66253 3321 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3322 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3323 return; \
9a64fbe4 3324 } \
76db3ba4 3325 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3326 EA = tcg_temp_new(); \
76db3ba4
AJ		 3327 gen_addr_reg_index(ctx, EA); \
3328 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3329 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3330 tcg_temp_free(EA); \
79aceca5
FB		 3331}
3332
a0d7d5a7
AJ		 3333#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3334GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3335{ \
a0d7d5a7 3336 TCGv EA; \
76a66253 3337 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3338 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3339 return; \
3340 } \
76db3ba4 3341 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3342 EA = tcg_temp_new(); \
76db3ba4
AJ		 3343 gen_addr_reg_index(ctx, EA); \
3344 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3345 tcg_temp_free(EA); \
79aceca5
FB		 3346}
3347
a0d7d5a7
AJ		 3348#define GEN_LDFS(name, ldop, op, type) \
3349GEN_LDF(name, ldop, op | 0x20, type); \
3350GEN_LDUF(name, ldop, op | 0x21, type); \
3351GEN_LDUXF(name, ldop, op | 0x01, type); \
3352GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3353
76db3ba4 3354static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3355{
3356 TCGv t0 = tcg_temp_new();
3357 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3358 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3359 tcg_gen_trunc_tl_i32(t1, t0);
3360 tcg_temp_free(t0);
3361 gen_helper_float32_to_float64(arg1, t1);
3362 tcg_temp_free_i32(t1);
3363}
79aceca5 3364
a0d7d5a7
AJ		 3365 /* lfd lfdu lfdux lfdx */
3366GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3367 /* lfs lfsu lfsux lfsx */
3368GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3369
3370/*** Floating-point store ***/
a0d7d5a7
AJ		 3371#define GEN_STF(name, stop, opc, type) \
3372GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3373{ \
a0d7d5a7 3374 TCGv EA; \
76a66253 3375 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3376 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3377 return; \
3378 } \
76db3ba4 3379 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3380 EA = tcg_temp_new(); \
76db3ba4
AJ		 3381 gen_addr_imm_index(ctx, EA, 0); \
3382 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3383 tcg_temp_free(EA); \
79aceca5
FB		 3384}
3385
a0d7d5a7
AJ		 3386#define GEN_STUF(name, stop, opc, type) \
3387GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3388{ \
a0d7d5a7 3389 TCGv EA; \
76a66253 3390 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3391 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3392 return; \
3393 } \
76a66253 3394 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3395 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3396 return; \
9a64fbe4 3397 } \
76db3ba4 3398 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3399 EA = tcg_temp_new(); \
76db3ba4
AJ		 3400 gen_addr_imm_index(ctx, EA, 0); \
3401 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3402 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3403 tcg_temp_free(EA); \
79aceca5
FB		 3404}
3405
a0d7d5a7
AJ		 3406#define GEN_STUXF(name, stop, opc, type) \
3407GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3408{ \
a0d7d5a7 3409 TCGv EA; \
76a66253 3410 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3411 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3412 return; \
3413 } \
76a66253 3414 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3415 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3416 return; \
9a64fbe4 3417 } \
76db3ba4 3418 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3419 EA = tcg_temp_new(); \
76db3ba4
AJ		 3420 gen_addr_reg_index(ctx, EA); \
3421 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3422 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3423 tcg_temp_free(EA); \
79aceca5
FB		 3424}
3425
a0d7d5a7
AJ		 3426#define GEN_STXF(name, stop, opc2, opc3, type) \
3427GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3428{ \
a0d7d5a7 3429 TCGv EA; \
76a66253 3430 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3431 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3432 return; \
3433 } \
76db3ba4 3434 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3435 EA = tcg_temp_new(); \
76db3ba4
AJ		 3436 gen_addr_reg_index(ctx, EA); \
3437 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3438 tcg_temp_free(EA); \
79aceca5
FB		 3439}
3440
a0d7d5a7
AJ		 3441#define GEN_STFS(name, stop, op, type) \
3442GEN_STF(name, stop, op | 0x20, type); \
3443GEN_STUF(name, stop, op | 0x21, type); \
3444GEN_STUXF(name, stop, op | 0x01, type); \
3445GEN_STXF(name, stop, 0x17, op | 0x00, type)
3446
76db3ba4 3447static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3448{
3449 TCGv_i32 t0 = tcg_temp_new_i32();
3450 TCGv t1 = tcg_temp_new();
3451 gen_helper_float64_to_float32(t0, arg1);
3452 tcg_gen_extu_i32_tl(t1, t0);
3453 tcg_temp_free_i32(t0);
76db3ba4 3454 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3455 tcg_temp_free(t1);
3456}
79aceca5
FB		 3457
3458/* stfd stfdu stfdux stfdx */
a0d7d5a7 3459GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3460/* stfs stfsu stfsux stfsx */
a0d7d5a7 3461GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3462
3463/* Optional: */
76db3ba4 3464static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3465{
3466 TCGv t0 = tcg_temp_new();
3467 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3468 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3469 tcg_temp_free(t0);
3470}
79aceca5 3471/* stfiwx */
a0d7d5a7 3472GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3473
3474/*** Branch ***/
b068d6a7
JM		 3475static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3476 target_ulong dest)
c1942362
FB		 3477{
3478 TranslationBlock *tb;
3479 tb = ctx->tb;
a2ffb812
AJ		 3480#if defined(TARGET_PPC64)
3481 if (!ctx->sf_mode)
3482 dest = (uint32_t) dest;
3483#endif
57fec1fe 3484 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3485 likely(!ctx->singlestep_enabled)) {
57fec1fe 3486 tcg_gen_goto_tb(n);
a2ffb812 3487 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3488 tcg_gen_exit_tb((long)tb + n);
c1942362 3489 } else {
a2ffb812 3490 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3491 if (unlikely(ctx->singlestep_enabled)) {
3492 if ((ctx->singlestep_enabled &
bdc4e053 3493 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3494 ctx->exception == POWERPC_EXCP_BRANCH) {
3495 target_ulong tmp = ctx->nip;
3496 ctx->nip = dest;
e06fcd75 3497 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3498 ctx->nip = tmp;
3499 }
3500 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3501 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3502 }
3503 }
57fec1fe 3504 tcg_gen_exit_tb(0);
c1942362 3505 }
c53be334
FB		 3506}
3507
b068d6a7 3508static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3509{
3510#if defined(TARGET_PPC64)
a2ffb812
AJ		 3511 if (ctx->sf_mode == 0)
3512 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3513 else
3514#endif
a2ffb812 3515 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3516}
3517
79aceca5
FB		 3518/* b ba bl bla */
3519GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3520{
76a66253 3521 target_ulong li, target;
38a64f9d 3522
8cbcb4fa 3523 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3524 /* sign extend LI */
76a66253 3525#if defined(TARGET_PPC64)
d9bce9d9
JM		 3526 if (ctx->sf_mode)
3527 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3528 else
76a66253 3529#endif
d9bce9d9 3530 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3531 if (likely(AA(ctx->opcode) == 0))
046d6672 3532 target = ctx->nip + li - 4;
79aceca5 3533 else
9a64fbe4 3534 target = li;
e1833e1f
JM		 3535 if (LK(ctx->opcode))
3536 gen_setlr(ctx, ctx->nip);
c1942362 3537 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3538}
3539
e98a6e40
FB		 3540#define BCOND_IM 0
3541#define BCOND_LR 1
3542#define BCOND_CTR 2
3543
b068d6a7 3544static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3545{
d9bce9d9 3546 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3547 int l1 = gen_new_label();
3548 TCGv target;
e98a6e40 3549
8cbcb4fa 3550 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3551 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3552 target = tcg_temp_local_new();
a2ffb812
AJ		 3553 if (type == BCOND_CTR)
3554 tcg_gen_mov_tl(target, cpu_ctr);
3555 else
3556 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3557 }
e1833e1f
JM		 3558 if (LK(ctx->opcode))
3559 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3560 l1 = gen_new_label();
3561 if ((bo & 0x4) == 0) {
3562 /* Decrement and test CTR */
a7812ae4 3563 TCGv temp = tcg_temp_new();
a2ffb812 3564 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3565 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3566 return;
3567 }
3568 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3569#if defined(TARGET_PPC64)
a2ffb812
AJ		 3570 if (!ctx->sf_mode)
3571 tcg_gen_ext32u_tl(temp, cpu_ctr);
3572 else
d9bce9d9 3573#endif
a2ffb812
AJ		 3574 tcg_gen_mov_tl(temp, cpu_ctr);
3575 if (bo & 0x2) {
3576 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3577 } else {
3578 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3579 }
a7812ae4 3580 tcg_temp_free(temp);
a2ffb812
AJ		 3581 }
3582 if ((bo & 0x10) == 0) {
3583 /* Test CR */
3584 uint32_t bi = BI(ctx->opcode);
3585 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3586 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3587
d9bce9d9 3588 if (bo & 0x8) {
a2ffb812
AJ		 3589 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3590 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3591 } else {
a2ffb812
AJ		 3592 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3593 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3594 }
a7812ae4 3595 tcg_temp_free_i32(temp);
d9bce9d9 3596 }
e98a6e40 3597 if (type == BCOND_IM) {
a2ffb812
AJ		 3598 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3599 if (likely(AA(ctx->opcode) == 0)) {
3600 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3601 } else {
3602 gen_goto_tb(ctx, 0, li);
3603 }
c53be334 3604 gen_set_label(l1);
c1942362 3605 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3606 } else {
d9bce9d9 3607#if defined(TARGET_PPC64)
a2ffb812
AJ		 3608 if (!(ctx->sf_mode))
3609 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3610 else
3611#endif
3612 tcg_gen_andi_tl(cpu_nip, target, ~3);
3613 tcg_gen_exit_tb(0);
3614 gen_set_label(l1);
3615#if defined(TARGET_PPC64)
3616 if (!(ctx->sf_mode))
3617 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3618 else
3619#endif
a2ffb812 3620 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3621 tcg_gen_exit_tb(0);
08e46e54 3622 }
e98a6e40
FB		 3623}
3624
3625GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3626{
e98a6e40
FB		 3627 gen_bcond(ctx, BCOND_IM);
3628}
3629
3630GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3631{
e98a6e40
FB		 3632 gen_bcond(ctx, BCOND_CTR);
3633}
3634
3635GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3636{
e98a6e40
FB		 3637 gen_bcond(ctx, BCOND_LR);
3638}
79aceca5
FB		 3639
3640/*** Condition register logical ***/
e1571908
AJ		 3641#define GEN_CRLOGIC(name, tcg_op, opc) \
3642GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3643{ \
fc0d441e
JM		 3644 uint8_t bitmask; \
3645 int sh; \
a7812ae4 3646 TCGv_i32 t0, t1; \
fc0d441e 3647 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3648 t0 = tcg_temp_new_i32(); \
fc0d441e 3649 if (sh > 0) \
fea0c503 3650 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3651 else if (sh < 0) \
fea0c503 3652 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3653 else \
fea0c503 3654 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3655 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3656 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3657 if (sh > 0) \
fea0c503 3658 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3659 else if (sh < 0) \
fea0c503 3660 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3661 else \
fea0c503
AJ		 3662 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3663 tcg_op(t0, t0, t1); \
fc0d441e 3664 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3665 tcg_gen_andi_i32(t0, t0, bitmask); \
3666 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3667 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3668 tcg_temp_free_i32(t0); \
3669 tcg_temp_free_i32(t1); \
79aceca5
FB		 3670}
3671
3672/* crand */
e1571908 3673GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3674/* crandc */
e1571908 3675GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3676/* creqv */
e1571908 3677GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3678/* crnand */
e1571908 3679GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3680/* crnor */
e1571908 3681GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3682/* cror */
e1571908 3683GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3684/* crorc */
e1571908 3685GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3686/* crxor */
e1571908 3687GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3688/* mcrf */
3689GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3690{
47e4661c 3691 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3692}
3693
3694/*** System linkage ***/
76db3ba4 3695/* rfi (mem_idx only) */
76a66253 3696GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3697{
9a64fbe4 3698#if defined(CONFIG_USER_ONLY)
e06fcd75 3699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 3700#else
3701 /* Restore CPU state */
76db3ba4 3702 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 3704 return;
9a64fbe4 3705 }
d72a19f7 3706 gen_helper_rfi();
e06fcd75 3707 gen_sync_exception(ctx);
9a64fbe4 3708#endif
79aceca5
FB		 3709}
3710
426613db 3711#if defined(TARGET_PPC64)
a750fc0b 3712GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3713{
3714#if defined(CONFIG_USER_ONLY)
e06fcd75 3715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3716#else
3717 /* Restore CPU state */
76db3ba4 3718 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3720 return;
3721 }
d72a19f7 3722 gen_helper_rfid();
e06fcd75 3723 gen_sync_exception(ctx);
426613db
JM		 3724#endif
3725}
426613db 3726
5b8105fa 3727GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3728{
3729#if defined(CONFIG_USER_ONLY)
e06fcd75 3730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3731#else
3732 /* Restore CPU state */
76db3ba4 3733 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 3734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3735 return;
3736 }
d72a19f7 3737 gen_helper_hrfid();
e06fcd75 3738 gen_sync_exception(ctx);
be147d08
JM		 3739#endif
3740}
3741#endif
3742
79aceca5 3743/* sc */
417bf010
JM		 3744#if defined(CONFIG_USER_ONLY)
3745#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3746#else
3747#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3748#endif
e1833e1f 3749GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3750{
e1833e1f
JM		 3751 uint32_t lev;
3752
3753 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3754 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3755}
3756
3757/*** Trap ***/
3758/* tw */
76a66253 3759GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3760{
cab3bee2 3761 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3762 /* Update the nip since this might generate a trap exception */
d9bce9d9 3763 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3764 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3765 tcg_temp_free_i32(t0);
79aceca5
FB		 3766}
3767
3768/* twi */
3769GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3770{
cab3bee2
AJ		 3771 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3772 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3773 /* Update the nip since this might generate a trap exception */
3774 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3775 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3776 tcg_temp_free(t0);
3777 tcg_temp_free_i32(t1);
79aceca5
FB		 3778}
3779
d9bce9d9
JM		 3780#if defined(TARGET_PPC64)
3781/* td */
3782GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3783{
cab3bee2 3784 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3785 /* Update the nip since this might generate a trap exception */
3786 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3787 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3788 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3789}
3790
3791/* tdi */
3792GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3793{
cab3bee2
AJ		 3794 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3795 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3796 /* Update the nip since this might generate a trap exception */
3797 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3798 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3799 tcg_temp_free(t0);
3800 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3801}
3802#endif
3803
79aceca5 3804/*** Processor control ***/
79aceca5
FB		 3805/* mcrxr */
3806GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3807{
3d7b417e
AJ		 3808 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3809 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3810 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3811}
3812
3813/* mfcr */
76a66253 3814GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3815{
76a66253 3816 uint32_t crm, crn;
3b46e624 3817
76a66253
JM		 3818 if (likely(ctx->opcode & 0x00100000)) {
3819 crm = CRM(ctx->opcode);
3820 if (likely((crm ^ (crm - 1)) == 0)) {
3821 crn = ffs(crm);
e1571908 3822 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3823 }
d9bce9d9 3824 } else {
a7812ae4 3825 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3826 }
79aceca5
FB		 3827}
3828
3829/* mfmsr */
3830GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3831{
9a64fbe4 3832#if defined(CONFIG_USER_ONLY)
e06fcd75 3833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3834#else
76db3ba4 3835 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3837 return;
9a64fbe4 3838 }
6527f6ea 3839 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3840#endif
79aceca5
FB		 3841}
3842
a11b8151 3843#if 1
6f2d8978 3844#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3845#else
3846static void spr_noaccess (void *opaque, int sprn)
3847{
3848 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3849 printf("ERROR: try to access SPR %d !\n", sprn);
3850}
3851#define SPR_NOACCESS (&spr_noaccess)
3852#endif
3853
79aceca5 3854/* mfspr */
b068d6a7 3855static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3856{
45d827d2 3857 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3858 uint32_t sprn = SPR(ctx->opcode);
3859
3fc6c082 3860#if !defined(CONFIG_USER_ONLY)
76db3ba4 3861 if (ctx->mem_idx == 2)
be147d08 3862 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 3863 else if (ctx->mem_idx)
3fc6c082
FB		 3864 read_cb = ctx->spr_cb[sprn].oea_read;
3865 else
9a64fbe4 3866#endif
3fc6c082 3867 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3868 if (likely(read_cb != NULL)) {
3869 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3870 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3871 } else {
3872 /* Privilege exception */
9fceefa7
JM		 3873 /* This is a hack to avoid warnings when running Linux:
3874 * this OS breaks the PowerPC virtualisation model,
3875 * allowing userland application to read the PVR
3876 */
3877 if (sprn != SPR_PVR) {
3878 if (loglevel != 0) {
6b542af7 3879 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3880 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3881 }
077fc206
JM		 3882 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3883 sprn, sprn, ctx->nip);
f24e5695 3884 }
e06fcd75 3885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3886 }
3fc6c082
FB		 3887 } else {
3888 /* Not defined */
4a057712 3889 if (loglevel != 0) {
077fc206
JM		 3890 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3891 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3892 }
077fc206
JM		 3893 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3894 sprn, sprn, ctx->nip);
e06fcd75 3895 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3896 }
79aceca5
FB		 3897}
3898
3fc6c082 3899GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3900{
3fc6c082 3901 gen_op_mfspr(ctx);
76a66253 3902}
3fc6c082
FB		 3903
3904/* mftb */
a750fc0b 3905GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3906{
3907 gen_op_mfspr(ctx);
79aceca5
FB		 3908}
3909
3910/* mtcrf */
8dd4983c 3911GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3912{
76a66253 3913 uint32_t crm, crn;
3b46e624 3914
76a66253
JM		 3915 crm = CRM(ctx->opcode);
3916 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3917 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3918 crn = ffs(crm);
a7812ae4
PB		 3919 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3920 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3921 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3922 tcg_temp_free_i32(temp);
76a66253 3923 } else {
a7812ae4
PB		 3924 TCGv_i32 temp = tcg_const_i32(crm);
3925 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3926 tcg_temp_free_i32(temp);
76a66253 3927 }
79aceca5
FB		 3928}
3929
3930/* mtmsr */
426613db 3931#if defined(TARGET_PPC64)
be147d08 3932GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3933{
3934#if defined(CONFIG_USER_ONLY)
e06fcd75 3935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 3936#else
76db3ba4 3937 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 3939 return;
3940 }
be147d08
JM		 3941 if (ctx->opcode & 0x00010000) {
3942 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3943 TCGv t0 = tcg_temp_new();
3944 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3945 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3946 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3947 tcg_temp_free(t0);
be147d08 3948 } else {
056b05f8
JM		 3949 /* XXX: we need to update nip before the store
3950 * if we enter power saving mode, we will exit the loop
3951 * directly from ppc_store_msr
3952 */
be147d08 3953 gen_update_nip(ctx, ctx->nip);
6527f6ea 3954 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3955 /* Must stop the translation as machine state (may have) changed */
3956 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3957 gen_stop_exception(ctx);
be147d08 3958 }
426613db
JM		 3959#endif
3960}
3961#endif
3962
79aceca5
FB		 3963GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3964{
9a64fbe4 3965#if defined(CONFIG_USER_ONLY)
e06fcd75 3966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3967#else
76db3ba4 3968 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3970 return;
9a64fbe4 3971 }
be147d08
JM		 3972 if (ctx->opcode & 0x00010000) {
3973 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3974 TCGv t0 = tcg_temp_new();
3975 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3976 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3977 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3978 tcg_temp_free(t0);
be147d08 3979 } else {
056b05f8
JM		 3980 /* XXX: we need to update nip before the store
3981 * if we enter power saving mode, we will exit the loop
3982 * directly from ppc_store_msr
3983 */
be147d08 3984 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3985#if defined(TARGET_PPC64)
6527f6ea
AJ		 3986 if (!ctx->sf_mode) {
3987 TCGv t0 = tcg_temp_new();
3988 TCGv t1 = tcg_temp_new();
3989 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3990 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3991 tcg_gen_or_tl(t0, t0, t1);
3992 tcg_temp_free(t1);
3993 gen_helper_store_msr(t0);
3994 tcg_temp_free(t0);
3995 } else
d9bce9d9 3996#endif
6527f6ea 3997 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 3998 /* Must stop the translation as machine state (may have) changed */
6527f6ea 3999 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4000 gen_stop_exception(ctx);
be147d08 4001 }
9a64fbe4 4002#endif
79aceca5
FB		 4003}
4004
4005/* mtspr */
4006GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4007{
45d827d2 4008 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4009 uint32_t sprn = SPR(ctx->opcode);
4010
3fc6c082 4011#if !defined(CONFIG_USER_ONLY)
76db3ba4 4012 if (ctx->mem_idx == 2)
be147d08 4013 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 4014 else if (ctx->mem_idx)
3fc6c082
FB		 4015 write_cb = ctx->spr_cb[sprn].oea_write;
4016 else
9a64fbe4 4017#endif
3fc6c082 4018 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4019 if (likely(write_cb != NULL)) {
4020 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4021 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4022 } else {
4023 /* Privilege exception */
4a057712 4024 if (loglevel != 0) {
077fc206
JM		 4025 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4026 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4027 }
077fc206
JM		 4028 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4029 sprn, sprn, ctx->nip);
e06fcd75 4030 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4031 }
3fc6c082
FB		 4032 } else {
4033 /* Not defined */
4a057712 4034 if (loglevel != 0) {
077fc206
JM		 4035 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4036 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4037 }
077fc206
JM		 4038 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4039 sprn, sprn, ctx->nip);
e06fcd75 4040 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4041 }
79aceca5
FB		 4042}
4043
4044/*** Cache management ***/
79aceca5 4045/* dcbf */
0db1b20e 4046GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4047{
dac454af 4048 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4049 TCGv t0;
4050 gen_set_access_type(ctx, ACCESS_CACHE);
4051 t0 = tcg_temp_new();
4052 gen_addr_reg_index(ctx, t0);
4053 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4054 tcg_temp_free(t0);
79aceca5
FB		 4055}
4056
4057/* dcbi (Supervisor only) */
9a64fbe4 4058GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4059{
a541f297 4060#if defined(CONFIG_USER_ONLY)
e06fcd75 4061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4062#else
b61f2753 4063 TCGv EA, val;
76db3ba4 4064 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4066 return;
9a64fbe4 4067 }
a7812ae4 4068 EA = tcg_temp_new();
76db3ba4
AJ		 4069 gen_set_access_type(ctx, ACCESS_CACHE);
4070 gen_addr_reg_index(ctx, EA);
a7812ae4 4071 val = tcg_temp_new();
76a66253 4072 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4073 gen_qemu_ld8u(ctx, val, EA);
4074 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4075 tcg_temp_free(val);
4076 tcg_temp_free(EA);
a541f297 4077#endif
79aceca5
FB		 4078}
4079
4080/* dcdst */
9a64fbe4 4081GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4082{
76a66253 4083 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4084 TCGv t0;
4085 gen_set_access_type(ctx, ACCESS_CACHE);
4086 t0 = tcg_temp_new();
4087 gen_addr_reg_index(ctx, t0);
4088 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4089 tcg_temp_free(t0);
79aceca5
FB		 4090}
4091
4092/* dcbt */
0db1b20e 4093GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4094{
0db1b20e 4095 /* interpreted as no-op */
76a66253
JM		 4096 /* XXX: specification say this is treated as a load by the MMU
4097 * but does not generate any exception
4098 */
79aceca5
FB		 4099}
4100
4101/* dcbtst */
0db1b20e 4102GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4103{
0db1b20e 4104 /* interpreted as no-op */
76a66253
JM		 4105 /* XXX: specification say this is treated as a load by the MMU
4106 * but does not generate any exception
4107 */
79aceca5
FB		 4108}
4109
4110/* dcbz */
d63001d1 4111GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4112{
76db3ba4
AJ		 4113 TCGv t0;
4114 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4115 /* NIP cannot be restored if the memory exception comes from an helper */
4116 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4117 t0 = tcg_temp_new();
4118 gen_addr_reg_index(ctx, t0);
799a8c8d
AJ		 4119 gen_helper_dcbz(t0);
4120 tcg_temp_free(t0);
d63001d1
JM		 4121}
4122
c7697e1f 4123GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4124{
76db3ba4
AJ		 4125 TCGv t0;
4126 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4127 /* NIP cannot be restored if the memory exception comes from an helper */
4128 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4129 t0 = tcg_temp_new();
4130 gen_addr_reg_index(ctx, t0);
d63001d1 4131 if (ctx->opcode & 0x00200000)
799a8c8d 4132 gen_helper_dcbz(t0);
d63001d1 4133 else
799a8c8d
AJ		 4134 gen_helper_dcbz_970(t0);
4135 tcg_temp_free(t0);
79aceca5
FB		 4136}
4137
4138/* icbi */
1b413d55 4139GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4140{
76db3ba4
AJ		 4141 TCGv t0;
4142 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4143 /* NIP cannot be restored if the memory exception comes from an helper */
4144 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4145 t0 = tcg_temp_new();
4146 gen_addr_reg_index(ctx, t0);
37d269df
AJ		 4147 gen_helper_icbi(t0);
4148 tcg_temp_free(t0);
79aceca5
FB		 4149}
4150
4151/* Optional: */
4152/* dcba */
a750fc0b 4153GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4154{
0db1b20e
JM		 4155 /* interpreted as no-op */
4156 /* XXX: specification say this is treated as a store by the MMU
4157 * but does not generate any exception
4158 */
79aceca5
FB		 4159}
4160
4161/*** Segment register manipulation ***/
4162/* Supervisor only: */
4163/* mfsr */
4164GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4165{
9a64fbe4 4166#if defined(CONFIG_USER_ONLY)
e06fcd75 4167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4168#else
74d37793 4169 TCGv t0;
76db3ba4 4170 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4172 return;
9a64fbe4 4173 }
74d37793
AJ		 4174 t0 = tcg_const_tl(SR(ctx->opcode));
4175 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4176 tcg_temp_free(t0);
9a64fbe4 4177#endif
79aceca5
FB		 4178}
4179
4180/* mfsrin */
9a64fbe4 4181GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4182{
9a64fbe4 4183#if defined(CONFIG_USER_ONLY)
e06fcd75 4184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4185#else
74d37793 4186 TCGv t0;
76db3ba4 4187 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4189 return;
9a64fbe4 4190 }
74d37793
AJ		 4191 t0 = tcg_temp_new();
4192 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4193 tcg_gen_andi_tl(t0, t0, 0xF);
4194 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4195 tcg_temp_free(t0);
9a64fbe4 4196#endif
79aceca5
FB		 4197}
4198
4199/* mtsr */
e63c59cb 4200GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4201{
9a64fbe4 4202#if defined(CONFIG_USER_ONLY)
e06fcd75 4203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4204#else
74d37793 4205 TCGv t0;
76db3ba4 4206 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4208 return;
9a64fbe4 4209 }
74d37793
AJ		 4210 t0 = tcg_const_tl(SR(ctx->opcode));
4211 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4212 tcg_temp_free(t0);
9a64fbe4 4213#endif
79aceca5
FB		 4214}
4215
4216/* mtsrin */
9a64fbe4 4217GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4218{
9a64fbe4 4219#if defined(CONFIG_USER_ONLY)
e06fcd75 4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4221#else
74d37793 4222 TCGv t0;
76db3ba4 4223 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4225 return;
9a64fbe4 4226 }
74d37793
AJ		 4227 t0 = tcg_temp_new();
4228 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4229 tcg_gen_andi_tl(t0, t0, 0xF);
4230 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4231 tcg_temp_free(t0);
9a64fbe4 4232#endif
79aceca5
FB		 4233}
4234
12de9a39
JM		 4235#if defined(TARGET_PPC64)
4236/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4237/* mfsr */
c7697e1f 4238GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4239{
4240#if defined(CONFIG_USER_ONLY)
e06fcd75 4241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4242#else
74d37793 4243 TCGv t0;
76db3ba4 4244 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4246 return;
4247 }
74d37793
AJ		 4248 t0 = tcg_const_tl(SR(ctx->opcode));
4249 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4250 tcg_temp_free(t0);
12de9a39
JM		 4251#endif
4252}
4253
4254/* mfsrin */
c7697e1f
JM		 4255GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4256 PPC_SEGMENT_64B)
12de9a39
JM		 4257{
4258#if defined(CONFIG_USER_ONLY)
e06fcd75 4259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4260#else
74d37793 4261 TCGv t0;
76db3ba4 4262 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4264 return;
4265 }
74d37793
AJ		 4266 t0 = tcg_temp_new();
4267 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4268 tcg_gen_andi_tl(t0, t0, 0xF);
4269 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4270 tcg_temp_free(t0);
12de9a39
JM		 4271#endif
4272}
4273
4274/* mtsr */
c7697e1f 4275GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4276{
4277#if defined(CONFIG_USER_ONLY)
e06fcd75 4278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4279#else
74d37793 4280 TCGv t0;
76db3ba4 4281 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4283 return;
4284 }
74d37793
AJ		 4285 t0 = tcg_const_tl(SR(ctx->opcode));
4286 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4287 tcg_temp_free(t0);
12de9a39
JM		 4288#endif
4289}
4290
4291/* mtsrin */
c7697e1f
JM		 4292GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4293 PPC_SEGMENT_64B)
12de9a39
JM		 4294{
4295#if defined(CONFIG_USER_ONLY)
e06fcd75 4296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4297#else
74d37793 4298 TCGv t0;
76db3ba4 4299 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4300 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4301 return;
4302 }
74d37793
AJ		 4303 t0 = tcg_temp_new();
4304 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4305 tcg_gen_andi_tl(t0, t0, 0xF);
4306 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4307 tcg_temp_free(t0);
12de9a39
JM		 4308#endif
4309}
4310#endif /* defined(TARGET_PPC64) */
4311
79aceca5 4312/*** Lookaside buffer management ***/
76db3ba4 4313/* Optional & mem_idx only: */
79aceca5 4314/* tlbia */
3fc6c082 4315GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4316{
9a64fbe4 4317#if defined(CONFIG_USER_ONLY)
e06fcd75 4318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4319#else
76db3ba4 4320 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4322 return;
9a64fbe4 4323 }
74d37793 4324 gen_helper_tlbia();
9a64fbe4 4325#endif
79aceca5
FB		 4326}
4327
4328/* tlbie */
76a66253 4329GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4330{
9a64fbe4 4331#if defined(CONFIG_USER_ONLY)
e06fcd75 4332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4333#else
76db3ba4 4334 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4336 return;
9a64fbe4 4337 }
d9bce9d9 4338#if defined(TARGET_PPC64)
74d37793
AJ		 4339 if (!ctx->sf_mode) {
4340 TCGv t0 = tcg_temp_new();
4341 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4342 gen_helper_tlbie(t0);
4343 tcg_temp_free(t0);
4344 } else
d9bce9d9 4345#endif
74d37793 4346 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4347#endif
79aceca5
FB		 4348}
4349
4350/* tlbsync */
76a66253 4351GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4352{
9a64fbe4 4353#if defined(CONFIG_USER_ONLY)
e06fcd75 4354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4355#else
76db3ba4 4356 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4357 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4358 return;
9a64fbe4
FB		 4359 }
4360 /* This has no effect: it should ensure that all previous
4361 * tlbie have completed
4362 */
e06fcd75 4363 gen_stop_exception(ctx);
9a64fbe4 4364#endif
79aceca5
FB		 4365}
4366
426613db
JM		 4367#if defined(TARGET_PPC64)
4368/* slbia */
4369GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4370{
4371#if defined(CONFIG_USER_ONLY)
e06fcd75 4372 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4373#else
76db3ba4 4374 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4376 return;
4377 }
74d37793 4378 gen_helper_slbia();
426613db
JM		 4379#endif
4380}
4381
4382/* slbie */
4383GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4384{
4385#if defined(CONFIG_USER_ONLY)
e06fcd75 4386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4387#else
76db3ba4 4388 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4390 return;
4391 }
74d37793 4392 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4393#endif
4394}
4395#endif
4396
79aceca5
FB		 4397/*** External control ***/
4398/* Optional: */
111bfab3 4399/* eciwx */
79aceca5
FB		 4400GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4401{
76db3ba4 4402 TCGv t0;
fa407c03 4403 /* Should check EAR[E] ! */
76db3ba4
AJ		 4404 gen_set_access_type(ctx, ACCESS_EXT);
4405 t0 = tcg_temp_new();
4406 gen_addr_reg_index(ctx, t0);
fa407c03 4407 gen_check_align(ctx, t0, 0x03);
76db3ba4 4408 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4409 tcg_temp_free(t0);
76a66253
JM		 4410}
4411
4412/* ecowx */
4413GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4414{
76db3ba4 4415 TCGv t0;
fa407c03 4416 /* Should check EAR[E] ! */
76db3ba4
AJ		 4417 gen_set_access_type(ctx, ACCESS_EXT);
4418 t0 = tcg_temp_new();
4419 gen_addr_reg_index(ctx, t0);
fa407c03 4420 gen_check_align(ctx, t0, 0x03);
76db3ba4 4421 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4422 tcg_temp_free(t0);
76a66253
JM		 4423}
4424
4425/* PowerPC 601 specific instructions */
4426/* abs - abs. */
4427GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4428{
22e0e173
AJ		 4429 int l1 = gen_new_label();
4430 int l2 = gen_new_label();
4431 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4432 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4433 tcg_gen_br(l2);
4434 gen_set_label(l1);
4435 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4436 gen_set_label(l2);
76a66253 4437 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4438 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4439}
4440
4441/* abso - abso. */
4442GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4443{
22e0e173
AJ		 4444 int l1 = gen_new_label();
4445 int l2 = gen_new_label();
4446 int l3 = gen_new_label();
4447 /* Start with XER OV disabled, the most likely case */
4448 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4449 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4450 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4451 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4452 tcg_gen_br(l2);
4453 gen_set_label(l1);
4454 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4455 tcg_gen_br(l3);
4456 gen_set_label(l2);
4457 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4458 gen_set_label(l3);
76a66253 4459 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4460 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4461}
4462
4463/* clcs */
a750fc0b 4464GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4465{
22e0e173
AJ		 4466 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4467 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4468 tcg_temp_free_i32(t0);
c7697e1f 4469 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4470}
4471
4472/* div - div. */
4473GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4474{
22e0e173 4475 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4476 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4477 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4478}
4479
4480/* divo - divo. */
4481GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4482{
22e0e173 4483 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4484 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4485 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4486}
4487
4488/* divs - divs. */
4489GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4490{
22e0e173 4491 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4492 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4493 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4494}
4495
4496/* divso - divso. */
4497GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4498{
22e0e173 4499 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4500 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4501 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4502}
4503
4504/* doz - doz. */
4505GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4506{
22e0e173
AJ		 4507 int l1 = gen_new_label();
4508 int l2 = gen_new_label();
4509 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4510 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4511 tcg_gen_br(l2);
4512 gen_set_label(l1);
4513 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4514 gen_set_label(l2);
76a66253 4515 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4516 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4517}
4518
4519/* dozo - dozo. */
4520GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4521{
22e0e173
AJ		 4522 int l1 = gen_new_label();
4523 int l2 = gen_new_label();
4524 TCGv t0 = tcg_temp_new();
4525 TCGv t1 = tcg_temp_new();
4526 TCGv t2 = tcg_temp_new();
4527 /* Start with XER OV disabled, the most likely case */
4528 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4529 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4530 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4531 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4532 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4533 tcg_gen_andc_tl(t1, t1, t2);
4534 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4535 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4536 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4537 tcg_gen_br(l2);
4538 gen_set_label(l1);
4539 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4540 gen_set_label(l2);
4541 tcg_temp_free(t0);
4542 tcg_temp_free(t1);
4543 tcg_temp_free(t2);
76a66253 4544 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4545 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4546}
4547
4548/* dozi */
4549GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4550{
22e0e173
AJ		 4551 target_long simm = SIMM(ctx->opcode);
4552 int l1 = gen_new_label();
4553 int l2 = gen_new_label();
4554 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4555 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4556 tcg_gen_br(l2);
4557 gen_set_label(l1);
4558 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4559 gen_set_label(l2);
4560 if (unlikely(Rc(ctx->opcode) != 0))
4561 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4562}
4563
76a66253
JM		 4564/* lscbx - lscbx. */
4565GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4566{
bdb4b689
AJ		 4567 TCGv t0 = tcg_temp_new();
4568 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4569 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4570 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4571
76db3ba4 4572 gen_addr_reg_index(ctx, t0);
76a66253 4573 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4574 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4575 gen_helper_lscbx(t0, t0, t1, t2, t3);
4576 tcg_temp_free_i32(t1);
4577 tcg_temp_free_i32(t2);
4578 tcg_temp_free_i32(t3);
3d7b417e 4579 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4580 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4581 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4582 gen_set_Rc0(ctx, t0);
4583 tcg_temp_free(t0);
76a66253
JM		 4584}
4585
4586/* maskg - maskg. */
4587GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4588{
22e0e173
AJ		 4589 int l1 = gen_new_label();
4590 TCGv t0 = tcg_temp_new();
4591 TCGv t1 = tcg_temp_new();
4592 TCGv t2 = tcg_temp_new();
4593 TCGv t3 = tcg_temp_new();
4594 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4595 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4596 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4597 tcg_gen_addi_tl(t2, t0, 1);
4598 tcg_gen_shr_tl(t2, t3, t2);
4599 tcg_gen_shr_tl(t3, t3, t1);
4600 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4601 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4602 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4603 gen_set_label(l1);
4604 tcg_temp_free(t0);
4605 tcg_temp_free(t1);
4606 tcg_temp_free(t2);
4607 tcg_temp_free(t3);
76a66253 4608 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4609 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4610}
4611
4612/* maskir - maskir. */
4613GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4614{
22e0e173
AJ		 4615 TCGv t0 = tcg_temp_new();
4616 TCGv t1 = tcg_temp_new();
4617 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4618 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4619 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4620 tcg_temp_free(t0);
4621 tcg_temp_free(t1);
76a66253 4622 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4623 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4624}
4625
4626/* mul - mul. */
4627GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4628{
22e0e173
AJ		 4629 TCGv_i64 t0 = tcg_temp_new_i64();
4630 TCGv_i64 t1 = tcg_temp_new_i64();
4631 TCGv t2 = tcg_temp_new();
4632 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4633 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4634 tcg_gen_mul_i64(t0, t0, t1);
4635 tcg_gen_trunc_i64_tl(t2, t0);
4636 gen_store_spr(SPR_MQ, t2);
4637 tcg_gen_shri_i64(t1, t0, 32);
4638 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4639 tcg_temp_free_i64(t0);
4640 tcg_temp_free_i64(t1);
4641 tcg_temp_free(t2);
76a66253 4642 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4643 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4644}
4645
4646/* mulo - mulo. */
4647GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4648{
22e0e173
AJ		 4649 int l1 = gen_new_label();
4650 TCGv_i64 t0 = tcg_temp_new_i64();
4651 TCGv_i64 t1 = tcg_temp_new_i64();
4652 TCGv t2 = tcg_temp_new();
4653 /* Start with XER OV disabled, the most likely case */
4654 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4655 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4656 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4657 tcg_gen_mul_i64(t0, t0, t1);
4658 tcg_gen_trunc_i64_tl(t2, t0);
4659 gen_store_spr(SPR_MQ, t2);
4660 tcg_gen_shri_i64(t1, t0, 32);
4661 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4662 tcg_gen_ext32s_i64(t1, t0);
4663 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4664 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4665 gen_set_label(l1);
4666 tcg_temp_free_i64(t0);
4667 tcg_temp_free_i64(t1);
4668 tcg_temp_free(t2);
76a66253 4669 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4670 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4671}
4672
4673/* nabs - nabs. */
4674GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4675{
22e0e173
AJ		 4676 int l1 = gen_new_label();
4677 int l2 = gen_new_label();
4678 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4679 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4680 tcg_gen_br(l2);
4681 gen_set_label(l1);
4682 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4683 gen_set_label(l2);
76a66253 4684 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4685 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4686}
4687
4688/* nabso - nabso. */
4689GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4690{
22e0e173
AJ		 4691 int l1 = gen_new_label();
4692 int l2 = gen_new_label();
4693 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4694 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4695 tcg_gen_br(l2);
4696 gen_set_label(l1);
4697 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4698 gen_set_label(l2);
4699 /* nabs never overflows */
4700 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4701 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4702 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4703}
4704
4705/* rlmi - rlmi. */
4706GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4707{
7487953d
AJ		 4708 uint32_t mb = MB(ctx->opcode);
4709 uint32_t me = ME(ctx->opcode);
4710 TCGv t0 = tcg_temp_new();
4711 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4712 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4713 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4714 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4715 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4716 tcg_temp_free(t0);
76a66253 4717 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4718 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4719}
4720
4721/* rrib - rrib. */
4722GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4723{
7487953d
AJ		 4724 TCGv t0 = tcg_temp_new();
4725 TCGv t1 = tcg_temp_new();
4726 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4727 tcg_gen_movi_tl(t1, 0x80000000);
4728 tcg_gen_shr_tl(t1, t1, t0);
4729 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4730 tcg_gen_and_tl(t0, t0, t1);
4731 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4732 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4733 tcg_temp_free(t0);
4734 tcg_temp_free(t1);
76a66253 4735 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4736 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4737}
4738
4739/* sle - sle. */
4740GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4741{
7487953d
AJ		 4742 TCGv t0 = tcg_temp_new();
4743 TCGv t1 = tcg_temp_new();
4744 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4745 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4746 tcg_gen_subfi_tl(t1, 32, t1);
4747 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4748 tcg_gen_or_tl(t1, t0, t1);
4749 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4750 gen_store_spr(SPR_MQ, t1);
4751 tcg_temp_free(t0);
4752 tcg_temp_free(t1);
76a66253 4753 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4754 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4755}
4756
4757/* sleq - sleq. */
4758GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4759{
7487953d
AJ		 4760 TCGv t0 = tcg_temp_new();
4761 TCGv t1 = tcg_temp_new();
4762 TCGv t2 = tcg_temp_new();
4763 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4764 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4765 tcg_gen_shl_tl(t2, t2, t0);
4766 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4767 gen_load_spr(t1, SPR_MQ);
4768 gen_store_spr(SPR_MQ, t0);
4769 tcg_gen_and_tl(t0, t0, t2);
4770 tcg_gen_andc_tl(t1, t1, t2);
4771 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4772 tcg_temp_free(t0);
4773 tcg_temp_free(t1);
4774 tcg_temp_free(t2);
76a66253 4775 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4776 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4777}
4778
4779/* sliq - sliq. */
4780GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4781{
7487953d
AJ		 4782 int sh = SH(ctx->opcode);
4783 TCGv t0 = tcg_temp_new();
4784 TCGv t1 = tcg_temp_new();
4785 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4786 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4787 tcg_gen_or_tl(t1, t0, t1);
4788 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4789 gen_store_spr(SPR_MQ, t1);
4790 tcg_temp_free(t0);
4791 tcg_temp_free(t1);
76a66253 4792 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4793 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4794}
4795
4796/* slliq - slliq. */
4797GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4798{
7487953d
AJ		 4799 int sh = SH(ctx->opcode);
4800 TCGv t0 = tcg_temp_new();
4801 TCGv t1 = tcg_temp_new();
4802 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4803 gen_load_spr(t1, SPR_MQ);
4804 gen_store_spr(SPR_MQ, t0);
4805 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4806 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4807 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4808 tcg_temp_free(t0);
4809 tcg_temp_free(t1);
76a66253 4810 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4811 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4812}
4813
4814/* sllq - sllq. */
4815GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4816{
7487953d
AJ		 4817 int l1 = gen_new_label();
4818 int l2 = gen_new_label();
4819 TCGv t0 = tcg_temp_local_new();
4820 TCGv t1 = tcg_temp_local_new();
4821 TCGv t2 = tcg_temp_local_new();
4822 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4823 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4824 tcg_gen_shl_tl(t1, t1, t2);
4825 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4826 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4827 gen_load_spr(t0, SPR_MQ);
4828 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4829 tcg_gen_br(l2);
4830 gen_set_label(l1);
4831 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4832 gen_load_spr(t2, SPR_MQ);
4833 tcg_gen_andc_tl(t1, t2, t1);
4834 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4835 gen_set_label(l2);
4836 tcg_temp_free(t0);
4837 tcg_temp_free(t1);
4838 tcg_temp_free(t2);
76a66253 4839 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4840 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4841}
4842
4843/* slq - slq. */
4844GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4845{
7487953d
AJ		 4846 int l1 = gen_new_label();
4847 TCGv t0 = tcg_temp_new();
4848 TCGv t1 = tcg_temp_new();
4849 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4850 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4851 tcg_gen_subfi_tl(t1, 32, t1);
4852 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4853 tcg_gen_or_tl(t1, t0, t1);
4854 gen_store_spr(SPR_MQ, t1);
4855 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4856 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4857 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4858 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4859 gen_set_label(l1);
4860 tcg_temp_free(t0);
4861 tcg_temp_free(t1);
76a66253 4862 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4863 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4864}
4865
d9bce9d9 4866/* sraiq - sraiq. */
76a66253
JM		 4867GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4868{
7487953d
AJ		 4869 int sh = SH(ctx->opcode);
4870 int l1 = gen_new_label();
4871 TCGv t0 = tcg_temp_new();
4872 TCGv t1 = tcg_temp_new();
4873 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4874 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4875 tcg_gen_or_tl(t0, t0, t1);
4876 gen_store_spr(SPR_MQ, t0);
4877 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4878 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4879 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4880 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4881 gen_set_label(l1);
4882 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4883 tcg_temp_free(t0);
4884 tcg_temp_free(t1);
76a66253 4885 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4887}
4888
4889/* sraq - sraq. */
4890GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4891{
7487953d
AJ		 4892 int l1 = gen_new_label();
4893 int l2 = gen_new_label();
4894 TCGv t0 = tcg_temp_new();
4895 TCGv t1 = tcg_temp_local_new();
4896 TCGv t2 = tcg_temp_local_new();
4897 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4898 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4899 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4900 tcg_gen_subfi_tl(t2, 32, t2);
4901 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4902 tcg_gen_or_tl(t0, t0, t2);
4903 gen_store_spr(SPR_MQ, t0);
4904 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4905 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4906 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4907 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4908 gen_set_label(l1);
4909 tcg_temp_free(t0);
4910 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4911 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4912 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4913 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4914 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4915 gen_set_label(l2);
4916 tcg_temp_free(t1);
4917 tcg_temp_free(t2);
76a66253 4918 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4919 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4920}
4921
4922/* sre - sre. */
4923GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4924{
7487953d
AJ		 4925 TCGv t0 = tcg_temp_new();
4926 TCGv t1 = tcg_temp_new();
4927 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4928 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4929 tcg_gen_subfi_tl(t1, 32, t1);
4930 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4931 tcg_gen_or_tl(t1, t0, t1);
4932 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4933 gen_store_spr(SPR_MQ, t1);
4934 tcg_temp_free(t0);
4935 tcg_temp_free(t1);
76a66253 4936 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4937 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4938}
4939
4940/* srea - srea. */
4941GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4942{
7487953d
AJ		 4943 TCGv t0 = tcg_temp_new();
4944 TCGv t1 = tcg_temp_new();
4945 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4946 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4947 gen_store_spr(SPR_MQ, t0);
4948 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4949 tcg_temp_free(t0);
4950 tcg_temp_free(t1);
76a66253 4951 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4952 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4953}
4954
4955/* sreq */
4956GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4957{
7487953d
AJ		 4958 TCGv t0 = tcg_temp_new();
4959 TCGv t1 = tcg_temp_new();
4960 TCGv t2 = tcg_temp_new();
4961 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4962 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4963 tcg_gen_shr_tl(t1, t1, t0);
4964 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4965 gen_load_spr(t2, SPR_MQ);
4966 gen_store_spr(SPR_MQ, t0);
4967 tcg_gen_and_tl(t0, t0, t1);
4968 tcg_gen_andc_tl(t2, t2, t1);
4969 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4970 tcg_temp_free(t0);
4971 tcg_temp_free(t1);
4972 tcg_temp_free(t2);
76a66253 4973 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4975}
4976
4977/* sriq */
4978GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4979{
7487953d
AJ		 4980 int sh = SH(ctx->opcode);
4981 TCGv t0 = tcg_temp_new();
4982 TCGv t1 = tcg_temp_new();
4983 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4984 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4985 tcg_gen_or_tl(t1, t0, t1);
4986 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4987 gen_store_spr(SPR_MQ, t1);
4988 tcg_temp_free(t0);
4989 tcg_temp_free(t1);
76a66253 4990 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4991 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4992}
4993
4994/* srliq */
4995GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4996{
7487953d
AJ		 4997 int sh = SH(ctx->opcode);
4998 TCGv t0 = tcg_temp_new();
4999 TCGv t1 = tcg_temp_new();
5000 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5001 gen_load_spr(t1, SPR_MQ);
5002 gen_store_spr(SPR_MQ, t0);
5003 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5004 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5005 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5006 tcg_temp_free(t0);
5007 tcg_temp_free(t1);
76a66253 5008 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5010}
5011
5012/* srlq */
5013GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5014{
7487953d
AJ		 5015 int l1 = gen_new_label();
5016 int l2 = gen_new_label();
5017 TCGv t0 = tcg_temp_local_new();
5018 TCGv t1 = tcg_temp_local_new();
5019 TCGv t2 = tcg_temp_local_new();
5020 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5021 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5022 tcg_gen_shr_tl(t2, t1, t2);
5023 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5024 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5025 gen_load_spr(t0, SPR_MQ);
5026 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5027 tcg_gen_br(l2);
5028 gen_set_label(l1);
5029 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5030 tcg_gen_and_tl(t0, t0, t2);
5031 gen_load_spr(t1, SPR_MQ);
5032 tcg_gen_andc_tl(t1, t1, t2);
5033 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5034 gen_set_label(l2);
5035 tcg_temp_free(t0);
5036 tcg_temp_free(t1);
5037 tcg_temp_free(t2);
76a66253 5038 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5039 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5040}
5041
5042/* srq */
5043GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5044{
7487953d
AJ		 5045 int l1 = gen_new_label();
5046 TCGv t0 = tcg_temp_new();
5047 TCGv t1 = tcg_temp_new();
5048 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5049 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5050 tcg_gen_subfi_tl(t1, 32, t1);
5051 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5052 tcg_gen_or_tl(t1, t0, t1);
5053 gen_store_spr(SPR_MQ, t1);
5054 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5055 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5056 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5057 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5058 gen_set_label(l1);
5059 tcg_temp_free(t0);
5060 tcg_temp_free(t1);
76a66253 5061 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5062 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5063}
5064
5065/* PowerPC 602 specific instructions */
5066/* dsa */
5067GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5068{
5069 /* XXX: TODO */
e06fcd75 5070 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5071}
5072
5073/* esa */
5074GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5075{
5076 /* XXX: TODO */
e06fcd75 5077 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5078}
5079
5080/* mfrom */
5081GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5082{
5083#if defined(CONFIG_USER_ONLY)
e06fcd75 5084 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5085#else
76db3ba4 5086 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5088 return;
5089 }
cf02a65c 5090 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5091#endif
5092}
5093
5094/* 602 - 603 - G2 TLB management */
5095/* tlbld */
c7697e1f 5096GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5097{
5098#if defined(CONFIG_USER_ONLY)
e06fcd75 5099 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5100#else
76db3ba4 5101 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5103 return;
5104 }
74d37793 5105 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5106#endif
5107}
5108
5109/* tlbli */
c7697e1f 5110GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5111{
5112#if defined(CONFIG_USER_ONLY)
e06fcd75 5113 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5114#else
76db3ba4 5115 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5117 return;
5118 }
74d37793 5119 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5120#endif
5121}
5122
7dbe11ac
JM		 5123/* 74xx TLB management */
5124/* tlbld */
c7697e1f 5125GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5126{
5127#if defined(CONFIG_USER_ONLY)
e06fcd75 5128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5129#else
76db3ba4 5130 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5132 return;
5133 }
74d37793 5134 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5135#endif
5136}
5137
5138/* tlbli */
c7697e1f 5139GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5140{
5141#if defined(CONFIG_USER_ONLY)
e06fcd75 5142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5143#else
76db3ba4 5144 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5146 return;
5147 }
74d37793 5148 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5149#endif
5150}
5151
76a66253
JM		 5152/* POWER instructions not in PowerPC 601 */
5153/* clf */
5154GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5155{
5156 /* Cache line flush: implemented as no-op */
5157}
5158
5159/* cli */
5160GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5161{
7f75ffd3 5162 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5163#if defined(CONFIG_USER_ONLY)
e06fcd75 5164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5165#else
76db3ba4 5166 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5168 return;
5169 }
5170#endif
5171}
5172
5173/* dclst */
5174GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5175{
5176 /* Data cache line store: treated as no-op */
5177}
5178
5179GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5180{
5181#if defined(CONFIG_USER_ONLY)
e06fcd75 5182 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5183#else
74d37793
AJ		 5184 int ra = rA(ctx->opcode);
5185 int rd = rD(ctx->opcode);
5186 TCGv t0;
76db3ba4 5187 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5189 return;
5190 }
74d37793 5191 t0 = tcg_temp_new();
76db3ba4 5192 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5193 tcg_gen_shri_tl(t0, t0, 28);
5194 tcg_gen_andi_tl(t0, t0, 0xF);
5195 gen_helper_load_sr(cpu_gpr[rd], t0);
5196 tcg_temp_free(t0);
76a66253 5197 if (ra != 0 && ra != rd)
74d37793 5198 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5199#endif
5200}
5201
5202GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5203{
5204#if defined(CONFIG_USER_ONLY)
e06fcd75 5205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5206#else
22e0e173 5207 TCGv t0;
76db3ba4 5208 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5210 return;
5211 }
22e0e173 5212 t0 = tcg_temp_new();
76db3ba4 5213 gen_addr_reg_index(ctx, t0);
22e0e173
AJ		 5214 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5215 tcg_temp_free(t0);
76a66253
JM		 5216#endif
5217}
5218
5219GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5220{
5221#if defined(CONFIG_USER_ONLY)
e06fcd75 5222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5223#else
76db3ba4 5224 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5226 return;
5227 }
d72a19f7 5228 gen_helper_rfsvc();
e06fcd75 5229 gen_sync_exception(ctx);
76a66253
JM		 5230#endif
5231}
5232
5233/* svc is not implemented for now */
5234
5235/* POWER2 specific instructions */
5236/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5237
5238/* lfq */
5239GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5240{
01a4afeb 5241 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5242 TCGv t0;
5243 gen_set_access_type(ctx, ACCESS_FLOAT);
5244 t0 = tcg_temp_new();
5245 gen_addr_imm_index(ctx, t0, 0);
5246 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5247 gen_addr_add(ctx, t0, t0, 8);
5248 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5249 tcg_temp_free(t0);
76a66253
JM		 5250}
5251
5252/* lfqu */
5253GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5254{
5255 int ra = rA(ctx->opcode);
01a4afeb 5256 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5257 TCGv t0, t1;
5258 gen_set_access_type(ctx, ACCESS_FLOAT);
5259 t0 = tcg_temp_new();
5260 t1 = tcg_temp_new();
5261 gen_addr_imm_index(ctx, t0, 0);
5262 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5263 gen_addr_add(ctx, t1, t0, 8);
5264 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5265 if (ra != 0)
01a4afeb
AJ		 5266 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5267 tcg_temp_free(t0);
5268 tcg_temp_free(t1);
76a66253
JM		 5269}
5270
5271/* lfqux */
5272GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5273{
5274 int ra = rA(ctx->opcode);
01a4afeb 5275 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5276 gen_set_access_type(ctx, ACCESS_FLOAT);
5277 TCGv t0, t1;
5278 t0 = tcg_temp_new();
5279 gen_addr_reg_index(ctx, t0);
5280 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5281 t1 = tcg_temp_new();
5282 gen_addr_add(ctx, t1, t0, 8);
5283 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5284 tcg_temp_free(t1);
76a66253 5285 if (ra != 0)
01a4afeb
AJ		 5286 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5287 tcg_temp_free(t0);
76a66253
JM		 5288}
5289
5290/* lfqx */
5291GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5292{
01a4afeb 5293 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5294 TCGv t0;
5295 gen_set_access_type(ctx, ACCESS_FLOAT);
5296 t0 = tcg_temp_new();
5297 gen_addr_reg_index(ctx, t0);
5298 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5299 gen_addr_add(ctx, t0, t0, 8);
5300 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5301 tcg_temp_free(t0);
76a66253
JM		 5302}
5303
5304/* stfq */
5305GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5306{
01a4afeb 5307 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5308 TCGv t0;
5309 gen_set_access_type(ctx, ACCESS_FLOAT);
5310 t0 = tcg_temp_new();
5311 gen_addr_imm_index(ctx, t0, 0);
5312 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5313 gen_addr_add(ctx, t0, t0, 8);
5314 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5315 tcg_temp_free(t0);
76a66253
JM		 5316}
5317
5318/* stfqu */
5319GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5320{
5321 int ra = rA(ctx->opcode);
01a4afeb 5322 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5323 TCGv t0, t1;
5324 gen_set_access_type(ctx, ACCESS_FLOAT);
5325 t0 = tcg_temp_new();
5326 gen_addr_imm_index(ctx, t0, 0);
5327 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5328 t1 = tcg_temp_new();
5329 gen_addr_add(ctx, t1, t0, 8);
5330 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5331 tcg_temp_free(t1);
76a66253 5332 if (ra != 0)
01a4afeb
AJ		 5333 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5334 tcg_temp_free(t0);
76a66253
JM		 5335}
5336
5337/* stfqux */
5338GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5339{
5340 int ra = rA(ctx->opcode);
01a4afeb 5341 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5342 TCGv t0, t1;
5343 gen_set_access_type(ctx, ACCESS_FLOAT);
5344 t0 = tcg_temp_new();
5345 gen_addr_reg_index(ctx, t0);
5346 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5347 t1 = tcg_temp_new();
5348 gen_addr_add(ctx, t1, t0, 8);
5349 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5350 tcg_temp_free(t1);
76a66253 5351 if (ra != 0)
01a4afeb
AJ		 5352 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5353 tcg_temp_free(t0);
76a66253
JM		 5354}
5355
5356/* stfqx */
5357GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5358{
01a4afeb 5359 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5360 TCGv t0;
5361 gen_set_access_type(ctx, ACCESS_FLOAT);
5362 t0 = tcg_temp_new();
5363 gen_addr_reg_index(ctx, t0);
5364 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5365 gen_addr_add(ctx, t0, t0, 8);
5366 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5367 tcg_temp_free(t0);
76a66253
JM		 5368}
5369
5370/* BookE specific instructions */
2662a059 5371/* XXX: not implemented on 440 ? */
05332d70 5372GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5373{
5374 /* XXX: TODO */
e06fcd75 5375 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5376}
5377
2662a059 5378/* XXX: not implemented on 440 ? */
05332d70 5379GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5380{
5381#if defined(CONFIG_USER_ONLY)
e06fcd75 5382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5383#else
74d37793 5384 TCGv t0;
76db3ba4 5385 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5387 return;
5388 }
ec72e276 5389 t0 = tcg_temp_new();
76db3ba4 5390 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5391 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5392 tcg_temp_free(t0);
76a66253
JM		 5393#endif
5394}
5395
5396/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5397static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5398 int opc2, int opc3,
5399 int ra, int rb, int rt, int Rc)
76a66253 5400{
182608d4
AJ		 5401 TCGv t0, t1;
5402
a7812ae4
PB		 5403 t0 = tcg_temp_local_new();
5404 t1 = tcg_temp_local_new();
182608d4 5405
76a66253
JM		 5406 switch (opc3 & 0x0D) {
5407 case 0x05:
5408 /* macchw - macchw. - macchwo - macchwo. */
5409 /* macchws - macchws. - macchwso - macchwso. */
5410 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5411 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5412 /* mulchw - mulchw. */
182608d4
AJ		 5413 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5414 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5415 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5416 break;
5417 case 0x04:
5418 /* macchwu - macchwu. - macchwuo - macchwuo. */
5419 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5420 /* mulchwu - mulchwu. */
182608d4
AJ		 5421 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5422 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5423 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5424 break;
5425 case 0x01:
5426 /* machhw - machhw. - machhwo - machhwo. */
5427 /* machhws - machhws. - machhwso - machhwso. */
5428 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5429 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5430 /* mulhhw - mulhhw. */
182608d4
AJ		 5431 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5432 tcg_gen_ext16s_tl(t0, t0);
5433 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5434 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5435 break;
5436 case 0x00:
5437 /* machhwu - machhwu. - machhwuo - machhwuo. */
5438 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5439 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5440 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5441 tcg_gen_ext16u_tl(t0, t0);
5442 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5443 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5444 break;
5445 case 0x0D:
5446 /* maclhw - maclhw. - maclhwo - maclhwo. */
5447 /* maclhws - maclhws. - maclhwso - maclhwso. */
5448 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5449 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5450 /* mullhw - mullhw. */
182608d4
AJ		 5451 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5452 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5453 break;
5454 case 0x0C:
5455 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5456 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5457 /* mullhwu - mullhwu. */
182608d4
AJ		 5458 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5459 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5460 break;
5461 }
76a66253 5462 if (opc2 & 0x04) {
182608d4
AJ		 5463 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5464 tcg_gen_mul_tl(t1, t0, t1);
5465 if (opc2 & 0x02) {
5466 /* nmultiply-and-accumulate (0x0E) */
5467 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5468 } else {
5469 /* multiply-and-accumulate (0x0C) */
5470 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5471 }
5472
5473 if (opc3 & 0x12) {
5474 /* Check overflow and/or saturate */
5475 int l1 = gen_new_label();
5476
5477 if (opc3 & 0x10) {
5478 /* Start with XER OV disabled, the most likely case */
5479 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5480 }
5481 if (opc3 & 0x01) {
5482 /* Signed */
5483 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5484 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5485 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5486 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5487 if (opc3 & 0x02) {
182608d4
AJ		 5488 /* Saturate */
5489 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5490 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5491 }
5492 } else {
5493 /* Unsigned */
5494 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5495 if (opc3 & 0x02) {
182608d4
AJ		 5496 /* Saturate */
5497 tcg_gen_movi_tl(t0, UINT32_MAX);
5498 }
5499 }
5500 if (opc3 & 0x10) {
5501 /* Check overflow */
5502 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5503 }
5504 gen_set_label(l1);
5505 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5506 }
5507 } else {
5508 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5509 }
182608d4
AJ		 5510 tcg_temp_free(t0);
5511 tcg_temp_free(t1);
76a66253
JM		 5512 if (unlikely(Rc) != 0) {
5513 /* Update Rc0 */
182608d4 5514 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5515 }
5516}
5517
a750fc0b
JM		 5518#define GEN_MAC_HANDLER(name, opc2, opc3) \
5519GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5520{ \
5521 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5522 rD(ctx->opcode), Rc(ctx->opcode)); \
5523}
5524
5525/* macchw - macchw. */
a750fc0b 5526GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5527/* macchwo - macchwo. */
a750fc0b 5528GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5529/* macchws - macchws. */
a750fc0b 5530GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5531/* macchwso - macchwso. */
a750fc0b 5532GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5533/* macchwsu - macchwsu. */
a750fc0b 5534GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5535/* macchwsuo - macchwsuo. */
a750fc0b 5536GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5537/* macchwu - macchwu. */
a750fc0b 5538GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5539/* macchwuo - macchwuo. */
a750fc0b 5540GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5541/* machhw - machhw. */
a750fc0b 5542GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5543/* machhwo - machhwo. */
a750fc0b 5544GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5545/* machhws - machhws. */
a750fc0b 5546GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5547/* machhwso - machhwso. */
a750fc0b 5548GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5549/* machhwsu - machhwsu. */
a750fc0b 5550GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5551/* machhwsuo - machhwsuo. */
a750fc0b 5552GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5553/* machhwu - machhwu. */
a750fc0b 5554GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5555/* machhwuo - machhwuo. */
a750fc0b 5556GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5557/* maclhw - maclhw. */
a750fc0b 5558GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5559/* maclhwo - maclhwo. */
a750fc0b 5560GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5561/* maclhws - maclhws. */
a750fc0b 5562GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5563/* maclhwso - maclhwso. */
a750fc0b 5564GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5565/* maclhwu - maclhwu. */
a750fc0b 5566GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5567/* maclhwuo - maclhwuo. */
a750fc0b 5568GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5569/* maclhwsu - maclhwsu. */
a750fc0b 5570GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5571/* maclhwsuo - maclhwsuo. */
a750fc0b 5572GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5573/* nmacchw - nmacchw. */
a750fc0b 5574GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5575/* nmacchwo - nmacchwo. */
a750fc0b 5576GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5577/* nmacchws - nmacchws. */
a750fc0b 5578GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5579/* nmacchwso - nmacchwso. */
a750fc0b 5580GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5581/* nmachhw - nmachhw. */
a750fc0b 5582GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5583/* nmachhwo - nmachhwo. */
a750fc0b 5584GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5585/* nmachhws - nmachhws. */
a750fc0b 5586GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5587/* nmachhwso - nmachhwso. */
a750fc0b 5588GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5589/* nmaclhw - nmaclhw. */
a750fc0b 5590GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5591/* nmaclhwo - nmaclhwo. */
a750fc0b 5592GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5593/* nmaclhws - nmaclhws. */
a750fc0b 5594GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5595/* nmaclhwso - nmaclhwso. */
a750fc0b 5596GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5597
5598/* mulchw - mulchw. */
a750fc0b 5599GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5600/* mulchwu - mulchwu. */
a750fc0b 5601GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5602/* mulhhw - mulhhw. */
a750fc0b 5603GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5604/* mulhhwu - mulhhwu. */
a750fc0b 5605GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5606/* mullhw - mullhw. */
a750fc0b 5607GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5608/* mullhwu - mullhwu. */
a750fc0b 5609GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5610
5611/* mfdcr */
05332d70 5612GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5613{
5614#if defined(CONFIG_USER_ONLY)
e06fcd75 5615 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5616#else
06dca6a7 5617 TCGv dcrn;
76db3ba4 5618 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5619 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5620 return;
5621 }
06dca6a7
AJ		 5622 /* NIP cannot be restored if the memory exception comes from an helper */
5623 gen_update_nip(ctx, ctx->nip - 4);
5624 dcrn = tcg_const_tl(SPR(ctx->opcode));
5625 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5626 tcg_temp_free(dcrn);
76a66253
JM		 5627#endif
5628}
5629
5630/* mtdcr */
05332d70 5631GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5632{
5633#if defined(CONFIG_USER_ONLY)
e06fcd75 5634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5635#else
06dca6a7 5636 TCGv dcrn;
76db3ba4 5637 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5639 return;
5640 }
06dca6a7
AJ		 5641 /* NIP cannot be restored if the memory exception comes from an helper */
5642 gen_update_nip(ctx, ctx->nip - 4);
5643 dcrn = tcg_const_tl(SPR(ctx->opcode));
5644 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5645 tcg_temp_free(dcrn);
a42bd6cc
JM		 5646#endif
5647}
5648
5649/* mfdcrx */
2662a059 5650/* XXX: not implemented on 440 ? */
05332d70 5651GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5652{
5653#if defined(CONFIG_USER_ONLY)
e06fcd75 5654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5655#else
76db3ba4 5656 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5658 return;
5659 }
06dca6a7
AJ		 5660 /* NIP cannot be restored if the memory exception comes from an helper */
5661 gen_update_nip(ctx, ctx->nip - 4);
5662 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5663 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5664#endif
5665}
5666
5667/* mtdcrx */
2662a059 5668/* XXX: not implemented on 440 ? */
05332d70 5669GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5670{
5671#if defined(CONFIG_USER_ONLY)
e06fcd75 5672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5673#else
76db3ba4 5674 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5676 return;
5677 }
06dca6a7
AJ		 5678 /* NIP cannot be restored if the memory exception comes from an helper */
5679 gen_update_nip(ctx, ctx->nip - 4);
5680 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5681 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5682#endif
5683}
5684
a750fc0b
JM		 5685/* mfdcrux (PPC 460) : user-mode access to DCR */
5686GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5687{
06dca6a7
AJ		 5688 /* NIP cannot be restored if the memory exception comes from an helper */
5689 gen_update_nip(ctx, ctx->nip - 4);
5690 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5691 /* Note: Rc update flag set leads to undefined state of Rc0 */
5692}
5693
5694/* mtdcrux (PPC 460) : user-mode access to DCR */
5695GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5696{
06dca6a7
AJ		 5697 /* NIP cannot be restored if the memory exception comes from an helper */
5698 gen_update_nip(ctx, ctx->nip - 4);
5699 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5700 /* Note: Rc update flag set leads to undefined state of Rc0 */
5701}
5702
76a66253
JM		 5703/* dccci */
5704GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5705{
5706#if defined(CONFIG_USER_ONLY)
e06fcd75 5707 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5708#else
76db3ba4 5709 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5710 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5711 return;
5712 }
5713 /* interpreted as no-op */
5714#endif
5715}
5716
5717/* dcread */
5718GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5719{
5720#if defined(CONFIG_USER_ONLY)
e06fcd75 5721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5722#else
b61f2753 5723 TCGv EA, val;
76db3ba4 5724 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5726 return;
5727 }
76db3ba4 5728 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5729 EA = tcg_temp_new();
76db3ba4 5730 gen_addr_reg_index(ctx, EA);
a7812ae4 5731 val = tcg_temp_new();
76db3ba4 5732 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5733 tcg_temp_free(val);
5734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5735 tcg_temp_free(EA);
76a66253
JM		 5736#endif
5737}
5738
5739/* icbt */
c7697e1f 5740GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5741{
5742 /* interpreted as no-op */
5743 /* XXX: specification say this is treated as a load by the MMU
5744 * but does not generate any exception
5745 */
5746}
5747
5748/* iccci */
5749GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5750{
5751#if defined(CONFIG_USER_ONLY)
e06fcd75 5752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5753#else
76db3ba4 5754 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5756 return;
5757 }
5758 /* interpreted as no-op */
5759#endif
5760}
5761
5762/* icread */
5763GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5764{
5765#if defined(CONFIG_USER_ONLY)
e06fcd75 5766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5767#else
76db3ba4 5768 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5770 return;
5771 }
5772 /* interpreted as no-op */
5773#endif
5774}
5775
76db3ba4 5776/* rfci (mem_idx only) */
c7697e1f 5777GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5778{
5779#if defined(CONFIG_USER_ONLY)
e06fcd75 5780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5781#else
76db3ba4 5782 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5784 return;
5785 }
5786 /* Restore CPU state */
d72a19f7 5787 gen_helper_40x_rfci();
e06fcd75 5788 gen_sync_exception(ctx);
a42bd6cc
JM		 5789#endif
5790}
5791
5792GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5793{
5794#if defined(CONFIG_USER_ONLY)
e06fcd75 5795 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5796#else
76db3ba4 5797 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5799 return;
5800 }
5801 /* Restore CPU state */
d72a19f7 5802 gen_helper_rfci();
e06fcd75 5803 gen_sync_exception(ctx);
a42bd6cc
JM		 5804#endif
5805}
5806
5807/* BookE specific */
2662a059 5808/* XXX: not implemented on 440 ? */
05332d70 5809GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5810{
5811#if defined(CONFIG_USER_ONLY)
e06fcd75 5812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5813#else
76db3ba4 5814 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5816 return;
5817 }
5818 /* Restore CPU state */
d72a19f7 5819 gen_helper_rfdi();
e06fcd75 5820 gen_sync_exception(ctx);
76a66253
JM		 5821#endif
5822}
5823
2662a059 5824/* XXX: not implemented on 440 ? */
a750fc0b 5825GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5826{
5827#if defined(CONFIG_USER_ONLY)
e06fcd75 5828 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5829#else
76db3ba4 5830 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5832 return;
5833 }
5834 /* Restore CPU state */
d72a19f7 5835 gen_helper_rfmci();
e06fcd75 5836 gen_sync_exception(ctx);
a42bd6cc
JM		 5837#endif
5838}
5eb7995e 5839
d9bce9d9 5840/* TLB management - PowerPC 405 implementation */
76a66253 5841/* tlbre */
c7697e1f 5842GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5843{
5844#if defined(CONFIG_USER_ONLY)
e06fcd75 5845 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5846#else
76db3ba4 5847 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5849 return;
5850 }
5851 switch (rB(ctx->opcode)) {
5852 case 0:
74d37793 5853 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5854 break;
5855 case 1:
74d37793 5856 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5857 break;
5858 default:
e06fcd75 5859 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5860 break;
9a64fbe4 5861 }
76a66253
JM		 5862#endif
5863}
5864
d9bce9d9 5865/* tlbsx - tlbsx. */
c7697e1f 5866GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5867{
5868#if defined(CONFIG_USER_ONLY)
e06fcd75 5869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5870#else
74d37793 5871 TCGv t0;
76db3ba4 5872 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5873 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5874 return;
5875 }
74d37793 5876 t0 = tcg_temp_new();
76db3ba4 5877 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5878 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5879 tcg_temp_free(t0);
5880 if (Rc(ctx->opcode)) {
5881 int l1 = gen_new_label();
5882 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5883 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5884 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5885 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5886 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5887 gen_set_label(l1);
5888 }
76a66253 5889#endif
79aceca5
FB		 5890}
5891
76a66253 5892/* tlbwe */
c7697e1f 5893GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5894{
76a66253 5895#if defined(CONFIG_USER_ONLY)
e06fcd75 5896 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5897#else
76db3ba4 5898 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5899 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5900 return;
5901 }
5902 switch (rB(ctx->opcode)) {
5903 case 0:
74d37793 5904 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5905 break;
5906 case 1:
74d37793 5907 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5908 break;
5909 default:
e06fcd75 5910 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5911 break;
9a64fbe4 5912 }
76a66253
JM		 5913#endif
5914}
5915
a4bb6c3e 5916/* TLB management - PowerPC 440 implementation */
5eb7995e 5917/* tlbre */
c7697e1f 5918GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5919{
5920#if defined(CONFIG_USER_ONLY)
e06fcd75 5921 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5922#else
76db3ba4 5923 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5924 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5925 return;
5926 }
5927 switch (rB(ctx->opcode)) {
5928 case 0:
5eb7995e 5929 case 1:
5eb7995e 5930 case 2:
74d37793
AJ		 5931 {
5932 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5933 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5934 tcg_temp_free_i32(t0);
5935 }
5eb7995e
JM		 5936 break;
5937 default:
e06fcd75 5938 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 5939 break;
5940 }
5941#endif
5942}
5943
5944/* tlbsx - tlbsx. */
c7697e1f 5945GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5946{
5947#if defined(CONFIG_USER_ONLY)
e06fcd75 5948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5949#else
74d37793 5950 TCGv t0;
76db3ba4 5951 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5952 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5953 return;
5954 }
74d37793 5955 t0 = tcg_temp_new();
76db3ba4 5956 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5957 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5958 tcg_temp_free(t0);
5959 if (Rc(ctx->opcode)) {
5960 int l1 = gen_new_label();
5961 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5962 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5963 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5964 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5965 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5966 gen_set_label(l1);
5967 }
5eb7995e
JM		 5968#endif
5969}
5970
5971/* tlbwe */
c7697e1f 5972GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5973{
5974#if defined(CONFIG_USER_ONLY)
e06fcd75 5975 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5976#else
76db3ba4 5977 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5978 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5979 return;
5980 }
5981 switch (rB(ctx->opcode)) {
5982 case 0:
5eb7995e 5983 case 1:
5eb7995e 5984 case 2:
74d37793
AJ		 5985 {
5986 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5987 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5988 tcg_temp_free_i32(t0);
5989 }
5eb7995e
JM		 5990 break;
5991 default:
e06fcd75 5992 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 5993 break;
5994 }
5995#endif
5996}
5997
76a66253 5998/* wrtee */
05332d70 5999GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6000{
6001#if defined(CONFIG_USER_ONLY)
e06fcd75 6002 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6003#else
6527f6ea 6004 TCGv t0;
76db3ba4 6005 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6006 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6007 return;
6008 }
6527f6ea
AJ		 6009 t0 = tcg_temp_new();
6010 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6011 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6012 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6013 tcg_temp_free(t0);
dee96f6c
JM		 6014 /* Stop translation to have a chance to raise an exception
6015 * if we just set msr_ee to 1
6016 */
e06fcd75 6017 gen_stop_exception(ctx);
76a66253
JM		 6018#endif
6019}
6020
6021/* wrteei */
05332d70 6022GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6023{
6024#if defined(CONFIG_USER_ONLY)
e06fcd75 6025 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6026#else
76db3ba4 6027 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6028 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6029 return;
6030 }
6527f6ea
AJ		 6031 if (ctx->opcode & 0x00010000) {
6032 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6033 /* Stop translation to have a chance to raise an exception */
e06fcd75 6034 gen_stop_exception(ctx);
6527f6ea
AJ		 6035 } else {
6036 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6037 }
76a66253
JM		 6038#endif
6039}
6040
08e46e54 6041/* PowerPC 440 specific instructions */
76a66253
JM		 6042/* dlmzb */
6043GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6044{
ef0d51af
AJ		 6045 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6046 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6047 cpu_gpr[rB(ctx->opcode)], t0);
6048 tcg_temp_free_i32(t0);
76a66253
JM		 6049}
6050
6051/* mbar replaces eieio on 440 */
26370046 6052GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
76a66253
JM		 6053{
6054 /* interpreted as no-op */
6055}
6056
6057/* msync replaces sync on 440 */
0db1b20e 6058GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6059{
6060 /* interpreted as no-op */
6061}
6062
6063/* icbt */
c7697e1f 6064GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6065{
6066 /* interpreted as no-op */
6067 /* XXX: specification say this is treated as a load by the MMU
6068 * but does not generate any exception
6069 */
79aceca5
FB		 6070}
6071
a9d9eb8f
JM		 6072/*** Altivec vector extension ***/
6073/* Altivec registers moves */
a9d9eb8f 6074
a9d9eb8f 6075#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6076GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6077{ \
fe1e5c53 6078 TCGv EA; \
a9d9eb8f 6079 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6080 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6081 return; \
6082 } \
76db3ba4 6083 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6084 EA = tcg_temp_new(); \
76db3ba4 6085 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6086 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6087 if (ctx->le_mode) { \
6088 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6089 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6090 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6091 } else { \
76db3ba4 6092 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6093 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6094 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6095 } \
6096 tcg_temp_free(EA); \
a9d9eb8f
JM		 6097}
6098
6099#define GEN_VR_STX(name, opc2, opc3) \
6100GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6101{ \
fe1e5c53 6102 TCGv EA; \
a9d9eb8f 6103 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6104 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6105 return; \
6106 } \
76db3ba4 6107 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6108 EA = tcg_temp_new(); \
76db3ba4 6109 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6110 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6111 if (ctx->le_mode) { \
6112 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6113 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6114 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6115 } else { \
76db3ba4 6116 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6117 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6118 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6119 } \
6120 tcg_temp_free(EA); \
a9d9eb8f
JM		 6121}
6122
fe1e5c53 6123GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6124/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6125GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6126
fe1e5c53 6127GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6128/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6129GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6130
0487d6a8 6131/*** SPE extension ***/
0487d6a8 6132/* Register moves */
3cd7d1dd 6133
a7812ae4 6134static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6135#if defined(TARGET_PPC64)
6136 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6137#else
36aa55dc 6138 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6139#endif
f78fb44e 6140}
3cd7d1dd 6141
a7812ae4 6142static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6143#if defined(TARGET_PPC64)
6144 tcg_gen_mov_i64(cpu_gpr[reg], t);
6145#else
a7812ae4 6146 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6147 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6148 tcg_gen_shri_i64(tmp, t, 32);
6149 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6150 tcg_temp_free_i64(tmp);
3cd7d1dd 6151#endif
f78fb44e 6152}
3cd7d1dd 6153
0487d6a8
JM		 6154#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6155GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6156{ \
6157 if (Rc(ctx->opcode)) \
6158 gen_##name1(ctx); \
6159 else \
6160 gen_##name0(ctx); \
6161}
6162
6163/* Handler for undefined SPE opcodes */
b068d6a7 6164static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6165{
e06fcd75 6166 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 6167}
6168
57951c27
AJ		 6169/* SPE logic */
6170#if defined(TARGET_PPC64)
6171#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6172static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6173{ \
6174 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6175 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6176 return; \
6177 } \
57951c27
AJ		 6178 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6179 cpu_gpr[rB(ctx->opcode)]); \
6180}
6181#else
6182#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6183static always_inline void gen_##name (DisasContext *ctx) \
6184{ \
6185 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6186 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6187 return; \
6188 } \
6189 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6190 cpu_gpr[rB(ctx->opcode)]); \
6191 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6192 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6193}
57951c27
AJ		 6194#endif
6195
6196GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6197GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6198GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6199GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6200GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6201GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6202GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6203GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6204
57951c27
AJ		 6205/* SPE logic immediate */
6206#if defined(TARGET_PPC64)
6207#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6208static always_inline void gen_##name (DisasContext *ctx) \
6209{ \
6210 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6211 gen_exception(ctx, POWERPC_EXCP_APU); \
3d3a6a0a
AJ		 6212 return; \
6213 } \
a7812ae4
PB		 6214 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6215 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6216 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6217 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6218 tcg_opi(t0, t0, rB(ctx->opcode)); \
6219 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6220 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6221 tcg_temp_free_i64(t2); \
57951c27
AJ		 6222 tcg_opi(t1, t1, rB(ctx->opcode)); \
6223 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6224 tcg_temp_free_i32(t0); \
6225 tcg_temp_free_i32(t1); \
3d3a6a0a 6226}
57951c27
AJ		 6227#else
6228#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6229static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6230{ \
6231 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6232 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6233 return; \
6234 } \
57951c27
AJ		 6235 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6236 rB(ctx->opcode)); \
6237 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6238 rB(ctx->opcode)); \
0487d6a8 6239}
57951c27
AJ		 6240#endif
6241GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6242GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6243GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6244GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6245
57951c27
AJ		 6246/* SPE arithmetic */
6247#if defined(TARGET_PPC64)
6248#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6249static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6250{ \
6251 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6252 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6253 return; \
6254 } \
a7812ae4
PB		 6255 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6256 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6257 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6258 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6259 tcg_op(t0, t0); \
6260 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6261 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6262 tcg_temp_free_i64(t2); \
57951c27
AJ		 6263 tcg_op(t1, t1); \
6264 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6265 tcg_temp_free_i32(t0); \
6266 tcg_temp_free_i32(t1); \
0487d6a8 6267}
57951c27 6268#else
a7812ae4 6269#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6270static always_inline void gen_##name (DisasContext *ctx) \
6271{ \
6272 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6273 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6274 return; \
6275 } \
6276 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6277 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6278}
6279#endif
0487d6a8 6280
a7812ae4 6281static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6282{
6283 int l1 = gen_new_label();
6284 int l2 = gen_new_label();
0487d6a8 6285
57951c27
AJ		 6286 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6287 tcg_gen_neg_i32(ret, arg1);
6288 tcg_gen_br(l2);
6289 gen_set_label(l1);
a7812ae4 6290 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6291 gen_set_label(l2);
6292}
6293GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6294GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6295GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6296GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6297static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6298{
57951c27
AJ		 6299 tcg_gen_addi_i32(ret, arg1, 0x8000);
6300 tcg_gen_ext16u_i32(ret, ret);
6301}
6302GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6303GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6304GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6305
57951c27
AJ		 6306#if defined(TARGET_PPC64)
6307#define GEN_SPEOP_ARITH2(name, tcg_op) \
6308static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6309{ \
6310 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6311 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6312 return; \
6313 } \
a7812ae4
PB		 6314 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6315 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6316 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6317 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
57951c27
AJ		 6318 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6319 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6320 tcg_op(t0, t0, t2); \
6321 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6322 tcg_gen_trunc_i64_i32(t1, t3); \
6323 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6324 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6325 tcg_temp_free_i64(t3); \
57951c27 6326 tcg_op(t1, t1, t2); \
a7812ae4 6327 tcg_temp_free_i32(t2); \
57951c27 6328 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6329 tcg_temp_free_i32(t0); \
6330 tcg_temp_free_i32(t1); \
0487d6a8 6331}
57951c27
AJ		 6332#else
6333#define GEN_SPEOP_ARITH2(name, tcg_op) \
6334static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6335{ \
6336 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6337 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6338 return; \
6339 } \
57951c27
AJ		 6340 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6341 cpu_gpr[rB(ctx->opcode)]); \
6342 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6343 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6344}
57951c27 6345#endif
0487d6a8 6346
a7812ae4 6347static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6348{
a7812ae4 6349 TCGv_i32 t0;
57951c27 6350 int l1, l2;
0487d6a8 6351
57951c27
AJ		 6352 l1 = gen_new_label();
6353 l2 = gen_new_label();
a7812ae4 6354 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6355 /* No error here: 6 bits are used */
6356 tcg_gen_andi_i32(t0, arg2, 0x3F);
6357 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6358 tcg_gen_shr_i32(ret, arg1, t0);
6359 tcg_gen_br(l2);
6360 gen_set_label(l1);
6361 tcg_gen_movi_i32(ret, 0);
6362 tcg_gen_br(l2);
a7812ae4 6363 tcg_temp_free_i32(t0);
57951c27
AJ		 6364}
6365GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6366static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6367{
a7812ae4 6368 TCGv_i32 t0;
57951c27
AJ		 6369 int l1, l2;
6370
6371 l1 = gen_new_label();
6372 l2 = gen_new_label();
a7812ae4 6373 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6374 /* No error here: 6 bits are used */
6375 tcg_gen_andi_i32(t0, arg2, 0x3F);
6376 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6377 tcg_gen_sar_i32(ret, arg1, t0);
6378 tcg_gen_br(l2);
6379 gen_set_label(l1);
6380 tcg_gen_movi_i32(ret, 0);
6381 tcg_gen_br(l2);
a7812ae4 6382 tcg_temp_free_i32(t0);
57951c27
AJ		 6383}
6384GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6385static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6386{
a7812ae4 6387 TCGv_i32 t0;
57951c27
AJ		 6388 int l1, l2;
6389
6390 l1 = gen_new_label();
6391 l2 = gen_new_label();
a7812ae4 6392 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6393 /* No error here: 6 bits are used */
6394 tcg_gen_andi_i32(t0, arg2, 0x3F);
6395 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6396 tcg_gen_shl_i32(ret, arg1, t0);
6397 tcg_gen_br(l2);
6398 gen_set_label(l1);
6399 tcg_gen_movi_i32(ret, 0);
6400 tcg_gen_br(l2);
a7812ae4 6401 tcg_temp_free_i32(t0);
57951c27
AJ		 6402}
6403GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6404static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6405{
a7812ae4 6406 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6407 tcg_gen_andi_i32(t0, arg2, 0x1F);
6408 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6409 tcg_temp_free_i32(t0);
57951c27
AJ		 6410}
6411GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6412static always_inline void gen_evmergehi (DisasContext *ctx)
6413{
6414 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6415 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6416 return;
6417 }
6418#if defined(TARGET_PPC64)
a7812ae4
PB		 6419 TCGv t0 = tcg_temp_new();
6420 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6421 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6422 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6423 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6424 tcg_temp_free(t0);
6425 tcg_temp_free(t1);
6426#else
6427 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6428 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6429#endif
6430}
6431GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6432static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6433{
57951c27
AJ		 6434 tcg_gen_sub_i32(ret, arg2, arg1);
6435}
6436GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6437
57951c27
AJ		 6438/* SPE arithmetic immediate */
6439#if defined(TARGET_PPC64)
6440#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6441static always_inline void gen_##name (DisasContext *ctx) \
6442{ \
6443 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6444 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6445 return; \
6446 } \
a7812ae4
PB		 6447 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6448 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6449 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6450 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6451 tcg_op(t0, t0, rA(ctx->opcode)); \
6452 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6453 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 6454 tcg_temp_free_i64(t2); \
57951c27
AJ		 6455 tcg_op(t1, t1, rA(ctx->opcode)); \
6456 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6457 tcg_temp_free_i32(t0); \
6458 tcg_temp_free_i32(t1); \
57951c27
AJ		 6459}
6460#else
6461#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6462static always_inline void gen_##name (DisasContext *ctx) \
6463{ \
6464 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6465 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6466 return; \
6467 } \
6468 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6469 rA(ctx->opcode)); \
6470 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6471 rA(ctx->opcode)); \
6472}
6473#endif
6474GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6475GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6476
6477/* SPE comparison */
6478#if defined(TARGET_PPC64)
6479#define GEN_SPEOP_COMP(name, tcg_cond) \
6480static always_inline void gen_##name (DisasContext *ctx) \
6481{ \
6482 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6483 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6484 return; \
6485 } \
6486 int l1 = gen_new_label(); \
6487 int l2 = gen_new_label(); \
6488 int l3 = gen_new_label(); \
6489 int l4 = gen_new_label(); \
a7812ae4
PB		 6490 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6491 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6492 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6493 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6494 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6495 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6496 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6497 tcg_gen_br(l2); \
6498 gen_set_label(l1); \
6499 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6500 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6501 gen_set_label(l2); \
6502 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6503 tcg_gen_trunc_i64_i32(t0, t2); \
6504 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6505 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6506 tcg_temp_free_i64(t2); \
57951c27
AJ		 6507 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6508 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6509 ~(CRF_CH | CRF_CH_AND_CL)); \
6510 tcg_gen_br(l4); \
6511 gen_set_label(l3); \
6512 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6513 CRF_CH | CRF_CH_OR_CL); \
6514 gen_set_label(l4); \
a7812ae4
PB		 6515 tcg_temp_free_i32(t0); \
6516 tcg_temp_free_i32(t1); \
57951c27
AJ		 6517}
6518#else
6519#define GEN_SPEOP_COMP(name, tcg_cond) \
6520static always_inline void gen_##name (DisasContext *ctx) \
6521{ \
6522 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6523 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6524 return; \
6525 } \
6526 int l1 = gen_new_label(); \
6527 int l2 = gen_new_label(); \
6528 int l3 = gen_new_label(); \
6529 int l4 = gen_new_label(); \
6530 \
6531 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6532 cpu_gpr[rB(ctx->opcode)], l1); \
6533 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6534 tcg_gen_br(l2); \
6535 gen_set_label(l1); \
6536 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6537 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6538 gen_set_label(l2); \
6539 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6540 cpu_gprh[rB(ctx->opcode)], l3); \
6541 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6542 ~(CRF_CH | CRF_CH_AND_CL)); \
6543 tcg_gen_br(l4); \
6544 gen_set_label(l3); \
6545 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6546 CRF_CH | CRF_CH_OR_CL); \
6547 gen_set_label(l4); \
6548}
6549#endif
6550GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6551GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6552GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6553GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6554GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6555
6556/* SPE misc */
6557static always_inline void gen_brinc (DisasContext *ctx)
6558{
6559 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6560 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6561 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6562}
57951c27
AJ		 6563static always_inline void gen_evmergelo (DisasContext *ctx)
6564{
6565 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6566 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6567 return;
6568 }
6569#if defined(TARGET_PPC64)
a7812ae4
PB		 6570 TCGv t0 = tcg_temp_new();
6571 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6572 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6573 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6574 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6575 tcg_temp_free(t0);
6576 tcg_temp_free(t1);
6577#else
6578 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6579 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6580#endif
6581}
6582static always_inline void gen_evmergehilo (DisasContext *ctx)
6583{
6584 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6585 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6586 return;
6587 }
6588#if defined(TARGET_PPC64)
a7812ae4
PB		 6589 TCGv t0 = tcg_temp_new();
6590 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6591 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6592 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6593 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6594 tcg_temp_free(t0);
6595 tcg_temp_free(t1);
6596#else
6597 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6598 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6599#endif
6600}
6601static always_inline void gen_evmergelohi (DisasContext *ctx)
6602{
6603 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6604 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6605 return;
6606 }
6607#if defined(TARGET_PPC64)
a7812ae4
PB		 6608 TCGv t0 = tcg_temp_new();
6609 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6610 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6611 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6612 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6613 tcg_temp_free(t0);
6614 tcg_temp_free(t1);
6615#else
6616 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6617 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6618#endif
6619}
6620static always_inline void gen_evsplati (DisasContext *ctx)
6621{
38d14952 6622 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 6623
57951c27 6624#if defined(TARGET_PPC64)
38d14952 6625 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6626#else
6627 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6628 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6629#endif
6630}
b068d6a7 6631static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 6632{
38d14952 6633 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 6634
57951c27 6635#if defined(TARGET_PPC64)
38d14952 6636 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6637#else
6638 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6639 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6640#endif
0487d6a8
JM		 6641}
6642
57951c27
AJ		 6643static always_inline void gen_evsel (DisasContext *ctx)
6644{
6645 int l1 = gen_new_label();
6646 int l2 = gen_new_label();
6647 int l3 = gen_new_label();
6648 int l4 = gen_new_label();
a7812ae4 6649 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 6650#if defined(TARGET_PPC64)
a7812ae4
PB		 6651 TCGv t1 = tcg_temp_local_new();
6652 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 6653#endif
6654 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6655 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6656#if defined(TARGET_PPC64)
6657 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6658#else
6659 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6660#endif
6661 tcg_gen_br(l2);
6662 gen_set_label(l1);
6663#if defined(TARGET_PPC64)
6664 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6665#else
6666 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6667#endif
6668 gen_set_label(l2);
6669 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6670 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6671#if defined(TARGET_PPC64)
6672 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6673#else
6674 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6675#endif
6676 tcg_gen_br(l4);
6677 gen_set_label(l3);
6678#if defined(TARGET_PPC64)
6679 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6680#else
6681 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6682#endif
6683 gen_set_label(l4);
a7812ae4 6684 tcg_temp_free_i32(t0);
57951c27
AJ		 6685#if defined(TARGET_PPC64)
6686 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6687 tcg_temp_free(t1);
6688 tcg_temp_free(t2);
6689#endif
6690}
6691GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6692{
6693 gen_evsel(ctx);
6694}
6695GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6696{
6697 gen_evsel(ctx);
6698}
6699GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6700{
6701 gen_evsel(ctx);
6702}
6703GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6704{
6705 gen_evsel(ctx);
6706}
0487d6a8
JM		 6707
6708GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6709GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6710GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6711GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6712GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6713GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6714GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6715GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6716GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6717GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6718GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6719GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6720GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6721GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6722GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6723GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6724GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6725GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6726GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6727GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6728GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6729GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6730GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6731GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6732GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6733
6a6ae23f 6734/* SPE load and stores */
76db3ba4 6735static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 6736{
6737 target_ulong uimm = rB(ctx->opcode);
6738
76db3ba4 6739 if (rA(ctx->opcode) == 0) {
6a6ae23f 6740 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 6741 } else {
6a6ae23f 6742 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
76db3ba4
AJ		 6743#if defined(TARGET_PPC64)
6744 if (!ctx->sf_mode) {
6745 tcg_gen_ext32u_tl(EA, EA);
6746 }
6747#endif
6748 }
0487d6a8 6749}
6a6ae23f
AJ		 6750
6751static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6752{
6753#if defined(TARGET_PPC64)
76db3ba4 6754 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 6755#else
6756 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 6757 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 6758 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6759 tcg_gen_shri_i64(t0, t0, 32);
6760 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6761 tcg_temp_free_i64(t0);
6762#endif
0487d6a8 6763}
6a6ae23f
AJ		 6764
6765static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6766{
0487d6a8 6767#if defined(TARGET_PPC64)
6a6ae23f 6768 TCGv t0 = tcg_temp_new();
76db3ba4 6769 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 6770 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 6771 gen_addr_add(ctx, addr, addr, 4);
6772 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 6773 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6774 tcg_temp_free(t0);
6775#else
76db3ba4
AJ		 6776 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
6777 gen_addr_add(ctx, addr, addr, 4);
6778 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 6779#endif
0487d6a8 6780}
6a6ae23f
AJ		 6781
6782static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6783{
6784 TCGv t0 = tcg_temp_new();
6785#if defined(TARGET_PPC64)
76db3ba4 6786 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 6787 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 6788 gen_addr_add(ctx, addr, addr, 2);
6789 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6790 tcg_gen_shli_tl(t0, t0, 32);
6791 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 6792 gen_addr_add(ctx, addr, addr, 2);
6793 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6794 tcg_gen_shli_tl(t0, t0, 16);
6795 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 6796 gen_addr_add(ctx, addr, addr, 2);
6797 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 6798 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6799#else
76db3ba4 6800 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 6801 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 6802 gen_addr_add(ctx, addr, addr, 2);
6803 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 6804 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 6805 gen_addr_add(ctx, addr, addr, 2);
6806 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 6807 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 6808 gen_addr_add(ctx, addr, addr, 2);
6809 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 6810 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6811#endif
6a6ae23f 6812 tcg_temp_free(t0);
0487d6a8
JM		 6813}
6814
6a6ae23f
AJ		 6815static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6816{
6817 TCGv t0 = tcg_temp_new();
76db3ba4 6818 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6819#if defined(TARGET_PPC64)
6820 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6821 tcg_gen_shli_tl(t0, t0, 16);
6822 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6823#else
6824 tcg_gen_shli_tl(t0, t0, 16);
6825 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6826 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6827#endif
6828 tcg_temp_free(t0);
0487d6a8
JM		 6829}
6830
6a6ae23f
AJ		 6831static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6832{
6833 TCGv t0 = tcg_temp_new();
76db3ba4 6834 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6835#if defined(TARGET_PPC64)
6836 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6837 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6838#else
6839 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6840 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6841#endif
6842 tcg_temp_free(t0);
0487d6a8
JM		 6843}
6844
6a6ae23f
AJ		 6845static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6846{
6847 TCGv t0 = tcg_temp_new();
76db3ba4 6848 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 6849#if defined(TARGET_PPC64)
6850 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6851 tcg_gen_ext32u_tl(t0, t0);
6852 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6853#else
6854 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6855 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6856#endif
6857 tcg_temp_free(t0);
6858}
6859
6860static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6861{
6862 TCGv t0 = tcg_temp_new();
6863#if defined(TARGET_PPC64)
76db3ba4 6864 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 6865 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 6866 gen_addr_add(ctx, addr, addr, 2);
6867 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6868 tcg_gen_shli_tl(t0, t0, 16);
6869 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6870#else
76db3ba4 6871 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 6872 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 6873 gen_addr_add(ctx, addr, addr, 2);
6874 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6875 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6876#endif
6877 tcg_temp_free(t0);
6878}
6879
6880static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6881{
6882#if defined(TARGET_PPC64)
6883 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 6884 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6885 gen_addr_add(ctx, addr, addr, 2);
6886 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6887 tcg_gen_shli_tl(t0, t0, 32);
6888 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6889 tcg_temp_free(t0);
6890#else
76db3ba4
AJ		 6891 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
6892 gen_addr_add(ctx, addr, addr, 2);
6893 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 6894#endif
6895}
6896
6897static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6898{
6899#if defined(TARGET_PPC64)
6900 TCGv t0 = tcg_temp_new();
76db3ba4 6901 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 6902 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 6903 gen_addr_add(ctx, addr, addr, 2);
6904 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 6905 tcg_gen_shli_tl(t0, t0, 32);
6906 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6907 tcg_temp_free(t0);
6908#else
76db3ba4
AJ		 6909 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
6910 gen_addr_add(ctx, addr, addr, 2);
6911 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 6912#endif
6913}
6914
6915static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6916{
6917 TCGv t0 = tcg_temp_new();
76db3ba4 6918 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 6919#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6920 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6921 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6922#else
6923 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6924 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6925#endif
6926 tcg_temp_free(t0);
6927}
6928
6929static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6930{
6931 TCGv t0 = tcg_temp_new();
6932#if defined(TARGET_PPC64)
76db3ba4 6933 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6934 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6935 tcg_gen_shli_tl(t0, t0, 32);
6936 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 6937 gen_addr_add(ctx, addr, addr, 2);
6938 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6939 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6940 tcg_gen_shli_tl(t0, t0, 16);
6941 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6942#else
76db3ba4 6943 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6944 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6945 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 6946 gen_addr_add(ctx, addr, addr, 2);
6947 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 6948 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6949 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 6950#endif
6a6ae23f
AJ		 6951 tcg_temp_free(t0);
6952}
6953
6954static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6955{
6956#if defined(TARGET_PPC64)
76db3ba4 6957 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 6958#else
6a6ae23f
AJ		 6959 TCGv_i64 t0 = tcg_temp_new_i64();
6960 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 6961 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 6962 tcg_temp_free_i64(t0);
6963#endif
6964}
6965
6966static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6967{
0487d6a8 6968#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6969 TCGv t0 = tcg_temp_new();
6970 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 6971 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 6972 tcg_temp_free(t0);
6973#else
76db3ba4 6974 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 6975#endif
76db3ba4
AJ		 6976 gen_addr_add(ctx, addr, addr, 4);
6977 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 6978}
6979
6980static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6981{
6982 TCGv t0 = tcg_temp_new();
6983#if defined(TARGET_PPC64)
6984 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6985#else
6986 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6987#endif
76db3ba4
AJ		 6988 gen_qemu_st16(ctx, t0, addr);
6989 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 6990#if defined(TARGET_PPC64)
6991 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 6992 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 6993#else
76db3ba4 6994 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 6995#endif
76db3ba4 6996 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 6997 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 6998 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 6999 tcg_temp_free(t0);
76db3ba4
AJ		 7000 gen_addr_add(ctx, addr, addr, 2);
7001 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7002}
7003
7004static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7005{
7006 TCGv t0 = tcg_temp_new();
7007#if defined(TARGET_PPC64)
7008 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7009#else
7010 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7011#endif
76db3ba4
AJ		 7012 gen_qemu_st16(ctx, t0, addr);
7013 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7014 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7015 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7016 tcg_temp_free(t0);
7017}
7018
7019static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7020{
7021#if defined(TARGET_PPC64)
7022 TCGv t0 = tcg_temp_new();
7023 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7024 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7025 tcg_temp_free(t0);
7026#else
76db3ba4 7027 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7028#endif
76db3ba4
AJ		 7029 gen_addr_add(ctx, addr, addr, 2);
7030 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7031}
7032
7033static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7034{
7035#if defined(TARGET_PPC64)
7036 TCGv t0 = tcg_temp_new();
7037 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7038 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7039 tcg_temp_free(t0);
7040#else
76db3ba4 7041 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7042#endif
7043}
7044
7045static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7046{
76db3ba4 7047 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7048}
7049
7050#define GEN_SPEOP_LDST(name, opc2, sh) \
76db3ba4 7051GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6a6ae23f
AJ		 7052{ \
7053 TCGv t0; \
7054 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7055 gen_exception(ctx, POWERPC_EXCP_APU); \
6a6ae23f
AJ		 7056 return; \
7057 } \
76db3ba4 7058 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 7059 t0 = tcg_temp_new(); \
7060 if (Rc(ctx->opcode)) { \
76db3ba4 7061 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 7062 } else { \
76db3ba4 7063 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 7064 } \
7065 gen_op_##name(ctx, t0); \
7066 tcg_temp_free(t0); \
7067}
7068
7069GEN_SPEOP_LDST(evldd, 0x00, 3);
7070GEN_SPEOP_LDST(evldw, 0x01, 3);
7071GEN_SPEOP_LDST(evldh, 0x02, 3);
7072GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7073GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7074GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7075GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7076GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7077GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7078GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7079GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7080
7081GEN_SPEOP_LDST(evstdd, 0x10, 3);
7082GEN_SPEOP_LDST(evstdw, 0x11, 3);
7083GEN_SPEOP_LDST(evstdh, 0x12, 3);
7084GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7085GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7086GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7087GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7088
7089/* Multiply and add - TODO */
7090#if 0
7091GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7092GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7093GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7094GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7095GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7096GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7097GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7098GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7099GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7100GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7101GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7102GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7103
7104GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7105GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7106GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7107GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7108GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7109GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7110GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7111GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7112GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7113GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7114GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7115GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7116GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7117GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7118
7119GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7120GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7121GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7122GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7123GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7124GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7125
7126GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7127GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7128GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7129GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7130GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7131GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7132GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7133GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7134GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7135GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7136GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7137GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7138
7139GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7140GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7141GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7142GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7143GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7144
7145GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7146GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7147GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7148GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7149GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7150GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7151GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7152GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7153GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7154GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7155GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7156GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7157
7158GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7159GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7160GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7161GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7162GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7163#endif
7164
7165/*** SPE floating-point extension ***/
1c97856d
AJ		 7166#if defined(TARGET_PPC64)
7167#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7168static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7169{ \
1c97856d
AJ		 7170 TCGv_i32 t0; \
7171 TCGv t1; \
7172 t0 = tcg_temp_new_i32(); \
7173 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7174 gen_helper_##name(t0, t0); \
7175 t1 = tcg_temp_new(); \
7176 tcg_gen_extu_i32_tl(t1, t0); \
7177 tcg_temp_free_i32(t0); \
7178 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7179 0xFFFFFFFF00000000ULL); \
7180 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7181 tcg_temp_free(t1); \
0487d6a8 7182}
1c97856d
AJ		 7183#define GEN_SPEFPUOP_CONV_32_64(name) \
7184static always_inline void gen_##name (DisasContext *ctx) \
7185{ \
7186 TCGv_i32 t0; \
7187 TCGv t1; \
7188 t0 = tcg_temp_new_i32(); \
7189 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7190 t1 = tcg_temp_new(); \
7191 tcg_gen_extu_i32_tl(t1, t0); \
7192 tcg_temp_free_i32(t0); \
7193 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7194 0xFFFFFFFF00000000ULL); \
7195 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7196 tcg_temp_free(t1); \
7197}
7198#define GEN_SPEFPUOP_CONV_64_32(name) \
7199static always_inline void gen_##name (DisasContext *ctx) \
7200{ \
7201 TCGv_i32 t0 = tcg_temp_new_i32(); \
7202 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7203 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7204 tcg_temp_free_i32(t0); \
7205}
7206#define GEN_SPEFPUOP_CONV_64_64(name) \
7207static always_inline void gen_##name (DisasContext *ctx) \
7208{ \
7209 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7210}
7211#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7212static always_inline void gen_##name (DisasContext *ctx) \
7213{ \
1c97856d
AJ		 7214 TCGv_i32 t0, t1; \
7215 TCGv_i64 t2; \
57951c27 7216 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7217 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7218 return; \
7219 } \
1c97856d
AJ		 7220 t0 = tcg_temp_new_i32(); \
7221 t1 = tcg_temp_new_i32(); \
7222 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7223 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7224 gen_helper_##name(t0, t0, t1); \
7225 tcg_temp_free_i32(t1); \
7226 t2 = tcg_temp_new(); \
7227 tcg_gen_extu_i32_tl(t2, t0); \
7228 tcg_temp_free_i32(t0); \
7229 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7230 0xFFFFFFFF00000000ULL); \
7231 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7232 tcg_temp_free(t2); \
57951c27 7233}
1c97856d 7234#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7235static always_inline void gen_##name (DisasContext *ctx) \
7236{ \
7237 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7238 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7239 return; \
7240 } \
1c97856d
AJ		 7241 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7242 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7243}
1c97856d 7244#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7245static always_inline void gen_##name (DisasContext *ctx) \
7246{ \
1c97856d 7247 TCGv_i32 t0, t1; \
57951c27 7248 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7249 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7250 return; \
7251 } \
1c97856d
AJ		 7252 t0 = tcg_temp_new_i32(); \
7253 t1 = tcg_temp_new_i32(); \
7254 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7255 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7256 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7257 tcg_temp_free_i32(t0); \
7258 tcg_temp_free_i32(t1); \
7259}
7260#define GEN_SPEFPUOP_COMP_64(name) \
7261static always_inline void gen_##name (DisasContext *ctx) \
7262{ \
7263 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7264 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7265 return; \
7266 } \
7267 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7268 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7269}
7270#else
7271#define GEN_SPEFPUOP_CONV_32_32(name) \
7272static always_inline void gen_##name (DisasContext *ctx) \
7273{ \
7274 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7275}
1c97856d
AJ		 7276#define GEN_SPEFPUOP_CONV_32_64(name) \
7277static always_inline void gen_##name (DisasContext *ctx) \
7278{ \
7279 TCGv_i64 t0 = tcg_temp_new_i64(); \
7280 gen_load_gpr64(t0, rB(ctx->opcode)); \
7281 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7282 tcg_temp_free_i64(t0); \
7283}
7284#define GEN_SPEFPUOP_CONV_64_32(name) \
7285static always_inline void gen_##name (DisasContext *ctx) \
7286{ \
7287 TCGv_i64 t0 = tcg_temp_new_i64(); \
7288 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7289 gen_store_gpr64(rD(ctx->opcode), t0); \
7290 tcg_temp_free_i64(t0); \
7291}
7292#define GEN_SPEFPUOP_CONV_64_64(name) \
7293static always_inline void gen_##name (DisasContext *ctx) \
7294{ \
7295 TCGv_i64 t0 = tcg_temp_new_i64(); \
7296 gen_load_gpr64(t0, rB(ctx->opcode)); \
7297 gen_helper_##name(t0, t0); \
7298 gen_store_gpr64(rD(ctx->opcode), t0); \
7299 tcg_temp_free_i64(t0); \
7300}
7301#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7302static always_inline void gen_##name (DisasContext *ctx) \
7303{ \
7304 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7305 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7306 return; \
7307 } \
7308 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7309 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7310}
7311#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7312static always_inline void gen_##name (DisasContext *ctx) \
7313{ \
7314 TCGv_i64 t0, t1; \
7315 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7316 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7317 return; \
7318 } \
7319 t0 = tcg_temp_new_i64(); \
7320 t1 = tcg_temp_new_i64(); \
7321 gen_load_gpr64(t0, rA(ctx->opcode)); \
7322 gen_load_gpr64(t1, rB(ctx->opcode)); \
7323 gen_helper_##name(t0, t0, t1); \
7324 gen_store_gpr64(rD(ctx->opcode), t0); \
7325 tcg_temp_free_i64(t0); \
7326 tcg_temp_free_i64(t1); \
7327}
7328#define GEN_SPEFPUOP_COMP_32(name) \
7329static always_inline void gen_##name (DisasContext *ctx) \
7330{ \
7331 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7332 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7333 return; \
7334 } \
7335 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7336 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7337}
7338#define GEN_SPEFPUOP_COMP_64(name) \
7339static always_inline void gen_##name (DisasContext *ctx) \
7340{ \
7341 TCGv_i64 t0, t1; \
7342 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7343 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7344 return; \
7345 } \
7346 t0 = tcg_temp_new_i64(); \
7347 t1 = tcg_temp_new_i64(); \
7348 gen_load_gpr64(t0, rA(ctx->opcode)); \
7349 gen_load_gpr64(t1, rB(ctx->opcode)); \
7350 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7351 tcg_temp_free_i64(t0); \
7352 tcg_temp_free_i64(t1); \
7353}
7354#endif
57951c27 7355
0487d6a8
JM		 7356/* Single precision floating-point vectors operations */
7357/* Arithmetic */
1c97856d
AJ		 7358GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7359GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7360GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7361GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7362static always_inline void gen_evfsabs (DisasContext *ctx)
7363{
7364 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7365 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7366 return;
7367 }
7368#if defined(TARGET_PPC64)
7369 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7370#else
7371 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7372 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7373#endif
7374}
7375static always_inline void gen_evfsnabs (DisasContext *ctx)
7376{
7377 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7378 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7379 return;
7380 }
7381#if defined(TARGET_PPC64)
7382 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7383#else
7384 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7385 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7386#endif
7387}
7388static always_inline void gen_evfsneg (DisasContext *ctx)
7389{
7390 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7391 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7392 return;
7393 }
7394#if defined(TARGET_PPC64)
7395 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7396#else
7397 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7398 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7399#endif
7400}
7401
0487d6a8 7402/* Conversion */
1c97856d
AJ		 7403GEN_SPEFPUOP_CONV_64_64(evfscfui);
7404GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7405GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7406GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7407GEN_SPEFPUOP_CONV_64_64(evfsctui);
7408GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7409GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7410GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7411GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7412GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7413
0487d6a8 7414/* Comparison */
1c97856d
AJ		 7415GEN_SPEFPUOP_COMP_64(evfscmpgt);
7416GEN_SPEFPUOP_COMP_64(evfscmplt);
7417GEN_SPEFPUOP_COMP_64(evfscmpeq);
7418GEN_SPEFPUOP_COMP_64(evfststgt);
7419GEN_SPEFPUOP_COMP_64(evfststlt);
7420GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7421
7422/* Opcodes definitions */
7423GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7424GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7425GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7426GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7427GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7428GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7429GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7430GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7431GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7432GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7433GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7434GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7435GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7436GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7437
7438/* Single precision floating-point operations */
7439/* Arithmetic */
1c97856d
AJ		 7440GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7441GEN_SPEFPUOP_ARITH2_32_32(efssub);
7442GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7443GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7444static always_inline void gen_efsabs (DisasContext *ctx)
7445{
7446 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7447 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7448 return;
7449 }
7450 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7451}
7452static always_inline void gen_efsnabs (DisasContext *ctx)
7453{
7454 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7455 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7456 return;
7457 }
7458 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7459}
7460static always_inline void gen_efsneg (DisasContext *ctx)
7461{
7462 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7463 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7464 return;
7465 }
7466 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7467}
7468
0487d6a8 7469/* Conversion */
1c97856d
AJ		 7470GEN_SPEFPUOP_CONV_32_32(efscfui);
7471GEN_SPEFPUOP_CONV_32_32(efscfsi);
7472GEN_SPEFPUOP_CONV_32_32(efscfuf);
7473GEN_SPEFPUOP_CONV_32_32(efscfsf);
7474GEN_SPEFPUOP_CONV_32_32(efsctui);
7475GEN_SPEFPUOP_CONV_32_32(efsctsi);
7476GEN_SPEFPUOP_CONV_32_32(efsctuf);
7477GEN_SPEFPUOP_CONV_32_32(efsctsf);
7478GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7479GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7480GEN_SPEFPUOP_CONV_32_64(efscfd);
7481
0487d6a8 7482/* Comparison */
1c97856d
AJ		 7483GEN_SPEFPUOP_COMP_32(efscmpgt);
7484GEN_SPEFPUOP_COMP_32(efscmplt);
7485GEN_SPEFPUOP_COMP_32(efscmpeq);
7486GEN_SPEFPUOP_COMP_32(efststgt);
7487GEN_SPEFPUOP_COMP_32(efststlt);
7488GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7489
7490/* Opcodes definitions */
05332d70 7491GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7492GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7493GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7494GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7495GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7496GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7497GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7498GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7499GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7500GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7501GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7502GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7503GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7504GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7505
7506/* Double precision floating-point operations */
7507/* Arithmetic */
1c97856d
AJ		 7508GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7509GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7510GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7511GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7512static always_inline void gen_efdabs (DisasContext *ctx)
7513{
7514 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7515 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7516 return;
7517 }
7518#if defined(TARGET_PPC64)
7519 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7520#else
7521 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7522#endif
7523}
7524static always_inline void gen_efdnabs (DisasContext *ctx)
7525{
7526 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7527 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7528 return;
7529 }
7530#if defined(TARGET_PPC64)
7531 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7532#else
7533 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7534#endif
7535}
7536static always_inline void gen_efdneg (DisasContext *ctx)
7537{
7538 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7539 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7540 return;
7541 }
7542#if defined(TARGET_PPC64)
7543 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7544#else
7545 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7546#endif
7547}
7548
0487d6a8 7549/* Conversion */
1c97856d
AJ		 7550GEN_SPEFPUOP_CONV_64_32(efdcfui);
7551GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7552GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7553GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7554GEN_SPEFPUOP_CONV_32_64(efdctui);
7555GEN_SPEFPUOP_CONV_32_64(efdctsi);
7556GEN_SPEFPUOP_CONV_32_64(efdctuf);
7557GEN_SPEFPUOP_CONV_32_64(efdctsf);
7558GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7559GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7560GEN_SPEFPUOP_CONV_64_32(efdcfs);
7561GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7562GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7563GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7564GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 7565
0487d6a8 7566/* Comparison */
1c97856d
AJ		 7567GEN_SPEFPUOP_COMP_64(efdcmpgt);
7568GEN_SPEFPUOP_COMP_64(efdcmplt);
7569GEN_SPEFPUOP_COMP_64(efdcmpeq);
7570GEN_SPEFPUOP_COMP_64(efdtstgt);
7571GEN_SPEFPUOP_COMP_64(efdtstlt);
7572GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 7573
7574/* Opcodes definitions */
7575GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7576GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7577GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7578GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7579GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7580GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7581GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7582GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7583GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7584GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7585GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7586GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7587GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7588GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7589GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7590GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 7591
79aceca5
FB		 7592/* End opcode list */
7593GEN_OPCODE_MARK(end);
7594
3fc6c082 7595#include "translate_init.c"
0411a972 7596#include "helper_regs.h"
79aceca5 7597
9a64fbe4 7598/*****************************************************************************/
3fc6c082 7599/* Misc PowerPC helpers */
36081602
JM		 7600void cpu_dump_state (CPUState *env, FILE *f,
7601 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7602 int flags)
79aceca5 7603{
3fc6c082
FB		 7604#define RGPL 4
7605#define RFPL 4
3fc6c082 7606
79aceca5
FB		 7607 int i;
7608
077fc206 7609 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 7610 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 7611 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7612 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 7613#if !defined(NO_TIMER_DUMP)
077fc206 7614 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 7615#if !defined(CONFIG_USER_ONLY)
7616 "DECR %08x"
7617#endif
7618 "\n",
077fc206 7619 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 7620#if !defined(CONFIG_USER_ONLY)
7621 , cpu_ppc_load_decr(env)
7622#endif
7623 );
077fc206 7624#endif
76a66253 7625 for (i = 0; i < 32; i++) {
3fc6c082
FB		 7626 if ((i & (RGPL - 1)) == 0)
7627 cpu_fprintf(f, "GPR%02d", i);
6b542af7 7628 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 7629 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 7630 cpu_fprintf(f, "\n");
76a66253 7631 }
3fc6c082 7632 cpu_fprintf(f, "CR ");
76a66253 7633 for (i = 0; i < 8; i++)
7fe48483
FB		 7634 cpu_fprintf(f, "%01x", env->crf[i]);
7635 cpu_fprintf(f, " [");
76a66253
JM		 7636 for (i = 0; i < 8; i++) {
7637 char a = '-';
7638 if (env->crf[i] & 0x08)
7639 a = 'L';
7640 else if (env->crf[i] & 0x04)
7641 a = 'G';
7642 else if (env->crf[i] & 0x02)
7643 a = 'E';
7fe48483 7644 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 7645 }
6b542af7 7646 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 7647 for (i = 0; i < 32; i++) {
7648 if ((i & (RFPL - 1)) == 0)
7649 cpu_fprintf(f, "FPR%02d", i);
26a76461 7650 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 7651 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 7652 cpu_fprintf(f, "\n");
79aceca5 7653 }
f2e63a42 7654#if !defined(CONFIG_USER_ONLY)
6b542af7 7655 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 7656 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 7657#endif
79aceca5 7658
3fc6c082
FB		 7659#undef RGPL
7660#undef RFPL
79aceca5
FB		 7661}
7662
76a66253
JM		 7663void cpu_dump_statistics (CPUState *env, FILE*f,
7664 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7665 int flags)
7666{
7667#if defined(DO_PPC_STATISTICS)
7668 opc_handler_t **t1, **t2, **t3, *handler;
7669 int op1, op2, op3;
7670
7671 t1 = env->opcodes;
7672 for (op1 = 0; op1 < 64; op1++) {
7673 handler = t1[op1];
7674 if (is_indirect_opcode(handler)) {
7675 t2 = ind_table(handler);
7676 for (op2 = 0; op2 < 32; op2++) {
7677 handler = t2[op2];
7678 if (is_indirect_opcode(handler)) {
7679 t3 = ind_table(handler);
7680 for (op3 = 0; op3 < 32; op3++) {
7681 handler = t3[op3];
7682 if (handler->count == 0)
7683 continue;
7684 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7685 "%016llx %lld\n",
7686 op1, op2, op3, op1, (op3 << 5) | op2,
7687 handler->oname,
7688 handler->count, handler->count);
7689 }
7690 } else {
7691 if (handler->count == 0)
7692 continue;
7693 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7694 "%016llx %lld\n",
7695 op1, op2, op1, op2, handler->oname,
7696 handler->count, handler->count);
7697 }
7698 }
7699 } else {
7700 if (handler->count == 0)
7701 continue;
7702 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7703 op1, op1, handler->oname,
7704 handler->count, handler->count);
7705 }
7706 }
7707#endif
7708}
7709
9a64fbe4 7710/*****************************************************************************/
2cfc5f17
TS		 7711static always_inline void gen_intermediate_code_internal (CPUState *env,
7712 TranslationBlock *tb,
7713 int search_pc)
79aceca5 7714{
9fddaa0c 7715 DisasContext ctx, *ctxp = &ctx;
79aceca5 7716 opc_handler_t **table, *handler;
0fa85d43 7717 target_ulong pc_start;
79aceca5 7718 uint16_t *gen_opc_end;
a1d1bb31 7719 CPUBreakpoint *bp;
79aceca5 7720 int j, lj = -1;
2e70f6ef
PB		 7721 int num_insns;
7722 int max_insns;
79aceca5
FB		 7723
7724 pc_start = tb->pc;
79aceca5 7725 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 7726#if defined(OPTIMIZE_FPRF_UPDATE)
7727 gen_fprf_ptr = gen_fprf_buf;
7728#endif
046d6672 7729 ctx.nip = pc_start;
79aceca5 7730 ctx.tb = tb;
e1833e1f 7731 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 7732 ctx.spr_cb = env->spr_cb;
76db3ba4
AJ		 7733 ctx.mem_idx = env->mmu_idx;
7734 ctx.access_type = -1;
7735 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 7736#if defined(TARGET_PPC64)
7737 ctx.sf_mode = msr_sf;
9a64fbe4 7738#endif
3cc62370 7739 ctx.fpu_enabled = msr_fp;
a9d9eb8f 7740 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 7741 ctx.spe_enabled = msr_spe;
7742 else
7743 ctx.spe_enabled = 0;
a9d9eb8f
JM		 7744 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7745 ctx.altivec_enabled = msr_vr;
7746 else
7747 ctx.altivec_enabled = 0;
d26bfc9a 7748 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 7749 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 7750 else
8cbcb4fa 7751 ctx.singlestep_enabled = 0;
d26bfc9a 7752 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 7753 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7754 if (unlikely(env->singlestep_enabled))
7755 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 7756#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 7757 /* Single step trace mode */
7758 msr_se = 1;
7759#endif
2e70f6ef
PB		 7760 num_insns = 0;
7761 max_insns = tb->cflags & CF_COUNT_MASK;
7762 if (max_insns == 0)
7763 max_insns = CF_COUNT_MASK;
7764
7765 gen_icount_start();
9a64fbe4 7766 /* Set env in case of segfault during code fetch */
e1833e1f 7767 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 7768 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7769 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 7770 if (bp->pc == ctx.nip) {
e06fcd75 7771 gen_debug_exception(ctxp);
ea4e754f
FB		 7772 break;
7773 }
7774 }
7775 }
76a66253 7776 if (unlikely(search_pc)) {
79aceca5
FB		 7777 j = gen_opc_ptr - gen_opc_buf;
7778 if (lj < j) {
7779 lj++;
7780 while (lj < j)
7781 gen_opc_instr_start[lj++] = 0;
046d6672 7782 gen_opc_pc[lj] = ctx.nip;
79aceca5 7783 gen_opc_instr_start[lj] = 1;
2e70f6ef 7784 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 7785 }
7786 }
9fddaa0c
FB		 7787#if defined PPC_DEBUG_DISAS
7788 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 7789 fprintf(logfile, "----------------\n");
1b9eb036 7790 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
76db3ba4 7791 ctx.nip, ctx.mem_idx, (int)msr_ir);
9a64fbe4
FB		 7792 }
7793#endif
2e70f6ef
PB		 7794 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7795 gen_io_start();
76db3ba4 7796 if (unlikely(ctx.le_mode)) {
056401ea
JM		 7797 ctx.opcode = bswap32(ldl_code(ctx.nip));
7798 } else {
7799 ctx.opcode = ldl_code(ctx.nip);
111bfab3 7800 }
9fddaa0c
FB		 7801#if defined PPC_DEBUG_DISAS
7802 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 7803 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 7804 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 7805 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 7806 }
7807#endif
046d6672 7808 ctx.nip += 4;
3fc6c082 7809 table = env->opcodes;
2e70f6ef 7810 num_insns++;
79aceca5
FB		 7811 handler = table[opc1(ctx.opcode)];
7812 if (is_indirect_opcode(handler)) {
7813 table = ind_table(handler);
7814 handler = table[opc2(ctx.opcode)];
7815 if (is_indirect_opcode(handler)) {
7816 table = ind_table(handler);
7817 handler = table[opc3(ctx.opcode)];
7818 }
7819 }
7820 /* Is opcode *REALLY* valid ? */
76a66253 7821 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7822 if (loglevel != 0) {
76a66253 7823 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 7824 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 7825 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7826 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7827 } else {
7828 printf("invalid/unsupported opcode: "
6b542af7 7829 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 7830 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7831 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7832 }
76a66253
JM		 7833 } else {
7834 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7835 if (loglevel != 0) {
79aceca5 7836 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 7837 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 7838 ctx.opcode & handler->inval, opc1(ctx.opcode),
7839 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7840 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7841 } else {
7842 printf("invalid bits: %08x for opcode: "
6b542af7 7843 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 7844 ctx.opcode & handler->inval, opc1(ctx.opcode),
7845 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7846 ctx.opcode, ctx.nip - 4);
76a66253 7847 }
e06fcd75 7848 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 7849 break;
79aceca5 7850 }
79aceca5 7851 }
4b3686fa 7852 (*(handler->handler))(&ctx);
76a66253
JM		 7853#if defined(DO_PPC_STATISTICS)
7854 handler->count++;
7855#endif
9a64fbe4 7856 /* Check trace mode exceptions */
8cbcb4fa
AJ		 7857 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7858 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7859 ctx.exception != POWERPC_SYSCALL &&
7860 ctx.exception != POWERPC_EXCP_TRAP &&
7861 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 7862 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 7863 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 7864 (env->singlestep_enabled) ||
7865 num_insns >= max_insns)) {
d26bfc9a
JM		 7866 /* if we reach a page boundary or are single stepping, stop
7867 * generation
7868 */
8dd4983c 7869 break;
76a66253 7870 }
3fc6c082
FB		 7871#if defined (DO_SINGLE_STEP)
7872 break;
7873#endif
7874 }
2e70f6ef
PB		 7875 if (tb->cflags & CF_LAST_IO)
7876 gen_io_end();
e1833e1f 7877 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7878 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7879 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa 7880 if (unlikely(env->singlestep_enabled)) {
e06fcd75 7881 gen_debug_exception(ctxp);
8cbcb4fa 7882 }
76a66253 7883 /* Generate the return instruction */
57fec1fe 7884 tcg_gen_exit_tb(0);
9a64fbe4 7885 }
2e70f6ef 7886 gen_icount_end(tb, num_insns);
79aceca5 7887 *gen_opc_ptr = INDEX_op_end;
76a66253 7888 if (unlikely(search_pc)) {
9a64fbe4
FB		 7889 j = gen_opc_ptr - gen_opc_buf;
7890 lj++;
7891 while (lj <= j)
7892 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7893 } else {
046d6672 7894 tb->size = ctx.nip - pc_start;
2e70f6ef 7895 tb->icount = num_insns;
9a64fbe4 7896 }
d9bce9d9 7897#if defined(DEBUG_DISAS)
9fddaa0c 7898 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7899 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7900 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7901 }
7902 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7903 int flags;
237c0af0 7904 flags = env->bfd_mach;
76db3ba4 7905 flags |= ctx.le_mode << 16;
0fa85d43 7906 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7907 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7908 fprintf(logfile, "\n");
9fddaa0c 7909 }
79aceca5 7910#endif
79aceca5
FB		 7911}
7912
2cfc5f17 7913void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 7914{
2cfc5f17 7915 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 7916}
7917
2cfc5f17 7918void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7919{
2cfc5f17 7920 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7921}
d2856f1a
AJ		 7922
7923void gen_pc_load(CPUState *env, TranslationBlock *tb,
7924 unsigned long searched_pc, int pc_pos, void *puc)
7925{
d2856f1a 7926 env->nip = gen_opc_pc[pc_pos];
d2856f1a 7927}
Qemu copy for testing