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Always make PowerPC hypervisor mode memory accesses and instructions
[qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5
FB		 28#include "disas.h"
29
a750fc0b 30/* Include definitions for instructions classes and implementations flags */
79aceca5 31//#define DO_SINGLE_STEP
9fddaa0c 32//#define PPC_DEBUG_DISAS
a496775f 33//#define DEBUG_MEMORY_ACCESSES
76a66253 34//#define DO_PPC_STATISTICS
7c58044c 35//#define OPTIMIZE_FPRF_UPDATE
79aceca5 36
a750fc0b
JM		 37/*****************************************************************************/
38/* Code translation helpers */
d9bce9d9 39#if defined(USE_DIRECT_JUMP)
c53be334
FB		 40#define TBPARAM(x)
41#else
42#define TBPARAM(x) (long)(x)
43#endif
44
79aceca5
FB		 45enum {
46#define DEF(s, n, copy_size) INDEX_op_ ## s,
47#include "opc.h"
48#undef DEF
49 NB_OPS,
50};
51
52static uint16_t *gen_opc_ptr;
53static uint32_t *gen_opparam_ptr;
7c58044c
JM		 54#if defined(OPTIMIZE_FPRF_UPDATE)
55static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
56static uint16_t **gen_fprf_ptr;
57#endif
79aceca5
FB		 58
59#include "gen-op.h"
28b6751f 60
b068d6a7 61static always_inline void gen_set_T0 (target_ulong val)
d9bce9d9
JM		 62{
63#if defined(TARGET_PPC64)
64 if (val >> 32)
65 gen_op_set_T0_64(val >> 32, val);
66 else
67#endif
68 gen_op_set_T0(val);
69}
70
b068d6a7 71static always_inline void gen_set_T1 (target_ulong val)
d9bce9d9
JM		 72{
73#if defined(TARGET_PPC64)
74 if (val >> 32)
75 gen_op_set_T1_64(val >> 32, val);
76 else
77#endif
78 gen_op_set_T1(val);
79}
80
81#define GEN8(func, NAME) \
9a64fbe4
FB		 82static GenOpFunc *NAME ## _table [8] = { \
83NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
84NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
85}; \
b068d6a7 86static always_inline void func (int n) \
9a64fbe4
FB		 87{ \
88 NAME ## _table[n](); \
89}
90
91#define GEN16(func, NAME) \
92static GenOpFunc *NAME ## _table [16] = { \
93NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
94NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
95NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
96NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
97}; \
b068d6a7 98static always_inline void func (int n) \
9a64fbe4
FB		 99{ \
100 NAME ## _table[n](); \
28b6751f
FB		 101}
102
d9bce9d9 103#define GEN32(func, NAME) \
9a64fbe4
FB		 104static GenOpFunc *NAME ## _table [32] = { \
105NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
106NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
107NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
108NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
109NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
110NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
111NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
112NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
113}; \
b068d6a7 114static always_inline void func (int n) \
9a64fbe4
FB		 115{ \
116 NAME ## _table[n](); \
117}
118
119/* Condition register moves */
120GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
121GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
122GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
fc0d441e 123#if 0 // Unused
9a64fbe4 124GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
fc0d441e 125#endif
28b6751f 126
9a64fbe4
FB		 127/* General purpose registers moves */
128GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
129GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
130GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
131
132GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
133GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
76a66253 134#if 0 // unused
9a64fbe4 135GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
76a66253 136#endif
28b6751f 137
fb0eaffc
FB		 138/* floating point registers moves */
139GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
140GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
141GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
142GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
143GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
76a66253 144#if 0 // unused
fb0eaffc 145GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
76a66253 146#endif
79aceca5
FB		 147
148/* internal defines */
149typedef struct DisasContext {
150 struct TranslationBlock *tb;
0fa85d43 151 target_ulong nip;
79aceca5 152 uint32_t opcode;
9a64fbe4 153 uint32_t exception;
3cc62370
FB		 154 /* Routine used to access memory */
155 int mem_idx;
156 /* Translation flags */
9a64fbe4 157#if !defined(CONFIG_USER_ONLY)
79aceca5 158 int supervisor;
d9bce9d9
JM		 159#endif
160#if defined(TARGET_PPC64)
161 int sf_mode;
9a64fbe4 162#endif
3cc62370 163 int fpu_enabled;
a9d9eb8f 164 int altivec_enabled;
0487d6a8 165 int spe_enabled;
3fc6c082 166 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 167 int singlestep_enabled;
d63001d1 168 int dcache_line_size;
79aceca5
FB		 169} DisasContext;
170
3fc6c082 171struct opc_handler_t {
79aceca5
FB		 172 /* invalid bits */
173 uint32_t inval;
9a64fbe4 174 /* instruction type */
0487d6a8 175 uint64_t type;
79aceca5
FB		 176 /* handler */
177 void (*handler)(DisasContext *ctx);
a750fc0b 178#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
76a66253 179 const unsigned char *oname;
a750fc0b
JM		 180#endif
181#if defined(DO_PPC_STATISTICS)
76a66253
JM		 182 uint64_t count;
183#endif
3fc6c082 184};
79aceca5 185
b068d6a7 186static always_inline void gen_set_Rc0 (DisasContext *ctx)
76a66253 187{
d9bce9d9
JM		 188#if defined(TARGET_PPC64)
189 if (ctx->sf_mode)
190 gen_op_cmpi_64(0);
191 else
192#endif
193 gen_op_cmpi(0);
76a66253
JM		 194 gen_op_set_Rc0();
195}
196
7c58044c
JM		 197static always_inline void gen_reset_fpstatus (void)
198{
199#ifdef CONFIG_SOFTFLOAT
200 gen_op_reset_fpstatus();
201#endif
202}
203
204static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
205{
206 if (set_fprf != 0) {
207 /* This case might be optimized later */
208#if defined(OPTIMIZE_FPRF_UPDATE)
209 *gen_fprf_ptr++ = gen_opc_ptr;
210#endif
211 gen_op_compute_fprf(1);
212 if (unlikely(set_rc))
213 gen_op_store_T0_crf(1);
214 gen_op_float_check_status();
215 } else if (unlikely(set_rc)) {
216 /* We always need to compute fpcc */
217 gen_op_compute_fprf(0);
218 gen_op_store_T0_crf(1);
219 if (set_fprf)
220 gen_op_float_check_status();
221 }
222}
223
224static always_inline void gen_optimize_fprf (void)
225{
226#if defined(OPTIMIZE_FPRF_UPDATE)
227 uint16_t **ptr;
228
229 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
230 *ptr = INDEX_op_nop1;
231 gen_fprf_ptr = gen_fprf_buf;
232#endif
233}
234
b068d6a7 235static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 236{
237#if defined(TARGET_PPC64)
238 if (ctx->sf_mode)
239 gen_op_update_nip_64(nip >> 32, nip);
240 else
241#endif
242 gen_op_update_nip(nip);
243}
244
e1833e1f 245#define GEN_EXCP(ctx, excp, error) \
79aceca5 246do { \
e1833e1f 247 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 248 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 249 } \
250 gen_op_raise_exception_err((excp), (error)); \
251 ctx->exception = (excp); \
79aceca5
FB		 252} while (0)
253
e1833e1f
JM		 254#define GEN_EXCP_INVAL(ctx) \
255GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
256 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 257
e1833e1f
JM		 258#define GEN_EXCP_PRIVOPC(ctx) \
259GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
260 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 261
e1833e1f
JM		 262#define GEN_EXCP_PRIVREG(ctx) \
263GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
264 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
265
266#define GEN_EXCP_NO_FP(ctx) \
267GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
268
269#define GEN_EXCP_NO_AP(ctx) \
270GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 271
a9d9eb8f
JM		 272#define GEN_EXCP_NO_VR(ctx) \
273GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
274
f24e5695 275/* Stop translation */
b068d6a7 276static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 277{
d9bce9d9 278 gen_update_nip(ctx, ctx->nip);
e1833e1f 279 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 280}
281
f24e5695 282/* No need to update nip here, as execution flow will change */
b068d6a7 283static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 284{
e1833e1f 285 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 286}
287
79aceca5
FB		 288#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
289static void gen_##name (DisasContext *ctx); \
290GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
291static void gen_##name (DisasContext *ctx)
292
c7697e1f
JM		 293#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
294static void gen_##name (DisasContext *ctx); \
295GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
296static void gen_##name (DisasContext *ctx)
297
79aceca5
FB		 298typedef struct opcode_t {
299 unsigned char opc1, opc2, opc3;
18fba28c
FB		 300#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
301 unsigned char pad[5];
302#else
303 unsigned char pad[1];
304#endif
79aceca5 305 opc_handler_t handler;
3fc6c082 306 const unsigned char *oname;
79aceca5
FB		 307} opcode_t;
308
a750fc0b 309/*****************************************************************************/
79aceca5
FB		 310/*** Instruction decoding ***/
311#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 312static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 313{ \
314 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
315}
316
317#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 318static always_inline int32_t name (uint32_t opcode) \
79aceca5 319{ \
18fba28c 320 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 321}
322
323/* Opcode part 1 */
324EXTRACT_HELPER(opc1, 26, 6);
325/* Opcode part 2 */
326EXTRACT_HELPER(opc2, 1, 5);
327/* Opcode part 3 */
328EXTRACT_HELPER(opc3, 6, 5);
329/* Update Cr0 flags */
330EXTRACT_HELPER(Rc, 0, 1);
331/* Destination */
332EXTRACT_HELPER(rD, 21, 5);
333/* Source */
334EXTRACT_HELPER(rS, 21, 5);
335/* First operand */
336EXTRACT_HELPER(rA, 16, 5);
337/* Second operand */
338EXTRACT_HELPER(rB, 11, 5);
339/* Third operand */
340EXTRACT_HELPER(rC, 6, 5);
341/*** Get CRn ***/
342EXTRACT_HELPER(crfD, 23, 3);
343EXTRACT_HELPER(crfS, 18, 3);
344EXTRACT_HELPER(crbD, 21, 5);
345EXTRACT_HELPER(crbA, 16, 5);
346EXTRACT_HELPER(crbB, 11, 5);
347/* SPR / TBL */
3fc6c082 348EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 349static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 350{
351 uint32_t sprn = _SPR(opcode);
352
353 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
354}
79aceca5
FB		 355/*** Get constants ***/
356EXTRACT_HELPER(IMM, 12, 8);
357/* 16 bits signed immediate value */
358EXTRACT_SHELPER(SIMM, 0, 16);
359/* 16 bits unsigned immediate value */
360EXTRACT_HELPER(UIMM, 0, 16);
361/* Bit count */
362EXTRACT_HELPER(NB, 11, 5);
363/* Shift count */
364EXTRACT_HELPER(SH, 11, 5);
365/* Mask start */
366EXTRACT_HELPER(MB, 6, 5);
367/* Mask end */
368EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 369/* Trap operand */
370EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 371
372EXTRACT_HELPER(CRM, 12, 8);
373EXTRACT_HELPER(FM, 17, 8);
374EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 375EXTRACT_HELPER(FPIMM, 20, 4);
376
79aceca5
FB		 377/*** Jump target decoding ***/
378/* Displacement */
379EXTRACT_SHELPER(d, 0, 16);
380/* Immediate address */
b068d6a7 381static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 382{
383 return (opcode >> 0) & 0x03FFFFFC;
384}
385
b068d6a7 386static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 387{
388 return (opcode >> 0) & 0xFFFC;
389}
390
391EXTRACT_HELPER(BO, 21, 5);
392EXTRACT_HELPER(BI, 16, 5);
393/* Absolute/relative address */
394EXTRACT_HELPER(AA, 1, 1);
395/* Link */
396EXTRACT_HELPER(LK, 0, 1);
397
398/* Create a mask between <start> and <end> bits */
b068d6a7 399static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 400{
76a66253 401 target_ulong ret;
79aceca5 402
76a66253
JM		 403#if defined(TARGET_PPC64)
404 if (likely(start == 0)) {
6f2d8978 405 ret = UINT64_MAX << (63 - end);
76a66253 406 } else if (likely(end == 63)) {
6f2d8978 407 ret = UINT64_MAX >> start;
76a66253
JM		 408 }
409#else
410 if (likely(start == 0)) {
6f2d8978 411 ret = UINT32_MAX << (31 - end);
76a66253 412 } else if (likely(end == 31)) {
6f2d8978 413 ret = UINT32_MAX >> start;
76a66253
JM		 414 }
415#endif
416 else {
417 ret = (((target_ulong)(-1ULL)) >> (start)) ^
418 (((target_ulong)(-1ULL) >> (end)) >> 1);
419 if (unlikely(start > end))
420 return ~ret;
421 }
79aceca5
FB		 422
423 return ret;
424}
425
a750fc0b
JM		 426/*****************************************************************************/
427/* PowerPC Instructions types definitions */
428enum {
1b413d55 429 PPC_NONE = 0x0000000000000000ULL,
12de9a39 430 /* PowerPC base instructions set */
1b413d55
JM		 431 PPC_INSNS_BASE = 0x0000000000000001ULL,
432 /* integer operations instructions */
a750fc0b 433#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 434 /* flow control instructions */
a750fc0b 435#define PPC_FLOW PPC_INSNS_BASE
1b413d55 436 /* virtual memory instructions */
a750fc0b 437#define PPC_MEM PPC_INSNS_BASE
1b413d55 438 /* ld/st with reservation instructions */
a750fc0b 439#define PPC_RES PPC_INSNS_BASE
1b413d55 440 /* spr/msr access instructions */
a750fc0b 441#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 442 /* Deprecated instruction sets */
443 /* Original POWER instruction set */
444 PPC_POWER = 0x0000000000000001ULL,
445 /* POWER2 instruction set extension */
446 PPC_POWER2 = 0x0000000000000002ULL,
447 /* Power RTC support */
448 PPC_POWER_RTC = 0x0000000000000004ULL,
449 /* Power-to-PowerPC bridge (601) */
450 PPC_POWER_BR = 0x0000000000000008ULL,
451 /* 64 bits PowerPC instruction set */
452 PPC_64B = 0x0000000000000010ULL,
453 /* New 64 bits extensions (PowerPC 2.0x) */
454 PPC_64BX = 0x0000000000000020ULL,
455 /* 64 bits hypervisor extensions */
456 PPC_64H = 0x0000000000000040ULL,
457 /* New wait instruction (PowerPC 2.0x) */
458 PPC_WAIT = 0x0000000000000080ULL,
459 /* Time base mftb instruction */
460 PPC_MFTB = 0x0000000000000100ULL,
461
462 /* Fixed-point unit extensions */
463 /* PowerPC 602 specific */
464 PPC_602_SPEC = 0x0000000000000200ULL,
465 /* PowerPC 2.03 specification extensions */
466 PPC_203 = 0x0000000000000400ULL,
467
468 /* Floating-point unit extensions */
469 /* Optional floating point instructions */
470 PPC_FLOAT = 0x0000000000010000ULL,
471 /* New floating-point extensions (PowerPC 2.0x) */
472 PPC_FLOAT_EXT = 0x0000000000020000ULL,
473 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
474 PPC_FLOAT_FRES = 0x0000000000080000ULL,
475 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
476 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
477 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
478 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
479
480 /* Vector/SIMD extensions */
481 /* Altivec support */
482 PPC_ALTIVEC = 0x0000000001000000ULL,
483 /* e500 vector instructions */
484 PPC_E500_VECTOR = 0x0000000002000000ULL,
485 /* PowerPC 2.03 SPE extension */
486 PPC_SPE = 0x0000000004000000ULL,
487 /* PowerPC 2.03 SPE floating-point extension */
488 PPC_SPEFPU = 0x0000000008000000ULL,
489
12de9a39 490 /* Optional memory control instructions */
1b413d55
JM		 491 PPC_MEM_TLBIA = 0x0000000010000000ULL,
492 PPC_MEM_TLBIE = 0x0000000020000000ULL,
493 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
494 /* sync instruction */
495 PPC_MEM_SYNC = 0x0000000080000000ULL,
496 /* eieio instruction */
497 PPC_MEM_EIEIO = 0x0000000100000000ULL,
498
499 /* Cache control instructions */
500 PPC_CACHE = 0x0000001000000000ULL,
501 /* icbi instruction */
502 PPC_CACHE_ICBI = 0x0000002000000000ULL,
503 /* dcbz instruction with fixed cache line size */
504 PPC_CACHE_DCBZ = 0x0000004000000000ULL,
505 /* dcbz instruction with tunable cache line size */
506 PPC_CACHE_DCBZT = 0x0000008000000000ULL,
507 /* dcba instruction */
508 PPC_CACHE_DCBA = 0x0000010000000000ULL,
509
510 /* MMU related extensions */
511 /* external control instructions */
512 PPC_EXTERN = 0x0000100000000000ULL,
513 /* segment register access instructions */
514 PPC_SEGMENT = 0x0000200000000000ULL,
515 /* PowerPC 6xx TLB management instructions */
516 PPC_6xx_TLB = 0x0000400000000000ULL,
517 /* PowerPC 74xx TLB management instructions */
518 PPC_74xx_TLB = 0x0000800000000000ULL,
519 /* PowerPC 40x TLB management instructions */
520 PPC_40x_TLB = 0x0001000000000000ULL,
521 /* segment register access instructions for PowerPC 64 "bridge" */
522 PPC_SEGMENT_64B = 0x0002000000000000ULL,
523 /* SLB management */
524 PPC_SLBI = 0x0004000000000000ULL,
525
12de9a39 526 /* Embedded PowerPC dedicated instructions */
1b413d55 527 PPC_EMB_COMMON = 0x0010000000000000ULL,
12de9a39 528 /* PowerPC 40x exception model */
1b413d55 529 PPC_40x_EXCP = 0x0020000000000000ULL,
12de9a39 530 /* PowerPC 405 Mac instructions */
1b413d55 531 PPC_405_MAC = 0x0040000000000000ULL,
12de9a39 532 /* PowerPC 440 specific instructions */
1b413d55 533 PPC_440_SPEC = 0x0080000000000000ULL,
12de9a39 534 /* BookE (embedded) PowerPC specification */
1b413d55
JM		 535 PPC_BOOKE = 0x0100000000000000ULL,
536 /* More BookE (embedded) instructions... */
537 PPC_BOOKE_EXT = 0x0200000000000000ULL,
12de9a39 538 /* PowerPC 4xx dedicated instructions */
1b413d55 539 PPC_4xx_COMMON = 0x0400000000000000ULL,
12de9a39 540 /* PowerPC 40x ibct instructions */
1b413d55 541 PPC_40x_ICBT = 0x0800000000000000ULL,
12de9a39 542 /* rfmci is not implemented in all BookE PowerPC */
1b413d55 543 PPC_RFMCI = 0x1000000000000000ULL,
12de9a39 544 /* user-mode DCR access, implemented in PowerPC 460 */
1b413d55 545 PPC_DCRUX = 0x2000000000000000ULL,
a750fc0b
JM		 546};
547
548/*****************************************************************************/
549/* PowerPC instructions table */
3fc6c082
FB		 550#if HOST_LONG_BITS == 64
551#define OPC_ALIGN 8
552#else
553#define OPC_ALIGN 4
554#endif
1b039c09 555#if defined(__APPLE__)
d9bce9d9 556#define OPCODES_SECTION \
3fc6c082 557 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 558#else
d9bce9d9 559#define OPCODES_SECTION \
3fc6c082 560 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 561#endif
562
76a66253 563#if defined(DO_PPC_STATISTICS)
79aceca5 564#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 565OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 566 .opc1 = op1, \
567 .opc2 = op2, \
568 .opc3 = op3, \
18fba28c 569 .pad = { 0, }, \
79aceca5
FB		 570 .handler = { \
571 .inval = invl, \
9a64fbe4 572 .type = _typ, \
79aceca5 573 .handler = &gen_##name, \
76a66253 574 .oname = stringify(name), \
79aceca5 575 }, \
3fc6c082 576 .oname = stringify(name), \
79aceca5 577}
c7697e1f
JM		 578#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
579OPCODES_SECTION opcode_t opc_##name = { \
580 .opc1 = op1, \
581 .opc2 = op2, \
582 .opc3 = op3, \
583 .pad = { 0, }, \
584 .handler = { \
585 .inval = invl, \
586 .type = _typ, \
587 .handler = &gen_##name, \
588 .oname = onam, \
589 }, \
590 .oname = onam, \
591}
76a66253
JM		 592#else
593#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
594OPCODES_SECTION opcode_t opc_##name = { \
595 .opc1 = op1, \
596 .opc2 = op2, \
597 .opc3 = op3, \
598 .pad = { 0, }, \
599 .handler = { \
600 .inval = invl, \
601 .type = _typ, \
602 .handler = &gen_##name, \
603 }, \
604 .oname = stringify(name), \
605}
c7697e1f
JM		 606#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
607OPCODES_SECTION opcode_t opc_##name = { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .pad = { 0, }, \
612 .handler = { \
613 .inval = invl, \
614 .type = _typ, \
615 .handler = &gen_##name, \
616 }, \
617 .oname = onam, \
618}
76a66253 619#endif
79aceca5
FB		 620
621#define GEN_OPCODE_MARK(name) \
18fba28c 622OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 623 .opc1 = 0xFF, \
624 .opc2 = 0xFF, \
625 .opc3 = 0xFF, \
18fba28c 626 .pad = { 0, }, \
79aceca5
FB		 627 .handler = { \
628 .inval = 0x00000000, \
9a64fbe4 629 .type = 0x00, \
79aceca5
FB		 630 .handler = NULL, \
631 }, \
3fc6c082 632 .oname = stringify(name), \
79aceca5
FB		 633}
634
635/* Start opcode list */
636GEN_OPCODE_MARK(start);
637
638/* Invalid instruction */
9a64fbe4
FB		 639GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
640{
e1833e1f 641 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 642}
643
79aceca5
FB		 644static opc_handler_t invalid_handler = {
645 .inval = 0xFFFFFFFF,
9a64fbe4 646 .type = PPC_NONE,
79aceca5
FB		 647 .handler = gen_invalid,
648};
649
650/*** Integer arithmetic ***/
d9bce9d9
JM		 651#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
652GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5
FB		 653{ \
654 gen_op_load_gpr_T0(rA(ctx->opcode)); \
655 gen_op_load_gpr_T1(rB(ctx->opcode)); \
656 gen_op_##name(); \
79aceca5 657 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 658 if (unlikely(Rc(ctx->opcode) != 0)) \
659 gen_set_Rc0(ctx); \
79aceca5
FB		 660}
661
d9bce9d9
JM		 662#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
663GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5
FB		 664{ \
665 gen_op_load_gpr_T0(rA(ctx->opcode)); \
666 gen_op_load_gpr_T1(rB(ctx->opcode)); \
667 gen_op_##name(); \
79aceca5 668 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 669 if (unlikely(Rc(ctx->opcode) != 0)) \
670 gen_set_Rc0(ctx); \
79aceca5
FB		 671}
672
d9bce9d9
JM		 673#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
674GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5
FB		 675{ \
676 gen_op_load_gpr_T0(rA(ctx->opcode)); \
677 gen_op_##name(); \
79aceca5 678 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 679 if (unlikely(Rc(ctx->opcode) != 0)) \
680 gen_set_Rc0(ctx); \
79aceca5 681}
d9bce9d9
JM		 682#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
683GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5
FB		 684{ \
685 gen_op_load_gpr_T0(rA(ctx->opcode)); \
686 gen_op_##name(); \
79aceca5 687 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 688 if (unlikely(Rc(ctx->opcode) != 0)) \
689 gen_set_Rc0(ctx); \
79aceca5
FB		 690}
691
692/* Two operands arithmetic functions */
d9bce9d9
JM		 693#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
694__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
695__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
696
697/* Two operands arithmetic functions with no overflow allowed */
698#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
699__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
700
701/* One operand arithmetic functions */
702#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
703__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
704__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
705
706#if defined(TARGET_PPC64)
707#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
708GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
709{ \
710 gen_op_load_gpr_T0(rA(ctx->opcode)); \
711 gen_op_load_gpr_T1(rB(ctx->opcode)); \
712 if (ctx->sf_mode) \
713 gen_op_##name##_64(); \
714 else \
715 gen_op_##name(); \
716 gen_op_store_T0_gpr(rD(ctx->opcode)); \
717 if (unlikely(Rc(ctx->opcode) != 0)) \
718 gen_set_Rc0(ctx); \
719}
720
721#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
722GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
723{ \
724 gen_op_load_gpr_T0(rA(ctx->opcode)); \
725 gen_op_load_gpr_T1(rB(ctx->opcode)); \
726 if (ctx->sf_mode) \
727 gen_op_##name##_64(); \
728 else \
729 gen_op_##name(); \
730 gen_op_store_T0_gpr(rD(ctx->opcode)); \
731 if (unlikely(Rc(ctx->opcode) != 0)) \
732 gen_set_Rc0(ctx); \
733}
734
735#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
736GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
737{ \
738 gen_op_load_gpr_T0(rA(ctx->opcode)); \
739 if (ctx->sf_mode) \
740 gen_op_##name##_64(); \
741 else \
742 gen_op_##name(); \
743 gen_op_store_T0_gpr(rD(ctx->opcode)); \
744 if (unlikely(Rc(ctx->opcode) != 0)) \
745 gen_set_Rc0(ctx); \
746}
747#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
748GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
749{ \
750 gen_op_load_gpr_T0(rA(ctx->opcode)); \
751 if (ctx->sf_mode) \
752 gen_op_##name##_64(); \
753 else \
754 gen_op_##name(); \
755 gen_op_store_T0_gpr(rD(ctx->opcode)); \
756 if (unlikely(Rc(ctx->opcode) != 0)) \
757 gen_set_Rc0(ctx); \
758}
759
760/* Two operands arithmetic functions */
761#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
762__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
763__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 764
765/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 766#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
767__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 768
769/* One operand arithmetic functions */
d9bce9d9
JM		 770#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
771__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
772__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
773#else
774#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
775#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
776#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
777#endif
79aceca5
FB		 778
779/* add add. addo addo. */
b068d6a7 780static always_inline void gen_op_addo (void)
d9bce9d9
JM		 781{
782 gen_op_move_T2_T0();
783 gen_op_add();
784 gen_op_check_addo();
785}
786#if defined(TARGET_PPC64)
787#define gen_op_add_64 gen_op_add
b068d6a7 788static always_inline void gen_op_addo_64 (void)
d9bce9d9
JM		 789{
790 gen_op_move_T2_T0();
791 gen_op_add();
792 gen_op_check_addo_64();
793}
794#endif
795GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 796/* addc addc. addco addco. */
b068d6a7 797static always_inline void gen_op_addc (void)
d9bce9d9
JM		 798{
799 gen_op_move_T2_T0();
800 gen_op_add();
801 gen_op_check_addc();
802}
b068d6a7 803static always_inline void gen_op_addco (void)
d9bce9d9
JM		 804{
805 gen_op_move_T2_T0();
806 gen_op_add();
807 gen_op_check_addc();
808 gen_op_check_addo();
809}
810#if defined(TARGET_PPC64)
b068d6a7 811static always_inline void gen_op_addc_64 (void)
d9bce9d9
JM		 812{
813 gen_op_move_T2_T0();
814 gen_op_add();
815 gen_op_check_addc_64();
816}
b068d6a7 817static always_inline void gen_op_addco_64 (void)
d9bce9d9
JM		 818{
819 gen_op_move_T2_T0();
820 gen_op_add();
821 gen_op_check_addc_64();
822 gen_op_check_addo_64();
823}
824#endif
825GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 826/* adde adde. addeo addeo. */
b068d6a7 827static always_inline void gen_op_addeo (void)
d9bce9d9
JM		 828{
829 gen_op_move_T2_T0();
830 gen_op_adde();
831 gen_op_check_addo();
832}
833#if defined(TARGET_PPC64)
b068d6a7 834static always_inline void gen_op_addeo_64 (void)
d9bce9d9
JM		 835{
836 gen_op_move_T2_T0();
837 gen_op_adde_64();
838 gen_op_check_addo_64();
839}
840#endif
841GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 842/* addme addme. addmeo addmeo. */
b068d6a7 843static always_inline void gen_op_addme (void)
d9bce9d9
JM		 844{
845 gen_op_move_T1_T0();
846 gen_op_add_me();
847}
848#if defined(TARGET_PPC64)
b068d6a7 849static always_inline void gen_op_addme_64 (void)
d9bce9d9
JM		 850{
851 gen_op_move_T1_T0();
852 gen_op_add_me_64();
853}
854#endif
855GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 856/* addze addze. addzeo addzeo. */
b068d6a7 857static always_inline void gen_op_addze (void)
d9bce9d9
JM		 858{
859 gen_op_move_T2_T0();
860 gen_op_add_ze();
861 gen_op_check_addc();
862}
b068d6a7 863static always_inline void gen_op_addzeo (void)
d9bce9d9
JM		 864{
865 gen_op_move_T2_T0();
866 gen_op_add_ze();
867 gen_op_check_addc();
868 gen_op_check_addo();
869}
870#if defined(TARGET_PPC64)
b068d6a7 871static always_inline void gen_op_addze_64 (void)
d9bce9d9
JM		 872{
873 gen_op_move_T2_T0();
874 gen_op_add_ze();
875 gen_op_check_addc_64();
876}
b068d6a7 877static always_inline void gen_op_addzeo_64 (void)
d9bce9d9
JM		 878{
879 gen_op_move_T2_T0();
880 gen_op_add_ze();
881 gen_op_check_addc_64();
882 gen_op_check_addo_64();
883}
884#endif
885GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 886/* divw divw. divwo divwo. */
d9bce9d9 887GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 888/* divwu divwu. divwuo divwuo. */
d9bce9d9 889GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 890/* mulhw mulhw. */
d9bce9d9 891GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 892/* mulhwu mulhwu. */
d9bce9d9 893GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 894/* mullw mullw. mullwo mullwo. */
d9bce9d9 895GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 896/* neg neg. nego nego. */
d9bce9d9 897GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 898/* subf subf. subfo subfo. */
b068d6a7 899static always_inline void gen_op_subfo (void)
d9bce9d9 900{
c3e10c7b 901 gen_op_moven_T2_T0();
d9bce9d9 902 gen_op_subf();
c3e10c7b 903 gen_op_check_addo();
d9bce9d9
JM		 904}
905#if defined(TARGET_PPC64)
906#define gen_op_subf_64 gen_op_subf
b068d6a7 907static always_inline void gen_op_subfo_64 (void)
d9bce9d9 908{
c3e10c7b 909 gen_op_moven_T2_T0();
d9bce9d9 910 gen_op_subf();
c3e10c7b 911 gen_op_check_addo_64();
d9bce9d9
JM		 912}
913#endif
914GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 915/* subfc subfc. subfco subfco. */
b068d6a7 916static always_inline void gen_op_subfc (void)
d9bce9d9
JM		 917{
918 gen_op_subf();
919 gen_op_check_subfc();
920}
b068d6a7 921static always_inline void gen_op_subfco (void)
d9bce9d9 922{
c3e10c7b 923 gen_op_moven_T2_T0();
d9bce9d9
JM		 924 gen_op_subf();
925 gen_op_check_subfc();
c3e10c7b 926 gen_op_check_addo();
d9bce9d9
JM		 927}
928#if defined(TARGET_PPC64)
b068d6a7 929static always_inline void gen_op_subfc_64 (void)
d9bce9d9
JM		 930{
931 gen_op_subf();
932 gen_op_check_subfc_64();
933}
b068d6a7 934static always_inline void gen_op_subfco_64 (void)
d9bce9d9 935{
c3e10c7b 936 gen_op_moven_T2_T0();
d9bce9d9
JM		 937 gen_op_subf();
938 gen_op_check_subfc_64();
c3e10c7b 939 gen_op_check_addo_64();
d9bce9d9
JM		 940}
941#endif
942GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 943/* subfe subfe. subfeo subfeo. */
b068d6a7 944static always_inline void gen_op_subfeo (void)
d9bce9d9 945{
c3e10c7b 946 gen_op_moven_T2_T0();
d9bce9d9 947 gen_op_subfe();
c3e10c7b 948 gen_op_check_addo();
d9bce9d9
JM		 949}
950#if defined(TARGET_PPC64)
951#define gen_op_subfe_64 gen_op_subfe
b068d6a7 952static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 953{
c3e10c7b 954 gen_op_moven_T2_T0();
d9bce9d9 955 gen_op_subfe_64();
c3e10c7b 956 gen_op_check_addo_64();
d9bce9d9
JM		 957}
958#endif
959GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 960/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 961GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 962/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 963GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 964/* addi */
965GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
966{
76a66253 967 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 968
969 if (rA(ctx->opcode) == 0) {
76a66253 970 /* li case */
d9bce9d9 971 gen_set_T0(simm);
79aceca5
FB		 972 } else {
973 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 974 if (likely(simm != 0))
975 gen_op_addi(simm);
79aceca5
FB		 976 }
977 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 978}
979/* addic */
980GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
981{
76a66253
JM		 982 target_long simm = SIMM(ctx->opcode);
983
79aceca5 984 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 985 if (likely(simm != 0)) {
986 gen_op_move_T2_T0();
987 gen_op_addi(simm);
988#if defined(TARGET_PPC64)
989 if (ctx->sf_mode)
990 gen_op_check_addc_64();
991 else
992#endif
993 gen_op_check_addc();
e864cabd
JM		 994 } else {
995 gen_op_clear_xer_ca();
d9bce9d9 996 }
79aceca5 997 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 998}
999/* addic. */
c7697e1f 1000GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1001{
76a66253
JM		 1002 target_long simm = SIMM(ctx->opcode);
1003
79aceca5 1004 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 1005 if (likely(simm != 0)) {
1006 gen_op_move_T2_T0();
1007 gen_op_addi(simm);
1008#if defined(TARGET_PPC64)
1009 if (ctx->sf_mode)
1010 gen_op_check_addc_64();
1011 else
1012#endif
1013 gen_op_check_addc();
966439a6
JM		 1014 } else {
1015 gen_op_clear_xer_ca();
d9bce9d9 1016 }
79aceca5 1017 gen_op_store_T0_gpr(rD(ctx->opcode));
76a66253 1018 gen_set_Rc0(ctx);
79aceca5
FB		 1019}
1020/* addis */
1021GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1022{
76a66253 1023 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1024
1025 if (rA(ctx->opcode) == 0) {
76a66253 1026 /* lis case */
d9bce9d9 1027 gen_set_T0(simm << 16);
79aceca5
FB		 1028 } else {
1029 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 1030 if (likely(simm != 0))
1031 gen_op_addi(simm << 16);
79aceca5
FB		 1032 }
1033 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1034}
1035/* mulli */
1036GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1037{
1038 gen_op_load_gpr_T0(rA(ctx->opcode));
1039 gen_op_mulli(SIMM(ctx->opcode));
1040 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1041}
1042/* subfic */
1043GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1044{
1045 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 1046#if defined(TARGET_PPC64)
1047 if (ctx->sf_mode)
1048 gen_op_subfic_64(SIMM(ctx->opcode));
1049 else
1050#endif
1051 gen_op_subfic(SIMM(ctx->opcode));
79aceca5 1052 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1053}
1054
d9bce9d9
JM		 1055#if defined(TARGET_PPC64)
1056/* mulhd mulhd. */
a750fc0b 1057GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1058/* mulhdu mulhdu. */
a750fc0b 1059GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1060/* mulld mulld. mulldo mulldo. */
a750fc0b 1061GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1062/* divd divd. divdo divdo. */
a750fc0b 1063GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1064/* divdu divdu. divduo divduo. */
a750fc0b 1065GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1066#endif
1067
79aceca5 1068/*** Integer comparison ***/
d9bce9d9
JM		 1069#if defined(TARGET_PPC64)
1070#define GEN_CMP(name, opc, type) \
1071GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1072{ \
1073 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1074 gen_op_load_gpr_T1(rB(ctx->opcode)); \
e3878283 1075 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
d9bce9d9
JM		 1076 gen_op_##name##_64(); \
1077 else \
1078 gen_op_##name(); \
1079 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1080}
1081#else
1082#define GEN_CMP(name, opc, type) \
1083GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
79aceca5
FB		 1084{ \
1085 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1086 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1087 gen_op_##name(); \
1088 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5 1089}
d9bce9d9 1090#endif
79aceca5
FB		 1091
1092/* cmp */
d9bce9d9 1093GEN_CMP(cmp, 0x00, PPC_INTEGER);
79aceca5
FB		 1094/* cmpi */
1095GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1096{
1097 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9 1098#if defined(TARGET_PPC64)
e3878283 1099 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1100 gen_op_cmpi_64(SIMM(ctx->opcode));
1101 else
1102#endif
1103 gen_op_cmpi(SIMM(ctx->opcode));
79aceca5 1104 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1105}
1106/* cmpl */
d9bce9d9 1107GEN_CMP(cmpl, 0x01, PPC_INTEGER);
79aceca5
FB		 1108/* cmpli */
1109GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1110{
1111 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9 1112#if defined(TARGET_PPC64)
e3878283 1113 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1114 gen_op_cmpli_64(UIMM(ctx->opcode));
1115 else
1116#endif
1117 gen_op_cmpli(UIMM(ctx->opcode));
79aceca5 1118 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1119}
1120
d9bce9d9
JM		 1121/* isel (PowerPC 2.03 specification) */
1122GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1123{
1124 uint32_t bi = rC(ctx->opcode);
1125 uint32_t mask;
1126
1127 if (rA(ctx->opcode) == 0) {
1128 gen_set_T0(0);
1129 } else {
1130 gen_op_load_gpr_T1(rA(ctx->opcode));
1131 }
1132 gen_op_load_gpr_T2(rB(ctx->opcode));
1133 mask = 1 << (3 - (bi & 0x03));
1134 gen_op_load_crf_T0(bi >> 2);
1135 gen_op_test_true(mask);
1136 gen_op_isel();
1137 gen_op_store_T0_gpr(rD(ctx->opcode));
1138}
1139
79aceca5 1140/*** Integer logical ***/
d9bce9d9
JM		 1141#define __GEN_LOGICAL2(name, opc2, opc3, type) \
1142GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
79aceca5
FB		 1143{ \
1144 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1145 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1146 gen_op_##name(); \
79aceca5 1147 gen_op_store_T0_gpr(rA(ctx->opcode)); \
76a66253
JM		 1148 if (unlikely(Rc(ctx->opcode) != 0)) \
1149 gen_set_Rc0(ctx); \
79aceca5 1150}
d9bce9d9
JM		 1151#define GEN_LOGICAL2(name, opc, type) \
1152__GEN_LOGICAL2(name, 0x1C, opc, type)
79aceca5 1153
d9bce9d9
JM		 1154#define GEN_LOGICAL1(name, opc, type) \
1155GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5
FB		 1156{ \
1157 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1158 gen_op_##name(); \
79aceca5 1159 gen_op_store_T0_gpr(rA(ctx->opcode)); \
76a66253
JM		 1160 if (unlikely(Rc(ctx->opcode) != 0)) \
1161 gen_set_Rc0(ctx); \
79aceca5
FB		 1162}
1163
1164/* and & and. */
d9bce9d9 1165GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
79aceca5 1166/* andc & andc. */
d9bce9d9 1167GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
79aceca5 1168/* andi. */
c7697e1f 1169GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5
FB		 1170{
1171 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253 1172 gen_op_andi_T0(UIMM(ctx->opcode));
79aceca5 1173 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253 1174 gen_set_Rc0(ctx);
79aceca5
FB		 1175}
1176/* andis. */
c7697e1f 1177GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5
FB		 1178{
1179 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253 1180 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
79aceca5 1181 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253 1182 gen_set_Rc0(ctx);
79aceca5
FB		 1183}
1184
1185/* cntlzw */
d9bce9d9 1186GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
79aceca5 1187/* eqv & eqv. */
d9bce9d9 1188GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
79aceca5 1189/* extsb & extsb. */
d9bce9d9 1190GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
79aceca5 1191/* extsh & extsh. */
d9bce9d9 1192GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
79aceca5 1193/* nand & nand. */
d9bce9d9 1194GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
79aceca5 1195/* nor & nor. */
d9bce9d9 1196GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
9a64fbe4 1197
79aceca5 1198/* or & or. */
9a64fbe4
FB		 1199GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1200{
76a66253
JM		 1201 int rs, ra, rb;
1202
1203 rs = rS(ctx->opcode);
1204 ra = rA(ctx->opcode);
1205 rb = rB(ctx->opcode);
1206 /* Optimisation for mr. ri case */
1207 if (rs != ra || rs != rb) {
1208 gen_op_load_gpr_T0(rs);
1209 if (rs != rb) {
1210 gen_op_load_gpr_T1(rb);
1211 gen_op_or();
1212 }
1213 gen_op_store_T0_gpr(ra);
1214 if (unlikely(Rc(ctx->opcode) != 0))
1215 gen_set_Rc0(ctx);
1216 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1217 gen_op_load_gpr_T0(rs);
1218 gen_set_Rc0(ctx);
c80f84e3
JM		 1219#if defined(TARGET_PPC64)
1220 } else {
1221 switch (rs) {
1222 case 1:
1223 /* Set process priority to low */
1224 gen_op_store_pri(2);
1225 break;
1226 case 6:
1227 /* Set process priority to medium-low */
1228 gen_op_store_pri(3);
1229 break;
1230 case 2:
1231 /* Set process priority to normal */
1232 gen_op_store_pri(4);
1233 break;
be147d08
JM		 1234#if !defined(CONFIG_USER_ONLY)
1235 case 31:
1236 if (ctx->supervisor > 0) {
1237 /* Set process priority to very low */
1238 gen_op_store_pri(1);
1239 }
1240 break;
1241 case 5:
1242 if (ctx->supervisor > 0) {
1243 /* Set process priority to medium-hight */
1244 gen_op_store_pri(5);
1245 }
1246 break;
1247 case 3:
1248 if (ctx->supervisor > 0) {
1249 /* Set process priority to high */
1250 gen_op_store_pri(6);
1251 }
1252 break;
be147d08
JM		 1253 case 7:
1254 if (ctx->supervisor > 1) {
1255 /* Set process priority to very high */
1256 gen_op_store_pri(7);
1257 }
1258 break;
be147d08 1259#endif
c80f84e3
JM		 1260 default:
1261 /* nop */
1262 break;
1263 }
1264#endif
9a64fbe4 1265 }
9a64fbe4
FB		 1266}
1267
79aceca5 1268/* orc & orc. */
d9bce9d9 1269GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
79aceca5 1270/* xor & xor. */
9a64fbe4
FB		 1271GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1272{
1273 gen_op_load_gpr_T0(rS(ctx->opcode));
1274 /* Optimisation for "set to zero" case */
1275 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1276 gen_op_load_gpr_T1(rB(ctx->opcode));
1277 gen_op_xor();
1278 } else {
76a66253 1279 gen_op_reset_T0();
9a64fbe4 1280 }
9a64fbe4 1281 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1282 if (unlikely(Rc(ctx->opcode) != 0))
1283 gen_set_Rc0(ctx);
9a64fbe4 1284}
79aceca5
FB		 1285/* ori */
1286GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1287{
76a66253 1288 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1289
9a64fbe4
FB		 1290 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1291 /* NOP */
76a66253 1292 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1293 return;
76a66253
JM		 1294 }
1295 gen_op_load_gpr_T0(rS(ctx->opcode));
1296 if (likely(uimm != 0))
79aceca5 1297 gen_op_ori(uimm);
76a66253 1298 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1299}
1300/* oris */
1301GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1302{
76a66253 1303 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1304
9a64fbe4
FB		 1305 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1306 /* NOP */
1307 return;
76a66253
JM		 1308 }
1309 gen_op_load_gpr_T0(rS(ctx->opcode));
1310 if (likely(uimm != 0))
79aceca5 1311 gen_op_ori(uimm << 16);
76a66253 1312 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1313}
1314/* xori */
1315GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1316{
76a66253 1317 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1318
1319 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1320 /* NOP */
1321 return;
1322 }
79aceca5 1323 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1324 if (likely(uimm != 0))
1325 gen_op_xori(uimm);
79aceca5 1326 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1327}
1328
1329/* xoris */
1330GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1331{
76a66253 1332 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1333
1334 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1335 /* NOP */
1336 return;
1337 }
79aceca5 1338 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1339 if (likely(uimm != 0))
1340 gen_op_xori(uimm << 16);
79aceca5 1341 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1342}
1343
d9bce9d9
JM		 1344/* popcntb : PowerPC 2.03 specification */
1345GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1346{
1347 gen_op_load_gpr_T0(rS(ctx->opcode));
1348#if defined(TARGET_PPC64)
1349 if (ctx->sf_mode)
1350 gen_op_popcntb_64();
1351 else
1352#endif
1353 gen_op_popcntb();
1354 gen_op_store_T0_gpr(rA(ctx->opcode));
1355}
1356
1357#if defined(TARGET_PPC64)
1358/* extsw & extsw. */
1359GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1360/* cntlzd */
1361GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1362#endif
1363
79aceca5
FB		 1364/*** Integer rotate ***/
1365/* rlwimi & rlwimi. */
1366GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1367{
76a66253
JM		 1368 target_ulong mask;
1369 uint32_t mb, me, sh;
79aceca5
FB		 1370
1371 mb = MB(ctx->opcode);
1372 me = ME(ctx->opcode);
76a66253 1373 sh = SH(ctx->opcode);
76a66253
JM		 1374 if (likely(sh == 0)) {
1375 if (likely(mb == 0 && me == 31)) {
1376 gen_op_load_gpr_T0(rS(ctx->opcode));
1377 goto do_store;
1378 } else if (likely(mb == 31 && me == 0)) {
1379 gen_op_load_gpr_T0(rA(ctx->opcode));
1380 goto do_store;
1381 }
1382 gen_op_load_gpr_T0(rS(ctx->opcode));
1383 gen_op_load_gpr_T1(rA(ctx->opcode));
1384 goto do_mask;
1385 }
79aceca5 1386 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 1387 gen_op_load_gpr_T1(rA(ctx->opcode));
76a66253
JM		 1388 gen_op_rotli32_T0(SH(ctx->opcode));
1389 do_mask:
1390#if defined(TARGET_PPC64)
1391 mb += 32;
1392 me += 32;
1393#endif
1394 mask = MASK(mb, me);
1395 gen_op_andi_T0(mask);
1396 gen_op_andi_T1(~mask);
1397 gen_op_or();
1398 do_store:
79aceca5 1399 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1400 if (unlikely(Rc(ctx->opcode) != 0))
1401 gen_set_Rc0(ctx);
79aceca5
FB		 1402}
1403/* rlwinm & rlwinm. */
1404GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1405{
1406 uint32_t mb, me, sh;
3b46e624 1407
79aceca5
FB		 1408 sh = SH(ctx->opcode);
1409 mb = MB(ctx->opcode);
1410 me = ME(ctx->opcode);
1411 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1412 if (likely(sh == 0)) {
1413 goto do_mask;
1414 }
1415 if (likely(mb == 0)) {
1416 if (likely(me == 31)) {
1417 gen_op_rotli32_T0(sh);
1418 goto do_store;
1419 } else if (likely(me == (31 - sh))) {
1420 gen_op_sli_T0(sh);
1421 goto do_store;
79aceca5 1422 }
76a66253
JM		 1423 } else if (likely(me == 31)) {
1424 if (likely(sh == (32 - mb))) {
1425 gen_op_srli_T0(mb);
1426 goto do_store;
79aceca5
FB		 1427 }
1428 }
76a66253
JM		 1429 gen_op_rotli32_T0(sh);
1430 do_mask:
1431#if defined(TARGET_PPC64)
1432 mb += 32;
1433 me += 32;
1434#endif
1435 gen_op_andi_T0(MASK(mb, me));
1436 do_store:
79aceca5 1437 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1438 if (unlikely(Rc(ctx->opcode) != 0))
1439 gen_set_Rc0(ctx);
79aceca5
FB		 1440}
1441/* rlwnm & rlwnm. */
1442GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1443{
1444 uint32_t mb, me;
1445
1446 mb = MB(ctx->opcode);
1447 me = ME(ctx->opcode);
1448 gen_op_load_gpr_T0(rS(ctx->opcode));
1449 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 1450 gen_op_rotl32_T0_T1();
1451 if (unlikely(mb != 0 || me != 31)) {
1452#if defined(TARGET_PPC64)
1453 mb += 32;
1454 me += 32;
1455#endif
1456 gen_op_andi_T0(MASK(mb, me));
79aceca5 1457 }
79aceca5 1458 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1459 if (unlikely(Rc(ctx->opcode) != 0))
1460 gen_set_Rc0(ctx);
79aceca5
FB		 1461}
1462
d9bce9d9
JM		 1463#if defined(TARGET_PPC64)
1464#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1465GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1466{ \
1467 gen_##name(ctx, 0); \
1468} \
c7697e1f
JM		 1469GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1470 PPC_64B) \
d9bce9d9
JM		 1471{ \
1472 gen_##name(ctx, 1); \
1473}
1474#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1475GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1476{ \
1477 gen_##name(ctx, 0, 0); \
1478} \
c7697e1f
JM		 1479GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1480 PPC_64B) \
d9bce9d9
JM		 1481{ \
1482 gen_##name(ctx, 0, 1); \
1483} \
c7697e1f
JM		 1484GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1485 PPC_64B) \
d9bce9d9
JM		 1486{ \
1487 gen_##name(ctx, 1, 0); \
1488} \
c7697e1f
JM		 1489GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1490 PPC_64B) \
d9bce9d9
JM		 1491{ \
1492 gen_##name(ctx, 1, 1); \
1493}
51789c41 1494
b068d6a7 1495static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
40d0591e
JM		 1496{
1497 if (mask >> 32)
1498 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1499 else
1500 gen_op_andi_T0(mask);
1501}
1502
b068d6a7 1503static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
40d0591e
JM		 1504{
1505 if (mask >> 32)
1506 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1507 else
1508 gen_op_andi_T1(mask);
1509}
1510
b068d6a7
JM		 1511static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1512 uint32_t me, uint32_t sh)
51789c41
JM		 1513{
1514 gen_op_load_gpr_T0(rS(ctx->opcode));
1515 if (likely(sh == 0)) {
1516 goto do_mask;
1517 }
1518 if (likely(mb == 0)) {
1519 if (likely(me == 63)) {
40d0591e 1520 gen_op_rotli64_T0(sh);
51789c41
JM		 1521 goto do_store;
1522 } else if (likely(me == (63 - sh))) {
1523 gen_op_sli_T0(sh);
1524 goto do_store;
1525 }
1526 } else if (likely(me == 63)) {
1527 if (likely(sh == (64 - mb))) {
40d0591e 1528 gen_op_srli_T0_64(mb);
51789c41
JM		 1529 goto do_store;
1530 }
1531 }
1532 gen_op_rotli64_T0(sh);
1533 do_mask:
40d0591e 1534 gen_andi_T0_64(ctx, MASK(mb, me));
51789c41
JM		 1535 do_store:
1536 gen_op_store_T0_gpr(rA(ctx->opcode));
1537 if (unlikely(Rc(ctx->opcode) != 0))
1538 gen_set_Rc0(ctx);
1539}
d9bce9d9 1540/* rldicl - rldicl. */
b068d6a7 1541static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1542{
51789c41 1543 uint32_t sh, mb;
d9bce9d9 1544
9d53c753
JM		 1545 sh = SH(ctx->opcode) | (shn << 5);
1546 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1547 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1548}
51789c41 1549GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1550/* rldicr - rldicr. */
b068d6a7 1551static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1552{
51789c41 1553 uint32_t sh, me;
d9bce9d9 1554
9d53c753
JM		 1555 sh = SH(ctx->opcode) | (shn << 5);
1556 me = MB(ctx->opcode) | (men << 5);
51789c41 1557 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1558}
51789c41 1559GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1560/* rldic - rldic. */
b068d6a7 1561static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1562{
51789c41 1563 uint32_t sh, mb;
d9bce9d9 1564
9d53c753
JM		 1565 sh = SH(ctx->opcode) | (shn << 5);
1566 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1567 gen_rldinm(ctx, mb, 63 - sh, sh);
1568}
1569GEN_PPC64_R4(rldic, 0x1E, 0x04);
1570
b068d6a7
JM		 1571static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1572 uint32_t me)
51789c41
JM		 1573{
1574 gen_op_load_gpr_T0(rS(ctx->opcode));
1575 gen_op_load_gpr_T1(rB(ctx->opcode));
1576 gen_op_rotl64_T0_T1();
1577 if (unlikely(mb != 0 || me != 63)) {
40d0591e 1578 gen_andi_T0_64(ctx, MASK(mb, me));
51789c41
JM		 1579 }
1580 gen_op_store_T0_gpr(rA(ctx->opcode));
1581 if (unlikely(Rc(ctx->opcode) != 0))
1582 gen_set_Rc0(ctx);
d9bce9d9 1583}
51789c41 1584
d9bce9d9 1585/* rldcl - rldcl. */
b068d6a7 1586static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1587{
51789c41 1588 uint32_t mb;
d9bce9d9 1589
9d53c753 1590 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1591 gen_rldnm(ctx, mb, 63);
d9bce9d9 1592}
36081602 1593GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1594/* rldcr - rldcr. */
b068d6a7 1595static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1596{
51789c41 1597 uint32_t me;
d9bce9d9 1598
9d53c753 1599 me = MB(ctx->opcode) | (men << 5);
51789c41 1600 gen_rldnm(ctx, 0, me);
d9bce9d9 1601}
36081602 1602GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1603/* rldimi - rldimi. */
b068d6a7 1604static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1605{
51789c41 1606 uint64_t mask;
271a916e 1607 uint32_t sh, mb, me;
d9bce9d9 1608
9d53c753
JM		 1609 sh = SH(ctx->opcode) | (shn << 5);
1610 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1611 me = 63 - sh;
51789c41
JM		 1612 if (likely(sh == 0)) {
1613 if (likely(mb == 0)) {
1614 gen_op_load_gpr_T0(rS(ctx->opcode));
1615 goto do_store;
51789c41
JM		 1616 }
1617 gen_op_load_gpr_T0(rS(ctx->opcode));
1618 gen_op_load_gpr_T1(rA(ctx->opcode));
1619 goto do_mask;
1620 }
1621 gen_op_load_gpr_T0(rS(ctx->opcode));
1622 gen_op_load_gpr_T1(rA(ctx->opcode));
40d0591e 1623 gen_op_rotli64_T0(sh);
51789c41 1624 do_mask:
271a916e 1625 mask = MASK(mb, me);
40d0591e
JM		 1626 gen_andi_T0_64(ctx, mask);
1627 gen_andi_T1_64(ctx, ~mask);
51789c41
JM		 1628 gen_op_or();
1629 do_store:
1630 gen_op_store_T0_gpr(rA(ctx->opcode));
1631 if (unlikely(Rc(ctx->opcode) != 0))
1632 gen_set_Rc0(ctx);
d9bce9d9 1633}
36081602 1634GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1635#endif
1636
79aceca5
FB		 1637/*** Integer shift ***/
1638/* slw & slw. */
d9bce9d9 1639__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
79aceca5 1640/* sraw & sraw. */
d9bce9d9 1641__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
79aceca5
FB		 1642/* srawi & srawi. */
1643GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1644{
d9bce9d9 1645 int mb, me;
79aceca5 1646 gen_op_load_gpr_T0(rS(ctx->opcode));
d9bce9d9
JM		 1647 if (SH(ctx->opcode) != 0) {
1648 gen_op_move_T1_T0();
1649 mb = 32 - SH(ctx->opcode);
1650 me = 31;
1651#if defined(TARGET_PPC64)
1652 mb += 32;
1653 me += 32;
1654#endif
1655 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1656 }
79aceca5 1657 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1658 if (unlikely(Rc(ctx->opcode) != 0))
1659 gen_set_Rc0(ctx);
79aceca5
FB		 1660}
1661/* srw & srw. */
d9bce9d9
JM		 1662__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1663
1664#if defined(TARGET_PPC64)
1665/* sld & sld. */
1666__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1667/* srad & srad. */
1668__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1669/* sradi & sradi. */
b068d6a7 1670static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9
JM		 1671{
1672 uint64_t mask;
1673 int sh, mb, me;
1674
1675 gen_op_load_gpr_T0(rS(ctx->opcode));
1676 sh = SH(ctx->opcode) + (n << 5);
1677 if (sh != 0) {
1678 gen_op_move_T1_T0();
1679 mb = 64 - SH(ctx->opcode);
1680 me = 63;
1681 mask = MASK(mb, me);
1682 gen_op_sradi(sh, mask >> 32, mask);
1683 }
1684 gen_op_store_T0_gpr(rA(ctx->opcode));
1685 if (unlikely(Rc(ctx->opcode) != 0))
1686 gen_set_Rc0(ctx);
1687}
c7697e1f 1688GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1689{
1690 gen_sradi(ctx, 0);
1691}
c7697e1f 1692GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1693{
1694 gen_sradi(ctx, 1);
1695}
1696/* srd & srd. */
1697__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1698#endif
79aceca5
FB		 1699
1700/*** Floating-Point arithmetic ***/
7c58044c 1701#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1702GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1703{ \
76a66253 1704 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1705 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1706 return; \
1707 } \
9a64fbe4
FB		 1708 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1709 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1710 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
7c58044c 1711 gen_reset_fpstatus(); \
4ecc3190
FB		 1712 gen_op_f##op(); \
1713 if (isfloat) { \
1714 gen_op_frsp(); \
1715 } \
9a64fbe4 1716 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1717 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1718}
1719
7c58044c
JM		 1720#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1721_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1722_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1723
7c58044c
JM		 1724#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1725GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1726{ \
76a66253 1727 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1728 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1729 return; \
1730 } \
9a64fbe4
FB		 1731 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1732 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
7c58044c 1733 gen_reset_fpstatus(); \
4ecc3190
FB		 1734 gen_op_f##op(); \
1735 if (isfloat) { \
1736 gen_op_frsp(); \
1737 } \
9a64fbe4 1738 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1739 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1740}
7c58044c
JM		 1741#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1742_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1743_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1744
7c58044c
JM		 1745#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1746GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1747{ \
76a66253 1748 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1749 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1750 return; \
1751 } \
9a64fbe4
FB		 1752 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1753 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
7c58044c 1754 gen_reset_fpstatus(); \
4ecc3190
FB		 1755 gen_op_f##op(); \
1756 if (isfloat) { \
1757 gen_op_frsp(); \
1758 } \
9a64fbe4 1759 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1760 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1761}
7c58044c
JM		 1762#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1763_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1764_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1765
7c58044c 1766#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 1767GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 1768{ \
76a66253 1769 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1770 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1771 return; \
1772 } \
9a64fbe4 1773 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
7c58044c 1774 gen_reset_fpstatus(); \
9a64fbe4
FB		 1775 gen_op_f##name(); \
1776 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1777 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1778}
1779
7c58044c 1780#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 1781GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 1782{ \
76a66253 1783 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1784 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1785 return; \
1786 } \
9a64fbe4 1787 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
7c58044c 1788 gen_reset_fpstatus(); \
9a64fbe4
FB		 1789 gen_op_f##name(); \
1790 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1791 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1792}
1793
9a64fbe4 1794/* fadd - fadds */
7c58044c 1795GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1796/* fdiv - fdivs */
7c58044c 1797GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1798/* fmul - fmuls */
7c58044c 1799GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 1800
d7e4b87e 1801/* fre */
7c58044c 1802GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 1803
a750fc0b 1804/* fres */
7c58044c 1805GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 1806
a750fc0b 1807/* frsqrte */
7c58044c
JM		 1808GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1809
1810/* frsqrtes */
1811static always_inline void gen_op_frsqrtes (void)
1812{
1813 gen_op_frsqrte();
1814 gen_op_frsp();
1815}
1b413d55 1816GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 1817
a750fc0b 1818/* fsel */
7c58044c 1819_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 1820/* fsub - fsubs */
7c58044c 1821GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 1822/* Optional: */
1823/* fsqrt */
a750fc0b 1824GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 1825{
76a66253 1826 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1827 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 1828 return;
1829 }
c7d344af 1830 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 1831 gen_reset_fpstatus();
c7d344af
FB		 1832 gen_op_fsqrt();
1833 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1834 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 1835}
79aceca5 1836
a750fc0b 1837GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 1838{
76a66253 1839 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1840 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1841 return;
1842 }
9a64fbe4 1843 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 1844 gen_reset_fpstatus();
4ecc3190
FB		 1845 gen_op_fsqrt();
1846 gen_op_frsp();
9a64fbe4 1847 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1848 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 1849}
1850
1851/*** Floating-Point multiply-and-add ***/
4ecc3190 1852/* fmadd - fmadds */
7c58044c 1853GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 1854/* fmsub - fmsubs */
7c58044c 1855GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 1856/* fnmadd - fnmadds */
7c58044c 1857GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 1858/* fnmsub - fnmsubs */
7c58044c 1859GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 1860
1861/*** Floating-Point round & convert ***/
1862/* fctiw */
7c58044c 1863GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 1864/* fctiwz */
7c58044c 1865GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 1866/* frsp */
7c58044c 1867GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 1868#if defined(TARGET_PPC64)
1869/* fcfid */
7c58044c 1870GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 1871/* fctid */
7c58044c 1872GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 1873/* fctidz */
7c58044c 1874GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 1875#endif
79aceca5 1876
d7e4b87e 1877/* frin */
7c58044c 1878GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 1879/* friz */
7c58044c 1880GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 1881/* frip */
7c58044c 1882GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 1883/* frim */
7c58044c 1884GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 1885
79aceca5
FB		 1886/*** Floating-Point compare ***/
1887/* fcmpo */
76a66253 1888GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 1889{
76a66253 1890 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1891 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1892 return;
1893 }
9a64fbe4
FB		 1894 gen_op_load_fpr_FT0(rA(ctx->opcode));
1895 gen_op_load_fpr_FT1(rB(ctx->opcode));
7c58044c 1896 gen_reset_fpstatus();
9a64fbe4
FB		 1897 gen_op_fcmpo();
1898 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1899 gen_op_float_check_status();
79aceca5
FB		 1900}
1901
1902/* fcmpu */
76a66253 1903GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 1904{
76a66253 1905 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1906 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1907 return;
1908 }
9a64fbe4
FB		 1909 gen_op_load_fpr_FT0(rA(ctx->opcode));
1910 gen_op_load_fpr_FT1(rB(ctx->opcode));
7c58044c 1911 gen_reset_fpstatus();
9a64fbe4
FB		 1912 gen_op_fcmpu();
1913 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1914 gen_op_float_check_status();
79aceca5
FB		 1915}
1916
9a64fbe4
FB		 1917/*** Floating-point move ***/
1918/* fabs */
7c58044c
JM		 1919/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1920GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 1921
1922/* fmr - fmr. */
7c58044c 1923/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 1924GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1925{
76a66253 1926 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1927 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1928 return;
1929 }
9a64fbe4
FB		 1930 gen_op_load_fpr_FT0(rB(ctx->opcode));
1931 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1932 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 1933}
1934
1935/* fnabs */
7c58044c
JM		 1936/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1937GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 1938/* fneg */
7c58044c
JM		 1939/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1940GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 1941
79aceca5
FB		 1942/*** Floating-Point status & ctrl register ***/
1943/* mcrfs */
1944GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1945{
7c58044c
JM		 1946 int bfa;
1947
76a66253 1948 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1949 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1950 return;
1951 }
7c58044c
JM		 1952 gen_optimize_fprf();
1953 bfa = 4 * (7 - crfS(ctx->opcode));
1954 gen_op_load_fpscr_T0(bfa);
fb0eaffc 1955 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1956 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 1957}
1958
1959/* mffs */
1960GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1961{
76a66253 1962 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1963 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1964 return;
1965 }
7c58044c
JM		 1966 gen_optimize_fprf();
1967 gen_reset_fpstatus();
1968 gen_op_load_fpscr_FT0();
fb0eaffc 1969 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1970 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 1971}
1972
1973/* mtfsb0 */
1974GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1975{
fb0eaffc 1976 uint8_t crb;
3b46e624 1977
76a66253 1978 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1979 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1980 return;
1981 }
7c58044c
JM		 1982 crb = 32 - (crbD(ctx->opcode) >> 2);
1983 gen_optimize_fprf();
1984 gen_reset_fpstatus();
1985 if (likely(crb != 30 && crb != 29))
1986 gen_op_fpscr_resetbit(~(1 << crb));
1987 if (unlikely(Rc(ctx->opcode) != 0)) {
1988 gen_op_load_fpcc();
1989 gen_op_set_Rc0();
1990 }
79aceca5
FB		 1991}
1992
1993/* mtfsb1 */
1994GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1995{
fb0eaffc 1996 uint8_t crb;
3b46e624 1997
76a66253 1998 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1999 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2000 return;
2001 }
7c58044c
JM		 2002 crb = 32 - (crbD(ctx->opcode) >> 2);
2003 gen_optimize_fprf();
2004 gen_reset_fpstatus();
2005 /* XXX: we pretend we can only do IEEE floating-point computations */
2006 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2007 gen_op_fpscr_setbit(crb);
2008 if (unlikely(Rc(ctx->opcode) != 0)) {
2009 gen_op_load_fpcc();
2010 gen_op_set_Rc0();
2011 }
2012 /* We can raise a differed exception */
2013 gen_op_float_check_status();
79aceca5
FB		 2014}
2015
2016/* mtfsf */
2017GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2018{
76a66253 2019 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2020 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2021 return;
2022 }
7c58044c 2023 gen_optimize_fprf();
fb0eaffc 2024 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 2025 gen_reset_fpstatus();
28b6751f 2026 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c
JM		 2027 if (unlikely(Rc(ctx->opcode) != 0)) {
2028 gen_op_load_fpcc();
2029 gen_op_set_Rc0();
2030 }
2031 /* We can raise a differed exception */
2032 gen_op_float_check_status();
79aceca5
FB		 2033}
2034
2035/* mtfsfi */
2036GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2037{
7c58044c
JM		 2038 int bf, sh;
2039
76a66253 2040 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2041 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2042 return;
2043 }
7c58044c
JM		 2044 bf = crbD(ctx->opcode) >> 2;
2045 sh = 7 - bf;
2046 gen_optimize_fprf();
2047 gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2048 gen_reset_fpstatus();
2049 gen_op_store_fpscr(1 << sh);
2050 if (unlikely(Rc(ctx->opcode) != 0)) {
2051 gen_op_load_fpcc();
2052 gen_op_set_Rc0();
2053 }
2054 /* We can raise a differed exception */
2055 gen_op_float_check_status();
79aceca5
FB		 2056}
2057
76a66253
JM		 2058/*** Addressing modes ***/
2059/* Register indirect with immediate index : EA = (rA|0) + SIMM */
b068d6a7
JM		 2060static always_inline void gen_addr_imm_index (DisasContext *ctx,
2061 target_long maskl)
76a66253
JM		 2062{
2063 target_long simm = SIMM(ctx->opcode);
2064
be147d08 2065 simm &= ~maskl;
76a66253 2066 if (rA(ctx->opcode) == 0) {
d9bce9d9 2067 gen_set_T0(simm);
76a66253
JM		 2068 } else {
2069 gen_op_load_gpr_T0(rA(ctx->opcode));
2070 if (likely(simm != 0))
2071 gen_op_addi(simm);
2072 }
a496775f
JM		 2073#ifdef DEBUG_MEMORY_ACCESSES
2074 gen_op_print_mem_EA();
2075#endif
76a66253
JM		 2076}
2077
b068d6a7 2078static always_inline void gen_addr_reg_index (DisasContext *ctx)
76a66253
JM		 2079{
2080 if (rA(ctx->opcode) == 0) {
2081 gen_op_load_gpr_T0(rB(ctx->opcode));
2082 } else {
2083 gen_op_load_gpr_T0(rA(ctx->opcode));
2084 gen_op_load_gpr_T1(rB(ctx->opcode));
2085 gen_op_add();
2086 }
a496775f
JM		 2087#ifdef DEBUG_MEMORY_ACCESSES
2088 gen_op_print_mem_EA();
2089#endif
76a66253
JM		 2090}
2091
b068d6a7 2092static always_inline void gen_addr_register (DisasContext *ctx)
76a66253
JM		 2093{
2094 if (rA(ctx->opcode) == 0) {
2095 gen_op_reset_T0();
2096 } else {
2097 gen_op_load_gpr_T0(rA(ctx->opcode));
2098 }
a496775f
JM		 2099#ifdef DEBUG_MEMORY_ACCESSES
2100 gen_op_print_mem_EA();
2101#endif
76a66253
JM		 2102}
2103
7863667f
JM		 2104#if defined(TARGET_PPC64)
2105#define _GEN_MEM_FUNCS(name, mode) \
2106 &gen_op_##name##_##mode, \
2107 &gen_op_##name##_le_##mode, \
2108 &gen_op_##name##_64_##mode, \
2109 &gen_op_##name##_le_64_##mode
2110#else
2111#define _GEN_MEM_FUNCS(name, mode) \
2112 &gen_op_##name##_##mode, \
2113 &gen_op_##name##_le_##mode
2114#endif
9a64fbe4 2115#if defined(CONFIG_USER_ONLY)
d9bce9d9 2116#if defined(TARGET_PPC64)
7863667f 2117#define NB_MEM_FUNCS 4
d9bce9d9 2118#else
7863667f 2119#define NB_MEM_FUNCS 2
d9bce9d9 2120#endif
7863667f
JM		 2121#define GEN_MEM_FUNCS(name) \
2122 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2123#else
d9bce9d9 2124#if defined(TARGET_PPC64)
7863667f 2125#define NB_MEM_FUNCS 12
2857068e 2126#else
7863667f 2127#define NB_MEM_FUNCS 6
2857068e 2128#endif
7863667f
JM		 2129#define GEN_MEM_FUNCS(name) \
2130 _GEN_MEM_FUNCS(name, user), \
2131 _GEN_MEM_FUNCS(name, kernel), \
2132 _GEN_MEM_FUNCS(name, hypv)
2133#endif
2134
2135/*** Integer load ***/
2136#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
111bfab3 2137/* Byte access routine are endian safe */
7863667f
JM		 2138#define gen_op_lbz_le_raw gen_op_lbz_raw
2139#define gen_op_lbz_le_user gen_op_lbz_user
2140#define gen_op_lbz_le_kernel gen_op_lbz_kernel
2141#define gen_op_lbz_le_hypv gen_op_lbz_hypv
2142#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2857068e 2143#define gen_op_lbz_le_64_user gen_op_lbz_64_user
d9bce9d9 2144#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
7863667f
JM		 2145#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2146#define gen_op_stb_le_raw gen_op_stb_raw
2147#define gen_op_stb_le_user gen_op_stb_user
2148#define gen_op_stb_le_kernel gen_op_stb_kernel
2149#define gen_op_stb_le_hypv gen_op_stb_hypv
2150#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2151#define gen_op_stb_le_64_user gen_op_stb_64_user
2152#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2153#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
d9bce9d9 2154#define OP_LD_TABLE(width) \
7863667f
JM		 2155static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2156 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2157};
2158#define OP_ST_TABLE(width) \
7863667f
JM		 2159static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2160 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2161};
9a64fbe4 2162
d9bce9d9
JM		 2163#define GEN_LD(width, opc, type) \
2164GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2165{ \
9d53c753 2166 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2167 op_ldst(l##width); \
79aceca5 2168 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 2169}
2170
d9bce9d9
JM		 2171#define GEN_LDU(width, opc, type) \
2172GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2173{ \
76a66253
JM		 2174 if (unlikely(rA(ctx->opcode) == 0 || \
2175 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2176 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2177 return; \
9a64fbe4 2178 } \
9d53c753 2179 if (type == PPC_64B) \
be147d08 2180 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2181 else \
2182 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2183 op_ldst(l##width); \
79aceca5
FB		 2184 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2185 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2186}
2187
d9bce9d9
JM		 2188#define GEN_LDUX(width, opc2, opc3, type) \
2189GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2190{ \
76a66253
JM		 2191 if (unlikely(rA(ctx->opcode) == 0 || \
2192 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2193 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2194 return; \
9a64fbe4 2195 } \
76a66253 2196 gen_addr_reg_index(ctx); \
9a64fbe4 2197 op_ldst(l##width); \
79aceca5
FB		 2198 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2199 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2200}
2201
d9bce9d9
JM		 2202#define GEN_LDX(width, opc2, opc3, type) \
2203GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2204{ \
76a66253 2205 gen_addr_reg_index(ctx); \
9a64fbe4 2206 op_ldst(l##width); \
79aceca5 2207 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 2208}
2209
d9bce9d9 2210#define GEN_LDS(width, op, type) \
9a64fbe4 2211OP_LD_TABLE(width); \
d9bce9d9
JM		 2212GEN_LD(width, op | 0x20, type); \
2213GEN_LDU(width, op | 0x21, type); \
2214GEN_LDUX(width, 0x17, op | 0x01, type); \
2215GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2216
2217/* lbz lbzu lbzux lbzx */
d9bce9d9 2218GEN_LDS(bz, 0x02, PPC_INTEGER);
79aceca5 2219/* lha lhau lhaux lhax */
d9bce9d9 2220GEN_LDS(ha, 0x0A, PPC_INTEGER);
79aceca5 2221/* lhz lhzu lhzux lhzx */
d9bce9d9 2222GEN_LDS(hz, 0x08, PPC_INTEGER);
79aceca5 2223/* lwz lwzu lwzux lwzx */
d9bce9d9
JM		 2224GEN_LDS(wz, 0x00, PPC_INTEGER);
2225#if defined(TARGET_PPC64)
2226OP_LD_TABLE(wa);
2227OP_LD_TABLE(d);
2228/* lwaux */
2229GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2230/* lwax */
2231GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2232/* ldux */
2233GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2234/* ldx */
2235GEN_LDX(d, 0x15, 0x00, PPC_64B);
2236GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2237{
2238 if (Rc(ctx->opcode)) {
2239 if (unlikely(rA(ctx->opcode) == 0 ||
2240 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2241 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2242 return;
2243 }
2244 }
be147d08 2245 gen_addr_imm_index(ctx, 0x03);
d9bce9d9
JM		 2246 if (ctx->opcode & 0x02) {
2247 /* lwa (lwau is undefined) */
2248 op_ldst(lwa);
2249 } else {
2250 /* ld - ldu */
2251 op_ldst(ld);
2252 }
2253 gen_op_store_T1_gpr(rD(ctx->opcode));
2254 if (Rc(ctx->opcode))
2255 gen_op_store_T0_gpr(rA(ctx->opcode));
2256}
be147d08
JM		 2257/* lq */
2258GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2259{
2260#if defined(CONFIG_USER_ONLY)
2261 GEN_EXCP_PRIVOPC(ctx);
2262#else
2263 int ra, rd;
2264
2265 /* Restore CPU state */
2266 if (unlikely(ctx->supervisor == 0)) {
2267 GEN_EXCP_PRIVOPC(ctx);
2268 return;
2269 }
2270 ra = rA(ctx->opcode);
2271 rd = rD(ctx->opcode);
2272 if (unlikely((rd & 1) || rd == ra)) {
2273 GEN_EXCP_INVAL(ctx);
2274 return;
2275 }
2276 if (unlikely(ctx->mem_idx & 1)) {
2277 /* Little-endian mode is not handled */
2278 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2279 return;
2280 }
2281 gen_addr_imm_index(ctx, 0x0F);
2282 op_ldst(ld);
2283 gen_op_store_T1_gpr(rd);
2284 gen_op_addi(8);
2285 op_ldst(ld);
2286 gen_op_store_T1_gpr(rd + 1);
2287#endif
2288}
d9bce9d9 2289#endif
79aceca5
FB		 2290
2291/*** Integer store ***/
d9bce9d9
JM		 2292#define GEN_ST(width, opc, type) \
2293GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2294{ \
9d53c753 2295 gen_addr_imm_index(ctx, 0); \
9a64fbe4
FB		 2296 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2297 op_ldst(st##width); \
79aceca5
FB		 2298}
2299
d9bce9d9
JM		 2300#define GEN_STU(width, opc, type) \
2301GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2302{ \
76a66253 2303 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2304 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2305 return; \
9a64fbe4 2306 } \
9d53c753 2307 if (type == PPC_64B) \
be147d08 2308 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2309 else \
2310 gen_addr_imm_index(ctx, 0); \
79aceca5 2311 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 2312 op_ldst(st##width); \
79aceca5 2313 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2314}
2315
d9bce9d9
JM		 2316#define GEN_STUX(width, opc2, opc3, type) \
2317GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2318{ \
76a66253 2319 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2320 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2321 return; \
9a64fbe4 2322 } \
76a66253 2323 gen_addr_reg_index(ctx); \
9a64fbe4
FB		 2324 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2325 op_ldst(st##width); \
79aceca5 2326 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2327}
2328
d9bce9d9
JM		 2329#define GEN_STX(width, opc2, opc3, type) \
2330GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2331{ \
76a66253 2332 gen_addr_reg_index(ctx); \
9a64fbe4
FB		 2333 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2334 op_ldst(st##width); \
79aceca5
FB		 2335}
2336
d9bce9d9 2337#define GEN_STS(width, op, type) \
9a64fbe4 2338OP_ST_TABLE(width); \
d9bce9d9
JM		 2339GEN_ST(width, op | 0x20, type); \
2340GEN_STU(width, op | 0x21, type); \
2341GEN_STUX(width, 0x17, op | 0x01, type); \
2342GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2343
2344/* stb stbu stbux stbx */
d9bce9d9 2345GEN_STS(b, 0x06, PPC_INTEGER);
79aceca5 2346/* sth sthu sthux sthx */
d9bce9d9 2347GEN_STS(h, 0x0C, PPC_INTEGER);
79aceca5 2348/* stw stwu stwux stwx */
d9bce9d9
JM		 2349GEN_STS(w, 0x04, PPC_INTEGER);
2350#if defined(TARGET_PPC64)
2351OP_ST_TABLE(d);
426613db
JM		 2352GEN_STUX(d, 0x15, 0x05, PPC_64B);
2353GEN_STX(d, 0x15, 0x04, PPC_64B);
be147d08 2354GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2355{
be147d08
JM		 2356 int rs;
2357
2358 rs = rS(ctx->opcode);
2359 if ((ctx->opcode & 0x3) == 0x2) {
2360#if defined(CONFIG_USER_ONLY)
2361 GEN_EXCP_PRIVOPC(ctx);
2362#else
2363 /* stq */
2364 if (unlikely(ctx->supervisor == 0)) {
2365 GEN_EXCP_PRIVOPC(ctx);
2366 return;
2367 }
2368 if (unlikely(rs & 1)) {
e1833e1f 2369 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2370 return;
2371 }
be147d08
JM		 2372 if (unlikely(ctx->mem_idx & 1)) {
2373 /* Little-endian mode is not handled */
2374 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2375 return;
2376 }
2377 gen_addr_imm_index(ctx, 0x03);
2378 gen_op_load_gpr_T1(rs);
2379 op_ldst(std);
2380 gen_op_addi(8);
2381 gen_op_load_gpr_T1(rs + 1);
2382 op_ldst(std);
2383#endif
2384 } else {
2385 /* std / stdu */
2386 if (Rc(ctx->opcode)) {
2387 if (unlikely(rA(ctx->opcode) == 0)) {
2388 GEN_EXCP_INVAL(ctx);
2389 return;
2390 }
2391 }
2392 gen_addr_imm_index(ctx, 0x03);
2393 gen_op_load_gpr_T1(rs);
2394 op_ldst(std);
2395 if (Rc(ctx->opcode))
2396 gen_op_store_T0_gpr(rA(ctx->opcode));
d9bce9d9 2397 }
d9bce9d9
JM		 2398}
2399#endif
79aceca5
FB		 2400/*** Integer load and store with byte reverse ***/
2401/* lhbrx */
9a64fbe4 2402OP_LD_TABLE(hbr);
d9bce9d9 2403GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
79aceca5 2404/* lwbrx */
9a64fbe4 2405OP_LD_TABLE(wbr);
d9bce9d9 2406GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
79aceca5 2407/* sthbrx */
9a64fbe4 2408OP_ST_TABLE(hbr);
d9bce9d9 2409GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
79aceca5 2410/* stwbrx */
9a64fbe4 2411OP_ST_TABLE(wbr);
d9bce9d9 2412GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2413
2414/*** Integer load and store multiple ***/
111bfab3 2415#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 2416static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2417 GEN_MEM_FUNCS(lmw),
d9bce9d9 2418};
7863667f
JM		 2419static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2420 GEN_MEM_FUNCS(stmw),
d9bce9d9 2421};
9a64fbe4 2422
79aceca5
FB		 2423/* lmw */
2424GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2425{
76a66253 2426 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2427 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2428 gen_addr_imm_index(ctx, 0);
9a64fbe4 2429 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2430}
2431
2432/* stmw */
2433GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2434{
76a66253 2435 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2436 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2437 gen_addr_imm_index(ctx, 0);
9a64fbe4 2438 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2439}
2440
2441/*** Integer load and store strings ***/
9a64fbe4
FB		 2442#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2443#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
7863667f
JM		 2444static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2445 GEN_MEM_FUNCS(lswi),
d9bce9d9 2446};
7863667f
JM		 2447static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2448 GEN_MEM_FUNCS(lswx),
d9bce9d9 2449};
7863667f
JM		 2450static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2451 GEN_MEM_FUNCS(stsw),
9a64fbe4 2452};
9a64fbe4 2453
79aceca5 2454/* lswi */
3fc6c082 2455/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2456 * rA is in the range of registers to be loaded.
2457 * In an other hand, IBM says this is valid, but rA won't be loaded.
2458 * For now, I'll follow the spec...
2459 */
79aceca5
FB		 2460GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2461{
2462 int nb = NB(ctx->opcode);
2463 int start = rD(ctx->opcode);
9a64fbe4 2464 int ra = rA(ctx->opcode);
79aceca5
FB		 2465 int nr;
2466
2467 if (nb == 0)
2468 nb = 32;
2469 nr = nb / 4;
76a66253
JM		 2470 if (unlikely(((start + nr) > 32 &&
2471 start <= ra && (start + nr - 32) > ra) ||
2472 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 2473 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2474 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2475 return;
297d8e62 2476 }
8dd4983c 2477 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2478 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 2479 gen_addr_register(ctx);
2480 gen_op_set_T1(nb);
9a64fbe4 2481 op_ldsts(lswi, start);
79aceca5
FB		 2482}
2483
2484/* lswx */
2485GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2486{
9a64fbe4
FB		 2487 int ra = rA(ctx->opcode);
2488 int rb = rB(ctx->opcode);
2489
76a66253 2490 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2491 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2492 gen_addr_reg_index(ctx);
9a64fbe4 2493 if (ra == 0) {
9a64fbe4 2494 ra = rb;
79aceca5 2495 }
9a64fbe4
FB		 2496 gen_op_load_xer_bc();
2497 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 2498}
2499
2500/* stswi */
2501GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2502{
4b3686fa
FB		 2503 int nb = NB(ctx->opcode);
2504
76a66253 2505 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2506 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2507 gen_addr_register(ctx);
4b3686fa
FB		 2508 if (nb == 0)
2509 nb = 32;
2510 gen_op_set_T1(nb);
9a64fbe4 2511 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2512}
2513
2514/* stswx */
2515GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2516{
8dd4983c 2517 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 2518 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 2519 gen_addr_reg_index(ctx);
2520 gen_op_load_xer_bc();
9a64fbe4 2521 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2522}
2523
2524/*** Memory synchronisation ***/
2525/* eieio */
0db1b20e 2526GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 2527{
79aceca5
FB		 2528}
2529
2530/* isync */
0db1b20e 2531GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 2532{
e1833e1f 2533 GEN_STOP(ctx);
79aceca5
FB		 2534}
2535
111bfab3
FB		 2536#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2537#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 2538static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2539 GEN_MEM_FUNCS(lwarx),
111bfab3 2540};
7863667f
JM		 2541static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2542 GEN_MEM_FUNCS(stwcx),
985a19d6 2543};
9a64fbe4 2544
111bfab3 2545/* lwarx */
76a66253 2546GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 2547{
30032c94
JM		 2548 /* NIP cannot be restored if the memory exception comes from an helper */
2549 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2550 gen_addr_reg_index(ctx);
985a19d6 2551 op_lwarx();
79aceca5 2552 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 2553}
2554
2555/* stwcx. */
c7697e1f 2556GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 2557{
30032c94
JM		 2558 /* NIP cannot be restored if the memory exception comes from an helper */
2559 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2560 gen_addr_reg_index(ctx);
9a64fbe4
FB		 2561 gen_op_load_gpr_T1(rS(ctx->opcode));
2562 op_stwcx();
79aceca5
FB		 2563}
2564
426613db
JM		 2565#if defined(TARGET_PPC64)
2566#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2567#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 2568static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2569 GEN_MEM_FUNCS(ldarx),
426613db 2570};
7863667f
JM		 2571static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2572 GEN_MEM_FUNCS(stdcx),
426613db 2573};
426613db
JM		 2574
2575/* ldarx */
a750fc0b 2576GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 2577{
30032c94
JM		 2578 /* NIP cannot be restored if the memory exception comes from an helper */
2579 gen_update_nip(ctx, ctx->nip - 4);
426613db
JM		 2580 gen_addr_reg_index(ctx);
2581 op_ldarx();
2582 gen_op_store_T1_gpr(rD(ctx->opcode));
2583}
2584
2585/* stdcx. */
c7697e1f 2586GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 2587{
30032c94
JM		 2588 /* NIP cannot be restored if the memory exception comes from an helper */
2589 gen_update_nip(ctx, ctx->nip - 4);
426613db
JM		 2590 gen_addr_reg_index(ctx);
2591 gen_op_load_gpr_T1(rS(ctx->opcode));
2592 op_stdcx();
2593}
2594#endif /* defined(TARGET_PPC64) */
2595
79aceca5 2596/* sync */
a902d886 2597GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 2598{
79aceca5
FB		 2599}
2600
0db1b20e
JM		 2601/* wait */
2602GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2603{
2604 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 2605 gen_op_wait();
2606 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 2607}
2608
79aceca5 2609/*** Floating-point load ***/
477023a6
JM		 2610#define GEN_LDF(width, opc, type) \
2611GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2612{ \
76a66253 2613 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2614 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2615 return; \
2616 } \
9d53c753 2617 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2618 op_ldst(l##width); \
76a66253 2619 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5
FB		 2620}
2621
477023a6
JM		 2622#define GEN_LDUF(width, opc, type) \
2623GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2624{ \
76a66253 2625 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2626 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2627 return; \
2628 } \
76a66253 2629 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2630 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2631 return; \
9a64fbe4 2632 } \
9d53c753 2633 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2634 op_ldst(l##width); \
76a66253 2635 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5 2636 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2637}
2638
477023a6
JM		 2639#define GEN_LDUXF(width, opc, type) \
2640GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2641{ \
76a66253 2642 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2643 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2644 return; \
2645 } \
76a66253 2646 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2647 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2648 return; \
9a64fbe4 2649 } \
76a66253 2650 gen_addr_reg_index(ctx); \
9a64fbe4 2651 op_ldst(l##width); \
76a66253 2652 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5 2653 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2654}
2655
477023a6
JM		 2656#define GEN_LDXF(width, opc2, opc3, type) \
2657GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2658{ \
76a66253 2659 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2660 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2661 return; \
2662 } \
76a66253 2663 gen_addr_reg_index(ctx); \
9a64fbe4 2664 op_ldst(l##width); \
76a66253 2665 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5
FB		 2666}
2667
477023a6 2668#define GEN_LDFS(width, op, type) \
9a64fbe4 2669OP_LD_TABLE(width); \
477023a6
JM		 2670GEN_LDF(width, op | 0x20, type); \
2671GEN_LDUF(width, op | 0x21, type); \
2672GEN_LDUXF(width, op | 0x01, type); \
2673GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 2674
2675/* lfd lfdu lfdux lfdx */
477023a6 2676GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 2677/* lfs lfsu lfsux lfsx */
477023a6 2678GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 2679
2680/*** Floating-point store ***/
477023a6
JM		 2681#define GEN_STF(width, opc, type) \
2682GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2683{ \
76a66253 2684 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2685 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2686 return; \
2687 } \
9d53c753 2688 gen_addr_imm_index(ctx, 0); \
76a66253 2689 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 2690 op_ldst(st##width); \
79aceca5
FB		 2691}
2692
477023a6
JM		 2693#define GEN_STUF(width, opc, type) \
2694GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2695{ \
76a66253 2696 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2697 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2698 return; \
2699 } \
76a66253 2700 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2701 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2702 return; \
9a64fbe4 2703 } \
9d53c753 2704 gen_addr_imm_index(ctx, 0); \
76a66253 2705 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 2706 op_ldst(st##width); \
79aceca5 2707 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2708}
2709
477023a6
JM		 2710#define GEN_STUXF(width, opc, type) \
2711GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2712{ \
76a66253 2713 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2714 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2715 return; \
2716 } \
76a66253 2717 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2718 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2719 return; \
9a64fbe4 2720 } \
76a66253
JM		 2721 gen_addr_reg_index(ctx); \
2722 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 2723 op_ldst(st##width); \
79aceca5 2724 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2725}
2726
477023a6
JM		 2727#define GEN_STXF(width, opc2, opc3, type) \
2728GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2729{ \
76a66253 2730 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2731 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2732 return; \
2733 } \
76a66253
JM		 2734 gen_addr_reg_index(ctx); \
2735 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 2736 op_ldst(st##width); \
79aceca5
FB		 2737}
2738
477023a6 2739#define GEN_STFS(width, op, type) \
9a64fbe4 2740OP_ST_TABLE(width); \
477023a6
JM		 2741GEN_STF(width, op | 0x20, type); \
2742GEN_STUF(width, op | 0x21, type); \
2743GEN_STUXF(width, op | 0x01, type); \
2744GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 2745
2746/* stfd stfdu stfdux stfdx */
477023a6 2747GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 2748/* stfs stfsu stfsux stfsx */
477023a6 2749GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 2750
2751/* Optional: */
2752/* stfiwx */
477023a6
JM		 2753OP_ST_TABLE(fiwx);
2754GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 2755
2756/*** Branch ***/
b068d6a7
JM		 2757static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2758 target_ulong dest)
c1942362
FB		 2759{
2760 TranslationBlock *tb;
2761 tb = ctx->tb;
2762 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
2763 if (n == 0)
2764 gen_op_goto_tb0(TBPARAM(tb));
2765 else
2766 gen_op_goto_tb1(TBPARAM(tb));
d9bce9d9
JM		 2767 gen_set_T1(dest);
2768#if defined(TARGET_PPC64)
2769 if (ctx->sf_mode)
2770 gen_op_b_T1_64();
2771 else
2772#endif
2773 gen_op_b_T1();
c1942362 2774 gen_op_set_T0((long)tb + n);
ea4e754f
FB		 2775 if (ctx->singlestep_enabled)
2776 gen_op_debug();
c1942362
FB		 2777 gen_op_exit_tb();
2778 } else {
d9bce9d9
JM		 2779 gen_set_T1(dest);
2780#if defined(TARGET_PPC64)
2781 if (ctx->sf_mode)
2782 gen_op_b_T1_64();
2783 else
2784#endif
2785 gen_op_b_T1();
76a66253 2786 gen_op_reset_T0();
ea4e754f
FB		 2787 if (ctx->singlestep_enabled)
2788 gen_op_debug();
c1942362
FB		 2789 gen_op_exit_tb();
2790 }
c53be334
FB		 2791}
2792
b068d6a7 2793static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 2794{
2795#if defined(TARGET_PPC64)
2796 if (ctx->sf_mode != 0 && (nip >> 32))
2797 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2798 else
2799#endif
2800 gen_op_setlr(ctx->nip);
2801}
2802
79aceca5
FB		 2803/* b ba bl bla */
2804GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2805{
76a66253 2806 target_ulong li, target;
38a64f9d
FB		 2807
2808 /* sign extend LI */
76a66253 2809#if defined(TARGET_PPC64)
d9bce9d9
JM		 2810 if (ctx->sf_mode)
2811 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
2812 else
76a66253 2813#endif
d9bce9d9 2814 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 2815 if (likely(AA(ctx->opcode) == 0))
046d6672 2816 target = ctx->nip + li - 4;
79aceca5 2817 else
9a64fbe4 2818 target = li;
d9bce9d9 2819#if defined(TARGET_PPC64)
e1833e1f
JM		 2820 if (!ctx->sf_mode)
2821 target = (uint32_t)target;
d9bce9d9 2822#endif
e1833e1f
JM		 2823 if (LK(ctx->opcode))
2824 gen_setlr(ctx, ctx->nip);
c1942362 2825 gen_goto_tb(ctx, 0, target);
e1833e1f 2826 ctx->exception = POWERPC_EXCP_BRANCH;
79aceca5
FB		 2827}
2828
e98a6e40
FB		 2829#define BCOND_IM 0
2830#define BCOND_LR 1
2831#define BCOND_CTR 2
2832
b068d6a7 2833static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 2834{
76a66253
JM		 2835 target_ulong target = 0;
2836 target_ulong li;
d9bce9d9
JM		 2837 uint32_t bo = BO(ctx->opcode);
2838 uint32_t bi = BI(ctx->opcode);
2839 uint32_t mask;
e98a6e40 2840
e98a6e40 2841 if ((bo & 0x4) == 0)
d9bce9d9 2842 gen_op_dec_ctr();
e98a6e40
FB		 2843 switch(type) {
2844 case BCOND_IM:
76a66253
JM		 2845 li = (target_long)((int16_t)(BD(ctx->opcode)));
2846 if (likely(AA(ctx->opcode) == 0)) {
046d6672 2847 target = ctx->nip + li - 4;
e98a6e40
FB		 2848 } else {
2849 target = li;
2850 }
e1833e1f
JM		 2851#if defined(TARGET_PPC64)
2852 if (!ctx->sf_mode)
2853 target = (uint32_t)target;
2854#endif
e98a6e40
FB		 2855 break;
2856 case BCOND_CTR:
2857 gen_op_movl_T1_ctr();
2858 break;
2859 default:
2860 case BCOND_LR:
2861 gen_op_movl_T1_lr();
2862 break;
2863 }
e1833e1f
JM		 2864 if (LK(ctx->opcode))
2865 gen_setlr(ctx, ctx->nip);
e98a6e40 2866 if (bo & 0x10) {
d9bce9d9
JM		 2867 /* No CR condition */
2868 switch (bo & 0x6) {
2869 case 0:
2870#if defined(TARGET_PPC64)
2871 if (ctx->sf_mode)
2872 gen_op_test_ctr_64();
2873 else
2874#endif
2875 gen_op_test_ctr();
2876 break;
2877 case 2:
2878#if defined(TARGET_PPC64)
2879 if (ctx->sf_mode)
2880 gen_op_test_ctrz_64();
2881 else
2882#endif
2883 gen_op_test_ctrz();
e98a6e40 2884 break;
e98a6e40 2885 default:
d9bce9d9
JM		 2886 case 4:
2887 case 6:
e98a6e40 2888 if (type == BCOND_IM) {
c1942362 2889 gen_goto_tb(ctx, 0, target);
056b05f8 2890 goto out;
e98a6e40 2891 } else {
d9bce9d9
JM		 2892#if defined(TARGET_PPC64)
2893 if (ctx->sf_mode)
2894 gen_op_b_T1_64();
2895 else
2896#endif
2897 gen_op_b_T1();
76a66253 2898 gen_op_reset_T0();
056b05f8 2899 goto no_test;
e98a6e40 2900 }
056b05f8 2901 break;
e98a6e40 2902 }
d9bce9d9
JM		 2903 } else {
2904 mask = 1 << (3 - (bi & 0x03));
2905 gen_op_load_crf_T0(bi >> 2);
2906 if (bo & 0x8) {
2907 switch (bo & 0x6) {
2908 case 0:
2909#if defined(TARGET_PPC64)
2910 if (ctx->sf_mode)
2911 gen_op_test_ctr_true_64(mask);
2912 else
2913#endif
2914 gen_op_test_ctr_true(mask);
2915 break;
2916 case 2:
2917#if defined(TARGET_PPC64)
2918 if (ctx->sf_mode)
2919 gen_op_test_ctrz_true_64(mask);
2920 else
2921#endif
2922 gen_op_test_ctrz_true(mask);
2923 break;
2924 default:
2925 case 4:
2926 case 6:
e98a6e40 2927 gen_op_test_true(mask);
d9bce9d9
JM		 2928 break;
2929 }
2930 } else {
2931 switch (bo & 0x6) {
2932 case 0:
2933#if defined(TARGET_PPC64)
2934 if (ctx->sf_mode)
2935 gen_op_test_ctr_false_64(mask);
2936 else
2937#endif
2938 gen_op_test_ctr_false(mask);
3b46e624 2939 break;
d9bce9d9
JM		 2940 case 2:
2941#if defined(TARGET_PPC64)
2942 if (ctx->sf_mode)
2943 gen_op_test_ctrz_false_64(mask);
2944 else
2945#endif
2946 gen_op_test_ctrz_false(mask);
2947 break;
e98a6e40 2948 default:
d9bce9d9
JM		 2949 case 4:
2950 case 6:
e98a6e40 2951 gen_op_test_false(mask);
d9bce9d9
JM		 2952 break;
2953 }
2954 }
2955 }
e98a6e40 2956 if (type == BCOND_IM) {
c53be334
FB		 2957 int l1 = gen_new_label();
2958 gen_op_jz_T0(l1);
c1942362 2959 gen_goto_tb(ctx, 0, target);
c53be334 2960 gen_set_label(l1);
c1942362 2961 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 2962 } else {
d9bce9d9
JM		 2963#if defined(TARGET_PPC64)
2964 if (ctx->sf_mode)
2965 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
2966 else
2967#endif
2968 gen_op_btest_T1(ctx->nip);
76a66253 2969 gen_op_reset_T0();
36081602 2970 no_test:
08e46e54
JM		 2971 if (ctx->singlestep_enabled)
2972 gen_op_debug();
2973 gen_op_exit_tb();
2974 }
056b05f8 2975 out:
e1833e1f 2976 ctx->exception = POWERPC_EXCP_BRANCH;
e98a6e40
FB		 2977}
2978
2979GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 2980{
e98a6e40
FB		 2981 gen_bcond(ctx, BCOND_IM);
2982}
2983
2984GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 2985{
e98a6e40
FB		 2986 gen_bcond(ctx, BCOND_CTR);
2987}
2988
2989GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 2990{
e98a6e40
FB		 2991 gen_bcond(ctx, BCOND_LR);
2992}
79aceca5
FB		 2993
2994/*** Condition register logical ***/
2995#define GEN_CRLOGIC(op, opc) \
2996GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
2997{ \
fc0d441e
JM		 2998 uint8_t bitmask; \
2999 int sh; \
79aceca5 3000 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
fc0d441e
JM		 3001 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3002 if (sh > 0) \
3003 gen_op_srli_T0(sh); \
3004 else if (sh < 0) \
3005 gen_op_sli_T0(-sh); \
79aceca5 3006 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
fc0d441e
JM		 3007 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3008 if (sh > 0) \
3009 gen_op_srli_T1(sh); \
3010 else if (sh < 0) \
3011 gen_op_sli_T1(-sh); \
79aceca5 3012 gen_op_##op(); \
fc0d441e
JM		 3013 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3014 gen_op_andi_T0(bitmask); \
79aceca5 3015 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
fc0d441e
JM		 3016 gen_op_andi_T1(~bitmask); \
3017 gen_op_or(); \
3018 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 3019}
3020
3021/* crand */
76a66253 3022GEN_CRLOGIC(and, 0x08);
79aceca5 3023/* crandc */
76a66253 3024GEN_CRLOGIC(andc, 0x04);
79aceca5 3025/* creqv */
76a66253 3026GEN_CRLOGIC(eqv, 0x09);
79aceca5 3027/* crnand */
76a66253 3028GEN_CRLOGIC(nand, 0x07);
79aceca5 3029/* crnor */
76a66253 3030GEN_CRLOGIC(nor, 0x01);
79aceca5 3031/* cror */
76a66253 3032GEN_CRLOGIC(or, 0x0E);
79aceca5 3033/* crorc */
76a66253 3034GEN_CRLOGIC(orc, 0x0D);
79aceca5 3035/* crxor */
76a66253 3036GEN_CRLOGIC(xor, 0x06);
79aceca5
FB		 3037/* mcrf */
3038GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3039{
3040 gen_op_load_crf_T0(crfS(ctx->opcode));
3041 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 3042}
3043
3044/*** System linkage ***/
3045/* rfi (supervisor only) */
76a66253 3046GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3047{
9a64fbe4 3048#if defined(CONFIG_USER_ONLY)
e1833e1f 3049 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3050#else
3051 /* Restore CPU state */
76a66253 3052 if (unlikely(!ctx->supervisor)) {
e1833e1f 3053 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3054 return;
9a64fbe4 3055 }
a42bd6cc 3056 gen_op_rfi();
e1833e1f 3057 GEN_SYNC(ctx);
9a64fbe4 3058#endif
79aceca5
FB		 3059}
3060
426613db 3061#if defined(TARGET_PPC64)
a750fc0b 3062GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3063{
3064#if defined(CONFIG_USER_ONLY)
e1833e1f 3065 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3066#else
3067 /* Restore CPU state */
3068 if (unlikely(!ctx->supervisor)) {
e1833e1f 3069 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3070 return;
3071 }
a42bd6cc 3072 gen_op_rfid();
e1833e1f 3073 GEN_SYNC(ctx);
426613db
JM		 3074#endif
3075}
426613db 3076
be147d08
JM		 3077GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3078{
3079#if defined(CONFIG_USER_ONLY)
3080 GEN_EXCP_PRIVOPC(ctx);
3081#else
3082 /* Restore CPU state */
3083 if (unlikely(ctx->supervisor <= 1)) {
3084 GEN_EXCP_PRIVOPC(ctx);
3085 return;
3086 }
3087 gen_op_hrfid();
3088 GEN_SYNC(ctx);
3089#endif
3090}
3091#endif
3092
79aceca5 3093/* sc */
417bf010
JM		 3094#if defined(CONFIG_USER_ONLY)
3095#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3096#else
3097#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3098#endif
e1833e1f 3099GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3100{
e1833e1f
JM		 3101 uint32_t lev;
3102
3103 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3104 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3105}
3106
3107/*** Trap ***/
3108/* tw */
76a66253 3109GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3110{
9a64fbe4
FB		 3111 gen_op_load_gpr_T0(rA(ctx->opcode));
3112 gen_op_load_gpr_T1(rB(ctx->opcode));
a0ae05aa 3113 /* Update the nip since this might generate a trap exception */
d9bce9d9 3114 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3115 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3116}
3117
3118/* twi */
3119GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3120{
9a64fbe4 3121 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 3122 gen_set_T1(SIMM(ctx->opcode));
3123 /* Update the nip since this might generate a trap exception */
3124 gen_update_nip(ctx, ctx->nip);
76a66253 3125 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3126}
3127
d9bce9d9
JM		 3128#if defined(TARGET_PPC64)
3129/* td */
3130GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3131{
3132 gen_op_load_gpr_T0(rA(ctx->opcode));
3133 gen_op_load_gpr_T1(rB(ctx->opcode));
3134 /* Update the nip since this might generate a trap exception */
3135 gen_update_nip(ctx, ctx->nip);
3136 gen_op_td(TO(ctx->opcode));
3137}
3138
3139/* tdi */
3140GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3141{
3142 gen_op_load_gpr_T0(rA(ctx->opcode));
3143 gen_set_T1(SIMM(ctx->opcode));
3144 /* Update the nip since this might generate a trap exception */
3145 gen_update_nip(ctx, ctx->nip);
3146 gen_op_td(TO(ctx->opcode));
3147}
3148#endif
3149
79aceca5 3150/*** Processor control ***/
79aceca5
FB		 3151/* mcrxr */
3152GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3153{
3154 gen_op_load_xer_cr();
3155 gen_op_store_T0_crf(crfD(ctx->opcode));
e864cabd
JM		 3156 gen_op_clear_xer_ov();
3157 gen_op_clear_xer_ca();
79aceca5
FB		 3158}
3159
3160/* mfcr */
76a66253 3161GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3162{
76a66253 3163 uint32_t crm, crn;
3b46e624 3164
76a66253
JM		 3165 if (likely(ctx->opcode & 0x00100000)) {
3166 crm = CRM(ctx->opcode);
3167 if (likely((crm ^ (crm - 1)) == 0)) {
3168 crn = ffs(crm);
3169 gen_op_load_cro(7 - crn);
3170 }
d9bce9d9
JM		 3171 } else {
3172 gen_op_load_cr();
3173 }
79aceca5 3174 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 3175}
3176
3177/* mfmsr */
3178GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3179{
9a64fbe4 3180#if defined(CONFIG_USER_ONLY)
e1833e1f 3181 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3182#else
76a66253 3183 if (unlikely(!ctx->supervisor)) {
e1833e1f 3184 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3185 return;
9a64fbe4 3186 }
79aceca5
FB		 3187 gen_op_load_msr();
3188 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 3189#endif
79aceca5
FB		 3190}
3191
a11b8151 3192#if 1
6f2d8978 3193#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3194#else
3195static void spr_noaccess (void *opaque, int sprn)
3196{
3197 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3198 printf("ERROR: try to access SPR %d !\n", sprn);
3199}
3200#define SPR_NOACCESS (&spr_noaccess)
3201#endif
3202
79aceca5 3203/* mfspr */
b068d6a7 3204static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3205{
3fc6c082 3206 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3207 uint32_t sprn = SPR(ctx->opcode);
3208
3fc6c082 3209#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3210 if (ctx->supervisor == 2)
3211 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3212 else if (ctx->supervisor)
3fc6c082
FB		 3213 read_cb = ctx->spr_cb[sprn].oea_read;
3214 else
9a64fbe4 3215#endif
3fc6c082 3216 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3217 if (likely(read_cb != NULL)) {
3218 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082
FB		 3219 (*read_cb)(ctx, sprn);
3220 gen_op_store_T0_gpr(rD(ctx->opcode));
3221 } else {
3222 /* Privilege exception */
9fceefa7
JM		 3223 /* This is a hack to avoid warnings when running Linux:
3224 * this OS breaks the PowerPC virtualisation model,
3225 * allowing userland application to read the PVR
3226 */
3227 if (sprn != SPR_PVR) {
3228 if (loglevel != 0) {
077fc206
JM		 3229 fprintf(logfile, "Trying to read privileged spr %d %03x at"
3230 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3231 }
077fc206
JM		 3232 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3233 sprn, sprn, ctx->nip);
f24e5695 3234 }
e1833e1f 3235 GEN_EXCP_PRIVREG(ctx);
79aceca5 3236 }
3fc6c082
FB		 3237 } else {
3238 /* Not defined */
4a057712 3239 if (loglevel != 0) {
077fc206
JM		 3240 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3241 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3242 }
077fc206
JM		 3243 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3244 sprn, sprn, ctx->nip);
e1833e1f
JM		 3245 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3246 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3247 }
79aceca5
FB		 3248}
3249
3fc6c082 3250GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3251{
3fc6c082 3252 gen_op_mfspr(ctx);
76a66253 3253}
3fc6c082
FB		 3254
3255/* mftb */
a750fc0b 3256GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3257{
3258 gen_op_mfspr(ctx);
79aceca5
FB		 3259}
3260
3261/* mtcrf */
8dd4983c 3262GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3263{
76a66253 3264 uint32_t crm, crn;
3b46e624 3265
79aceca5 3266 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 3267 crm = CRM(ctx->opcode);
3268 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3269 crn = ffs(crm);
3270 gen_op_srli_T0(crn * 4);
3271 gen_op_andi_T0(0xF);
3272 gen_op_store_cro(7 - crn);
3273 } else {
3274 gen_op_store_cr(crm);
3275 }
79aceca5
FB		 3276}
3277
3278/* mtmsr */
426613db 3279#if defined(TARGET_PPC64)
be147d08 3280GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3281{
3282#if defined(CONFIG_USER_ONLY)
e1833e1f 3283 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3284#else
3285 if (unlikely(!ctx->supervisor)) {
e1833e1f 3286 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3287 return;
3288 }
426613db 3289 gen_op_load_gpr_T0(rS(ctx->opcode));
be147d08
JM		 3290 if (ctx->opcode & 0x00010000) {
3291 /* Special form that does not need any synchronisation */
3292 gen_op_update_riee();
3293 } else {
056b05f8
JM		 3294 /* XXX: we need to update nip before the store
3295 * if we enter power saving mode, we will exit the loop
3296 * directly from ppc_store_msr
3297 */
be147d08
JM		 3298 gen_update_nip(ctx, ctx->nip);
3299 gen_op_store_msr();
3300 /* Must stop the translation as machine state (may have) changed */
3301 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3302 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3303 }
426613db
JM		 3304#endif
3305}
3306#endif
3307
79aceca5
FB		 3308GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3309{
9a64fbe4 3310#if defined(CONFIG_USER_ONLY)
e1833e1f 3311 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3312#else
76a66253 3313 if (unlikely(!ctx->supervisor)) {
e1833e1f 3314 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3315 return;
9a64fbe4 3316 }
79aceca5 3317 gen_op_load_gpr_T0(rS(ctx->opcode));
be147d08
JM		 3318 if (ctx->opcode & 0x00010000) {
3319 /* Special form that does not need any synchronisation */
3320 gen_op_update_riee();
3321 } else {
056b05f8
JM		 3322 /* XXX: we need to update nip before the store
3323 * if we enter power saving mode, we will exit the loop
3324 * directly from ppc_store_msr
3325 */
be147d08 3326 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3327#if defined(TARGET_PPC64)
be147d08
JM		 3328 if (!ctx->sf_mode)
3329 gen_op_store_msr_32();
3330 else
d9bce9d9 3331#endif
be147d08
JM		 3332 gen_op_store_msr();
3333 /* Must stop the translation as machine state (may have) changed */
3334 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3335 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3336 }
9a64fbe4 3337#endif
79aceca5
FB		 3338}
3339
3340/* mtspr */
3341GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3342{
3fc6c082 3343 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3344 uint32_t sprn = SPR(ctx->opcode);
3345
3fc6c082 3346#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3347 if (ctx->supervisor == 2)
3348 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3349 else if (ctx->supervisor)
3fc6c082
FB		 3350 write_cb = ctx->spr_cb[sprn].oea_write;
3351 else
9a64fbe4 3352#endif
3fc6c082 3353 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3354 if (likely(write_cb != NULL)) {
3355 if (likely(write_cb != SPR_NOACCESS)) {
3fc6c082
FB		 3356 gen_op_load_gpr_T0(rS(ctx->opcode));
3357 (*write_cb)(ctx, sprn);
3358 } else {
3359 /* Privilege exception */
4a057712 3360 if (loglevel != 0) {
077fc206
JM		 3361 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3362 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3363 }
077fc206
JM		 3364 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3365 sprn, sprn, ctx->nip);
e1833e1f 3366 GEN_EXCP_PRIVREG(ctx);
76a66253 3367 }
3fc6c082
FB		 3368 } else {
3369 /* Not defined */
4a057712 3370 if (loglevel != 0) {
077fc206
JM		 3371 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3372 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3373 }
077fc206
JM		 3374 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3375 sprn, sprn, ctx->nip);
e1833e1f
JM		 3376 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3377 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3378 }
79aceca5
FB		 3379}
3380
3381/*** Cache management ***/
79aceca5 3382/* dcbf */
0db1b20e 3383GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3384{
dac454af 3385 /* XXX: specification says this is treated as a load by the MMU */
76a66253 3386 gen_addr_reg_index(ctx);
a541f297 3387 op_ldst(lbz);
79aceca5
FB		 3388}
3389
3390/* dcbi (Supervisor only) */
9a64fbe4 3391GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3392{
a541f297 3393#if defined(CONFIG_USER_ONLY)
e1833e1f 3394 GEN_EXCP_PRIVOPC(ctx);
a541f297 3395#else
76a66253 3396 if (unlikely(!ctx->supervisor)) {
e1833e1f 3397 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3398 return;
9a64fbe4 3399 }
76a66253
JM		 3400 gen_addr_reg_index(ctx);
3401 /* XXX: specification says this should be treated as a store by the MMU */
dac454af 3402 op_ldst(lbz);
a541f297
FB		 3403 op_ldst(stb);
3404#endif
79aceca5
FB		 3405}
3406
3407/* dcdst */
9a64fbe4 3408GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3409{
76a66253
JM		 3410 /* XXX: specification say this is treated as a load by the MMU */
3411 gen_addr_reg_index(ctx);
a541f297 3412 op_ldst(lbz);
79aceca5
FB		 3413}
3414
3415/* dcbt */
0db1b20e 3416GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3417{
0db1b20e 3418 /* interpreted as no-op */
76a66253
JM		 3419 /* XXX: specification say this is treated as a load by the MMU
3420 * but does not generate any exception
3421 */
79aceca5
FB		 3422}
3423
3424/* dcbtst */
0db1b20e 3425GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3426{
0db1b20e 3427 /* interpreted as no-op */
76a66253
JM		 3428 /* XXX: specification say this is treated as a load by the MMU
3429 * but does not generate any exception
3430 */
79aceca5
FB		 3431}
3432
3433/* dcbz */
d63001d1 3434#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 3435static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3436 /* 32 bytes cache line size */
d63001d1 3437 {
7863667f
JM		 3438#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3439#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3440#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3441#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3442#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3443#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3444#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3445#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3446 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 3447 },
7863667f 3448 /* 64 bytes cache line size */
d63001d1 3449 {
7863667f
JM		 3450#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3451#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3452#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3453#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3454#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3455#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3456#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3457#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3458 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 3459 },
7863667f 3460 /* 128 bytes cache line size */
d63001d1 3461 {
7863667f
JM		 3462#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3463#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3464#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3465#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3466#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3467#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3468#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3469#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3470 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 3471 },
7863667f 3472 /* tunable cache line size */
d63001d1 3473 {
7863667f
JM		 3474#define gen_op_dcbz_le_raw gen_op_dcbz_raw
3475#define gen_op_dcbz_le_user gen_op_dcbz_user
3476#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3477#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3478#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3479#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3480#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3481#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3482 GEN_MEM_FUNCS(dcbz),
d63001d1 3483 },
76a66253 3484};
9a64fbe4 3485
b068d6a7
JM		 3486static always_inline void handler_dcbz (DisasContext *ctx,
3487 int dcache_line_size)
d63001d1
JM		 3488{
3489 int n;
3490
3491 switch (dcache_line_size) {
3492 case 32:
3493 n = 0;
3494 break;
3495 case 64:
3496 n = 1;
3497 break;
3498 case 128:
3499 n = 2;
3500 break;
3501 default:
3502 n = 3;
3503 break;
3504 }
3505 op_dcbz(n);
3506}
3507
3508GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 3509{
76a66253 3510 gen_addr_reg_index(ctx);
d63001d1
JM		 3511 handler_dcbz(ctx, ctx->dcache_line_size);
3512 gen_op_check_reservation();
3513}
3514
c7697e1f 3515GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1
JM		 3516{
3517 gen_addr_reg_index(ctx);
3518 if (ctx->opcode & 0x00200000)
3519 handler_dcbz(ctx, ctx->dcache_line_size);
3520 else
3521 handler_dcbz(ctx, -1);
4b3686fa 3522 gen_op_check_reservation();
79aceca5
FB		 3523}
3524
3525/* icbi */
36f69651 3526#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 3527#define gen_op_icbi_le_raw gen_op_icbi_raw
3528#define gen_op_icbi_le_user gen_op_icbi_user
3529#define gen_op_icbi_le_kernel gen_op_icbi_kernel
3530#define gen_op_icbi_le_hypv gen_op_icbi_hypv
3531#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3532#define gen_op_icbi_le_64_user gen_op_icbi_64_user
3533#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3534#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3535static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3536 GEN_MEM_FUNCS(icbi),
36f69651 3537};
e1833e1f 3538
1b413d55 3539GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 3540{
30032c94
JM		 3541 /* NIP cannot be restored if the memory exception comes from an helper */
3542 gen_update_nip(ctx, ctx->nip - 4);
76a66253 3543 gen_addr_reg_index(ctx);
36f69651 3544 op_icbi();
79aceca5
FB		 3545}
3546
3547/* Optional: */
3548/* dcba */
a750fc0b 3549GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 3550{
0db1b20e
JM		 3551 /* interpreted as no-op */
3552 /* XXX: specification say this is treated as a store by the MMU
3553 * but does not generate any exception
3554 */
79aceca5
FB		 3555}
3556
3557/*** Segment register manipulation ***/
3558/* Supervisor only: */
3559/* mfsr */
3560GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3561{
9a64fbe4 3562#if defined(CONFIG_USER_ONLY)
e1833e1f 3563 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3564#else
76a66253 3565 if (unlikely(!ctx->supervisor)) {
e1833e1f 3566 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3567 return;
9a64fbe4 3568 }
76a66253
JM		 3569 gen_op_set_T1(SR(ctx->opcode));
3570 gen_op_load_sr();
9a64fbe4
FB		 3571 gen_op_store_T0_gpr(rD(ctx->opcode));
3572#endif
79aceca5
FB		 3573}
3574
3575/* mfsrin */
9a64fbe4 3576GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 3577{
9a64fbe4 3578#if defined(CONFIG_USER_ONLY)
e1833e1f 3579 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3580#else
76a66253 3581 if (unlikely(!ctx->supervisor)) {
e1833e1f 3582 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3583 return;
9a64fbe4
FB		 3584 }
3585 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 3586 gen_op_srli_T1(28);
3587 gen_op_load_sr();
9a64fbe4
FB		 3588 gen_op_store_T0_gpr(rD(ctx->opcode));
3589#endif
79aceca5
FB		 3590}
3591
3592/* mtsr */
e63c59cb 3593GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 3594{
9a64fbe4 3595#if defined(CONFIG_USER_ONLY)
e1833e1f 3596 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3597#else
76a66253 3598 if (unlikely(!ctx->supervisor)) {
e1833e1f 3599 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3600 return;
9a64fbe4
FB		 3601 }
3602 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 3603 gen_op_set_T1(SR(ctx->opcode));
3604 gen_op_store_sr();
9a64fbe4 3605#endif
79aceca5
FB		 3606}
3607
3608/* mtsrin */
9a64fbe4 3609GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 3610{
9a64fbe4 3611#if defined(CONFIG_USER_ONLY)
e1833e1f 3612 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3613#else
76a66253 3614 if (unlikely(!ctx->supervisor)) {
e1833e1f 3615 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3616 return;
9a64fbe4
FB		 3617 }
3618 gen_op_load_gpr_T0(rS(ctx->opcode));
3619 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 3620 gen_op_srli_T1(28);
3621 gen_op_store_sr();
9a64fbe4 3622#endif
79aceca5
FB		 3623}
3624
12de9a39
JM		 3625#if defined(TARGET_PPC64)
3626/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3627/* mfsr */
c7697e1f 3628GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 3629{
3630#if defined(CONFIG_USER_ONLY)
3631 GEN_EXCP_PRIVREG(ctx);
3632#else
3633 if (unlikely(!ctx->supervisor)) {
3634 GEN_EXCP_PRIVREG(ctx);
3635 return;
3636 }
3637 gen_op_set_T1(SR(ctx->opcode));
3638 gen_op_load_slb();
3639 gen_op_store_T0_gpr(rD(ctx->opcode));
3640#endif
3641}
3642
3643/* mfsrin */
c7697e1f
JM		 3644GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3645 PPC_SEGMENT_64B)
12de9a39
JM		 3646{
3647#if defined(CONFIG_USER_ONLY)
3648 GEN_EXCP_PRIVREG(ctx);
3649#else
3650 if (unlikely(!ctx->supervisor)) {
3651 GEN_EXCP_PRIVREG(ctx);
3652 return;
3653 }
3654 gen_op_load_gpr_T1(rB(ctx->opcode));
3655 gen_op_srli_T1(28);
3656 gen_op_load_slb();
3657 gen_op_store_T0_gpr(rD(ctx->opcode));
3658#endif
3659}
3660
3661/* mtsr */
c7697e1f 3662GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 3663{
3664#if defined(CONFIG_USER_ONLY)
3665 GEN_EXCP_PRIVREG(ctx);
3666#else
3667 if (unlikely(!ctx->supervisor)) {
3668 GEN_EXCP_PRIVREG(ctx);
3669 return;
3670 }
3671 gen_op_load_gpr_T0(rS(ctx->opcode));
3672 gen_op_set_T1(SR(ctx->opcode));
3673 gen_op_store_slb();
3674#endif
3675}
3676
3677/* mtsrin */
c7697e1f
JM		 3678GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3679 PPC_SEGMENT_64B)
12de9a39
JM		 3680{
3681#if defined(CONFIG_USER_ONLY)
3682 GEN_EXCP_PRIVREG(ctx);
3683#else
3684 if (unlikely(!ctx->supervisor)) {
3685 GEN_EXCP_PRIVREG(ctx);
3686 return;
3687 }
3688 gen_op_load_gpr_T0(rS(ctx->opcode));
3689 gen_op_load_gpr_T1(rB(ctx->opcode));
3690 gen_op_srli_T1(28);
3691 gen_op_store_slb();
3692#endif
3693}
3694#endif /* defined(TARGET_PPC64) */
3695
79aceca5
FB		 3696/*** Lookaside buffer management ***/
3697/* Optional & supervisor only: */
3698/* tlbia */
3fc6c082 3699GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 3700{
9a64fbe4 3701#if defined(CONFIG_USER_ONLY)
e1833e1f 3702 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3703#else
76a66253 3704 if (unlikely(!ctx->supervisor)) {
4a057712 3705 if (loglevel != 0)
9fddaa0c 3706 fprintf(logfile, "%s: ! supervisor\n", __func__);
e1833e1f 3707 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3708 return;
9a64fbe4
FB		 3709 }
3710 gen_op_tlbia();
3711#endif
79aceca5
FB		 3712}
3713
3714/* tlbie */
76a66253 3715GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 3716{
9a64fbe4 3717#if defined(CONFIG_USER_ONLY)
e1833e1f 3718 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3719#else
76a66253 3720 if (unlikely(!ctx->supervisor)) {
e1833e1f 3721 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3722 return;
9a64fbe4
FB		 3723 }
3724 gen_op_load_gpr_T0(rB(ctx->opcode));
d9bce9d9
JM		 3725#if defined(TARGET_PPC64)
3726 if (ctx->sf_mode)
3727 gen_op_tlbie_64();
3728 else
3729#endif
3730 gen_op_tlbie();
9a64fbe4 3731#endif
79aceca5
FB		 3732}
3733
3734/* tlbsync */
76a66253 3735GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 3736{
9a64fbe4 3737#if defined(CONFIG_USER_ONLY)
e1833e1f 3738 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3739#else
76a66253 3740 if (unlikely(!ctx->supervisor)) {
e1833e1f 3741 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3742 return;
9a64fbe4
FB		 3743 }
3744 /* This has no effect: it should ensure that all previous
3745 * tlbie have completed
3746 */
e1833e1f 3747 GEN_STOP(ctx);
9a64fbe4 3748#endif
79aceca5
FB		 3749}
3750
426613db
JM		 3751#if defined(TARGET_PPC64)
3752/* slbia */
3753GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
3754{
3755#if defined(CONFIG_USER_ONLY)
e1833e1f 3756 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3757#else
3758 if (unlikely(!ctx->supervisor)) {
4a057712 3759 if (loglevel != 0)
426613db 3760 fprintf(logfile, "%s: ! supervisor\n", __func__);
e1833e1f 3761 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3762 return;
3763 }
3764 gen_op_slbia();
426613db
JM		 3765#endif
3766}
3767
3768/* slbie */
3769GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3770{
3771#if defined(CONFIG_USER_ONLY)
e1833e1f 3772 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3773#else
3774 if (unlikely(!ctx->supervisor)) {
e1833e1f 3775 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3776 return;
3777 }
3778 gen_op_load_gpr_T0(rB(ctx->opcode));
3779 gen_op_slbie();
426613db
JM		 3780#endif
3781}
3782#endif
3783
79aceca5
FB		 3784/*** External control ***/
3785/* Optional: */
9a64fbe4
FB		 3786#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3787#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 3788static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
3789 GEN_MEM_FUNCS(eciwx),
111bfab3 3790};
7863667f
JM		 3791static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
3792 GEN_MEM_FUNCS(ecowx),
111bfab3 3793};
9a64fbe4 3794
111bfab3 3795/* eciwx */
79aceca5
FB		 3796GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
3797{
9a64fbe4 3798 /* Should check EAR[E] & alignment ! */
76a66253
JM		 3799 gen_addr_reg_index(ctx);
3800 op_eciwx();
3801 gen_op_store_T0_gpr(rD(ctx->opcode));
3802}
3803
3804/* ecowx */
3805GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3806{
3807 /* Should check EAR[E] & alignment ! */
3808 gen_addr_reg_index(ctx);
3809 gen_op_load_gpr_T1(rS(ctx->opcode));
3810 op_ecowx();
3811}
3812
3813/* PowerPC 601 specific instructions */
3814/* abs - abs. */
3815GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3816{
3817 gen_op_load_gpr_T0(rA(ctx->opcode));
3818 gen_op_POWER_abs();
3819 gen_op_store_T0_gpr(rD(ctx->opcode));
3820 if (unlikely(Rc(ctx->opcode) != 0))
3821 gen_set_Rc0(ctx);
3822}
3823
3824/* abso - abso. */
3825GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3826{
3827 gen_op_load_gpr_T0(rA(ctx->opcode));
3828 gen_op_POWER_abso();
3829 gen_op_store_T0_gpr(rD(ctx->opcode));
3830 if (unlikely(Rc(ctx->opcode) != 0))
3831 gen_set_Rc0(ctx);
3832}
3833
3834/* clcs */
a750fc0b 3835GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253
JM		 3836{
3837 gen_op_load_gpr_T0(rA(ctx->opcode));
3838 gen_op_POWER_clcs();
c7697e1f 3839 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 3840 gen_op_store_T0_gpr(rD(ctx->opcode));
3841}
3842
3843/* div - div. */
3844GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3845{
3846 gen_op_load_gpr_T0(rA(ctx->opcode));
3847 gen_op_load_gpr_T1(rB(ctx->opcode));
3848 gen_op_POWER_div();
3849 gen_op_store_T0_gpr(rD(ctx->opcode));
3850 if (unlikely(Rc(ctx->opcode) != 0))
3851 gen_set_Rc0(ctx);
3852}
3853
3854/* divo - divo. */
3855GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3856{
3857 gen_op_load_gpr_T0(rA(ctx->opcode));
3858 gen_op_load_gpr_T1(rB(ctx->opcode));
3859 gen_op_POWER_divo();
3860 gen_op_store_T0_gpr(rD(ctx->opcode));
3861 if (unlikely(Rc(ctx->opcode) != 0))
3862 gen_set_Rc0(ctx);
3863}
3864
3865/* divs - divs. */
3866GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3867{
3868 gen_op_load_gpr_T0(rA(ctx->opcode));
3869 gen_op_load_gpr_T1(rB(ctx->opcode));
3870 gen_op_POWER_divs();
3871 gen_op_store_T0_gpr(rD(ctx->opcode));
3872 if (unlikely(Rc(ctx->opcode) != 0))
3873 gen_set_Rc0(ctx);
3874}
3875
3876/* divso - divso. */
3877GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3878{
3879 gen_op_load_gpr_T0(rA(ctx->opcode));
3880 gen_op_load_gpr_T1(rB(ctx->opcode));
3881 gen_op_POWER_divso();
3882 gen_op_store_T0_gpr(rD(ctx->opcode));
3883 if (unlikely(Rc(ctx->opcode) != 0))
3884 gen_set_Rc0(ctx);
3885}
3886
3887/* doz - doz. */
3888GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3889{
3890 gen_op_load_gpr_T0(rA(ctx->opcode));
3891 gen_op_load_gpr_T1(rB(ctx->opcode));
3892 gen_op_POWER_doz();
3893 gen_op_store_T0_gpr(rD(ctx->opcode));
3894 if (unlikely(Rc(ctx->opcode) != 0))
3895 gen_set_Rc0(ctx);
3896}
3897
3898/* dozo - dozo. */
3899GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3900{
3901 gen_op_load_gpr_T0(rA(ctx->opcode));
3902 gen_op_load_gpr_T1(rB(ctx->opcode));
3903 gen_op_POWER_dozo();
3904 gen_op_store_T0_gpr(rD(ctx->opcode));
3905 if (unlikely(Rc(ctx->opcode) != 0))
3906 gen_set_Rc0(ctx);
3907}
3908
3909/* dozi */
3910GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
3911{
3912 gen_op_load_gpr_T0(rA(ctx->opcode));
3913 gen_op_set_T1(SIMM(ctx->opcode));
3914 gen_op_POWER_doz();
3915 gen_op_store_T0_gpr(rD(ctx->opcode));
3916}
3917
7863667f
JM		 3918/* As lscbx load from memory byte after byte, it's always endian safe.
3919 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3920 */
2857068e 3921#define op_POWER_lscbx(start, ra, rb) \
76a66253 3922(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 3923#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
3924#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
3925#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
3926#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
3927#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
3928#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
3929#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
3930#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
3931#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
3932#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
3933#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
3934#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
3935static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
3936 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 3937};
76a66253
JM		 3938
3939/* lscbx - lscbx. */
3940GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
3941{
3942 int ra = rA(ctx->opcode);
3943 int rb = rB(ctx->opcode);
3944
3945 gen_addr_reg_index(ctx);
3946 if (ra == 0) {
3947 ra = rb;
3948 }
3949 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3950 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 3951 gen_op_load_xer_bc();
3952 gen_op_load_xer_cmp();
3953 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3954 gen_op_store_xer_bc();
3955 if (unlikely(Rc(ctx->opcode) != 0))
3956 gen_set_Rc0(ctx);
3957}
3958
3959/* maskg - maskg. */
3960GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
3961{
3962 gen_op_load_gpr_T0(rS(ctx->opcode));
3963 gen_op_load_gpr_T1(rB(ctx->opcode));
3964 gen_op_POWER_maskg();
3965 gen_op_store_T0_gpr(rA(ctx->opcode));
3966 if (unlikely(Rc(ctx->opcode) != 0))
3967 gen_set_Rc0(ctx);
3968}
3969
3970/* maskir - maskir. */
3971GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
3972{
3973 gen_op_load_gpr_T0(rA(ctx->opcode));
3974 gen_op_load_gpr_T1(rS(ctx->opcode));
3975 gen_op_load_gpr_T2(rB(ctx->opcode));
3976 gen_op_POWER_maskir();
3977 gen_op_store_T0_gpr(rA(ctx->opcode));
3978 if (unlikely(Rc(ctx->opcode) != 0))
3979 gen_set_Rc0(ctx);
3980}
3981
3982/* mul - mul. */
3983GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
3984{
3985 gen_op_load_gpr_T0(rA(ctx->opcode));
3986 gen_op_load_gpr_T1(rB(ctx->opcode));
3987 gen_op_POWER_mul();
3988 gen_op_store_T0_gpr(rD(ctx->opcode));
3989 if (unlikely(Rc(ctx->opcode) != 0))
3990 gen_set_Rc0(ctx);
3991}
3992
3993/* mulo - mulo. */
3994GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
3995{
3996 gen_op_load_gpr_T0(rA(ctx->opcode));
3997 gen_op_load_gpr_T1(rB(ctx->opcode));
3998 gen_op_POWER_mulo();
3999 gen_op_store_T0_gpr(rD(ctx->opcode));
4000 if (unlikely(Rc(ctx->opcode) != 0))
4001 gen_set_Rc0(ctx);
4002}
4003
4004/* nabs - nabs. */
4005GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4006{
4007 gen_op_load_gpr_T0(rA(ctx->opcode));
4008 gen_op_POWER_nabs();
4009 gen_op_store_T0_gpr(rD(ctx->opcode));
4010 if (unlikely(Rc(ctx->opcode) != 0))
4011 gen_set_Rc0(ctx);
4012}
4013
4014/* nabso - nabso. */
4015GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4016{
4017 gen_op_load_gpr_T0(rA(ctx->opcode));
4018 gen_op_POWER_nabso();
4019 gen_op_store_T0_gpr(rD(ctx->opcode));
4020 if (unlikely(Rc(ctx->opcode) != 0))
4021 gen_set_Rc0(ctx);
4022}
4023
4024/* rlmi - rlmi. */
4025GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4026{
4027 uint32_t mb, me;
4028
4029 mb = MB(ctx->opcode);
4030 me = ME(ctx->opcode);
4031 gen_op_load_gpr_T0(rS(ctx->opcode));
4032 gen_op_load_gpr_T1(rA(ctx->opcode));
4033 gen_op_load_gpr_T2(rB(ctx->opcode));
4034 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4035 gen_op_store_T0_gpr(rA(ctx->opcode));
4036 if (unlikely(Rc(ctx->opcode) != 0))
4037 gen_set_Rc0(ctx);
4038}
4039
4040/* rrib - rrib. */
4041GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4042{
4043 gen_op_load_gpr_T0(rS(ctx->opcode));
4044 gen_op_load_gpr_T1(rA(ctx->opcode));
4045 gen_op_load_gpr_T2(rB(ctx->opcode));
4046 gen_op_POWER_rrib();
4047 gen_op_store_T0_gpr(rA(ctx->opcode));
4048 if (unlikely(Rc(ctx->opcode) != 0))
4049 gen_set_Rc0(ctx);
4050}
4051
4052/* sle - sle. */
4053GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4054{
4055 gen_op_load_gpr_T0(rS(ctx->opcode));
4056 gen_op_load_gpr_T1(rB(ctx->opcode));
4057 gen_op_POWER_sle();
4058 gen_op_store_T0_gpr(rA(ctx->opcode));
4059 if (unlikely(Rc(ctx->opcode) != 0))
4060 gen_set_Rc0(ctx);
4061}
4062
4063/* sleq - sleq. */
4064GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4065{
4066 gen_op_load_gpr_T0(rS(ctx->opcode));
4067 gen_op_load_gpr_T1(rB(ctx->opcode));
4068 gen_op_POWER_sleq();
4069 gen_op_store_T0_gpr(rA(ctx->opcode));
4070 if (unlikely(Rc(ctx->opcode) != 0))
4071 gen_set_Rc0(ctx);
4072}
4073
4074/* sliq - sliq. */
4075GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4076{
4077 gen_op_load_gpr_T0(rS(ctx->opcode));
4078 gen_op_set_T1(SH(ctx->opcode));
4079 gen_op_POWER_sle();
4080 gen_op_store_T0_gpr(rA(ctx->opcode));
4081 if (unlikely(Rc(ctx->opcode) != 0))
4082 gen_set_Rc0(ctx);
4083}
4084
4085/* slliq - slliq. */
4086GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4087{
4088 gen_op_load_gpr_T0(rS(ctx->opcode));
4089 gen_op_set_T1(SH(ctx->opcode));
4090 gen_op_POWER_sleq();
4091 gen_op_store_T0_gpr(rA(ctx->opcode));
4092 if (unlikely(Rc(ctx->opcode) != 0))
4093 gen_set_Rc0(ctx);
4094}
4095
4096/* sllq - sllq. */
4097GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4098{
4099 gen_op_load_gpr_T0(rS(ctx->opcode));
4100 gen_op_load_gpr_T1(rB(ctx->opcode));
4101 gen_op_POWER_sllq();
4102 gen_op_store_T0_gpr(rA(ctx->opcode));
4103 if (unlikely(Rc(ctx->opcode) != 0))
4104 gen_set_Rc0(ctx);
4105}
4106
4107/* slq - slq. */
4108GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4109{
4110 gen_op_load_gpr_T0(rS(ctx->opcode));
4111 gen_op_load_gpr_T1(rB(ctx->opcode));
4112 gen_op_POWER_slq();
4113 gen_op_store_T0_gpr(rA(ctx->opcode));
4114 if (unlikely(Rc(ctx->opcode) != 0))
4115 gen_set_Rc0(ctx);
4116}
4117
d9bce9d9 4118/* sraiq - sraiq. */
76a66253
JM		 4119GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4120{
4121 gen_op_load_gpr_T0(rS(ctx->opcode));
4122 gen_op_set_T1(SH(ctx->opcode));
4123 gen_op_POWER_sraq();
4124 gen_op_store_T0_gpr(rA(ctx->opcode));
4125 if (unlikely(Rc(ctx->opcode) != 0))
4126 gen_set_Rc0(ctx);
4127}
4128
4129/* sraq - sraq. */
4130GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4131{
4132 gen_op_load_gpr_T0(rS(ctx->opcode));
4133 gen_op_load_gpr_T1(rB(ctx->opcode));
4134 gen_op_POWER_sraq();
4135 gen_op_store_T0_gpr(rA(ctx->opcode));
4136 if (unlikely(Rc(ctx->opcode) != 0))
4137 gen_set_Rc0(ctx);
4138}
4139
4140/* sre - sre. */
4141GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4142{
4143 gen_op_load_gpr_T0(rS(ctx->opcode));
4144 gen_op_load_gpr_T1(rB(ctx->opcode));
4145 gen_op_POWER_sre();
4146 gen_op_store_T0_gpr(rA(ctx->opcode));
4147 if (unlikely(Rc(ctx->opcode) != 0))
4148 gen_set_Rc0(ctx);
4149}
4150
4151/* srea - srea. */
4152GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4153{
4154 gen_op_load_gpr_T0(rS(ctx->opcode));
4155 gen_op_load_gpr_T1(rB(ctx->opcode));
4156 gen_op_POWER_srea();
4157 gen_op_store_T0_gpr(rA(ctx->opcode));
4158 if (unlikely(Rc(ctx->opcode) != 0))
4159 gen_set_Rc0(ctx);
4160}
4161
4162/* sreq */
4163GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4164{
4165 gen_op_load_gpr_T0(rS(ctx->opcode));
4166 gen_op_load_gpr_T1(rB(ctx->opcode));
4167 gen_op_POWER_sreq();
4168 gen_op_store_T0_gpr(rA(ctx->opcode));
4169 if (unlikely(Rc(ctx->opcode) != 0))
4170 gen_set_Rc0(ctx);
4171}
4172
4173/* sriq */
4174GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4175{
4176 gen_op_load_gpr_T0(rS(ctx->opcode));
4177 gen_op_set_T1(SH(ctx->opcode));
4178 gen_op_POWER_srq();
4179 gen_op_store_T0_gpr(rA(ctx->opcode));
4180 if (unlikely(Rc(ctx->opcode) != 0))
4181 gen_set_Rc0(ctx);
4182}
4183
4184/* srliq */
4185GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4186{
4187 gen_op_load_gpr_T0(rS(ctx->opcode));
4188 gen_op_load_gpr_T1(rB(ctx->opcode));
4189 gen_op_set_T1(SH(ctx->opcode));
4190 gen_op_POWER_srlq();
4191 gen_op_store_T0_gpr(rA(ctx->opcode));
4192 if (unlikely(Rc(ctx->opcode) != 0))
4193 gen_set_Rc0(ctx);
4194}
4195
4196/* srlq */
4197GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4198{
4199 gen_op_load_gpr_T0(rS(ctx->opcode));
4200 gen_op_load_gpr_T1(rB(ctx->opcode));
4201 gen_op_POWER_srlq();
4202 gen_op_store_T0_gpr(rA(ctx->opcode));
4203 if (unlikely(Rc(ctx->opcode) != 0))
4204 gen_set_Rc0(ctx);
4205}
4206
4207/* srq */
4208GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4209{
4210 gen_op_load_gpr_T0(rS(ctx->opcode));
4211 gen_op_load_gpr_T1(rB(ctx->opcode));
4212 gen_op_POWER_srq();
4213 gen_op_store_T0_gpr(rA(ctx->opcode));
4214 if (unlikely(Rc(ctx->opcode) != 0))
4215 gen_set_Rc0(ctx);
4216}
4217
4218/* PowerPC 602 specific instructions */
4219/* dsa */
4220GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4221{
4222 /* XXX: TODO */
e1833e1f 4223 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4224}
4225
4226/* esa */
4227GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4228{
4229 /* XXX: TODO */
e1833e1f 4230 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4231}
4232
4233/* mfrom */
4234GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4235{
4236#if defined(CONFIG_USER_ONLY)
e1833e1f 4237 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4238#else
4239 if (unlikely(!ctx->supervisor)) {
e1833e1f 4240 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4241 return;
4242 }
4243 gen_op_load_gpr_T0(rA(ctx->opcode));
4244 gen_op_602_mfrom();
4245 gen_op_store_T0_gpr(rD(ctx->opcode));
4246#endif
4247}
4248
4249/* 602 - 603 - G2 TLB management */
4250/* tlbld */
c7697e1f 4251GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4252{
4253#if defined(CONFIG_USER_ONLY)
e1833e1f 4254 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4255#else
4256 if (unlikely(!ctx->supervisor)) {
e1833e1f 4257 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4258 return;
4259 }
4260 gen_op_load_gpr_T0(rB(ctx->opcode));
4261 gen_op_6xx_tlbld();
76a66253
JM		 4262#endif
4263}
4264
4265/* tlbli */
c7697e1f 4266GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4267{
4268#if defined(CONFIG_USER_ONLY)
e1833e1f 4269 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4270#else
4271 if (unlikely(!ctx->supervisor)) {
e1833e1f 4272 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4273 return;
4274 }
4275 gen_op_load_gpr_T0(rB(ctx->opcode));
4276 gen_op_6xx_tlbli();
76a66253
JM		 4277#endif
4278}
4279
7dbe11ac
JM		 4280/* 74xx TLB management */
4281/* tlbld */
c7697e1f 4282GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4283{
4284#if defined(CONFIG_USER_ONLY)
4285 GEN_EXCP_PRIVOPC(ctx);
4286#else
4287 if (unlikely(!ctx->supervisor)) {
4288 GEN_EXCP_PRIVOPC(ctx);
4289 return;
4290 }
4291 gen_op_load_gpr_T0(rB(ctx->opcode));
4292 gen_op_74xx_tlbld();
4293#endif
4294}
4295
4296/* tlbli */
c7697e1f 4297GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4298{
4299#if defined(CONFIG_USER_ONLY)
4300 GEN_EXCP_PRIVOPC(ctx);
4301#else
4302 if (unlikely(!ctx->supervisor)) {
4303 GEN_EXCP_PRIVOPC(ctx);
4304 return;
4305 }
4306 gen_op_load_gpr_T0(rB(ctx->opcode));
4307 gen_op_74xx_tlbli();
4308#endif
4309}
4310
76a66253
JM		 4311/* POWER instructions not in PowerPC 601 */
4312/* clf */
4313GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4314{
4315 /* Cache line flush: implemented as no-op */
4316}
4317
4318/* cli */
4319GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4320{
7f75ffd3 4321 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4322#if defined(CONFIG_USER_ONLY)
e1833e1f 4323 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4324#else
4325 if (unlikely(!ctx->supervisor)) {
e1833e1f 4326 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4327 return;
4328 }
4329#endif
4330}
4331
4332/* dclst */
4333GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4334{
4335 /* Data cache line store: treated as no-op */
4336}
4337
4338GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4339{
4340#if defined(CONFIG_USER_ONLY)
e1833e1f 4341 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4342#else
4343 if (unlikely(!ctx->supervisor)) {
e1833e1f 4344 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4345 return;
4346 }
4347 int ra = rA(ctx->opcode);
4348 int rd = rD(ctx->opcode);
4349
4350 gen_addr_reg_index(ctx);
4351 gen_op_POWER_mfsri();
4352 gen_op_store_T0_gpr(rd);
4353 if (ra != 0 && ra != rd)
4354 gen_op_store_T1_gpr(ra);
4355#endif
4356}
4357
4358GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4359{
4360#if defined(CONFIG_USER_ONLY)
e1833e1f 4361 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4362#else
4363 if (unlikely(!ctx->supervisor)) {
e1833e1f 4364 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4365 return;
4366 }
4367 gen_addr_reg_index(ctx);
4368 gen_op_POWER_rac();
4369 gen_op_store_T0_gpr(rD(ctx->opcode));
4370#endif
4371}
4372
4373GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4374{
4375#if defined(CONFIG_USER_ONLY)
e1833e1f 4376 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4377#else
4378 if (unlikely(!ctx->supervisor)) {
e1833e1f 4379 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4380 return;
4381 }
4382 gen_op_POWER_rfsvc();
e1833e1f 4383 GEN_SYNC(ctx);
76a66253
JM		 4384#endif
4385}
4386
4387/* svc is not implemented for now */
4388
4389/* POWER2 specific instructions */
4390/* Quad manipulation (load/store two floats at a time) */
7863667f 4391/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 4392#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4393#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 4394#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4395#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4396#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4397#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4398#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4399#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4400#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4401#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4402#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4403#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4404#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4405#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4406#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4407#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4408#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4409#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4410static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4411 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 4412};
7863667f
JM		 4413static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4414 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 4415};
76a66253
JM		 4416
4417/* lfq */
4418GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4419{
4420 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4421 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4422 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4423 op_POWER2_lfq();
4424 gen_op_store_FT0_fpr(rD(ctx->opcode));
4425 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4426}
4427
4428/* lfqu */
4429GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4430{
4431 int ra = rA(ctx->opcode);
4432
4433 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4434 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4435 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4436 op_POWER2_lfq();
4437 gen_op_store_FT0_fpr(rD(ctx->opcode));
4438 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4439 if (ra != 0)
4440 gen_op_store_T0_gpr(ra);
4441}
4442
4443/* lfqux */
4444GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4445{
4446 int ra = rA(ctx->opcode);
4447
4448 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4449 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4450 gen_addr_reg_index(ctx);
4451 op_POWER2_lfq();
4452 gen_op_store_FT0_fpr(rD(ctx->opcode));
4453 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4454 if (ra != 0)
4455 gen_op_store_T0_gpr(ra);
4456}
4457
4458/* lfqx */
4459GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4460{
4461 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4462 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4463 gen_addr_reg_index(ctx);
4464 op_POWER2_lfq();
4465 gen_op_store_FT0_fpr(rD(ctx->opcode));
4466 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4467}
4468
4469/* stfq */
4470GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4471{
4472 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4473 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4474 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4475 gen_op_load_fpr_FT0(rS(ctx->opcode));
4476 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4477 op_POWER2_stfq();
4478}
4479
4480/* stfqu */
4481GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4482{
4483 int ra = rA(ctx->opcode);
4484
4485 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4486 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4487 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4488 gen_op_load_fpr_FT0(rS(ctx->opcode));
4489 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4490 op_POWER2_stfq();
4491 if (ra != 0)
4492 gen_op_store_T0_gpr(ra);
4493}
4494
4495/* stfqux */
4496GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4497{
4498 int ra = rA(ctx->opcode);
4499
4500 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4501 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4502 gen_addr_reg_index(ctx);
4503 gen_op_load_fpr_FT0(rS(ctx->opcode));
4504 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4505 op_POWER2_stfq();
4506 if (ra != 0)
4507 gen_op_store_T0_gpr(ra);
4508}
4509
4510/* stfqx */
4511GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4512{
4513 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4514 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4515 gen_addr_reg_index(ctx);
4516 gen_op_load_fpr_FT0(rS(ctx->opcode));
4517 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4518 op_POWER2_stfq();
4519}
4520
4521/* BookE specific instructions */
2662a059 4522/* XXX: not implemented on 440 ? */
a750fc0b 4523GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
76a66253
JM		 4524{
4525 /* XXX: TODO */
e1833e1f 4526 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4527}
4528
2662a059 4529/* XXX: not implemented on 440 ? */
a750fc0b 4530GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
76a66253
JM		 4531{
4532#if defined(CONFIG_USER_ONLY)
e1833e1f 4533 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4534#else
4535 if (unlikely(!ctx->supervisor)) {
e1833e1f 4536 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4537 return;
4538 }
4539 gen_addr_reg_index(ctx);
4540 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 4541#if defined(TARGET_PPC64)
4542 if (ctx->sf_mode)
4543 gen_op_tlbie_64();
4544 else
4545#endif
4546 gen_op_tlbie();
76a66253
JM		 4547#endif
4548}
4549
4550/* All 405 MAC instructions are translated here */
b068d6a7
JM		 4551static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4552 int opc2, int opc3,
4553 int ra, int rb, int rt, int Rc)
76a66253
JM		 4554{
4555 gen_op_load_gpr_T0(ra);
4556 gen_op_load_gpr_T1(rb);
4557 switch (opc3 & 0x0D) {
4558 case 0x05:
4559 /* macchw - macchw. - macchwo - macchwo. */
4560 /* macchws - macchws. - macchwso - macchwso. */
4561 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4562 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4563 /* mulchw - mulchw. */
4564 gen_op_405_mulchw();
4565 break;
4566 case 0x04:
4567 /* macchwu - macchwu. - macchwuo - macchwuo. */
4568 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4569 /* mulchwu - mulchwu. */
4570 gen_op_405_mulchwu();
4571 break;
4572 case 0x01:
4573 /* machhw - machhw. - machhwo - machhwo. */
4574 /* machhws - machhws. - machhwso - machhwso. */
4575 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4576 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4577 /* mulhhw - mulhhw. */
4578 gen_op_405_mulhhw();
4579 break;
4580 case 0x00:
4581 /* machhwu - machhwu. - machhwuo - machhwuo. */
4582 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4583 /* mulhhwu - mulhhwu. */
4584 gen_op_405_mulhhwu();
4585 break;
4586 case 0x0D:
4587 /* maclhw - maclhw. - maclhwo - maclhwo. */
4588 /* maclhws - maclhws. - maclhwso - maclhwso. */
4589 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4590 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4591 /* mullhw - mullhw. */
4592 gen_op_405_mullhw();
4593 break;
4594 case 0x0C:
4595 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4596 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4597 /* mullhwu - mullhwu. */
4598 gen_op_405_mullhwu();
4599 break;
4600 }
4601 if (opc2 & 0x02) {
4602 /* nmultiply-and-accumulate (0x0E) */
4603 gen_op_neg();
4604 }
4605 if (opc2 & 0x04) {
4606 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4607 gen_op_load_gpr_T2(rt);
4608 gen_op_move_T1_T0();
4609 gen_op_405_add_T0_T2();
4610 }
4611 if (opc3 & 0x10) {
4612 /* Check overflow */
4613 if (opc3 & 0x01)
c3e10c7b 4614 gen_op_check_addo();
76a66253
JM		 4615 else
4616 gen_op_405_check_ovu();
4617 }
4618 if (opc3 & 0x02) {
4619 /* Saturate */
4620 if (opc3 & 0x01)
4621 gen_op_405_check_sat();
4622 else
4623 gen_op_405_check_satu();
4624 }
4625 gen_op_store_T0_gpr(rt);
4626 if (unlikely(Rc) != 0) {
4627 /* Update Rc0 */
4628 gen_set_Rc0(ctx);
4629 }
4630}
4631
a750fc0b
JM		 4632#define GEN_MAC_HANDLER(name, opc2, opc3) \
4633GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 4634{ \
4635 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4636 rD(ctx->opcode), Rc(ctx->opcode)); \
4637}
4638
4639/* macchw - macchw. */
a750fc0b 4640GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 4641/* macchwo - macchwo. */
a750fc0b 4642GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 4643/* macchws - macchws. */
a750fc0b 4644GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 4645/* macchwso - macchwso. */
a750fc0b 4646GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 4647/* macchwsu - macchwsu. */
a750fc0b 4648GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 4649/* macchwsuo - macchwsuo. */
a750fc0b 4650GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 4651/* macchwu - macchwu. */
a750fc0b 4652GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 4653/* macchwuo - macchwuo. */
a750fc0b 4654GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 4655/* machhw - machhw. */
a750fc0b 4656GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 4657/* machhwo - machhwo. */
a750fc0b 4658GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 4659/* machhws - machhws. */
a750fc0b 4660GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 4661/* machhwso - machhwso. */
a750fc0b 4662GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 4663/* machhwsu - machhwsu. */
a750fc0b 4664GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 4665/* machhwsuo - machhwsuo. */
a750fc0b 4666GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 4667/* machhwu - machhwu. */
a750fc0b 4668GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 4669/* machhwuo - machhwuo. */
a750fc0b 4670GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 4671/* maclhw - maclhw. */
a750fc0b 4672GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 4673/* maclhwo - maclhwo. */
a750fc0b 4674GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 4675/* maclhws - maclhws. */
a750fc0b 4676GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 4677/* maclhwso - maclhwso. */
a750fc0b 4678GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 4679/* maclhwu - maclhwu. */
a750fc0b 4680GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 4681/* maclhwuo - maclhwuo. */
a750fc0b 4682GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 4683/* maclhwsu - maclhwsu. */
a750fc0b 4684GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 4685/* maclhwsuo - maclhwsuo. */
a750fc0b 4686GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 4687/* nmacchw - nmacchw. */
a750fc0b 4688GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 4689/* nmacchwo - nmacchwo. */
a750fc0b 4690GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 4691/* nmacchws - nmacchws. */
a750fc0b 4692GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 4693/* nmacchwso - nmacchwso. */
a750fc0b 4694GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 4695/* nmachhw - nmachhw. */
a750fc0b 4696GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 4697/* nmachhwo - nmachhwo. */
a750fc0b 4698GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 4699/* nmachhws - nmachhws. */
a750fc0b 4700GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 4701/* nmachhwso - nmachhwso. */
a750fc0b 4702GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 4703/* nmaclhw - nmaclhw. */
a750fc0b 4704GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 4705/* nmaclhwo - nmaclhwo. */
a750fc0b 4706GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 4707/* nmaclhws - nmaclhws. */
a750fc0b 4708GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 4709/* nmaclhwso - nmaclhwso. */
a750fc0b 4710GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 4711
4712/* mulchw - mulchw. */
a750fc0b 4713GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 4714/* mulchwu - mulchwu. */
a750fc0b 4715GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 4716/* mulhhw - mulhhw. */
a750fc0b 4717GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 4718/* mulhhwu - mulhhwu. */
a750fc0b 4719GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 4720/* mullhw - mullhw. */
a750fc0b 4721GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 4722/* mullhwu - mullhwu. */
a750fc0b 4723GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 4724
4725/* mfdcr */
4726GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
4727{
4728#if defined(CONFIG_USER_ONLY)
e1833e1f 4729 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4730#else
4731 uint32_t dcrn = SPR(ctx->opcode);
4732
4733 if (unlikely(!ctx->supervisor)) {
e1833e1f 4734 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4735 return;
4736 }
a42bd6cc
JM		 4737 gen_op_set_T0(dcrn);
4738 gen_op_load_dcr();
76a66253
JM		 4739 gen_op_store_T0_gpr(rD(ctx->opcode));
4740#endif
4741}
4742
4743/* mtdcr */
4744GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
4745{
4746#if defined(CONFIG_USER_ONLY)
e1833e1f 4747 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4748#else
4749 uint32_t dcrn = SPR(ctx->opcode);
4750
4751 if (unlikely(!ctx->supervisor)) {
e1833e1f 4752 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4753 return;
4754 }
a42bd6cc
JM		 4755 gen_op_set_T0(dcrn);
4756 gen_op_load_gpr_T1(rS(ctx->opcode));
4757 gen_op_store_dcr();
4758#endif
4759}
4760
4761/* mfdcrx */
2662a059 4762/* XXX: not implemented on 440 ? */
a750fc0b 4763GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
a42bd6cc
JM		 4764{
4765#if defined(CONFIG_USER_ONLY)
e1833e1f 4766 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4767#else
4768 if (unlikely(!ctx->supervisor)) {
e1833e1f 4769 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4770 return;
4771 }
4772 gen_op_load_gpr_T0(rA(ctx->opcode));
4773 gen_op_load_dcr();
4774 gen_op_store_T0_gpr(rD(ctx->opcode));
a750fc0b 4775 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 4776#endif
4777}
4778
4779/* mtdcrx */
2662a059 4780/* XXX: not implemented on 440 ? */
a750fc0b 4781GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
a42bd6cc
JM		 4782{
4783#if defined(CONFIG_USER_ONLY)
e1833e1f 4784 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4785#else
4786 if (unlikely(!ctx->supervisor)) {
e1833e1f 4787 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4788 return;
4789 }
4790 gen_op_load_gpr_T0(rA(ctx->opcode));
4791 gen_op_load_gpr_T1(rS(ctx->opcode));
4792 gen_op_store_dcr();
a750fc0b 4793 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 4794#endif
4795}
4796
a750fc0b
JM		 4797/* mfdcrux (PPC 460) : user-mode access to DCR */
4798GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
4799{
4800 gen_op_load_gpr_T0(rA(ctx->opcode));
4801 gen_op_load_dcr();
4802 gen_op_store_T0_gpr(rD(ctx->opcode));
4803 /* Note: Rc update flag set leads to undefined state of Rc0 */
4804}
4805
4806/* mtdcrux (PPC 460) : user-mode access to DCR */
4807GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
4808{
4809 gen_op_load_gpr_T0(rA(ctx->opcode));
4810 gen_op_load_gpr_T1(rS(ctx->opcode));
4811 gen_op_store_dcr();
4812 /* Note: Rc update flag set leads to undefined state of Rc0 */
4813}
4814
76a66253
JM		 4815/* dccci */
4816GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4817{
4818#if defined(CONFIG_USER_ONLY)
e1833e1f 4819 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4820#else
4821 if (unlikely(!ctx->supervisor)) {
e1833e1f 4822 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4823 return;
4824 }
4825 /* interpreted as no-op */
4826#endif
4827}
4828
4829/* dcread */
4830GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4831{
4832#if defined(CONFIG_USER_ONLY)
e1833e1f 4833 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4834#else
4835 if (unlikely(!ctx->supervisor)) {
e1833e1f 4836 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4837 return;
4838 }
4839 gen_addr_reg_index(ctx);
4840 op_ldst(lwz);
4841 gen_op_store_T0_gpr(rD(ctx->opcode));
4842#endif
4843}
4844
4845/* icbt */
c7697e1f 4846GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 4847{
4848 /* interpreted as no-op */
4849 /* XXX: specification say this is treated as a load by the MMU
4850 * but does not generate any exception
4851 */
4852}
4853
4854/* iccci */
4855GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
4856{
4857#if defined(CONFIG_USER_ONLY)
e1833e1f 4858 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4859#else
4860 if (unlikely(!ctx->supervisor)) {
e1833e1f 4861 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4862 return;
4863 }
4864 /* interpreted as no-op */
4865#endif
4866}
4867
4868/* icread */
4869GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
4870{
4871#if defined(CONFIG_USER_ONLY)
e1833e1f 4872 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4873#else
4874 if (unlikely(!ctx->supervisor)) {
e1833e1f 4875 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4876 return;
4877 }
4878 /* interpreted as no-op */
4879#endif
4880}
4881
4882/* rfci (supervisor only) */
c7697e1f 4883GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 4884{
4885#if defined(CONFIG_USER_ONLY)
e1833e1f 4886 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4887#else
4888 if (unlikely(!ctx->supervisor)) {
e1833e1f 4889 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4890 return;
4891 }
4892 /* Restore CPU state */
4893 gen_op_40x_rfci();
e1833e1f 4894 GEN_SYNC(ctx);
a42bd6cc
JM		 4895#endif
4896}
4897
4898GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4899{
4900#if defined(CONFIG_USER_ONLY)
e1833e1f 4901 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4902#else
4903 if (unlikely(!ctx->supervisor)) {
e1833e1f 4904 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4905 return;
4906 }
4907 /* Restore CPU state */
4908 gen_op_rfci();
e1833e1f 4909 GEN_SYNC(ctx);
a42bd6cc
JM		 4910#endif
4911}
4912
4913/* BookE specific */
2662a059 4914/* XXX: not implemented on 440 ? */
a750fc0b 4915GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
76a66253
JM		 4916{
4917#if defined(CONFIG_USER_ONLY)
e1833e1f 4918 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4919#else
4920 if (unlikely(!ctx->supervisor)) {
e1833e1f 4921 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4922 return;
4923 }
4924 /* Restore CPU state */
a42bd6cc 4925 gen_op_rfdi();
e1833e1f 4926 GEN_SYNC(ctx);
76a66253
JM		 4927#endif
4928}
4929
2662a059 4930/* XXX: not implemented on 440 ? */
a750fc0b 4931GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 4932{
4933#if defined(CONFIG_USER_ONLY)
e1833e1f 4934 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4935#else
4936 if (unlikely(!ctx->supervisor)) {
e1833e1f 4937 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4938 return;
4939 }
4940 /* Restore CPU state */
4941 gen_op_rfmci();
e1833e1f 4942 GEN_SYNC(ctx);
a42bd6cc
JM		 4943#endif
4944}
5eb7995e 4945
d9bce9d9 4946/* TLB management - PowerPC 405 implementation */
76a66253 4947/* tlbre */
c7697e1f 4948GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 4949{
4950#if defined(CONFIG_USER_ONLY)
e1833e1f 4951 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4952#else
4953 if (unlikely(!ctx->supervisor)) {
e1833e1f 4954 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4955 return;
4956 }
4957 switch (rB(ctx->opcode)) {
4958 case 0:
9a64fbe4 4959 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 4960 gen_op_4xx_tlbre_hi();
4961 gen_op_store_T0_gpr(rD(ctx->opcode));
4962 break;
4963 case 1:
4964 gen_op_load_gpr_T0(rA(ctx->opcode));
4965 gen_op_4xx_tlbre_lo();
4966 gen_op_store_T0_gpr(rD(ctx->opcode));
4967 break;
4968 default:
e1833e1f 4969 GEN_EXCP_INVAL(ctx);
76a66253 4970 break;
9a64fbe4 4971 }
76a66253
JM		 4972#endif
4973}
4974
d9bce9d9 4975/* tlbsx - tlbsx. */
c7697e1f 4976GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 4977{
4978#if defined(CONFIG_USER_ONLY)
e1833e1f 4979 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4980#else
4981 if (unlikely(!ctx->supervisor)) {
e1833e1f 4982 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4983 return;
4984 }
4985 gen_addr_reg_index(ctx);
daf4f96e 4986 gen_op_4xx_tlbsx();
76a66253 4987 if (Rc(ctx->opcode))
daf4f96e 4988 gen_op_4xx_tlbsx_check();
9a64fbe4 4989 gen_op_store_T0_gpr(rD(ctx->opcode));
76a66253 4990#endif
79aceca5
FB		 4991}
4992
76a66253 4993/* tlbwe */
c7697e1f 4994GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 4995{
76a66253 4996#if defined(CONFIG_USER_ONLY)
e1833e1f 4997 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4998#else
4999 if (unlikely(!ctx->supervisor)) {
e1833e1f 5000 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5001 return;
5002 }
5003 switch (rB(ctx->opcode)) {
5004 case 0:
9a64fbe4 5005 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 5006 gen_op_load_gpr_T1(rS(ctx->opcode));
5007 gen_op_4xx_tlbwe_hi();
5008 break;
5009 case 1:
5010 gen_op_load_gpr_T0(rA(ctx->opcode));
5011 gen_op_load_gpr_T1(rS(ctx->opcode));
5012 gen_op_4xx_tlbwe_lo();
5013 break;
5014 default:
e1833e1f 5015 GEN_EXCP_INVAL(ctx);
76a66253 5016 break;
9a64fbe4 5017 }
76a66253
JM		 5018#endif
5019}
5020
a4bb6c3e 5021/* TLB management - PowerPC 440 implementation */
5eb7995e 5022/* tlbre */
c7697e1f 5023GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5024{
5025#if defined(CONFIG_USER_ONLY)
e1833e1f 5026 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5027#else
5028 if (unlikely(!ctx->supervisor)) {
e1833e1f 5029 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5030 return;
5031 }
5032 switch (rB(ctx->opcode)) {
5033 case 0:
5eb7995e 5034 case 1:
5eb7995e
JM		 5035 case 2:
5036 gen_op_load_gpr_T0(rA(ctx->opcode));
a4bb6c3e 5037 gen_op_440_tlbre(rB(ctx->opcode));
5eb7995e
JM		 5038 gen_op_store_T0_gpr(rD(ctx->opcode));
5039 break;
5040 default:
e1833e1f 5041 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5042 break;
5043 }
5044#endif
5045}
5046
5047/* tlbsx - tlbsx. */
c7697e1f 5048GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5049{
5050#if defined(CONFIG_USER_ONLY)
e1833e1f 5051 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5052#else
5053 if (unlikely(!ctx->supervisor)) {
e1833e1f 5054 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5055 return;
5056 }
5057 gen_addr_reg_index(ctx);
daf4f96e 5058 gen_op_440_tlbsx();
5eb7995e 5059 if (Rc(ctx->opcode))
daf4f96e 5060 gen_op_4xx_tlbsx_check();
5eb7995e
JM		 5061 gen_op_store_T0_gpr(rD(ctx->opcode));
5062#endif
5063}
5064
5065/* tlbwe */
c7697e1f 5066GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5067{
5068#if defined(CONFIG_USER_ONLY)
e1833e1f 5069 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5070#else
5071 if (unlikely(!ctx->supervisor)) {
e1833e1f 5072 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5073 return;
5074 }
5075 switch (rB(ctx->opcode)) {
5076 case 0:
5eb7995e 5077 case 1:
5eb7995e
JM		 5078 case 2:
5079 gen_op_load_gpr_T0(rA(ctx->opcode));
5080 gen_op_load_gpr_T1(rS(ctx->opcode));
a4bb6c3e 5081 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5082 break;
5083 default:
e1833e1f 5084 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5085 break;
5086 }
5087#endif
5088}
5089
76a66253
JM		 5090/* wrtee */
5091GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
5092{
5093#if defined(CONFIG_USER_ONLY)
e1833e1f 5094 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5095#else
5096 if (unlikely(!ctx->supervisor)) {
e1833e1f 5097 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5098 return;
5099 }
5100 gen_op_load_gpr_T0(rD(ctx->opcode));
a42bd6cc 5101 gen_op_wrte();
dee96f6c
JM		 5102 /* Stop translation to have a chance to raise an exception
5103 * if we just set msr_ee to 1
5104 */
e1833e1f 5105 GEN_STOP(ctx);
76a66253
JM		 5106#endif
5107}
5108
5109/* wrteei */
5110GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
5111{
5112#if defined(CONFIG_USER_ONLY)
e1833e1f 5113 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5114#else
5115 if (unlikely(!ctx->supervisor)) {
e1833e1f 5116 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5117 return;
5118 }
5119 gen_op_set_T0(ctx->opcode & 0x00010000);
a42bd6cc 5120 gen_op_wrte();
dee96f6c
JM		 5121 /* Stop translation to have a chance to raise an exception
5122 * if we just set msr_ee to 1
5123 */
e1833e1f 5124 GEN_STOP(ctx);
76a66253
JM		 5125#endif
5126}
5127
08e46e54 5128/* PowerPC 440 specific instructions */
76a66253
JM		 5129/* dlmzb */
5130GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5131{
5132 gen_op_load_gpr_T0(rS(ctx->opcode));
5133 gen_op_load_gpr_T1(rB(ctx->opcode));
5134 gen_op_440_dlmzb();
5135 gen_op_store_T0_gpr(rA(ctx->opcode));
5136 gen_op_store_xer_bc();
5137 if (Rc(ctx->opcode)) {
5138 gen_op_440_dlmzb_update_Rc();
5139 gen_op_store_T0_crf(0);
5140 }
5141}
5142
5143/* mbar replaces eieio on 440 */
5144GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5145{
5146 /* interpreted as no-op */
5147}
5148
5149/* msync replaces sync on 440 */
0db1b20e 5150GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5151{
5152 /* interpreted as no-op */
5153}
5154
5155/* icbt */
c7697e1f 5156GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5157{
5158 /* interpreted as no-op */
5159 /* XXX: specification say this is treated as a load by the MMU
5160 * but does not generate any exception
5161 */
79aceca5
FB		 5162}
5163
a9d9eb8f
JM		 5164/*** Altivec vector extension ***/
5165/* Altivec registers moves */
5166GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5167GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5168GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5169
5170GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5171GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5172#if 0 // unused
5173GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5174#endif
5175
5176#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5177#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5178static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5179 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5180};
5181#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5182static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5183 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5184};
a9d9eb8f
JM		 5185
5186#define GEN_VR_LDX(name, opc2, opc3) \
5187GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5188{ \
5189 if (unlikely(!ctx->altivec_enabled)) { \
5190 GEN_EXCP_NO_VR(ctx); \
5191 return; \
5192 } \
5193 gen_addr_reg_index(ctx); \
5194 op_vr_ldst(vr_l##name); \
5195 gen_op_store_A0_avr(rD(ctx->opcode)); \
5196}
5197
5198#define GEN_VR_STX(name, opc2, opc3) \
5199GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5200{ \
5201 if (unlikely(!ctx->altivec_enabled)) { \
5202 GEN_EXCP_NO_VR(ctx); \
5203 return; \
5204 } \
5205 gen_addr_reg_index(ctx); \
5206 gen_op_load_avr_A0(rS(ctx->opcode)); \
5207 op_vr_ldst(vr_st##name); \
5208}
5209
5210OP_VR_LD_TABLE(vx);
5211GEN_VR_LDX(vx, 0x07, 0x03);
5212/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5213#define gen_op_vr_lvxl gen_op_vr_lvx
5214GEN_VR_LDX(vxl, 0x07, 0x0B);
5215
5216OP_VR_ST_TABLE(vx);
5217GEN_VR_STX(vx, 0x07, 0x07);
5218/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5219#define gen_op_vr_stvxl gen_op_vr_stvx
5220GEN_VR_STX(vxl, 0x07, 0x0F);
5221
0487d6a8 5222/*** SPE extension ***/
0487d6a8 5223/* Register moves */
65d6c0f3 5224#if !defined(TARGET_PPC64)
3cd7d1dd 5225
0487d6a8
JM		 5226GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5227GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5228#if 0 // unused
5229GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5230#endif
5231
5232GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5233GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5234#if 0 // unused
5235GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5236#endif
5237
65d6c0f3 5238#else /* !defined(TARGET_PPC64) */
3cd7d1dd
JM		 5239
5240/* No specific load/store functions: GPRs are already 64 bits */
5241#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
5242#define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
5243#if 0 // unused
5244#define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
5245#endif
5246
5247#define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
5248#define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
5249#if 0 // unused
5250#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
5251#endif
5252
65d6c0f3 5253#endif /* !defined(TARGET_PPC64) */
3cd7d1dd 5254
0487d6a8
JM		 5255#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5256GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5257{ \
5258 if (Rc(ctx->opcode)) \
5259 gen_##name1(ctx); \
5260 else \
5261 gen_##name0(ctx); \
5262}
5263
5264/* Handler for undefined SPE opcodes */
b068d6a7 5265static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5266{
e1833e1f 5267 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5268}
5269
5270/* SPE load and stores */
b068d6a7 5271static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
0487d6a8
JM		 5272{
5273 target_long simm = rB(ctx->opcode);
5274
5275 if (rA(ctx->opcode) == 0) {
5276 gen_set_T0(simm << sh);
5277 } else {
5278 gen_op_load_gpr_T0(rA(ctx->opcode));
5279 if (likely(simm != 0))
5280 gen_op_addi(simm << sh);
5281 }
5282}
5283
5284#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5285#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5286static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5287 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5288};
5289#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5290static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5291 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5292};
0487d6a8
JM		 5293
5294#define GEN_SPE_LD(name, sh) \
b068d6a7 5295static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5296{ \
5297 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5298 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5299 return; \
5300 } \
5301 gen_addr_spe_imm_index(ctx, sh); \
5302 op_spe_ldst(spe_l##name); \
5303 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5304}
5305
5306#define GEN_SPE_LDX(name) \
b068d6a7 5307static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 5308{ \
5309 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5310 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5311 return; \
5312 } \
5313 gen_addr_reg_index(ctx); \
5314 op_spe_ldst(spe_l##name); \
5315 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5316}
5317
5318#define GEN_SPEOP_LD(name, sh) \
5319OP_SPE_LD_TABLE(name); \
5320GEN_SPE_LD(name, sh); \
5321GEN_SPE_LDX(name)
5322
5323#define GEN_SPE_ST(name, sh) \
b068d6a7 5324static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 5325{ \
5326 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5327 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5328 return; \
5329 } \
5330 gen_addr_spe_imm_index(ctx, sh); \
5331 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5332 op_spe_ldst(spe_st##name); \
5333}
5334
5335#define GEN_SPE_STX(name) \
b068d6a7 5336static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 5337{ \
5338 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5339 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5340 return; \
5341 } \
5342 gen_addr_reg_index(ctx); \
5343 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5344 op_spe_ldst(spe_st##name); \
5345}
5346
5347#define GEN_SPEOP_ST(name, sh) \
5348OP_SPE_ST_TABLE(name); \
5349GEN_SPE_ST(name, sh); \
5350GEN_SPE_STX(name)
5351
5352#define GEN_SPEOP_LDST(name, sh) \
5353GEN_SPEOP_LD(name, sh); \
5354GEN_SPEOP_ST(name, sh)
5355
5356/* SPE arithmetic and logic */
5357#define GEN_SPEOP_ARITH2(name) \
b068d6a7 5358static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5359{ \
5360 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5361 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5362 return; \
5363 } \
5364 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5365 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5366 gen_op_##name(); \
5367 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5368}
5369
5370#define GEN_SPEOP_ARITH1(name) \
b068d6a7 5371static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5372{ \
5373 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5374 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5375 return; \
5376 } \
5377 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5378 gen_op_##name(); \
5379 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5380}
5381
5382#define GEN_SPEOP_COMP(name) \
b068d6a7 5383static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5384{ \
5385 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5386 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5387 return; \
5388 } \
5389 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5390 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5391 gen_op_##name(); \
5392 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5393}
5394
5395/* Logical */
5396GEN_SPEOP_ARITH2(evand);
5397GEN_SPEOP_ARITH2(evandc);
5398GEN_SPEOP_ARITH2(evxor);
5399GEN_SPEOP_ARITH2(evor);
5400GEN_SPEOP_ARITH2(evnor);
5401GEN_SPEOP_ARITH2(eveqv);
5402GEN_SPEOP_ARITH2(evorc);
5403GEN_SPEOP_ARITH2(evnand);
5404GEN_SPEOP_ARITH2(evsrwu);
5405GEN_SPEOP_ARITH2(evsrws);
5406GEN_SPEOP_ARITH2(evslw);
5407GEN_SPEOP_ARITH2(evrlw);
5408GEN_SPEOP_ARITH2(evmergehi);
5409GEN_SPEOP_ARITH2(evmergelo);
5410GEN_SPEOP_ARITH2(evmergehilo);
5411GEN_SPEOP_ARITH2(evmergelohi);
5412
5413/* Arithmetic */
5414GEN_SPEOP_ARITH2(evaddw);
5415GEN_SPEOP_ARITH2(evsubfw);
5416GEN_SPEOP_ARITH1(evabs);
5417GEN_SPEOP_ARITH1(evneg);
5418GEN_SPEOP_ARITH1(evextsb);
5419GEN_SPEOP_ARITH1(evextsh);
5420GEN_SPEOP_ARITH1(evrndw);
5421GEN_SPEOP_ARITH1(evcntlzw);
5422GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 5423static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 5424{
5425 /* Note: brinc is usable even if SPE is disabled */
3cd7d1dd
JM		 5426 gen_op_load_gpr_T0(rA(ctx->opcode));
5427 gen_op_load_gpr_T1(rB(ctx->opcode));
0487d6a8 5428 gen_op_brinc();
3cd7d1dd 5429 gen_op_store_T0_gpr(rD(ctx->opcode));
0487d6a8
JM		 5430}
5431
5432#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 5433static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5434{ \
5435 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5436 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5437 return; \
5438 } \
5439 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5440 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5441 gen_op_##name(); \
5442 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5443}
5444
5445#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 5446static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5447{ \
5448 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5449 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5450 return; \
5451 } \
5452 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5453 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5454 gen_op_##name(); \
5455 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5456}
5457
5458GEN_SPEOP_ARITH_IMM2(evaddw);
5459#define gen_evaddiw gen_evaddwi
5460GEN_SPEOP_ARITH_IMM2(evsubfw);
5461#define gen_evsubifw gen_evsubfwi
5462GEN_SPEOP_LOGIC_IMM2(evslw);
5463GEN_SPEOP_LOGIC_IMM2(evsrwu);
5464#define gen_evsrwis gen_evsrwsi
5465GEN_SPEOP_LOGIC_IMM2(evsrws);
5466#define gen_evsrwiu gen_evsrwui
5467GEN_SPEOP_LOGIC_IMM2(evrlw);
5468
b068d6a7 5469static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 5470{
5471 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5472
5473 gen_op_splatwi_T0_64(imm);
5474 gen_op_store_T0_gpr64(rD(ctx->opcode));
5475}
5476
b068d6a7 5477static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 5478{
5479 uint32_t imm = rA(ctx->opcode) << 27;
5480
5481 gen_op_splatwi_T0_64(imm);
5482 gen_op_store_T0_gpr64(rD(ctx->opcode));
5483}
5484
5485/* Comparison */
5486GEN_SPEOP_COMP(evcmpgtu);
5487GEN_SPEOP_COMP(evcmpgts);
5488GEN_SPEOP_COMP(evcmpltu);
5489GEN_SPEOP_COMP(evcmplts);
5490GEN_SPEOP_COMP(evcmpeq);
5491
5492GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5493GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5494GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5495GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5496GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5497GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5498GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5499GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5500GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5501GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5502GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5503GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5504GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5505GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5506GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5507GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5508GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5509GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5510GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5511GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5512GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5513GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5514GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5515GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5516GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5517
b068d6a7 5518static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 5519{
5520 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 5521 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 5522 return;
5523 }
5524 gen_op_load_crf_T0(ctx->opcode & 0x7);
5525 gen_op_load_gpr64_T0(rA(ctx->opcode));
5526 gen_op_load_gpr64_T1(rB(ctx->opcode));
5527 gen_op_evsel();
5528 gen_op_store_T0_gpr64(rD(ctx->opcode));
5529}
5530
c7697e1f 5531GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5532{
5533 gen_evsel(ctx);
5534}
c7697e1f 5535GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5536{
5537 gen_evsel(ctx);
5538}
c7697e1f 5539GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5540{
5541 gen_evsel(ctx);
5542}
c7697e1f 5543GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5544{
5545 gen_evsel(ctx);
5546}
5547
5548/* Load and stores */
5549#if defined(TARGET_PPC64)
5550/* In that case, we already have 64 bits load & stores
5551 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5552 */
7863667f
JM		 5553#define gen_op_spe_ldd_raw gen_op_ld_raw
5554#define gen_op_spe_ldd_user gen_op_ld_user
5555#define gen_op_spe_ldd_kernel gen_op_ld_kernel
5556#define gen_op_spe_ldd_hypv gen_op_ld_hypv
5557#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5558#define gen_op_spe_ldd_64_user gen_op_ld_64_user
5559#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5560#define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
5561#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5562#define gen_op_spe_ldd_le_user gen_op_ld_le_user
5563#define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
5564#define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
5565#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5566#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5567#define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
5568#define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
5569#define gen_op_spe_stdd_raw gen_op_std_raw
5570#define gen_op_spe_stdd_user gen_op_std_user
5571#define gen_op_spe_stdd_kernel gen_op_std_kernel
5572#define gen_op_spe_stdd_hypv gen_op_std_hypv
5573#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5574#define gen_op_spe_stdd_64_user gen_op_std_64_user
5575#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5576#define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
5577#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5578#define gen_op_spe_stdd_le_user gen_op_std_le_user
5579#define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
5580#define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
5581#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5582#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5583#define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
5584#define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
0487d6a8
JM		 5585#endif /* defined(TARGET_PPC64) */
5586GEN_SPEOP_LDST(dd, 3);
5587GEN_SPEOP_LDST(dw, 3);
5588GEN_SPEOP_LDST(dh, 3);
5589GEN_SPEOP_LDST(whe, 2);
5590GEN_SPEOP_LD(whou, 2);
5591GEN_SPEOP_LD(whos, 2);
5592GEN_SPEOP_ST(who, 2);
5593
5594#if defined(TARGET_PPC64)
5595/* In that case, spe_stwwo is equivalent to stw */
7863667f
JM		 5596#define gen_op_spe_stwwo_raw gen_op_stw_raw
5597#define gen_op_spe_stwwo_user gen_op_stw_user
5598#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5599#define gen_op_spe_stwwo_hypv gen_op_stw_hypv
5600#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5601#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5602#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5603#define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
5604#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5605#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5606#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5607#define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
5608#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5609#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
0487d6a8 5610#define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
7863667f 5611#define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
0487d6a8
JM		 5612#endif
5613#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 5614static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 5615{ \
5616 gen_op_srli32_T1_64(); \
5617 gen_op_spe_stwwo_##suffix(); \
5618}
5619#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 5620static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 5621{ \
5622 gen_op_srli32_T1_64(); \
5623 gen_op_spe_stwwo_le_##suffix(); \
5624}
5625#if defined(TARGET_PPC64)
5626#define GEN_OP_SPE_STWWE(suffix) \
5627_GEN_OP_SPE_STWWE(suffix); \
5628_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 5629static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 5630{ \
5631 gen_op_srli32_T1_64(); \
5632 gen_op_spe_stwwo_64_##suffix(); \
5633} \
b068d6a7 5634static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 5635{ \
5636 gen_op_srli32_T1_64(); \
5637 gen_op_spe_stwwo_le_64_##suffix(); \
5638}
5639#else
5640#define GEN_OP_SPE_STWWE(suffix) \
5641_GEN_OP_SPE_STWWE(suffix); \
5642_GEN_OP_SPE_STWWE_LE(suffix)
5643#endif
5644#if defined(CONFIG_USER_ONLY)
5645GEN_OP_SPE_STWWE(raw);
5646#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 5647GEN_OP_SPE_STWWE(user);
7863667f
JM		 5648GEN_OP_SPE_STWWE(kernel);
5649GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 5650#endif /* defined(CONFIG_USER_ONLY) */
5651GEN_SPEOP_ST(wwe, 2);
5652GEN_SPEOP_ST(wwo, 2);
5653
5654#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 5655static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 5656{ \
5657 gen_op_##op##_##suffix(); \
5658 gen_op_splatw_T1_64(); \
5659}
5660
5661#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 5662static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 5663{ \
5664 gen_op_spe_lh_##suffix(); \
5665 gen_op_sli16_T1_64(); \
5666}
5667
5668#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 5669static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 5670{ \
5671 gen_op_spe_lh_##suffix(); \
5672 gen_op_extsh_T1_64(); \
5673}
5674
5675#if defined(CONFIG_USER_ONLY)
5676GEN_OP_SPE_LHE(raw);
5677GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
5678GEN_OP_SPE_LHE(le_raw);
5679GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
5680GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
5681GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
5682GEN_OP_SPE_LHX(raw);
5683GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
5684GEN_OP_SPE_LHX(le_raw);
5685GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
5686#if defined(TARGET_PPC64)
5687GEN_OP_SPE_LHE(64_raw);
5688GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
5689GEN_OP_SPE_LHE(le_64_raw);
5690GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
5691GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
5692GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
5693GEN_OP_SPE_LHX(64_raw);
5694GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
5695GEN_OP_SPE_LHX(le_64_raw);
5696GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
5697#endif
5698#else
0487d6a8 5699GEN_OP_SPE_LHE(user);
7863667f
JM		 5700GEN_OP_SPE_LHE(kernel);
5701GEN_OP_SPE_LHE(hypv);
0487d6a8 5702GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 5703GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
5704GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 5705GEN_OP_SPE_LHE(le_user);
7863667f
JM		 5706GEN_OP_SPE_LHE(le_kernel);
5707GEN_OP_SPE_LHE(le_hypv);
0487d6a8 5708GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 5709GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
5710GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 5711GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 5712GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
5713GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 5714GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 5715GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
5716GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 5717GEN_OP_SPE_LHX(user);
7863667f
JM		 5718GEN_OP_SPE_LHX(kernel);
5719GEN_OP_SPE_LHX(hypv);
0487d6a8 5720GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 5721GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
5722GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 5723GEN_OP_SPE_LHX(le_user);
7863667f
JM		 5724GEN_OP_SPE_LHX(le_kernel);
5725GEN_OP_SPE_LHX(le_hypv);
0487d6a8 5726GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 5727GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
5728GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 5729#if defined(TARGET_PPC64)
0487d6a8 5730GEN_OP_SPE_LHE(64_user);
7863667f
JM		 5731GEN_OP_SPE_LHE(64_kernel);
5732GEN_OP_SPE_LHE(64_hypv);
0487d6a8 5733GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 5734GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
5735GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 5736GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 5737GEN_OP_SPE_LHE(le_64_kernel);
5738GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 5739GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 5740GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
5741GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 5742GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 5743GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
5744GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 5745GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 5746GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
5747GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 5748GEN_OP_SPE_LHX(64_user);
7863667f
JM		 5749GEN_OP_SPE_LHX(64_kernel);
5750GEN_OP_SPE_LHX(64_hypv);
0487d6a8 5751GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 5752GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
5753GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 5754GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 5755GEN_OP_SPE_LHX(le_64_kernel);
5756GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 5757GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 5758GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
5759GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 5760#endif
5761#endif
5762GEN_SPEOP_LD(hhesplat, 1);
5763GEN_SPEOP_LD(hhousplat, 1);
5764GEN_SPEOP_LD(hhossplat, 1);
5765GEN_SPEOP_LD(wwsplat, 2);
5766GEN_SPEOP_LD(whsplat, 2);
5767
5768GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
5769GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
5770GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
5771GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
5772GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
5773GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
5774GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
5775GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
5776GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
5777GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
5778GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
5779GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
5780GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
5781GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
5782GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
5783GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
5784GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
5785GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
5786
5787/* Multiply and add - TODO */
5788#if 0
5789GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
5790GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
5791GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
5792GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
5793GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
5794GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
5795GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
5796GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
5797GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
5798GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
5799GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
5800GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
5801
5802GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
5803GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
5804GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
5805GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
5806GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
5807GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
5808GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
5809GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
5810GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
5811GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
5812GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
5813GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
5814GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
5815GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
5816
5817GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
5818GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
5819GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
5820GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
5821GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
5822GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
5823
5824GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
5825GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
5826GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
5827GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
5828GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
5829GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
5830GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
5831GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
5832GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
5833GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
5834GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
5835GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
5836
5837GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
5838GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
5839GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
5840GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
5841GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
5842
5843GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
5844GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
5845GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
5846GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
5847GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
5848GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
5849GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
5850GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
5851GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
5852GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
5853GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
5854GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
5855
5856GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
5857GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
5858GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
5859GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
5860GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
5861#endif
5862
5863/*** SPE floating-point extension ***/
5864#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 5865static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5866{ \
5867 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5868 gen_op_##name(); \
5869 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5870}
5871
5872/* Single precision floating-point vectors operations */
5873/* Arithmetic */
5874GEN_SPEOP_ARITH2(evfsadd);
5875GEN_SPEOP_ARITH2(evfssub);
5876GEN_SPEOP_ARITH2(evfsmul);
5877GEN_SPEOP_ARITH2(evfsdiv);
5878GEN_SPEOP_ARITH1(evfsabs);
5879GEN_SPEOP_ARITH1(evfsnabs);
5880GEN_SPEOP_ARITH1(evfsneg);
5881/* Conversion */
5882GEN_SPEFPUOP_CONV(evfscfui);
5883GEN_SPEFPUOP_CONV(evfscfsi);
5884GEN_SPEFPUOP_CONV(evfscfuf);
5885GEN_SPEFPUOP_CONV(evfscfsf);
5886GEN_SPEFPUOP_CONV(evfsctui);
5887GEN_SPEFPUOP_CONV(evfsctsi);
5888GEN_SPEFPUOP_CONV(evfsctuf);
5889GEN_SPEFPUOP_CONV(evfsctsf);
5890GEN_SPEFPUOP_CONV(evfsctuiz);
5891GEN_SPEFPUOP_CONV(evfsctsiz);
5892/* Comparison */
5893GEN_SPEOP_COMP(evfscmpgt);
5894GEN_SPEOP_COMP(evfscmplt);
5895GEN_SPEOP_COMP(evfscmpeq);
5896GEN_SPEOP_COMP(evfststgt);
5897GEN_SPEOP_COMP(evfststlt);
5898GEN_SPEOP_COMP(evfststeq);
5899
5900/* Opcodes definitions */
5901GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
5902GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
5903GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
5904GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
5905GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
5906GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
5907GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
5908GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
5909GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
5910GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
5911GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
5912GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
5913GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
5914GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
5915
5916/* Single precision floating-point operations */
5917/* Arithmetic */
5918GEN_SPEOP_ARITH2(efsadd);
5919GEN_SPEOP_ARITH2(efssub);
5920GEN_SPEOP_ARITH2(efsmul);
5921GEN_SPEOP_ARITH2(efsdiv);
5922GEN_SPEOP_ARITH1(efsabs);
5923GEN_SPEOP_ARITH1(efsnabs);
5924GEN_SPEOP_ARITH1(efsneg);
5925/* Conversion */
5926GEN_SPEFPUOP_CONV(efscfui);
5927GEN_SPEFPUOP_CONV(efscfsi);
5928GEN_SPEFPUOP_CONV(efscfuf);
5929GEN_SPEFPUOP_CONV(efscfsf);
5930GEN_SPEFPUOP_CONV(efsctui);
5931GEN_SPEFPUOP_CONV(efsctsi);
5932GEN_SPEFPUOP_CONV(efsctuf);
5933GEN_SPEFPUOP_CONV(efsctsf);
5934GEN_SPEFPUOP_CONV(efsctuiz);
5935GEN_SPEFPUOP_CONV(efsctsiz);
5936GEN_SPEFPUOP_CONV(efscfd);
5937/* Comparison */
5938GEN_SPEOP_COMP(efscmpgt);
5939GEN_SPEOP_COMP(efscmplt);
5940GEN_SPEOP_COMP(efscmpeq);
5941GEN_SPEOP_COMP(efststgt);
5942GEN_SPEOP_COMP(efststlt);
5943GEN_SPEOP_COMP(efststeq);
5944
5945/* Opcodes definitions */
5946GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
5947GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
5948GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
5949GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
5950GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
5951GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
5952GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
5953GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
5954GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
5955GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
5956GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
5957GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
5958GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
5959
5960/* Double precision floating-point operations */
5961/* Arithmetic */
5962GEN_SPEOP_ARITH2(efdadd);
5963GEN_SPEOP_ARITH2(efdsub);
5964GEN_SPEOP_ARITH2(efdmul);
5965GEN_SPEOP_ARITH2(efddiv);
5966GEN_SPEOP_ARITH1(efdabs);
5967GEN_SPEOP_ARITH1(efdnabs);
5968GEN_SPEOP_ARITH1(efdneg);
5969/* Conversion */
5970
5971GEN_SPEFPUOP_CONV(efdcfui);
5972GEN_SPEFPUOP_CONV(efdcfsi);
5973GEN_SPEFPUOP_CONV(efdcfuf);
5974GEN_SPEFPUOP_CONV(efdcfsf);
5975GEN_SPEFPUOP_CONV(efdctui);
5976GEN_SPEFPUOP_CONV(efdctsi);
5977GEN_SPEFPUOP_CONV(efdctuf);
5978GEN_SPEFPUOP_CONV(efdctsf);
5979GEN_SPEFPUOP_CONV(efdctuiz);
5980GEN_SPEFPUOP_CONV(efdctsiz);
5981GEN_SPEFPUOP_CONV(efdcfs);
5982GEN_SPEFPUOP_CONV(efdcfuid);
5983GEN_SPEFPUOP_CONV(efdcfsid);
5984GEN_SPEFPUOP_CONV(efdctuidz);
5985GEN_SPEFPUOP_CONV(efdctsidz);
5986/* Comparison */
5987GEN_SPEOP_COMP(efdcmpgt);
5988GEN_SPEOP_COMP(efdcmplt);
5989GEN_SPEOP_COMP(efdcmpeq);
5990GEN_SPEOP_COMP(efdtstgt);
5991GEN_SPEOP_COMP(efdtstlt);
5992GEN_SPEOP_COMP(efdtsteq);
5993
5994/* Opcodes definitions */
5995GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
5996GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
5997GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
5998GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
5999GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6000GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6001GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6002GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6003GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6004GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6005GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6006GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6007GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6008GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6009GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6010GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6011
79aceca5
FB		 6012/* End opcode list */
6013GEN_OPCODE_MARK(end);
6014
3fc6c082 6015#include "translate_init.c"
0411a972 6016#include "helper_regs.h"
79aceca5 6017
9a64fbe4 6018/*****************************************************************************/
3fc6c082 6019/* Misc PowerPC helpers */
36081602
JM		 6020void cpu_dump_state (CPUState *env, FILE *f,
6021 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6022 int flags)
79aceca5 6023{
3fc6c082
FB		 6024#if defined(TARGET_PPC64) || 1
6025#define FILL ""
3fc6c082
FB		 6026#define RGPL 4
6027#define RFPL 4
6028#else
6029#define FILL " "
3fc6c082
FB		 6030#define RGPL 8
6031#define RFPL 4
6032#endif
6033
79aceca5
FB		 6034 int i;
6035
077fc206
JM		 6036 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6037 env->nip, env->lr, env->ctr, hreg_load_xer(env));
6038 cpu_fprintf(f, "MSR " REGX FILL " HID0 " REGX FILL " HF " REGX FILL
6039 " idx %d\n",
6040 env->msr, env->hflags, env->spr[SPR_HID0], env->mmu_idx);
d9bce9d9 6041#if !defined(NO_TIMER_DUMP)
077fc206 6042 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6043#if !defined(CONFIG_USER_ONLY)
6044 "DECR %08x"
6045#endif
6046 "\n",
077fc206 6047 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6048#if !defined(CONFIG_USER_ONLY)
6049 , cpu_ppc_load_decr(env)
6050#endif
6051 );
077fc206 6052#endif
76a66253 6053 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6054 if ((i & (RGPL - 1)) == 0)
6055 cpu_fprintf(f, "GPR%02d", i);
a750fc0b 6056 cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
3fc6c082 6057 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6058 cpu_fprintf(f, "\n");
76a66253 6059 }
3fc6c082 6060 cpu_fprintf(f, "CR ");
76a66253 6061 for (i = 0; i < 8; i++)
7fe48483
FB		 6062 cpu_fprintf(f, "%01x", env->crf[i]);
6063 cpu_fprintf(f, " [");
76a66253
JM		 6064 for (i = 0; i < 8; i++) {
6065 char a = '-';
6066 if (env->crf[i] & 0x08)
6067 a = 'L';
6068 else if (env->crf[i] & 0x04)
6069 a = 'G';
6070 else if (env->crf[i] & 0x02)
6071 a = 'E';
7fe48483 6072 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6073 }
3fc6c082
FB		 6074 cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
6075 for (i = 0; i < 32; i++) {
6076 if ((i & (RFPL - 1)) == 0)
6077 cpu_fprintf(f, "FPR%02d", i);
26a76461 6078 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6079 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6080 cpu_fprintf(f, "\n");
79aceca5 6081 }
f2e63a42 6082#if !defined(CONFIG_USER_ONLY)
077fc206 6083 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " SDR1 " REGX "\n",
3fc6c082 6084 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6085#endif
79aceca5 6086
3fc6c082
FB		 6087#undef RGPL
6088#undef RFPL
6089#undef FILL
79aceca5
FB		 6090}
6091
76a66253
JM		 6092void cpu_dump_statistics (CPUState *env, FILE*f,
6093 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6094 int flags)
6095{
6096#if defined(DO_PPC_STATISTICS)
6097 opc_handler_t **t1, **t2, **t3, *handler;
6098 int op1, op2, op3;
6099
6100 t1 = env->opcodes;
6101 for (op1 = 0; op1 < 64; op1++) {
6102 handler = t1[op1];
6103 if (is_indirect_opcode(handler)) {
6104 t2 = ind_table(handler);
6105 for (op2 = 0; op2 < 32; op2++) {
6106 handler = t2[op2];
6107 if (is_indirect_opcode(handler)) {
6108 t3 = ind_table(handler);
6109 for (op3 = 0; op3 < 32; op3++) {
6110 handler = t3[op3];
6111 if (handler->count == 0)
6112 continue;
6113 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6114 "%016llx %lld\n",
6115 op1, op2, op3, op1, (op3 << 5) | op2,
6116 handler->oname,
6117 handler->count, handler->count);
6118 }
6119 } else {
6120 if (handler->count == 0)
6121 continue;
6122 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6123 "%016llx %lld\n",
6124 op1, op2, op1, op2, handler->oname,
6125 handler->count, handler->count);
6126 }
6127 }
6128 } else {
6129 if (handler->count == 0)
6130 continue;
6131 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6132 op1, op1, handler->oname,
6133 handler->count, handler->count);
6134 }
6135 }
6136#endif
6137}
6138
9a64fbe4 6139/*****************************************************************************/
b068d6a7
JM		 6140static always_inline int gen_intermediate_code_internal (CPUState *env,
6141 TranslationBlock *tb,
6142 int search_pc)
79aceca5 6143{
9fddaa0c 6144 DisasContext ctx, *ctxp = &ctx;
79aceca5 6145 opc_handler_t **table, *handler;
0fa85d43 6146 target_ulong pc_start;
79aceca5 6147 uint16_t *gen_opc_end;
056401ea 6148 int supervisor, little_endian;
d26bfc9a 6149 int single_step, branch_step;
79aceca5 6150 int j, lj = -1;
79aceca5
FB		 6151
6152 pc_start = tb->pc;
6153 gen_opc_ptr = gen_opc_buf;
6154 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6155 gen_opparam_ptr = gen_opparam_buf;
7c58044c
JM		 6156#if defined(OPTIMIZE_FPRF_UPDATE)
6157 gen_fprf_ptr = gen_fprf_buf;
6158#endif
c53be334 6159 nb_gen_labels = 0;
046d6672 6160 ctx.nip = pc_start;
79aceca5 6161 ctx.tb = tb;
e1833e1f 6162 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6163 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6164 supervisor = env->mmu_idx;
6165#if !defined(CONFIG_USER_ONLY)
2857068e 6166 ctx.supervisor = supervisor;
d9bce9d9 6167#endif
056401ea 6168 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6169#if defined(TARGET_PPC64)
6170 ctx.sf_mode = msr_sf;
056401ea 6171 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6172#else
056401ea 6173 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6174#endif
d63001d1 6175 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6176 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6177 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6178 ctx.spe_enabled = msr_spe;
6179 else
6180 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6181 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6182 ctx.altivec_enabled = msr_vr;
6183 else
6184 ctx.altivec_enabled = 0;
d26bfc9a
JM		 6185 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6186 single_step = 1;
6187 else
6188 single_step = 0;
6189 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6190 branch_step = 1;
6191 else
6192 branch_step = 0;
b33c17e1 6193 ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;
3fc6c082 6194#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6195 /* Single step trace mode */
6196 msr_se = 1;
6197#endif
6198 /* Set env in case of segfault during code fetch */
e1833e1f 6199 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6200 if (unlikely(env->nb_breakpoints > 0)) {
6201 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6202 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6203 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6204 gen_op_debug();
6205 break;
6206 }
6207 }
6208 }
76a66253 6209 if (unlikely(search_pc)) {
79aceca5
FB		 6210 j = gen_opc_ptr - gen_opc_buf;
6211 if (lj < j) {
6212 lj++;
6213 while (lj < j)
6214 gen_opc_instr_start[lj++] = 0;
046d6672 6215 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 6216 gen_opc_instr_start[lj] = 1;
6217 }
6218 }
9fddaa0c
FB		 6219#if defined PPC_DEBUG_DISAS
6220 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6221 fprintf(logfile, "----------------\n");
1b9eb036 6222 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6223 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6224 }
6225#endif
056401ea
JM		 6226 if (unlikely(little_endian)) {
6227 ctx.opcode = bswap32(ldl_code(ctx.nip));
6228 } else {
6229 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6230 }
9fddaa0c
FB		 6231#if defined PPC_DEBUG_DISAS
6232 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6233 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6234 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6235 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6236 }
6237#endif
046d6672 6238 ctx.nip += 4;
3fc6c082 6239 table = env->opcodes;
79aceca5
FB		 6240 handler = table[opc1(ctx.opcode)];
6241 if (is_indirect_opcode(handler)) {
6242 table = ind_table(handler);
6243 handler = table[opc2(ctx.opcode)];
6244 if (is_indirect_opcode(handler)) {
6245 table = ind_table(handler);
6246 handler = table[opc3(ctx.opcode)];
6247 }
6248 }
6249 /* Is opcode *REALLY* valid ? */
76a66253 6250 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6251 if (loglevel != 0) {
76a66253 6252 fprintf(logfile, "invalid/unsupported opcode: "
1b9eb036 6253 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
76a66253 6254 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6255 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6256 } else {
6257 printf("invalid/unsupported opcode: "
1b9eb036 6258 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
4b3686fa 6259 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6260 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6261 }
76a66253
JM		 6262 } else {
6263 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6264 if (loglevel != 0) {
79aceca5 6265 fprintf(logfile, "invalid bits: %08x for opcode: "
e1833e1f 6266 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
79aceca5
FB		 6267 ctx.opcode & handler->inval, opc1(ctx.opcode),
6268 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6269 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6270 } else {
6271 printf("invalid bits: %08x for opcode: "
e1833e1f 6272 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
76a66253
JM		 6273 ctx.opcode & handler->inval, opc1(ctx.opcode),
6274 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6275 ctx.opcode, ctx.nip - 4);
76a66253 6276 }
e1833e1f 6277 GEN_EXCP_INVAL(ctxp);
4b3686fa 6278 break;
79aceca5 6279 }
79aceca5 6280 }
4b3686fa 6281 (*(handler->handler))(&ctx);
76a66253
JM		 6282#if defined(DO_PPC_STATISTICS)
6283 handler->count++;
6284#endif
9a64fbe4 6285 /* Check trace mode exceptions */
d26bfc9a
JM		 6286 if (unlikely(branch_step != 0 &&
6287 ctx.exception == POWERPC_EXCP_BRANCH)) {
6288 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6289 } else if (unlikely(single_step != 0 &&
6290 (ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
6291 (ctx.nip & 0xFC) != 0x04) &&
417bf010 6292 ctx.exception != POWERPC_SYSCALL &&
d26bfc9a 6293 ctx.exception != POWERPC_EXCP_TRAP)) {
e1833e1f 6294 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a
JM		 6295 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
6296 (env->singlestep_enabled))) {
6297 /* if we reach a page boundary or are single stepping, stop
6298 * generation
6299 */
8dd4983c 6300 break;
76a66253 6301 }
3fc6c082
FB		 6302#if defined (DO_SINGLE_STEP)
6303 break;
6304#endif
6305 }
e1833e1f 6306 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6307 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6308 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
76a66253
JM		 6309 gen_op_reset_T0();
6310 /* Generate the return instruction */
6311 gen_op_exit_tb();
9a64fbe4 6312 }
79aceca5 6313 *gen_opc_ptr = INDEX_op_end;
76a66253 6314 if (unlikely(search_pc)) {
9a64fbe4
FB		 6315 j = gen_opc_ptr - gen_opc_buf;
6316 lj++;
6317 while (lj <= j)
6318 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6319 } else {
046d6672 6320 tb->size = ctx.nip - pc_start;
9a64fbe4 6321 }
d9bce9d9 6322#if defined(DEBUG_DISAS)
9fddaa0c 6323 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6324 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6325 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6326 }
6327 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6328 int flags;
237c0af0 6329 flags = env->bfd_mach;
056401ea 6330 flags |= little_endian << 16;
0fa85d43 6331 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6332 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6333 fprintf(logfile, "\n");
9fddaa0c
FB		 6334 }
6335 if (loglevel & CPU_LOG_TB_OP) {
79aceca5
FB		 6336 fprintf(logfile, "OP:\n");
6337 dump_ops(gen_opc_buf, gen_opparam_buf);
6338 fprintf(logfile, "\n");
6339 }
6340#endif
79aceca5
FB		 6341 return 0;
6342}
6343
9a64fbe4 6344int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 6345{
6346 return gen_intermediate_code_internal(env, tb, 0);
6347}
6348
9a64fbe4 6349int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 6350{
6351 return gen_intermediate_code_internal(env, tb, 1);
6352}
Qemu copy for testing