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target-ppc: convert dcbz instruction to TCG
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
79aceca5 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
7c58044c 44//#define OPTIMIZE_FPRF_UPDATE
79aceca5 45
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 52#if !defined(TARGET_PPC64)
1d542695 53 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 54#endif
a5e26afa 55 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
f78fb44e
AJ		 58static TCGv cpu_gpr[32];
59#if !defined(TARGET_PPC64)
60static TCGv cpu_gprh[32];
61#endif
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64static TCGv_i32 cpu_crf[8];
bd568f18 65static TCGv cpu_nip;
cfdcd37a
AJ		 66static TCGv cpu_ctr;
67static TCGv cpu_lr;
3d7b417e 68static TCGv cpu_xer;
a7812ae4 69static TCGv_i32 cpu_fpscr;
a7859e89 70static TCGv_i32 cpu_access_type;
f78fb44e
AJ		 71
72/* dyngen register indexes */
73static TCGv cpu_T[3];
2e70f6ef
PB		 74
75#include "gen-icount.h"
76
77void ppc_translate_init(void)
78{
f78fb44e
AJ		 79 int i;
80 char* p;
b2437bf2 81 static int done_init = 0;
f78fb44e 82
2e70f6ef
PB		 83 if (done_init)
84 return;
f78fb44e 85
a7812ae4 86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1c73fe5b 87#if TARGET_LONG_BITS > HOST_LONG_BITS
a7812ae4
PB		 88 cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");
89 cpu_T[1] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t1), "T1");
90 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
1c73fe5b 91#else
a7812ae4
PB		 92 cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");
93 cpu_T[1] = tcg_global_reg_new(TCG_AREG2, "T1");
4870167d
AJ		 94#ifdef HOST_I386
95 /* XXX: This is a temporary workaround for i386.
96 * On i386 qemu_st32 runs out of registers.
97 * The proper fix is to remove cpu_T.
98 */
a7812ae4 99 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
4870167d 100#else
a7812ae4 101 cpu_T[2] = tcg_global_reg_new(TCG_AREG3, "T2");
1c73fe5b 102#endif
a7812ae4
PB		 103#endif
104
f78fb44e 105 p = cpu_reg_names;
47e4661c
AJ		 106
107 for (i = 0; i < 8; i++) {
108 sprintf(p, "crf%d", i);
a7812ae4
PB		 109 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 111 p += 5;
112 }
113
f78fb44e
AJ		 114 for (i = 0; i < 32; i++) {
115 sprintf(p, "r%d", i);
a7812ae4 116 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 117 offsetof(CPUState, gpr[i]), p);
118 p += (i < 10) ? 3 : 4;
119#if !defined(TARGET_PPC64)
120 sprintf(p, "r%dH", i);
a7812ae4
PB		 121 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 123 p += (i < 10) ? 4 : 5;
124#endif
1d542695 125
a5e26afa 126 sprintf(p, "fp%d", i);
a7812ae4
PB		 127 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
128 offsetof(CPUState, fpr[i]), p);
ec1ac72d 129 p += (i < 10) ? 4 : 5;
a5e26afa 130
1d542695 131 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 132#ifdef WORDS_BIGENDIAN
133 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
134 offsetof(CPUState, avr[i].u64[0]), p);
135#else
a7812ae4 136 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 137 offsetof(CPUState, avr[i].u64[1]), p);
138#endif
1d542695 139 p += (i < 10) ? 6 : 7;
ec1ac72d 140
1d542695 141 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 142#ifdef WORDS_BIGENDIAN
143 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUState, avr[i].u64[1]), p);
145#else
a7812ae4 146 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 147 offsetof(CPUState, avr[i].u64[0]), p);
148#endif
1d542695 149 p += (i < 10) ? 6 : 7;
f78fb44e 150 }
f10dc08e 151
a7812ae4 152 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 153 offsetof(CPUState, nip), "nip");
154
a7812ae4 155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 156 offsetof(CPUState, ctr), "ctr");
157
a7812ae4 158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 159 offsetof(CPUState, lr), "lr");
160
a7812ae4 161 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 162 offsetof(CPUState, xer), "xer");
163
a7812ae4
PB		 164 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
165 offsetof(CPUState, fpscr), "fpscr");
e1571908 166
a7859e89
AJ		 167 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
168 offsetof(CPUState, access_type), "access_type");
169
f10dc08e 170 /* register helpers */
a7812ae4 171#define GEN_HELPER 2
f10dc08e
AJ		 172#include "helper.h"
173
2e70f6ef
PB		 174 done_init = 1;
175}
176
7c58044c
JM		 177#if defined(OPTIMIZE_FPRF_UPDATE)
178static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
179static uint16_t **gen_fprf_ptr;
180#endif
79aceca5 181
79aceca5
FB		 182/* internal defines */
183typedef struct DisasContext {
184 struct TranslationBlock *tb;
0fa85d43 185 target_ulong nip;
79aceca5 186 uint32_t opcode;
9a64fbe4 187 uint32_t exception;
3cc62370
FB		 188 /* Routine used to access memory */
189 int mem_idx;
190 /* Translation flags */
9a64fbe4 191#if !defined(CONFIG_USER_ONLY)
79aceca5 192 int supervisor;
d9bce9d9
JM		 193#endif
194#if defined(TARGET_PPC64)
195 int sf_mode;
9a64fbe4 196#endif
3cc62370 197 int fpu_enabled;
a9d9eb8f 198 int altivec_enabled;
0487d6a8 199 int spe_enabled;
3fc6c082 200 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 201 int singlestep_enabled;
79aceca5
FB		 202} DisasContext;
203
3fc6c082 204struct opc_handler_t {
79aceca5
FB		 205 /* invalid bits */
206 uint32_t inval;
9a64fbe4 207 /* instruction type */
0487d6a8 208 uint64_t type;
79aceca5
FB		 209 /* handler */
210 void (*handler)(DisasContext *ctx);
a750fc0b 211#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 212 const char *oname;
a750fc0b
JM		 213#endif
214#if defined(DO_PPC_STATISTICS)
76a66253
JM		 215 uint64_t count;
216#endif
3fc6c082 217};
79aceca5 218
7c58044c
JM		 219static always_inline void gen_reset_fpstatus (void)
220{
221#ifdef CONFIG_SOFTFLOAT
222 gen_op_reset_fpstatus();
223#endif
224}
225
0f2f39c2 226static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 227{
0f2f39c2 228 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 229
7c58044c
JM		 230 if (set_fprf != 0) {
231 /* This case might be optimized later */
232#if defined(OPTIMIZE_FPRF_UPDATE)
233 *gen_fprf_ptr++ = gen_opc_ptr;
234#endif
0f2f39c2 235 tcg_gen_movi_i32(t0, 1);
af12906f 236 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 237 if (unlikely(set_rc)) {
0f2f39c2 238 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 239 }
af12906f 240 gen_helper_float_check_status();
7c58044c
JM		 241 } else if (unlikely(set_rc)) {
242 /* We always need to compute fpcc */
0f2f39c2 243 tcg_gen_movi_i32(t0, 0);
af12906f 244 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 245 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 246 if (set_fprf)
af12906f 247 gen_helper_float_check_status();
7c58044c 248 }
af12906f 249
0f2f39c2 250 tcg_temp_free_i32(t0);
7c58044c
JM		 251}
252
253static always_inline void gen_optimize_fprf (void)
254{
255#if defined(OPTIMIZE_FPRF_UPDATE)
256 uint16_t **ptr;
257
258 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
259 *ptr = INDEX_op_nop1;
260 gen_fprf_ptr = gen_fprf_buf;
261#endif
262}
263
a7859e89
AJ		 264static always_inline void gen_set_access_type(int access_type)
265{
266 tcg_gen_movi_i32(cpu_access_type, access_type);
267}
268
b068d6a7 269static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 270{
271#if defined(TARGET_PPC64)
272 if (ctx->sf_mode)
bd568f18 273 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 274 else
275#endif
bd568f18 276 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 277}
278
e1833e1f 279#define GEN_EXCP(ctx, excp, error) \
79aceca5 280do { \
64adab3f
AJ		 281 TCGv_i32 t0 = tcg_const_i32(excp); \
282 TCGv_i32 t1 = tcg_const_i32(error); \
e1833e1f 283 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 284 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c 285 } \
64adab3f
AJ		 286 gen_helper_raise_exception_err(t0, t1); \
287 tcg_temp_free_i32(t0); \
288 tcg_temp_free_i32(t1); \
9fddaa0c 289 ctx->exception = (excp); \
79aceca5
FB		 290} while (0)
291
e1833e1f
JM		 292#define GEN_EXCP_INVAL(ctx) \
293GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
294 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 295
e1833e1f
JM		 296#define GEN_EXCP_PRIVOPC(ctx) \
297GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
298 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 299
e1833e1f
JM		 300#define GEN_EXCP_PRIVREG(ctx) \
301GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
302 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
303
304#define GEN_EXCP_NO_FP(ctx) \
305GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
306
307#define GEN_EXCP_NO_AP(ctx) \
308GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 309
a9d9eb8f
JM		 310#define GEN_EXCP_NO_VR(ctx) \
311GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
312
f24e5695 313/* Stop translation */
b068d6a7 314static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 315{
d9bce9d9 316 gen_update_nip(ctx, ctx->nip);
e1833e1f 317 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 318}
319
f24e5695 320/* No need to update nip here, as execution flow will change */
b068d6a7 321static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 322{
e1833e1f 323 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 324}
325
79aceca5
FB		 326#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
327static void gen_##name (DisasContext *ctx); \
328GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
329static void gen_##name (DisasContext *ctx)
330
c7697e1f
JM		 331#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
332static void gen_##name (DisasContext *ctx); \
333GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
334static void gen_##name (DisasContext *ctx)
335
79aceca5
FB		 336typedef struct opcode_t {
337 unsigned char opc1, opc2, opc3;
1235fc06 338#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 339 unsigned char pad[5];
340#else
341 unsigned char pad[1];
342#endif
79aceca5 343 opc_handler_t handler;
b55266b5 344 const char *oname;
79aceca5
FB		 345} opcode_t;
346
a750fc0b 347/*****************************************************************************/
79aceca5
FB		 348/*** Instruction decoding ***/
349#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 350static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 351{ \
352 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
353}
354
355#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 356static always_inline int32_t name (uint32_t opcode) \
79aceca5 357{ \
18fba28c 358 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 359}
360
361/* Opcode part 1 */
362EXTRACT_HELPER(opc1, 26, 6);
363/* Opcode part 2 */
364EXTRACT_HELPER(opc2, 1, 5);
365/* Opcode part 3 */
366EXTRACT_HELPER(opc3, 6, 5);
367/* Update Cr0 flags */
368EXTRACT_HELPER(Rc, 0, 1);
369/* Destination */
370EXTRACT_HELPER(rD, 21, 5);
371/* Source */
372EXTRACT_HELPER(rS, 21, 5);
373/* First operand */
374EXTRACT_HELPER(rA, 16, 5);
375/* Second operand */
376EXTRACT_HELPER(rB, 11, 5);
377/* Third operand */
378EXTRACT_HELPER(rC, 6, 5);
379/*** Get CRn ***/
380EXTRACT_HELPER(crfD, 23, 3);
381EXTRACT_HELPER(crfS, 18, 3);
382EXTRACT_HELPER(crbD, 21, 5);
383EXTRACT_HELPER(crbA, 16, 5);
384EXTRACT_HELPER(crbB, 11, 5);
385/* SPR / TBL */
3fc6c082 386EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 387static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 388{
389 uint32_t sprn = _SPR(opcode);
390
391 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
392}
79aceca5
FB		 393/*** Get constants ***/
394EXTRACT_HELPER(IMM, 12, 8);
395/* 16 bits signed immediate value */
396EXTRACT_SHELPER(SIMM, 0, 16);
397/* 16 bits unsigned immediate value */
398EXTRACT_HELPER(UIMM, 0, 16);
399/* Bit count */
400EXTRACT_HELPER(NB, 11, 5);
401/* Shift count */
402EXTRACT_HELPER(SH, 11, 5);
403/* Mask start */
404EXTRACT_HELPER(MB, 6, 5);
405/* Mask end */
406EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 407/* Trap operand */
408EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 409
410EXTRACT_HELPER(CRM, 12, 8);
411EXTRACT_HELPER(FM, 17, 8);
412EXTRACT_HELPER(SR, 16, 4);
e4bb997e 413EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 414
79aceca5
FB		 415/*** Jump target decoding ***/
416/* Displacement */
417EXTRACT_SHELPER(d, 0, 16);
418/* Immediate address */
b068d6a7 419static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 420{
421 return (opcode >> 0) & 0x03FFFFFC;
422}
423
b068d6a7 424static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 425{
426 return (opcode >> 0) & 0xFFFC;
427}
428
429EXTRACT_HELPER(BO, 21, 5);
430EXTRACT_HELPER(BI, 16, 5);
431/* Absolute/relative address */
432EXTRACT_HELPER(AA, 1, 1);
433/* Link */
434EXTRACT_HELPER(LK, 0, 1);
435
436/* Create a mask between <start> and <end> bits */
b068d6a7 437static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 438{
76a66253 439 target_ulong ret;
79aceca5 440
76a66253
JM		 441#if defined(TARGET_PPC64)
442 if (likely(start == 0)) {
6f2d8978 443 ret = UINT64_MAX << (63 - end);
76a66253 444 } else if (likely(end == 63)) {
6f2d8978 445 ret = UINT64_MAX >> start;
76a66253
JM		 446 }
447#else
448 if (likely(start == 0)) {
6f2d8978 449 ret = UINT32_MAX << (31 - end);
76a66253 450 } else if (likely(end == 31)) {
6f2d8978 451 ret = UINT32_MAX >> start;
76a66253
JM		 452 }
453#endif
454 else {
455 ret = (((target_ulong)(-1ULL)) >> (start)) ^
456 (((target_ulong)(-1ULL) >> (end)) >> 1);
457 if (unlikely(start > end))
458 return ~ret;
459 }
79aceca5
FB		 460
461 return ret;
462}
463
a750fc0b
JM		 464/*****************************************************************************/
465/* PowerPC Instructions types definitions */
466enum {
1b413d55 467 PPC_NONE = 0x0000000000000000ULL,
12de9a39 468 /* PowerPC base instructions set */
1b413d55
JM		 469 PPC_INSNS_BASE = 0x0000000000000001ULL,
470 /* integer operations instructions */
a750fc0b 471#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 472 /* flow control instructions */
a750fc0b 473#define PPC_FLOW PPC_INSNS_BASE
1b413d55 474 /* virtual memory instructions */
a750fc0b 475#define PPC_MEM PPC_INSNS_BASE
1b413d55 476 /* ld/st with reservation instructions */
a750fc0b 477#define PPC_RES PPC_INSNS_BASE
1b413d55 478 /* spr/msr access instructions */
a750fc0b 479#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 480 /* Deprecated instruction sets */
481 /* Original POWER instruction set */
f610349f 482 PPC_POWER = 0x0000000000000002ULL,
1b413d55 483 /* POWER2 instruction set extension */
f610349f 484 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 485 /* Power RTC support */
f610349f 486 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 487 /* Power-to-PowerPC bridge (601) */
f610349f 488 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 489 /* 64 bits PowerPC instruction set */
f610349f 490 PPC_64B = 0x0000000000000020ULL,
1b413d55 491 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 492 PPC_64BX = 0x0000000000000040ULL,
1b413d55 493 /* 64 bits hypervisor extensions */
f610349f 494 PPC_64H = 0x0000000000000080ULL,
1b413d55 495 /* New wait instruction (PowerPC 2.0x) */
f610349f 496 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 497 /* Time base mftb instruction */
f610349f 498 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 499
500 /* Fixed-point unit extensions */
501 /* PowerPC 602 specific */
f610349f 502 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 503 /* isel instruction */
504 PPC_ISEL = 0x0000000000000800ULL,
505 /* popcntb instruction */
506 PPC_POPCNTB = 0x0000000000001000ULL,
507 /* string load / store */
508 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 509
510 /* Floating-point unit extensions */
511 /* Optional floating point instructions */
512 PPC_FLOAT = 0x0000000000010000ULL,
513 /* New floating-point extensions (PowerPC 2.0x) */
514 PPC_FLOAT_EXT = 0x0000000000020000ULL,
515 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
516 PPC_FLOAT_FRES = 0x0000000000080000ULL,
517 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
518 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
519 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
520 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
521
522 /* Vector/SIMD extensions */
523 /* Altivec support */
524 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 525 /* PowerPC 2.03 SPE extension */
05332d70 526 PPC_SPE = 0x0000000002000000ULL,
1b413d55 527 /* PowerPC 2.03 SPE floating-point extension */
05332d70 528 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 529
12de9a39 530 /* Optional memory control instructions */
1b413d55
JM		 531 PPC_MEM_TLBIA = 0x0000000010000000ULL,
532 PPC_MEM_TLBIE = 0x0000000020000000ULL,
533 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
534 /* sync instruction */
535 PPC_MEM_SYNC = 0x0000000080000000ULL,
536 /* eieio instruction */
537 PPC_MEM_EIEIO = 0x0000000100000000ULL,
538
539 /* Cache control instructions */
c8623f2e 540 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 541 /* icbi instruction */
05332d70 542 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 543 /* dcbz instruction with fixed cache line size */
05332d70 544 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 545 /* dcbz instruction with tunable cache line size */
05332d70 546 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 547 /* dcba instruction */
05332d70
JM		 548 PPC_CACHE_DCBA = 0x0000002000000000ULL,
549 /* Freescale cache locking instructions */
550 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 551
552 /* MMU related extensions */
553 /* external control instructions */
05332d70 554 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 555 /* segment register access instructions */
05332d70 556 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 557 /* PowerPC 6xx TLB management instructions */
05332d70 558 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 559 /* PowerPC 74xx TLB management instructions */
05332d70 560 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 561 /* PowerPC 40x TLB management instructions */
05332d70 562 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 563 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 564 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 565 /* SLB management */
05332d70 566 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 567
12de9a39 568 /* Embedded PowerPC dedicated instructions */
05332d70 569 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 570 /* PowerPC 40x exception model */
05332d70 571 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 572 /* PowerPC 405 Mac instructions */
05332d70 573 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 574 /* PowerPC 440 specific instructions */
05332d70 575 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 576 /* BookE (embedded) PowerPC specification */
05332d70
JM		 577 PPC_BOOKE = 0x0010000000000000ULL,
578 /* mfapidi instruction */
579 PPC_MFAPIDI = 0x0020000000000000ULL,
580 /* tlbiva instruction */
581 PPC_TLBIVA = 0x0040000000000000ULL,
582 /* tlbivax instruction */
583 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 584 /* PowerPC 4xx dedicated instructions */
05332d70 585 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 586 /* PowerPC 40x ibct instructions */
05332d70 587 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 588 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 589 PPC_RFMCI = 0x0400000000000000ULL,
590 /* rfdi instruction */
591 PPC_RFDI = 0x0800000000000000ULL,
592 /* DCR accesses */
593 PPC_DCR = 0x1000000000000000ULL,
594 /* DCR extended accesse */
595 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 596 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 597 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 598};
599
600/*****************************************************************************/
601/* PowerPC instructions table */
3fc6c082
FB		 602#if HOST_LONG_BITS == 64
603#define OPC_ALIGN 8
604#else
605#define OPC_ALIGN 4
606#endif
1b039c09 607#if defined(__APPLE__)
d9bce9d9 608#define OPCODES_SECTION \
3fc6c082 609 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 610#else
d9bce9d9 611#define OPCODES_SECTION \
3fc6c082 612 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 613#endif
614
76a66253 615#if defined(DO_PPC_STATISTICS)
79aceca5 616#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 617OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 618 .opc1 = op1, \
619 .opc2 = op2, \
620 .opc3 = op3, \
18fba28c 621 .pad = { 0, }, \
79aceca5
FB		 622 .handler = { \
623 .inval = invl, \
9a64fbe4 624 .type = _typ, \
79aceca5 625 .handler = &gen_##name, \
76a66253 626 .oname = stringify(name), \
79aceca5 627 }, \
3fc6c082 628 .oname = stringify(name), \
79aceca5 629}
c7697e1f
JM		 630#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
631OPCODES_SECTION opcode_t opc_##name = { \
632 .opc1 = op1, \
633 .opc2 = op2, \
634 .opc3 = op3, \
635 .pad = { 0, }, \
636 .handler = { \
637 .inval = invl, \
638 .type = _typ, \
639 .handler = &gen_##name, \
640 .oname = onam, \
641 }, \
642 .oname = onam, \
643}
76a66253
JM		 644#else
645#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
646OPCODES_SECTION opcode_t opc_##name = { \
647 .opc1 = op1, \
648 .opc2 = op2, \
649 .opc3 = op3, \
650 .pad = { 0, }, \
651 .handler = { \
652 .inval = invl, \
653 .type = _typ, \
654 .handler = &gen_##name, \
655 }, \
656 .oname = stringify(name), \
657}
c7697e1f
JM		 658#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
659OPCODES_SECTION opcode_t opc_##name = { \
660 .opc1 = op1, \
661 .opc2 = op2, \
662 .opc3 = op3, \
663 .pad = { 0, }, \
664 .handler = { \
665 .inval = invl, \
666 .type = _typ, \
667 .handler = &gen_##name, \
668 }, \
669 .oname = onam, \
670}
76a66253 671#endif
79aceca5
FB		 672
673#define GEN_OPCODE_MARK(name) \
18fba28c 674OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 675 .opc1 = 0xFF, \
676 .opc2 = 0xFF, \
677 .opc3 = 0xFF, \
18fba28c 678 .pad = { 0, }, \
79aceca5
FB		 679 .handler = { \
680 .inval = 0x00000000, \
9a64fbe4 681 .type = 0x00, \
79aceca5
FB		 682 .handler = NULL, \
683 }, \
3fc6c082 684 .oname = stringify(name), \
79aceca5
FB		 685}
686
687/* Start opcode list */
688GEN_OPCODE_MARK(start);
689
690/* Invalid instruction */
9a64fbe4
FB		 691GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
692{
e1833e1f 693 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 694}
695
79aceca5
FB		 696static opc_handler_t invalid_handler = {
697 .inval = 0xFFFFFFFF,
9a64fbe4 698 .type = PPC_NONE,
79aceca5
FB		 699 .handler = gen_invalid,
700};
701
e1571908
AJ		 702/*** Integer comparison ***/
703
ea363694 704static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 705{
706 int l1, l2, l3;
707
269f3e95
AJ		 708 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
709 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 710 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
711
712 l1 = gen_new_label();
713 l2 = gen_new_label();
714 l3 = gen_new_label();
715 if (s) {
ea363694
AJ		 716 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
717 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 718 } else {
ea363694
AJ		 719 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
720 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 721 }
722 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
723 tcg_gen_br(l3);
724 gen_set_label(l1);
725 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
726 tcg_gen_br(l3);
727 gen_set_label(l2);
728 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
729 gen_set_label(l3);
730}
731
ea363694 732static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 733{
ea363694
AJ		 734 TCGv t0 = tcg_const_local_tl(arg1);
735 gen_op_cmp(arg0, t0, s, crf);
736 tcg_temp_free(t0);
e1571908
AJ		 737}
738
739#if defined(TARGET_PPC64)
ea363694 740static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 741{
ea363694 742 TCGv t0, t1;
a7812ae4
PB		 743 t0 = tcg_temp_local_new();
744 t1 = tcg_temp_local_new();
e1571908 745 if (s) {
ea363694
AJ		 746 tcg_gen_ext32s_tl(t0, arg0);
747 tcg_gen_ext32s_tl(t1, arg1);
e1571908 748 } else {
ea363694
AJ		 749 tcg_gen_ext32u_tl(t0, arg0);
750 tcg_gen_ext32u_tl(t1, arg1);
e1571908 751 }
ea363694
AJ		 752 gen_op_cmp(t0, t1, s, crf);
753 tcg_temp_free(t1);
754 tcg_temp_free(t0);
e1571908
AJ		 755}
756
ea363694 757static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 758{
ea363694
AJ		 759 TCGv t0 = tcg_const_local_tl(arg1);
760 gen_op_cmp32(arg0, t0, s, crf);
761 tcg_temp_free(t0);
e1571908
AJ		 762}
763#endif
764
765static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
766{
767#if defined(TARGET_PPC64)
768 if (!(ctx->sf_mode))
769 gen_op_cmpi32(reg, 0, 1, 0);
770 else
771#endif
772 gen_op_cmpi(reg, 0, 1, 0);
773}
774
775/* cmp */
776GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
777{
778#if defined(TARGET_PPC64)
779 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
780 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
781 1, crfD(ctx->opcode));
782 else
783#endif
784 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
785 1, crfD(ctx->opcode));
786}
787
788/* cmpi */
789GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
790{
791#if defined(TARGET_PPC64)
792 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
793 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
794 1, crfD(ctx->opcode));
795 else
796#endif
797 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
798 1, crfD(ctx->opcode));
799}
800
801/* cmpl */
802GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
803{
804#if defined(TARGET_PPC64)
805 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
806 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
807 0, crfD(ctx->opcode));
808 else
809#endif
810 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
811 0, crfD(ctx->opcode));
812}
813
814/* cmpli */
815GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
816{
817#if defined(TARGET_PPC64)
818 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
819 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
820 0, crfD(ctx->opcode));
821 else
822#endif
823 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
824 0, crfD(ctx->opcode));
825}
826
827/* isel (PowerPC 2.03 specification) */
828GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
829{
830 int l1, l2;
831 uint32_t bi = rC(ctx->opcode);
832 uint32_t mask;
a7812ae4 833 TCGv_i32 t0;
e1571908
AJ		 834
835 l1 = gen_new_label();
836 l2 = gen_new_label();
837
838 mask = 1 << (3 - (bi & 0x03));
a7812ae4 839 t0 = tcg_temp_new_i32();
fea0c503
AJ		 840 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
841 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 842 if (rA(ctx->opcode) == 0)
843 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
844 else
845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
846 tcg_gen_br(l2);
847 gen_set_label(l1);
848 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
849 gen_set_label(l2);
a7812ae4 850 tcg_temp_free_i32(t0);
e1571908
AJ		 851}
852
79aceca5 853/*** Integer arithmetic ***/
79aceca5 854
74637406
AJ		 855static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
856{
857 int l1;
858 TCGv t0;
79aceca5 859
74637406
AJ		 860 l1 = gen_new_label();
861 /* Start with XER OV disabled, the most likely case */
862 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 863 t0 = tcg_temp_local_new();
74637406
AJ		 864 tcg_gen_xor_tl(t0, arg0, arg1);
865#if defined(TARGET_PPC64)
866 if (!ctx->sf_mode)
867 tcg_gen_ext32s_tl(t0, t0);
868#endif
869 if (sub)
870 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
871 else
872 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
873 tcg_gen_xor_tl(t0, arg1, arg2);
874#if defined(TARGET_PPC64)
875 if (!ctx->sf_mode)
876 tcg_gen_ext32s_tl(t0, t0);
877#endif
878 if (sub)
879 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
880 else
881 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
882 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
883 gen_set_label(l1);
884 tcg_temp_free(t0);
79aceca5
FB		 885}
886
74637406
AJ		 887static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
888{
889 int l1 = gen_new_label();
d9bce9d9
JM		 890
891#if defined(TARGET_PPC64)
74637406
AJ		 892 if (!(ctx->sf_mode)) {
893 TCGv t0, t1;
a7812ae4
PB		 894 t0 = tcg_temp_new();
895 t1 = tcg_temp_new();
d9bce9d9 896
74637406
AJ		 897 tcg_gen_ext32u_tl(t0, arg1);
898 tcg_gen_ext32u_tl(t1, arg2);
899 if (sub) {
900 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 901 } else {
74637406
AJ		 902 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
903 }
a9730017
AJ		 904 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
905 gen_set_label(l1);
906 tcg_temp_free(t0);
907 tcg_temp_free(t1);
74637406
AJ		 908 } else
909#endif
a9730017
AJ		 910 {
911 if (sub) {
912 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
913 } else {
914 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
915 }
916 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
917 gen_set_label(l1);
74637406 918 }
d9bce9d9
JM		 919}
920
74637406
AJ		 921/* Common add function */
922static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
923 int add_ca, int compute_ca, int compute_ov)
924{
925 TCGv t0, t1;
d9bce9d9 926
74637406 927 if ((!compute_ca && !compute_ov) ||
a7812ae4 928 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 929 t0 = ret;
930 } else {
a7812ae4 931 t0 = tcg_temp_local_new();
74637406 932 }
79aceca5 933
74637406 934 if (add_ca) {
a7812ae4 935 t1 = tcg_temp_local_new();
74637406
AJ		 936 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
937 tcg_gen_shri_tl(t1, t1, XER_CA);
938 }
79aceca5 939
74637406
AJ		 940 if (compute_ca && compute_ov) {
941 /* Start with XER CA and OV disabled, the most likely case */
942 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
943 } else if (compute_ca) {
944 /* Start with XER CA disabled, the most likely case */
945 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
946 } else if (compute_ov) {
947 /* Start with XER OV disabled, the most likely case */
948 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
949 }
79aceca5 950
74637406
AJ		 951 tcg_gen_add_tl(t0, arg1, arg2);
952
953 if (compute_ca) {
954 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
955 }
956 if (add_ca) {
957 tcg_gen_add_tl(t0, t0, t1);
958 gen_op_arith_compute_ca(ctx, t0, t1, 0);
959 tcg_temp_free(t1);
960 }
961 if (compute_ov) {
962 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
963 }
964
965 if (unlikely(Rc(ctx->opcode) != 0))
966 gen_set_Rc0(ctx, t0);
967
a7812ae4 968 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 969 tcg_gen_mov_tl(ret, t0);
970 tcg_temp_free(t0);
971 }
39dd32ee 972}
74637406
AJ		 973/* Add functions with two operands */
974#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
975GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
976{ \
977 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 add_ca, compute_ca, compute_ov); \
980}
981/* Add functions with one operand and one immediate */
982#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
983 add_ca, compute_ca, compute_ov) \
984GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
985{ \
986 TCGv t0 = tcg_const_local_tl(const_val); \
987 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
988 cpu_gpr[rA(ctx->opcode)], t0, \
989 add_ca, compute_ca, compute_ov); \
990 tcg_temp_free(t0); \
991}
992
993/* add add. addo addo. */
994GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
995GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
996/* addc addc. addco addco. */
997GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
998GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
999/* adde adde. addeo addeo. */
1000GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1001GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1002/* addme addme. addmeo addmeo. */
1003GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1004GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1005/* addze addze. addzeo addzeo.*/
1006GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1007GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1008/* addi */
1009GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1010{
74637406
AJ		 1011 target_long simm = SIMM(ctx->opcode);
1012
1013 if (rA(ctx->opcode) == 0) {
1014 /* li case */
1015 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1016 } else {
1017 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1018 }
d9bce9d9 1019}
74637406
AJ		 1020/* addic addic.*/
1021static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1022 int compute_Rc0)
d9bce9d9 1023{
74637406
AJ		 1024 target_long simm = SIMM(ctx->opcode);
1025
1026 /* Start with XER CA and OV disabled, the most likely case */
1027 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1028
1029 if (likely(simm != 0)) {
a7812ae4 1030 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1031 tcg_gen_addi_tl(t0, arg1, simm);
1032 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1033 tcg_gen_mov_tl(ret, t0);
1034 tcg_temp_free(t0);
1035 } else {
1036 tcg_gen_mov_tl(ret, arg1);
1037 }
1038 if (compute_Rc0) {
1039 gen_set_Rc0(ctx, ret);
1040 }
d9bce9d9 1041}
74637406 1042GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1043{
74637406 1044 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1045}
74637406 1046GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1047{
74637406 1048 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1049}
74637406
AJ		 1050/* addis */
1051GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1052{
74637406
AJ		 1053 target_long simm = SIMM(ctx->opcode);
1054
1055 if (rA(ctx->opcode) == 0) {
1056 /* lis case */
1057 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1058 } else {
1059 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1060 }
d9bce9d9 1061}
74637406
AJ		 1062
1063static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1064 int sign, int compute_ov)
d9bce9d9 1065{
2ef1b120
AJ		 1066 int l1 = gen_new_label();
1067 int l2 = gen_new_label();
a7812ae4
PB		 1068 TCGv_i32 t0 = tcg_temp_local_new_i32();
1069 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1070
2ef1b120
AJ		 1071 tcg_gen_trunc_tl_i32(t0, arg1);
1072 tcg_gen_trunc_tl_i32(t1, arg2);
1073 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1074 if (sign) {
2ef1b120
AJ		 1075 int l3 = gen_new_label();
1076 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1078 gen_set_label(l3);
2ef1b120 1079 tcg_gen_div_i32(t0, t0, t1);
74637406 1080 } else {
2ef1b120 1081 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1082 }
1083 if (compute_ov) {
1084 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1085 }
1086 tcg_gen_br(l2);
1087 gen_set_label(l1);
1088 if (sign) {
2ef1b120 1089 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1090 } else {
1091 tcg_gen_movi_i32(t0, 0);
1092 }
1093 if (compute_ov) {
1094 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1095 }
1096 gen_set_label(l2);
2ef1b120 1097 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1098 tcg_temp_free_i32(t0);
1099 tcg_temp_free_i32(t1);
74637406
AJ		 1100 if (unlikely(Rc(ctx->opcode) != 0))
1101 gen_set_Rc0(ctx, ret);
d9bce9d9 1102}
74637406
AJ		 1103/* Div functions */
1104#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1105GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1106{ \
1107 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1108 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1109 sign, compute_ov); \
1110}
1111/* divwu divwu. divwuo divwuo. */
1112GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1113GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1114/* divw divw. divwo divwo. */
1115GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1116GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1117#if defined(TARGET_PPC64)
2ef1b120
AJ		 1118static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1119 int sign, int compute_ov)
d9bce9d9 1120{
2ef1b120
AJ		 1121 int l1 = gen_new_label();
1122 int l2 = gen_new_label();
74637406
AJ		 1123
1124 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1125 if (sign) {
2ef1b120 1126 int l3 = gen_new_label();
74637406
AJ		 1127 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1128 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1129 gen_set_label(l3);
74637406
AJ		 1130 tcg_gen_div_i64(ret, arg1, arg2);
1131 } else {
1132 tcg_gen_divu_i64(ret, arg1, arg2);
1133 }
1134 if (compute_ov) {
1135 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1136 }
1137 tcg_gen_br(l2);
1138 gen_set_label(l1);
1139 if (sign) {
1140 tcg_gen_sari_i64(ret, arg1, 63);
1141 } else {
1142 tcg_gen_movi_i64(ret, 0);
1143 }
1144 if (compute_ov) {
1145 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1146 }
1147 gen_set_label(l2);
1148 if (unlikely(Rc(ctx->opcode) != 0))
1149 gen_set_Rc0(ctx, ret);
d9bce9d9 1150}
74637406
AJ		 1151#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1152GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1153{ \
2ef1b120
AJ		 1154 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1155 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1156 sign, compute_ov); \
74637406
AJ		 1157}
1158/* divwu divwu. divwuo divwuo. */
1159GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1160GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1161/* divw divw. divwo divwo. */
1162GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1163GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1164#endif
74637406
AJ		 1165
1166/* mulhw mulhw. */
1167GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1168{
a7812ae4 1169 TCGv_i64 t0, t1;
74637406 1170
a7812ae4
PB		 1171 t0 = tcg_temp_new_i64();
1172 t1 = tcg_temp_new_i64();
74637406
AJ		 1173#if defined(TARGET_PPC64)
1174 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1175 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1176 tcg_gen_mul_i64(t0, t0, t1);
1177 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1178#else
1179 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(t0, t0, 32);
1183 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1184#endif
a7812ae4
PB		 1185 tcg_temp_free_i64(t0);
1186 tcg_temp_free_i64(t1);
74637406
AJ		 1187 if (unlikely(Rc(ctx->opcode) != 0))
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1189}
74637406
AJ		 1190/* mulhwu mulhwu. */
1191GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1192{
a7812ae4 1193 TCGv_i64 t0, t1;
74637406 1194
a7812ae4
PB		 1195 t0 = tcg_temp_new_i64();
1196 t1 = tcg_temp_new_i64();
d9bce9d9 1197#if defined(TARGET_PPC64)
74637406
AJ		 1198 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1199 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1200 tcg_gen_mul_i64(t0, t0, t1);
1201 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1202#else
1203 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(t0, t0, 32);
1207 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1208#endif
a7812ae4
PB		 1209 tcg_temp_free_i64(t0);
1210 tcg_temp_free_i64(t1);
74637406
AJ		 1211 if (unlikely(Rc(ctx->opcode) != 0))
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1213}
74637406
AJ		 1214/* mullw mullw. */
1215GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1216{
74637406
AJ		 1217 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1218 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1219 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1220 if (unlikely(Rc(ctx->opcode) != 0))
1221 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1222}
74637406
AJ		 1223/* mullwo mullwo. */
1224GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1225{
74637406 1226 int l1;
a7812ae4 1227 TCGv_i64 t0, t1;
74637406 1228
a7812ae4
PB		 1229 t0 = tcg_temp_new_i64();
1230 t1 = tcg_temp_new_i64();
74637406
AJ		 1231 l1 = gen_new_label();
1232 /* Start with XER OV disabled, the most likely case */
1233 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1234#if defined(TARGET_PPC64)
1235 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1236 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1237#else
1238 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1239 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1240#endif
74637406
AJ		 1241 tcg_gen_mul_i64(t0, t0, t1);
1242#if defined(TARGET_PPC64)
1243 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1244 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1245#else
1246 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1247 tcg_gen_ext32s_i64(t1, t0);
1248 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1249#endif
1250 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1251 gen_set_label(l1);
a7812ae4
PB		 1252 tcg_temp_free_i64(t0);
1253 tcg_temp_free_i64(t1);
74637406
AJ		 1254 if (unlikely(Rc(ctx->opcode) != 0))
1255 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1256}
74637406
AJ		 1257/* mulli */
1258GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1259{
74637406
AJ		 1260 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1261 SIMM(ctx->opcode));
d9bce9d9
JM		 1262}
1263#if defined(TARGET_PPC64)
74637406
AJ		 1264#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1265GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1266{ \
a7812ae4 1267 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1268 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1269 if (unlikely(Rc(ctx->opcode) != 0)) \
1270 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1271}
74637406
AJ		 1272/* mulhd mulhd. */
1273GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1274/* mulhdu mulhdu. */
1275GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1276/* mulld mulld. */
1277GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1278{
74637406
AJ		 1279 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1280 cpu_gpr[rB(ctx->opcode)]);
1281 if (unlikely(Rc(ctx->opcode) != 0))
1282 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1283}
74637406
AJ		 1284/* mulldo mulldo. */
1285GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1286#endif
74637406
AJ		 1287
1288/* neg neg. nego nego. */
ec6469a3 1289static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1290{
ec6469a3
AJ		 1291 int l1 = gen_new_label();
1292 int l2 = gen_new_label();
a7812ae4 1293 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1294#if defined(TARGET_PPC64)
74637406 1295 if (ctx->sf_mode) {
741a7444 1296 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1297 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1298 } else
1299#endif
1300 {
1301 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1303 }
74637406
AJ		 1304 tcg_gen_neg_tl(ret, arg1);
1305 if (ov_check) {
1306 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1307 }
1308 tcg_gen_br(l2);
1309 gen_set_label(l1);
ec6469a3 1310 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1311 if (ov_check) {
1312 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1313 }
1314 gen_set_label(l2);
ec6469a3 1315 tcg_temp_free(t0);
74637406
AJ		 1316 if (unlikely(Rc(ctx->opcode) != 0))
1317 gen_set_Rc0(ctx, ret);
1318}
1319GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1320{
ec6469a3 1321 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1322}
74637406 1323GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1324{
ec6469a3 1325 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1326}
74637406
AJ		 1327
1328/* Common subf function */
1329static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1330 int add_ca, int compute_ca, int compute_ov)
79aceca5 1331{
74637406 1332 TCGv t0, t1;
76a66253 1333
74637406 1334 if ((!compute_ca && !compute_ov) ||
a7812ae4 1335 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1336 t0 = ret;
e864cabd 1337 } else {
a7812ae4 1338 t0 = tcg_temp_local_new();
d9bce9d9 1339 }
76a66253 1340
74637406 1341 if (add_ca) {
a7812ae4 1342 t1 = tcg_temp_local_new();
74637406
AJ		 1343 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1344 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1345 }
79aceca5 1346
74637406
AJ		 1347 if (compute_ca && compute_ov) {
1348 /* Start with XER CA and OV disabled, the most likely case */
1349 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1350 } else if (compute_ca) {
1351 /* Start with XER CA disabled, the most likely case */
1352 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1353 } else if (compute_ov) {
1354 /* Start with XER OV disabled, the most likely case */
1355 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1356 }
1357
1358 if (add_ca) {
1359 tcg_gen_not_tl(t0, arg1);
1360 tcg_gen_add_tl(t0, t0, arg2);
1361 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1362 tcg_gen_add_tl(t0, t0, t1);
1363 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1364 tcg_temp_free(t1);
79aceca5 1365 } else {
74637406
AJ		 1366 tcg_gen_sub_tl(t0, arg2, arg1);
1367 if (compute_ca) {
1368 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1369 }
1370 }
1371 if (compute_ov) {
1372 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1373 }
1374
1375 if (unlikely(Rc(ctx->opcode) != 0))
1376 gen_set_Rc0(ctx, t0);
1377
a7812ae4 1378 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1379 tcg_gen_mov_tl(ret, t0);
1380 tcg_temp_free(t0);
79aceca5 1381 }
79aceca5 1382}
74637406
AJ		 1383/* Sub functions with Two operands functions */
1384#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1385GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1386{ \
1387 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1388 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1389 add_ca, compute_ca, compute_ov); \
1390}
1391/* Sub functions with one operand and one immediate */
1392#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1393 add_ca, compute_ca, compute_ov) \
1394GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1395{ \
1396 TCGv t0 = tcg_const_local_tl(const_val); \
1397 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1398 cpu_gpr[rA(ctx->opcode)], t0, \
1399 add_ca, compute_ca, compute_ov); \
1400 tcg_temp_free(t0); \
1401}
1402/* subf subf. subfo subfo. */
1403GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1404GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1405/* subfc subfc. subfco subfco. */
1406GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1407GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1408/* subfe subfe. subfeo subfo. */
1409GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1410GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1411/* subfme subfme. subfmeo subfmeo. */
1412GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1413GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1414/* subfze subfze. subfzeo subfzeo.*/
1415GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1416GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1417/* subfic */
1418GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1419{
74637406
AJ		 1420 /* Start with XER CA and OV disabled, the most likely case */
1421 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1422 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1423 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1424 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1425 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1426 tcg_temp_free(t1);
1427 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1428 tcg_temp_free(t0);
79aceca5
FB		 1429}
1430
79aceca5 1431/*** Integer logical ***/
26d67362
AJ		 1432#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1433GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1434{ \
26d67362
AJ		 1435 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1436 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1437 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1438 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1439}
79aceca5 1440
26d67362 1441#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1442GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1443{ \
26d67362 1444 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1445 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1446 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1447}
1448
1449/* and & and. */
26d67362 1450GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1451/* andc & andc. */
26d67362 1452GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1453/* andi. */
c7697e1f 1454GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1455{
26d67362
AJ		 1456 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1457 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1458}
1459/* andis. */
c7697e1f 1460GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1461{
26d67362
AJ		 1462 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1463 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1464}
79aceca5 1465/* cntlzw */
26d67362
AJ		 1466GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1467{
a7812ae4 1468 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1469 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1470 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1471}
79aceca5 1472/* eqv & eqv. */
26d67362 1473GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1474/* extsb & extsb. */
26d67362 1475GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1476/* extsh & extsh. */
26d67362 1477GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1478/* nand & nand. */
26d67362 1479GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1480/* nor & nor. */
26d67362 1481GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1482/* or & or. */
9a64fbe4
FB		 1483GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1484{
76a66253
JM		 1485 int rs, ra, rb;
1486
1487 rs = rS(ctx->opcode);
1488 ra = rA(ctx->opcode);
1489 rb = rB(ctx->opcode);
1490 /* Optimisation for mr. ri case */
1491 if (rs != ra || rs != rb) {
26d67362
AJ		 1492 if (rs != rb)
1493 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1494 else
1495 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1496 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1497 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1498 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1499 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1500#if defined(TARGET_PPC64)
1501 } else {
26d67362
AJ		 1502 int prio = 0;
1503
c80f84e3
JM		 1504 switch (rs) {
1505 case 1:
1506 /* Set process priority to low */
26d67362 1507 prio = 2;
c80f84e3
JM		 1508 break;
1509 case 6:
1510 /* Set process priority to medium-low */
26d67362 1511 prio = 3;
c80f84e3
JM		 1512 break;
1513 case 2:
1514 /* Set process priority to normal */
26d67362 1515 prio = 4;
c80f84e3 1516 break;
be147d08
JM		 1517#if !defined(CONFIG_USER_ONLY)
1518 case 31:
1519 if (ctx->supervisor > 0) {
1520 /* Set process priority to very low */
26d67362 1521 prio = 1;
be147d08
JM		 1522 }
1523 break;
1524 case 5:
1525 if (ctx->supervisor > 0) {
1526 /* Set process priority to medium-hight */
26d67362 1527 prio = 5;
be147d08
JM		 1528 }
1529 break;
1530 case 3:
1531 if (ctx->supervisor > 0) {
1532 /* Set process priority to high */
26d67362 1533 prio = 6;
be147d08
JM		 1534 }
1535 break;
be147d08
JM		 1536 case 7:
1537 if (ctx->supervisor > 1) {
1538 /* Set process priority to very high */
26d67362 1539 prio = 7;
be147d08
JM		 1540 }
1541 break;
be147d08 1542#endif
c80f84e3
JM		 1543 default:
1544 /* nop */
1545 break;
1546 }
26d67362 1547 if (prio) {
a7812ae4 1548 TCGv t0 = tcg_temp_new();
ea363694
AJ		 1549 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1550 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1551 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1552 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1553 tcg_temp_free(t0);
26d67362 1554 }
c80f84e3 1555#endif
9a64fbe4 1556 }
9a64fbe4 1557}
79aceca5 1558/* orc & orc. */
26d67362 1559GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1560/* xor & xor. */
9a64fbe4
FB		 1561GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1562{
9a64fbe4 1563 /* Optimisation for "set to zero" case */
26d67362 1564 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1565 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1566 else
1567 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1568 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1570}
79aceca5
FB		 1571/* ori */
1572GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1573{
76a66253 1574 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1575
9a64fbe4
FB		 1576 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1577 /* NOP */
76a66253 1578 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1579 return;
76a66253 1580 }
26d67362 1581 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1582}
1583/* oris */
1584GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1585{
76a66253 1586 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1587
9a64fbe4
FB		 1588 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1589 /* NOP */
1590 return;
76a66253 1591 }
26d67362 1592 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1593}
1594/* xori */
1595GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1596{
76a66253 1597 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1598
1599 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1600 /* NOP */
1601 return;
1602 }
26d67362 1603 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1604}
79aceca5
FB		 1605/* xoris */
1606GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1607{
76a66253 1608 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1609
1610 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1611 /* NOP */
1612 return;
1613 }
26d67362 1614 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1615}
d9bce9d9 1616/* popcntb : PowerPC 2.03 specification */
05332d70 1617GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1618{
d9bce9d9
JM		 1619#if defined(TARGET_PPC64)
1620 if (ctx->sf_mode)
a7812ae4 1621 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1622 else
1623#endif
a7812ae4 1624 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1625}
1626
1627#if defined(TARGET_PPC64)
1628/* extsw & extsw. */
26d67362 1629GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1630/* cntlzd */
26d67362
AJ		 1631GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1632{
a7812ae4 1633 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1634 if (unlikely(Rc(ctx->opcode) != 0))
1635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1636}
d9bce9d9
JM		 1637#endif
1638
79aceca5
FB		 1639/*** Integer rotate ***/
1640/* rlwimi & rlwimi. */
1641GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1642{
76a66253 1643 uint32_t mb, me, sh;
79aceca5
FB		 1644
1645 mb = MB(ctx->opcode);
1646 me = ME(ctx->opcode);
76a66253 1647 sh = SH(ctx->opcode);
d03ef511
AJ		 1648 if (likely(sh == 0 && mb == 0 && me == 31)) {
1649 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1650 } else {
d03ef511 1651 target_ulong mask;
a7812ae4
PB		 1652 TCGv t1;
1653 TCGv t0 = tcg_temp_new();
54843a58 1654#if defined(TARGET_PPC64)
a7812ae4
PB		 1655 TCGv_i32 t2 = tcg_temp_new_i32();
1656 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1657 tcg_gen_rotli_i32(t2, t2, sh);
1658 tcg_gen_extu_i32_i64(t0, t2);
1659 tcg_temp_free_i32(t2);
54843a58
AJ		 1660#else
1661 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1662#endif
76a66253 1663#if defined(TARGET_PPC64)
d03ef511
AJ		 1664 mb += 32;
1665 me += 32;
76a66253 1666#endif
d03ef511 1667 mask = MASK(mb, me);
a7812ae4 1668 t1 = tcg_temp_new();
d03ef511
AJ		 1669 tcg_gen_andi_tl(t0, t0, mask);
1670 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1671 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1672 tcg_temp_free(t0);
1673 tcg_temp_free(t1);
1674 }
76a66253 1675 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1676 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1677}
1678/* rlwinm & rlwinm. */
1679GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1680{
1681 uint32_t mb, me, sh;
3b46e624 1682
79aceca5
FB		 1683 sh = SH(ctx->opcode);
1684 mb = MB(ctx->opcode);
1685 me = ME(ctx->opcode);
d03ef511
AJ		 1686
1687 if (likely(mb == 0 && me == (31 - sh))) {
1688 if (likely(sh == 0)) {
1689 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1690 } else {
a7812ae4 1691 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1692 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1693 tcg_gen_shli_tl(t0, t0, sh);
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1695 tcg_temp_free(t0);
79aceca5 1696 }
d03ef511 1697 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1698 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1699 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1700 tcg_gen_shri_tl(t0, t0, mb);
1701 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1702 tcg_temp_free(t0);
1703 } else {
a7812ae4 1704 TCGv t0 = tcg_temp_new();
54843a58 1705#if defined(TARGET_PPC64)
a7812ae4 1706 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1707 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1708 tcg_gen_rotli_i32(t1, t1, sh);
1709 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1710 tcg_temp_free_i32(t1);
54843a58
AJ		 1711#else
1712 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1713#endif
76a66253 1714#if defined(TARGET_PPC64)
d03ef511
AJ		 1715 mb += 32;
1716 me += 32;
76a66253 1717#endif
d03ef511
AJ		 1718 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1719 tcg_temp_free(t0);
1720 }
76a66253 1721 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1722 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1723}
1724/* rlwnm & rlwnm. */
1725GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1726{
1727 uint32_t mb, me;
54843a58
AJ		 1728 TCGv t0;
1729#if defined(TARGET_PPC64)
a7812ae4 1730 TCGv_i32 t1, t2;
54843a58 1731#endif
79aceca5
FB		 1732
1733 mb = MB(ctx->opcode);
1734 me = ME(ctx->opcode);
a7812ae4 1735 t0 = tcg_temp_new();
d03ef511 1736 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1737#if defined(TARGET_PPC64)
a7812ae4
PB		 1738 t1 = tcg_temp_new_i32();
1739 t2 = tcg_temp_new_i32();
54843a58
AJ		 1740 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1741 tcg_gen_trunc_i64_i32(t2, t0);
1742 tcg_gen_rotl_i32(t1, t1, t2);
1743 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1744 tcg_temp_free_i32(t1);
1745 tcg_temp_free_i32(t2);
54843a58
AJ		 1746#else
1747 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1748#endif
76a66253
JM		 1749 if (unlikely(mb != 0 || me != 31)) {
1750#if defined(TARGET_PPC64)
1751 mb += 32;
1752 me += 32;
1753#endif
54843a58 1754 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1755 } else {
54843a58 1756 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1757 }
54843a58 1758 tcg_temp_free(t0);
76a66253 1759 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1760 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1761}
1762
d9bce9d9
JM		 1763#if defined(TARGET_PPC64)
1764#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1765GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1766{ \
1767 gen_##name(ctx, 0); \
1768} \
c7697e1f
JM		 1769GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1770 PPC_64B) \
d9bce9d9
JM		 1771{ \
1772 gen_##name(ctx, 1); \
1773}
1774#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1775GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1776{ \
1777 gen_##name(ctx, 0, 0); \
1778} \
c7697e1f
JM		 1779GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1780 PPC_64B) \
d9bce9d9
JM		 1781{ \
1782 gen_##name(ctx, 0, 1); \
1783} \
c7697e1f
JM		 1784GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1785 PPC_64B) \
d9bce9d9
JM		 1786{ \
1787 gen_##name(ctx, 1, 0); \
1788} \
c7697e1f
JM		 1789GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1790 PPC_64B) \
d9bce9d9
JM		 1791{ \
1792 gen_##name(ctx, 1, 1); \
1793}
51789c41 1794
b068d6a7
JM		 1795static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1796 uint32_t me, uint32_t sh)
51789c41 1797{
d03ef511
AJ		 1798 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1799 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1800 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1801 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1802 } else {
a7812ae4 1803 TCGv t0 = tcg_temp_new();
54843a58 1804 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1805 if (likely(mb == 0 && me == 63)) {
54843a58 1806 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1807 } else {
1808 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1809 }
d03ef511 1810 tcg_temp_free(t0);
51789c41 1811 }
51789c41 1812 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1814}
d9bce9d9 1815/* rldicl - rldicl. */
b068d6a7 1816static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1817{
51789c41 1818 uint32_t sh, mb;
d9bce9d9 1819
9d53c753
JM		 1820 sh = SH(ctx->opcode) | (shn << 5);
1821 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1822 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1823}
51789c41 1824GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1825/* rldicr - rldicr. */
b068d6a7 1826static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1827{
51789c41 1828 uint32_t sh, me;
d9bce9d9 1829
9d53c753
JM		 1830 sh = SH(ctx->opcode) | (shn << 5);
1831 me = MB(ctx->opcode) | (men << 5);
51789c41 1832 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1833}
51789c41 1834GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1835/* rldic - rldic. */
b068d6a7 1836static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1837{
51789c41 1838 uint32_t sh, mb;
d9bce9d9 1839
9d53c753
JM		 1840 sh = SH(ctx->opcode) | (shn << 5);
1841 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1842 gen_rldinm(ctx, mb, 63 - sh, sh);
1843}
1844GEN_PPC64_R4(rldic, 0x1E, 0x04);
1845
b068d6a7
JM		 1846static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1847 uint32_t me)
51789c41 1848{
54843a58 1849 TCGv t0;
d03ef511
AJ		 1850
1851 mb = MB(ctx->opcode);
1852 me = ME(ctx->opcode);
a7812ae4 1853 t0 = tcg_temp_new();
d03ef511 1854 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1855 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1856 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1857 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1858 } else {
1859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1860 }
1861 tcg_temp_free(t0);
51789c41 1862 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1863 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1864}
51789c41 1865
d9bce9d9 1866/* rldcl - rldcl. */
b068d6a7 1867static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1868{
51789c41 1869 uint32_t mb;
d9bce9d9 1870
9d53c753 1871 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1872 gen_rldnm(ctx, mb, 63);
d9bce9d9 1873}
36081602 1874GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1875/* rldcr - rldcr. */
b068d6a7 1876static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1877{
51789c41 1878 uint32_t me;
d9bce9d9 1879
9d53c753 1880 me = MB(ctx->opcode) | (men << 5);
51789c41 1881 gen_rldnm(ctx, 0, me);
d9bce9d9 1882}
36081602 1883GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1884/* rldimi - rldimi. */
b068d6a7 1885static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1886{
271a916e 1887 uint32_t sh, mb, me;
d9bce9d9 1888
9d53c753
JM		 1889 sh = SH(ctx->opcode) | (shn << 5);
1890 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1891 me = 63 - sh;
d03ef511
AJ		 1892 if (unlikely(sh == 0 && mb == 0)) {
1893 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1894 } else {
1895 TCGv t0, t1;
1896 target_ulong mask;
1897
a7812ae4 1898 t0 = tcg_temp_new();
54843a58 1899 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1900 t1 = tcg_temp_new();
d03ef511
AJ		 1901 mask = MASK(mb, me);
1902 tcg_gen_andi_tl(t0, t0, mask);
1903 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1904 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1905 tcg_temp_free(t0);
1906 tcg_temp_free(t1);
51789c41 1907 }
51789c41 1908 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1910}
36081602 1911GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1912#endif
1913
79aceca5
FB		 1914/*** Integer shift ***/
1915/* slw & slw. */
26d67362
AJ		 1916GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1917{
fea0c503 1918 TCGv t0;
26d67362
AJ		 1919 int l1, l2;
1920 l1 = gen_new_label();
1921 l2 = gen_new_label();
1922
a7812ae4 1923 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1924 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1925 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1926 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1927 tcg_gen_br(l2);
1928 gen_set_label(l1);
fea0c503 1929 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1930 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1931 gen_set_label(l2);
fea0c503 1932 tcg_temp_free(t0);
26d67362
AJ		 1933 if (unlikely(Rc(ctx->opcode) != 0))
1934 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1935}
79aceca5 1936/* sraw & sraw. */
26d67362
AJ		 1937GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1938{
a7812ae4
PB		 1939 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1940 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1941 if (unlikely(Rc(ctx->opcode) != 0))
1942 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1943}
79aceca5
FB		 1944/* srawi & srawi. */
1945GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1946{
26d67362
AJ		 1947 int sh = SH(ctx->opcode);
1948 if (sh != 0) {
1949 int l1, l2;
fea0c503 1950 TCGv t0;
26d67362
AJ		 1951 l1 = gen_new_label();
1952 l2 = gen_new_label();
a7812ae4 1953 t0 = tcg_temp_local_new();
fea0c503
AJ		 1954 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1955 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1956 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1957 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1958 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1959 tcg_gen_br(l2);
1960 gen_set_label(l1);
269f3e95 1961 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1962 gen_set_label(l2);
fea0c503
AJ		 1963 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1964 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1965 tcg_temp_free(t0);
26d67362
AJ		 1966 } else {
1967 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1968 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1969 }
76a66253 1970 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1972}
1973/* srw & srw. */
26d67362
AJ		 1974GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1975{
fea0c503 1976 TCGv t0, t1;
26d67362
AJ		 1977 int l1, l2;
1978 l1 = gen_new_label();
1979 l2 = gen_new_label();
d9bce9d9 1980
a7812ae4 1981 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1982 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1983 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1984 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1985 tcg_gen_br(l2);
1986 gen_set_label(l1);
a7812ae4 1987 t1 = tcg_temp_new();
fea0c503
AJ		 1988 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1989 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1990 tcg_temp_free(t1);
26d67362 1991 gen_set_label(l2);
fea0c503 1992 tcg_temp_free(t0);
26d67362
AJ		 1993 if (unlikely(Rc(ctx->opcode) != 0))
1994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1995}
d9bce9d9
JM		 1996#if defined(TARGET_PPC64)
1997/* sld & sld. */
26d67362
AJ		 1998GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1999{
fea0c503 2000 TCGv t0;
26d67362
AJ		 2001 int l1, l2;
2002 l1 = gen_new_label();
2003 l2 = gen_new_label();
2004
a7812ae4 2005 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2006 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2007 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2008 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2009 tcg_gen_br(l2);
2010 gen_set_label(l1);
fea0c503 2011 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2012 gen_set_label(l2);
fea0c503 2013 tcg_temp_free(t0);
26d67362
AJ		 2014 if (unlikely(Rc(ctx->opcode) != 0))
2015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2016}
d9bce9d9 2017/* srad & srad. */
26d67362
AJ		 2018GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2019{
a7812ae4
PB		 2020 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2021 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2022 if (unlikely(Rc(ctx->opcode) != 0))
2023 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2024}
d9bce9d9 2025/* sradi & sradi. */
b068d6a7 2026static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2027{
26d67362 2028 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2029 if (sh != 0) {
26d67362 2030 int l1, l2;
fea0c503 2031 TCGv t0;
26d67362
AJ		 2032 l1 = gen_new_label();
2033 l2 = gen_new_label();
a7812ae4 2034 t0 = tcg_temp_local_new();
26d67362 2035 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2036 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2037 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2038 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2039 tcg_gen_br(l2);
2040 gen_set_label(l1);
269f3e95 2041 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2042 gen_set_label(l2);
a9730017 2043 tcg_temp_free(t0);
26d67362
AJ		 2044 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2045 } else {
2046 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2047 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2048 }
d9bce9d9 2049 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2050 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2051}
c7697e1f 2052GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2053{
2054 gen_sradi(ctx, 0);
2055}
c7697e1f 2056GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2057{
2058 gen_sradi(ctx, 1);
2059}
2060/* srd & srd. */
26d67362
AJ		 2061GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2062{
fea0c503 2063 TCGv t0;
26d67362
AJ		 2064 int l1, l2;
2065 l1 = gen_new_label();
2066 l2 = gen_new_label();
2067
a7812ae4 2068 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2069 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2070 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2071 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2072 tcg_gen_br(l2);
2073 gen_set_label(l1);
fea0c503 2074 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2075 gen_set_label(l2);
fea0c503 2076 tcg_temp_free(t0);
26d67362
AJ		 2077 if (unlikely(Rc(ctx->opcode) != 0))
2078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2079}
d9bce9d9 2080#endif
79aceca5
FB		 2081
2082/*** Floating-Point arithmetic ***/
7c58044c 2083#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2084GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2085{ \
76a66253 2086 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2087 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2088 return; \
2089 } \
7c58044c 2090 gen_reset_fpstatus(); \
af12906f
AJ		 2091 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2092 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2093 if (isfloat) { \
af12906f 2094 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2095 } \
af12906f
AJ		 2096 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2097 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2098}
2099
7c58044c
JM		 2100#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2101_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2102_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2103
7c58044c
JM		 2104#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2105GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2106{ \
76a66253 2107 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2108 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2109 return; \
2110 } \
7c58044c 2111 gen_reset_fpstatus(); \
af12906f
AJ		 2112 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2113 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2114 if (isfloat) { \
af12906f 2115 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2116 } \
af12906f
AJ		 2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2118 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2119}
7c58044c
JM		 2120#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2121_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2122_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2123
7c58044c
JM		 2124#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2125GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2126{ \
76a66253 2127 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2128 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2129 return; \
2130 } \
7c58044c 2131 gen_reset_fpstatus(); \
af12906f
AJ		 2132 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2133 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2134 if (isfloat) { \
af12906f 2135 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2136 } \
af12906f
AJ		 2137 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2138 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2139}
7c58044c
JM		 2140#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2141_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2142_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2143
7c58044c 2144#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2145GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2146{ \
76a66253 2147 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2148 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2149 return; \
2150 } \
7c58044c 2151 gen_reset_fpstatus(); \
af12906f
AJ		 2152 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2153 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2154 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2155}
2156
7c58044c 2157#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2158GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2159{ \
76a66253 2160 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2161 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2162 return; \
2163 } \
7c58044c 2164 gen_reset_fpstatus(); \
af12906f
AJ		 2165 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2167 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2168}
2169
9a64fbe4 2170/* fadd - fadds */
7c58044c 2171GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2172/* fdiv - fdivs */
7c58044c 2173GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2174/* fmul - fmuls */
7c58044c 2175GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2176
d7e4b87e 2177/* fre */
7c58044c 2178GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2179
a750fc0b 2180/* fres */
7c58044c 2181GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2182
a750fc0b 2183/* frsqrte */
7c58044c
JM		 2184GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2185
2186/* frsqrtes */
af12906f 2187GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2188{
af12906f
AJ		 2189 if (unlikely(!ctx->fpu_enabled)) {
2190 GEN_EXCP_NO_FP(ctx);
2191 return;
2192 }
2193 gen_reset_fpstatus();
2194 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2195 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2196 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2197}
79aceca5 2198
a750fc0b 2199/* fsel */
7c58044c 2200_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2201/* fsub - fsubs */
7c58044c 2202GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2203/* Optional: */
2204/* fsqrt */
a750fc0b 2205GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2206{
76a66253 2207 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2208 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2209 return;
2210 }
7c58044c 2211 gen_reset_fpstatus();
af12906f
AJ		 2212 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2214}
79aceca5 2215
a750fc0b 2216GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2217{
76a66253 2218 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2219 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2220 return;
2221 }
7c58044c 2222 gen_reset_fpstatus();
af12906f
AJ		 2223 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2224 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2225 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2226}
2227
2228/*** Floating-Point multiply-and-add ***/
4ecc3190 2229/* fmadd - fmadds */
7c58044c 2230GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2231/* fmsub - fmsubs */
7c58044c 2232GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2233/* fnmadd - fnmadds */
7c58044c 2234GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2235/* fnmsub - fnmsubs */
7c58044c 2236GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2237
2238/*** Floating-Point round & convert ***/
2239/* fctiw */
7c58044c 2240GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2241/* fctiwz */
7c58044c 2242GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2243/* frsp */
7c58044c 2244GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2245#if defined(TARGET_PPC64)
2246/* fcfid */
7c58044c 2247GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2248/* fctid */
7c58044c 2249GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2250/* fctidz */
7c58044c 2251GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2252#endif
79aceca5 2253
d7e4b87e 2254/* frin */
7c58044c 2255GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2256/* friz */
7c58044c 2257GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2258/* frip */
7c58044c 2259GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2260/* frim */
7c58044c 2261GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2262
79aceca5
FB		 2263/*** Floating-Point compare ***/
2264/* fcmpo */
76a66253 2265GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2266{
76a66253 2267 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2268 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2269 return;
2270 }
7c58044c 2271 gen_reset_fpstatus();
af12906f
AJ		 2272 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2273 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2274 gen_helper_float_check_status();
79aceca5
FB		 2275}
2276
2277/* fcmpu */
76a66253 2278GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2279{
76a66253 2280 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2281 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2282 return;
2283 }
7c58044c 2284 gen_reset_fpstatus();
af12906f
AJ		 2285 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2286 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2287 gen_helper_float_check_status();
79aceca5
FB		 2288}
2289
9a64fbe4
FB		 2290/*** Floating-point move ***/
2291/* fabs */
7c58044c
JM		 2292/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2293GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2294
2295/* fmr - fmr. */
7c58044c 2296/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2297GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2298{
76a66253 2299 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2300 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2301 return;
2302 }
af12906f
AJ		 2303 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2304 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2305}
2306
2307/* fnabs */
7c58044c
JM		 2308/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2309GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2310/* fneg */
7c58044c
JM		 2311/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2312GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2313
79aceca5
FB		 2314/*** Floating-Point status & ctrl register ***/
2315/* mcrfs */
2316GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2317{
7c58044c
JM		 2318 int bfa;
2319
76a66253 2320 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2321 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2322 return;
2323 }
7c58044c
JM		 2324 gen_optimize_fprf();
2325 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2326 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2327 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2328 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2329}
2330
2331/* mffs */
2332GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2333{
76a66253 2334 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2335 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2336 return;
2337 }
7c58044c
JM		 2338 gen_optimize_fprf();
2339 gen_reset_fpstatus();
af12906f
AJ		 2340 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2341 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2342}
2343
2344/* mtfsb0 */
2345GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2346{
fb0eaffc 2347 uint8_t crb;
3b46e624 2348
76a66253 2349 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2350 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2351 return;
2352 }
7c58044c
JM		 2353 crb = 32 - (crbD(ctx->opcode) >> 2);
2354 gen_optimize_fprf();
2355 gen_reset_fpstatus();
2356 if (likely(crb != 30 && crb != 29))
af12906f 2357 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
7c58044c 2358 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2359 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2360 }
79aceca5
FB		 2361}
2362
2363/* mtfsb1 */
2364GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2365{
fb0eaffc 2366 uint8_t crb;
3b46e624 2367
76a66253 2368 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2369 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2370 return;
2371 }
7c58044c
JM		 2372 crb = 32 - (crbD(ctx->opcode) >> 2);
2373 gen_optimize_fprf();
2374 gen_reset_fpstatus();
2375 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2376 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
0f2f39c2 2377 TCGv_i32 t0 = tcg_const_i32(crb);
af12906f 2378 gen_helper_fpscr_setbit(t0);
0f2f39c2 2379 tcg_temp_free_i32(t0);
af12906f 2380 }
7c58044c 2381 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2382 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2383 }
2384 /* We can raise a differed exception */
af12906f 2385 gen_helper_float_check_status();
79aceca5
FB		 2386}
2387
2388/* mtfsf */
2389GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2390{
0f2f39c2 2391 TCGv_i32 t0;
af12906f 2392
76a66253 2393 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2394 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2395 return;
2396 }
7c58044c 2397 gen_optimize_fprf();
7c58044c 2398 gen_reset_fpstatus();
af12906f
AJ		 2399 t0 = tcg_const_i32(FM(ctx->opcode));
2400 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2401 tcg_temp_free_i32(t0);
7c58044c 2402 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2403 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2404 }
2405 /* We can raise a differed exception */
af12906f 2406 gen_helper_float_check_status();
79aceca5
FB		 2407}
2408
2409/* mtfsfi */
2410GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2411{
7c58044c 2412 int bf, sh;
0f2f39c2
AJ		 2413 TCGv_i64 t0;
2414 TCGv_i32 t1;
7c58044c 2415
76a66253 2416 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2417 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2418 return;
2419 }
7c58044c
JM		 2420 bf = crbD(ctx->opcode) >> 2;
2421 sh = 7 - bf;
2422 gen_optimize_fprf();
7c58044c 2423 gen_reset_fpstatus();
0f2f39c2 2424 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2425 t1 = tcg_const_i32(1 << sh);
2426 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2427 tcg_temp_free_i64(t0);
2428 tcg_temp_free_i32(t1);
7c58044c 2429 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2430 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2431 }
2432 /* We can raise a differed exception */
af12906f 2433 gen_helper_float_check_status();
79aceca5
FB		 2434}
2435
76a66253
JM		 2436/*** Addressing modes ***/
2437/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2438static always_inline void gen_addr_imm_index (TCGv EA,
2439 DisasContext *ctx,
b068d6a7 2440 target_long maskl)
76a66253
JM		 2441{
2442 target_long simm = SIMM(ctx->opcode);
2443
be147d08 2444 simm &= ~maskl;
e2be8d8d
AJ		 2445 if (rA(ctx->opcode) == 0)
2446 tcg_gen_movi_tl(EA, simm);
2447 else if (likely(simm != 0))
2448 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2449 else
2450 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2451}
2452
e2be8d8d
AJ		 2453static always_inline void gen_addr_reg_index (TCGv EA,
2454 DisasContext *ctx)
76a66253 2455{
e2be8d8d
AJ		 2456 if (rA(ctx->opcode) == 0)
2457 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2458 else
2459 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2460}
2461
e2be8d8d
AJ		 2462static always_inline void gen_addr_register (TCGv EA,
2463 DisasContext *ctx)
76a66253 2464{
e2be8d8d
AJ		 2465 if (rA(ctx->opcode) == 0)
2466 tcg_gen_movi_tl(EA, 0);
2467 else
2468 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2469}
2470
7863667f
JM		 2471#if defined(TARGET_PPC64)
2472#define _GEN_MEM_FUNCS(name, mode) \
2473 &gen_op_##name##_##mode, \
2474 &gen_op_##name##_le_##mode, \
2475 &gen_op_##name##_64_##mode, \
2476 &gen_op_##name##_le_64_##mode
2477#else
2478#define _GEN_MEM_FUNCS(name, mode) \
2479 &gen_op_##name##_##mode, \
2480 &gen_op_##name##_le_##mode
2481#endif
9a64fbe4 2482#if defined(CONFIG_USER_ONLY)
d9bce9d9 2483#if defined(TARGET_PPC64)
7863667f 2484#define NB_MEM_FUNCS 4
d9bce9d9 2485#else
7863667f 2486#define NB_MEM_FUNCS 2
d9bce9d9 2487#endif
7863667f
JM		 2488#define GEN_MEM_FUNCS(name) \
2489 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2490#else
d9bce9d9 2491#if defined(TARGET_PPC64)
7863667f 2492#define NB_MEM_FUNCS 12
2857068e 2493#else
7863667f 2494#define NB_MEM_FUNCS 6
2857068e 2495#endif
7863667f
JM		 2496#define GEN_MEM_FUNCS(name) \
2497 _GEN_MEM_FUNCS(name, user), \
2498 _GEN_MEM_FUNCS(name, kernel), \
2499 _GEN_MEM_FUNCS(name, hypv)
2500#endif
2501
2502/*** Integer load ***/
b61f2753
AJ		 2503#if defined(TARGET_PPC64)
2504#define GEN_QEMU_LD_PPC64(width) \
2505static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2506{ \
2507 if (likely(flags & 2)) \
2508 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2509 else { \
a7812ae4 2510 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2511 tcg_gen_ext32u_tl(addr, t1); \
2512 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2513 tcg_temp_free(addr); \
2514 } \
2515}
2516GEN_QEMU_LD_PPC64(8u)
2517GEN_QEMU_LD_PPC64(8s)
2518GEN_QEMU_LD_PPC64(16u)
2519GEN_QEMU_LD_PPC64(16s)
2520GEN_QEMU_LD_PPC64(32u)
2521GEN_QEMU_LD_PPC64(32s)
2522GEN_QEMU_LD_PPC64(64)
2523
2524#define GEN_QEMU_ST_PPC64(width) \
2525static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2526{ \
2527 if (likely(flags & 2)) \
2528 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2529 else { \
a7812ae4 2530 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2531 tcg_gen_ext32u_tl(addr, t1); \
2532 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2533 tcg_temp_free(addr); \
2534 } \
2535}
2536GEN_QEMU_ST_PPC64(8)
2537GEN_QEMU_ST_PPC64(16)
2538GEN_QEMU_ST_PPC64(32)
2539GEN_QEMU_ST_PPC64(64)
2540
ea363694 2541static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2542{
ea363694 2543 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2544}
2545
ea363694 2546static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2547{
ea363694 2548 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2549}
2550
ea363694 2551static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2552{
2553 if (unlikely(flags & 1)) {
a7812ae4 2554 TCGv_i32 t0;
ea363694 2555 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2556 t0 = tcg_temp_new_i32();
ea363694
AJ		 2557 tcg_gen_trunc_tl_i32(t0, arg0);
2558 tcg_gen_bswap16_i32(t0, t0);
2559 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2560 tcg_temp_free_i32(t0);
b61f2753 2561 } else
ea363694 2562 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2563}
2564
ea363694 2565static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2566{
2567 if (unlikely(flags & 1)) {
a7812ae4 2568 TCGv_i32 t0;
ea363694 2569 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2570 t0 = tcg_temp_new_i32();
ea363694
AJ		 2571 tcg_gen_trunc_tl_i32(t0, arg0);
2572 tcg_gen_bswap16_i32(t0, t0);
2573 tcg_gen_extu_i32_tl(arg0, t0);
2574 tcg_gen_ext16s_tl(arg0, arg0);
a7812ae4 2575 tcg_temp_free_i32(t0);
b61f2753 2576 } else
ea363694 2577 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2578}
2579
ea363694 2580static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2581{
2582 if (unlikely(flags & 1)) {
a7812ae4 2583 TCGv_i32 t0;
ea363694 2584 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2585 t0 = tcg_temp_new_i32();
ea363694
AJ		 2586 tcg_gen_trunc_tl_i32(t0, arg0);
2587 tcg_gen_bswap_i32(t0, t0);
2588 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2589 tcg_temp_free_i32(t0);
b61f2753 2590 } else
ea363694 2591 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2592}
2593
ea363694 2594static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2595{
2596 if (unlikely(flags & 1)) {
a7812ae4 2597 TCGv_i32 t0;
ea363694 2598 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2599 t0 = tcg_temp_new_i32();
ea363694
AJ		 2600 tcg_gen_trunc_tl_i32(t0, arg0);
2601 tcg_gen_bswap_i32(t0, t0);
2602 tcg_gen_ext_i32_tl(arg0, t0);
a7812ae4 2603 tcg_temp_free_i32(t0);
b61f2753 2604 } else
ea363694 2605 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2606}
2607
ea363694 2608static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2609{
ea363694 2610 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2611 if (unlikely(flags & 1))
ea363694 2612 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2613}
2614
ea363694 2615static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2616{
ea363694 2617 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2618}
2619
ea363694 2620static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2621{
2622 if (unlikely(flags & 1)) {
a7812ae4
PB		 2623 TCGv_i32 t0;
2624 TCGv_i64 t1;
2625 t0 = tcg_temp_new_i32();
ea363694
AJ		 2626 tcg_gen_trunc_tl_i32(t0, arg0);
2627 tcg_gen_ext16u_i32(t0, t0);
2628 tcg_gen_bswap16_i32(t0, t0);
a7812ae4 2629 t1 = tcg_temp_new_i64();
ea363694 2630 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2631 tcg_temp_free_i32(t0);
ea363694 2632 gen_qemu_st16_ppc64(t1, arg1, flags);
a7812ae4 2633 tcg_temp_free_i64(t1);
b61f2753 2634 } else
ea363694 2635 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2636}
2637
ea363694 2638static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2639{
2640 if (unlikely(flags & 1)) {
a7812ae4
PB		 2641 TCGv_i32 t0;
2642 TCGv_i64 t1;
2643 t0 = tcg_temp_new_i32();
ea363694
AJ		 2644 tcg_gen_trunc_tl_i32(t0, arg0);
2645 tcg_gen_bswap_i32(t0, t0);
a7812ae4 2646 t1 = tcg_temp_new_i64();
ea363694 2647 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2648 tcg_temp_free_i32(t0);
ea363694 2649 gen_qemu_st32_ppc64(t1, arg1, flags);
a7812ae4 2650 tcg_temp_free_i64(t1);
b61f2753 2651 } else
ea363694 2652 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2653}
2654
ea363694 2655static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2656{
2657 if (unlikely(flags & 1)) {
a7812ae4 2658 TCGv_i64 t0 = tcg_temp_new_i64();
ea363694
AJ		 2659 tcg_gen_bswap_i64(t0, arg0);
2660 gen_qemu_st64_ppc64(t0, arg1, flags);
a7812ae4 2661 tcg_temp_free_i64(t0);
b61f2753 2662 } else
ea363694 2663 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2664}
2665
2666
2667#else /* defined(TARGET_PPC64) */
a0d7d5a7
AJ		 2668#define GEN_QEMU_LD_PPC32(width) \
2669static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2670{ \
2671 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2672}
2673GEN_QEMU_LD_PPC32(8u)
2674GEN_QEMU_LD_PPC32(8s)
2675GEN_QEMU_LD_PPC32(16u)
2676GEN_QEMU_LD_PPC32(16s)
2677GEN_QEMU_LD_PPC32(32u)
2678GEN_QEMU_LD_PPC32(32s)
a0d7d5a7
AJ		 2679static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2680{
2681 tcg_gen_qemu_ld64(arg0, arg1, flags >> 1);
2682}
b61f2753 2683
a0d7d5a7
AJ		 2684#define GEN_QEMU_ST_PPC32(width) \
2685static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2686{ \
2687 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2688}
2689GEN_QEMU_ST_PPC32(8)
2690GEN_QEMU_ST_PPC32(16)
2691GEN_QEMU_ST_PPC32(32)
a0d7d5a7
AJ		 2692static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2693{
2694 tcg_gen_qemu_st64(arg0, arg1, flags >> 1);
2695}
b61f2753 2696
ea363694 2697static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2698{
ea363694 2699 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2700}
2701
ea363694 2702static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2703{
ea363694 2704 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2705}
2706
ea363694 2707static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2708{
ea363694 2709 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2710 if (unlikely(flags & 1))
ea363694 2711 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2712}
2713
ea363694 2714static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2715{
2716 if (unlikely(flags & 1)) {
ea363694
AJ		 2717 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2718 tcg_gen_bswap16_i32(arg0, arg0);
2719 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2720 } else
ea363694 2721 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2722}
2723
ea363694 2724static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2725{
ea363694 2726 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2727 if (unlikely(flags & 1))
ea363694 2728 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2729}
2730
a0d7d5a7
AJ		 2731static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags)
2732{
2733 gen_qemu_ld64_ppc32(arg0, arg1, flags);
2734 if (unlikely(flags & 1))
2735 tcg_gen_bswap_i64(arg0, arg0);
2736}
2737
ea363694 2738static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2739{
e32ad5c2 2740 gen_qemu_st8_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2741}
2742
ea363694 2743static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2744{
2745 if (unlikely(flags & 1)) {
a7812ae4 2746 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2747 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2748 tcg_gen_bswap16_i32(temp, temp);
e32ad5c2 2749 gen_qemu_st16_ppc32(temp, arg1, flags);
a7812ae4 2750 tcg_temp_free_i32(temp);
b61f2753 2751 } else
e32ad5c2 2752 gen_qemu_st16_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2753}
2754
ea363694 2755static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2756{
2757 if (unlikely(flags & 1)) {
a7812ae4 2758 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2759 tcg_gen_bswap_i32(temp, arg0);
e32ad5c2 2760 gen_qemu_st32_ppc32(temp, arg1, flags);
a7812ae4 2761 tcg_temp_free_i32(temp);
b61f2753 2762 } else
e32ad5c2 2763 gen_qemu_st32_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2764}
2765
a0d7d5a7
AJ		 2766static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags)
2767{
2768 if (unlikely(flags & 1)) {
2769 TCGv_i64 temp = tcg_temp_new_i64();
2770 tcg_gen_bswap_i64(temp, arg0);
2771 gen_qemu_st64_ppc32(temp, arg1, flags);
2772 tcg_temp_free_i64(temp);
2773 } else
2774 gen_qemu_st64_ppc32(arg0, arg1, flags);
2775}
b61f2753
AJ		 2776#endif
2777
0c8aacd4
AJ		 2778#define GEN_LD(name, ldop, opc, type) \
2779GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2780{ \
0c8aacd4 2781 TCGv EA = tcg_temp_new(); \
a7859e89 2782 gen_set_access_type(ACCESS_INT); \
b61f2753 2783 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2784 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2785 tcg_temp_free(EA); \
79aceca5
FB		 2786}
2787
0c8aacd4
AJ		 2788#define GEN_LDU(name, ldop, opc, type) \
2789GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2790{ \
b61f2753 2791 TCGv EA; \
76a66253
JM		 2792 if (unlikely(rA(ctx->opcode) == 0 || \
2793 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2794 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2795 return; \
9a64fbe4 2796 } \
0c8aacd4 2797 EA = tcg_temp_new(); \
a7859e89 2798 gen_set_access_type(ACCESS_INT); \
9d53c753 2799 if (type == PPC_64B) \
b61f2753 2800 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2801 else \
b61f2753 2802 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2803 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2805 tcg_temp_free(EA); \
79aceca5
FB		 2806}
2807
0c8aacd4
AJ		 2808#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2809GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2810{ \
b61f2753 2811 TCGv EA; \
76a66253
JM		 2812 if (unlikely(rA(ctx->opcode) == 0 || \
2813 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2814 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2815 return; \
9a64fbe4 2816 } \
0c8aacd4 2817 EA = tcg_temp_new(); \
a7859e89 2818 gen_set_access_type(ACCESS_INT); \
b61f2753 2819 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2820 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2822 tcg_temp_free(EA); \
79aceca5
FB		 2823}
2824
0c8aacd4
AJ		 2825#define GEN_LDX(name, ldop, opc2, opc3, type) \
2826GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2827{ \
0c8aacd4 2828 TCGv EA = tcg_temp_new(); \
a7859e89 2829 gen_set_access_type(ACCESS_INT); \
b61f2753 2830 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2831 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2832 tcg_temp_free(EA); \
79aceca5
FB		 2833}
2834
0c8aacd4
AJ		 2835#define GEN_LDS(name, ldop, op, type) \
2836GEN_LD(name, ldop, op | 0x20, type); \
2837GEN_LDU(name, ldop, op | 0x21, type); \
2838GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2839GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2840
2841/* lbz lbzu lbzux lbzx */
0c8aacd4 2842GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2843/* lha lhau lhaux lhax */
0c8aacd4 2844GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2845/* lhz lhzu lhzux lhzx */
0c8aacd4 2846GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2847/* lwz lwzu lwzux lwzx */
0c8aacd4 2848GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2849#if defined(TARGET_PPC64)
d9bce9d9 2850/* lwaux */
0c8aacd4 2851GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2852/* lwax */
0c8aacd4 2853GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2854/* ldux */
0c8aacd4 2855GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2856/* ldx */
0c8aacd4 2857GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2858GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2859{
b61f2753 2860 TCGv EA;
d9bce9d9
JM		 2861 if (Rc(ctx->opcode)) {
2862 if (unlikely(rA(ctx->opcode) == 0 ||
2863 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2864 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2865 return;
2866 }
2867 }
a7812ae4 2868 EA = tcg_temp_new();
a7859e89 2869 gen_set_access_type(ACCESS_INT);
b61f2753 2870 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2871 if (ctx->opcode & 0x02) {
2872 /* lwa (lwau is undefined) */
b61f2753 2873 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2874 } else {
2875 /* ld - ldu */
b61f2753 2876 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2877 }
d9bce9d9 2878 if (Rc(ctx->opcode))
b61f2753
AJ		 2879 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2880 tcg_temp_free(EA);
d9bce9d9 2881}
be147d08
JM		 2882/* lq */
2883GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2884{
2885#if defined(CONFIG_USER_ONLY)
2886 GEN_EXCP_PRIVOPC(ctx);
2887#else
2888 int ra, rd;
b61f2753 2889 TCGv EA;
be147d08
JM		 2890
2891 /* Restore CPU state */
2892 if (unlikely(ctx->supervisor == 0)) {
2893 GEN_EXCP_PRIVOPC(ctx);
2894 return;
2895 }
2896 ra = rA(ctx->opcode);
2897 rd = rD(ctx->opcode);
2898 if (unlikely((rd & 1) || rd == ra)) {
2899 GEN_EXCP_INVAL(ctx);
2900 return;
2901 }
2902 if (unlikely(ctx->mem_idx & 1)) {
2903 /* Little-endian mode is not handled */
2904 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2905 return;
2906 }
a7812ae4 2907 EA = tcg_temp_new();
a7859e89 2908 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 2909 gen_addr_imm_index(EA, ctx, 0x0F);
2910 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2911 tcg_gen_addi_tl(EA, EA, 8);
2912 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2913 tcg_temp_free(EA);
be147d08
JM		 2914#endif
2915}
d9bce9d9 2916#endif
79aceca5
FB		 2917
2918/*** Integer store ***/
0c8aacd4
AJ		 2919#define GEN_ST(name, stop, opc, type) \
2920GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2921{ \
0c8aacd4 2922 TCGv EA = tcg_temp_new(); \
a7859e89 2923 gen_set_access_type(ACCESS_INT); \
b61f2753 2924 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2925 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2926 tcg_temp_free(EA); \
79aceca5
FB		 2927}
2928
0c8aacd4
AJ		 2929#define GEN_STU(name, stop, opc, type) \
2930GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2931{ \
b61f2753 2932 TCGv EA; \
76a66253 2933 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2934 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2935 return; \
9a64fbe4 2936 } \
0c8aacd4 2937 EA = tcg_temp_new(); \
a7859e89 2938 gen_set_access_type(ACCESS_INT); \
9d53c753 2939 if (type == PPC_64B) \
b61f2753 2940 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2941 else \
b61f2753 2942 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2943 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2944 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2945 tcg_temp_free(EA); \
79aceca5
FB		 2946}
2947
0c8aacd4
AJ		 2948#define GEN_STUX(name, stop, opc2, opc3, type) \
2949GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2950{ \
b61f2753 2951 TCGv EA; \
76a66253 2952 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2953 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2954 return; \
9a64fbe4 2955 } \
0c8aacd4 2956 EA = tcg_temp_new(); \
a7859e89 2957 gen_set_access_type(ACCESS_INT); \
b61f2753 2958 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2959 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2960 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2961 tcg_temp_free(EA); \
79aceca5
FB		 2962}
2963
0c8aacd4
AJ		 2964#define GEN_STX(name, stop, opc2, opc3, type) \
2965GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2966{ \
0c8aacd4 2967 TCGv EA = tcg_temp_new(); \
a7859e89 2968 gen_set_access_type(ACCESS_INT); \
b61f2753 2969 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2970 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2971 tcg_temp_free(EA); \
79aceca5
FB		 2972}
2973
0c8aacd4
AJ		 2974#define GEN_STS(name, stop, op, type) \
2975GEN_ST(name, stop, op | 0x20, type); \
2976GEN_STU(name, stop, op | 0x21, type); \
2977GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2978GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2979
2980/* stb stbu stbux stbx */
0c8aacd4 2981GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2982/* sth sthu sthux sthx */
0c8aacd4 2983GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2984/* stw stwu stwux stwx */
0c8aacd4 2985GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2986#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2987GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2988GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2989GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2990{
be147d08 2991 int rs;
b61f2753 2992 TCGv EA;
be147d08
JM		 2993
2994 rs = rS(ctx->opcode);
2995 if ((ctx->opcode & 0x3) == 0x2) {
2996#if defined(CONFIG_USER_ONLY)
2997 GEN_EXCP_PRIVOPC(ctx);
2998#else
2999 /* stq */
3000 if (unlikely(ctx->supervisor == 0)) {
3001 GEN_EXCP_PRIVOPC(ctx);
3002 return;
3003 }
3004 if (unlikely(rs & 1)) {
e1833e1f 3005 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 3006 return;
3007 }
be147d08
JM		 3008 if (unlikely(ctx->mem_idx & 1)) {
3009 /* Little-endian mode is not handled */
3010 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3011 return;
3012 }
a7812ae4 3013 EA = tcg_temp_new();
a7859e89 3014 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3015 gen_addr_imm_index(EA, ctx, 0x03);
3016 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3017 tcg_gen_addi_tl(EA, EA, 8);
3018 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3019 tcg_temp_free(EA);
be147d08
JM		 3020#endif
3021 } else {
3022 /* std / stdu */
3023 if (Rc(ctx->opcode)) {
3024 if (unlikely(rA(ctx->opcode) == 0)) {
3025 GEN_EXCP_INVAL(ctx);
3026 return;
3027 }
3028 }
a7812ae4 3029 EA = tcg_temp_new();
a7859e89 3030 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3031 gen_addr_imm_index(EA, ctx, 0x03);
3032 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 3033 if (Rc(ctx->opcode))
b61f2753
AJ		 3034 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3035 tcg_temp_free(EA);
d9bce9d9 3036 }
d9bce9d9
JM		 3037}
3038#endif
79aceca5
FB		 3039/*** Integer load and store with byte reverse ***/
3040/* lhbrx */
b61f2753
AJ		 3041void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3042{
a7812ae4
PB		 3043 TCGv_i32 temp = tcg_temp_new_i32();
3044 gen_qemu_ld16u(t0, t1, flags);
3045 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3046 tcg_gen_bswap16_i32(temp, temp);
3047 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3048 tcg_temp_free_i32(temp);
b61f2753 3049}
0c8aacd4 3050GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3051
79aceca5 3052/* lwbrx */
b61f2753
AJ		 3053void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3054{
a7812ae4
PB		 3055 TCGv_i32 temp = tcg_temp_new_i32();
3056 gen_qemu_ld32u(t0, t1, flags);
3057 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3058 tcg_gen_bswap_i32(temp, temp);
3059 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3060 tcg_temp_free_i32(temp);
b61f2753 3061}
0c8aacd4 3062GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3063
79aceca5 3064/* sthbrx */
b61f2753
AJ		 3065void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3066{
a7812ae4
PB		 3067 TCGv_i32 temp = tcg_temp_new_i32();
3068 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3069 tcg_gen_trunc_tl_i32(temp, t0);
3070 tcg_gen_ext16u_i32(temp, temp);
3071 tcg_gen_bswap16_i32(temp, temp);
a7812ae4
PB		 3072 tcg_gen_extu_i32_tl(t2, temp);
3073 tcg_temp_free_i32(temp);
3074 gen_qemu_st16(t2, t1, flags);
3075 tcg_temp_free(t2);
b61f2753 3076}
0c8aacd4 3077GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3078
79aceca5 3079/* stwbrx */
b61f2753
AJ		 3080void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3081{
a7812ae4
PB		 3082 TCGv_i32 temp = tcg_temp_new_i32();
3083 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3084 tcg_gen_trunc_tl_i32(temp, t0);
3085 tcg_gen_bswap_i32(temp, temp);
a7812ae4
PB		 3086 tcg_gen_extu_i32_tl(t2, temp);
3087 tcg_temp_free_i32(temp);
87006d13 3088 gen_qemu_st32(t2, t1, flags);
a7812ae4 3089 tcg_temp_free(t2);
b61f2753 3090}
0c8aacd4 3091GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3092
3093/*** Integer load and store multiple ***/
3094/* lmw */
3095GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3096{
ff4a62cd
AJ		 3097 TCGv t0 = tcg_temp_new();
3098 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
76a66253 3099 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3100 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3101 gen_addr_imm_index(t0, ctx, 0);
3102 gen_helper_lmw(t0, t1);
3103 tcg_temp_free(t0);
3104 tcg_temp_free_i32(t1);
79aceca5
FB		 3105}
3106
3107/* stmw */
3108GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3109{
ff4a62cd
AJ		 3110 TCGv t0 = tcg_temp_new();
3111 TCGv_i32 t1 = tcg_const_i32(rS(ctx->opcode));
76a66253 3112 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3113 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3114 gen_addr_imm_index(t0, ctx, 0);
3115 gen_helper_stmw(t0, t1);
3116 tcg_temp_free(t0);
3117 tcg_temp_free_i32(t1);
79aceca5
FB		 3118}
3119
3120/*** Integer load and store strings ***/
9a64fbe4
FB		 3121#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
3122#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 3123/* string load & stores are by definition endian-safe */
3124#define gen_op_lswi_le_raw gen_op_lswi_raw
3125#define gen_op_lswi_le_user gen_op_lswi_user
3126#define gen_op_lswi_le_kernel gen_op_lswi_kernel
3127#define gen_op_lswi_le_hypv gen_op_lswi_hypv
3128#define gen_op_lswi_le_64_raw gen_op_lswi_raw
3129#define gen_op_lswi_le_64_user gen_op_lswi_user
3130#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
3131#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 3132static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
3133 GEN_MEM_FUNCS(lswi),
d9bce9d9 3134};
e7c24003
JM		 3135#define gen_op_lswx_le_raw gen_op_lswx_raw
3136#define gen_op_lswx_le_user gen_op_lswx_user
3137#define gen_op_lswx_le_kernel gen_op_lswx_kernel
3138#define gen_op_lswx_le_hypv gen_op_lswx_hypv
3139#define gen_op_lswx_le_64_raw gen_op_lswx_raw
3140#define gen_op_lswx_le_64_user gen_op_lswx_user
3141#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
3142#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 3143static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
3144 GEN_MEM_FUNCS(lswx),
d9bce9d9 3145};
e7c24003
JM		 3146#define gen_op_stsw_le_raw gen_op_stsw_raw
3147#define gen_op_stsw_le_user gen_op_stsw_user
3148#define gen_op_stsw_le_kernel gen_op_stsw_kernel
3149#define gen_op_stsw_le_hypv gen_op_stsw_hypv
3150#define gen_op_stsw_le_64_raw gen_op_stsw_raw
3151#define gen_op_stsw_le_64_user gen_op_stsw_user
3152#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3153#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 3154static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3155 GEN_MEM_FUNCS(stsw),
9a64fbe4 3156};
9a64fbe4 3157
79aceca5 3158/* lswi */
3fc6c082 3159/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3160 * rA is in the range of registers to be loaded.
3161 * In an other hand, IBM says this is valid, but rA won't be loaded.
3162 * For now, I'll follow the spec...
3163 */
05332d70 3164GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 3165{
3166 int nb = NB(ctx->opcode);
3167 int start = rD(ctx->opcode);
9a64fbe4 3168 int ra = rA(ctx->opcode);
79aceca5
FB		 3169 int nr;
3170
3171 if (nb == 0)
3172 nb = 32;
3173 nr = nb / 4;
76a66253
JM		 3174 if (unlikely(((start + nr) > 32 &&
3175 start <= ra && (start + nr - 32) > ra) ||
3176 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3177 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3178 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3179 return;
297d8e62 3180 }
8dd4983c 3181 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3182 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3183 gen_addr_register(cpu_T[0], ctx);
86c581dc 3184 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3185 op_ldsts(lswi, start);
79aceca5
FB		 3186}
3187
3188/* lswx */
05332d70 3189GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3190{
9a64fbe4
FB		 3191 int ra = rA(ctx->opcode);
3192 int rb = rB(ctx->opcode);
3193
76a66253 3194 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3195 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3196 gen_addr_reg_index(cpu_T[0], ctx);
9a64fbe4 3197 if (ra == 0) {
9a64fbe4 3198 ra = rb;
79aceca5 3199 }
3d7b417e 3200 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3201 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 3202}
3203
3204/* stswi */
05332d70 3205GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3206{
4b3686fa
FB		 3207 int nb = NB(ctx->opcode);
3208
76a66253 3209 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3210 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3211 gen_addr_register(cpu_T[0], ctx);
4b3686fa
FB		 3212 if (nb == 0)
3213 nb = 32;
86c581dc 3214 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3215 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3216}
3217
3218/* stswx */
05332d70 3219GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3220{
8dd4983c 3221 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3222 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3223 gen_addr_reg_index(cpu_T[0], ctx);
3d7b417e 3224 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3225 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3226}
3227
3228/*** Memory synchronisation ***/
3229/* eieio */
0db1b20e 3230GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3231{
79aceca5
FB		 3232}
3233
3234/* isync */
0db1b20e 3235GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3236{
e1833e1f 3237 GEN_STOP(ctx);
79aceca5
FB		 3238}
3239
111bfab3
FB		 3240#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3241#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 3242static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3243 GEN_MEM_FUNCS(lwarx),
111bfab3 3244};
7863667f
JM		 3245static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3246 GEN_MEM_FUNCS(stwcx),
985a19d6 3247};
9a64fbe4 3248
111bfab3 3249/* lwarx */
76a66253 3250GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3251{
30032c94
JM		 3252 /* NIP cannot be restored if the memory exception comes from an helper */
3253 gen_update_nip(ctx, ctx->nip - 4);
a7859e89 3254 gen_set_access_type(ACCESS_RES);
e2be8d8d 3255 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 3256 op_lwarx();
f78fb44e 3257 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 3258}
3259
3260/* stwcx. */
c7697e1f 3261GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3262{
30032c94
JM		 3263 /* NIP cannot be restored if the memory exception comes from an helper */
3264 gen_update_nip(ctx, ctx->nip - 4);
a7859e89 3265 gen_set_access_type(ACCESS_RES);
e2be8d8d 3266 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3267 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 3268 op_stwcx();
79aceca5
FB		 3269}
3270
426613db
JM		 3271#if defined(TARGET_PPC64)
3272#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3273#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 3274static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3275 GEN_MEM_FUNCS(ldarx),
426613db 3276};
7863667f
JM		 3277static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3278 GEN_MEM_FUNCS(stdcx),
426613db 3279};
426613db
JM		 3280
3281/* ldarx */
a750fc0b 3282GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3283{
30032c94
JM		 3284 /* NIP cannot be restored if the memory exception comes from an helper */
3285 gen_update_nip(ctx, ctx->nip - 4);
a7859e89 3286 gen_set_access_type(ACCESS_RES);
e2be8d8d 3287 gen_addr_reg_index(cpu_T[0], ctx);
426613db 3288 op_ldarx();
f78fb44e 3289 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 3290}
3291
3292/* stdcx. */
c7697e1f 3293GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3294{
30032c94
JM		 3295 /* NIP cannot be restored if the memory exception comes from an helper */
3296 gen_update_nip(ctx, ctx->nip - 4);
a7859e89 3297 gen_set_access_type(ACCESS_RES);
e2be8d8d 3298 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3299 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 3300 op_stdcx();
3301}
3302#endif /* defined(TARGET_PPC64) */
3303
79aceca5 3304/* sync */
a902d886 3305GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3306{
79aceca5
FB		 3307}
3308
0db1b20e
JM		 3309/* wait */
3310GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3311{
931ff272
AJ		 3312 TCGv_i32 t0 = tcg_temp_new_i32();
3313 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3314 tcg_temp_free_i32(t0);
0db1b20e 3315 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08 3316 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3317}
3318
79aceca5 3319/*** Floating-point load ***/
a0d7d5a7
AJ		 3320#define GEN_LDF(name, ldop, opc, type) \
3321GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3322{ \
a0d7d5a7 3323 TCGv EA; \
76a66253 3324 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3325 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3326 return; \
3327 } \
a7859e89 3328 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3329 EA = tcg_temp_new(); \
3330 gen_addr_imm_index(EA, ctx, 0); \
3331 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3332 tcg_temp_free(EA); \
79aceca5
FB		 3333}
3334
a0d7d5a7
AJ		 3335#define GEN_LDUF(name, ldop, opc, type) \
3336GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3337{ \
a0d7d5a7 3338 TCGv EA; \
76a66253 3339 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3340 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3341 return; \
3342 } \
76a66253 3343 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3344 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3345 return; \
9a64fbe4 3346 } \
a7859e89 3347 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3348 EA = tcg_temp_new(); \
3349 gen_addr_imm_index(EA, ctx, 0); \
3350 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3351 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3352 tcg_temp_free(EA); \
79aceca5
FB		 3353}
3354
a0d7d5a7
AJ		 3355#define GEN_LDUXF(name, ldop, opc, type) \
3356GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3357{ \
a0d7d5a7 3358 TCGv EA; \
76a66253 3359 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3360 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3361 return; \
3362 } \
76a66253 3363 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3364 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3365 return; \
9a64fbe4 3366 } \
a7859e89 3367 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3368 EA = tcg_temp_new(); \
3369 gen_addr_reg_index(EA, ctx); \
3370 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3371 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3372 tcg_temp_free(EA); \
79aceca5
FB		 3373}
3374
a0d7d5a7
AJ		 3375#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3376GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3377{ \
a0d7d5a7 3378 TCGv EA; \
76a66253 3379 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3380 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3381 return; \
3382 } \
a7859e89 3383 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3384 EA = tcg_temp_new(); \
3385 gen_addr_reg_index(EA, ctx); \
3386 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3387 tcg_temp_free(EA); \
79aceca5
FB		 3388}
3389
a0d7d5a7
AJ		 3390#define GEN_LDFS(name, ldop, op, type) \
3391GEN_LDF(name, ldop, op | 0x20, type); \
3392GEN_LDUF(name, ldop, op | 0x21, type); \
3393GEN_LDUXF(name, ldop, op | 0x01, type); \
3394GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3395
3396static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3397{
3398 TCGv t0 = tcg_temp_new();
3399 TCGv_i32 t1 = tcg_temp_new_i32();
3400 gen_qemu_ld32u(t0, arg2, flags);
3401 tcg_gen_trunc_tl_i32(t1, t0);
3402 tcg_temp_free(t0);
3403 gen_helper_float32_to_float64(arg1, t1);
3404 tcg_temp_free_i32(t1);
3405}
79aceca5 3406
a0d7d5a7
AJ		 3407 /* lfd lfdu lfdux lfdx */
3408GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3409 /* lfs lfsu lfsux lfsx */
3410GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3411
3412/*** Floating-point store ***/
a0d7d5a7
AJ		 3413#define GEN_STF(name, stop, opc, type) \
3414GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3415{ \
a0d7d5a7 3416 TCGv EA; \
76a66253 3417 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3418 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3419 return; \
3420 } \
a7859e89 3421 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3422 EA = tcg_temp_new(); \
3423 gen_addr_imm_index(EA, ctx, 0); \
3424 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3425 tcg_temp_free(EA); \
79aceca5
FB		 3426}
3427
a0d7d5a7
AJ		 3428#define GEN_STUF(name, stop, opc, type) \
3429GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3430{ \
a0d7d5a7 3431 TCGv EA; \
76a66253 3432 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3433 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3434 return; \
3435 } \
76a66253 3436 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3437 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3438 return; \
9a64fbe4 3439 } \
a7859e89 3440 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3441 EA = tcg_temp_new(); \
3442 gen_addr_imm_index(EA, ctx, 0); \
3443 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3444 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3445 tcg_temp_free(EA); \
79aceca5
FB		 3446}
3447
a0d7d5a7
AJ		 3448#define GEN_STUXF(name, stop, opc, type) \
3449GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3450{ \
a0d7d5a7 3451 TCGv EA; \
76a66253 3452 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3453 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3454 return; \
3455 } \
76a66253 3456 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3457 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3458 return; \
9a64fbe4 3459 } \
a7859e89 3460 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3461 EA = tcg_temp_new(); \
3462 gen_addr_reg_index(EA, ctx); \
3463 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3464 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3465 tcg_temp_free(EA); \
79aceca5
FB		 3466}
3467
a0d7d5a7
AJ		 3468#define GEN_STXF(name, stop, opc2, opc3, type) \
3469GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3470{ \
a0d7d5a7 3471 TCGv EA; \
76a66253 3472 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3473 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3474 return; \
3475 } \
a7859e89 3476 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3477 EA = tcg_temp_new(); \
3478 gen_addr_reg_index(EA, ctx); \
3479 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3480 tcg_temp_free(EA); \
79aceca5
FB		 3481}
3482
a0d7d5a7
AJ		 3483#define GEN_STFS(name, stop, op, type) \
3484GEN_STF(name, stop, op | 0x20, type); \
3485GEN_STUF(name, stop, op | 0x21, type); \
3486GEN_STUXF(name, stop, op | 0x01, type); \
3487GEN_STXF(name, stop, 0x17, op | 0x00, type)
3488
3489static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3490{
3491 TCGv_i32 t0 = tcg_temp_new_i32();
3492 TCGv t1 = tcg_temp_new();
3493 gen_helper_float64_to_float32(t0, arg1);
3494 tcg_gen_extu_i32_tl(t1, t0);
3495 tcg_temp_free_i32(t0);
3496 gen_qemu_st32(t1, arg2, flags);
3497 tcg_temp_free(t1);
3498}
79aceca5
FB		 3499
3500/* stfd stfdu stfdux stfdx */
a0d7d5a7 3501GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3502/* stfs stfsu stfsux stfsx */
a0d7d5a7 3503GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3504
3505/* Optional: */
a0d7d5a7
AJ		 3506static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags)
3507{
3508 TCGv t0 = tcg_temp_new();
3509 tcg_gen_trunc_i64_tl(t0, arg1),
3510 gen_qemu_st32(t0, arg2, flags);
3511 tcg_temp_free(t0);
3512}
79aceca5 3513/* stfiwx */
a0d7d5a7 3514GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3515
3516/*** Branch ***/
b068d6a7
JM		 3517static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3518 target_ulong dest)
c1942362
FB		 3519{
3520 TranslationBlock *tb;
3521 tb = ctx->tb;
a2ffb812
AJ		 3522#if defined(TARGET_PPC64)
3523 if (!ctx->sf_mode)
3524 dest = (uint32_t) dest;
3525#endif
57fec1fe 3526 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3527 likely(!ctx->singlestep_enabled)) {
57fec1fe 3528 tcg_gen_goto_tb(n);
a2ffb812 3529 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3530 tcg_gen_exit_tb((long)tb + n);
c1942362 3531 } else {
a2ffb812 3532 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3533 if (unlikely(ctx->singlestep_enabled)) {
3534 if ((ctx->singlestep_enabled &
bdc4e053 3535 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3536 ctx->exception == POWERPC_EXCP_BRANCH) {
3537 target_ulong tmp = ctx->nip;
3538 ctx->nip = dest;
3539 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3540 ctx->nip = tmp;
3541 }
3542 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3543 gen_update_nip(ctx, dest);
64adab3f 3544 gen_helper_raise_debug();
8cbcb4fa
AJ		 3545 }
3546 }
57fec1fe 3547 tcg_gen_exit_tb(0);
c1942362 3548 }
c53be334
FB		 3549}
3550
b068d6a7 3551static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3552{
3553#if defined(TARGET_PPC64)
a2ffb812
AJ		 3554 if (ctx->sf_mode == 0)
3555 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3556 else
3557#endif
a2ffb812 3558 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3559}
3560
79aceca5
FB		 3561/* b ba bl bla */
3562GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3563{
76a66253 3564 target_ulong li, target;
38a64f9d 3565
8cbcb4fa 3566 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3567 /* sign extend LI */
76a66253 3568#if defined(TARGET_PPC64)
d9bce9d9
JM		 3569 if (ctx->sf_mode)
3570 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3571 else
76a66253 3572#endif
d9bce9d9 3573 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3574 if (likely(AA(ctx->opcode) == 0))
046d6672 3575 target = ctx->nip + li - 4;
79aceca5 3576 else
9a64fbe4 3577 target = li;
e1833e1f
JM		 3578 if (LK(ctx->opcode))
3579 gen_setlr(ctx, ctx->nip);
c1942362 3580 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3581}
3582
e98a6e40
FB		 3583#define BCOND_IM 0
3584#define BCOND_LR 1
3585#define BCOND_CTR 2
3586
b068d6a7 3587static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3588{
d9bce9d9 3589 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3590 int l1 = gen_new_label();
3591 TCGv target;
e98a6e40 3592
8cbcb4fa 3593 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3594 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3595 target = tcg_temp_local_new();
a2ffb812
AJ		 3596 if (type == BCOND_CTR)
3597 tcg_gen_mov_tl(target, cpu_ctr);
3598 else
3599 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3600 }
e1833e1f
JM		 3601 if (LK(ctx->opcode))
3602 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3603 l1 = gen_new_label();
3604 if ((bo & 0x4) == 0) {
3605 /* Decrement and test CTR */
a7812ae4 3606 TCGv temp = tcg_temp_new();
a2ffb812
AJ		 3607 if (unlikely(type == BCOND_CTR)) {
3608 GEN_EXCP_INVAL(ctx);
3609 return;
3610 }
3611 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3612#if defined(TARGET_PPC64)
a2ffb812
AJ		 3613 if (!ctx->sf_mode)
3614 tcg_gen_ext32u_tl(temp, cpu_ctr);
3615 else
d9bce9d9 3616#endif
a2ffb812
AJ		 3617 tcg_gen_mov_tl(temp, cpu_ctr);
3618 if (bo & 0x2) {
3619 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3620 } else {
3621 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3622 }
a7812ae4 3623 tcg_temp_free(temp);
a2ffb812
AJ		 3624 }
3625 if ((bo & 0x10) == 0) {
3626 /* Test CR */
3627 uint32_t bi = BI(ctx->opcode);
3628 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3629 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3630
d9bce9d9 3631 if (bo & 0x8) {
a2ffb812
AJ		 3632 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3633 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3634 } else {
a2ffb812
AJ		 3635 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3636 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3637 }
a7812ae4 3638 tcg_temp_free_i32(temp);
d9bce9d9 3639 }
e98a6e40 3640 if (type == BCOND_IM) {
a2ffb812
AJ		 3641 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3642 if (likely(AA(ctx->opcode) == 0)) {
3643 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3644 } else {
3645 gen_goto_tb(ctx, 0, li);
3646 }
c53be334 3647 gen_set_label(l1);
c1942362 3648 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3649 } else {
d9bce9d9 3650#if defined(TARGET_PPC64)
a2ffb812
AJ		 3651 if (!(ctx->sf_mode))
3652 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3653 else
3654#endif
3655 tcg_gen_andi_tl(cpu_nip, target, ~3);
3656 tcg_gen_exit_tb(0);
3657 gen_set_label(l1);
3658#if defined(TARGET_PPC64)
3659 if (!(ctx->sf_mode))
3660 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3661 else
3662#endif
a2ffb812 3663 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3664 tcg_gen_exit_tb(0);
08e46e54 3665 }
e98a6e40
FB		 3666}
3667
3668GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3669{
e98a6e40
FB		 3670 gen_bcond(ctx, BCOND_IM);
3671}
3672
3673GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3674{
e98a6e40
FB		 3675 gen_bcond(ctx, BCOND_CTR);
3676}
3677
3678GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3679{
e98a6e40
FB		 3680 gen_bcond(ctx, BCOND_LR);
3681}
79aceca5
FB		 3682
3683/*** Condition register logical ***/
e1571908
AJ		 3684#define GEN_CRLOGIC(name, tcg_op, opc) \
3685GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3686{ \
fc0d441e
JM		 3687 uint8_t bitmask; \
3688 int sh; \
a7812ae4 3689 TCGv_i32 t0, t1; \
fc0d441e 3690 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3691 t0 = tcg_temp_new_i32(); \
fc0d441e 3692 if (sh > 0) \
fea0c503 3693 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3694 else if (sh < 0) \
fea0c503 3695 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3696 else \
fea0c503 3697 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3698 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3699 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3700 if (sh > 0) \
fea0c503 3701 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3702 else if (sh < 0) \
fea0c503 3703 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3704 else \
fea0c503
AJ		 3705 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3706 tcg_op(t0, t0, t1); \
fc0d441e 3707 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3708 tcg_gen_andi_i32(t0, t0, bitmask); \
3709 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3710 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3711 tcg_temp_free_i32(t0); \
3712 tcg_temp_free_i32(t1); \
79aceca5
FB		 3713}
3714
3715/* crand */
e1571908 3716GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3717/* crandc */
e1571908 3718GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3719/* creqv */
e1571908 3720GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3721/* crnand */
e1571908 3722GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3723/* crnor */
e1571908 3724GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3725/* cror */
e1571908 3726GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3727/* crorc */
e1571908 3728GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3729/* crxor */
e1571908 3730GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3731/* mcrf */
3732GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3733{
47e4661c 3734 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3735}
3736
3737/*** System linkage ***/
3738/* rfi (supervisor only) */
76a66253 3739GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3740{
9a64fbe4 3741#if defined(CONFIG_USER_ONLY)
e1833e1f 3742 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3743#else
3744 /* Restore CPU state */
76a66253 3745 if (unlikely(!ctx->supervisor)) {
e1833e1f 3746 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3747 return;
9a64fbe4 3748 }
a42bd6cc 3749 gen_op_rfi();
e1833e1f 3750 GEN_SYNC(ctx);
9a64fbe4 3751#endif
79aceca5
FB		 3752}
3753
426613db 3754#if defined(TARGET_PPC64)
a750fc0b 3755GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3756{
3757#if defined(CONFIG_USER_ONLY)
e1833e1f 3758 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3759#else
3760 /* Restore CPU state */
3761 if (unlikely(!ctx->supervisor)) {
e1833e1f 3762 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3763 return;
3764 }
a42bd6cc 3765 gen_op_rfid();
e1833e1f 3766 GEN_SYNC(ctx);
426613db
JM		 3767#endif
3768}
426613db 3769
5b8105fa 3770GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3771{
3772#if defined(CONFIG_USER_ONLY)
3773 GEN_EXCP_PRIVOPC(ctx);
3774#else
3775 /* Restore CPU state */
3776 if (unlikely(ctx->supervisor <= 1)) {
3777 GEN_EXCP_PRIVOPC(ctx);
3778 return;
3779 }
3780 gen_op_hrfid();
3781 GEN_SYNC(ctx);
3782#endif
3783}
3784#endif
3785
79aceca5 3786/* sc */
417bf010
JM		 3787#if defined(CONFIG_USER_ONLY)
3788#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3789#else
3790#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3791#endif
e1833e1f 3792GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3793{
e1833e1f
JM		 3794 uint32_t lev;
3795
3796 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3797 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3798}
3799
3800/*** Trap ***/
3801/* tw */
76a66253 3802GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3803{
cab3bee2 3804 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3805 /* Update the nip since this might generate a trap exception */
d9bce9d9 3806 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3807 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3808 tcg_temp_free_i32(t0);
79aceca5
FB		 3809}
3810
3811/* twi */
3812GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3813{
cab3bee2
AJ		 3814 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3815 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3816 /* Update the nip since this might generate a trap exception */
3817 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3818 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3819 tcg_temp_free(t0);
3820 tcg_temp_free_i32(t1);
79aceca5
FB		 3821}
3822
d9bce9d9
JM		 3823#if defined(TARGET_PPC64)
3824/* td */
3825GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3826{
cab3bee2 3827 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3828 /* Update the nip since this might generate a trap exception */
3829 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3830 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3831 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3832}
3833
3834/* tdi */
3835GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3836{
cab3bee2
AJ		 3837 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3838 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3839 /* Update the nip since this might generate a trap exception */
3840 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3841 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3842 tcg_temp_free(t0);
3843 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3844}
3845#endif
3846
79aceca5 3847/*** Processor control ***/
79aceca5
FB		 3848/* mcrxr */
3849GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3850{
3d7b417e
AJ		 3851 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3852 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3853 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3854}
3855
3856/* mfcr */
76a66253 3857GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3858{
76a66253 3859 uint32_t crm, crn;
3b46e624 3860
76a66253
JM		 3861 if (likely(ctx->opcode & 0x00100000)) {
3862 crm = CRM(ctx->opcode);
3863 if (likely((crm ^ (crm - 1)) == 0)) {
3864 crn = ffs(crm);
e1571908 3865 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3866 }
d9bce9d9 3867 } else {
a7812ae4 3868 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3869 }
79aceca5
FB		 3870}
3871
3872/* mfmsr */
3873GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3874{
9a64fbe4 3875#if defined(CONFIG_USER_ONLY)
e1833e1f 3876 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3877#else
76a66253 3878 if (unlikely(!ctx->supervisor)) {
e1833e1f 3879 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3880 return;
9a64fbe4 3881 }
6676f424 3882 gen_op_load_msr();
f78fb44e 3883 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3884#endif
79aceca5
FB		 3885}
3886
a11b8151 3887#if 1
6f2d8978 3888#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3889#else
3890static void spr_noaccess (void *opaque, int sprn)
3891{
3892 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3893 printf("ERROR: try to access SPR %d !\n", sprn);
3894}
3895#define SPR_NOACCESS (&spr_noaccess)
3896#endif
3897
79aceca5 3898/* mfspr */
b068d6a7 3899static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3900{
3fc6c082 3901 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3902 uint32_t sprn = SPR(ctx->opcode);
3903
3fc6c082 3904#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3905 if (ctx->supervisor == 2)
3906 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3907 else if (ctx->supervisor)
3fc6c082
FB		 3908 read_cb = ctx->spr_cb[sprn].oea_read;
3909 else
9a64fbe4 3910#endif
3fc6c082 3911 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3912 if (likely(read_cb != NULL)) {
3913 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3914 (*read_cb)(ctx, sprn);
f78fb44e 3915 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3916 } else {
3917 /* Privilege exception */
9fceefa7
JM		 3918 /* This is a hack to avoid warnings when running Linux:
3919 * this OS breaks the PowerPC virtualisation model,
3920 * allowing userland application to read the PVR
3921 */
3922 if (sprn != SPR_PVR) {
3923 if (loglevel != 0) {
6b542af7 3924 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3925 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3926 }
077fc206
JM		 3927 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3928 sprn, sprn, ctx->nip);
f24e5695 3929 }
e1833e1f 3930 GEN_EXCP_PRIVREG(ctx);
79aceca5 3931 }
3fc6c082
FB		 3932 } else {
3933 /* Not defined */
4a057712 3934 if (loglevel != 0) {
077fc206
JM		 3935 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3936 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3937 }
077fc206
JM		 3938 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3939 sprn, sprn, ctx->nip);
e1833e1f
JM		 3940 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3941 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3942 }
79aceca5
FB		 3943}
3944
3fc6c082 3945GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3946{
3fc6c082 3947 gen_op_mfspr(ctx);
76a66253 3948}
3fc6c082
FB		 3949
3950/* mftb */
a750fc0b 3951GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3952{
3953 gen_op_mfspr(ctx);
79aceca5
FB		 3954}
3955
3956/* mtcrf */
8dd4983c 3957GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3958{
76a66253 3959 uint32_t crm, crn;
3b46e624 3960
76a66253
JM		 3961 crm = CRM(ctx->opcode);
3962 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3963 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3964 crn = ffs(crm);
a7812ae4
PB		 3965 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3966 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3967 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3968 tcg_temp_free_i32(temp);
76a66253 3969 } else {
a7812ae4
PB		 3970 TCGv_i32 temp = tcg_const_i32(crm);
3971 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3972 tcg_temp_free_i32(temp);
76a66253 3973 }
79aceca5
FB		 3974}
3975
3976/* mtmsr */
426613db 3977#if defined(TARGET_PPC64)
be147d08 3978GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3979{
3980#if defined(CONFIG_USER_ONLY)
e1833e1f 3981 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3982#else
3983 if (unlikely(!ctx->supervisor)) {
e1833e1f 3984 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3985 return;
3986 }
f78fb44e 3987 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3988 if (ctx->opcode & 0x00010000) {
3989 /* Special form that does not need any synchronisation */
3990 gen_op_update_riee();
3991 } else {
056b05f8
JM		 3992 /* XXX: we need to update nip before the store
3993 * if we enter power saving mode, we will exit the loop
3994 * directly from ppc_store_msr
3995 */
be147d08 3996 gen_update_nip(ctx, ctx->nip);
6676f424 3997 gen_op_store_msr();
be147d08
JM		 3998 /* Must stop the translation as machine state (may have) changed */
3999 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 4000 ctx->exception = POWERPC_EXCP_STOP;
be147d08 4001 }
426613db
JM		 4002#endif
4003}
4004#endif
4005
79aceca5
FB		 4006GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
4007{
9a64fbe4 4008#if defined(CONFIG_USER_ONLY)
e1833e1f 4009 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4010#else
76a66253 4011 if (unlikely(!ctx->supervisor)) {
e1833e1f 4012 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4013 return;
9a64fbe4 4014 }
f78fb44e 4015 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4016 if (ctx->opcode & 0x00010000) {
4017 /* Special form that does not need any synchronisation */
4018 gen_op_update_riee();
4019 } else {
056b05f8
JM		 4020 /* XXX: we need to update nip before the store
4021 * if we enter power saving mode, we will exit the loop
4022 * directly from ppc_store_msr
4023 */
be147d08 4024 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4025#if defined(TARGET_PPC64)
be147d08 4026 if (!ctx->sf_mode)
6676f424 4027 gen_op_store_msr_32();
be147d08 4028 else
d9bce9d9 4029#endif
6676f424 4030 gen_op_store_msr();
be147d08
JM		 4031 /* Must stop the translation as machine state (may have) changed */
4032 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 4033 ctx->exception = POWERPC_EXCP_STOP;
be147d08 4034 }
9a64fbe4 4035#endif
79aceca5
FB		 4036}
4037
4038/* mtspr */
4039GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4040{
3fc6c082 4041 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 4042 uint32_t sprn = SPR(ctx->opcode);
4043
3fc6c082 4044#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 4045 if (ctx->supervisor == 2)
4046 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 4047 else if (ctx->supervisor)
3fc6c082
FB		 4048 write_cb = ctx->spr_cb[sprn].oea_write;
4049 else
9a64fbe4 4050#endif
3fc6c082 4051 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4052 if (likely(write_cb != NULL)) {
4053 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 4054 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 4055 (*write_cb)(ctx, sprn);
4056 } else {
4057 /* Privilege exception */
4a057712 4058 if (loglevel != 0) {
077fc206
JM		 4059 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4060 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4061 }
077fc206
JM		 4062 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4063 sprn, sprn, ctx->nip);
e1833e1f 4064 GEN_EXCP_PRIVREG(ctx);
76a66253 4065 }
3fc6c082
FB		 4066 } else {
4067 /* Not defined */
4a057712 4068 if (loglevel != 0) {
077fc206
JM		 4069 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4070 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4071 }
077fc206
JM		 4072 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4073 sprn, sprn, ctx->nip);
e1833e1f
JM		 4074 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4075 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 4076 }
79aceca5
FB		 4077}
4078
4079/*** Cache management ***/
79aceca5 4080/* dcbf */
0db1b20e 4081GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4082{
dac454af 4083 /* XXX: specification says this is treated as a load by the MMU */
a7812ae4 4084 TCGv t0 = tcg_temp_new();
a7859e89 4085 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4086 gen_addr_reg_index(t0, ctx);
4087 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4088 tcg_temp_free(t0);
79aceca5
FB		 4089}
4090
4091/* dcbi (Supervisor only) */
9a64fbe4 4092GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4093{
a541f297 4094#if defined(CONFIG_USER_ONLY)
e1833e1f 4095 GEN_EXCP_PRIVOPC(ctx);
a541f297 4096#else
b61f2753 4097 TCGv EA, val;
76a66253 4098 if (unlikely(!ctx->supervisor)) {
e1833e1f 4099 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4100 return;
9a64fbe4 4101 }
a7812ae4 4102 EA = tcg_temp_new();
a7859e89 4103 gen_set_access_type(ACCESS_CACHE);
b61f2753 4104 gen_addr_reg_index(EA, ctx);
a7812ae4 4105 val = tcg_temp_new();
76a66253 4106 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 4107 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4108 gen_qemu_st8(val, EA, ctx->mem_idx);
4109 tcg_temp_free(val);
4110 tcg_temp_free(EA);
a541f297 4111#endif
79aceca5
FB		 4112}
4113
4114/* dcdst */
9a64fbe4 4115GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4116{
76a66253 4117 /* XXX: specification say this is treated as a load by the MMU */
a7812ae4 4118 TCGv t0 = tcg_temp_new();
a7859e89 4119 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4120 gen_addr_reg_index(t0, ctx);
4121 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4122 tcg_temp_free(t0);
79aceca5
FB		 4123}
4124
4125/* dcbt */
0db1b20e 4126GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4127{
0db1b20e 4128 /* interpreted as no-op */
76a66253
JM		 4129 /* XXX: specification say this is treated as a load by the MMU
4130 * but does not generate any exception
4131 */
79aceca5
FB		 4132}
4133
4134/* dcbtst */
0db1b20e 4135GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4136{
0db1b20e 4137 /* interpreted as no-op */
76a66253
JM		 4138 /* XXX: specification say this is treated as a load by the MMU
4139 * but does not generate any exception
4140 */
79aceca5
FB		 4141}
4142
4143/* dcbz */
d63001d1 4144GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4145{
799a8c8d
AJ		 4146 TCGv t0 = tcg_temp_new();
4147 gen_addr_reg_index(t0, ctx);
4148 /* NIP cannot be restored if the memory exception comes from an helper */
4149 gen_update_nip(ctx, ctx->nip - 4);
4150 gen_helper_dcbz(t0);
4151 tcg_temp_free(t0);
d63001d1
JM		 4152}
4153
c7697e1f 4154GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4155{
799a8c8d
AJ		 4156 TCGv t0 = tcg_temp_new();
4157 gen_addr_reg_index(t0, ctx);
4158 /* NIP cannot be restored if the memory exception comes from an helper */
4159 gen_update_nip(ctx, ctx->nip - 4);
d63001d1 4160 if (ctx->opcode & 0x00200000)
799a8c8d 4161 gen_helper_dcbz(t0);
d63001d1 4162 else
799a8c8d
AJ		 4163 gen_helper_dcbz_970(t0);
4164 tcg_temp_free(t0);
79aceca5
FB		 4165}
4166
4167/* icbi */
36f69651 4168#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 4169#define gen_op_icbi_le_raw gen_op_icbi_raw
4170#define gen_op_icbi_le_user gen_op_icbi_user
4171#define gen_op_icbi_le_kernel gen_op_icbi_kernel
4172#define gen_op_icbi_le_hypv gen_op_icbi_hypv
4173#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4174#define gen_op_icbi_le_64_user gen_op_icbi_64_user
4175#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4176#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4177static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4178 GEN_MEM_FUNCS(icbi),
36f69651 4179};
e1833e1f 4180
1b413d55 4181GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4182{
30032c94
JM		 4183 /* NIP cannot be restored if the memory exception comes from an helper */
4184 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4185 gen_addr_reg_index(cpu_T[0], ctx);
36f69651 4186 op_icbi();
79aceca5
FB		 4187}
4188
4189/* Optional: */
4190/* dcba */
a750fc0b 4191GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4192{
0db1b20e
JM		 4193 /* interpreted as no-op */
4194 /* XXX: specification say this is treated as a store by the MMU
4195 * but does not generate any exception
4196 */
79aceca5
FB		 4197}
4198
4199/*** Segment register manipulation ***/
4200/* Supervisor only: */
4201/* mfsr */
4202GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4203{
9a64fbe4 4204#if defined(CONFIG_USER_ONLY)
e1833e1f 4205 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4206#else
76a66253 4207 if (unlikely(!ctx->supervisor)) {
e1833e1f 4208 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4209 return;
9a64fbe4 4210 }
86c581dc 4211 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4212 gen_op_load_sr();
f78fb44e 4213 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4214#endif
79aceca5
FB		 4215}
4216
4217/* mfsrin */
9a64fbe4 4218GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4219{
9a64fbe4 4220#if defined(CONFIG_USER_ONLY)
e1833e1f 4221 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4222#else
76a66253 4223 if (unlikely(!ctx->supervisor)) {
e1833e1f 4224 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4225 return;
9a64fbe4 4226 }
f78fb44e 4227 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4228 gen_op_srli_T1(28);
4229 gen_op_load_sr();
f78fb44e 4230 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4231#endif
79aceca5
FB		 4232}
4233
4234/* mtsr */
e63c59cb 4235GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4236{
9a64fbe4 4237#if defined(CONFIG_USER_ONLY)
e1833e1f 4238 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4239#else
76a66253 4240 if (unlikely(!ctx->supervisor)) {
e1833e1f 4241 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4242 return;
9a64fbe4 4243 }
f78fb44e 4244 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4245 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4246 gen_op_store_sr();
9a64fbe4 4247#endif
79aceca5
FB		 4248}
4249
4250/* mtsrin */
9a64fbe4 4251GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4252{
9a64fbe4 4253#if defined(CONFIG_USER_ONLY)
e1833e1f 4254 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4255#else
76a66253 4256 if (unlikely(!ctx->supervisor)) {
e1833e1f 4257 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4258 return;
9a64fbe4 4259 }
f78fb44e
AJ		 4260 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4261 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4262 gen_op_srli_T1(28);
4263 gen_op_store_sr();
9a64fbe4 4264#endif
79aceca5
FB		 4265}
4266
12de9a39
JM		 4267#if defined(TARGET_PPC64)
4268/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4269/* mfsr */
c7697e1f 4270GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4271{
4272#if defined(CONFIG_USER_ONLY)
4273 GEN_EXCP_PRIVREG(ctx);
4274#else
4275 if (unlikely(!ctx->supervisor)) {
4276 GEN_EXCP_PRIVREG(ctx);
4277 return;
4278 }
86c581dc 4279 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4280 gen_op_load_slb();
f78fb44e 4281 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4282#endif
4283}
4284
4285/* mfsrin */
c7697e1f
JM		 4286GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4287 PPC_SEGMENT_64B)
12de9a39
JM		 4288{
4289#if defined(CONFIG_USER_ONLY)
4290 GEN_EXCP_PRIVREG(ctx);
4291#else
4292 if (unlikely(!ctx->supervisor)) {
4293 GEN_EXCP_PRIVREG(ctx);
4294 return;
4295 }
f78fb44e 4296 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4297 gen_op_srli_T1(28);
4298 gen_op_load_slb();
f78fb44e 4299 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4300#endif
4301}
4302
4303/* mtsr */
c7697e1f 4304GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4305{
4306#if defined(CONFIG_USER_ONLY)
4307 GEN_EXCP_PRIVREG(ctx);
4308#else
4309 if (unlikely(!ctx->supervisor)) {
4310 GEN_EXCP_PRIVREG(ctx);
4311 return;
4312 }
f78fb44e 4313 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4314 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4315 gen_op_store_slb();
4316#endif
4317}
4318
4319/* mtsrin */
c7697e1f
JM		 4320GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4321 PPC_SEGMENT_64B)
12de9a39
JM		 4322{
4323#if defined(CONFIG_USER_ONLY)
4324 GEN_EXCP_PRIVREG(ctx);
4325#else
4326 if (unlikely(!ctx->supervisor)) {
4327 GEN_EXCP_PRIVREG(ctx);
4328 return;
4329 }
f78fb44e
AJ		 4330 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4331 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4332 gen_op_srli_T1(28);
4333 gen_op_store_slb();
4334#endif
4335}
4336#endif /* defined(TARGET_PPC64) */
4337
79aceca5
FB		 4338/*** Lookaside buffer management ***/
4339/* Optional & supervisor only: */
4340/* tlbia */
3fc6c082 4341GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4342{
9a64fbe4 4343#if defined(CONFIG_USER_ONLY)
e1833e1f 4344 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4345#else
76a66253 4346 if (unlikely(!ctx->supervisor)) {
e1833e1f 4347 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4348 return;
9a64fbe4
FB		 4349 }
4350 gen_op_tlbia();
4351#endif
79aceca5
FB		 4352}
4353
4354/* tlbie */
76a66253 4355GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4356{
9a64fbe4 4357#if defined(CONFIG_USER_ONLY)
e1833e1f 4358 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4359#else
76a66253 4360 if (unlikely(!ctx->supervisor)) {
e1833e1f 4361 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4362 return;
9a64fbe4 4363 }
f78fb44e 4364 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4365#if defined(TARGET_PPC64)
4366 if (ctx->sf_mode)
4367 gen_op_tlbie_64();
4368 else
4369#endif
4370 gen_op_tlbie();
9a64fbe4 4371#endif
79aceca5
FB		 4372}
4373
4374/* tlbsync */
76a66253 4375GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4376{
9a64fbe4 4377#if defined(CONFIG_USER_ONLY)
e1833e1f 4378 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4379#else
76a66253 4380 if (unlikely(!ctx->supervisor)) {
e1833e1f 4381 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4382 return;
9a64fbe4
FB		 4383 }
4384 /* This has no effect: it should ensure that all previous
4385 * tlbie have completed
4386 */
e1833e1f 4387 GEN_STOP(ctx);
9a64fbe4 4388#endif
79aceca5
FB		 4389}
4390
426613db
JM		 4391#if defined(TARGET_PPC64)
4392/* slbia */
4393GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4394{
4395#if defined(CONFIG_USER_ONLY)
e1833e1f 4396 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4397#else
4398 if (unlikely(!ctx->supervisor)) {
e1833e1f 4399 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4400 return;
4401 }
4402 gen_op_slbia();
426613db
JM		 4403#endif
4404}
4405
4406/* slbie */
4407GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4408{
4409#if defined(CONFIG_USER_ONLY)
e1833e1f 4410 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4411#else
4412 if (unlikely(!ctx->supervisor)) {
e1833e1f 4413 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4414 return;
4415 }
f78fb44e 4416 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4417 gen_op_slbie();
426613db
JM		 4418#endif
4419}
4420#endif
4421
79aceca5
FB		 4422/*** External control ***/
4423/* Optional: */
9a64fbe4
FB		 4424#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4425#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4426static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4427 GEN_MEM_FUNCS(eciwx),
111bfab3 4428};
7863667f
JM		 4429static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4430 GEN_MEM_FUNCS(ecowx),
111bfab3 4431};
9a64fbe4 4432
111bfab3 4433/* eciwx */
79aceca5
FB		 4434GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4435{
9a64fbe4 4436 /* Should check EAR[E] & alignment ! */
a7859e89 4437 gen_set_access_type(ACCESS_RES);
e2be8d8d 4438 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4439 op_eciwx();
f78fb44e 4440 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4441}
4442
4443/* ecowx */
4444GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4445{
4446 /* Should check EAR[E] & alignment ! */
e2be8d8d 4447 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4448 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4449 op_ecowx();
4450}
4451
4452/* PowerPC 601 specific instructions */
4453/* abs - abs. */
4454GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4455{
f78fb44e 4456 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4457 gen_op_POWER_abs();
f78fb44e 4458 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4459 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4460 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4461}
4462
4463/* abso - abso. */
4464GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4465{
f78fb44e 4466 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4467 gen_op_POWER_abso();
f78fb44e 4468 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4469 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4470 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4471}
4472
4473/* clcs */
a750fc0b 4474GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4475{
f78fb44e 4476 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4477 gen_op_POWER_clcs();
c7697e1f 4478 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4479 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4480}
4481
4482/* div - div. */
4483GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4484{
f78fb44e
AJ		 4485 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4486 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4487 gen_op_POWER_div();
f78fb44e 4488 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4489 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4490 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4491}
4492
4493/* divo - divo. */
4494GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4495{
f78fb44e
AJ		 4496 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4497 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4498 gen_op_POWER_divo();
f78fb44e 4499 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4500 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4501 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4502}
4503
4504/* divs - divs. */
4505GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4506{
f78fb44e
AJ		 4507 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4508 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4509 gen_op_POWER_divs();
f78fb44e 4510 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4511 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4512 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4513}
4514
4515/* divso - divso. */
4516GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4517{
f78fb44e
AJ		 4518 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4519 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4520 gen_op_POWER_divso();
f78fb44e 4521 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4522 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4523 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4524}
4525
4526/* doz - doz. */
4527GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4528{
f78fb44e
AJ		 4529 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4530 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4531 gen_op_POWER_doz();
f78fb44e 4532 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4533 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4534 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4535}
4536
4537/* dozo - dozo. */
4538GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4539{
f78fb44e
AJ		 4540 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4541 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4542 gen_op_POWER_dozo();
f78fb44e 4543 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4544 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4545 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4546}
4547
4548/* dozi */
4549GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4550{
f78fb44e 4551 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4552 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4553 gen_op_POWER_doz();
f78fb44e 4554 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4555}
4556
7863667f
JM		 4557/* As lscbx load from memory byte after byte, it's always endian safe.
4558 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4559 */
2857068e 4560#define op_POWER_lscbx(start, ra, rb) \
76a66253 4561(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 4562#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4563#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4564#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4565#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4566#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4567#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4568#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4569#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4570#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4571#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4572#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4573#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4574static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4575 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4576};
76a66253
JM		 4577
4578/* lscbx - lscbx. */
4579GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4580{
4581 int ra = rA(ctx->opcode);
4582 int rb = rB(ctx->opcode);
4583
e2be8d8d 4584 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4585 if (ra == 0) {
4586 ra = rb;
4587 }
4588 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4589 gen_update_nip(ctx, ctx->nip - 4);
3d7b417e
AJ		 4590 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4591 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4592 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
76a66253 4593 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3d7b417e
AJ		 4594 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4595 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253 4596 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4597 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4598}
4599
4600/* maskg - maskg. */
4601GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4602{
f78fb44e
AJ		 4603 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4604 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4605 gen_op_POWER_maskg();
f78fb44e 4606 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4607 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4608 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4609}
4610
4611/* maskir - maskir. */
4612GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4613{
f78fb44e
AJ		 4614 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4615 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4616 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4617 gen_op_POWER_maskir();
f78fb44e 4618 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4619 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4620 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4621}
4622
4623/* mul - mul. */
4624GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4625{
f78fb44e
AJ		 4626 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4627 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4628 gen_op_POWER_mul();
f78fb44e 4629 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4630 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4631 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4632}
4633
4634/* mulo - mulo. */
4635GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4636{
f78fb44e
AJ		 4637 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4638 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4639 gen_op_POWER_mulo();
f78fb44e 4640 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4641 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4642 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4643}
4644
4645/* nabs - nabs. */
4646GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4647{
f78fb44e 4648 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4649 gen_op_POWER_nabs();
f78fb44e 4650 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4651 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4652 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4653}
4654
4655/* nabso - nabso. */
4656GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4657{
f78fb44e 4658 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4659 gen_op_POWER_nabso();
f78fb44e 4660 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4661 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4662 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4663}
4664
4665/* rlmi - rlmi. */
4666GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4667{
4668 uint32_t mb, me;
4669
4670 mb = MB(ctx->opcode);
4671 me = ME(ctx->opcode);
f78fb44e
AJ		 4672 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4673 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4674 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4675 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4676 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4677 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4678 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4679}
4680
4681/* rrib - rrib. */
4682GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4683{
f78fb44e
AJ		 4684 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4685 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4686 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4687 gen_op_POWER_rrib();
f78fb44e 4688 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4689 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4690 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4691}
4692
4693/* sle - sle. */
4694GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4695{
f78fb44e
AJ		 4696 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4697 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4698 gen_op_POWER_sle();
f78fb44e 4699 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4700 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4701 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4702}
4703
4704/* sleq - sleq. */
4705GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4706{
f78fb44e
AJ		 4707 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4708 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4709 gen_op_POWER_sleq();
f78fb44e 4710 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4711 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4712 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4713}
4714
4715/* sliq - sliq. */
4716GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4717{
f78fb44e 4718 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4719 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4720 gen_op_POWER_sle();
f78fb44e 4721 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4722 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4723 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4724}
4725
4726/* slliq - slliq. */
4727GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4728{
f78fb44e 4729 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4730 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4731 gen_op_POWER_sleq();
f78fb44e 4732 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4733 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4734 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4735}
4736
4737/* sllq - sllq. */
4738GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4739{
f78fb44e
AJ		 4740 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4741 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4742 gen_op_POWER_sllq();
f78fb44e 4743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4744 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4745 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4746}
4747
4748/* slq - slq. */
4749GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4750{
f78fb44e
AJ		 4751 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4752 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4753 gen_op_POWER_slq();
f78fb44e 4754 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4755 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4756 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4757}
4758
d9bce9d9 4759/* sraiq - sraiq. */
76a66253
JM		 4760GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4761{
f78fb44e 4762 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4763 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4764 gen_op_POWER_sraq();
f78fb44e 4765 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4766 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4767 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4768}
4769
4770/* sraq - sraq. */
4771GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4772{
f78fb44e
AJ		 4773 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4774 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4775 gen_op_POWER_sraq();
f78fb44e 4776 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4777 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4778 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4779}
4780
4781/* sre - sre. */
4782GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4783{
f78fb44e
AJ		 4784 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4785 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4786 gen_op_POWER_sre();
f78fb44e 4787 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4788 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4789 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4790}
4791
4792/* srea - srea. */
4793GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4794{
f78fb44e
AJ		 4795 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4796 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4797 gen_op_POWER_srea();
f78fb44e 4798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4799 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4800 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4801}
4802
4803/* sreq */
4804GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4805{
f78fb44e
AJ		 4806 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4807 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4808 gen_op_POWER_sreq();
f78fb44e 4809 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4810 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4811 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4812}
4813
4814/* sriq */
4815GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4816{
f78fb44e 4817 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4818 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4819 gen_op_POWER_srq();
f78fb44e 4820 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4821 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4822 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4823}
4824
4825/* srliq */
4826GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4827{
f78fb44e
AJ		 4828 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4829 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4830 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4831 gen_op_POWER_srlq();
f78fb44e 4832 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4833 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4834 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4835}
4836
4837/* srlq */
4838GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4839{
f78fb44e
AJ		 4840 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4841 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4842 gen_op_POWER_srlq();
f78fb44e 4843 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4844 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4845 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4846}
4847
4848/* srq */
4849GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4850{
f78fb44e
AJ		 4851 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4852 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4853 gen_op_POWER_srq();
f78fb44e 4854 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4855 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4856 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4857}
4858
4859/* PowerPC 602 specific instructions */
4860/* dsa */
4861GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4862{
4863 /* XXX: TODO */
e1833e1f 4864 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4865}
4866
4867/* esa */
4868GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4869{
4870 /* XXX: TODO */
e1833e1f 4871 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4872}
4873
4874/* mfrom */
4875GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4876{
4877#if defined(CONFIG_USER_ONLY)
e1833e1f 4878 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4879#else
4880 if (unlikely(!ctx->supervisor)) {
e1833e1f 4881 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4882 return;
4883 }
cf02a65c 4884 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4885#endif
4886}
4887
4888/* 602 - 603 - G2 TLB management */
4889/* tlbld */
c7697e1f 4890GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4891{
4892#if defined(CONFIG_USER_ONLY)
e1833e1f 4893 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4894#else
4895 if (unlikely(!ctx->supervisor)) {
e1833e1f 4896 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4897 return;
4898 }
0f3955e2 4899 gen_helper_load_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4900#endif
4901}
4902
4903/* tlbli */
c7697e1f 4904GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4905{
4906#if defined(CONFIG_USER_ONLY)
e1833e1f 4907 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4908#else
4909 if (unlikely(!ctx->supervisor)) {
e1833e1f 4910 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4911 return;
4912 }
0f3955e2 4913 gen_helper_load_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4914#endif
4915}
4916
7dbe11ac
JM		 4917/* 74xx TLB management */
4918/* tlbld */
c7697e1f 4919GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4920{
4921#if defined(CONFIG_USER_ONLY)
4922 GEN_EXCP_PRIVOPC(ctx);
4923#else
4924 if (unlikely(!ctx->supervisor)) {
4925 GEN_EXCP_PRIVOPC(ctx);
4926 return;
4927 }
0f3955e2 4928 gen_helper_load_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4929#endif
4930}
4931
4932/* tlbli */
c7697e1f 4933GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4934{
4935#if defined(CONFIG_USER_ONLY)
4936 GEN_EXCP_PRIVOPC(ctx);
4937#else
4938 if (unlikely(!ctx->supervisor)) {
4939 GEN_EXCP_PRIVOPC(ctx);
4940 return;
4941 }
0f3955e2 4942 gen_helper_load_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4943#endif
4944}
4945
76a66253
JM		 4946/* POWER instructions not in PowerPC 601 */
4947/* clf */
4948GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4949{
4950 /* Cache line flush: implemented as no-op */
4951}
4952
4953/* cli */
4954GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4955{
7f75ffd3 4956 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4957#if defined(CONFIG_USER_ONLY)
e1833e1f 4958 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4959#else
4960 if (unlikely(!ctx->supervisor)) {
e1833e1f 4961 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4962 return;
4963 }
4964#endif
4965}
4966
4967/* dclst */
4968GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4969{
4970 /* Data cache line store: treated as no-op */
4971}
4972
4973GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4974{
4975#if defined(CONFIG_USER_ONLY)
e1833e1f 4976 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4977#else
4978 if (unlikely(!ctx->supervisor)) {
e1833e1f 4979 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4980 return;
4981 }
4982 int ra = rA(ctx->opcode);
4983 int rd = rD(ctx->opcode);
4984
e2be8d8d 4985 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4986 gen_op_POWER_mfsri();
f78fb44e 4987 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4988 if (ra != 0 && ra != rd)
f78fb44e 4989 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4990#endif
4991}
4992
4993GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4994{
4995#if defined(CONFIG_USER_ONLY)
e1833e1f 4996 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4997#else
4998 if (unlikely(!ctx->supervisor)) {
e1833e1f 4999 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5000 return;
5001 }
e2be8d8d 5002 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5003 gen_op_POWER_rac();
f78fb44e 5004 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5005#endif
5006}
5007
5008GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5009{
5010#if defined(CONFIG_USER_ONLY)
e1833e1f 5011 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5012#else
5013 if (unlikely(!ctx->supervisor)) {
e1833e1f 5014 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5015 return;
5016 }
5017 gen_op_POWER_rfsvc();
e1833e1f 5018 GEN_SYNC(ctx);
76a66253
JM		 5019#endif
5020}
5021
5022/* svc is not implemented for now */
5023
5024/* POWER2 specific instructions */
5025/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5026
5027/* lfq */
5028GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5029{
01a4afeb
AJ		 5030 int rd = rD(ctx->opcode);
5031 TCGv t0 = tcg_temp_new();
5032 gen_addr_imm_index(t0, ctx, 0);
5033 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5034 tcg_gen_addi_tl(t0, t0, 8);
5035 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5036 tcg_temp_free(t0);
76a66253
JM		 5037}
5038
5039/* lfqu */
5040GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5041{
5042 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5043 int rd = rD(ctx->opcode);
5044 TCGv t0 = tcg_temp_new();
5045 TCGv t1 = tcg_temp_new();
5046 gen_addr_imm_index(t0, ctx, 0);
5047 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5048 tcg_gen_addi_tl(t1, t0, 8);
5049 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5050 if (ra != 0)
01a4afeb
AJ		 5051 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
76a66253
JM		 5054}
5055
5056/* lfqux */
5057GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5058{
5059 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5060 int rd = rD(ctx->opcode);
5061 TCGv t0 = tcg_temp_new();
5062 TCGv t1 = tcg_temp_new();
5063 gen_addr_reg_index(t0, ctx);
5064 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5065 tcg_gen_addi_tl(t1, t0, 8);
5066 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5067 if (ra != 0)
01a4afeb
AJ		 5068 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5069 tcg_temp_free(t0);
5070 tcg_temp_free(t1);
76a66253
JM		 5071}
5072
5073/* lfqx */
5074GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5075{
01a4afeb
AJ		 5076 int rd = rD(ctx->opcode);
5077 TCGv t0 = tcg_temp_new();
5078 gen_addr_reg_index(t0, ctx);
5079 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5080 tcg_gen_addi_tl(t0, t0, 8);
5081 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5082 tcg_temp_free(t0);
76a66253
JM		 5083}
5084
5085/* stfq */
5086GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5087{
01a4afeb
AJ		 5088 int rd = rD(ctx->opcode);
5089 TCGv t0 = tcg_temp_new();
5090 gen_addr_imm_index(t0, ctx, 0);
5091 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5092 tcg_gen_addi_tl(t0, t0, 8);
5093 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5094 tcg_temp_free(t0);
76a66253
JM		 5095}
5096
5097/* stfqu */
5098GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5099{
5100 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5101 int rd = rD(ctx->opcode);
5102 TCGv t0 = tcg_temp_new();
5103 TCGv t1 = tcg_temp_new();
5104 gen_addr_imm_index(t0, ctx, 0);
5105 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5106 tcg_gen_addi_tl(t1, t0, 8);
5107 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5108 if (ra != 0)
01a4afeb
AJ		 5109 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5110 tcg_temp_free(t0);
5111 tcg_temp_free(t1);
76a66253
JM		 5112}
5113
5114/* stfqux */
5115GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5116{
5117 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5118 int rd = rD(ctx->opcode);
5119 TCGv t0 = tcg_temp_new();
5120 TCGv t1 = tcg_temp_new();
5121 gen_addr_reg_index(t0, ctx);
5122 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5123 tcg_gen_addi_tl(t1, t0, 8);
5124 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5125 if (ra != 0)
01a4afeb
AJ		 5126 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5127 tcg_temp_free(t0);
5128 tcg_temp_free(t1);
76a66253
JM		 5129}
5130
5131/* stfqx */
5132GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5133{
01a4afeb
AJ		 5134 int rd = rD(ctx->opcode);
5135 TCGv t0 = tcg_temp_new();
5136 gen_addr_reg_index(t0, ctx);
5137 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5138 tcg_gen_addi_tl(t0, t0, 8);
5139 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5140 tcg_temp_free(t0);
76a66253
JM		 5141}
5142
5143/* BookE specific instructions */
2662a059 5144/* XXX: not implemented on 440 ? */
05332d70 5145GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5146{
5147 /* XXX: TODO */
e1833e1f 5148 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5149}
5150
2662a059 5151/* XXX: not implemented on 440 ? */
05332d70 5152GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5153{
5154#if defined(CONFIG_USER_ONLY)
e1833e1f 5155 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5156#else
5157 if (unlikely(!ctx->supervisor)) {
e1833e1f 5158 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5159 return;
5160 }
e2be8d8d 5161 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5162 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5163#if defined(TARGET_PPC64)
5164 if (ctx->sf_mode)
5165 gen_op_tlbie_64();
5166 else
5167#endif
5168 gen_op_tlbie();
76a66253
JM		 5169#endif
5170}
5171
5172/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5173static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5174 int opc2, int opc3,
5175 int ra, int rb, int rt, int Rc)
76a66253 5176{
182608d4
AJ		 5177 TCGv t0, t1;
5178
a7812ae4
PB		 5179 t0 = tcg_temp_local_new();
5180 t1 = tcg_temp_local_new();
182608d4 5181
76a66253
JM		 5182 switch (opc3 & 0x0D) {
5183 case 0x05:
5184 /* macchw - macchw. - macchwo - macchwo. */
5185 /* macchws - macchws. - macchwso - macchwso. */
5186 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5187 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5188 /* mulchw - mulchw. */
182608d4
AJ		 5189 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5190 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5191 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5192 break;
5193 case 0x04:
5194 /* macchwu - macchwu. - macchwuo - macchwuo. */
5195 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5196 /* mulchwu - mulchwu. */
182608d4
AJ		 5197 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5198 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5199 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5200 break;
5201 case 0x01:
5202 /* machhw - machhw. - machhwo - machhwo. */
5203 /* machhws - machhws. - machhwso - machhwso. */
5204 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5205 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5206 /* mulhhw - mulhhw. */
182608d4
AJ		 5207 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5208 tcg_gen_ext16s_tl(t0, t0);
5209 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5210 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5211 break;
5212 case 0x00:
5213 /* machhwu - machhwu. - machhwuo - machhwuo. */
5214 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5215 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5216 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5217 tcg_gen_ext16u_tl(t0, t0);
5218 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5219 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5220 break;
5221 case 0x0D:
5222 /* maclhw - maclhw. - maclhwo - maclhwo. */
5223 /* maclhws - maclhws. - maclhwso - maclhwso. */
5224 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5225 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5226 /* mullhw - mullhw. */
182608d4
AJ		 5227 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5228 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5229 break;
5230 case 0x0C:
5231 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5232 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5233 /* mullhwu - mullhwu. */
182608d4
AJ		 5234 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5235 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5236 break;
5237 }
76a66253 5238 if (opc2 & 0x04) {
182608d4
AJ		 5239 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5240 tcg_gen_mul_tl(t1, t0, t1);
5241 if (opc2 & 0x02) {
5242 /* nmultiply-and-accumulate (0x0E) */
5243 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5244 } else {
5245 /* multiply-and-accumulate (0x0C) */
5246 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5247 }
5248
5249 if (opc3 & 0x12) {
5250 /* Check overflow and/or saturate */
5251 int l1 = gen_new_label();
5252
5253 if (opc3 & 0x10) {
5254 /* Start with XER OV disabled, the most likely case */
5255 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5256 }
5257 if (opc3 & 0x01) {
5258 /* Signed */
5259 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5260 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5261 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5262 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5263 if (opc3 & 0x02) {
182608d4
AJ		 5264 /* Saturate */
5265 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5266 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5267 }
5268 } else {
5269 /* Unsigned */
5270 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5271 if (opc3 & 0x02) {
182608d4
AJ		 5272 /* Saturate */
5273 tcg_gen_movi_tl(t0, UINT32_MAX);
5274 }
5275 }
5276 if (opc3 & 0x10) {
5277 /* Check overflow */
5278 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5279 }
5280 gen_set_label(l1);
5281 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5282 }
5283 } else {
5284 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5285 }
182608d4
AJ		 5286 tcg_temp_free(t0);
5287 tcg_temp_free(t1);
76a66253
JM		 5288 if (unlikely(Rc) != 0) {
5289 /* Update Rc0 */
182608d4 5290 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5291 }
5292}
5293
a750fc0b
JM		 5294#define GEN_MAC_HANDLER(name, opc2, opc3) \
5295GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5296{ \
5297 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5298 rD(ctx->opcode), Rc(ctx->opcode)); \
5299}
5300
5301/* macchw - macchw. */
a750fc0b 5302GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5303/* macchwo - macchwo. */
a750fc0b 5304GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5305/* macchws - macchws. */
a750fc0b 5306GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5307/* macchwso - macchwso. */
a750fc0b 5308GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5309/* macchwsu - macchwsu. */
a750fc0b 5310GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5311/* macchwsuo - macchwsuo. */
a750fc0b 5312GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5313/* macchwu - macchwu. */
a750fc0b 5314GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5315/* macchwuo - macchwuo. */
a750fc0b 5316GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5317/* machhw - machhw. */
a750fc0b 5318GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5319/* machhwo - machhwo. */
a750fc0b 5320GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5321/* machhws - machhws. */
a750fc0b 5322GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5323/* machhwso - machhwso. */
a750fc0b 5324GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5325/* machhwsu - machhwsu. */
a750fc0b 5326GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5327/* machhwsuo - machhwsuo. */
a750fc0b 5328GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5329/* machhwu - machhwu. */
a750fc0b 5330GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5331/* machhwuo - machhwuo. */
a750fc0b 5332GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5333/* maclhw - maclhw. */
a750fc0b 5334GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5335/* maclhwo - maclhwo. */
a750fc0b 5336GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5337/* maclhws - maclhws. */
a750fc0b 5338GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5339/* maclhwso - maclhwso. */
a750fc0b 5340GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5341/* maclhwu - maclhwu. */
a750fc0b 5342GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5343/* maclhwuo - maclhwuo. */
a750fc0b 5344GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5345/* maclhwsu - maclhwsu. */
a750fc0b 5346GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5347/* maclhwsuo - maclhwsuo. */
a750fc0b 5348GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5349/* nmacchw - nmacchw. */
a750fc0b 5350GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5351/* nmacchwo - nmacchwo. */
a750fc0b 5352GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5353/* nmacchws - nmacchws. */
a750fc0b 5354GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5355/* nmacchwso - nmacchwso. */
a750fc0b 5356GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5357/* nmachhw - nmachhw. */
a750fc0b 5358GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5359/* nmachhwo - nmachhwo. */
a750fc0b 5360GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5361/* nmachhws - nmachhws. */
a750fc0b 5362GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5363/* nmachhwso - nmachhwso. */
a750fc0b 5364GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5365/* nmaclhw - nmaclhw. */
a750fc0b 5366GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5367/* nmaclhwo - nmaclhwo. */
a750fc0b 5368GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5369/* nmaclhws - nmaclhws. */
a750fc0b 5370GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5371/* nmaclhwso - nmaclhwso. */
a750fc0b 5372GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5373
5374/* mulchw - mulchw. */
a750fc0b 5375GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5376/* mulchwu - mulchwu. */
a750fc0b 5377GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5378/* mulhhw - mulhhw. */
a750fc0b 5379GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5380/* mulhhwu - mulhhwu. */
a750fc0b 5381GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5382/* mullhw - mullhw. */
a750fc0b 5383GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5384/* mullhwu - mullhwu. */
a750fc0b 5385GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5386
5387/* mfdcr */
05332d70 5388GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5389{
5390#if defined(CONFIG_USER_ONLY)
e1833e1f 5391 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5392#else
5393 uint32_t dcrn = SPR(ctx->opcode);
5394
5395 if (unlikely(!ctx->supervisor)) {
e1833e1f 5396 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5397 return;
5398 }
86c581dc 5399 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5400 gen_op_load_dcr();
f78fb44e 5401 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5402#endif
5403}
5404
5405/* mtdcr */
05332d70 5406GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5407{
5408#if defined(CONFIG_USER_ONLY)
e1833e1f 5409 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5410#else
5411 uint32_t dcrn = SPR(ctx->opcode);
5412
5413 if (unlikely(!ctx->supervisor)) {
e1833e1f 5414 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5415 return;
5416 }
86c581dc 5417 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5418 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5419 gen_op_store_dcr();
5420#endif
5421}
5422
5423/* mfdcrx */
2662a059 5424/* XXX: not implemented on 440 ? */
05332d70 5425GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5426{
5427#if defined(CONFIG_USER_ONLY)
e1833e1f 5428 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5429#else
5430 if (unlikely(!ctx->supervisor)) {
e1833e1f 5431 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5432 return;
5433 }
f78fb44e 5434 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5435 gen_op_load_dcr();
f78fb44e 5436 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5437 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5438#endif
5439}
5440
5441/* mtdcrx */
2662a059 5442/* XXX: not implemented on 440 ? */
05332d70 5443GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5444{
5445#if defined(CONFIG_USER_ONLY)
e1833e1f 5446 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5447#else
5448 if (unlikely(!ctx->supervisor)) {
e1833e1f 5449 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5450 return;
5451 }
f78fb44e
AJ		 5452 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5453 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5454 gen_op_store_dcr();
a750fc0b 5455 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5456#endif
5457}
5458
a750fc0b
JM		 5459/* mfdcrux (PPC 460) : user-mode access to DCR */
5460GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5461{
f78fb44e 5462 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5463 gen_op_load_dcr();
f78fb44e 5464 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5465 /* Note: Rc update flag set leads to undefined state of Rc0 */
5466}
5467
5468/* mtdcrux (PPC 460) : user-mode access to DCR */
5469GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5470{
f78fb44e
AJ		 5471 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5472 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5473 gen_op_store_dcr();
5474 /* Note: Rc update flag set leads to undefined state of Rc0 */
5475}
5476
76a66253
JM		 5477/* dccci */
5478GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5479{
5480#if defined(CONFIG_USER_ONLY)
e1833e1f 5481 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5482#else
5483 if (unlikely(!ctx->supervisor)) {
e1833e1f 5484 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5485 return;
5486 }
5487 /* interpreted as no-op */
5488#endif
5489}
5490
5491/* dcread */
5492GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5493{
5494#if defined(CONFIG_USER_ONLY)
e1833e1f 5495 GEN_EXCP_PRIVOPC(ctx);
76a66253 5496#else
b61f2753 5497 TCGv EA, val;
76a66253 5498 if (unlikely(!ctx->supervisor)) {
e1833e1f 5499 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5500 return;
5501 }
a7812ae4 5502 EA = tcg_temp_new();
a7859e89 5503 gen_set_access_type(ACCESS_CACHE);
b61f2753 5504 gen_addr_reg_index(EA, ctx);
a7812ae4 5505 val = tcg_temp_new();
b61f2753
AJ		 5506 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5507 tcg_temp_free(val);
5508 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5509 tcg_temp_free(EA);
76a66253
JM		 5510#endif
5511}
5512
5513/* icbt */
c7697e1f 5514GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5515{
5516 /* interpreted as no-op */
5517 /* XXX: specification say this is treated as a load by the MMU
5518 * but does not generate any exception
5519 */
5520}
5521
5522/* iccci */
5523GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5524{
5525#if defined(CONFIG_USER_ONLY)
e1833e1f 5526 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5527#else
5528 if (unlikely(!ctx->supervisor)) {
e1833e1f 5529 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5530 return;
5531 }
5532 /* interpreted as no-op */
5533#endif
5534}
5535
5536/* icread */
5537GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5538{
5539#if defined(CONFIG_USER_ONLY)
e1833e1f 5540 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5541#else
5542 if (unlikely(!ctx->supervisor)) {
e1833e1f 5543 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5544 return;
5545 }
5546 /* interpreted as no-op */
5547#endif
5548}
5549
5550/* rfci (supervisor only) */
c7697e1f 5551GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5552{
5553#if defined(CONFIG_USER_ONLY)
e1833e1f 5554 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5555#else
5556 if (unlikely(!ctx->supervisor)) {
e1833e1f 5557 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5558 return;
5559 }
5560 /* Restore CPU state */
5561 gen_op_40x_rfci();
e1833e1f 5562 GEN_SYNC(ctx);
a42bd6cc
JM		 5563#endif
5564}
5565
5566GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5567{
5568#if defined(CONFIG_USER_ONLY)
e1833e1f 5569 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5570#else
5571 if (unlikely(!ctx->supervisor)) {
e1833e1f 5572 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5573 return;
5574 }
5575 /* Restore CPU state */
5576 gen_op_rfci();
e1833e1f 5577 GEN_SYNC(ctx);
a42bd6cc
JM		 5578#endif
5579}
5580
5581/* BookE specific */
2662a059 5582/* XXX: not implemented on 440 ? */
05332d70 5583GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5584{
5585#if defined(CONFIG_USER_ONLY)
e1833e1f 5586 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5587#else
5588 if (unlikely(!ctx->supervisor)) {
e1833e1f 5589 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5590 return;
5591 }
5592 /* Restore CPU state */
a42bd6cc 5593 gen_op_rfdi();
e1833e1f 5594 GEN_SYNC(ctx);
76a66253
JM		 5595#endif
5596}
5597
2662a059 5598/* XXX: not implemented on 440 ? */
a750fc0b 5599GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5600{
5601#if defined(CONFIG_USER_ONLY)
e1833e1f 5602 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5603#else
5604 if (unlikely(!ctx->supervisor)) {
e1833e1f 5605 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5606 return;
5607 }
5608 /* Restore CPU state */
5609 gen_op_rfmci();
e1833e1f 5610 GEN_SYNC(ctx);
a42bd6cc
JM		 5611#endif
5612}
5eb7995e 5613
d9bce9d9 5614/* TLB management - PowerPC 405 implementation */
76a66253 5615/* tlbre */
c7697e1f 5616GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5617{
5618#if defined(CONFIG_USER_ONLY)
e1833e1f 5619 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5620#else
5621 if (unlikely(!ctx->supervisor)) {
e1833e1f 5622 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5623 return;
5624 }
5625 switch (rB(ctx->opcode)) {
5626 case 0:
f78fb44e 5627 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5628 gen_op_4xx_tlbre_hi();
f78fb44e 5629 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5630 break;
5631 case 1:
f78fb44e 5632 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5633 gen_op_4xx_tlbre_lo();
f78fb44e 5634 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5635 break;
5636 default:
e1833e1f 5637 GEN_EXCP_INVAL(ctx);
76a66253 5638 break;
9a64fbe4 5639 }
76a66253
JM		 5640#endif
5641}
5642
d9bce9d9 5643/* tlbsx - tlbsx. */
c7697e1f 5644GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5645{
5646#if defined(CONFIG_USER_ONLY)
e1833e1f 5647 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5648#else
5649 if (unlikely(!ctx->supervisor)) {
e1833e1f 5650 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5651 return;
5652 }
e2be8d8d 5653 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5654 gen_op_4xx_tlbsx();
76a66253 5655 if (Rc(ctx->opcode))
daf4f96e 5656 gen_op_4xx_tlbsx_check();
f78fb44e 5657 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5658#endif
79aceca5
FB		 5659}
5660
76a66253 5661/* tlbwe */
c7697e1f 5662GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5663{
76a66253 5664#if defined(CONFIG_USER_ONLY)
e1833e1f 5665 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5666#else
5667 if (unlikely(!ctx->supervisor)) {
e1833e1f 5668 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5669 return;
5670 }
5671 switch (rB(ctx->opcode)) {
5672 case 0:
f78fb44e
AJ		 5673 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5674 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5675 gen_op_4xx_tlbwe_hi();
5676 break;
5677 case 1:
f78fb44e
AJ		 5678 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5679 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5680 gen_op_4xx_tlbwe_lo();
5681 break;
5682 default:
e1833e1f 5683 GEN_EXCP_INVAL(ctx);
76a66253 5684 break;
9a64fbe4 5685 }
76a66253
JM		 5686#endif
5687}
5688
a4bb6c3e 5689/* TLB management - PowerPC 440 implementation */
5eb7995e 5690/* tlbre */
c7697e1f 5691GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5692{
5693#if defined(CONFIG_USER_ONLY)
e1833e1f 5694 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5695#else
5696 if (unlikely(!ctx->supervisor)) {
e1833e1f 5697 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5698 return;
5699 }
5700 switch (rB(ctx->opcode)) {
5701 case 0:
5eb7995e 5702 case 1:
5eb7995e 5703 case 2:
f78fb44e 5704 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5705 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5706 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5707 break;
5708 default:
e1833e1f 5709 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5710 break;
5711 }
5712#endif
5713}
5714
5715/* tlbsx - tlbsx. */
c7697e1f 5716GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5717{
5718#if defined(CONFIG_USER_ONLY)
e1833e1f 5719 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5720#else
5721 if (unlikely(!ctx->supervisor)) {
e1833e1f 5722 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5723 return;
5724 }
e2be8d8d 5725 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5726 gen_op_440_tlbsx();
5eb7995e 5727 if (Rc(ctx->opcode))
daf4f96e 5728 gen_op_4xx_tlbsx_check();
f78fb44e 5729 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5730#endif
5731}
5732
5733/* tlbwe */
c7697e1f 5734GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5735{
5736#if defined(CONFIG_USER_ONLY)
e1833e1f 5737 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5738#else
5739 if (unlikely(!ctx->supervisor)) {
e1833e1f 5740 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5741 return;
5742 }
5743 switch (rB(ctx->opcode)) {
5744 case 0:
5eb7995e 5745 case 1:
5eb7995e 5746 case 2:
f78fb44e
AJ		 5747 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5748 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5749 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5750 break;
5751 default:
e1833e1f 5752 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5753 break;
5754 }
5755#endif
5756}
5757
76a66253 5758/* wrtee */
05332d70 5759GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5760{
5761#if defined(CONFIG_USER_ONLY)
e1833e1f 5762 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5763#else
5764 if (unlikely(!ctx->supervisor)) {
e1833e1f 5765 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5766 return;
5767 }
f78fb44e 5768 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5769 gen_op_wrte();
dee96f6c
JM		 5770 /* Stop translation to have a chance to raise an exception
5771 * if we just set msr_ee to 1
5772 */
e1833e1f 5773 GEN_STOP(ctx);
76a66253
JM		 5774#endif
5775}
5776
5777/* wrteei */
05332d70 5778GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5779{
5780#if defined(CONFIG_USER_ONLY)
e1833e1f 5781 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5782#else
5783 if (unlikely(!ctx->supervisor)) {
e1833e1f 5784 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5785 return;
5786 }
86c581dc 5787 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5788 gen_op_wrte();
dee96f6c
JM		 5789 /* Stop translation to have a chance to raise an exception
5790 * if we just set msr_ee to 1
5791 */
e1833e1f 5792 GEN_STOP(ctx);
76a66253
JM		 5793#endif
5794}
5795
08e46e54 5796/* PowerPC 440 specific instructions */
76a66253
JM		 5797/* dlmzb */
5798GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5799{
f78fb44e
AJ		 5800 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5801 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5802 gen_op_440_dlmzb();
f78fb44e 5803 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5804 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5805 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5806 if (Rc(ctx->opcode)) {
5807 gen_op_440_dlmzb_update_Rc();
a7812ae4
PB		 5808 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_T[0]);
5809 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 0xf);
76a66253
JM		 5810 }
5811}
5812
5813/* mbar replaces eieio on 440 */
5814GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5815{
5816 /* interpreted as no-op */
5817}
5818
5819/* msync replaces sync on 440 */
0db1b20e 5820GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5821{
5822 /* interpreted as no-op */
5823}
5824
5825/* icbt */
c7697e1f 5826GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5827{
5828 /* interpreted as no-op */
5829 /* XXX: specification say this is treated as a load by the MMU
5830 * but does not generate any exception
5831 */
79aceca5
FB		 5832}
5833
a9d9eb8f
JM		 5834/*** Altivec vector extension ***/
5835/* Altivec registers moves */
a9d9eb8f 5836
a9d9eb8f 5837#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 5838GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 5839{ \
fe1e5c53 5840 TCGv EA; \
a9d9eb8f
JM		 5841 if (unlikely(!ctx->altivec_enabled)) { \
5842 GEN_EXCP_NO_VR(ctx); \
5843 return; \
5844 } \
fe1e5c53
AJ		 5845 EA = tcg_temp_new(); \
5846 gen_addr_reg_index(EA, ctx); \
5847 tcg_gen_andi_tl(EA, EA, ~0xf); \
5848 if (ctx->mem_idx & 1) { \
5849 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5850 tcg_gen_addi_tl(EA, EA, 8); \
5851 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5852 } else { \
5853 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5854 tcg_gen_addi_tl(EA, EA, 8); \
5855 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5856 } \
5857 tcg_temp_free(EA); \
a9d9eb8f
JM		 5858}
5859
5860#define GEN_VR_STX(name, opc2, opc3) \
5861GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5862{ \
fe1e5c53 5863 TCGv EA; \
a9d9eb8f
JM		 5864 if (unlikely(!ctx->altivec_enabled)) { \
5865 GEN_EXCP_NO_VR(ctx); \
5866 return; \
5867 } \
fe1e5c53
AJ		 5868 EA = tcg_temp_new(); \
5869 gen_addr_reg_index(EA, ctx); \
5870 tcg_gen_andi_tl(EA, EA, ~0xf); \
5871 if (ctx->mem_idx & 1) { \
5872 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5873 tcg_gen_addi_tl(EA, EA, 8); \
5874 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5875 } else { \
5876 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5877 tcg_gen_addi_tl(EA, EA, 8); \
5878 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5879 } \
5880 tcg_temp_free(EA); \
a9d9eb8f
JM		 5881}
5882
fe1e5c53 5883GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 5884/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 5885GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 5886
fe1e5c53 5887GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 5888/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 5889GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 5890
0487d6a8 5891/*** SPE extension ***/
0487d6a8 5892/* Register moves */
3cd7d1dd 5893
a7812ae4 5894static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 5895#if defined(TARGET_PPC64)
5896 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5897#else
36aa55dc 5898 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5899#endif
f78fb44e 5900}
3cd7d1dd 5901
a7812ae4 5902static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 5903#if defined(TARGET_PPC64)
5904 tcg_gen_mov_i64(cpu_gpr[reg], t);
5905#else
a7812ae4 5906 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 5907 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 5908 tcg_gen_shri_i64(tmp, t, 32);
5909 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 5910 tcg_temp_free_i64(tmp);
3cd7d1dd 5911#endif
f78fb44e 5912}
3cd7d1dd 5913
0487d6a8
JM		 5914#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5915GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5916{ \
5917 if (Rc(ctx->opcode)) \
5918 gen_##name1(ctx); \
5919 else \
5920 gen_##name0(ctx); \
5921}
5922
5923/* Handler for undefined SPE opcodes */
b068d6a7 5924static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5925{
e1833e1f 5926 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5927}
5928
57951c27
AJ		 5929/* SPE logic */
5930#if defined(TARGET_PPC64)
5931#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 5932static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5933{ \
5934 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5935 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5936 return; \
5937 } \
57951c27
AJ		 5938 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5939 cpu_gpr[rB(ctx->opcode)]); \
5940}
5941#else
5942#define GEN_SPEOP_LOGIC2(name, tcg_op) \
5943static always_inline void gen_##name (DisasContext *ctx) \
5944{ \
5945 if (unlikely(!ctx->spe_enabled)) { \
5946 GEN_EXCP_NO_AP(ctx); \
5947 return; \
5948 } \
5949 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5950 cpu_gpr[rB(ctx->opcode)]); \
5951 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
5952 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 5953}
57951c27
AJ		 5954#endif
5955
5956GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
5957GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
5958GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
5959GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
5960GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
5961GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
5962GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
5963GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 5964
57951c27
AJ		 5965/* SPE logic immediate */
5966#if defined(TARGET_PPC64)
5967#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 5968static always_inline void gen_##name (DisasContext *ctx) \
5969{ \
5970 if (unlikely(!ctx->spe_enabled)) { \
5971 GEN_EXCP_NO_AP(ctx); \
5972 return; \
5973 } \
a7812ae4
PB		 5974 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
5975 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
5976 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 5977 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
5978 tcg_opi(t0, t0, rB(ctx->opcode)); \
5979 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
5980 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 5981 tcg_temp_free_i64(t2); \
57951c27
AJ		 5982 tcg_opi(t1, t1, rB(ctx->opcode)); \
5983 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 5984 tcg_temp_free_i32(t0); \
5985 tcg_temp_free_i32(t1); \
3d3a6a0a 5986}
57951c27
AJ		 5987#else
5988#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 5989static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5990{ \
5991 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5992 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5993 return; \
5994 } \
57951c27
AJ		 5995 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5996 rB(ctx->opcode)); \
5997 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
5998 rB(ctx->opcode)); \
0487d6a8 5999}
57951c27
AJ		 6000#endif
6001GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6002GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6003GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6004GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6005
57951c27
AJ		 6006/* SPE arithmetic */
6007#if defined(TARGET_PPC64)
6008#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6009static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6010{ \
6011 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6012 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6013 return; \
6014 } \
a7812ae4
PB		 6015 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6016 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6017 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6018 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6019 tcg_op(t0, t0); \
6020 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6021 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6022 tcg_temp_free_i64(t2); \
57951c27
AJ		 6023 tcg_op(t1, t1); \
6024 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6025 tcg_temp_free_i32(t0); \
6026 tcg_temp_free_i32(t1); \
0487d6a8 6027}
57951c27 6028#else
a7812ae4 6029#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6030static always_inline void gen_##name (DisasContext *ctx) \
6031{ \
6032 if (unlikely(!ctx->spe_enabled)) { \
6033 GEN_EXCP_NO_AP(ctx); \
6034 return; \
6035 } \
6036 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6037 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6038}
6039#endif
0487d6a8 6040
a7812ae4 6041static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6042{
6043 int l1 = gen_new_label();
6044 int l2 = gen_new_label();
0487d6a8 6045
57951c27
AJ		 6046 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6047 tcg_gen_neg_i32(ret, arg1);
6048 tcg_gen_br(l2);
6049 gen_set_label(l1);
a7812ae4 6050 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6051 gen_set_label(l2);
6052}
6053GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6054GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6055GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6056GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6057static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6058{
57951c27
AJ		 6059 tcg_gen_addi_i32(ret, arg1, 0x8000);
6060 tcg_gen_ext16u_i32(ret, ret);
6061}
6062GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6063GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6064GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6065
57951c27
AJ		 6066#if defined(TARGET_PPC64)
6067#define GEN_SPEOP_ARITH2(name, tcg_op) \
6068static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6069{ \
6070 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6071 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6072 return; \
6073 } \
a7812ae4
PB		 6074 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6075 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6076 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6077 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
57951c27
AJ		 6078 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6079 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6080 tcg_op(t0, t0, t2); \
6081 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6082 tcg_gen_trunc_i64_i32(t1, t3); \
6083 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6084 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6085 tcg_temp_free_i64(t3); \
57951c27 6086 tcg_op(t1, t1, t2); \
a7812ae4 6087 tcg_temp_free_i32(t2); \
57951c27 6088 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6089 tcg_temp_free_i32(t0); \
6090 tcg_temp_free_i32(t1); \
0487d6a8 6091}
57951c27
AJ		 6092#else
6093#define GEN_SPEOP_ARITH2(name, tcg_op) \
6094static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6095{ \
6096 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6097 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6098 return; \
6099 } \
57951c27
AJ		 6100 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6101 cpu_gpr[rB(ctx->opcode)]); \
6102 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6103 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6104}
57951c27 6105#endif
0487d6a8 6106
a7812ae4 6107static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6108{
a7812ae4 6109 TCGv_i32 t0;
57951c27 6110 int l1, l2;
0487d6a8 6111
57951c27
AJ		 6112 l1 = gen_new_label();
6113 l2 = gen_new_label();
a7812ae4 6114 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6115 /* No error here: 6 bits are used */
6116 tcg_gen_andi_i32(t0, arg2, 0x3F);
6117 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6118 tcg_gen_shr_i32(ret, arg1, t0);
6119 tcg_gen_br(l2);
6120 gen_set_label(l1);
6121 tcg_gen_movi_i32(ret, 0);
6122 tcg_gen_br(l2);
a7812ae4 6123 tcg_temp_free_i32(t0);
57951c27
AJ		 6124}
6125GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6126static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6127{
a7812ae4 6128 TCGv_i32 t0;
57951c27
AJ		 6129 int l1, l2;
6130
6131 l1 = gen_new_label();
6132 l2 = gen_new_label();
a7812ae4 6133 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6134 /* No error here: 6 bits are used */
6135 tcg_gen_andi_i32(t0, arg2, 0x3F);
6136 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6137 tcg_gen_sar_i32(ret, arg1, t0);
6138 tcg_gen_br(l2);
6139 gen_set_label(l1);
6140 tcg_gen_movi_i32(ret, 0);
6141 tcg_gen_br(l2);
a7812ae4 6142 tcg_temp_free_i32(t0);
57951c27
AJ		 6143}
6144GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6145static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6146{
a7812ae4 6147 TCGv_i32 t0;
57951c27
AJ		 6148 int l1, l2;
6149
6150 l1 = gen_new_label();
6151 l2 = gen_new_label();
a7812ae4 6152 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6153 /* No error here: 6 bits are used */
6154 tcg_gen_andi_i32(t0, arg2, 0x3F);
6155 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6156 tcg_gen_shl_i32(ret, arg1, t0);
6157 tcg_gen_br(l2);
6158 gen_set_label(l1);
6159 tcg_gen_movi_i32(ret, 0);
6160 tcg_gen_br(l2);
a7812ae4 6161 tcg_temp_free_i32(t0);
57951c27
AJ		 6162}
6163GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6164static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6165{
a7812ae4 6166 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6167 tcg_gen_andi_i32(t0, arg2, 0x1F);
6168 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6169 tcg_temp_free_i32(t0);
57951c27
AJ		 6170}
6171GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6172static always_inline void gen_evmergehi (DisasContext *ctx)
6173{
6174 if (unlikely(!ctx->spe_enabled)) {
6175 GEN_EXCP_NO_AP(ctx);
6176 return;
6177 }
6178#if defined(TARGET_PPC64)
a7812ae4
PB		 6179 TCGv t0 = tcg_temp_new();
6180 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6181 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6182 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6183 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6184 tcg_temp_free(t0);
6185 tcg_temp_free(t1);
6186#else
6187 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6188 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6189#endif
6190}
6191GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6192static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6193{
57951c27
AJ		 6194 tcg_gen_sub_i32(ret, arg2, arg1);
6195}
6196GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6197
57951c27
AJ		 6198/* SPE arithmetic immediate */
6199#if defined(TARGET_PPC64)
6200#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6201static always_inline void gen_##name (DisasContext *ctx) \
6202{ \
6203 if (unlikely(!ctx->spe_enabled)) { \
6204 GEN_EXCP_NO_AP(ctx); \
6205 return; \
6206 } \
a7812ae4
PB		 6207 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6208 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6209 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6210 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6211 tcg_op(t0, t0, rA(ctx->opcode)); \
6212 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6213 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6214 tcg_temp_free_i64(t2); \
57951c27
AJ		 6215 tcg_op(t1, t1, rA(ctx->opcode)); \
6216 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6217 tcg_temp_free_i32(t0); \
6218 tcg_temp_free_i32(t1); \
57951c27
AJ		 6219}
6220#else
6221#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6222static always_inline void gen_##name (DisasContext *ctx) \
6223{ \
6224 if (unlikely(!ctx->spe_enabled)) { \
6225 GEN_EXCP_NO_AP(ctx); \
6226 return; \
6227 } \
6228 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6229 rA(ctx->opcode)); \
6230 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6231 rA(ctx->opcode)); \
6232}
6233#endif
6234GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6235GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6236
6237/* SPE comparison */
6238#if defined(TARGET_PPC64)
6239#define GEN_SPEOP_COMP(name, tcg_cond) \
6240static always_inline void gen_##name (DisasContext *ctx) \
6241{ \
6242 if (unlikely(!ctx->spe_enabled)) { \
6243 GEN_EXCP_NO_AP(ctx); \
6244 return; \
6245 } \
6246 int l1 = gen_new_label(); \
6247 int l2 = gen_new_label(); \
6248 int l3 = gen_new_label(); \
6249 int l4 = gen_new_label(); \
a7812ae4
PB		 6250 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6251 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6252 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6253 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6254 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6255 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6256 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6257 tcg_gen_br(l2); \
6258 gen_set_label(l1); \
6259 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6260 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6261 gen_set_label(l2); \
6262 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6263 tcg_gen_trunc_i64_i32(t0, t2); \
6264 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6265 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6266 tcg_temp_free_i64(t2); \
57951c27
AJ		 6267 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6268 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6269 ~(CRF_CH | CRF_CH_AND_CL)); \
6270 tcg_gen_br(l4); \
6271 gen_set_label(l3); \
6272 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6273 CRF_CH | CRF_CH_OR_CL); \
6274 gen_set_label(l4); \
a7812ae4
PB		 6275 tcg_temp_free_i32(t0); \
6276 tcg_temp_free_i32(t1); \
57951c27
AJ		 6277}
6278#else
6279#define GEN_SPEOP_COMP(name, tcg_cond) \
6280static always_inline void gen_##name (DisasContext *ctx) \
6281{ \
6282 if (unlikely(!ctx->spe_enabled)) { \
6283 GEN_EXCP_NO_AP(ctx); \
6284 return; \
6285 } \
6286 int l1 = gen_new_label(); \
6287 int l2 = gen_new_label(); \
6288 int l3 = gen_new_label(); \
6289 int l4 = gen_new_label(); \
6290 \
6291 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6292 cpu_gpr[rB(ctx->opcode)], l1); \
6293 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6294 tcg_gen_br(l2); \
6295 gen_set_label(l1); \
6296 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6297 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6298 gen_set_label(l2); \
6299 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6300 cpu_gprh[rB(ctx->opcode)], l3); \
6301 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6302 ~(CRF_CH | CRF_CH_AND_CL)); \
6303 tcg_gen_br(l4); \
6304 gen_set_label(l3); \
6305 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6306 CRF_CH | CRF_CH_OR_CL); \
6307 gen_set_label(l4); \
6308}
6309#endif
6310GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6311GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6312GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6313GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6314GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6315
6316/* SPE misc */
6317static always_inline void gen_brinc (DisasContext *ctx)
6318{
6319 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6320 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6321 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6322}
57951c27
AJ		 6323static always_inline void gen_evmergelo (DisasContext *ctx)
6324{
6325 if (unlikely(!ctx->spe_enabled)) {
6326 GEN_EXCP_NO_AP(ctx);
6327 return;
6328 }
6329#if defined(TARGET_PPC64)
a7812ae4
PB		 6330 TCGv t0 = tcg_temp_new();
6331 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6332 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6333 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6334 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6335 tcg_temp_free(t0);
6336 tcg_temp_free(t1);
6337#else
6338 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6339 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6340#endif
6341}
6342static always_inline void gen_evmergehilo (DisasContext *ctx)
6343{
6344 if (unlikely(!ctx->spe_enabled)) {
6345 GEN_EXCP_NO_AP(ctx);
6346 return;
6347 }
6348#if defined(TARGET_PPC64)
a7812ae4
PB		 6349 TCGv t0 = tcg_temp_new();
6350 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6351 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6352 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6353 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6354 tcg_temp_free(t0);
6355 tcg_temp_free(t1);
6356#else
6357 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6358 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6359#endif
6360}
6361static always_inline void gen_evmergelohi (DisasContext *ctx)
6362{
6363 if (unlikely(!ctx->spe_enabled)) {
6364 GEN_EXCP_NO_AP(ctx);
6365 return;
6366 }
6367#if defined(TARGET_PPC64)
a7812ae4
PB		 6368 TCGv t0 = tcg_temp_new();
6369 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6370 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6371 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6372 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6373 tcg_temp_free(t0);
6374 tcg_temp_free(t1);
6375#else
6376 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6377 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6378#endif
6379}
6380static always_inline void gen_evsplati (DisasContext *ctx)
6381{
38d14952 6382 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 6383
57951c27 6384#if defined(TARGET_PPC64)
38d14952 6385 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6386#else
6387 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6388 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6389#endif
6390}
b068d6a7 6391static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 6392{
38d14952 6393 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 6394
57951c27 6395#if defined(TARGET_PPC64)
38d14952 6396 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6397#else
6398 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6399 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6400#endif
0487d6a8
JM		 6401}
6402
57951c27
AJ		 6403static always_inline void gen_evsel (DisasContext *ctx)
6404{
6405 int l1 = gen_new_label();
6406 int l2 = gen_new_label();
6407 int l3 = gen_new_label();
6408 int l4 = gen_new_label();
a7812ae4 6409 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 6410#if defined(TARGET_PPC64)
a7812ae4
PB		 6411 TCGv t1 = tcg_temp_local_new();
6412 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 6413#endif
6414 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6415 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6416#if defined(TARGET_PPC64)
6417 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6418#else
6419 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6420#endif
6421 tcg_gen_br(l2);
6422 gen_set_label(l1);
6423#if defined(TARGET_PPC64)
6424 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6425#else
6426 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6427#endif
6428 gen_set_label(l2);
6429 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6430 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6431#if defined(TARGET_PPC64)
6432 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6433#else
6434 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6435#endif
6436 tcg_gen_br(l4);
6437 gen_set_label(l3);
6438#if defined(TARGET_PPC64)
6439 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6440#else
6441 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6442#endif
6443 gen_set_label(l4);
a7812ae4 6444 tcg_temp_free_i32(t0);
57951c27
AJ		 6445#if defined(TARGET_PPC64)
6446 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6447 tcg_temp_free(t1);
6448 tcg_temp_free(t2);
6449#endif
6450}
6451GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6452{
6453 gen_evsel(ctx);
6454}
6455GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6456{
6457 gen_evsel(ctx);
6458}
6459GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6460{
6461 gen_evsel(ctx);
6462}
6463GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6464{
6465 gen_evsel(ctx);
6466}
0487d6a8
JM		 6467
6468GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6469GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6470GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6471GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6472GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6473GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6474GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6475GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6476GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6477GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6478GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6479GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6480GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6481GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6482GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6483GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6484GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6485GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6486GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6487GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6488GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6489GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6490GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6491GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6492GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6493
6a6ae23f
AJ		 6494/* SPE load and stores */
6495static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
6496{
6497 target_ulong uimm = rB(ctx->opcode);
6498
6499 if (rA(ctx->opcode) == 0)
6500 tcg_gen_movi_tl(EA, uimm << sh);
6501 else
6502 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
0487d6a8 6503}
6a6ae23f
AJ		 6504
6505static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6506{
6507#if defined(TARGET_PPC64)
6508 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6509#else
6510 TCGv_i64 t0 = tcg_temp_new_i64();
6511 gen_qemu_ld64(t0, addr, ctx->mem_idx);
6512 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6513 tcg_gen_shri_i64(t0, t0, 32);
6514 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6515 tcg_temp_free_i64(t0);
6516#endif
0487d6a8 6517}
6a6ae23f
AJ		 6518
6519static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6520{
0487d6a8 6521#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6522 TCGv t0 = tcg_temp_new();
6523 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6524 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6525 tcg_gen_addi_tl(addr, addr, 4);
6526 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6527 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6528 tcg_temp_free(t0);
6529#else
6530 gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6531 tcg_gen_addi_tl(addr, addr, 4);
6532 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6533#endif
0487d6a8 6534}
6a6ae23f
AJ		 6535
6536static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6537{
6538 TCGv t0 = tcg_temp_new();
6539#if defined(TARGET_PPC64)
6540 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6541 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6542 tcg_gen_addi_tl(addr, addr, 2);
6543 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6544 tcg_gen_shli_tl(t0, t0, 32);
6545 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6546 tcg_gen_addi_tl(addr, addr, 2);
6547 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6548 tcg_gen_shli_tl(t0, t0, 16);
6549 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6550 tcg_gen_addi_tl(addr, addr, 2);
6551 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6552 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6553#else
6a6ae23f
AJ		 6554 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6555 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6556 tcg_gen_addi_tl(addr, addr, 2);
6557 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6558 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6559 tcg_gen_addi_tl(addr, addr, 2);
6560 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6561 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6562 tcg_gen_addi_tl(addr, addr, 2);
6563 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6564 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6565#endif
6a6ae23f 6566 tcg_temp_free(t0);
0487d6a8
JM		 6567}
6568
6a6ae23f
AJ		 6569static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6570{
6571 TCGv t0 = tcg_temp_new();
6572 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6573#if defined(TARGET_PPC64)
6574 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6575 tcg_gen_shli_tl(t0, t0, 16);
6576 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6577#else
6578 tcg_gen_shli_tl(t0, t0, 16);
6579 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6580 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6581#endif
6582 tcg_temp_free(t0);
0487d6a8
JM		 6583}
6584
6a6ae23f
AJ		 6585static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6586{
6587 TCGv t0 = tcg_temp_new();
6588 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6589#if defined(TARGET_PPC64)
6590 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6591 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6592#else
6593 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6594 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6595#endif
6596 tcg_temp_free(t0);
0487d6a8
JM		 6597}
6598
6a6ae23f
AJ		 6599static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6600{
6601 TCGv t0 = tcg_temp_new();
6602 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6603#if defined(TARGET_PPC64)
6604 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6605 tcg_gen_ext32u_tl(t0, t0);
6606 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6607#else
6608 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6609 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6610#endif
6611 tcg_temp_free(t0);
6612}
6613
6614static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6615{
6616 TCGv t0 = tcg_temp_new();
6617#if defined(TARGET_PPC64)
6618 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6619 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6620 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6621 tcg_gen_shli_tl(t0, t0, 16);
6622 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6623#else
6624 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6625 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6626 tcg_gen_addi_tl(addr, addr, 2);
6627 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6628 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6629#endif
6630 tcg_temp_free(t0);
6631}
6632
6633static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6634{
6635#if defined(TARGET_PPC64)
6636 TCGv t0 = tcg_temp_new();
6637 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6638 tcg_gen_addi_tl(addr, addr, 2);
6639 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6640 tcg_gen_shli_tl(t0, t0, 32);
6641 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6642 tcg_temp_free(t0);
6643#else
6644 gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6645 tcg_gen_addi_tl(addr, addr, 2);
6646 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6647#endif
6648}
6649
6650static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6651{
6652#if defined(TARGET_PPC64)
6653 TCGv t0 = tcg_temp_new();
6654 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6655 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6656 tcg_gen_addi_tl(addr, addr, 2);
6657 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6658 tcg_gen_shli_tl(t0, t0, 32);
6659 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6660 tcg_temp_free(t0);
6661#else
6662 gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6663 tcg_gen_addi_tl(addr, addr, 2);
6664 gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6665#endif
6666}
6667
6668static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6669{
6670 TCGv t0 = tcg_temp_new();
6671 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
0487d6a8 6672#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6673 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6674 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6675#else
6676 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6677 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6678#endif
6679 tcg_temp_free(t0);
6680}
6681
6682static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6683{
6684 TCGv t0 = tcg_temp_new();
6685#if defined(TARGET_PPC64)
6686 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6687 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6688 tcg_gen_shli_tl(t0, t0, 32);
6689 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6690 tcg_gen_addi_tl(addr, addr, 2);
6691 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6692 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6693 tcg_gen_shli_tl(t0, t0, 16);
6694 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6695#else
6696 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6697 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6698 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6699 tcg_gen_addi_tl(addr, addr, 2);
6700 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6701 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6702 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 6703#endif
6a6ae23f
AJ		 6704 tcg_temp_free(t0);
6705}
6706
6707static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6708{
6709#if defined(TARGET_PPC64)
6710 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
0487d6a8 6711#else
6a6ae23f
AJ		 6712 TCGv_i64 t0 = tcg_temp_new_i64();
6713 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6714 gen_qemu_st64(t0, addr, ctx->mem_idx);
6715 tcg_temp_free_i64(t0);
6716#endif
6717}
6718
6719static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6720{
0487d6a8 6721#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6722 TCGv t0 = tcg_temp_new();
6723 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6724 gen_qemu_st32(t0, addr, ctx->mem_idx);
6725 tcg_temp_free(t0);
6726#else
6727 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6728#endif
6729 tcg_gen_addi_tl(addr, addr, 4);
6730 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6731}
6732
6733static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6734{
6735 TCGv t0 = tcg_temp_new();
6736#if defined(TARGET_PPC64)
6737 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6738#else
6739 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6740#endif
6741 gen_qemu_st16(t0, addr, ctx->mem_idx);
6742 tcg_gen_addi_tl(addr, addr, 2);
6743#if defined(TARGET_PPC64)
6744 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6745 gen_qemu_st16(t0, addr, ctx->mem_idx);
6746#else
6747 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6748#endif
6749 tcg_gen_addi_tl(addr, addr, 2);
6750 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6751 gen_qemu_st16(t0, addr, ctx->mem_idx);
6752 tcg_temp_free(t0);
6753 tcg_gen_addi_tl(addr, addr, 2);
6754 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6755}
6756
6757static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6758{
6759 TCGv t0 = tcg_temp_new();
6760#if defined(TARGET_PPC64)
6761 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6762#else
6763 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6764#endif
6765 gen_qemu_st16(t0, addr, ctx->mem_idx);
6766 tcg_gen_addi_tl(addr, addr, 2);
6767 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6768 gen_qemu_st16(t0, addr, ctx->mem_idx);
6769 tcg_temp_free(t0);
6770}
6771
6772static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6773{
6774#if defined(TARGET_PPC64)
6775 TCGv t0 = tcg_temp_new();
6776 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6777 gen_qemu_st16(t0, addr, ctx->mem_idx);
6778 tcg_temp_free(t0);
6779#else
6780 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6781#endif
6782 tcg_gen_addi_tl(addr, addr, 2);
6783 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6784}
6785
6786static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6787{
6788#if defined(TARGET_PPC64)
6789 TCGv t0 = tcg_temp_new();
6790 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6791 gen_qemu_st32(t0, addr, ctx->mem_idx);
6792 tcg_temp_free(t0);
6793#else
6794 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6795#endif
6796}
6797
6798static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6799{
6800 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6801}
6802
6803#define GEN_SPEOP_LDST(name, opc2, sh) \
6804GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6805{ \
6806 TCGv t0; \
6807 if (unlikely(!ctx->spe_enabled)) { \
6808 GEN_EXCP_NO_AP(ctx); \
6809 return; \
6810 } \
6811 t0 = tcg_temp_new(); \
6812 if (Rc(ctx->opcode)) { \
6813 gen_addr_spe_imm_index(t0, ctx, sh); \
6814 } else { \
6815 gen_addr_reg_index(t0, ctx); \
6816 } \
6817 gen_op_##name(ctx, t0); \
6818 tcg_temp_free(t0); \
6819}
6820
6821GEN_SPEOP_LDST(evldd, 0x00, 3);
6822GEN_SPEOP_LDST(evldw, 0x01, 3);
6823GEN_SPEOP_LDST(evldh, 0x02, 3);
6824GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
6825GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
6826GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
6827GEN_SPEOP_LDST(evlwhe, 0x08, 2);
6828GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
6829GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
6830GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
6831GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
6832
6833GEN_SPEOP_LDST(evstdd, 0x10, 3);
6834GEN_SPEOP_LDST(evstdw, 0x11, 3);
6835GEN_SPEOP_LDST(evstdh, 0x12, 3);
6836GEN_SPEOP_LDST(evstwhe, 0x18, 2);
6837GEN_SPEOP_LDST(evstwho, 0x1A, 2);
6838GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
6839GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 6840
6841/* Multiply and add - TODO */
6842#if 0
6843GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6844GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6845GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6846GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6847GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6848GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6849GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6850GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6851GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6852GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6853GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6854GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6855
6856GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6857GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6858GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6859GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6860GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6861GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6862GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6863GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6864GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6865GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6866GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6867GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6868GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6869GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6870
6871GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6872GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6873GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6874GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6875GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6876GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6877
6878GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6879GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6880GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6881GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6882GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6883GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6884GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6885GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6886GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6887GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6888GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6889GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6890
6891GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6892GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6893GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6894GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6895GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6896
6897GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6898GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6899GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6900GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6901GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6902GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6903GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6904GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6905GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6906GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6907GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6908GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6909
6910GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6911GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6912GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6913GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6914GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6915#endif
6916
6917/*** SPE floating-point extension ***/
1c97856d
AJ		 6918#if defined(TARGET_PPC64)
6919#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 6920static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6921{ \
1c97856d
AJ		 6922 TCGv_i32 t0; \
6923 TCGv t1; \
6924 t0 = tcg_temp_new_i32(); \
6925 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6926 gen_helper_##name(t0, t0); \
6927 t1 = tcg_temp_new(); \
6928 tcg_gen_extu_i32_tl(t1, t0); \
6929 tcg_temp_free_i32(t0); \
6930 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6931 0xFFFFFFFF00000000ULL); \
6932 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6933 tcg_temp_free(t1); \
0487d6a8 6934}
1c97856d
AJ		 6935#define GEN_SPEFPUOP_CONV_32_64(name) \
6936static always_inline void gen_##name (DisasContext *ctx) \
6937{ \
6938 TCGv_i32 t0; \
6939 TCGv t1; \
6940 t0 = tcg_temp_new_i32(); \
6941 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
6942 t1 = tcg_temp_new(); \
6943 tcg_gen_extu_i32_tl(t1, t0); \
6944 tcg_temp_free_i32(t0); \
6945 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6946 0xFFFFFFFF00000000ULL); \
6947 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6948 tcg_temp_free(t1); \
6949}
6950#define GEN_SPEFPUOP_CONV_64_32(name) \
6951static always_inline void gen_##name (DisasContext *ctx) \
6952{ \
6953 TCGv_i32 t0 = tcg_temp_new_i32(); \
6954 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6955 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
6956 tcg_temp_free_i32(t0); \
6957}
6958#define GEN_SPEFPUOP_CONV_64_64(name) \
6959static always_inline void gen_##name (DisasContext *ctx) \
6960{ \
6961 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6962}
6963#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 6964static always_inline void gen_##name (DisasContext *ctx) \
6965{ \
1c97856d
AJ		 6966 TCGv_i32 t0, t1; \
6967 TCGv_i64 t2; \
57951c27
AJ		 6968 if (unlikely(!ctx->spe_enabled)) { \
6969 GEN_EXCP_NO_AP(ctx); \
6970 return; \
6971 } \
1c97856d
AJ		 6972 t0 = tcg_temp_new_i32(); \
6973 t1 = tcg_temp_new_i32(); \
6974 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6975 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6976 gen_helper_##name(t0, t0, t1); \
6977 tcg_temp_free_i32(t1); \
6978 t2 = tcg_temp_new(); \
6979 tcg_gen_extu_i32_tl(t2, t0); \
6980 tcg_temp_free_i32(t0); \
6981 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6982 0xFFFFFFFF00000000ULL); \
6983 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
6984 tcg_temp_free(t2); \
57951c27 6985}
1c97856d 6986#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 6987static always_inline void gen_##name (DisasContext *ctx) \
6988{ \
6989 if (unlikely(!ctx->spe_enabled)) { \
6990 GEN_EXCP_NO_AP(ctx); \
6991 return; \
6992 } \
1c97856d
AJ		 6993 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6994 cpu_gpr[rB(ctx->opcode)]); \
57951c27 6995}
1c97856d 6996#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 6997static always_inline void gen_##name (DisasContext *ctx) \
6998{ \
1c97856d 6999 TCGv_i32 t0, t1; \
57951c27
AJ		 7000 if (unlikely(!ctx->spe_enabled)) { \
7001 GEN_EXCP_NO_AP(ctx); \
7002 return; \
7003 } \
1c97856d
AJ		 7004 t0 = tcg_temp_new_i32(); \
7005 t1 = tcg_temp_new_i32(); \
7006 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7007 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7008 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7009 tcg_temp_free_i32(t0); \
7010 tcg_temp_free_i32(t1); \
7011}
7012#define GEN_SPEFPUOP_COMP_64(name) \
7013static always_inline void gen_##name (DisasContext *ctx) \
7014{ \
7015 if (unlikely(!ctx->spe_enabled)) { \
7016 GEN_EXCP_NO_AP(ctx); \
7017 return; \
7018 } \
7019 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7020 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7021}
7022#else
7023#define GEN_SPEFPUOP_CONV_32_32(name) \
7024static always_inline void gen_##name (DisasContext *ctx) \
7025{ \
7026 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7027}
1c97856d
AJ		 7028#define GEN_SPEFPUOP_CONV_32_64(name) \
7029static always_inline void gen_##name (DisasContext *ctx) \
7030{ \
7031 TCGv_i64 t0 = tcg_temp_new_i64(); \
7032 gen_load_gpr64(t0, rB(ctx->opcode)); \
7033 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7034 tcg_temp_free_i64(t0); \
7035}
7036#define GEN_SPEFPUOP_CONV_64_32(name) \
7037static always_inline void gen_##name (DisasContext *ctx) \
7038{ \
7039 TCGv_i64 t0 = tcg_temp_new_i64(); \
7040 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7041 gen_store_gpr64(rD(ctx->opcode), t0); \
7042 tcg_temp_free_i64(t0); \
7043}
7044#define GEN_SPEFPUOP_CONV_64_64(name) \
7045static always_inline void gen_##name (DisasContext *ctx) \
7046{ \
7047 TCGv_i64 t0 = tcg_temp_new_i64(); \
7048 gen_load_gpr64(t0, rB(ctx->opcode)); \
7049 gen_helper_##name(t0, t0); \
7050 gen_store_gpr64(rD(ctx->opcode), t0); \
7051 tcg_temp_free_i64(t0); \
7052}
7053#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7054static always_inline void gen_##name (DisasContext *ctx) \
7055{ \
7056 if (unlikely(!ctx->spe_enabled)) { \
7057 GEN_EXCP_NO_AP(ctx); \
7058 return; \
7059 } \
7060 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7061 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7062}
7063#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7064static always_inline void gen_##name (DisasContext *ctx) \
7065{ \
7066 TCGv_i64 t0, t1; \
7067 if (unlikely(!ctx->spe_enabled)) { \
7068 GEN_EXCP_NO_AP(ctx); \
7069 return; \
7070 } \
7071 t0 = tcg_temp_new_i64(); \
7072 t1 = tcg_temp_new_i64(); \
7073 gen_load_gpr64(t0, rA(ctx->opcode)); \
7074 gen_load_gpr64(t1, rB(ctx->opcode)); \
7075 gen_helper_##name(t0, t0, t1); \
7076 gen_store_gpr64(rD(ctx->opcode), t0); \
7077 tcg_temp_free_i64(t0); \
7078 tcg_temp_free_i64(t1); \
7079}
7080#define GEN_SPEFPUOP_COMP_32(name) \
7081static always_inline void gen_##name (DisasContext *ctx) \
7082{ \
7083 if (unlikely(!ctx->spe_enabled)) { \
7084 GEN_EXCP_NO_AP(ctx); \
7085 return; \
7086 } \
7087 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7088 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7089}
7090#define GEN_SPEFPUOP_COMP_64(name) \
7091static always_inline void gen_##name (DisasContext *ctx) \
7092{ \
7093 TCGv_i64 t0, t1; \
7094 if (unlikely(!ctx->spe_enabled)) { \
7095 GEN_EXCP_NO_AP(ctx); \
7096 return; \
7097 } \
7098 t0 = tcg_temp_new_i64(); \
7099 t1 = tcg_temp_new_i64(); \
7100 gen_load_gpr64(t0, rA(ctx->opcode)); \
7101 gen_load_gpr64(t1, rB(ctx->opcode)); \
7102 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7103 tcg_temp_free_i64(t0); \
7104 tcg_temp_free_i64(t1); \
7105}
7106#endif
57951c27 7107
0487d6a8
JM		 7108/* Single precision floating-point vectors operations */
7109/* Arithmetic */
1c97856d
AJ		 7110GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7111GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7112GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7113GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7114static always_inline void gen_evfsabs (DisasContext *ctx)
7115{
7116 if (unlikely(!ctx->spe_enabled)) {
7117 GEN_EXCP_NO_AP(ctx);
7118 return;
7119 }
7120#if defined(TARGET_PPC64)
7121 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7122#else
7123 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7124 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7125#endif
7126}
7127static always_inline void gen_evfsnabs (DisasContext *ctx)
7128{
7129 if (unlikely(!ctx->spe_enabled)) {
7130 GEN_EXCP_NO_AP(ctx);
7131 return;
7132 }
7133#if defined(TARGET_PPC64)
7134 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7135#else
7136 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7137 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7138#endif
7139}
7140static always_inline void gen_evfsneg (DisasContext *ctx)
7141{
7142 if (unlikely(!ctx->spe_enabled)) {
7143 GEN_EXCP_NO_AP(ctx);
7144 return;
7145 }
7146#if defined(TARGET_PPC64)
7147 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7148#else
7149 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7150 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7151#endif
7152}
7153
0487d6a8 7154/* Conversion */
1c97856d
AJ		 7155GEN_SPEFPUOP_CONV_64_64(evfscfui);
7156GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7157GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7158GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7159GEN_SPEFPUOP_CONV_64_64(evfsctui);
7160GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7161GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7162GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7163GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7164GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7165
0487d6a8 7166/* Comparison */
1c97856d
AJ		 7167GEN_SPEFPUOP_COMP_64(evfscmpgt);
7168GEN_SPEFPUOP_COMP_64(evfscmplt);
7169GEN_SPEFPUOP_COMP_64(evfscmpeq);
7170GEN_SPEFPUOP_COMP_64(evfststgt);
7171GEN_SPEFPUOP_COMP_64(evfststlt);
7172GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7173
7174/* Opcodes definitions */
7175GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7176GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7177GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7178GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7179GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7180GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7181GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7182GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7183GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7184GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7185GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7186GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7187GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7188GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7189
7190/* Single precision floating-point operations */
7191/* Arithmetic */
1c97856d
AJ		 7192GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7193GEN_SPEFPUOP_ARITH2_32_32(efssub);
7194GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7195GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7196static always_inline void gen_efsabs (DisasContext *ctx)
7197{
7198 if (unlikely(!ctx->spe_enabled)) {
7199 GEN_EXCP_NO_AP(ctx);
7200 return;
7201 }
7202 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7203}
7204static always_inline void gen_efsnabs (DisasContext *ctx)
7205{
7206 if (unlikely(!ctx->spe_enabled)) {
7207 GEN_EXCP_NO_AP(ctx);
7208 return;
7209 }
7210 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7211}
7212static always_inline void gen_efsneg (DisasContext *ctx)
7213{
7214 if (unlikely(!ctx->spe_enabled)) {
7215 GEN_EXCP_NO_AP(ctx);
7216 return;
7217 }
7218 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7219}
7220
0487d6a8 7221/* Conversion */
1c97856d
AJ		 7222GEN_SPEFPUOP_CONV_32_32(efscfui);
7223GEN_SPEFPUOP_CONV_32_32(efscfsi);
7224GEN_SPEFPUOP_CONV_32_32(efscfuf);
7225GEN_SPEFPUOP_CONV_32_32(efscfsf);
7226GEN_SPEFPUOP_CONV_32_32(efsctui);
7227GEN_SPEFPUOP_CONV_32_32(efsctsi);
7228GEN_SPEFPUOP_CONV_32_32(efsctuf);
7229GEN_SPEFPUOP_CONV_32_32(efsctsf);
7230GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7231GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7232GEN_SPEFPUOP_CONV_32_64(efscfd);
7233
0487d6a8 7234/* Comparison */
1c97856d
AJ		 7235GEN_SPEFPUOP_COMP_32(efscmpgt);
7236GEN_SPEFPUOP_COMP_32(efscmplt);
7237GEN_SPEFPUOP_COMP_32(efscmpeq);
7238GEN_SPEFPUOP_COMP_32(efststgt);
7239GEN_SPEFPUOP_COMP_32(efststlt);
7240GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7241
7242/* Opcodes definitions */
05332d70 7243GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7244GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7245GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7246GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7247GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7248GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7249GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7250GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7251GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7252GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7253GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7254GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7255GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7256GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7257
7258/* Double precision floating-point operations */
7259/* Arithmetic */
1c97856d
AJ		 7260GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7261GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7262GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7263GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7264static always_inline void gen_efdabs (DisasContext *ctx)
7265{
7266 if (unlikely(!ctx->spe_enabled)) {
7267 GEN_EXCP_NO_AP(ctx);
7268 return;
7269 }
7270#if defined(TARGET_PPC64)
7271 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7272#else
7273 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7274#endif
7275}
7276static always_inline void gen_efdnabs (DisasContext *ctx)
7277{
7278 if (unlikely(!ctx->spe_enabled)) {
7279 GEN_EXCP_NO_AP(ctx);
7280 return;
7281 }
7282#if defined(TARGET_PPC64)
7283 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7284#else
7285 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7286#endif
7287}
7288static always_inline void gen_efdneg (DisasContext *ctx)
7289{
7290 if (unlikely(!ctx->spe_enabled)) {
7291 GEN_EXCP_NO_AP(ctx);
7292 return;
7293 }
7294#if defined(TARGET_PPC64)
7295 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7296#else
7297 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7298#endif
7299}
7300
0487d6a8 7301/* Conversion */
1c97856d
AJ		 7302GEN_SPEFPUOP_CONV_64_32(efdcfui);
7303GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7304GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7305GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7306GEN_SPEFPUOP_CONV_32_64(efdctui);
7307GEN_SPEFPUOP_CONV_32_64(efdctsi);
7308GEN_SPEFPUOP_CONV_32_64(efdctuf);
7309GEN_SPEFPUOP_CONV_32_64(efdctsf);
7310GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7311GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7312GEN_SPEFPUOP_CONV_64_32(efdcfs);
7313GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7314GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7315GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7316GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 7317
0487d6a8 7318/* Comparison */
1c97856d
AJ		 7319GEN_SPEFPUOP_COMP_64(efdcmpgt);
7320GEN_SPEFPUOP_COMP_64(efdcmplt);
7321GEN_SPEFPUOP_COMP_64(efdcmpeq);
7322GEN_SPEFPUOP_COMP_64(efdtstgt);
7323GEN_SPEFPUOP_COMP_64(efdtstlt);
7324GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 7325
7326/* Opcodes definitions */
7327GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7328GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7329GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7330GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7331GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7332GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7333GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7334GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7335GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7336GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7337GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7338GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7339GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7340GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7341GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7342GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 7343
79aceca5
FB		 7344/* End opcode list */
7345GEN_OPCODE_MARK(end);
7346
3fc6c082 7347#include "translate_init.c"
0411a972 7348#include "helper_regs.h"
79aceca5 7349
9a64fbe4 7350/*****************************************************************************/
3fc6c082 7351/* Misc PowerPC helpers */
36081602
JM		 7352void cpu_dump_state (CPUState *env, FILE *f,
7353 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7354 int flags)
79aceca5 7355{
3fc6c082
FB		 7356#define RGPL 4
7357#define RFPL 4
3fc6c082 7358
79aceca5
FB		 7359 int i;
7360
077fc206 7361 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 7362 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 7363 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7364 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 7365#if !defined(NO_TIMER_DUMP)
077fc206 7366 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 7367#if !defined(CONFIG_USER_ONLY)
7368 "DECR %08x"
7369#endif
7370 "\n",
077fc206 7371 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 7372#if !defined(CONFIG_USER_ONLY)
7373 , cpu_ppc_load_decr(env)
7374#endif
7375 );
077fc206 7376#endif
76a66253 7377 for (i = 0; i < 32; i++) {
3fc6c082
FB		 7378 if ((i & (RGPL - 1)) == 0)
7379 cpu_fprintf(f, "GPR%02d", i);
6b542af7 7380 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 7381 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 7382 cpu_fprintf(f, "\n");
76a66253 7383 }
3fc6c082 7384 cpu_fprintf(f, "CR ");
76a66253 7385 for (i = 0; i < 8; i++)
7fe48483
FB		 7386 cpu_fprintf(f, "%01x", env->crf[i]);
7387 cpu_fprintf(f, " [");
76a66253
JM		 7388 for (i = 0; i < 8; i++) {
7389 char a = '-';
7390 if (env->crf[i] & 0x08)
7391 a = 'L';
7392 else if (env->crf[i] & 0x04)
7393 a = 'G';
7394 else if (env->crf[i] & 0x02)
7395 a = 'E';
7fe48483 7396 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 7397 }
6b542af7 7398 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 7399 for (i = 0; i < 32; i++) {
7400 if ((i & (RFPL - 1)) == 0)
7401 cpu_fprintf(f, "FPR%02d", i);
26a76461 7402 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 7403 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 7404 cpu_fprintf(f, "\n");
79aceca5 7405 }
f2e63a42 7406#if !defined(CONFIG_USER_ONLY)
6b542af7 7407 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 7408 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 7409#endif
79aceca5 7410
3fc6c082
FB		 7411#undef RGPL
7412#undef RFPL
79aceca5
FB		 7413}
7414
76a66253
JM		 7415void cpu_dump_statistics (CPUState *env, FILE*f,
7416 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7417 int flags)
7418{
7419#if defined(DO_PPC_STATISTICS)
7420 opc_handler_t **t1, **t2, **t3, *handler;
7421 int op1, op2, op3;
7422
7423 t1 = env->opcodes;
7424 for (op1 = 0; op1 < 64; op1++) {
7425 handler = t1[op1];
7426 if (is_indirect_opcode(handler)) {
7427 t2 = ind_table(handler);
7428 for (op2 = 0; op2 < 32; op2++) {
7429 handler = t2[op2];
7430 if (is_indirect_opcode(handler)) {
7431 t3 = ind_table(handler);
7432 for (op3 = 0; op3 < 32; op3++) {
7433 handler = t3[op3];
7434 if (handler->count == 0)
7435 continue;
7436 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7437 "%016llx %lld\n",
7438 op1, op2, op3, op1, (op3 << 5) | op2,
7439 handler->oname,
7440 handler->count, handler->count);
7441 }
7442 } else {
7443 if (handler->count == 0)
7444 continue;
7445 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7446 "%016llx %lld\n",
7447 op1, op2, op1, op2, handler->oname,
7448 handler->count, handler->count);
7449 }
7450 }
7451 } else {
7452 if (handler->count == 0)
7453 continue;
7454 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7455 op1, op1, handler->oname,
7456 handler->count, handler->count);
7457 }
7458 }
7459#endif
7460}
7461
9a64fbe4 7462/*****************************************************************************/
2cfc5f17
TS		 7463static always_inline void gen_intermediate_code_internal (CPUState *env,
7464 TranslationBlock *tb,
7465 int search_pc)
79aceca5 7466{
9fddaa0c 7467 DisasContext ctx, *ctxp = &ctx;
79aceca5 7468 opc_handler_t **table, *handler;
0fa85d43 7469 target_ulong pc_start;
79aceca5 7470 uint16_t *gen_opc_end;
056401ea 7471 int supervisor, little_endian;
a1d1bb31 7472 CPUBreakpoint *bp;
79aceca5 7473 int j, lj = -1;
2e70f6ef
PB		 7474 int num_insns;
7475 int max_insns;
79aceca5
FB		 7476
7477 pc_start = tb->pc;
79aceca5 7478 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 7479#if defined(OPTIMIZE_FPRF_UPDATE)
7480 gen_fprf_ptr = gen_fprf_buf;
7481#endif
046d6672 7482 ctx.nip = pc_start;
79aceca5 7483 ctx.tb = tb;
e1833e1f 7484 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 7485 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 7486 supervisor = env->mmu_idx;
7487#if !defined(CONFIG_USER_ONLY)
2857068e 7488 ctx.supervisor = supervisor;
d9bce9d9 7489#endif
056401ea 7490 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 7491#if defined(TARGET_PPC64)
7492 ctx.sf_mode = msr_sf;
056401ea 7493 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 7494#else
056401ea 7495 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 7496#endif
3cc62370 7497 ctx.fpu_enabled = msr_fp;
a9d9eb8f 7498 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 7499 ctx.spe_enabled = msr_spe;
7500 else
7501 ctx.spe_enabled = 0;
a9d9eb8f
JM		 7502 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7503 ctx.altivec_enabled = msr_vr;
7504 else
7505 ctx.altivec_enabled = 0;
d26bfc9a 7506 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 7507 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 7508 else
8cbcb4fa 7509 ctx.singlestep_enabled = 0;
d26bfc9a 7510 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 7511 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7512 if (unlikely(env->singlestep_enabled))
7513 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 7514#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 7515 /* Single step trace mode */
7516 msr_se = 1;
7517#endif
2e70f6ef
PB		 7518 num_insns = 0;
7519 max_insns = tb->cflags & CF_COUNT_MASK;
7520 if (max_insns == 0)
7521 max_insns = CF_COUNT_MASK;
7522
7523 gen_icount_start();
9a64fbe4 7524 /* Set env in case of segfault during code fetch */
e1833e1f 7525 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 7526 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7527 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 7528 if (bp->pc == ctx.nip) {
5fafdf24 7529 gen_update_nip(&ctx, ctx.nip);
64adab3f 7530 gen_helper_raise_debug();
ea4e754f
FB		 7531 break;
7532 }
7533 }
7534 }
76a66253 7535 if (unlikely(search_pc)) {
79aceca5
FB		 7536 j = gen_opc_ptr - gen_opc_buf;
7537 if (lj < j) {
7538 lj++;
7539 while (lj < j)
7540 gen_opc_instr_start[lj++] = 0;
046d6672 7541 gen_opc_pc[lj] = ctx.nip;
79aceca5 7542 gen_opc_instr_start[lj] = 1;
2e70f6ef 7543 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 7544 }
7545 }
9fddaa0c
FB		 7546#if defined PPC_DEBUG_DISAS
7547 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 7548 fprintf(logfile, "----------------\n");
1b9eb036 7549 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 7550 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 7551 }
7552#endif
2e70f6ef
PB		 7553 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7554 gen_io_start();
056401ea
JM		 7555 if (unlikely(little_endian)) {
7556 ctx.opcode = bswap32(ldl_code(ctx.nip));
7557 } else {
7558 ctx.opcode = ldl_code(ctx.nip);
111bfab3 7559 }
9fddaa0c
FB		 7560#if defined PPC_DEBUG_DISAS
7561 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 7562 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 7563 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 7564 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 7565 }
7566#endif
046d6672 7567 ctx.nip += 4;
3fc6c082 7568 table = env->opcodes;
2e70f6ef 7569 num_insns++;
79aceca5
FB		 7570 handler = table[opc1(ctx.opcode)];
7571 if (is_indirect_opcode(handler)) {
7572 table = ind_table(handler);
7573 handler = table[opc2(ctx.opcode)];
7574 if (is_indirect_opcode(handler)) {
7575 table = ind_table(handler);
7576 handler = table[opc3(ctx.opcode)];
7577 }
7578 }
7579 /* Is opcode *REALLY* valid ? */
76a66253 7580 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7581 if (loglevel != 0) {
76a66253 7582 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 7583 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 7584 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7585 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7586 } else {
7587 printf("invalid/unsupported opcode: "
6b542af7 7588 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 7589 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7590 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7591 }
76a66253
JM		 7592 } else {
7593 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7594 if (loglevel != 0) {
79aceca5 7595 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 7596 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 7597 ctx.opcode & handler->inval, opc1(ctx.opcode),
7598 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7599 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7600 } else {
7601 printf("invalid bits: %08x for opcode: "
6b542af7 7602 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 7603 ctx.opcode & handler->inval, opc1(ctx.opcode),
7604 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7605 ctx.opcode, ctx.nip - 4);
76a66253 7606 }
e1833e1f 7607 GEN_EXCP_INVAL(ctxp);
4b3686fa 7608 break;
79aceca5 7609 }
79aceca5 7610 }
4b3686fa 7611 (*(handler->handler))(&ctx);
76a66253
JM		 7612#if defined(DO_PPC_STATISTICS)
7613 handler->count++;
7614#endif
9a64fbe4 7615 /* Check trace mode exceptions */
8cbcb4fa
AJ		 7616 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7617 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7618 ctx.exception != POWERPC_SYSCALL &&
7619 ctx.exception != POWERPC_EXCP_TRAP &&
7620 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 7621 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 7622 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 7623 (env->singlestep_enabled) ||
7624 num_insns >= max_insns)) {
d26bfc9a
JM		 7625 /* if we reach a page boundary or are single stepping, stop
7626 * generation
7627 */
8dd4983c 7628 break;
76a66253 7629 }
3fc6c082
FB		 7630#if defined (DO_SINGLE_STEP)
7631 break;
7632#endif
7633 }
2e70f6ef
PB		 7634 if (tb->cflags & CF_LAST_IO)
7635 gen_io_end();
e1833e1f 7636 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7637 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7638 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 7639 if (unlikely(env->singlestep_enabled)) {
7640 gen_update_nip(&ctx, ctx.nip);
64adab3f 7641 gen_helper_raise_debug();
8cbcb4fa 7642 }
76a66253 7643 /* Generate the return instruction */
57fec1fe 7644 tcg_gen_exit_tb(0);
9a64fbe4 7645 }
2e70f6ef 7646 gen_icount_end(tb, num_insns);
79aceca5 7647 *gen_opc_ptr = INDEX_op_end;
76a66253 7648 if (unlikely(search_pc)) {
9a64fbe4
FB		 7649 j = gen_opc_ptr - gen_opc_buf;
7650 lj++;
7651 while (lj <= j)
7652 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7653 } else {
046d6672 7654 tb->size = ctx.nip - pc_start;
2e70f6ef 7655 tb->icount = num_insns;
9a64fbe4 7656 }
d9bce9d9 7657#if defined(DEBUG_DISAS)
9fddaa0c 7658 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7659 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7660 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7661 }
7662 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7663 int flags;
237c0af0 7664 flags = env->bfd_mach;
056401ea 7665 flags |= little_endian << 16;
0fa85d43 7666 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7667 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7668 fprintf(logfile, "\n");
9fddaa0c 7669 }
79aceca5 7670#endif
79aceca5
FB		 7671}
7672
2cfc5f17 7673void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 7674{
2cfc5f17 7675 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 7676}
7677
2cfc5f17 7678void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7679{
2cfc5f17 7680 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7681}
d2856f1a
AJ		 7682
7683void gen_pc_load(CPUState *env, TranslationBlock *tb,
7684 unsigned long searched_pc, int pc_pos, void *puc)
7685{
d2856f1a 7686 env->nip = gen_opc_pc[pc_pos];
d2856f1a 7687}
Qemu copy for testing