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79aceca5
FB		 1/*
2 * PPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5
FB		 28#include "disas.h"
29
30//#define DO_SINGLE_STEP
31//#define DO_STEP_FLUSH
9a64fbe4 32//#define DEBUG_DISAS
9fddaa0c 33//#define PPC_DEBUG_DISAS
79aceca5
FB		 34
35enum {
36#define DEF(s, n, copy_size) INDEX_op_ ## s,
37#include "opc.h"
38#undef DEF
39 NB_OPS,
40};
41
42static uint16_t *gen_opc_ptr;
43static uint32_t *gen_opparam_ptr;
44
45#include "gen-op.h"
28b6751f 46
28b6751f 47#define GEN8(func, NAME) \
9a64fbe4
FB		 48static GenOpFunc *NAME ## _table [8] = { \
49NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
50NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
51}; \
52static inline void func(int n) \
53{ \
54 NAME ## _table[n](); \
55}
56
57#define GEN16(func, NAME) \
58static GenOpFunc *NAME ## _table [16] = { \
59NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
60NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
61NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
62NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
63}; \
64static inline void func(int n) \
65{ \
66 NAME ## _table[n](); \
28b6751f
FB		 67}
68
69#define GEN32(func, NAME) \
9a64fbe4
FB		 70static GenOpFunc *NAME ## _table [32] = { \
71NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
72NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
73NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
74NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
75NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
76NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
77NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
78NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
79}; \
80static inline void func(int n) \
81{ \
82 NAME ## _table[n](); \
83}
84
85/* Condition register moves */
86GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
87GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
88GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
89GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
28b6751f 90
fb0eaffc
FB		 91/* Floating point condition and status register moves */
92GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
93GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
94GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
95static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
96 &gen_op_store_T0_fpscri_fpscr0,
97 &gen_op_store_T0_fpscri_fpscr1,
98 &gen_op_store_T0_fpscri_fpscr2,
99 &gen_op_store_T0_fpscri_fpscr3,
100 &gen_op_store_T0_fpscri_fpscr4,
101 &gen_op_store_T0_fpscri_fpscr5,
102 &gen_op_store_T0_fpscri_fpscr6,
103 &gen_op_store_T0_fpscri_fpscr7,
104};
105static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
106{
107 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
108}
109
9a64fbe4
FB		 110/* Segment register moves */
111GEN16(gen_op_load_sr, gen_op_load_sr);
112GEN16(gen_op_store_sr, gen_op_store_sr);
28b6751f 113
9a64fbe4
FB		 114/* General purpose registers moves */
115GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
116GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
117GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
118
119GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
120GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
121GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
28b6751f 122
fb0eaffc
FB		 123/* floating point registers moves */
124GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
125GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
126GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
127GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
128GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
129GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
79aceca5
FB		 130
131static uint8_t spr_access[1024 / 2];
132
133/* internal defines */
134typedef struct DisasContext {
135 struct TranslationBlock *tb;
046d6672 136 uint32_t nip;
79aceca5 137 uint32_t opcode;
9a64fbe4 138 uint32_t exception;
9a64fbe4
FB		 139 /* Execution mode */
140#if !defined(CONFIG_USER_ONLY)
79aceca5 141 int supervisor;
9a64fbe4
FB		 142#endif
143 /* Routine used to access memory */
144 int mem_idx;
79aceca5
FB		 145} DisasContext;
146
147typedef struct opc_handler_t {
148 /* invalid bits */
149 uint32_t inval;
9a64fbe4
FB		 150 /* instruction type */
151 uint32_t type;
79aceca5
FB		 152 /* handler */
153 void (*handler)(DisasContext *ctx);
154} opc_handler_t;
155
9fddaa0c 156#define RET_EXCP(ctx, excp, error) \
79aceca5 157do { \
9fddaa0c
FB		 158 if ((ctx)->exception == EXCP_NONE) { \
159 gen_op_update_nip((ctx)->nip); \
160 } \
161 gen_op_raise_exception_err((excp), (error)); \
162 ctx->exception = (excp); \
79aceca5
FB		 163} while (0)
164
9fddaa0c
FB		 165#define RET_INVAL(ctx) \
166RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
167
168#define RET_PRIVOPC(ctx) \
169RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
9a64fbe4 170
9fddaa0c
FB		 171#define RET_PRIVREG(ctx) \
172RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
9a64fbe4 173
9fddaa0c
FB		 174#define RET_MTMSR(ctx) \
175RET_EXCP((ctx), EXCP_MTMSR, 0)
79aceca5
FB		 176
177#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
178static void gen_##name (DisasContext *ctx); \
179GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
180static void gen_##name (DisasContext *ctx)
181
79aceca5
FB		 182typedef struct opcode_t {
183 unsigned char opc1, opc2, opc3;
79aceca5
FB		 184 opc_handler_t handler;
185} opcode_t;
186
79aceca5
FB		 187/*** Instruction decoding ***/
188#define EXTRACT_HELPER(name, shift, nb) \
189static inline uint32_t name (uint32_t opcode) \
190{ \
191 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
192}
193
194#define EXTRACT_SHELPER(name, shift, nb) \
195static inline int32_t name (uint32_t opcode) \
196{ \
197 return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \
198}
199
200/* Opcode part 1 */
201EXTRACT_HELPER(opc1, 26, 6);
202/* Opcode part 2 */
203EXTRACT_HELPER(opc2, 1, 5);
204/* Opcode part 3 */
205EXTRACT_HELPER(opc3, 6, 5);
206/* Update Cr0 flags */
207EXTRACT_HELPER(Rc, 0, 1);
208/* Destination */
209EXTRACT_HELPER(rD, 21, 5);
210/* Source */
211EXTRACT_HELPER(rS, 21, 5);
212/* First operand */
213EXTRACT_HELPER(rA, 16, 5);
214/* Second operand */
215EXTRACT_HELPER(rB, 11, 5);
216/* Third operand */
217EXTRACT_HELPER(rC, 6, 5);
218/*** Get CRn ***/
219EXTRACT_HELPER(crfD, 23, 3);
220EXTRACT_HELPER(crfS, 18, 3);
221EXTRACT_HELPER(crbD, 21, 5);
222EXTRACT_HELPER(crbA, 16, 5);
223EXTRACT_HELPER(crbB, 11, 5);
224/* SPR / TBL */
225EXTRACT_HELPER(SPR, 11, 10);
226/*** Get constants ***/
227EXTRACT_HELPER(IMM, 12, 8);
228/* 16 bits signed immediate value */
229EXTRACT_SHELPER(SIMM, 0, 16);
230/* 16 bits unsigned immediate value */
231EXTRACT_HELPER(UIMM, 0, 16);
232/* Bit count */
233EXTRACT_HELPER(NB, 11, 5);
234/* Shift count */
235EXTRACT_HELPER(SH, 11, 5);
236/* Mask start */
237EXTRACT_HELPER(MB, 6, 5);
238/* Mask end */
239EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 240/* Trap operand */
241EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 242
243EXTRACT_HELPER(CRM, 12, 8);
244EXTRACT_HELPER(FM, 17, 8);
245EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 246EXTRACT_HELPER(FPIMM, 20, 4);
247
79aceca5
FB		 248/*** Jump target decoding ***/
249/* Displacement */
250EXTRACT_SHELPER(d, 0, 16);
251/* Immediate address */
252static inline uint32_t LI (uint32_t opcode)
253{
254 return (opcode >> 0) & 0x03FFFFFC;
255}
256
257static inline uint32_t BD (uint32_t opcode)
258{
259 return (opcode >> 0) & 0xFFFC;
260}
261
262EXTRACT_HELPER(BO, 21, 5);
263EXTRACT_HELPER(BI, 16, 5);
264/* Absolute/relative address */
265EXTRACT_HELPER(AA, 1, 1);
266/* Link */
267EXTRACT_HELPER(LK, 0, 1);
268
269/* Create a mask between <start> and <end> bits */
270static inline uint32_t MASK (uint32_t start, uint32_t end)
271{
272 uint32_t ret;
273
274 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
275 if (start > end)
276 return ~ret;
277
278 return ret;
279}
280
281#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
1ef59d0a 282__attribute__ ((section(".opcodes"), unused, aligned (8) )) \
79aceca5
FB		 283static opcode_t opc_##name = { \
284 .opc1 = op1, \
285 .opc2 = op2, \
286 .opc3 = op3, \
79aceca5
FB		 287 .handler = { \
288 .inval = invl, \
9a64fbe4 289 .type = _typ, \
79aceca5
FB		 290 .handler = &gen_##name, \
291 }, \
292}
293
294#define GEN_OPCODE_MARK(name) \
1ef59d0a 295__attribute__ ((section(".opcodes"), unused, aligned (8) )) \
79aceca5
FB		 296static opcode_t opc_##name = { \
297 .opc1 = 0xFF, \
298 .opc2 = 0xFF, \
299 .opc3 = 0xFF, \
79aceca5
FB		 300 .handler = { \
301 .inval = 0x00000000, \
9a64fbe4 302 .type = 0x00, \
79aceca5
FB		 303 .handler = NULL, \
304 }, \
305}
306
307/* Start opcode list */
308GEN_OPCODE_MARK(start);
309
310/* Invalid instruction */
9a64fbe4
FB		 311GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
312{
9fddaa0c 313 RET_INVAL(ctx);
9a64fbe4
FB		 314}
315
316/* Special opcode to stop emulation */
317GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
79aceca5 318{
9fddaa0c 319 RET_EXCP(ctx, EXCP_HLT, 0);
9a64fbe4
FB		 320}
321
322/* Special opcode to call open-firmware */
323GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
324{
9fddaa0c 325 RET_EXCP(ctx, EXCP_OFCALL, 0);
9a64fbe4
FB		 326}
327
328/* Special opcode to call RTAS */
329GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
330{
331 printf("RTAS entry point !\n");
9fddaa0c 332 RET_EXCP(ctx, EXCP_RTASCALL, 0);
79aceca5
FB		 333}
334
335static opc_handler_t invalid_handler = {
336 .inval = 0xFFFFFFFF,
9a64fbe4 337 .type = PPC_NONE,
79aceca5
FB		 338 .handler = gen_invalid,
339};
340
341/*** Integer arithmetic ***/
342#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
343GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
344{ \
345 gen_op_load_gpr_T0(rA(ctx->opcode)); \
346 gen_op_load_gpr_T1(rB(ctx->opcode)); \
347 gen_op_##name(); \
348 if (Rc(ctx->opcode) != 0) \
349 gen_op_set_Rc0(); \
350 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 351}
352
353#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
354GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
355{ \
356 gen_op_load_gpr_T0(rA(ctx->opcode)); \
357 gen_op_load_gpr_T1(rB(ctx->opcode)); \
358 gen_op_##name(); \
359 if (Rc(ctx->opcode) != 0) \
360 gen_op_set_Rc0_ov(); \
361 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 362}
363
364#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
365GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
366{ \
367 gen_op_load_gpr_T0(rA(ctx->opcode)); \
368 gen_op_##name(); \
369 if (Rc(ctx->opcode) != 0) \
370 gen_op_set_Rc0(); \
371 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 372}
373#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
374GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
375{ \
376 gen_op_load_gpr_T0(rA(ctx->opcode)); \
377 gen_op_##name(); \
378 if (Rc(ctx->opcode) != 0) \
379 gen_op_set_Rc0_ov(); \
380 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 381}
382
383/* Two operands arithmetic functions */
384#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
385__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
386__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
387
388/* Two operands arithmetic functions with no overflow allowed */
389#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
390__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
391
392/* One operand arithmetic functions */
393#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
394__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
395__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
396
397/* add add. addo addo. */
398GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
399/* addc addc. addco addco. */
400GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
401/* adde adde. addeo addeo. */
402GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
403/* addme addme. addmeo addmeo. */
404GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
405/* addze addze. addzeo addzeo. */
406GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
407/* divw divw. divwo divwo. */
408GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
409/* divwu divwu. divwuo divwuo. */
410GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
411/* mulhw mulhw. */
412GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
413/* mulhwu mulhwu. */
414GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
415/* mullw mullw. mullwo mullwo. */
416GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
417/* neg neg. nego nego. */
418GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
419/* subf subf. subfo subfo. */
420GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
421/* subfc subfc. subfco subfco. */
422GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
423/* subfe subfe. subfeo subfeo. */
424GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
425/* subfme subfme. subfmeo subfmeo. */
426GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
427/* subfze subfze. subfzeo subfzeo. */
428GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
429/* addi */
430GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
431{
432 int32_t simm = SIMM(ctx->opcode);
433
434 if (rA(ctx->opcode) == 0) {
435 gen_op_set_T0(simm);
436 } else {
437 gen_op_load_gpr_T0(rA(ctx->opcode));
438 gen_op_addi(simm);
439 }
440 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 441}
442/* addic */
443GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
444{
445 gen_op_load_gpr_T0(rA(ctx->opcode));
446 gen_op_addic(SIMM(ctx->opcode));
447 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 448}
449/* addic. */
450GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
451{
452 gen_op_load_gpr_T0(rA(ctx->opcode));
453 gen_op_addic(SIMM(ctx->opcode));
454 gen_op_set_Rc0();
455 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 456}
457/* addis */
458GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
459{
460 int32_t simm = SIMM(ctx->opcode);
461
462 if (rA(ctx->opcode) == 0) {
463 gen_op_set_T0(simm << 16);
464 } else {
465 gen_op_load_gpr_T0(rA(ctx->opcode));
466 gen_op_addi(simm << 16);
467 }
468 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 469}
470/* mulli */
471GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
472{
473 gen_op_load_gpr_T0(rA(ctx->opcode));
474 gen_op_mulli(SIMM(ctx->opcode));
475 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 476}
477/* subfic */
478GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
479{
480 gen_op_load_gpr_T0(rA(ctx->opcode));
481 gen_op_subfic(SIMM(ctx->opcode));
482 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 483}
484
485/*** Integer comparison ***/
486#define GEN_CMP(name, opc) \
487GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
488{ \
489 gen_op_load_gpr_T0(rA(ctx->opcode)); \
490 gen_op_load_gpr_T1(rB(ctx->opcode)); \
491 gen_op_##name(); \
492 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5
FB		 493}
494
495/* cmp */
496GEN_CMP(cmp, 0x00);
497/* cmpi */
498GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
499{
500 gen_op_load_gpr_T0(rA(ctx->opcode));
501 gen_op_cmpi(SIMM(ctx->opcode));
502 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 503}
504/* cmpl */
505GEN_CMP(cmpl, 0x01);
506/* cmpli */
507GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
508{
509 gen_op_load_gpr_T0(rA(ctx->opcode));
510 gen_op_cmpli(UIMM(ctx->opcode));
511 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 512}
513
514/*** Integer logical ***/
515#define __GEN_LOGICAL2(name, opc2, opc3) \
516GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
517{ \
518 gen_op_load_gpr_T0(rS(ctx->opcode)); \
519 gen_op_load_gpr_T1(rB(ctx->opcode)); \
520 gen_op_##name(); \
521 if (Rc(ctx->opcode) != 0) \
522 gen_op_set_Rc0(); \
523 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 524}
525#define GEN_LOGICAL2(name, opc) \
526__GEN_LOGICAL2(name, 0x1C, opc)
527
528#define GEN_LOGICAL1(name, opc) \
529GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
530{ \
531 gen_op_load_gpr_T0(rS(ctx->opcode)); \
532 gen_op_##name(); \
533 if (Rc(ctx->opcode) != 0) \
534 gen_op_set_Rc0(); \
535 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 536}
537
538/* and & and. */
539GEN_LOGICAL2(and, 0x00);
540/* andc & andc. */
541GEN_LOGICAL2(andc, 0x01);
542/* andi. */
543GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
544{
545 gen_op_load_gpr_T0(rS(ctx->opcode));
546 gen_op_andi_(UIMM(ctx->opcode));
547 gen_op_set_Rc0();
548 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 549}
550/* andis. */
551GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
552{
553 gen_op_load_gpr_T0(rS(ctx->opcode));
554 gen_op_andi_(UIMM(ctx->opcode) << 16);
555 gen_op_set_Rc0();
556 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 557}
558
559/* cntlzw */
560GEN_LOGICAL1(cntlzw, 0x00);
561/* eqv & eqv. */
562GEN_LOGICAL2(eqv, 0x08);
563/* extsb & extsb. */
564GEN_LOGICAL1(extsb, 0x1D);
565/* extsh & extsh. */
566GEN_LOGICAL1(extsh, 0x1C);
567/* nand & nand. */
568GEN_LOGICAL2(nand, 0x0E);
569/* nor & nor. */
570GEN_LOGICAL2(nor, 0x03);
9a64fbe4 571
79aceca5 572/* or & or. */
9a64fbe4
FB		 573GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
574{
575 gen_op_load_gpr_T0(rS(ctx->opcode));
576 /* Optimisation for mr case */
577 if (rS(ctx->opcode) != rB(ctx->opcode)) {
578 gen_op_load_gpr_T1(rB(ctx->opcode));
579 gen_op_or();
580 }
581 if (Rc(ctx->opcode) != 0)
582 gen_op_set_Rc0();
583 gen_op_store_T0_gpr(rA(ctx->opcode));
584}
585
79aceca5
FB		 586/* orc & orc. */
587GEN_LOGICAL2(orc, 0x0C);
588/* xor & xor. */
9a64fbe4
FB		 589GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
590{
591 gen_op_load_gpr_T0(rS(ctx->opcode));
592 /* Optimisation for "set to zero" case */
593 if (rS(ctx->opcode) != rB(ctx->opcode)) {
594 gen_op_load_gpr_T1(rB(ctx->opcode));
595 gen_op_xor();
596 } else {
597 gen_op_set_T0(0);
598 }
599 if (Rc(ctx->opcode) != 0)
600 gen_op_set_Rc0();
601 gen_op_store_T0_gpr(rA(ctx->opcode));
602}
79aceca5
FB		 603/* ori */
604GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
605{
606 uint32_t uimm = UIMM(ctx->opcode);
607
9a64fbe4
FB		 608 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
609 /* NOP */
610 return;
79aceca5 611 }
79aceca5 612 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 613 if (uimm != 0)
79aceca5
FB		 614 gen_op_ori(uimm);
615 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 616}
617/* oris */
618GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
619{
620 uint32_t uimm = UIMM(ctx->opcode);
621
9a64fbe4
FB		 622 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
623 /* NOP */
624 return;
79aceca5 625 }
79aceca5 626 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 627 if (uimm != 0)
79aceca5
FB		 628 gen_op_ori(uimm << 16);
629 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 630}
631/* xori */
632GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
633{
9a64fbe4
FB		 634 uint32_t uimm = UIMM(ctx->opcode);
635
636 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
637 /* NOP */
638 return;
639 }
79aceca5 640 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 641 if (uimm != 0)
79aceca5
FB		 642 gen_op_xori(UIMM(ctx->opcode));
643 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 644}
645
646/* xoris */
647GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
648{
9a64fbe4
FB		 649 uint32_t uimm = UIMM(ctx->opcode);
650
651 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
652 /* NOP */
653 return;
654 }
79aceca5 655 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 656 if (uimm != 0)
79aceca5
FB		 657 gen_op_xori(UIMM(ctx->opcode) << 16);
658 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 659}
660
661/*** Integer rotate ***/
662/* rlwimi & rlwimi. */
663GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
664{
665 uint32_t mb, me;
666
667 mb = MB(ctx->opcode);
668 me = ME(ctx->opcode);
669 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 670 gen_op_load_gpr_T1(rA(ctx->opcode));
79aceca5
FB		 671 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
672 if (Rc(ctx->opcode) != 0)
673 gen_op_set_Rc0();
674 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 675}
676/* rlwinm & rlwinm. */
677GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
678{
679 uint32_t mb, me, sh;
680
681 sh = SH(ctx->opcode);
682 mb = MB(ctx->opcode);
683 me = ME(ctx->opcode);
684 gen_op_load_gpr_T0(rS(ctx->opcode));
79aceca5
FB		 685 if (mb == 0) {
686 if (me == 31) {
687 gen_op_rotlwi(sh);
688 goto store;
689 } else if (me == (31 - sh)) {
690 gen_op_slwi(sh);
691 goto store;
692 } else if (sh == 0) {
693 gen_op_andi_(MASK(0, me));
694 goto store;
695 }
696 } else if (me == 31) {
697 if (sh == (32 - mb)) {
698 gen_op_srwi(mb);
699 goto store;
700 } else if (sh == 0) {
701 gen_op_andi_(MASK(mb, 31));
702 goto store;
703 }
704 }
705 gen_op_rlwinm(sh, MASK(mb, me));
706store:
707 if (Rc(ctx->opcode) != 0)
708 gen_op_set_Rc0();
709 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 710}
711/* rlwnm & rlwnm. */
712GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
713{
714 uint32_t mb, me;
715
716 mb = MB(ctx->opcode);
717 me = ME(ctx->opcode);
718 gen_op_load_gpr_T0(rS(ctx->opcode));
719 gen_op_load_gpr_T1(rB(ctx->opcode));
720 if (mb == 0 && me == 31) {
721 gen_op_rotl();
722 } else
723 {
724 gen_op_rlwnm(MASK(mb, me));
725 }
726 if (Rc(ctx->opcode) != 0)
727 gen_op_set_Rc0();
728 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 729}
730
731/*** Integer shift ***/
732/* slw & slw. */
733__GEN_LOGICAL2(slw, 0x18, 0x00);
734/* sraw & sraw. */
735__GEN_LOGICAL2(sraw, 0x18, 0x18);
736/* srawi & srawi. */
737GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
738{
739 gen_op_load_gpr_T0(rS(ctx->opcode));
740 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
741 if (Rc(ctx->opcode) != 0)
742 gen_op_set_Rc0();
743 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 744}
745/* srw & srw. */
746__GEN_LOGICAL2(srw, 0x18, 0x10);
747
748/*** Floating-Point arithmetic ***/
9a64fbe4
FB		 749#define _GEN_FLOAT_ACB(name, op1, op2) \
750GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
751{ \
752 gen_op_reset_scrfx(); \
753 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
754 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
755 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
756 gen_op_f##name(); \
757 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
758 if (Rc(ctx->opcode)) \
759 gen_op_set_Rc1(); \
760}
761
762#define GEN_FLOAT_ACB(name, op2) \
763_GEN_FLOAT_ACB(name, 0x3F, op2); \
764_GEN_FLOAT_ACB(name##s, 0x3B, op2);
765
766#define _GEN_FLOAT_AB(name, op1, op2, inval) \
767GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
768{ \
769 gen_op_reset_scrfx(); \
770 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
771 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
772 gen_op_f##name(); \
773 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
774 if (Rc(ctx->opcode)) \
775 gen_op_set_Rc1(); \
776}
777#define GEN_FLOAT_AB(name, op2, inval) \
778_GEN_FLOAT_AB(name, 0x3F, op2, inval); \
779_GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
780
781#define _GEN_FLOAT_AC(name, op1, op2, inval) \
782GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
783{ \
784 gen_op_reset_scrfx(); \
785 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
786 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
787 gen_op_f##name(); \
788 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
789 if (Rc(ctx->opcode)) \
790 gen_op_set_Rc1(); \
791}
792#define GEN_FLOAT_AC(name, op2, inval) \
793_GEN_FLOAT_AC(name, 0x3F, op2, inval); \
794_GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
795
796#define GEN_FLOAT_B(name, op2, op3) \
797GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
798{ \
799 gen_op_reset_scrfx(); \
800 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
801 gen_op_f##name(); \
802 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
803 if (Rc(ctx->opcode)) \
804 gen_op_set_Rc1(); \
79aceca5
FB		 805}
806
9a64fbe4
FB		 807#define GEN_FLOAT_BS(name, op2) \
808GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
809{ \
810 gen_op_reset_scrfx(); \
811 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
812 gen_op_f##name(); \
813 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
814 if (Rc(ctx->opcode)) \
815 gen_op_set_Rc1(); \
79aceca5
FB		 816}
817
9a64fbe4
FB		 818/* fadd - fadds */
819GEN_FLOAT_AB(add, 0x15, 0x000007C0);
79aceca5 820/* fdiv */
9a64fbe4 821GEN_FLOAT_AB(div, 0x12, 0x000007C0);
79aceca5 822/* fmul */
9a64fbe4 823GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
79aceca5
FB		 824
825/* fres */
9a64fbe4 826GEN_FLOAT_BS(res, 0x18);
79aceca5
FB		 827
828/* frsqrte */
9a64fbe4 829GEN_FLOAT_BS(rsqrte, 0x1A);
79aceca5
FB		 830
831/* fsel */
9a64fbe4 832_GEN_FLOAT_ACB(sel, 0x3F, 0x17);
79aceca5 833/* fsub */
9a64fbe4 834GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
79aceca5
FB		 835/* Optional: */
836/* fsqrt */
9a64fbe4 837GEN_FLOAT_BS(sqrt, 0x16);
79aceca5 838
9a64fbe4 839GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
79aceca5 840{
9a64fbe4
FB		 841 gen_op_reset_scrfx();
842 gen_op_load_fpr_FT0(rB(ctx->opcode));
843 gen_op_fsqrts();
844 gen_op_store_FT0_fpr(rD(ctx->opcode));
845 if (Rc(ctx->opcode))
846 gen_op_set_Rc1();
79aceca5
FB		 847}
848
849/*** Floating-Point multiply-and-add ***/
850/* fmadd */
9a64fbe4 851GEN_FLOAT_ACB(madd, 0x1D);
79aceca5 852/* fmsub */
9a64fbe4 853GEN_FLOAT_ACB(msub, 0x1C);
79aceca5 854/* fnmadd */
9a64fbe4 855GEN_FLOAT_ACB(nmadd, 0x1F);
79aceca5 856/* fnmsub */
9a64fbe4 857GEN_FLOAT_ACB(nmsub, 0x1E);
79aceca5
FB		 858
859/*** Floating-Point round & convert ***/
860/* fctiw */
9a64fbe4 861GEN_FLOAT_B(ctiw, 0x0E, 0x00);
79aceca5 862/* fctiwz */
9a64fbe4 863GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
79aceca5 864/* frsp */
9a64fbe4 865GEN_FLOAT_B(rsp, 0x0C, 0x00);
79aceca5
FB		 866
867/*** Floating-Point compare ***/
868/* fcmpo */
869GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
870{
9a64fbe4
FB		 871 gen_op_reset_scrfx();
872 gen_op_load_fpr_FT0(rA(ctx->opcode));
873 gen_op_load_fpr_FT1(rB(ctx->opcode));
874 gen_op_fcmpo();
875 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 876}
877
878/* fcmpu */
879GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
880{
9a64fbe4
FB		 881 gen_op_reset_scrfx();
882 gen_op_load_fpr_FT0(rA(ctx->opcode));
883 gen_op_load_fpr_FT1(rB(ctx->opcode));
884 gen_op_fcmpu();
885 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 886}
887
9a64fbe4
FB		 888/*** Floating-point move ***/
889/* fabs */
890GEN_FLOAT_B(abs, 0x08, 0x08);
891
892/* fmr - fmr. */
893GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
894{
895 gen_op_reset_scrfx();
896 gen_op_load_fpr_FT0(rB(ctx->opcode));
897 gen_op_store_FT0_fpr(rD(ctx->opcode));
898 if (Rc(ctx->opcode))
899 gen_op_set_Rc1();
900}
901
902/* fnabs */
903GEN_FLOAT_B(nabs, 0x08, 0x04);
904/* fneg */
905GEN_FLOAT_B(neg, 0x08, 0x01);
906
79aceca5
FB		 907/*** Floating-Point status & ctrl register ***/
908/* mcrfs */
909GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
910{
fb0eaffc
FB		 911 gen_op_load_fpscr_T0(crfS(ctx->opcode));
912 gen_op_store_T0_crf(crfD(ctx->opcode));
913 gen_op_clear_fpscr(crfS(ctx->opcode));
79aceca5
FB		 914}
915
916/* mffs */
917GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
918{
28b6751f 919 gen_op_load_fpscr();
fb0eaffc
FB		 920 gen_op_store_FT0_fpr(rD(ctx->opcode));
921 if (Rc(ctx->opcode))
922 gen_op_set_Rc1();
79aceca5
FB		 923}
924
925/* mtfsb0 */
926GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
927{
fb0eaffc
FB		 928 uint8_t crb;
929
930 crb = crbD(ctx->opcode) >> 2;
931 gen_op_load_fpscr_T0(crb);
932 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
933 gen_op_store_T0_fpscr(crb);
934 if (Rc(ctx->opcode))
935 gen_op_set_Rc1();
79aceca5
FB		 936}
937
938/* mtfsb1 */
939GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
940{
fb0eaffc
FB		 941 uint8_t crb;
942
943 crb = crbD(ctx->opcode) >> 2;
944 gen_op_load_fpscr_T0(crb);
945 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
946 gen_op_store_T0_fpscr(crb);
947 if (Rc(ctx->opcode))
948 gen_op_set_Rc1();
79aceca5
FB		 949}
950
951/* mtfsf */
952GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
953{
fb0eaffc 954 gen_op_load_fpr_FT0(rB(ctx->opcode));
28b6751f 955 gen_op_store_fpscr(FM(ctx->opcode));
fb0eaffc
FB		 956 if (Rc(ctx->opcode))
957 gen_op_set_Rc1();
79aceca5
FB		 958}
959
960/* mtfsfi */
961GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
962{
fb0eaffc
FB		 963 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
964 if (Rc(ctx->opcode))
965 gen_op_set_Rc1();
79aceca5
FB		 966}
967
968/*** Integer load ***/
9a64fbe4
FB		 969#if defined(CONFIG_USER_ONLY)
970#define op_ldst(name) gen_op_##name##_raw()
971#define OP_LD_TABLE(width)
972#define OP_ST_TABLE(width)
973#else
974#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
975#define OP_LD_TABLE(width) \
976static GenOpFunc *gen_op_l##width[] = { \
977 &gen_op_l##width##_user, \
978 &gen_op_l##width##_kernel, \
979}
980#define OP_ST_TABLE(width) \
981static GenOpFunc *gen_op_st##width[] = { \
982 &gen_op_st##width##_user, \
983 &gen_op_st##width##_kernel, \
984}
985#endif
986
987#define GEN_LD(width, opc) \
79aceca5
FB		 988GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
989{ \
990 uint32_t simm = SIMM(ctx->opcode); \
991 if (rA(ctx->opcode) == 0) { \
9a64fbe4 992 gen_op_set_T0(simm); \
79aceca5
FB		 993 } else { \
994 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 995 if (simm != 0) \
996 gen_op_addi(simm); \
79aceca5 997 } \
9a64fbe4 998 op_ldst(l##width); \
79aceca5 999 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1000}
1001
9a64fbe4 1002#define GEN_LDU(width, opc) \
79aceca5
FB		 1003GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1004{ \
9a64fbe4 1005 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1006 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1007 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1008 RET_INVAL(ctx); \
1009 return; \
9a64fbe4 1010 } \
79aceca5 1011 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1012 if (simm != 0) \
1013 gen_op_addi(simm); \
1014 op_ldst(l##width); \
79aceca5
FB		 1015 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1016 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1017}
1018
9a64fbe4 1019#define GEN_LDUX(width, opc) \
79aceca5
FB		 1020GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1021{ \
1022 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1023 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1024 RET_INVAL(ctx); \
1025 return; \
9a64fbe4 1026 } \
79aceca5
FB		 1027 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1028 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1029 gen_op_add(); \
1030 op_ldst(l##width); \
79aceca5
FB		 1031 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1032 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1033}
1034
9a64fbe4 1035#define GEN_LDX(width, opc2, opc3) \
79aceca5
FB		 1036GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1037{ \
1038 if (rA(ctx->opcode) == 0) { \
1039 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1040 } else { \
1041 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1042 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1043 gen_op_add(); \
79aceca5 1044 } \
9a64fbe4 1045 op_ldst(l##width); \
79aceca5 1046 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1047}
1048
9a64fbe4
FB		 1049#define GEN_LDS(width, op) \
1050OP_LD_TABLE(width); \
1051GEN_LD(width, op | 0x20); \
1052GEN_LDU(width, op | 0x21); \
1053GEN_LDUX(width, op | 0x01); \
1054GEN_LDX(width, 0x17, op | 0x00)
79aceca5
FB		 1055
1056/* lbz lbzu lbzux lbzx */
9a64fbe4 1057GEN_LDS(bz, 0x02);
79aceca5 1058/* lha lhau lhaux lhax */
9a64fbe4 1059GEN_LDS(ha, 0x0A);
79aceca5 1060/* lhz lhzu lhzux lhzx */
9a64fbe4 1061GEN_LDS(hz, 0x08);
79aceca5 1062/* lwz lwzu lwzux lwzx */
9a64fbe4 1063GEN_LDS(wz, 0x00);
79aceca5
FB		 1064
1065/*** Integer store ***/
9a64fbe4 1066#define GEN_ST(width, opc) \
79aceca5
FB		 1067GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1068{ \
1069 uint32_t simm = SIMM(ctx->opcode); \
1070 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1071 gen_op_set_T0(simm); \
79aceca5
FB		 1072 } else { \
1073 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1074 if (simm != 0) \
1075 gen_op_addi(simm); \
79aceca5 1076 } \
9a64fbe4
FB		 1077 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1078 op_ldst(st##width); \
79aceca5
FB		 1079}
1080
9a64fbe4 1081#define GEN_STU(width, opc) \
79aceca5
FB		 1082GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1083{ \
9a64fbe4
FB		 1084 uint32_t simm = SIMM(ctx->opcode); \
1085 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1086 RET_INVAL(ctx); \
1087 return; \
9a64fbe4 1088 } \
79aceca5 1089 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1090 if (simm != 0) \
1091 gen_op_addi(simm); \
79aceca5 1092 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 1093 op_ldst(st##width); \
79aceca5 1094 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1095}
1096
9a64fbe4 1097#define GEN_STUX(width, opc) \
79aceca5
FB		 1098GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1099{ \
9a64fbe4 1100 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1101 RET_INVAL(ctx); \
1102 return; \
9a64fbe4 1103 } \
79aceca5
FB		 1104 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1105 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1106 gen_op_add(); \
1107 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1108 op_ldst(st##width); \
79aceca5 1109 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1110}
1111
9a64fbe4 1112#define GEN_STX(width, opc2, opc3) \
79aceca5
FB		 1113GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1114{ \
1115 if (rA(ctx->opcode) == 0) { \
1116 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1117 } else { \
1118 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1119 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1120 gen_op_add(); \
79aceca5 1121 } \
9a64fbe4
FB		 1122 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1123 op_ldst(st##width); \
79aceca5
FB		 1124}
1125
9a64fbe4
FB		 1126#define GEN_STS(width, op) \
1127OP_ST_TABLE(width); \
1128GEN_ST(width, op | 0x20); \
1129GEN_STU(width, op | 0x21); \
1130GEN_STUX(width, op | 0x01); \
1131GEN_STX(width, 0x17, op | 0x00)
79aceca5
FB		 1132
1133/* stb stbu stbux stbx */
9a64fbe4 1134GEN_STS(b, 0x06);
79aceca5 1135/* sth sthu sthux sthx */
9a64fbe4 1136GEN_STS(h, 0x0C);
79aceca5 1137/* stw stwu stwux stwx */
9a64fbe4 1138GEN_STS(w, 0x04);
79aceca5
FB		 1139
1140/*** Integer load and store with byte reverse ***/
1141/* lhbrx */
9a64fbe4
FB		 1142OP_LD_TABLE(hbr);
1143GEN_LDX(hbr, 0x16, 0x18);
79aceca5 1144/* lwbrx */
9a64fbe4
FB		 1145OP_LD_TABLE(wbr);
1146GEN_LDX(wbr, 0x16, 0x10);
79aceca5 1147/* sthbrx */
9a64fbe4
FB		 1148OP_ST_TABLE(hbr);
1149GEN_STX(hbr, 0x16, 0x1C);
79aceca5 1150/* stwbrx */
9a64fbe4
FB		 1151OP_ST_TABLE(wbr);
1152GEN_STX(wbr, 0x16, 0x14);
79aceca5
FB		 1153
1154/*** Integer load and store multiple ***/
9a64fbe4
FB		 1155#if defined(CONFIG_USER_ONLY)
1156#define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1157#else
1158#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1159static GenOpFunc1 *gen_op_lmw[] = {
1160 &gen_op_lmw_user,
1161 &gen_op_lmw_kernel,
1162};
1163static GenOpFunc1 *gen_op_stmw[] = {
1164 &gen_op_stmw_user,
1165 &gen_op_stmw_kernel,
1166};
1167#endif
1168
79aceca5
FB		 1169/* lmw */
1170GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1171{
9a64fbe4
FB		 1172 int simm = SIMM(ctx->opcode);
1173
79aceca5 1174 if (rA(ctx->opcode) == 0) {
9a64fbe4 1175 gen_op_set_T0(simm);
79aceca5
FB		 1176 } else {
1177 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1178 if (simm != 0)
1179 gen_op_addi(simm);
79aceca5 1180 }
9a64fbe4 1181 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 1182}
1183
1184/* stmw */
1185GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1186{
9a64fbe4
FB		 1187 int simm = SIMM(ctx->opcode);
1188
79aceca5 1189 if (rA(ctx->opcode) == 0) {
9a64fbe4 1190 gen_op_set_T0(simm);
79aceca5
FB		 1191 } else {
1192 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1193 if (simm != 0)
1194 gen_op_addi(simm);
79aceca5 1195 }
9a64fbe4 1196 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 1197}
1198
1199/*** Integer load and store strings ***/
9a64fbe4
FB		 1200#if defined(CONFIG_USER_ONLY)
1201#define op_ldsts(name, start) gen_op_##name##_raw(start)
1202#define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1203#else
1204#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1205#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1206static GenOpFunc1 *gen_op_lswi[] = {
1207 &gen_op_lswi_user,
1208 &gen_op_lswi_kernel,
1209};
1210static GenOpFunc3 *gen_op_lswx[] = {
1211 &gen_op_lswx_user,
1212 &gen_op_lswx_kernel,
1213};
1214static GenOpFunc1 *gen_op_stsw[] = {
1215 &gen_op_stsw_user,
1216 &gen_op_stsw_kernel,
1217};
1218#endif
1219
79aceca5 1220/* lswi */
9a64fbe4
FB		 1221/* PPC32 specification says we must generate an exception if
1222 * rA is in the range of registers to be loaded.
1223 * In an other hand, IBM says this is valid, but rA won't be loaded.
1224 * For now, I'll follow the spec...
1225 */
79aceca5
FB		 1226GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1227{
1228 int nb = NB(ctx->opcode);
1229 int start = rD(ctx->opcode);
9a64fbe4 1230 int ra = rA(ctx->opcode);
79aceca5
FB		 1231 int nr;
1232
1233 if (nb == 0)
1234 nb = 32;
1235 nr = nb / 4;
297d8e62
FB		 1236 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1237 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
9fddaa0c
FB		 1238 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1239 return;
297d8e62 1240 }
9a64fbe4 1241 if (ra == 0) {
79aceca5
FB		 1242 gen_op_set_T0(0);
1243 } else {
9a64fbe4 1244 gen_op_load_gpr_T0(ra);
79aceca5 1245 }
9a64fbe4
FB		 1246 gen_op_set_T1(nb);
1247 op_ldsts(lswi, start);
79aceca5
FB		 1248}
1249
1250/* lswx */
1251GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1252{
9a64fbe4
FB		 1253 int ra = rA(ctx->opcode);
1254 int rb = rB(ctx->opcode);
1255
1256 if (ra == 0) {
1257 gen_op_load_gpr_T0(rb);
1258 ra = rb;
79aceca5 1259 } else {
9a64fbe4
FB		 1260 gen_op_load_gpr_T0(ra);
1261 gen_op_load_gpr_T1(rb);
1262 gen_op_add();
79aceca5 1263 }
9a64fbe4
FB		 1264 gen_op_load_xer_bc();
1265 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 1266}
1267
1268/* stswi */
1269GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1270{
79aceca5
FB		 1271 if (rA(ctx->opcode) == 0) {
1272 gen_op_set_T0(0);
1273 } else {
1274 gen_op_load_gpr_T0(rA(ctx->opcode));
1275 }
9a64fbe4
FB		 1276 gen_op_set_T1(NB(ctx->opcode));
1277 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1278}
1279
1280/* stswx */
1281GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1282{
9a64fbe4
FB		 1283 int ra = rA(ctx->opcode);
1284
1285 if (ra == 0) {
1286 gen_op_load_gpr_T0(rB(ctx->opcode));
1287 ra = rB(ctx->opcode);
79aceca5 1288 } else {
9a64fbe4
FB		 1289 gen_op_load_gpr_T0(ra);
1290 gen_op_load_gpr_T1(rB(ctx->opcode));
1291 gen_op_add();
79aceca5 1292 }
9a64fbe4
FB		 1293 gen_op_load_xer_bc();
1294 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1295}
1296
1297/*** Memory synchronisation ***/
1298/* eieio */
1299GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1300{
79aceca5
FB		 1301}
1302
1303/* isync */
1304GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1305{
79aceca5
FB		 1306}
1307
1308/* lwarx */
9a64fbe4 1309#if defined(CONFIG_USER_ONLY)
985a19d6 1310#define op_lwarx() gen_op_lwarx_raw()
9a64fbe4
FB		 1311#define op_stwcx() gen_op_stwcx_raw()
1312#else
985a19d6
FB		 1313#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1314static GenOpFunc *gen_op_lwarx[] = {
1315 &gen_op_lwarx_user,
1316 &gen_op_lwarx_kernel,
1317};
9a64fbe4
FB		 1318#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1319static GenOpFunc *gen_op_stwcx[] = {
1320 &gen_op_stwcx_user,
1321 &gen_op_stwcx_kernel,
1322};
1323#endif
1324
1325GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
79aceca5 1326{
79aceca5
FB		 1327 if (rA(ctx->opcode) == 0) {
1328 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1329 } else {
1330 gen_op_load_gpr_T0(rA(ctx->opcode));
1331 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1332 gen_op_add();
79aceca5 1333 }
985a19d6 1334 op_lwarx();
79aceca5 1335 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 1336}
1337
1338/* stwcx. */
9a64fbe4 1339GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 1340{
79aceca5
FB		 1341 if (rA(ctx->opcode) == 0) {
1342 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1343 } else {
1344 gen_op_load_gpr_T0(rA(ctx->opcode));
1345 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1346 gen_op_add();
79aceca5 1347 }
9a64fbe4
FB		 1348 gen_op_load_gpr_T1(rS(ctx->opcode));
1349 op_stwcx();
79aceca5
FB		 1350}
1351
1352/* sync */
1353GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1354{
79aceca5
FB		 1355}
1356
1357/*** Floating-point load ***/
9a64fbe4
FB		 1358#define GEN_LDF(width, opc) \
1359GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1360{ \
1361 uint32_t simm = SIMM(ctx->opcode); \
1362 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1363 gen_op_set_T0(simm); \
79aceca5
FB		 1364 } else { \
1365 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1366 if (simm != 0) \
1367 gen_op_addi(simm); \
79aceca5 1368 } \
9a64fbe4
FB		 1369 op_ldst(l##width); \
1370 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1371}
1372
9a64fbe4
FB		 1373#define GEN_LDUF(width, opc) \
1374GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1375{ \
9a64fbe4 1376 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1377 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1378 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1379 RET_INVAL(ctx); \
1380 return; \
9a64fbe4 1381 } \
79aceca5 1382 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1383 if (simm != 0) \
1384 gen_op_addi(simm); \
1385 op_ldst(l##width); \
1386 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1387 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1388}
1389
9a64fbe4
FB		 1390#define GEN_LDUXF(width, opc) \
1391GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1392{ \
1393 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1394 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1395 RET_INVAL(ctx); \
1396 return; \
9a64fbe4 1397 } \
79aceca5
FB		 1398 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1399 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1400 gen_op_add(); \
1401 op_ldst(l##width); \
1402 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1403 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1404}
1405
9a64fbe4
FB		 1406#define GEN_LDXF(width, opc2, opc3) \
1407GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1408{ \
1409 if (rA(ctx->opcode) == 0) { \
1410 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1411 } else { \
1412 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1413 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1414 gen_op_add(); \
79aceca5 1415 } \
9a64fbe4
FB		 1416 op_ldst(l##width); \
1417 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1418}
1419
9a64fbe4
FB		 1420#define GEN_LDFS(width, op) \
1421OP_LD_TABLE(width); \
1422GEN_LDF(width, op | 0x20); \
1423GEN_LDUF(width, op | 0x21); \
1424GEN_LDUXF(width, op | 0x01); \
1425GEN_LDXF(width, 0x17, op | 0x00)
79aceca5
FB		 1426
1427/* lfd lfdu lfdux lfdx */
9a64fbe4 1428GEN_LDFS(fd, 0x12);
79aceca5 1429/* lfs lfsu lfsux lfsx */
9a64fbe4 1430GEN_LDFS(fs, 0x10);
79aceca5
FB		 1431
1432/*** Floating-point store ***/
1433#define GEN_STF(width, opc) \
9a64fbe4 1434GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1435{ \
1436 uint32_t simm = SIMM(ctx->opcode); \
1437 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1438 gen_op_set_T0(simm); \
79aceca5
FB		 1439 } else { \
1440 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1441 if (simm != 0) \
1442 gen_op_addi(simm); \
79aceca5 1443 } \
9a64fbe4
FB		 1444 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1445 op_ldst(st##width); \
79aceca5
FB		 1446}
1447
9a64fbe4
FB		 1448#define GEN_STUF(width, opc) \
1449GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1450{ \
9a64fbe4
FB		 1451 uint32_t simm = SIMM(ctx->opcode); \
1452 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1453 RET_INVAL(ctx); \
1454 return; \
9a64fbe4 1455 } \
79aceca5 1456 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1457 if (simm != 0) \
1458 gen_op_addi(simm); \
1459 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1460 op_ldst(st##width); \
79aceca5 1461 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1462}
1463
9a64fbe4
FB		 1464#define GEN_STUXF(width, opc) \
1465GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5 1466{ \
9a64fbe4 1467 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1468 RET_INVAL(ctx); \
1469 return; \
9a64fbe4 1470 } \
79aceca5
FB		 1471 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1472 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1473 gen_op_add(); \
1474 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1475 op_ldst(st##width); \
79aceca5 1476 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1477}
1478
9a64fbe4
FB		 1479#define GEN_STXF(width, opc2, opc3) \
1480GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1481{ \
1482 if (rA(ctx->opcode) == 0) { \
1483 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1484 } else { \
1485 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1486 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1487 gen_op_add(); \
79aceca5 1488 } \
9a64fbe4
FB		 1489 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1490 op_ldst(st##width); \
79aceca5
FB		 1491}
1492
9a64fbe4
FB		 1493#define GEN_STFS(width, op) \
1494OP_ST_TABLE(width); \
1495GEN_STF(width, op | 0x20); \
1496GEN_STUF(width, op | 0x21); \
1497GEN_STUXF(width, op | 0x01); \
1498GEN_STXF(width, 0x17, op | 0x00)
79aceca5
FB		 1499
1500/* stfd stfdu stfdux stfdx */
9a64fbe4 1501GEN_STFS(fd, 0x16);
79aceca5 1502/* stfs stfsu stfsux stfsx */
9a64fbe4 1503GEN_STFS(fs, 0x14);
79aceca5
FB		 1504
1505/* Optional: */
1506/* stfiwx */
1507GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1508{
9fddaa0c 1509 RET_INVAL(ctx);
79aceca5
FB		 1510}
1511
1512/*** Branch ***/
79aceca5
FB		 1513
1514/* b ba bl bla */
1515GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1516{
1517 uint32_t li = s_ext24(LI(ctx->opcode)), target;
1518
1519 if (AA(ctx->opcode) == 0)
046d6672 1520 target = ctx->nip + li - 4;
79aceca5 1521 else
9a64fbe4 1522 target = li;
9a64fbe4 1523 if (LK(ctx->opcode)) {
046d6672 1524 gen_op_setlr(ctx->nip);
9a64fbe4 1525 }
e98a6e40 1526 gen_op_b((long)ctx->tb, target);
9a64fbe4 1527 ctx->exception = EXCP_BRANCH;
79aceca5
FB		 1528}
1529
e98a6e40
FB		 1530#define BCOND_IM 0
1531#define BCOND_LR 1
1532#define BCOND_CTR 2
1533
1534static inline void gen_bcond(DisasContext *ctx, int type)
1535{
1536 uint32_t target = 0;
1537 uint32_t bo = BO(ctx->opcode);
1538 uint32_t bi = BI(ctx->opcode);
1539 uint32_t mask;
1540 uint32_t li;
1541
e98a6e40
FB		 1542 if ((bo & 0x4) == 0)
1543 gen_op_dec_ctr();
1544 switch(type) {
1545 case BCOND_IM:
1546 li = s_ext16(BD(ctx->opcode));
1547 if (AA(ctx->opcode) == 0) {
046d6672 1548 target = ctx->nip + li - 4;
e98a6e40
FB		 1549 } else {
1550 target = li;
1551 }
1552 break;
1553 case BCOND_CTR:
1554 gen_op_movl_T1_ctr();
1555 break;
1556 default:
1557 case BCOND_LR:
1558 gen_op_movl_T1_lr();
1559 break;
1560 }
1561 if (LK(ctx->opcode)) {
046d6672 1562 gen_op_setlr(ctx->nip);
e98a6e40
FB		 1563 }
1564 if (bo & 0x10) {
1565 /* No CR condition */
1566 switch (bo & 0x6) {
1567 case 0:
1568 gen_op_test_ctr();
1569 break;
1570 case 2:
1571 gen_op_test_ctrz();
1572 break;
1573 default:
1574 case 4:
1575 case 6:
1576 if (type == BCOND_IM) {
1577 gen_op_b((long)ctx->tb, target);
1578 } else {
1579 gen_op_b_T1();
e98a6e40
FB		 1580 }
1581 goto no_test;
1582 }
1583 } else {
1584 mask = 1 << (3 - (bi & 0x03));
1585 gen_op_load_crf_T0(bi >> 2);
1586 if (bo & 0x8) {
1587 switch (bo & 0x6) {
1588 case 0:
1589 gen_op_test_ctr_true(mask);
1590 break;
1591 case 2:
1592 gen_op_test_ctrz_true(mask);
1593 break;
1594 default:
1595 case 4:
1596 case 6:
1597 gen_op_test_true(mask);
1598 break;
1599 }
1600 } else {
1601 switch (bo & 0x6) {
1602 case 0:
1603 gen_op_test_ctr_false(mask);
1604 break;
1605 case 2:
1606 gen_op_test_ctrz_false(mask);
1607 break;
1608 default:
1609 case 4:
1610 case 6:
1611 gen_op_test_false(mask);
1612 break;
1613 }
1614 }
1615 }
1616 if (type == BCOND_IM) {
046d6672 1617 gen_op_btest((long)ctx->tb, target, ctx->nip);
e98a6e40 1618 } else {
046d6672 1619 gen_op_btest_T1(ctx->nip);
e98a6e40
FB		 1620 }
1621 no_test:
1622 ctx->exception = EXCP_BRANCH;
1623}
1624
1625GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1626{
1627 gen_bcond(ctx, BCOND_IM);
1628}
1629
1630GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1631{
1632 gen_bcond(ctx, BCOND_CTR);
1633}
1634
1635GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1636{
1637 gen_bcond(ctx, BCOND_LR);
1638}
79aceca5
FB		 1639
1640/*** Condition register logical ***/
1641#define GEN_CRLOGIC(op, opc) \
1642GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1643{ \
1644 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1645 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1646 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1647 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1648 gen_op_##op(); \
1649 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1650 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1651 3 - (crbD(ctx->opcode) & 0x03)); \
1652 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 1653}
1654
1655/* crand */
1656GEN_CRLOGIC(and, 0x08)
1657/* crandc */
1658GEN_CRLOGIC(andc, 0x04)
1659/* creqv */
1660GEN_CRLOGIC(eqv, 0x09)
1661/* crnand */
1662GEN_CRLOGIC(nand, 0x07)
1663/* crnor */
1664GEN_CRLOGIC(nor, 0x01)
1665/* cror */
1666GEN_CRLOGIC(or, 0x0E)
1667/* crorc */
1668GEN_CRLOGIC(orc, 0x0D)
1669/* crxor */
1670GEN_CRLOGIC(xor, 0x06)
1671/* mcrf */
1672GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1673{
1674 gen_op_load_crf_T0(crfS(ctx->opcode));
1675 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1676}
1677
1678/*** System linkage ***/
1679/* rfi (supervisor only) */
1680GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1681{
9a64fbe4 1682#if defined(CONFIG_USER_ONLY)
9fddaa0c 1683 RET_PRIVOPC(ctx);
9a64fbe4
FB		 1684#else
1685 /* Restore CPU state */
1686 if (!ctx->supervisor) {
9fddaa0c
FB		 1687 RET_PRIVOPC(ctx);
1688 return;
9a64fbe4
FB		 1689 }
1690 gen_op_rfi();
9fddaa0c 1691 RET_EXCP(ctx, EXCP_RFI, 0);
9a64fbe4 1692#endif
79aceca5
FB		 1693}
1694
1695/* sc */
1696GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1697{
9a64fbe4 1698#if defined(CONFIG_USER_ONLY)
9fddaa0c 1699 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
9a64fbe4 1700#else
9fddaa0c 1701 RET_EXCP(ctx, EXCP_SYSCALL, 0);
9a64fbe4 1702#endif
79aceca5
FB		 1703}
1704
1705/*** Trap ***/
1706/* tw */
1707GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1708{
9a64fbe4
FB		 1709 gen_op_load_gpr_T0(rA(ctx->opcode));
1710 gen_op_load_gpr_T1(rB(ctx->opcode));
1711 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 1712}
1713
1714/* twi */
1715GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1716{
9a64fbe4
FB		 1717 gen_op_load_gpr_T0(rA(ctx->opcode));
1718#if 0
1719 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1720 SIMM(ctx->opcode), TO(ctx->opcode));
1721#endif
1722 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
79aceca5
FB		 1723}
1724
1725/*** Processor control ***/
1726static inline int check_spr_access (int spr, int rw, int supervisor)
1727{
1728 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1729
9a64fbe4
FB		 1730#if 0
1731 if (spr != LR && spr != CTR) {
1732 if (loglevel > 0) {
1733 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1734 SPR_ENCODE(spr), supervisor, rw, rights,
1735 (rights >> ((2 * supervisor) + rw)) & 1);
1736 } else {
1737 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1738 SPR_ENCODE(spr), supervisor, rw, rights,
1739 (rights >> ((2 * supervisor) + rw)) & 1);
1740 }
1741 }
1742#endif
1743 if (rights == 0)
1744 return -1;
79aceca5
FB		 1745 rights = rights >> (2 * supervisor);
1746 rights = rights >> rw;
1747
1748 return rights & 1;
1749}
1750
1751/* mcrxr */
1752GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1753{
1754 gen_op_load_xer_cr();
1755 gen_op_store_T0_crf(crfD(ctx->opcode));
1756 gen_op_clear_xer_cr();
79aceca5
FB		 1757}
1758
1759/* mfcr */
1760GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1761{
1762 gen_op_load_cr();
1763 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1764}
1765
1766/* mfmsr */
1767GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1768{
9a64fbe4 1769#if defined(CONFIG_USER_ONLY)
9fddaa0c 1770 RET_PRIVREG(ctx);
9a64fbe4
FB		 1771#else
1772 if (!ctx->supervisor) {
9fddaa0c
FB		 1773 RET_PRIVREG(ctx);
1774 return;
9a64fbe4 1775 }
79aceca5
FB		 1776 gen_op_load_msr();
1777 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 1778#endif
79aceca5
FB		 1779}
1780
1781/* mfspr */
1782GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1783{
1784 uint32_t sprn = SPR(ctx->opcode);
1785
9a64fbe4
FB		 1786#if defined(CONFIG_USER_ONLY)
1787 switch (check_spr_access(sprn, 0, 0))
1788#else
1789 switch (check_spr_access(sprn, 0, ctx->supervisor))
1790#endif
1791 {
1792 case -1:
9fddaa0c
FB		 1793 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1794 return;
9a64fbe4 1795 case 0:
9fddaa0c
FB		 1796 RET_PRIVREG(ctx);
1797 return;
9a64fbe4
FB		 1798 default:
1799 break;
79aceca5 1800 }
9a64fbe4
FB		 1801 switch (sprn) {
1802 case XER:
79aceca5
FB		 1803 gen_op_load_xer();
1804 break;
9a64fbe4
FB		 1805 case LR:
1806 gen_op_load_lr();
1807 break;
1808 case CTR:
1809 gen_op_load_ctr();
1810 break;
1811 case IBAT0U:
1812 gen_op_load_ibat(0, 0);
1813 break;
1814 case IBAT1U:
1815 gen_op_load_ibat(0, 1);
1816 break;
1817 case IBAT2U:
1818 gen_op_load_ibat(0, 2);
1819 break;
1820 case IBAT3U:
1821 gen_op_load_ibat(0, 3);
1822 break;
1823 case IBAT4U:
1824 gen_op_load_ibat(0, 4);
1825 break;
1826 case IBAT5U:
1827 gen_op_load_ibat(0, 5);
1828 break;
1829 case IBAT6U:
1830 gen_op_load_ibat(0, 6);
1831 break;
1832 case IBAT7U:
1833 gen_op_load_ibat(0, 7);
1834 break;
1835 case IBAT0L:
1836 gen_op_load_ibat(1, 0);
1837 break;
1838 case IBAT1L:
1839 gen_op_load_ibat(1, 1);
1840 break;
1841 case IBAT2L:
1842 gen_op_load_ibat(1, 2);
1843 break;
1844 case IBAT3L:
1845 gen_op_load_ibat(1, 3);
1846 break;
1847 case IBAT4L:
1848 gen_op_load_ibat(1, 4);
1849 break;
1850 case IBAT5L:
1851 gen_op_load_ibat(1, 5);
1852 break;
1853 case IBAT6L:
1854 gen_op_load_ibat(1, 6);
1855 break;
1856 case IBAT7L:
1857 gen_op_load_ibat(1, 7);
1858 break;
1859 case DBAT0U:
1860 gen_op_load_dbat(0, 0);
1861 break;
1862 case DBAT1U:
1863 gen_op_load_dbat(0, 1);
1864 break;
1865 case DBAT2U:
1866 gen_op_load_dbat(0, 2);
1867 break;
1868 case DBAT3U:
1869 gen_op_load_dbat(0, 3);
1870 break;
1871 case DBAT4U:
1872 gen_op_load_dbat(0, 4);
1873 break;
1874 case DBAT5U:
1875 gen_op_load_dbat(0, 5);
1876 break;
1877 case DBAT6U:
1878 gen_op_load_dbat(0, 6);
1879 break;
1880 case DBAT7U:
1881 gen_op_load_dbat(0, 7);
1882 break;
1883 case DBAT0L:
1884 gen_op_load_dbat(1, 0);
1885 break;
1886 case DBAT1L:
1887 gen_op_load_dbat(1, 1);
1888 break;
1889 case DBAT2L:
1890 gen_op_load_dbat(1, 2);
1891 break;
1892 case DBAT3L:
1893 gen_op_load_dbat(1, 3);
1894 break;
1895 case DBAT4L:
1896 gen_op_load_dbat(1, 4);
1897 break;
1898 case DBAT5L:
1899 gen_op_load_dbat(1, 5);
1900 break;
1901 case DBAT6L:
1902 gen_op_load_dbat(1, 6);
1903 break;
1904 case DBAT7L:
1905 gen_op_load_dbat(1, 7);
1906 break;
1907 case SDR1:
1908 gen_op_load_sdr1();
1909 break;
1910 case V_TBL:
9fddaa0c 1911 gen_op_load_tbl();
79aceca5 1912 break;
9a64fbe4 1913 case V_TBU:
9fddaa0c 1914 gen_op_load_tbu();
9a64fbe4
FB		 1915 break;
1916 case DECR:
9fddaa0c 1917 gen_op_load_decr();
79aceca5
FB		 1918 break;
1919 default:
1920 gen_op_load_spr(sprn);
1921 break;
1922 }
9a64fbe4 1923 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1924}
1925
1926/* mftb */
1927GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
1928{
1929 uint32_t sprn = SPR(ctx->opcode);
1930
79aceca5 1931 /* We need to update the time base before reading it */
9a64fbe4
FB		 1932 switch (sprn) {
1933 case V_TBL:
9a64fbe4 1934 /* TBL is still in T0 */
9fddaa0c 1935 gen_op_load_tbl();
79aceca5 1936 break;
9a64fbe4 1937 case V_TBU:
9fddaa0c 1938 gen_op_load_tbu();
79aceca5
FB		 1939 break;
1940 default:
9fddaa0c
FB		 1941 RET_INVAL(ctx);
1942 return;
79aceca5 1943 }
9a64fbe4 1944 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1945}
1946
1947/* mtcrf */
1948GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
1949{
1950 gen_op_load_gpr_T0(rS(ctx->opcode));
1951 gen_op_store_cr(CRM(ctx->opcode));
79aceca5
FB		 1952}
1953
1954/* mtmsr */
1955GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
1956{
9a64fbe4 1957#if defined(CONFIG_USER_ONLY)
9fddaa0c 1958 RET_PRIVREG(ctx);
9a64fbe4
FB		 1959#else
1960 if (!ctx->supervisor) {
9fddaa0c
FB		 1961 RET_PRIVREG(ctx);
1962 return;
9a64fbe4 1963 }
79aceca5
FB		 1964 gen_op_load_gpr_T0(rS(ctx->opcode));
1965 gen_op_store_msr();
1966 /* Must stop the translation as machine state (may have) changed */
9fddaa0c 1967 RET_MTMSR(ctx);
9a64fbe4 1968#endif
79aceca5
FB		 1969}
1970
1971/* mtspr */
1972GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
1973{
1974 uint32_t sprn = SPR(ctx->opcode);
1975
9a64fbe4
FB		 1976#if 0
1977 if (loglevel > 0) {
1978 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
1979 rS(ctx->opcode), sprn);
1980 }
1981#endif
1982#if defined(CONFIG_USER_ONLY)
1983 switch (check_spr_access(sprn, 1, 0))
1984#else
1985 switch (check_spr_access(sprn, 1, ctx->supervisor))
1986#endif
1987 {
1988 case -1:
9fddaa0c 1989 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
9a64fbe4
FB		 1990 break;
1991 case 0:
9fddaa0c 1992 RET_PRIVREG(ctx);
9a64fbe4
FB		 1993 break;
1994 default:
1995 break;
1996 }
79aceca5 1997 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4
FB		 1998 switch (sprn) {
1999 case XER:
79aceca5 2000 gen_op_store_xer();
9a64fbe4
FB		 2001 break;
2002 case LR:
9a64fbe4
FB		 2003 gen_op_store_lr();
2004 break;
2005 case CTR:
2006 gen_op_store_ctr();
2007 break;
2008 case IBAT0U:
2009 gen_op_store_ibat(0, 0);
2010 gen_op_tlbia();
2011 break;
2012 case IBAT1U:
2013 gen_op_store_ibat(0, 1);
2014 gen_op_tlbia();
2015 break;
2016 case IBAT2U:
2017 gen_op_store_ibat(0, 2);
2018 gen_op_tlbia();
2019 break;
2020 case IBAT3U:
2021 gen_op_store_ibat(0, 3);
2022 gen_op_tlbia();
2023 break;
2024 case IBAT4U:
2025 gen_op_store_ibat(0, 4);
2026 gen_op_tlbia();
2027 break;
2028 case IBAT5U:
2029 gen_op_store_ibat(0, 5);
2030 gen_op_tlbia();
2031 break;
2032 case IBAT6U:
2033 gen_op_store_ibat(0, 6);
2034 gen_op_tlbia();
2035 break;
2036 case IBAT7U:
2037 gen_op_store_ibat(0, 7);
2038 gen_op_tlbia();
2039 break;
2040 case IBAT0L:
2041 gen_op_store_ibat(1, 0);
2042 gen_op_tlbia();
2043 break;
2044 case IBAT1L:
2045 gen_op_store_ibat(1, 1);
2046 gen_op_tlbia();
2047 break;
2048 case IBAT2L:
2049 gen_op_store_ibat(1, 2);
2050 gen_op_tlbia();
2051 break;
2052 case IBAT3L:
2053 gen_op_store_ibat(1, 3);
2054 gen_op_tlbia();
2055 break;
2056 case IBAT4L:
2057 gen_op_store_ibat(1, 4);
2058 gen_op_tlbia();
2059 break;
2060 case IBAT5L:
2061 gen_op_store_ibat(1, 5);
2062 gen_op_tlbia();
2063 break;
2064 case IBAT6L:
2065 gen_op_store_ibat(1, 6);
2066 gen_op_tlbia();
2067 break;
2068 case IBAT7L:
2069 gen_op_store_ibat(1, 7);
2070 gen_op_tlbia();
2071 break;
2072 case DBAT0U:
2073 gen_op_store_dbat(0, 0);
2074 gen_op_tlbia();
2075 break;
2076 case DBAT1U:
2077 gen_op_store_dbat(0, 1);
2078 gen_op_tlbia();
2079 break;
2080 case DBAT2U:
2081 gen_op_store_dbat(0, 2);
2082 gen_op_tlbia();
2083 break;
2084 case DBAT3U:
2085 gen_op_store_dbat(0, 3);
2086 gen_op_tlbia();
2087 break;
2088 case DBAT4U:
2089 gen_op_store_dbat(0, 4);
2090 gen_op_tlbia();
2091 break;
2092 case DBAT5U:
2093 gen_op_store_dbat(0, 5);
2094 gen_op_tlbia();
2095 break;
2096 case DBAT6U:
2097 gen_op_store_dbat(0, 6);
2098 gen_op_tlbia();
2099 break;
2100 case DBAT7U:
2101 gen_op_store_dbat(0, 7);
2102 gen_op_tlbia();
2103 break;
2104 case DBAT0L:
2105 gen_op_store_dbat(1, 0);
2106 gen_op_tlbia();
2107 break;
2108 case DBAT1L:
2109 gen_op_store_dbat(1, 1);
2110 gen_op_tlbia();
2111 break;
2112 case DBAT2L:
2113 gen_op_store_dbat(1, 2);
2114 gen_op_tlbia();
2115 break;
2116 case DBAT3L:
2117 gen_op_store_dbat(1, 3);
2118 gen_op_tlbia();
2119 break;
2120 case DBAT4L:
2121 gen_op_store_dbat(1, 4);
2122 gen_op_tlbia();
2123 break;
2124 case DBAT5L:
2125 gen_op_store_dbat(1, 5);
2126 gen_op_tlbia();
2127 break;
2128 case DBAT6L:
2129 gen_op_store_dbat(1, 6);
2130 gen_op_tlbia();
2131 break;
2132 case DBAT7L:
2133 gen_op_store_dbat(1, 7);
2134 gen_op_tlbia();
2135 break;
2136 case SDR1:
2137 gen_op_store_sdr1();
2138 gen_op_tlbia();
2139 break;
2140 case O_TBL:
9fddaa0c 2141 gen_op_store_tbl();
9a64fbe4
FB		 2142 break;
2143 case O_TBU:
9fddaa0c 2144 gen_op_store_tbu();
9a64fbe4
FB		 2145 break;
2146 case DECR:
2147 gen_op_store_decr();
9a64fbe4
FB		 2148 break;
2149 default:
79aceca5 2150 gen_op_store_spr(sprn);
9a64fbe4 2151 break;
79aceca5 2152 }
79aceca5
FB		 2153}
2154
2155/*** Cache management ***/
2156/* For now, all those will be implemented as nop:
2157 * this is valid, regarding the PowerPC specs...
9a64fbe4 2158 * We just have to flush tb while invalidating instruction cache lines...
79aceca5
FB		 2159 */
2160/* dcbf */
9a64fbe4 2161GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
79aceca5 2162{
a541f297
FB		 2163 if (rA(ctx->opcode) == 0) {
2164 gen_op_load_gpr_T0(rB(ctx->opcode));
2165 } else {
2166 gen_op_load_gpr_T0(rA(ctx->opcode));
2167 gen_op_load_gpr_T1(rB(ctx->opcode));
2168 gen_op_add();
2169 }
2170 op_ldst(lbz);
79aceca5
FB		 2171}
2172
2173/* dcbi (Supervisor only) */
9a64fbe4 2174GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 2175{
a541f297 2176#if defined(CONFIG_USER_ONLY)
9fddaa0c 2177 RET_PRIVOPC(ctx);
a541f297
FB		 2178#else
2179 if (!ctx->supervisor) {
9fddaa0c
FB		 2180 RET_PRIVOPC(ctx);
2181 return;
9a64fbe4 2182 }
a541f297
FB		 2183 if (rA(ctx->opcode) == 0) {
2184 gen_op_load_gpr_T0(rB(ctx->opcode));
2185 } else {
2186 gen_op_load_gpr_T0(rA(ctx->opcode));
2187 gen_op_load_gpr_T1(rB(ctx->opcode));
2188 gen_op_add();
2189 }
2190 op_ldst(lbz);
2191 op_ldst(stb);
2192#endif
79aceca5
FB		 2193}
2194
2195/* dcdst */
9a64fbe4 2196GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 2197{
a541f297
FB		 2198 if (rA(ctx->opcode) == 0) {
2199 gen_op_load_gpr_T0(rB(ctx->opcode));
2200 } else {
2201 gen_op_load_gpr_T0(rA(ctx->opcode));
2202 gen_op_load_gpr_T1(rB(ctx->opcode));
2203 gen_op_add();
2204 }
2205 op_ldst(lbz);
79aceca5
FB		 2206}
2207
2208/* dcbt */
9a64fbe4 2209GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
79aceca5 2210{
79aceca5
FB		 2211}
2212
2213/* dcbtst */
9a64fbe4 2214GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
79aceca5 2215{
79aceca5
FB		 2216}
2217
2218/* dcbz */
9a64fbe4
FB		 2219#if defined(CONFIG_USER_ONLY)
2220#define op_dcbz() gen_op_dcbz_raw()
2221#else
2222#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2223static GenOpFunc *gen_op_dcbz[] = {
2224 &gen_op_dcbz_user,
2225 &gen_op_dcbz_kernel,
2226};
2227#endif
2228
2229GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
79aceca5 2230{
fb0eaffc
FB		 2231 if (rA(ctx->opcode) == 0) {
2232 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2233 } else {
2234 gen_op_load_gpr_T0(rA(ctx->opcode));
2235 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2236 gen_op_add();
fb0eaffc 2237 }
9a64fbe4 2238 op_dcbz();
79aceca5
FB		 2239}
2240
2241/* icbi */
9a64fbe4 2242GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
79aceca5 2243{
fb0eaffc
FB		 2244 if (rA(ctx->opcode) == 0) {
2245 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2246 } else {
2247 gen_op_load_gpr_T0(rA(ctx->opcode));
2248 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2249 gen_op_add();
fb0eaffc 2250 }
9a64fbe4 2251 gen_op_icbi();
79aceca5
FB		 2252}
2253
2254/* Optional: */
2255/* dcba */
9a64fbe4 2256GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
79aceca5 2257{
79aceca5
FB		 2258}
2259
2260/*** Segment register manipulation ***/
2261/* Supervisor only: */
2262/* mfsr */
2263GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2264{
9a64fbe4 2265#if defined(CONFIG_USER_ONLY)
9fddaa0c 2266 RET_PRIVREG(ctx);
9a64fbe4
FB		 2267#else
2268 if (!ctx->supervisor) {
9fddaa0c
FB		 2269 RET_PRIVREG(ctx);
2270 return;
9a64fbe4
FB		 2271 }
2272 gen_op_load_sr(SR(ctx->opcode));
2273 gen_op_store_T0_gpr(rD(ctx->opcode));
2274#endif
79aceca5
FB		 2275}
2276
2277/* mfsrin */
9a64fbe4 2278GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 2279{
9a64fbe4 2280#if defined(CONFIG_USER_ONLY)
9fddaa0c 2281 RET_PRIVREG(ctx);
9a64fbe4
FB		 2282#else
2283 if (!ctx->supervisor) {
9fddaa0c
FB		 2284 RET_PRIVREG(ctx);
2285 return;
9a64fbe4
FB		 2286 }
2287 gen_op_load_gpr_T1(rB(ctx->opcode));
2288 gen_op_load_srin();
2289 gen_op_store_T0_gpr(rD(ctx->opcode));
2290#endif
79aceca5
FB		 2291}
2292
2293/* mtsr */
e63c59cb 2294GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 2295{
9a64fbe4 2296#if defined(CONFIG_USER_ONLY)
9fddaa0c 2297 RET_PRIVREG(ctx);
9a64fbe4
FB		 2298#else
2299 if (!ctx->supervisor) {
9fddaa0c
FB		 2300 RET_PRIVREG(ctx);
2301 return;
9a64fbe4
FB		 2302 }
2303 gen_op_load_gpr_T0(rS(ctx->opcode));
2304 gen_op_store_sr(SR(ctx->opcode));
9fddaa0c 2305#if 0
9a64fbe4 2306 gen_op_tlbia();
9fddaa0c
FB		 2307 RET_MTMSR(ctx);
2308#endif
9a64fbe4 2309#endif
79aceca5
FB		 2310}
2311
2312/* mtsrin */
9a64fbe4 2313GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 2314{
9a64fbe4 2315#if defined(CONFIG_USER_ONLY)
9fddaa0c 2316 RET_PRIVREG(ctx);
9a64fbe4
FB		 2317#else
2318 if (!ctx->supervisor) {
9fddaa0c
FB		 2319 RET_PRIVREG(ctx);
2320 return;
9a64fbe4
FB		 2321 }
2322 gen_op_load_gpr_T0(rS(ctx->opcode));
2323 gen_op_load_gpr_T1(rB(ctx->opcode));
2324 gen_op_store_srin();
2325 gen_op_tlbia();
2326#endif
79aceca5
FB		 2327}
2328
2329/*** Lookaside buffer management ***/
2330/* Optional & supervisor only: */
2331/* tlbia */
9a64fbe4 2332GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
79aceca5 2333{
9a64fbe4 2334#if defined(CONFIG_USER_ONLY)
9fddaa0c 2335 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2336#else
2337 if (!ctx->supervisor) {
9fddaa0c
FB		 2338 if (loglevel)
2339 fprintf(logfile, "%s: ! supervisor\n", __func__);
2340 RET_PRIVOPC(ctx);
2341 return;
9a64fbe4
FB		 2342 }
2343 gen_op_tlbia();
2344#endif
79aceca5
FB		 2345}
2346
2347/* tlbie */
9a64fbe4 2348GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
79aceca5 2349{
9a64fbe4 2350#if defined(CONFIG_USER_ONLY)
9fddaa0c 2351 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2352#else
2353 if (!ctx->supervisor) {
9fddaa0c
FB		 2354 RET_PRIVOPC(ctx);
2355 return;
9a64fbe4
FB		 2356 }
2357 gen_op_load_gpr_T0(rB(ctx->opcode));
2358 gen_op_tlbie();
2359#endif
79aceca5
FB		 2360}
2361
2362/* tlbsync */
e63c59cb 2363GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
79aceca5 2364{
9a64fbe4 2365#if defined(CONFIG_USER_ONLY)
9fddaa0c 2366 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2367#else
2368 if (!ctx->supervisor) {
9fddaa0c
FB		 2369 RET_PRIVOPC(ctx);
2370 return;
9a64fbe4
FB		 2371 }
2372 /* This has no effect: it should ensure that all previous
2373 * tlbie have completed
2374 */
2375#endif
79aceca5
FB		 2376}
2377
2378/*** External control ***/
2379/* Optional: */
2380/* eciwx */
9a64fbe4
FB		 2381#if defined(CONFIG_USER_ONLY)
2382#define op_eciwx() gen_op_eciwx_raw()
2383#define op_ecowx() gen_op_ecowx_raw()
2384#else
2385#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2386#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2387static GenOpFunc *gen_op_eciwx[] = {
2388 &gen_op_eciwx_user,
2389 &gen_op_eciwx_kernel,
2390};
2391static GenOpFunc *gen_op_ecowx[] = {
2392 &gen_op_ecowx_user,
2393 &gen_op_ecowx_kernel,
2394};
2395#endif
2396
79aceca5
FB		 2397GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2398{
9a64fbe4
FB		 2399 /* Should check EAR[E] & alignment ! */
2400 if (rA(ctx->opcode) == 0) {
2401 gen_op_load_gpr_T0(rB(ctx->opcode));
2402 } else {
2403 gen_op_load_gpr_T0(rA(ctx->opcode));
2404 gen_op_load_gpr_T1(rB(ctx->opcode));
2405 gen_op_add();
2406 }
2407 op_eciwx();
2408 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2409}
2410
2411/* ecowx */
2412GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2413{
9a64fbe4
FB		 2414 /* Should check EAR[E] & alignment ! */
2415 if (rA(ctx->opcode) == 0) {
2416 gen_op_load_gpr_T0(rB(ctx->opcode));
2417 } else {
2418 gen_op_load_gpr_T0(rA(ctx->opcode));
2419 gen_op_load_gpr_T1(rB(ctx->opcode));
2420 gen_op_add();
2421 }
2422 gen_op_load_gpr_T2(rS(ctx->opcode));
2423 op_ecowx();
79aceca5
FB		 2424}
2425
2426/* End opcode list */
2427GEN_OPCODE_MARK(end);
2428
2429/*****************************************************************************/
9a64fbe4 2430#include <stdlib.h>
79aceca5 2431#include <string.h>
9a64fbe4
FB		 2432
2433int fflush (FILE *stream);
79aceca5
FB		 2434
2435/* Main ppc opcodes table:
2436 * at init, all opcodes are invalids
2437 */
2438static opc_handler_t *ppc_opcodes[0x40];
2439
2440/* Opcode types */
2441enum {
2442 PPC_DIRECT = 0, /* Opcode routine */
2443 PPC_INDIRECT = 1, /* Indirect opcode table */
2444};
2445
2446static inline int is_indirect_opcode (void *handler)
2447{
2448 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2449}
2450
2451static inline opc_handler_t **ind_table(void *handler)
2452{
2453 return (opc_handler_t **)((unsigned long)handler & ~3);
2454}
2455
9a64fbe4 2456/* Instruction table creation */
79aceca5
FB		 2457/* Opcodes tables creation */
2458static void fill_new_table (opc_handler_t **table, int len)
2459{
2460 int i;
2461
2462 for (i = 0; i < len; i++)
2463 table[i] = &invalid_handler;
2464}
2465
2466static int create_new_table (opc_handler_t **table, unsigned char idx)
2467{
2468 opc_handler_t **tmp;
2469
2470 tmp = malloc(0x20 * sizeof(opc_handler_t));
2471 if (tmp == NULL)
2472 return -1;
2473 fill_new_table(tmp, 0x20);
2474 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2475
2476 return 0;
2477}
2478
2479static int insert_in_table (opc_handler_t **table, unsigned char idx,
2480 opc_handler_t *handler)
2481{
2482 if (table[idx] != &invalid_handler)
2483 return -1;
2484 table[idx] = handler;
2485
2486 return 0;
2487}
2488
9a64fbe4
FB		 2489static int register_direct_insn (opc_handler_t **ppc_opcodes,
2490 unsigned char idx, opc_handler_t *handler)
79aceca5
FB		 2491{
2492 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9a64fbe4 2493 printf("*** ERROR: opcode %02x already assigned in main "
79aceca5
FB		 2494 "opcode table\n", idx);
2495 return -1;
2496 }
2497
2498 return 0;
2499}
2500
2501static int register_ind_in_table (opc_handler_t **table,
2502 unsigned char idx1, unsigned char idx2,
2503 opc_handler_t *handler)
2504{
2505 if (table[idx1] == &invalid_handler) {
2506 if (create_new_table(table, idx1) < 0) {
9a64fbe4 2507 printf("*** ERROR: unable to create indirect table "
79aceca5
FB		 2508 "idx=%02x\n", idx1);
2509 return -1;
2510 }
2511 } else {
2512 if (!is_indirect_opcode(table[idx1])) {
9a64fbe4 2513 printf("*** ERROR: idx %02x already assigned to a direct "
79aceca5
FB		 2514 "opcode\n", idx1);
2515 return -1;
2516 }
2517 }
2518 if (handler != NULL &&
2519 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9a64fbe4 2520 printf("*** ERROR: opcode %02x already assigned in "
79aceca5
FB		 2521 "opcode table %02x\n", idx2, idx1);
2522 return -1;
2523 }
2524
2525 return 0;
2526}
2527
9a64fbe4
FB		 2528static int register_ind_insn (opc_handler_t **ppc_opcodes,
2529 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2530 opc_handler_t *handler)
2531{
2532 int ret;
2533
2534 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2535
2536 return ret;
2537}
2538
9a64fbe4
FB		 2539static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2540 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2541 unsigned char idx3, opc_handler_t *handler)
2542{
2543 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9a64fbe4 2544 printf("*** ERROR: unable to join indirect table idx "
79aceca5
FB		 2545 "[%02x-%02x]\n", idx1, idx2);
2546 return -1;
2547 }
2548 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2549 handler) < 0) {
9a64fbe4 2550 printf("*** ERROR: unable to insert opcode "
79aceca5
FB		 2551 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2552 return -1;
2553 }
2554
2555 return 0;
2556}
2557
9a64fbe4 2558static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
79aceca5
FB		 2559{
2560 if (insn->opc2 != 0xFF) {
2561 if (insn->opc3 != 0xFF) {
9a64fbe4
FB		 2562 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2563 insn->opc3, &insn->handler) < 0)
79aceca5
FB		 2564 return -1;
2565 } else {
9a64fbe4
FB		 2566 if (register_ind_insn(ppc_opcodes, insn->opc1,
2567 insn->opc2, &insn->handler) < 0)
79aceca5
FB		 2568 return -1;
2569 }
2570 } else {
9a64fbe4 2571 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
79aceca5
FB		 2572 return -1;
2573 }
2574
2575 return 0;
2576}
2577
2578static int test_opcode_table (opc_handler_t **table, int len)
2579{
2580 int i, count, tmp;
2581
2582 for (i = 0, count = 0; i < len; i++) {
2583 /* Consistency fixup */
2584 if (table[i] == NULL)
2585 table[i] = &invalid_handler;
2586 if (table[i] != &invalid_handler) {
2587 if (is_indirect_opcode(table[i])) {
2588 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2589 if (tmp == 0) {
2590 free(table[i]);
2591 table[i] = &invalid_handler;
2592 } else {
2593 count++;
2594 }
2595 } else {
2596 count++;
2597 }
2598 }
2599 }
2600
2601 return count;
2602}
2603
9a64fbe4 2604static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
79aceca5
FB		 2605{
2606 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9a64fbe4 2607 printf("*** WARNING: no opcode defined !\n");
79aceca5
FB		 2608}
2609
9a64fbe4 2610#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
79aceca5
FB		 2611#define SPR_UR SPR_RIGHTS(0, 0)
2612#define SPR_UW SPR_RIGHTS(1, 0)
2613#define SPR_SR SPR_RIGHTS(0, 1)
2614#define SPR_SW SPR_RIGHTS(1, 1)
2615
2616#define spr_set_rights(spr, rights) \
2617do { \
2618 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2619} while (0)
2620
9a64fbe4 2621static void init_spr_rights (uint32_t pvr)
79aceca5
FB		 2622{
2623 /* XER (SPR 1) */
9a64fbe4 2624 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2625 /* LR (SPR 8) */
9a64fbe4 2626 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2627 /* CTR (SPR 9) */
9a64fbe4 2628 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2629 /* TBL (SPR 268) */
9a64fbe4 2630 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
79aceca5 2631 /* TBU (SPR 269) */
9a64fbe4 2632 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
79aceca5 2633 /* DSISR (SPR 18) */
9a64fbe4 2634 spr_set_rights(DSISR, SPR_SR | SPR_SW);
79aceca5 2635 /* DAR (SPR 19) */
9a64fbe4 2636 spr_set_rights(DAR, SPR_SR | SPR_SW);
79aceca5 2637 /* DEC (SPR 22) */
9a64fbe4 2638 spr_set_rights(DECR, SPR_SR | SPR_SW);
79aceca5 2639 /* SDR1 (SPR 25) */
9a64fbe4
FB		 2640 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2641 /* SRR0 (SPR 26) */
2642 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2643 /* SRR1 (SPR 27) */
2644 spr_set_rights(SRR1, SPR_SR | SPR_SW);
79aceca5 2645 /* SPRG0 (SPR 272) */
9a64fbe4 2646 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
79aceca5 2647 /* SPRG1 (SPR 273) */
9a64fbe4 2648 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
79aceca5 2649 /* SPRG2 (SPR 274) */
9a64fbe4 2650 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
79aceca5 2651 /* SPRG3 (SPR 275) */
9a64fbe4 2652 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
79aceca5 2653 /* ASR (SPR 280) */
9a64fbe4 2654 spr_set_rights(ASR, SPR_SR | SPR_SW);
79aceca5 2655 /* EAR (SPR 282) */
9a64fbe4
FB		 2656 spr_set_rights(EAR, SPR_SR | SPR_SW);
2657 /* TBL (SPR 284) */
2658 spr_set_rights(O_TBL, SPR_SW);
2659 /* TBU (SPR 285) */
2660 spr_set_rights(O_TBU, SPR_SW);
2661 /* PVR (SPR 287) */
2662 spr_set_rights(PVR, SPR_SR);
79aceca5 2663 /* IBAT0U (SPR 528) */
9a64fbe4 2664 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
79aceca5 2665 /* IBAT0L (SPR 529) */
9a64fbe4 2666 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
79aceca5 2667 /* IBAT1U (SPR 530) */
9a64fbe4 2668 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
79aceca5 2669 /* IBAT1L (SPR 531) */
9a64fbe4 2670 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
79aceca5 2671 /* IBAT2U (SPR 532) */
9a64fbe4 2672 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
79aceca5 2673 /* IBAT2L (SPR 533) */
9a64fbe4 2674 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
79aceca5 2675 /* IBAT3U (SPR 534) */
9a64fbe4 2676 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
79aceca5 2677 /* IBAT3L (SPR 535) */
9a64fbe4 2678 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
79aceca5 2679 /* DBAT0U (SPR 536) */
9a64fbe4 2680 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
79aceca5 2681 /* DBAT0L (SPR 537) */
9a64fbe4 2682 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
79aceca5 2683 /* DBAT1U (SPR 538) */
9a64fbe4 2684 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
79aceca5 2685 /* DBAT1L (SPR 539) */
9a64fbe4 2686 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
79aceca5 2687 /* DBAT2U (SPR 540) */
9a64fbe4 2688 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
79aceca5 2689 /* DBAT2L (SPR 541) */
9a64fbe4 2690 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
79aceca5 2691 /* DBAT3U (SPR 542) */
9a64fbe4 2692 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
79aceca5 2693 /* DBAT3L (SPR 543) */
9a64fbe4 2694 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
79aceca5 2695 /* DABR (SPR 1013) */
9a64fbe4 2696 spr_set_rights(DABR, SPR_SR | SPR_SW);
79aceca5 2697 /* FPECR (SPR 1022) */
9a64fbe4 2698 spr_set_rights(FPECR, SPR_SR | SPR_SW);
79aceca5 2699 /* PIR (SPR 1023) */
9a64fbe4
FB		 2700 spr_set_rights(PIR, SPR_SR | SPR_SW);
2701 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2702 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2703 (pvr & 0xFFFF0000) == 0x70000000) {
2704 /* HID0 */
2705 spr_set_rights(SPR_ENCODE(1008), SPR_SR | SPR_SW);
2706 /* HID1 */
2707 spr_set_rights(SPR_ENCODE(1009), SPR_SR | SPR_SW);
2708 /* IABR */
2709 spr_set_rights(SPR_ENCODE(1010), SPR_SR | SPR_SW);
2710 /* ICTC */
2711 spr_set_rights(SPR_ENCODE(1019), SPR_SR | SPR_SW);
2712 /* L2CR */
2713 spr_set_rights(SPR_ENCODE(1017), SPR_SR | SPR_SW);
2714 /* MMCR0 */
2715 spr_set_rights(SPR_ENCODE(952), SPR_SR | SPR_SW);
2716 /* MMCR1 */
2717 spr_set_rights(SPR_ENCODE(956), SPR_SR | SPR_SW);
2718 /* PMC1 */
2719 spr_set_rights(SPR_ENCODE(953), SPR_SR | SPR_SW);
2720 /* PMC2 */
2721 spr_set_rights(SPR_ENCODE(954), SPR_SR | SPR_SW);
2722 /* PMC3 */
2723 spr_set_rights(SPR_ENCODE(957), SPR_SR | SPR_SW);
2724 /* PMC4 */
2725 spr_set_rights(SPR_ENCODE(958), SPR_SR | SPR_SW);
2726 /* SIA */
2727 spr_set_rights(SPR_ENCODE(955), SPR_SR | SPR_SW);
2728 /* THRM1 */
2729 spr_set_rights(SPR_ENCODE(1020), SPR_SR | SPR_SW);
2730 /* THRM2 */
2731 spr_set_rights(SPR_ENCODE(1021), SPR_SR | SPR_SW);
2732 /* THRM3 */
2733 spr_set_rights(SPR_ENCODE(1022), SPR_SR | SPR_SW);
2734 /* UMMCR0 */
2735 spr_set_rights(SPR_ENCODE(936), SPR_UR | SPR_UW);
2736 /* UMMCR1 */
2737 spr_set_rights(SPR_ENCODE(940), SPR_UR | SPR_UW);
2738 /* UPMC1 */
2739 spr_set_rights(SPR_ENCODE(937), SPR_UR | SPR_UW);
2740 /* UPMC2 */
2741 spr_set_rights(SPR_ENCODE(938), SPR_UR | SPR_UW);
2742 /* UPMC3 */
2743 spr_set_rights(SPR_ENCODE(941), SPR_UR | SPR_UW);
2744 /* UPMC4 */
2745 spr_set_rights(SPR_ENCODE(942), SPR_UR | SPR_UW);
2746 /* USIA */
2747 spr_set_rights(SPR_ENCODE(939), SPR_UR | SPR_UW);
2748 }
2749 /* MPC755 has special registers */
2750 if (pvr == 0x00083100) {
2751 /* SPRG4 */
2752 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2753 /* SPRG5 */
2754 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2755 /* SPRG6 */
2756 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2757 /* SPRG7 */
2758 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2759 /* IBAT4U */
2760 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2761 /* IBAT4L */
2762 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2763 /* IBAT5U */
2764 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2765 /* IBAT5L */
2766 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2767 /* IBAT6U */
2768 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2769 /* IBAT6L */
2770 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2771 /* IBAT7U */
2772 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2773 /* IBAT7L */
2774 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2775 /* DBAT4U */
2776 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2777 /* DBAT4L */
2778 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2779 /* DBAT5U */
2780 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2781 /* DBAT5L */
2782 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2783 /* DBAT6U */
2784 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2785 /* DBAT6L */
2786 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2787 /* DBAT7U */
2788 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2789 /* DBAT7L */
2790 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2791 /* DMISS */
2792 spr_set_rights(SPR_ENCODE(976), SPR_SR | SPR_SW);
2793 /* DCMP */
2794 spr_set_rights(SPR_ENCODE(977), SPR_SR | SPR_SW);
2795 /* DHASH1 */
2796 spr_set_rights(SPR_ENCODE(978), SPR_SR | SPR_SW);
2797 /* DHASH2 */
2798 spr_set_rights(SPR_ENCODE(979), SPR_SR | SPR_SW);
2799 /* IMISS */
2800 spr_set_rights(SPR_ENCODE(980), SPR_SR | SPR_SW);
2801 /* ICMP */
2802 spr_set_rights(SPR_ENCODE(981), SPR_SR | SPR_SW);
2803 /* RPA */
2804 spr_set_rights(SPR_ENCODE(982), SPR_SR | SPR_SW);
2805 /* HID2 */
2806 spr_set_rights(SPR_ENCODE(1011), SPR_SR | SPR_SW);
2807 /* L2PM */
2808 spr_set_rights(SPR_ENCODE(1016), SPR_SR | SPR_SW);
2809 }
79aceca5
FB		 2810}
2811
9a64fbe4
FB		 2812/*****************************************************************************/
2813/* PPC "main stream" common instructions (no optional ones) */
79aceca5
FB		 2814
2815typedef struct ppc_proc_t {
2816 int flags;
2817 void *specific;
2818} ppc_proc_t;
2819
2820typedef struct ppc_def_t {
2821 unsigned long pvr;
2822 unsigned long pvr_mask;
2823 ppc_proc_t *proc;
2824} ppc_def_t;
2825
2826static ppc_proc_t ppc_proc_common = {
2827 .flags = PPC_COMMON,
2828 .specific = NULL,
2829};
2830
9a64fbe4
FB		 2831static ppc_proc_t ppc_proc_G3 = {
2832 .flags = PPC_750,
2833 .specific = NULL,
2834};
2835
79aceca5
FB		 2836static ppc_def_t ppc_defs[] =
2837{
9a64fbe4
FB		 2838 /* MPC740/745/750/755 (G3) */
2839 {
2840 .pvr = 0x00080000,
2841 .pvr_mask = 0xFFFF0000,
2842 .proc = &ppc_proc_G3,
2843 },
2844 /* IBM 750FX (G3 embedded) */
2845 {
2846 .pvr = 0x70000000,
2847 .pvr_mask = 0xFFFF0000,
2848 .proc = &ppc_proc_G3,
2849 },
2850 /* Fallback (generic PPC) */
79aceca5
FB		 2851 {
2852 .pvr = 0x00000000,
2853 .pvr_mask = 0x00000000,
2854 .proc = &ppc_proc_common,
2855 },
2856};
2857
9a64fbe4 2858static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
79aceca5
FB		 2859{
2860 opcode_t *opc;
2861 int i, flags;
2862
2863 fill_new_table(ppc_opcodes, 0x40);
2864 for (i = 0; ; i++) {
2865 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2866 (pvr & ppc_defs[i].pvr_mask)) {
2867 flags = ppc_defs[i].proc->flags;
2868 break;
2869 }
2870 }
2871
2872 for (opc = &opc_start + 1; opc != &opc_end; opc++) {
9a64fbe4
FB		 2873 if ((opc->handler.type & flags) != 0)
2874 if (register_insn(ppc_opcodes, opc) < 0) {
2875 printf("*** ERROR initializing PPC instruction "
79aceca5
FB		 2876 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2877 opc->opc3);
2878 return -1;
2879 }
2880 }
9a64fbe4 2881 fix_opcode_tables(ppc_opcodes);
79aceca5
FB		 2882
2883 return 0;
2884}
2885
9a64fbe4 2886
79aceca5 2887/*****************************************************************************/
9a64fbe4 2888/* Misc PPC helpers */
79aceca5
FB		 2889
2890void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags)
2891{
2892 int i;
2893
9a64fbe4
FB		 2894 fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
2895 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
a541f297 2896 _load_xer(env), _load_msr(env));
79aceca5
FB		 2897 for (i = 0; i < 32; i++) {
2898 if ((i & 7) == 0)
9a64fbe4
FB		 2899 fprintf(f, "GPR%02d:", i);
2900 fprintf(f, " %08x", env->gpr[i]);
79aceca5 2901 if ((i & 7) == 7)
9a64fbe4 2902 fprintf(f, "\n");
79aceca5 2903 }
9a64fbe4 2904 fprintf(f, "CR: 0x");
79aceca5 2905 for (i = 0; i < 8; i++)
9a64fbe4
FB		 2906 fprintf(f, "%01x", env->crf[i]);
2907 fprintf(f, " [");
79aceca5
FB		 2908 for (i = 0; i < 8; i++) {
2909 char a = '-';
79aceca5
FB		 2910 if (env->crf[i] & 0x08)
2911 a = 'L';
2912 else if (env->crf[i] & 0x04)
2913 a = 'G';
2914 else if (env->crf[i] & 0x02)
2915 a = 'E';
9a64fbe4 2916 fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
79aceca5 2917 }
9a64fbe4 2918 fprintf(f, " ] ");
9fddaa0c
FB		 2919 fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
2920 cpu_ppc_load_tbl(env));
79aceca5
FB		 2921 for (i = 0; i < 16; i++) {
2922 if ((i & 3) == 0)
9a64fbe4
FB		 2923 fprintf(f, "FPR%02d:", i);
2924 fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
79aceca5 2925 if ((i & 3) == 3)
9a64fbe4 2926 fprintf(f, "\n");
79aceca5 2927 }
9fddaa0c
FB		 2928 fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
2929 env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env));
9a64fbe4
FB		 2930 fprintf(f, "reservation 0x%08x\n", env->reserve);
2931 fflush(f);
79aceca5
FB		 2932}
2933
9a64fbe4
FB		 2934#if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
2935int setup_machine (CPUPPCState *env, uint32_t mid);
2936#endif
2937
79aceca5
FB		 2938CPUPPCState *cpu_ppc_init(void)
2939{
2940 CPUPPCState *env;
2941
2942 cpu_exec_init();
2943
2944 env = malloc(sizeof(CPUPPCState));
2945 if (!env)
2946 return NULL;
2947 memset(env, 0, sizeof(CPUPPCState));
9a64fbe4
FB		 2948#if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
2949 setup_machine(env, 0);
2950#else
2951// env->spr[PVR] = 0; /* Basic PPC */
2952 env->spr[PVR] = 0x00080100; /* G3 CPU */
2953// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
2954// env->spr[PVR] = 0x00070100; /* IBM 750FX */
2955#endif
9a64fbe4 2956 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
79aceca5 2957 return NULL;
9a64fbe4 2958 init_spr_rights(env->spr[PVR]);
ad081323 2959 tlb_flush(env, 1);
9a64fbe4
FB		 2960#if defined (DO_SINGLE_STEP)
2961 /* Single step trace mode */
2962 msr_se = 1;
2963#endif
2964#if defined(CONFIG_USER_ONLY)
2965 msr_pr = 1;
2966#endif
a541f297 2967 env->access_type = ACCESS_INT;
79aceca5
FB		 2968
2969 return env;
2970}
2971
2972void cpu_ppc_close(CPUPPCState *env)
2973{
2974 /* Should also remove all opcode tables... */
2975 free(env);
2976}
2977
9a64fbe4 2978/*****************************************************************************/
9a64fbe4
FB		 2979int print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr,
2980 int dialect);
2981
79aceca5
FB		 2982int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
2983 int search_pc)
2984{
9fddaa0c 2985 DisasContext ctx, *ctxp = &ctx;
79aceca5
FB		 2986 opc_handler_t **table, *handler;
2987 uint32_t pc_start;
2988 uint16_t *gen_opc_end;
2989 int j, lj = -1;
79aceca5
FB		 2990
2991 pc_start = tb->pc;
2992 gen_opc_ptr = gen_opc_buf;
2993 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2994 gen_opparam_ptr = gen_opparam_buf;
046d6672 2995 ctx.nip = pc_start;
79aceca5 2996 ctx.tb = tb;
9a64fbe4
FB		 2997 ctx.exception = EXCP_NONE;
2998#if defined(CONFIG_USER_ONLY)
2999 ctx.mem_idx = 0;
3000#else
3001 ctx.supervisor = 1 - msr_pr;
3002 ctx.mem_idx = (1 - msr_pr);
3003#endif
3004#if defined (DO_SINGLE_STEP)
3005 /* Single step trace mode */
3006 msr_se = 1;
3007#endif
a541f297 3008 env->access_type = ACCESS_CODE;
9a64fbe4
FB		 3009 /* Set env in case of segfault during code fetch */
3010 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
79aceca5
FB		 3011 if (search_pc) {
3012 if (loglevel > 0)
3013 fprintf(logfile, "Search PC...\n");
3014 j = gen_opc_ptr - gen_opc_buf;
3015 if (lj < j) {
3016 lj++;
3017 while (lj < j)
3018 gen_opc_instr_start[lj++] = 0;
046d6672 3019 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 3020 gen_opc_instr_start[lj] = 1;
3021 }
3022 }
9fddaa0c
FB		 3023#if defined PPC_DEBUG_DISAS
3024 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 3025 fprintf(logfile, "----------------\n");
046d6672 3026 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
9a64fbe4
FB		 3027 ctx.nip, 1 - msr_pr, msr_ir);
3028 }
3029#endif
046d6672 3030 ctx.opcode = ldl_code((void *)ctx.nip);
9fddaa0c
FB		 3031#if defined PPC_DEBUG_DISAS
3032 if (loglevel & CPU_LOG_TB_IN_ASM) {
9a64fbe4
FB		 3033 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3034 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3035 opc3(ctx.opcode));
79aceca5
FB		 3036 }
3037#endif
046d6672 3038 ctx.nip += 4;
79aceca5
FB		 3039 table = ppc_opcodes;
3040 handler = table[opc1(ctx.opcode)];
3041 if (is_indirect_opcode(handler)) {
3042 table = ind_table(handler);
3043 handler = table[opc2(ctx.opcode)];
3044 if (is_indirect_opcode(handler)) {
3045 table = ind_table(handler);
3046 handler = table[opc3(ctx.opcode)];
3047 }
3048 }
3049 /* Is opcode *REALLY* valid ? */
3050 if ((ctx.opcode & handler->inval) != 0) {
3051 if (loglevel > 0) {
3052 if (handler->handler == &gen_invalid) {
3053 fprintf(logfile, "invalid/unsupported opcode: "
046d6672 3054 "%02x -%02x - %02x (%08x) 0x%08x\n",
9a64fbe4 3055 opc1(ctx.opcode), opc2(ctx.opcode),
046d6672 3056 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4);
79aceca5
FB		 3057 } else {
3058 fprintf(logfile, "invalid bits: %08x for opcode: "
046d6672 3059 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
79aceca5
FB		 3060 ctx.opcode & handler->inval, opc1(ctx.opcode),
3061 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3062 ctx.opcode, ctx.nip - 4);
79aceca5 3063 }
9a64fbe4
FB		 3064 } else {
3065 if (handler->handler == &gen_invalid) {
3066 printf("invalid/unsupported opcode: "
046d6672 3067 "%02x -%02x - %02x (%08x) 0x%08x\n",
9a64fbe4 3068 opc1(ctx.opcode), opc2(ctx.opcode),
046d6672 3069 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 3070 } else {
3071 printf("invalid bits: %08x for opcode: "
046d6672 3072 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
9a64fbe4
FB		 3073 ctx.opcode & handler->inval, opc1(ctx.opcode),
3074 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3075 ctx.opcode, ctx.nip - 4);
9a64fbe4 3076 }
79aceca5 3077 }
9a64fbe4 3078 (*gen_invalid)(&ctx);
79aceca5 3079 } else {
9a64fbe4 3080 (*(handler->handler))(&ctx);
79aceca5 3081 }
9a64fbe4
FB		 3082 /* Check trace mode exceptions */
3083 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3084 /* Check in single step trace mode
3085 * we need to stop except if:
3086 * - rfi, trap or syscall
3087 * - first instruction of an exception handler
3088 */
046d6672
FB		 3089 (msr_se && (ctx.nip < 0x100 ||
3090 ctx.nip > 0xF00 ||
3091 (ctx.nip & 0xFC) != 0x04) &&
9a64fbe4
FB		 3092 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3093 ctx.exception != EXCP_TRAP)) {
9fddaa0c 3094 RET_EXCP(ctxp, EXCP_TRACE, 0);
9a64fbe4 3095 }
a541f297 3096 /* if we reach a page boundary, stop generation */
046d6672 3097 if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
9fddaa0c 3098 RET_EXCP(ctxp, EXCP_BRANCH, 0);
79aceca5 3099 }
9a64fbe4 3100 }
9fddaa0c
FB		 3101 if (ctx.exception == EXCP_NONE) {
3102 gen_op_b((unsigned long)ctx.tb, ctx.nip);
3103 } else if (ctx.exception != EXCP_BRANCH) {
3104 gen_op_set_T0(0);
9a64fbe4
FB		 3105 }
3106#if 1
79aceca5
FB		 3107 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3108 * do bad business and then qemu crashes !
3109 */
3110 gen_op_set_T0(0);
9a64fbe4 3111#endif
79aceca5
FB		 3112 /* Generate the return instruction */
3113 gen_op_exit_tb();
3114 *gen_opc_ptr = INDEX_op_end;
9a64fbe4
FB		 3115 if (search_pc) {
3116 j = gen_opc_ptr - gen_opc_buf;
3117 lj++;
3118 while (lj <= j)
3119 gen_opc_instr_start[lj++] = 0;
79aceca5 3120 tb->size = 0;
985a19d6 3121#if 0
9a64fbe4
FB		 3122 if (loglevel > 0) {
3123 page_dump(logfile);
3124 }
985a19d6 3125#endif
9a64fbe4 3126 } else {
046d6672 3127 tb->size = ctx.nip - pc_start;
9a64fbe4 3128 }
a541f297 3129 env->access_type = ACCESS_INT;
79aceca5 3130#ifdef DEBUG_DISAS
9fddaa0c 3131 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4
FB		 3132 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
3133 cpu_ppc_dump_state(env, logfile, 0);
9fddaa0c
FB		 3134 }
3135 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 3136 fprintf(logfile, "IN: %s\n", lookup_symbol((void *)pc_start));
046d6672 3137 disas(logfile, (void *)pc_start, ctx.nip - pc_start, 0, 0);
79aceca5 3138 fprintf(logfile, "\n");
9fddaa0c
FB		 3139 }
3140 if (loglevel & CPU_LOG_TB_OP) {
79aceca5
FB		 3141 fprintf(logfile, "OP:\n");
3142 dump_ops(gen_opc_buf, gen_opparam_buf);
3143 fprintf(logfile, "\n");
3144 }
3145#endif
3146
3147 return 0;
3148}
3149
9a64fbe4 3150int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3151{
3152 return gen_intermediate_code_internal(env, tb, 0);
3153}
3154
9a64fbe4 3155int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3156{
3157 return gen_intermediate_code_internal(env, tb, 1);
3158}
Qemu copy for testing