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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
79aceca5 | 21 | #include "cpu.h" |
76cad711 | 22 | #include "disas/disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
1de7afc9 | 24 | #include "qemu/host-utils.h" |
79aceca5 | 25 | |
a7812ae4 PB |
26 | #include "helper.h" |
27 | #define GEN_HELPER 1 | |
28 | #include "helper.h" | |
29 | ||
8cbcb4fa AJ |
30 | #define CPU_SINGLE_STEP 0x1 |
31 | #define CPU_BRANCH_STEP 0x2 | |
32 | #define GDBSTUB_SINGLE_STEP 0x4 | |
33 | ||
a750fc0b | 34 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 35 | //#define PPC_DEBUG_DISAS |
76a66253 | 36 | //#define DO_PPC_STATISTICS |
79aceca5 | 37 | |
d12d51d5 | 38 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 39 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
40 | #else |
41 | # define LOG_DISAS(...) do { } while (0) | |
42 | #endif | |
a750fc0b JM |
43 | /*****************************************************************************/ |
44 | /* Code translation helpers */ | |
c53be334 | 45 | |
f78fb44e | 46 | /* global register indexes */ |
a7812ae4 | 47 | static TCGv_ptr cpu_env; |
1d542695 | 48 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
f78fb44e | 49 | #if !defined(TARGET_PPC64) |
1d542695 | 50 | + 10*4 + 22*5 /* SPE GPRh */ |
f78fb44e | 51 | #endif |
a5e26afa | 52 | + 10*4 + 22*5 /* FPR */ |
47e4661c AJ |
53 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
54 | + 8*5 /* CRF */]; | |
f78fb44e AJ |
55 | static TCGv cpu_gpr[32]; |
56 | #if !defined(TARGET_PPC64) | |
57 | static TCGv cpu_gprh[32]; | |
58 | #endif | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fpr[32]; |
60 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
61 | static TCGv_i32 cpu_crf[8]; | |
bd568f18 | 62 | static TCGv cpu_nip; |
6527f6ea | 63 | static TCGv cpu_msr; |
cfdcd37a AJ |
64 | static TCGv cpu_ctr; |
65 | static TCGv cpu_lr; | |
697ab892 DG |
66 | #if defined(TARGET_PPC64) |
67 | static TCGv cpu_cfar; | |
68 | #endif | |
da91a00f | 69 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 70 | static TCGv cpu_reserve; |
30304420 | 71 | static TCGv cpu_fpscr; |
a7859e89 | 72 | static TCGv_i32 cpu_access_type; |
f78fb44e | 73 | |
022c62cb | 74 | #include "exec/gen-icount.h" |
2e70f6ef PB |
75 | |
76 | void ppc_translate_init(void) | |
77 | { | |
f78fb44e AJ |
78 | int i; |
79 | char* p; | |
2dc766da | 80 | size_t cpu_reg_names_size; |
b2437bf2 | 81 | static int done_init = 0; |
f78fb44e | 82 | |
2e70f6ef PB |
83 | if (done_init) |
84 | return; | |
f78fb44e | 85 | |
a7812ae4 | 86 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 87 | |
f78fb44e | 88 | p = cpu_reg_names; |
2dc766da | 89 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
90 | |
91 | for (i = 0; i < 8; i++) { | |
2dc766da | 92 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 | 93 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 94 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 95 | p += 5; |
2dc766da | 96 | cpu_reg_names_size -= 5; |
47e4661c AJ |
97 | } |
98 | ||
f78fb44e | 99 | for (i = 0; i < 32; i++) { |
2dc766da | 100 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 101 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 102 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 103 | p += (i < 10) ? 3 : 4; |
2dc766da | 104 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
f78fb44e | 105 | #if !defined(TARGET_PPC64) |
2dc766da | 106 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
a7812ae4 | 107 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 108 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 109 | p += (i < 10) ? 4 : 5; |
2dc766da | 110 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 111 | #endif |
1d542695 | 112 | |
2dc766da | 113 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 | 114 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 115 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 116 | p += (i < 10) ? 4 : 5; |
2dc766da | 117 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 118 | |
2dc766da | 119 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 120 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 121 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 122 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 123 | #else |
a7812ae4 | 124 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 125 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 126 | #endif |
1d542695 | 127 | p += (i < 10) ? 6 : 7; |
2dc766da | 128 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 129 | |
2dc766da | 130 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 131 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 132 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 133 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 134 | #else |
a7812ae4 | 135 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 136 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 137 | #endif |
1d542695 | 138 | p += (i < 10) ? 6 : 7; |
2dc766da | 139 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
f78fb44e | 140 | } |
f10dc08e | 141 | |
a7812ae4 | 142 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 143 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 144 | |
6527f6ea | 145 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 146 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 147 | |
a7812ae4 | 148 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 149 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 150 | |
a7812ae4 | 151 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 152 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 153 | |
697ab892 DG |
154 | #if defined(TARGET_PPC64) |
155 | cpu_cfar = tcg_global_mem_new(TCG_AREG0, | |
1328c2bf | 156 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
157 | #endif |
158 | ||
a7812ae4 | 159 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 160 | offsetof(CPUPPCState, xer), "xer"); |
da91a00f RH |
161 | cpu_so = tcg_global_mem_new(TCG_AREG0, |
162 | offsetof(CPUPPCState, so), "SO"); | |
163 | cpu_ov = tcg_global_mem_new(TCG_AREG0, | |
164 | offsetof(CPUPPCState, ov), "OV"); | |
165 | cpu_ca = tcg_global_mem_new(TCG_AREG0, | |
166 | offsetof(CPUPPCState, ca), "CA"); | |
3d7b417e | 167 | |
cf360a32 | 168 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 169 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 170 | "reserve_addr"); |
cf360a32 | 171 | |
30304420 DG |
172 | cpu_fpscr = tcg_global_mem_new(TCG_AREG0, |
173 | offsetof(CPUPPCState, fpscr), "fpscr"); | |
e1571908 | 174 | |
a7859e89 | 175 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 176 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 177 | |
f10dc08e | 178 | /* register helpers */ |
a7812ae4 | 179 | #define GEN_HELPER 2 |
f10dc08e AJ |
180 | #include "helper.h" |
181 | ||
2e70f6ef PB |
182 | done_init = 1; |
183 | } | |
184 | ||
79aceca5 FB |
185 | /* internal defines */ |
186 | typedef struct DisasContext { | |
187 | struct TranslationBlock *tb; | |
0fa85d43 | 188 | target_ulong nip; |
79aceca5 | 189 | uint32_t opcode; |
9a64fbe4 | 190 | uint32_t exception; |
3cc62370 FB |
191 | /* Routine used to access memory */ |
192 | int mem_idx; | |
76db3ba4 | 193 | int access_type; |
3cc62370 | 194 | /* Translation flags */ |
76db3ba4 | 195 | int le_mode; |
d9bce9d9 JM |
196 | #if defined(TARGET_PPC64) |
197 | int sf_mode; | |
697ab892 | 198 | int has_cfar; |
9a64fbe4 | 199 | #endif |
3cc62370 | 200 | int fpu_enabled; |
a9d9eb8f | 201 | int altivec_enabled; |
0487d6a8 | 202 | int spe_enabled; |
c227f099 | 203 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 204 | int singlestep_enabled; |
79aceca5 FB |
205 | } DisasContext; |
206 | ||
79482e5a RH |
207 | /* True when active word size < size of target_long. */ |
208 | #ifdef TARGET_PPC64 | |
209 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
210 | #else | |
211 | # define NARROW_MODE(C) 0 | |
212 | #endif | |
213 | ||
c227f099 | 214 | struct opc_handler_t { |
70560da7 FC |
215 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
216 | uint32_t inval1; | |
217 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
218 | uint32_t inval2; | |
9a64fbe4 | 219 | /* instruction type */ |
0487d6a8 | 220 | uint64_t type; |
a5858d7a AG |
221 | /* extended instruction type */ |
222 | uint64_t type2; | |
79aceca5 FB |
223 | /* handler */ |
224 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 225 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 226 | const char *oname; |
a750fc0b JM |
227 | #endif |
228 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
229 | uint64_t count; |
230 | #endif | |
3fc6c082 | 231 | }; |
79aceca5 | 232 | |
636aa200 | 233 | static inline void gen_reset_fpstatus(void) |
7c58044c | 234 | { |
8e703949 | 235 | gen_helper_reset_fpstatus(cpu_env); |
7c58044c JM |
236 | } |
237 | ||
636aa200 | 238 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 239 | { |
0f2f39c2 | 240 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 241 | |
7c58044c JM |
242 | if (set_fprf != 0) { |
243 | /* This case might be optimized later */ | |
0f2f39c2 | 244 | tcg_gen_movi_i32(t0, 1); |
8e703949 | 245 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
a7812ae4 | 246 | if (unlikely(set_rc)) { |
0f2f39c2 | 247 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 248 | } |
8e703949 | 249 | gen_helper_float_check_status(cpu_env); |
7c58044c JM |
250 | } else if (unlikely(set_rc)) { |
251 | /* We always need to compute fpcc */ | |
0f2f39c2 | 252 | tcg_gen_movi_i32(t0, 0); |
8e703949 | 253 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
0f2f39c2 | 254 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 255 | } |
af12906f | 256 | |
0f2f39c2 | 257 | tcg_temp_free_i32(t0); |
7c58044c JM |
258 | } |
259 | ||
636aa200 | 260 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 261 | { |
76db3ba4 AJ |
262 | if (ctx->access_type != access_type) { |
263 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
264 | ctx->access_type = access_type; | |
265 | } | |
a7859e89 AJ |
266 | } |
267 | ||
636aa200 | 268 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 269 | { |
e0c8f9ce RH |
270 | if (NARROW_MODE(ctx)) { |
271 | nip = (uint32_t)nip; | |
272 | } | |
273 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
274 | } |
275 | ||
636aa200 | 276 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
277 | { |
278 | TCGv_i32 t0, t1; | |
279 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
280 | gen_update_nip(ctx, ctx->nip); | |
281 | } | |
282 | t0 = tcg_const_i32(excp); | |
283 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 284 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
285 | tcg_temp_free_i32(t0); |
286 | tcg_temp_free_i32(t1); | |
287 | ctx->exception = (excp); | |
288 | } | |
e1833e1f | 289 | |
636aa200 | 290 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
291 | { |
292 | TCGv_i32 t0; | |
293 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
294 | gen_update_nip(ctx, ctx->nip); | |
295 | } | |
296 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 297 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
298 | tcg_temp_free_i32(t0); |
299 | ctx->exception = (excp); | |
300 | } | |
e1833e1f | 301 | |
636aa200 | 302 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
303 | { |
304 | TCGv_i32 t0; | |
5518f3a6 | 305 | |
ee2b3994 SB |
306 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
307 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
5518f3a6 | 308 | gen_update_nip(ctx, ctx->nip); |
ee2b3994 | 309 | } |
e06fcd75 | 310 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 311 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
312 | tcg_temp_free_i32(t0); |
313 | } | |
9a64fbe4 | 314 | |
636aa200 | 315 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
316 | { |
317 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
318 | } | |
a9d9eb8f | 319 | |
f24e5695 | 320 | /* Stop translation */ |
636aa200 | 321 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 322 | { |
d9bce9d9 | 323 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 324 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
325 | } |
326 | ||
f24e5695 | 327 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 328 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 329 | { |
e1833e1f | 330 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
331 | } |
332 | ||
79aceca5 | 333 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
334 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
335 | ||
336 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
337 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 338 | |
c7697e1f | 339 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
340 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
341 | ||
342 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
343 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 344 | |
c227f099 | 345 | typedef struct opcode_t { |
79aceca5 | 346 | unsigned char opc1, opc2, opc3; |
1235fc06 | 347 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
348 | unsigned char pad[5]; |
349 | #else | |
350 | unsigned char pad[1]; | |
351 | #endif | |
c227f099 | 352 | opc_handler_t handler; |
b55266b5 | 353 | const char *oname; |
c227f099 | 354 | } opcode_t; |
79aceca5 | 355 | |
a750fc0b | 356 | /*****************************************************************************/ |
79aceca5 FB |
357 | /*** Instruction decoding ***/ |
358 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 359 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
360 | { \ |
361 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
362 | } | |
363 | ||
364 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 365 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 366 | { \ |
18fba28c | 367 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
368 | } |
369 | ||
370 | /* Opcode part 1 */ | |
371 | EXTRACT_HELPER(opc1, 26, 6); | |
372 | /* Opcode part 2 */ | |
373 | EXTRACT_HELPER(opc2, 1, 5); | |
374 | /* Opcode part 3 */ | |
375 | EXTRACT_HELPER(opc3, 6, 5); | |
376 | /* Update Cr0 flags */ | |
377 | EXTRACT_HELPER(Rc, 0, 1); | |
378 | /* Destination */ | |
379 | EXTRACT_HELPER(rD, 21, 5); | |
380 | /* Source */ | |
381 | EXTRACT_HELPER(rS, 21, 5); | |
382 | /* First operand */ | |
383 | EXTRACT_HELPER(rA, 16, 5); | |
384 | /* Second operand */ | |
385 | EXTRACT_HELPER(rB, 11, 5); | |
386 | /* Third operand */ | |
387 | EXTRACT_HELPER(rC, 6, 5); | |
388 | /*** Get CRn ***/ | |
389 | EXTRACT_HELPER(crfD, 23, 3); | |
390 | EXTRACT_HELPER(crfS, 18, 3); | |
391 | EXTRACT_HELPER(crbD, 21, 5); | |
392 | EXTRACT_HELPER(crbA, 16, 5); | |
393 | EXTRACT_HELPER(crbB, 11, 5); | |
394 | /* SPR / TBL */ | |
3fc6c082 | 395 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 396 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
397 | { |
398 | uint32_t sprn = _SPR(opcode); | |
399 | ||
400 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
401 | } | |
79aceca5 FB |
402 | /*** Get constants ***/ |
403 | EXTRACT_HELPER(IMM, 12, 8); | |
404 | /* 16 bits signed immediate value */ | |
405 | EXTRACT_SHELPER(SIMM, 0, 16); | |
406 | /* 16 bits unsigned immediate value */ | |
407 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
408 | /* 5 bits signed immediate value */ |
409 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
410 | /* 5 bits signed immediate value */ |
411 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
412 | /* Bit count */ |
413 | EXTRACT_HELPER(NB, 11, 5); | |
414 | /* Shift count */ | |
415 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
416 | /* Vector shift count */ |
417 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
418 | /* Mask start */ |
419 | EXTRACT_HELPER(MB, 6, 5); | |
420 | /* Mask end */ | |
421 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
422 | /* Trap operand */ |
423 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
424 | |
425 | EXTRACT_HELPER(CRM, 12, 8); | |
426 | EXTRACT_HELPER(FM, 17, 8); | |
427 | EXTRACT_HELPER(SR, 16, 4); | |
e4bb997e | 428 | EXTRACT_HELPER(FPIMM, 12, 4); |
fb0eaffc | 429 | |
79aceca5 FB |
430 | /*** Jump target decoding ***/ |
431 | /* Displacement */ | |
432 | EXTRACT_SHELPER(d, 0, 16); | |
433 | /* Immediate address */ | |
636aa200 | 434 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
435 | { |
436 | return (opcode >> 0) & 0x03FFFFFC; | |
437 | } | |
438 | ||
636aa200 | 439 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
440 | { |
441 | return (opcode >> 0) & 0xFFFC; | |
442 | } | |
443 | ||
444 | EXTRACT_HELPER(BO, 21, 5); | |
445 | EXTRACT_HELPER(BI, 16, 5); | |
446 | /* Absolute/relative address */ | |
447 | EXTRACT_HELPER(AA, 1, 1); | |
448 | /* Link */ | |
449 | EXTRACT_HELPER(LK, 0, 1); | |
450 | ||
451 | /* Create a mask between <start> and <end> bits */ | |
636aa200 | 452 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 453 | { |
76a66253 | 454 | target_ulong ret; |
79aceca5 | 455 | |
76a66253 JM |
456 | #if defined(TARGET_PPC64) |
457 | if (likely(start == 0)) { | |
6f2d8978 | 458 | ret = UINT64_MAX << (63 - end); |
76a66253 | 459 | } else if (likely(end == 63)) { |
6f2d8978 | 460 | ret = UINT64_MAX >> start; |
76a66253 JM |
461 | } |
462 | #else | |
463 | if (likely(start == 0)) { | |
6f2d8978 | 464 | ret = UINT32_MAX << (31 - end); |
76a66253 | 465 | } else if (likely(end == 31)) { |
6f2d8978 | 466 | ret = UINT32_MAX >> start; |
76a66253 JM |
467 | } |
468 | #endif | |
469 | else { | |
470 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
471 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
472 | if (unlikely(start > end)) | |
473 | return ~ret; | |
474 | } | |
79aceca5 FB |
475 | |
476 | return ret; | |
477 | } | |
478 | ||
a750fc0b | 479 | /*****************************************************************************/ |
a750fc0b | 480 | /* PowerPC instructions table */ |
933dc6eb | 481 | |
76a66253 | 482 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 483 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 484 | { \ |
79aceca5 FB |
485 | .opc1 = op1, \ |
486 | .opc2 = op2, \ | |
487 | .opc3 = op3, \ | |
18fba28c | 488 | .pad = { 0, }, \ |
79aceca5 | 489 | .handler = { \ |
70560da7 FC |
490 | .inval1 = invl, \ |
491 | .type = _typ, \ | |
492 | .type2 = _typ2, \ | |
493 | .handler = &gen_##name, \ | |
494 | .oname = stringify(name), \ | |
495 | }, \ | |
496 | .oname = stringify(name), \ | |
497 | } | |
498 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
499 | { \ | |
500 | .opc1 = op1, \ | |
501 | .opc2 = op2, \ | |
502 | .opc3 = op3, \ | |
503 | .pad = { 0, }, \ | |
504 | .handler = { \ | |
505 | .inval1 = invl1, \ | |
506 | .inval2 = invl2, \ | |
9a64fbe4 | 507 | .type = _typ, \ |
a5858d7a | 508 | .type2 = _typ2, \ |
79aceca5 | 509 | .handler = &gen_##name, \ |
76a66253 | 510 | .oname = stringify(name), \ |
79aceca5 | 511 | }, \ |
3fc6c082 | 512 | .oname = stringify(name), \ |
79aceca5 | 513 | } |
a5858d7a | 514 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 515 | { \ |
c7697e1f JM |
516 | .opc1 = op1, \ |
517 | .opc2 = op2, \ | |
518 | .opc3 = op3, \ | |
519 | .pad = { 0, }, \ | |
520 | .handler = { \ | |
70560da7 | 521 | .inval1 = invl, \ |
c7697e1f | 522 | .type = _typ, \ |
a5858d7a | 523 | .type2 = _typ2, \ |
c7697e1f JM |
524 | .handler = &gen_##name, \ |
525 | .oname = onam, \ | |
526 | }, \ | |
527 | .oname = onam, \ | |
528 | } | |
76a66253 | 529 | #else |
a5858d7a | 530 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 531 | { \ |
c7697e1f JM |
532 | .opc1 = op1, \ |
533 | .opc2 = op2, \ | |
534 | .opc3 = op3, \ | |
535 | .pad = { 0, }, \ | |
536 | .handler = { \ | |
70560da7 FC |
537 | .inval1 = invl, \ |
538 | .type = _typ, \ | |
539 | .type2 = _typ2, \ | |
540 | .handler = &gen_##name, \ | |
541 | }, \ | |
542 | .oname = stringify(name), \ | |
543 | } | |
544 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
545 | { \ | |
546 | .opc1 = op1, \ | |
547 | .opc2 = op2, \ | |
548 | .opc3 = op3, \ | |
549 | .pad = { 0, }, \ | |
550 | .handler = { \ | |
551 | .inval1 = invl1, \ | |
552 | .inval2 = invl2, \ | |
c7697e1f | 553 | .type = _typ, \ |
a5858d7a | 554 | .type2 = _typ2, \ |
c7697e1f | 555 | .handler = &gen_##name, \ |
5c55ff99 BS |
556 | }, \ |
557 | .oname = stringify(name), \ | |
558 | } | |
a5858d7a | 559 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
560 | { \ |
561 | .opc1 = op1, \ | |
562 | .opc2 = op2, \ | |
563 | .opc3 = op3, \ | |
564 | .pad = { 0, }, \ | |
565 | .handler = { \ | |
70560da7 | 566 | .inval1 = invl, \ |
5c55ff99 | 567 | .type = _typ, \ |
a5858d7a | 568 | .type2 = _typ2, \ |
5c55ff99 BS |
569 | .handler = &gen_##name, \ |
570 | }, \ | |
571 | .oname = onam, \ | |
572 | } | |
573 | #endif | |
2e610050 | 574 | |
5c55ff99 | 575 | /* SPR load/store helpers */ |
636aa200 | 576 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 577 | { |
1328c2bf | 578 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 579 | } |
2e610050 | 580 | |
636aa200 | 581 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 582 | { |
1328c2bf | 583 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 584 | } |
2e610050 | 585 | |
54623277 | 586 | /* Invalid instruction */ |
99e300ef | 587 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 588 | { |
e06fcd75 | 589 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
590 | } |
591 | ||
c227f099 | 592 | static opc_handler_t invalid_handler = { |
70560da7 FC |
593 | .inval1 = 0xFFFFFFFF, |
594 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 595 | .type = PPC_NONE, |
a5858d7a | 596 | .type2 = PPC_NONE, |
79aceca5 FB |
597 | .handler = gen_invalid, |
598 | }; | |
599 | ||
e1571908 AJ |
600 | /*** Integer comparison ***/ |
601 | ||
636aa200 | 602 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 603 | { |
2fdcb629 RH |
604 | TCGv t0 = tcg_temp_new(); |
605 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 606 | |
da91a00f | 607 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 608 | |
2fdcb629 RH |
609 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
610 | tcg_gen_trunc_tl_i32(t1, t0); | |
611 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
612 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
613 | ||
614 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
615 | tcg_gen_trunc_tl_i32(t1, t0); | |
616 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
617 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
618 | ||
619 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
620 | tcg_gen_trunc_tl_i32(t1, t0); | |
621 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
622 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
623 | ||
624 | tcg_temp_free(t0); | |
625 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
626 | } |
627 | ||
636aa200 | 628 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 629 | { |
2fdcb629 | 630 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
631 | gen_op_cmp(arg0, t0, s, crf); |
632 | tcg_temp_free(t0); | |
e1571908 AJ |
633 | } |
634 | ||
636aa200 | 635 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 636 | { |
ea363694 | 637 | TCGv t0, t1; |
2fdcb629 RH |
638 | t0 = tcg_temp_new(); |
639 | t1 = tcg_temp_new(); | |
e1571908 | 640 | if (s) { |
ea363694 AJ |
641 | tcg_gen_ext32s_tl(t0, arg0); |
642 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 643 | } else { |
ea363694 AJ |
644 | tcg_gen_ext32u_tl(t0, arg0); |
645 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 646 | } |
ea363694 AJ |
647 | gen_op_cmp(t0, t1, s, crf); |
648 | tcg_temp_free(t1); | |
649 | tcg_temp_free(t0); | |
e1571908 AJ |
650 | } |
651 | ||
636aa200 | 652 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 653 | { |
2fdcb629 | 654 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
655 | gen_op_cmp32(arg0, t0, s, crf); |
656 | tcg_temp_free(t0); | |
e1571908 | 657 | } |
e1571908 | 658 | |
636aa200 | 659 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 660 | { |
02765534 | 661 | if (NARROW_MODE(ctx)) { |
e1571908 | 662 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 663 | } else { |
e1571908 | 664 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 665 | } |
e1571908 AJ |
666 | } |
667 | ||
668 | /* cmp */ | |
99e300ef | 669 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 670 | { |
02765534 | 671 | if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { |
e1571908 AJ |
672 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
673 | 1, crfD(ctx->opcode)); | |
02765534 | 674 | } else { |
e1571908 AJ |
675 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
676 | 1, crfD(ctx->opcode)); | |
02765534 | 677 | } |
e1571908 AJ |
678 | } |
679 | ||
680 | /* cmpi */ | |
99e300ef | 681 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 682 | { |
02765534 | 683 | if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { |
e1571908 AJ |
684 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
685 | 1, crfD(ctx->opcode)); | |
02765534 | 686 | } else { |
e1571908 AJ |
687 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
688 | 1, crfD(ctx->opcode)); | |
02765534 | 689 | } |
e1571908 AJ |
690 | } |
691 | ||
692 | /* cmpl */ | |
99e300ef | 693 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 694 | { |
02765534 | 695 | if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { |
e1571908 AJ |
696 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
697 | 0, crfD(ctx->opcode)); | |
02765534 | 698 | } else { |
e1571908 AJ |
699 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
700 | 0, crfD(ctx->opcode)); | |
02765534 | 701 | } |
e1571908 AJ |
702 | } |
703 | ||
704 | /* cmpli */ | |
99e300ef | 705 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 706 | { |
02765534 | 707 | if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { |
e1571908 AJ |
708 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
709 | 0, crfD(ctx->opcode)); | |
02765534 | 710 | } else { |
e1571908 AJ |
711 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
712 | 0, crfD(ctx->opcode)); | |
02765534 | 713 | } |
e1571908 AJ |
714 | } |
715 | ||
716 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 717 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
718 | { |
719 | int l1, l2; | |
720 | uint32_t bi = rC(ctx->opcode); | |
721 | uint32_t mask; | |
a7812ae4 | 722 | TCGv_i32 t0; |
e1571908 AJ |
723 | |
724 | l1 = gen_new_label(); | |
725 | l2 = gen_new_label(); | |
726 | ||
727 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 728 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
729 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
730 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
731 | if (rA(ctx->opcode) == 0) |
732 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
733 | else | |
734 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
735 | tcg_gen_br(l2); | |
736 | gen_set_label(l1); | |
737 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
738 | gen_set_label(l2); | |
a7812ae4 | 739 | tcg_temp_free_i32(t0); |
e1571908 AJ |
740 | } |
741 | ||
79aceca5 | 742 | /*** Integer arithmetic ***/ |
79aceca5 | 743 | |
636aa200 BS |
744 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
745 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 746 | { |
ffe30937 | 747 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 748 | |
8e7a6db9 | 749 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 750 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
751 | if (sub) { |
752 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
753 | } else { | |
754 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
755 | } | |
756 | tcg_temp_free(t0); | |
02765534 | 757 | if (NARROW_MODE(ctx)) { |
ffe30937 RH |
758 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
759 | } | |
ffe30937 RH |
760 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
761 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
762 | } |
763 | ||
74637406 | 764 | /* Common add function */ |
636aa200 | 765 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
766 | TCGv arg2, bool add_ca, bool compute_ca, |
767 | bool compute_ov, bool compute_rc0) | |
74637406 | 768 | { |
b5a73f8d | 769 | TCGv t0 = ret; |
d9bce9d9 | 770 | |
752d634e | 771 | if (compute_ca || compute_ov) { |
146de60d | 772 | t0 = tcg_temp_new(); |
74637406 | 773 | } |
79aceca5 | 774 | |
da91a00f | 775 | if (compute_ca) { |
79482e5a | 776 | if (NARROW_MODE(ctx)) { |
752d634e RH |
777 | /* Caution: a non-obvious corner case of the spec is that we |
778 | must produce the *entire* 64-bit addition, but produce the | |
779 | carry into bit 32. */ | |
79482e5a | 780 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
781 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
782 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
783 | if (add_ca) { |
784 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
785 | } | |
752d634e RH |
786 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
787 | tcg_temp_free(t1); | |
788 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
789 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
b5a73f8d | 790 | } else { |
79482e5a RH |
791 | TCGv zero = tcg_const_tl(0); |
792 | if (add_ca) { | |
793 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
794 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
795 | } else { | |
796 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
797 | } | |
798 | tcg_temp_free(zero); | |
b5a73f8d | 799 | } |
b5a73f8d RH |
800 | } else { |
801 | tcg_gen_add_tl(t0, arg1, arg2); | |
802 | if (add_ca) { | |
803 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
804 | } | |
da91a00f | 805 | } |
79aceca5 | 806 | |
74637406 AJ |
807 | if (compute_ov) { |
808 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
809 | } | |
b5a73f8d | 810 | if (unlikely(compute_rc0)) { |
74637406 | 811 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 812 | } |
74637406 | 813 | |
a7812ae4 | 814 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
815 | tcg_gen_mov_tl(ret, t0); |
816 | tcg_temp_free(t0); | |
817 | } | |
39dd32ee | 818 | } |
74637406 AJ |
819 | /* Add functions with two operands */ |
820 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 821 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
822 | { \ |
823 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
824 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 825 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
826 | } |
827 | /* Add functions with one operand and one immediate */ | |
828 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
829 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 830 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 831 | { \ |
b5a73f8d | 832 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
833 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
834 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 835 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
836 | tcg_temp_free(t0); \ |
837 | } | |
838 | ||
839 | /* add add. addo addo. */ | |
840 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
841 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
842 | /* addc addc. addco addco. */ | |
843 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
844 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
845 | /* adde adde. addeo addeo. */ | |
846 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
847 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
848 | /* addme addme. addmeo addmeo. */ | |
849 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
850 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
851 | /* addze addze. addzeo addzeo.*/ | |
852 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
853 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
854 | /* addi */ | |
99e300ef | 855 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 856 | { |
74637406 AJ |
857 | target_long simm = SIMM(ctx->opcode); |
858 | ||
859 | if (rA(ctx->opcode) == 0) { | |
860 | /* li case */ | |
861 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
862 | } else { | |
b5a73f8d RH |
863 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
864 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 865 | } |
d9bce9d9 | 866 | } |
74637406 | 867 | /* addic addic.*/ |
b5a73f8d | 868 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 869 | { |
b5a73f8d RH |
870 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
871 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
872 | c, 0, 1, 0, compute_rc0); | |
873 | tcg_temp_free(c); | |
d9bce9d9 | 874 | } |
99e300ef BS |
875 | |
876 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 877 | { |
b5a73f8d | 878 | gen_op_addic(ctx, 0); |
d9bce9d9 | 879 | } |
e8eaa2c0 BS |
880 | |
881 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 882 | { |
b5a73f8d | 883 | gen_op_addic(ctx, 1); |
d9bce9d9 | 884 | } |
99e300ef | 885 | |
54623277 | 886 | /* addis */ |
99e300ef | 887 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 888 | { |
74637406 AJ |
889 | target_long simm = SIMM(ctx->opcode); |
890 | ||
891 | if (rA(ctx->opcode) == 0) { | |
892 | /* lis case */ | |
893 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
894 | } else { | |
b5a73f8d RH |
895 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
896 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 897 | } |
d9bce9d9 | 898 | } |
74637406 | 899 | |
636aa200 BS |
900 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
901 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 902 | { |
2ef1b120 AJ |
903 | int l1 = gen_new_label(); |
904 | int l2 = gen_new_label(); | |
a7812ae4 PB |
905 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
906 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 907 | |
2ef1b120 AJ |
908 | tcg_gen_trunc_tl_i32(t0, arg1); |
909 | tcg_gen_trunc_tl_i32(t1, arg2); | |
910 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 911 | if (sign) { |
2ef1b120 AJ |
912 | int l3 = gen_new_label(); |
913 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
914 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 915 | gen_set_label(l3); |
2ef1b120 | 916 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 917 | } else { |
2ef1b120 | 918 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
919 | } |
920 | if (compute_ov) { | |
da91a00f | 921 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
922 | } |
923 | tcg_gen_br(l2); | |
924 | gen_set_label(l1); | |
925 | if (sign) { | |
2ef1b120 | 926 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
927 | } else { |
928 | tcg_gen_movi_i32(t0, 0); | |
929 | } | |
930 | if (compute_ov) { | |
da91a00f RH |
931 | tcg_gen_movi_tl(cpu_ov, 1); |
932 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
933 | } |
934 | gen_set_label(l2); | |
2ef1b120 | 935 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
936 | tcg_temp_free_i32(t0); |
937 | tcg_temp_free_i32(t1); | |
74637406 AJ |
938 | if (unlikely(Rc(ctx->opcode) != 0)) |
939 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 940 | } |
74637406 AJ |
941 | /* Div functions */ |
942 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 943 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
944 | { \ |
945 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
946 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
947 | sign, compute_ov); \ | |
948 | } | |
949 | /* divwu divwu. divwuo divwuo. */ | |
950 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
951 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
952 | /* divw divw. divwo divwo. */ | |
953 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
954 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
d9bce9d9 | 955 | #if defined(TARGET_PPC64) |
636aa200 BS |
956 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
957 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 958 | { |
2ef1b120 AJ |
959 | int l1 = gen_new_label(); |
960 | int l2 = gen_new_label(); | |
74637406 AJ |
961 | |
962 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
963 | if (sign) { | |
2ef1b120 | 964 | int l3 = gen_new_label(); |
74637406 AJ |
965 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
966 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
967 | gen_set_label(l3); | |
74637406 AJ |
968 | tcg_gen_div_i64(ret, arg1, arg2); |
969 | } else { | |
970 | tcg_gen_divu_i64(ret, arg1, arg2); | |
971 | } | |
972 | if (compute_ov) { | |
da91a00f | 973 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
974 | } |
975 | tcg_gen_br(l2); | |
976 | gen_set_label(l1); | |
977 | if (sign) { | |
978 | tcg_gen_sari_i64(ret, arg1, 63); | |
979 | } else { | |
980 | tcg_gen_movi_i64(ret, 0); | |
981 | } | |
982 | if (compute_ov) { | |
da91a00f RH |
983 | tcg_gen_movi_tl(cpu_ov, 1); |
984 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
985 | } |
986 | gen_set_label(l2); | |
987 | if (unlikely(Rc(ctx->opcode) != 0)) | |
988 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 989 | } |
74637406 | 990 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 991 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 992 | { \ |
2ef1b120 AJ |
993 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
994 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
995 | sign, compute_ov); \ | |
74637406 AJ |
996 | } |
997 | /* divwu divwu. divwuo divwuo. */ | |
998 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
999 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1000 | /* divw divw. divwo divwo. */ | |
1001 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1002 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
d9bce9d9 | 1003 | #endif |
74637406 AJ |
1004 | |
1005 | /* mulhw mulhw. */ | |
99e300ef | 1006 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1007 | { |
23ad1d5d RH |
1008 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1009 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1010 | |
23ad1d5d RH |
1011 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1012 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1013 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1014 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1015 | tcg_temp_free_i32(t0); | |
1016 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1017 | if (unlikely(Rc(ctx->opcode) != 0)) |
1018 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1019 | } |
99e300ef | 1020 | |
54623277 | 1021 | /* mulhwu mulhwu. */ |
99e300ef | 1022 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1023 | { |
23ad1d5d RH |
1024 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1025 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1026 | |
23ad1d5d RH |
1027 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1028 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1029 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1030 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1031 | tcg_temp_free_i32(t0); | |
1032 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1033 | if (unlikely(Rc(ctx->opcode) != 0)) |
1034 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1035 | } |
99e300ef | 1036 | |
54623277 | 1037 | /* mullw mullw. */ |
99e300ef | 1038 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1039 | { |
74637406 AJ |
1040 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1041 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1042 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
74637406 AJ |
1043 | if (unlikely(Rc(ctx->opcode) != 0)) |
1044 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1045 | } |
99e300ef | 1046 | |
54623277 | 1047 | /* mullwo mullwo. */ |
99e300ef | 1048 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1049 | { |
e4a2c846 RH |
1050 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1051 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1052 | |
e4a2c846 RH |
1053 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1054 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1055 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1056 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1057 | ||
1058 | tcg_gen_sari_i32(t0, t0, 31); | |
1059 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1060 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
1061 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1062 | ||
1063 | tcg_temp_free_i32(t0); | |
1064 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1065 | if (unlikely(Rc(ctx->opcode) != 0)) |
1066 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1067 | } |
99e300ef | 1068 | |
54623277 | 1069 | /* mulli */ |
99e300ef | 1070 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1071 | { |
74637406 AJ |
1072 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1073 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1074 | } |
23ad1d5d | 1075 | |
d9bce9d9 | 1076 | #if defined(TARGET_PPC64) |
74637406 | 1077 | /* mulhd mulhd. */ |
23ad1d5d RH |
1078 | static void gen_mulhd(DisasContext *ctx) |
1079 | { | |
1080 | TCGv lo = tcg_temp_new(); | |
1081 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1082 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1083 | tcg_temp_free(lo); | |
1084 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1085 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1086 | } | |
1087 | } | |
1088 | ||
74637406 | 1089 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1090 | static void gen_mulhdu(DisasContext *ctx) |
1091 | { | |
1092 | TCGv lo = tcg_temp_new(); | |
1093 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1094 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1095 | tcg_temp_free(lo); | |
1096 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1097 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1098 | } | |
1099 | } | |
99e300ef | 1100 | |
54623277 | 1101 | /* mulld mulld. */ |
99e300ef | 1102 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1103 | { |
74637406 AJ |
1104 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1105 | cpu_gpr[rB(ctx->opcode)]); | |
1106 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1107 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1108 | } |
d15f74fb | 1109 | |
74637406 | 1110 | /* mulldo mulldo. */ |
d15f74fb BS |
1111 | static void gen_mulldo(DisasContext *ctx) |
1112 | { | |
1113 | gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env, | |
1114 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1115 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1116 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1117 | } | |
1118 | } | |
d9bce9d9 | 1119 | #endif |
74637406 | 1120 | |
74637406 | 1121 | /* Common subf function */ |
636aa200 | 1122 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1123 | TCGv arg2, bool add_ca, bool compute_ca, |
1124 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1125 | { |
b5a73f8d | 1126 | TCGv t0 = ret; |
79aceca5 | 1127 | |
752d634e | 1128 | if (compute_ca || compute_ov) { |
b5a73f8d | 1129 | t0 = tcg_temp_new(); |
da91a00f | 1130 | } |
74637406 | 1131 | |
79482e5a RH |
1132 | if (compute_ca) { |
1133 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1134 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1135 | /* Caution: a non-obvious corner case of the spec is that we |
1136 | must produce the *entire* 64-bit addition, but produce the | |
1137 | carry into bit 32. */ | |
79482e5a | 1138 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1139 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1140 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1141 | if (add_ca) { |
752d634e | 1142 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1143 | } else { |
752d634e | 1144 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1145 | } |
752d634e | 1146 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1147 | tcg_gen_add_tl(t0, t0, inv1); |
752d634e RH |
1148 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1149 | tcg_temp_free(t1); | |
1150 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
1151 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
79482e5a | 1152 | } else if (add_ca) { |
08f4a0f7 RH |
1153 | TCGv zero, inv1 = tcg_temp_new(); |
1154 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1155 | zero = tcg_const_tl(0); |
1156 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1157 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
b5a73f8d | 1158 | tcg_temp_free(zero); |
08f4a0f7 | 1159 | tcg_temp_free(inv1); |
b5a73f8d | 1160 | } else { |
79482e5a | 1161 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1162 | tcg_gen_sub_tl(t0, arg2, arg1); |
b5a73f8d | 1163 | } |
79482e5a RH |
1164 | } else if (add_ca) { |
1165 | /* Since we're ignoring carry-out, we can simplify the | |
1166 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1167 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1168 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1169 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1170 | } else { |
b5a73f8d | 1171 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1172 | } |
b5a73f8d | 1173 | |
74637406 AJ |
1174 | if (compute_ov) { |
1175 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1176 | } | |
b5a73f8d | 1177 | if (unlikely(compute_rc0)) { |
74637406 | 1178 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1179 | } |
74637406 | 1180 | |
a7812ae4 | 1181 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1182 | tcg_gen_mov_tl(ret, t0); |
1183 | tcg_temp_free(t0); | |
79aceca5 | 1184 | } |
79aceca5 | 1185 | } |
74637406 AJ |
1186 | /* Sub functions with Two operands functions */ |
1187 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1188 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1189 | { \ |
1190 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1191 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1192 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1193 | } |
1194 | /* Sub functions with one operand and one immediate */ | |
1195 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1196 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1197 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1198 | { \ |
b5a73f8d | 1199 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1200 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1201 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1202 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1203 | tcg_temp_free(t0); \ |
1204 | } | |
1205 | /* subf subf. subfo subfo. */ | |
1206 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1207 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1208 | /* subfc subfc. subfco subfco. */ | |
1209 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1210 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1211 | /* subfe subfe. subfeo subfo. */ | |
1212 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1213 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1214 | /* subfme subfme. subfmeo subfmeo. */ | |
1215 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1216 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1217 | /* subfze subfze. subfzeo subfzeo.*/ | |
1218 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1219 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1220 | |
54623277 | 1221 | /* subfic */ |
99e300ef | 1222 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1223 | { |
b5a73f8d RH |
1224 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1225 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1226 | c, 0, 1, 0, 0); | |
1227 | tcg_temp_free(c); | |
79aceca5 FB |
1228 | } |
1229 | ||
fd3f0081 RH |
1230 | /* neg neg. nego nego. */ |
1231 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1232 | { | |
1233 | TCGv zero = tcg_const_tl(0); | |
1234 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1235 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1236 | tcg_temp_free(zero); | |
1237 | } | |
1238 | ||
1239 | static void gen_neg(DisasContext *ctx) | |
1240 | { | |
1241 | gen_op_arith_neg(ctx, 0); | |
1242 | } | |
1243 | ||
1244 | static void gen_nego(DisasContext *ctx) | |
1245 | { | |
1246 | gen_op_arith_neg(ctx, 1); | |
1247 | } | |
1248 | ||
79aceca5 | 1249 | /*** Integer logical ***/ |
26d67362 | 1250 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1251 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1252 | { \ |
26d67362 AJ |
1253 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1254 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1255 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1256 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1257 | } |
79aceca5 | 1258 | |
26d67362 | 1259 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1260 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1261 | { \ |
26d67362 | 1262 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1263 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1264 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1265 | } |
1266 | ||
1267 | /* and & and. */ | |
26d67362 | 1268 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1269 | /* andc & andc. */ |
26d67362 | 1270 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1271 | |
54623277 | 1272 | /* andi. */ |
e8eaa2c0 | 1273 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1274 | { |
26d67362 AJ |
1275 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1276 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1277 | } |
e8eaa2c0 | 1278 | |
54623277 | 1279 | /* andis. */ |
e8eaa2c0 | 1280 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1281 | { |
26d67362 AJ |
1282 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1283 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1284 | } |
99e300ef | 1285 | |
54623277 | 1286 | /* cntlzw */ |
99e300ef | 1287 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1288 | { |
a7812ae4 | 1289 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1290 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1291 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1292 | } |
79aceca5 | 1293 | /* eqv & eqv. */ |
26d67362 | 1294 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1295 | /* extsb & extsb. */ |
26d67362 | 1296 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1297 | /* extsh & extsh. */ |
26d67362 | 1298 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1299 | /* nand & nand. */ |
26d67362 | 1300 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1301 | /* nor & nor. */ |
26d67362 | 1302 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1303 | |
54623277 | 1304 | /* or & or. */ |
99e300ef | 1305 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1306 | { |
76a66253 JM |
1307 | int rs, ra, rb; |
1308 | ||
1309 | rs = rS(ctx->opcode); | |
1310 | ra = rA(ctx->opcode); | |
1311 | rb = rB(ctx->opcode); | |
1312 | /* Optimisation for mr. ri case */ | |
1313 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1314 | if (rs != rb) |
1315 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1316 | else | |
1317 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1318 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1319 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1320 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1321 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1322 | #if defined(TARGET_PPC64) |
1323 | } else { | |
26d67362 AJ |
1324 | int prio = 0; |
1325 | ||
c80f84e3 JM |
1326 | switch (rs) { |
1327 | case 1: | |
1328 | /* Set process priority to low */ | |
26d67362 | 1329 | prio = 2; |
c80f84e3 JM |
1330 | break; |
1331 | case 6: | |
1332 | /* Set process priority to medium-low */ | |
26d67362 | 1333 | prio = 3; |
c80f84e3 JM |
1334 | break; |
1335 | case 2: | |
1336 | /* Set process priority to normal */ | |
26d67362 | 1337 | prio = 4; |
c80f84e3 | 1338 | break; |
be147d08 JM |
1339 | #if !defined(CONFIG_USER_ONLY) |
1340 | case 31: | |
76db3ba4 | 1341 | if (ctx->mem_idx > 0) { |
be147d08 | 1342 | /* Set process priority to very low */ |
26d67362 | 1343 | prio = 1; |
be147d08 JM |
1344 | } |
1345 | break; | |
1346 | case 5: | |
76db3ba4 | 1347 | if (ctx->mem_idx > 0) { |
be147d08 | 1348 | /* Set process priority to medium-hight */ |
26d67362 | 1349 | prio = 5; |
be147d08 JM |
1350 | } |
1351 | break; | |
1352 | case 3: | |
76db3ba4 | 1353 | if (ctx->mem_idx > 0) { |
be147d08 | 1354 | /* Set process priority to high */ |
26d67362 | 1355 | prio = 6; |
be147d08 JM |
1356 | } |
1357 | break; | |
be147d08 | 1358 | case 7: |
76db3ba4 | 1359 | if (ctx->mem_idx > 1) { |
be147d08 | 1360 | /* Set process priority to very high */ |
26d67362 | 1361 | prio = 7; |
be147d08 JM |
1362 | } |
1363 | break; | |
be147d08 | 1364 | #endif |
c80f84e3 JM |
1365 | default: |
1366 | /* nop */ | |
1367 | break; | |
1368 | } | |
26d67362 | 1369 | if (prio) { |
a7812ae4 | 1370 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1371 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1372 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1373 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1374 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1375 | tcg_temp_free(t0); |
26d67362 | 1376 | } |
c80f84e3 | 1377 | #endif |
9a64fbe4 | 1378 | } |
9a64fbe4 | 1379 | } |
79aceca5 | 1380 | /* orc & orc. */ |
26d67362 | 1381 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1382 | |
54623277 | 1383 | /* xor & xor. */ |
99e300ef | 1384 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1385 | { |
9a64fbe4 | 1386 | /* Optimisation for "set to zero" case */ |
26d67362 | 1387 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1388 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1389 | else |
1390 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1391 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1392 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1393 | } |
99e300ef | 1394 | |
54623277 | 1395 | /* ori */ |
99e300ef | 1396 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1397 | { |
76a66253 | 1398 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1399 | |
9a64fbe4 FB |
1400 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1401 | /* NOP */ | |
76a66253 | 1402 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1403 | return; |
76a66253 | 1404 | } |
26d67362 | 1405 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1406 | } |
99e300ef | 1407 | |
54623277 | 1408 | /* oris */ |
99e300ef | 1409 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1410 | { |
76a66253 | 1411 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1412 | |
9a64fbe4 FB |
1413 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1414 | /* NOP */ | |
1415 | return; | |
76a66253 | 1416 | } |
26d67362 | 1417 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1418 | } |
99e300ef | 1419 | |
54623277 | 1420 | /* xori */ |
99e300ef | 1421 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1422 | { |
76a66253 | 1423 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1424 | |
1425 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1426 | /* NOP */ | |
1427 | return; | |
1428 | } | |
26d67362 | 1429 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1430 | } |
99e300ef | 1431 | |
54623277 | 1432 | /* xoris */ |
99e300ef | 1433 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1434 | { |
76a66253 | 1435 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1436 | |
1437 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1438 | /* NOP */ | |
1439 | return; | |
1440 | } | |
26d67362 | 1441 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1442 | } |
99e300ef | 1443 | |
54623277 | 1444 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1445 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1446 | { |
eaabeef2 DG |
1447 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1448 | } | |
1449 | ||
1450 | static void gen_popcntw(DisasContext *ctx) | |
1451 | { | |
1452 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1453 | } | |
1454 | ||
d9bce9d9 | 1455 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1456 | /* popcntd: PowerPC 2.06 specification */ |
1457 | static void gen_popcntd(DisasContext *ctx) | |
1458 | { | |
1459 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1460 | } |
eaabeef2 | 1461 | #endif |
d9bce9d9 JM |
1462 | |
1463 | #if defined(TARGET_PPC64) | |
1464 | /* extsw & extsw. */ | |
26d67362 | 1465 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1466 | |
54623277 | 1467 | /* cntlzd */ |
99e300ef | 1468 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1469 | { |
a7812ae4 | 1470 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1471 | if (unlikely(Rc(ctx->opcode) != 0)) |
1472 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1473 | } | |
d9bce9d9 JM |
1474 | #endif |
1475 | ||
79aceca5 | 1476 | /*** Integer rotate ***/ |
99e300ef | 1477 | |
54623277 | 1478 | /* rlwimi & rlwimi. */ |
99e300ef | 1479 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1480 | { |
76a66253 | 1481 | uint32_t mb, me, sh; |
79aceca5 FB |
1482 | |
1483 | mb = MB(ctx->opcode); | |
1484 | me = ME(ctx->opcode); | |
76a66253 | 1485 | sh = SH(ctx->opcode); |
d03ef511 AJ |
1486 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1487 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1488 | } else { | |
d03ef511 | 1489 | target_ulong mask; |
a7812ae4 PB |
1490 | TCGv t1; |
1491 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1492 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1493 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1494 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1495 | tcg_gen_rotli_i32(t2, t2, sh); | |
1496 | tcg_gen_extu_i32_i64(t0, t2); | |
1497 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1498 | #else |
1499 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1500 | #endif | |
76a66253 | 1501 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1502 | mb += 32; |
1503 | me += 32; | |
76a66253 | 1504 | #endif |
d03ef511 | 1505 | mask = MASK(mb, me); |
a7812ae4 | 1506 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1507 | tcg_gen_andi_tl(t0, t0, mask); |
1508 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1509 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1510 | tcg_temp_free(t0); | |
1511 | tcg_temp_free(t1); | |
1512 | } | |
76a66253 | 1513 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1514 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1515 | } |
99e300ef | 1516 | |
54623277 | 1517 | /* rlwinm & rlwinm. */ |
99e300ef | 1518 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1519 | { |
1520 | uint32_t mb, me, sh; | |
3b46e624 | 1521 | |
79aceca5 FB |
1522 | sh = SH(ctx->opcode); |
1523 | mb = MB(ctx->opcode); | |
1524 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1525 | |
1526 | if (likely(mb == 0 && me == (31 - sh))) { | |
1527 | if (likely(sh == 0)) { | |
1528 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1529 | } else { | |
a7812ae4 | 1530 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1531 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1532 | tcg_gen_shli_tl(t0, t0, sh); | |
1533 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1534 | tcg_temp_free(t0); | |
79aceca5 | 1535 | } |
d03ef511 | 1536 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1537 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1538 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1539 | tcg_gen_shri_tl(t0, t0, mb); | |
1540 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1541 | tcg_temp_free(t0); | |
1542 | } else { | |
a7812ae4 | 1543 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1544 | #if defined(TARGET_PPC64) |
a7812ae4 | 1545 | TCGv_i32 t1 = tcg_temp_new_i32(); |
54843a58 AJ |
1546 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1547 | tcg_gen_rotli_i32(t1, t1, sh); | |
1548 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 | 1549 | tcg_temp_free_i32(t1); |
54843a58 AJ |
1550 | #else |
1551 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1552 | #endif | |
76a66253 | 1553 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1554 | mb += 32; |
1555 | me += 32; | |
76a66253 | 1556 | #endif |
d03ef511 AJ |
1557 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1558 | tcg_temp_free(t0); | |
1559 | } | |
76a66253 | 1560 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1561 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1562 | } |
99e300ef | 1563 | |
54623277 | 1564 | /* rlwnm & rlwnm. */ |
99e300ef | 1565 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1566 | { |
1567 | uint32_t mb, me; | |
54843a58 AJ |
1568 | TCGv t0; |
1569 | #if defined(TARGET_PPC64) | |
a7812ae4 | 1570 | TCGv_i32 t1, t2; |
54843a58 | 1571 | #endif |
79aceca5 FB |
1572 | |
1573 | mb = MB(ctx->opcode); | |
1574 | me = ME(ctx->opcode); | |
a7812ae4 | 1575 | t0 = tcg_temp_new(); |
d03ef511 | 1576 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1577 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1578 | t1 = tcg_temp_new_i32(); |
1579 | t2 = tcg_temp_new_i32(); | |
54843a58 AJ |
1580 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1581 | tcg_gen_trunc_i64_i32(t2, t0); | |
1582 | tcg_gen_rotl_i32(t1, t1, t2); | |
1583 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 PB |
1584 | tcg_temp_free_i32(t1); |
1585 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1586 | #else |
1587 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1588 | #endif | |
76a66253 JM |
1589 | if (unlikely(mb != 0 || me != 31)) { |
1590 | #if defined(TARGET_PPC64) | |
1591 | mb += 32; | |
1592 | me += 32; | |
1593 | #endif | |
54843a58 | 1594 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1595 | } else { |
54843a58 | 1596 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1597 | } |
54843a58 | 1598 | tcg_temp_free(t0); |
76a66253 | 1599 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1600 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1601 | } |
1602 | ||
d9bce9d9 JM |
1603 | #if defined(TARGET_PPC64) |
1604 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1605 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1606 | { \ |
1607 | gen_##name(ctx, 0); \ | |
1608 | } \ | |
e8eaa2c0 BS |
1609 | \ |
1610 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1611 | { \ |
1612 | gen_##name(ctx, 1); \ | |
1613 | } | |
1614 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1615 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1616 | { \ |
1617 | gen_##name(ctx, 0, 0); \ | |
1618 | } \ | |
e8eaa2c0 BS |
1619 | \ |
1620 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1621 | { \ |
1622 | gen_##name(ctx, 0, 1); \ | |
1623 | } \ | |
e8eaa2c0 BS |
1624 | \ |
1625 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1626 | { \ |
1627 | gen_##name(ctx, 1, 0); \ | |
1628 | } \ | |
e8eaa2c0 BS |
1629 | \ |
1630 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1631 | { \ |
1632 | gen_##name(ctx, 1, 1); \ | |
1633 | } | |
51789c41 | 1634 | |
636aa200 BS |
1635 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1636 | uint32_t sh) | |
51789c41 | 1637 | { |
d03ef511 AJ |
1638 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1639 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1640 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1641 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1642 | } else { | |
a7812ae4 | 1643 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1644 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1645 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1646 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1647 | } else { |
1648 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1649 | } |
d03ef511 | 1650 | tcg_temp_free(t0); |
51789c41 | 1651 | } |
51789c41 | 1652 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1653 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1654 | } |
d9bce9d9 | 1655 | /* rldicl - rldicl. */ |
636aa200 | 1656 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1657 | { |
51789c41 | 1658 | uint32_t sh, mb; |
d9bce9d9 | 1659 | |
9d53c753 JM |
1660 | sh = SH(ctx->opcode) | (shn << 5); |
1661 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1662 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1663 | } |
51789c41 | 1664 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1665 | /* rldicr - rldicr. */ |
636aa200 | 1666 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1667 | { |
51789c41 | 1668 | uint32_t sh, me; |
d9bce9d9 | 1669 | |
9d53c753 JM |
1670 | sh = SH(ctx->opcode) | (shn << 5); |
1671 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1672 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1673 | } |
51789c41 | 1674 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1675 | /* rldic - rldic. */ |
636aa200 | 1676 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1677 | { |
51789c41 | 1678 | uint32_t sh, mb; |
d9bce9d9 | 1679 | |
9d53c753 JM |
1680 | sh = SH(ctx->opcode) | (shn << 5); |
1681 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1682 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1683 | } | |
1684 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1685 | ||
636aa200 | 1686 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1687 | { |
54843a58 | 1688 | TCGv t0; |
d03ef511 AJ |
1689 | |
1690 | mb = MB(ctx->opcode); | |
1691 | me = ME(ctx->opcode); | |
a7812ae4 | 1692 | t0 = tcg_temp_new(); |
d03ef511 | 1693 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1694 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1695 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1696 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1697 | } else { | |
1698 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1699 | } | |
1700 | tcg_temp_free(t0); | |
51789c41 | 1701 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1702 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1703 | } |
51789c41 | 1704 | |
d9bce9d9 | 1705 | /* rldcl - rldcl. */ |
636aa200 | 1706 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1707 | { |
51789c41 | 1708 | uint32_t mb; |
d9bce9d9 | 1709 | |
9d53c753 | 1710 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1711 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1712 | } |
36081602 | 1713 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1714 | /* rldcr - rldcr. */ |
636aa200 | 1715 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1716 | { |
51789c41 | 1717 | uint32_t me; |
d9bce9d9 | 1718 | |
9d53c753 | 1719 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1720 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1721 | } |
36081602 | 1722 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1723 | /* rldimi - rldimi. */ |
636aa200 | 1724 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1725 | { |
271a916e | 1726 | uint32_t sh, mb, me; |
d9bce9d9 | 1727 | |
9d53c753 JM |
1728 | sh = SH(ctx->opcode) | (shn << 5); |
1729 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1730 | me = 63 - sh; |
d03ef511 AJ |
1731 | if (unlikely(sh == 0 && mb == 0)) { |
1732 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1733 | } else { | |
1734 | TCGv t0, t1; | |
1735 | target_ulong mask; | |
1736 | ||
a7812ae4 | 1737 | t0 = tcg_temp_new(); |
54843a58 | 1738 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1739 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1740 | mask = MASK(mb, me); |
1741 | tcg_gen_andi_tl(t0, t0, mask); | |
1742 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1743 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1744 | tcg_temp_free(t0); | |
1745 | tcg_temp_free(t1); | |
51789c41 | 1746 | } |
51789c41 | 1747 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1748 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1749 | } |
36081602 | 1750 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1751 | #endif |
1752 | ||
79aceca5 | 1753 | /*** Integer shift ***/ |
99e300ef | 1754 | |
54623277 | 1755 | /* slw & slw. */ |
99e300ef | 1756 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1757 | { |
7fd6bf7d | 1758 | TCGv t0, t1; |
26d67362 | 1759 | |
7fd6bf7d AJ |
1760 | t0 = tcg_temp_new(); |
1761 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1762 | #if defined(TARGET_PPC64) | |
1763 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1764 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1765 | #else | |
1766 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1767 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1768 | #endif | |
1769 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1770 | t1 = tcg_temp_new(); | |
1771 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1772 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1773 | tcg_temp_free(t1); | |
fea0c503 | 1774 | tcg_temp_free(t0); |
7fd6bf7d | 1775 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1776 | if (unlikely(Rc(ctx->opcode) != 0)) |
1777 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1778 | } | |
99e300ef | 1779 | |
54623277 | 1780 | /* sraw & sraw. */ |
99e300ef | 1781 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1782 | { |
d15f74fb | 1783 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1784 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1785 | if (unlikely(Rc(ctx->opcode) != 0)) |
1786 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1787 | } | |
99e300ef | 1788 | |
54623277 | 1789 | /* srawi & srawi. */ |
99e300ef | 1790 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1791 | { |
26d67362 | 1792 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
1793 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1794 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
1795 | if (sh == 0) { | |
1796 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 1797 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1798 | } else { |
ba4af3e4 RH |
1799 | TCGv t0; |
1800 | tcg_gen_ext32s_tl(dst, src); | |
1801 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
1802 | t0 = tcg_temp_new(); | |
1803 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
1804 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
1805 | tcg_temp_free(t0); | |
1806 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
1807 | tcg_gen_sari_tl(dst, dst, sh); | |
1808 | } | |
1809 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1810 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 1811 | } |
79aceca5 | 1812 | } |
99e300ef | 1813 | |
54623277 | 1814 | /* srw & srw. */ |
99e300ef | 1815 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1816 | { |
fea0c503 | 1817 | TCGv t0, t1; |
d9bce9d9 | 1818 | |
7fd6bf7d AJ |
1819 | t0 = tcg_temp_new(); |
1820 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1821 | #if defined(TARGET_PPC64) | |
1822 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1823 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1824 | #else | |
1825 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1826 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1827 | #endif | |
1828 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1829 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1830 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1831 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1832 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1833 | tcg_temp_free(t1); |
fea0c503 | 1834 | tcg_temp_free(t0); |
26d67362 AJ |
1835 | if (unlikely(Rc(ctx->opcode) != 0)) |
1836 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1837 | } | |
54623277 | 1838 | |
d9bce9d9 JM |
1839 | #if defined(TARGET_PPC64) |
1840 | /* sld & sld. */ | |
99e300ef | 1841 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1842 | { |
7fd6bf7d | 1843 | TCGv t0, t1; |
26d67362 | 1844 | |
7fd6bf7d AJ |
1845 | t0 = tcg_temp_new(); |
1846 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1847 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1848 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1849 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1850 | t1 = tcg_temp_new(); | |
1851 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1852 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1853 | tcg_temp_free(t1); | |
fea0c503 | 1854 | tcg_temp_free(t0); |
26d67362 AJ |
1855 | if (unlikely(Rc(ctx->opcode) != 0)) |
1856 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1857 | } | |
99e300ef | 1858 | |
54623277 | 1859 | /* srad & srad. */ |
99e300ef | 1860 | static void gen_srad(DisasContext *ctx) |
26d67362 | 1861 | { |
d15f74fb | 1862 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1863 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1864 | if (unlikely(Rc(ctx->opcode) != 0)) |
1865 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1866 | } | |
d9bce9d9 | 1867 | /* sradi & sradi. */ |
636aa200 | 1868 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 1869 | { |
26d67362 | 1870 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
1871 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1872 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
1873 | if (sh == 0) { | |
1874 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 1875 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1876 | } else { |
ba4af3e4 RH |
1877 | TCGv t0; |
1878 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
1879 | t0 = tcg_temp_new(); | |
1880 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
1881 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
1882 | tcg_temp_free(t0); | |
1883 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
1884 | tcg_gen_sari_tl(dst, src, sh); | |
1885 | } | |
1886 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1887 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 1888 | } |
d9bce9d9 | 1889 | } |
e8eaa2c0 BS |
1890 | |
1891 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
1892 | { |
1893 | gen_sradi(ctx, 0); | |
1894 | } | |
e8eaa2c0 BS |
1895 | |
1896 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
1897 | { |
1898 | gen_sradi(ctx, 1); | |
1899 | } | |
99e300ef | 1900 | |
54623277 | 1901 | /* srd & srd. */ |
99e300ef | 1902 | static void gen_srd(DisasContext *ctx) |
26d67362 | 1903 | { |
7fd6bf7d | 1904 | TCGv t0, t1; |
26d67362 | 1905 | |
7fd6bf7d AJ |
1906 | t0 = tcg_temp_new(); |
1907 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1908 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1909 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1910 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1911 | t1 = tcg_temp_new(); | |
1912 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1913 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1914 | tcg_temp_free(t1); | |
fea0c503 | 1915 | tcg_temp_free(t0); |
26d67362 AJ |
1916 | if (unlikely(Rc(ctx->opcode) != 0)) |
1917 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1918 | } | |
d9bce9d9 | 1919 | #endif |
79aceca5 FB |
1920 | |
1921 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 1922 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 1923 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1924 | { \ |
76a66253 | 1925 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1926 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1927 | return; \ |
1928 | } \ | |
eb44b959 AJ |
1929 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
1930 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 1931 | gen_reset_fpstatus(); \ |
8e703949 BS |
1932 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1933 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 1934 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 1935 | if (isfloat) { \ |
8e703949 BS |
1936 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1937 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 1938 | } \ |
af12906f AJ |
1939 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
1940 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
1941 | } |
1942 | ||
7c58044c JM |
1943 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
1944 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
1945 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 1946 | |
7c58044c | 1947 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 1948 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1949 | { \ |
76a66253 | 1950 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1951 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1952 | return; \ |
1953 | } \ | |
eb44b959 AJ |
1954 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
1955 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 1956 | gen_reset_fpstatus(); \ |
8e703949 BS |
1957 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1958 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 1959 | cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 1960 | if (isfloat) { \ |
8e703949 BS |
1961 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1962 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 1963 | } \ |
af12906f AJ |
1964 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
1965 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 1966 | } |
7c58044c JM |
1967 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
1968 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
1969 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 1970 | |
7c58044c | 1971 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 1972 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1973 | { \ |
76a66253 | 1974 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1975 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1976 | return; \ |
1977 | } \ | |
eb44b959 AJ |
1978 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
1979 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 1980 | gen_reset_fpstatus(); \ |
8e703949 BS |
1981 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1982 | cpu_fpr[rA(ctx->opcode)], \ | |
1983 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 1984 | if (isfloat) { \ |
8e703949 BS |
1985 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1986 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 1987 | } \ |
af12906f AJ |
1988 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
1989 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 1990 | } |
7c58044c JM |
1991 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
1992 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
1993 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 1994 | |
7c58044c | 1995 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 1996 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1997 | { \ |
76a66253 | 1998 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1999 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2000 | return; \ |
2001 | } \ | |
eb44b959 AJ |
2002 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2003 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2004 | gen_reset_fpstatus(); \ |
8e703949 BS |
2005 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2006 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2007 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2008 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2009 | } |
2010 | ||
7c58044c | 2011 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2012 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2013 | { \ |
76a66253 | 2014 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2015 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2016 | return; \ |
2017 | } \ | |
eb44b959 AJ |
2018 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2019 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2020 | gen_reset_fpstatus(); \ |
8e703949 BS |
2021 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2022 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2023 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2024 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2025 | } |
2026 | ||
9a64fbe4 | 2027 | /* fadd - fadds */ |
7c58044c | 2028 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2029 | /* fdiv - fdivs */ |
7c58044c | 2030 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2031 | /* fmul - fmuls */ |
7c58044c | 2032 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2033 | |
d7e4b87e | 2034 | /* fre */ |
7c58044c | 2035 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2036 | |
a750fc0b | 2037 | /* fres */ |
7c58044c | 2038 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2039 | |
a750fc0b | 2040 | /* frsqrte */ |
7c58044c JM |
2041 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2042 | ||
2043 | /* frsqrtes */ | |
99e300ef | 2044 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2045 | { |
af12906f | 2046 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2047 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2048 | return; |
2049 | } | |
eb44b959 AJ |
2050 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2051 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f | 2052 | gen_reset_fpstatus(); |
8e703949 BS |
2053 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2054 | cpu_fpr[rB(ctx->opcode)]); | |
2055 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2056 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2057 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
7c58044c | 2058 | } |
79aceca5 | 2059 | |
a750fc0b | 2060 | /* fsel */ |
7c58044c | 2061 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2062 | /* fsub - fsubs */ |
7c58044c | 2063 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2064 | /* Optional: */ |
99e300ef | 2065 | |
54623277 | 2066 | /* fsqrt */ |
99e300ef | 2067 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2068 | { |
76a66253 | 2069 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2070 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2071 | return; |
2072 | } | |
eb44b959 AJ |
2073 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2074 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2075 | gen_reset_fpstatus(); |
8e703949 BS |
2076 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2077 | cpu_fpr[rB(ctx->opcode)]); | |
af12906f | 2078 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
c7d344af | 2079 | } |
79aceca5 | 2080 | |
99e300ef | 2081 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2082 | { |
76a66253 | 2083 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2084 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2085 | return; |
2086 | } | |
eb44b959 AJ |
2087 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2088 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2089 | gen_reset_fpstatus(); |
8e703949 BS |
2090 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2091 | cpu_fpr[rB(ctx->opcode)]); | |
2092 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2093 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2094 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2095 | } |
2096 | ||
2097 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2098 | /* fmadd - fmadds */ |
7c58044c | 2099 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2100 | /* fmsub - fmsubs */ |
7c58044c | 2101 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2102 | /* fnmadd - fnmadds */ |
7c58044c | 2103 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2104 | /* fnmsub - fnmsubs */ |
7c58044c | 2105 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2106 | |
2107 | /*** Floating-Point round & convert ***/ | |
2108 | /* fctiw */ | |
7c58044c | 2109 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2110 | /* fctiwz */ |
7c58044c | 2111 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2112 | /* frsp */ |
7c58044c | 2113 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2114 | #if defined(TARGET_PPC64) |
2115 | /* fcfid */ | |
7c58044c | 2116 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
426613db | 2117 | /* fctid */ |
7c58044c | 2118 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
426613db | 2119 | /* fctidz */ |
7c58044c | 2120 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
426613db | 2121 | #endif |
79aceca5 | 2122 | |
d7e4b87e | 2123 | /* frin */ |
7c58044c | 2124 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2125 | /* friz */ |
7c58044c | 2126 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2127 | /* frip */ |
7c58044c | 2128 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2129 | /* frim */ |
7c58044c | 2130 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2131 | |
79aceca5 | 2132 | /*** Floating-Point compare ***/ |
99e300ef | 2133 | |
54623277 | 2134 | /* fcmpo */ |
99e300ef | 2135 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2136 | { |
330c483b | 2137 | TCGv_i32 crf; |
76a66253 | 2138 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2139 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2140 | return; |
2141 | } | |
eb44b959 AJ |
2142 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2143 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2144 | gen_reset_fpstatus(); |
9a819377 | 2145 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2146 | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2147 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2148 | tcg_temp_free_i32(crf); |
8e703949 | 2149 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2150 | } |
2151 | ||
2152 | /* fcmpu */ | |
99e300ef | 2153 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2154 | { |
330c483b | 2155 | TCGv_i32 crf; |
76a66253 | 2156 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2157 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2158 | return; |
2159 | } | |
eb44b959 AJ |
2160 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2161 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2162 | gen_reset_fpstatus(); |
9a819377 | 2163 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2164 | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2165 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2166 | tcg_temp_free_i32(crf); |
8e703949 | 2167 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2168 | } |
2169 | ||
9a64fbe4 FB |
2170 | /*** Floating-point move ***/ |
2171 | /* fabs */ | |
7c58044c | 2172 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2173 | static void gen_fabs(DisasContext *ctx) |
2174 | { | |
2175 | if (unlikely(!ctx->fpu_enabled)) { | |
2176 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2177 | return; | |
2178 | } | |
2179 | tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2180 | ~(1ULL << 63)); | |
2181 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2182 | } | |
9a64fbe4 FB |
2183 | |
2184 | /* fmr - fmr. */ | |
7c58044c | 2185 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2186 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2187 | { |
76a66253 | 2188 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2189 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2190 | return; |
2191 | } | |
af12906f AJ |
2192 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2193 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2194 | } |
2195 | ||
2196 | /* fnabs */ | |
7c58044c | 2197 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2198 | static void gen_fnabs(DisasContext *ctx) |
2199 | { | |
2200 | if (unlikely(!ctx->fpu_enabled)) { | |
2201 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2202 | return; | |
2203 | } | |
2204 | tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2205 | 1ULL << 63); | |
2206 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2207 | } | |
2208 | ||
9a64fbe4 | 2209 | /* fneg */ |
7c58044c | 2210 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2211 | static void gen_fneg(DisasContext *ctx) |
2212 | { | |
2213 | if (unlikely(!ctx->fpu_enabled)) { | |
2214 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2215 | return; | |
2216 | } | |
2217 | tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2218 | 1ULL << 63); | |
2219 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2220 | } | |
9a64fbe4 | 2221 | |
79aceca5 | 2222 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2223 | |
54623277 | 2224 | /* mcrfs */ |
99e300ef | 2225 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2226 | { |
30304420 | 2227 | TCGv tmp = tcg_temp_new(); |
7c58044c JM |
2228 | int bfa; |
2229 | ||
76a66253 | 2230 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2231 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2232 | return; |
2233 | } | |
7c58044c | 2234 | bfa = 4 * (7 - crfS(ctx->opcode)); |
30304420 DG |
2235 | tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); |
2236 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); | |
2237 | tcg_temp_free(tmp); | |
e1571908 | 2238 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
30304420 | 2239 | tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2240 | } |
2241 | ||
2242 | /* mffs */ | |
99e300ef | 2243 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2244 | { |
76a66253 | 2245 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2246 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2247 | return; |
2248 | } | |
7c58044c | 2249 | gen_reset_fpstatus(); |
30304420 | 2250 | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
af12906f | 2251 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2252 | } |
2253 | ||
2254 | /* mtfsb0 */ | |
99e300ef | 2255 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2256 | { |
fb0eaffc | 2257 | uint8_t crb; |
3b46e624 | 2258 | |
76a66253 | 2259 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2260 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2261 | return; |
2262 | } | |
6e35d524 | 2263 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2264 | gen_reset_fpstatus(); |
6e35d524 | 2265 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2266 | TCGv_i32 t0; |
2267 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2268 | gen_update_nip(ctx, ctx->nip - 4); | |
2269 | t0 = tcg_const_i32(crb); | |
8e703949 | 2270 | gen_helper_fpscr_clrbit(cpu_env, t0); |
6e35d524 AJ |
2271 | tcg_temp_free_i32(t0); |
2272 | } | |
7c58044c | 2273 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2274 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2275 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c | 2276 | } |
79aceca5 FB |
2277 | } |
2278 | ||
2279 | /* mtfsb1 */ | |
99e300ef | 2280 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2281 | { |
fb0eaffc | 2282 | uint8_t crb; |
3b46e624 | 2283 | |
76a66253 | 2284 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2285 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2286 | return; |
2287 | } | |
6e35d524 | 2288 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2289 | gen_reset_fpstatus(); |
2290 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2291 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2292 | TCGv_i32 t0; |
2293 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2294 | gen_update_nip(ctx, ctx->nip - 4); | |
2295 | t0 = tcg_const_i32(crb); | |
8e703949 | 2296 | gen_helper_fpscr_setbit(cpu_env, t0); |
0f2f39c2 | 2297 | tcg_temp_free_i32(t0); |
af12906f | 2298 | } |
7c58044c | 2299 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2300 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2301 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2302 | } |
2303 | /* We can raise a differed exception */ | |
8e703949 | 2304 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2305 | } |
2306 | ||
2307 | /* mtfsf */ | |
99e300ef | 2308 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2309 | { |
0f2f39c2 | 2310 | TCGv_i32 t0; |
4911012d | 2311 | int L = ctx->opcode & 0x02000000; |
af12906f | 2312 | |
76a66253 | 2313 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2314 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2315 | return; |
2316 | } | |
eb44b959 AJ |
2317 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2318 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2319 | gen_reset_fpstatus(); |
4911012d BS |
2320 | if (L) |
2321 | t0 = tcg_const_i32(0xff); | |
2322 | else | |
2323 | t0 = tcg_const_i32(FM(ctx->opcode)); | |
8e703949 | 2324 | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2325 | tcg_temp_free_i32(t0); |
7c58044c | 2326 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2327 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2328 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2329 | } |
2330 | /* We can raise a differed exception */ | |
8e703949 | 2331 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2332 | } |
2333 | ||
2334 | /* mtfsfi */ | |
99e300ef | 2335 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2336 | { |
7c58044c | 2337 | int bf, sh; |
0f2f39c2 AJ |
2338 | TCGv_i64 t0; |
2339 | TCGv_i32 t1; | |
7c58044c | 2340 | |
76a66253 | 2341 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2342 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2343 | return; |
2344 | } | |
7c58044c JM |
2345 | bf = crbD(ctx->opcode) >> 2; |
2346 | sh = 7 - bf; | |
eb44b959 AJ |
2347 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2348 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2349 | gen_reset_fpstatus(); |
0f2f39c2 | 2350 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); |
af12906f | 2351 | t1 = tcg_const_i32(1 << sh); |
8e703949 | 2352 | gen_helper_store_fpscr(cpu_env, t0, t1); |
0f2f39c2 AJ |
2353 | tcg_temp_free_i64(t0); |
2354 | tcg_temp_free_i32(t1); | |
7c58044c | 2355 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2356 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2357 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2358 | } |
2359 | /* We can raise a differed exception */ | |
8e703949 | 2360 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2361 | } |
2362 | ||
76a66253 JM |
2363 | /*** Addressing modes ***/ |
2364 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2365 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2366 | target_long maskl) | |
76a66253 JM |
2367 | { |
2368 | target_long simm = SIMM(ctx->opcode); | |
2369 | ||
be147d08 | 2370 | simm &= ~maskl; |
76db3ba4 | 2371 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2372 | if (NARROW_MODE(ctx)) { |
2373 | simm = (uint32_t)simm; | |
2374 | } | |
e2be8d8d | 2375 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2376 | } else if (likely(simm != 0)) { |
e2be8d8d | 2377 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2378 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2379 | tcg_gen_ext32u_tl(EA, EA); |
2380 | } | |
76db3ba4 | 2381 | } else { |
c791fe84 | 2382 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2383 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2384 | } else { |
2385 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2386 | } | |
76db3ba4 | 2387 | } |
76a66253 JM |
2388 | } |
2389 | ||
636aa200 | 2390 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2391 | { |
76db3ba4 | 2392 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2393 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2394 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2395 | } else { |
2396 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2397 | } | |
76db3ba4 | 2398 | } else { |
e2be8d8d | 2399 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2400 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2401 | tcg_gen_ext32u_tl(EA, EA); |
2402 | } | |
76db3ba4 | 2403 | } |
76a66253 JM |
2404 | } |
2405 | ||
636aa200 | 2406 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2407 | { |
76db3ba4 | 2408 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2409 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2410 | } else if (NARROW_MODE(ctx)) { |
2411 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2412 | } else { |
c791fe84 | 2413 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2414 | } |
2415 | } | |
2416 | ||
636aa200 BS |
2417 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2418 | target_long val) | |
76db3ba4 AJ |
2419 | { |
2420 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2421 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2422 | tcg_gen_ext32u_tl(ret, ret); |
2423 | } | |
76a66253 JM |
2424 | } |
2425 | ||
636aa200 | 2426 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 AJ |
2427 | { |
2428 | int l1 = gen_new_label(); | |
2429 | TCGv t0 = tcg_temp_new(); | |
2430 | TCGv_i32 t1, t2; | |
2431 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2432 | gen_update_nip(ctx, ctx->nip - 4); | |
2433 | tcg_gen_andi_tl(t0, EA, mask); | |
2434 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2435 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2436 | t2 = tcg_const_i32(0); | |
e5f17ac6 | 2437 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2438 | tcg_temp_free_i32(t1); |
2439 | tcg_temp_free_i32(t2); | |
2440 | gen_set_label(l1); | |
2441 | tcg_temp_free(t0); | |
2442 | } | |
2443 | ||
7863667f | 2444 | /*** Integer load ***/ |
636aa200 | 2445 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2446 | { |
2447 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2448 | } | |
2449 | ||
636aa200 | 2450 | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2451 | { |
2452 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); | |
2453 | } | |
2454 | ||
636aa200 | 2455 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2456 | { |
2457 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); | |
2458 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2459 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2460 | } |
b61f2753 AJ |
2461 | } |
2462 | ||
636aa200 | 2463 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2464 | { |
76db3ba4 | 2465 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2466 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
fa3966a3 | 2467 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2468 | tcg_gen_ext16s_tl(arg1, arg1); |
76db3ba4 AJ |
2469 | } else { |
2470 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); | |
2471 | } | |
b61f2753 AJ |
2472 | } |
2473 | ||
636aa200 | 2474 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2475 | { |
76db3ba4 AJ |
2476 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2477 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2478 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2479 | } |
b61f2753 AJ |
2480 | } |
2481 | ||
76db3ba4 | 2482 | #if defined(TARGET_PPC64) |
636aa200 | 2483 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2484 | { |
a457e7ee | 2485 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2486 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
fa3966a3 AJ |
2487 | tcg_gen_bswap32_tl(arg1, arg1); |
2488 | tcg_gen_ext32s_tl(arg1, arg1); | |
b61f2753 | 2489 | } else |
76db3ba4 | 2490 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
b61f2753 | 2491 | } |
76db3ba4 | 2492 | #endif |
b61f2753 | 2493 | |
636aa200 | 2494 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2495 | { |
76db3ba4 AJ |
2496 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2497 | if (unlikely(ctx->le_mode)) { | |
66896cb8 | 2498 | tcg_gen_bswap64_i64(arg1, arg1); |
76db3ba4 | 2499 | } |
b61f2753 AJ |
2500 | } |
2501 | ||
636aa200 | 2502 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2503 | { |
76db3ba4 | 2504 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2505 | } |
2506 | ||
636aa200 | 2507 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2508 | { |
76db3ba4 | 2509 | if (unlikely(ctx->le_mode)) { |
76db3ba4 AJ |
2510 | TCGv t0 = tcg_temp_new(); |
2511 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2512 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2513 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2514 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2515 | } else { |
2516 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2517 | } | |
b61f2753 AJ |
2518 | } |
2519 | ||
636aa200 | 2520 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2521 | { |
76db3ba4 | 2522 | if (unlikely(ctx->le_mode)) { |
fa3966a3 AJ |
2523 | TCGv t0 = tcg_temp_new(); |
2524 | tcg_gen_ext32u_tl(t0, arg1); | |
2525 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2526 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2527 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2528 | } else { |
2529 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2530 | } | |
b61f2753 AJ |
2531 | } |
2532 | ||
636aa200 | 2533 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2534 | { |
76db3ba4 | 2535 | if (unlikely(ctx->le_mode)) { |
a7812ae4 | 2536 | TCGv_i64 t0 = tcg_temp_new_i64(); |
66896cb8 | 2537 | tcg_gen_bswap64_i64(t0, arg1); |
76db3ba4 | 2538 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
a7812ae4 | 2539 | tcg_temp_free_i64(t0); |
b61f2753 | 2540 | } else |
76db3ba4 | 2541 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2542 | } |
2543 | ||
0c8aacd4 | 2544 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2545 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2546 | { \ |
76db3ba4 AJ |
2547 | TCGv EA; \ |
2548 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2549 | EA = tcg_temp_new(); \ | |
2550 | gen_addr_imm_index(ctx, EA, 0); \ | |
2551 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2552 | tcg_temp_free(EA); \ |
79aceca5 FB |
2553 | } |
2554 | ||
0c8aacd4 | 2555 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2556 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2557 | { \ |
b61f2753 | 2558 | TCGv EA; \ |
76a66253 JM |
2559 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2560 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2561 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2562 | return; \ |
9a64fbe4 | 2563 | } \ |
76db3ba4 | 2564 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2565 | EA = tcg_temp_new(); \ |
9d53c753 | 2566 | if (type == PPC_64B) \ |
76db3ba4 | 2567 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2568 | else \ |
76db3ba4 AJ |
2569 | gen_addr_imm_index(ctx, EA, 0); \ |
2570 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2571 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2572 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2573 | } |
2574 | ||
0c8aacd4 | 2575 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2576 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2577 | { \ |
b61f2753 | 2578 | TCGv EA; \ |
76a66253 JM |
2579 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2580 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2581 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2582 | return; \ |
9a64fbe4 | 2583 | } \ |
76db3ba4 | 2584 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2585 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2586 | gen_addr_reg_index(ctx, EA); \ |
2587 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2588 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2589 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2590 | } |
2591 | ||
cd6e9320 | 2592 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
99e300ef | 2593 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2594 | { \ |
76db3ba4 AJ |
2595 | TCGv EA; \ |
2596 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2597 | EA = tcg_temp_new(); \ | |
2598 | gen_addr_reg_index(ctx, EA); \ | |
2599 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2600 | tcg_temp_free(EA); \ |
79aceca5 | 2601 | } |
cd6e9320 TH |
2602 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2603 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2604 | |
0c8aacd4 AJ |
2605 | #define GEN_LDS(name, ldop, op, type) \ |
2606 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2607 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2608 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2609 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2610 | |
2611 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2612 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2613 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2614 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2615 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2616 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2617 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2618 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2619 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2620 | /* lwaux */ |
0c8aacd4 | 2621 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2622 | /* lwax */ |
0c8aacd4 | 2623 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2624 | /* ldux */ |
0c8aacd4 | 2625 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2626 | /* ldx */ |
0c8aacd4 | 2627 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2628 | |
2629 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2630 | { |
b61f2753 | 2631 | TCGv EA; |
d9bce9d9 JM |
2632 | if (Rc(ctx->opcode)) { |
2633 | if (unlikely(rA(ctx->opcode) == 0 || | |
2634 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2635 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2636 | return; |
2637 | } | |
2638 | } | |
76db3ba4 | 2639 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2640 | EA = tcg_temp_new(); |
76db3ba4 | 2641 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2642 | if (ctx->opcode & 0x02) { |
2643 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2644 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2645 | } else { |
2646 | /* ld - ldu */ | |
76db3ba4 | 2647 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2648 | } |
d9bce9d9 | 2649 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2650 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2651 | tcg_temp_free(EA); | |
d9bce9d9 | 2652 | } |
99e300ef | 2653 | |
54623277 | 2654 | /* lq */ |
99e300ef | 2655 | static void gen_lq(DisasContext *ctx) |
be147d08 JM |
2656 | { |
2657 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2658 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2659 | #else |
2660 | int ra, rd; | |
b61f2753 | 2661 | TCGv EA; |
be147d08 JM |
2662 | |
2663 | /* Restore CPU state */ | |
76db3ba4 | 2664 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2665 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2666 | return; |
2667 | } | |
2668 | ra = rA(ctx->opcode); | |
2669 | rd = rD(ctx->opcode); | |
2670 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2671 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2672 | return; |
2673 | } | |
76db3ba4 | 2674 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2675 | /* Little-endian mode is not handled */ |
e06fcd75 | 2676 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2677 | return; |
2678 | } | |
76db3ba4 | 2679 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2680 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2681 | gen_addr_imm_index(ctx, EA, 0x0F); |
2682 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2683 | gen_addr_add(ctx, EA, EA, 8); | |
2684 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
b61f2753 | 2685 | tcg_temp_free(EA); |
be147d08 JM |
2686 | #endif |
2687 | } | |
d9bce9d9 | 2688 | #endif |
79aceca5 FB |
2689 | |
2690 | /*** Integer store ***/ | |
0c8aacd4 | 2691 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2692 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2693 | { \ |
76db3ba4 AJ |
2694 | TCGv EA; \ |
2695 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2696 | EA = tcg_temp_new(); \ | |
2697 | gen_addr_imm_index(ctx, EA, 0); \ | |
2698 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2699 | tcg_temp_free(EA); \ |
79aceca5 FB |
2700 | } |
2701 | ||
0c8aacd4 | 2702 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2703 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2704 | { \ |
b61f2753 | 2705 | TCGv EA; \ |
76a66253 | 2706 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2707 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2708 | return; \ |
9a64fbe4 | 2709 | } \ |
76db3ba4 | 2710 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2711 | EA = tcg_temp_new(); \ |
9d53c753 | 2712 | if (type == PPC_64B) \ |
76db3ba4 | 2713 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2714 | else \ |
76db3ba4 AJ |
2715 | gen_addr_imm_index(ctx, EA, 0); \ |
2716 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2717 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2718 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2719 | } |
2720 | ||
0c8aacd4 | 2721 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2722 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2723 | { \ |
b61f2753 | 2724 | TCGv EA; \ |
76a66253 | 2725 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2726 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2727 | return; \ |
9a64fbe4 | 2728 | } \ |
76db3ba4 | 2729 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2730 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2731 | gen_addr_reg_index(ctx, EA); \ |
2732 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2733 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2734 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2735 | } |
2736 | ||
cd6e9320 TH |
2737 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
2738 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 2739 | { \ |
76db3ba4 AJ |
2740 | TCGv EA; \ |
2741 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2742 | EA = tcg_temp_new(); \ | |
2743 | gen_addr_reg_index(ctx, EA); \ | |
2744 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2745 | tcg_temp_free(EA); \ |
79aceca5 | 2746 | } |
cd6e9320 TH |
2747 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
2748 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2749 | |
0c8aacd4 AJ |
2750 | #define GEN_STS(name, stop, op, type) \ |
2751 | GEN_ST(name, stop, op | 0x20, type); \ | |
2752 | GEN_STU(name, stop, op | 0x21, type); \ | |
2753 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2754 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2755 | |
2756 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2757 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2758 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2759 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2760 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2761 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2762 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
2763 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2764 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
2765 | |
2766 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2767 | { |
be147d08 | 2768 | int rs; |
b61f2753 | 2769 | TCGv EA; |
be147d08 JM |
2770 | |
2771 | rs = rS(ctx->opcode); | |
2772 | if ((ctx->opcode & 0x3) == 0x2) { | |
2773 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2774 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2775 | #else |
2776 | /* stq */ | |
76db3ba4 | 2777 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2778 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2779 | return; |
2780 | } | |
2781 | if (unlikely(rs & 1)) { | |
e06fcd75 | 2782 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2783 | return; |
2784 | } | |
76db3ba4 | 2785 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2786 | /* Little-endian mode is not handled */ |
e06fcd75 | 2787 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2788 | return; |
2789 | } | |
76db3ba4 | 2790 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2791 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2792 | gen_addr_imm_index(ctx, EA, 0x03); |
2793 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
2794 | gen_addr_add(ctx, EA, EA, 8); | |
2795 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
b61f2753 | 2796 | tcg_temp_free(EA); |
be147d08 JM |
2797 | #endif |
2798 | } else { | |
2799 | /* std / stdu */ | |
2800 | if (Rc(ctx->opcode)) { | |
2801 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2802 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2803 | return; |
2804 | } | |
2805 | } | |
76db3ba4 | 2806 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2807 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2808 | gen_addr_imm_index(ctx, EA, 0x03); |
2809 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 2810 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2811 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2812 | tcg_temp_free(EA); | |
d9bce9d9 | 2813 | } |
d9bce9d9 JM |
2814 | } |
2815 | #endif | |
79aceca5 FB |
2816 | /*** Integer load and store with byte reverse ***/ |
2817 | /* lhbrx */ | |
86178a57 | 2818 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2819 | { |
76db3ba4 AJ |
2820 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2821 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2822 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2823 | } |
b61f2753 | 2824 | } |
0c8aacd4 | 2825 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2826 | |
79aceca5 | 2827 | /* lwbrx */ |
86178a57 | 2828 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2829 | { |
76db3ba4 AJ |
2830 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2831 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2832 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2833 | } |
b61f2753 | 2834 | } |
0c8aacd4 | 2835 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2836 | |
cd6e9320 TH |
2837 | #if defined(TARGET_PPC64) |
2838 | /* ldbrx */ | |
2839 | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2840 | { | |
2841 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); | |
2842 | if (likely(!ctx->le_mode)) { | |
2843 | tcg_gen_bswap64_tl(arg1, arg1); | |
2844 | } | |
2845 | } | |
2846 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); | |
2847 | #endif /* TARGET_PPC64 */ | |
2848 | ||
79aceca5 | 2849 | /* sthbrx */ |
86178a57 | 2850 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2851 | { |
76db3ba4 | 2852 | if (likely(!ctx->le_mode)) { |
76db3ba4 AJ |
2853 | TCGv t0 = tcg_temp_new(); |
2854 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2855 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2856 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2857 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2858 | } else { |
2859 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2860 | } | |
b61f2753 | 2861 | } |
0c8aacd4 | 2862 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 2863 | |
79aceca5 | 2864 | /* stwbrx */ |
86178a57 | 2865 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2866 | { |
76db3ba4 | 2867 | if (likely(!ctx->le_mode)) { |
fa3966a3 AJ |
2868 | TCGv t0 = tcg_temp_new(); |
2869 | tcg_gen_ext32u_tl(t0, arg1); | |
2870 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2871 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2872 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2873 | } else { |
2874 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2875 | } | |
b61f2753 | 2876 | } |
0c8aacd4 | 2877 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 | 2878 | |
cd6e9320 TH |
2879 | #if defined(TARGET_PPC64) |
2880 | /* stdbrx */ | |
2881 | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2882 | { | |
2883 | if (likely(!ctx->le_mode)) { | |
2884 | TCGv t0 = tcg_temp_new(); | |
2885 | tcg_gen_bswap64_tl(t0, arg1); | |
2886 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); | |
2887 | tcg_temp_free(t0); | |
2888 | } else { | |
2889 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); | |
2890 | } | |
2891 | } | |
2892 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); | |
2893 | #endif /* TARGET_PPC64 */ | |
2894 | ||
79aceca5 | 2895 | /*** Integer load and store multiple ***/ |
99e300ef | 2896 | |
54623277 | 2897 | /* lmw */ |
99e300ef | 2898 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2899 | { |
76db3ba4 AJ |
2900 | TCGv t0; |
2901 | TCGv_i32 t1; | |
2902 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2903 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2904 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2905 | t0 = tcg_temp_new(); |
2906 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2907 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2908 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2909 | tcg_temp_free(t0); |
2910 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2911 | } |
2912 | ||
2913 | /* stmw */ | |
99e300ef | 2914 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2915 | { |
76db3ba4 AJ |
2916 | TCGv t0; |
2917 | TCGv_i32 t1; | |
2918 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2919 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2920 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2921 | t0 = tcg_temp_new(); |
2922 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2923 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2924 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2925 | tcg_temp_free(t0); |
2926 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2927 | } |
2928 | ||
2929 | /*** Integer load and store strings ***/ | |
54623277 | 2930 | |
79aceca5 | 2931 | /* lswi */ |
3fc6c082 | 2932 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
2933 | * rA is in the range of registers to be loaded. |
2934 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
2935 | * For now, I'll follow the spec... | |
2936 | */ | |
99e300ef | 2937 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 2938 | { |
dfbc799d AJ |
2939 | TCGv t0; |
2940 | TCGv_i32 t1, t2; | |
79aceca5 FB |
2941 | int nb = NB(ctx->opcode); |
2942 | int start = rD(ctx->opcode); | |
9a64fbe4 | 2943 | int ra = rA(ctx->opcode); |
79aceca5 FB |
2944 | int nr; |
2945 | ||
2946 | if (nb == 0) | |
2947 | nb = 32; | |
2948 | nr = nb / 4; | |
76a66253 JM |
2949 | if (unlikely(((start + nr) > 32 && |
2950 | start <= ra && (start + nr - 32) > ra) || | |
2951 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 2952 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 2953 | return; |
297d8e62 | 2954 | } |
76db3ba4 | 2955 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 2956 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2957 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 2958 | t0 = tcg_temp_new(); |
76db3ba4 | 2959 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
2960 | t1 = tcg_const_i32(nb); |
2961 | t2 = tcg_const_i32(start); | |
2f5a189c | 2962 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2963 | tcg_temp_free(t0); |
2964 | tcg_temp_free_i32(t1); | |
2965 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2966 | } |
2967 | ||
2968 | /* lswx */ | |
99e300ef | 2969 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 2970 | { |
76db3ba4 AJ |
2971 | TCGv t0; |
2972 | TCGv_i32 t1, t2, t3; | |
2973 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2974 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2975 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2976 | t0 = tcg_temp_new(); |
2977 | gen_addr_reg_index(ctx, t0); | |
2978 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2979 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
2980 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 2981 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
2982 | tcg_temp_free(t0); |
2983 | tcg_temp_free_i32(t1); | |
2984 | tcg_temp_free_i32(t2); | |
2985 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
2986 | } |
2987 | ||
2988 | /* stswi */ | |
99e300ef | 2989 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 2990 | { |
76db3ba4 AJ |
2991 | TCGv t0; |
2992 | TCGv_i32 t1, t2; | |
4b3686fa | 2993 | int nb = NB(ctx->opcode); |
76db3ba4 | 2994 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 2995 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2996 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2997 | t0 = tcg_temp_new(); |
2998 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
2999 | if (nb == 0) |
3000 | nb = 32; | |
dfbc799d | 3001 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3002 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3003 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3004 | tcg_temp_free(t0); |
3005 | tcg_temp_free_i32(t1); | |
3006 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3007 | } |
3008 | ||
3009 | /* stswx */ | |
99e300ef | 3010 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3011 | { |
76db3ba4 AJ |
3012 | TCGv t0; |
3013 | TCGv_i32 t1, t2; | |
3014 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3015 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3016 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3017 | t0 = tcg_temp_new(); |
3018 | gen_addr_reg_index(ctx, t0); | |
3019 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3020 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3021 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3022 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3023 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3024 | tcg_temp_free(t0); |
3025 | tcg_temp_free_i32(t1); | |
3026 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3027 | } |
3028 | ||
3029 | /*** Memory synchronisation ***/ | |
3030 | /* eieio */ | |
99e300ef | 3031 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3032 | { |
79aceca5 FB |
3033 | } |
3034 | ||
3035 | /* isync */ | |
99e300ef | 3036 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3037 | { |
e06fcd75 | 3038 | gen_stop_exception(ctx); |
79aceca5 FB |
3039 | } |
3040 | ||
111bfab3 | 3041 | /* lwarx */ |
99e300ef | 3042 | static void gen_lwarx(DisasContext *ctx) |
79aceca5 | 3043 | { |
76db3ba4 | 3044 | TCGv t0; |
18b21a2f | 3045 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3046 | gen_set_access_type(ctx, ACCESS_RES); |
3047 | t0 = tcg_temp_local_new(); | |
3048 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3049 | gen_check_align(ctx, t0, 0x03); |
18b21a2f | 3050 | gen_qemu_ld32u(ctx, gpr, t0); |
cf360a32 | 3051 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3052 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3053 | tcg_temp_free(t0); |
79aceca5 FB |
3054 | } |
3055 | ||
4425265b NF |
3056 | #if defined(CONFIG_USER_ONLY) |
3057 | static void gen_conditional_store (DisasContext *ctx, TCGv EA, | |
3058 | int reg, int size) | |
3059 | { | |
3060 | TCGv t0 = tcg_temp_new(); | |
3061 | uint32_t save_exception = ctx->exception; | |
3062 | ||
1328c2bf | 3063 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
4425265b | 3064 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
1328c2bf | 3065 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b NF |
3066 | tcg_temp_free(t0); |
3067 | gen_update_nip(ctx, ctx->nip-4); | |
3068 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3069 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3070 | ctx->exception = save_exception; | |
3071 | } | |
3072 | #endif | |
3073 | ||
79aceca5 | 3074 | /* stwcx. */ |
e8eaa2c0 | 3075 | static void gen_stwcx_(DisasContext *ctx) |
79aceca5 | 3076 | { |
76db3ba4 AJ |
3077 | TCGv t0; |
3078 | gen_set_access_type(ctx, ACCESS_RES); | |
3079 | t0 = tcg_temp_local_new(); | |
3080 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3081 | gen_check_align(ctx, t0, 0x03); |
4425265b NF |
3082 | #if defined(CONFIG_USER_ONLY) |
3083 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); | |
3084 | #else | |
3085 | { | |
3086 | int l1; | |
3087 | ||
da91a00f | 3088 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3089 | l1 = gen_new_label(); |
3090 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3091 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3092 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3093 | gen_set_label(l1); | |
3094 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3095 | } | |
3096 | #endif | |
cf360a32 | 3097 | tcg_temp_free(t0); |
79aceca5 FB |
3098 | } |
3099 | ||
426613db | 3100 | #if defined(TARGET_PPC64) |
426613db | 3101 | /* ldarx */ |
99e300ef | 3102 | static void gen_ldarx(DisasContext *ctx) |
426613db | 3103 | { |
76db3ba4 | 3104 | TCGv t0; |
18b21a2f | 3105 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3106 | gen_set_access_type(ctx, ACCESS_RES); |
3107 | t0 = tcg_temp_local_new(); | |
3108 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3109 | gen_check_align(ctx, t0, 0x07); |
18b21a2f | 3110 | gen_qemu_ld64(ctx, gpr, t0); |
cf360a32 | 3111 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3112 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3113 | tcg_temp_free(t0); |
426613db JM |
3114 | } |
3115 | ||
3116 | /* stdcx. */ | |
e8eaa2c0 | 3117 | static void gen_stdcx_(DisasContext *ctx) |
426613db | 3118 | { |
76db3ba4 AJ |
3119 | TCGv t0; |
3120 | gen_set_access_type(ctx, ACCESS_RES); | |
3121 | t0 = tcg_temp_local_new(); | |
3122 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3123 | gen_check_align(ctx, t0, 0x07); |
4425265b NF |
3124 | #if defined(CONFIG_USER_ONLY) |
3125 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); | |
3126 | #else | |
3127 | { | |
3128 | int l1; | |
da91a00f | 3129 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3130 | l1 = gen_new_label(); |
3131 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3132 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3133 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3134 | gen_set_label(l1); | |
3135 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3136 | } | |
3137 | #endif | |
cf360a32 | 3138 | tcg_temp_free(t0); |
426613db JM |
3139 | } |
3140 | #endif /* defined(TARGET_PPC64) */ | |
3141 | ||
79aceca5 | 3142 | /* sync */ |
99e300ef | 3143 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3144 | { |
79aceca5 FB |
3145 | } |
3146 | ||
0db1b20e | 3147 | /* wait */ |
99e300ef | 3148 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3149 | { |
931ff272 | 3150 | TCGv_i32 t0 = tcg_temp_new_i32(); |
259186a7 AF |
3151 | tcg_gen_st_i32(t0, cpu_env, |
3152 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3153 | tcg_temp_free_i32(t0); |
0db1b20e | 3154 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3155 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3156 | } |
3157 | ||
79aceca5 | 3158 | /*** Floating-point load ***/ |
a0d7d5a7 | 3159 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3160 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3161 | { \ |
a0d7d5a7 | 3162 | TCGv EA; \ |
76a66253 | 3163 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3164 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3165 | return; \ |
3166 | } \ | |
76db3ba4 | 3167 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3168 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3169 | gen_addr_imm_index(ctx, EA, 0); \ |
3170 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3171 | tcg_temp_free(EA); \ |
79aceca5 FB |
3172 | } |
3173 | ||
a0d7d5a7 | 3174 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3175 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3176 | { \ |
a0d7d5a7 | 3177 | TCGv EA; \ |
76a66253 | 3178 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3179 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3180 | return; \ |
3181 | } \ | |
76a66253 | 3182 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3183 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3184 | return; \ |
9a64fbe4 | 3185 | } \ |
76db3ba4 | 3186 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3187 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3188 | gen_addr_imm_index(ctx, EA, 0); \ |
3189 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3190 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3191 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3192 | } |
3193 | ||
a0d7d5a7 | 3194 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3195 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3196 | { \ |
a0d7d5a7 | 3197 | TCGv EA; \ |
76a66253 | 3198 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3199 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3200 | return; \ |
3201 | } \ | |
76a66253 | 3202 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3203 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3204 | return; \ |
9a64fbe4 | 3205 | } \ |
76db3ba4 | 3206 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3207 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3208 | gen_addr_reg_index(ctx, EA); \ |
3209 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3210 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3211 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3212 | } |
3213 | ||
a0d7d5a7 | 3214 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3215 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3216 | { \ |
a0d7d5a7 | 3217 | TCGv EA; \ |
76a66253 | 3218 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3219 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3220 | return; \ |
3221 | } \ | |
76db3ba4 | 3222 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3223 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3224 | gen_addr_reg_index(ctx, EA); \ |
3225 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3226 | tcg_temp_free(EA); \ |
79aceca5 FB |
3227 | } |
3228 | ||
a0d7d5a7 AJ |
3229 | #define GEN_LDFS(name, ldop, op, type) \ |
3230 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3231 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3232 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3233 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3234 | ||
636aa200 | 3235 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3236 | { |
3237 | TCGv t0 = tcg_temp_new(); | |
3238 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3239 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3240 | tcg_gen_trunc_tl_i32(t1, t0); |
3241 | tcg_temp_free(t0); | |
8e703949 | 3242 | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
a0d7d5a7 AJ |
3243 | tcg_temp_free_i32(t1); |
3244 | } | |
79aceca5 | 3245 | |
a0d7d5a7 AJ |
3246 | /* lfd lfdu lfdux lfdx */ |
3247 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3248 | /* lfs lfsu lfsux lfsx */ | |
3249 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 FB |
3250 | |
3251 | /*** Floating-point store ***/ | |
a0d7d5a7 | 3252 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3253 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3254 | { \ |
a0d7d5a7 | 3255 | TCGv EA; \ |
76a66253 | 3256 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3257 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3258 | return; \ |
3259 | } \ | |
76db3ba4 | 3260 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3261 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3262 | gen_addr_imm_index(ctx, EA, 0); \ |
3263 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3264 | tcg_temp_free(EA); \ |
79aceca5 FB |
3265 | } |
3266 | ||
a0d7d5a7 | 3267 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3268 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3269 | { \ |
a0d7d5a7 | 3270 | TCGv EA; \ |
76a66253 | 3271 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3272 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3273 | return; \ |
3274 | } \ | |
76a66253 | 3275 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3276 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3277 | return; \ |
9a64fbe4 | 3278 | } \ |
76db3ba4 | 3279 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3280 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3281 | gen_addr_imm_index(ctx, EA, 0); \ |
3282 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3283 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3284 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3285 | } |
3286 | ||
a0d7d5a7 | 3287 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3288 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3289 | { \ |
a0d7d5a7 | 3290 | TCGv EA; \ |
76a66253 | 3291 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3292 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3293 | return; \ |
3294 | } \ | |
76a66253 | 3295 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3296 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3297 | return; \ |
9a64fbe4 | 3298 | } \ |
76db3ba4 | 3299 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3300 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3301 | gen_addr_reg_index(ctx, EA); \ |
3302 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3303 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3304 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3305 | } |
3306 | ||
a0d7d5a7 | 3307 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3308 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3309 | { \ |
a0d7d5a7 | 3310 | TCGv EA; \ |
76a66253 | 3311 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3312 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3313 | return; \ |
3314 | } \ | |
76db3ba4 | 3315 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3316 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3317 | gen_addr_reg_index(ctx, EA); \ |
3318 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3319 | tcg_temp_free(EA); \ |
79aceca5 FB |
3320 | } |
3321 | ||
a0d7d5a7 AJ |
3322 | #define GEN_STFS(name, stop, op, type) \ |
3323 | GEN_STF(name, stop, op | 0x20, type); \ | |
3324 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3325 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3326 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3327 | ||
636aa200 | 3328 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3329 | { |
3330 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3331 | TCGv t1 = tcg_temp_new(); | |
8e703949 | 3332 | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
a0d7d5a7 AJ |
3333 | tcg_gen_extu_i32_tl(t1, t0); |
3334 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3335 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3336 | tcg_temp_free(t1); |
3337 | } | |
79aceca5 FB |
3338 | |
3339 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3340 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3341 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3342 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 FB |
3343 | |
3344 | /* Optional: */ | |
636aa200 | 3345 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3346 | { |
3347 | TCGv t0 = tcg_temp_new(); | |
3348 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3349 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3350 | tcg_temp_free(t0); |
3351 | } | |
79aceca5 | 3352 | /* stfiwx */ |
a0d7d5a7 | 3353 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 | 3354 | |
697ab892 DG |
3355 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3356 | { | |
3357 | #if defined(TARGET_PPC64) | |
3358 | if (ctx->has_cfar) | |
3359 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3360 | #endif | |
3361 | } | |
3362 | ||
79aceca5 | 3363 | /*** Branch ***/ |
636aa200 | 3364 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 FB |
3365 | { |
3366 | TranslationBlock *tb; | |
3367 | tb = ctx->tb; | |
e0c8f9ce | 3368 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3369 | dest = (uint32_t) dest; |
e0c8f9ce | 3370 | } |
57fec1fe | 3371 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3372 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3373 | tcg_gen_goto_tb(n); |
a2ffb812 | 3374 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
4b4a72e5 | 3375 | tcg_gen_exit_tb((tcg_target_long)tb + n); |
c1942362 | 3376 | } else { |
a2ffb812 | 3377 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3378 | if (unlikely(ctx->singlestep_enabled)) { |
3379 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3380 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3381 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3382 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
8cbcb4fa AJ |
3383 | target_ulong tmp = ctx->nip; |
3384 | ctx->nip = dest; | |
e06fcd75 | 3385 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3386 | ctx->nip = tmp; |
3387 | } | |
3388 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3389 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3390 | } |
3391 | } | |
57fec1fe | 3392 | tcg_gen_exit_tb(0); |
c1942362 | 3393 | } |
c53be334 FB |
3394 | } |
3395 | ||
636aa200 | 3396 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3397 | { |
e0c8f9ce RH |
3398 | if (NARROW_MODE(ctx)) { |
3399 | nip = (uint32_t)nip; | |
3400 | } | |
3401 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3402 | } |
3403 | ||
79aceca5 | 3404 | /* b ba bl bla */ |
99e300ef | 3405 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3406 | { |
76a66253 | 3407 | target_ulong li, target; |
38a64f9d | 3408 | |
8cbcb4fa | 3409 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3410 | /* sign extend LI */ |
e0c8f9ce RH |
3411 | li = LI(ctx->opcode); |
3412 | li = (li ^ 0x02000000) - 0x02000000; | |
3413 | if (likely(AA(ctx->opcode) == 0)) { | |
046d6672 | 3414 | target = ctx->nip + li - 4; |
e0c8f9ce | 3415 | } else { |
9a64fbe4 | 3416 | target = li; |
e0c8f9ce RH |
3417 | } |
3418 | if (LK(ctx->opcode)) { | |
e1833e1f | 3419 | gen_setlr(ctx, ctx->nip); |
e0c8f9ce | 3420 | } |
697ab892 | 3421 | gen_update_cfar(ctx, ctx->nip); |
c1942362 | 3422 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3423 | } |
3424 | ||
e98a6e40 FB |
3425 | #define BCOND_IM 0 |
3426 | #define BCOND_LR 1 | |
3427 | #define BCOND_CTR 2 | |
3428 | ||
636aa200 | 3429 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3430 | { |
d9bce9d9 | 3431 | uint32_t bo = BO(ctx->opcode); |
05f92404 | 3432 | int l1; |
a2ffb812 | 3433 | TCGv target; |
e98a6e40 | 3434 | |
8cbcb4fa | 3435 | ctx->exception = POWERPC_EXCP_BRANCH; |
a2ffb812 | 3436 | if (type == BCOND_LR || type == BCOND_CTR) { |
a7812ae4 | 3437 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3438 | if (type == BCOND_CTR) |
3439 | tcg_gen_mov_tl(target, cpu_ctr); | |
3440 | else | |
3441 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3442 | } else { |
3443 | TCGV_UNUSED(target); | |
e98a6e40 | 3444 | } |
e1833e1f JM |
3445 | if (LK(ctx->opcode)) |
3446 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3447 | l1 = gen_new_label(); |
3448 | if ((bo & 0x4) == 0) { | |
3449 | /* Decrement and test CTR */ | |
a7812ae4 | 3450 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3451 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3452 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3453 | return; |
3454 | } | |
3455 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3456 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3457 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3458 | } else { |
a2ffb812 | 3459 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3460 | } |
a2ffb812 AJ |
3461 | if (bo & 0x2) { |
3462 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3463 | } else { | |
3464 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3465 | } |
a7812ae4 | 3466 | tcg_temp_free(temp); |
a2ffb812 AJ |
3467 | } |
3468 | if ((bo & 0x10) == 0) { | |
3469 | /* Test CR */ | |
3470 | uint32_t bi = BI(ctx->opcode); | |
3471 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3472 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3473 | |
d9bce9d9 | 3474 | if (bo & 0x8) { |
a2ffb812 AJ |
3475 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3476 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3477 | } else { |
a2ffb812 AJ |
3478 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3479 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3480 | } |
a7812ae4 | 3481 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3482 | } |
697ab892 | 3483 | gen_update_cfar(ctx, ctx->nip); |
e98a6e40 | 3484 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3485 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3486 | if (likely(AA(ctx->opcode) == 0)) { | |
3487 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3488 | } else { | |
3489 | gen_goto_tb(ctx, 0, li); | |
3490 | } | |
c53be334 | 3491 | gen_set_label(l1); |
c1942362 | 3492 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3493 | } else { |
e0c8f9ce | 3494 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3495 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3496 | } else { |
a2ffb812 | 3497 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3498 | } |
a2ffb812 AJ |
3499 | tcg_gen_exit_tb(0); |
3500 | gen_set_label(l1); | |
e0c8f9ce | 3501 | gen_update_nip(ctx, ctx->nip); |
57fec1fe | 3502 | tcg_gen_exit_tb(0); |
08e46e54 | 3503 | } |
e98a6e40 FB |
3504 | } |
3505 | ||
99e300ef | 3506 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3507 | { |
e98a6e40 FB |
3508 | gen_bcond(ctx, BCOND_IM); |
3509 | } | |
3510 | ||
99e300ef | 3511 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3512 | { |
e98a6e40 FB |
3513 | gen_bcond(ctx, BCOND_CTR); |
3514 | } | |
3515 | ||
99e300ef | 3516 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3517 | { |
e98a6e40 FB |
3518 | gen_bcond(ctx, BCOND_LR); |
3519 | } | |
79aceca5 FB |
3520 | |
3521 | /*** Condition register logical ***/ | |
e1571908 | 3522 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3523 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3524 | { \ |
fc0d441e JM |
3525 | uint8_t bitmask; \ |
3526 | int sh; \ | |
a7812ae4 | 3527 | TCGv_i32 t0, t1; \ |
fc0d441e | 3528 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3529 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3530 | if (sh > 0) \ |
fea0c503 | 3531 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3532 | else if (sh < 0) \ |
fea0c503 | 3533 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3534 | else \ |
fea0c503 | 3535 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3536 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3537 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3538 | if (sh > 0) \ | |
fea0c503 | 3539 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3540 | else if (sh < 0) \ |
fea0c503 | 3541 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3542 | else \ |
fea0c503 AJ |
3543 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3544 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3545 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3546 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3547 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3548 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3549 | tcg_temp_free_i32(t0); \ |
3550 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3551 | } |
3552 | ||
3553 | /* crand */ | |
e1571908 | 3554 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3555 | /* crandc */ |
e1571908 | 3556 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3557 | /* creqv */ |
e1571908 | 3558 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3559 | /* crnand */ |
e1571908 | 3560 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3561 | /* crnor */ |
e1571908 | 3562 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3563 | /* cror */ |
e1571908 | 3564 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3565 | /* crorc */ |
e1571908 | 3566 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3567 | /* crxor */ |
e1571908 | 3568 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3569 | |
54623277 | 3570 | /* mcrf */ |
99e300ef | 3571 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3572 | { |
47e4661c | 3573 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3574 | } |
3575 | ||
3576 | /*** System linkage ***/ | |
99e300ef | 3577 | |
54623277 | 3578 | /* rfi (mem_idx only) */ |
99e300ef | 3579 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3580 | { |
9a64fbe4 | 3581 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3582 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3583 | #else |
3584 | /* Restore CPU state */ | |
76db3ba4 | 3585 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3586 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3587 | return; |
9a64fbe4 | 3588 | } |
697ab892 | 3589 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3590 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3591 | gen_sync_exception(ctx); |
9a64fbe4 | 3592 | #endif |
79aceca5 FB |
3593 | } |
3594 | ||
426613db | 3595 | #if defined(TARGET_PPC64) |
99e300ef | 3596 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3597 | { |
3598 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3599 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3600 | #else |
3601 | /* Restore CPU state */ | |
76db3ba4 | 3602 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3603 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3604 | return; |
3605 | } | |
697ab892 | 3606 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3607 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3608 | gen_sync_exception(ctx); |
426613db JM |
3609 | #endif |
3610 | } | |
426613db | 3611 | |
99e300ef | 3612 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3613 | { |
3614 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3615 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3616 | #else |
3617 | /* Restore CPU state */ | |
76db3ba4 | 3618 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 3619 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3620 | return; |
3621 | } | |
e5f17ac6 | 3622 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3623 | gen_sync_exception(ctx); |
be147d08 JM |
3624 | #endif |
3625 | } | |
3626 | #endif | |
3627 | ||
79aceca5 | 3628 | /* sc */ |
417bf010 JM |
3629 | #if defined(CONFIG_USER_ONLY) |
3630 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3631 | #else | |
3632 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3633 | #endif | |
99e300ef | 3634 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3635 | { |
e1833e1f JM |
3636 | uint32_t lev; |
3637 | ||
3638 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3639 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3640 | } |
3641 | ||
3642 | /*** Trap ***/ | |
99e300ef | 3643 | |
54623277 | 3644 | /* tw */ |
99e300ef | 3645 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3646 | { |
cab3bee2 | 3647 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3648 | /* Update the nip since this might generate a trap exception */ |
3649 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3650 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3651 | t0); | |
cab3bee2 | 3652 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3653 | } |
3654 | ||
3655 | /* twi */ | |
99e300ef | 3656 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3657 | { |
cab3bee2 AJ |
3658 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3659 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3660 | /* Update the nip since this might generate a trap exception */ |
3661 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3662 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3663 | tcg_temp_free(t0); |
3664 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3665 | } |
3666 | ||
d9bce9d9 JM |
3667 | #if defined(TARGET_PPC64) |
3668 | /* td */ | |
99e300ef | 3669 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3670 | { |
cab3bee2 | 3671 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3672 | /* Update the nip since this might generate a trap exception */ |
3673 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3674 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3675 | t0); | |
cab3bee2 | 3676 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3677 | } |
3678 | ||
3679 | /* tdi */ | |
99e300ef | 3680 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3681 | { |
cab3bee2 AJ |
3682 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3683 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3684 | /* Update the nip since this might generate a trap exception */ |
3685 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3686 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3687 | tcg_temp_free(t0); |
3688 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3689 | } |
3690 | #endif | |
3691 | ||
79aceca5 | 3692 | /*** Processor control ***/ |
99e300ef | 3693 | |
da91a00f RH |
3694 | static void gen_read_xer(TCGv dst) |
3695 | { | |
3696 | TCGv t0 = tcg_temp_new(); | |
3697 | TCGv t1 = tcg_temp_new(); | |
3698 | TCGv t2 = tcg_temp_new(); | |
3699 | tcg_gen_mov_tl(dst, cpu_xer); | |
3700 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
3701 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
3702 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
3703 | tcg_gen_or_tl(t0, t0, t1); | |
3704 | tcg_gen_or_tl(dst, dst, t2); | |
3705 | tcg_gen_or_tl(dst, dst, t0); | |
3706 | tcg_temp_free(t0); | |
3707 | tcg_temp_free(t1); | |
3708 | tcg_temp_free(t2); | |
3709 | } | |
3710 | ||
3711 | static void gen_write_xer(TCGv src) | |
3712 | { | |
3713 | tcg_gen_andi_tl(cpu_xer, src, | |
3714 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
3715 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
3716 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
3717 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
3718 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
3719 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
3720 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
3721 | } | |
3722 | ||
54623277 | 3723 | /* mcrxr */ |
99e300ef | 3724 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3725 | { |
da91a00f RH |
3726 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3727 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3728 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3729 | ||
3730 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
3731 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
3732 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
3733 | tcg_gen_shri_i32(t0, t0, 2); | |
3734 | tcg_gen_shri_i32(t1, t1, 1); | |
3735 | tcg_gen_or_i32(dst, dst, t0); | |
3736 | tcg_gen_or_i32(dst, dst, t1); | |
3737 | tcg_temp_free_i32(t0); | |
3738 | tcg_temp_free_i32(t1); | |
3739 | ||
3740 | tcg_gen_movi_tl(cpu_so, 0); | |
3741 | tcg_gen_movi_tl(cpu_ov, 0); | |
3742 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
3743 | } |
3744 | ||
0cfe11ea | 3745 | /* mfcr mfocrf */ |
99e300ef | 3746 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3747 | { |
76a66253 | 3748 | uint32_t crm, crn; |
3b46e624 | 3749 | |
76a66253 JM |
3750 | if (likely(ctx->opcode & 0x00100000)) { |
3751 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3752 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3753 | crn = ctz32 (crm); |
e1571908 | 3754 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3755 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3756 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3757 | } |
d9bce9d9 | 3758 | } else { |
651721b2 AJ |
3759 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3760 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3761 | tcg_gen_shli_i32(t0, t0, 4); | |
3762 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3763 | tcg_gen_shli_i32(t0, t0, 4); | |
3764 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3765 | tcg_gen_shli_i32(t0, t0, 4); | |
3766 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3767 | tcg_gen_shli_i32(t0, t0, 4); | |
3768 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3769 | tcg_gen_shli_i32(t0, t0, 4); | |
3770 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3771 | tcg_gen_shli_i32(t0, t0, 4); | |
3772 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3773 | tcg_gen_shli_i32(t0, t0, 4); | |
3774 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3775 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3776 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3777 | } |
79aceca5 FB |
3778 | } |
3779 | ||
3780 | /* mfmsr */ | |
99e300ef | 3781 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3782 | { |
9a64fbe4 | 3783 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3784 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3785 | #else |
76db3ba4 | 3786 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3787 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3788 | return; |
9a64fbe4 | 3789 | } |
6527f6ea | 3790 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 3791 | #endif |
79aceca5 FB |
3792 | } |
3793 | ||
7b13448f | 3794 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3fc6c082 | 3795 | { |
7b13448f | 3796 | #if 0 |
3fc6c082 FB |
3797 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3798 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3799 | #endif |
3fc6c082 FB |
3800 | } |
3801 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3802 | |
79aceca5 | 3803 | /* mfspr */ |
636aa200 | 3804 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 3805 | { |
45d827d2 | 3806 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
3807 | uint32_t sprn = SPR(ctx->opcode); |
3808 | ||
3fc6c082 | 3809 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 3810 | if (ctx->mem_idx == 2) |
be147d08 | 3811 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 3812 | else if (ctx->mem_idx) |
3fc6c082 FB |
3813 | read_cb = ctx->spr_cb[sprn].oea_read; |
3814 | else | |
9a64fbe4 | 3815 | #endif |
3fc6c082 | 3816 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
3817 | if (likely(read_cb != NULL)) { |
3818 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 3819 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
3820 | } else { |
3821 | /* Privilege exception */ | |
9fceefa7 JM |
3822 | /* This is a hack to avoid warnings when running Linux: |
3823 | * this OS breaks the PowerPC virtualisation model, | |
3824 | * allowing userland application to read the PVR | |
3825 | */ | |
3826 | if (sprn != SPR_PVR) { | |
93fcfe39 | 3827 | qemu_log("Trying to read privileged spr %d %03x at " |
90e189ec BS |
3828 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3829 | printf("Trying to read privileged spr %d %03x at " | |
3830 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); | |
f24e5695 | 3831 | } |
e06fcd75 | 3832 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 3833 | } |
3fc6c082 FB |
3834 | } else { |
3835 | /* Not defined */ | |
93fcfe39 | 3836 | qemu_log("Trying to read invalid spr %d %03x at " |
90e189ec BS |
3837 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3838 | printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 3839 | sprn, sprn, ctx->nip); |
e06fcd75 | 3840 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 3841 | } |
79aceca5 FB |
3842 | } |
3843 | ||
99e300ef | 3844 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 3845 | { |
3fc6c082 | 3846 | gen_op_mfspr(ctx); |
76a66253 | 3847 | } |
3fc6c082 FB |
3848 | |
3849 | /* mftb */ | |
99e300ef | 3850 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
3851 | { |
3852 | gen_op_mfspr(ctx); | |
79aceca5 FB |
3853 | } |
3854 | ||
0cfe11ea | 3855 | /* mtcrf mtocrf*/ |
99e300ef | 3856 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 3857 | { |
76a66253 | 3858 | uint32_t crm, crn; |
3b46e624 | 3859 | |
76a66253 | 3860 | crm = CRM(ctx->opcode); |
8dd640e4 | 3861 | if (likely((ctx->opcode & 0x00100000))) { |
3862 | if (crm && ((crm & (crm - 1)) == 0)) { | |
3863 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 3864 | crn = ctz32 (crm); |
8dd640e4 | 3865 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
3866 | tcg_gen_shri_i32(temp, temp, crn * 4); |
3867 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 3868 | tcg_temp_free_i32(temp); |
3869 | } | |
76a66253 | 3870 | } else { |
651721b2 AJ |
3871 | TCGv_i32 temp = tcg_temp_new_i32(); |
3872 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
3873 | for (crn = 0 ; crn < 8 ; crn++) { | |
3874 | if (crm & (1 << crn)) { | |
3875 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
3876 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
3877 | } | |
3878 | } | |
a7812ae4 | 3879 | tcg_temp_free_i32(temp); |
76a66253 | 3880 | } |
79aceca5 FB |
3881 | } |
3882 | ||
3883 | /* mtmsr */ | |
426613db | 3884 | #if defined(TARGET_PPC64) |
99e300ef | 3885 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
3886 | { |
3887 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3888 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 3889 | #else |
76db3ba4 | 3890 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3891 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
3892 | return; |
3893 | } | |
be147d08 JM |
3894 | if (ctx->opcode & 0x00010000) { |
3895 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3896 | TCGv t0 = tcg_temp_new(); |
3897 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
3898 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
3899 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
3900 | tcg_temp_free(t0); | |
be147d08 | 3901 | } else { |
056b05f8 JM |
3902 | /* XXX: we need to update nip before the store |
3903 | * if we enter power saving mode, we will exit the loop | |
3904 | * directly from ppc_store_msr | |
3905 | */ | |
be147d08 | 3906 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 3907 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
3908 | /* Must stop the translation as machine state (may have) changed */ |
3909 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 3910 | gen_stop_exception(ctx); |
be147d08 | 3911 | } |
426613db JM |
3912 | #endif |
3913 | } | |
3914 | #endif | |
3915 | ||
99e300ef | 3916 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 3917 | { |
9a64fbe4 | 3918 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3919 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3920 | #else |
76db3ba4 | 3921 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3922 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3923 | return; |
9a64fbe4 | 3924 | } |
be147d08 JM |
3925 | if (ctx->opcode & 0x00010000) { |
3926 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3927 | TCGv t0 = tcg_temp_new(); |
3928 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
3929 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
3930 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
3931 | tcg_temp_free(t0); | |
be147d08 | 3932 | } else { |
8018dc63 AG |
3933 | TCGv msr = tcg_temp_new(); |
3934 | ||
056b05f8 JM |
3935 | /* XXX: we need to update nip before the store |
3936 | * if we enter power saving mode, we will exit the loop | |
3937 | * directly from ppc_store_msr | |
3938 | */ | |
be147d08 | 3939 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 3940 | #if defined(TARGET_PPC64) |
8018dc63 AG |
3941 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
3942 | #else | |
3943 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 3944 | #endif |
e5f17ac6 | 3945 | gen_helper_store_msr(cpu_env, msr); |
be147d08 | 3946 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 3947 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 3948 | gen_stop_exception(ctx); |
be147d08 | 3949 | } |
9a64fbe4 | 3950 | #endif |
79aceca5 FB |
3951 | } |
3952 | ||
3953 | /* mtspr */ | |
99e300ef | 3954 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 3955 | { |
45d827d2 | 3956 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
3957 | uint32_t sprn = SPR(ctx->opcode); |
3958 | ||
3fc6c082 | 3959 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 3960 | if (ctx->mem_idx == 2) |
be147d08 | 3961 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 3962 | else if (ctx->mem_idx) |
3fc6c082 FB |
3963 | write_cb = ctx->spr_cb[sprn].oea_write; |
3964 | else | |
9a64fbe4 | 3965 | #endif |
3fc6c082 | 3966 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
3967 | if (likely(write_cb != NULL)) { |
3968 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 3969 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
3970 | } else { |
3971 | /* Privilege exception */ | |
93fcfe39 | 3972 | qemu_log("Trying to write privileged spr %d %03x at " |
90e189ec BS |
3973 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3974 | printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx | |
3975 | "\n", sprn, sprn, ctx->nip); | |
e06fcd75 | 3976 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 3977 | } |
3fc6c082 FB |
3978 | } else { |
3979 | /* Not defined */ | |
93fcfe39 | 3980 | qemu_log("Trying to write invalid spr %d %03x at " |
90e189ec BS |
3981 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3982 | printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 3983 | sprn, sprn, ctx->nip); |
e06fcd75 | 3984 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 3985 | } |
79aceca5 FB |
3986 | } |
3987 | ||
3988 | /*** Cache management ***/ | |
99e300ef | 3989 | |
54623277 | 3990 | /* dcbf */ |
99e300ef | 3991 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 3992 | { |
dac454af | 3993 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
3994 | TCGv t0; |
3995 | gen_set_access_type(ctx, ACCESS_CACHE); | |
3996 | t0 = tcg_temp_new(); | |
3997 | gen_addr_reg_index(ctx, t0); | |
3998 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 3999 | tcg_temp_free(t0); |
79aceca5 FB |
4000 | } |
4001 | ||
4002 | /* dcbi (Supervisor only) */ | |
99e300ef | 4003 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4004 | { |
a541f297 | 4005 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4006 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4007 | #else |
b61f2753 | 4008 | TCGv EA, val; |
76db3ba4 | 4009 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4010 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4011 | return; |
9a64fbe4 | 4012 | } |
a7812ae4 | 4013 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4014 | gen_set_access_type(ctx, ACCESS_CACHE); |
4015 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4016 | val = tcg_temp_new(); |
76a66253 | 4017 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4018 | gen_qemu_ld8u(ctx, val, EA); |
4019 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4020 | tcg_temp_free(val); |
4021 | tcg_temp_free(EA); | |
a541f297 | 4022 | #endif |
79aceca5 FB |
4023 | } |
4024 | ||
4025 | /* dcdst */ | |
99e300ef | 4026 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4027 | { |
76a66253 | 4028 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4029 | TCGv t0; |
4030 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4031 | t0 = tcg_temp_new(); | |
4032 | gen_addr_reg_index(ctx, t0); | |
4033 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4034 | tcg_temp_free(t0); |
79aceca5 FB |
4035 | } |
4036 | ||
4037 | /* dcbt */ | |
99e300ef | 4038 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4039 | { |
0db1b20e | 4040 | /* interpreted as no-op */ |
76a66253 JM |
4041 | /* XXX: specification say this is treated as a load by the MMU |
4042 | * but does not generate any exception | |
4043 | */ | |
79aceca5 FB |
4044 | } |
4045 | ||
4046 | /* dcbtst */ | |
99e300ef | 4047 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4048 | { |
0db1b20e | 4049 | /* interpreted as no-op */ |
76a66253 JM |
4050 | /* XXX: specification say this is treated as a load by the MMU |
4051 | * but does not generate any exception | |
4052 | */ | |
79aceca5 FB |
4053 | } |
4054 | ||
4055 | /* dcbz */ | |
99e300ef | 4056 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4057 | { |
8e33944f AG |
4058 | TCGv tcgv_addr; |
4059 | TCGv_i32 tcgv_is_dcbzl; | |
4060 | int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; | |
d63001d1 | 4061 | |
76db3ba4 | 4062 | gen_set_access_type(ctx, ACCESS_CACHE); |
799a8c8d AJ |
4063 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4064 | gen_update_nip(ctx, ctx->nip - 4); | |
8e33944f AG |
4065 | tcgv_addr = tcg_temp_new(); |
4066 | tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); | |
4067 | ||
4068 | gen_addr_reg_index(ctx, tcgv_addr); | |
4069 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); | |
4070 | ||
4071 | tcg_temp_free(tcgv_addr); | |
4072 | tcg_temp_free_i32(tcgv_is_dcbzl); | |
79aceca5 FB |
4073 | } |
4074 | ||
ae1c1a3d | 4075 | /* dst / dstt */ |
99e300ef | 4076 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4077 | { |
4078 | if (rA(ctx->opcode) == 0) { | |
4079 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4080 | } else { | |
4081 | /* interpreted as no-op */ | |
4082 | } | |
4083 | } | |
4084 | ||
4085 | /* dstst /dststt */ | |
99e300ef | 4086 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4087 | { |
4088 | if (rA(ctx->opcode) == 0) { | |
4089 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4090 | } else { | |
4091 | /* interpreted as no-op */ | |
4092 | } | |
4093 | ||
4094 | } | |
4095 | ||
4096 | /* dss / dssall */ | |
99e300ef | 4097 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4098 | { |
4099 | /* interpreted as no-op */ | |
4100 | } | |
4101 | ||
79aceca5 | 4102 | /* icbi */ |
99e300ef | 4103 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4104 | { |
76db3ba4 AJ |
4105 | TCGv t0; |
4106 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4107 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4108 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4109 | t0 = tcg_temp_new(); |
4110 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4111 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4112 | tcg_temp_free(t0); |
79aceca5 FB |
4113 | } |
4114 | ||
4115 | /* Optional: */ | |
4116 | /* dcba */ | |
99e300ef | 4117 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4118 | { |
0db1b20e JM |
4119 | /* interpreted as no-op */ |
4120 | /* XXX: specification say this is treated as a store by the MMU | |
4121 | * but does not generate any exception | |
4122 | */ | |
79aceca5 FB |
4123 | } |
4124 | ||
4125 | /*** Segment register manipulation ***/ | |
4126 | /* Supervisor only: */ | |
99e300ef | 4127 | |
54623277 | 4128 | /* mfsr */ |
99e300ef | 4129 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4130 | { |
9a64fbe4 | 4131 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4132 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4133 | #else |
74d37793 | 4134 | TCGv t0; |
76db3ba4 | 4135 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4136 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4137 | return; |
9a64fbe4 | 4138 | } |
74d37793 | 4139 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4140 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4141 | tcg_temp_free(t0); |
9a64fbe4 | 4142 | #endif |
79aceca5 FB |
4143 | } |
4144 | ||
4145 | /* mfsrin */ | |
99e300ef | 4146 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4147 | { |
9a64fbe4 | 4148 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4149 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4150 | #else |
74d37793 | 4151 | TCGv t0; |
76db3ba4 | 4152 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4153 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4154 | return; |
9a64fbe4 | 4155 | } |
74d37793 AJ |
4156 | t0 = tcg_temp_new(); |
4157 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4158 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4159 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4160 | tcg_temp_free(t0); |
9a64fbe4 | 4161 | #endif |
79aceca5 FB |
4162 | } |
4163 | ||
4164 | /* mtsr */ | |
99e300ef | 4165 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4166 | { |
9a64fbe4 | 4167 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4168 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4169 | #else |
74d37793 | 4170 | TCGv t0; |
76db3ba4 | 4171 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4172 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4173 | return; |
9a64fbe4 | 4174 | } |
74d37793 | 4175 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4176 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4177 | tcg_temp_free(t0); |
9a64fbe4 | 4178 | #endif |
79aceca5 FB |
4179 | } |
4180 | ||
4181 | /* mtsrin */ | |
99e300ef | 4182 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4183 | { |
9a64fbe4 | 4184 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4185 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4186 | #else |
74d37793 | 4187 | TCGv t0; |
76db3ba4 | 4188 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4189 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4190 | return; |
9a64fbe4 | 4191 | } |
74d37793 AJ |
4192 | t0 = tcg_temp_new(); |
4193 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4194 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4195 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4196 | tcg_temp_free(t0); |
9a64fbe4 | 4197 | #endif |
79aceca5 FB |
4198 | } |
4199 | ||
12de9a39 JM |
4200 | #if defined(TARGET_PPC64) |
4201 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4202 | |
54623277 | 4203 | /* mfsr */ |
e8eaa2c0 | 4204 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4205 | { |
4206 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4207 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4208 | #else |
74d37793 | 4209 | TCGv t0; |
76db3ba4 | 4210 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4211 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4212 | return; |
4213 | } | |
74d37793 | 4214 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4215 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4216 | tcg_temp_free(t0); |
12de9a39 JM |
4217 | #endif |
4218 | } | |
4219 | ||
4220 | /* mfsrin */ | |
e8eaa2c0 | 4221 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4222 | { |
4223 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4224 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4225 | #else |
74d37793 | 4226 | TCGv t0; |
76db3ba4 | 4227 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4228 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4229 | return; |
4230 | } | |
74d37793 AJ |
4231 | t0 = tcg_temp_new(); |
4232 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4233 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4234 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4235 | tcg_temp_free(t0); |
12de9a39 JM |
4236 | #endif |
4237 | } | |
4238 | ||
4239 | /* mtsr */ | |
e8eaa2c0 | 4240 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4241 | { |
4242 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4243 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4244 | #else |
74d37793 | 4245 | TCGv t0; |
76db3ba4 | 4246 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4247 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4248 | return; |
4249 | } | |
74d37793 | 4250 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4251 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4252 | tcg_temp_free(t0); |
12de9a39 JM |
4253 | #endif |
4254 | } | |
4255 | ||
4256 | /* mtsrin */ | |
e8eaa2c0 | 4257 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4258 | { |
4259 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4260 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4261 | #else |
74d37793 | 4262 | TCGv t0; |
76db3ba4 | 4263 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4264 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4265 | return; |
4266 | } | |
74d37793 AJ |
4267 | t0 = tcg_temp_new(); |
4268 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4269 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4270 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4271 | tcg_temp_free(t0); |
12de9a39 JM |
4272 | #endif |
4273 | } | |
f6b868fc BS |
4274 | |
4275 | /* slbmte */ | |
e8eaa2c0 | 4276 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4277 | { |
4278 | #if defined(CONFIG_USER_ONLY) | |
4279 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4280 | #else | |
4281 | if (unlikely(!ctx->mem_idx)) { | |
4282 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4283 | return; | |
4284 | } | |
c6c7cf05 BS |
4285 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4286 | cpu_gpr[rS(ctx->opcode)]); | |
f6b868fc BS |
4287 | #endif |
4288 | } | |
4289 | ||
efdef95f DG |
4290 | static void gen_slbmfee(DisasContext *ctx) |
4291 | { | |
4292 | #if defined(CONFIG_USER_ONLY) | |
4293 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4294 | #else | |
4295 | if (unlikely(!ctx->mem_idx)) { | |
4296 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4297 | return; | |
4298 | } | |
c6c7cf05 | 4299 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4300 | cpu_gpr[rB(ctx->opcode)]); |
4301 | #endif | |
4302 | } | |
4303 | ||
4304 | static void gen_slbmfev(DisasContext *ctx) | |
4305 | { | |
4306 | #if defined(CONFIG_USER_ONLY) | |
4307 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4308 | #else | |
4309 | if (unlikely(!ctx->mem_idx)) { | |
4310 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4311 | return; | |
4312 | } | |
c6c7cf05 | 4313 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4314 | cpu_gpr[rB(ctx->opcode)]); |
4315 | #endif | |
4316 | } | |
12de9a39 JM |
4317 | #endif /* defined(TARGET_PPC64) */ |
4318 | ||
79aceca5 | 4319 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4320 | /* Optional & mem_idx only: */ |
99e300ef | 4321 | |
54623277 | 4322 | /* tlbia */ |
99e300ef | 4323 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4324 | { |
9a64fbe4 | 4325 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4326 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4327 | #else |
76db3ba4 | 4328 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4329 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4330 | return; |
9a64fbe4 | 4331 | } |
c6c7cf05 | 4332 | gen_helper_tlbia(cpu_env); |
9a64fbe4 | 4333 | #endif |
79aceca5 FB |
4334 | } |
4335 | ||
bf14b1ce | 4336 | /* tlbiel */ |
99e300ef | 4337 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4338 | { |
4339 | #if defined(CONFIG_USER_ONLY) | |
4340 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4341 | #else | |
4342 | if (unlikely(!ctx->mem_idx)) { | |
4343 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4344 | return; | |
4345 | } | |
c6c7cf05 | 4346 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
bf14b1ce BS |
4347 | #endif |
4348 | } | |
4349 | ||
79aceca5 | 4350 | /* tlbie */ |
99e300ef | 4351 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4352 | { |
9a64fbe4 | 4353 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4354 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4355 | #else |
76db3ba4 | 4356 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4357 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4358 | return; |
9a64fbe4 | 4359 | } |
9ca3f7f3 | 4360 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4361 | TCGv t0 = tcg_temp_new(); |
4362 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4363 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4364 | tcg_temp_free(t0); |
9ca3f7f3 | 4365 | } else { |
c6c7cf05 | 4366 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4367 | } |
9a64fbe4 | 4368 | #endif |
79aceca5 FB |
4369 | } |
4370 | ||
4371 | /* tlbsync */ | |
99e300ef | 4372 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4373 | { |
9a64fbe4 | 4374 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4375 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4376 | #else |
76db3ba4 | 4377 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4378 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4379 | return; |
9a64fbe4 FB |
4380 | } |
4381 | /* This has no effect: it should ensure that all previous | |
4382 | * tlbie have completed | |
4383 | */ | |
e06fcd75 | 4384 | gen_stop_exception(ctx); |
9a64fbe4 | 4385 | #endif |
79aceca5 FB |
4386 | } |
4387 | ||
426613db JM |
4388 | #if defined(TARGET_PPC64) |
4389 | /* slbia */ | |
99e300ef | 4390 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4391 | { |
4392 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4393 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4394 | #else |
76db3ba4 | 4395 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4396 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4397 | return; |
4398 | } | |
c6c7cf05 | 4399 | gen_helper_slbia(cpu_env); |
426613db JM |
4400 | #endif |
4401 | } | |
4402 | ||
4403 | /* slbie */ | |
99e300ef | 4404 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4405 | { |
4406 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4407 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4408 | #else |
76db3ba4 | 4409 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4410 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4411 | return; |
4412 | } | |
c6c7cf05 | 4413 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4414 | #endif |
4415 | } | |
4416 | #endif | |
4417 | ||
79aceca5 FB |
4418 | /*** External control ***/ |
4419 | /* Optional: */ | |
99e300ef | 4420 | |
54623277 | 4421 | /* eciwx */ |
99e300ef | 4422 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4423 | { |
76db3ba4 | 4424 | TCGv t0; |
fa407c03 | 4425 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4426 | gen_set_access_type(ctx, ACCESS_EXT); |
4427 | t0 = tcg_temp_new(); | |
4428 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4429 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4430 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4431 | tcg_temp_free(t0); |
76a66253 JM |
4432 | } |
4433 | ||
4434 | /* ecowx */ | |
99e300ef | 4435 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4436 | { |
76db3ba4 | 4437 | TCGv t0; |
fa407c03 | 4438 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4439 | gen_set_access_type(ctx, ACCESS_EXT); |
4440 | t0 = tcg_temp_new(); | |
4441 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4442 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4443 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4444 | tcg_temp_free(t0); |
76a66253 JM |
4445 | } |
4446 | ||
4447 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4448 | |
54623277 | 4449 | /* abs - abs. */ |
99e300ef | 4450 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4451 | { |
22e0e173 AJ |
4452 | int l1 = gen_new_label(); |
4453 | int l2 = gen_new_label(); | |
4454 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4455 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4456 | tcg_gen_br(l2); | |
4457 | gen_set_label(l1); | |
4458 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4459 | gen_set_label(l2); | |
76a66253 | 4460 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4461 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4462 | } |
4463 | ||
4464 | /* abso - abso. */ | |
99e300ef | 4465 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4466 | { |
22e0e173 AJ |
4467 | int l1 = gen_new_label(); |
4468 | int l2 = gen_new_label(); | |
4469 | int l3 = gen_new_label(); | |
4470 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4471 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4472 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4473 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4474 | tcg_gen_movi_tl(cpu_ov, 1); |
4475 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4476 | tcg_gen_br(l2); |
4477 | gen_set_label(l1); | |
4478 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4479 | tcg_gen_br(l3); | |
4480 | gen_set_label(l2); | |
4481 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4482 | gen_set_label(l3); | |
76a66253 | 4483 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4484 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4485 | } |
4486 | ||
4487 | /* clcs */ | |
99e300ef | 4488 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4489 | { |
22e0e173 | 4490 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4491 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4492 | tcg_temp_free_i32(t0); |
c7697e1f | 4493 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4494 | } |
4495 | ||
4496 | /* div - div. */ | |
99e300ef | 4497 | static void gen_div(DisasContext *ctx) |
76a66253 | 4498 | { |
d15f74fb BS |
4499 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4500 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4501 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4502 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4503 | } |
4504 | ||
4505 | /* divo - divo. */ | |
99e300ef | 4506 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4507 | { |
d15f74fb BS |
4508 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4509 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4510 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4511 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4512 | } |
4513 | ||
4514 | /* divs - divs. */ | |
99e300ef | 4515 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4516 | { |
d15f74fb BS |
4517 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4518 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4519 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4520 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4521 | } |
4522 | ||
4523 | /* divso - divso. */ | |
99e300ef | 4524 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4525 | { |
d15f74fb BS |
4526 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4527 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4528 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4529 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4530 | } |
4531 | ||
4532 | /* doz - doz. */ | |
99e300ef | 4533 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4534 | { |
22e0e173 AJ |
4535 | int l1 = gen_new_label(); |
4536 | int l2 = gen_new_label(); | |
4537 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4538 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4539 | tcg_gen_br(l2); | |
4540 | gen_set_label(l1); | |
4541 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4542 | gen_set_label(l2); | |
76a66253 | 4543 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4544 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4545 | } |
4546 | ||
4547 | /* dozo - dozo. */ | |
99e300ef | 4548 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4549 | { |
22e0e173 AJ |
4550 | int l1 = gen_new_label(); |
4551 | int l2 = gen_new_label(); | |
4552 | TCGv t0 = tcg_temp_new(); | |
4553 | TCGv t1 = tcg_temp_new(); | |
4554 | TCGv t2 = tcg_temp_new(); | |
4555 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4556 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4557 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4558 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4559 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4560 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4561 | tcg_gen_andc_tl(t1, t1, t2); | |
4562 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4563 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4564 | tcg_gen_movi_tl(cpu_ov, 1); |
4565 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4566 | tcg_gen_br(l2); |
4567 | gen_set_label(l1); | |
4568 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4569 | gen_set_label(l2); | |
4570 | tcg_temp_free(t0); | |
4571 | tcg_temp_free(t1); | |
4572 | tcg_temp_free(t2); | |
76a66253 | 4573 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4574 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4575 | } |
4576 | ||
4577 | /* dozi */ | |
99e300ef | 4578 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4579 | { |
22e0e173 AJ |
4580 | target_long simm = SIMM(ctx->opcode); |
4581 | int l1 = gen_new_label(); | |
4582 | int l2 = gen_new_label(); | |
4583 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
4584 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4585 | tcg_gen_br(l2); | |
4586 | gen_set_label(l1); | |
4587 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4588 | gen_set_label(l2); | |
4589 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4590 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4591 | } |
4592 | ||
76a66253 | 4593 | /* lscbx - lscbx. */ |
99e300ef | 4594 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4595 | { |
bdb4b689 AJ |
4596 | TCGv t0 = tcg_temp_new(); |
4597 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4598 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4599 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4600 | |
76db3ba4 | 4601 | gen_addr_reg_index(ctx, t0); |
76a66253 | 4602 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 4603 | gen_update_nip(ctx, ctx->nip - 4); |
2f5a189c | 4604 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4605 | tcg_temp_free_i32(t1); |
4606 | tcg_temp_free_i32(t2); | |
4607 | tcg_temp_free_i32(t3); | |
3d7b417e | 4608 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4609 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4610 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4611 | gen_set_Rc0(ctx, t0); |
4612 | tcg_temp_free(t0); | |
76a66253 JM |
4613 | } |
4614 | ||
4615 | /* maskg - maskg. */ | |
99e300ef | 4616 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4617 | { |
22e0e173 AJ |
4618 | int l1 = gen_new_label(); |
4619 | TCGv t0 = tcg_temp_new(); | |
4620 | TCGv t1 = tcg_temp_new(); | |
4621 | TCGv t2 = tcg_temp_new(); | |
4622 | TCGv t3 = tcg_temp_new(); | |
4623 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4624 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4625 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4626 | tcg_gen_addi_tl(t2, t0, 1); | |
4627 | tcg_gen_shr_tl(t2, t3, t2); | |
4628 | tcg_gen_shr_tl(t3, t3, t1); | |
4629 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4630 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4631 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4632 | gen_set_label(l1); | |
4633 | tcg_temp_free(t0); | |
4634 | tcg_temp_free(t1); | |
4635 | tcg_temp_free(t2); | |
4636 | tcg_temp_free(t3); | |
76a66253 | 4637 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4638 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4639 | } |
4640 | ||
4641 | /* maskir - maskir. */ | |
99e300ef | 4642 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4643 | { |
22e0e173 AJ |
4644 | TCGv t0 = tcg_temp_new(); |
4645 | TCGv t1 = tcg_temp_new(); | |
4646 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4647 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4648 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4649 | tcg_temp_free(t0); | |
4650 | tcg_temp_free(t1); | |
76a66253 | 4651 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4652 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4653 | } |
4654 | ||
4655 | /* mul - mul. */ | |
99e300ef | 4656 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4657 | { |
22e0e173 AJ |
4658 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4659 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4660 | TCGv t2 = tcg_temp_new(); | |
4661 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4662 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4663 | tcg_gen_mul_i64(t0, t0, t1); | |
4664 | tcg_gen_trunc_i64_tl(t2, t0); | |
4665 | gen_store_spr(SPR_MQ, t2); | |
4666 | tcg_gen_shri_i64(t1, t0, 32); | |
4667 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4668 | tcg_temp_free_i64(t0); | |
4669 | tcg_temp_free_i64(t1); | |
4670 | tcg_temp_free(t2); | |
76a66253 | 4671 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4672 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4673 | } |
4674 | ||
4675 | /* mulo - mulo. */ | |
99e300ef | 4676 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4677 | { |
22e0e173 AJ |
4678 | int l1 = gen_new_label(); |
4679 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
4680 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4681 | TCGv t2 = tcg_temp_new(); | |
4682 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4683 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4684 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4685 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4686 | tcg_gen_mul_i64(t0, t0, t1); | |
4687 | tcg_gen_trunc_i64_tl(t2, t0); | |
4688 | gen_store_spr(SPR_MQ, t2); | |
4689 | tcg_gen_shri_i64(t1, t0, 32); | |
4690 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4691 | tcg_gen_ext32s_i64(t1, t0); | |
4692 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
4693 | tcg_gen_movi_tl(cpu_ov, 1); |
4694 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4695 | gen_set_label(l1); |
4696 | tcg_temp_free_i64(t0); | |
4697 | tcg_temp_free_i64(t1); | |
4698 | tcg_temp_free(t2); | |
76a66253 | 4699 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4700 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4701 | } |
4702 | ||
4703 | /* nabs - nabs. */ | |
99e300ef | 4704 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4705 | { |
22e0e173 AJ |
4706 | int l1 = gen_new_label(); |
4707 | int l2 = gen_new_label(); | |
4708 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4709 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4710 | tcg_gen_br(l2); | |
4711 | gen_set_label(l1); | |
4712 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4713 | gen_set_label(l2); | |
76a66253 | 4714 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4715 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4716 | } |
4717 | ||
4718 | /* nabso - nabso. */ | |
99e300ef | 4719 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4720 | { |
22e0e173 AJ |
4721 | int l1 = gen_new_label(); |
4722 | int l2 = gen_new_label(); | |
4723 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4724 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4725 | tcg_gen_br(l2); | |
4726 | gen_set_label(l1); | |
4727 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4728 | gen_set_label(l2); | |
4729 | /* nabs never overflows */ | |
da91a00f | 4730 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 4731 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4732 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4733 | } |
4734 | ||
4735 | /* rlmi - rlmi. */ | |
99e300ef | 4736 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4737 | { |
7487953d AJ |
4738 | uint32_t mb = MB(ctx->opcode); |
4739 | uint32_t me = ME(ctx->opcode); | |
4740 | TCGv t0 = tcg_temp_new(); | |
4741 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4742 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4743 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4744 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4745 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4746 | tcg_temp_free(t0); | |
76a66253 | 4747 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4748 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4749 | } |
4750 | ||
4751 | /* rrib - rrib. */ | |
99e300ef | 4752 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4753 | { |
7487953d AJ |
4754 | TCGv t0 = tcg_temp_new(); |
4755 | TCGv t1 = tcg_temp_new(); | |
4756 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4757 | tcg_gen_movi_tl(t1, 0x80000000); | |
4758 | tcg_gen_shr_tl(t1, t1, t0); | |
4759 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4760 | tcg_gen_and_tl(t0, t0, t1); | |
4761 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4762 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4763 | tcg_temp_free(t0); | |
4764 | tcg_temp_free(t1); | |
76a66253 | 4765 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4766 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4767 | } |
4768 | ||
4769 | /* sle - sle. */ | |
99e300ef | 4770 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4771 | { |
7487953d AJ |
4772 | TCGv t0 = tcg_temp_new(); |
4773 | TCGv t1 = tcg_temp_new(); | |
4774 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4775 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4776 | tcg_gen_subfi_tl(t1, 32, t1); | |
4777 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4778 | tcg_gen_or_tl(t1, t0, t1); | |
4779 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4780 | gen_store_spr(SPR_MQ, t1); | |
4781 | tcg_temp_free(t0); | |
4782 | tcg_temp_free(t1); | |
76a66253 | 4783 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4784 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4785 | } |
4786 | ||
4787 | /* sleq - sleq. */ | |
99e300ef | 4788 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4789 | { |
7487953d AJ |
4790 | TCGv t0 = tcg_temp_new(); |
4791 | TCGv t1 = tcg_temp_new(); | |
4792 | TCGv t2 = tcg_temp_new(); | |
4793 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4794 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
4795 | tcg_gen_shl_tl(t2, t2, t0); | |
4796 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4797 | gen_load_spr(t1, SPR_MQ); | |
4798 | gen_store_spr(SPR_MQ, t0); | |
4799 | tcg_gen_and_tl(t0, t0, t2); | |
4800 | tcg_gen_andc_tl(t1, t1, t2); | |
4801 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4802 | tcg_temp_free(t0); | |
4803 | tcg_temp_free(t1); | |
4804 | tcg_temp_free(t2); | |
76a66253 | 4805 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4806 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4807 | } |
4808 | ||
4809 | /* sliq - sliq. */ | |
99e300ef | 4810 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 4811 | { |
7487953d AJ |
4812 | int sh = SH(ctx->opcode); |
4813 | TCGv t0 = tcg_temp_new(); | |
4814 | TCGv t1 = tcg_temp_new(); | |
4815 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4816 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4817 | tcg_gen_or_tl(t1, t0, t1); | |
4818 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4819 | gen_store_spr(SPR_MQ, t1); | |
4820 | tcg_temp_free(t0); | |
4821 | tcg_temp_free(t1); | |
76a66253 | 4822 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4823 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4824 | } |
4825 | ||
4826 | /* slliq - slliq. */ | |
99e300ef | 4827 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 4828 | { |
7487953d AJ |
4829 | int sh = SH(ctx->opcode); |
4830 | TCGv t0 = tcg_temp_new(); | |
4831 | TCGv t1 = tcg_temp_new(); | |
4832 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4833 | gen_load_spr(t1, SPR_MQ); | |
4834 | gen_store_spr(SPR_MQ, t0); | |
4835 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
4836 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
4837 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4838 | tcg_temp_free(t0); | |
4839 | tcg_temp_free(t1); | |
76a66253 | 4840 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4841 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4842 | } |
4843 | ||
4844 | /* sllq - sllq. */ | |
99e300ef | 4845 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 4846 | { |
7487953d AJ |
4847 | int l1 = gen_new_label(); |
4848 | int l2 = gen_new_label(); | |
4849 | TCGv t0 = tcg_temp_local_new(); | |
4850 | TCGv t1 = tcg_temp_local_new(); | |
4851 | TCGv t2 = tcg_temp_local_new(); | |
4852 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4853 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4854 | tcg_gen_shl_tl(t1, t1, t2); | |
4855 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4856 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
4857 | gen_load_spr(t0, SPR_MQ); | |
4858 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4859 | tcg_gen_br(l2); | |
4860 | gen_set_label(l1); | |
4861 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4862 | gen_load_spr(t2, SPR_MQ); | |
4863 | tcg_gen_andc_tl(t1, t2, t1); | |
4864 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4865 | gen_set_label(l2); | |
4866 | tcg_temp_free(t0); | |
4867 | tcg_temp_free(t1); | |
4868 | tcg_temp_free(t2); | |
76a66253 | 4869 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4870 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4871 | } |
4872 | ||
4873 | /* slq - slq. */ | |
99e300ef | 4874 | static void gen_slq(DisasContext *ctx) |
76a66253 | 4875 | { |
7487953d AJ |
4876 | int l1 = gen_new_label(); |
4877 | TCGv t0 = tcg_temp_new(); | |
4878 | TCGv t1 = tcg_temp_new(); | |
4879 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4880 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4881 | tcg_gen_subfi_tl(t1, 32, t1); | |
4882 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4883 | tcg_gen_or_tl(t1, t0, t1); | |
4884 | gen_store_spr(SPR_MQ, t1); | |
4885 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4886 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4887 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
4888 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
4889 | gen_set_label(l1); | |
4890 | tcg_temp_free(t0); | |
4891 | tcg_temp_free(t1); | |
76a66253 | 4892 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4893 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4894 | } |
4895 | ||
d9bce9d9 | 4896 | /* sraiq - sraiq. */ |
99e300ef | 4897 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 4898 | { |
7487953d AJ |
4899 | int sh = SH(ctx->opcode); |
4900 | int l1 = gen_new_label(); | |
4901 | TCGv t0 = tcg_temp_new(); | |
4902 | TCGv t1 = tcg_temp_new(); | |
4903 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4904 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4905 | tcg_gen_or_tl(t0, t0, t1); | |
4906 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 4907 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
4908 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
4909 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 4910 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
4911 | gen_set_label(l1); |
4912 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
4913 | tcg_temp_free(t0); | |
4914 | tcg_temp_free(t1); | |
76a66253 | 4915 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4916 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4917 | } |
4918 | ||
4919 | /* sraq - sraq. */ | |
99e300ef | 4920 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 4921 | { |
7487953d AJ |
4922 | int l1 = gen_new_label(); |
4923 | int l2 = gen_new_label(); | |
4924 | TCGv t0 = tcg_temp_new(); | |
4925 | TCGv t1 = tcg_temp_local_new(); | |
4926 | TCGv t2 = tcg_temp_local_new(); | |
4927 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4928 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4929 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
4930 | tcg_gen_subfi_tl(t2, 32, t2); | |
4931 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
4932 | tcg_gen_or_tl(t0, t0, t2); | |
4933 | gen_store_spr(SPR_MQ, t0); | |
4934 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4935 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
4936 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
4937 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
4938 | gen_set_label(l1); | |
4939 | tcg_temp_free(t0); | |
4940 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 4941 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
4942 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
4943 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 4944 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
4945 | gen_set_label(l2); |
4946 | tcg_temp_free(t1); | |
4947 | tcg_temp_free(t2); | |
76a66253 | 4948 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4949 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4950 | } |
4951 | ||
4952 | /* sre - sre. */ | |
99e300ef | 4953 | static void gen_sre(DisasContext *ctx) |
76a66253 | 4954 | { |
7487953d AJ |
4955 | TCGv t0 = tcg_temp_new(); |
4956 | TCGv t1 = tcg_temp_new(); | |
4957 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4958 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4959 | tcg_gen_subfi_tl(t1, 32, t1); | |
4960 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4961 | tcg_gen_or_tl(t1, t0, t1); | |
4962 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4963 | gen_store_spr(SPR_MQ, t1); | |
4964 | tcg_temp_free(t0); | |
4965 | tcg_temp_free(t1); | |
76a66253 | 4966 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4967 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4968 | } |
4969 | ||
4970 | /* srea - srea. */ | |
99e300ef | 4971 | static void gen_srea(DisasContext *ctx) |
76a66253 | 4972 | { |
7487953d AJ |
4973 | TCGv t0 = tcg_temp_new(); |
4974 | TCGv t1 = tcg_temp_new(); | |
4975 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4976 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4977 | gen_store_spr(SPR_MQ, t0); | |
4978 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
4979 | tcg_temp_free(t0); | |
4980 | tcg_temp_free(t1); | |
76a66253 | 4981 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4982 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4983 | } |
4984 | ||
4985 | /* sreq */ | |
99e300ef | 4986 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 4987 | { |
7487953d AJ |
4988 | TCGv t0 = tcg_temp_new(); |
4989 | TCGv t1 = tcg_temp_new(); | |
4990 | TCGv t2 = tcg_temp_new(); | |
4991 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4992 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4993 | tcg_gen_shr_tl(t1, t1, t0); | |
4994 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4995 | gen_load_spr(t2, SPR_MQ); | |
4996 | gen_store_spr(SPR_MQ, t0); | |
4997 | tcg_gen_and_tl(t0, t0, t1); | |
4998 | tcg_gen_andc_tl(t2, t2, t1); | |
4999 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5000 | tcg_temp_free(t0); | |
5001 | tcg_temp_free(t1); | |
5002 | tcg_temp_free(t2); | |
76a66253 | 5003 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5004 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5005 | } |
5006 | ||
5007 | /* sriq */ | |
99e300ef | 5008 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5009 | { |
7487953d AJ |
5010 | int sh = SH(ctx->opcode); |
5011 | TCGv t0 = tcg_temp_new(); | |
5012 | TCGv t1 = tcg_temp_new(); | |
5013 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5014 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5015 | tcg_gen_or_tl(t1, t0, t1); | |
5016 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5017 | gen_store_spr(SPR_MQ, t1); | |
5018 | tcg_temp_free(t0); | |
5019 | tcg_temp_free(t1); | |
76a66253 | 5020 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5021 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5022 | } |
5023 | ||
5024 | /* srliq */ | |
99e300ef | 5025 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5026 | { |
7487953d AJ |
5027 | int sh = SH(ctx->opcode); |
5028 | TCGv t0 = tcg_temp_new(); | |
5029 | TCGv t1 = tcg_temp_new(); | |
5030 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5031 | gen_load_spr(t1, SPR_MQ); | |
5032 | gen_store_spr(SPR_MQ, t0); | |
5033 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5034 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5035 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5036 | tcg_temp_free(t0); | |
5037 | tcg_temp_free(t1); | |
76a66253 | 5038 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5039 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5040 | } |
5041 | ||
5042 | /* srlq */ | |
99e300ef | 5043 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5044 | { |
7487953d AJ |
5045 | int l1 = gen_new_label(); |
5046 | int l2 = gen_new_label(); | |
5047 | TCGv t0 = tcg_temp_local_new(); | |
5048 | TCGv t1 = tcg_temp_local_new(); | |
5049 | TCGv t2 = tcg_temp_local_new(); | |
5050 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5051 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5052 | tcg_gen_shr_tl(t2, t1, t2); | |
5053 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5054 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5055 | gen_load_spr(t0, SPR_MQ); | |
5056 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5057 | tcg_gen_br(l2); | |
5058 | gen_set_label(l1); | |
5059 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5060 | tcg_gen_and_tl(t0, t0, t2); | |
5061 | gen_load_spr(t1, SPR_MQ); | |
5062 | tcg_gen_andc_tl(t1, t1, t2); | |
5063 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5064 | gen_set_label(l2); | |
5065 | tcg_temp_free(t0); | |
5066 | tcg_temp_free(t1); | |
5067 | tcg_temp_free(t2); | |
76a66253 | 5068 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5069 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5070 | } |
5071 | ||
5072 | /* srq */ | |
99e300ef | 5073 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5074 | { |
7487953d AJ |
5075 | int l1 = gen_new_label(); |
5076 | TCGv t0 = tcg_temp_new(); | |
5077 | TCGv t1 = tcg_temp_new(); | |
5078 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5079 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5080 | tcg_gen_subfi_tl(t1, 32, t1); | |
5081 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5082 | tcg_gen_or_tl(t1, t0, t1); | |
5083 | gen_store_spr(SPR_MQ, t1); | |
5084 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5085 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5086 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5087 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5088 | gen_set_label(l1); | |
5089 | tcg_temp_free(t0); | |
5090 | tcg_temp_free(t1); | |
76a66253 | 5091 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5092 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5093 | } |
5094 | ||
5095 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5096 | |
54623277 | 5097 | /* dsa */ |
99e300ef | 5098 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5099 | { |
5100 | /* XXX: TODO */ | |
e06fcd75 | 5101 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5102 | } |
5103 | ||
5104 | /* esa */ | |
99e300ef | 5105 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5106 | { |
5107 | /* XXX: TODO */ | |
e06fcd75 | 5108 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5109 | } |
5110 | ||
5111 | /* mfrom */ | |
99e300ef | 5112 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5113 | { |
5114 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5115 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5116 | #else |
76db3ba4 | 5117 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5118 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5119 | return; |
5120 | } | |
cf02a65c | 5121 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5122 | #endif |
5123 | } | |
5124 | ||
5125 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5126 | |
54623277 | 5127 | /* tlbld */ |
e8eaa2c0 | 5128 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5129 | { |
5130 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5131 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5132 | #else |
76db3ba4 | 5133 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5134 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5135 | return; |
5136 | } | |
c6c7cf05 | 5137 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5138 | #endif |
5139 | } | |
5140 | ||
5141 | /* tlbli */ | |
e8eaa2c0 | 5142 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5143 | { |
5144 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5145 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5146 | #else |
76db3ba4 | 5147 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5148 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5149 | return; |
5150 | } | |
c6c7cf05 | 5151 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5152 | #endif |
5153 | } | |
5154 | ||
7dbe11ac | 5155 | /* 74xx TLB management */ |
e8eaa2c0 | 5156 | |
54623277 | 5157 | /* tlbld */ |
e8eaa2c0 | 5158 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5159 | { |
5160 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5161 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5162 | #else |
76db3ba4 | 5163 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5164 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5165 | return; |
5166 | } | |
c6c7cf05 | 5167 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5168 | #endif |
5169 | } | |
5170 | ||
5171 | /* tlbli */ | |
e8eaa2c0 | 5172 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5173 | { |
5174 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5175 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5176 | #else |
76db3ba4 | 5177 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5178 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5179 | return; |
5180 | } | |
c6c7cf05 | 5181 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5182 | #endif |
5183 | } | |
5184 | ||
76a66253 | 5185 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5186 | |
54623277 | 5187 | /* clf */ |
99e300ef | 5188 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5189 | { |
5190 | /* Cache line flush: implemented as no-op */ | |
5191 | } | |
5192 | ||
5193 | /* cli */ | |
99e300ef | 5194 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5195 | { |
7f75ffd3 | 5196 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5197 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5198 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5199 | #else |
76db3ba4 | 5200 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5201 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5202 | return; |
5203 | } | |
5204 | #endif | |
5205 | } | |
5206 | ||
5207 | /* dclst */ | |
99e300ef | 5208 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5209 | { |
5210 | /* Data cache line store: treated as no-op */ | |
5211 | } | |
5212 | ||
99e300ef | 5213 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5214 | { |
5215 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5216 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5217 | #else |
74d37793 AJ |
5218 | int ra = rA(ctx->opcode); |
5219 | int rd = rD(ctx->opcode); | |
5220 | TCGv t0; | |
76db3ba4 | 5221 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5222 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5223 | return; |
5224 | } | |
74d37793 | 5225 | t0 = tcg_temp_new(); |
76db3ba4 | 5226 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5227 | tcg_gen_shri_tl(t0, t0, 28); |
5228 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5229 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5230 | tcg_temp_free(t0); |
76a66253 | 5231 | if (ra != 0 && ra != rd) |
74d37793 | 5232 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5233 | #endif |
5234 | } | |
5235 | ||
99e300ef | 5236 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5237 | { |
5238 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5239 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5240 | #else |
22e0e173 | 5241 | TCGv t0; |
76db3ba4 | 5242 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5243 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5244 | return; |
5245 | } | |
22e0e173 | 5246 | t0 = tcg_temp_new(); |
76db3ba4 | 5247 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5248 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5249 | tcg_temp_free(t0); |
76a66253 JM |
5250 | #endif |
5251 | } | |
5252 | ||
99e300ef | 5253 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5254 | { |
5255 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5256 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5257 | #else |
76db3ba4 | 5258 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5259 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5260 | return; |
5261 | } | |
e5f17ac6 | 5262 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5263 | gen_sync_exception(ctx); |
76a66253 JM |
5264 | #endif |
5265 | } | |
5266 | ||
5267 | /* svc is not implemented for now */ | |
5268 | ||
5269 | /* POWER2 specific instructions */ | |
5270 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5271 | |
5272 | /* lfq */ | |
99e300ef | 5273 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5274 | { |
01a4afeb | 5275 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5276 | TCGv t0; |
5277 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5278 | t0 = tcg_temp_new(); | |
5279 | gen_addr_imm_index(ctx, t0, 0); | |
5280 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5281 | gen_addr_add(ctx, t0, t0, 8); | |
5282 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5283 | tcg_temp_free(t0); |
76a66253 JM |
5284 | } |
5285 | ||
5286 | /* lfqu */ | |
99e300ef | 5287 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5288 | { |
5289 | int ra = rA(ctx->opcode); | |
01a4afeb | 5290 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5291 | TCGv t0, t1; |
5292 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5293 | t0 = tcg_temp_new(); | |
5294 | t1 = tcg_temp_new(); | |
5295 | gen_addr_imm_index(ctx, t0, 0); | |
5296 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5297 | gen_addr_add(ctx, t1, t0, 8); | |
5298 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5299 | if (ra != 0) |
01a4afeb AJ |
5300 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5301 | tcg_temp_free(t0); | |
5302 | tcg_temp_free(t1); | |
76a66253 JM |
5303 | } |
5304 | ||
5305 | /* lfqux */ | |
99e300ef | 5306 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5307 | { |
5308 | int ra = rA(ctx->opcode); | |
01a4afeb | 5309 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5310 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5311 | TCGv t0, t1; | |
5312 | t0 = tcg_temp_new(); | |
5313 | gen_addr_reg_index(ctx, t0); | |
5314 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5315 | t1 = tcg_temp_new(); | |
5316 | gen_addr_add(ctx, t1, t0, 8); | |
5317 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5318 | tcg_temp_free(t1); | |
76a66253 | 5319 | if (ra != 0) |
01a4afeb AJ |
5320 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5321 | tcg_temp_free(t0); | |
76a66253 JM |
5322 | } |
5323 | ||
5324 | /* lfqx */ | |
99e300ef | 5325 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5326 | { |
01a4afeb | 5327 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5328 | TCGv t0; |
5329 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5330 | t0 = tcg_temp_new(); | |
5331 | gen_addr_reg_index(ctx, t0); | |
5332 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5333 | gen_addr_add(ctx, t0, t0, 8); | |
5334 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5335 | tcg_temp_free(t0); |
76a66253 JM |
5336 | } |
5337 | ||
5338 | /* stfq */ | |
99e300ef | 5339 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5340 | { |
01a4afeb | 5341 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5342 | TCGv t0; |
5343 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5344 | t0 = tcg_temp_new(); | |
5345 | gen_addr_imm_index(ctx, t0, 0); | |
5346 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5347 | gen_addr_add(ctx, t0, t0, 8); | |
5348 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5349 | tcg_temp_free(t0); |
76a66253 JM |
5350 | } |
5351 | ||
5352 | /* stfqu */ | |
99e300ef | 5353 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5354 | { |
5355 | int ra = rA(ctx->opcode); | |
01a4afeb | 5356 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5357 | TCGv t0, t1; |
5358 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5359 | t0 = tcg_temp_new(); | |
5360 | gen_addr_imm_index(ctx, t0, 0); | |
5361 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5362 | t1 = tcg_temp_new(); | |
5363 | gen_addr_add(ctx, t1, t0, 8); | |
5364 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5365 | tcg_temp_free(t1); | |
76a66253 | 5366 | if (ra != 0) |
01a4afeb AJ |
5367 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5368 | tcg_temp_free(t0); | |
76a66253 JM |
5369 | } |
5370 | ||
5371 | /* stfqux */ | |
99e300ef | 5372 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5373 | { |
5374 | int ra = rA(ctx->opcode); | |
01a4afeb | 5375 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5376 | TCGv t0, t1; |
5377 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5378 | t0 = tcg_temp_new(); | |
5379 | gen_addr_reg_index(ctx, t0); | |
5380 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5381 | t1 = tcg_temp_new(); | |
5382 | gen_addr_add(ctx, t1, t0, 8); | |
5383 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5384 | tcg_temp_free(t1); | |
76a66253 | 5385 | if (ra != 0) |
01a4afeb AJ |
5386 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5387 | tcg_temp_free(t0); | |
76a66253 JM |
5388 | } |
5389 | ||
5390 | /* stfqx */ | |
99e300ef | 5391 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5392 | { |
01a4afeb | 5393 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5394 | TCGv t0; |
5395 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5396 | t0 = tcg_temp_new(); | |
5397 | gen_addr_reg_index(ctx, t0); | |
5398 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5399 | gen_addr_add(ctx, t0, t0, 8); | |
5400 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5401 | tcg_temp_free(t0); |
76a66253 JM |
5402 | } |
5403 | ||
5404 | /* BookE specific instructions */ | |
99e300ef | 5405 | |
54623277 | 5406 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5407 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5408 | { |
5409 | /* XXX: TODO */ | |
e06fcd75 | 5410 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5411 | } |
5412 | ||
2662a059 | 5413 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5414 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5415 | { |
5416 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5417 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5418 | #else |
74d37793 | 5419 | TCGv t0; |
76db3ba4 | 5420 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5421 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5422 | return; |
5423 | } | |
ec72e276 | 5424 | t0 = tcg_temp_new(); |
76db3ba4 | 5425 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5426 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5427 | tcg_temp_free(t0); |
76a66253 JM |
5428 | #endif |
5429 | } | |
5430 | ||
5431 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5432 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5433 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5434 | { |
182608d4 AJ |
5435 | TCGv t0, t1; |
5436 | ||
a7812ae4 PB |
5437 | t0 = tcg_temp_local_new(); |
5438 | t1 = tcg_temp_local_new(); | |
182608d4 | 5439 | |
76a66253 JM |
5440 | switch (opc3 & 0x0D) { |
5441 | case 0x05: | |
5442 | /* macchw - macchw. - macchwo - macchwo. */ | |
5443 | /* macchws - macchws. - macchwso - macchwso. */ | |
5444 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5445 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5446 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5447 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5448 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5449 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5450 | break; |
5451 | case 0x04: | |
5452 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5453 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5454 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5455 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5456 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5457 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5458 | break; |
5459 | case 0x01: | |
5460 | /* machhw - machhw. - machhwo - machhwo. */ | |
5461 | /* machhws - machhws. - machhwso - machhwso. */ | |
5462 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5463 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5464 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5465 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5466 | tcg_gen_ext16s_tl(t0, t0); | |
5467 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5468 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5469 | break; |
5470 | case 0x00: | |
5471 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5472 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5473 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5474 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5475 | tcg_gen_ext16u_tl(t0, t0); | |
5476 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5477 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5478 | break; |
5479 | case 0x0D: | |
5480 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5481 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5482 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5483 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5484 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5485 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5486 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5487 | break; |
5488 | case 0x0C: | |
5489 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5490 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5491 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5492 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5493 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5494 | break; |
5495 | } | |
76a66253 | 5496 | if (opc2 & 0x04) { |
182608d4 AJ |
5497 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5498 | tcg_gen_mul_tl(t1, t0, t1); | |
5499 | if (opc2 & 0x02) { | |
5500 | /* nmultiply-and-accumulate (0x0E) */ | |
5501 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5502 | } else { | |
5503 | /* multiply-and-accumulate (0x0C) */ | |
5504 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5505 | } | |
5506 | ||
5507 | if (opc3 & 0x12) { | |
5508 | /* Check overflow and/or saturate */ | |
5509 | int l1 = gen_new_label(); | |
5510 | ||
5511 | if (opc3 & 0x10) { | |
5512 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5513 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5514 | } |
5515 | if (opc3 & 0x01) { | |
5516 | /* Signed */ | |
5517 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5518 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5519 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5520 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5521 | if (opc3 & 0x02) { |
182608d4 AJ |
5522 | /* Saturate */ |
5523 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5524 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5525 | } | |
5526 | } else { | |
5527 | /* Unsigned */ | |
5528 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5529 | if (opc3 & 0x02) { |
182608d4 AJ |
5530 | /* Saturate */ |
5531 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5532 | } | |
5533 | } | |
5534 | if (opc3 & 0x10) { | |
5535 | /* Check overflow */ | |
da91a00f RH |
5536 | tcg_gen_movi_tl(cpu_ov, 1); |
5537 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5538 | } |
5539 | gen_set_label(l1); | |
5540 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5541 | } | |
5542 | } else { | |
5543 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5544 | } |
182608d4 AJ |
5545 | tcg_temp_free(t0); |
5546 | tcg_temp_free(t1); | |
76a66253 JM |
5547 | if (unlikely(Rc) != 0) { |
5548 | /* Update Rc0 */ | |
182608d4 | 5549 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5550 | } |
5551 | } | |
5552 | ||
a750fc0b | 5553 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5554 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5555 | { \ |
5556 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5557 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5558 | } | |
5559 | ||
5560 | /* macchw - macchw. */ | |
a750fc0b | 5561 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5562 | /* macchwo - macchwo. */ |
a750fc0b | 5563 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5564 | /* macchws - macchws. */ |
a750fc0b | 5565 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5566 | /* macchwso - macchwso. */ |
a750fc0b | 5567 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5568 | /* macchwsu - macchwsu. */ |
a750fc0b | 5569 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5570 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5571 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5572 | /* macchwu - macchwu. */ |
a750fc0b | 5573 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5574 | /* macchwuo - macchwuo. */ |
a750fc0b | 5575 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5576 | /* machhw - machhw. */ |
a750fc0b | 5577 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5578 | /* machhwo - machhwo. */ |
a750fc0b | 5579 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5580 | /* machhws - machhws. */ |
a750fc0b | 5581 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5582 | /* machhwso - machhwso. */ |
a750fc0b | 5583 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5584 | /* machhwsu - machhwsu. */ |
a750fc0b | 5585 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5586 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5587 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5588 | /* machhwu - machhwu. */ |
a750fc0b | 5589 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5590 | /* machhwuo - machhwuo. */ |
a750fc0b | 5591 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5592 | /* maclhw - maclhw. */ |
a750fc0b | 5593 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5594 | /* maclhwo - maclhwo. */ |
a750fc0b | 5595 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5596 | /* maclhws - maclhws. */ |
a750fc0b | 5597 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5598 | /* maclhwso - maclhwso. */ |
a750fc0b | 5599 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5600 | /* maclhwu - maclhwu. */ |
a750fc0b | 5601 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5602 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5603 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5604 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5605 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5606 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5607 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5608 | /* nmacchw - nmacchw. */ |
a750fc0b | 5609 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5610 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5611 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5612 | /* nmacchws - nmacchws. */ |
a750fc0b | 5613 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5614 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5615 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5616 | /* nmachhw - nmachhw. */ |
a750fc0b | 5617 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5618 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5619 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5620 | /* nmachhws - nmachhws. */ |
a750fc0b | 5621 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5622 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5623 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5624 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5625 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5626 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5627 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5628 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5629 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5630 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5631 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5632 | |
5633 | /* mulchw - mulchw. */ | |
a750fc0b | 5634 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5635 | /* mulchwu - mulchwu. */ |
a750fc0b | 5636 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5637 | /* mulhhw - mulhhw. */ |
a750fc0b | 5638 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5639 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5640 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5641 | /* mullhw - mullhw. */ |
a750fc0b | 5642 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5643 | /* mullhwu - mullhwu. */ |
a750fc0b | 5644 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5645 | |
5646 | /* mfdcr */ | |
99e300ef | 5647 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5648 | { |
5649 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5650 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5651 | #else |
06dca6a7 | 5652 | TCGv dcrn; |
76db3ba4 | 5653 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5654 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5655 | return; |
5656 | } | |
06dca6a7 AJ |
5657 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5658 | gen_update_nip(ctx, ctx->nip - 4); | |
5659 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5660 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5661 | tcg_temp_free(dcrn); |
76a66253 JM |
5662 | #endif |
5663 | } | |
5664 | ||
5665 | /* mtdcr */ | |
99e300ef | 5666 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5667 | { |
5668 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5669 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5670 | #else |
06dca6a7 | 5671 | TCGv dcrn; |
76db3ba4 | 5672 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5673 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5674 | return; |
5675 | } | |
06dca6a7 AJ |
5676 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5677 | gen_update_nip(ctx, ctx->nip - 4); | |
5678 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5679 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5680 | tcg_temp_free(dcrn); |
a42bd6cc JM |
5681 | #endif |
5682 | } | |
5683 | ||
5684 | /* mfdcrx */ | |
2662a059 | 5685 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5686 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5687 | { |
5688 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5689 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5690 | #else |
76db3ba4 | 5691 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5692 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5693 | return; |
5694 | } | |
06dca6a7 AJ |
5695 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5696 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5697 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5698 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5699 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
5700 | #endif |
5701 | } | |
5702 | ||
5703 | /* mtdcrx */ | |
2662a059 | 5704 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5705 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5706 | { |
5707 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5708 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5709 | #else |
76db3ba4 | 5710 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5711 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5712 | return; |
5713 | } | |
06dca6a7 AJ |
5714 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5715 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5716 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5717 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5718 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
5719 | #endif |
5720 | } | |
5721 | ||
a750fc0b | 5722 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5723 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5724 | { |
06dca6a7 AJ |
5725 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5726 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5727 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5728 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5729 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5730 | } | |
5731 | ||
5732 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5733 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5734 | { |
06dca6a7 AJ |
5735 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5736 | gen_update_nip(ctx, ctx->nip - 4); | |
975e5463 | 5737 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5738 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5739 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5740 | } | |
5741 | ||
76a66253 | 5742 | /* dccci */ |
99e300ef | 5743 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
5744 | { |
5745 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5746 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5747 | #else |
76db3ba4 | 5748 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5749 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5750 | return; |
5751 | } | |
5752 | /* interpreted as no-op */ | |
5753 | #endif | |
5754 | } | |
5755 | ||
5756 | /* dcread */ | |
99e300ef | 5757 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5758 | { |
5759 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5760 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5761 | #else |
b61f2753 | 5762 | TCGv EA, val; |
76db3ba4 | 5763 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5764 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5765 | return; |
5766 | } | |
76db3ba4 | 5767 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5768 | EA = tcg_temp_new(); |
76db3ba4 | 5769 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5770 | val = tcg_temp_new(); |
76db3ba4 | 5771 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5772 | tcg_temp_free(val); |
5773 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5774 | tcg_temp_free(EA); | |
76a66253 JM |
5775 | #endif |
5776 | } | |
5777 | ||
5778 | /* icbt */ | |
e8eaa2c0 | 5779 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5780 | { |
5781 | /* interpreted as no-op */ | |
5782 | /* XXX: specification say this is treated as a load by the MMU | |
5783 | * but does not generate any exception | |
5784 | */ | |
5785 | } | |
5786 | ||
5787 | /* iccci */ | |
99e300ef | 5788 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
5789 | { |
5790 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5791 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5792 | #else |
76db3ba4 | 5793 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5794 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5795 | return; |
5796 | } | |
5797 | /* interpreted as no-op */ | |
5798 | #endif | |
5799 | } | |
5800 | ||
5801 | /* icread */ | |
99e300ef | 5802 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
5803 | { |
5804 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5805 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5806 | #else |
76db3ba4 | 5807 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5808 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5809 | return; |
5810 | } | |
5811 | /* interpreted as no-op */ | |
5812 | #endif | |
5813 | } | |
5814 | ||
76db3ba4 | 5815 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 5816 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5817 | { |
5818 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5819 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5820 | #else |
76db3ba4 | 5821 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5822 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5823 | return; |
5824 | } | |
5825 | /* Restore CPU state */ | |
e5f17ac6 | 5826 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 5827 | gen_sync_exception(ctx); |
a42bd6cc JM |
5828 | #endif |
5829 | } | |
5830 | ||
99e300ef | 5831 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5832 | { |
5833 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5834 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5835 | #else |
76db3ba4 | 5836 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5837 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5838 | return; |
5839 | } | |
5840 | /* Restore CPU state */ | |
e5f17ac6 | 5841 | gen_helper_rfci(cpu_env); |
e06fcd75 | 5842 | gen_sync_exception(ctx); |
a42bd6cc JM |
5843 | #endif |
5844 | } | |
5845 | ||
5846 | /* BookE specific */ | |
99e300ef | 5847 | |
54623277 | 5848 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5849 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5850 | { |
5851 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5852 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5853 | #else |
76db3ba4 | 5854 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5855 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5856 | return; |
5857 | } | |
5858 | /* Restore CPU state */ | |
e5f17ac6 | 5859 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 5860 | gen_sync_exception(ctx); |
76a66253 JM |
5861 | #endif |
5862 | } | |
5863 | ||
2662a059 | 5864 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5865 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5866 | { |
5867 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5868 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5869 | #else |
76db3ba4 | 5870 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5871 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5872 | return; |
5873 | } | |
5874 | /* Restore CPU state */ | |
e5f17ac6 | 5875 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 5876 | gen_sync_exception(ctx); |
a42bd6cc JM |
5877 | #endif |
5878 | } | |
5eb7995e | 5879 | |
d9bce9d9 | 5880 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5881 | |
54623277 | 5882 | /* tlbre */ |
e8eaa2c0 | 5883 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5884 | { |
5885 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5886 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5887 | #else |
76db3ba4 | 5888 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5889 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5890 | return; |
5891 | } | |
5892 | switch (rB(ctx->opcode)) { | |
5893 | case 0: | |
c6c7cf05 BS |
5894 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5895 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5896 | break; |
5897 | case 1: | |
c6c7cf05 BS |
5898 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5899 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5900 | break; |
5901 | default: | |
e06fcd75 | 5902 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5903 | break; |
9a64fbe4 | 5904 | } |
76a66253 JM |
5905 | #endif |
5906 | } | |
5907 | ||
d9bce9d9 | 5908 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5909 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5910 | { |
5911 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5912 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5913 | #else |
74d37793 | 5914 | TCGv t0; |
76db3ba4 | 5915 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5916 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5917 | return; |
5918 | } | |
74d37793 | 5919 | t0 = tcg_temp_new(); |
76db3ba4 | 5920 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5921 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
5922 | tcg_temp_free(t0); |
5923 | if (Rc(ctx->opcode)) { | |
5924 | int l1 = gen_new_label(); | |
da91a00f | 5925 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5926 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5927 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5928 | gen_set_label(l1); | |
5929 | } | |
76a66253 | 5930 | #endif |
79aceca5 FB |
5931 | } |
5932 | ||
76a66253 | 5933 | /* tlbwe */ |
e8eaa2c0 | 5934 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 5935 | { |
76a66253 | 5936 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5937 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5938 | #else |
76db3ba4 | 5939 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5940 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5941 | return; |
5942 | } | |
5943 | switch (rB(ctx->opcode)) { | |
5944 | case 0: | |
c6c7cf05 BS |
5945 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5946 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5947 | break; |
5948 | case 1: | |
c6c7cf05 BS |
5949 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5950 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5951 | break; |
5952 | default: | |
e06fcd75 | 5953 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5954 | break; |
9a64fbe4 | 5955 | } |
76a66253 JM |
5956 | #endif |
5957 | } | |
5958 | ||
a4bb6c3e | 5959 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 5960 | |
54623277 | 5961 | /* tlbre */ |
e8eaa2c0 | 5962 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
5963 | { |
5964 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5965 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 5966 | #else |
76db3ba4 | 5967 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5968 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
5969 | return; |
5970 | } | |
5971 | switch (rB(ctx->opcode)) { | |
5972 | case 0: | |
5eb7995e | 5973 | case 1: |
5eb7995e | 5974 | case 2: |
74d37793 AJ |
5975 | { |
5976 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
5977 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5978 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
5979 | tcg_temp_free_i32(t0); |
5980 | } | |
5eb7995e JM |
5981 | break; |
5982 | default: | |
e06fcd75 | 5983 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5984 | break; |
5985 | } | |
5986 | #endif | |
5987 | } | |
5988 | ||
5989 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 5990 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
5991 | { |
5992 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5993 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 5994 | #else |
74d37793 | 5995 | TCGv t0; |
76db3ba4 | 5996 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5997 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
5998 | return; |
5999 | } | |
74d37793 | 6000 | t0 = tcg_temp_new(); |
76db3ba4 | 6001 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6002 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6003 | tcg_temp_free(t0); |
6004 | if (Rc(ctx->opcode)) { | |
6005 | int l1 = gen_new_label(); | |
da91a00f | 6006 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6007 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6008 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6009 | gen_set_label(l1); | |
6010 | } | |
5eb7995e JM |
6011 | #endif |
6012 | } | |
6013 | ||
6014 | /* tlbwe */ | |
e8eaa2c0 | 6015 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6016 | { |
6017 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6018 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6019 | #else |
76db3ba4 | 6020 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6021 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6022 | return; |
6023 | } | |
6024 | switch (rB(ctx->opcode)) { | |
6025 | case 0: | |
5eb7995e | 6026 | case 1: |
5eb7995e | 6027 | case 2: |
74d37793 AJ |
6028 | { |
6029 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6030 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6031 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6032 | tcg_temp_free_i32(t0); |
6033 | } | |
5eb7995e JM |
6034 | break; |
6035 | default: | |
e06fcd75 | 6036 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6037 | break; |
6038 | } | |
6039 | #endif | |
6040 | } | |
6041 | ||
01662f3e AG |
6042 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6043 | ||
6044 | /* tlbre */ | |
6045 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6046 | { | |
6047 | #if defined(CONFIG_USER_ONLY) | |
6048 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6049 | #else | |
6050 | if (unlikely(!ctx->mem_idx)) { | |
6051 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6052 | return; | |
6053 | } | |
6054 | ||
c6c7cf05 | 6055 | gen_helper_booke206_tlbre(cpu_env); |
01662f3e AG |
6056 | #endif |
6057 | } | |
6058 | ||
6059 | /* tlbsx - tlbsx. */ | |
6060 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6061 | { | |
6062 | #if defined(CONFIG_USER_ONLY) | |
6063 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6064 | #else | |
6065 | TCGv t0; | |
6066 | if (unlikely(!ctx->mem_idx)) { | |
6067 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6068 | return; | |
6069 | } | |
6070 | ||
6071 | if (rA(ctx->opcode)) { | |
6072 | t0 = tcg_temp_new(); | |
6073 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6074 | } else { | |
6075 | t0 = tcg_const_tl(0); | |
6076 | } | |
6077 | ||
6078 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6079 | gen_helper_booke206_tlbsx(cpu_env, t0); |
01662f3e AG |
6080 | #endif |
6081 | } | |
6082 | ||
6083 | /* tlbwe */ | |
6084 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6085 | { | |
6086 | #if defined(CONFIG_USER_ONLY) | |
6087 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6088 | #else | |
6089 | if (unlikely(!ctx->mem_idx)) { | |
6090 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6091 | return; | |
6092 | } | |
3f162d11 | 6093 | gen_update_nip(ctx, ctx->nip - 4); |
c6c7cf05 | 6094 | gen_helper_booke206_tlbwe(cpu_env); |
01662f3e AG |
6095 | #endif |
6096 | } | |
6097 | ||
6098 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6099 | { | |
6100 | #if defined(CONFIG_USER_ONLY) | |
6101 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6102 | #else | |
6103 | TCGv t0; | |
6104 | if (unlikely(!ctx->mem_idx)) { | |
6105 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6106 | return; | |
6107 | } | |
6108 | ||
6109 | t0 = tcg_temp_new(); | |
6110 | gen_addr_reg_index(ctx, t0); | |
6111 | ||
c6c7cf05 | 6112 | gen_helper_booke206_tlbivax(cpu_env, t0); |
01662f3e AG |
6113 | #endif |
6114 | } | |
6115 | ||
6d3db821 AG |
6116 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6117 | { | |
6118 | #if defined(CONFIG_USER_ONLY) | |
6119 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6120 | #else | |
6121 | TCGv t0; | |
6122 | if (unlikely(!ctx->mem_idx)) { | |
6123 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6124 | return; | |
6125 | } | |
6126 | ||
6127 | t0 = tcg_temp_new(); | |
6128 | gen_addr_reg_index(ctx, t0); | |
6129 | ||
6130 | switch((ctx->opcode >> 21) & 0x3) { | |
6131 | case 0: | |
c6c7cf05 | 6132 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6133 | break; |
6134 | case 1: | |
c6c7cf05 | 6135 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6136 | break; |
6137 | case 3: | |
c6c7cf05 | 6138 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6139 | break; |
6140 | default: | |
6141 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6142 | break; | |
6143 | } | |
6144 | ||
6145 | tcg_temp_free(t0); | |
6146 | #endif | |
6147 | } | |
6148 | ||
01662f3e | 6149 | |
76a66253 | 6150 | /* wrtee */ |
99e300ef | 6151 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6152 | { |
6153 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6154 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6155 | #else |
6527f6ea | 6156 | TCGv t0; |
76db3ba4 | 6157 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6158 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6159 | return; |
6160 | } | |
6527f6ea AJ |
6161 | t0 = tcg_temp_new(); |
6162 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6163 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6164 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6165 | tcg_temp_free(t0); | |
dee96f6c JM |
6166 | /* Stop translation to have a chance to raise an exception |
6167 | * if we just set msr_ee to 1 | |
6168 | */ | |
e06fcd75 | 6169 | gen_stop_exception(ctx); |
76a66253 JM |
6170 | #endif |
6171 | } | |
6172 | ||
6173 | /* wrteei */ | |
99e300ef | 6174 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6175 | { |
6176 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6177 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6178 | #else |
76db3ba4 | 6179 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6180 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6181 | return; |
6182 | } | |
fbe73008 | 6183 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6184 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6185 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6186 | gen_stop_exception(ctx); |
6527f6ea | 6187 | } else { |
1b6e5f99 | 6188 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6189 | } |
76a66253 JM |
6190 | #endif |
6191 | } | |
6192 | ||
08e46e54 | 6193 | /* PowerPC 440 specific instructions */ |
99e300ef | 6194 | |
54623277 | 6195 | /* dlmzb */ |
99e300ef | 6196 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6197 | { |
ef0d51af | 6198 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6199 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6200 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6201 | tcg_temp_free_i32(t0); |
76a66253 JM |
6202 | } |
6203 | ||
6204 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6205 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6206 | { |
6207 | /* interpreted as no-op */ | |
6208 | } | |
6209 | ||
6210 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6211 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6212 | { |
6213 | /* interpreted as no-op */ | |
6214 | } | |
6215 | ||
6216 | /* icbt */ | |
e8eaa2c0 | 6217 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6218 | { |
6219 | /* interpreted as no-op */ | |
6220 | /* XXX: specification say this is treated as a load by the MMU | |
6221 | * but does not generate any exception | |
6222 | */ | |
79aceca5 FB |
6223 | } |
6224 | ||
9e0b5cb1 AG |
6225 | /* Embedded.Processor Control */ |
6226 | ||
6227 | static void gen_msgclr(DisasContext *ctx) | |
6228 | { | |
6229 | #if defined(CONFIG_USER_ONLY) | |
6230 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6231 | #else | |
6232 | if (unlikely(ctx->mem_idx == 0)) { | |
6233 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6234 | return; | |
6235 | } | |
6236 | ||
e5f17ac6 | 6237 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9e0b5cb1 AG |
6238 | #endif |
6239 | } | |
6240 | ||
d5d11a39 AG |
6241 | static void gen_msgsnd(DisasContext *ctx) |
6242 | { | |
6243 | #if defined(CONFIG_USER_ONLY) | |
6244 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6245 | #else | |
6246 | if (unlikely(ctx->mem_idx == 0)) { | |
6247 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6248 | return; | |
6249 | } | |
6250 | ||
6251 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6252 | #endif | |
6253 | } | |
6254 | ||
a9d9eb8f JM |
6255 | /*** Altivec vector extension ***/ |
6256 | /* Altivec registers moves */ | |
a9d9eb8f | 6257 | |
636aa200 | 6258 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6259 | { |
e4704b3b | 6260 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6261 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6262 | return r; | |
6263 | } | |
6264 | ||
a9d9eb8f | 6265 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6266 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6267 | { \ |
fe1e5c53 | 6268 | TCGv EA; \ |
a9d9eb8f | 6269 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6270 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6271 | return; \ |
6272 | } \ | |
76db3ba4 | 6273 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6274 | EA = tcg_temp_new(); \ |
76db3ba4 | 6275 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6276 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6277 | if (ctx->le_mode) { \ |
6278 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6279 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6280 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6281 | } else { \ |
76db3ba4 | 6282 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6283 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6284 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6285 | } \ |
6286 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6287 | } |
6288 | ||
6289 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6290 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6291 | { \ |
fe1e5c53 | 6292 | TCGv EA; \ |
a9d9eb8f | 6293 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6294 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6295 | return; \ |
6296 | } \ | |
76db3ba4 | 6297 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6298 | EA = tcg_temp_new(); \ |
76db3ba4 | 6299 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6300 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6301 | if (ctx->le_mode) { \ |
6302 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6303 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6304 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6305 | } else { \ |
76db3ba4 | 6306 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6307 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6308 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6309 | } \ |
6310 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6311 | } |
6312 | ||
cbfb6ae9 | 6313 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef | 6314 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6315 | { \ |
6316 | TCGv EA; \ | |
6317 | TCGv_ptr rs; \ | |
6318 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6319 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6320 | return; \ | |
6321 | } \ | |
6322 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6323 | EA = tcg_temp_new(); \ | |
6324 | gen_addr_reg_index(ctx, EA); \ | |
6325 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6326 | gen_helper_lve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6327 | tcg_temp_free(EA); \ |
6328 | tcg_temp_free_ptr(rs); \ | |
6329 | } | |
6330 | ||
6331 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef | 6332 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6333 | { \ |
6334 | TCGv EA; \ | |
6335 | TCGv_ptr rs; \ | |
6336 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6337 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6338 | return; \ | |
6339 | } \ | |
6340 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6341 | EA = tcg_temp_new(); \ | |
6342 | gen_addr_reg_index(ctx, EA); \ | |
6343 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6344 | gen_helper_stve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6345 | tcg_temp_free(EA); \ |
6346 | tcg_temp_free_ptr(rs); \ | |
6347 | } | |
6348 | ||
fe1e5c53 | 6349 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6350 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6351 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6352 | |
cbfb6ae9 AJ |
6353 | GEN_VR_LVE(bx, 0x07, 0x00); |
6354 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6355 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6356 | ||
fe1e5c53 | 6357 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6358 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6359 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6360 | |
cbfb6ae9 AJ |
6361 | GEN_VR_STVE(bx, 0x07, 0x04); |
6362 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6363 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6364 | ||
99e300ef | 6365 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6366 | { |
6367 | TCGv_ptr rd; | |
6368 | TCGv EA; | |
6369 | if (unlikely(!ctx->altivec_enabled)) { | |
6370 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6371 | return; | |
6372 | } | |
6373 | EA = tcg_temp_new(); | |
6374 | gen_addr_reg_index(ctx, EA); | |
6375 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6376 | gen_helper_lvsl(rd, EA); | |
6377 | tcg_temp_free(EA); | |
6378 | tcg_temp_free_ptr(rd); | |
6379 | } | |
6380 | ||
99e300ef | 6381 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6382 | { |
6383 | TCGv_ptr rd; | |
6384 | TCGv EA; | |
6385 | if (unlikely(!ctx->altivec_enabled)) { | |
6386 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6387 | return; | |
6388 | } | |
6389 | EA = tcg_temp_new(); | |
6390 | gen_addr_reg_index(ctx, EA); | |
6391 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6392 | gen_helper_lvsr(rd, EA); | |
6393 | tcg_temp_free(EA); | |
6394 | tcg_temp_free_ptr(rd); | |
6395 | } | |
6396 | ||
99e300ef | 6397 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6398 | { |
6399 | TCGv_i32 t; | |
6400 | if (unlikely(!ctx->altivec_enabled)) { | |
6401 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6402 | return; | |
6403 | } | |
6404 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6405 | t = tcg_temp_new_i32(); | |
1328c2bf | 6406 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
785f451b | 6407 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
fce5ecb7 | 6408 | tcg_temp_free_i32(t); |
785f451b AJ |
6409 | } |
6410 | ||
99e300ef | 6411 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6412 | { |
6e87b7c7 | 6413 | TCGv_ptr p; |
785f451b AJ |
6414 | if (unlikely(!ctx->altivec_enabled)) { |
6415 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6416 | return; | |
6417 | } | |
6e87b7c7 | 6418 | p = gen_avr_ptr(rD(ctx->opcode)); |
d15f74fb | 6419 | gen_helper_mtvscr(cpu_env, p); |
6e87b7c7 | 6420 | tcg_temp_free_ptr(p); |
785f451b AJ |
6421 | } |
6422 | ||
7a9b96cf AJ |
6423 | /* Logical operations */ |
6424 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6425 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6426 | { \ |
6427 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6428 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6429 | return; \ | |
6430 | } \ | |
6431 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6432 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6433 | } | |
6434 | ||
6435 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6436 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6437 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6438 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6439 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
6440 | ||
8e27dd6f | 6441 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6442 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6443 | { \ |
6444 | TCGv_ptr ra, rb, rd; \ | |
6445 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6446 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6447 | return; \ | |
6448 | } \ | |
6449 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6450 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6451 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6452 | gen_helper_##name (rd, ra, rb); \ | |
6453 | tcg_temp_free_ptr(ra); \ | |
6454 | tcg_temp_free_ptr(rb); \ | |
6455 | tcg_temp_free_ptr(rd); \ | |
6456 | } | |
6457 | ||
d15f74fb BS |
6458 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
6459 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6460 | { \ | |
6461 | TCGv_ptr ra, rb, rd; \ | |
6462 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6463 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6464 | return; \ | |
6465 | } \ | |
6466 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6467 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6468 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
54cddd21 | 6469 | gen_helper_##name(cpu_env, rd, ra, rb); \ |
d15f74fb BS |
6470 | tcg_temp_free_ptr(ra); \ |
6471 | tcg_temp_free_ptr(rb); \ | |
6472 | tcg_temp_free_ptr(rd); \ | |
6473 | } | |
6474 | ||
7872c51c AJ |
6475 | GEN_VXFORM(vaddubm, 0, 0); |
6476 | GEN_VXFORM(vadduhm, 0, 1); | |
6477 | GEN_VXFORM(vadduwm, 0, 2); | |
6478 | GEN_VXFORM(vsububm, 0, 16); | |
6479 | GEN_VXFORM(vsubuhm, 0, 17); | |
6480 | GEN_VXFORM(vsubuwm, 0, 18); | |
e4039339 AJ |
6481 | GEN_VXFORM(vmaxub, 1, 0); |
6482 | GEN_VXFORM(vmaxuh, 1, 1); | |
6483 | GEN_VXFORM(vmaxuw, 1, 2); | |
6484 | GEN_VXFORM(vmaxsb, 1, 4); | |
6485 | GEN_VXFORM(vmaxsh, 1, 5); | |
6486 | GEN_VXFORM(vmaxsw, 1, 6); | |
6487 | GEN_VXFORM(vminub, 1, 8); | |
6488 | GEN_VXFORM(vminuh, 1, 9); | |
6489 | GEN_VXFORM(vminuw, 1, 10); | |
6490 | GEN_VXFORM(vminsb, 1, 12); | |
6491 | GEN_VXFORM(vminsh, 1, 13); | |
6492 | GEN_VXFORM(vminsw, 1, 14); | |
fab3cbe9 AJ |
6493 | GEN_VXFORM(vavgub, 1, 16); |
6494 | GEN_VXFORM(vavguh, 1, 17); | |
6495 | GEN_VXFORM(vavguw, 1, 18); | |
6496 | GEN_VXFORM(vavgsb, 1, 20); | |
6497 | GEN_VXFORM(vavgsh, 1, 21); | |
6498 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6499 | GEN_VXFORM(vmrghb, 6, 0); |
6500 | GEN_VXFORM(vmrghh, 6, 1); | |
6501 | GEN_VXFORM(vmrghw, 6, 2); | |
6502 | GEN_VXFORM(vmrglb, 6, 4); | |
6503 | GEN_VXFORM(vmrglh, 6, 5); | |
6504 | GEN_VXFORM(vmrglw, 6, 6); | |
2c277908 AJ |
6505 | GEN_VXFORM(vmuloub, 4, 0); |
6506 | GEN_VXFORM(vmulouh, 4, 1); | |
6507 | GEN_VXFORM(vmulosb, 4, 4); | |
6508 | GEN_VXFORM(vmulosh, 4, 5); | |
6509 | GEN_VXFORM(vmuleub, 4, 8); | |
6510 | GEN_VXFORM(vmuleuh, 4, 9); | |
6511 | GEN_VXFORM(vmulesb, 4, 12); | |
6512 | GEN_VXFORM(vmulesh, 4, 13); | |
d79f0809 AJ |
6513 | GEN_VXFORM(vslb, 2, 4); |
6514 | GEN_VXFORM(vslh, 2, 5); | |
6515 | GEN_VXFORM(vslw, 2, 6); | |
07ef34c3 AJ |
6516 | GEN_VXFORM(vsrb, 2, 8); |
6517 | GEN_VXFORM(vsrh, 2, 9); | |
6518 | GEN_VXFORM(vsrw, 2, 10); | |
6519 | GEN_VXFORM(vsrab, 2, 12); | |
6520 | GEN_VXFORM(vsrah, 2, 13); | |
6521 | GEN_VXFORM(vsraw, 2, 14); | |
7b239bec AJ |
6522 | GEN_VXFORM(vslo, 6, 16); |
6523 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
6524 | GEN_VXFORM(vaddcuw, 0, 6); |
6525 | GEN_VXFORM(vsubcuw, 0, 22); | |
d15f74fb BS |
6526 | GEN_VXFORM_ENV(vaddubs, 0, 8); |
6527 | GEN_VXFORM_ENV(vadduhs, 0, 9); | |
6528 | GEN_VXFORM_ENV(vadduws, 0, 10); | |
6529 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
6530 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
6531 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
6532 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
6533 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
6534 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
6535 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
6536 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
6537 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
5e1d0985 AJ |
6538 | GEN_VXFORM(vrlb, 2, 0); |
6539 | GEN_VXFORM(vrlh, 2, 1); | |
6540 | GEN_VXFORM(vrlw, 2, 2); | |
d9430add AJ |
6541 | GEN_VXFORM(vsl, 2, 7); |
6542 | GEN_VXFORM(vsr, 2, 11); | |
d15f74fb BS |
6543 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
6544 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
6545 | GEN_VXFORM_ENV(vpkuhus, 7, 2); | |
6546 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
6547 | GEN_VXFORM_ENV(vpkshus, 7, 4); | |
6548 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
6549 | GEN_VXFORM_ENV(vpkshss, 7, 6); | |
6550 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
1dd9ffb9 | 6551 | GEN_VXFORM(vpkpx, 7, 12); |
d15f74fb BS |
6552 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
6553 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
6554 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
6555 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
6556 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
6557 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
6558 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
6559 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
6560 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
fab3cbe9 | 6561 | |
0cbcd906 | 6562 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 6563 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
6564 | { \ |
6565 | TCGv_ptr ra, rb, rd; \ | |
6566 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6567 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6568 | return; \ | |
6569 | } \ | |
6570 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6571 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6572 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
d15f74fb | 6573 | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
0cbcd906 AJ |
6574 | tcg_temp_free_ptr(ra); \ |
6575 | tcg_temp_free_ptr(rb); \ | |
6576 | tcg_temp_free_ptr(rd); \ | |
6577 | } | |
6578 | ||
6579 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
6580 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
6581 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
6582 | ||
1add6e23 AJ |
6583 | GEN_VXRFORM(vcmpequb, 3, 0) |
6584 | GEN_VXRFORM(vcmpequh, 3, 1) | |
6585 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6586 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
6587 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
6588 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6589 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
6590 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
6591 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
819ca121 AJ |
6592 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6593 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
6594 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
6595 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 6596 | |
c026766b | 6597 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6598 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
6599 | { \ |
6600 | TCGv_ptr rd; \ | |
6601 | TCGv_i32 simm; \ | |
6602 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6603 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6604 | return; \ | |
6605 | } \ | |
6606 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6607 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6608 | gen_helper_##name (rd, simm); \ | |
6609 | tcg_temp_free_i32(simm); \ | |
6610 | tcg_temp_free_ptr(rd); \ | |
6611 | } | |
6612 | ||
6613 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
6614 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
6615 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
6616 | ||
de5f2484 | 6617 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 6618 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
6619 | { \ |
6620 | TCGv_ptr rb, rd; \ | |
6621 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6622 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6623 | return; \ | |
6624 | } \ | |
6625 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6626 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6627 | gen_helper_##name (rd, rb); \ | |
6628 | tcg_temp_free_ptr(rb); \ | |
6629 | tcg_temp_free_ptr(rd); \ | |
6630 | } | |
6631 | ||
d15f74fb BS |
6632 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ |
6633 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6634 | { \ | |
6635 | TCGv_ptr rb, rd; \ | |
6636 | \ | |
6637 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6638 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6639 | return; \ | |
6640 | } \ | |
6641 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6642 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6643 | gen_helper_##name(cpu_env, rd, rb); \ | |
6644 | tcg_temp_free_ptr(rb); \ | |
6645 | tcg_temp_free_ptr(rd); \ | |
6646 | } | |
6647 | ||
6cf1c6e5 AJ |
6648 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6649 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
6650 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
6651 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
79f85c3a AJ |
6652 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6653 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
d15f74fb BS |
6654 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
6655 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
6656 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
6657 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
6658 | GEN_VXFORM_NOA_ENV(vrfim, 5, 8); | |
6659 | GEN_VXFORM_NOA_ENV(vrfin, 5, 9); | |
6660 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
6661 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 11); | |
79f85c3a | 6662 | |
21d21583 | 6663 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6664 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
6665 | { \ |
6666 | TCGv_ptr rd; \ | |
6667 | TCGv_i32 simm; \ | |
6668 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6669 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6670 | return; \ | |
6671 | } \ | |
6672 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6673 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6674 | gen_helper_##name (rd, simm); \ | |
6675 | tcg_temp_free_i32(simm); \ | |
6676 | tcg_temp_free_ptr(rd); \ | |
6677 | } | |
6678 | ||
27a4edb3 | 6679 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 6680 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
6681 | { \ |
6682 | TCGv_ptr rb, rd; \ | |
6683 | TCGv_i32 uimm; \ | |
6684 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6685 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6686 | return; \ | |
6687 | } \ | |
6688 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6689 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6690 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6691 | gen_helper_##name (rd, rb, uimm); \ | |
6692 | tcg_temp_free_i32(uimm); \ | |
6693 | tcg_temp_free_ptr(rb); \ | |
6694 | tcg_temp_free_ptr(rd); \ | |
6695 | } | |
6696 | ||
d15f74fb BS |
6697 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
6698 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6699 | { \ | |
6700 | TCGv_ptr rb, rd; \ | |
6701 | TCGv_i32 uimm; \ | |
6702 | \ | |
6703 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6704 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6705 | return; \ | |
6706 | } \ | |
6707 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6708 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6709 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6710 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
6711 | tcg_temp_free_i32(uimm); \ | |
6712 | tcg_temp_free_ptr(rb); \ | |
6713 | tcg_temp_free_ptr(rd); \ | |
6714 | } | |
6715 | ||
e4e6bee7 AJ |
6716 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6717 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
6718 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
d15f74fb BS |
6719 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
6720 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
6721 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
6722 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
e4e6bee7 | 6723 | |
99e300ef | 6724 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
6725 | { |
6726 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 6727 | TCGv_i32 sh; |
cd633b10 AJ |
6728 | if (unlikely(!ctx->altivec_enabled)) { |
6729 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6730 | return; | |
6731 | } | |
6732 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6733 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6734 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6735 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
6736 | gen_helper_vsldoi (rd, ra, rb, sh); | |
6737 | tcg_temp_free_ptr(ra); | |
6738 | tcg_temp_free_ptr(rb); | |
6739 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 6740 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
6741 | } |
6742 | ||
707cec33 | 6743 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
d15f74fb | 6744 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
6745 | { \ |
6746 | TCGv_ptr ra, rb, rc, rd; \ | |
6747 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6748 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6749 | return; \ | |
6750 | } \ | |
6751 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6752 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6753 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6754 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6755 | if (Rc(ctx->opcode)) { \ | |
d15f74fb | 6756 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
707cec33 | 6757 | } else { \ |
d15f74fb | 6758 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
707cec33 AJ |
6759 | } \ |
6760 | tcg_temp_free_ptr(ra); \ | |
6761 | tcg_temp_free_ptr(rb); \ | |
6762 | tcg_temp_free_ptr(rc); \ | |
6763 | tcg_temp_free_ptr(rd); \ | |
6764 | } | |
6765 | ||
b161ae27 AJ |
6766 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
6767 | ||
99e300ef | 6768 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
6769 | { |
6770 | TCGv_ptr ra, rb, rc, rd; | |
6771 | if (unlikely(!ctx->altivec_enabled)) { | |
6772 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6773 | return; | |
6774 | } | |
6775 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6776 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6777 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
6778 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6779 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
6780 | tcg_temp_free_ptr(ra); | |
6781 | tcg_temp_free_ptr(rb); | |
6782 | tcg_temp_free_ptr(rc); | |
6783 | tcg_temp_free_ptr(rd); | |
6784 | } | |
6785 | ||
b04ae981 | 6786 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 6787 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 6788 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 6789 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 6790 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 6791 | |
0487d6a8 | 6792 | /*** SPE extension ***/ |
0487d6a8 | 6793 | /* Register moves */ |
3cd7d1dd | 6794 | |
a0e13900 FC |
6795 | |
6796 | static inline void gen_evmra(DisasContext *ctx) | |
6797 | { | |
6798 | ||
6799 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 6800 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
6801 | return; |
6802 | } | |
6803 | ||
6804 | #if defined(TARGET_PPC64) | |
6805 | /* rD := rA */ | |
6806 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6807 | ||
6808 | /* spe_acc := rA */ | |
6809 | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], | |
6810 | cpu_env, | |
1328c2bf | 6811 | offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
6812 | #else |
6813 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
6814 | ||
6815 | /* tmp := rA_lo + rA_hi << 32 */ | |
6816 | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6817 | ||
6818 | /* spe_acc := tmp */ | |
1328c2bf | 6819 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
6820 | tcg_temp_free_i64(tmp); |
6821 | ||
6822 | /* rD := rA */ | |
6823 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6824 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6825 | #endif | |
6826 | } | |
6827 | ||
636aa200 BS |
6828 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
6829 | { | |
f78fb44e AJ |
6830 | #if defined(TARGET_PPC64) |
6831 | tcg_gen_mov_i64(t, cpu_gpr[reg]); | |
6832 | #else | |
36aa55dc | 6833 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
3cd7d1dd | 6834 | #endif |
f78fb44e | 6835 | } |
3cd7d1dd | 6836 | |
636aa200 BS |
6837 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
6838 | { | |
f78fb44e AJ |
6839 | #if defined(TARGET_PPC64) |
6840 | tcg_gen_mov_i64(cpu_gpr[reg], t); | |
6841 | #else | |
a7812ae4 | 6842 | TCGv_i64 tmp = tcg_temp_new_i64(); |
f78fb44e | 6843 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
f78fb44e AJ |
6844 | tcg_gen_shri_i64(tmp, t, 32); |
6845 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); | |
a7812ae4 | 6846 | tcg_temp_free_i64(tmp); |
3cd7d1dd | 6847 | #endif |
f78fb44e | 6848 | } |
3cd7d1dd | 6849 | |
70560da7 | 6850 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
99e300ef | 6851 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
6852 | { \ |
6853 | if (Rc(ctx->opcode)) \ | |
6854 | gen_##name1(ctx); \ | |
6855 | else \ | |
6856 | gen_##name0(ctx); \ | |
6857 | } | |
6858 | ||
6859 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 6860 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 6861 | { |
e06fcd75 | 6862 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
6863 | } |
6864 | ||
57951c27 AJ |
6865 | /* SPE logic */ |
6866 | #if defined(TARGET_PPC64) | |
6867 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6868 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6869 | { \ |
6870 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6871 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
6872 | return; \ |
6873 | } \ | |
57951c27 AJ |
6874 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6875 | cpu_gpr[rB(ctx->opcode)]); \ | |
6876 | } | |
6877 | #else | |
6878 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6879 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6880 | { \ |
6881 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6882 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
6883 | return; \ |
6884 | } \ | |
6885 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
6886 | cpu_gpr[rB(ctx->opcode)]); \ | |
6887 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6888 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 6889 | } |
57951c27 AJ |
6890 | #endif |
6891 | ||
6892 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
6893 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
6894 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
6895 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
6896 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
6897 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
6898 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
6899 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 6900 | |
57951c27 AJ |
6901 | /* SPE logic immediate */ |
6902 | #if defined(TARGET_PPC64) | |
6903 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 6904 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a AJ |
6905 | { \ |
6906 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6907 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
3d3a6a0a AJ |
6908 | return; \ |
6909 | } \ | |
a7812ae4 PB |
6910 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6911 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6912 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6913 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6914 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
6915 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6916 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6917 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6918 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
6919 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6920 | tcg_temp_free_i32(t0); \ |
6921 | tcg_temp_free_i32(t1); \ | |
3d3a6a0a | 6922 | } |
57951c27 AJ |
6923 | #else |
6924 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 6925 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6926 | { \ |
6927 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6928 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
6929 | return; \ |
6930 | } \ | |
57951c27 AJ |
6931 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6932 | rB(ctx->opcode)); \ | |
6933 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6934 | rB(ctx->opcode)); \ | |
0487d6a8 | 6935 | } |
57951c27 AJ |
6936 | #endif |
6937 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); | |
6938 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
6939 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
6940 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 6941 | |
57951c27 AJ |
6942 | /* SPE arithmetic */ |
6943 | #if defined(TARGET_PPC64) | |
6944 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
636aa200 | 6945 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6946 | { \ |
6947 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6948 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
6949 | return; \ |
6950 | } \ | |
a7812ae4 PB |
6951 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6952 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6953 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6954 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6955 | tcg_op(t0, t0); \ | |
6956 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6957 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6958 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6959 | tcg_op(t1, t1); \ |
6960 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6961 | tcg_temp_free_i32(t0); \ |
6962 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 6963 | } |
57951c27 | 6964 | #else |
a7812ae4 | 6965 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 6966 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6967 | { \ |
6968 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6969 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
6970 | return; \ |
6971 | } \ | |
6972 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ | |
6973 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
6974 | } | |
6975 | #endif | |
0487d6a8 | 6976 | |
636aa200 | 6977 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
6978 | { |
6979 | int l1 = gen_new_label(); | |
6980 | int l2 = gen_new_label(); | |
0487d6a8 | 6981 | |
57951c27 AJ |
6982 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
6983 | tcg_gen_neg_i32(ret, arg1); | |
6984 | tcg_gen_br(l2); | |
6985 | gen_set_label(l1); | |
a7812ae4 | 6986 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
6987 | gen_set_label(l2); |
6988 | } | |
6989 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
6990 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
6991 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
6992 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 6993 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 6994 | { |
57951c27 AJ |
6995 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
6996 | tcg_gen_ext16u_i32(ret, ret); | |
6997 | } | |
6998 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
6999 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
7000 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 7001 | |
57951c27 AJ |
7002 | #if defined(TARGET_PPC64) |
7003 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7004 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7005 | { \ |
7006 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7007 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7008 | return; \ |
7009 | } \ | |
a7812ae4 PB |
7010 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7011 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7012 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ | |
501e23c4 | 7013 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
57951c27 AJ |
7014 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7015 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ | |
7016 | tcg_op(t0, t0, t2); \ | |
7017 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7018 | tcg_gen_trunc_i64_i32(t1, t3); \ | |
7019 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7020 | tcg_gen_trunc_i64_i32(t2, t3); \ | |
a7812ae4 | 7021 | tcg_temp_free_i64(t3); \ |
57951c27 | 7022 | tcg_op(t1, t1, t2); \ |
a7812ae4 | 7023 | tcg_temp_free_i32(t2); \ |
57951c27 | 7024 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
a7812ae4 PB |
7025 | tcg_temp_free_i32(t0); \ |
7026 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7027 | } |
57951c27 AJ |
7028 | #else |
7029 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7030 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7031 | { \ |
7032 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7033 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7034 | return; \ |
7035 | } \ | |
57951c27 AJ |
7036 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7037 | cpu_gpr[rB(ctx->opcode)]); \ | |
7038 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7039 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 7040 | } |
57951c27 | 7041 | #endif |
0487d6a8 | 7042 | |
636aa200 | 7043 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7044 | { |
a7812ae4 | 7045 | TCGv_i32 t0; |
57951c27 | 7046 | int l1, l2; |
0487d6a8 | 7047 | |
57951c27 AJ |
7048 | l1 = gen_new_label(); |
7049 | l2 = gen_new_label(); | |
a7812ae4 | 7050 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7051 | /* No error here: 6 bits are used */ |
7052 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7053 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7054 | tcg_gen_shr_i32(ret, arg1, t0); | |
7055 | tcg_gen_br(l2); | |
7056 | gen_set_label(l1); | |
7057 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7058 | gen_set_label(l2); |
a7812ae4 | 7059 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7060 | } |
7061 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 7062 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7063 | { |
a7812ae4 | 7064 | TCGv_i32 t0; |
57951c27 AJ |
7065 | int l1, l2; |
7066 | ||
7067 | l1 = gen_new_label(); | |
7068 | l2 = gen_new_label(); | |
a7812ae4 | 7069 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7070 | /* No error here: 6 bits are used */ |
7071 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7072 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7073 | tcg_gen_sar_i32(ret, arg1, t0); | |
7074 | tcg_gen_br(l2); | |
7075 | gen_set_label(l1); | |
7076 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7077 | gen_set_label(l2); |
a7812ae4 | 7078 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7079 | } |
7080 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 7081 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7082 | { |
a7812ae4 | 7083 | TCGv_i32 t0; |
57951c27 AJ |
7084 | int l1, l2; |
7085 | ||
7086 | l1 = gen_new_label(); | |
7087 | l2 = gen_new_label(); | |
a7812ae4 | 7088 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7089 | /* No error here: 6 bits are used */ |
7090 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7091 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7092 | tcg_gen_shl_i32(ret, arg1, t0); | |
7093 | tcg_gen_br(l2); | |
7094 | gen_set_label(l1); | |
7095 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 7096 | gen_set_label(l2); |
a7812ae4 | 7097 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7098 | } |
7099 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 7100 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7101 | { |
a7812ae4 | 7102 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
7103 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
7104 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 7105 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7106 | } |
7107 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 7108 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
7109 | { |
7110 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7111 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7112 | return; |
7113 | } | |
7114 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7115 | TCGv t0 = tcg_temp_new(); |
7116 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7117 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7118 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
7119 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7120 | tcg_temp_free(t0); | |
7121 | tcg_temp_free(t1); | |
7122 | #else | |
7123 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7124 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7125 | #endif | |
7126 | } | |
7127 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 7128 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 7129 | { |
57951c27 AJ |
7130 | tcg_gen_sub_i32(ret, arg2, arg1); |
7131 | } | |
7132 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 7133 | |
57951c27 AJ |
7134 | /* SPE arithmetic immediate */ |
7135 | #if defined(TARGET_PPC64) | |
7136 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7137 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7138 | { \ |
7139 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7140 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7141 | return; \ |
7142 | } \ | |
a7812ae4 PB |
7143 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7144 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7145 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7146 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7147 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
7148 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7149 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
e06fcd75 | 7150 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7151 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
7152 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7153 | tcg_temp_free_i32(t0); \ |
7154 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7155 | } |
7156 | #else | |
7157 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7158 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7159 | { \ |
7160 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7161 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7162 | return; \ |
7163 | } \ | |
7164 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
7165 | rA(ctx->opcode)); \ | |
7166 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ | |
7167 | rA(ctx->opcode)); \ | |
7168 | } | |
7169 | #endif | |
7170 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); | |
7171 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
7172 | ||
7173 | /* SPE comparison */ | |
7174 | #if defined(TARGET_PPC64) | |
7175 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7176 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7177 | { \ |
7178 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7179 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7180 | return; \ |
7181 | } \ | |
7182 | int l1 = gen_new_label(); \ | |
7183 | int l2 = gen_new_label(); \ | |
7184 | int l3 = gen_new_label(); \ | |
7185 | int l4 = gen_new_label(); \ | |
a7812ae4 PB |
7186 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7187 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7188 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7189 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7190 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7191 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ | |
a7812ae4 | 7192 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
7193 | tcg_gen_br(l2); \ |
7194 | gen_set_label(l1); \ | |
7195 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7196 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7197 | gen_set_label(l2); \ | |
7198 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7199 | tcg_gen_trunc_i64_i32(t0, t2); \ | |
7200 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7201 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7202 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7203 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
7204 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7205 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7206 | tcg_gen_br(l4); \ | |
7207 | gen_set_label(l3); \ | |
7208 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7209 | CRF_CH | CRF_CH_OR_CL); \ | |
7210 | gen_set_label(l4); \ | |
a7812ae4 PB |
7211 | tcg_temp_free_i32(t0); \ |
7212 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7213 | } |
7214 | #else | |
7215 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7216 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7217 | { \ |
7218 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7219 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7220 | return; \ |
7221 | } \ | |
7222 | int l1 = gen_new_label(); \ | |
7223 | int l2 = gen_new_label(); \ | |
7224 | int l3 = gen_new_label(); \ | |
7225 | int l4 = gen_new_label(); \ | |
7226 | \ | |
7227 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
7228 | cpu_gpr[rB(ctx->opcode)], l1); \ | |
7229 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ | |
7230 | tcg_gen_br(l2); \ | |
7231 | gen_set_label(l1); \ | |
7232 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7233 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7234 | gen_set_label(l2); \ | |
7235 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ | |
7236 | cpu_gprh[rB(ctx->opcode)], l3); \ | |
7237 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7238 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7239 | tcg_gen_br(l4); \ | |
7240 | gen_set_label(l3); \ | |
7241 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7242 | CRF_CH | CRF_CH_OR_CL); \ | |
7243 | gen_set_label(l4); \ | |
7244 | } | |
7245 | #endif | |
7246 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); | |
7247 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
7248 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
7249 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
7250 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
7251 | ||
7252 | /* SPE misc */ | |
636aa200 | 7253 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
7254 | { |
7255 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
7256 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
7257 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 7258 | } |
636aa200 | 7259 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
7260 | { |
7261 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7262 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7263 | return; |
7264 | } | |
7265 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7266 | TCGv t0 = tcg_temp_new(); |
7267 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7268 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7269 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); |
7270 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7271 | tcg_temp_free(t0); | |
7272 | tcg_temp_free(t1); | |
7273 | #else | |
57951c27 | 7274 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
33890b3e | 7275 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7276 | #endif |
7277 | } | |
636aa200 | 7278 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
7279 | { |
7280 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7281 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7282 | return; |
7283 | } | |
7284 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7285 | TCGv t0 = tcg_temp_new(); |
7286 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7287 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7288 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); |
7289 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7290 | tcg_temp_free(t0); | |
7291 | tcg_temp_free(t1); | |
7292 | #else | |
7293 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7294 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7295 | #endif | |
7296 | } | |
636aa200 | 7297 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
7298 | { |
7299 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7300 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7301 | return; |
7302 | } | |
7303 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7304 | TCGv t0 = tcg_temp_new(); |
7305 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7306 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7307 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
7308 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7309 | tcg_temp_free(t0); | |
7310 | tcg_temp_free(t1); | |
7311 | #else | |
33890b3e NF |
7312 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
7313 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
7314 | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); | |
7315 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7316 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); | |
7317 | tcg_temp_free_i32(tmp); | |
7318 | } else { | |
7319 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7320 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7321 | } | |
57951c27 AJ |
7322 | #endif |
7323 | } | |
636aa200 | 7324 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 7325 | { |
ae01847f | 7326 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 7327 | |
57951c27 | 7328 | #if defined(TARGET_PPC64) |
38d14952 | 7329 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7330 | #else |
7331 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7332 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7333 | #endif | |
7334 | } | |
636aa200 | 7335 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 7336 | { |
ae01847f | 7337 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 7338 | |
57951c27 | 7339 | #if defined(TARGET_PPC64) |
38d14952 | 7340 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7341 | #else |
7342 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7343 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7344 | #endif | |
0487d6a8 JM |
7345 | } |
7346 | ||
636aa200 | 7347 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 AJ |
7348 | { |
7349 | int l1 = gen_new_label(); | |
7350 | int l2 = gen_new_label(); | |
7351 | int l3 = gen_new_label(); | |
7352 | int l4 = gen_new_label(); | |
a7812ae4 | 7353 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 | 7354 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
7355 | TCGv t1 = tcg_temp_local_new(); |
7356 | TCGv t2 = tcg_temp_local_new(); | |
57951c27 AJ |
7357 | #endif |
7358 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); | |
7359 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
7360 | #if defined(TARGET_PPC64) | |
7361 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7362 | #else | |
7363 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7364 | #endif | |
7365 | tcg_gen_br(l2); | |
7366 | gen_set_label(l1); | |
7367 | #if defined(TARGET_PPC64) | |
7368 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7369 | #else | |
7370 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7371 | #endif | |
7372 | gen_set_label(l2); | |
7373 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
7374 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
7375 | #if defined(TARGET_PPC64) | |
17d9b3af | 7376 | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
7377 | #else |
7378 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7379 | #endif | |
7380 | tcg_gen_br(l4); | |
7381 | gen_set_label(l3); | |
7382 | #if defined(TARGET_PPC64) | |
17d9b3af | 7383 | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7384 | #else |
7385 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7386 | #endif | |
7387 | gen_set_label(l4); | |
a7812ae4 | 7388 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7389 | #if defined(TARGET_PPC64) |
7390 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); | |
7391 | tcg_temp_free(t1); | |
7392 | tcg_temp_free(t2); | |
7393 | #endif | |
7394 | } | |
e8eaa2c0 BS |
7395 | |
7396 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
7397 | { |
7398 | gen_evsel(ctx); | |
7399 | } | |
e8eaa2c0 BS |
7400 | |
7401 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
7402 | { |
7403 | gen_evsel(ctx); | |
7404 | } | |
e8eaa2c0 BS |
7405 | |
7406 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
7407 | { |
7408 | gen_evsel(ctx); | |
7409 | } | |
e8eaa2c0 BS |
7410 | |
7411 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
7412 | { |
7413 | gen_evsel(ctx); | |
7414 | } | |
0487d6a8 | 7415 | |
a0e13900 FC |
7416 | /* Multiply */ |
7417 | ||
7418 | static inline void gen_evmwumi(DisasContext *ctx) | |
7419 | { | |
7420 | TCGv_i64 t0, t1; | |
7421 | ||
7422 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7423 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7424 | return; |
7425 | } | |
7426 | ||
7427 | t0 = tcg_temp_new_i64(); | |
7428 | t1 = tcg_temp_new_i64(); | |
7429 | ||
7430 | /* t0 := rA; t1 := rB */ | |
7431 | #if defined(TARGET_PPC64) | |
7432 | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7433 | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7434 | #else | |
7435 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7436 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7437 | #endif | |
7438 | ||
7439 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7440 | ||
7441 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7442 | ||
7443 | tcg_temp_free_i64(t0); | |
7444 | tcg_temp_free_i64(t1); | |
7445 | } | |
7446 | ||
7447 | static inline void gen_evmwumia(DisasContext *ctx) | |
7448 | { | |
7449 | TCGv_i64 tmp; | |
7450 | ||
7451 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7452 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7453 | return; |
7454 | } | |
7455 | ||
7456 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7457 | ||
7458 | tmp = tcg_temp_new_i64(); | |
7459 | ||
7460 | /* acc := rD */ | |
7461 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7462 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7463 | tcg_temp_free_i64(tmp); |
7464 | } | |
7465 | ||
7466 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
7467 | { | |
7468 | TCGv_i64 acc; | |
7469 | TCGv_i64 tmp; | |
7470 | ||
7471 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7472 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7473 | return; |
7474 | } | |
7475 | ||
7476 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7477 | ||
7478 | acc = tcg_temp_new_i64(); | |
7479 | tmp = tcg_temp_new_i64(); | |
7480 | ||
7481 | /* tmp := rD */ | |
7482 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7483 | ||
7484 | /* Load acc */ | |
1328c2bf | 7485 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7486 | |
7487 | /* acc := tmp + acc */ | |
7488 | tcg_gen_add_i64(acc, acc, tmp); | |
7489 | ||
7490 | /* Store acc */ | |
1328c2bf | 7491 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7492 | |
7493 | /* rD := acc */ | |
7494 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7495 | ||
7496 | tcg_temp_free_i64(acc); | |
7497 | tcg_temp_free_i64(tmp); | |
7498 | } | |
7499 | ||
7500 | static inline void gen_evmwsmi(DisasContext *ctx) | |
7501 | { | |
7502 | TCGv_i64 t0, t1; | |
7503 | ||
7504 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7505 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7506 | return; |
7507 | } | |
7508 | ||
7509 | t0 = tcg_temp_new_i64(); | |
7510 | t1 = tcg_temp_new_i64(); | |
7511 | ||
7512 | /* t0 := rA; t1 := rB */ | |
7513 | #if defined(TARGET_PPC64) | |
7514 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7515 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7516 | #else | |
7517 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7518 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7519 | #endif | |
7520 | ||
7521 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7522 | ||
7523 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7524 | ||
7525 | tcg_temp_free_i64(t0); | |
7526 | tcg_temp_free_i64(t1); | |
7527 | } | |
7528 | ||
7529 | static inline void gen_evmwsmia(DisasContext *ctx) | |
7530 | { | |
7531 | TCGv_i64 tmp; | |
7532 | ||
7533 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7534 | ||
7535 | tmp = tcg_temp_new_i64(); | |
7536 | ||
7537 | /* acc := rD */ | |
7538 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7539 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7540 | |
7541 | tcg_temp_free_i64(tmp); | |
7542 | } | |
7543 | ||
7544 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
7545 | { | |
7546 | TCGv_i64 acc = tcg_temp_new_i64(); | |
7547 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
7548 | ||
7549 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7550 | ||
7551 | acc = tcg_temp_new_i64(); | |
7552 | tmp = tcg_temp_new_i64(); | |
7553 | ||
7554 | /* tmp := rD */ | |
7555 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7556 | ||
7557 | /* Load acc */ | |
1328c2bf | 7558 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7559 | |
7560 | /* acc := tmp + acc */ | |
7561 | tcg_gen_add_i64(acc, acc, tmp); | |
7562 | ||
7563 | /* Store acc */ | |
1328c2bf | 7564 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7565 | |
7566 | /* rD := acc */ | |
7567 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7568 | ||
7569 | tcg_temp_free_i64(acc); | |
7570 | tcg_temp_free_i64(tmp); | |
7571 | } | |
7572 | ||
70560da7 FC |
7573 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
7574 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7575 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7576 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7577 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7578 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7579 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7580 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // | |
7581 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); | |
7582 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7583 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7584 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7585 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7586 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7587 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7588 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
7589 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7590 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7591 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7592 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); | |
7593 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7594 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7595 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // | |
7596 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); | |
7597 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7598 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7599 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7600 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7601 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// | |
0487d6a8 | 7602 | |
6a6ae23f | 7603 | /* SPE load and stores */ |
636aa200 | 7604 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
7605 | { |
7606 | target_ulong uimm = rB(ctx->opcode); | |
7607 | ||
76db3ba4 | 7608 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 7609 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 7610 | } else { |
6a6ae23f | 7611 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
c791fe84 | 7612 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
7613 | tcg_gen_ext32u_tl(EA, EA); |
7614 | } | |
76db3ba4 | 7615 | } |
0487d6a8 | 7616 | } |
6a6ae23f | 7617 | |
636aa200 | 7618 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7619 | { |
7620 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7621 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
6a6ae23f AJ |
7622 | #else |
7623 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
76db3ba4 | 7624 | gen_qemu_ld64(ctx, t0, addr); |
6a6ae23f AJ |
7625 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7626 | tcg_gen_shri_i64(t0, t0, 32); | |
7627 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); | |
7628 | tcg_temp_free_i64(t0); | |
7629 | #endif | |
0487d6a8 | 7630 | } |
6a6ae23f | 7631 | |
636aa200 | 7632 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7633 | { |
0487d6a8 | 7634 | #if defined(TARGET_PPC64) |
6a6ae23f | 7635 | TCGv t0 = tcg_temp_new(); |
76db3ba4 | 7636 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f | 7637 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
76db3ba4 AJ |
7638 | gen_addr_add(ctx, addr, addr, 4); |
7639 | gen_qemu_ld32u(ctx, t0, addr); | |
6a6ae23f AJ |
7640 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7641 | tcg_temp_free(t0); | |
7642 | #else | |
76db3ba4 AJ |
7643 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7644 | gen_addr_add(ctx, addr, addr, 4); | |
7645 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f | 7646 | #endif |
0487d6a8 | 7647 | } |
6a6ae23f | 7648 | |
636aa200 | 7649 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7650 | { |
7651 | TCGv t0 = tcg_temp_new(); | |
7652 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7653 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7654 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7655 | gen_addr_add(ctx, addr, addr, 2); |
7656 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7657 | tcg_gen_shli_tl(t0, t0, 32); |
7658 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7659 | gen_addr_add(ctx, addr, addr, 2); |
7660 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7661 | tcg_gen_shli_tl(t0, t0, 16); |
7662 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7663 | gen_addr_add(ctx, addr, addr, 2); |
7664 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7665 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7666 | #else |
76db3ba4 | 7667 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7668 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7669 | gen_addr_add(ctx, addr, addr, 2); |
7670 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7671 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7672 | gen_addr_add(ctx, addr, addr, 2); |
7673 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7674 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7675 | gen_addr_add(ctx, addr, addr, 2); |
7676 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7677 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7678 | #endif |
6a6ae23f | 7679 | tcg_temp_free(t0); |
0487d6a8 JM |
7680 | } |
7681 | ||
636aa200 | 7682 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7683 | { |
7684 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7685 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7686 | #if defined(TARGET_PPC64) |
7687 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
7688 | tcg_gen_shli_tl(t0, t0, 16); | |
7689 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7690 | #else | |
7691 | tcg_gen_shli_tl(t0, t0, 16); | |
7692 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7693 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7694 | #endif | |
7695 | tcg_temp_free(t0); | |
0487d6a8 JM |
7696 | } |
7697 | ||
636aa200 | 7698 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7699 | { |
7700 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7701 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7702 | #if defined(TARGET_PPC64) |
7703 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7704 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7705 | #else | |
7706 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7707 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7708 | #endif | |
7709 | tcg_temp_free(t0); | |
0487d6a8 JM |
7710 | } |
7711 | ||
636aa200 | 7712 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7713 | { |
7714 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7715 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
7716 | #if defined(TARGET_PPC64) |
7717 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7718 | tcg_gen_ext32u_tl(t0, t0); | |
7719 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7720 | #else | |
7721 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7722 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7723 | #endif | |
7724 | tcg_temp_free(t0); | |
7725 | } | |
7726 | ||
636aa200 | 7727 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7728 | { |
7729 | TCGv t0 = tcg_temp_new(); | |
7730 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7731 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7732 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7733 | gen_addr_add(ctx, addr, addr, 2); |
7734 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7735 | tcg_gen_shli_tl(t0, t0, 16); |
7736 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7737 | #else | |
76db3ba4 | 7738 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7739 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7740 | gen_addr_add(ctx, addr, addr, 2); |
7741 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7742 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7743 | #endif | |
7744 | tcg_temp_free(t0); | |
7745 | } | |
7746 | ||
636aa200 | 7747 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7748 | { |
7749 | #if defined(TARGET_PPC64) | |
7750 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 AJ |
7751 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7752 | gen_addr_add(ctx, addr, addr, 2); | |
7753 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7754 | tcg_gen_shli_tl(t0, t0, 32); |
7755 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7756 | tcg_temp_free(t0); | |
7757 | #else | |
76db3ba4 AJ |
7758 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7759 | gen_addr_add(ctx, addr, addr, 2); | |
7760 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7761 | #endif |
7762 | } | |
7763 | ||
636aa200 | 7764 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7765 | { |
7766 | #if defined(TARGET_PPC64) | |
7767 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7768 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f | 7769 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7770 | gen_addr_add(ctx, addr, addr, 2); |
7771 | gen_qemu_ld16s(ctx, t0, addr); | |
6a6ae23f AJ |
7772 | tcg_gen_shli_tl(t0, t0, 32); |
7773 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7774 | tcg_temp_free(t0); | |
7775 | #else | |
76db3ba4 AJ |
7776 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7777 | gen_addr_add(ctx, addr, addr, 2); | |
7778 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7779 | #endif |
7780 | } | |
7781 | ||
636aa200 | 7782 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7783 | { |
7784 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7785 | gen_qemu_ld32u(ctx, t0, addr); |
0487d6a8 | 7786 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7787 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
7788 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7789 | #else | |
7790 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7791 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7792 | #endif | |
7793 | tcg_temp_free(t0); | |
7794 | } | |
7795 | ||
636aa200 | 7796 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7797 | { |
7798 | TCGv t0 = tcg_temp_new(); | |
7799 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7800 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7801 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
7802 | tcg_gen_shli_tl(t0, t0, 32); | |
7803 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7804 | gen_addr_add(ctx, addr, addr, 2); |
7805 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7806 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7807 | tcg_gen_shli_tl(t0, t0, 16); | |
7808 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7809 | #else | |
76db3ba4 | 7810 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7811 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
7812 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7813 | gen_addr_add(ctx, addr, addr, 2); |
7814 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7815 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7816 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
0487d6a8 | 7817 | #endif |
6a6ae23f AJ |
7818 | tcg_temp_free(t0); |
7819 | } | |
7820 | ||
636aa200 | 7821 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7822 | { |
7823 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7824 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
0487d6a8 | 7825 | #else |
6a6ae23f AJ |
7826 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7827 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); | |
76db3ba4 | 7828 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f AJ |
7829 | tcg_temp_free_i64(t0); |
7830 | #endif | |
7831 | } | |
7832 | ||
636aa200 | 7833 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7834 | { |
0487d6a8 | 7835 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7836 | TCGv t0 = tcg_temp_new(); |
7837 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7838 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7839 | tcg_temp_free(t0); |
7840 | #else | |
76db3ba4 | 7841 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7842 | #endif |
76db3ba4 AJ |
7843 | gen_addr_add(ctx, addr, addr, 4); |
7844 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7845 | } |
7846 | ||
636aa200 | 7847 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7848 | { |
7849 | TCGv t0 = tcg_temp_new(); | |
7850 | #if defined(TARGET_PPC64) | |
7851 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7852 | #else | |
7853 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7854 | #endif | |
76db3ba4 AJ |
7855 | gen_qemu_st16(ctx, t0, addr); |
7856 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f AJ |
7857 | #if defined(TARGET_PPC64) |
7858 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7859 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7860 | #else |
76db3ba4 | 7861 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7862 | #endif |
76db3ba4 | 7863 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 7864 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7865 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7866 | tcg_temp_free(t0); |
76db3ba4 AJ |
7867 | gen_addr_add(ctx, addr, addr, 2); |
7868 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7869 | } |
7870 | ||
636aa200 | 7871 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7872 | { |
7873 | TCGv t0 = tcg_temp_new(); | |
7874 | #if defined(TARGET_PPC64) | |
7875 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7876 | #else | |
7877 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7878 | #endif | |
76db3ba4 AJ |
7879 | gen_qemu_st16(ctx, t0, addr); |
7880 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 7881 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7882 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7883 | tcg_temp_free(t0); |
7884 | } | |
7885 | ||
636aa200 | 7886 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7887 | { |
7888 | #if defined(TARGET_PPC64) | |
7889 | TCGv t0 = tcg_temp_new(); | |
7890 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7891 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7892 | tcg_temp_free(t0); |
7893 | #else | |
76db3ba4 | 7894 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7895 | #endif |
76db3ba4 AJ |
7896 | gen_addr_add(ctx, addr, addr, 2); |
7897 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7898 | } |
7899 | ||
636aa200 | 7900 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7901 | { |
7902 | #if defined(TARGET_PPC64) | |
7903 | TCGv t0 = tcg_temp_new(); | |
7904 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7905 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7906 | tcg_temp_free(t0); |
7907 | #else | |
76db3ba4 | 7908 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7909 | #endif |
7910 | } | |
7911 | ||
636aa200 | 7912 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7913 | { |
76db3ba4 | 7914 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7915 | } |
7916 | ||
7917 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 7918 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
7919 | { \ |
7920 | TCGv t0; \ | |
7921 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7922 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
6a6ae23f AJ |
7923 | return; \ |
7924 | } \ | |
76db3ba4 | 7925 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
7926 | t0 = tcg_temp_new(); \ |
7927 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 7928 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 7929 | } else { \ |
76db3ba4 | 7930 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
7931 | } \ |
7932 | gen_op_##name(ctx, t0); \ | |
7933 | tcg_temp_free(t0); \ | |
7934 | } | |
7935 | ||
7936 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
7937 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
7938 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
7939 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
7940 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
7941 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
7942 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
7943 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
7944 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
7945 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
7946 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
7947 | ||
7948 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
7949 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
7950 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
7951 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
7952 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
7953 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
7954 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
7955 | |
7956 | /* Multiply and add - TODO */ | |
7957 | #if 0 | |
70560da7 FC |
7958 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
7959 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7960 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
7961 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7962 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
7963 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7964 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7965 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7966 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
7967 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7968 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
7969 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7970 | ||
7971 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7972 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7973 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7974 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7975 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7976 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7977 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7978 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7979 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7980 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7981 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7982 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7983 | ||
7984 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
7985 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
7986 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
7987 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
7988 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); | |
7989 | ||
7990 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
7991 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7992 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
7993 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7994 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
7995 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7996 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
7997 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7998 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
7999 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8000 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8001 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8002 | ||
8003 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8004 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8005 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8006 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8007 | ||
8008 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8009 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8010 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8011 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8012 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8013 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8014 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8015 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8016 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8017 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8018 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8019 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8020 | ||
8021 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8022 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8023 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8024 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8025 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
8026 | #endif |
8027 | ||
8028 | /*** SPE floating-point extension ***/ | |
1c97856d AJ |
8029 | #if defined(TARGET_PPC64) |
8030 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8031 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8032 | { \ |
1c97856d AJ |
8033 | TCGv_i32 t0; \ |
8034 | TCGv t1; \ | |
8035 | t0 = tcg_temp_new_i32(); \ | |
8036 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8037 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8038 | t1 = tcg_temp_new(); \ |
8039 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8040 | tcg_temp_free_i32(t0); \ | |
8041 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8042 | 0xFFFFFFFF00000000ULL); \ | |
8043 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8044 | tcg_temp_free(t1); \ | |
0487d6a8 | 8045 | } |
1c97856d | 8046 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8047 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8048 | { \ |
8049 | TCGv_i32 t0; \ | |
8050 | TCGv t1; \ | |
8051 | t0 = tcg_temp_new_i32(); \ | |
8e703949 | 8052 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8053 | t1 = tcg_temp_new(); \ |
8054 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8055 | tcg_temp_free_i32(t0); \ | |
8056 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8057 | 0xFFFFFFFF00000000ULL); \ | |
8058 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8059 | tcg_temp_free(t1); \ | |
8060 | } | |
8061 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8062 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8063 | { \ |
8064 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
8065 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8066 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8067 | tcg_temp_free_i32(t0); \ |
8068 | } | |
8069 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8070 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8071 | { \ |
8e703949 BS |
8072 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8073 | cpu_gpr[rB(ctx->opcode)]); \ | |
1c97856d AJ |
8074 | } |
8075 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8076 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8077 | { \ |
1c97856d AJ |
8078 | TCGv_i32 t0, t1; \ |
8079 | TCGv_i64 t2; \ | |
57951c27 | 8080 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8081 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8082 | return; \ |
8083 | } \ | |
1c97856d AJ |
8084 | t0 = tcg_temp_new_i32(); \ |
8085 | t1 = tcg_temp_new_i32(); \ | |
8086 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8087 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8088 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8089 | tcg_temp_free_i32(t1); \ |
8090 | t2 = tcg_temp_new(); \ | |
8091 | tcg_gen_extu_i32_tl(t2, t0); \ | |
8092 | tcg_temp_free_i32(t0); \ | |
8093 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8094 | 0xFFFFFFFF00000000ULL); \ | |
8095 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ | |
8096 | tcg_temp_free(t2); \ | |
57951c27 | 8097 | } |
1c97856d | 8098 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
636aa200 | 8099 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8100 | { \ |
8101 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8102 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8103 | return; \ |
8104 | } \ | |
8e703949 BS |
8105 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8106 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8107 | } |
1c97856d | 8108 | #define GEN_SPEFPUOP_COMP_32(name) \ |
636aa200 | 8109 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8110 | { \ |
1c97856d | 8111 | TCGv_i32 t0, t1; \ |
57951c27 | 8112 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8113 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8114 | return; \ |
8115 | } \ | |
1c97856d AJ |
8116 | t0 = tcg_temp_new_i32(); \ |
8117 | t1 = tcg_temp_new_i32(); \ | |
8118 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8119 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8120 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8121 | tcg_temp_free_i32(t0); \ |
8122 | tcg_temp_free_i32(t1); \ | |
8123 | } | |
8124 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8125 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8126 | { \ |
8127 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8128 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8129 | return; \ |
8130 | } \ | |
8e703949 | 8131 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8132 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8133 | } | |
8134 | #else | |
8135 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8136 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8137 | { \ |
8e703949 BS |
8138 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8139 | cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8140 | } |
1c97856d | 8141 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8142 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8143 | { \ |
8144 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8145 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8146 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8147 | tcg_temp_free_i64(t0); \ |
8148 | } | |
8149 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8150 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8151 | { \ |
8152 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8e703949 | 8153 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8154 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8155 | tcg_temp_free_i64(t0); \ | |
8156 | } | |
8157 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8158 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8159 | { \ |
8160 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8161 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8162 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8163 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8164 | tcg_temp_free_i64(t0); \ | |
8165 | } | |
8166 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8167 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8168 | { \ |
8169 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8170 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8171 | return; \ |
8172 | } \ | |
8e703949 | 8173 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8174 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8175 | } | |
8176 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 8177 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8178 | { \ |
8179 | TCGv_i64 t0, t1; \ | |
8180 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8181 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8182 | return; \ |
8183 | } \ | |
8184 | t0 = tcg_temp_new_i64(); \ | |
8185 | t1 = tcg_temp_new_i64(); \ | |
8186 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8187 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8188 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8189 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8190 | tcg_temp_free_i64(t0); \ | |
8191 | tcg_temp_free_i64(t1); \ | |
8192 | } | |
8193 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 8194 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8195 | { \ |
8196 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8197 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8198 | return; \ |
8199 | } \ | |
8e703949 | 8200 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8201 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8202 | } | |
8203 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8204 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8205 | { \ |
8206 | TCGv_i64 t0, t1; \ | |
8207 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8208 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8209 | return; \ |
8210 | } \ | |
8211 | t0 = tcg_temp_new_i64(); \ | |
8212 | t1 = tcg_temp_new_i64(); \ | |
8213 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8214 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8215 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8216 | tcg_temp_free_i64(t0); \ |
8217 | tcg_temp_free_i64(t1); \ | |
8218 | } | |
8219 | #endif | |
57951c27 | 8220 | |
0487d6a8 JM |
8221 | /* Single precision floating-point vectors operations */ |
8222 | /* Arithmetic */ | |
1c97856d AJ |
8223 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
8224 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
8225 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
8226 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 8227 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
8228 | { |
8229 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8230 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8231 | return; |
8232 | } | |
8233 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8234 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); |
1c97856d | 8235 | #else |
6d5c34fa MP |
8236 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); |
8237 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8238 | #endif |
8239 | } | |
636aa200 | 8240 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
8241 | { |
8242 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8243 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8244 | return; |
8245 | } | |
8246 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8247 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8248 | #else |
6d5c34fa MP |
8249 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8250 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8251 | #endif |
8252 | } | |
636aa200 | 8253 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
8254 | { |
8255 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8256 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8257 | return; |
8258 | } | |
8259 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8260 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8261 | #else |
6d5c34fa MP |
8262 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8263 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8264 | #endif |
8265 | } | |
8266 | ||
0487d6a8 | 8267 | /* Conversion */ |
1c97856d AJ |
8268 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8269 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
8270 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
8271 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
8272 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
8273 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
8274 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
8275 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
8276 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
8277 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
8278 | ||
0487d6a8 | 8279 | /* Comparison */ |
1c97856d AJ |
8280 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8281 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
8282 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
8283 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
8284 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
8285 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
8286 | |
8287 | /* Opcodes definitions */ | |
70560da7 FC |
8288 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8289 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8290 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8291 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8292 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8293 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8294 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8295 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8296 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8297 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8298 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8299 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8300 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8301 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8302 | |
8303 | /* Single precision floating-point operations */ | |
8304 | /* Arithmetic */ | |
1c97856d AJ |
8305 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8306 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
8307 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
8308 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 8309 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
8310 | { |
8311 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8312 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8313 | return; |
8314 | } | |
6d5c34fa | 8315 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 8316 | } |
636aa200 | 8317 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
8318 | { |
8319 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8320 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8321 | return; |
8322 | } | |
6d5c34fa | 8323 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 8324 | } |
636aa200 | 8325 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
8326 | { |
8327 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8328 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8329 | return; |
8330 | } | |
6d5c34fa | 8331 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
8332 | } |
8333 | ||
0487d6a8 | 8334 | /* Conversion */ |
1c97856d AJ |
8335 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8336 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
8337 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
8338 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
8339 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
8340 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
8341 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
8342 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
8343 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
8344 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
8345 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
8346 | ||
0487d6a8 | 8347 | /* Comparison */ |
1c97856d AJ |
8348 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
8349 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
8350 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
8351 | GEN_SPEFPUOP_COMP_32(efststgt); | |
8352 | GEN_SPEFPUOP_COMP_32(efststlt); | |
8353 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
8354 | |
8355 | /* Opcodes definitions */ | |
70560da7 FC |
8356 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8357 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8358 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8359 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8360 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8361 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // | |
8362 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8363 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8364 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8365 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8366 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8367 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8368 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8369 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8370 | |
8371 | /* Double precision floating-point operations */ | |
8372 | /* Arithmetic */ | |
1c97856d AJ |
8373 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
8374 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
8375 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
8376 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 8377 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
8378 | { |
8379 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8380 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8381 | return; |
8382 | } | |
8383 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8384 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); |
1c97856d | 8385 | #else |
6d5c34fa MP |
8386 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8387 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8388 | #endif |
8389 | } | |
636aa200 | 8390 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
8391 | { |
8392 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8393 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8394 | return; |
8395 | } | |
8396 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8397 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8398 | #else |
6d5c34fa MP |
8399 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8400 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8401 | #endif |
8402 | } | |
636aa200 | 8403 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
8404 | { |
8405 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8406 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8407 | return; |
8408 | } | |
8409 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8410 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8411 | #else |
6d5c34fa MP |
8412 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8413 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8414 | #endif |
8415 | } | |
8416 | ||
0487d6a8 | 8417 | /* Conversion */ |
1c97856d AJ |
8418 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
8419 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
8420 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
8421 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
8422 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
8423 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
8424 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
8425 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
8426 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
8427 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
8428 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
8429 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
8430 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
8431 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
8432 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 8433 | |
0487d6a8 | 8434 | /* Comparison */ |
1c97856d AJ |
8435 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
8436 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
8437 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
8438 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
8439 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
8440 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
8441 | |
8442 | /* Opcodes definitions */ | |
70560da7 FC |
8443 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
8444 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8445 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // | |
8446 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8447 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // | |
8448 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8449 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8450 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // | |
8451 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8452 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8453 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8454 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8455 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8456 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8457 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8458 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
0487d6a8 | 8459 | |
c227f099 | 8460 | static opcode_t opcodes[] = { |
5c55ff99 BS |
8461 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
8462 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
8463 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8464 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
8465 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8466 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), | |
8467 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8468 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8469 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8470 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8471 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
8472 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
8473 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
8474 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
8475 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8476 | #if defined(TARGET_PPC64) | |
8477 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
8478 | #endif | |
8479 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
8480 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
8481 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8482 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8483 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8484 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
8485 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
8486 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
8487 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8488 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8489 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8490 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8491 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), | |
eaabeef2 | 8492 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 8493 | #if defined(TARGET_PPC64) |
eaabeef2 | 8494 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 BS |
8495 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
8496 | #endif | |
8497 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8498 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8499 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8500 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
8501 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
8502 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
8503 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
8504 | #if defined(TARGET_PPC64) | |
8505 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
8506 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
8507 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
8508 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
8509 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
8510 | #endif | |
8511 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
8512 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8513 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8514 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
8515 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
bf45a2e6 | 8516 | GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), |
5c55ff99 | 8517 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
bf45a2e6 AJ |
8518 | GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), |
8519 | GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), | |
5c55ff99 BS |
8520 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
8521 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
8522 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
8523 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
8524 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT), | |
8525 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT), | |
8526 | #if defined(TARGET_PPC64) | |
8527 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8528 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
8529 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8530 | #endif | |
8531 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8532 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8533 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
8534 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
8535 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
8536 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
8537 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
8538 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
f844c817 | 8539 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
5c55ff99 BS |
8540 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
8541 | #if defined(TARGET_PPC64) | |
f844c817 | 8542 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
5c55ff99 BS |
8543 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
8544 | #endif | |
8545 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
8546 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
8547 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8548 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8549 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
8550 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
8551 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), | |
8552 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
8553 | #if defined(TARGET_PPC64) | |
8554 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
8555 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
8556 | #endif | |
8557 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
8558 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
8559 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8560 | #if defined(TARGET_PPC64) | |
8561 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
8562 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8563 | #endif | |
8564 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
8565 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
8566 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
8567 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
8568 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
8569 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
8570 | #if defined(TARGET_PPC64) | |
8571 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
8572 | #endif | |
8573 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
8574 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), | |
8575 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
8576 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
8577 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
8578 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), | |
8579 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), | |
8e33944f | 8580 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
8581 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
8582 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
8583 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
8584 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
8585 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
8586 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
8587 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
8588 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
8589 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
8590 | #if defined(TARGET_PPC64) | |
8591 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
8592 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
8593 | PPC_SEGMENT_64B), | |
8594 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
8595 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
8596 | PPC_SEGMENT_64B), | |
efdef95f DG |
8597 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
8598 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
8599 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
8600 | #endif |
8601 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
8602 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
8603 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
8604 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
8605 | #if defined(TARGET_PPC64) | |
8606 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
8607 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
8608 | #endif | |
8609 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
8610 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
8611 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
8612 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
8613 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
8614 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
8615 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
8616 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
8617 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
8618 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
8619 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
8620 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8621 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
8622 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
8623 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
8624 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
8625 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
8626 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
8627 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
8628 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8629 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
8630 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
8631 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
8632 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
8633 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
8634 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
8635 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
8636 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
8637 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
8638 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
8639 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
8640 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
8641 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
8642 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
8643 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
8644 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
8645 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
8646 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
8647 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
8648 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
8649 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
8650 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
8651 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
8652 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
8653 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
8654 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
8655 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
8656 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
8657 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
8658 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8659 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8660 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
8661 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
8662 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8663 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8664 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
8665 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
8666 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
8667 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
8668 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
8669 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
8670 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
8671 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
8672 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
8673 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
8674 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
8675 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
8676 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
8677 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
8678 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
8679 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 8680 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
8681 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
8682 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
8683 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
8684 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
8685 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
8686 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
8687 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
8688 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
8689 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
8690 | PPC_NONE, PPC2_BOOKE206), | |
8691 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
8692 | PPC_NONE, PPC2_BOOKE206), | |
8693 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
8694 | PPC_NONE, PPC2_BOOKE206), | |
8695 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
8696 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
8697 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
8698 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
8699 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
8700 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
8701 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
8702 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 8703 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 8704 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 8705 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
8706 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
8707 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 8708 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
8709 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
8710 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
8711 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
8712 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
8713 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
8714 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
8715 | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), | |
8716 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), | |
8717 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
8718 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
8719 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
8720 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
8721 | ||
8722 | #undef GEN_INT_ARITH_ADD | |
8723 | #undef GEN_INT_ARITH_ADD_CONST | |
8724 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8725 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
8726 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
8727 | add_ca, compute_ca, compute_ov) \ | |
8728 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
8729 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
8730 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
8731 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
8732 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
8733 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
8734 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
8735 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
8736 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
8737 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
8738 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
8739 | ||
8740 | #undef GEN_INT_ARITH_DIVW | |
8741 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
8742 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
8743 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
8744 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
8745 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
8746 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
8747 | ||
8748 | #if defined(TARGET_PPC64) | |
8749 | #undef GEN_INT_ARITH_DIVD | |
8750 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
8751 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8752 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
8753 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
8754 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
8755 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
8756 | ||
8757 | #undef GEN_INT_ARITH_MUL_HELPER | |
8758 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
8759 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8760 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
8761 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
8762 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
8763 | #endif | |
8764 | ||
8765 | #undef GEN_INT_ARITH_SUBF | |
8766 | #undef GEN_INT_ARITH_SUBF_CONST | |
8767 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8768 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
8769 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
8770 | add_ca, compute_ca, compute_ov) \ | |
8771 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
8772 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
8773 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
8774 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
8775 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
8776 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
8777 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
8778 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
8779 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
8780 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
8781 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
8782 | ||
8783 | #undef GEN_LOGICAL1 | |
8784 | #undef GEN_LOGICAL2 | |
8785 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
8786 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
8787 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
8788 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
8789 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
8790 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
8791 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
8792 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
8793 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
8794 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
8795 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
8796 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
8797 | #if defined(TARGET_PPC64) | |
8798 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
8799 | #endif | |
8800 | ||
8801 | #if defined(TARGET_PPC64) | |
8802 | #undef GEN_PPC64_R2 | |
8803 | #undef GEN_PPC64_R4 | |
8804 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
8805 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8806 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8807 | PPC_64B) | |
8808 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
8809 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8810 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
8811 | PPC_64B), \ | |
8812 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8813 | PPC_64B), \ | |
8814 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
8815 | PPC_64B) | |
8816 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
8817 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
8818 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
8819 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
8820 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
8821 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
8822 | #endif | |
8823 | ||
8824 | #undef _GEN_FLOAT_ACB | |
8825 | #undef GEN_FLOAT_ACB | |
8826 | #undef _GEN_FLOAT_AB | |
8827 | #undef GEN_FLOAT_AB | |
8828 | #undef _GEN_FLOAT_AC | |
8829 | #undef GEN_FLOAT_AC | |
8830 | #undef GEN_FLOAT_B | |
8831 | #undef GEN_FLOAT_BS | |
8832 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
8833 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
8834 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
8835 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
8836 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
8837 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8838 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8839 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
8840 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8841 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8842 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8843 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8844 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
8845 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8846 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8847 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
8848 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
8849 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
8850 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
8851 | ||
8852 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
8853 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
8854 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
8855 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
8856 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
8857 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
8858 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
8859 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
8860 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
8861 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
8862 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
8863 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
8864 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), | |
8865 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), | |
8866 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), | |
8867 | #if defined(TARGET_PPC64) | |
8868 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), | |
8869 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), | |
8870 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), | |
8871 | #endif | |
8872 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), | |
8873 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
8874 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
8875 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
5c55ff99 BS |
8876 | |
8877 | #undef GEN_LD | |
8878 | #undef GEN_LDU | |
8879 | #undef GEN_LDUX | |
cd6e9320 | 8880 | #undef GEN_LDX_E |
5c55ff99 BS |
8881 | #undef GEN_LDS |
8882 | #define GEN_LD(name, ldop, opc, type) \ | |
8883 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8884 | #define GEN_LDU(name, ldop, opc, type) \ | |
8885 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8886 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
8887 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
8888 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
8889 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
8890 | #define GEN_LDS(name, ldop, op, type) \ |
8891 | GEN_LD(name, ldop, op | 0x20, type) \ | |
8892 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
8893 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
8894 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
8895 | ||
8896 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
8897 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
8898 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
8899 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
8900 | #if defined(TARGET_PPC64) | |
8901 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
8902 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
8903 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
8904 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
cd6e9320 | 8905 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
8906 | #endif |
8907 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
8908 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
8909 | ||
8910 | #undef GEN_ST | |
8911 | #undef GEN_STU | |
8912 | #undef GEN_STUX | |
cd6e9320 | 8913 | #undef GEN_STX_E |
5c55ff99 BS |
8914 | #undef GEN_STS |
8915 | #define GEN_ST(name, stop, opc, type) \ | |
8916 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8917 | #define GEN_STU(name, stop, opc, type) \ | |
8918 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8919 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
8920 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
8921 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
8922 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
8923 | #define GEN_STS(name, stop, op, type) \ |
8924 | GEN_ST(name, stop, op | 0x20, type) \ | |
8925 | GEN_STU(name, stop, op | 0x21, type) \ | |
8926 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
8927 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
8928 | ||
8929 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
8930 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
8931 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
8932 | #if defined(TARGET_PPC64) | |
8933 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
8934 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
cd6e9320 | 8935 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
8936 | #endif |
8937 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
8938 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
8939 | ||
8940 | #undef GEN_LDF | |
8941 | #undef GEN_LDUF | |
8942 | #undef GEN_LDUXF | |
8943 | #undef GEN_LDXF | |
8944 | #undef GEN_LDFS | |
8945 | #define GEN_LDF(name, ldop, opc, type) \ | |
8946 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8947 | #define GEN_LDUF(name, ldop, opc, type) \ | |
8948 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8949 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
8950 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
8951 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
8952 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
8953 | #define GEN_LDFS(name, ldop, op, type) \ | |
8954 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
8955 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
8956 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
8957 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
8958 | ||
8959 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
8960 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
8961 | ||
8962 | #undef GEN_STF | |
8963 | #undef GEN_STUF | |
8964 | #undef GEN_STUXF | |
8965 | #undef GEN_STXF | |
8966 | #undef GEN_STFS | |
8967 | #define GEN_STF(name, stop, opc, type) \ | |
8968 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8969 | #define GEN_STUF(name, stop, opc, type) \ | |
8970 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8971 | #define GEN_STUXF(name, stop, opc, type) \ | |
8972 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
8973 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
8974 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
8975 | #define GEN_STFS(name, stop, op, type) \ | |
8976 | GEN_STF(name, stop, op | 0x20, type) \ | |
8977 | GEN_STUF(name, stop, op | 0x21, type) \ | |
8978 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
8979 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
8980 | ||
8981 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
8982 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
8983 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
8984 | ||
8985 | #undef GEN_CRLOGIC | |
8986 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
8987 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
8988 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
8989 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
8990 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
8991 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
8992 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
8993 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
8994 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
8995 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
8996 | ||
8997 | #undef GEN_MAC_HANDLER | |
8998 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
8999 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
9000 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
9001 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
9002 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
9003 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
9004 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
9005 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
9006 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
9007 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
9008 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
9009 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
9010 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
9011 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
9012 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
9013 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
9014 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
9015 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
9016 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
9017 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
9018 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
9019 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
9020 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
9021 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
9022 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
9023 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
9024 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
9025 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
9026 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
9027 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
9028 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
9029 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
9030 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
9031 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
9032 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
9033 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
9034 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
9035 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
9036 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
9037 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
9038 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
9039 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
9040 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
9041 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
9042 | ||
9043 | #undef GEN_VR_LDX | |
9044 | #undef GEN_VR_STX | |
9045 | #undef GEN_VR_LVE | |
9046 | #undef GEN_VR_STVE | |
9047 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
9048 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9049 | #define GEN_VR_STX(name, opc2, opc3) \ | |
9050 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9051 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
9052 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9053 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
9054 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9055 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
9056 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
9057 | GEN_VR_LVE(bx, 0x07, 0x00), | |
9058 | GEN_VR_LVE(hx, 0x07, 0x01), | |
9059 | GEN_VR_LVE(wx, 0x07, 0x02), | |
9060 | GEN_VR_STX(svx, 0x07, 0x07), | |
9061 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
9062 | GEN_VR_STVE(bx, 0x07, 0x04), | |
9063 | GEN_VR_STVE(hx, 0x07, 0x05), | |
9064 | GEN_VR_STVE(wx, 0x07, 0x06), | |
9065 | ||
9066 | #undef GEN_VX_LOGICAL | |
9067 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
9068 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9069 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), | |
9070 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
9071 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
9072 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
9073 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
9074 | ||
9075 | #undef GEN_VXFORM | |
9076 | #define GEN_VXFORM(name, opc2, opc3) \ | |
9077 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9078 | GEN_VXFORM(vaddubm, 0, 0), | |
9079 | GEN_VXFORM(vadduhm, 0, 1), | |
9080 | GEN_VXFORM(vadduwm, 0, 2), | |
9081 | GEN_VXFORM(vsububm, 0, 16), | |
9082 | GEN_VXFORM(vsubuhm, 0, 17), | |
9083 | GEN_VXFORM(vsubuwm, 0, 18), | |
9084 | GEN_VXFORM(vmaxub, 1, 0), | |
9085 | GEN_VXFORM(vmaxuh, 1, 1), | |
9086 | GEN_VXFORM(vmaxuw, 1, 2), | |
9087 | GEN_VXFORM(vmaxsb, 1, 4), | |
9088 | GEN_VXFORM(vmaxsh, 1, 5), | |
9089 | GEN_VXFORM(vmaxsw, 1, 6), | |
9090 | GEN_VXFORM(vminub, 1, 8), | |
9091 | GEN_VXFORM(vminuh, 1, 9), | |
9092 | GEN_VXFORM(vminuw, 1, 10), | |
9093 | GEN_VXFORM(vminsb, 1, 12), | |
9094 | GEN_VXFORM(vminsh, 1, 13), | |
9095 | GEN_VXFORM(vminsw, 1, 14), | |
9096 | GEN_VXFORM(vavgub, 1, 16), | |
9097 | GEN_VXFORM(vavguh, 1, 17), | |
9098 | GEN_VXFORM(vavguw, 1, 18), | |
9099 | GEN_VXFORM(vavgsb, 1, 20), | |
9100 | GEN_VXFORM(vavgsh, 1, 21), | |
9101 | GEN_VXFORM(vavgsw, 1, 22), | |
9102 | GEN_VXFORM(vmrghb, 6, 0), | |
9103 | GEN_VXFORM(vmrghh, 6, 1), | |
9104 | GEN_VXFORM(vmrghw, 6, 2), | |
9105 | GEN_VXFORM(vmrglb, 6, 4), | |
9106 | GEN_VXFORM(vmrglh, 6, 5), | |
9107 | GEN_VXFORM(vmrglw, 6, 6), | |
9108 | GEN_VXFORM(vmuloub, 4, 0), | |
9109 | GEN_VXFORM(vmulouh, 4, 1), | |
9110 | GEN_VXFORM(vmulosb, 4, 4), | |
9111 | GEN_VXFORM(vmulosh, 4, 5), | |
9112 | GEN_VXFORM(vmuleub, 4, 8), | |
9113 | GEN_VXFORM(vmuleuh, 4, 9), | |
9114 | GEN_VXFORM(vmulesb, 4, 12), | |
9115 | GEN_VXFORM(vmulesh, 4, 13), | |
9116 | GEN_VXFORM(vslb, 2, 4), | |
9117 | GEN_VXFORM(vslh, 2, 5), | |
9118 | GEN_VXFORM(vslw, 2, 6), | |
9119 | GEN_VXFORM(vsrb, 2, 8), | |
9120 | GEN_VXFORM(vsrh, 2, 9), | |
9121 | GEN_VXFORM(vsrw, 2, 10), | |
9122 | GEN_VXFORM(vsrab, 2, 12), | |
9123 | GEN_VXFORM(vsrah, 2, 13), | |
9124 | GEN_VXFORM(vsraw, 2, 14), | |
9125 | GEN_VXFORM(vslo, 6, 16), | |
9126 | GEN_VXFORM(vsro, 6, 17), | |
9127 | GEN_VXFORM(vaddcuw, 0, 6), | |
9128 | GEN_VXFORM(vsubcuw, 0, 22), | |
9129 | GEN_VXFORM(vaddubs, 0, 8), | |
9130 | GEN_VXFORM(vadduhs, 0, 9), | |
9131 | GEN_VXFORM(vadduws, 0, 10), | |
9132 | GEN_VXFORM(vaddsbs, 0, 12), | |
9133 | GEN_VXFORM(vaddshs, 0, 13), | |
9134 | GEN_VXFORM(vaddsws, 0, 14), | |
9135 | GEN_VXFORM(vsububs, 0, 24), | |
9136 | GEN_VXFORM(vsubuhs, 0, 25), | |
9137 | GEN_VXFORM(vsubuws, 0, 26), | |
9138 | GEN_VXFORM(vsubsbs, 0, 28), | |
9139 | GEN_VXFORM(vsubshs, 0, 29), | |
9140 | GEN_VXFORM(vsubsws, 0, 30), | |
9141 | GEN_VXFORM(vrlb, 2, 0), | |
9142 | GEN_VXFORM(vrlh, 2, 1), | |
9143 | GEN_VXFORM(vrlw, 2, 2), | |
9144 | GEN_VXFORM(vsl, 2, 7), | |
9145 | GEN_VXFORM(vsr, 2, 11), | |
9146 | GEN_VXFORM(vpkuhum, 7, 0), | |
9147 | GEN_VXFORM(vpkuwum, 7, 1), | |
9148 | GEN_VXFORM(vpkuhus, 7, 2), | |
9149 | GEN_VXFORM(vpkuwus, 7, 3), | |
9150 | GEN_VXFORM(vpkshus, 7, 4), | |
9151 | GEN_VXFORM(vpkswus, 7, 5), | |
9152 | GEN_VXFORM(vpkshss, 7, 6), | |
9153 | GEN_VXFORM(vpkswss, 7, 7), | |
9154 | GEN_VXFORM(vpkpx, 7, 12), | |
9155 | GEN_VXFORM(vsum4ubs, 4, 24), | |
9156 | GEN_VXFORM(vsum4sbs, 4, 28), | |
9157 | GEN_VXFORM(vsum4shs, 4, 25), | |
9158 | GEN_VXFORM(vsum2sws, 4, 26), | |
9159 | GEN_VXFORM(vsumsws, 4, 30), | |
9160 | GEN_VXFORM(vaddfp, 5, 0), | |
9161 | GEN_VXFORM(vsubfp, 5, 1), | |
9162 | GEN_VXFORM(vmaxfp, 5, 16), | |
9163 | GEN_VXFORM(vminfp, 5, 17), | |
9164 | ||
9165 | #undef GEN_VXRFORM1 | |
9166 | #undef GEN_VXRFORM | |
9167 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
9168 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
9169 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
9170 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
9171 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
9172 | GEN_VXRFORM(vcmpequb, 3, 0) | |
9173 | GEN_VXRFORM(vcmpequh, 3, 1) | |
9174 | GEN_VXRFORM(vcmpequw, 3, 2) | |
9175 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
9176 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
9177 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
9178 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
9179 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
9180 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
9181 | GEN_VXRFORM(vcmpeqfp, 3, 3) | |
9182 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
9183 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
9184 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
9185 | ||
9186 | #undef GEN_VXFORM_SIMM | |
9187 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
9188 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9189 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
9190 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
9191 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
9192 | ||
9193 | #undef GEN_VXFORM_NOA | |
9194 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
9195 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
9196 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
9197 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
9198 | GEN_VXFORM_NOA(vupklsb, 7, 10), | |
9199 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
9200 | GEN_VXFORM_NOA(vupkhpx, 7, 13), | |
9201 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
9202 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
9203 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 9204 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 BS |
9205 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
9206 | GEN_VXFORM_NOA(vrfim, 5, 8), | |
9207 | GEN_VXFORM_NOA(vrfin, 5, 9), | |
9208 | GEN_VXFORM_NOA(vrfip, 5, 10), | |
9209 | GEN_VXFORM_NOA(vrfiz, 5, 11), | |
9210 | ||
9211 | #undef GEN_VXFORM_UIMM | |
9212 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
9213 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9214 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
9215 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
9216 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
9217 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
9218 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
9219 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
9220 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
9221 | ||
9222 | #undef GEN_VAFORM_PAIRED | |
9223 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
9224 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
9225 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
9226 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
9227 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
9228 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
9229 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
9230 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
9231 | ||
9232 | #undef GEN_SPE | |
70560da7 FC |
9233 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
9234 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) | |
9235 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9236 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9237 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9238 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9239 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9240 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9241 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9242 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), | |
9243 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), | |
9244 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9245 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9246 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9247 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9248 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9249 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9250 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), | |
9251 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9252 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9253 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9254 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9255 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9256 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9257 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9258 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9259 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9260 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9261 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9262 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9263 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), | |
9264 | ||
9265 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9266 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9267 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9268 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9269 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9270 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9271 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9272 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9273 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9274 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9275 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9276 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9277 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9278 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9279 | ||
9280 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9281 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9282 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9283 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9284 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9285 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), | |
9286 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9287 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9288 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9289 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9290 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9291 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9292 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9293 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9294 | ||
9295 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9296 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9297 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), | |
9298 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9299 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9300 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9301 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9302 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), | |
9303 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9304 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9305 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9306 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9307 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9308 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9309 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9310 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
5c55ff99 BS |
9311 | |
9312 | #undef GEN_SPEOP_LDST | |
9313 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
9314 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
9315 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
9316 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
9317 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
9318 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
9319 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
9320 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
9321 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
9322 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
9323 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
9324 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
9325 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
9326 | ||
9327 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
9328 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
9329 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
9330 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
9331 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
9332 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
9333 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
9334 | }; | |
9335 | ||
0411a972 | 9336 | #include "helper_regs.h" |
a1389542 | 9337 | #include "translate_init.c" |
79aceca5 | 9338 | |
9a64fbe4 | 9339 | /*****************************************************************************/ |
3fc6c082 | 9340 | /* Misc PowerPC helpers */ |
1328c2bf | 9341 | void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf, |
36081602 | 9342 | int flags) |
79aceca5 | 9343 | { |
3fc6c082 FB |
9344 | #define RGPL 4 |
9345 | #define RFPL 4 | |
3fc6c082 | 9346 | |
79aceca5 FB |
9347 | int i; |
9348 | ||
29979a8d AG |
9349 | cpu_synchronize_state(env); |
9350 | ||
90e189ec | 9351 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9a78eead | 9352 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
da91a00f | 9353 | env->nip, env->lr, env->ctr, cpu_read_xer(env)); |
90e189ec BS |
9354 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9355 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
9356 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 9357 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 9358 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 9359 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 9360 | " DECR %08" PRIu32 |
76a66253 JM |
9361 | #endif |
9362 | "\n", | |
077fc206 | 9363 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
9364 | #if !defined(CONFIG_USER_ONLY) |
9365 | , cpu_ppc_load_decr(env) | |
9366 | #endif | |
9367 | ); | |
077fc206 | 9368 | #endif |
76a66253 | 9369 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
9370 | if ((i & (RGPL - 1)) == 0) |
9371 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 9372 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 9373 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 9374 | cpu_fprintf(f, "\n"); |
76a66253 | 9375 | } |
3fc6c082 | 9376 | cpu_fprintf(f, "CR "); |
76a66253 | 9377 | for (i = 0; i < 8; i++) |
7fe48483 FB |
9378 | cpu_fprintf(f, "%01x", env->crf[i]); |
9379 | cpu_fprintf(f, " ["); | |
76a66253 JM |
9380 | for (i = 0; i < 8; i++) { |
9381 | char a = '-'; | |
9382 | if (env->crf[i] & 0x08) | |
9383 | a = 'L'; | |
9384 | else if (env->crf[i] & 0x04) | |
9385 | a = 'G'; | |
9386 | else if (env->crf[i] & 0x02) | |
9387 | a = 'E'; | |
7fe48483 | 9388 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 9389 | } |
90e189ec BS |
9390 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
9391 | env->reserve_addr); | |
3fc6c082 FB |
9392 | for (i = 0; i < 32; i++) { |
9393 | if ((i & (RFPL - 1)) == 0) | |
9394 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 9395 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 9396 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 9397 | cpu_fprintf(f, "\n"); |
79aceca5 | 9398 | } |
30304420 | 9399 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 9400 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
9401 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
9402 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
9403 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
9404 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
9405 | ||
9406 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
9407 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
9408 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
9409 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
9410 | ||
9411 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
9412 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
9413 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
9414 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
9415 | ||
9416 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
9417 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
9418 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
9419 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
9420 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
9421 | ||
9422 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
9423 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
9424 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
9425 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
9426 | ||
9427 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
9428 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
9429 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
9430 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
9431 | ||
9432 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
9433 | " EPR " TARGET_FMT_lx "\n", | |
9434 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
9435 | env->spr[SPR_BOOKE_EPR]); | |
9436 | ||
9437 | /* FSL-specific */ | |
9438 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
9439 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
9440 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
9441 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
9442 | ||
9443 | /* | |
9444 | * IVORs are left out as they are large and do not change often -- | |
9445 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
9446 | */ | |
9447 | } | |
9448 | ||
697ab892 DG |
9449 | #if defined(TARGET_PPC64) |
9450 | if (env->flags & POWERPC_FLAG_CFAR) { | |
9451 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
9452 | } | |
9453 | #endif | |
9454 | ||
90dc8812 SW |
9455 | switch (env->mmu_model) { |
9456 | case POWERPC_MMU_32B: | |
9457 | case POWERPC_MMU_601: | |
9458 | case POWERPC_MMU_SOFT_6xx: | |
9459 | case POWERPC_MMU_SOFT_74xx: | |
9460 | #if defined(TARGET_PPC64) | |
90dc8812 SW |
9461 | case POWERPC_MMU_64B: |
9462 | #endif | |
9463 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); | |
9464 | break; | |
01662f3e | 9465 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
9466 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
9467 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
9468 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
9469 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
9470 | ||
9471 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
9472 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
9473 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
9474 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
9475 | ||
9476 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
9477 | " TLB1CFG " TARGET_FMT_lx "\n", | |
9478 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
9479 | env->spr[SPR_BOOKE_TLB1CFG]); | |
9480 | break; | |
9481 | default: | |
9482 | break; | |
9483 | } | |
f2e63a42 | 9484 | #endif |
79aceca5 | 9485 | |
3fc6c082 FB |
9486 | #undef RGPL |
9487 | #undef RFPL | |
79aceca5 FB |
9488 | } |
9489 | ||
1328c2bf | 9490 | void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf, |
76a66253 JM |
9491 | int flags) |
9492 | { | |
9493 | #if defined(DO_PPC_STATISTICS) | |
c227f099 | 9494 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
9495 | int op1, op2, op3; |
9496 | ||
9497 | t1 = env->opcodes; | |
9498 | for (op1 = 0; op1 < 64; op1++) { | |
9499 | handler = t1[op1]; | |
9500 | if (is_indirect_opcode(handler)) { | |
9501 | t2 = ind_table(handler); | |
9502 | for (op2 = 0; op2 < 32; op2++) { | |
9503 | handler = t2[op2]; | |
9504 | if (is_indirect_opcode(handler)) { | |
9505 | t3 = ind_table(handler); | |
9506 | for (op3 = 0; op3 < 32; op3++) { | |
9507 | handler = t3[op3]; | |
9508 | if (handler->count == 0) | |
9509 | continue; | |
9510 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9511 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9512 | op1, op2, op3, op1, (op3 << 5) | op2, |
9513 | handler->oname, | |
9514 | handler->count, handler->count); | |
9515 | } | |
9516 | } else { | |
9517 | if (handler->count == 0) | |
9518 | continue; | |
9519 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9520 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9521 | op1, op2, op1, op2, handler->oname, |
9522 | handler->count, handler->count); | |
9523 | } | |
9524 | } | |
9525 | } else { | |
9526 | if (handler->count == 0) | |
9527 | continue; | |
0bfcd599 BS |
9528 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
9529 | " %" PRId64 "\n", | |
76a66253 JM |
9530 | op1, op1, handler->oname, |
9531 | handler->count, handler->count); | |
9532 | } | |
9533 | } | |
9534 | #endif | |
9535 | } | |
9536 | ||
9a64fbe4 | 9537 | /*****************************************************************************/ |
1328c2bf | 9538 | static inline void gen_intermediate_code_internal(CPUPPCState *env, |
636aa200 BS |
9539 | TranslationBlock *tb, |
9540 | int search_pc) | |
79aceca5 | 9541 | { |
9fddaa0c | 9542 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 9543 | opc_handler_t **table, *handler; |
0fa85d43 | 9544 | target_ulong pc_start; |
79aceca5 | 9545 | uint16_t *gen_opc_end; |
a1d1bb31 | 9546 | CPUBreakpoint *bp; |
79aceca5 | 9547 | int j, lj = -1; |
2e70f6ef PB |
9548 | int num_insns; |
9549 | int max_insns; | |
79aceca5 FB |
9550 | |
9551 | pc_start = tb->pc; | |
92414b31 | 9552 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 9553 | ctx.nip = pc_start; |
79aceca5 | 9554 | ctx.tb = tb; |
e1833e1f | 9555 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 9556 | ctx.spr_cb = env->spr_cb; |
76db3ba4 AJ |
9557 | ctx.mem_idx = env->mmu_idx; |
9558 | ctx.access_type = -1; | |
9559 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
d9bce9d9 | 9560 | #if defined(TARGET_PPC64) |
e42a61f1 | 9561 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 9562 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 9563 | #endif |
3cc62370 | 9564 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 9565 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
9566 | ctx.spe_enabled = msr_spe; |
9567 | else | |
9568 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
9569 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
9570 | ctx.altivec_enabled = msr_vr; | |
9571 | else | |
9572 | ctx.altivec_enabled = 0; | |
d26bfc9a | 9573 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 9574 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 9575 | else |
8cbcb4fa | 9576 | ctx.singlestep_enabled = 0; |
d26bfc9a | 9577 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa AJ |
9578 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
9579 | if (unlikely(env->singlestep_enabled)) | |
9580 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
3fc6c082 | 9581 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
9582 | /* Single step trace mode */ |
9583 | msr_se = 1; | |
9584 | #endif | |
2e70f6ef PB |
9585 | num_insns = 0; |
9586 | max_insns = tb->cflags & CF_COUNT_MASK; | |
9587 | if (max_insns == 0) | |
9588 | max_insns = CF_COUNT_MASK; | |
9589 | ||
806f352d | 9590 | gen_tb_start(); |
9a64fbe4 | 9591 | /* Set env in case of segfault during code fetch */ |
efd7f486 EV |
9592 | while (ctx.exception == POWERPC_EXCP_NONE |
9593 | && tcg_ctx.gen_opc_ptr < gen_opc_end) { | |
72cf2d4f BS |
9594 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
9595 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 9596 | if (bp->pc == ctx.nip) { |
e06fcd75 | 9597 | gen_debug_exception(ctxp); |
ea4e754f FB |
9598 | break; |
9599 | } | |
9600 | } | |
9601 | } | |
76a66253 | 9602 | if (unlikely(search_pc)) { |
92414b31 | 9603 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
79aceca5 FB |
9604 | if (lj < j) { |
9605 | lj++; | |
9606 | while (lj < j) | |
ab1103de | 9607 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
79aceca5 | 9608 | } |
25983cad | 9609 | tcg_ctx.gen_opc_pc[lj] = ctx.nip; |
ab1103de | 9610 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 9611 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
79aceca5 | 9612 | } |
d12d51d5 | 9613 | LOG_DISAS("----------------\n"); |
90e189ec | 9614 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 9615 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
2e70f6ef PB |
9616 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9617 | gen_io_start(); | |
76db3ba4 | 9618 | if (unlikely(ctx.le_mode)) { |
2f5a189c | 9619 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 9620 | } else { |
2f5a189c | 9621 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 9622 | } |
d12d51d5 | 9623 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 9624 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
476b6d16 | 9625 | opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); |
fdefe51c | 9626 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
731c54f8 | 9627 | tcg_gen_debug_insn_start(ctx.nip); |
fdefe51c | 9628 | } |
046d6672 | 9629 | ctx.nip += 4; |
3fc6c082 | 9630 | table = env->opcodes; |
2e70f6ef | 9631 | num_insns++; |
79aceca5 FB |
9632 | handler = table[opc1(ctx.opcode)]; |
9633 | if (is_indirect_opcode(handler)) { | |
9634 | table = ind_table(handler); | |
9635 | handler = table[opc2(ctx.opcode)]; | |
9636 | if (is_indirect_opcode(handler)) { | |
9637 | table = ind_table(handler); | |
9638 | handler = table[opc3(ctx.opcode)]; | |
9639 | } | |
9640 | } | |
9641 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 9642 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
9643 | if (qemu_log_enabled()) { |
9644 | qemu_log("invalid/unsupported opcode: " | |
90e189ec BS |
9645 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
9646 | opc1(ctx.opcode), opc2(ctx.opcode), | |
9647 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa | 9648 | } |
76a66253 | 9649 | } else { |
70560da7 FC |
9650 | uint32_t inval; |
9651 | ||
9652 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
9653 | inval = handler->inval2; | |
9654 | } else { | |
9655 | inval = handler->inval1; | |
9656 | } | |
9657 | ||
9658 | if (unlikely((ctx.opcode & inval) != 0)) { | |
93fcfe39 AL |
9659 | if (qemu_log_enabled()) { |
9660 | qemu_log("invalid bits: %08x for opcode: " | |
90e189ec | 9661 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
70560da7 | 9662 | ctx.opcode & inval, opc1(ctx.opcode), |
90e189ec BS |
9663 | opc2(ctx.opcode), opc3(ctx.opcode), |
9664 | ctx.opcode, ctx.nip - 4); | |
76a66253 | 9665 | } |
e06fcd75 | 9666 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 9667 | break; |
79aceca5 | 9668 | } |
79aceca5 | 9669 | } |
4b3686fa | 9670 | (*(handler->handler))(&ctx); |
76a66253 JM |
9671 | #if defined(DO_PPC_STATISTICS) |
9672 | handler->count++; | |
9673 | #endif | |
9a64fbe4 | 9674 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
9675 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
9676 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
9677 | ctx.exception != POWERPC_SYSCALL && | |
9678 | ctx.exception != POWERPC_EXCP_TRAP && | |
9679 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 9680 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 9681 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
2e70f6ef | 9682 | (env->singlestep_enabled) || |
1b530a6d | 9683 | singlestep || |
2e70f6ef | 9684 | num_insns >= max_insns)) { |
d26bfc9a JM |
9685 | /* if we reach a page boundary or are single stepping, stop |
9686 | * generation | |
9687 | */ | |
8dd4983c | 9688 | break; |
76a66253 | 9689 | } |
3fc6c082 | 9690 | } |
2e70f6ef PB |
9691 | if (tb->cflags & CF_LAST_IO) |
9692 | gen_io_end(); | |
e1833e1f | 9693 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 9694 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 9695 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
8cbcb4fa | 9696 | if (unlikely(env->singlestep_enabled)) { |
e06fcd75 | 9697 | gen_debug_exception(ctxp); |
8cbcb4fa | 9698 | } |
76a66253 | 9699 | /* Generate the return instruction */ |
57fec1fe | 9700 | tcg_gen_exit_tb(0); |
9a64fbe4 | 9701 | } |
806f352d | 9702 | gen_tb_end(tb, num_insns); |
efd7f486 | 9703 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
76a66253 | 9704 | if (unlikely(search_pc)) { |
92414b31 | 9705 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
9a64fbe4 FB |
9706 | lj++; |
9707 | while (lj <= j) | |
ab1103de | 9708 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
9a64fbe4 | 9709 | } else { |
046d6672 | 9710 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 9711 | tb->icount = num_insns; |
9a64fbe4 | 9712 | } |
d9bce9d9 | 9713 | #if defined(DEBUG_DISAS) |
8fec2b8c | 9714 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 9715 | int flags; |
237c0af0 | 9716 | flags = env->bfd_mach; |
76db3ba4 | 9717 | flags |= ctx.le_mode << 16; |
93fcfe39 | 9718 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
f4359b9f | 9719 | log_target_disas(env, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 9720 | qemu_log("\n"); |
9fddaa0c | 9721 | } |
79aceca5 | 9722 | #endif |
79aceca5 FB |
9723 | } |
9724 | ||
1328c2bf | 9725 | void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9726 | { |
2cfc5f17 | 9727 | gen_intermediate_code_internal(env, tb, 0); |
79aceca5 FB |
9728 | } |
9729 | ||
1328c2bf | 9730 | void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9731 | { |
2cfc5f17 | 9732 | gen_intermediate_code_internal(env, tb, 1); |
79aceca5 | 9733 | } |
d2856f1a | 9734 | |
1328c2bf | 9735 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 9736 | { |
25983cad | 9737 | env->nip = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 9738 | } |