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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
79aceca5 | 21 | #include "cpu.h" |
76cad711 | 22 | #include "disas/disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
1de7afc9 | 24 | #include "qemu/host-utils.h" |
79aceca5 | 25 | |
a7812ae4 PB |
26 | #include "helper.h" |
27 | #define GEN_HELPER 1 | |
28 | #include "helper.h" | |
29 | ||
8cbcb4fa AJ |
30 | #define CPU_SINGLE_STEP 0x1 |
31 | #define CPU_BRANCH_STEP 0x2 | |
32 | #define GDBSTUB_SINGLE_STEP 0x4 | |
33 | ||
a750fc0b | 34 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 35 | //#define PPC_DEBUG_DISAS |
76a66253 | 36 | //#define DO_PPC_STATISTICS |
79aceca5 | 37 | |
d12d51d5 | 38 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 39 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
40 | #else |
41 | # define LOG_DISAS(...) do { } while (0) | |
42 | #endif | |
a750fc0b JM |
43 | /*****************************************************************************/ |
44 | /* Code translation helpers */ | |
c53be334 | 45 | |
f78fb44e | 46 | /* global register indexes */ |
a7812ae4 | 47 | static TCGv_ptr cpu_env; |
1d542695 | 48 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
f78fb44e | 49 | #if !defined(TARGET_PPC64) |
1d542695 | 50 | + 10*4 + 22*5 /* SPE GPRh */ |
f78fb44e | 51 | #endif |
a5e26afa | 52 | + 10*4 + 22*5 /* FPR */ |
47e4661c AJ |
53 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
54 | + 8*5 /* CRF */]; | |
f78fb44e AJ |
55 | static TCGv cpu_gpr[32]; |
56 | #if !defined(TARGET_PPC64) | |
57 | static TCGv cpu_gprh[32]; | |
58 | #endif | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fpr[32]; |
60 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
61 | static TCGv_i32 cpu_crf[8]; | |
bd568f18 | 62 | static TCGv cpu_nip; |
6527f6ea | 63 | static TCGv cpu_msr; |
cfdcd37a AJ |
64 | static TCGv cpu_ctr; |
65 | static TCGv cpu_lr; | |
697ab892 DG |
66 | #if defined(TARGET_PPC64) |
67 | static TCGv cpu_cfar; | |
68 | #endif | |
da91a00f | 69 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 70 | static TCGv cpu_reserve; |
30304420 | 71 | static TCGv cpu_fpscr; |
a7859e89 | 72 | static TCGv_i32 cpu_access_type; |
f78fb44e | 73 | |
022c62cb | 74 | #include "exec/gen-icount.h" |
2e70f6ef PB |
75 | |
76 | void ppc_translate_init(void) | |
77 | { | |
f78fb44e AJ |
78 | int i; |
79 | char* p; | |
2dc766da | 80 | size_t cpu_reg_names_size; |
b2437bf2 | 81 | static int done_init = 0; |
f78fb44e | 82 | |
2e70f6ef PB |
83 | if (done_init) |
84 | return; | |
f78fb44e | 85 | |
a7812ae4 | 86 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 87 | |
f78fb44e | 88 | p = cpu_reg_names; |
2dc766da | 89 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
90 | |
91 | for (i = 0; i < 8; i++) { | |
2dc766da | 92 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 | 93 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 94 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 95 | p += 5; |
2dc766da | 96 | cpu_reg_names_size -= 5; |
47e4661c AJ |
97 | } |
98 | ||
f78fb44e | 99 | for (i = 0; i < 32; i++) { |
2dc766da | 100 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 101 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 102 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 103 | p += (i < 10) ? 3 : 4; |
2dc766da | 104 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
f78fb44e | 105 | #if !defined(TARGET_PPC64) |
2dc766da | 106 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
a7812ae4 | 107 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 108 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 109 | p += (i < 10) ? 4 : 5; |
2dc766da | 110 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 111 | #endif |
1d542695 | 112 | |
2dc766da | 113 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 | 114 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 115 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 116 | p += (i < 10) ? 4 : 5; |
2dc766da | 117 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 118 | |
2dc766da | 119 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 120 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 121 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 122 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 123 | #else |
a7812ae4 | 124 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 125 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 126 | #endif |
1d542695 | 127 | p += (i < 10) ? 6 : 7; |
2dc766da | 128 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 129 | |
2dc766da | 130 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 131 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 132 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 133 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 134 | #else |
a7812ae4 | 135 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 136 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 137 | #endif |
1d542695 | 138 | p += (i < 10) ? 6 : 7; |
2dc766da | 139 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
f78fb44e | 140 | } |
f10dc08e | 141 | |
a7812ae4 | 142 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 143 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 144 | |
6527f6ea | 145 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 146 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 147 | |
a7812ae4 | 148 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 149 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 150 | |
a7812ae4 | 151 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 152 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 153 | |
697ab892 DG |
154 | #if defined(TARGET_PPC64) |
155 | cpu_cfar = tcg_global_mem_new(TCG_AREG0, | |
1328c2bf | 156 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
157 | #endif |
158 | ||
a7812ae4 | 159 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 160 | offsetof(CPUPPCState, xer), "xer"); |
da91a00f RH |
161 | cpu_so = tcg_global_mem_new(TCG_AREG0, |
162 | offsetof(CPUPPCState, so), "SO"); | |
163 | cpu_ov = tcg_global_mem_new(TCG_AREG0, | |
164 | offsetof(CPUPPCState, ov), "OV"); | |
165 | cpu_ca = tcg_global_mem_new(TCG_AREG0, | |
166 | offsetof(CPUPPCState, ca), "CA"); | |
3d7b417e | 167 | |
cf360a32 | 168 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 169 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 170 | "reserve_addr"); |
cf360a32 | 171 | |
30304420 DG |
172 | cpu_fpscr = tcg_global_mem_new(TCG_AREG0, |
173 | offsetof(CPUPPCState, fpscr), "fpscr"); | |
e1571908 | 174 | |
a7859e89 | 175 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 176 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 177 | |
f10dc08e | 178 | /* register helpers */ |
a7812ae4 | 179 | #define GEN_HELPER 2 |
f10dc08e AJ |
180 | #include "helper.h" |
181 | ||
2e70f6ef PB |
182 | done_init = 1; |
183 | } | |
184 | ||
79aceca5 FB |
185 | /* internal defines */ |
186 | typedef struct DisasContext { | |
187 | struct TranslationBlock *tb; | |
0fa85d43 | 188 | target_ulong nip; |
79aceca5 | 189 | uint32_t opcode; |
9a64fbe4 | 190 | uint32_t exception; |
3cc62370 FB |
191 | /* Routine used to access memory */ |
192 | int mem_idx; | |
76db3ba4 | 193 | int access_type; |
3cc62370 | 194 | /* Translation flags */ |
76db3ba4 | 195 | int le_mode; |
d9bce9d9 JM |
196 | #if defined(TARGET_PPC64) |
197 | int sf_mode; | |
697ab892 | 198 | int has_cfar; |
9a64fbe4 | 199 | #endif |
3cc62370 | 200 | int fpu_enabled; |
a9d9eb8f | 201 | int altivec_enabled; |
0487d6a8 | 202 | int spe_enabled; |
c227f099 | 203 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 204 | int singlestep_enabled; |
79aceca5 FB |
205 | } DisasContext; |
206 | ||
c227f099 | 207 | struct opc_handler_t { |
70560da7 FC |
208 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
209 | uint32_t inval1; | |
210 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
211 | uint32_t inval2; | |
9a64fbe4 | 212 | /* instruction type */ |
0487d6a8 | 213 | uint64_t type; |
a5858d7a AG |
214 | /* extended instruction type */ |
215 | uint64_t type2; | |
79aceca5 FB |
216 | /* handler */ |
217 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 218 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 219 | const char *oname; |
a750fc0b JM |
220 | #endif |
221 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
222 | uint64_t count; |
223 | #endif | |
3fc6c082 | 224 | }; |
79aceca5 | 225 | |
636aa200 | 226 | static inline void gen_reset_fpstatus(void) |
7c58044c | 227 | { |
8e703949 | 228 | gen_helper_reset_fpstatus(cpu_env); |
7c58044c JM |
229 | } |
230 | ||
636aa200 | 231 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 232 | { |
0f2f39c2 | 233 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 234 | |
7c58044c JM |
235 | if (set_fprf != 0) { |
236 | /* This case might be optimized later */ | |
0f2f39c2 | 237 | tcg_gen_movi_i32(t0, 1); |
8e703949 | 238 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
a7812ae4 | 239 | if (unlikely(set_rc)) { |
0f2f39c2 | 240 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 241 | } |
8e703949 | 242 | gen_helper_float_check_status(cpu_env); |
7c58044c JM |
243 | } else if (unlikely(set_rc)) { |
244 | /* We always need to compute fpcc */ | |
0f2f39c2 | 245 | tcg_gen_movi_i32(t0, 0); |
8e703949 | 246 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
0f2f39c2 | 247 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 248 | } |
af12906f | 249 | |
0f2f39c2 | 250 | tcg_temp_free_i32(t0); |
7c58044c JM |
251 | } |
252 | ||
636aa200 | 253 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 254 | { |
76db3ba4 AJ |
255 | if (ctx->access_type != access_type) { |
256 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
257 | ctx->access_type = access_type; | |
258 | } | |
a7859e89 AJ |
259 | } |
260 | ||
636aa200 | 261 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 JM |
262 | { |
263 | #if defined(TARGET_PPC64) | |
264 | if (ctx->sf_mode) | |
bd568f18 | 265 | tcg_gen_movi_tl(cpu_nip, nip); |
d9bce9d9 JM |
266 | else |
267 | #endif | |
bd568f18 | 268 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
d9bce9d9 JM |
269 | } |
270 | ||
636aa200 | 271 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
272 | { |
273 | TCGv_i32 t0, t1; | |
274 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
275 | gen_update_nip(ctx, ctx->nip); | |
276 | } | |
277 | t0 = tcg_const_i32(excp); | |
278 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 279 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
280 | tcg_temp_free_i32(t0); |
281 | tcg_temp_free_i32(t1); | |
282 | ctx->exception = (excp); | |
283 | } | |
e1833e1f | 284 | |
636aa200 | 285 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
286 | { |
287 | TCGv_i32 t0; | |
288 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
289 | gen_update_nip(ctx, ctx->nip); | |
290 | } | |
291 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 292 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
293 | tcg_temp_free_i32(t0); |
294 | ctx->exception = (excp); | |
295 | } | |
e1833e1f | 296 | |
636aa200 | 297 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
298 | { |
299 | TCGv_i32 t0; | |
5518f3a6 | 300 | |
ee2b3994 SB |
301 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
302 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
5518f3a6 | 303 | gen_update_nip(ctx, ctx->nip); |
ee2b3994 | 304 | } |
e06fcd75 | 305 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 306 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
307 | tcg_temp_free_i32(t0); |
308 | } | |
9a64fbe4 | 309 | |
636aa200 | 310 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
311 | { |
312 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
313 | } | |
a9d9eb8f | 314 | |
f24e5695 | 315 | /* Stop translation */ |
636aa200 | 316 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 317 | { |
d9bce9d9 | 318 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 319 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
320 | } |
321 | ||
f24e5695 | 322 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 323 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 324 | { |
e1833e1f | 325 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
326 | } |
327 | ||
79aceca5 | 328 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
329 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
330 | ||
331 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
332 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 333 | |
c7697e1f | 334 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
335 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
336 | ||
337 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
338 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 339 | |
c227f099 | 340 | typedef struct opcode_t { |
79aceca5 | 341 | unsigned char opc1, opc2, opc3; |
1235fc06 | 342 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
343 | unsigned char pad[5]; |
344 | #else | |
345 | unsigned char pad[1]; | |
346 | #endif | |
c227f099 | 347 | opc_handler_t handler; |
b55266b5 | 348 | const char *oname; |
c227f099 | 349 | } opcode_t; |
79aceca5 | 350 | |
a750fc0b | 351 | /*****************************************************************************/ |
79aceca5 FB |
352 | /*** Instruction decoding ***/ |
353 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 354 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
355 | { \ |
356 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
357 | } | |
358 | ||
359 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 360 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 361 | { \ |
18fba28c | 362 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
363 | } |
364 | ||
365 | /* Opcode part 1 */ | |
366 | EXTRACT_HELPER(opc1, 26, 6); | |
367 | /* Opcode part 2 */ | |
368 | EXTRACT_HELPER(opc2, 1, 5); | |
369 | /* Opcode part 3 */ | |
370 | EXTRACT_HELPER(opc3, 6, 5); | |
371 | /* Update Cr0 flags */ | |
372 | EXTRACT_HELPER(Rc, 0, 1); | |
373 | /* Destination */ | |
374 | EXTRACT_HELPER(rD, 21, 5); | |
375 | /* Source */ | |
376 | EXTRACT_HELPER(rS, 21, 5); | |
377 | /* First operand */ | |
378 | EXTRACT_HELPER(rA, 16, 5); | |
379 | /* Second operand */ | |
380 | EXTRACT_HELPER(rB, 11, 5); | |
381 | /* Third operand */ | |
382 | EXTRACT_HELPER(rC, 6, 5); | |
383 | /*** Get CRn ***/ | |
384 | EXTRACT_HELPER(crfD, 23, 3); | |
385 | EXTRACT_HELPER(crfS, 18, 3); | |
386 | EXTRACT_HELPER(crbD, 21, 5); | |
387 | EXTRACT_HELPER(crbA, 16, 5); | |
388 | EXTRACT_HELPER(crbB, 11, 5); | |
389 | /* SPR / TBL */ | |
3fc6c082 | 390 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 391 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
392 | { |
393 | uint32_t sprn = _SPR(opcode); | |
394 | ||
395 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
396 | } | |
79aceca5 FB |
397 | /*** Get constants ***/ |
398 | EXTRACT_HELPER(IMM, 12, 8); | |
399 | /* 16 bits signed immediate value */ | |
400 | EXTRACT_SHELPER(SIMM, 0, 16); | |
401 | /* 16 bits unsigned immediate value */ | |
402 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
403 | /* 5 bits signed immediate value */ |
404 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
405 | /* 5 bits signed immediate value */ |
406 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
407 | /* Bit count */ |
408 | EXTRACT_HELPER(NB, 11, 5); | |
409 | /* Shift count */ | |
410 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
411 | /* Vector shift count */ |
412 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
413 | /* Mask start */ |
414 | EXTRACT_HELPER(MB, 6, 5); | |
415 | /* Mask end */ | |
416 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
417 | /* Trap operand */ |
418 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
419 | |
420 | EXTRACT_HELPER(CRM, 12, 8); | |
421 | EXTRACT_HELPER(FM, 17, 8); | |
422 | EXTRACT_HELPER(SR, 16, 4); | |
e4bb997e | 423 | EXTRACT_HELPER(FPIMM, 12, 4); |
fb0eaffc | 424 | |
79aceca5 FB |
425 | /*** Jump target decoding ***/ |
426 | /* Displacement */ | |
427 | EXTRACT_SHELPER(d, 0, 16); | |
428 | /* Immediate address */ | |
636aa200 | 429 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
430 | { |
431 | return (opcode >> 0) & 0x03FFFFFC; | |
432 | } | |
433 | ||
636aa200 | 434 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
435 | { |
436 | return (opcode >> 0) & 0xFFFC; | |
437 | } | |
438 | ||
439 | EXTRACT_HELPER(BO, 21, 5); | |
440 | EXTRACT_HELPER(BI, 16, 5); | |
441 | /* Absolute/relative address */ | |
442 | EXTRACT_HELPER(AA, 1, 1); | |
443 | /* Link */ | |
444 | EXTRACT_HELPER(LK, 0, 1); | |
445 | ||
446 | /* Create a mask between <start> and <end> bits */ | |
636aa200 | 447 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 448 | { |
76a66253 | 449 | target_ulong ret; |
79aceca5 | 450 | |
76a66253 JM |
451 | #if defined(TARGET_PPC64) |
452 | if (likely(start == 0)) { | |
6f2d8978 | 453 | ret = UINT64_MAX << (63 - end); |
76a66253 | 454 | } else if (likely(end == 63)) { |
6f2d8978 | 455 | ret = UINT64_MAX >> start; |
76a66253 JM |
456 | } |
457 | #else | |
458 | if (likely(start == 0)) { | |
6f2d8978 | 459 | ret = UINT32_MAX << (31 - end); |
76a66253 | 460 | } else if (likely(end == 31)) { |
6f2d8978 | 461 | ret = UINT32_MAX >> start; |
76a66253 JM |
462 | } |
463 | #endif | |
464 | else { | |
465 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
466 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
467 | if (unlikely(start > end)) | |
468 | return ~ret; | |
469 | } | |
79aceca5 FB |
470 | |
471 | return ret; | |
472 | } | |
473 | ||
a750fc0b | 474 | /*****************************************************************************/ |
a750fc0b | 475 | /* PowerPC instructions table */ |
933dc6eb | 476 | |
76a66253 | 477 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 478 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 479 | { \ |
79aceca5 FB |
480 | .opc1 = op1, \ |
481 | .opc2 = op2, \ | |
482 | .opc3 = op3, \ | |
18fba28c | 483 | .pad = { 0, }, \ |
79aceca5 | 484 | .handler = { \ |
70560da7 FC |
485 | .inval1 = invl, \ |
486 | .type = _typ, \ | |
487 | .type2 = _typ2, \ | |
488 | .handler = &gen_##name, \ | |
489 | .oname = stringify(name), \ | |
490 | }, \ | |
491 | .oname = stringify(name), \ | |
492 | } | |
493 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
494 | { \ | |
495 | .opc1 = op1, \ | |
496 | .opc2 = op2, \ | |
497 | .opc3 = op3, \ | |
498 | .pad = { 0, }, \ | |
499 | .handler = { \ | |
500 | .inval1 = invl1, \ | |
501 | .inval2 = invl2, \ | |
9a64fbe4 | 502 | .type = _typ, \ |
a5858d7a | 503 | .type2 = _typ2, \ |
79aceca5 | 504 | .handler = &gen_##name, \ |
76a66253 | 505 | .oname = stringify(name), \ |
79aceca5 | 506 | }, \ |
3fc6c082 | 507 | .oname = stringify(name), \ |
79aceca5 | 508 | } |
a5858d7a | 509 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 510 | { \ |
c7697e1f JM |
511 | .opc1 = op1, \ |
512 | .opc2 = op2, \ | |
513 | .opc3 = op3, \ | |
514 | .pad = { 0, }, \ | |
515 | .handler = { \ | |
70560da7 | 516 | .inval1 = invl, \ |
c7697e1f | 517 | .type = _typ, \ |
a5858d7a | 518 | .type2 = _typ2, \ |
c7697e1f JM |
519 | .handler = &gen_##name, \ |
520 | .oname = onam, \ | |
521 | }, \ | |
522 | .oname = onam, \ | |
523 | } | |
76a66253 | 524 | #else |
a5858d7a | 525 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 526 | { \ |
c7697e1f JM |
527 | .opc1 = op1, \ |
528 | .opc2 = op2, \ | |
529 | .opc3 = op3, \ | |
530 | .pad = { 0, }, \ | |
531 | .handler = { \ | |
70560da7 FC |
532 | .inval1 = invl, \ |
533 | .type = _typ, \ | |
534 | .type2 = _typ2, \ | |
535 | .handler = &gen_##name, \ | |
536 | }, \ | |
537 | .oname = stringify(name), \ | |
538 | } | |
539 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
540 | { \ | |
541 | .opc1 = op1, \ | |
542 | .opc2 = op2, \ | |
543 | .opc3 = op3, \ | |
544 | .pad = { 0, }, \ | |
545 | .handler = { \ | |
546 | .inval1 = invl1, \ | |
547 | .inval2 = invl2, \ | |
c7697e1f | 548 | .type = _typ, \ |
a5858d7a | 549 | .type2 = _typ2, \ |
c7697e1f | 550 | .handler = &gen_##name, \ |
5c55ff99 BS |
551 | }, \ |
552 | .oname = stringify(name), \ | |
553 | } | |
a5858d7a | 554 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
555 | { \ |
556 | .opc1 = op1, \ | |
557 | .opc2 = op2, \ | |
558 | .opc3 = op3, \ | |
559 | .pad = { 0, }, \ | |
560 | .handler = { \ | |
70560da7 | 561 | .inval1 = invl, \ |
5c55ff99 | 562 | .type = _typ, \ |
a5858d7a | 563 | .type2 = _typ2, \ |
5c55ff99 BS |
564 | .handler = &gen_##name, \ |
565 | }, \ | |
566 | .oname = onam, \ | |
567 | } | |
568 | #endif | |
2e610050 | 569 | |
5c55ff99 | 570 | /* SPR load/store helpers */ |
636aa200 | 571 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 572 | { |
1328c2bf | 573 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 574 | } |
2e610050 | 575 | |
636aa200 | 576 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 577 | { |
1328c2bf | 578 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 579 | } |
2e610050 | 580 | |
54623277 | 581 | /* Invalid instruction */ |
99e300ef | 582 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 583 | { |
e06fcd75 | 584 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
585 | } |
586 | ||
c227f099 | 587 | static opc_handler_t invalid_handler = { |
70560da7 FC |
588 | .inval1 = 0xFFFFFFFF, |
589 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 590 | .type = PPC_NONE, |
a5858d7a | 591 | .type2 = PPC_NONE, |
79aceca5 FB |
592 | .handler = gen_invalid, |
593 | }; | |
594 | ||
e1571908 AJ |
595 | /*** Integer comparison ***/ |
596 | ||
636aa200 | 597 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 598 | { |
2fdcb629 RH |
599 | TCGv t0 = tcg_temp_new(); |
600 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 601 | |
da91a00f | 602 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 603 | |
2fdcb629 RH |
604 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
605 | tcg_gen_trunc_tl_i32(t1, t0); | |
606 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
607 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
608 | ||
609 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
610 | tcg_gen_trunc_tl_i32(t1, t0); | |
611 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
612 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
613 | ||
614 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
615 | tcg_gen_trunc_tl_i32(t1, t0); | |
616 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
617 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
618 | ||
619 | tcg_temp_free(t0); | |
620 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
621 | } |
622 | ||
636aa200 | 623 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 624 | { |
2fdcb629 | 625 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
626 | gen_op_cmp(arg0, t0, s, crf); |
627 | tcg_temp_free(t0); | |
e1571908 AJ |
628 | } |
629 | ||
630 | #if defined(TARGET_PPC64) | |
636aa200 | 631 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 632 | { |
ea363694 | 633 | TCGv t0, t1; |
2fdcb629 RH |
634 | t0 = tcg_temp_new(); |
635 | t1 = tcg_temp_new(); | |
e1571908 | 636 | if (s) { |
ea363694 AJ |
637 | tcg_gen_ext32s_tl(t0, arg0); |
638 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 639 | } else { |
ea363694 AJ |
640 | tcg_gen_ext32u_tl(t0, arg0); |
641 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 642 | } |
ea363694 AJ |
643 | gen_op_cmp(t0, t1, s, crf); |
644 | tcg_temp_free(t1); | |
645 | tcg_temp_free(t0); | |
e1571908 AJ |
646 | } |
647 | ||
636aa200 | 648 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 649 | { |
2fdcb629 | 650 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
651 | gen_op_cmp32(arg0, t0, s, crf); |
652 | tcg_temp_free(t0); | |
e1571908 AJ |
653 | } |
654 | #endif | |
655 | ||
636aa200 | 656 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 AJ |
657 | { |
658 | #if defined(TARGET_PPC64) | |
659 | if (!(ctx->sf_mode)) | |
660 | gen_op_cmpi32(reg, 0, 1, 0); | |
661 | else | |
662 | #endif | |
663 | gen_op_cmpi(reg, 0, 1, 0); | |
664 | } | |
665 | ||
666 | /* cmp */ | |
99e300ef | 667 | static void gen_cmp(DisasContext *ctx) |
e1571908 AJ |
668 | { |
669 | #if defined(TARGET_PPC64) | |
670 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
671 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
672 | 1, crfD(ctx->opcode)); | |
673 | else | |
674 | #endif | |
675 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
676 | 1, crfD(ctx->opcode)); | |
677 | } | |
678 | ||
679 | /* cmpi */ | |
99e300ef | 680 | static void gen_cmpi(DisasContext *ctx) |
e1571908 AJ |
681 | { |
682 | #if defined(TARGET_PPC64) | |
683 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
684 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
685 | 1, crfD(ctx->opcode)); | |
686 | else | |
687 | #endif | |
688 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
689 | 1, crfD(ctx->opcode)); | |
690 | } | |
691 | ||
692 | /* cmpl */ | |
99e300ef | 693 | static void gen_cmpl(DisasContext *ctx) |
e1571908 AJ |
694 | { |
695 | #if defined(TARGET_PPC64) | |
696 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
697 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
698 | 0, crfD(ctx->opcode)); | |
699 | else | |
700 | #endif | |
701 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
702 | 0, crfD(ctx->opcode)); | |
703 | } | |
704 | ||
705 | /* cmpli */ | |
99e300ef | 706 | static void gen_cmpli(DisasContext *ctx) |
e1571908 AJ |
707 | { |
708 | #if defined(TARGET_PPC64) | |
709 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
710 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
711 | 0, crfD(ctx->opcode)); | |
712 | else | |
713 | #endif | |
714 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
715 | 0, crfD(ctx->opcode)); | |
716 | } | |
717 | ||
718 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 719 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
720 | { |
721 | int l1, l2; | |
722 | uint32_t bi = rC(ctx->opcode); | |
723 | uint32_t mask; | |
a7812ae4 | 724 | TCGv_i32 t0; |
e1571908 AJ |
725 | |
726 | l1 = gen_new_label(); | |
727 | l2 = gen_new_label(); | |
728 | ||
729 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 730 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
731 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
732 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
733 | if (rA(ctx->opcode) == 0) |
734 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
735 | else | |
736 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
737 | tcg_gen_br(l2); | |
738 | gen_set_label(l1); | |
739 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
740 | gen_set_label(l2); | |
a7812ae4 | 741 | tcg_temp_free_i32(t0); |
e1571908 AJ |
742 | } |
743 | ||
79aceca5 | 744 | /*** Integer arithmetic ***/ |
79aceca5 | 745 | |
636aa200 BS |
746 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
747 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 748 | { |
ffe30937 | 749 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 750 | |
ffe30937 | 751 | tcg_gen_xor_tl(cpu_ov, arg0, arg1); |
74637406 | 752 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
753 | if (sub) { |
754 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
755 | } else { | |
756 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
757 | } | |
758 | tcg_temp_free(t0); | |
74637406 | 759 | #if defined(TARGET_PPC64) |
ffe30937 RH |
760 | if (!ctx->sf_mode) { |
761 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); | |
762 | } | |
74637406 | 763 | #endif |
ffe30937 RH |
764 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
765 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
766 | } |
767 | ||
74637406 | 768 | /* Common add function */ |
636aa200 | 769 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
770 | TCGv arg2, bool add_ca, bool compute_ca, |
771 | bool compute_ov, bool compute_rc0) | |
74637406 | 772 | { |
b5a73f8d | 773 | TCGv t0 = ret; |
d9bce9d9 | 774 | |
b5a73f8d RH |
775 | if (((compute_ca && add_ca) || compute_ov) |
776 | && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) { | |
146de60d | 777 | t0 = tcg_temp_new(); |
74637406 | 778 | } |
79aceca5 | 779 | |
da91a00f | 780 | if (compute_ca) { |
b5a73f8d RH |
781 | TCGv zero = tcg_const_tl(0); |
782 | if (add_ca) { | |
783 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
784 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
785 | } else { | |
786 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
787 | } | |
788 | tcg_temp_free(zero); | |
789 | } else { | |
790 | tcg_gen_add_tl(t0, arg1, arg2); | |
791 | if (add_ca) { | |
792 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
793 | } | |
da91a00f | 794 | } |
79aceca5 | 795 | |
74637406 AJ |
796 | if (compute_ov) { |
797 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
798 | } | |
b5a73f8d | 799 | if (unlikely(compute_rc0)) { |
74637406 | 800 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 801 | } |
74637406 | 802 | |
a7812ae4 | 803 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
804 | tcg_gen_mov_tl(ret, t0); |
805 | tcg_temp_free(t0); | |
806 | } | |
39dd32ee | 807 | } |
74637406 AJ |
808 | /* Add functions with two operands */ |
809 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 810 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
811 | { \ |
812 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
813 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 814 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
815 | } |
816 | /* Add functions with one operand and one immediate */ | |
817 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
818 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 819 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 820 | { \ |
b5a73f8d | 821 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
822 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
823 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 824 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
825 | tcg_temp_free(t0); \ |
826 | } | |
827 | ||
828 | /* add add. addo addo. */ | |
829 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
830 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
831 | /* addc addc. addco addco. */ | |
832 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
833 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
834 | /* adde adde. addeo addeo. */ | |
835 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
836 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
837 | /* addme addme. addmeo addmeo. */ | |
838 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
839 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
840 | /* addze addze. addzeo addzeo.*/ | |
841 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
842 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
843 | /* addi */ | |
99e300ef | 844 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 845 | { |
74637406 AJ |
846 | target_long simm = SIMM(ctx->opcode); |
847 | ||
848 | if (rA(ctx->opcode) == 0) { | |
849 | /* li case */ | |
850 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
851 | } else { | |
b5a73f8d RH |
852 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
853 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 854 | } |
d9bce9d9 | 855 | } |
74637406 | 856 | /* addic addic.*/ |
b5a73f8d | 857 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 858 | { |
b5a73f8d RH |
859 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
860 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
861 | c, 0, 1, 0, compute_rc0); | |
862 | tcg_temp_free(c); | |
d9bce9d9 | 863 | } |
99e300ef BS |
864 | |
865 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 866 | { |
b5a73f8d | 867 | gen_op_addic(ctx, 0); |
d9bce9d9 | 868 | } |
e8eaa2c0 BS |
869 | |
870 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 871 | { |
b5a73f8d | 872 | gen_op_addic(ctx, 1); |
d9bce9d9 | 873 | } |
99e300ef | 874 | |
54623277 | 875 | /* addis */ |
99e300ef | 876 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 877 | { |
74637406 AJ |
878 | target_long simm = SIMM(ctx->opcode); |
879 | ||
880 | if (rA(ctx->opcode) == 0) { | |
881 | /* lis case */ | |
882 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
883 | } else { | |
b5a73f8d RH |
884 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
885 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 886 | } |
d9bce9d9 | 887 | } |
74637406 | 888 | |
636aa200 BS |
889 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
890 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 891 | { |
2ef1b120 AJ |
892 | int l1 = gen_new_label(); |
893 | int l2 = gen_new_label(); | |
a7812ae4 PB |
894 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
895 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 896 | |
2ef1b120 AJ |
897 | tcg_gen_trunc_tl_i32(t0, arg1); |
898 | tcg_gen_trunc_tl_i32(t1, arg2); | |
899 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 900 | if (sign) { |
2ef1b120 AJ |
901 | int l3 = gen_new_label(); |
902 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
903 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 904 | gen_set_label(l3); |
2ef1b120 | 905 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 906 | } else { |
2ef1b120 | 907 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
908 | } |
909 | if (compute_ov) { | |
da91a00f | 910 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
911 | } |
912 | tcg_gen_br(l2); | |
913 | gen_set_label(l1); | |
914 | if (sign) { | |
2ef1b120 | 915 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
916 | } else { |
917 | tcg_gen_movi_i32(t0, 0); | |
918 | } | |
919 | if (compute_ov) { | |
da91a00f RH |
920 | tcg_gen_movi_tl(cpu_ov, 1); |
921 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
922 | } |
923 | gen_set_label(l2); | |
2ef1b120 | 924 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
925 | tcg_temp_free_i32(t0); |
926 | tcg_temp_free_i32(t1); | |
74637406 AJ |
927 | if (unlikely(Rc(ctx->opcode) != 0)) |
928 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 929 | } |
74637406 AJ |
930 | /* Div functions */ |
931 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 932 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
933 | { \ |
934 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
935 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
936 | sign, compute_ov); \ | |
937 | } | |
938 | /* divwu divwu. divwuo divwuo. */ | |
939 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
940 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
941 | /* divw divw. divwo divwo. */ | |
942 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
943 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
d9bce9d9 | 944 | #if defined(TARGET_PPC64) |
636aa200 BS |
945 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
946 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 947 | { |
2ef1b120 AJ |
948 | int l1 = gen_new_label(); |
949 | int l2 = gen_new_label(); | |
74637406 AJ |
950 | |
951 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
952 | if (sign) { | |
2ef1b120 | 953 | int l3 = gen_new_label(); |
74637406 AJ |
954 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
955 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
956 | gen_set_label(l3); | |
74637406 AJ |
957 | tcg_gen_div_i64(ret, arg1, arg2); |
958 | } else { | |
959 | tcg_gen_divu_i64(ret, arg1, arg2); | |
960 | } | |
961 | if (compute_ov) { | |
da91a00f | 962 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
963 | } |
964 | tcg_gen_br(l2); | |
965 | gen_set_label(l1); | |
966 | if (sign) { | |
967 | tcg_gen_sari_i64(ret, arg1, 63); | |
968 | } else { | |
969 | tcg_gen_movi_i64(ret, 0); | |
970 | } | |
971 | if (compute_ov) { | |
da91a00f RH |
972 | tcg_gen_movi_tl(cpu_ov, 1); |
973 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
974 | } |
975 | gen_set_label(l2); | |
976 | if (unlikely(Rc(ctx->opcode) != 0)) | |
977 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 978 | } |
74637406 | 979 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 980 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 981 | { \ |
2ef1b120 AJ |
982 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
983 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
984 | sign, compute_ov); \ | |
74637406 AJ |
985 | } |
986 | /* divwu divwu. divwuo divwuo. */ | |
987 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
988 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
989 | /* divw divw. divwo divwo. */ | |
990 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
991 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
d9bce9d9 | 992 | #endif |
74637406 AJ |
993 | |
994 | /* mulhw mulhw. */ | |
99e300ef | 995 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 996 | { |
23ad1d5d RH |
997 | TCGv_i32 t0 = tcg_temp_new_i32(); |
998 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 999 | |
23ad1d5d RH |
1000 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1001 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1002 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1003 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1004 | tcg_temp_free_i32(t0); | |
1005 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1006 | if (unlikely(Rc(ctx->opcode) != 0)) |
1007 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1008 | } |
99e300ef | 1009 | |
54623277 | 1010 | /* mulhwu mulhwu. */ |
99e300ef | 1011 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1012 | { |
23ad1d5d RH |
1013 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1014 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1015 | |
23ad1d5d RH |
1016 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1017 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1018 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1019 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1020 | tcg_temp_free_i32(t0); | |
1021 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1022 | if (unlikely(Rc(ctx->opcode) != 0)) |
1023 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1024 | } |
99e300ef | 1025 | |
54623277 | 1026 | /* mullw mullw. */ |
99e300ef | 1027 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1028 | { |
74637406 AJ |
1029 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1030 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1031 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
74637406 AJ |
1032 | if (unlikely(Rc(ctx->opcode) != 0)) |
1033 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1034 | } |
99e300ef | 1035 | |
54623277 | 1036 | /* mullwo mullwo. */ |
99e300ef | 1037 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1038 | { |
74637406 | 1039 | int l1; |
a7812ae4 | 1040 | TCGv_i64 t0, t1; |
74637406 | 1041 | |
a7812ae4 PB |
1042 | t0 = tcg_temp_new_i64(); |
1043 | t1 = tcg_temp_new_i64(); | |
74637406 AJ |
1044 | l1 = gen_new_label(); |
1045 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 1046 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
1047 | #if defined(TARGET_PPC64) |
1048 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1049 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1050 | #else | |
1051 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1052 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
d9bce9d9 | 1053 | #endif |
74637406 AJ |
1054 | tcg_gen_mul_i64(t0, t0, t1); |
1055 | #if defined(TARGET_PPC64) | |
1056 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1057 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); | |
1058 | #else | |
1059 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1060 | tcg_gen_ext32s_i64(t1, t0); | |
1061 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
1062 | #endif | |
da91a00f RH |
1063 | tcg_gen_movi_tl(cpu_ov, 1); |
1064 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 | 1065 | gen_set_label(l1); |
a7812ae4 PB |
1066 | tcg_temp_free_i64(t0); |
1067 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1068 | if (unlikely(Rc(ctx->opcode) != 0)) |
1069 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1070 | } |
99e300ef | 1071 | |
54623277 | 1072 | /* mulli */ |
99e300ef | 1073 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1074 | { |
74637406 AJ |
1075 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1076 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1077 | } |
23ad1d5d | 1078 | |
d9bce9d9 | 1079 | #if defined(TARGET_PPC64) |
74637406 | 1080 | /* mulhd mulhd. */ |
23ad1d5d RH |
1081 | static void gen_mulhd(DisasContext *ctx) |
1082 | { | |
1083 | TCGv lo = tcg_temp_new(); | |
1084 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1085 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1086 | tcg_temp_free(lo); | |
1087 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1088 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1089 | } | |
1090 | } | |
1091 | ||
74637406 | 1092 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1093 | static void gen_mulhdu(DisasContext *ctx) |
1094 | { | |
1095 | TCGv lo = tcg_temp_new(); | |
1096 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1097 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1098 | tcg_temp_free(lo); | |
1099 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1100 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1101 | } | |
1102 | } | |
99e300ef | 1103 | |
54623277 | 1104 | /* mulld mulld. */ |
99e300ef | 1105 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1106 | { |
74637406 AJ |
1107 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1108 | cpu_gpr[rB(ctx->opcode)]); | |
1109 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1110 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1111 | } |
d15f74fb | 1112 | |
74637406 | 1113 | /* mulldo mulldo. */ |
d15f74fb BS |
1114 | static void gen_mulldo(DisasContext *ctx) |
1115 | { | |
1116 | gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env, | |
1117 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1118 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1119 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1120 | } | |
1121 | } | |
d9bce9d9 | 1122 | #endif |
74637406 AJ |
1123 | |
1124 | /* neg neg. nego nego. */ | |
636aa200 BS |
1125 | static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1, |
1126 | int ov_check) | |
d9bce9d9 | 1127 | { |
ec6469a3 AJ |
1128 | int l1 = gen_new_label(); |
1129 | int l2 = gen_new_label(); | |
a7812ae4 | 1130 | TCGv t0 = tcg_temp_local_new(); |
d9bce9d9 | 1131 | #if defined(TARGET_PPC64) |
74637406 | 1132 | if (ctx->sf_mode) { |
741a7444 | 1133 | tcg_gen_mov_tl(t0, arg1); |
ec6469a3 AJ |
1134 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); |
1135 | } else | |
1136 | #endif | |
1137 | { | |
1138 | tcg_gen_ext32s_tl(t0, arg1); | |
74637406 AJ |
1139 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); |
1140 | } | |
74637406 AJ |
1141 | tcg_gen_neg_tl(ret, arg1); |
1142 | if (ov_check) { | |
da91a00f | 1143 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
1144 | } |
1145 | tcg_gen_br(l2); | |
1146 | gen_set_label(l1); | |
ec6469a3 | 1147 | tcg_gen_mov_tl(ret, t0); |
74637406 | 1148 | if (ov_check) { |
da91a00f RH |
1149 | tcg_gen_movi_tl(cpu_ov, 1); |
1150 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
1151 | } |
1152 | gen_set_label(l2); | |
ec6469a3 | 1153 | tcg_temp_free(t0); |
74637406 AJ |
1154 | if (unlikely(Rc(ctx->opcode) != 0)) |
1155 | gen_set_Rc0(ctx, ret); | |
1156 | } | |
99e300ef BS |
1157 | |
1158 | static void gen_neg(DisasContext *ctx) | |
d9bce9d9 | 1159 | { |
ec6469a3 | 1160 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
d9bce9d9 | 1161 | } |
99e300ef BS |
1162 | |
1163 | static void gen_nego(DisasContext *ctx) | |
79aceca5 | 1164 | { |
ec6469a3 | 1165 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
79aceca5 | 1166 | } |
74637406 AJ |
1167 | |
1168 | /* Common subf function */ | |
636aa200 | 1169 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1170 | TCGv arg2, bool add_ca, bool compute_ca, |
1171 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1172 | { |
b5a73f8d | 1173 | TCGv t0 = ret; |
79aceca5 | 1174 | |
b5a73f8d RH |
1175 | if (((add_ca && compute_ca) || compute_ov) |
1176 | && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) { | |
1177 | t0 = tcg_temp_new(); | |
da91a00f | 1178 | } |
74637406 AJ |
1179 | |
1180 | if (add_ca) { | |
b5a73f8d RH |
1181 | /* dest = ~arg1 + arg2 + ca = arg2 - arg1 + ca - 1. */ |
1182 | if (compute_ca) { | |
1183 | TCGv zero; | |
1184 | tcg_gen_subi_tl(cpu_ca, cpu_ca, 1); | |
1185 | zero = tcg_const_tl(0); | |
1186 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
1187 | tcg_gen_sub2_tl(t0, cpu_ca, t0, cpu_ca, arg1, zero); | |
1188 | tcg_temp_free(zero); | |
1189 | } else { | |
1190 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1191 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1192 | tcg_gen_subi_tl(t0, t0, 1); | |
1193 | } | |
79aceca5 | 1194 | } else { |
74637406 | 1195 | if (compute_ca) { |
b5a73f8d | 1196 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
74637406 | 1197 | } |
b5a73f8d | 1198 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1199 | } |
b5a73f8d | 1200 | |
74637406 AJ |
1201 | if (compute_ov) { |
1202 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1203 | } | |
b5a73f8d | 1204 | if (unlikely(compute_rc0)) { |
74637406 | 1205 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1206 | } |
74637406 | 1207 | |
a7812ae4 | 1208 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1209 | tcg_gen_mov_tl(ret, t0); |
1210 | tcg_temp_free(t0); | |
79aceca5 | 1211 | } |
79aceca5 | 1212 | } |
74637406 AJ |
1213 | /* Sub functions with Two operands functions */ |
1214 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1215 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1216 | { \ |
1217 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1218 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1219 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1220 | } |
1221 | /* Sub functions with one operand and one immediate */ | |
1222 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1223 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1224 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1225 | { \ |
b5a73f8d | 1226 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1227 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1228 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1229 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1230 | tcg_temp_free(t0); \ |
1231 | } | |
1232 | /* subf subf. subfo subfo. */ | |
1233 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1234 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1235 | /* subfc subfc. subfco subfco. */ | |
1236 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1237 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1238 | /* subfe subfe. subfeo subfo. */ | |
1239 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1240 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1241 | /* subfme subfme. subfmeo subfmeo. */ | |
1242 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1243 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1244 | /* subfze subfze. subfzeo subfzeo.*/ | |
1245 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1246 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1247 | |
54623277 | 1248 | /* subfic */ |
99e300ef | 1249 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1250 | { |
b5a73f8d RH |
1251 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1252 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1253 | c, 0, 1, 0, 0); | |
1254 | tcg_temp_free(c); | |
79aceca5 FB |
1255 | } |
1256 | ||
79aceca5 | 1257 | /*** Integer logical ***/ |
26d67362 | 1258 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1259 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1260 | { \ |
26d67362 AJ |
1261 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1262 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1263 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1264 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1265 | } |
79aceca5 | 1266 | |
26d67362 | 1267 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1268 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1269 | { \ |
26d67362 | 1270 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1271 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1272 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1273 | } |
1274 | ||
1275 | /* and & and. */ | |
26d67362 | 1276 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1277 | /* andc & andc. */ |
26d67362 | 1278 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1279 | |
54623277 | 1280 | /* andi. */ |
e8eaa2c0 | 1281 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1282 | { |
26d67362 AJ |
1283 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1284 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1285 | } |
e8eaa2c0 | 1286 | |
54623277 | 1287 | /* andis. */ |
e8eaa2c0 | 1288 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1289 | { |
26d67362 AJ |
1290 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1291 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1292 | } |
99e300ef | 1293 | |
54623277 | 1294 | /* cntlzw */ |
99e300ef | 1295 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1296 | { |
a7812ae4 | 1297 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1298 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1299 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1300 | } |
79aceca5 | 1301 | /* eqv & eqv. */ |
26d67362 | 1302 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1303 | /* extsb & extsb. */ |
26d67362 | 1304 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1305 | /* extsh & extsh. */ |
26d67362 | 1306 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1307 | /* nand & nand. */ |
26d67362 | 1308 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1309 | /* nor & nor. */ |
26d67362 | 1310 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1311 | |
54623277 | 1312 | /* or & or. */ |
99e300ef | 1313 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1314 | { |
76a66253 JM |
1315 | int rs, ra, rb; |
1316 | ||
1317 | rs = rS(ctx->opcode); | |
1318 | ra = rA(ctx->opcode); | |
1319 | rb = rB(ctx->opcode); | |
1320 | /* Optimisation for mr. ri case */ | |
1321 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1322 | if (rs != rb) |
1323 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1324 | else | |
1325 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1326 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1327 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1328 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1329 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1330 | #if defined(TARGET_PPC64) |
1331 | } else { | |
26d67362 AJ |
1332 | int prio = 0; |
1333 | ||
c80f84e3 JM |
1334 | switch (rs) { |
1335 | case 1: | |
1336 | /* Set process priority to low */ | |
26d67362 | 1337 | prio = 2; |
c80f84e3 JM |
1338 | break; |
1339 | case 6: | |
1340 | /* Set process priority to medium-low */ | |
26d67362 | 1341 | prio = 3; |
c80f84e3 JM |
1342 | break; |
1343 | case 2: | |
1344 | /* Set process priority to normal */ | |
26d67362 | 1345 | prio = 4; |
c80f84e3 | 1346 | break; |
be147d08 JM |
1347 | #if !defined(CONFIG_USER_ONLY) |
1348 | case 31: | |
76db3ba4 | 1349 | if (ctx->mem_idx > 0) { |
be147d08 | 1350 | /* Set process priority to very low */ |
26d67362 | 1351 | prio = 1; |
be147d08 JM |
1352 | } |
1353 | break; | |
1354 | case 5: | |
76db3ba4 | 1355 | if (ctx->mem_idx > 0) { |
be147d08 | 1356 | /* Set process priority to medium-hight */ |
26d67362 | 1357 | prio = 5; |
be147d08 JM |
1358 | } |
1359 | break; | |
1360 | case 3: | |
76db3ba4 | 1361 | if (ctx->mem_idx > 0) { |
be147d08 | 1362 | /* Set process priority to high */ |
26d67362 | 1363 | prio = 6; |
be147d08 JM |
1364 | } |
1365 | break; | |
be147d08 | 1366 | case 7: |
76db3ba4 | 1367 | if (ctx->mem_idx > 1) { |
be147d08 | 1368 | /* Set process priority to very high */ |
26d67362 | 1369 | prio = 7; |
be147d08 JM |
1370 | } |
1371 | break; | |
be147d08 | 1372 | #endif |
c80f84e3 JM |
1373 | default: |
1374 | /* nop */ | |
1375 | break; | |
1376 | } | |
26d67362 | 1377 | if (prio) { |
a7812ae4 | 1378 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1379 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1380 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1381 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1382 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1383 | tcg_temp_free(t0); |
26d67362 | 1384 | } |
c80f84e3 | 1385 | #endif |
9a64fbe4 | 1386 | } |
9a64fbe4 | 1387 | } |
79aceca5 | 1388 | /* orc & orc. */ |
26d67362 | 1389 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1390 | |
54623277 | 1391 | /* xor & xor. */ |
99e300ef | 1392 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1393 | { |
9a64fbe4 | 1394 | /* Optimisation for "set to zero" case */ |
26d67362 | 1395 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1396 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1397 | else |
1398 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1399 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1400 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1401 | } |
99e300ef | 1402 | |
54623277 | 1403 | /* ori */ |
99e300ef | 1404 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1405 | { |
76a66253 | 1406 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1407 | |
9a64fbe4 FB |
1408 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1409 | /* NOP */ | |
76a66253 | 1410 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1411 | return; |
76a66253 | 1412 | } |
26d67362 | 1413 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1414 | } |
99e300ef | 1415 | |
54623277 | 1416 | /* oris */ |
99e300ef | 1417 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1418 | { |
76a66253 | 1419 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1420 | |
9a64fbe4 FB |
1421 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1422 | /* NOP */ | |
1423 | return; | |
76a66253 | 1424 | } |
26d67362 | 1425 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1426 | } |
99e300ef | 1427 | |
54623277 | 1428 | /* xori */ |
99e300ef | 1429 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1430 | { |
76a66253 | 1431 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1432 | |
1433 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1434 | /* NOP */ | |
1435 | return; | |
1436 | } | |
26d67362 | 1437 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1438 | } |
99e300ef | 1439 | |
54623277 | 1440 | /* xoris */ |
99e300ef | 1441 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1442 | { |
76a66253 | 1443 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1444 | |
1445 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1446 | /* NOP */ | |
1447 | return; | |
1448 | } | |
26d67362 | 1449 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1450 | } |
99e300ef | 1451 | |
54623277 | 1452 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1453 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1454 | { |
eaabeef2 DG |
1455 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1456 | } | |
1457 | ||
1458 | static void gen_popcntw(DisasContext *ctx) | |
1459 | { | |
1460 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1461 | } | |
1462 | ||
d9bce9d9 | 1463 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1464 | /* popcntd: PowerPC 2.06 specification */ |
1465 | static void gen_popcntd(DisasContext *ctx) | |
1466 | { | |
1467 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1468 | } |
eaabeef2 | 1469 | #endif |
d9bce9d9 JM |
1470 | |
1471 | #if defined(TARGET_PPC64) | |
1472 | /* extsw & extsw. */ | |
26d67362 | 1473 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1474 | |
54623277 | 1475 | /* cntlzd */ |
99e300ef | 1476 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1477 | { |
a7812ae4 | 1478 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1479 | if (unlikely(Rc(ctx->opcode) != 0)) |
1480 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1481 | } | |
d9bce9d9 JM |
1482 | #endif |
1483 | ||
79aceca5 | 1484 | /*** Integer rotate ***/ |
99e300ef | 1485 | |
54623277 | 1486 | /* rlwimi & rlwimi. */ |
99e300ef | 1487 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1488 | { |
76a66253 | 1489 | uint32_t mb, me, sh; |
79aceca5 FB |
1490 | |
1491 | mb = MB(ctx->opcode); | |
1492 | me = ME(ctx->opcode); | |
76a66253 | 1493 | sh = SH(ctx->opcode); |
d03ef511 AJ |
1494 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1495 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1496 | } else { | |
d03ef511 | 1497 | target_ulong mask; |
a7812ae4 PB |
1498 | TCGv t1; |
1499 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1500 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1501 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1502 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1503 | tcg_gen_rotli_i32(t2, t2, sh); | |
1504 | tcg_gen_extu_i32_i64(t0, t2); | |
1505 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1506 | #else |
1507 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1508 | #endif | |
76a66253 | 1509 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1510 | mb += 32; |
1511 | me += 32; | |
76a66253 | 1512 | #endif |
d03ef511 | 1513 | mask = MASK(mb, me); |
a7812ae4 | 1514 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1515 | tcg_gen_andi_tl(t0, t0, mask); |
1516 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1517 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1518 | tcg_temp_free(t0); | |
1519 | tcg_temp_free(t1); | |
1520 | } | |
76a66253 | 1521 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1522 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1523 | } |
99e300ef | 1524 | |
54623277 | 1525 | /* rlwinm & rlwinm. */ |
99e300ef | 1526 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1527 | { |
1528 | uint32_t mb, me, sh; | |
3b46e624 | 1529 | |
79aceca5 FB |
1530 | sh = SH(ctx->opcode); |
1531 | mb = MB(ctx->opcode); | |
1532 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1533 | |
1534 | if (likely(mb == 0 && me == (31 - sh))) { | |
1535 | if (likely(sh == 0)) { | |
1536 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1537 | } else { | |
a7812ae4 | 1538 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1539 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1540 | tcg_gen_shli_tl(t0, t0, sh); | |
1541 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1542 | tcg_temp_free(t0); | |
79aceca5 | 1543 | } |
d03ef511 | 1544 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1545 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1546 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1547 | tcg_gen_shri_tl(t0, t0, mb); | |
1548 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1549 | tcg_temp_free(t0); | |
1550 | } else { | |
a7812ae4 | 1551 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1552 | #if defined(TARGET_PPC64) |
a7812ae4 | 1553 | TCGv_i32 t1 = tcg_temp_new_i32(); |
54843a58 AJ |
1554 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1555 | tcg_gen_rotli_i32(t1, t1, sh); | |
1556 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 | 1557 | tcg_temp_free_i32(t1); |
54843a58 AJ |
1558 | #else |
1559 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1560 | #endif | |
76a66253 | 1561 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1562 | mb += 32; |
1563 | me += 32; | |
76a66253 | 1564 | #endif |
d03ef511 AJ |
1565 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1566 | tcg_temp_free(t0); | |
1567 | } | |
76a66253 | 1568 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1569 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1570 | } |
99e300ef | 1571 | |
54623277 | 1572 | /* rlwnm & rlwnm. */ |
99e300ef | 1573 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1574 | { |
1575 | uint32_t mb, me; | |
54843a58 AJ |
1576 | TCGv t0; |
1577 | #if defined(TARGET_PPC64) | |
a7812ae4 | 1578 | TCGv_i32 t1, t2; |
54843a58 | 1579 | #endif |
79aceca5 FB |
1580 | |
1581 | mb = MB(ctx->opcode); | |
1582 | me = ME(ctx->opcode); | |
a7812ae4 | 1583 | t0 = tcg_temp_new(); |
d03ef511 | 1584 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1585 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1586 | t1 = tcg_temp_new_i32(); |
1587 | t2 = tcg_temp_new_i32(); | |
54843a58 AJ |
1588 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1589 | tcg_gen_trunc_i64_i32(t2, t0); | |
1590 | tcg_gen_rotl_i32(t1, t1, t2); | |
1591 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 PB |
1592 | tcg_temp_free_i32(t1); |
1593 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1594 | #else |
1595 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1596 | #endif | |
76a66253 JM |
1597 | if (unlikely(mb != 0 || me != 31)) { |
1598 | #if defined(TARGET_PPC64) | |
1599 | mb += 32; | |
1600 | me += 32; | |
1601 | #endif | |
54843a58 | 1602 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1603 | } else { |
54843a58 | 1604 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1605 | } |
54843a58 | 1606 | tcg_temp_free(t0); |
76a66253 | 1607 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1608 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1609 | } |
1610 | ||
d9bce9d9 JM |
1611 | #if defined(TARGET_PPC64) |
1612 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1613 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1614 | { \ |
1615 | gen_##name(ctx, 0); \ | |
1616 | } \ | |
e8eaa2c0 BS |
1617 | \ |
1618 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1619 | { \ |
1620 | gen_##name(ctx, 1); \ | |
1621 | } | |
1622 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1623 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1624 | { \ |
1625 | gen_##name(ctx, 0, 0); \ | |
1626 | } \ | |
e8eaa2c0 BS |
1627 | \ |
1628 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1629 | { \ |
1630 | gen_##name(ctx, 0, 1); \ | |
1631 | } \ | |
e8eaa2c0 BS |
1632 | \ |
1633 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1634 | { \ |
1635 | gen_##name(ctx, 1, 0); \ | |
1636 | } \ | |
e8eaa2c0 BS |
1637 | \ |
1638 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1639 | { \ |
1640 | gen_##name(ctx, 1, 1); \ | |
1641 | } | |
51789c41 | 1642 | |
636aa200 BS |
1643 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1644 | uint32_t sh) | |
51789c41 | 1645 | { |
d03ef511 AJ |
1646 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1647 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1648 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1649 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1650 | } else { | |
a7812ae4 | 1651 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1652 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1653 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1654 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1655 | } else { |
1656 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1657 | } |
d03ef511 | 1658 | tcg_temp_free(t0); |
51789c41 | 1659 | } |
51789c41 | 1660 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1661 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1662 | } |
d9bce9d9 | 1663 | /* rldicl - rldicl. */ |
636aa200 | 1664 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1665 | { |
51789c41 | 1666 | uint32_t sh, mb; |
d9bce9d9 | 1667 | |
9d53c753 JM |
1668 | sh = SH(ctx->opcode) | (shn << 5); |
1669 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1670 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1671 | } |
51789c41 | 1672 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1673 | /* rldicr - rldicr. */ |
636aa200 | 1674 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1675 | { |
51789c41 | 1676 | uint32_t sh, me; |
d9bce9d9 | 1677 | |
9d53c753 JM |
1678 | sh = SH(ctx->opcode) | (shn << 5); |
1679 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1680 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1681 | } |
51789c41 | 1682 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1683 | /* rldic - rldic. */ |
636aa200 | 1684 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1685 | { |
51789c41 | 1686 | uint32_t sh, mb; |
d9bce9d9 | 1687 | |
9d53c753 JM |
1688 | sh = SH(ctx->opcode) | (shn << 5); |
1689 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1690 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1691 | } | |
1692 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1693 | ||
636aa200 | 1694 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1695 | { |
54843a58 | 1696 | TCGv t0; |
d03ef511 AJ |
1697 | |
1698 | mb = MB(ctx->opcode); | |
1699 | me = ME(ctx->opcode); | |
a7812ae4 | 1700 | t0 = tcg_temp_new(); |
d03ef511 | 1701 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1702 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1703 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1704 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1705 | } else { | |
1706 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1707 | } | |
1708 | tcg_temp_free(t0); | |
51789c41 | 1709 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1710 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1711 | } |
51789c41 | 1712 | |
d9bce9d9 | 1713 | /* rldcl - rldcl. */ |
636aa200 | 1714 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1715 | { |
51789c41 | 1716 | uint32_t mb; |
d9bce9d9 | 1717 | |
9d53c753 | 1718 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1719 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1720 | } |
36081602 | 1721 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1722 | /* rldcr - rldcr. */ |
636aa200 | 1723 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1724 | { |
51789c41 | 1725 | uint32_t me; |
d9bce9d9 | 1726 | |
9d53c753 | 1727 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1728 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1729 | } |
36081602 | 1730 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1731 | /* rldimi - rldimi. */ |
636aa200 | 1732 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1733 | { |
271a916e | 1734 | uint32_t sh, mb, me; |
d9bce9d9 | 1735 | |
9d53c753 JM |
1736 | sh = SH(ctx->opcode) | (shn << 5); |
1737 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1738 | me = 63 - sh; |
d03ef511 AJ |
1739 | if (unlikely(sh == 0 && mb == 0)) { |
1740 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1741 | } else { | |
1742 | TCGv t0, t1; | |
1743 | target_ulong mask; | |
1744 | ||
a7812ae4 | 1745 | t0 = tcg_temp_new(); |
54843a58 | 1746 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1747 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1748 | mask = MASK(mb, me); |
1749 | tcg_gen_andi_tl(t0, t0, mask); | |
1750 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1751 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1752 | tcg_temp_free(t0); | |
1753 | tcg_temp_free(t1); | |
51789c41 | 1754 | } |
51789c41 | 1755 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1756 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1757 | } |
36081602 | 1758 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1759 | #endif |
1760 | ||
79aceca5 | 1761 | /*** Integer shift ***/ |
99e300ef | 1762 | |
54623277 | 1763 | /* slw & slw. */ |
99e300ef | 1764 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1765 | { |
7fd6bf7d | 1766 | TCGv t0, t1; |
26d67362 | 1767 | |
7fd6bf7d AJ |
1768 | t0 = tcg_temp_new(); |
1769 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1770 | #if defined(TARGET_PPC64) | |
1771 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1772 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1773 | #else | |
1774 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1775 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1776 | #endif | |
1777 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1778 | t1 = tcg_temp_new(); | |
1779 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1780 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1781 | tcg_temp_free(t1); | |
fea0c503 | 1782 | tcg_temp_free(t0); |
7fd6bf7d | 1783 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1784 | if (unlikely(Rc(ctx->opcode) != 0)) |
1785 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1786 | } | |
99e300ef | 1787 | |
54623277 | 1788 | /* sraw & sraw. */ |
99e300ef | 1789 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1790 | { |
d15f74fb | 1791 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1792 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1793 | if (unlikely(Rc(ctx->opcode) != 0)) |
1794 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1795 | } | |
99e300ef | 1796 | |
54623277 | 1797 | /* srawi & srawi. */ |
99e300ef | 1798 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1799 | { |
26d67362 AJ |
1800 | int sh = SH(ctx->opcode); |
1801 | if (sh != 0) { | |
1802 | int l1, l2; | |
fea0c503 | 1803 | TCGv t0; |
26d67362 AJ |
1804 | l1 = gen_new_label(); |
1805 | l2 = gen_new_label(); | |
a7812ae4 | 1806 | t0 = tcg_temp_local_new(); |
fea0c503 AJ |
1807 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1808 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
1809 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); | |
1810 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
da91a00f | 1811 | tcg_gen_movi_tl(cpu_ca, 1); |
26d67362 AJ |
1812 | tcg_gen_br(l2); |
1813 | gen_set_label(l1); | |
da91a00f | 1814 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1815 | gen_set_label(l2); |
fea0c503 AJ |
1816 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1817 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); | |
1818 | tcg_temp_free(t0); | |
26d67362 AJ |
1819 | } else { |
1820 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
da91a00f | 1821 | tcg_gen_movi_tl(cpu_ca, 0); |
d9bce9d9 | 1822 | } |
76a66253 | 1823 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1824 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1825 | } |
99e300ef | 1826 | |
54623277 | 1827 | /* srw & srw. */ |
99e300ef | 1828 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1829 | { |
fea0c503 | 1830 | TCGv t0, t1; |
d9bce9d9 | 1831 | |
7fd6bf7d AJ |
1832 | t0 = tcg_temp_new(); |
1833 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1834 | #if defined(TARGET_PPC64) | |
1835 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1836 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1837 | #else | |
1838 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1839 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1840 | #endif | |
1841 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1842 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1843 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1844 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1845 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1846 | tcg_temp_free(t1); |
fea0c503 | 1847 | tcg_temp_free(t0); |
26d67362 AJ |
1848 | if (unlikely(Rc(ctx->opcode) != 0)) |
1849 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1850 | } | |
54623277 | 1851 | |
d9bce9d9 JM |
1852 | #if defined(TARGET_PPC64) |
1853 | /* sld & sld. */ | |
99e300ef | 1854 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1855 | { |
7fd6bf7d | 1856 | TCGv t0, t1; |
26d67362 | 1857 | |
7fd6bf7d AJ |
1858 | t0 = tcg_temp_new(); |
1859 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1860 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1861 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1862 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1863 | t1 = tcg_temp_new(); | |
1864 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1865 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1866 | tcg_temp_free(t1); | |
fea0c503 | 1867 | tcg_temp_free(t0); |
26d67362 AJ |
1868 | if (unlikely(Rc(ctx->opcode) != 0)) |
1869 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1870 | } | |
99e300ef | 1871 | |
54623277 | 1872 | /* srad & srad. */ |
99e300ef | 1873 | static void gen_srad(DisasContext *ctx) |
26d67362 | 1874 | { |
d15f74fb | 1875 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1876 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1877 | if (unlikely(Rc(ctx->opcode) != 0)) |
1878 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1879 | } | |
d9bce9d9 | 1880 | /* sradi & sradi. */ |
636aa200 | 1881 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 1882 | { |
26d67362 | 1883 | int sh = SH(ctx->opcode) + (n << 5); |
d9bce9d9 | 1884 | if (sh != 0) { |
26d67362 | 1885 | int l1, l2; |
fea0c503 | 1886 | TCGv t0; |
26d67362 AJ |
1887 | l1 = gen_new_label(); |
1888 | l2 = gen_new_label(); | |
a7812ae4 | 1889 | t0 = tcg_temp_local_new(); |
26d67362 | 1890 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); |
fea0c503 AJ |
1891 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1892 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
da91a00f | 1893 | tcg_gen_movi_tl(cpu_ca, 1); |
26d67362 AJ |
1894 | tcg_gen_br(l2); |
1895 | gen_set_label(l1); | |
da91a00f | 1896 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1897 | gen_set_label(l2); |
a9730017 | 1898 | tcg_temp_free(t0); |
26d67362 AJ |
1899 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1900 | } else { | |
1901 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
da91a00f | 1902 | tcg_gen_movi_tl(cpu_ca, 0); |
d9bce9d9 | 1903 | } |
d9bce9d9 | 1904 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1905 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1906 | } |
e8eaa2c0 BS |
1907 | |
1908 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
1909 | { |
1910 | gen_sradi(ctx, 0); | |
1911 | } | |
e8eaa2c0 BS |
1912 | |
1913 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
1914 | { |
1915 | gen_sradi(ctx, 1); | |
1916 | } | |
99e300ef | 1917 | |
54623277 | 1918 | /* srd & srd. */ |
99e300ef | 1919 | static void gen_srd(DisasContext *ctx) |
26d67362 | 1920 | { |
7fd6bf7d | 1921 | TCGv t0, t1; |
26d67362 | 1922 | |
7fd6bf7d AJ |
1923 | t0 = tcg_temp_new(); |
1924 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1925 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1926 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1927 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1928 | t1 = tcg_temp_new(); | |
1929 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1930 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1931 | tcg_temp_free(t1); | |
fea0c503 | 1932 | tcg_temp_free(t0); |
26d67362 AJ |
1933 | if (unlikely(Rc(ctx->opcode) != 0)) |
1934 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1935 | } | |
d9bce9d9 | 1936 | #endif |
79aceca5 FB |
1937 | |
1938 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 1939 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 1940 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1941 | { \ |
76a66253 | 1942 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1943 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1944 | return; \ |
1945 | } \ | |
eb44b959 AJ |
1946 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
1947 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 1948 | gen_reset_fpstatus(); \ |
8e703949 BS |
1949 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1950 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 1951 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 1952 | if (isfloat) { \ |
8e703949 BS |
1953 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1954 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 1955 | } \ |
af12906f AJ |
1956 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
1957 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
1958 | } |
1959 | ||
7c58044c JM |
1960 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
1961 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
1962 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 1963 | |
7c58044c | 1964 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 1965 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1966 | { \ |
76a66253 | 1967 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1968 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1969 | return; \ |
1970 | } \ | |
eb44b959 AJ |
1971 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
1972 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 1973 | gen_reset_fpstatus(); \ |
8e703949 BS |
1974 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1975 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 1976 | cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 1977 | if (isfloat) { \ |
8e703949 BS |
1978 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1979 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 1980 | } \ |
af12906f AJ |
1981 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
1982 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 1983 | } |
7c58044c JM |
1984 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
1985 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
1986 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 1987 | |
7c58044c | 1988 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 1989 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1990 | { \ |
76a66253 | 1991 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1992 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1993 | return; \ |
1994 | } \ | |
eb44b959 AJ |
1995 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
1996 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 1997 | gen_reset_fpstatus(); \ |
8e703949 BS |
1998 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
1999 | cpu_fpr[rA(ctx->opcode)], \ | |
2000 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2001 | if (isfloat) { \ |
8e703949 BS |
2002 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2003 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2004 | } \ |
af12906f AJ |
2005 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2006 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2007 | } |
7c58044c JM |
2008 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2009 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2010 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2011 | |
7c58044c | 2012 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 2013 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2014 | { \ |
76a66253 | 2015 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2016 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2017 | return; \ |
2018 | } \ | |
eb44b959 AJ |
2019 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2020 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2021 | gen_reset_fpstatus(); \ |
8e703949 BS |
2022 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2023 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2024 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2025 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2026 | } |
2027 | ||
7c58044c | 2028 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2029 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2030 | { \ |
76a66253 | 2031 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2032 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2033 | return; \ |
2034 | } \ | |
eb44b959 AJ |
2035 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2036 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2037 | gen_reset_fpstatus(); \ |
8e703949 BS |
2038 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2039 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2040 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2041 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2042 | } |
2043 | ||
9a64fbe4 | 2044 | /* fadd - fadds */ |
7c58044c | 2045 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2046 | /* fdiv - fdivs */ |
7c58044c | 2047 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2048 | /* fmul - fmuls */ |
7c58044c | 2049 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2050 | |
d7e4b87e | 2051 | /* fre */ |
7c58044c | 2052 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2053 | |
a750fc0b | 2054 | /* fres */ |
7c58044c | 2055 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2056 | |
a750fc0b | 2057 | /* frsqrte */ |
7c58044c JM |
2058 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2059 | ||
2060 | /* frsqrtes */ | |
99e300ef | 2061 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2062 | { |
af12906f | 2063 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2064 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2065 | return; |
2066 | } | |
eb44b959 AJ |
2067 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2068 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f | 2069 | gen_reset_fpstatus(); |
8e703949 BS |
2070 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2071 | cpu_fpr[rB(ctx->opcode)]); | |
2072 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2073 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2074 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
7c58044c | 2075 | } |
79aceca5 | 2076 | |
a750fc0b | 2077 | /* fsel */ |
7c58044c | 2078 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2079 | /* fsub - fsubs */ |
7c58044c | 2080 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2081 | /* Optional: */ |
99e300ef | 2082 | |
54623277 | 2083 | /* fsqrt */ |
99e300ef | 2084 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2085 | { |
76a66253 | 2086 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2087 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2088 | return; |
2089 | } | |
eb44b959 AJ |
2090 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2091 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2092 | gen_reset_fpstatus(); |
8e703949 BS |
2093 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2094 | cpu_fpr[rB(ctx->opcode)]); | |
af12906f | 2095 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
c7d344af | 2096 | } |
79aceca5 | 2097 | |
99e300ef | 2098 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2099 | { |
76a66253 | 2100 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2101 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2102 | return; |
2103 | } | |
eb44b959 AJ |
2104 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2105 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2106 | gen_reset_fpstatus(); |
8e703949 BS |
2107 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2108 | cpu_fpr[rB(ctx->opcode)]); | |
2109 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2110 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2111 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2112 | } |
2113 | ||
2114 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2115 | /* fmadd - fmadds */ |
7c58044c | 2116 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2117 | /* fmsub - fmsubs */ |
7c58044c | 2118 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2119 | /* fnmadd - fnmadds */ |
7c58044c | 2120 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2121 | /* fnmsub - fnmsubs */ |
7c58044c | 2122 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2123 | |
2124 | /*** Floating-Point round & convert ***/ | |
2125 | /* fctiw */ | |
7c58044c | 2126 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2127 | /* fctiwz */ |
7c58044c | 2128 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2129 | /* frsp */ |
7c58044c | 2130 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2131 | #if defined(TARGET_PPC64) |
2132 | /* fcfid */ | |
7c58044c | 2133 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
426613db | 2134 | /* fctid */ |
7c58044c | 2135 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
426613db | 2136 | /* fctidz */ |
7c58044c | 2137 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
426613db | 2138 | #endif |
79aceca5 | 2139 | |
d7e4b87e | 2140 | /* frin */ |
7c58044c | 2141 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2142 | /* friz */ |
7c58044c | 2143 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2144 | /* frip */ |
7c58044c | 2145 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2146 | /* frim */ |
7c58044c | 2147 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2148 | |
79aceca5 | 2149 | /*** Floating-Point compare ***/ |
99e300ef | 2150 | |
54623277 | 2151 | /* fcmpo */ |
99e300ef | 2152 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2153 | { |
330c483b | 2154 | TCGv_i32 crf; |
76a66253 | 2155 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2156 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2157 | return; |
2158 | } | |
eb44b959 AJ |
2159 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2160 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2161 | gen_reset_fpstatus(); |
9a819377 | 2162 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2163 | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2164 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2165 | tcg_temp_free_i32(crf); |
8e703949 | 2166 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2167 | } |
2168 | ||
2169 | /* fcmpu */ | |
99e300ef | 2170 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2171 | { |
330c483b | 2172 | TCGv_i32 crf; |
76a66253 | 2173 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2174 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2175 | return; |
2176 | } | |
eb44b959 AJ |
2177 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2178 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2179 | gen_reset_fpstatus(); |
9a819377 | 2180 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2181 | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2182 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2183 | tcg_temp_free_i32(crf); |
8e703949 | 2184 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2185 | } |
2186 | ||
9a64fbe4 FB |
2187 | /*** Floating-point move ***/ |
2188 | /* fabs */ | |
7c58044c JM |
2189 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
2190 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); | |
9a64fbe4 FB |
2191 | |
2192 | /* fmr - fmr. */ | |
7c58044c | 2193 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2194 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2195 | { |
76a66253 | 2196 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2197 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2198 | return; |
2199 | } | |
af12906f AJ |
2200 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2201 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2202 | } |
2203 | ||
2204 | /* fnabs */ | |
7c58044c JM |
2205 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
2206 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); | |
9a64fbe4 | 2207 | /* fneg */ |
7c58044c JM |
2208 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
2209 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); | |
9a64fbe4 | 2210 | |
79aceca5 | 2211 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2212 | |
54623277 | 2213 | /* mcrfs */ |
99e300ef | 2214 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2215 | { |
30304420 | 2216 | TCGv tmp = tcg_temp_new(); |
7c58044c JM |
2217 | int bfa; |
2218 | ||
76a66253 | 2219 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2220 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2221 | return; |
2222 | } | |
7c58044c | 2223 | bfa = 4 * (7 - crfS(ctx->opcode)); |
30304420 DG |
2224 | tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); |
2225 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); | |
2226 | tcg_temp_free(tmp); | |
e1571908 | 2227 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
30304420 | 2228 | tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2229 | } |
2230 | ||
2231 | /* mffs */ | |
99e300ef | 2232 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2233 | { |
76a66253 | 2234 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2235 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2236 | return; |
2237 | } | |
7c58044c | 2238 | gen_reset_fpstatus(); |
30304420 | 2239 | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
af12906f | 2240 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2241 | } |
2242 | ||
2243 | /* mtfsb0 */ | |
99e300ef | 2244 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2245 | { |
fb0eaffc | 2246 | uint8_t crb; |
3b46e624 | 2247 | |
76a66253 | 2248 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2249 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2250 | return; |
2251 | } | |
6e35d524 | 2252 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2253 | gen_reset_fpstatus(); |
6e35d524 | 2254 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2255 | TCGv_i32 t0; |
2256 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2257 | gen_update_nip(ctx, ctx->nip - 4); | |
2258 | t0 = tcg_const_i32(crb); | |
8e703949 | 2259 | gen_helper_fpscr_clrbit(cpu_env, t0); |
6e35d524 AJ |
2260 | tcg_temp_free_i32(t0); |
2261 | } | |
7c58044c | 2262 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2263 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2264 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c | 2265 | } |
79aceca5 FB |
2266 | } |
2267 | ||
2268 | /* mtfsb1 */ | |
99e300ef | 2269 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2270 | { |
fb0eaffc | 2271 | uint8_t crb; |
3b46e624 | 2272 | |
76a66253 | 2273 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2274 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2275 | return; |
2276 | } | |
6e35d524 | 2277 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2278 | gen_reset_fpstatus(); |
2279 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2280 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2281 | TCGv_i32 t0; |
2282 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2283 | gen_update_nip(ctx, ctx->nip - 4); | |
2284 | t0 = tcg_const_i32(crb); | |
8e703949 | 2285 | gen_helper_fpscr_setbit(cpu_env, t0); |
0f2f39c2 | 2286 | tcg_temp_free_i32(t0); |
af12906f | 2287 | } |
7c58044c | 2288 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2289 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2290 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2291 | } |
2292 | /* We can raise a differed exception */ | |
8e703949 | 2293 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2294 | } |
2295 | ||
2296 | /* mtfsf */ | |
99e300ef | 2297 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2298 | { |
0f2f39c2 | 2299 | TCGv_i32 t0; |
4911012d | 2300 | int L = ctx->opcode & 0x02000000; |
af12906f | 2301 | |
76a66253 | 2302 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2303 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2304 | return; |
2305 | } | |
eb44b959 AJ |
2306 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2307 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2308 | gen_reset_fpstatus(); |
4911012d BS |
2309 | if (L) |
2310 | t0 = tcg_const_i32(0xff); | |
2311 | else | |
2312 | t0 = tcg_const_i32(FM(ctx->opcode)); | |
8e703949 | 2313 | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2314 | tcg_temp_free_i32(t0); |
7c58044c | 2315 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2316 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2317 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2318 | } |
2319 | /* We can raise a differed exception */ | |
8e703949 | 2320 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2321 | } |
2322 | ||
2323 | /* mtfsfi */ | |
99e300ef | 2324 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2325 | { |
7c58044c | 2326 | int bf, sh; |
0f2f39c2 AJ |
2327 | TCGv_i64 t0; |
2328 | TCGv_i32 t1; | |
7c58044c | 2329 | |
76a66253 | 2330 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2331 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2332 | return; |
2333 | } | |
7c58044c JM |
2334 | bf = crbD(ctx->opcode) >> 2; |
2335 | sh = 7 - bf; | |
eb44b959 AJ |
2336 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2337 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2338 | gen_reset_fpstatus(); |
0f2f39c2 | 2339 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); |
af12906f | 2340 | t1 = tcg_const_i32(1 << sh); |
8e703949 | 2341 | gen_helper_store_fpscr(cpu_env, t0, t1); |
0f2f39c2 AJ |
2342 | tcg_temp_free_i64(t0); |
2343 | tcg_temp_free_i32(t1); | |
7c58044c | 2344 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2345 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2346 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2347 | } |
2348 | /* We can raise a differed exception */ | |
8e703949 | 2349 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2350 | } |
2351 | ||
76a66253 JM |
2352 | /*** Addressing modes ***/ |
2353 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2354 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2355 | target_long maskl) | |
76a66253 JM |
2356 | { |
2357 | target_long simm = SIMM(ctx->opcode); | |
2358 | ||
be147d08 | 2359 | simm &= ~maskl; |
76db3ba4 AJ |
2360 | if (rA(ctx->opcode) == 0) { |
2361 | #if defined(TARGET_PPC64) | |
2362 | if (!ctx->sf_mode) { | |
2363 | tcg_gen_movi_tl(EA, (uint32_t)simm); | |
2364 | } else | |
2365 | #endif | |
e2be8d8d | 2366 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2367 | } else if (likely(simm != 0)) { |
e2be8d8d | 2368 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
76db3ba4 AJ |
2369 | #if defined(TARGET_PPC64) |
2370 | if (!ctx->sf_mode) { | |
2371 | tcg_gen_ext32u_tl(EA, EA); | |
2372 | } | |
2373 | #endif | |
2374 | } else { | |
2375 | #if defined(TARGET_PPC64) | |
2376 | if (!ctx->sf_mode) { | |
2377 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2378 | } else | |
2379 | #endif | |
e2be8d8d | 2380 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 | 2381 | } |
76a66253 JM |
2382 | } |
2383 | ||
636aa200 | 2384 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2385 | { |
76db3ba4 AJ |
2386 | if (rA(ctx->opcode) == 0) { |
2387 | #if defined(TARGET_PPC64) | |
2388 | if (!ctx->sf_mode) { | |
2389 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2390 | } else | |
2391 | #endif | |
e2be8d8d | 2392 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 | 2393 | } else { |
e2be8d8d | 2394 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 AJ |
2395 | #if defined(TARGET_PPC64) |
2396 | if (!ctx->sf_mode) { | |
2397 | tcg_gen_ext32u_tl(EA, EA); | |
2398 | } | |
2399 | #endif | |
2400 | } | |
76a66253 JM |
2401 | } |
2402 | ||
636aa200 | 2403 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2404 | { |
76db3ba4 | 2405 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2406 | tcg_gen_movi_tl(EA, 0); |
76db3ba4 AJ |
2407 | } else { |
2408 | #if defined(TARGET_PPC64) | |
2409 | if (!ctx->sf_mode) { | |
2410 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2411 | } else | |
2412 | #endif | |
2413 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2414 | } | |
2415 | } | |
2416 | ||
636aa200 BS |
2417 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2418 | target_long val) | |
76db3ba4 AJ |
2419 | { |
2420 | tcg_gen_addi_tl(ret, arg1, val); | |
2421 | #if defined(TARGET_PPC64) | |
2422 | if (!ctx->sf_mode) { | |
2423 | tcg_gen_ext32u_tl(ret, ret); | |
2424 | } | |
2425 | #endif | |
76a66253 JM |
2426 | } |
2427 | ||
636aa200 | 2428 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 AJ |
2429 | { |
2430 | int l1 = gen_new_label(); | |
2431 | TCGv t0 = tcg_temp_new(); | |
2432 | TCGv_i32 t1, t2; | |
2433 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2434 | gen_update_nip(ctx, ctx->nip - 4); | |
2435 | tcg_gen_andi_tl(t0, EA, mask); | |
2436 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2437 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2438 | t2 = tcg_const_i32(0); | |
e5f17ac6 | 2439 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2440 | tcg_temp_free_i32(t1); |
2441 | tcg_temp_free_i32(t2); | |
2442 | gen_set_label(l1); | |
2443 | tcg_temp_free(t0); | |
2444 | } | |
2445 | ||
7863667f | 2446 | /*** Integer load ***/ |
636aa200 | 2447 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2448 | { |
2449 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2450 | } | |
2451 | ||
636aa200 | 2452 | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2453 | { |
2454 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); | |
2455 | } | |
2456 | ||
636aa200 | 2457 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2458 | { |
2459 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); | |
2460 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2461 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2462 | } |
b61f2753 AJ |
2463 | } |
2464 | ||
636aa200 | 2465 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2466 | { |
76db3ba4 | 2467 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2468 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
fa3966a3 | 2469 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2470 | tcg_gen_ext16s_tl(arg1, arg1); |
76db3ba4 AJ |
2471 | } else { |
2472 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); | |
2473 | } | |
b61f2753 AJ |
2474 | } |
2475 | ||
636aa200 | 2476 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2477 | { |
76db3ba4 AJ |
2478 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2479 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2480 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2481 | } |
b61f2753 AJ |
2482 | } |
2483 | ||
76db3ba4 | 2484 | #if defined(TARGET_PPC64) |
636aa200 | 2485 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2486 | { |
a457e7ee | 2487 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2488 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
fa3966a3 AJ |
2489 | tcg_gen_bswap32_tl(arg1, arg1); |
2490 | tcg_gen_ext32s_tl(arg1, arg1); | |
b61f2753 | 2491 | } else |
76db3ba4 | 2492 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
b61f2753 | 2493 | } |
76db3ba4 | 2494 | #endif |
b61f2753 | 2495 | |
636aa200 | 2496 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2497 | { |
76db3ba4 AJ |
2498 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2499 | if (unlikely(ctx->le_mode)) { | |
66896cb8 | 2500 | tcg_gen_bswap64_i64(arg1, arg1); |
76db3ba4 | 2501 | } |
b61f2753 AJ |
2502 | } |
2503 | ||
636aa200 | 2504 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2505 | { |
76db3ba4 | 2506 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2507 | } |
2508 | ||
636aa200 | 2509 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2510 | { |
76db3ba4 | 2511 | if (unlikely(ctx->le_mode)) { |
76db3ba4 AJ |
2512 | TCGv t0 = tcg_temp_new(); |
2513 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2514 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2515 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2516 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2517 | } else { |
2518 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2519 | } | |
b61f2753 AJ |
2520 | } |
2521 | ||
636aa200 | 2522 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2523 | { |
76db3ba4 | 2524 | if (unlikely(ctx->le_mode)) { |
fa3966a3 AJ |
2525 | TCGv t0 = tcg_temp_new(); |
2526 | tcg_gen_ext32u_tl(t0, arg1); | |
2527 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2528 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2529 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2530 | } else { |
2531 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2532 | } | |
b61f2753 AJ |
2533 | } |
2534 | ||
636aa200 | 2535 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2536 | { |
76db3ba4 | 2537 | if (unlikely(ctx->le_mode)) { |
a7812ae4 | 2538 | TCGv_i64 t0 = tcg_temp_new_i64(); |
66896cb8 | 2539 | tcg_gen_bswap64_i64(t0, arg1); |
76db3ba4 | 2540 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
a7812ae4 | 2541 | tcg_temp_free_i64(t0); |
b61f2753 | 2542 | } else |
76db3ba4 | 2543 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2544 | } |
2545 | ||
0c8aacd4 | 2546 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2547 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2548 | { \ |
76db3ba4 AJ |
2549 | TCGv EA; \ |
2550 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2551 | EA = tcg_temp_new(); \ | |
2552 | gen_addr_imm_index(ctx, EA, 0); \ | |
2553 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2554 | tcg_temp_free(EA); \ |
79aceca5 FB |
2555 | } |
2556 | ||
0c8aacd4 | 2557 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2558 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2559 | { \ |
b61f2753 | 2560 | TCGv EA; \ |
76a66253 JM |
2561 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2562 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2563 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2564 | return; \ |
9a64fbe4 | 2565 | } \ |
76db3ba4 | 2566 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2567 | EA = tcg_temp_new(); \ |
9d53c753 | 2568 | if (type == PPC_64B) \ |
76db3ba4 | 2569 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2570 | else \ |
76db3ba4 AJ |
2571 | gen_addr_imm_index(ctx, EA, 0); \ |
2572 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2573 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2574 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2575 | } |
2576 | ||
0c8aacd4 | 2577 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2578 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2579 | { \ |
b61f2753 | 2580 | TCGv EA; \ |
76a66253 JM |
2581 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2582 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2583 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2584 | return; \ |
9a64fbe4 | 2585 | } \ |
76db3ba4 | 2586 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2587 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2588 | gen_addr_reg_index(ctx, EA); \ |
2589 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2590 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2591 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2592 | } |
2593 | ||
cd6e9320 | 2594 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
99e300ef | 2595 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2596 | { \ |
76db3ba4 AJ |
2597 | TCGv EA; \ |
2598 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2599 | EA = tcg_temp_new(); \ | |
2600 | gen_addr_reg_index(ctx, EA); \ | |
2601 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2602 | tcg_temp_free(EA); \ |
79aceca5 | 2603 | } |
cd6e9320 TH |
2604 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2605 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2606 | |
0c8aacd4 AJ |
2607 | #define GEN_LDS(name, ldop, op, type) \ |
2608 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2609 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2610 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2611 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2612 | |
2613 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2614 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2615 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2616 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2617 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2618 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2619 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2620 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2621 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2622 | /* lwaux */ |
0c8aacd4 | 2623 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2624 | /* lwax */ |
0c8aacd4 | 2625 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2626 | /* ldux */ |
0c8aacd4 | 2627 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2628 | /* ldx */ |
0c8aacd4 | 2629 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2630 | |
2631 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2632 | { |
b61f2753 | 2633 | TCGv EA; |
d9bce9d9 JM |
2634 | if (Rc(ctx->opcode)) { |
2635 | if (unlikely(rA(ctx->opcode) == 0 || | |
2636 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2637 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2638 | return; |
2639 | } | |
2640 | } | |
76db3ba4 | 2641 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2642 | EA = tcg_temp_new(); |
76db3ba4 | 2643 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2644 | if (ctx->opcode & 0x02) { |
2645 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2646 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2647 | } else { |
2648 | /* ld - ldu */ | |
76db3ba4 | 2649 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2650 | } |
d9bce9d9 | 2651 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2652 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2653 | tcg_temp_free(EA); | |
d9bce9d9 | 2654 | } |
99e300ef | 2655 | |
54623277 | 2656 | /* lq */ |
99e300ef | 2657 | static void gen_lq(DisasContext *ctx) |
be147d08 JM |
2658 | { |
2659 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2660 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2661 | #else |
2662 | int ra, rd; | |
b61f2753 | 2663 | TCGv EA; |
be147d08 JM |
2664 | |
2665 | /* Restore CPU state */ | |
76db3ba4 | 2666 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2667 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2668 | return; |
2669 | } | |
2670 | ra = rA(ctx->opcode); | |
2671 | rd = rD(ctx->opcode); | |
2672 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2673 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2674 | return; |
2675 | } | |
76db3ba4 | 2676 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2677 | /* Little-endian mode is not handled */ |
e06fcd75 | 2678 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2679 | return; |
2680 | } | |
76db3ba4 | 2681 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2682 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2683 | gen_addr_imm_index(ctx, EA, 0x0F); |
2684 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2685 | gen_addr_add(ctx, EA, EA, 8); | |
2686 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
b61f2753 | 2687 | tcg_temp_free(EA); |
be147d08 JM |
2688 | #endif |
2689 | } | |
d9bce9d9 | 2690 | #endif |
79aceca5 FB |
2691 | |
2692 | /*** Integer store ***/ | |
0c8aacd4 | 2693 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2694 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2695 | { \ |
76db3ba4 AJ |
2696 | TCGv EA; \ |
2697 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2698 | EA = tcg_temp_new(); \ | |
2699 | gen_addr_imm_index(ctx, EA, 0); \ | |
2700 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2701 | tcg_temp_free(EA); \ |
79aceca5 FB |
2702 | } |
2703 | ||
0c8aacd4 | 2704 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2705 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2706 | { \ |
b61f2753 | 2707 | TCGv EA; \ |
76a66253 | 2708 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2709 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2710 | return; \ |
9a64fbe4 | 2711 | } \ |
76db3ba4 | 2712 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2713 | EA = tcg_temp_new(); \ |
9d53c753 | 2714 | if (type == PPC_64B) \ |
76db3ba4 | 2715 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2716 | else \ |
76db3ba4 AJ |
2717 | gen_addr_imm_index(ctx, EA, 0); \ |
2718 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2719 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2720 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2721 | } |
2722 | ||
0c8aacd4 | 2723 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2724 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2725 | { \ |
b61f2753 | 2726 | TCGv EA; \ |
76a66253 | 2727 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2728 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2729 | return; \ |
9a64fbe4 | 2730 | } \ |
76db3ba4 | 2731 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2732 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2733 | gen_addr_reg_index(ctx, EA); \ |
2734 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2735 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2736 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2737 | } |
2738 | ||
cd6e9320 TH |
2739 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
2740 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 2741 | { \ |
76db3ba4 AJ |
2742 | TCGv EA; \ |
2743 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2744 | EA = tcg_temp_new(); \ | |
2745 | gen_addr_reg_index(ctx, EA); \ | |
2746 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2747 | tcg_temp_free(EA); \ |
79aceca5 | 2748 | } |
cd6e9320 TH |
2749 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
2750 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2751 | |
0c8aacd4 AJ |
2752 | #define GEN_STS(name, stop, op, type) \ |
2753 | GEN_ST(name, stop, op | 0x20, type); \ | |
2754 | GEN_STU(name, stop, op | 0x21, type); \ | |
2755 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2756 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2757 | |
2758 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2759 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2760 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2761 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2762 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2763 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2764 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
2765 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2766 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
2767 | |
2768 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2769 | { |
be147d08 | 2770 | int rs; |
b61f2753 | 2771 | TCGv EA; |
be147d08 JM |
2772 | |
2773 | rs = rS(ctx->opcode); | |
2774 | if ((ctx->opcode & 0x3) == 0x2) { | |
2775 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2776 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2777 | #else |
2778 | /* stq */ | |
76db3ba4 | 2779 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2780 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2781 | return; |
2782 | } | |
2783 | if (unlikely(rs & 1)) { | |
e06fcd75 | 2784 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2785 | return; |
2786 | } | |
76db3ba4 | 2787 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2788 | /* Little-endian mode is not handled */ |
e06fcd75 | 2789 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2790 | return; |
2791 | } | |
76db3ba4 | 2792 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2793 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2794 | gen_addr_imm_index(ctx, EA, 0x03); |
2795 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
2796 | gen_addr_add(ctx, EA, EA, 8); | |
2797 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
b61f2753 | 2798 | tcg_temp_free(EA); |
be147d08 JM |
2799 | #endif |
2800 | } else { | |
2801 | /* std / stdu */ | |
2802 | if (Rc(ctx->opcode)) { | |
2803 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2804 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2805 | return; |
2806 | } | |
2807 | } | |
76db3ba4 | 2808 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2809 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2810 | gen_addr_imm_index(ctx, EA, 0x03); |
2811 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 2812 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2813 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2814 | tcg_temp_free(EA); | |
d9bce9d9 | 2815 | } |
d9bce9d9 JM |
2816 | } |
2817 | #endif | |
79aceca5 FB |
2818 | /*** Integer load and store with byte reverse ***/ |
2819 | /* lhbrx */ | |
86178a57 | 2820 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2821 | { |
76db3ba4 AJ |
2822 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2823 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2824 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2825 | } |
b61f2753 | 2826 | } |
0c8aacd4 | 2827 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2828 | |
79aceca5 | 2829 | /* lwbrx */ |
86178a57 | 2830 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2831 | { |
76db3ba4 AJ |
2832 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2833 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2834 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2835 | } |
b61f2753 | 2836 | } |
0c8aacd4 | 2837 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2838 | |
cd6e9320 TH |
2839 | #if defined(TARGET_PPC64) |
2840 | /* ldbrx */ | |
2841 | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2842 | { | |
2843 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); | |
2844 | if (likely(!ctx->le_mode)) { | |
2845 | tcg_gen_bswap64_tl(arg1, arg1); | |
2846 | } | |
2847 | } | |
2848 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); | |
2849 | #endif /* TARGET_PPC64 */ | |
2850 | ||
79aceca5 | 2851 | /* sthbrx */ |
86178a57 | 2852 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2853 | { |
76db3ba4 | 2854 | if (likely(!ctx->le_mode)) { |
76db3ba4 AJ |
2855 | TCGv t0 = tcg_temp_new(); |
2856 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2857 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2858 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2859 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2860 | } else { |
2861 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2862 | } | |
b61f2753 | 2863 | } |
0c8aacd4 | 2864 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 2865 | |
79aceca5 | 2866 | /* stwbrx */ |
86178a57 | 2867 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2868 | { |
76db3ba4 | 2869 | if (likely(!ctx->le_mode)) { |
fa3966a3 AJ |
2870 | TCGv t0 = tcg_temp_new(); |
2871 | tcg_gen_ext32u_tl(t0, arg1); | |
2872 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2873 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2874 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2875 | } else { |
2876 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2877 | } | |
b61f2753 | 2878 | } |
0c8aacd4 | 2879 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 | 2880 | |
cd6e9320 TH |
2881 | #if defined(TARGET_PPC64) |
2882 | /* stdbrx */ | |
2883 | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2884 | { | |
2885 | if (likely(!ctx->le_mode)) { | |
2886 | TCGv t0 = tcg_temp_new(); | |
2887 | tcg_gen_bswap64_tl(t0, arg1); | |
2888 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); | |
2889 | tcg_temp_free(t0); | |
2890 | } else { | |
2891 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); | |
2892 | } | |
2893 | } | |
2894 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); | |
2895 | #endif /* TARGET_PPC64 */ | |
2896 | ||
79aceca5 | 2897 | /*** Integer load and store multiple ***/ |
99e300ef | 2898 | |
54623277 | 2899 | /* lmw */ |
99e300ef | 2900 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2901 | { |
76db3ba4 AJ |
2902 | TCGv t0; |
2903 | TCGv_i32 t1; | |
2904 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2905 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2906 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2907 | t0 = tcg_temp_new(); |
2908 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2909 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2910 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2911 | tcg_temp_free(t0); |
2912 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2913 | } |
2914 | ||
2915 | /* stmw */ | |
99e300ef | 2916 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2917 | { |
76db3ba4 AJ |
2918 | TCGv t0; |
2919 | TCGv_i32 t1; | |
2920 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2921 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2922 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2923 | t0 = tcg_temp_new(); |
2924 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2925 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2926 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2927 | tcg_temp_free(t0); |
2928 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2929 | } |
2930 | ||
2931 | /*** Integer load and store strings ***/ | |
54623277 | 2932 | |
79aceca5 | 2933 | /* lswi */ |
3fc6c082 | 2934 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
2935 | * rA is in the range of registers to be loaded. |
2936 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
2937 | * For now, I'll follow the spec... | |
2938 | */ | |
99e300ef | 2939 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 2940 | { |
dfbc799d AJ |
2941 | TCGv t0; |
2942 | TCGv_i32 t1, t2; | |
79aceca5 FB |
2943 | int nb = NB(ctx->opcode); |
2944 | int start = rD(ctx->opcode); | |
9a64fbe4 | 2945 | int ra = rA(ctx->opcode); |
79aceca5 FB |
2946 | int nr; |
2947 | ||
2948 | if (nb == 0) | |
2949 | nb = 32; | |
2950 | nr = nb / 4; | |
76a66253 JM |
2951 | if (unlikely(((start + nr) > 32 && |
2952 | start <= ra && (start + nr - 32) > ra) || | |
2953 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 2954 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 2955 | return; |
297d8e62 | 2956 | } |
76db3ba4 | 2957 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 2958 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2959 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 2960 | t0 = tcg_temp_new(); |
76db3ba4 | 2961 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
2962 | t1 = tcg_const_i32(nb); |
2963 | t2 = tcg_const_i32(start); | |
2f5a189c | 2964 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2965 | tcg_temp_free(t0); |
2966 | tcg_temp_free_i32(t1); | |
2967 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2968 | } |
2969 | ||
2970 | /* lswx */ | |
99e300ef | 2971 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 2972 | { |
76db3ba4 AJ |
2973 | TCGv t0; |
2974 | TCGv_i32 t1, t2, t3; | |
2975 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2976 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2977 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2978 | t0 = tcg_temp_new(); |
2979 | gen_addr_reg_index(ctx, t0); | |
2980 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2981 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
2982 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 2983 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
2984 | tcg_temp_free(t0); |
2985 | tcg_temp_free_i32(t1); | |
2986 | tcg_temp_free_i32(t2); | |
2987 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
2988 | } |
2989 | ||
2990 | /* stswi */ | |
99e300ef | 2991 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 2992 | { |
76db3ba4 AJ |
2993 | TCGv t0; |
2994 | TCGv_i32 t1, t2; | |
4b3686fa | 2995 | int nb = NB(ctx->opcode); |
76db3ba4 | 2996 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 2997 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2998 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2999 | t0 = tcg_temp_new(); |
3000 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3001 | if (nb == 0) |
3002 | nb = 32; | |
dfbc799d | 3003 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3004 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3005 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3006 | tcg_temp_free(t0); |
3007 | tcg_temp_free_i32(t1); | |
3008 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3009 | } |
3010 | ||
3011 | /* stswx */ | |
99e300ef | 3012 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3013 | { |
76db3ba4 AJ |
3014 | TCGv t0; |
3015 | TCGv_i32 t1, t2; | |
3016 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3017 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3018 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3019 | t0 = tcg_temp_new(); |
3020 | gen_addr_reg_index(ctx, t0); | |
3021 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3022 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3023 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3024 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3025 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3026 | tcg_temp_free(t0); |
3027 | tcg_temp_free_i32(t1); | |
3028 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3029 | } |
3030 | ||
3031 | /*** Memory synchronisation ***/ | |
3032 | /* eieio */ | |
99e300ef | 3033 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3034 | { |
79aceca5 FB |
3035 | } |
3036 | ||
3037 | /* isync */ | |
99e300ef | 3038 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3039 | { |
e06fcd75 | 3040 | gen_stop_exception(ctx); |
79aceca5 FB |
3041 | } |
3042 | ||
111bfab3 | 3043 | /* lwarx */ |
99e300ef | 3044 | static void gen_lwarx(DisasContext *ctx) |
79aceca5 | 3045 | { |
76db3ba4 | 3046 | TCGv t0; |
18b21a2f | 3047 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3048 | gen_set_access_type(ctx, ACCESS_RES); |
3049 | t0 = tcg_temp_local_new(); | |
3050 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3051 | gen_check_align(ctx, t0, 0x03); |
18b21a2f | 3052 | gen_qemu_ld32u(ctx, gpr, t0); |
cf360a32 | 3053 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3054 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3055 | tcg_temp_free(t0); |
79aceca5 FB |
3056 | } |
3057 | ||
4425265b NF |
3058 | #if defined(CONFIG_USER_ONLY) |
3059 | static void gen_conditional_store (DisasContext *ctx, TCGv EA, | |
3060 | int reg, int size) | |
3061 | { | |
3062 | TCGv t0 = tcg_temp_new(); | |
3063 | uint32_t save_exception = ctx->exception; | |
3064 | ||
1328c2bf | 3065 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
4425265b | 3066 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
1328c2bf | 3067 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b NF |
3068 | tcg_temp_free(t0); |
3069 | gen_update_nip(ctx, ctx->nip-4); | |
3070 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3071 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3072 | ctx->exception = save_exception; | |
3073 | } | |
3074 | #endif | |
3075 | ||
79aceca5 | 3076 | /* stwcx. */ |
e8eaa2c0 | 3077 | static void gen_stwcx_(DisasContext *ctx) |
79aceca5 | 3078 | { |
76db3ba4 AJ |
3079 | TCGv t0; |
3080 | gen_set_access_type(ctx, ACCESS_RES); | |
3081 | t0 = tcg_temp_local_new(); | |
3082 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3083 | gen_check_align(ctx, t0, 0x03); |
4425265b NF |
3084 | #if defined(CONFIG_USER_ONLY) |
3085 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); | |
3086 | #else | |
3087 | { | |
3088 | int l1; | |
3089 | ||
da91a00f | 3090 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3091 | l1 = gen_new_label(); |
3092 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3093 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3094 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3095 | gen_set_label(l1); | |
3096 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3097 | } | |
3098 | #endif | |
cf360a32 | 3099 | tcg_temp_free(t0); |
79aceca5 FB |
3100 | } |
3101 | ||
426613db | 3102 | #if defined(TARGET_PPC64) |
426613db | 3103 | /* ldarx */ |
99e300ef | 3104 | static void gen_ldarx(DisasContext *ctx) |
426613db | 3105 | { |
76db3ba4 | 3106 | TCGv t0; |
18b21a2f | 3107 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3108 | gen_set_access_type(ctx, ACCESS_RES); |
3109 | t0 = tcg_temp_local_new(); | |
3110 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3111 | gen_check_align(ctx, t0, 0x07); |
18b21a2f | 3112 | gen_qemu_ld64(ctx, gpr, t0); |
cf360a32 | 3113 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3114 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3115 | tcg_temp_free(t0); |
426613db JM |
3116 | } |
3117 | ||
3118 | /* stdcx. */ | |
e8eaa2c0 | 3119 | static void gen_stdcx_(DisasContext *ctx) |
426613db | 3120 | { |
76db3ba4 AJ |
3121 | TCGv t0; |
3122 | gen_set_access_type(ctx, ACCESS_RES); | |
3123 | t0 = tcg_temp_local_new(); | |
3124 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3125 | gen_check_align(ctx, t0, 0x07); |
4425265b NF |
3126 | #if defined(CONFIG_USER_ONLY) |
3127 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); | |
3128 | #else | |
3129 | { | |
3130 | int l1; | |
da91a00f | 3131 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4425265b NF |
3132 | l1 = gen_new_label(); |
3133 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3134 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3135 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3136 | gen_set_label(l1); | |
3137 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3138 | } | |
3139 | #endif | |
cf360a32 | 3140 | tcg_temp_free(t0); |
426613db JM |
3141 | } |
3142 | #endif /* defined(TARGET_PPC64) */ | |
3143 | ||
79aceca5 | 3144 | /* sync */ |
99e300ef | 3145 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3146 | { |
79aceca5 FB |
3147 | } |
3148 | ||
0db1b20e | 3149 | /* wait */ |
99e300ef | 3150 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3151 | { |
931ff272 | 3152 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1328c2bf | 3153 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted)); |
931ff272 | 3154 | tcg_temp_free_i32(t0); |
0db1b20e | 3155 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3156 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3157 | } |
3158 | ||
79aceca5 | 3159 | /*** Floating-point load ***/ |
a0d7d5a7 | 3160 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3161 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3162 | { \ |
a0d7d5a7 | 3163 | TCGv EA; \ |
76a66253 | 3164 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3165 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3166 | return; \ |
3167 | } \ | |
76db3ba4 | 3168 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3169 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3170 | gen_addr_imm_index(ctx, EA, 0); \ |
3171 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3172 | tcg_temp_free(EA); \ |
79aceca5 FB |
3173 | } |
3174 | ||
a0d7d5a7 | 3175 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3176 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3177 | { \ |
a0d7d5a7 | 3178 | TCGv EA; \ |
76a66253 | 3179 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3180 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3181 | return; \ |
3182 | } \ | |
76a66253 | 3183 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3184 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3185 | return; \ |
9a64fbe4 | 3186 | } \ |
76db3ba4 | 3187 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3188 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3189 | gen_addr_imm_index(ctx, EA, 0); \ |
3190 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3191 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3192 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3193 | } |
3194 | ||
a0d7d5a7 | 3195 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3196 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3197 | { \ |
a0d7d5a7 | 3198 | TCGv EA; \ |
76a66253 | 3199 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3200 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3201 | return; \ |
3202 | } \ | |
76a66253 | 3203 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3204 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3205 | return; \ |
9a64fbe4 | 3206 | } \ |
76db3ba4 | 3207 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3208 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3209 | gen_addr_reg_index(ctx, EA); \ |
3210 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3211 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3212 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3213 | } |
3214 | ||
a0d7d5a7 | 3215 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3216 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3217 | { \ |
a0d7d5a7 | 3218 | TCGv EA; \ |
76a66253 | 3219 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3220 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3221 | return; \ |
3222 | } \ | |
76db3ba4 | 3223 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3224 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3225 | gen_addr_reg_index(ctx, EA); \ |
3226 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3227 | tcg_temp_free(EA); \ |
79aceca5 FB |
3228 | } |
3229 | ||
a0d7d5a7 AJ |
3230 | #define GEN_LDFS(name, ldop, op, type) \ |
3231 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3232 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3233 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3234 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3235 | ||
636aa200 | 3236 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3237 | { |
3238 | TCGv t0 = tcg_temp_new(); | |
3239 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3240 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3241 | tcg_gen_trunc_tl_i32(t1, t0); |
3242 | tcg_temp_free(t0); | |
8e703949 | 3243 | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
a0d7d5a7 AJ |
3244 | tcg_temp_free_i32(t1); |
3245 | } | |
79aceca5 | 3246 | |
a0d7d5a7 AJ |
3247 | /* lfd lfdu lfdux lfdx */ |
3248 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3249 | /* lfs lfsu lfsux lfsx */ | |
3250 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 FB |
3251 | |
3252 | /*** Floating-point store ***/ | |
a0d7d5a7 | 3253 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3254 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3255 | { \ |
a0d7d5a7 | 3256 | TCGv EA; \ |
76a66253 | 3257 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3258 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3259 | return; \ |
3260 | } \ | |
76db3ba4 | 3261 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3262 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3263 | gen_addr_imm_index(ctx, EA, 0); \ |
3264 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3265 | tcg_temp_free(EA); \ |
79aceca5 FB |
3266 | } |
3267 | ||
a0d7d5a7 | 3268 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3269 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3270 | { \ |
a0d7d5a7 | 3271 | TCGv EA; \ |
76a66253 | 3272 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3273 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3274 | return; \ |
3275 | } \ | |
76a66253 | 3276 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3277 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3278 | return; \ |
9a64fbe4 | 3279 | } \ |
76db3ba4 | 3280 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3281 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3282 | gen_addr_imm_index(ctx, EA, 0); \ |
3283 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3284 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3285 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3286 | } |
3287 | ||
a0d7d5a7 | 3288 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3289 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3290 | { \ |
a0d7d5a7 | 3291 | TCGv EA; \ |
76a66253 | 3292 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3293 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3294 | return; \ |
3295 | } \ | |
76a66253 | 3296 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3297 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3298 | return; \ |
9a64fbe4 | 3299 | } \ |
76db3ba4 | 3300 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3301 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3302 | gen_addr_reg_index(ctx, EA); \ |
3303 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3304 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3305 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3306 | } |
3307 | ||
a0d7d5a7 | 3308 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3309 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3310 | { \ |
a0d7d5a7 | 3311 | TCGv EA; \ |
76a66253 | 3312 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3313 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3314 | return; \ |
3315 | } \ | |
76db3ba4 | 3316 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3317 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3318 | gen_addr_reg_index(ctx, EA); \ |
3319 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3320 | tcg_temp_free(EA); \ |
79aceca5 FB |
3321 | } |
3322 | ||
a0d7d5a7 AJ |
3323 | #define GEN_STFS(name, stop, op, type) \ |
3324 | GEN_STF(name, stop, op | 0x20, type); \ | |
3325 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3326 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3327 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3328 | ||
636aa200 | 3329 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3330 | { |
3331 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3332 | TCGv t1 = tcg_temp_new(); | |
8e703949 | 3333 | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
a0d7d5a7 AJ |
3334 | tcg_gen_extu_i32_tl(t1, t0); |
3335 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3336 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3337 | tcg_temp_free(t1); |
3338 | } | |
79aceca5 FB |
3339 | |
3340 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3341 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3342 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3343 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 FB |
3344 | |
3345 | /* Optional: */ | |
636aa200 | 3346 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3347 | { |
3348 | TCGv t0 = tcg_temp_new(); | |
3349 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3350 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3351 | tcg_temp_free(t0); |
3352 | } | |
79aceca5 | 3353 | /* stfiwx */ |
a0d7d5a7 | 3354 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 | 3355 | |
697ab892 DG |
3356 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3357 | { | |
3358 | #if defined(TARGET_PPC64) | |
3359 | if (ctx->has_cfar) | |
3360 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3361 | #endif | |
3362 | } | |
3363 | ||
79aceca5 | 3364 | /*** Branch ***/ |
636aa200 | 3365 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 FB |
3366 | { |
3367 | TranslationBlock *tb; | |
3368 | tb = ctx->tb; | |
a2ffb812 AJ |
3369 | #if defined(TARGET_PPC64) |
3370 | if (!ctx->sf_mode) | |
3371 | dest = (uint32_t) dest; | |
3372 | #endif | |
57fec1fe | 3373 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3374 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3375 | tcg_gen_goto_tb(n); |
a2ffb812 | 3376 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
4b4a72e5 | 3377 | tcg_gen_exit_tb((tcg_target_long)tb + n); |
c1942362 | 3378 | } else { |
a2ffb812 | 3379 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3380 | if (unlikely(ctx->singlestep_enabled)) { |
3381 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3382 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3383 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3384 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
8cbcb4fa AJ |
3385 | target_ulong tmp = ctx->nip; |
3386 | ctx->nip = dest; | |
e06fcd75 | 3387 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3388 | ctx->nip = tmp; |
3389 | } | |
3390 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3391 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3392 | } |
3393 | } | |
57fec1fe | 3394 | tcg_gen_exit_tb(0); |
c1942362 | 3395 | } |
c53be334 FB |
3396 | } |
3397 | ||
636aa200 | 3398 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f JM |
3399 | { |
3400 | #if defined(TARGET_PPC64) | |
a2ffb812 AJ |
3401 | if (ctx->sf_mode == 0) |
3402 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); | |
e1833e1f JM |
3403 | else |
3404 | #endif | |
a2ffb812 | 3405 | tcg_gen_movi_tl(cpu_lr, nip); |
e1833e1f JM |
3406 | } |
3407 | ||
79aceca5 | 3408 | /* b ba bl bla */ |
99e300ef | 3409 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3410 | { |
76a66253 | 3411 | target_ulong li, target; |
38a64f9d | 3412 | |
8cbcb4fa | 3413 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3414 | /* sign extend LI */ |
76a66253 | 3415 | #if defined(TARGET_PPC64) |
d9bce9d9 JM |
3416 | if (ctx->sf_mode) |
3417 | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; | |
3418 | else | |
76a66253 | 3419 | #endif |
d9bce9d9 | 3420 | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
76a66253 | 3421 | if (likely(AA(ctx->opcode) == 0)) |
046d6672 | 3422 | target = ctx->nip + li - 4; |
79aceca5 | 3423 | else |
9a64fbe4 | 3424 | target = li; |
e1833e1f JM |
3425 | if (LK(ctx->opcode)) |
3426 | gen_setlr(ctx, ctx->nip); | |
697ab892 | 3427 | gen_update_cfar(ctx, ctx->nip); |
c1942362 | 3428 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3429 | } |
3430 | ||
e98a6e40 FB |
3431 | #define BCOND_IM 0 |
3432 | #define BCOND_LR 1 | |
3433 | #define BCOND_CTR 2 | |
3434 | ||
636aa200 | 3435 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3436 | { |
d9bce9d9 | 3437 | uint32_t bo = BO(ctx->opcode); |
05f92404 | 3438 | int l1; |
a2ffb812 | 3439 | TCGv target; |
e98a6e40 | 3440 | |
8cbcb4fa | 3441 | ctx->exception = POWERPC_EXCP_BRANCH; |
a2ffb812 | 3442 | if (type == BCOND_LR || type == BCOND_CTR) { |
a7812ae4 | 3443 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3444 | if (type == BCOND_CTR) |
3445 | tcg_gen_mov_tl(target, cpu_ctr); | |
3446 | else | |
3447 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3448 | } else { |
3449 | TCGV_UNUSED(target); | |
e98a6e40 | 3450 | } |
e1833e1f JM |
3451 | if (LK(ctx->opcode)) |
3452 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3453 | l1 = gen_new_label(); |
3454 | if ((bo & 0x4) == 0) { | |
3455 | /* Decrement and test CTR */ | |
a7812ae4 | 3456 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3457 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3458 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3459 | return; |
3460 | } | |
3461 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
d9bce9d9 | 3462 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3463 | if (!ctx->sf_mode) |
3464 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3465 | else | |
d9bce9d9 | 3466 | #endif |
a2ffb812 AJ |
3467 | tcg_gen_mov_tl(temp, cpu_ctr); |
3468 | if (bo & 0x2) { | |
3469 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3470 | } else { | |
3471 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3472 | } |
a7812ae4 | 3473 | tcg_temp_free(temp); |
a2ffb812 AJ |
3474 | } |
3475 | if ((bo & 0x10) == 0) { | |
3476 | /* Test CR */ | |
3477 | uint32_t bi = BI(ctx->opcode); | |
3478 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3479 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3480 | |
d9bce9d9 | 3481 | if (bo & 0x8) { |
a2ffb812 AJ |
3482 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3483 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3484 | } else { |
a2ffb812 AJ |
3485 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3486 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3487 | } |
a7812ae4 | 3488 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3489 | } |
697ab892 | 3490 | gen_update_cfar(ctx, ctx->nip); |
e98a6e40 | 3491 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3492 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3493 | if (likely(AA(ctx->opcode) == 0)) { | |
3494 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3495 | } else { | |
3496 | gen_goto_tb(ctx, 0, li); | |
3497 | } | |
c53be334 | 3498 | gen_set_label(l1); |
c1942362 | 3499 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3500 | } else { |
d9bce9d9 | 3501 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3502 | if (!(ctx->sf_mode)) |
3503 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); | |
3504 | else | |
3505 | #endif | |
3506 | tcg_gen_andi_tl(cpu_nip, target, ~3); | |
3507 | tcg_gen_exit_tb(0); | |
3508 | gen_set_label(l1); | |
3509 | #if defined(TARGET_PPC64) | |
3510 | if (!(ctx->sf_mode)) | |
3511 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); | |
d9bce9d9 JM |
3512 | else |
3513 | #endif | |
a2ffb812 | 3514 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
57fec1fe | 3515 | tcg_gen_exit_tb(0); |
08e46e54 | 3516 | } |
e98a6e40 FB |
3517 | } |
3518 | ||
99e300ef | 3519 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3520 | { |
e98a6e40 FB |
3521 | gen_bcond(ctx, BCOND_IM); |
3522 | } | |
3523 | ||
99e300ef | 3524 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3525 | { |
e98a6e40 FB |
3526 | gen_bcond(ctx, BCOND_CTR); |
3527 | } | |
3528 | ||
99e300ef | 3529 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3530 | { |
e98a6e40 FB |
3531 | gen_bcond(ctx, BCOND_LR); |
3532 | } | |
79aceca5 FB |
3533 | |
3534 | /*** Condition register logical ***/ | |
e1571908 | 3535 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3536 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3537 | { \ |
fc0d441e JM |
3538 | uint8_t bitmask; \ |
3539 | int sh; \ | |
a7812ae4 | 3540 | TCGv_i32 t0, t1; \ |
fc0d441e | 3541 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3542 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3543 | if (sh > 0) \ |
fea0c503 | 3544 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3545 | else if (sh < 0) \ |
fea0c503 | 3546 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3547 | else \ |
fea0c503 | 3548 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3549 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3550 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3551 | if (sh > 0) \ | |
fea0c503 | 3552 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3553 | else if (sh < 0) \ |
fea0c503 | 3554 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3555 | else \ |
fea0c503 AJ |
3556 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3557 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3558 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3559 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3560 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3561 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3562 | tcg_temp_free_i32(t0); \ |
3563 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3564 | } |
3565 | ||
3566 | /* crand */ | |
e1571908 | 3567 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3568 | /* crandc */ |
e1571908 | 3569 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3570 | /* creqv */ |
e1571908 | 3571 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3572 | /* crnand */ |
e1571908 | 3573 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3574 | /* crnor */ |
e1571908 | 3575 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3576 | /* cror */ |
e1571908 | 3577 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3578 | /* crorc */ |
e1571908 | 3579 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3580 | /* crxor */ |
e1571908 | 3581 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3582 | |
54623277 | 3583 | /* mcrf */ |
99e300ef | 3584 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3585 | { |
47e4661c | 3586 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3587 | } |
3588 | ||
3589 | /*** System linkage ***/ | |
99e300ef | 3590 | |
54623277 | 3591 | /* rfi (mem_idx only) */ |
99e300ef | 3592 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3593 | { |
9a64fbe4 | 3594 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3595 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3596 | #else |
3597 | /* Restore CPU state */ | |
76db3ba4 | 3598 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3599 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3600 | return; |
9a64fbe4 | 3601 | } |
697ab892 | 3602 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3603 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3604 | gen_sync_exception(ctx); |
9a64fbe4 | 3605 | #endif |
79aceca5 FB |
3606 | } |
3607 | ||
426613db | 3608 | #if defined(TARGET_PPC64) |
99e300ef | 3609 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3610 | { |
3611 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3612 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3613 | #else |
3614 | /* Restore CPU state */ | |
76db3ba4 | 3615 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3616 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3617 | return; |
3618 | } | |
697ab892 | 3619 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3620 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3621 | gen_sync_exception(ctx); |
426613db JM |
3622 | #endif |
3623 | } | |
426613db | 3624 | |
99e300ef | 3625 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3626 | { |
3627 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3628 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3629 | #else |
3630 | /* Restore CPU state */ | |
76db3ba4 | 3631 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 3632 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3633 | return; |
3634 | } | |
e5f17ac6 | 3635 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3636 | gen_sync_exception(ctx); |
be147d08 JM |
3637 | #endif |
3638 | } | |
3639 | #endif | |
3640 | ||
79aceca5 | 3641 | /* sc */ |
417bf010 JM |
3642 | #if defined(CONFIG_USER_ONLY) |
3643 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3644 | #else | |
3645 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3646 | #endif | |
99e300ef | 3647 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3648 | { |
e1833e1f JM |
3649 | uint32_t lev; |
3650 | ||
3651 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3652 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3653 | } |
3654 | ||
3655 | /*** Trap ***/ | |
99e300ef | 3656 | |
54623277 | 3657 | /* tw */ |
99e300ef | 3658 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3659 | { |
cab3bee2 | 3660 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3661 | /* Update the nip since this might generate a trap exception */ |
3662 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3663 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3664 | t0); | |
cab3bee2 | 3665 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3666 | } |
3667 | ||
3668 | /* twi */ | |
99e300ef | 3669 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3670 | { |
cab3bee2 AJ |
3671 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3672 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3673 | /* Update the nip since this might generate a trap exception */ |
3674 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3675 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3676 | tcg_temp_free(t0); |
3677 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3678 | } |
3679 | ||
d9bce9d9 JM |
3680 | #if defined(TARGET_PPC64) |
3681 | /* td */ | |
99e300ef | 3682 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3683 | { |
cab3bee2 | 3684 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3685 | /* Update the nip since this might generate a trap exception */ |
3686 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3687 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3688 | t0); | |
cab3bee2 | 3689 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3690 | } |
3691 | ||
3692 | /* tdi */ | |
99e300ef | 3693 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3694 | { |
cab3bee2 AJ |
3695 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3696 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3697 | /* Update the nip since this might generate a trap exception */ |
3698 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3699 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3700 | tcg_temp_free(t0); |
3701 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3702 | } |
3703 | #endif | |
3704 | ||
79aceca5 | 3705 | /*** Processor control ***/ |
99e300ef | 3706 | |
da91a00f RH |
3707 | static void gen_read_xer(TCGv dst) |
3708 | { | |
3709 | TCGv t0 = tcg_temp_new(); | |
3710 | TCGv t1 = tcg_temp_new(); | |
3711 | TCGv t2 = tcg_temp_new(); | |
3712 | tcg_gen_mov_tl(dst, cpu_xer); | |
3713 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
3714 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
3715 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
3716 | tcg_gen_or_tl(t0, t0, t1); | |
3717 | tcg_gen_or_tl(dst, dst, t2); | |
3718 | tcg_gen_or_tl(dst, dst, t0); | |
3719 | tcg_temp_free(t0); | |
3720 | tcg_temp_free(t1); | |
3721 | tcg_temp_free(t2); | |
3722 | } | |
3723 | ||
3724 | static void gen_write_xer(TCGv src) | |
3725 | { | |
3726 | tcg_gen_andi_tl(cpu_xer, src, | |
3727 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
3728 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
3729 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
3730 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
3731 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
3732 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
3733 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
3734 | } | |
3735 | ||
54623277 | 3736 | /* mcrxr */ |
99e300ef | 3737 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3738 | { |
da91a00f RH |
3739 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3740 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3741 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3742 | ||
3743 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
3744 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
3745 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
3746 | tcg_gen_shri_i32(t0, t0, 2); | |
3747 | tcg_gen_shri_i32(t1, t1, 1); | |
3748 | tcg_gen_or_i32(dst, dst, t0); | |
3749 | tcg_gen_or_i32(dst, dst, t1); | |
3750 | tcg_temp_free_i32(t0); | |
3751 | tcg_temp_free_i32(t1); | |
3752 | ||
3753 | tcg_gen_movi_tl(cpu_so, 0); | |
3754 | tcg_gen_movi_tl(cpu_ov, 0); | |
3755 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
3756 | } |
3757 | ||
0cfe11ea | 3758 | /* mfcr mfocrf */ |
99e300ef | 3759 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3760 | { |
76a66253 | 3761 | uint32_t crm, crn; |
3b46e624 | 3762 | |
76a66253 JM |
3763 | if (likely(ctx->opcode & 0x00100000)) { |
3764 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3765 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3766 | crn = ctz32 (crm); |
e1571908 | 3767 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3768 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3769 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3770 | } |
d9bce9d9 | 3771 | } else { |
651721b2 AJ |
3772 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3773 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3774 | tcg_gen_shli_i32(t0, t0, 4); | |
3775 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3776 | tcg_gen_shli_i32(t0, t0, 4); | |
3777 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3778 | tcg_gen_shli_i32(t0, t0, 4); | |
3779 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3780 | tcg_gen_shli_i32(t0, t0, 4); | |
3781 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3782 | tcg_gen_shli_i32(t0, t0, 4); | |
3783 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3784 | tcg_gen_shli_i32(t0, t0, 4); | |
3785 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3786 | tcg_gen_shli_i32(t0, t0, 4); | |
3787 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3788 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3789 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3790 | } |
79aceca5 FB |
3791 | } |
3792 | ||
3793 | /* mfmsr */ | |
99e300ef | 3794 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3795 | { |
9a64fbe4 | 3796 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3797 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3798 | #else |
76db3ba4 | 3799 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3800 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3801 | return; |
9a64fbe4 | 3802 | } |
6527f6ea | 3803 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 3804 | #endif |
79aceca5 FB |
3805 | } |
3806 | ||
7b13448f | 3807 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3fc6c082 | 3808 | { |
7b13448f | 3809 | #if 0 |
3fc6c082 FB |
3810 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3811 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3812 | #endif |
3fc6c082 FB |
3813 | } |
3814 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3815 | |
79aceca5 | 3816 | /* mfspr */ |
636aa200 | 3817 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 3818 | { |
45d827d2 | 3819 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
3820 | uint32_t sprn = SPR(ctx->opcode); |
3821 | ||
3fc6c082 | 3822 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 3823 | if (ctx->mem_idx == 2) |
be147d08 | 3824 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 3825 | else if (ctx->mem_idx) |
3fc6c082 FB |
3826 | read_cb = ctx->spr_cb[sprn].oea_read; |
3827 | else | |
9a64fbe4 | 3828 | #endif |
3fc6c082 | 3829 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
3830 | if (likely(read_cb != NULL)) { |
3831 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 3832 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
3833 | } else { |
3834 | /* Privilege exception */ | |
9fceefa7 JM |
3835 | /* This is a hack to avoid warnings when running Linux: |
3836 | * this OS breaks the PowerPC virtualisation model, | |
3837 | * allowing userland application to read the PVR | |
3838 | */ | |
3839 | if (sprn != SPR_PVR) { | |
93fcfe39 | 3840 | qemu_log("Trying to read privileged spr %d %03x at " |
90e189ec BS |
3841 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3842 | printf("Trying to read privileged spr %d %03x at " | |
3843 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); | |
f24e5695 | 3844 | } |
e06fcd75 | 3845 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 3846 | } |
3fc6c082 FB |
3847 | } else { |
3848 | /* Not defined */ | |
93fcfe39 | 3849 | qemu_log("Trying to read invalid spr %d %03x at " |
90e189ec BS |
3850 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3851 | printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 3852 | sprn, sprn, ctx->nip); |
e06fcd75 | 3853 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 3854 | } |
79aceca5 FB |
3855 | } |
3856 | ||
99e300ef | 3857 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 3858 | { |
3fc6c082 | 3859 | gen_op_mfspr(ctx); |
76a66253 | 3860 | } |
3fc6c082 FB |
3861 | |
3862 | /* mftb */ | |
99e300ef | 3863 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
3864 | { |
3865 | gen_op_mfspr(ctx); | |
79aceca5 FB |
3866 | } |
3867 | ||
0cfe11ea | 3868 | /* mtcrf mtocrf*/ |
99e300ef | 3869 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 3870 | { |
76a66253 | 3871 | uint32_t crm, crn; |
3b46e624 | 3872 | |
76a66253 | 3873 | crm = CRM(ctx->opcode); |
8dd640e4 | 3874 | if (likely((ctx->opcode & 0x00100000))) { |
3875 | if (crm && ((crm & (crm - 1)) == 0)) { | |
3876 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 3877 | crn = ctz32 (crm); |
8dd640e4 | 3878 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
3879 | tcg_gen_shri_i32(temp, temp, crn * 4); |
3880 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 3881 | tcg_temp_free_i32(temp); |
3882 | } | |
76a66253 | 3883 | } else { |
651721b2 AJ |
3884 | TCGv_i32 temp = tcg_temp_new_i32(); |
3885 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
3886 | for (crn = 0 ; crn < 8 ; crn++) { | |
3887 | if (crm & (1 << crn)) { | |
3888 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
3889 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
3890 | } | |
3891 | } | |
a7812ae4 | 3892 | tcg_temp_free_i32(temp); |
76a66253 | 3893 | } |
79aceca5 FB |
3894 | } |
3895 | ||
3896 | /* mtmsr */ | |
426613db | 3897 | #if defined(TARGET_PPC64) |
99e300ef | 3898 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
3899 | { |
3900 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3901 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 3902 | #else |
76db3ba4 | 3903 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3904 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
3905 | return; |
3906 | } | |
be147d08 JM |
3907 | if (ctx->opcode & 0x00010000) { |
3908 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3909 | TCGv t0 = tcg_temp_new(); |
3910 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
3911 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
3912 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
3913 | tcg_temp_free(t0); | |
be147d08 | 3914 | } else { |
056b05f8 JM |
3915 | /* XXX: we need to update nip before the store |
3916 | * if we enter power saving mode, we will exit the loop | |
3917 | * directly from ppc_store_msr | |
3918 | */ | |
be147d08 | 3919 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 3920 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
3921 | /* Must stop the translation as machine state (may have) changed */ |
3922 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 3923 | gen_stop_exception(ctx); |
be147d08 | 3924 | } |
426613db JM |
3925 | #endif |
3926 | } | |
3927 | #endif | |
3928 | ||
99e300ef | 3929 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 3930 | { |
9a64fbe4 | 3931 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3932 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3933 | #else |
76db3ba4 | 3934 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3935 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3936 | return; |
9a64fbe4 | 3937 | } |
be147d08 JM |
3938 | if (ctx->opcode & 0x00010000) { |
3939 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3940 | TCGv t0 = tcg_temp_new(); |
3941 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
3942 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
3943 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
3944 | tcg_temp_free(t0); | |
be147d08 | 3945 | } else { |
8018dc63 AG |
3946 | TCGv msr = tcg_temp_new(); |
3947 | ||
056b05f8 JM |
3948 | /* XXX: we need to update nip before the store |
3949 | * if we enter power saving mode, we will exit the loop | |
3950 | * directly from ppc_store_msr | |
3951 | */ | |
be147d08 | 3952 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 3953 | #if defined(TARGET_PPC64) |
8018dc63 AG |
3954 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
3955 | #else | |
3956 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 3957 | #endif |
e5f17ac6 | 3958 | gen_helper_store_msr(cpu_env, msr); |
be147d08 | 3959 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 3960 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 3961 | gen_stop_exception(ctx); |
be147d08 | 3962 | } |
9a64fbe4 | 3963 | #endif |
79aceca5 FB |
3964 | } |
3965 | ||
3966 | /* mtspr */ | |
99e300ef | 3967 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 3968 | { |
45d827d2 | 3969 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
3970 | uint32_t sprn = SPR(ctx->opcode); |
3971 | ||
3fc6c082 | 3972 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 3973 | if (ctx->mem_idx == 2) |
be147d08 | 3974 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 3975 | else if (ctx->mem_idx) |
3fc6c082 FB |
3976 | write_cb = ctx->spr_cb[sprn].oea_write; |
3977 | else | |
9a64fbe4 | 3978 | #endif |
3fc6c082 | 3979 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
3980 | if (likely(write_cb != NULL)) { |
3981 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 3982 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
3983 | } else { |
3984 | /* Privilege exception */ | |
93fcfe39 | 3985 | qemu_log("Trying to write privileged spr %d %03x at " |
90e189ec BS |
3986 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3987 | printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx | |
3988 | "\n", sprn, sprn, ctx->nip); | |
e06fcd75 | 3989 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 3990 | } |
3fc6c082 FB |
3991 | } else { |
3992 | /* Not defined */ | |
93fcfe39 | 3993 | qemu_log("Trying to write invalid spr %d %03x at " |
90e189ec BS |
3994 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3995 | printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 3996 | sprn, sprn, ctx->nip); |
e06fcd75 | 3997 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 3998 | } |
79aceca5 FB |
3999 | } |
4000 | ||
4001 | /*** Cache management ***/ | |
99e300ef | 4002 | |
54623277 | 4003 | /* dcbf */ |
99e300ef | 4004 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4005 | { |
dac454af | 4006 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4007 | TCGv t0; |
4008 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4009 | t0 = tcg_temp_new(); | |
4010 | gen_addr_reg_index(ctx, t0); | |
4011 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4012 | tcg_temp_free(t0); |
79aceca5 FB |
4013 | } |
4014 | ||
4015 | /* dcbi (Supervisor only) */ | |
99e300ef | 4016 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4017 | { |
a541f297 | 4018 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4019 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4020 | #else |
b61f2753 | 4021 | TCGv EA, val; |
76db3ba4 | 4022 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4023 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4024 | return; |
9a64fbe4 | 4025 | } |
a7812ae4 | 4026 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4027 | gen_set_access_type(ctx, ACCESS_CACHE); |
4028 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4029 | val = tcg_temp_new(); |
76a66253 | 4030 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4031 | gen_qemu_ld8u(ctx, val, EA); |
4032 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4033 | tcg_temp_free(val); |
4034 | tcg_temp_free(EA); | |
a541f297 | 4035 | #endif |
79aceca5 FB |
4036 | } |
4037 | ||
4038 | /* dcdst */ | |
99e300ef | 4039 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4040 | { |
76a66253 | 4041 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4042 | TCGv t0; |
4043 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4044 | t0 = tcg_temp_new(); | |
4045 | gen_addr_reg_index(ctx, t0); | |
4046 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4047 | tcg_temp_free(t0); |
79aceca5 FB |
4048 | } |
4049 | ||
4050 | /* dcbt */ | |
99e300ef | 4051 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4052 | { |
0db1b20e | 4053 | /* interpreted as no-op */ |
76a66253 JM |
4054 | /* XXX: specification say this is treated as a load by the MMU |
4055 | * but does not generate any exception | |
4056 | */ | |
79aceca5 FB |
4057 | } |
4058 | ||
4059 | /* dcbtst */ | |
99e300ef | 4060 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4061 | { |
0db1b20e | 4062 | /* interpreted as no-op */ |
76a66253 JM |
4063 | /* XXX: specification say this is treated as a load by the MMU |
4064 | * but does not generate any exception | |
4065 | */ | |
79aceca5 FB |
4066 | } |
4067 | ||
4068 | /* dcbz */ | |
99e300ef | 4069 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4070 | { |
8e33944f AG |
4071 | TCGv tcgv_addr; |
4072 | TCGv_i32 tcgv_is_dcbzl; | |
4073 | int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; | |
d63001d1 | 4074 | |
76db3ba4 | 4075 | gen_set_access_type(ctx, ACCESS_CACHE); |
799a8c8d AJ |
4076 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4077 | gen_update_nip(ctx, ctx->nip - 4); | |
8e33944f AG |
4078 | tcgv_addr = tcg_temp_new(); |
4079 | tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); | |
4080 | ||
4081 | gen_addr_reg_index(ctx, tcgv_addr); | |
4082 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); | |
4083 | ||
4084 | tcg_temp_free(tcgv_addr); | |
4085 | tcg_temp_free_i32(tcgv_is_dcbzl); | |
79aceca5 FB |
4086 | } |
4087 | ||
ae1c1a3d | 4088 | /* dst / dstt */ |
99e300ef | 4089 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4090 | { |
4091 | if (rA(ctx->opcode) == 0) { | |
4092 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4093 | } else { | |
4094 | /* interpreted as no-op */ | |
4095 | } | |
4096 | } | |
4097 | ||
4098 | /* dstst /dststt */ | |
99e300ef | 4099 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4100 | { |
4101 | if (rA(ctx->opcode) == 0) { | |
4102 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4103 | } else { | |
4104 | /* interpreted as no-op */ | |
4105 | } | |
4106 | ||
4107 | } | |
4108 | ||
4109 | /* dss / dssall */ | |
99e300ef | 4110 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4111 | { |
4112 | /* interpreted as no-op */ | |
4113 | } | |
4114 | ||
79aceca5 | 4115 | /* icbi */ |
99e300ef | 4116 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4117 | { |
76db3ba4 AJ |
4118 | TCGv t0; |
4119 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4120 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4121 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4122 | t0 = tcg_temp_new(); |
4123 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4124 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4125 | tcg_temp_free(t0); |
79aceca5 FB |
4126 | } |
4127 | ||
4128 | /* Optional: */ | |
4129 | /* dcba */ | |
99e300ef | 4130 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4131 | { |
0db1b20e JM |
4132 | /* interpreted as no-op */ |
4133 | /* XXX: specification say this is treated as a store by the MMU | |
4134 | * but does not generate any exception | |
4135 | */ | |
79aceca5 FB |
4136 | } |
4137 | ||
4138 | /*** Segment register manipulation ***/ | |
4139 | /* Supervisor only: */ | |
99e300ef | 4140 | |
54623277 | 4141 | /* mfsr */ |
99e300ef | 4142 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4143 | { |
9a64fbe4 | 4144 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4145 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4146 | #else |
74d37793 | 4147 | TCGv t0; |
76db3ba4 | 4148 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4149 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4150 | return; |
9a64fbe4 | 4151 | } |
74d37793 | 4152 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4153 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4154 | tcg_temp_free(t0); |
9a64fbe4 | 4155 | #endif |
79aceca5 FB |
4156 | } |
4157 | ||
4158 | /* mfsrin */ | |
99e300ef | 4159 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4160 | { |
9a64fbe4 | 4161 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4162 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4163 | #else |
74d37793 | 4164 | TCGv t0; |
76db3ba4 | 4165 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4166 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4167 | return; |
9a64fbe4 | 4168 | } |
74d37793 AJ |
4169 | t0 = tcg_temp_new(); |
4170 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4171 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4172 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4173 | tcg_temp_free(t0); |
9a64fbe4 | 4174 | #endif |
79aceca5 FB |
4175 | } |
4176 | ||
4177 | /* mtsr */ | |
99e300ef | 4178 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4179 | { |
9a64fbe4 | 4180 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4181 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4182 | #else |
74d37793 | 4183 | TCGv t0; |
76db3ba4 | 4184 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4185 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4186 | return; |
9a64fbe4 | 4187 | } |
74d37793 | 4188 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4189 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4190 | tcg_temp_free(t0); |
9a64fbe4 | 4191 | #endif |
79aceca5 FB |
4192 | } |
4193 | ||
4194 | /* mtsrin */ | |
99e300ef | 4195 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4196 | { |
9a64fbe4 | 4197 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4198 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4199 | #else |
74d37793 | 4200 | TCGv t0; |
76db3ba4 | 4201 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4202 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4203 | return; |
9a64fbe4 | 4204 | } |
74d37793 AJ |
4205 | t0 = tcg_temp_new(); |
4206 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4207 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4208 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4209 | tcg_temp_free(t0); |
9a64fbe4 | 4210 | #endif |
79aceca5 FB |
4211 | } |
4212 | ||
12de9a39 JM |
4213 | #if defined(TARGET_PPC64) |
4214 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4215 | |
54623277 | 4216 | /* mfsr */ |
e8eaa2c0 | 4217 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4218 | { |
4219 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4220 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4221 | #else |
74d37793 | 4222 | TCGv t0; |
76db3ba4 | 4223 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4224 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4225 | return; |
4226 | } | |
74d37793 | 4227 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4228 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4229 | tcg_temp_free(t0); |
12de9a39 JM |
4230 | #endif |
4231 | } | |
4232 | ||
4233 | /* mfsrin */ | |
e8eaa2c0 | 4234 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4235 | { |
4236 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4237 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4238 | #else |
74d37793 | 4239 | TCGv t0; |
76db3ba4 | 4240 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4241 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4242 | return; |
4243 | } | |
74d37793 AJ |
4244 | t0 = tcg_temp_new(); |
4245 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4246 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4247 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4248 | tcg_temp_free(t0); |
12de9a39 JM |
4249 | #endif |
4250 | } | |
4251 | ||
4252 | /* mtsr */ | |
e8eaa2c0 | 4253 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4254 | { |
4255 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4256 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4257 | #else |
74d37793 | 4258 | TCGv t0; |
76db3ba4 | 4259 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4260 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4261 | return; |
4262 | } | |
74d37793 | 4263 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4264 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4265 | tcg_temp_free(t0); |
12de9a39 JM |
4266 | #endif |
4267 | } | |
4268 | ||
4269 | /* mtsrin */ | |
e8eaa2c0 | 4270 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4271 | { |
4272 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4273 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4274 | #else |
74d37793 | 4275 | TCGv t0; |
76db3ba4 | 4276 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4277 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4278 | return; |
4279 | } | |
74d37793 AJ |
4280 | t0 = tcg_temp_new(); |
4281 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4282 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4283 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4284 | tcg_temp_free(t0); |
12de9a39 JM |
4285 | #endif |
4286 | } | |
f6b868fc BS |
4287 | |
4288 | /* slbmte */ | |
e8eaa2c0 | 4289 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4290 | { |
4291 | #if defined(CONFIG_USER_ONLY) | |
4292 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4293 | #else | |
4294 | if (unlikely(!ctx->mem_idx)) { | |
4295 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4296 | return; | |
4297 | } | |
c6c7cf05 BS |
4298 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4299 | cpu_gpr[rS(ctx->opcode)]); | |
f6b868fc BS |
4300 | #endif |
4301 | } | |
4302 | ||
efdef95f DG |
4303 | static void gen_slbmfee(DisasContext *ctx) |
4304 | { | |
4305 | #if defined(CONFIG_USER_ONLY) | |
4306 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4307 | #else | |
4308 | if (unlikely(!ctx->mem_idx)) { | |
4309 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4310 | return; | |
4311 | } | |
c6c7cf05 | 4312 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4313 | cpu_gpr[rB(ctx->opcode)]); |
4314 | #endif | |
4315 | } | |
4316 | ||
4317 | static void gen_slbmfev(DisasContext *ctx) | |
4318 | { | |
4319 | #if defined(CONFIG_USER_ONLY) | |
4320 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4321 | #else | |
4322 | if (unlikely(!ctx->mem_idx)) { | |
4323 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4324 | return; | |
4325 | } | |
c6c7cf05 | 4326 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4327 | cpu_gpr[rB(ctx->opcode)]); |
4328 | #endif | |
4329 | } | |
12de9a39 JM |
4330 | #endif /* defined(TARGET_PPC64) */ |
4331 | ||
79aceca5 | 4332 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4333 | /* Optional & mem_idx only: */ |
99e300ef | 4334 | |
54623277 | 4335 | /* tlbia */ |
99e300ef | 4336 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4337 | { |
9a64fbe4 | 4338 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4339 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4340 | #else |
76db3ba4 | 4341 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4342 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4343 | return; |
9a64fbe4 | 4344 | } |
c6c7cf05 | 4345 | gen_helper_tlbia(cpu_env); |
9a64fbe4 | 4346 | #endif |
79aceca5 FB |
4347 | } |
4348 | ||
bf14b1ce | 4349 | /* tlbiel */ |
99e300ef | 4350 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4351 | { |
4352 | #if defined(CONFIG_USER_ONLY) | |
4353 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4354 | #else | |
4355 | if (unlikely(!ctx->mem_idx)) { | |
4356 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4357 | return; | |
4358 | } | |
c6c7cf05 | 4359 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
bf14b1ce BS |
4360 | #endif |
4361 | } | |
4362 | ||
79aceca5 | 4363 | /* tlbie */ |
99e300ef | 4364 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4365 | { |
9a64fbe4 | 4366 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4367 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4368 | #else |
76db3ba4 | 4369 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4370 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4371 | return; |
9a64fbe4 | 4372 | } |
d9bce9d9 | 4373 | #if defined(TARGET_PPC64) |
74d37793 AJ |
4374 | if (!ctx->sf_mode) { |
4375 | TCGv t0 = tcg_temp_new(); | |
4376 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4377 | gen_helper_tlbie(cpu_env, t0); |
74d37793 AJ |
4378 | tcg_temp_free(t0); |
4379 | } else | |
d9bce9d9 | 4380 | #endif |
c6c7cf05 | 4381 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9a64fbe4 | 4382 | #endif |
79aceca5 FB |
4383 | } |
4384 | ||
4385 | /* tlbsync */ | |
99e300ef | 4386 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4387 | { |
9a64fbe4 | 4388 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4389 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4390 | #else |
76db3ba4 | 4391 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4392 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4393 | return; |
9a64fbe4 FB |
4394 | } |
4395 | /* This has no effect: it should ensure that all previous | |
4396 | * tlbie have completed | |
4397 | */ | |
e06fcd75 | 4398 | gen_stop_exception(ctx); |
9a64fbe4 | 4399 | #endif |
79aceca5 FB |
4400 | } |
4401 | ||
426613db JM |
4402 | #if defined(TARGET_PPC64) |
4403 | /* slbia */ | |
99e300ef | 4404 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4405 | { |
4406 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4407 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4408 | #else |
76db3ba4 | 4409 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4410 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4411 | return; |
4412 | } | |
c6c7cf05 | 4413 | gen_helper_slbia(cpu_env); |
426613db JM |
4414 | #endif |
4415 | } | |
4416 | ||
4417 | /* slbie */ | |
99e300ef | 4418 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4419 | { |
4420 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4421 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4422 | #else |
76db3ba4 | 4423 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4424 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4425 | return; |
4426 | } | |
c6c7cf05 | 4427 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4428 | #endif |
4429 | } | |
4430 | #endif | |
4431 | ||
79aceca5 FB |
4432 | /*** External control ***/ |
4433 | /* Optional: */ | |
99e300ef | 4434 | |
54623277 | 4435 | /* eciwx */ |
99e300ef | 4436 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4437 | { |
76db3ba4 | 4438 | TCGv t0; |
fa407c03 | 4439 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4440 | gen_set_access_type(ctx, ACCESS_EXT); |
4441 | t0 = tcg_temp_new(); | |
4442 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4443 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4444 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4445 | tcg_temp_free(t0); |
76a66253 JM |
4446 | } |
4447 | ||
4448 | /* ecowx */ | |
99e300ef | 4449 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4450 | { |
76db3ba4 | 4451 | TCGv t0; |
fa407c03 | 4452 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4453 | gen_set_access_type(ctx, ACCESS_EXT); |
4454 | t0 = tcg_temp_new(); | |
4455 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4456 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4457 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4458 | tcg_temp_free(t0); |
76a66253 JM |
4459 | } |
4460 | ||
4461 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4462 | |
54623277 | 4463 | /* abs - abs. */ |
99e300ef | 4464 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4465 | { |
22e0e173 AJ |
4466 | int l1 = gen_new_label(); |
4467 | int l2 = gen_new_label(); | |
4468 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4469 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4470 | tcg_gen_br(l2); | |
4471 | gen_set_label(l1); | |
4472 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4473 | gen_set_label(l2); | |
76a66253 | 4474 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4475 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4476 | } |
4477 | ||
4478 | /* abso - abso. */ | |
99e300ef | 4479 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4480 | { |
22e0e173 AJ |
4481 | int l1 = gen_new_label(); |
4482 | int l2 = gen_new_label(); | |
4483 | int l3 = gen_new_label(); | |
4484 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4485 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4486 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4487 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4488 | tcg_gen_movi_tl(cpu_ov, 1); |
4489 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4490 | tcg_gen_br(l2); |
4491 | gen_set_label(l1); | |
4492 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4493 | tcg_gen_br(l3); | |
4494 | gen_set_label(l2); | |
4495 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4496 | gen_set_label(l3); | |
76a66253 | 4497 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4498 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4499 | } |
4500 | ||
4501 | /* clcs */ | |
99e300ef | 4502 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4503 | { |
22e0e173 | 4504 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4505 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4506 | tcg_temp_free_i32(t0); |
c7697e1f | 4507 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4508 | } |
4509 | ||
4510 | /* div - div. */ | |
99e300ef | 4511 | static void gen_div(DisasContext *ctx) |
76a66253 | 4512 | { |
d15f74fb BS |
4513 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4514 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4515 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4516 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4517 | } |
4518 | ||
4519 | /* divo - divo. */ | |
99e300ef | 4520 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4521 | { |
d15f74fb BS |
4522 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4523 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4524 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4525 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4526 | } |
4527 | ||
4528 | /* divs - divs. */ | |
99e300ef | 4529 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4530 | { |
d15f74fb BS |
4531 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4532 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4533 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4534 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4535 | } |
4536 | ||
4537 | /* divso - divso. */ | |
99e300ef | 4538 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4539 | { |
d15f74fb BS |
4540 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4541 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4542 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4543 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4544 | } |
4545 | ||
4546 | /* doz - doz. */ | |
99e300ef | 4547 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4548 | { |
22e0e173 AJ |
4549 | int l1 = gen_new_label(); |
4550 | int l2 = gen_new_label(); | |
4551 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4552 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4553 | tcg_gen_br(l2); | |
4554 | gen_set_label(l1); | |
4555 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4556 | gen_set_label(l2); | |
76a66253 | 4557 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4558 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4559 | } |
4560 | ||
4561 | /* dozo - dozo. */ | |
99e300ef | 4562 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4563 | { |
22e0e173 AJ |
4564 | int l1 = gen_new_label(); |
4565 | int l2 = gen_new_label(); | |
4566 | TCGv t0 = tcg_temp_new(); | |
4567 | TCGv t1 = tcg_temp_new(); | |
4568 | TCGv t2 = tcg_temp_new(); | |
4569 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4570 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4571 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4572 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4573 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4574 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4575 | tcg_gen_andc_tl(t1, t1, t2); | |
4576 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4577 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4578 | tcg_gen_movi_tl(cpu_ov, 1); |
4579 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4580 | tcg_gen_br(l2); |
4581 | gen_set_label(l1); | |
4582 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4583 | gen_set_label(l2); | |
4584 | tcg_temp_free(t0); | |
4585 | tcg_temp_free(t1); | |
4586 | tcg_temp_free(t2); | |
76a66253 | 4587 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4588 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4589 | } |
4590 | ||
4591 | /* dozi */ | |
99e300ef | 4592 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4593 | { |
22e0e173 AJ |
4594 | target_long simm = SIMM(ctx->opcode); |
4595 | int l1 = gen_new_label(); | |
4596 | int l2 = gen_new_label(); | |
4597 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
4598 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4599 | tcg_gen_br(l2); | |
4600 | gen_set_label(l1); | |
4601 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4602 | gen_set_label(l2); | |
4603 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4604 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4605 | } |
4606 | ||
76a66253 | 4607 | /* lscbx - lscbx. */ |
99e300ef | 4608 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4609 | { |
bdb4b689 AJ |
4610 | TCGv t0 = tcg_temp_new(); |
4611 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4612 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4613 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4614 | |
76db3ba4 | 4615 | gen_addr_reg_index(ctx, t0); |
76a66253 | 4616 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 4617 | gen_update_nip(ctx, ctx->nip - 4); |
2f5a189c | 4618 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4619 | tcg_temp_free_i32(t1); |
4620 | tcg_temp_free_i32(t2); | |
4621 | tcg_temp_free_i32(t3); | |
3d7b417e | 4622 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4623 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4624 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4625 | gen_set_Rc0(ctx, t0); |
4626 | tcg_temp_free(t0); | |
76a66253 JM |
4627 | } |
4628 | ||
4629 | /* maskg - maskg. */ | |
99e300ef | 4630 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4631 | { |
22e0e173 AJ |
4632 | int l1 = gen_new_label(); |
4633 | TCGv t0 = tcg_temp_new(); | |
4634 | TCGv t1 = tcg_temp_new(); | |
4635 | TCGv t2 = tcg_temp_new(); | |
4636 | TCGv t3 = tcg_temp_new(); | |
4637 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4638 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4639 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4640 | tcg_gen_addi_tl(t2, t0, 1); | |
4641 | tcg_gen_shr_tl(t2, t3, t2); | |
4642 | tcg_gen_shr_tl(t3, t3, t1); | |
4643 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4644 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4645 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4646 | gen_set_label(l1); | |
4647 | tcg_temp_free(t0); | |
4648 | tcg_temp_free(t1); | |
4649 | tcg_temp_free(t2); | |
4650 | tcg_temp_free(t3); | |
76a66253 | 4651 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4652 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4653 | } |
4654 | ||
4655 | /* maskir - maskir. */ | |
99e300ef | 4656 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4657 | { |
22e0e173 AJ |
4658 | TCGv t0 = tcg_temp_new(); |
4659 | TCGv t1 = tcg_temp_new(); | |
4660 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4661 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4662 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4663 | tcg_temp_free(t0); | |
4664 | tcg_temp_free(t1); | |
76a66253 | 4665 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4666 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4667 | } |
4668 | ||
4669 | /* mul - mul. */ | |
99e300ef | 4670 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4671 | { |
22e0e173 AJ |
4672 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4673 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4674 | TCGv t2 = tcg_temp_new(); | |
4675 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4676 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4677 | tcg_gen_mul_i64(t0, t0, t1); | |
4678 | tcg_gen_trunc_i64_tl(t2, t0); | |
4679 | gen_store_spr(SPR_MQ, t2); | |
4680 | tcg_gen_shri_i64(t1, t0, 32); | |
4681 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4682 | tcg_temp_free_i64(t0); | |
4683 | tcg_temp_free_i64(t1); | |
4684 | tcg_temp_free(t2); | |
76a66253 | 4685 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4686 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4687 | } |
4688 | ||
4689 | /* mulo - mulo. */ | |
99e300ef | 4690 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4691 | { |
22e0e173 AJ |
4692 | int l1 = gen_new_label(); |
4693 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
4694 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4695 | TCGv t2 = tcg_temp_new(); | |
4696 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4697 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4698 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4699 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4700 | tcg_gen_mul_i64(t0, t0, t1); | |
4701 | tcg_gen_trunc_i64_tl(t2, t0); | |
4702 | gen_store_spr(SPR_MQ, t2); | |
4703 | tcg_gen_shri_i64(t1, t0, 32); | |
4704 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4705 | tcg_gen_ext32s_i64(t1, t0); | |
4706 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
4707 | tcg_gen_movi_tl(cpu_ov, 1); |
4708 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4709 | gen_set_label(l1); |
4710 | tcg_temp_free_i64(t0); | |
4711 | tcg_temp_free_i64(t1); | |
4712 | tcg_temp_free(t2); | |
76a66253 | 4713 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4714 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4715 | } |
4716 | ||
4717 | /* nabs - nabs. */ | |
99e300ef | 4718 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4719 | { |
22e0e173 AJ |
4720 | int l1 = gen_new_label(); |
4721 | int l2 = gen_new_label(); | |
4722 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4723 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4724 | tcg_gen_br(l2); | |
4725 | gen_set_label(l1); | |
4726 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4727 | gen_set_label(l2); | |
76a66253 | 4728 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4729 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4730 | } |
4731 | ||
4732 | /* nabso - nabso. */ | |
99e300ef | 4733 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4734 | { |
22e0e173 AJ |
4735 | int l1 = gen_new_label(); |
4736 | int l2 = gen_new_label(); | |
4737 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4738 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4739 | tcg_gen_br(l2); | |
4740 | gen_set_label(l1); | |
4741 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4742 | gen_set_label(l2); | |
4743 | /* nabs never overflows */ | |
da91a00f | 4744 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 4745 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4746 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4747 | } |
4748 | ||
4749 | /* rlmi - rlmi. */ | |
99e300ef | 4750 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4751 | { |
7487953d AJ |
4752 | uint32_t mb = MB(ctx->opcode); |
4753 | uint32_t me = ME(ctx->opcode); | |
4754 | TCGv t0 = tcg_temp_new(); | |
4755 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4756 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4757 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4758 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4759 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4760 | tcg_temp_free(t0); | |
76a66253 | 4761 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4762 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4763 | } |
4764 | ||
4765 | /* rrib - rrib. */ | |
99e300ef | 4766 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4767 | { |
7487953d AJ |
4768 | TCGv t0 = tcg_temp_new(); |
4769 | TCGv t1 = tcg_temp_new(); | |
4770 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4771 | tcg_gen_movi_tl(t1, 0x80000000); | |
4772 | tcg_gen_shr_tl(t1, t1, t0); | |
4773 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4774 | tcg_gen_and_tl(t0, t0, t1); | |
4775 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4776 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4777 | tcg_temp_free(t0); | |
4778 | tcg_temp_free(t1); | |
76a66253 | 4779 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4780 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4781 | } |
4782 | ||
4783 | /* sle - sle. */ | |
99e300ef | 4784 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4785 | { |
7487953d AJ |
4786 | TCGv t0 = tcg_temp_new(); |
4787 | TCGv t1 = tcg_temp_new(); | |
4788 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4789 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4790 | tcg_gen_subfi_tl(t1, 32, t1); | |
4791 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4792 | tcg_gen_or_tl(t1, t0, t1); | |
4793 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4794 | gen_store_spr(SPR_MQ, t1); | |
4795 | tcg_temp_free(t0); | |
4796 | tcg_temp_free(t1); | |
76a66253 | 4797 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4798 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4799 | } |
4800 | ||
4801 | /* sleq - sleq. */ | |
99e300ef | 4802 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4803 | { |
7487953d AJ |
4804 | TCGv t0 = tcg_temp_new(); |
4805 | TCGv t1 = tcg_temp_new(); | |
4806 | TCGv t2 = tcg_temp_new(); | |
4807 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4808 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
4809 | tcg_gen_shl_tl(t2, t2, t0); | |
4810 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4811 | gen_load_spr(t1, SPR_MQ); | |
4812 | gen_store_spr(SPR_MQ, t0); | |
4813 | tcg_gen_and_tl(t0, t0, t2); | |
4814 | tcg_gen_andc_tl(t1, t1, t2); | |
4815 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4816 | tcg_temp_free(t0); | |
4817 | tcg_temp_free(t1); | |
4818 | tcg_temp_free(t2); | |
76a66253 | 4819 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4820 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4821 | } |
4822 | ||
4823 | /* sliq - sliq. */ | |
99e300ef | 4824 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 4825 | { |
7487953d AJ |
4826 | int sh = SH(ctx->opcode); |
4827 | TCGv t0 = tcg_temp_new(); | |
4828 | TCGv t1 = tcg_temp_new(); | |
4829 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4830 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4831 | tcg_gen_or_tl(t1, t0, t1); | |
4832 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4833 | gen_store_spr(SPR_MQ, t1); | |
4834 | tcg_temp_free(t0); | |
4835 | tcg_temp_free(t1); | |
76a66253 | 4836 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4837 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4838 | } |
4839 | ||
4840 | /* slliq - slliq. */ | |
99e300ef | 4841 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 4842 | { |
7487953d AJ |
4843 | int sh = SH(ctx->opcode); |
4844 | TCGv t0 = tcg_temp_new(); | |
4845 | TCGv t1 = tcg_temp_new(); | |
4846 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4847 | gen_load_spr(t1, SPR_MQ); | |
4848 | gen_store_spr(SPR_MQ, t0); | |
4849 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
4850 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
4851 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4852 | tcg_temp_free(t0); | |
4853 | tcg_temp_free(t1); | |
76a66253 | 4854 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4855 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4856 | } |
4857 | ||
4858 | /* sllq - sllq. */ | |
99e300ef | 4859 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 4860 | { |
7487953d AJ |
4861 | int l1 = gen_new_label(); |
4862 | int l2 = gen_new_label(); | |
4863 | TCGv t0 = tcg_temp_local_new(); | |
4864 | TCGv t1 = tcg_temp_local_new(); | |
4865 | TCGv t2 = tcg_temp_local_new(); | |
4866 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4867 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4868 | tcg_gen_shl_tl(t1, t1, t2); | |
4869 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4870 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
4871 | gen_load_spr(t0, SPR_MQ); | |
4872 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4873 | tcg_gen_br(l2); | |
4874 | gen_set_label(l1); | |
4875 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4876 | gen_load_spr(t2, SPR_MQ); | |
4877 | tcg_gen_andc_tl(t1, t2, t1); | |
4878 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4879 | gen_set_label(l2); | |
4880 | tcg_temp_free(t0); | |
4881 | tcg_temp_free(t1); | |
4882 | tcg_temp_free(t2); | |
76a66253 | 4883 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4884 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4885 | } |
4886 | ||
4887 | /* slq - slq. */ | |
99e300ef | 4888 | static void gen_slq(DisasContext *ctx) |
76a66253 | 4889 | { |
7487953d AJ |
4890 | int l1 = gen_new_label(); |
4891 | TCGv t0 = tcg_temp_new(); | |
4892 | TCGv t1 = tcg_temp_new(); | |
4893 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4894 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4895 | tcg_gen_subfi_tl(t1, 32, t1); | |
4896 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4897 | tcg_gen_or_tl(t1, t0, t1); | |
4898 | gen_store_spr(SPR_MQ, t1); | |
4899 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4900 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4901 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
4902 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
4903 | gen_set_label(l1); | |
4904 | tcg_temp_free(t0); | |
4905 | tcg_temp_free(t1); | |
76a66253 | 4906 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4907 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4908 | } |
4909 | ||
d9bce9d9 | 4910 | /* sraiq - sraiq. */ |
99e300ef | 4911 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 4912 | { |
7487953d AJ |
4913 | int sh = SH(ctx->opcode); |
4914 | int l1 = gen_new_label(); | |
4915 | TCGv t0 = tcg_temp_new(); | |
4916 | TCGv t1 = tcg_temp_new(); | |
4917 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4918 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4919 | tcg_gen_or_tl(t0, t0, t1); | |
4920 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 4921 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
4922 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
4923 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 4924 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
4925 | gen_set_label(l1); |
4926 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
4927 | tcg_temp_free(t0); | |
4928 | tcg_temp_free(t1); | |
76a66253 | 4929 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4930 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4931 | } |
4932 | ||
4933 | /* sraq - sraq. */ | |
99e300ef | 4934 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 4935 | { |
7487953d AJ |
4936 | int l1 = gen_new_label(); |
4937 | int l2 = gen_new_label(); | |
4938 | TCGv t0 = tcg_temp_new(); | |
4939 | TCGv t1 = tcg_temp_local_new(); | |
4940 | TCGv t2 = tcg_temp_local_new(); | |
4941 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4942 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4943 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
4944 | tcg_gen_subfi_tl(t2, 32, t2); | |
4945 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
4946 | tcg_gen_or_tl(t0, t0, t2); | |
4947 | gen_store_spr(SPR_MQ, t0); | |
4948 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4949 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
4950 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
4951 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
4952 | gen_set_label(l1); | |
4953 | tcg_temp_free(t0); | |
4954 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 4955 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
4956 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
4957 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 4958 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
4959 | gen_set_label(l2); |
4960 | tcg_temp_free(t1); | |
4961 | tcg_temp_free(t2); | |
76a66253 | 4962 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4963 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4964 | } |
4965 | ||
4966 | /* sre - sre. */ | |
99e300ef | 4967 | static void gen_sre(DisasContext *ctx) |
76a66253 | 4968 | { |
7487953d AJ |
4969 | TCGv t0 = tcg_temp_new(); |
4970 | TCGv t1 = tcg_temp_new(); | |
4971 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4972 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4973 | tcg_gen_subfi_tl(t1, 32, t1); | |
4974 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4975 | tcg_gen_or_tl(t1, t0, t1); | |
4976 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4977 | gen_store_spr(SPR_MQ, t1); | |
4978 | tcg_temp_free(t0); | |
4979 | tcg_temp_free(t1); | |
76a66253 | 4980 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4981 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4982 | } |
4983 | ||
4984 | /* srea - srea. */ | |
99e300ef | 4985 | static void gen_srea(DisasContext *ctx) |
76a66253 | 4986 | { |
7487953d AJ |
4987 | TCGv t0 = tcg_temp_new(); |
4988 | TCGv t1 = tcg_temp_new(); | |
4989 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4990 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4991 | gen_store_spr(SPR_MQ, t0); | |
4992 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
4993 | tcg_temp_free(t0); | |
4994 | tcg_temp_free(t1); | |
76a66253 | 4995 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4996 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4997 | } |
4998 | ||
4999 | /* sreq */ | |
99e300ef | 5000 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5001 | { |
7487953d AJ |
5002 | TCGv t0 = tcg_temp_new(); |
5003 | TCGv t1 = tcg_temp_new(); | |
5004 | TCGv t2 = tcg_temp_new(); | |
5005 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5006 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5007 | tcg_gen_shr_tl(t1, t1, t0); | |
5008 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5009 | gen_load_spr(t2, SPR_MQ); | |
5010 | gen_store_spr(SPR_MQ, t0); | |
5011 | tcg_gen_and_tl(t0, t0, t1); | |
5012 | tcg_gen_andc_tl(t2, t2, t1); | |
5013 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5014 | tcg_temp_free(t0); | |
5015 | tcg_temp_free(t1); | |
5016 | tcg_temp_free(t2); | |
76a66253 | 5017 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5018 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5019 | } |
5020 | ||
5021 | /* sriq */ | |
99e300ef | 5022 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5023 | { |
7487953d AJ |
5024 | int sh = SH(ctx->opcode); |
5025 | TCGv t0 = tcg_temp_new(); | |
5026 | TCGv t1 = tcg_temp_new(); | |
5027 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5028 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5029 | tcg_gen_or_tl(t1, t0, t1); | |
5030 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5031 | gen_store_spr(SPR_MQ, t1); | |
5032 | tcg_temp_free(t0); | |
5033 | tcg_temp_free(t1); | |
76a66253 | 5034 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5035 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5036 | } |
5037 | ||
5038 | /* srliq */ | |
99e300ef | 5039 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5040 | { |
7487953d AJ |
5041 | int sh = SH(ctx->opcode); |
5042 | TCGv t0 = tcg_temp_new(); | |
5043 | TCGv t1 = tcg_temp_new(); | |
5044 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5045 | gen_load_spr(t1, SPR_MQ); | |
5046 | gen_store_spr(SPR_MQ, t0); | |
5047 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5048 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5049 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5050 | tcg_temp_free(t0); | |
5051 | tcg_temp_free(t1); | |
76a66253 | 5052 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5053 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5054 | } |
5055 | ||
5056 | /* srlq */ | |
99e300ef | 5057 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5058 | { |
7487953d AJ |
5059 | int l1 = gen_new_label(); |
5060 | int l2 = gen_new_label(); | |
5061 | TCGv t0 = tcg_temp_local_new(); | |
5062 | TCGv t1 = tcg_temp_local_new(); | |
5063 | TCGv t2 = tcg_temp_local_new(); | |
5064 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5065 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5066 | tcg_gen_shr_tl(t2, t1, t2); | |
5067 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5068 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5069 | gen_load_spr(t0, SPR_MQ); | |
5070 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5071 | tcg_gen_br(l2); | |
5072 | gen_set_label(l1); | |
5073 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5074 | tcg_gen_and_tl(t0, t0, t2); | |
5075 | gen_load_spr(t1, SPR_MQ); | |
5076 | tcg_gen_andc_tl(t1, t1, t2); | |
5077 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5078 | gen_set_label(l2); | |
5079 | tcg_temp_free(t0); | |
5080 | tcg_temp_free(t1); | |
5081 | tcg_temp_free(t2); | |
76a66253 | 5082 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5083 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5084 | } |
5085 | ||
5086 | /* srq */ | |
99e300ef | 5087 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5088 | { |
7487953d AJ |
5089 | int l1 = gen_new_label(); |
5090 | TCGv t0 = tcg_temp_new(); | |
5091 | TCGv t1 = tcg_temp_new(); | |
5092 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5093 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5094 | tcg_gen_subfi_tl(t1, 32, t1); | |
5095 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5096 | tcg_gen_or_tl(t1, t0, t1); | |
5097 | gen_store_spr(SPR_MQ, t1); | |
5098 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5099 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5100 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5101 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5102 | gen_set_label(l1); | |
5103 | tcg_temp_free(t0); | |
5104 | tcg_temp_free(t1); | |
76a66253 | 5105 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5106 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5107 | } |
5108 | ||
5109 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5110 | |
54623277 | 5111 | /* dsa */ |
99e300ef | 5112 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5113 | { |
5114 | /* XXX: TODO */ | |
e06fcd75 | 5115 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5116 | } |
5117 | ||
5118 | /* esa */ | |
99e300ef | 5119 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5120 | { |
5121 | /* XXX: TODO */ | |
e06fcd75 | 5122 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5123 | } |
5124 | ||
5125 | /* mfrom */ | |
99e300ef | 5126 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5127 | { |
5128 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5129 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5130 | #else |
76db3ba4 | 5131 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5132 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5133 | return; |
5134 | } | |
cf02a65c | 5135 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5136 | #endif |
5137 | } | |
5138 | ||
5139 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5140 | |
54623277 | 5141 | /* tlbld */ |
e8eaa2c0 | 5142 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5143 | { |
5144 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5145 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5146 | #else |
76db3ba4 | 5147 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5148 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5149 | return; |
5150 | } | |
c6c7cf05 | 5151 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5152 | #endif |
5153 | } | |
5154 | ||
5155 | /* tlbli */ | |
e8eaa2c0 | 5156 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5157 | { |
5158 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5159 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5160 | #else |
76db3ba4 | 5161 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5162 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5163 | return; |
5164 | } | |
c6c7cf05 | 5165 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5166 | #endif |
5167 | } | |
5168 | ||
7dbe11ac | 5169 | /* 74xx TLB management */ |
e8eaa2c0 | 5170 | |
54623277 | 5171 | /* tlbld */ |
e8eaa2c0 | 5172 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5173 | { |
5174 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5175 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5176 | #else |
76db3ba4 | 5177 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5178 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5179 | return; |
5180 | } | |
c6c7cf05 | 5181 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5182 | #endif |
5183 | } | |
5184 | ||
5185 | /* tlbli */ | |
e8eaa2c0 | 5186 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5187 | { |
5188 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5189 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5190 | #else |
76db3ba4 | 5191 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5192 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5193 | return; |
5194 | } | |
c6c7cf05 | 5195 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5196 | #endif |
5197 | } | |
5198 | ||
76a66253 | 5199 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5200 | |
54623277 | 5201 | /* clf */ |
99e300ef | 5202 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5203 | { |
5204 | /* Cache line flush: implemented as no-op */ | |
5205 | } | |
5206 | ||
5207 | /* cli */ | |
99e300ef | 5208 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5209 | { |
7f75ffd3 | 5210 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5211 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5212 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5213 | #else |
76db3ba4 | 5214 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5215 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5216 | return; |
5217 | } | |
5218 | #endif | |
5219 | } | |
5220 | ||
5221 | /* dclst */ | |
99e300ef | 5222 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5223 | { |
5224 | /* Data cache line store: treated as no-op */ | |
5225 | } | |
5226 | ||
99e300ef | 5227 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5228 | { |
5229 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5230 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5231 | #else |
74d37793 AJ |
5232 | int ra = rA(ctx->opcode); |
5233 | int rd = rD(ctx->opcode); | |
5234 | TCGv t0; | |
76db3ba4 | 5235 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5236 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5237 | return; |
5238 | } | |
74d37793 | 5239 | t0 = tcg_temp_new(); |
76db3ba4 | 5240 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5241 | tcg_gen_shri_tl(t0, t0, 28); |
5242 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5243 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5244 | tcg_temp_free(t0); |
76a66253 | 5245 | if (ra != 0 && ra != rd) |
74d37793 | 5246 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5247 | #endif |
5248 | } | |
5249 | ||
99e300ef | 5250 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5251 | { |
5252 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5253 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5254 | #else |
22e0e173 | 5255 | TCGv t0; |
76db3ba4 | 5256 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5257 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5258 | return; |
5259 | } | |
22e0e173 | 5260 | t0 = tcg_temp_new(); |
76db3ba4 | 5261 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5262 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5263 | tcg_temp_free(t0); |
76a66253 JM |
5264 | #endif |
5265 | } | |
5266 | ||
99e300ef | 5267 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5268 | { |
5269 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5270 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5271 | #else |
76db3ba4 | 5272 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5273 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5274 | return; |
5275 | } | |
e5f17ac6 | 5276 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5277 | gen_sync_exception(ctx); |
76a66253 JM |
5278 | #endif |
5279 | } | |
5280 | ||
5281 | /* svc is not implemented for now */ | |
5282 | ||
5283 | /* POWER2 specific instructions */ | |
5284 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5285 | |
5286 | /* lfq */ | |
99e300ef | 5287 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5288 | { |
01a4afeb | 5289 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5290 | TCGv t0; |
5291 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5292 | t0 = tcg_temp_new(); | |
5293 | gen_addr_imm_index(ctx, t0, 0); | |
5294 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5295 | gen_addr_add(ctx, t0, t0, 8); | |
5296 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5297 | tcg_temp_free(t0); |
76a66253 JM |
5298 | } |
5299 | ||
5300 | /* lfqu */ | |
99e300ef | 5301 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5302 | { |
5303 | int ra = rA(ctx->opcode); | |
01a4afeb | 5304 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5305 | TCGv t0, t1; |
5306 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5307 | t0 = tcg_temp_new(); | |
5308 | t1 = tcg_temp_new(); | |
5309 | gen_addr_imm_index(ctx, t0, 0); | |
5310 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5311 | gen_addr_add(ctx, t1, t0, 8); | |
5312 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5313 | if (ra != 0) |
01a4afeb AJ |
5314 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5315 | tcg_temp_free(t0); | |
5316 | tcg_temp_free(t1); | |
76a66253 JM |
5317 | } |
5318 | ||
5319 | /* lfqux */ | |
99e300ef | 5320 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5321 | { |
5322 | int ra = rA(ctx->opcode); | |
01a4afeb | 5323 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5324 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5325 | TCGv t0, t1; | |
5326 | t0 = tcg_temp_new(); | |
5327 | gen_addr_reg_index(ctx, t0); | |
5328 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5329 | t1 = tcg_temp_new(); | |
5330 | gen_addr_add(ctx, t1, t0, 8); | |
5331 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5332 | tcg_temp_free(t1); | |
76a66253 | 5333 | if (ra != 0) |
01a4afeb AJ |
5334 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5335 | tcg_temp_free(t0); | |
76a66253 JM |
5336 | } |
5337 | ||
5338 | /* lfqx */ | |
99e300ef | 5339 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5340 | { |
01a4afeb | 5341 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5342 | TCGv t0; |
5343 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5344 | t0 = tcg_temp_new(); | |
5345 | gen_addr_reg_index(ctx, t0); | |
5346 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5347 | gen_addr_add(ctx, t0, t0, 8); | |
5348 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5349 | tcg_temp_free(t0); |
76a66253 JM |
5350 | } |
5351 | ||
5352 | /* stfq */ | |
99e300ef | 5353 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5354 | { |
01a4afeb | 5355 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5356 | TCGv t0; |
5357 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5358 | t0 = tcg_temp_new(); | |
5359 | gen_addr_imm_index(ctx, t0, 0); | |
5360 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5361 | gen_addr_add(ctx, t0, t0, 8); | |
5362 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5363 | tcg_temp_free(t0); |
76a66253 JM |
5364 | } |
5365 | ||
5366 | /* stfqu */ | |
99e300ef | 5367 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5368 | { |
5369 | int ra = rA(ctx->opcode); | |
01a4afeb | 5370 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5371 | TCGv t0, t1; |
5372 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5373 | t0 = tcg_temp_new(); | |
5374 | gen_addr_imm_index(ctx, t0, 0); | |
5375 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5376 | t1 = tcg_temp_new(); | |
5377 | gen_addr_add(ctx, t1, t0, 8); | |
5378 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5379 | tcg_temp_free(t1); | |
76a66253 | 5380 | if (ra != 0) |
01a4afeb AJ |
5381 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5382 | tcg_temp_free(t0); | |
76a66253 JM |
5383 | } |
5384 | ||
5385 | /* stfqux */ | |
99e300ef | 5386 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5387 | { |
5388 | int ra = rA(ctx->opcode); | |
01a4afeb | 5389 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5390 | TCGv t0, t1; |
5391 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5392 | t0 = tcg_temp_new(); | |
5393 | gen_addr_reg_index(ctx, t0); | |
5394 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5395 | t1 = tcg_temp_new(); | |
5396 | gen_addr_add(ctx, t1, t0, 8); | |
5397 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5398 | tcg_temp_free(t1); | |
76a66253 | 5399 | if (ra != 0) |
01a4afeb AJ |
5400 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5401 | tcg_temp_free(t0); | |
76a66253 JM |
5402 | } |
5403 | ||
5404 | /* stfqx */ | |
99e300ef | 5405 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5406 | { |
01a4afeb | 5407 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5408 | TCGv t0; |
5409 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5410 | t0 = tcg_temp_new(); | |
5411 | gen_addr_reg_index(ctx, t0); | |
5412 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5413 | gen_addr_add(ctx, t0, t0, 8); | |
5414 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5415 | tcg_temp_free(t0); |
76a66253 JM |
5416 | } |
5417 | ||
5418 | /* BookE specific instructions */ | |
99e300ef | 5419 | |
54623277 | 5420 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5421 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5422 | { |
5423 | /* XXX: TODO */ | |
e06fcd75 | 5424 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5425 | } |
5426 | ||
2662a059 | 5427 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5428 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5429 | { |
5430 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5431 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5432 | #else |
74d37793 | 5433 | TCGv t0; |
76db3ba4 | 5434 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5435 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5436 | return; |
5437 | } | |
ec72e276 | 5438 | t0 = tcg_temp_new(); |
76db3ba4 | 5439 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5440 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5441 | tcg_temp_free(t0); |
76a66253 JM |
5442 | #endif |
5443 | } | |
5444 | ||
5445 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5446 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5447 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5448 | { |
182608d4 AJ |
5449 | TCGv t0, t1; |
5450 | ||
a7812ae4 PB |
5451 | t0 = tcg_temp_local_new(); |
5452 | t1 = tcg_temp_local_new(); | |
182608d4 | 5453 | |
76a66253 JM |
5454 | switch (opc3 & 0x0D) { |
5455 | case 0x05: | |
5456 | /* macchw - macchw. - macchwo - macchwo. */ | |
5457 | /* macchws - macchws. - macchwso - macchwso. */ | |
5458 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5459 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5460 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5461 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5462 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5463 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5464 | break; |
5465 | case 0x04: | |
5466 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5467 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5468 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5469 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5470 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5471 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5472 | break; |
5473 | case 0x01: | |
5474 | /* machhw - machhw. - machhwo - machhwo. */ | |
5475 | /* machhws - machhws. - machhwso - machhwso. */ | |
5476 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5477 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5478 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5479 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5480 | tcg_gen_ext16s_tl(t0, t0); | |
5481 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5482 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5483 | break; |
5484 | case 0x00: | |
5485 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5486 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5487 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5488 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5489 | tcg_gen_ext16u_tl(t0, t0); | |
5490 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5491 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5492 | break; |
5493 | case 0x0D: | |
5494 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5495 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5496 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5497 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5498 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5499 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5500 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5501 | break; |
5502 | case 0x0C: | |
5503 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5504 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5505 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5506 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5507 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5508 | break; |
5509 | } | |
76a66253 | 5510 | if (opc2 & 0x04) { |
182608d4 AJ |
5511 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5512 | tcg_gen_mul_tl(t1, t0, t1); | |
5513 | if (opc2 & 0x02) { | |
5514 | /* nmultiply-and-accumulate (0x0E) */ | |
5515 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5516 | } else { | |
5517 | /* multiply-and-accumulate (0x0C) */ | |
5518 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5519 | } | |
5520 | ||
5521 | if (opc3 & 0x12) { | |
5522 | /* Check overflow and/or saturate */ | |
5523 | int l1 = gen_new_label(); | |
5524 | ||
5525 | if (opc3 & 0x10) { | |
5526 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5527 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5528 | } |
5529 | if (opc3 & 0x01) { | |
5530 | /* Signed */ | |
5531 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5532 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5533 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5534 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5535 | if (opc3 & 0x02) { |
182608d4 AJ |
5536 | /* Saturate */ |
5537 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5538 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5539 | } | |
5540 | } else { | |
5541 | /* Unsigned */ | |
5542 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5543 | if (opc3 & 0x02) { |
182608d4 AJ |
5544 | /* Saturate */ |
5545 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5546 | } | |
5547 | } | |
5548 | if (opc3 & 0x10) { | |
5549 | /* Check overflow */ | |
da91a00f RH |
5550 | tcg_gen_movi_tl(cpu_ov, 1); |
5551 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5552 | } |
5553 | gen_set_label(l1); | |
5554 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5555 | } | |
5556 | } else { | |
5557 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5558 | } |
182608d4 AJ |
5559 | tcg_temp_free(t0); |
5560 | tcg_temp_free(t1); | |
76a66253 JM |
5561 | if (unlikely(Rc) != 0) { |
5562 | /* Update Rc0 */ | |
182608d4 | 5563 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5564 | } |
5565 | } | |
5566 | ||
a750fc0b | 5567 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5568 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5569 | { \ |
5570 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5571 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5572 | } | |
5573 | ||
5574 | /* macchw - macchw. */ | |
a750fc0b | 5575 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5576 | /* macchwo - macchwo. */ |
a750fc0b | 5577 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5578 | /* macchws - macchws. */ |
a750fc0b | 5579 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5580 | /* macchwso - macchwso. */ |
a750fc0b | 5581 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5582 | /* macchwsu - macchwsu. */ |
a750fc0b | 5583 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5584 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5585 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5586 | /* macchwu - macchwu. */ |
a750fc0b | 5587 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5588 | /* macchwuo - macchwuo. */ |
a750fc0b | 5589 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5590 | /* machhw - machhw. */ |
a750fc0b | 5591 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5592 | /* machhwo - machhwo. */ |
a750fc0b | 5593 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5594 | /* machhws - machhws. */ |
a750fc0b | 5595 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5596 | /* machhwso - machhwso. */ |
a750fc0b | 5597 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5598 | /* machhwsu - machhwsu. */ |
a750fc0b | 5599 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5600 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5601 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5602 | /* machhwu - machhwu. */ |
a750fc0b | 5603 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5604 | /* machhwuo - machhwuo. */ |
a750fc0b | 5605 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5606 | /* maclhw - maclhw. */ |
a750fc0b | 5607 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5608 | /* maclhwo - maclhwo. */ |
a750fc0b | 5609 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5610 | /* maclhws - maclhws. */ |
a750fc0b | 5611 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5612 | /* maclhwso - maclhwso. */ |
a750fc0b | 5613 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5614 | /* maclhwu - maclhwu. */ |
a750fc0b | 5615 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5616 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5617 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5618 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5619 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5620 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5621 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5622 | /* nmacchw - nmacchw. */ |
a750fc0b | 5623 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5624 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5625 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5626 | /* nmacchws - nmacchws. */ |
a750fc0b | 5627 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5628 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5629 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5630 | /* nmachhw - nmachhw. */ |
a750fc0b | 5631 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5632 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5633 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5634 | /* nmachhws - nmachhws. */ |
a750fc0b | 5635 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5636 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5637 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5638 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5639 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5640 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5641 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5642 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5643 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5644 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5645 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5646 | |
5647 | /* mulchw - mulchw. */ | |
a750fc0b | 5648 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5649 | /* mulchwu - mulchwu. */ |
a750fc0b | 5650 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5651 | /* mulhhw - mulhhw. */ |
a750fc0b | 5652 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5653 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5654 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5655 | /* mullhw - mullhw. */ |
a750fc0b | 5656 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5657 | /* mullhwu - mullhwu. */ |
a750fc0b | 5658 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5659 | |
5660 | /* mfdcr */ | |
99e300ef | 5661 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5662 | { |
5663 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5664 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5665 | #else |
06dca6a7 | 5666 | TCGv dcrn; |
76db3ba4 | 5667 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5668 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5669 | return; |
5670 | } | |
06dca6a7 AJ |
5671 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5672 | gen_update_nip(ctx, ctx->nip - 4); | |
5673 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5674 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5675 | tcg_temp_free(dcrn); |
76a66253 JM |
5676 | #endif |
5677 | } | |
5678 | ||
5679 | /* mtdcr */ | |
99e300ef | 5680 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5681 | { |
5682 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5683 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5684 | #else |
06dca6a7 | 5685 | TCGv dcrn; |
76db3ba4 | 5686 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5687 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5688 | return; |
5689 | } | |
06dca6a7 AJ |
5690 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5691 | gen_update_nip(ctx, ctx->nip - 4); | |
5692 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5693 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5694 | tcg_temp_free(dcrn); |
a42bd6cc JM |
5695 | #endif |
5696 | } | |
5697 | ||
5698 | /* mfdcrx */ | |
2662a059 | 5699 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5700 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5701 | { |
5702 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5703 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5704 | #else |
76db3ba4 | 5705 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5706 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5707 | return; |
5708 | } | |
06dca6a7 AJ |
5709 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5710 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5711 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5712 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5713 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
5714 | #endif |
5715 | } | |
5716 | ||
5717 | /* mtdcrx */ | |
2662a059 | 5718 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5719 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5720 | { |
5721 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5722 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5723 | #else |
76db3ba4 | 5724 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5725 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5726 | return; |
5727 | } | |
06dca6a7 AJ |
5728 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5729 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5730 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5731 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5732 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
5733 | #endif |
5734 | } | |
5735 | ||
a750fc0b | 5736 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5737 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5738 | { |
06dca6a7 AJ |
5739 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5740 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5741 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5742 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5743 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5744 | } | |
5745 | ||
5746 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5747 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5748 | { |
06dca6a7 AJ |
5749 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5750 | gen_update_nip(ctx, ctx->nip - 4); | |
975e5463 | 5751 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5752 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5753 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5754 | } | |
5755 | ||
76a66253 | 5756 | /* dccci */ |
99e300ef | 5757 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
5758 | { |
5759 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5760 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5761 | #else |
76db3ba4 | 5762 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5763 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5764 | return; |
5765 | } | |
5766 | /* interpreted as no-op */ | |
5767 | #endif | |
5768 | } | |
5769 | ||
5770 | /* dcread */ | |
99e300ef | 5771 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5772 | { |
5773 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5774 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5775 | #else |
b61f2753 | 5776 | TCGv EA, val; |
76db3ba4 | 5777 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5778 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5779 | return; |
5780 | } | |
76db3ba4 | 5781 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5782 | EA = tcg_temp_new(); |
76db3ba4 | 5783 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5784 | val = tcg_temp_new(); |
76db3ba4 | 5785 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5786 | tcg_temp_free(val); |
5787 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5788 | tcg_temp_free(EA); | |
76a66253 JM |
5789 | #endif |
5790 | } | |
5791 | ||
5792 | /* icbt */ | |
e8eaa2c0 | 5793 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5794 | { |
5795 | /* interpreted as no-op */ | |
5796 | /* XXX: specification say this is treated as a load by the MMU | |
5797 | * but does not generate any exception | |
5798 | */ | |
5799 | } | |
5800 | ||
5801 | /* iccci */ | |
99e300ef | 5802 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
5803 | { |
5804 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5805 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5806 | #else |
76db3ba4 | 5807 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5808 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5809 | return; |
5810 | } | |
5811 | /* interpreted as no-op */ | |
5812 | #endif | |
5813 | } | |
5814 | ||
5815 | /* icread */ | |
99e300ef | 5816 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
5817 | { |
5818 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5819 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5820 | #else |
76db3ba4 | 5821 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5822 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5823 | return; |
5824 | } | |
5825 | /* interpreted as no-op */ | |
5826 | #endif | |
5827 | } | |
5828 | ||
76db3ba4 | 5829 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 5830 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5831 | { |
5832 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5833 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5834 | #else |
76db3ba4 | 5835 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5836 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5837 | return; |
5838 | } | |
5839 | /* Restore CPU state */ | |
e5f17ac6 | 5840 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 5841 | gen_sync_exception(ctx); |
a42bd6cc JM |
5842 | #endif |
5843 | } | |
5844 | ||
99e300ef | 5845 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5846 | { |
5847 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5848 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5849 | #else |
76db3ba4 | 5850 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5851 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5852 | return; |
5853 | } | |
5854 | /* Restore CPU state */ | |
e5f17ac6 | 5855 | gen_helper_rfci(cpu_env); |
e06fcd75 | 5856 | gen_sync_exception(ctx); |
a42bd6cc JM |
5857 | #endif |
5858 | } | |
5859 | ||
5860 | /* BookE specific */ | |
99e300ef | 5861 | |
54623277 | 5862 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5863 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5864 | { |
5865 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5866 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5867 | #else |
76db3ba4 | 5868 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5869 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5870 | return; |
5871 | } | |
5872 | /* Restore CPU state */ | |
e5f17ac6 | 5873 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 5874 | gen_sync_exception(ctx); |
76a66253 JM |
5875 | #endif |
5876 | } | |
5877 | ||
2662a059 | 5878 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5879 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5880 | { |
5881 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5882 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5883 | #else |
76db3ba4 | 5884 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5885 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5886 | return; |
5887 | } | |
5888 | /* Restore CPU state */ | |
e5f17ac6 | 5889 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 5890 | gen_sync_exception(ctx); |
a42bd6cc JM |
5891 | #endif |
5892 | } | |
5eb7995e | 5893 | |
d9bce9d9 | 5894 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5895 | |
54623277 | 5896 | /* tlbre */ |
e8eaa2c0 | 5897 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5898 | { |
5899 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5900 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5901 | #else |
76db3ba4 | 5902 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5903 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5904 | return; |
5905 | } | |
5906 | switch (rB(ctx->opcode)) { | |
5907 | case 0: | |
c6c7cf05 BS |
5908 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5909 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5910 | break; |
5911 | case 1: | |
c6c7cf05 BS |
5912 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5913 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5914 | break; |
5915 | default: | |
e06fcd75 | 5916 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5917 | break; |
9a64fbe4 | 5918 | } |
76a66253 JM |
5919 | #endif |
5920 | } | |
5921 | ||
d9bce9d9 | 5922 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5923 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5924 | { |
5925 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5926 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5927 | #else |
74d37793 | 5928 | TCGv t0; |
76db3ba4 | 5929 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5930 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5931 | return; |
5932 | } | |
74d37793 | 5933 | t0 = tcg_temp_new(); |
76db3ba4 | 5934 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5935 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
5936 | tcg_temp_free(t0); |
5937 | if (Rc(ctx->opcode)) { | |
5938 | int l1 = gen_new_label(); | |
da91a00f | 5939 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5940 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5941 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5942 | gen_set_label(l1); | |
5943 | } | |
76a66253 | 5944 | #endif |
79aceca5 FB |
5945 | } |
5946 | ||
76a66253 | 5947 | /* tlbwe */ |
e8eaa2c0 | 5948 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 5949 | { |
76a66253 | 5950 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5951 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5952 | #else |
76db3ba4 | 5953 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5954 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5955 | return; |
5956 | } | |
5957 | switch (rB(ctx->opcode)) { | |
5958 | case 0: | |
c6c7cf05 BS |
5959 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5960 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5961 | break; |
5962 | case 1: | |
c6c7cf05 BS |
5963 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5964 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5965 | break; |
5966 | default: | |
e06fcd75 | 5967 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5968 | break; |
9a64fbe4 | 5969 | } |
76a66253 JM |
5970 | #endif |
5971 | } | |
5972 | ||
a4bb6c3e | 5973 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 5974 | |
54623277 | 5975 | /* tlbre */ |
e8eaa2c0 | 5976 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
5977 | { |
5978 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5979 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 5980 | #else |
76db3ba4 | 5981 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5982 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
5983 | return; |
5984 | } | |
5985 | switch (rB(ctx->opcode)) { | |
5986 | case 0: | |
5eb7995e | 5987 | case 1: |
5eb7995e | 5988 | case 2: |
74d37793 AJ |
5989 | { |
5990 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
5991 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5992 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
5993 | tcg_temp_free_i32(t0); |
5994 | } | |
5eb7995e JM |
5995 | break; |
5996 | default: | |
e06fcd75 | 5997 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5998 | break; |
5999 | } | |
6000 | #endif | |
6001 | } | |
6002 | ||
6003 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6004 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6005 | { |
6006 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6007 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6008 | #else |
74d37793 | 6009 | TCGv t0; |
76db3ba4 | 6010 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6011 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6012 | return; |
6013 | } | |
74d37793 | 6014 | t0 = tcg_temp_new(); |
76db3ba4 | 6015 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6016 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6017 | tcg_temp_free(t0); |
6018 | if (Rc(ctx->opcode)) { | |
6019 | int l1 = gen_new_label(); | |
da91a00f | 6020 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6021 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6022 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6023 | gen_set_label(l1); | |
6024 | } | |
5eb7995e JM |
6025 | #endif |
6026 | } | |
6027 | ||
6028 | /* tlbwe */ | |
e8eaa2c0 | 6029 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6030 | { |
6031 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6032 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6033 | #else |
76db3ba4 | 6034 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6035 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6036 | return; |
6037 | } | |
6038 | switch (rB(ctx->opcode)) { | |
6039 | case 0: | |
5eb7995e | 6040 | case 1: |
5eb7995e | 6041 | case 2: |
74d37793 AJ |
6042 | { |
6043 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6044 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6045 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6046 | tcg_temp_free_i32(t0); |
6047 | } | |
5eb7995e JM |
6048 | break; |
6049 | default: | |
e06fcd75 | 6050 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6051 | break; |
6052 | } | |
6053 | #endif | |
6054 | } | |
6055 | ||
01662f3e AG |
6056 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6057 | ||
6058 | /* tlbre */ | |
6059 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6060 | { | |
6061 | #if defined(CONFIG_USER_ONLY) | |
6062 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6063 | #else | |
6064 | if (unlikely(!ctx->mem_idx)) { | |
6065 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6066 | return; | |
6067 | } | |
6068 | ||
c6c7cf05 | 6069 | gen_helper_booke206_tlbre(cpu_env); |
01662f3e AG |
6070 | #endif |
6071 | } | |
6072 | ||
6073 | /* tlbsx - tlbsx. */ | |
6074 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6075 | { | |
6076 | #if defined(CONFIG_USER_ONLY) | |
6077 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6078 | #else | |
6079 | TCGv t0; | |
6080 | if (unlikely(!ctx->mem_idx)) { | |
6081 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6082 | return; | |
6083 | } | |
6084 | ||
6085 | if (rA(ctx->opcode)) { | |
6086 | t0 = tcg_temp_new(); | |
6087 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6088 | } else { | |
6089 | t0 = tcg_const_tl(0); | |
6090 | } | |
6091 | ||
6092 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6093 | gen_helper_booke206_tlbsx(cpu_env, t0); |
01662f3e AG |
6094 | #endif |
6095 | } | |
6096 | ||
6097 | /* tlbwe */ | |
6098 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6099 | { | |
6100 | #if defined(CONFIG_USER_ONLY) | |
6101 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6102 | #else | |
6103 | if (unlikely(!ctx->mem_idx)) { | |
6104 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6105 | return; | |
6106 | } | |
3f162d11 | 6107 | gen_update_nip(ctx, ctx->nip - 4); |
c6c7cf05 | 6108 | gen_helper_booke206_tlbwe(cpu_env); |
01662f3e AG |
6109 | #endif |
6110 | } | |
6111 | ||
6112 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6113 | { | |
6114 | #if defined(CONFIG_USER_ONLY) | |
6115 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6116 | #else | |
6117 | TCGv t0; | |
6118 | if (unlikely(!ctx->mem_idx)) { | |
6119 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6120 | return; | |
6121 | } | |
6122 | ||
6123 | t0 = tcg_temp_new(); | |
6124 | gen_addr_reg_index(ctx, t0); | |
6125 | ||
c6c7cf05 | 6126 | gen_helper_booke206_tlbivax(cpu_env, t0); |
01662f3e AG |
6127 | #endif |
6128 | } | |
6129 | ||
6d3db821 AG |
6130 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6131 | { | |
6132 | #if defined(CONFIG_USER_ONLY) | |
6133 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6134 | #else | |
6135 | TCGv t0; | |
6136 | if (unlikely(!ctx->mem_idx)) { | |
6137 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6138 | return; | |
6139 | } | |
6140 | ||
6141 | t0 = tcg_temp_new(); | |
6142 | gen_addr_reg_index(ctx, t0); | |
6143 | ||
6144 | switch((ctx->opcode >> 21) & 0x3) { | |
6145 | case 0: | |
c6c7cf05 | 6146 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6147 | break; |
6148 | case 1: | |
c6c7cf05 | 6149 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6150 | break; |
6151 | case 3: | |
c6c7cf05 | 6152 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6153 | break; |
6154 | default: | |
6155 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6156 | break; | |
6157 | } | |
6158 | ||
6159 | tcg_temp_free(t0); | |
6160 | #endif | |
6161 | } | |
6162 | ||
01662f3e | 6163 | |
76a66253 | 6164 | /* wrtee */ |
99e300ef | 6165 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6166 | { |
6167 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6168 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6169 | #else |
6527f6ea | 6170 | TCGv t0; |
76db3ba4 | 6171 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6172 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6173 | return; |
6174 | } | |
6527f6ea AJ |
6175 | t0 = tcg_temp_new(); |
6176 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6177 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6178 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6179 | tcg_temp_free(t0); | |
dee96f6c JM |
6180 | /* Stop translation to have a chance to raise an exception |
6181 | * if we just set msr_ee to 1 | |
6182 | */ | |
e06fcd75 | 6183 | gen_stop_exception(ctx); |
76a66253 JM |
6184 | #endif |
6185 | } | |
6186 | ||
6187 | /* wrteei */ | |
99e300ef | 6188 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6189 | { |
6190 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6191 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6192 | #else |
76db3ba4 | 6193 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6194 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6195 | return; |
6196 | } | |
fbe73008 | 6197 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6198 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6199 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6200 | gen_stop_exception(ctx); |
6527f6ea | 6201 | } else { |
1b6e5f99 | 6202 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6203 | } |
76a66253 JM |
6204 | #endif |
6205 | } | |
6206 | ||
08e46e54 | 6207 | /* PowerPC 440 specific instructions */ |
99e300ef | 6208 | |
54623277 | 6209 | /* dlmzb */ |
99e300ef | 6210 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6211 | { |
ef0d51af | 6212 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6213 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6214 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6215 | tcg_temp_free_i32(t0); |
76a66253 JM |
6216 | } |
6217 | ||
6218 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6219 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6220 | { |
6221 | /* interpreted as no-op */ | |
6222 | } | |
6223 | ||
6224 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6225 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6226 | { |
6227 | /* interpreted as no-op */ | |
6228 | } | |
6229 | ||
6230 | /* icbt */ | |
e8eaa2c0 | 6231 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6232 | { |
6233 | /* interpreted as no-op */ | |
6234 | /* XXX: specification say this is treated as a load by the MMU | |
6235 | * but does not generate any exception | |
6236 | */ | |
79aceca5 FB |
6237 | } |
6238 | ||
9e0b5cb1 AG |
6239 | /* Embedded.Processor Control */ |
6240 | ||
6241 | static void gen_msgclr(DisasContext *ctx) | |
6242 | { | |
6243 | #if defined(CONFIG_USER_ONLY) | |
6244 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6245 | #else | |
6246 | if (unlikely(ctx->mem_idx == 0)) { | |
6247 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6248 | return; | |
6249 | } | |
6250 | ||
e5f17ac6 | 6251 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9e0b5cb1 AG |
6252 | #endif |
6253 | } | |
6254 | ||
d5d11a39 AG |
6255 | static void gen_msgsnd(DisasContext *ctx) |
6256 | { | |
6257 | #if defined(CONFIG_USER_ONLY) | |
6258 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6259 | #else | |
6260 | if (unlikely(ctx->mem_idx == 0)) { | |
6261 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6262 | return; | |
6263 | } | |
6264 | ||
6265 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6266 | #endif | |
6267 | } | |
6268 | ||
a9d9eb8f JM |
6269 | /*** Altivec vector extension ***/ |
6270 | /* Altivec registers moves */ | |
a9d9eb8f | 6271 | |
636aa200 | 6272 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6273 | { |
e4704b3b | 6274 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6275 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6276 | return r; | |
6277 | } | |
6278 | ||
a9d9eb8f | 6279 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6280 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6281 | { \ |
fe1e5c53 | 6282 | TCGv EA; \ |
a9d9eb8f | 6283 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6284 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6285 | return; \ |
6286 | } \ | |
76db3ba4 | 6287 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6288 | EA = tcg_temp_new(); \ |
76db3ba4 | 6289 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6290 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6291 | if (ctx->le_mode) { \ |
6292 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6293 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6294 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6295 | } else { \ |
76db3ba4 | 6296 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6297 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6298 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6299 | } \ |
6300 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6301 | } |
6302 | ||
6303 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6304 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6305 | { \ |
fe1e5c53 | 6306 | TCGv EA; \ |
a9d9eb8f | 6307 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6308 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6309 | return; \ |
6310 | } \ | |
76db3ba4 | 6311 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6312 | EA = tcg_temp_new(); \ |
76db3ba4 | 6313 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6314 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6315 | if (ctx->le_mode) { \ |
6316 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6317 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6318 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6319 | } else { \ |
76db3ba4 | 6320 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6321 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6322 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6323 | } \ |
6324 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6325 | } |
6326 | ||
cbfb6ae9 | 6327 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef | 6328 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6329 | { \ |
6330 | TCGv EA; \ | |
6331 | TCGv_ptr rs; \ | |
6332 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6333 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6334 | return; \ | |
6335 | } \ | |
6336 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6337 | EA = tcg_temp_new(); \ | |
6338 | gen_addr_reg_index(ctx, EA); \ | |
6339 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6340 | gen_helper_lve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6341 | tcg_temp_free(EA); \ |
6342 | tcg_temp_free_ptr(rs); \ | |
6343 | } | |
6344 | ||
6345 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef | 6346 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6347 | { \ |
6348 | TCGv EA; \ | |
6349 | TCGv_ptr rs; \ | |
6350 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6351 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6352 | return; \ | |
6353 | } \ | |
6354 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6355 | EA = tcg_temp_new(); \ | |
6356 | gen_addr_reg_index(ctx, EA); \ | |
6357 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6358 | gen_helper_stve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6359 | tcg_temp_free(EA); \ |
6360 | tcg_temp_free_ptr(rs); \ | |
6361 | } | |
6362 | ||
fe1e5c53 | 6363 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6364 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6365 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6366 | |
cbfb6ae9 AJ |
6367 | GEN_VR_LVE(bx, 0x07, 0x00); |
6368 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6369 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6370 | ||
fe1e5c53 | 6371 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6372 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6373 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6374 | |
cbfb6ae9 AJ |
6375 | GEN_VR_STVE(bx, 0x07, 0x04); |
6376 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6377 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6378 | ||
99e300ef | 6379 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6380 | { |
6381 | TCGv_ptr rd; | |
6382 | TCGv EA; | |
6383 | if (unlikely(!ctx->altivec_enabled)) { | |
6384 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6385 | return; | |
6386 | } | |
6387 | EA = tcg_temp_new(); | |
6388 | gen_addr_reg_index(ctx, EA); | |
6389 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6390 | gen_helper_lvsl(rd, EA); | |
6391 | tcg_temp_free(EA); | |
6392 | tcg_temp_free_ptr(rd); | |
6393 | } | |
6394 | ||
99e300ef | 6395 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6396 | { |
6397 | TCGv_ptr rd; | |
6398 | TCGv EA; | |
6399 | if (unlikely(!ctx->altivec_enabled)) { | |
6400 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6401 | return; | |
6402 | } | |
6403 | EA = tcg_temp_new(); | |
6404 | gen_addr_reg_index(ctx, EA); | |
6405 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6406 | gen_helper_lvsr(rd, EA); | |
6407 | tcg_temp_free(EA); | |
6408 | tcg_temp_free_ptr(rd); | |
6409 | } | |
6410 | ||
99e300ef | 6411 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6412 | { |
6413 | TCGv_i32 t; | |
6414 | if (unlikely(!ctx->altivec_enabled)) { | |
6415 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6416 | return; | |
6417 | } | |
6418 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6419 | t = tcg_temp_new_i32(); | |
1328c2bf | 6420 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
785f451b | 6421 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
fce5ecb7 | 6422 | tcg_temp_free_i32(t); |
785f451b AJ |
6423 | } |
6424 | ||
99e300ef | 6425 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6426 | { |
6e87b7c7 | 6427 | TCGv_ptr p; |
785f451b AJ |
6428 | if (unlikely(!ctx->altivec_enabled)) { |
6429 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6430 | return; | |
6431 | } | |
6e87b7c7 | 6432 | p = gen_avr_ptr(rD(ctx->opcode)); |
d15f74fb | 6433 | gen_helper_mtvscr(cpu_env, p); |
6e87b7c7 | 6434 | tcg_temp_free_ptr(p); |
785f451b AJ |
6435 | } |
6436 | ||
7a9b96cf AJ |
6437 | /* Logical operations */ |
6438 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6439 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6440 | { \ |
6441 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6442 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6443 | return; \ | |
6444 | } \ | |
6445 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6446 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6447 | } | |
6448 | ||
6449 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6450 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6451 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6452 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6453 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
6454 | ||
8e27dd6f | 6455 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6456 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6457 | { \ |
6458 | TCGv_ptr ra, rb, rd; \ | |
6459 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6460 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6461 | return; \ | |
6462 | } \ | |
6463 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6464 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6465 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6466 | gen_helper_##name (rd, ra, rb); \ | |
6467 | tcg_temp_free_ptr(ra); \ | |
6468 | tcg_temp_free_ptr(rb); \ | |
6469 | tcg_temp_free_ptr(rd); \ | |
6470 | } | |
6471 | ||
d15f74fb BS |
6472 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
6473 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6474 | { \ | |
6475 | TCGv_ptr ra, rb, rd; \ | |
6476 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6477 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6478 | return; \ | |
6479 | } \ | |
6480 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6481 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6482 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
54cddd21 | 6483 | gen_helper_##name(cpu_env, rd, ra, rb); \ |
d15f74fb BS |
6484 | tcg_temp_free_ptr(ra); \ |
6485 | tcg_temp_free_ptr(rb); \ | |
6486 | tcg_temp_free_ptr(rd); \ | |
6487 | } | |
6488 | ||
7872c51c AJ |
6489 | GEN_VXFORM(vaddubm, 0, 0); |
6490 | GEN_VXFORM(vadduhm, 0, 1); | |
6491 | GEN_VXFORM(vadduwm, 0, 2); | |
6492 | GEN_VXFORM(vsububm, 0, 16); | |
6493 | GEN_VXFORM(vsubuhm, 0, 17); | |
6494 | GEN_VXFORM(vsubuwm, 0, 18); | |
e4039339 AJ |
6495 | GEN_VXFORM(vmaxub, 1, 0); |
6496 | GEN_VXFORM(vmaxuh, 1, 1); | |
6497 | GEN_VXFORM(vmaxuw, 1, 2); | |
6498 | GEN_VXFORM(vmaxsb, 1, 4); | |
6499 | GEN_VXFORM(vmaxsh, 1, 5); | |
6500 | GEN_VXFORM(vmaxsw, 1, 6); | |
6501 | GEN_VXFORM(vminub, 1, 8); | |
6502 | GEN_VXFORM(vminuh, 1, 9); | |
6503 | GEN_VXFORM(vminuw, 1, 10); | |
6504 | GEN_VXFORM(vminsb, 1, 12); | |
6505 | GEN_VXFORM(vminsh, 1, 13); | |
6506 | GEN_VXFORM(vminsw, 1, 14); | |
fab3cbe9 AJ |
6507 | GEN_VXFORM(vavgub, 1, 16); |
6508 | GEN_VXFORM(vavguh, 1, 17); | |
6509 | GEN_VXFORM(vavguw, 1, 18); | |
6510 | GEN_VXFORM(vavgsb, 1, 20); | |
6511 | GEN_VXFORM(vavgsh, 1, 21); | |
6512 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6513 | GEN_VXFORM(vmrghb, 6, 0); |
6514 | GEN_VXFORM(vmrghh, 6, 1); | |
6515 | GEN_VXFORM(vmrghw, 6, 2); | |
6516 | GEN_VXFORM(vmrglb, 6, 4); | |
6517 | GEN_VXFORM(vmrglh, 6, 5); | |
6518 | GEN_VXFORM(vmrglw, 6, 6); | |
2c277908 AJ |
6519 | GEN_VXFORM(vmuloub, 4, 0); |
6520 | GEN_VXFORM(vmulouh, 4, 1); | |
6521 | GEN_VXFORM(vmulosb, 4, 4); | |
6522 | GEN_VXFORM(vmulosh, 4, 5); | |
6523 | GEN_VXFORM(vmuleub, 4, 8); | |
6524 | GEN_VXFORM(vmuleuh, 4, 9); | |
6525 | GEN_VXFORM(vmulesb, 4, 12); | |
6526 | GEN_VXFORM(vmulesh, 4, 13); | |
d79f0809 AJ |
6527 | GEN_VXFORM(vslb, 2, 4); |
6528 | GEN_VXFORM(vslh, 2, 5); | |
6529 | GEN_VXFORM(vslw, 2, 6); | |
07ef34c3 AJ |
6530 | GEN_VXFORM(vsrb, 2, 8); |
6531 | GEN_VXFORM(vsrh, 2, 9); | |
6532 | GEN_VXFORM(vsrw, 2, 10); | |
6533 | GEN_VXFORM(vsrab, 2, 12); | |
6534 | GEN_VXFORM(vsrah, 2, 13); | |
6535 | GEN_VXFORM(vsraw, 2, 14); | |
7b239bec AJ |
6536 | GEN_VXFORM(vslo, 6, 16); |
6537 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
6538 | GEN_VXFORM(vaddcuw, 0, 6); |
6539 | GEN_VXFORM(vsubcuw, 0, 22); | |
d15f74fb BS |
6540 | GEN_VXFORM_ENV(vaddubs, 0, 8); |
6541 | GEN_VXFORM_ENV(vadduhs, 0, 9); | |
6542 | GEN_VXFORM_ENV(vadduws, 0, 10); | |
6543 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
6544 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
6545 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
6546 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
6547 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
6548 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
6549 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
6550 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
6551 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
5e1d0985 AJ |
6552 | GEN_VXFORM(vrlb, 2, 0); |
6553 | GEN_VXFORM(vrlh, 2, 1); | |
6554 | GEN_VXFORM(vrlw, 2, 2); | |
d9430add AJ |
6555 | GEN_VXFORM(vsl, 2, 7); |
6556 | GEN_VXFORM(vsr, 2, 11); | |
d15f74fb BS |
6557 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
6558 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
6559 | GEN_VXFORM_ENV(vpkuhus, 7, 2); | |
6560 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
6561 | GEN_VXFORM_ENV(vpkshus, 7, 4); | |
6562 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
6563 | GEN_VXFORM_ENV(vpkshss, 7, 6); | |
6564 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
1dd9ffb9 | 6565 | GEN_VXFORM(vpkpx, 7, 12); |
d15f74fb BS |
6566 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
6567 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
6568 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
6569 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
6570 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
6571 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
6572 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
6573 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
6574 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
fab3cbe9 | 6575 | |
0cbcd906 | 6576 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 6577 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
6578 | { \ |
6579 | TCGv_ptr ra, rb, rd; \ | |
6580 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6581 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6582 | return; \ | |
6583 | } \ | |
6584 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6585 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6586 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
d15f74fb | 6587 | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
0cbcd906 AJ |
6588 | tcg_temp_free_ptr(ra); \ |
6589 | tcg_temp_free_ptr(rb); \ | |
6590 | tcg_temp_free_ptr(rd); \ | |
6591 | } | |
6592 | ||
6593 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
6594 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
6595 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
6596 | ||
1add6e23 AJ |
6597 | GEN_VXRFORM(vcmpequb, 3, 0) |
6598 | GEN_VXRFORM(vcmpequh, 3, 1) | |
6599 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6600 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
6601 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
6602 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6603 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
6604 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
6605 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
819ca121 AJ |
6606 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6607 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
6608 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
6609 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 6610 | |
c026766b | 6611 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6612 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
6613 | { \ |
6614 | TCGv_ptr rd; \ | |
6615 | TCGv_i32 simm; \ | |
6616 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6617 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6618 | return; \ | |
6619 | } \ | |
6620 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6621 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6622 | gen_helper_##name (rd, simm); \ | |
6623 | tcg_temp_free_i32(simm); \ | |
6624 | tcg_temp_free_ptr(rd); \ | |
6625 | } | |
6626 | ||
6627 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
6628 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
6629 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
6630 | ||
de5f2484 | 6631 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 6632 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
6633 | { \ |
6634 | TCGv_ptr rb, rd; \ | |
6635 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6636 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6637 | return; \ | |
6638 | } \ | |
6639 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6640 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6641 | gen_helper_##name (rd, rb); \ | |
6642 | tcg_temp_free_ptr(rb); \ | |
6643 | tcg_temp_free_ptr(rd); \ | |
6644 | } | |
6645 | ||
d15f74fb BS |
6646 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ |
6647 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6648 | { \ | |
6649 | TCGv_ptr rb, rd; \ | |
6650 | \ | |
6651 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6652 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6653 | return; \ | |
6654 | } \ | |
6655 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6656 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6657 | gen_helper_##name(cpu_env, rd, rb); \ | |
6658 | tcg_temp_free_ptr(rb); \ | |
6659 | tcg_temp_free_ptr(rd); \ | |
6660 | } | |
6661 | ||
6cf1c6e5 AJ |
6662 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6663 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
6664 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
6665 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
79f85c3a AJ |
6666 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6667 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
d15f74fb BS |
6668 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
6669 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
6670 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
6671 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
6672 | GEN_VXFORM_NOA_ENV(vrfim, 5, 8); | |
6673 | GEN_VXFORM_NOA_ENV(vrfin, 5, 9); | |
6674 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
6675 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 11); | |
79f85c3a | 6676 | |
21d21583 | 6677 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6678 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
6679 | { \ |
6680 | TCGv_ptr rd; \ | |
6681 | TCGv_i32 simm; \ | |
6682 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6683 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6684 | return; \ | |
6685 | } \ | |
6686 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6687 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6688 | gen_helper_##name (rd, simm); \ | |
6689 | tcg_temp_free_i32(simm); \ | |
6690 | tcg_temp_free_ptr(rd); \ | |
6691 | } | |
6692 | ||
27a4edb3 | 6693 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 6694 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
6695 | { \ |
6696 | TCGv_ptr rb, rd; \ | |
6697 | TCGv_i32 uimm; \ | |
6698 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6699 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6700 | return; \ | |
6701 | } \ | |
6702 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6703 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6704 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6705 | gen_helper_##name (rd, rb, uimm); \ | |
6706 | tcg_temp_free_i32(uimm); \ | |
6707 | tcg_temp_free_ptr(rb); \ | |
6708 | tcg_temp_free_ptr(rd); \ | |
6709 | } | |
6710 | ||
d15f74fb BS |
6711 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
6712 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6713 | { \ | |
6714 | TCGv_ptr rb, rd; \ | |
6715 | TCGv_i32 uimm; \ | |
6716 | \ | |
6717 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6718 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6719 | return; \ | |
6720 | } \ | |
6721 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6722 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6723 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6724 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
6725 | tcg_temp_free_i32(uimm); \ | |
6726 | tcg_temp_free_ptr(rb); \ | |
6727 | tcg_temp_free_ptr(rd); \ | |
6728 | } | |
6729 | ||
e4e6bee7 AJ |
6730 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6731 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
6732 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
d15f74fb BS |
6733 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
6734 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
6735 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
6736 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
e4e6bee7 | 6737 | |
99e300ef | 6738 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
6739 | { |
6740 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 6741 | TCGv_i32 sh; |
cd633b10 AJ |
6742 | if (unlikely(!ctx->altivec_enabled)) { |
6743 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6744 | return; | |
6745 | } | |
6746 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6747 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6748 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6749 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
6750 | gen_helper_vsldoi (rd, ra, rb, sh); | |
6751 | tcg_temp_free_ptr(ra); | |
6752 | tcg_temp_free_ptr(rb); | |
6753 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 6754 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
6755 | } |
6756 | ||
707cec33 | 6757 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
d15f74fb | 6758 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
6759 | { \ |
6760 | TCGv_ptr ra, rb, rc, rd; \ | |
6761 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6762 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6763 | return; \ | |
6764 | } \ | |
6765 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6766 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6767 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6768 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6769 | if (Rc(ctx->opcode)) { \ | |
d15f74fb | 6770 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
707cec33 | 6771 | } else { \ |
d15f74fb | 6772 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
707cec33 AJ |
6773 | } \ |
6774 | tcg_temp_free_ptr(ra); \ | |
6775 | tcg_temp_free_ptr(rb); \ | |
6776 | tcg_temp_free_ptr(rc); \ | |
6777 | tcg_temp_free_ptr(rd); \ | |
6778 | } | |
6779 | ||
b161ae27 AJ |
6780 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
6781 | ||
99e300ef | 6782 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
6783 | { |
6784 | TCGv_ptr ra, rb, rc, rd; | |
6785 | if (unlikely(!ctx->altivec_enabled)) { | |
6786 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6787 | return; | |
6788 | } | |
6789 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6790 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6791 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
6792 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6793 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
6794 | tcg_temp_free_ptr(ra); | |
6795 | tcg_temp_free_ptr(rb); | |
6796 | tcg_temp_free_ptr(rc); | |
6797 | tcg_temp_free_ptr(rd); | |
6798 | } | |
6799 | ||
b04ae981 | 6800 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 6801 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 6802 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 6803 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 6804 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 6805 | |
0487d6a8 | 6806 | /*** SPE extension ***/ |
0487d6a8 | 6807 | /* Register moves */ |
3cd7d1dd | 6808 | |
a0e13900 FC |
6809 | |
6810 | static inline void gen_evmra(DisasContext *ctx) | |
6811 | { | |
6812 | ||
6813 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 6814 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
6815 | return; |
6816 | } | |
6817 | ||
6818 | #if defined(TARGET_PPC64) | |
6819 | /* rD := rA */ | |
6820 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6821 | ||
6822 | /* spe_acc := rA */ | |
6823 | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], | |
6824 | cpu_env, | |
1328c2bf | 6825 | offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
6826 | #else |
6827 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
6828 | ||
6829 | /* tmp := rA_lo + rA_hi << 32 */ | |
6830 | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6831 | ||
6832 | /* spe_acc := tmp */ | |
1328c2bf | 6833 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
6834 | tcg_temp_free_i64(tmp); |
6835 | ||
6836 | /* rD := rA */ | |
6837 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6838 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6839 | #endif | |
6840 | } | |
6841 | ||
636aa200 BS |
6842 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
6843 | { | |
f78fb44e AJ |
6844 | #if defined(TARGET_PPC64) |
6845 | tcg_gen_mov_i64(t, cpu_gpr[reg]); | |
6846 | #else | |
36aa55dc | 6847 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
3cd7d1dd | 6848 | #endif |
f78fb44e | 6849 | } |
3cd7d1dd | 6850 | |
636aa200 BS |
6851 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
6852 | { | |
f78fb44e AJ |
6853 | #if defined(TARGET_PPC64) |
6854 | tcg_gen_mov_i64(cpu_gpr[reg], t); | |
6855 | #else | |
a7812ae4 | 6856 | TCGv_i64 tmp = tcg_temp_new_i64(); |
f78fb44e | 6857 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
f78fb44e AJ |
6858 | tcg_gen_shri_i64(tmp, t, 32); |
6859 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); | |
a7812ae4 | 6860 | tcg_temp_free_i64(tmp); |
3cd7d1dd | 6861 | #endif |
f78fb44e | 6862 | } |
3cd7d1dd | 6863 | |
70560da7 | 6864 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
99e300ef | 6865 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
6866 | { \ |
6867 | if (Rc(ctx->opcode)) \ | |
6868 | gen_##name1(ctx); \ | |
6869 | else \ | |
6870 | gen_##name0(ctx); \ | |
6871 | } | |
6872 | ||
6873 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 6874 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 6875 | { |
e06fcd75 | 6876 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
6877 | } |
6878 | ||
57951c27 AJ |
6879 | /* SPE logic */ |
6880 | #if defined(TARGET_PPC64) | |
6881 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6882 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6883 | { \ |
6884 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6885 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
6886 | return; \ |
6887 | } \ | |
57951c27 AJ |
6888 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6889 | cpu_gpr[rB(ctx->opcode)]); \ | |
6890 | } | |
6891 | #else | |
6892 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6893 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6894 | { \ |
6895 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6896 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
6897 | return; \ |
6898 | } \ | |
6899 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
6900 | cpu_gpr[rB(ctx->opcode)]); \ | |
6901 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6902 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 6903 | } |
57951c27 AJ |
6904 | #endif |
6905 | ||
6906 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
6907 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
6908 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
6909 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
6910 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
6911 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
6912 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
6913 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 6914 | |
57951c27 AJ |
6915 | /* SPE logic immediate */ |
6916 | #if defined(TARGET_PPC64) | |
6917 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 6918 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a AJ |
6919 | { \ |
6920 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6921 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
3d3a6a0a AJ |
6922 | return; \ |
6923 | } \ | |
a7812ae4 PB |
6924 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6925 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6926 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6927 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6928 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
6929 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6930 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6931 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6932 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
6933 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6934 | tcg_temp_free_i32(t0); \ |
6935 | tcg_temp_free_i32(t1); \ | |
3d3a6a0a | 6936 | } |
57951c27 AJ |
6937 | #else |
6938 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 6939 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6940 | { \ |
6941 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6942 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
6943 | return; \ |
6944 | } \ | |
57951c27 AJ |
6945 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6946 | rB(ctx->opcode)); \ | |
6947 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6948 | rB(ctx->opcode)); \ | |
0487d6a8 | 6949 | } |
57951c27 AJ |
6950 | #endif |
6951 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); | |
6952 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
6953 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
6954 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 6955 | |
57951c27 AJ |
6956 | /* SPE arithmetic */ |
6957 | #if defined(TARGET_PPC64) | |
6958 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
636aa200 | 6959 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6960 | { \ |
6961 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6962 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
6963 | return; \ |
6964 | } \ | |
a7812ae4 PB |
6965 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6966 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6967 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6968 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6969 | tcg_op(t0, t0); \ | |
6970 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6971 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6972 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6973 | tcg_op(t1, t1); \ |
6974 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6975 | tcg_temp_free_i32(t0); \ |
6976 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 6977 | } |
57951c27 | 6978 | #else |
a7812ae4 | 6979 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 6980 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6981 | { \ |
6982 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6983 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
6984 | return; \ |
6985 | } \ | |
6986 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ | |
6987 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
6988 | } | |
6989 | #endif | |
0487d6a8 | 6990 | |
636aa200 | 6991 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
6992 | { |
6993 | int l1 = gen_new_label(); | |
6994 | int l2 = gen_new_label(); | |
0487d6a8 | 6995 | |
57951c27 AJ |
6996 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
6997 | tcg_gen_neg_i32(ret, arg1); | |
6998 | tcg_gen_br(l2); | |
6999 | gen_set_label(l1); | |
a7812ae4 | 7000 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
7001 | gen_set_label(l2); |
7002 | } | |
7003 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
7004 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
7005 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
7006 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 7007 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 7008 | { |
57951c27 AJ |
7009 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
7010 | tcg_gen_ext16u_i32(ret, ret); | |
7011 | } | |
7012 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
7013 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
7014 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 7015 | |
57951c27 AJ |
7016 | #if defined(TARGET_PPC64) |
7017 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7018 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7019 | { \ |
7020 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7021 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7022 | return; \ |
7023 | } \ | |
a7812ae4 PB |
7024 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7025 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7026 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ | |
501e23c4 | 7027 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
57951c27 AJ |
7028 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7029 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ | |
7030 | tcg_op(t0, t0, t2); \ | |
7031 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7032 | tcg_gen_trunc_i64_i32(t1, t3); \ | |
7033 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7034 | tcg_gen_trunc_i64_i32(t2, t3); \ | |
a7812ae4 | 7035 | tcg_temp_free_i64(t3); \ |
57951c27 | 7036 | tcg_op(t1, t1, t2); \ |
a7812ae4 | 7037 | tcg_temp_free_i32(t2); \ |
57951c27 | 7038 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
a7812ae4 PB |
7039 | tcg_temp_free_i32(t0); \ |
7040 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7041 | } |
57951c27 AJ |
7042 | #else |
7043 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7044 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7045 | { \ |
7046 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7047 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7048 | return; \ |
7049 | } \ | |
57951c27 AJ |
7050 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7051 | cpu_gpr[rB(ctx->opcode)]); \ | |
7052 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7053 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 7054 | } |
57951c27 | 7055 | #endif |
0487d6a8 | 7056 | |
636aa200 | 7057 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7058 | { |
a7812ae4 | 7059 | TCGv_i32 t0; |
57951c27 | 7060 | int l1, l2; |
0487d6a8 | 7061 | |
57951c27 AJ |
7062 | l1 = gen_new_label(); |
7063 | l2 = gen_new_label(); | |
a7812ae4 | 7064 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7065 | /* No error here: 6 bits are used */ |
7066 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7067 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7068 | tcg_gen_shr_i32(ret, arg1, t0); | |
7069 | tcg_gen_br(l2); | |
7070 | gen_set_label(l1); | |
7071 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7072 | gen_set_label(l2); |
a7812ae4 | 7073 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7074 | } |
7075 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 7076 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7077 | { |
a7812ae4 | 7078 | TCGv_i32 t0; |
57951c27 AJ |
7079 | int l1, l2; |
7080 | ||
7081 | l1 = gen_new_label(); | |
7082 | l2 = gen_new_label(); | |
a7812ae4 | 7083 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7084 | /* No error here: 6 bits are used */ |
7085 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7086 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7087 | tcg_gen_sar_i32(ret, arg1, t0); | |
7088 | tcg_gen_br(l2); | |
7089 | gen_set_label(l1); | |
7090 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7091 | gen_set_label(l2); |
a7812ae4 | 7092 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7093 | } |
7094 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 7095 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7096 | { |
a7812ae4 | 7097 | TCGv_i32 t0; |
57951c27 AJ |
7098 | int l1, l2; |
7099 | ||
7100 | l1 = gen_new_label(); | |
7101 | l2 = gen_new_label(); | |
a7812ae4 | 7102 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7103 | /* No error here: 6 bits are used */ |
7104 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7105 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7106 | tcg_gen_shl_i32(ret, arg1, t0); | |
7107 | tcg_gen_br(l2); | |
7108 | gen_set_label(l1); | |
7109 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 7110 | gen_set_label(l2); |
a7812ae4 | 7111 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7112 | } |
7113 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 7114 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7115 | { |
a7812ae4 | 7116 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
7117 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
7118 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 7119 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7120 | } |
7121 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 7122 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
7123 | { |
7124 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7125 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7126 | return; |
7127 | } | |
7128 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7129 | TCGv t0 = tcg_temp_new(); |
7130 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7131 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7132 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
7133 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7134 | tcg_temp_free(t0); | |
7135 | tcg_temp_free(t1); | |
7136 | #else | |
7137 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7138 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7139 | #endif | |
7140 | } | |
7141 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 7142 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 7143 | { |
57951c27 AJ |
7144 | tcg_gen_sub_i32(ret, arg2, arg1); |
7145 | } | |
7146 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 7147 | |
57951c27 AJ |
7148 | /* SPE arithmetic immediate */ |
7149 | #if defined(TARGET_PPC64) | |
7150 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7151 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7152 | { \ |
7153 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7154 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7155 | return; \ |
7156 | } \ | |
a7812ae4 PB |
7157 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7158 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7159 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7160 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7161 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
7162 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7163 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
e06fcd75 | 7164 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7165 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
7166 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7167 | tcg_temp_free_i32(t0); \ |
7168 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7169 | } |
7170 | #else | |
7171 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7172 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7173 | { \ |
7174 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7175 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7176 | return; \ |
7177 | } \ | |
7178 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
7179 | rA(ctx->opcode)); \ | |
7180 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ | |
7181 | rA(ctx->opcode)); \ | |
7182 | } | |
7183 | #endif | |
7184 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); | |
7185 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
7186 | ||
7187 | /* SPE comparison */ | |
7188 | #if defined(TARGET_PPC64) | |
7189 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7190 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7191 | { \ |
7192 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7193 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7194 | return; \ |
7195 | } \ | |
7196 | int l1 = gen_new_label(); \ | |
7197 | int l2 = gen_new_label(); \ | |
7198 | int l3 = gen_new_label(); \ | |
7199 | int l4 = gen_new_label(); \ | |
a7812ae4 PB |
7200 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7201 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7202 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7203 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7204 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7205 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ | |
a7812ae4 | 7206 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
7207 | tcg_gen_br(l2); \ |
7208 | gen_set_label(l1); \ | |
7209 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7210 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7211 | gen_set_label(l2); \ | |
7212 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7213 | tcg_gen_trunc_i64_i32(t0, t2); \ | |
7214 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7215 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7216 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7217 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
7218 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7219 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7220 | tcg_gen_br(l4); \ | |
7221 | gen_set_label(l3); \ | |
7222 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7223 | CRF_CH | CRF_CH_OR_CL); \ | |
7224 | gen_set_label(l4); \ | |
a7812ae4 PB |
7225 | tcg_temp_free_i32(t0); \ |
7226 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7227 | } |
7228 | #else | |
7229 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7230 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7231 | { \ |
7232 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7233 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7234 | return; \ |
7235 | } \ | |
7236 | int l1 = gen_new_label(); \ | |
7237 | int l2 = gen_new_label(); \ | |
7238 | int l3 = gen_new_label(); \ | |
7239 | int l4 = gen_new_label(); \ | |
7240 | \ | |
7241 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
7242 | cpu_gpr[rB(ctx->opcode)], l1); \ | |
7243 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ | |
7244 | tcg_gen_br(l2); \ | |
7245 | gen_set_label(l1); \ | |
7246 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7247 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7248 | gen_set_label(l2); \ | |
7249 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ | |
7250 | cpu_gprh[rB(ctx->opcode)], l3); \ | |
7251 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7252 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7253 | tcg_gen_br(l4); \ | |
7254 | gen_set_label(l3); \ | |
7255 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7256 | CRF_CH | CRF_CH_OR_CL); \ | |
7257 | gen_set_label(l4); \ | |
7258 | } | |
7259 | #endif | |
7260 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); | |
7261 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
7262 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
7263 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
7264 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
7265 | ||
7266 | /* SPE misc */ | |
636aa200 | 7267 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
7268 | { |
7269 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
7270 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
7271 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 7272 | } |
636aa200 | 7273 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
7274 | { |
7275 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7276 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7277 | return; |
7278 | } | |
7279 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7280 | TCGv t0 = tcg_temp_new(); |
7281 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7282 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7283 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); |
7284 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7285 | tcg_temp_free(t0); | |
7286 | tcg_temp_free(t1); | |
7287 | #else | |
57951c27 | 7288 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
33890b3e | 7289 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7290 | #endif |
7291 | } | |
636aa200 | 7292 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
7293 | { |
7294 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7295 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7296 | return; |
7297 | } | |
7298 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7299 | TCGv t0 = tcg_temp_new(); |
7300 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7301 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7302 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); |
7303 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7304 | tcg_temp_free(t0); | |
7305 | tcg_temp_free(t1); | |
7306 | #else | |
7307 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7308 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7309 | #endif | |
7310 | } | |
636aa200 | 7311 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
7312 | { |
7313 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7314 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7315 | return; |
7316 | } | |
7317 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7318 | TCGv t0 = tcg_temp_new(); |
7319 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7320 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7321 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
7322 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7323 | tcg_temp_free(t0); | |
7324 | tcg_temp_free(t1); | |
7325 | #else | |
33890b3e NF |
7326 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
7327 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
7328 | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); | |
7329 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7330 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); | |
7331 | tcg_temp_free_i32(tmp); | |
7332 | } else { | |
7333 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7334 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7335 | } | |
57951c27 AJ |
7336 | #endif |
7337 | } | |
636aa200 | 7338 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 7339 | { |
ae01847f | 7340 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 7341 | |
57951c27 | 7342 | #if defined(TARGET_PPC64) |
38d14952 | 7343 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7344 | #else |
7345 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7346 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7347 | #endif | |
7348 | } | |
636aa200 | 7349 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 7350 | { |
ae01847f | 7351 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 7352 | |
57951c27 | 7353 | #if defined(TARGET_PPC64) |
38d14952 | 7354 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7355 | #else |
7356 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7357 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7358 | #endif | |
0487d6a8 JM |
7359 | } |
7360 | ||
636aa200 | 7361 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 AJ |
7362 | { |
7363 | int l1 = gen_new_label(); | |
7364 | int l2 = gen_new_label(); | |
7365 | int l3 = gen_new_label(); | |
7366 | int l4 = gen_new_label(); | |
a7812ae4 | 7367 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 | 7368 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
7369 | TCGv t1 = tcg_temp_local_new(); |
7370 | TCGv t2 = tcg_temp_local_new(); | |
57951c27 AJ |
7371 | #endif |
7372 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); | |
7373 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
7374 | #if defined(TARGET_PPC64) | |
7375 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7376 | #else | |
7377 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7378 | #endif | |
7379 | tcg_gen_br(l2); | |
7380 | gen_set_label(l1); | |
7381 | #if defined(TARGET_PPC64) | |
7382 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7383 | #else | |
7384 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7385 | #endif | |
7386 | gen_set_label(l2); | |
7387 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
7388 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
7389 | #if defined(TARGET_PPC64) | |
17d9b3af | 7390 | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
7391 | #else |
7392 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7393 | #endif | |
7394 | tcg_gen_br(l4); | |
7395 | gen_set_label(l3); | |
7396 | #if defined(TARGET_PPC64) | |
17d9b3af | 7397 | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7398 | #else |
7399 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7400 | #endif | |
7401 | gen_set_label(l4); | |
a7812ae4 | 7402 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7403 | #if defined(TARGET_PPC64) |
7404 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); | |
7405 | tcg_temp_free(t1); | |
7406 | tcg_temp_free(t2); | |
7407 | #endif | |
7408 | } | |
e8eaa2c0 BS |
7409 | |
7410 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
7411 | { |
7412 | gen_evsel(ctx); | |
7413 | } | |
e8eaa2c0 BS |
7414 | |
7415 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
7416 | { |
7417 | gen_evsel(ctx); | |
7418 | } | |
e8eaa2c0 BS |
7419 | |
7420 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
7421 | { |
7422 | gen_evsel(ctx); | |
7423 | } | |
e8eaa2c0 BS |
7424 | |
7425 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
7426 | { |
7427 | gen_evsel(ctx); | |
7428 | } | |
0487d6a8 | 7429 | |
a0e13900 FC |
7430 | /* Multiply */ |
7431 | ||
7432 | static inline void gen_evmwumi(DisasContext *ctx) | |
7433 | { | |
7434 | TCGv_i64 t0, t1; | |
7435 | ||
7436 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7437 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7438 | return; |
7439 | } | |
7440 | ||
7441 | t0 = tcg_temp_new_i64(); | |
7442 | t1 = tcg_temp_new_i64(); | |
7443 | ||
7444 | /* t0 := rA; t1 := rB */ | |
7445 | #if defined(TARGET_PPC64) | |
7446 | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7447 | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7448 | #else | |
7449 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7450 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7451 | #endif | |
7452 | ||
7453 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7454 | ||
7455 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7456 | ||
7457 | tcg_temp_free_i64(t0); | |
7458 | tcg_temp_free_i64(t1); | |
7459 | } | |
7460 | ||
7461 | static inline void gen_evmwumia(DisasContext *ctx) | |
7462 | { | |
7463 | TCGv_i64 tmp; | |
7464 | ||
7465 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7466 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7467 | return; |
7468 | } | |
7469 | ||
7470 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7471 | ||
7472 | tmp = tcg_temp_new_i64(); | |
7473 | ||
7474 | /* acc := rD */ | |
7475 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7476 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7477 | tcg_temp_free_i64(tmp); |
7478 | } | |
7479 | ||
7480 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
7481 | { | |
7482 | TCGv_i64 acc; | |
7483 | TCGv_i64 tmp; | |
7484 | ||
7485 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7486 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7487 | return; |
7488 | } | |
7489 | ||
7490 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7491 | ||
7492 | acc = tcg_temp_new_i64(); | |
7493 | tmp = tcg_temp_new_i64(); | |
7494 | ||
7495 | /* tmp := rD */ | |
7496 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7497 | ||
7498 | /* Load acc */ | |
1328c2bf | 7499 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7500 | |
7501 | /* acc := tmp + acc */ | |
7502 | tcg_gen_add_i64(acc, acc, tmp); | |
7503 | ||
7504 | /* Store acc */ | |
1328c2bf | 7505 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7506 | |
7507 | /* rD := acc */ | |
7508 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7509 | ||
7510 | tcg_temp_free_i64(acc); | |
7511 | tcg_temp_free_i64(tmp); | |
7512 | } | |
7513 | ||
7514 | static inline void gen_evmwsmi(DisasContext *ctx) | |
7515 | { | |
7516 | TCGv_i64 t0, t1; | |
7517 | ||
7518 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7519 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7520 | return; |
7521 | } | |
7522 | ||
7523 | t0 = tcg_temp_new_i64(); | |
7524 | t1 = tcg_temp_new_i64(); | |
7525 | ||
7526 | /* t0 := rA; t1 := rB */ | |
7527 | #if defined(TARGET_PPC64) | |
7528 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7529 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7530 | #else | |
7531 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7532 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7533 | #endif | |
7534 | ||
7535 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7536 | ||
7537 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7538 | ||
7539 | tcg_temp_free_i64(t0); | |
7540 | tcg_temp_free_i64(t1); | |
7541 | } | |
7542 | ||
7543 | static inline void gen_evmwsmia(DisasContext *ctx) | |
7544 | { | |
7545 | TCGv_i64 tmp; | |
7546 | ||
7547 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7548 | ||
7549 | tmp = tcg_temp_new_i64(); | |
7550 | ||
7551 | /* acc := rD */ | |
7552 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7553 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7554 | |
7555 | tcg_temp_free_i64(tmp); | |
7556 | } | |
7557 | ||
7558 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
7559 | { | |
7560 | TCGv_i64 acc = tcg_temp_new_i64(); | |
7561 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
7562 | ||
7563 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7564 | ||
7565 | acc = tcg_temp_new_i64(); | |
7566 | tmp = tcg_temp_new_i64(); | |
7567 | ||
7568 | /* tmp := rD */ | |
7569 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7570 | ||
7571 | /* Load acc */ | |
1328c2bf | 7572 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7573 | |
7574 | /* acc := tmp + acc */ | |
7575 | tcg_gen_add_i64(acc, acc, tmp); | |
7576 | ||
7577 | /* Store acc */ | |
1328c2bf | 7578 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7579 | |
7580 | /* rD := acc */ | |
7581 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7582 | ||
7583 | tcg_temp_free_i64(acc); | |
7584 | tcg_temp_free_i64(tmp); | |
7585 | } | |
7586 | ||
70560da7 FC |
7587 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
7588 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7589 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7590 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7591 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7592 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7593 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7594 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // | |
7595 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); | |
7596 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7597 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7598 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7599 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7600 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7601 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7602 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
7603 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7604 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7605 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7606 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); | |
7607 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7608 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7609 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // | |
7610 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); | |
7611 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7612 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7613 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7614 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7615 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// | |
0487d6a8 | 7616 | |
6a6ae23f | 7617 | /* SPE load and stores */ |
636aa200 | 7618 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
7619 | { |
7620 | target_ulong uimm = rB(ctx->opcode); | |
7621 | ||
76db3ba4 | 7622 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 7623 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 7624 | } else { |
6a6ae23f | 7625 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
76db3ba4 AJ |
7626 | #if defined(TARGET_PPC64) |
7627 | if (!ctx->sf_mode) { | |
7628 | tcg_gen_ext32u_tl(EA, EA); | |
7629 | } | |
7630 | #endif | |
7631 | } | |
0487d6a8 | 7632 | } |
6a6ae23f | 7633 | |
636aa200 | 7634 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7635 | { |
7636 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7637 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
6a6ae23f AJ |
7638 | #else |
7639 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
76db3ba4 | 7640 | gen_qemu_ld64(ctx, t0, addr); |
6a6ae23f AJ |
7641 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7642 | tcg_gen_shri_i64(t0, t0, 32); | |
7643 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); | |
7644 | tcg_temp_free_i64(t0); | |
7645 | #endif | |
0487d6a8 | 7646 | } |
6a6ae23f | 7647 | |
636aa200 | 7648 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7649 | { |
0487d6a8 | 7650 | #if defined(TARGET_PPC64) |
6a6ae23f | 7651 | TCGv t0 = tcg_temp_new(); |
76db3ba4 | 7652 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f | 7653 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
76db3ba4 AJ |
7654 | gen_addr_add(ctx, addr, addr, 4); |
7655 | gen_qemu_ld32u(ctx, t0, addr); | |
6a6ae23f AJ |
7656 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7657 | tcg_temp_free(t0); | |
7658 | #else | |
76db3ba4 AJ |
7659 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7660 | gen_addr_add(ctx, addr, addr, 4); | |
7661 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f | 7662 | #endif |
0487d6a8 | 7663 | } |
6a6ae23f | 7664 | |
636aa200 | 7665 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7666 | { |
7667 | TCGv t0 = tcg_temp_new(); | |
7668 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7669 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7670 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7671 | gen_addr_add(ctx, addr, addr, 2); |
7672 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7673 | tcg_gen_shli_tl(t0, t0, 32); |
7674 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7675 | gen_addr_add(ctx, addr, addr, 2); |
7676 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7677 | tcg_gen_shli_tl(t0, t0, 16); |
7678 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7679 | gen_addr_add(ctx, addr, addr, 2); |
7680 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7681 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7682 | #else |
76db3ba4 | 7683 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7684 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7685 | gen_addr_add(ctx, addr, addr, 2); |
7686 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7687 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7688 | gen_addr_add(ctx, addr, addr, 2); |
7689 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7690 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7691 | gen_addr_add(ctx, addr, addr, 2); |
7692 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7693 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7694 | #endif |
6a6ae23f | 7695 | tcg_temp_free(t0); |
0487d6a8 JM |
7696 | } |
7697 | ||
636aa200 | 7698 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7699 | { |
7700 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7701 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7702 | #if defined(TARGET_PPC64) |
7703 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
7704 | tcg_gen_shli_tl(t0, t0, 16); | |
7705 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7706 | #else | |
7707 | tcg_gen_shli_tl(t0, t0, 16); | |
7708 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7709 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7710 | #endif | |
7711 | tcg_temp_free(t0); | |
0487d6a8 JM |
7712 | } |
7713 | ||
636aa200 | 7714 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7715 | { |
7716 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7717 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7718 | #if defined(TARGET_PPC64) |
7719 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7720 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7721 | #else | |
7722 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7723 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7724 | #endif | |
7725 | tcg_temp_free(t0); | |
0487d6a8 JM |
7726 | } |
7727 | ||
636aa200 | 7728 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7729 | { |
7730 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7731 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
7732 | #if defined(TARGET_PPC64) |
7733 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7734 | tcg_gen_ext32u_tl(t0, t0); | |
7735 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7736 | #else | |
7737 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7738 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7739 | #endif | |
7740 | tcg_temp_free(t0); | |
7741 | } | |
7742 | ||
636aa200 | 7743 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7744 | { |
7745 | TCGv t0 = tcg_temp_new(); | |
7746 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7747 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7748 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7749 | gen_addr_add(ctx, addr, addr, 2); |
7750 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7751 | tcg_gen_shli_tl(t0, t0, 16); |
7752 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7753 | #else | |
76db3ba4 | 7754 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7755 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7756 | gen_addr_add(ctx, addr, addr, 2); |
7757 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7758 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7759 | #endif | |
7760 | tcg_temp_free(t0); | |
7761 | } | |
7762 | ||
636aa200 | 7763 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7764 | { |
7765 | #if defined(TARGET_PPC64) | |
7766 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 AJ |
7767 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7768 | gen_addr_add(ctx, addr, addr, 2); | |
7769 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7770 | tcg_gen_shli_tl(t0, t0, 32); |
7771 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7772 | tcg_temp_free(t0); | |
7773 | #else | |
76db3ba4 AJ |
7774 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7775 | gen_addr_add(ctx, addr, addr, 2); | |
7776 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7777 | #endif |
7778 | } | |
7779 | ||
636aa200 | 7780 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7781 | { |
7782 | #if defined(TARGET_PPC64) | |
7783 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7784 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f | 7785 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7786 | gen_addr_add(ctx, addr, addr, 2); |
7787 | gen_qemu_ld16s(ctx, t0, addr); | |
6a6ae23f AJ |
7788 | tcg_gen_shli_tl(t0, t0, 32); |
7789 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7790 | tcg_temp_free(t0); | |
7791 | #else | |
76db3ba4 AJ |
7792 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7793 | gen_addr_add(ctx, addr, addr, 2); | |
7794 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7795 | #endif |
7796 | } | |
7797 | ||
636aa200 | 7798 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7799 | { |
7800 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7801 | gen_qemu_ld32u(ctx, t0, addr); |
0487d6a8 | 7802 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7803 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
7804 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7805 | #else | |
7806 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7807 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7808 | #endif | |
7809 | tcg_temp_free(t0); | |
7810 | } | |
7811 | ||
636aa200 | 7812 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7813 | { |
7814 | TCGv t0 = tcg_temp_new(); | |
7815 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7816 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7817 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
7818 | tcg_gen_shli_tl(t0, t0, 32); | |
7819 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7820 | gen_addr_add(ctx, addr, addr, 2); |
7821 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7822 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7823 | tcg_gen_shli_tl(t0, t0, 16); | |
7824 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7825 | #else | |
76db3ba4 | 7826 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7827 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
7828 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7829 | gen_addr_add(ctx, addr, addr, 2); |
7830 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7831 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7832 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
0487d6a8 | 7833 | #endif |
6a6ae23f AJ |
7834 | tcg_temp_free(t0); |
7835 | } | |
7836 | ||
636aa200 | 7837 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7838 | { |
7839 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7840 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
0487d6a8 | 7841 | #else |
6a6ae23f AJ |
7842 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7843 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); | |
76db3ba4 | 7844 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f AJ |
7845 | tcg_temp_free_i64(t0); |
7846 | #endif | |
7847 | } | |
7848 | ||
636aa200 | 7849 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7850 | { |
0487d6a8 | 7851 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7852 | TCGv t0 = tcg_temp_new(); |
7853 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7854 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7855 | tcg_temp_free(t0); |
7856 | #else | |
76db3ba4 | 7857 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7858 | #endif |
76db3ba4 AJ |
7859 | gen_addr_add(ctx, addr, addr, 4); |
7860 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7861 | } |
7862 | ||
636aa200 | 7863 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7864 | { |
7865 | TCGv t0 = tcg_temp_new(); | |
7866 | #if defined(TARGET_PPC64) | |
7867 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7868 | #else | |
7869 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7870 | #endif | |
76db3ba4 AJ |
7871 | gen_qemu_st16(ctx, t0, addr); |
7872 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f AJ |
7873 | #if defined(TARGET_PPC64) |
7874 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7875 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7876 | #else |
76db3ba4 | 7877 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7878 | #endif |
76db3ba4 | 7879 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 7880 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7881 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7882 | tcg_temp_free(t0); |
76db3ba4 AJ |
7883 | gen_addr_add(ctx, addr, addr, 2); |
7884 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7885 | } |
7886 | ||
636aa200 | 7887 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7888 | { |
7889 | TCGv t0 = tcg_temp_new(); | |
7890 | #if defined(TARGET_PPC64) | |
7891 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7892 | #else | |
7893 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7894 | #endif | |
76db3ba4 AJ |
7895 | gen_qemu_st16(ctx, t0, addr); |
7896 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 7897 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7898 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7899 | tcg_temp_free(t0); |
7900 | } | |
7901 | ||
636aa200 | 7902 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7903 | { |
7904 | #if defined(TARGET_PPC64) | |
7905 | TCGv t0 = tcg_temp_new(); | |
7906 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7907 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7908 | tcg_temp_free(t0); |
7909 | #else | |
76db3ba4 | 7910 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7911 | #endif |
76db3ba4 AJ |
7912 | gen_addr_add(ctx, addr, addr, 2); |
7913 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7914 | } |
7915 | ||
636aa200 | 7916 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7917 | { |
7918 | #if defined(TARGET_PPC64) | |
7919 | TCGv t0 = tcg_temp_new(); | |
7920 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7921 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7922 | tcg_temp_free(t0); |
7923 | #else | |
76db3ba4 | 7924 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7925 | #endif |
7926 | } | |
7927 | ||
636aa200 | 7928 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7929 | { |
76db3ba4 | 7930 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7931 | } |
7932 | ||
7933 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 7934 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
7935 | { \ |
7936 | TCGv t0; \ | |
7937 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7938 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
6a6ae23f AJ |
7939 | return; \ |
7940 | } \ | |
76db3ba4 | 7941 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
7942 | t0 = tcg_temp_new(); \ |
7943 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 7944 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 7945 | } else { \ |
76db3ba4 | 7946 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
7947 | } \ |
7948 | gen_op_##name(ctx, t0); \ | |
7949 | tcg_temp_free(t0); \ | |
7950 | } | |
7951 | ||
7952 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
7953 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
7954 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
7955 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
7956 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
7957 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
7958 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
7959 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
7960 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
7961 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
7962 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
7963 | ||
7964 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
7965 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
7966 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
7967 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
7968 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
7969 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
7970 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
7971 | |
7972 | /* Multiply and add - TODO */ | |
7973 | #if 0 | |
70560da7 FC |
7974 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
7975 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7976 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
7977 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7978 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
7979 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7980 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7981 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7982 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
7983 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7984 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
7985 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7986 | ||
7987 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7988 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7989 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7990 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7991 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7992 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7993 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7994 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7995 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7996 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7997 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7998 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
7999 | ||
8000 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8001 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8002 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8003 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8004 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); | |
8005 | ||
8006 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8007 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8008 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8009 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8010 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8011 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8012 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8013 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8014 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8015 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8016 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8017 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8018 | ||
8019 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8020 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8021 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8022 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8023 | ||
8024 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8025 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8026 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8027 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8028 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8029 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8030 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8031 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8032 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8033 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8034 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8035 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8036 | ||
8037 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8038 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8039 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8040 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8041 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
8042 | #endif |
8043 | ||
8044 | /*** SPE floating-point extension ***/ | |
1c97856d AJ |
8045 | #if defined(TARGET_PPC64) |
8046 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8047 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8048 | { \ |
1c97856d AJ |
8049 | TCGv_i32 t0; \ |
8050 | TCGv t1; \ | |
8051 | t0 = tcg_temp_new_i32(); \ | |
8052 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8053 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8054 | t1 = tcg_temp_new(); \ |
8055 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8056 | tcg_temp_free_i32(t0); \ | |
8057 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8058 | 0xFFFFFFFF00000000ULL); \ | |
8059 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8060 | tcg_temp_free(t1); \ | |
0487d6a8 | 8061 | } |
1c97856d | 8062 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8063 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8064 | { \ |
8065 | TCGv_i32 t0; \ | |
8066 | TCGv t1; \ | |
8067 | t0 = tcg_temp_new_i32(); \ | |
8e703949 | 8068 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8069 | t1 = tcg_temp_new(); \ |
8070 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8071 | tcg_temp_free_i32(t0); \ | |
8072 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8073 | 0xFFFFFFFF00000000ULL); \ | |
8074 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8075 | tcg_temp_free(t1); \ | |
8076 | } | |
8077 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8078 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8079 | { \ |
8080 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
8081 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8082 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8083 | tcg_temp_free_i32(t0); \ |
8084 | } | |
8085 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8086 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8087 | { \ |
8e703949 BS |
8088 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8089 | cpu_gpr[rB(ctx->opcode)]); \ | |
1c97856d AJ |
8090 | } |
8091 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8092 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8093 | { \ |
1c97856d AJ |
8094 | TCGv_i32 t0, t1; \ |
8095 | TCGv_i64 t2; \ | |
57951c27 | 8096 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8097 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8098 | return; \ |
8099 | } \ | |
1c97856d AJ |
8100 | t0 = tcg_temp_new_i32(); \ |
8101 | t1 = tcg_temp_new_i32(); \ | |
8102 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8103 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8104 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8105 | tcg_temp_free_i32(t1); \ |
8106 | t2 = tcg_temp_new(); \ | |
8107 | tcg_gen_extu_i32_tl(t2, t0); \ | |
8108 | tcg_temp_free_i32(t0); \ | |
8109 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8110 | 0xFFFFFFFF00000000ULL); \ | |
8111 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ | |
8112 | tcg_temp_free(t2); \ | |
57951c27 | 8113 | } |
1c97856d | 8114 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
636aa200 | 8115 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8116 | { \ |
8117 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8118 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8119 | return; \ |
8120 | } \ | |
8e703949 BS |
8121 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8122 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8123 | } |
1c97856d | 8124 | #define GEN_SPEFPUOP_COMP_32(name) \ |
636aa200 | 8125 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8126 | { \ |
1c97856d | 8127 | TCGv_i32 t0, t1; \ |
57951c27 | 8128 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8129 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8130 | return; \ |
8131 | } \ | |
1c97856d AJ |
8132 | t0 = tcg_temp_new_i32(); \ |
8133 | t1 = tcg_temp_new_i32(); \ | |
8134 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8135 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8136 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8137 | tcg_temp_free_i32(t0); \ |
8138 | tcg_temp_free_i32(t1); \ | |
8139 | } | |
8140 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8141 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8142 | { \ |
8143 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8144 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8145 | return; \ |
8146 | } \ | |
8e703949 | 8147 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8148 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8149 | } | |
8150 | #else | |
8151 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8152 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8153 | { \ |
8e703949 BS |
8154 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8155 | cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8156 | } |
1c97856d | 8157 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8158 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8159 | { \ |
8160 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8161 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8162 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8163 | tcg_temp_free_i64(t0); \ |
8164 | } | |
8165 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8166 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8167 | { \ |
8168 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8e703949 | 8169 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8170 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8171 | tcg_temp_free_i64(t0); \ | |
8172 | } | |
8173 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8174 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8175 | { \ |
8176 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8177 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8178 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8179 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8180 | tcg_temp_free_i64(t0); \ | |
8181 | } | |
8182 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8183 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8184 | { \ |
8185 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8186 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8187 | return; \ |
8188 | } \ | |
8e703949 | 8189 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8190 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8191 | } | |
8192 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 8193 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8194 | { \ |
8195 | TCGv_i64 t0, t1; \ | |
8196 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8197 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8198 | return; \ |
8199 | } \ | |
8200 | t0 = tcg_temp_new_i64(); \ | |
8201 | t1 = tcg_temp_new_i64(); \ | |
8202 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8203 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8204 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8205 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8206 | tcg_temp_free_i64(t0); \ | |
8207 | tcg_temp_free_i64(t1); \ | |
8208 | } | |
8209 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 8210 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8211 | { \ |
8212 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8213 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8214 | return; \ |
8215 | } \ | |
8e703949 | 8216 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8217 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8218 | } | |
8219 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8220 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8221 | { \ |
8222 | TCGv_i64 t0, t1; \ | |
8223 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8224 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8225 | return; \ |
8226 | } \ | |
8227 | t0 = tcg_temp_new_i64(); \ | |
8228 | t1 = tcg_temp_new_i64(); \ | |
8229 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8230 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8231 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8232 | tcg_temp_free_i64(t0); \ |
8233 | tcg_temp_free_i64(t1); \ | |
8234 | } | |
8235 | #endif | |
57951c27 | 8236 | |
0487d6a8 JM |
8237 | /* Single precision floating-point vectors operations */ |
8238 | /* Arithmetic */ | |
1c97856d AJ |
8239 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
8240 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
8241 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
8242 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 8243 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
8244 | { |
8245 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8246 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8247 | return; |
8248 | } | |
8249 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8250 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); |
1c97856d | 8251 | #else |
6d5c34fa MP |
8252 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); |
8253 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8254 | #endif |
8255 | } | |
636aa200 | 8256 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
8257 | { |
8258 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8259 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8260 | return; |
8261 | } | |
8262 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8263 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8264 | #else |
6d5c34fa MP |
8265 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8266 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8267 | #endif |
8268 | } | |
636aa200 | 8269 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
8270 | { |
8271 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8272 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8273 | return; |
8274 | } | |
8275 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8276 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8277 | #else |
6d5c34fa MP |
8278 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8279 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8280 | #endif |
8281 | } | |
8282 | ||
0487d6a8 | 8283 | /* Conversion */ |
1c97856d AJ |
8284 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8285 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
8286 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
8287 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
8288 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
8289 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
8290 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
8291 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
8292 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
8293 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
8294 | ||
0487d6a8 | 8295 | /* Comparison */ |
1c97856d AJ |
8296 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8297 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
8298 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
8299 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
8300 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
8301 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
8302 | |
8303 | /* Opcodes definitions */ | |
70560da7 FC |
8304 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8305 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8306 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8307 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8308 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8309 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8310 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8311 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8312 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8313 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8314 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8315 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8316 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8317 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8318 | |
8319 | /* Single precision floating-point operations */ | |
8320 | /* Arithmetic */ | |
1c97856d AJ |
8321 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8322 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
8323 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
8324 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 8325 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
8326 | { |
8327 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8328 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8329 | return; |
8330 | } | |
6d5c34fa | 8331 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 8332 | } |
636aa200 | 8333 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
8334 | { |
8335 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8336 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8337 | return; |
8338 | } | |
6d5c34fa | 8339 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 8340 | } |
636aa200 | 8341 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
8342 | { |
8343 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8344 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8345 | return; |
8346 | } | |
6d5c34fa | 8347 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
8348 | } |
8349 | ||
0487d6a8 | 8350 | /* Conversion */ |
1c97856d AJ |
8351 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8352 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
8353 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
8354 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
8355 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
8356 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
8357 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
8358 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
8359 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
8360 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
8361 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
8362 | ||
0487d6a8 | 8363 | /* Comparison */ |
1c97856d AJ |
8364 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
8365 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
8366 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
8367 | GEN_SPEFPUOP_COMP_32(efststgt); | |
8368 | GEN_SPEFPUOP_COMP_32(efststlt); | |
8369 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
8370 | |
8371 | /* Opcodes definitions */ | |
70560da7 FC |
8372 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8373 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8374 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8375 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8376 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8377 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // | |
8378 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8379 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8380 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8381 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8382 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8383 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8384 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8385 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8386 | |
8387 | /* Double precision floating-point operations */ | |
8388 | /* Arithmetic */ | |
1c97856d AJ |
8389 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
8390 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
8391 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
8392 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 8393 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
8394 | { |
8395 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8396 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8397 | return; |
8398 | } | |
8399 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8400 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); |
1c97856d | 8401 | #else |
6d5c34fa MP |
8402 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8403 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8404 | #endif |
8405 | } | |
636aa200 | 8406 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
8407 | { |
8408 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8409 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8410 | return; |
8411 | } | |
8412 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8413 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8414 | #else |
6d5c34fa MP |
8415 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8416 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8417 | #endif |
8418 | } | |
636aa200 | 8419 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
8420 | { |
8421 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8422 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8423 | return; |
8424 | } | |
8425 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8426 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8427 | #else |
6d5c34fa MP |
8428 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8429 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8430 | #endif |
8431 | } | |
8432 | ||
0487d6a8 | 8433 | /* Conversion */ |
1c97856d AJ |
8434 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
8435 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
8436 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
8437 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
8438 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
8439 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
8440 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
8441 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
8442 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
8443 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
8444 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
8445 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
8446 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
8447 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
8448 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 8449 | |
0487d6a8 | 8450 | /* Comparison */ |
1c97856d AJ |
8451 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
8452 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
8453 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
8454 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
8455 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
8456 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
8457 | |
8458 | /* Opcodes definitions */ | |
70560da7 FC |
8459 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
8460 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8461 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // | |
8462 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8463 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // | |
8464 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8465 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8466 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // | |
8467 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8468 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8469 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8470 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8471 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8472 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8473 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8474 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
0487d6a8 | 8475 | |
c227f099 | 8476 | static opcode_t opcodes[] = { |
5c55ff99 BS |
8477 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
8478 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
8479 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8480 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
8481 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8482 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), | |
8483 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8484 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8485 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8486 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8487 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
8488 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
8489 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
8490 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
8491 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8492 | #if defined(TARGET_PPC64) | |
8493 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
8494 | #endif | |
8495 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
8496 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
8497 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8498 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8499 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8500 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
8501 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
8502 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
8503 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8504 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8505 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8506 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8507 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), | |
eaabeef2 | 8508 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 8509 | #if defined(TARGET_PPC64) |
eaabeef2 | 8510 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 BS |
8511 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
8512 | #endif | |
8513 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8514 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8515 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8516 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
8517 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
8518 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
8519 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
8520 | #if defined(TARGET_PPC64) | |
8521 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
8522 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
8523 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
8524 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
8525 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
8526 | #endif | |
8527 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
8528 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8529 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8530 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
8531 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
8532 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), | |
8533 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), | |
8534 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
8535 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
8536 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
8537 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT), | |
8538 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT), | |
8539 | #if defined(TARGET_PPC64) | |
8540 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8541 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
8542 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8543 | #endif | |
8544 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8545 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8546 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
8547 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
8548 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
8549 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
8550 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
8551 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
f844c817 | 8552 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
5c55ff99 BS |
8553 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
8554 | #if defined(TARGET_PPC64) | |
f844c817 | 8555 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
5c55ff99 BS |
8556 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
8557 | #endif | |
8558 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
8559 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
8560 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8561 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8562 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
8563 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
8564 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), | |
8565 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
8566 | #if defined(TARGET_PPC64) | |
8567 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
8568 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
8569 | #endif | |
8570 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
8571 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
8572 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8573 | #if defined(TARGET_PPC64) | |
8574 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
8575 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8576 | #endif | |
8577 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
8578 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
8579 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
8580 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
8581 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
8582 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
8583 | #if defined(TARGET_PPC64) | |
8584 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
8585 | #endif | |
8586 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
8587 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), | |
8588 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
8589 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
8590 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
8591 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), | |
8592 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), | |
8e33944f | 8593 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
8594 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
8595 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
8596 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
8597 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
8598 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
8599 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
8600 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
8601 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
8602 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
8603 | #if defined(TARGET_PPC64) | |
8604 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
8605 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
8606 | PPC_SEGMENT_64B), | |
8607 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
8608 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
8609 | PPC_SEGMENT_64B), | |
efdef95f DG |
8610 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
8611 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
8612 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
8613 | #endif |
8614 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
8615 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
8616 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
8617 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
8618 | #if defined(TARGET_PPC64) | |
8619 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
8620 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
8621 | #endif | |
8622 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
8623 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
8624 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
8625 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
8626 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
8627 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
8628 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
8629 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
8630 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
8631 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
8632 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
8633 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8634 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
8635 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
8636 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
8637 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
8638 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
8639 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
8640 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
8641 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8642 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
8643 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
8644 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
8645 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
8646 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
8647 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
8648 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
8649 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
8650 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
8651 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
8652 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
8653 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
8654 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
8655 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
8656 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
8657 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
8658 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
8659 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
8660 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
8661 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
8662 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
8663 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
8664 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
8665 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
8666 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
8667 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
8668 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
8669 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
8670 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
8671 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8672 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8673 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
8674 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
8675 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8676 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8677 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
8678 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
8679 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
8680 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
8681 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
8682 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
8683 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
8684 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
8685 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
8686 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
8687 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
8688 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
8689 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
8690 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
8691 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
8692 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 8693 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
8694 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
8695 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
8696 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
8697 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
8698 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
8699 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
8700 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
8701 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
8702 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
8703 | PPC_NONE, PPC2_BOOKE206), | |
8704 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
8705 | PPC_NONE, PPC2_BOOKE206), | |
8706 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
8707 | PPC_NONE, PPC2_BOOKE206), | |
8708 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
8709 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
8710 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
8711 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
8712 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
8713 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
8714 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
8715 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 8716 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 8717 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 8718 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
8719 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
8720 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 8721 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
8722 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
8723 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
8724 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
8725 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
8726 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
8727 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
8728 | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), | |
8729 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), | |
8730 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
8731 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
8732 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
8733 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
8734 | ||
8735 | #undef GEN_INT_ARITH_ADD | |
8736 | #undef GEN_INT_ARITH_ADD_CONST | |
8737 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8738 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
8739 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
8740 | add_ca, compute_ca, compute_ov) \ | |
8741 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
8742 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
8743 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
8744 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
8745 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
8746 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
8747 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
8748 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
8749 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
8750 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
8751 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
8752 | ||
8753 | #undef GEN_INT_ARITH_DIVW | |
8754 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
8755 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
8756 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
8757 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
8758 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
8759 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
8760 | ||
8761 | #if defined(TARGET_PPC64) | |
8762 | #undef GEN_INT_ARITH_DIVD | |
8763 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
8764 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8765 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
8766 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
8767 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
8768 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
8769 | ||
8770 | #undef GEN_INT_ARITH_MUL_HELPER | |
8771 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
8772 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8773 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
8774 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
8775 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
8776 | #endif | |
8777 | ||
8778 | #undef GEN_INT_ARITH_SUBF | |
8779 | #undef GEN_INT_ARITH_SUBF_CONST | |
8780 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8781 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
8782 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
8783 | add_ca, compute_ca, compute_ov) \ | |
8784 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
8785 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
8786 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
8787 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
8788 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
8789 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
8790 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
8791 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
8792 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
8793 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
8794 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
8795 | ||
8796 | #undef GEN_LOGICAL1 | |
8797 | #undef GEN_LOGICAL2 | |
8798 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
8799 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
8800 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
8801 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
8802 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
8803 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
8804 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
8805 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
8806 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
8807 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
8808 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
8809 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
8810 | #if defined(TARGET_PPC64) | |
8811 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
8812 | #endif | |
8813 | ||
8814 | #if defined(TARGET_PPC64) | |
8815 | #undef GEN_PPC64_R2 | |
8816 | #undef GEN_PPC64_R4 | |
8817 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
8818 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8819 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8820 | PPC_64B) | |
8821 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
8822 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8823 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
8824 | PPC_64B), \ | |
8825 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8826 | PPC_64B), \ | |
8827 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
8828 | PPC_64B) | |
8829 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
8830 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
8831 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
8832 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
8833 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
8834 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
8835 | #endif | |
8836 | ||
8837 | #undef _GEN_FLOAT_ACB | |
8838 | #undef GEN_FLOAT_ACB | |
8839 | #undef _GEN_FLOAT_AB | |
8840 | #undef GEN_FLOAT_AB | |
8841 | #undef _GEN_FLOAT_AC | |
8842 | #undef GEN_FLOAT_AC | |
8843 | #undef GEN_FLOAT_B | |
8844 | #undef GEN_FLOAT_BS | |
8845 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
8846 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
8847 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
8848 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
8849 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
8850 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8851 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8852 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
8853 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8854 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8855 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8856 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8857 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
8858 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8859 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8860 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
8861 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
8862 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
8863 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
8864 | ||
8865 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
8866 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
8867 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
8868 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
8869 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
8870 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
8871 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
8872 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
8873 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
8874 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
8875 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
8876 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
8877 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), | |
8878 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), | |
8879 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), | |
8880 | #if defined(TARGET_PPC64) | |
8881 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), | |
8882 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), | |
8883 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), | |
8884 | #endif | |
8885 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), | |
8886 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
8887 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
8888 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
8889 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT), | |
8890 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT), | |
8891 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT), | |
8892 | ||
8893 | #undef GEN_LD | |
8894 | #undef GEN_LDU | |
8895 | #undef GEN_LDUX | |
cd6e9320 | 8896 | #undef GEN_LDX_E |
5c55ff99 BS |
8897 | #undef GEN_LDS |
8898 | #define GEN_LD(name, ldop, opc, type) \ | |
8899 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8900 | #define GEN_LDU(name, ldop, opc, type) \ | |
8901 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8902 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
8903 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
8904 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
8905 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
8906 | #define GEN_LDS(name, ldop, op, type) \ |
8907 | GEN_LD(name, ldop, op | 0x20, type) \ | |
8908 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
8909 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
8910 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
8911 | ||
8912 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
8913 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
8914 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
8915 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
8916 | #if defined(TARGET_PPC64) | |
8917 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
8918 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
8919 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
8920 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
cd6e9320 | 8921 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
8922 | #endif |
8923 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
8924 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
8925 | ||
8926 | #undef GEN_ST | |
8927 | #undef GEN_STU | |
8928 | #undef GEN_STUX | |
cd6e9320 | 8929 | #undef GEN_STX_E |
5c55ff99 BS |
8930 | #undef GEN_STS |
8931 | #define GEN_ST(name, stop, opc, type) \ | |
8932 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8933 | #define GEN_STU(name, stop, opc, type) \ | |
8934 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8935 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
8936 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
8937 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
8938 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
8939 | #define GEN_STS(name, stop, op, type) \ |
8940 | GEN_ST(name, stop, op | 0x20, type) \ | |
8941 | GEN_STU(name, stop, op | 0x21, type) \ | |
8942 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
8943 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
8944 | ||
8945 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
8946 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
8947 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
8948 | #if defined(TARGET_PPC64) | |
8949 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
8950 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
cd6e9320 | 8951 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
8952 | #endif |
8953 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
8954 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
8955 | ||
8956 | #undef GEN_LDF | |
8957 | #undef GEN_LDUF | |
8958 | #undef GEN_LDUXF | |
8959 | #undef GEN_LDXF | |
8960 | #undef GEN_LDFS | |
8961 | #define GEN_LDF(name, ldop, opc, type) \ | |
8962 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8963 | #define GEN_LDUF(name, ldop, opc, type) \ | |
8964 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8965 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
8966 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
8967 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
8968 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
8969 | #define GEN_LDFS(name, ldop, op, type) \ | |
8970 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
8971 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
8972 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
8973 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
8974 | ||
8975 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
8976 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
8977 | ||
8978 | #undef GEN_STF | |
8979 | #undef GEN_STUF | |
8980 | #undef GEN_STUXF | |
8981 | #undef GEN_STXF | |
8982 | #undef GEN_STFS | |
8983 | #define GEN_STF(name, stop, opc, type) \ | |
8984 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8985 | #define GEN_STUF(name, stop, opc, type) \ | |
8986 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8987 | #define GEN_STUXF(name, stop, opc, type) \ | |
8988 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
8989 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
8990 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
8991 | #define GEN_STFS(name, stop, op, type) \ | |
8992 | GEN_STF(name, stop, op | 0x20, type) \ | |
8993 | GEN_STUF(name, stop, op | 0x21, type) \ | |
8994 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
8995 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
8996 | ||
8997 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
8998 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
8999 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
9000 | ||
9001 | #undef GEN_CRLOGIC | |
9002 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
9003 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
9004 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
9005 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
9006 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
9007 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
9008 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
9009 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
9010 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
9011 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
9012 | ||
9013 | #undef GEN_MAC_HANDLER | |
9014 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
9015 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
9016 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
9017 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
9018 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
9019 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
9020 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
9021 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
9022 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
9023 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
9024 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
9025 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
9026 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
9027 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
9028 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
9029 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
9030 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
9031 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
9032 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
9033 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
9034 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
9035 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
9036 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
9037 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
9038 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
9039 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
9040 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
9041 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
9042 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
9043 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
9044 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
9045 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
9046 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
9047 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
9048 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
9049 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
9050 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
9051 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
9052 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
9053 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
9054 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
9055 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
9056 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
9057 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
9058 | ||
9059 | #undef GEN_VR_LDX | |
9060 | #undef GEN_VR_STX | |
9061 | #undef GEN_VR_LVE | |
9062 | #undef GEN_VR_STVE | |
9063 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
9064 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9065 | #define GEN_VR_STX(name, opc2, opc3) \ | |
9066 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9067 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
9068 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9069 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
9070 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9071 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
9072 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
9073 | GEN_VR_LVE(bx, 0x07, 0x00), | |
9074 | GEN_VR_LVE(hx, 0x07, 0x01), | |
9075 | GEN_VR_LVE(wx, 0x07, 0x02), | |
9076 | GEN_VR_STX(svx, 0x07, 0x07), | |
9077 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
9078 | GEN_VR_STVE(bx, 0x07, 0x04), | |
9079 | GEN_VR_STVE(hx, 0x07, 0x05), | |
9080 | GEN_VR_STVE(wx, 0x07, 0x06), | |
9081 | ||
9082 | #undef GEN_VX_LOGICAL | |
9083 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
9084 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9085 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), | |
9086 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
9087 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
9088 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
9089 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
9090 | ||
9091 | #undef GEN_VXFORM | |
9092 | #define GEN_VXFORM(name, opc2, opc3) \ | |
9093 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9094 | GEN_VXFORM(vaddubm, 0, 0), | |
9095 | GEN_VXFORM(vadduhm, 0, 1), | |
9096 | GEN_VXFORM(vadduwm, 0, 2), | |
9097 | GEN_VXFORM(vsububm, 0, 16), | |
9098 | GEN_VXFORM(vsubuhm, 0, 17), | |
9099 | GEN_VXFORM(vsubuwm, 0, 18), | |
9100 | GEN_VXFORM(vmaxub, 1, 0), | |
9101 | GEN_VXFORM(vmaxuh, 1, 1), | |
9102 | GEN_VXFORM(vmaxuw, 1, 2), | |
9103 | GEN_VXFORM(vmaxsb, 1, 4), | |
9104 | GEN_VXFORM(vmaxsh, 1, 5), | |
9105 | GEN_VXFORM(vmaxsw, 1, 6), | |
9106 | GEN_VXFORM(vminub, 1, 8), | |
9107 | GEN_VXFORM(vminuh, 1, 9), | |
9108 | GEN_VXFORM(vminuw, 1, 10), | |
9109 | GEN_VXFORM(vminsb, 1, 12), | |
9110 | GEN_VXFORM(vminsh, 1, 13), | |
9111 | GEN_VXFORM(vminsw, 1, 14), | |
9112 | GEN_VXFORM(vavgub, 1, 16), | |
9113 | GEN_VXFORM(vavguh, 1, 17), | |
9114 | GEN_VXFORM(vavguw, 1, 18), | |
9115 | GEN_VXFORM(vavgsb, 1, 20), | |
9116 | GEN_VXFORM(vavgsh, 1, 21), | |
9117 | GEN_VXFORM(vavgsw, 1, 22), | |
9118 | GEN_VXFORM(vmrghb, 6, 0), | |
9119 | GEN_VXFORM(vmrghh, 6, 1), | |
9120 | GEN_VXFORM(vmrghw, 6, 2), | |
9121 | GEN_VXFORM(vmrglb, 6, 4), | |
9122 | GEN_VXFORM(vmrglh, 6, 5), | |
9123 | GEN_VXFORM(vmrglw, 6, 6), | |
9124 | GEN_VXFORM(vmuloub, 4, 0), | |
9125 | GEN_VXFORM(vmulouh, 4, 1), | |
9126 | GEN_VXFORM(vmulosb, 4, 4), | |
9127 | GEN_VXFORM(vmulosh, 4, 5), | |
9128 | GEN_VXFORM(vmuleub, 4, 8), | |
9129 | GEN_VXFORM(vmuleuh, 4, 9), | |
9130 | GEN_VXFORM(vmulesb, 4, 12), | |
9131 | GEN_VXFORM(vmulesh, 4, 13), | |
9132 | GEN_VXFORM(vslb, 2, 4), | |
9133 | GEN_VXFORM(vslh, 2, 5), | |
9134 | GEN_VXFORM(vslw, 2, 6), | |
9135 | GEN_VXFORM(vsrb, 2, 8), | |
9136 | GEN_VXFORM(vsrh, 2, 9), | |
9137 | GEN_VXFORM(vsrw, 2, 10), | |
9138 | GEN_VXFORM(vsrab, 2, 12), | |
9139 | GEN_VXFORM(vsrah, 2, 13), | |
9140 | GEN_VXFORM(vsraw, 2, 14), | |
9141 | GEN_VXFORM(vslo, 6, 16), | |
9142 | GEN_VXFORM(vsro, 6, 17), | |
9143 | GEN_VXFORM(vaddcuw, 0, 6), | |
9144 | GEN_VXFORM(vsubcuw, 0, 22), | |
9145 | GEN_VXFORM(vaddubs, 0, 8), | |
9146 | GEN_VXFORM(vadduhs, 0, 9), | |
9147 | GEN_VXFORM(vadduws, 0, 10), | |
9148 | GEN_VXFORM(vaddsbs, 0, 12), | |
9149 | GEN_VXFORM(vaddshs, 0, 13), | |
9150 | GEN_VXFORM(vaddsws, 0, 14), | |
9151 | GEN_VXFORM(vsububs, 0, 24), | |
9152 | GEN_VXFORM(vsubuhs, 0, 25), | |
9153 | GEN_VXFORM(vsubuws, 0, 26), | |
9154 | GEN_VXFORM(vsubsbs, 0, 28), | |
9155 | GEN_VXFORM(vsubshs, 0, 29), | |
9156 | GEN_VXFORM(vsubsws, 0, 30), | |
9157 | GEN_VXFORM(vrlb, 2, 0), | |
9158 | GEN_VXFORM(vrlh, 2, 1), | |
9159 | GEN_VXFORM(vrlw, 2, 2), | |
9160 | GEN_VXFORM(vsl, 2, 7), | |
9161 | GEN_VXFORM(vsr, 2, 11), | |
9162 | GEN_VXFORM(vpkuhum, 7, 0), | |
9163 | GEN_VXFORM(vpkuwum, 7, 1), | |
9164 | GEN_VXFORM(vpkuhus, 7, 2), | |
9165 | GEN_VXFORM(vpkuwus, 7, 3), | |
9166 | GEN_VXFORM(vpkshus, 7, 4), | |
9167 | GEN_VXFORM(vpkswus, 7, 5), | |
9168 | GEN_VXFORM(vpkshss, 7, 6), | |
9169 | GEN_VXFORM(vpkswss, 7, 7), | |
9170 | GEN_VXFORM(vpkpx, 7, 12), | |
9171 | GEN_VXFORM(vsum4ubs, 4, 24), | |
9172 | GEN_VXFORM(vsum4sbs, 4, 28), | |
9173 | GEN_VXFORM(vsum4shs, 4, 25), | |
9174 | GEN_VXFORM(vsum2sws, 4, 26), | |
9175 | GEN_VXFORM(vsumsws, 4, 30), | |
9176 | GEN_VXFORM(vaddfp, 5, 0), | |
9177 | GEN_VXFORM(vsubfp, 5, 1), | |
9178 | GEN_VXFORM(vmaxfp, 5, 16), | |
9179 | GEN_VXFORM(vminfp, 5, 17), | |
9180 | ||
9181 | #undef GEN_VXRFORM1 | |
9182 | #undef GEN_VXRFORM | |
9183 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
9184 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
9185 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
9186 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
9187 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
9188 | GEN_VXRFORM(vcmpequb, 3, 0) | |
9189 | GEN_VXRFORM(vcmpequh, 3, 1) | |
9190 | GEN_VXRFORM(vcmpequw, 3, 2) | |
9191 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
9192 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
9193 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
9194 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
9195 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
9196 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
9197 | GEN_VXRFORM(vcmpeqfp, 3, 3) | |
9198 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
9199 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
9200 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
9201 | ||
9202 | #undef GEN_VXFORM_SIMM | |
9203 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
9204 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9205 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
9206 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
9207 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
9208 | ||
9209 | #undef GEN_VXFORM_NOA | |
9210 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
9211 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
9212 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
9213 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
9214 | GEN_VXFORM_NOA(vupklsb, 7, 10), | |
9215 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
9216 | GEN_VXFORM_NOA(vupkhpx, 7, 13), | |
9217 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
9218 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
9219 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 9220 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 BS |
9221 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
9222 | GEN_VXFORM_NOA(vrfim, 5, 8), | |
9223 | GEN_VXFORM_NOA(vrfin, 5, 9), | |
9224 | GEN_VXFORM_NOA(vrfip, 5, 10), | |
9225 | GEN_VXFORM_NOA(vrfiz, 5, 11), | |
9226 | ||
9227 | #undef GEN_VXFORM_UIMM | |
9228 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
9229 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9230 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
9231 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
9232 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
9233 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
9234 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
9235 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
9236 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
9237 | ||
9238 | #undef GEN_VAFORM_PAIRED | |
9239 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
9240 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
9241 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
9242 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
9243 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
9244 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
9245 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
9246 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
9247 | ||
9248 | #undef GEN_SPE | |
70560da7 FC |
9249 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
9250 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) | |
9251 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9252 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9253 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9254 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9255 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9256 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9257 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9258 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), | |
9259 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), | |
9260 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9261 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9262 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9263 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9264 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9265 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9266 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), | |
9267 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9268 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9269 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9270 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9271 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9272 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9273 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9274 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9275 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9276 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9277 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9278 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9279 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), | |
9280 | ||
9281 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9282 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9283 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9284 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9285 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9286 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9287 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9288 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9289 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9290 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9291 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9292 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9293 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9294 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9295 | ||
9296 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9297 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9298 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9299 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9300 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9301 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), | |
9302 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9303 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9304 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9305 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9306 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9307 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9308 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9309 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9310 | ||
9311 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9312 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9313 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), | |
9314 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9315 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9316 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9317 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9318 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), | |
9319 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9320 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9321 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9322 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9323 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9324 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9325 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9326 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
5c55ff99 BS |
9327 | |
9328 | #undef GEN_SPEOP_LDST | |
9329 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
9330 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
9331 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
9332 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
9333 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
9334 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
9335 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
9336 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
9337 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
9338 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
9339 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
9340 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
9341 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
9342 | ||
9343 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
9344 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
9345 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
9346 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
9347 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
9348 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
9349 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
9350 | }; | |
9351 | ||
0411a972 | 9352 | #include "helper_regs.h" |
a1389542 | 9353 | #include "translate_init.c" |
79aceca5 | 9354 | |
9a64fbe4 | 9355 | /*****************************************************************************/ |
3fc6c082 | 9356 | /* Misc PowerPC helpers */ |
1328c2bf | 9357 | void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf, |
36081602 | 9358 | int flags) |
79aceca5 | 9359 | { |
3fc6c082 FB |
9360 | #define RGPL 4 |
9361 | #define RFPL 4 | |
3fc6c082 | 9362 | |
79aceca5 FB |
9363 | int i; |
9364 | ||
29979a8d AG |
9365 | cpu_synchronize_state(env); |
9366 | ||
90e189ec | 9367 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9a78eead | 9368 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
da91a00f | 9369 | env->nip, env->lr, env->ctr, cpu_read_xer(env)); |
90e189ec BS |
9370 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9371 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
9372 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 9373 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 9374 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 9375 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 9376 | " DECR %08" PRIu32 |
76a66253 JM |
9377 | #endif |
9378 | "\n", | |
077fc206 | 9379 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
9380 | #if !defined(CONFIG_USER_ONLY) |
9381 | , cpu_ppc_load_decr(env) | |
9382 | #endif | |
9383 | ); | |
077fc206 | 9384 | #endif |
76a66253 | 9385 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
9386 | if ((i & (RGPL - 1)) == 0) |
9387 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 9388 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 9389 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 9390 | cpu_fprintf(f, "\n"); |
76a66253 | 9391 | } |
3fc6c082 | 9392 | cpu_fprintf(f, "CR "); |
76a66253 | 9393 | for (i = 0; i < 8; i++) |
7fe48483 FB |
9394 | cpu_fprintf(f, "%01x", env->crf[i]); |
9395 | cpu_fprintf(f, " ["); | |
76a66253 JM |
9396 | for (i = 0; i < 8; i++) { |
9397 | char a = '-'; | |
9398 | if (env->crf[i] & 0x08) | |
9399 | a = 'L'; | |
9400 | else if (env->crf[i] & 0x04) | |
9401 | a = 'G'; | |
9402 | else if (env->crf[i] & 0x02) | |
9403 | a = 'E'; | |
7fe48483 | 9404 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 9405 | } |
90e189ec BS |
9406 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
9407 | env->reserve_addr); | |
3fc6c082 FB |
9408 | for (i = 0; i < 32; i++) { |
9409 | if ((i & (RFPL - 1)) == 0) | |
9410 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 9411 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 9412 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 9413 | cpu_fprintf(f, "\n"); |
79aceca5 | 9414 | } |
30304420 | 9415 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 9416 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
9417 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
9418 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
9419 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
9420 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
9421 | ||
9422 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
9423 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
9424 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
9425 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
9426 | ||
9427 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
9428 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
9429 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
9430 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
9431 | ||
9432 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
9433 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
9434 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
9435 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
9436 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
9437 | ||
9438 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
9439 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
9440 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
9441 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
9442 | ||
9443 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
9444 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
9445 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
9446 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
9447 | ||
9448 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
9449 | " EPR " TARGET_FMT_lx "\n", | |
9450 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
9451 | env->spr[SPR_BOOKE_EPR]); | |
9452 | ||
9453 | /* FSL-specific */ | |
9454 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
9455 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
9456 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
9457 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
9458 | ||
9459 | /* | |
9460 | * IVORs are left out as they are large and do not change often -- | |
9461 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
9462 | */ | |
9463 | } | |
9464 | ||
697ab892 DG |
9465 | #if defined(TARGET_PPC64) |
9466 | if (env->flags & POWERPC_FLAG_CFAR) { | |
9467 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
9468 | } | |
9469 | #endif | |
9470 | ||
90dc8812 SW |
9471 | switch (env->mmu_model) { |
9472 | case POWERPC_MMU_32B: | |
9473 | case POWERPC_MMU_601: | |
9474 | case POWERPC_MMU_SOFT_6xx: | |
9475 | case POWERPC_MMU_SOFT_74xx: | |
9476 | #if defined(TARGET_PPC64) | |
9477 | case POWERPC_MMU_620: | |
9478 | case POWERPC_MMU_64B: | |
9479 | #endif | |
9480 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); | |
9481 | break; | |
01662f3e | 9482 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
9483 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
9484 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
9485 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
9486 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
9487 | ||
9488 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
9489 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
9490 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
9491 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
9492 | ||
9493 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
9494 | " TLB1CFG " TARGET_FMT_lx "\n", | |
9495 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
9496 | env->spr[SPR_BOOKE_TLB1CFG]); | |
9497 | break; | |
9498 | default: | |
9499 | break; | |
9500 | } | |
f2e63a42 | 9501 | #endif |
79aceca5 | 9502 | |
3fc6c082 FB |
9503 | #undef RGPL |
9504 | #undef RFPL | |
79aceca5 FB |
9505 | } |
9506 | ||
1328c2bf | 9507 | void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf, |
76a66253 JM |
9508 | int flags) |
9509 | { | |
9510 | #if defined(DO_PPC_STATISTICS) | |
c227f099 | 9511 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
9512 | int op1, op2, op3; |
9513 | ||
9514 | t1 = env->opcodes; | |
9515 | for (op1 = 0; op1 < 64; op1++) { | |
9516 | handler = t1[op1]; | |
9517 | if (is_indirect_opcode(handler)) { | |
9518 | t2 = ind_table(handler); | |
9519 | for (op2 = 0; op2 < 32; op2++) { | |
9520 | handler = t2[op2]; | |
9521 | if (is_indirect_opcode(handler)) { | |
9522 | t3 = ind_table(handler); | |
9523 | for (op3 = 0; op3 < 32; op3++) { | |
9524 | handler = t3[op3]; | |
9525 | if (handler->count == 0) | |
9526 | continue; | |
9527 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9528 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9529 | op1, op2, op3, op1, (op3 << 5) | op2, |
9530 | handler->oname, | |
9531 | handler->count, handler->count); | |
9532 | } | |
9533 | } else { | |
9534 | if (handler->count == 0) | |
9535 | continue; | |
9536 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9537 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9538 | op1, op2, op1, op2, handler->oname, |
9539 | handler->count, handler->count); | |
9540 | } | |
9541 | } | |
9542 | } else { | |
9543 | if (handler->count == 0) | |
9544 | continue; | |
0bfcd599 BS |
9545 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
9546 | " %" PRId64 "\n", | |
76a66253 JM |
9547 | op1, op1, handler->oname, |
9548 | handler->count, handler->count); | |
9549 | } | |
9550 | } | |
9551 | #endif | |
9552 | } | |
9553 | ||
9a64fbe4 | 9554 | /*****************************************************************************/ |
1328c2bf | 9555 | static inline void gen_intermediate_code_internal(CPUPPCState *env, |
636aa200 BS |
9556 | TranslationBlock *tb, |
9557 | int search_pc) | |
79aceca5 | 9558 | { |
9fddaa0c | 9559 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 9560 | opc_handler_t **table, *handler; |
0fa85d43 | 9561 | target_ulong pc_start; |
79aceca5 | 9562 | uint16_t *gen_opc_end; |
a1d1bb31 | 9563 | CPUBreakpoint *bp; |
79aceca5 | 9564 | int j, lj = -1; |
2e70f6ef PB |
9565 | int num_insns; |
9566 | int max_insns; | |
79aceca5 FB |
9567 | |
9568 | pc_start = tb->pc; | |
92414b31 | 9569 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 9570 | ctx.nip = pc_start; |
79aceca5 | 9571 | ctx.tb = tb; |
e1833e1f | 9572 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 9573 | ctx.spr_cb = env->spr_cb; |
76db3ba4 AJ |
9574 | ctx.mem_idx = env->mmu_idx; |
9575 | ctx.access_type = -1; | |
9576 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
d9bce9d9 | 9577 | #if defined(TARGET_PPC64) |
e42a61f1 | 9578 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 9579 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 9580 | #endif |
3cc62370 | 9581 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 9582 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
9583 | ctx.spe_enabled = msr_spe; |
9584 | else | |
9585 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
9586 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
9587 | ctx.altivec_enabled = msr_vr; | |
9588 | else | |
9589 | ctx.altivec_enabled = 0; | |
d26bfc9a | 9590 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 9591 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 9592 | else |
8cbcb4fa | 9593 | ctx.singlestep_enabled = 0; |
d26bfc9a | 9594 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa AJ |
9595 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
9596 | if (unlikely(env->singlestep_enabled)) | |
9597 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
3fc6c082 | 9598 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
9599 | /* Single step trace mode */ |
9600 | msr_se = 1; | |
9601 | #endif | |
2e70f6ef PB |
9602 | num_insns = 0; |
9603 | max_insns = tb->cflags & CF_COUNT_MASK; | |
9604 | if (max_insns == 0) | |
9605 | max_insns = CF_COUNT_MASK; | |
9606 | ||
9607 | gen_icount_start(); | |
9a64fbe4 | 9608 | /* Set env in case of segfault during code fetch */ |
efd7f486 EV |
9609 | while (ctx.exception == POWERPC_EXCP_NONE |
9610 | && tcg_ctx.gen_opc_ptr < gen_opc_end) { | |
72cf2d4f BS |
9611 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
9612 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 9613 | if (bp->pc == ctx.nip) { |
e06fcd75 | 9614 | gen_debug_exception(ctxp); |
ea4e754f FB |
9615 | break; |
9616 | } | |
9617 | } | |
9618 | } | |
76a66253 | 9619 | if (unlikely(search_pc)) { |
92414b31 | 9620 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
79aceca5 FB |
9621 | if (lj < j) { |
9622 | lj++; | |
9623 | while (lj < j) | |
ab1103de | 9624 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
79aceca5 | 9625 | } |
25983cad | 9626 | tcg_ctx.gen_opc_pc[lj] = ctx.nip; |
ab1103de | 9627 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 9628 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
79aceca5 | 9629 | } |
d12d51d5 | 9630 | LOG_DISAS("----------------\n"); |
90e189ec | 9631 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 9632 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
2e70f6ef PB |
9633 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9634 | gen_io_start(); | |
76db3ba4 | 9635 | if (unlikely(ctx.le_mode)) { |
2f5a189c | 9636 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 9637 | } else { |
2f5a189c | 9638 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 9639 | } |
d12d51d5 | 9640 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 9641 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
476b6d16 | 9642 | opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); |
fdefe51c | 9643 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
731c54f8 | 9644 | tcg_gen_debug_insn_start(ctx.nip); |
fdefe51c | 9645 | } |
046d6672 | 9646 | ctx.nip += 4; |
3fc6c082 | 9647 | table = env->opcodes; |
2e70f6ef | 9648 | num_insns++; |
79aceca5 FB |
9649 | handler = table[opc1(ctx.opcode)]; |
9650 | if (is_indirect_opcode(handler)) { | |
9651 | table = ind_table(handler); | |
9652 | handler = table[opc2(ctx.opcode)]; | |
9653 | if (is_indirect_opcode(handler)) { | |
9654 | table = ind_table(handler); | |
9655 | handler = table[opc3(ctx.opcode)]; | |
9656 | } | |
9657 | } | |
9658 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 9659 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
9660 | if (qemu_log_enabled()) { |
9661 | qemu_log("invalid/unsupported opcode: " | |
90e189ec BS |
9662 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
9663 | opc1(ctx.opcode), opc2(ctx.opcode), | |
9664 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa | 9665 | } |
76a66253 | 9666 | } else { |
70560da7 FC |
9667 | uint32_t inval; |
9668 | ||
9669 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
9670 | inval = handler->inval2; | |
9671 | } else { | |
9672 | inval = handler->inval1; | |
9673 | } | |
9674 | ||
9675 | if (unlikely((ctx.opcode & inval) != 0)) { | |
93fcfe39 AL |
9676 | if (qemu_log_enabled()) { |
9677 | qemu_log("invalid bits: %08x for opcode: " | |
90e189ec | 9678 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
70560da7 | 9679 | ctx.opcode & inval, opc1(ctx.opcode), |
90e189ec BS |
9680 | opc2(ctx.opcode), opc3(ctx.opcode), |
9681 | ctx.opcode, ctx.nip - 4); | |
76a66253 | 9682 | } |
e06fcd75 | 9683 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 9684 | break; |
79aceca5 | 9685 | } |
79aceca5 | 9686 | } |
4b3686fa | 9687 | (*(handler->handler))(&ctx); |
76a66253 JM |
9688 | #if defined(DO_PPC_STATISTICS) |
9689 | handler->count++; | |
9690 | #endif | |
9a64fbe4 | 9691 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
9692 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
9693 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
9694 | ctx.exception != POWERPC_SYSCALL && | |
9695 | ctx.exception != POWERPC_EXCP_TRAP && | |
9696 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 9697 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 9698 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
2e70f6ef | 9699 | (env->singlestep_enabled) || |
1b530a6d | 9700 | singlestep || |
2e70f6ef | 9701 | num_insns >= max_insns)) { |
d26bfc9a JM |
9702 | /* if we reach a page boundary or are single stepping, stop |
9703 | * generation | |
9704 | */ | |
8dd4983c | 9705 | break; |
76a66253 | 9706 | } |
3fc6c082 | 9707 | } |
2e70f6ef PB |
9708 | if (tb->cflags & CF_LAST_IO) |
9709 | gen_io_end(); | |
e1833e1f | 9710 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 9711 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 9712 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
8cbcb4fa | 9713 | if (unlikely(env->singlestep_enabled)) { |
e06fcd75 | 9714 | gen_debug_exception(ctxp); |
8cbcb4fa | 9715 | } |
76a66253 | 9716 | /* Generate the return instruction */ |
57fec1fe | 9717 | tcg_gen_exit_tb(0); |
9a64fbe4 | 9718 | } |
2e70f6ef | 9719 | gen_icount_end(tb, num_insns); |
efd7f486 | 9720 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
76a66253 | 9721 | if (unlikely(search_pc)) { |
92414b31 | 9722 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
9a64fbe4 FB |
9723 | lj++; |
9724 | while (lj <= j) | |
ab1103de | 9725 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
9a64fbe4 | 9726 | } else { |
046d6672 | 9727 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 9728 | tb->icount = num_insns; |
9a64fbe4 | 9729 | } |
d9bce9d9 | 9730 | #if defined(DEBUG_DISAS) |
8fec2b8c | 9731 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 9732 | int flags; |
237c0af0 | 9733 | flags = env->bfd_mach; |
76db3ba4 | 9734 | flags |= ctx.le_mode << 16; |
93fcfe39 | 9735 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
f4359b9f | 9736 | log_target_disas(env, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 9737 | qemu_log("\n"); |
9fddaa0c | 9738 | } |
79aceca5 | 9739 | #endif |
79aceca5 FB |
9740 | } |
9741 | ||
1328c2bf | 9742 | void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9743 | { |
2cfc5f17 | 9744 | gen_intermediate_code_internal(env, tb, 0); |
79aceca5 FB |
9745 | } |
9746 | ||
1328c2bf | 9747 | void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9748 | { |
2cfc5f17 | 9749 | gen_intermediate_code_internal(env, tb, 1); |
79aceca5 | 9750 | } |
d2856f1a | 9751 | |
1328c2bf | 9752 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 9753 | { |
25983cad | 9754 | env->nip = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 9755 | } |