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- remove the ugly "stop" pseudo-opcode.
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5
FB		 1/*
2 * PPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5
FB		 28#include "disas.h"
29
30//#define DO_SINGLE_STEP
9fddaa0c 31//#define PPC_DEBUG_DISAS
79aceca5
FB		 32
33enum {
34#define DEF(s, n, copy_size) INDEX_op_ ## s,
35#include "opc.h"
36#undef DEF
37 NB_OPS,
38};
39
40static uint16_t *gen_opc_ptr;
41static uint32_t *gen_opparam_ptr;
42
43#include "gen-op.h"
28b6751f 44
28b6751f 45#define GEN8(func, NAME) \
9a64fbe4
FB		 46static GenOpFunc *NAME ## _table [8] = { \
47NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
48NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
49}; \
50static inline void func(int n) \
51{ \
52 NAME ## _table[n](); \
53}
54
55#define GEN16(func, NAME) \
56static GenOpFunc *NAME ## _table [16] = { \
57NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
58NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
59NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
60NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
61}; \
62static inline void func(int n) \
63{ \
64 NAME ## _table[n](); \
28b6751f
FB		 65}
66
67#define GEN32(func, NAME) \
9a64fbe4
FB		 68static GenOpFunc *NAME ## _table [32] = { \
69NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
72NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
73NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
74NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
75NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
76NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
77}; \
78static inline void func(int n) \
79{ \
80 NAME ## _table[n](); \
81}
82
83/* Condition register moves */
84GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
85GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
86GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
87GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
28b6751f 88
fb0eaffc
FB		 89/* Floating point condition and status register moves */
90GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
91GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
92GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
93static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
94 &gen_op_store_T0_fpscri_fpscr0,
95 &gen_op_store_T0_fpscri_fpscr1,
96 &gen_op_store_T0_fpscri_fpscr2,
97 &gen_op_store_T0_fpscri_fpscr3,
98 &gen_op_store_T0_fpscri_fpscr4,
99 &gen_op_store_T0_fpscri_fpscr5,
100 &gen_op_store_T0_fpscri_fpscr6,
101 &gen_op_store_T0_fpscri_fpscr7,
102};
103static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
104{
105 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
106}
107
9a64fbe4
FB		 108/* Segment register moves */
109GEN16(gen_op_load_sr, gen_op_load_sr);
110GEN16(gen_op_store_sr, gen_op_store_sr);
28b6751f 111
9a64fbe4
FB		 112/* General purpose registers moves */
113GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
114GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
115GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
116
117GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
118GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
119GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
28b6751f 120
fb0eaffc
FB		 121/* floating point registers moves */
122GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
123GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
124GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
125GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
126GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
127GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
79aceca5
FB		 128
129static uint8_t spr_access[1024 / 2];
130
131/* internal defines */
132typedef struct DisasContext {
133 struct TranslationBlock *tb;
0fa85d43 134 target_ulong nip;
79aceca5 135 uint32_t opcode;
9a64fbe4 136 uint32_t exception;
3cc62370
FB		 137 /* Routine used to access memory */
138 int mem_idx;
139 /* Translation flags */
9a64fbe4 140#if !defined(CONFIG_USER_ONLY)
79aceca5 141 int supervisor;
9a64fbe4 142#endif
3cc62370 143 int fpu_enabled;
79aceca5
FB		 144} DisasContext;
145
146typedef struct opc_handler_t {
147 /* invalid bits */
148 uint32_t inval;
9a64fbe4
FB		 149 /* instruction type */
150 uint32_t type;
79aceca5
FB		 151 /* handler */
152 void (*handler)(DisasContext *ctx);
153} opc_handler_t;
154
9fddaa0c 155#define RET_EXCP(ctx, excp, error) \
79aceca5 156do { \
9fddaa0c
FB		 157 if ((ctx)->exception == EXCP_NONE) { \
158 gen_op_update_nip((ctx)->nip); \
159 } \
160 gen_op_raise_exception_err((excp), (error)); \
161 ctx->exception = (excp); \
79aceca5
FB		 162} while (0)
163
9fddaa0c
FB		 164#define RET_INVAL(ctx) \
165RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
166
167#define RET_PRIVOPC(ctx) \
168RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
9a64fbe4 169
9fddaa0c
FB		 170#define RET_PRIVREG(ctx) \
171RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
9a64fbe4 172
9fddaa0c
FB		 173#define RET_MTMSR(ctx) \
174RET_EXCP((ctx), EXCP_MTMSR, 0)
79aceca5
FB		 175
176#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
177static void gen_##name (DisasContext *ctx); \
178GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
179static void gen_##name (DisasContext *ctx)
180
79aceca5
FB		 181typedef struct opcode_t {
182 unsigned char opc1, opc2, opc3;
18fba28c
FB		 183#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
184 unsigned char pad[5];
185#else
186 unsigned char pad[1];
187#endif
79aceca5
FB		 188 opc_handler_t handler;
189} opcode_t;
190
79aceca5
FB		 191/*** Instruction decoding ***/
192#define EXTRACT_HELPER(name, shift, nb) \
193static inline uint32_t name (uint32_t opcode) \
194{ \
195 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
196}
197
198#define EXTRACT_SHELPER(name, shift, nb) \
199static inline int32_t name (uint32_t opcode) \
200{ \
18fba28c 201 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 202}
203
204/* Opcode part 1 */
205EXTRACT_HELPER(opc1, 26, 6);
206/* Opcode part 2 */
207EXTRACT_HELPER(opc2, 1, 5);
208/* Opcode part 3 */
209EXTRACT_HELPER(opc3, 6, 5);
210/* Update Cr0 flags */
211EXTRACT_HELPER(Rc, 0, 1);
212/* Destination */
213EXTRACT_HELPER(rD, 21, 5);
214/* Source */
215EXTRACT_HELPER(rS, 21, 5);
216/* First operand */
217EXTRACT_HELPER(rA, 16, 5);
218/* Second operand */
219EXTRACT_HELPER(rB, 11, 5);
220/* Third operand */
221EXTRACT_HELPER(rC, 6, 5);
222/*** Get CRn ***/
223EXTRACT_HELPER(crfD, 23, 3);
224EXTRACT_HELPER(crfS, 18, 3);
225EXTRACT_HELPER(crbD, 21, 5);
226EXTRACT_HELPER(crbA, 16, 5);
227EXTRACT_HELPER(crbB, 11, 5);
228/* SPR / TBL */
229EXTRACT_HELPER(SPR, 11, 10);
230/*** Get constants ***/
231EXTRACT_HELPER(IMM, 12, 8);
232/* 16 bits signed immediate value */
233EXTRACT_SHELPER(SIMM, 0, 16);
234/* 16 bits unsigned immediate value */
235EXTRACT_HELPER(UIMM, 0, 16);
236/* Bit count */
237EXTRACT_HELPER(NB, 11, 5);
238/* Shift count */
239EXTRACT_HELPER(SH, 11, 5);
240/* Mask start */
241EXTRACT_HELPER(MB, 6, 5);
242/* Mask end */
243EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 244/* Trap operand */
245EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 246
247EXTRACT_HELPER(CRM, 12, 8);
248EXTRACT_HELPER(FM, 17, 8);
249EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 250EXTRACT_HELPER(FPIMM, 20, 4);
251
79aceca5
FB		 252/*** Jump target decoding ***/
253/* Displacement */
254EXTRACT_SHELPER(d, 0, 16);
255/* Immediate address */
256static inline uint32_t LI (uint32_t opcode)
257{
258 return (opcode >> 0) & 0x03FFFFFC;
259}
260
261static inline uint32_t BD (uint32_t opcode)
262{
263 return (opcode >> 0) & 0xFFFC;
264}
265
266EXTRACT_HELPER(BO, 21, 5);
267EXTRACT_HELPER(BI, 16, 5);
268/* Absolute/relative address */
269EXTRACT_HELPER(AA, 1, 1);
270/* Link */
271EXTRACT_HELPER(LK, 0, 1);
272
273/* Create a mask between <start> and <end> bits */
274static inline uint32_t MASK (uint32_t start, uint32_t end)
275{
276 uint32_t ret;
277
278 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
279 if (start > end)
280 return ~ret;
281
282 return ret;
283}
284
1b039c09 285#if defined(__APPLE__)
933dc6eb 286#define OPCODES_SECTION \
1b039c09 287 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) ))
933dc6eb 288#else
1b039c09
FB		 289#define OPCODES_SECTION \
290 __attribute__ ((section(".opcodes"), unused, aligned (8) ))
933dc6eb
FB		 291#endif
292
79aceca5 293#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 294OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 295 .opc1 = op1, \
296 .opc2 = op2, \
297 .opc3 = op3, \
18fba28c 298 .pad = { 0, }, \
79aceca5
FB		 299 .handler = { \
300 .inval = invl, \
9a64fbe4 301 .type = _typ, \
79aceca5
FB		 302 .handler = &gen_##name, \
303 }, \
304}
305
306#define GEN_OPCODE_MARK(name) \
18fba28c 307OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 308 .opc1 = 0xFF, \
309 .opc2 = 0xFF, \
310 .opc3 = 0xFF, \
18fba28c 311 .pad = { 0, }, \
79aceca5
FB		 312 .handler = { \
313 .inval = 0x00000000, \
9a64fbe4 314 .type = 0x00, \
79aceca5
FB		 315 .handler = NULL, \
316 }, \
317}
318
319/* Start opcode list */
320GEN_OPCODE_MARK(start);
321
322/* Invalid instruction */
9a64fbe4
FB		 323GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
324{
9fddaa0c 325 RET_INVAL(ctx);
9a64fbe4
FB		 326}
327
79aceca5
FB		 328static opc_handler_t invalid_handler = {
329 .inval = 0xFFFFFFFF,
9a64fbe4 330 .type = PPC_NONE,
79aceca5
FB		 331 .handler = gen_invalid,
332};
333
334/*** Integer arithmetic ***/
335#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
336GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
337{ \
338 gen_op_load_gpr_T0(rA(ctx->opcode)); \
339 gen_op_load_gpr_T1(rB(ctx->opcode)); \
340 gen_op_##name(); \
341 if (Rc(ctx->opcode) != 0) \
342 gen_op_set_Rc0(); \
343 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 344}
345
346#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
347GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
348{ \
349 gen_op_load_gpr_T0(rA(ctx->opcode)); \
350 gen_op_load_gpr_T1(rB(ctx->opcode)); \
351 gen_op_##name(); \
352 if (Rc(ctx->opcode) != 0) \
18fba28c 353 gen_op_set_Rc0(); \
79aceca5 354 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 355}
356
357#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
358GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
359{ \
360 gen_op_load_gpr_T0(rA(ctx->opcode)); \
361 gen_op_##name(); \
362 if (Rc(ctx->opcode) != 0) \
363 gen_op_set_Rc0(); \
364 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 365}
366#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
367GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
368{ \
369 gen_op_load_gpr_T0(rA(ctx->opcode)); \
370 gen_op_##name(); \
371 if (Rc(ctx->opcode) != 0) \
18fba28c 372 gen_op_set_Rc0(); \
79aceca5 373 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 374}
375
376/* Two operands arithmetic functions */
377#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
378__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
379__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
380
381/* Two operands arithmetic functions with no overflow allowed */
382#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
383__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
384
385/* One operand arithmetic functions */
386#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
387__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
388__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
389
390/* add add. addo addo. */
391GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
392/* addc addc. addco addco. */
393GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
394/* adde adde. addeo addeo. */
395GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
396/* addme addme. addmeo addmeo. */
397GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
398/* addze addze. addzeo addzeo. */
399GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
400/* divw divw. divwo divwo. */
401GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
402/* divwu divwu. divwuo divwuo. */
403GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
404/* mulhw mulhw. */
405GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
406/* mulhwu mulhwu. */
407GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
408/* mullw mullw. mullwo mullwo. */
409GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
410/* neg neg. nego nego. */
411GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
412/* subf subf. subfo subfo. */
413GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
414/* subfc subfc. subfco subfco. */
415GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
416/* subfe subfe. subfeo subfeo. */
417GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
418/* subfme subfme. subfmeo subfmeo. */
419GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
420/* subfze subfze. subfzeo subfzeo. */
421GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
422/* addi */
423GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
424{
425 int32_t simm = SIMM(ctx->opcode);
426
427 if (rA(ctx->opcode) == 0) {
428 gen_op_set_T0(simm);
429 } else {
430 gen_op_load_gpr_T0(rA(ctx->opcode));
431 gen_op_addi(simm);
432 }
433 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 434}
435/* addic */
436GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
437{
438 gen_op_load_gpr_T0(rA(ctx->opcode));
439 gen_op_addic(SIMM(ctx->opcode));
440 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 441}
442/* addic. */
443GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
444{
445 gen_op_load_gpr_T0(rA(ctx->opcode));
446 gen_op_addic(SIMM(ctx->opcode));
447 gen_op_set_Rc0();
448 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 449}
450/* addis */
451GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
452{
453 int32_t simm = SIMM(ctx->opcode);
454
455 if (rA(ctx->opcode) == 0) {
456 gen_op_set_T0(simm << 16);
457 } else {
458 gen_op_load_gpr_T0(rA(ctx->opcode));
459 gen_op_addi(simm << 16);
460 }
461 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 462}
463/* mulli */
464GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
465{
466 gen_op_load_gpr_T0(rA(ctx->opcode));
467 gen_op_mulli(SIMM(ctx->opcode));
468 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 469}
470/* subfic */
471GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
472{
473 gen_op_load_gpr_T0(rA(ctx->opcode));
474 gen_op_subfic(SIMM(ctx->opcode));
475 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 476}
477
478/*** Integer comparison ***/
479#define GEN_CMP(name, opc) \
480GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
481{ \
482 gen_op_load_gpr_T0(rA(ctx->opcode)); \
483 gen_op_load_gpr_T1(rB(ctx->opcode)); \
484 gen_op_##name(); \
485 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5
FB		 486}
487
488/* cmp */
489GEN_CMP(cmp, 0x00);
490/* cmpi */
491GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
492{
493 gen_op_load_gpr_T0(rA(ctx->opcode));
494 gen_op_cmpi(SIMM(ctx->opcode));
495 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 496}
497/* cmpl */
498GEN_CMP(cmpl, 0x01);
499/* cmpli */
500GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
501{
502 gen_op_load_gpr_T0(rA(ctx->opcode));
503 gen_op_cmpli(UIMM(ctx->opcode));
504 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 505}
506
507/*** Integer logical ***/
508#define __GEN_LOGICAL2(name, opc2, opc3) \
509GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
510{ \
511 gen_op_load_gpr_T0(rS(ctx->opcode)); \
512 gen_op_load_gpr_T1(rB(ctx->opcode)); \
513 gen_op_##name(); \
514 if (Rc(ctx->opcode) != 0) \
515 gen_op_set_Rc0(); \
516 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 517}
518#define GEN_LOGICAL2(name, opc) \
519__GEN_LOGICAL2(name, 0x1C, opc)
520
521#define GEN_LOGICAL1(name, opc) \
522GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
523{ \
524 gen_op_load_gpr_T0(rS(ctx->opcode)); \
525 gen_op_##name(); \
526 if (Rc(ctx->opcode) != 0) \
527 gen_op_set_Rc0(); \
528 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 529}
530
531/* and & and. */
532GEN_LOGICAL2(and, 0x00);
533/* andc & andc. */
534GEN_LOGICAL2(andc, 0x01);
535/* andi. */
536GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
537{
538 gen_op_load_gpr_T0(rS(ctx->opcode));
539 gen_op_andi_(UIMM(ctx->opcode));
540 gen_op_set_Rc0();
541 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 542}
543/* andis. */
544GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
545{
546 gen_op_load_gpr_T0(rS(ctx->opcode));
547 gen_op_andi_(UIMM(ctx->opcode) << 16);
548 gen_op_set_Rc0();
549 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 550}
551
552/* cntlzw */
553GEN_LOGICAL1(cntlzw, 0x00);
554/* eqv & eqv. */
555GEN_LOGICAL2(eqv, 0x08);
556/* extsb & extsb. */
557GEN_LOGICAL1(extsb, 0x1D);
558/* extsh & extsh. */
559GEN_LOGICAL1(extsh, 0x1C);
560/* nand & nand. */
561GEN_LOGICAL2(nand, 0x0E);
562/* nor & nor. */
563GEN_LOGICAL2(nor, 0x03);
9a64fbe4 564
79aceca5 565/* or & or. */
9a64fbe4
FB		 566GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
567{
568 gen_op_load_gpr_T0(rS(ctx->opcode));
569 /* Optimisation for mr case */
570 if (rS(ctx->opcode) != rB(ctx->opcode)) {
571 gen_op_load_gpr_T1(rB(ctx->opcode));
572 gen_op_or();
573 }
574 if (Rc(ctx->opcode) != 0)
575 gen_op_set_Rc0();
576 gen_op_store_T0_gpr(rA(ctx->opcode));
577}
578
79aceca5
FB		 579/* orc & orc. */
580GEN_LOGICAL2(orc, 0x0C);
581/* xor & xor. */
9a64fbe4
FB		 582GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
583{
584 gen_op_load_gpr_T0(rS(ctx->opcode));
585 /* Optimisation for "set to zero" case */
586 if (rS(ctx->opcode) != rB(ctx->opcode)) {
587 gen_op_load_gpr_T1(rB(ctx->opcode));
588 gen_op_xor();
589 } else {
590 gen_op_set_T0(0);
591 }
592 if (Rc(ctx->opcode) != 0)
593 gen_op_set_Rc0();
594 gen_op_store_T0_gpr(rA(ctx->opcode));
595}
79aceca5
FB		 596/* ori */
597GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
598{
599 uint32_t uimm = UIMM(ctx->opcode);
600
9a64fbe4
FB		 601 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
602 /* NOP */
603 return;
79aceca5 604 }
79aceca5 605 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 606 if (uimm != 0)
79aceca5
FB		 607 gen_op_ori(uimm);
608 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 609}
610/* oris */
611GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
612{
613 uint32_t uimm = UIMM(ctx->opcode);
614
9a64fbe4
FB		 615 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
616 /* NOP */
617 return;
79aceca5 618 }
79aceca5 619 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 620 if (uimm != 0)
79aceca5
FB		 621 gen_op_ori(uimm << 16);
622 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 623}
624/* xori */
625GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
626{
9a64fbe4
FB		 627 uint32_t uimm = UIMM(ctx->opcode);
628
629 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
630 /* NOP */
631 return;
632 }
79aceca5 633 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 634 if (uimm != 0)
4b3686fa 635 gen_op_xori(uimm);
79aceca5 636 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 637}
638
639/* xoris */
640GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
641{
9a64fbe4
FB		 642 uint32_t uimm = UIMM(ctx->opcode);
643
644 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
645 /* NOP */
646 return;
647 }
79aceca5 648 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 649 if (uimm != 0)
4b3686fa 650 gen_op_xori(uimm << 16);
79aceca5 651 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 652}
653
654/*** Integer rotate ***/
655/* rlwimi & rlwimi. */
656GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
657{
658 uint32_t mb, me;
659
660 mb = MB(ctx->opcode);
661 me = ME(ctx->opcode);
662 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 663 gen_op_load_gpr_T1(rA(ctx->opcode));
79aceca5
FB		 664 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
665 if (Rc(ctx->opcode) != 0)
666 gen_op_set_Rc0();
667 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 668}
669/* rlwinm & rlwinm. */
670GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
671{
672 uint32_t mb, me, sh;
673
674 sh = SH(ctx->opcode);
675 mb = MB(ctx->opcode);
676 me = ME(ctx->opcode);
677 gen_op_load_gpr_T0(rS(ctx->opcode));
4b3686fa
FB		 678#if 1 // TRY
679 if (sh == 0) {
680 gen_op_andi_(MASK(mb, me));
681 goto store;
682 }
683#endif
79aceca5
FB		 684 if (mb == 0) {
685 if (me == 31) {
686 gen_op_rotlwi(sh);
687 goto store;
4b3686fa 688#if 0
79aceca5
FB		 689 } else if (me == (31 - sh)) {
690 gen_op_slwi(sh);
691 goto store;
4b3686fa 692#endif
79aceca5
FB		 693 }
694 } else if (me == 31) {
4b3686fa 695#if 0
79aceca5
FB		 696 if (sh == (32 - mb)) {
697 gen_op_srwi(mb);
698 goto store;
79aceca5 699 }
4b3686fa 700#endif
79aceca5
FB		 701 }
702 gen_op_rlwinm(sh, MASK(mb, me));
703store:
704 if (Rc(ctx->opcode) != 0)
705 gen_op_set_Rc0();
706 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 707}
708/* rlwnm & rlwnm. */
709GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
710{
711 uint32_t mb, me;
712
713 mb = MB(ctx->opcode);
714 me = ME(ctx->opcode);
715 gen_op_load_gpr_T0(rS(ctx->opcode));
716 gen_op_load_gpr_T1(rB(ctx->opcode));
717 if (mb == 0 && me == 31) {
718 gen_op_rotl();
719 } else
720 {
721 gen_op_rlwnm(MASK(mb, me));
722 }
723 if (Rc(ctx->opcode) != 0)
724 gen_op_set_Rc0();
725 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 726}
727
728/*** Integer shift ***/
729/* slw & slw. */
730__GEN_LOGICAL2(slw, 0x18, 0x00);
731/* sraw & sraw. */
732__GEN_LOGICAL2(sraw, 0x18, 0x18);
733/* srawi & srawi. */
734GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
735{
736 gen_op_load_gpr_T0(rS(ctx->opcode));
4ecc3190 737 if (SH(ctx->opcode) != 0)
79aceca5
FB		 738 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
739 if (Rc(ctx->opcode) != 0)
740 gen_op_set_Rc0();
741 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 742}
743/* srw & srw. */
744__GEN_LOGICAL2(srw, 0x18, 0x10);
745
746/*** Floating-Point arithmetic ***/
4ecc3190 747#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
9a64fbe4
FB		 748GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
749{ \
3cc62370
FB		 750 if (!ctx->fpu_enabled) { \
751 RET_EXCP(ctx, EXCP_NO_FP, 0); \
752 return; \
753 } \
9a64fbe4
FB		 754 gen_op_reset_scrfx(); \
755 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
756 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
757 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
4ecc3190
FB		 758 gen_op_f##op(); \
759 if (isfloat) { \
760 gen_op_frsp(); \
761 } \
9a64fbe4
FB		 762 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
763 if (Rc(ctx->opcode)) \
764 gen_op_set_Rc1(); \
765}
766
767#define GEN_FLOAT_ACB(name, op2) \
4ecc3190
FB		 768_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \
769_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
9a64fbe4 770
4ecc3190 771#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
9a64fbe4
FB		 772GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
773{ \
3cc62370
FB		 774 if (!ctx->fpu_enabled) { \
775 RET_EXCP(ctx, EXCP_NO_FP, 0); \
776 return; \
777 } \
9a64fbe4
FB		 778 gen_op_reset_scrfx(); \
779 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
780 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
4ecc3190
FB		 781 gen_op_f##op(); \
782 if (isfloat) { \
783 gen_op_frsp(); \
784 } \
9a64fbe4
FB		 785 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
786 if (Rc(ctx->opcode)) \
787 gen_op_set_Rc1(); \
788}
789#define GEN_FLOAT_AB(name, op2, inval) \
4ecc3190
FB		 790_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
791_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
9a64fbe4 792
4ecc3190 793#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
9a64fbe4
FB		 794GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
795{ \
3cc62370
FB		 796 if (!ctx->fpu_enabled) { \
797 RET_EXCP(ctx, EXCP_NO_FP, 0); \
798 return; \
799 } \
9a64fbe4
FB		 800 gen_op_reset_scrfx(); \
801 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
802 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
4ecc3190
FB		 803 gen_op_f##op(); \
804 if (isfloat) { \
805 gen_op_frsp(); \
806 } \
9a64fbe4
FB		 807 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
808 if (Rc(ctx->opcode)) \
809 gen_op_set_Rc1(); \
810}
811#define GEN_FLOAT_AC(name, op2, inval) \
4ecc3190
FB		 812_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
813_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
9a64fbe4
FB		 814
815#define GEN_FLOAT_B(name, op2, op3) \
816GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
817{ \
3cc62370
FB		 818 if (!ctx->fpu_enabled) { \
819 RET_EXCP(ctx, EXCP_NO_FP, 0); \
820 return; \
821 } \
9a64fbe4
FB		 822 gen_op_reset_scrfx(); \
823 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
824 gen_op_f##name(); \
825 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
826 if (Rc(ctx->opcode)) \
827 gen_op_set_Rc1(); \
79aceca5
FB		 828}
829
4ecc3190
FB		 830#define GEN_FLOAT_BS(name, op1, op2) \
831GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
9a64fbe4 832{ \
3cc62370
FB		 833 if (!ctx->fpu_enabled) { \
834 RET_EXCP(ctx, EXCP_NO_FP, 0); \
835 return; \
836 } \
9a64fbe4
FB		 837 gen_op_reset_scrfx(); \
838 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
839 gen_op_f##name(); \
840 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
841 if (Rc(ctx->opcode)) \
842 gen_op_set_Rc1(); \
79aceca5
FB		 843}
844
9a64fbe4
FB		 845/* fadd - fadds */
846GEN_FLOAT_AB(add, 0x15, 0x000007C0);
4ecc3190 847/* fdiv - fdivs */
9a64fbe4 848GEN_FLOAT_AB(div, 0x12, 0x000007C0);
4ecc3190 849/* fmul - fmuls */
9a64fbe4 850GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
79aceca5
FB		 851
852/* fres */
4ecc3190 853GEN_FLOAT_BS(res, 0x3B, 0x18);
79aceca5
FB		 854
855/* frsqrte */
4ecc3190 856GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
79aceca5
FB		 857
858/* fsel */
4ecc3190
FB		 859_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
860/* fsub - fsubs */
9a64fbe4 861GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
79aceca5
FB		 862/* Optional: */
863/* fsqrt */
c7d344af
FB		 864GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
865{
866 if (!ctx->fpu_enabled) {
867 RET_EXCP(ctx, EXCP_NO_FP, 0);
868 return;
869 }
870 gen_op_reset_scrfx();
871 gen_op_load_fpr_FT0(rB(ctx->opcode));
872 gen_op_fsqrt();
873 gen_op_store_FT0_fpr(rD(ctx->opcode));
874 if (Rc(ctx->opcode))
875 gen_op_set_Rc1();
876}
79aceca5 877
9a64fbe4 878GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
79aceca5 879{
3cc62370
FB		 880 if (!ctx->fpu_enabled) {
881 RET_EXCP(ctx, EXCP_NO_FP, 0);
882 return;
883 }
9a64fbe4
FB		 884 gen_op_reset_scrfx();
885 gen_op_load_fpr_FT0(rB(ctx->opcode));
4ecc3190
FB		 886 gen_op_fsqrt();
887 gen_op_frsp();
9a64fbe4
FB		 888 gen_op_store_FT0_fpr(rD(ctx->opcode));
889 if (Rc(ctx->opcode))
890 gen_op_set_Rc1();
79aceca5
FB		 891}
892
893/*** Floating-Point multiply-and-add ***/
4ecc3190 894/* fmadd - fmadds */
9a64fbe4 895GEN_FLOAT_ACB(madd, 0x1D);
4ecc3190 896/* fmsub - fmsubs */
9a64fbe4 897GEN_FLOAT_ACB(msub, 0x1C);
4ecc3190 898/* fnmadd - fnmadds */
9a64fbe4 899GEN_FLOAT_ACB(nmadd, 0x1F);
4ecc3190 900/* fnmsub - fnmsubs */
9a64fbe4 901GEN_FLOAT_ACB(nmsub, 0x1E);
79aceca5
FB		 902
903/*** Floating-Point round & convert ***/
904/* fctiw */
9a64fbe4 905GEN_FLOAT_B(ctiw, 0x0E, 0x00);
79aceca5 906/* fctiwz */
9a64fbe4 907GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
79aceca5 908/* frsp */
9a64fbe4 909GEN_FLOAT_B(rsp, 0x0C, 0x00);
79aceca5
FB		 910
911/*** Floating-Point compare ***/
912/* fcmpo */
913GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
914{
3cc62370
FB		 915 if (!ctx->fpu_enabled) {
916 RET_EXCP(ctx, EXCP_NO_FP, 0);
917 return;
918 }
9a64fbe4
FB		 919 gen_op_reset_scrfx();
920 gen_op_load_fpr_FT0(rA(ctx->opcode));
921 gen_op_load_fpr_FT1(rB(ctx->opcode));
922 gen_op_fcmpo();
923 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 924}
925
926/* fcmpu */
927GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
928{
3cc62370
FB		 929 if (!ctx->fpu_enabled) {
930 RET_EXCP(ctx, EXCP_NO_FP, 0);
931 return;
932 }
9a64fbe4
FB		 933 gen_op_reset_scrfx();
934 gen_op_load_fpr_FT0(rA(ctx->opcode));
935 gen_op_load_fpr_FT1(rB(ctx->opcode));
936 gen_op_fcmpu();
937 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 938}
939
9a64fbe4
FB		 940/*** Floating-point move ***/
941/* fabs */
942GEN_FLOAT_B(abs, 0x08, 0x08);
943
944/* fmr - fmr. */
945GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
946{
3cc62370
FB		 947 if (!ctx->fpu_enabled) {
948 RET_EXCP(ctx, EXCP_NO_FP, 0);
949 return;
950 }
9a64fbe4
FB		 951 gen_op_reset_scrfx();
952 gen_op_load_fpr_FT0(rB(ctx->opcode));
953 gen_op_store_FT0_fpr(rD(ctx->opcode));
954 if (Rc(ctx->opcode))
955 gen_op_set_Rc1();
956}
957
958/* fnabs */
959GEN_FLOAT_B(nabs, 0x08, 0x04);
960/* fneg */
961GEN_FLOAT_B(neg, 0x08, 0x01);
962
79aceca5
FB		 963/*** Floating-Point status & ctrl register ***/
964/* mcrfs */
965GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
966{
3cc62370
FB		 967 if (!ctx->fpu_enabled) {
968 RET_EXCP(ctx, EXCP_NO_FP, 0);
969 return;
970 }
fb0eaffc
FB		 971 gen_op_load_fpscr_T0(crfS(ctx->opcode));
972 gen_op_store_T0_crf(crfD(ctx->opcode));
973 gen_op_clear_fpscr(crfS(ctx->opcode));
79aceca5
FB		 974}
975
976/* mffs */
977GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
978{
3cc62370
FB		 979 if (!ctx->fpu_enabled) {
980 RET_EXCP(ctx, EXCP_NO_FP, 0);
981 return;
982 }
28b6751f 983 gen_op_load_fpscr();
fb0eaffc
FB		 984 gen_op_store_FT0_fpr(rD(ctx->opcode));
985 if (Rc(ctx->opcode))
986 gen_op_set_Rc1();
79aceca5
FB		 987}
988
989/* mtfsb0 */
990GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
991{
fb0eaffc
FB		 992 uint8_t crb;
993
3cc62370
FB		 994 if (!ctx->fpu_enabled) {
995 RET_EXCP(ctx, EXCP_NO_FP, 0);
996 return;
997 }
fb0eaffc
FB		 998 crb = crbD(ctx->opcode) >> 2;
999 gen_op_load_fpscr_T0(crb);
1000 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
1001 gen_op_store_T0_fpscr(crb);
1002 if (Rc(ctx->opcode))
1003 gen_op_set_Rc1();
79aceca5
FB		 1004}
1005
1006/* mtfsb1 */
1007GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1008{
fb0eaffc
FB		 1009 uint8_t crb;
1010
3cc62370
FB		 1011 if (!ctx->fpu_enabled) {
1012 RET_EXCP(ctx, EXCP_NO_FP, 0);
1013 return;
1014 }
fb0eaffc
FB		 1015 crb = crbD(ctx->opcode) >> 2;
1016 gen_op_load_fpscr_T0(crb);
1017 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1018 gen_op_store_T0_fpscr(crb);
1019 if (Rc(ctx->opcode))
1020 gen_op_set_Rc1();
79aceca5
FB		 1021}
1022
1023/* mtfsf */
1024GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1025{
3cc62370
FB		 1026 if (!ctx->fpu_enabled) {
1027 RET_EXCP(ctx, EXCP_NO_FP, 0);
1028 return;
1029 }
fb0eaffc 1030 gen_op_load_fpr_FT0(rB(ctx->opcode));
28b6751f 1031 gen_op_store_fpscr(FM(ctx->opcode));
fb0eaffc
FB		 1032 if (Rc(ctx->opcode))
1033 gen_op_set_Rc1();
79aceca5
FB		 1034}
1035
1036/* mtfsfi */
1037GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1038{
3cc62370
FB		 1039 if (!ctx->fpu_enabled) {
1040 RET_EXCP(ctx, EXCP_NO_FP, 0);
1041 return;
1042 }
fb0eaffc
FB		 1043 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1044 if (Rc(ctx->opcode))
1045 gen_op_set_Rc1();
79aceca5
FB		 1046}
1047
1048/*** Integer load ***/
9a64fbe4
FB		 1049#if defined(CONFIG_USER_ONLY)
1050#define op_ldst(name) gen_op_##name##_raw()
1051#define OP_LD_TABLE(width)
1052#define OP_ST_TABLE(width)
1053#else
1054#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
1055#define OP_LD_TABLE(width) \
1056static GenOpFunc *gen_op_l##width[] = { \
1057 &gen_op_l##width##_user, \
1058 &gen_op_l##width##_kernel, \
1059}
1060#define OP_ST_TABLE(width) \
1061static GenOpFunc *gen_op_st##width[] = { \
1062 &gen_op_st##width##_user, \
1063 &gen_op_st##width##_kernel, \
1064}
1065#endif
1066
1067#define GEN_LD(width, opc) \
79aceca5
FB		 1068GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1069{ \
1070 uint32_t simm = SIMM(ctx->opcode); \
1071 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1072 gen_op_set_T0(simm); \
79aceca5
FB		 1073 } else { \
1074 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1075 if (simm != 0) \
1076 gen_op_addi(simm); \
79aceca5 1077 } \
9a64fbe4 1078 op_ldst(l##width); \
79aceca5 1079 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1080}
1081
9a64fbe4 1082#define GEN_LDU(width, opc) \
79aceca5
FB		 1083GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1084{ \
9a64fbe4 1085 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1086 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1087 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1088 RET_INVAL(ctx); \
1089 return; \
9a64fbe4 1090 } \
79aceca5 1091 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1092 if (simm != 0) \
1093 gen_op_addi(simm); \
1094 op_ldst(l##width); \
79aceca5
FB		 1095 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1096 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1097}
1098
9a64fbe4 1099#define GEN_LDUX(width, opc) \
79aceca5
FB		 1100GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1101{ \
1102 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1103 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1104 RET_INVAL(ctx); \
1105 return; \
9a64fbe4 1106 } \
79aceca5
FB		 1107 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1108 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1109 gen_op_add(); \
1110 op_ldst(l##width); \
79aceca5
FB		 1111 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1112 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1113}
1114
9a64fbe4 1115#define GEN_LDX(width, opc2, opc3) \
79aceca5
FB		 1116GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1117{ \
1118 if (rA(ctx->opcode) == 0) { \
1119 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1120 } else { \
1121 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1122 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1123 gen_op_add(); \
79aceca5 1124 } \
9a64fbe4 1125 op_ldst(l##width); \
79aceca5 1126 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1127}
1128
9a64fbe4
FB		 1129#define GEN_LDS(width, op) \
1130OP_LD_TABLE(width); \
1131GEN_LD(width, op | 0x20); \
1132GEN_LDU(width, op | 0x21); \
1133GEN_LDUX(width, op | 0x01); \
1134GEN_LDX(width, 0x17, op | 0x00)
79aceca5
FB		 1135
1136/* lbz lbzu lbzux lbzx */
9a64fbe4 1137GEN_LDS(bz, 0x02);
79aceca5 1138/* lha lhau lhaux lhax */
9a64fbe4 1139GEN_LDS(ha, 0x0A);
79aceca5 1140/* lhz lhzu lhzux lhzx */
9a64fbe4 1141GEN_LDS(hz, 0x08);
79aceca5 1142/* lwz lwzu lwzux lwzx */
9a64fbe4 1143GEN_LDS(wz, 0x00);
79aceca5
FB		 1144
1145/*** Integer store ***/
9a64fbe4 1146#define GEN_ST(width, opc) \
79aceca5
FB		 1147GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1148{ \
1149 uint32_t simm = SIMM(ctx->opcode); \
1150 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1151 gen_op_set_T0(simm); \
79aceca5
FB		 1152 } else { \
1153 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1154 if (simm != 0) \
1155 gen_op_addi(simm); \
79aceca5 1156 } \
9a64fbe4
FB		 1157 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1158 op_ldst(st##width); \
79aceca5
FB		 1159}
1160
9a64fbe4 1161#define GEN_STU(width, opc) \
79aceca5
FB		 1162GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1163{ \
9a64fbe4
FB		 1164 uint32_t simm = SIMM(ctx->opcode); \
1165 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1166 RET_INVAL(ctx); \
1167 return; \
9a64fbe4 1168 } \
79aceca5 1169 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1170 if (simm != 0) \
1171 gen_op_addi(simm); \
79aceca5 1172 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 1173 op_ldst(st##width); \
79aceca5 1174 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1175}
1176
9a64fbe4 1177#define GEN_STUX(width, opc) \
79aceca5
FB		 1178GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1179{ \
9a64fbe4 1180 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1181 RET_INVAL(ctx); \
1182 return; \
9a64fbe4 1183 } \
79aceca5
FB		 1184 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1185 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1186 gen_op_add(); \
1187 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1188 op_ldst(st##width); \
79aceca5 1189 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1190}
1191
9a64fbe4 1192#define GEN_STX(width, opc2, opc3) \
79aceca5
FB		 1193GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1194{ \
1195 if (rA(ctx->opcode) == 0) { \
1196 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1197 } else { \
1198 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1199 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1200 gen_op_add(); \
79aceca5 1201 } \
9a64fbe4
FB		 1202 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1203 op_ldst(st##width); \
79aceca5
FB		 1204}
1205
9a64fbe4
FB		 1206#define GEN_STS(width, op) \
1207OP_ST_TABLE(width); \
1208GEN_ST(width, op | 0x20); \
1209GEN_STU(width, op | 0x21); \
1210GEN_STUX(width, op | 0x01); \
1211GEN_STX(width, 0x17, op | 0x00)
79aceca5
FB		 1212
1213/* stb stbu stbux stbx */
9a64fbe4 1214GEN_STS(b, 0x06);
79aceca5 1215/* sth sthu sthux sthx */
9a64fbe4 1216GEN_STS(h, 0x0C);
79aceca5 1217/* stw stwu stwux stwx */
9a64fbe4 1218GEN_STS(w, 0x04);
79aceca5
FB		 1219
1220/*** Integer load and store with byte reverse ***/
1221/* lhbrx */
9a64fbe4
FB		 1222OP_LD_TABLE(hbr);
1223GEN_LDX(hbr, 0x16, 0x18);
79aceca5 1224/* lwbrx */
9a64fbe4
FB		 1225OP_LD_TABLE(wbr);
1226GEN_LDX(wbr, 0x16, 0x10);
79aceca5 1227/* sthbrx */
9a64fbe4
FB		 1228OP_ST_TABLE(hbr);
1229GEN_STX(hbr, 0x16, 0x1C);
79aceca5 1230/* stwbrx */
9a64fbe4
FB		 1231OP_ST_TABLE(wbr);
1232GEN_STX(wbr, 0x16, 0x14);
79aceca5
FB		 1233
1234/*** Integer load and store multiple ***/
9a64fbe4
FB		 1235#if defined(CONFIG_USER_ONLY)
1236#define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1237#else
1238#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1239static GenOpFunc1 *gen_op_lmw[] = {
1240 &gen_op_lmw_user,
1241 &gen_op_lmw_kernel,
1242};
1243static GenOpFunc1 *gen_op_stmw[] = {
1244 &gen_op_stmw_user,
1245 &gen_op_stmw_kernel,
1246};
1247#endif
1248
79aceca5
FB		 1249/* lmw */
1250GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1251{
9a64fbe4
FB		 1252 int simm = SIMM(ctx->opcode);
1253
79aceca5 1254 if (rA(ctx->opcode) == 0) {
9a64fbe4 1255 gen_op_set_T0(simm);
79aceca5
FB		 1256 } else {
1257 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1258 if (simm != 0)
1259 gen_op_addi(simm);
79aceca5 1260 }
9a64fbe4 1261 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 1262}
1263
1264/* stmw */
1265GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1266{
9a64fbe4
FB		 1267 int simm = SIMM(ctx->opcode);
1268
79aceca5 1269 if (rA(ctx->opcode) == 0) {
9a64fbe4 1270 gen_op_set_T0(simm);
79aceca5
FB		 1271 } else {
1272 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1273 if (simm != 0)
1274 gen_op_addi(simm);
79aceca5 1275 }
9a64fbe4 1276 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 1277}
1278
1279/*** Integer load and store strings ***/
9a64fbe4
FB		 1280#if defined(CONFIG_USER_ONLY)
1281#define op_ldsts(name, start) gen_op_##name##_raw(start)
1282#define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1283#else
1284#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1285#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1286static GenOpFunc1 *gen_op_lswi[] = {
1287 &gen_op_lswi_user,
1288 &gen_op_lswi_kernel,
1289};
1290static GenOpFunc3 *gen_op_lswx[] = {
1291 &gen_op_lswx_user,
1292 &gen_op_lswx_kernel,
1293};
1294static GenOpFunc1 *gen_op_stsw[] = {
1295 &gen_op_stsw_user,
1296 &gen_op_stsw_kernel,
1297};
1298#endif
1299
79aceca5 1300/* lswi */
9a64fbe4
FB		 1301/* PPC32 specification says we must generate an exception if
1302 * rA is in the range of registers to be loaded.
1303 * In an other hand, IBM says this is valid, but rA won't be loaded.
1304 * For now, I'll follow the spec...
1305 */
79aceca5
FB		 1306GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1307{
1308 int nb = NB(ctx->opcode);
1309 int start = rD(ctx->opcode);
9a64fbe4 1310 int ra = rA(ctx->opcode);
79aceca5
FB		 1311 int nr;
1312
1313 if (nb == 0)
1314 nb = 32;
1315 nr = nb / 4;
297d8e62
FB		 1316 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1317 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
9fddaa0c
FB		 1318 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1319 return;
297d8e62 1320 }
9a64fbe4 1321 if (ra == 0) {
79aceca5
FB		 1322 gen_op_set_T0(0);
1323 } else {
9a64fbe4 1324 gen_op_load_gpr_T0(ra);
79aceca5 1325 }
9a64fbe4
FB		 1326 gen_op_set_T1(nb);
1327 op_ldsts(lswi, start);
79aceca5
FB		 1328}
1329
1330/* lswx */
1331GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1332{
9a64fbe4
FB		 1333 int ra = rA(ctx->opcode);
1334 int rb = rB(ctx->opcode);
1335
1336 if (ra == 0) {
1337 gen_op_load_gpr_T0(rb);
1338 ra = rb;
79aceca5 1339 } else {
9a64fbe4
FB		 1340 gen_op_load_gpr_T0(ra);
1341 gen_op_load_gpr_T1(rb);
1342 gen_op_add();
79aceca5 1343 }
9a64fbe4
FB		 1344 gen_op_load_xer_bc();
1345 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 1346}
1347
1348/* stswi */
1349GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1350{
4b3686fa
FB		 1351 int nb = NB(ctx->opcode);
1352
79aceca5
FB		 1353 if (rA(ctx->opcode) == 0) {
1354 gen_op_set_T0(0);
1355 } else {
1356 gen_op_load_gpr_T0(rA(ctx->opcode));
1357 }
4b3686fa
FB		 1358 if (nb == 0)
1359 nb = 32;
1360 gen_op_set_T1(nb);
9a64fbe4 1361 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1362}
1363
1364/* stswx */
1365GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1366{
9a64fbe4
FB		 1367 int ra = rA(ctx->opcode);
1368
1369 if (ra == 0) {
1370 gen_op_load_gpr_T0(rB(ctx->opcode));
1371 ra = rB(ctx->opcode);
79aceca5 1372 } else {
9a64fbe4
FB		 1373 gen_op_load_gpr_T0(ra);
1374 gen_op_load_gpr_T1(rB(ctx->opcode));
1375 gen_op_add();
79aceca5 1376 }
9a64fbe4
FB		 1377 gen_op_load_xer_bc();
1378 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1379}
1380
1381/*** Memory synchronisation ***/
1382/* eieio */
1383GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1384{
79aceca5
FB		 1385}
1386
1387/* isync */
1388GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1389{
79aceca5
FB		 1390}
1391
1392/* lwarx */
9a64fbe4 1393#if defined(CONFIG_USER_ONLY)
985a19d6 1394#define op_lwarx() gen_op_lwarx_raw()
9a64fbe4
FB		 1395#define op_stwcx() gen_op_stwcx_raw()
1396#else
985a19d6
FB		 1397#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1398static GenOpFunc *gen_op_lwarx[] = {
1399 &gen_op_lwarx_user,
1400 &gen_op_lwarx_kernel,
1401};
9a64fbe4
FB		 1402#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1403static GenOpFunc *gen_op_stwcx[] = {
1404 &gen_op_stwcx_user,
1405 &gen_op_stwcx_kernel,
1406};
1407#endif
1408
1409GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
79aceca5 1410{
79aceca5
FB		 1411 if (rA(ctx->opcode) == 0) {
1412 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1413 } else {
1414 gen_op_load_gpr_T0(rA(ctx->opcode));
1415 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1416 gen_op_add();
79aceca5 1417 }
985a19d6 1418 op_lwarx();
79aceca5 1419 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 1420}
1421
1422/* stwcx. */
9a64fbe4 1423GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 1424{
79aceca5
FB		 1425 if (rA(ctx->opcode) == 0) {
1426 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1427 } else {
1428 gen_op_load_gpr_T0(rA(ctx->opcode));
1429 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1430 gen_op_add();
79aceca5 1431 }
9a64fbe4
FB		 1432 gen_op_load_gpr_T1(rS(ctx->opcode));
1433 op_stwcx();
79aceca5
FB		 1434}
1435
1436/* sync */
1437GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1438{
79aceca5
FB		 1439}
1440
1441/*** Floating-point load ***/
9a64fbe4 1442#define GEN_LDF(width, opc) \
c7d344af 1443GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5
FB		 1444{ \
1445 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1446 if (!ctx->fpu_enabled) { \
1447 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1448 return; \
1449 } \
79aceca5 1450 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1451 gen_op_set_T0(simm); \
79aceca5
FB		 1452 } else { \
1453 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1454 if (simm != 0) \
1455 gen_op_addi(simm); \
79aceca5 1456 } \
9a64fbe4
FB		 1457 op_ldst(l##width); \
1458 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1459}
1460
9a64fbe4 1461#define GEN_LDUF(width, opc) \
c7d344af 1462GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5 1463{ \
9a64fbe4 1464 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1465 if (!ctx->fpu_enabled) { \
1466 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1467 return; \
1468 } \
79aceca5 1469 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1470 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1471 RET_INVAL(ctx); \
1472 return; \
9a64fbe4 1473 } \
79aceca5 1474 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1475 if (simm != 0) \
1476 gen_op_addi(simm); \
1477 op_ldst(l##width); \
1478 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1479 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1480}
1481
9a64fbe4 1482#define GEN_LDUXF(width, opc) \
c7d344af 1483GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
79aceca5 1484{ \
4ecc3190
FB		 1485 if (!ctx->fpu_enabled) { \
1486 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1487 return; \
1488 } \
79aceca5 1489 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1490 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1491 RET_INVAL(ctx); \
1492 return; \
9a64fbe4 1493 } \
79aceca5
FB		 1494 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1495 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1496 gen_op_add(); \
1497 op_ldst(l##width); \
1498 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1499 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1500}
1501
9a64fbe4 1502#define GEN_LDXF(width, opc2, opc3) \
c7d344af 1503GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
79aceca5 1504{ \
4ecc3190
FB		 1505 if (!ctx->fpu_enabled) { \
1506 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1507 return; \
1508 } \
79aceca5
FB		 1509 if (rA(ctx->opcode) == 0) { \
1510 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1511 } else { \
1512 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1513 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1514 gen_op_add(); \
79aceca5 1515 } \
9a64fbe4
FB		 1516 op_ldst(l##width); \
1517 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1518}
1519
9a64fbe4
FB		 1520#define GEN_LDFS(width, op) \
1521OP_LD_TABLE(width); \
1522GEN_LDF(width, op | 0x20); \
1523GEN_LDUF(width, op | 0x21); \
1524GEN_LDUXF(width, op | 0x01); \
1525GEN_LDXF(width, 0x17, op | 0x00)
79aceca5
FB		 1526
1527/* lfd lfdu lfdux lfdx */
9a64fbe4 1528GEN_LDFS(fd, 0x12);
79aceca5 1529/* lfs lfsu lfsux lfsx */
9a64fbe4 1530GEN_LDFS(fs, 0x10);
79aceca5
FB		 1531
1532/*** Floating-point store ***/
1533#define GEN_STF(width, opc) \
c7d344af 1534GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5
FB		 1535{ \
1536 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1537 if (!ctx->fpu_enabled) { \
1538 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1539 return; \
1540 } \
79aceca5 1541 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1542 gen_op_set_T0(simm); \
79aceca5
FB		 1543 } else { \
1544 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1545 if (simm != 0) \
1546 gen_op_addi(simm); \
79aceca5 1547 } \
9a64fbe4
FB		 1548 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1549 op_ldst(st##width); \
79aceca5
FB		 1550}
1551
9a64fbe4 1552#define GEN_STUF(width, opc) \
c7d344af 1553GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5 1554{ \
9a64fbe4 1555 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1556 if (!ctx->fpu_enabled) { \
1557 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1558 return; \
1559 } \
9a64fbe4 1560 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1561 RET_INVAL(ctx); \
1562 return; \
9a64fbe4 1563 } \
79aceca5 1564 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1565 if (simm != 0) \
1566 gen_op_addi(simm); \
1567 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1568 op_ldst(st##width); \
79aceca5 1569 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1570}
1571
9a64fbe4 1572#define GEN_STUXF(width, opc) \
c7d344af 1573GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
79aceca5 1574{ \
4ecc3190
FB		 1575 if (!ctx->fpu_enabled) { \
1576 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1577 return; \
1578 } \
9a64fbe4 1579 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1580 RET_INVAL(ctx); \
1581 return; \
9a64fbe4 1582 } \
79aceca5
FB		 1583 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1584 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1585 gen_op_add(); \
1586 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1587 op_ldst(st##width); \
79aceca5 1588 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1589}
1590
9a64fbe4 1591#define GEN_STXF(width, opc2, opc3) \
c7d344af 1592GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
79aceca5 1593{ \
4ecc3190
FB		 1594 if (!ctx->fpu_enabled) { \
1595 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1596 return; \
1597 } \
79aceca5
FB		 1598 if (rA(ctx->opcode) == 0) { \
1599 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1600 } else { \
1601 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1602 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1603 gen_op_add(); \
79aceca5 1604 } \
9a64fbe4
FB		 1605 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1606 op_ldst(st##width); \
79aceca5
FB		 1607}
1608
9a64fbe4
FB		 1609#define GEN_STFS(width, op) \
1610OP_ST_TABLE(width); \
1611GEN_STF(width, op | 0x20); \
1612GEN_STUF(width, op | 0x21); \
1613GEN_STUXF(width, op | 0x01); \
1614GEN_STXF(width, 0x17, op | 0x00)
79aceca5
FB		 1615
1616/* stfd stfdu stfdux stfdx */
9a64fbe4 1617GEN_STFS(fd, 0x16);
79aceca5 1618/* stfs stfsu stfsux stfsx */
9a64fbe4 1619GEN_STFS(fs, 0x14);
79aceca5
FB		 1620
1621/* Optional: */
1622/* stfiwx */
1623GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1624{
3cc62370
FB		 1625 if (!ctx->fpu_enabled) {
1626 RET_EXCP(ctx, EXCP_NO_FP, 0);
1627 return;
1628 }
9fddaa0c 1629 RET_INVAL(ctx);
79aceca5
FB		 1630}
1631
1632/*** Branch ***/
79aceca5
FB		 1633
1634/* b ba bl bla */
1635GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1636{
38a64f9d
FB		 1637 uint32_t li, target;
1638
1639 /* sign extend LI */
1640 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
79aceca5
FB		 1641
1642 if (AA(ctx->opcode) == 0)
046d6672 1643 target = ctx->nip + li - 4;
79aceca5 1644 else
9a64fbe4 1645 target = li;
9a64fbe4 1646 if (LK(ctx->opcode)) {
046d6672 1647 gen_op_setlr(ctx->nip);
9a64fbe4 1648 }
e98a6e40 1649 gen_op_b((long)ctx->tb, target);
9a64fbe4 1650 ctx->exception = EXCP_BRANCH;
79aceca5
FB		 1651}
1652
e98a6e40
FB		 1653#define BCOND_IM 0
1654#define BCOND_LR 1
1655#define BCOND_CTR 2
1656
1657static inline void gen_bcond(DisasContext *ctx, int type)
1658{
1659 uint32_t target = 0;
1660 uint32_t bo = BO(ctx->opcode);
1661 uint32_t bi = BI(ctx->opcode);
1662 uint32_t mask;
1663 uint32_t li;
1664
e98a6e40
FB		 1665 if ((bo & 0x4) == 0)
1666 gen_op_dec_ctr();
1667 switch(type) {
1668 case BCOND_IM:
18fba28c 1669 li = (int32_t)((int16_t)(BD(ctx->opcode)));
e98a6e40 1670 if (AA(ctx->opcode) == 0) {
046d6672 1671 target = ctx->nip + li - 4;
e98a6e40
FB		 1672 } else {
1673 target = li;
1674 }
1675 break;
1676 case BCOND_CTR:
1677 gen_op_movl_T1_ctr();
1678 break;
1679 default:
1680 case BCOND_LR:
1681 gen_op_movl_T1_lr();
1682 break;
1683 }
1684 if (LK(ctx->opcode)) {
046d6672 1685 gen_op_setlr(ctx->nip);
e98a6e40
FB		 1686 }
1687 if (bo & 0x10) {
1688 /* No CR condition */
1689 switch (bo & 0x6) {
1690 case 0:
1691 gen_op_test_ctr();
1692 break;
1693 case 2:
1694 gen_op_test_ctrz();
1695 break;
1696 default:
1697 case 4:
1698 case 6:
1699 if (type == BCOND_IM) {
1700 gen_op_b((long)ctx->tb, target);
1701 } else {
1702 gen_op_b_T1();
e98a6e40
FB		 1703 }
1704 goto no_test;
1705 }
1706 } else {
1707 mask = 1 << (3 - (bi & 0x03));
1708 gen_op_load_crf_T0(bi >> 2);
1709 if (bo & 0x8) {
1710 switch (bo & 0x6) {
1711 case 0:
1712 gen_op_test_ctr_true(mask);
1713 break;
1714 case 2:
1715 gen_op_test_ctrz_true(mask);
1716 break;
1717 default:
1718 case 4:
1719 case 6:
1720 gen_op_test_true(mask);
1721 break;
1722 }
1723 } else {
1724 switch (bo & 0x6) {
1725 case 0:
1726 gen_op_test_ctr_false(mask);
1727 break;
1728 case 2:
1729 gen_op_test_ctrz_false(mask);
1730 break;
1731 default:
1732 case 4:
1733 case 6:
1734 gen_op_test_false(mask);
1735 break;
1736 }
1737 }
1738 }
1739 if (type == BCOND_IM) {
046d6672 1740 gen_op_btest((long)ctx->tb, target, ctx->nip);
e98a6e40 1741 } else {
046d6672 1742 gen_op_btest_T1(ctx->nip);
e98a6e40
FB		 1743 }
1744 no_test:
1745 ctx->exception = EXCP_BRANCH;
1746}
1747
1748GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1749{
1750 gen_bcond(ctx, BCOND_IM);
1751}
1752
1753GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1754{
1755 gen_bcond(ctx, BCOND_CTR);
1756}
1757
1758GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1759{
1760 gen_bcond(ctx, BCOND_LR);
1761}
79aceca5
FB		 1762
1763/*** Condition register logical ***/
1764#define GEN_CRLOGIC(op, opc) \
1765GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1766{ \
1767 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1768 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1769 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1770 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1771 gen_op_##op(); \
1772 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1773 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1774 3 - (crbD(ctx->opcode) & 0x03)); \
1775 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 1776}
1777
1778/* crand */
1779GEN_CRLOGIC(and, 0x08)
1780/* crandc */
1781GEN_CRLOGIC(andc, 0x04)
1782/* creqv */
1783GEN_CRLOGIC(eqv, 0x09)
1784/* crnand */
1785GEN_CRLOGIC(nand, 0x07)
1786/* crnor */
1787GEN_CRLOGIC(nor, 0x01)
1788/* cror */
1789GEN_CRLOGIC(or, 0x0E)
1790/* crorc */
1791GEN_CRLOGIC(orc, 0x0D)
1792/* crxor */
1793GEN_CRLOGIC(xor, 0x06)
1794/* mcrf */
1795GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1796{
1797 gen_op_load_crf_T0(crfS(ctx->opcode));
1798 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1799}
1800
1801/*** System linkage ***/
1802/* rfi (supervisor only) */
1803GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1804{
9a64fbe4 1805#if defined(CONFIG_USER_ONLY)
9fddaa0c 1806 RET_PRIVOPC(ctx);
9a64fbe4
FB		 1807#else
1808 /* Restore CPU state */
1809 if (!ctx->supervisor) {
9fddaa0c
FB		 1810 RET_PRIVOPC(ctx);
1811 return;
9a64fbe4
FB		 1812 }
1813 gen_op_rfi();
9fddaa0c 1814 RET_EXCP(ctx, EXCP_RFI, 0);
9a64fbe4 1815#endif
79aceca5
FB		 1816}
1817
1818/* sc */
1819GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1820{
9a64fbe4 1821#if defined(CONFIG_USER_ONLY)
9fddaa0c 1822 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
9a64fbe4 1823#else
9fddaa0c 1824 RET_EXCP(ctx, EXCP_SYSCALL, 0);
9a64fbe4 1825#endif
79aceca5
FB		 1826}
1827
1828/*** Trap ***/
1829/* tw */
1830GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1831{
9a64fbe4
FB		 1832 gen_op_load_gpr_T0(rA(ctx->opcode));
1833 gen_op_load_gpr_T1(rB(ctx->opcode));
1834 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 1835}
1836
1837/* twi */
1838GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1839{
9a64fbe4
FB		 1840 gen_op_load_gpr_T0(rA(ctx->opcode));
1841#if 0
1842 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1843 SIMM(ctx->opcode), TO(ctx->opcode));
1844#endif
1845 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
79aceca5
FB		 1846}
1847
1848/*** Processor control ***/
1849static inline int check_spr_access (int spr, int rw, int supervisor)
1850{
1851 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1852
9a64fbe4
FB		 1853#if 0
1854 if (spr != LR && spr != CTR) {
1855 if (loglevel > 0) {
1856 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1857 SPR_ENCODE(spr), supervisor, rw, rights,
1858 (rights >> ((2 * supervisor) + rw)) & 1);
1859 } else {
1860 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1861 SPR_ENCODE(spr), supervisor, rw, rights,
1862 (rights >> ((2 * supervisor) + rw)) & 1);
1863 }
1864 }
1865#endif
1866 if (rights == 0)
1867 return -1;
79aceca5
FB		 1868 rights = rights >> (2 * supervisor);
1869 rights = rights >> rw;
1870
1871 return rights & 1;
1872}
1873
1874/* mcrxr */
1875GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1876{
1877 gen_op_load_xer_cr();
1878 gen_op_store_T0_crf(crfD(ctx->opcode));
1879 gen_op_clear_xer_cr();
79aceca5
FB		 1880}
1881
1882/* mfcr */
1883GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1884{
1885 gen_op_load_cr();
1886 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1887}
1888
1889/* mfmsr */
1890GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1891{
9a64fbe4 1892#if defined(CONFIG_USER_ONLY)
9fddaa0c 1893 RET_PRIVREG(ctx);
9a64fbe4
FB		 1894#else
1895 if (!ctx->supervisor) {
9fddaa0c
FB		 1896 RET_PRIVREG(ctx);
1897 return;
9a64fbe4 1898 }
79aceca5
FB		 1899 gen_op_load_msr();
1900 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 1901#endif
79aceca5
FB		 1902}
1903
1904/* mfspr */
1905GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1906{
1907 uint32_t sprn = SPR(ctx->opcode);
1908
9a64fbe4
FB		 1909#if defined(CONFIG_USER_ONLY)
1910 switch (check_spr_access(sprn, 0, 0))
1911#else
1912 switch (check_spr_access(sprn, 0, ctx->supervisor))
1913#endif
1914 {
1915 case -1:
9fddaa0c
FB		 1916 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1917 return;
9a64fbe4 1918 case 0:
9fddaa0c
FB		 1919 RET_PRIVREG(ctx);
1920 return;
9a64fbe4
FB		 1921 default:
1922 break;
79aceca5 1923 }
9a64fbe4
FB		 1924 switch (sprn) {
1925 case XER:
79aceca5
FB		 1926 gen_op_load_xer();
1927 break;
9a64fbe4
FB		 1928 case LR:
1929 gen_op_load_lr();
1930 break;
1931 case CTR:
1932 gen_op_load_ctr();
1933 break;
1934 case IBAT0U:
1935 gen_op_load_ibat(0, 0);
1936 break;
1937 case IBAT1U:
1938 gen_op_load_ibat(0, 1);
1939 break;
1940 case IBAT2U:
1941 gen_op_load_ibat(0, 2);
1942 break;
1943 case IBAT3U:
1944 gen_op_load_ibat(0, 3);
1945 break;
1946 case IBAT4U:
1947 gen_op_load_ibat(0, 4);
1948 break;
1949 case IBAT5U:
1950 gen_op_load_ibat(0, 5);
1951 break;
1952 case IBAT6U:
1953 gen_op_load_ibat(0, 6);
1954 break;
1955 case IBAT7U:
1956 gen_op_load_ibat(0, 7);
1957 break;
1958 case IBAT0L:
1959 gen_op_load_ibat(1, 0);
1960 break;
1961 case IBAT1L:
1962 gen_op_load_ibat(1, 1);
1963 break;
1964 case IBAT2L:
1965 gen_op_load_ibat(1, 2);
1966 break;
1967 case IBAT3L:
1968 gen_op_load_ibat(1, 3);
1969 break;
1970 case IBAT4L:
1971 gen_op_load_ibat(1, 4);
1972 break;
1973 case IBAT5L:
1974 gen_op_load_ibat(1, 5);
1975 break;
1976 case IBAT6L:
1977 gen_op_load_ibat(1, 6);
1978 break;
1979 case IBAT7L:
1980 gen_op_load_ibat(1, 7);
1981 break;
1982 case DBAT0U:
1983 gen_op_load_dbat(0, 0);
1984 break;
1985 case DBAT1U:
1986 gen_op_load_dbat(0, 1);
1987 break;
1988 case DBAT2U:
1989 gen_op_load_dbat(0, 2);
1990 break;
1991 case DBAT3U:
1992 gen_op_load_dbat(0, 3);
1993 break;
1994 case DBAT4U:
1995 gen_op_load_dbat(0, 4);
1996 break;
1997 case DBAT5U:
1998 gen_op_load_dbat(0, 5);
1999 break;
2000 case DBAT6U:
2001 gen_op_load_dbat(0, 6);
2002 break;
2003 case DBAT7U:
2004 gen_op_load_dbat(0, 7);
2005 break;
2006 case DBAT0L:
2007 gen_op_load_dbat(1, 0);
2008 break;
2009 case DBAT1L:
2010 gen_op_load_dbat(1, 1);
2011 break;
2012 case DBAT2L:
2013 gen_op_load_dbat(1, 2);
2014 break;
2015 case DBAT3L:
2016 gen_op_load_dbat(1, 3);
2017 break;
2018 case DBAT4L:
2019 gen_op_load_dbat(1, 4);
2020 break;
2021 case DBAT5L:
2022 gen_op_load_dbat(1, 5);
2023 break;
2024 case DBAT6L:
2025 gen_op_load_dbat(1, 6);
2026 break;
2027 case DBAT7L:
2028 gen_op_load_dbat(1, 7);
2029 break;
2030 case SDR1:
2031 gen_op_load_sdr1();
2032 break;
2033 case V_TBL:
9fddaa0c 2034 gen_op_load_tbl();
79aceca5 2035 break;
9a64fbe4 2036 case V_TBU:
9fddaa0c 2037 gen_op_load_tbu();
9a64fbe4
FB		 2038 break;
2039 case DECR:
9fddaa0c 2040 gen_op_load_decr();
79aceca5
FB		 2041 break;
2042 default:
2043 gen_op_load_spr(sprn);
2044 break;
2045 }
9a64fbe4 2046 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2047}
2048
2049/* mftb */
2050GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
2051{
2052 uint32_t sprn = SPR(ctx->opcode);
2053
79aceca5 2054 /* We need to update the time base before reading it */
9a64fbe4
FB		 2055 switch (sprn) {
2056 case V_TBL:
9fddaa0c 2057 gen_op_load_tbl();
79aceca5 2058 break;
9a64fbe4 2059 case V_TBU:
9fddaa0c 2060 gen_op_load_tbu();
79aceca5
FB		 2061 break;
2062 default:
9fddaa0c
FB		 2063 RET_INVAL(ctx);
2064 return;
79aceca5 2065 }
9a64fbe4 2066 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2067}
2068
2069/* mtcrf */
2070GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
2071{
2072 gen_op_load_gpr_T0(rS(ctx->opcode));
2073 gen_op_store_cr(CRM(ctx->opcode));
79aceca5
FB		 2074}
2075
2076/* mtmsr */
2077GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2078{
9a64fbe4 2079#if defined(CONFIG_USER_ONLY)
9fddaa0c 2080 RET_PRIVREG(ctx);
9a64fbe4
FB		 2081#else
2082 if (!ctx->supervisor) {
9fddaa0c
FB		 2083 RET_PRIVREG(ctx);
2084 return;
9a64fbe4 2085 }
79aceca5
FB		 2086 gen_op_load_gpr_T0(rS(ctx->opcode));
2087 gen_op_store_msr();
2088 /* Must stop the translation as machine state (may have) changed */
9fddaa0c 2089 RET_MTMSR(ctx);
9a64fbe4 2090#endif
79aceca5
FB		 2091}
2092
2093/* mtspr */
2094GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2095{
2096 uint32_t sprn = SPR(ctx->opcode);
2097
9a64fbe4
FB		 2098#if 0
2099 if (loglevel > 0) {
2100 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
2101 rS(ctx->opcode), sprn);
2102 }
2103#endif
2104#if defined(CONFIG_USER_ONLY)
2105 switch (check_spr_access(sprn, 1, 0))
2106#else
2107 switch (check_spr_access(sprn, 1, ctx->supervisor))
2108#endif
2109 {
2110 case -1:
9fddaa0c 2111 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
9a64fbe4
FB		 2112 break;
2113 case 0:
9fddaa0c 2114 RET_PRIVREG(ctx);
9a64fbe4
FB		 2115 break;
2116 default:
2117 break;
2118 }
79aceca5 2119 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4
FB		 2120 switch (sprn) {
2121 case XER:
79aceca5 2122 gen_op_store_xer();
9a64fbe4
FB		 2123 break;
2124 case LR:
9a64fbe4
FB		 2125 gen_op_store_lr();
2126 break;
2127 case CTR:
2128 gen_op_store_ctr();
2129 break;
2130 case IBAT0U:
2131 gen_op_store_ibat(0, 0);
4b3686fa 2132 RET_MTMSR(ctx);
9a64fbe4
FB		 2133 break;
2134 case IBAT1U:
2135 gen_op_store_ibat(0, 1);
4b3686fa 2136 RET_MTMSR(ctx);
9a64fbe4
FB		 2137 break;
2138 case IBAT2U:
2139 gen_op_store_ibat(0, 2);
4b3686fa 2140 RET_MTMSR(ctx);
9a64fbe4
FB		 2141 break;
2142 case IBAT3U:
2143 gen_op_store_ibat(0, 3);
4b3686fa 2144 RET_MTMSR(ctx);
9a64fbe4
FB		 2145 break;
2146 case IBAT4U:
2147 gen_op_store_ibat(0, 4);
4b3686fa 2148 RET_MTMSR(ctx);
9a64fbe4
FB		 2149 break;
2150 case IBAT5U:
2151 gen_op_store_ibat(0, 5);
4b3686fa 2152 RET_MTMSR(ctx);
9a64fbe4
FB		 2153 break;
2154 case IBAT6U:
2155 gen_op_store_ibat(0, 6);
4b3686fa 2156 RET_MTMSR(ctx);
9a64fbe4
FB		 2157 break;
2158 case IBAT7U:
2159 gen_op_store_ibat(0, 7);
4b3686fa 2160 RET_MTMSR(ctx);
9a64fbe4
FB		 2161 break;
2162 case IBAT0L:
2163 gen_op_store_ibat(1, 0);
4b3686fa 2164 RET_MTMSR(ctx);
9a64fbe4
FB		 2165 break;
2166 case IBAT1L:
2167 gen_op_store_ibat(1, 1);
4b3686fa 2168 RET_MTMSR(ctx);
9a64fbe4
FB		 2169 break;
2170 case IBAT2L:
2171 gen_op_store_ibat(1, 2);
4b3686fa 2172 RET_MTMSR(ctx);
9a64fbe4
FB		 2173 break;
2174 case IBAT3L:
2175 gen_op_store_ibat(1, 3);
4b3686fa 2176 RET_MTMSR(ctx);
9a64fbe4
FB		 2177 break;
2178 case IBAT4L:
2179 gen_op_store_ibat(1, 4);
4b3686fa 2180 RET_MTMSR(ctx);
9a64fbe4
FB		 2181 break;
2182 case IBAT5L:
2183 gen_op_store_ibat(1, 5);
4b3686fa 2184 RET_MTMSR(ctx);
9a64fbe4
FB		 2185 break;
2186 case IBAT6L:
2187 gen_op_store_ibat(1, 6);
4b3686fa 2188 RET_MTMSR(ctx);
9a64fbe4
FB		 2189 break;
2190 case IBAT7L:
2191 gen_op_store_ibat(1, 7);
4b3686fa 2192 RET_MTMSR(ctx);
9a64fbe4
FB		 2193 break;
2194 case DBAT0U:
2195 gen_op_store_dbat(0, 0);
4b3686fa 2196 RET_MTMSR(ctx);
9a64fbe4
FB		 2197 break;
2198 case DBAT1U:
2199 gen_op_store_dbat(0, 1);
4b3686fa 2200 RET_MTMSR(ctx);
9a64fbe4
FB		 2201 break;
2202 case DBAT2U:
2203 gen_op_store_dbat(0, 2);
4b3686fa 2204 RET_MTMSR(ctx);
9a64fbe4
FB		 2205 break;
2206 case DBAT3U:
2207 gen_op_store_dbat(0, 3);
4b3686fa 2208 RET_MTMSR(ctx);
9a64fbe4
FB		 2209 break;
2210 case DBAT4U:
2211 gen_op_store_dbat(0, 4);
4b3686fa 2212 RET_MTMSR(ctx);
9a64fbe4
FB		 2213 break;
2214 case DBAT5U:
2215 gen_op_store_dbat(0, 5);
4b3686fa 2216 RET_MTMSR(ctx);
9a64fbe4
FB		 2217 break;
2218 case DBAT6U:
2219 gen_op_store_dbat(0, 6);
4b3686fa 2220 RET_MTMSR(ctx);
9a64fbe4
FB		 2221 break;
2222 case DBAT7U:
2223 gen_op_store_dbat(0, 7);
4b3686fa 2224 RET_MTMSR(ctx);
9a64fbe4
FB		 2225 break;
2226 case DBAT0L:
2227 gen_op_store_dbat(1, 0);
4b3686fa 2228 RET_MTMSR(ctx);
9a64fbe4
FB		 2229 break;
2230 case DBAT1L:
2231 gen_op_store_dbat(1, 1);
4b3686fa 2232 RET_MTMSR(ctx);
9a64fbe4
FB		 2233 break;
2234 case DBAT2L:
2235 gen_op_store_dbat(1, 2);
4b3686fa 2236 RET_MTMSR(ctx);
9a64fbe4
FB		 2237 break;
2238 case DBAT3L:
2239 gen_op_store_dbat(1, 3);
4b3686fa 2240 RET_MTMSR(ctx);
9a64fbe4
FB		 2241 break;
2242 case DBAT4L:
2243 gen_op_store_dbat(1, 4);
4b3686fa 2244 RET_MTMSR(ctx);
9a64fbe4
FB		 2245 break;
2246 case DBAT5L:
2247 gen_op_store_dbat(1, 5);
4b3686fa 2248 RET_MTMSR(ctx);
9a64fbe4
FB		 2249 break;
2250 case DBAT6L:
2251 gen_op_store_dbat(1, 6);
4b3686fa 2252 RET_MTMSR(ctx);
9a64fbe4
FB		 2253 break;
2254 case DBAT7L:
2255 gen_op_store_dbat(1, 7);
4b3686fa 2256 RET_MTMSR(ctx);
9a64fbe4
FB		 2257 break;
2258 case SDR1:
2259 gen_op_store_sdr1();
4b3686fa 2260 RET_MTMSR(ctx);
9a64fbe4
FB		 2261 break;
2262 case O_TBL:
9fddaa0c 2263 gen_op_store_tbl();
9a64fbe4
FB		 2264 break;
2265 case O_TBU:
9fddaa0c 2266 gen_op_store_tbu();
9a64fbe4
FB		 2267 break;
2268 case DECR:
2269 gen_op_store_decr();
9a64fbe4
FB		 2270 break;
2271 default:
79aceca5 2272 gen_op_store_spr(sprn);
9a64fbe4 2273 break;
79aceca5 2274 }
79aceca5
FB		 2275}
2276
2277/*** Cache management ***/
2278/* For now, all those will be implemented as nop:
2279 * this is valid, regarding the PowerPC specs...
9a64fbe4 2280 * We just have to flush tb while invalidating instruction cache lines...
79aceca5
FB		 2281 */
2282/* dcbf */
9a64fbe4 2283GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
79aceca5 2284{
a541f297
FB		 2285 if (rA(ctx->opcode) == 0) {
2286 gen_op_load_gpr_T0(rB(ctx->opcode));
2287 } else {
2288 gen_op_load_gpr_T0(rA(ctx->opcode));
2289 gen_op_load_gpr_T1(rB(ctx->opcode));
2290 gen_op_add();
2291 }
2292 op_ldst(lbz);
79aceca5
FB		 2293}
2294
2295/* dcbi (Supervisor only) */
9a64fbe4 2296GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 2297{
a541f297 2298#if defined(CONFIG_USER_ONLY)
9fddaa0c 2299 RET_PRIVOPC(ctx);
a541f297
FB		 2300#else
2301 if (!ctx->supervisor) {
9fddaa0c
FB		 2302 RET_PRIVOPC(ctx);
2303 return;
9a64fbe4 2304 }
a541f297
FB		 2305 if (rA(ctx->opcode) == 0) {
2306 gen_op_load_gpr_T0(rB(ctx->opcode));
2307 } else {
2308 gen_op_load_gpr_T0(rA(ctx->opcode));
2309 gen_op_load_gpr_T1(rB(ctx->opcode));
2310 gen_op_add();
2311 }
2312 op_ldst(lbz);
2313 op_ldst(stb);
2314#endif
79aceca5
FB		 2315}
2316
2317/* dcdst */
9a64fbe4 2318GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 2319{
a541f297
FB		 2320 if (rA(ctx->opcode) == 0) {
2321 gen_op_load_gpr_T0(rB(ctx->opcode));
2322 } else {
2323 gen_op_load_gpr_T0(rA(ctx->opcode));
2324 gen_op_load_gpr_T1(rB(ctx->opcode));
2325 gen_op_add();
2326 }
2327 op_ldst(lbz);
79aceca5
FB		 2328}
2329
2330/* dcbt */
9a64fbe4 2331GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
79aceca5 2332{
79aceca5
FB		 2333}
2334
2335/* dcbtst */
9a64fbe4 2336GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
79aceca5 2337{
79aceca5
FB		 2338}
2339
2340/* dcbz */
9a64fbe4
FB		 2341#if defined(CONFIG_USER_ONLY)
2342#define op_dcbz() gen_op_dcbz_raw()
2343#else
2344#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2345static GenOpFunc *gen_op_dcbz[] = {
2346 &gen_op_dcbz_user,
2347 &gen_op_dcbz_kernel,
2348};
2349#endif
2350
2351GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
79aceca5 2352{
fb0eaffc
FB		 2353 if (rA(ctx->opcode) == 0) {
2354 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2355 } else {
2356 gen_op_load_gpr_T0(rA(ctx->opcode));
2357 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2358 gen_op_add();
fb0eaffc 2359 }
9a64fbe4 2360 op_dcbz();
4b3686fa 2361 gen_op_check_reservation();
79aceca5
FB		 2362}
2363
2364/* icbi */
9a64fbe4 2365GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
79aceca5 2366{
fb0eaffc
FB		 2367 if (rA(ctx->opcode) == 0) {
2368 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2369 } else {
2370 gen_op_load_gpr_T0(rA(ctx->opcode));
2371 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2372 gen_op_add();
fb0eaffc 2373 }
9a64fbe4 2374 gen_op_icbi();
79aceca5
FB		 2375}
2376
2377/* Optional: */
2378/* dcba */
c7d344af 2379GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT)
79aceca5 2380{
79aceca5
FB		 2381}
2382
2383/*** Segment register manipulation ***/
2384/* Supervisor only: */
2385/* mfsr */
2386GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2387{
9a64fbe4 2388#if defined(CONFIG_USER_ONLY)
9fddaa0c 2389 RET_PRIVREG(ctx);
9a64fbe4
FB		 2390#else
2391 if (!ctx->supervisor) {
9fddaa0c
FB		 2392 RET_PRIVREG(ctx);
2393 return;
9a64fbe4
FB		 2394 }
2395 gen_op_load_sr(SR(ctx->opcode));
2396 gen_op_store_T0_gpr(rD(ctx->opcode));
2397#endif
79aceca5
FB		 2398}
2399
2400/* mfsrin */
9a64fbe4 2401GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 2402{
9a64fbe4 2403#if defined(CONFIG_USER_ONLY)
9fddaa0c 2404 RET_PRIVREG(ctx);
9a64fbe4
FB		 2405#else
2406 if (!ctx->supervisor) {
9fddaa0c
FB		 2407 RET_PRIVREG(ctx);
2408 return;
9a64fbe4
FB		 2409 }
2410 gen_op_load_gpr_T1(rB(ctx->opcode));
2411 gen_op_load_srin();
2412 gen_op_store_T0_gpr(rD(ctx->opcode));
2413#endif
79aceca5
FB		 2414}
2415
2416/* mtsr */
e63c59cb 2417GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 2418{
9a64fbe4 2419#if defined(CONFIG_USER_ONLY)
9fddaa0c 2420 RET_PRIVREG(ctx);
9a64fbe4
FB		 2421#else
2422 if (!ctx->supervisor) {
9fddaa0c
FB		 2423 RET_PRIVREG(ctx);
2424 return;
9a64fbe4
FB		 2425 }
2426 gen_op_load_gpr_T0(rS(ctx->opcode));
2427 gen_op_store_sr(SR(ctx->opcode));
9a64fbe4 2428#endif
79aceca5
FB		 2429}
2430
2431/* mtsrin */
9a64fbe4 2432GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 2433{
9a64fbe4 2434#if defined(CONFIG_USER_ONLY)
9fddaa0c 2435 RET_PRIVREG(ctx);
9a64fbe4
FB		 2436#else
2437 if (!ctx->supervisor) {
9fddaa0c
FB		 2438 RET_PRIVREG(ctx);
2439 return;
9a64fbe4
FB		 2440 }
2441 gen_op_load_gpr_T0(rS(ctx->opcode));
2442 gen_op_load_gpr_T1(rB(ctx->opcode));
2443 gen_op_store_srin();
9a64fbe4 2444#endif
79aceca5
FB		 2445}
2446
2447/*** Lookaside buffer management ***/
2448/* Optional & supervisor only: */
2449/* tlbia */
9a64fbe4 2450GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
79aceca5 2451{
9a64fbe4 2452#if defined(CONFIG_USER_ONLY)
9fddaa0c 2453 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2454#else
2455 if (!ctx->supervisor) {
9fddaa0c
FB		 2456 if (loglevel)
2457 fprintf(logfile, "%s: ! supervisor\n", __func__);
2458 RET_PRIVOPC(ctx);
2459 return;
9a64fbe4
FB		 2460 }
2461 gen_op_tlbia();
4b3686fa 2462 RET_MTMSR(ctx);
9a64fbe4 2463#endif
79aceca5
FB		 2464}
2465
2466/* tlbie */
9a64fbe4 2467GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
79aceca5 2468{
9a64fbe4 2469#if defined(CONFIG_USER_ONLY)
9fddaa0c 2470 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2471#else
2472 if (!ctx->supervisor) {
9fddaa0c
FB		 2473 RET_PRIVOPC(ctx);
2474 return;
9a64fbe4
FB		 2475 }
2476 gen_op_load_gpr_T0(rB(ctx->opcode));
2477 gen_op_tlbie();
4b3686fa 2478 RET_MTMSR(ctx);
9a64fbe4 2479#endif
79aceca5
FB		 2480}
2481
2482/* tlbsync */
e63c59cb 2483GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
79aceca5 2484{
9a64fbe4 2485#if defined(CONFIG_USER_ONLY)
9fddaa0c 2486 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2487#else
2488 if (!ctx->supervisor) {
9fddaa0c
FB		 2489 RET_PRIVOPC(ctx);
2490 return;
9a64fbe4
FB		 2491 }
2492 /* This has no effect: it should ensure that all previous
2493 * tlbie have completed
2494 */
4b3686fa 2495 RET_MTMSR(ctx);
9a64fbe4 2496#endif
79aceca5
FB		 2497}
2498
2499/*** External control ***/
2500/* Optional: */
2501/* eciwx */
9a64fbe4
FB		 2502#if defined(CONFIG_USER_ONLY)
2503#define op_eciwx() gen_op_eciwx_raw()
2504#define op_ecowx() gen_op_ecowx_raw()
2505#else
2506#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2507#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2508static GenOpFunc *gen_op_eciwx[] = {
2509 &gen_op_eciwx_user,
2510 &gen_op_eciwx_kernel,
2511};
2512static GenOpFunc *gen_op_ecowx[] = {
2513 &gen_op_ecowx_user,
2514 &gen_op_ecowx_kernel,
2515};
2516#endif
2517
79aceca5
FB		 2518GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2519{
9a64fbe4
FB		 2520 /* Should check EAR[E] & alignment ! */
2521 if (rA(ctx->opcode) == 0) {
2522 gen_op_load_gpr_T0(rB(ctx->opcode));
2523 } else {
2524 gen_op_load_gpr_T0(rA(ctx->opcode));
2525 gen_op_load_gpr_T1(rB(ctx->opcode));
2526 gen_op_add();
2527 }
2528 op_eciwx();
2529 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2530}
2531
2532/* ecowx */
2533GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2534{
9a64fbe4
FB		 2535 /* Should check EAR[E] & alignment ! */
2536 if (rA(ctx->opcode) == 0) {
2537 gen_op_load_gpr_T0(rB(ctx->opcode));
2538 } else {
2539 gen_op_load_gpr_T0(rA(ctx->opcode));
2540 gen_op_load_gpr_T1(rB(ctx->opcode));
2541 gen_op_add();
2542 }
2543 gen_op_load_gpr_T2(rS(ctx->opcode));
2544 op_ecowx();
79aceca5
FB		 2545}
2546
2547/* End opcode list */
2548GEN_OPCODE_MARK(end);
2549
2550/*****************************************************************************/
9a64fbe4 2551#include <stdlib.h>
79aceca5 2552#include <string.h>
9a64fbe4
FB		 2553
2554int fflush (FILE *stream);
79aceca5
FB		 2555
2556/* Main ppc opcodes table:
2557 * at init, all opcodes are invalids
2558 */
2559static opc_handler_t *ppc_opcodes[0x40];
2560
2561/* Opcode types */
2562enum {
2563 PPC_DIRECT = 0, /* Opcode routine */
2564 PPC_INDIRECT = 1, /* Indirect opcode table */
2565};
2566
2567static inline int is_indirect_opcode (void *handler)
2568{
2569 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2570}
2571
2572static inline opc_handler_t **ind_table(void *handler)
2573{
2574 return (opc_handler_t **)((unsigned long)handler & ~3);
2575}
2576
9a64fbe4 2577/* Instruction table creation */
79aceca5
FB		 2578/* Opcodes tables creation */
2579static void fill_new_table (opc_handler_t **table, int len)
2580{
2581 int i;
2582
2583 for (i = 0; i < len; i++)
2584 table[i] = &invalid_handler;
2585}
2586
2587static int create_new_table (opc_handler_t **table, unsigned char idx)
2588{
2589 opc_handler_t **tmp;
2590
2591 tmp = malloc(0x20 * sizeof(opc_handler_t));
2592 if (tmp == NULL)
2593 return -1;
2594 fill_new_table(tmp, 0x20);
2595 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2596
2597 return 0;
2598}
2599
2600static int insert_in_table (opc_handler_t **table, unsigned char idx,
2601 opc_handler_t *handler)
2602{
2603 if (table[idx] != &invalid_handler)
2604 return -1;
2605 table[idx] = handler;
2606
2607 return 0;
2608}
2609
9a64fbe4
FB		 2610static int register_direct_insn (opc_handler_t **ppc_opcodes,
2611 unsigned char idx, opc_handler_t *handler)
79aceca5
FB		 2612{
2613 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9a64fbe4 2614 printf("*** ERROR: opcode %02x already assigned in main "
79aceca5
FB		 2615 "opcode table\n", idx);
2616 return -1;
2617 }
2618
2619 return 0;
2620}
2621
2622static int register_ind_in_table (opc_handler_t **table,
2623 unsigned char idx1, unsigned char idx2,
2624 opc_handler_t *handler)
2625{
2626 if (table[idx1] == &invalid_handler) {
2627 if (create_new_table(table, idx1) < 0) {
9a64fbe4 2628 printf("*** ERROR: unable to create indirect table "
79aceca5
FB		 2629 "idx=%02x\n", idx1);
2630 return -1;
2631 }
2632 } else {
2633 if (!is_indirect_opcode(table[idx1])) {
9a64fbe4 2634 printf("*** ERROR: idx %02x already assigned to a direct "
79aceca5
FB		 2635 "opcode\n", idx1);
2636 return -1;
2637 }
2638 }
2639 if (handler != NULL &&
2640 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9a64fbe4 2641 printf("*** ERROR: opcode %02x already assigned in "
79aceca5
FB		 2642 "opcode table %02x\n", idx2, idx1);
2643 return -1;
2644 }
2645
2646 return 0;
2647}
2648
9a64fbe4
FB		 2649static int register_ind_insn (opc_handler_t **ppc_opcodes,
2650 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2651 opc_handler_t *handler)
2652{
2653 int ret;
2654
2655 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2656
2657 return ret;
2658}
2659
9a64fbe4
FB		 2660static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2661 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2662 unsigned char idx3, opc_handler_t *handler)
2663{
2664 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9a64fbe4 2665 printf("*** ERROR: unable to join indirect table idx "
79aceca5
FB		 2666 "[%02x-%02x]\n", idx1, idx2);
2667 return -1;
2668 }
2669 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2670 handler) < 0) {
9a64fbe4 2671 printf("*** ERROR: unable to insert opcode "
79aceca5
FB		 2672 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2673 return -1;
2674 }
2675
2676 return 0;
2677}
2678
9a64fbe4 2679static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
79aceca5
FB		 2680{
2681 if (insn->opc2 != 0xFF) {
2682 if (insn->opc3 != 0xFF) {
9a64fbe4
FB		 2683 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2684 insn->opc3, &insn->handler) < 0)
79aceca5
FB		 2685 return -1;
2686 } else {
9a64fbe4
FB		 2687 if (register_ind_insn(ppc_opcodes, insn->opc1,
2688 insn->opc2, &insn->handler) < 0)
79aceca5
FB		 2689 return -1;
2690 }
2691 } else {
9a64fbe4 2692 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
79aceca5
FB		 2693 return -1;
2694 }
2695
2696 return 0;
2697}
2698
2699static int test_opcode_table (opc_handler_t **table, int len)
2700{
2701 int i, count, tmp;
2702
2703 for (i = 0, count = 0; i < len; i++) {
2704 /* Consistency fixup */
2705 if (table[i] == NULL)
2706 table[i] = &invalid_handler;
2707 if (table[i] != &invalid_handler) {
2708 if (is_indirect_opcode(table[i])) {
2709 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2710 if (tmp == 0) {
2711 free(table[i]);
2712 table[i] = &invalid_handler;
2713 } else {
2714 count++;
2715 }
2716 } else {
2717 count++;
2718 }
2719 }
2720 }
2721
2722 return count;
2723}
2724
9a64fbe4 2725static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
79aceca5
FB		 2726{
2727 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9a64fbe4 2728 printf("*** WARNING: no opcode defined !\n");
79aceca5
FB		 2729}
2730
9a64fbe4 2731#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
79aceca5
FB		 2732#define SPR_UR SPR_RIGHTS(0, 0)
2733#define SPR_UW SPR_RIGHTS(1, 0)
2734#define SPR_SR SPR_RIGHTS(0, 1)
2735#define SPR_SW SPR_RIGHTS(1, 1)
2736
2737#define spr_set_rights(spr, rights) \
2738do { \
2739 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2740} while (0)
2741
9a64fbe4 2742static void init_spr_rights (uint32_t pvr)
79aceca5
FB		 2743{
2744 /* XER (SPR 1) */
9a64fbe4 2745 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2746 /* LR (SPR 8) */
9a64fbe4 2747 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2748 /* CTR (SPR 9) */
9a64fbe4 2749 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2750 /* TBL (SPR 268) */
9a64fbe4 2751 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
79aceca5 2752 /* TBU (SPR 269) */
9a64fbe4 2753 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
79aceca5 2754 /* DSISR (SPR 18) */
9a64fbe4 2755 spr_set_rights(DSISR, SPR_SR | SPR_SW);
79aceca5 2756 /* DAR (SPR 19) */
9a64fbe4 2757 spr_set_rights(DAR, SPR_SR | SPR_SW);
79aceca5 2758 /* DEC (SPR 22) */
9a64fbe4 2759 spr_set_rights(DECR, SPR_SR | SPR_SW);
79aceca5 2760 /* SDR1 (SPR 25) */
9a64fbe4
FB		 2761 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2762 /* SRR0 (SPR 26) */
2763 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2764 /* SRR1 (SPR 27) */
2765 spr_set_rights(SRR1, SPR_SR | SPR_SW);
79aceca5 2766 /* SPRG0 (SPR 272) */
9a64fbe4 2767 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
79aceca5 2768 /* SPRG1 (SPR 273) */
9a64fbe4 2769 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
79aceca5 2770 /* SPRG2 (SPR 274) */
9a64fbe4 2771 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
79aceca5 2772 /* SPRG3 (SPR 275) */
9a64fbe4 2773 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
79aceca5 2774 /* ASR (SPR 280) */
9a64fbe4 2775 spr_set_rights(ASR, SPR_SR | SPR_SW);
79aceca5 2776 /* EAR (SPR 282) */
9a64fbe4
FB		 2777 spr_set_rights(EAR, SPR_SR | SPR_SW);
2778 /* TBL (SPR 284) */
2779 spr_set_rights(O_TBL, SPR_SW);
2780 /* TBU (SPR 285) */
2781 spr_set_rights(O_TBU, SPR_SW);
2782 /* PVR (SPR 287) */
2783 spr_set_rights(PVR, SPR_SR);
79aceca5 2784 /* IBAT0U (SPR 528) */
9a64fbe4 2785 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
79aceca5 2786 /* IBAT0L (SPR 529) */
9a64fbe4 2787 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
79aceca5 2788 /* IBAT1U (SPR 530) */
9a64fbe4 2789 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
79aceca5 2790 /* IBAT1L (SPR 531) */
9a64fbe4 2791 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
79aceca5 2792 /* IBAT2U (SPR 532) */
9a64fbe4 2793 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
79aceca5 2794 /* IBAT2L (SPR 533) */
9a64fbe4 2795 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
79aceca5 2796 /* IBAT3U (SPR 534) */
9a64fbe4 2797 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
79aceca5 2798 /* IBAT3L (SPR 535) */
9a64fbe4 2799 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
79aceca5 2800 /* DBAT0U (SPR 536) */
9a64fbe4 2801 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
79aceca5 2802 /* DBAT0L (SPR 537) */
9a64fbe4 2803 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
79aceca5 2804 /* DBAT1U (SPR 538) */
9a64fbe4 2805 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
79aceca5 2806 /* DBAT1L (SPR 539) */
9a64fbe4 2807 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
79aceca5 2808 /* DBAT2U (SPR 540) */
9a64fbe4 2809 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
79aceca5 2810 /* DBAT2L (SPR 541) */
9a64fbe4 2811 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
79aceca5 2812 /* DBAT3U (SPR 542) */
9a64fbe4 2813 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
79aceca5 2814 /* DBAT3L (SPR 543) */
9a64fbe4 2815 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
79aceca5 2816 /* FPECR (SPR 1022) */
9a64fbe4 2817 spr_set_rights(FPECR, SPR_SR | SPR_SW);
4b3686fa
FB		 2818 /* Special registers for PPC 604 */
2819 if ((pvr & 0xFFFF0000) == 0x00040000) {
2820 /* IABR */
2821 spr_set_rights(IABR , SPR_SR | SPR_SW);
2822 /* DABR (SPR 1013) */
2823 spr_set_rights(DABR, SPR_SR | SPR_SW);
2824 /* HID0 */
2825 spr_set_rights(HID0, SPR_SR | SPR_SW);
2826 /* PIR */
9a64fbe4 2827 spr_set_rights(PIR, SPR_SR | SPR_SW);
4b3686fa
FB		 2828 /* PMC1 */
2829 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2830 /* PMC2 */
2831 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2832 /* MMCR0 */
2833 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2834 /* SIA */
2835 spr_set_rights(SIA, SPR_SR | SPR_SW);
2836 /* SDA */
2837 spr_set_rights(SDA, SPR_SR | SPR_SW);
2838 }
9a64fbe4
FB		 2839 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2840 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2841 (pvr & 0xFFFF0000) == 0x70000000) {
2842 /* HID0 */
4b3686fa 2843 spr_set_rights(HID0, SPR_SR | SPR_SW);
9a64fbe4 2844 /* HID1 */
4b3686fa 2845 spr_set_rights(HID1, SPR_SR | SPR_SW);
9a64fbe4 2846 /* IABR */
4b3686fa 2847 spr_set_rights(IABR, SPR_SR | SPR_SW);
9a64fbe4 2848 /* ICTC */
4b3686fa 2849 spr_set_rights(ICTC, SPR_SR | SPR_SW);
9a64fbe4 2850 /* L2CR */
4b3686fa 2851 spr_set_rights(L2CR, SPR_SR | SPR_SW);
9a64fbe4 2852 /* MMCR0 */
4b3686fa 2853 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
9a64fbe4 2854 /* MMCR1 */
4b3686fa 2855 spr_set_rights(MMCR1, SPR_SR | SPR_SW);
9a64fbe4 2856 /* PMC1 */
4b3686fa 2857 spr_set_rights(PMC1, SPR_SR | SPR_SW);
9a64fbe4 2858 /* PMC2 */
4b3686fa 2859 spr_set_rights(PMC2, SPR_SR | SPR_SW);
9a64fbe4 2860 /* PMC3 */
4b3686fa 2861 spr_set_rights(PMC3, SPR_SR | SPR_SW);
9a64fbe4 2862 /* PMC4 */
4b3686fa 2863 spr_set_rights(PMC4, SPR_SR | SPR_SW);
9a64fbe4 2864 /* SIA */
4b3686fa
FB		 2865 spr_set_rights(SIA, SPR_SR | SPR_SW);
2866 /* SDA */
2867 spr_set_rights(SDA, SPR_SR | SPR_SW);
9a64fbe4 2868 /* THRM1 */
4b3686fa 2869 spr_set_rights(THRM1, SPR_SR | SPR_SW);
9a64fbe4 2870 /* THRM2 */
4b3686fa 2871 spr_set_rights(THRM2, SPR_SR | SPR_SW);
9a64fbe4 2872 /* THRM3 */
4b3686fa 2873 spr_set_rights(THRM3, SPR_SR | SPR_SW);
9a64fbe4 2874 /* UMMCR0 */
4b3686fa 2875 spr_set_rights(UMMCR0, SPR_UR | SPR_UW);
9a64fbe4 2876 /* UMMCR1 */
4b3686fa 2877 spr_set_rights(UMMCR1, SPR_UR | SPR_UW);
9a64fbe4 2878 /* UPMC1 */
4b3686fa 2879 spr_set_rights(UPMC1, SPR_UR | SPR_UW);
9a64fbe4 2880 /* UPMC2 */
4b3686fa 2881 spr_set_rights(UPMC2, SPR_UR | SPR_UW);
9a64fbe4 2882 /* UPMC3 */
4b3686fa 2883 spr_set_rights(UPMC3, SPR_UR | SPR_UW);
9a64fbe4 2884 /* UPMC4 */
4b3686fa 2885 spr_set_rights(UPMC4, SPR_UR | SPR_UW);
9a64fbe4 2886 /* USIA */
4b3686fa 2887 spr_set_rights(USIA, SPR_UR | SPR_UW);
9a64fbe4
FB		 2888 }
2889 /* MPC755 has special registers */
2890 if (pvr == 0x00083100) {
2891 /* SPRG4 */
2892 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2893 /* SPRG5 */
2894 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2895 /* SPRG6 */
2896 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2897 /* SPRG7 */
2898 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2899 /* IBAT4U */
2900 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2901 /* IBAT4L */
2902 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2903 /* IBAT5U */
2904 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2905 /* IBAT5L */
2906 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2907 /* IBAT6U */
2908 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2909 /* IBAT6L */
2910 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2911 /* IBAT7U */
2912 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2913 /* IBAT7L */
2914 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2915 /* DBAT4U */
2916 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2917 /* DBAT4L */
2918 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2919 /* DBAT5U */
2920 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2921 /* DBAT5L */
2922 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2923 /* DBAT6U */
2924 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2925 /* DBAT6L */
2926 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2927 /* DBAT7U */
2928 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2929 /* DBAT7L */
2930 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2931 /* DMISS */
4b3686fa 2932 spr_set_rights(DMISS, SPR_SR | SPR_SW);
9a64fbe4 2933 /* DCMP */
4b3686fa 2934 spr_set_rights(DCMP, SPR_SR | SPR_SW);
9a64fbe4 2935 /* DHASH1 */
4b3686fa 2936 spr_set_rights(DHASH1, SPR_SR | SPR_SW);
9a64fbe4 2937 /* DHASH2 */
4b3686fa 2938 spr_set_rights(DHASH2, SPR_SR | SPR_SW);
9a64fbe4 2939 /* IMISS */
4b3686fa 2940 spr_set_rights(IMISS, SPR_SR | SPR_SW);
9a64fbe4 2941 /* ICMP */
4b3686fa 2942 spr_set_rights(ICMP, SPR_SR | SPR_SW);
9a64fbe4 2943 /* RPA */
4b3686fa 2944 spr_set_rights(RPA, SPR_SR | SPR_SW);
9a64fbe4 2945 /* HID2 */
4b3686fa 2946 spr_set_rights(HID2, SPR_SR | SPR_SW);
9a64fbe4 2947 /* L2PM */
4b3686fa 2948 spr_set_rights(L2PM, SPR_SR | SPR_SW);
9a64fbe4 2949 }
79aceca5
FB		 2950}
2951
9a64fbe4
FB		 2952/*****************************************************************************/
2953/* PPC "main stream" common instructions (no optional ones) */
79aceca5
FB		 2954
2955typedef struct ppc_proc_t {
2956 int flags;
2957 void *specific;
2958} ppc_proc_t;
2959
2960typedef struct ppc_def_t {
2961 unsigned long pvr;
2962 unsigned long pvr_mask;
2963 ppc_proc_t *proc;
2964} ppc_def_t;
2965
2966static ppc_proc_t ppc_proc_common = {
2967 .flags = PPC_COMMON,
2968 .specific = NULL,
2969};
2970
9a64fbe4
FB		 2971static ppc_proc_t ppc_proc_G3 = {
2972 .flags = PPC_750,
2973 .specific = NULL,
2974};
2975
79aceca5
FB		 2976static ppc_def_t ppc_defs[] =
2977{
9a64fbe4
FB		 2978 /* MPC740/745/750/755 (G3) */
2979 {
2980 .pvr = 0x00080000,
2981 .pvr_mask = 0xFFFF0000,
2982 .proc = &ppc_proc_G3,
2983 },
2984 /* IBM 750FX (G3 embedded) */
2985 {
2986 .pvr = 0x70000000,
2987 .pvr_mask = 0xFFFF0000,
2988 .proc = &ppc_proc_G3,
2989 },
2990 /* Fallback (generic PPC) */
79aceca5
FB		 2991 {
2992 .pvr = 0x00000000,
2993 .pvr_mask = 0x00000000,
2994 .proc = &ppc_proc_common,
2995 },
2996};
2997
9a64fbe4 2998static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
79aceca5 2999{
18fba28c 3000 opcode_t *opc, *start, *end;
79aceca5
FB		 3001 int i, flags;
3002
3003 fill_new_table(ppc_opcodes, 0x40);
3004 for (i = 0; ; i++) {
3005 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
3006 (pvr & ppc_defs[i].pvr_mask)) {
3007 flags = ppc_defs[i].proc->flags;
3008 break;
3009 }
3010 }
3011
18fba28c
FB		 3012 if (&opc_start < &opc_end) {
3013 start = &opc_start;
3014 end = &opc_end;
3015 } else {
3016 start = &opc_end;
3017 end = &opc_start;
3018 }
3019 for (opc = start + 1; opc != end; opc++) {
9a64fbe4
FB		 3020 if ((opc->handler.type & flags) != 0)
3021 if (register_insn(ppc_opcodes, opc) < 0) {
3022 printf("*** ERROR initializing PPC instruction "
79aceca5
FB		 3023 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
3024 opc->opc3);
3025 return -1;
3026 }
3027 }
9a64fbe4 3028 fix_opcode_tables(ppc_opcodes);
79aceca5
FB		 3029
3030 return 0;
3031}
3032
9a64fbe4 3033
79aceca5 3034/*****************************************************************************/
9a64fbe4 3035/* Misc PPC helpers */
79aceca5 3036
7fe48483
FB		 3037void cpu_dump_state(CPUState *env, FILE *f,
3038 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3039 int flags)
79aceca5
FB		 3040{
3041 int i;
3042
7fe48483 3043 cpu_fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
9a64fbe4 3044 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
a541f297 3045 _load_xer(env), _load_msr(env));
79aceca5
FB		 3046 for (i = 0; i < 32; i++) {
3047 if ((i & 7) == 0)
7fe48483
FB		 3048 cpu_fprintf(f, "GPR%02d:", i);
3049 cpu_fprintf(f, " %08x", env->gpr[i]);
79aceca5 3050 if ((i & 7) == 7)
7fe48483 3051 cpu_fprintf(f, "\n");
79aceca5 3052 }
7fe48483 3053 cpu_fprintf(f, "CR: 0x");
79aceca5 3054 for (i = 0; i < 8; i++)
7fe48483
FB		 3055 cpu_fprintf(f, "%01x", env->crf[i]);
3056 cpu_fprintf(f, " [");
79aceca5
FB		 3057 for (i = 0; i < 8; i++) {
3058 char a = '-';
79aceca5
FB		 3059 if (env->crf[i] & 0x08)
3060 a = 'L';
3061 else if (env->crf[i] & 0x04)
3062 a = 'G';
3063 else if (env->crf[i] & 0x02)
3064 a = 'E';
7fe48483 3065 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
79aceca5 3066 }
7fe48483
FB		 3067 cpu_fprintf(f, " ] ");
3068 cpu_fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
9fddaa0c 3069 cpu_ppc_load_tbl(env));
79aceca5
FB		 3070 for (i = 0; i < 16; i++) {
3071 if ((i & 3) == 0)
7fe48483
FB		 3072 cpu_fprintf(f, "FPR%02d:", i);
3073 cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
79aceca5 3074 if ((i & 3) == 3)
7fe48483 3075 cpu_fprintf(f, "\n");
79aceca5 3076 }
7fe48483 3077 cpu_fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
9fddaa0c 3078 env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env));
7fe48483 3079 cpu_fprintf(f, "reservation 0x%08x\n", env->reserve);
79aceca5
FB		 3080}
3081
3082CPUPPCState *cpu_ppc_init(void)
3083{
3084 CPUPPCState *env;
3085
3086 cpu_exec_init();
3087
4b3686fa 3088 env = qemu_mallocz(sizeof(CPUPPCState));
79aceca5
FB		 3089 if (!env)
3090 return NULL;
9a64fbe4
FB		 3091// env->spr[PVR] = 0; /* Basic PPC */
3092 env->spr[PVR] = 0x00080100; /* G3 CPU */
3093// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
3094// env->spr[PVR] = 0x00070100; /* IBM 750FX */
ad081323 3095 tlb_flush(env, 1);
9a64fbe4
FB		 3096#if defined (DO_SINGLE_STEP)
3097 /* Single step trace mode */
3098 msr_se = 1;
3099#endif
4b3686fa
FB		 3100 msr_fp = 1; /* Allow floating point exceptions */
3101 msr_me = 1; /* Allow machine check exceptions */
9a64fbe4
FB		 3102#if defined(CONFIG_USER_ONLY)
3103 msr_pr = 1;
4b3686fa
FB		 3104 cpu_ppc_register(env, 0x00080000);
3105#else
3106 env->nip = 0xFFFFFFFC;
9a64fbe4 3107#endif
7496f526 3108 cpu_single_env = env;
79aceca5
FB		 3109 return env;
3110}
3111
4b3686fa
FB		 3112int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
3113{
3114 env->spr[PVR] = pvr;
3115 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
3116 return -1;
3117 init_spr_rights(env->spr[PVR]);
3118
3119 return 0;
3120}
3121
79aceca5
FB		 3122void cpu_ppc_close(CPUPPCState *env)
3123{
3124 /* Should also remove all opcode tables... */
3125 free(env);
3126}
3127
9a64fbe4 3128/*****************************************************************************/
79aceca5
FB		 3129int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3130 int search_pc)
3131{
9fddaa0c 3132 DisasContext ctx, *ctxp = &ctx;
79aceca5 3133 opc_handler_t **table, *handler;
0fa85d43 3134 target_ulong pc_start;
79aceca5
FB		 3135 uint16_t *gen_opc_end;
3136 int j, lj = -1;
79aceca5
FB		 3137
3138 pc_start = tb->pc;
3139 gen_opc_ptr = gen_opc_buf;
3140 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3141 gen_opparam_ptr = gen_opparam_buf;
046d6672 3142 ctx.nip = pc_start;
79aceca5 3143 ctx.tb = tb;
9a64fbe4
FB		 3144 ctx.exception = EXCP_NONE;
3145#if defined(CONFIG_USER_ONLY)
3146 ctx.mem_idx = 0;
3147#else
3148 ctx.supervisor = 1 - msr_pr;
3cc62370 3149 ctx.mem_idx = 1 - msr_pr;
9a64fbe4 3150#endif
3cc62370 3151 ctx.fpu_enabled = msr_fp;
9a64fbe4
FB		 3152#if defined (DO_SINGLE_STEP)
3153 /* Single step trace mode */
3154 msr_se = 1;
3155#endif
3156 /* Set env in case of segfault during code fetch */
3157 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
79aceca5 3158 if (search_pc) {
79aceca5
FB		 3159 j = gen_opc_ptr - gen_opc_buf;
3160 if (lj < j) {
3161 lj++;
3162 while (lj < j)
3163 gen_opc_instr_start[lj++] = 0;
046d6672 3164 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 3165 gen_opc_instr_start[lj] = 1;
3166 }
3167 }
9fddaa0c
FB		 3168#if defined PPC_DEBUG_DISAS
3169 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 3170 fprintf(logfile, "----------------\n");
046d6672 3171 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
9a64fbe4
FB		 3172 ctx.nip, 1 - msr_pr, msr_ir);
3173 }
3174#endif
0fa85d43 3175 ctx.opcode = ldl_code(ctx.nip);
9fddaa0c
FB		 3176#if defined PPC_DEBUG_DISAS
3177 if (loglevel & CPU_LOG_TB_IN_ASM) {
9a64fbe4
FB		 3178 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3179 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3180 opc3(ctx.opcode));
79aceca5
FB		 3181 }
3182#endif
046d6672 3183 ctx.nip += 4;
79aceca5
FB		 3184 table = ppc_opcodes;
3185 handler = table[opc1(ctx.opcode)];
3186 if (is_indirect_opcode(handler)) {
3187 table = ind_table(handler);
3188 handler = table[opc2(ctx.opcode)];
3189 if (is_indirect_opcode(handler)) {
3190 table = ind_table(handler);
3191 handler = table[opc3(ctx.opcode)];
3192 }
3193 }
3194 /* Is opcode *REALLY* valid ? */
79aceca5 3195 if (handler->handler == &gen_invalid) {
4b3686fa 3196 if (loglevel > 0) {
79aceca5 3197 fprintf(logfile, "invalid/unsupported opcode: "
4b3686fa 3198 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
9a64fbe4 3199 opc1(ctx.opcode), opc2(ctx.opcode),
4b3686fa
FB		 3200 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3201 } else {
3202 printf("invalid/unsupported opcode: "
3203 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3204 opc1(ctx.opcode), opc2(ctx.opcode),
3205 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3206 }
79aceca5 3207 } else {
4b3686fa
FB		 3208 if ((ctx.opcode & handler->inval) != 0) {
3209 if (loglevel > 0) {
79aceca5 3210 fprintf(logfile, "invalid bits: %08x for opcode: "
046d6672 3211 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
79aceca5
FB		 3212 ctx.opcode & handler->inval, opc1(ctx.opcode),
3213 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3214 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 3215 } else {
3216 printf("invalid bits: %08x for opcode: "
046d6672 3217 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
9a64fbe4
FB		 3218 ctx.opcode & handler->inval, opc1(ctx.opcode),
3219 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3220 ctx.opcode, ctx.nip - 4);
9a64fbe4 3221 }
4b3686fa
FB		 3222 RET_INVAL(ctxp);
3223 break;
79aceca5 3224 }
79aceca5 3225 }
4b3686fa 3226 (*(handler->handler))(&ctx);
9a64fbe4
FB		 3227 /* Check trace mode exceptions */
3228 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3229 /* Check in single step trace mode
3230 * we need to stop except if:
3231 * - rfi, trap or syscall
3232 * - first instruction of an exception handler
3233 */
046d6672
FB		 3234 (msr_se && (ctx.nip < 0x100 ||
3235 ctx.nip > 0xF00 ||
3236 (ctx.nip & 0xFC) != 0x04) &&
9a64fbe4
FB		 3237 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3238 ctx.exception != EXCP_TRAP)) {
9fddaa0c 3239 RET_EXCP(ctxp, EXCP_TRACE, 0);
9a64fbe4 3240 }
a541f297 3241 /* if we reach a page boundary, stop generation */
046d6672 3242 if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
9fddaa0c 3243 RET_EXCP(ctxp, EXCP_BRANCH, 0);
79aceca5 3244 }
9a64fbe4 3245 }
9fddaa0c
FB		 3246 if (ctx.exception == EXCP_NONE) {
3247 gen_op_b((unsigned long)ctx.tb, ctx.nip);
3248 } else if (ctx.exception != EXCP_BRANCH) {
3249 gen_op_set_T0(0);
9a64fbe4
FB		 3250 }
3251#if 1
79aceca5
FB		 3252 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3253 * do bad business and then qemu crashes !
3254 */
3255 gen_op_set_T0(0);
9a64fbe4 3256#endif
79aceca5
FB		 3257 /* Generate the return instruction */
3258 gen_op_exit_tb();
3259 *gen_opc_ptr = INDEX_op_end;
9a64fbe4
FB		 3260 if (search_pc) {
3261 j = gen_opc_ptr - gen_opc_buf;
3262 lj++;
3263 while (lj <= j)
3264 gen_opc_instr_start[lj++] = 0;
79aceca5 3265 tb->size = 0;
985a19d6 3266#if 0
9a64fbe4
FB		 3267 if (loglevel > 0) {
3268 page_dump(logfile);
3269 }
985a19d6 3270#endif
9a64fbe4 3271 } else {
046d6672 3272 tb->size = ctx.nip - pc_start;
9a64fbe4 3273 }
79aceca5 3274#ifdef DEBUG_DISAS
9fddaa0c 3275 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 3276 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 3277 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 3278 }
3279 if (loglevel & CPU_LOG_TB_IN_ASM) {
0fa85d43
FB		 3280 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3281 target_disas(logfile, pc_start, ctx.nip - pc_start, 0);
79aceca5 3282 fprintf(logfile, "\n");
9fddaa0c
FB		 3283 }
3284 if (loglevel & CPU_LOG_TB_OP) {
79aceca5
FB		 3285 fprintf(logfile, "OP:\n");
3286 dump_ops(gen_opc_buf, gen_opparam_buf);
3287 fprintf(logfile, "\n");
3288 }
3289#endif
79aceca5
FB		 3290 return 0;
3291}
3292
9a64fbe4 3293int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3294{
3295 return gen_intermediate_code_internal(env, tb, 0);
3296}
3297
9a64fbe4 3298int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3299{
3300 return gen_intermediate_code_internal(env, tb, 1);
3301}
Qemu copy for testing