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target-ppc: convert load/store with reservation instructions to TCG
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
79aceca5 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
7c58044c 44//#define OPTIMIZE_FPRF_UPDATE
79aceca5 45
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 52#if !defined(TARGET_PPC64)
1d542695 53 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 54#endif
a5e26afa 55 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
f78fb44e
AJ		 58static TCGv cpu_gpr[32];
59#if !defined(TARGET_PPC64)
60static TCGv cpu_gprh[32];
61#endif
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64static TCGv_i32 cpu_crf[8];
bd568f18 65static TCGv cpu_nip;
cfdcd37a
AJ		 66static TCGv cpu_ctr;
67static TCGv cpu_lr;
3d7b417e 68static TCGv cpu_xer;
cf360a32 69static TCGv cpu_reserve;
a7812ae4 70static TCGv_i32 cpu_fpscr;
a7859e89 71static TCGv_i32 cpu_access_type;
f78fb44e
AJ		 72
73/* dyngen register indexes */
74static TCGv cpu_T[3];
2e70f6ef
PB		 75
76#include "gen-icount.h"
77
78void ppc_translate_init(void)
79{
f78fb44e
AJ		 80 int i;
81 char* p;
b2437bf2 82 static int done_init = 0;
f78fb44e 83
2e70f6ef
PB		 84 if (done_init)
85 return;
f78fb44e 86
a7812ae4 87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1c73fe5b 88#if TARGET_LONG_BITS > HOST_LONG_BITS
a7812ae4
PB		 89 cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");
90 cpu_T[1] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t1), "T1");
91 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
1c73fe5b 92#else
a7812ae4
PB		 93 cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");
94 cpu_T[1] = tcg_global_reg_new(TCG_AREG2, "T1");
4870167d
AJ		 95#ifdef HOST_I386
96 /* XXX: This is a temporary workaround for i386.
97 * On i386 qemu_st32 runs out of registers.
98 * The proper fix is to remove cpu_T.
99 */
a7812ae4 100 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
4870167d 101#else
a7812ae4 102 cpu_T[2] = tcg_global_reg_new(TCG_AREG3, "T2");
1c73fe5b 103#endif
a7812ae4
PB		 104#endif
105
f78fb44e 106 p = cpu_reg_names;
47e4661c
AJ		 107
108 for (i = 0; i < 8; i++) {
109 sprintf(p, "crf%d", i);
a7812ae4
PB		 110 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 112 p += 5;
113 }
114
f78fb44e
AJ		 115 for (i = 0; i < 32; i++) {
116 sprintf(p, "r%d", i);
a7812ae4 117 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 118 offsetof(CPUState, gpr[i]), p);
119 p += (i < 10) ? 3 : 4;
120#if !defined(TARGET_PPC64)
121 sprintf(p, "r%dH", i);
a7812ae4
PB		 122 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
123 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 124 p += (i < 10) ? 4 : 5;
125#endif
1d542695 126
a5e26afa 127 sprintf(p, "fp%d", i);
a7812ae4
PB		 128 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
129 offsetof(CPUState, fpr[i]), p);
ec1ac72d 130 p += (i < 10) ? 4 : 5;
a5e26afa 131
1d542695 132 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 133#ifdef WORDS_BIGENDIAN
134 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUState, avr[i].u64[0]), p);
136#else
a7812ae4 137 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 138 offsetof(CPUState, avr[i].u64[1]), p);
139#endif
1d542695 140 p += (i < 10) ? 6 : 7;
ec1ac72d 141
1d542695 142 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 143#ifdef WORDS_BIGENDIAN
144 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
145 offsetof(CPUState, avr[i].u64[1]), p);
146#else
a7812ae4 147 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 148 offsetof(CPUState, avr[i].u64[0]), p);
149#endif
1d542695 150 p += (i < 10) ? 6 : 7;
f78fb44e 151 }
f10dc08e 152
a7812ae4 153 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 154 offsetof(CPUState, nip), "nip");
155
a7812ae4 156 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 157 offsetof(CPUState, ctr), "ctr");
158
a7812ae4 159 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 160 offsetof(CPUState, lr), "lr");
161
a7812ae4 162 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 163 offsetof(CPUState, xer), "xer");
164
cf360a32
AJ		 165 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUState, reserve), "reserve");
167
a7812ae4
PB		 168 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
169 offsetof(CPUState, fpscr), "fpscr");
e1571908 170
a7859e89
AJ		 171 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
172 offsetof(CPUState, access_type), "access_type");
173
f10dc08e 174 /* register helpers */
a7812ae4 175#define GEN_HELPER 2
f10dc08e
AJ		 176#include "helper.h"
177
2e70f6ef
PB		 178 done_init = 1;
179}
180
7c58044c
JM		 181#if defined(OPTIMIZE_FPRF_UPDATE)
182static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
183static uint16_t **gen_fprf_ptr;
184#endif
79aceca5 185
79aceca5
FB		 186/* internal defines */
187typedef struct DisasContext {
188 struct TranslationBlock *tb;
0fa85d43 189 target_ulong nip;
79aceca5 190 uint32_t opcode;
9a64fbe4 191 uint32_t exception;
3cc62370
FB		 192 /* Routine used to access memory */
193 int mem_idx;
194 /* Translation flags */
9a64fbe4 195#if !defined(CONFIG_USER_ONLY)
79aceca5 196 int supervisor;
d9bce9d9
JM		 197#endif
198#if defined(TARGET_PPC64)
199 int sf_mode;
9a64fbe4 200#endif
3cc62370 201 int fpu_enabled;
a9d9eb8f 202 int altivec_enabled;
0487d6a8 203 int spe_enabled;
3fc6c082 204 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 205 int singlestep_enabled;
79aceca5
FB		 206} DisasContext;
207
3fc6c082 208struct opc_handler_t {
79aceca5
FB		 209 /* invalid bits */
210 uint32_t inval;
9a64fbe4 211 /* instruction type */
0487d6a8 212 uint64_t type;
79aceca5
FB		 213 /* handler */
214 void (*handler)(DisasContext *ctx);
a750fc0b 215#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 216 const char *oname;
a750fc0b
JM		 217#endif
218#if defined(DO_PPC_STATISTICS)
76a66253
JM		 219 uint64_t count;
220#endif
3fc6c082 221};
79aceca5 222
7c58044c
JM		 223static always_inline void gen_reset_fpstatus (void)
224{
225#ifdef CONFIG_SOFTFLOAT
226 gen_op_reset_fpstatus();
227#endif
228}
229
0f2f39c2 230static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 231{
0f2f39c2 232 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 233
7c58044c
JM		 234 if (set_fprf != 0) {
235 /* This case might be optimized later */
236#if defined(OPTIMIZE_FPRF_UPDATE)
237 *gen_fprf_ptr++ = gen_opc_ptr;
238#endif
0f2f39c2 239 tcg_gen_movi_i32(t0, 1);
af12906f 240 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 241 if (unlikely(set_rc)) {
0f2f39c2 242 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 243 }
af12906f 244 gen_helper_float_check_status();
7c58044c
JM		 245 } else if (unlikely(set_rc)) {
246 /* We always need to compute fpcc */
0f2f39c2 247 tcg_gen_movi_i32(t0, 0);
af12906f 248 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 249 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 250 if (set_fprf)
af12906f 251 gen_helper_float_check_status();
7c58044c 252 }
af12906f 253
0f2f39c2 254 tcg_temp_free_i32(t0);
7c58044c
JM		 255}
256
257static always_inline void gen_optimize_fprf (void)
258{
259#if defined(OPTIMIZE_FPRF_UPDATE)
260 uint16_t **ptr;
261
262 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
263 *ptr = INDEX_op_nop1;
264 gen_fprf_ptr = gen_fprf_buf;
265#endif
266}
267
a7859e89
AJ		 268static always_inline void gen_set_access_type(int access_type)
269{
270 tcg_gen_movi_i32(cpu_access_type, access_type);
271}
272
b068d6a7 273static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 274{
275#if defined(TARGET_PPC64)
276 if (ctx->sf_mode)
bd568f18 277 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 278 else
279#endif
bd568f18 280 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 281}
282
e1833e1f 283#define GEN_EXCP(ctx, excp, error) \
79aceca5 284do { \
64adab3f
AJ		 285 TCGv_i32 t0 = tcg_const_i32(excp); \
286 TCGv_i32 t1 = tcg_const_i32(error); \
e1833e1f 287 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 288 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c 289 } \
64adab3f
AJ		 290 gen_helper_raise_exception_err(t0, t1); \
291 tcg_temp_free_i32(t0); \
292 tcg_temp_free_i32(t1); \
9fddaa0c 293 ctx->exception = (excp); \
79aceca5
FB		 294} while (0)
295
e1833e1f
JM		 296#define GEN_EXCP_INVAL(ctx) \
297GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
298 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 299
e1833e1f
JM		 300#define GEN_EXCP_PRIVOPC(ctx) \
301GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
302 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 303
e1833e1f
JM		 304#define GEN_EXCP_PRIVREG(ctx) \
305GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
306 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
307
308#define GEN_EXCP_NO_FP(ctx) \
309GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
310
311#define GEN_EXCP_NO_AP(ctx) \
312GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 313
a9d9eb8f
JM		 314#define GEN_EXCP_NO_VR(ctx) \
315GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
316
f24e5695 317/* Stop translation */
b068d6a7 318static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 319{
d9bce9d9 320 gen_update_nip(ctx, ctx->nip);
e1833e1f 321 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 322}
323
f24e5695 324/* No need to update nip here, as execution flow will change */
b068d6a7 325static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 326{
e1833e1f 327 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 328}
329
79aceca5
FB		 330#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
331static void gen_##name (DisasContext *ctx); \
332GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
333static void gen_##name (DisasContext *ctx)
334
c7697e1f
JM		 335#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
336static void gen_##name (DisasContext *ctx); \
337GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
338static void gen_##name (DisasContext *ctx)
339
79aceca5
FB		 340typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
1235fc06 342#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 343 unsigned char pad[5];
344#else
345 unsigned char pad[1];
346#endif
79aceca5 347 opc_handler_t handler;
b55266b5 348 const char *oname;
79aceca5
FB		 349} opcode_t;
350
a750fc0b 351/*****************************************************************************/
79aceca5
FB		 352/*** Instruction decoding ***/
353#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 354static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 355{ \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357}
358
359#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 360static always_inline int32_t name (uint32_t opcode) \
79aceca5 361{ \
18fba28c 362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 363}
364
365/* Opcode part 1 */
366EXTRACT_HELPER(opc1, 26, 6);
367/* Opcode part 2 */
368EXTRACT_HELPER(opc2, 1, 5);
369/* Opcode part 3 */
370EXTRACT_HELPER(opc3, 6, 5);
371/* Update Cr0 flags */
372EXTRACT_HELPER(Rc, 0, 1);
373/* Destination */
374EXTRACT_HELPER(rD, 21, 5);
375/* Source */
376EXTRACT_HELPER(rS, 21, 5);
377/* First operand */
378EXTRACT_HELPER(rA, 16, 5);
379/* Second operand */
380EXTRACT_HELPER(rB, 11, 5);
381/* Third operand */
382EXTRACT_HELPER(rC, 6, 5);
383/*** Get CRn ***/
384EXTRACT_HELPER(crfD, 23, 3);
385EXTRACT_HELPER(crfS, 18, 3);
386EXTRACT_HELPER(crbD, 21, 5);
387EXTRACT_HELPER(crbA, 16, 5);
388EXTRACT_HELPER(crbB, 11, 5);
389/* SPR / TBL */
3fc6c082 390EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 391static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 392{
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396}
79aceca5
FB		 397/*** Get constants ***/
398EXTRACT_HELPER(IMM, 12, 8);
399/* 16 bits signed immediate value */
400EXTRACT_SHELPER(SIMM, 0, 16);
401/* 16 bits unsigned immediate value */
402EXTRACT_HELPER(UIMM, 0, 16);
403/* Bit count */
404EXTRACT_HELPER(NB, 11, 5);
405/* Shift count */
406EXTRACT_HELPER(SH, 11, 5);
407/* Mask start */
408EXTRACT_HELPER(MB, 6, 5);
409/* Mask end */
410EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 411/* Trap operand */
412EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 413
414EXTRACT_HELPER(CRM, 12, 8);
415EXTRACT_HELPER(FM, 17, 8);
416EXTRACT_HELPER(SR, 16, 4);
e4bb997e 417EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 418
79aceca5
FB		 419/*** Jump target decoding ***/
420/* Displacement */
421EXTRACT_SHELPER(d, 0, 16);
422/* Immediate address */
b068d6a7 423static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 424{
425 return (opcode >> 0) & 0x03FFFFFC;
426}
427
b068d6a7 428static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 429{
430 return (opcode >> 0) & 0xFFFC;
431}
432
433EXTRACT_HELPER(BO, 21, 5);
434EXTRACT_HELPER(BI, 16, 5);
435/* Absolute/relative address */
436EXTRACT_HELPER(AA, 1, 1);
437/* Link */
438EXTRACT_HELPER(LK, 0, 1);
439
440/* Create a mask between <start> and <end> bits */
b068d6a7 441static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 442{
76a66253 443 target_ulong ret;
79aceca5 444
76a66253
JM		 445#if defined(TARGET_PPC64)
446 if (likely(start == 0)) {
6f2d8978 447 ret = UINT64_MAX << (63 - end);
76a66253 448 } else if (likely(end == 63)) {
6f2d8978 449 ret = UINT64_MAX >> start;
76a66253
JM		 450 }
451#else
452 if (likely(start == 0)) {
6f2d8978 453 ret = UINT32_MAX << (31 - end);
76a66253 454 } else if (likely(end == 31)) {
6f2d8978 455 ret = UINT32_MAX >> start;
76a66253
JM		 456 }
457#endif
458 else {
459 ret = (((target_ulong)(-1ULL)) >> (start)) ^
460 (((target_ulong)(-1ULL) >> (end)) >> 1);
461 if (unlikely(start > end))
462 return ~ret;
463 }
79aceca5
FB		 464
465 return ret;
466}
467
a750fc0b
JM		 468/*****************************************************************************/
469/* PowerPC Instructions types definitions */
470enum {
1b413d55 471 PPC_NONE = 0x0000000000000000ULL,
12de9a39 472 /* PowerPC base instructions set */
1b413d55
JM		 473 PPC_INSNS_BASE = 0x0000000000000001ULL,
474 /* integer operations instructions */
a750fc0b 475#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 476 /* flow control instructions */
a750fc0b 477#define PPC_FLOW PPC_INSNS_BASE
1b413d55 478 /* virtual memory instructions */
a750fc0b 479#define PPC_MEM PPC_INSNS_BASE
1b413d55 480 /* ld/st with reservation instructions */
a750fc0b 481#define PPC_RES PPC_INSNS_BASE
1b413d55 482 /* spr/msr access instructions */
a750fc0b 483#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 484 /* Deprecated instruction sets */
485 /* Original POWER instruction set */
f610349f 486 PPC_POWER = 0x0000000000000002ULL,
1b413d55 487 /* POWER2 instruction set extension */
f610349f 488 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 489 /* Power RTC support */
f610349f 490 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 491 /* Power-to-PowerPC bridge (601) */
f610349f 492 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 493 /* 64 bits PowerPC instruction set */
f610349f 494 PPC_64B = 0x0000000000000020ULL,
1b413d55 495 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 496 PPC_64BX = 0x0000000000000040ULL,
1b413d55 497 /* 64 bits hypervisor extensions */
f610349f 498 PPC_64H = 0x0000000000000080ULL,
1b413d55 499 /* New wait instruction (PowerPC 2.0x) */
f610349f 500 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 501 /* Time base mftb instruction */
f610349f 502 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 503
504 /* Fixed-point unit extensions */
505 /* PowerPC 602 specific */
f610349f 506 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 507 /* isel instruction */
508 PPC_ISEL = 0x0000000000000800ULL,
509 /* popcntb instruction */
510 PPC_POPCNTB = 0x0000000000001000ULL,
511 /* string load / store */
512 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 513
514 /* Floating-point unit extensions */
515 /* Optional floating point instructions */
516 PPC_FLOAT = 0x0000000000010000ULL,
517 /* New floating-point extensions (PowerPC 2.0x) */
518 PPC_FLOAT_EXT = 0x0000000000020000ULL,
519 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
520 PPC_FLOAT_FRES = 0x0000000000080000ULL,
521 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
522 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
523 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
524 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
525
526 /* Vector/SIMD extensions */
527 /* Altivec support */
528 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 529 /* PowerPC 2.03 SPE extension */
05332d70 530 PPC_SPE = 0x0000000002000000ULL,
1b413d55 531 /* PowerPC 2.03 SPE floating-point extension */
05332d70 532 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 533
12de9a39 534 /* Optional memory control instructions */
1b413d55
JM		 535 PPC_MEM_TLBIA = 0x0000000010000000ULL,
536 PPC_MEM_TLBIE = 0x0000000020000000ULL,
537 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
538 /* sync instruction */
539 PPC_MEM_SYNC = 0x0000000080000000ULL,
540 /* eieio instruction */
541 PPC_MEM_EIEIO = 0x0000000100000000ULL,
542
543 /* Cache control instructions */
c8623f2e 544 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 545 /* icbi instruction */
05332d70 546 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 547 /* dcbz instruction with fixed cache line size */
05332d70 548 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 549 /* dcbz instruction with tunable cache line size */
05332d70 550 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 551 /* dcba instruction */
05332d70
JM		 552 PPC_CACHE_DCBA = 0x0000002000000000ULL,
553 /* Freescale cache locking instructions */
554 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 555
556 /* MMU related extensions */
557 /* external control instructions */
05332d70 558 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 559 /* segment register access instructions */
05332d70 560 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 561 /* PowerPC 6xx TLB management instructions */
05332d70 562 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 563 /* PowerPC 74xx TLB management instructions */
05332d70 564 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 565 /* PowerPC 40x TLB management instructions */
05332d70 566 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 567 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 568 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 569 /* SLB management */
05332d70 570 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 571
12de9a39 572 /* Embedded PowerPC dedicated instructions */
05332d70 573 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 574 /* PowerPC 40x exception model */
05332d70 575 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 576 /* PowerPC 405 Mac instructions */
05332d70 577 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 578 /* PowerPC 440 specific instructions */
05332d70 579 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 580 /* BookE (embedded) PowerPC specification */
05332d70
JM		 581 PPC_BOOKE = 0x0010000000000000ULL,
582 /* mfapidi instruction */
583 PPC_MFAPIDI = 0x0020000000000000ULL,
584 /* tlbiva instruction */
585 PPC_TLBIVA = 0x0040000000000000ULL,
586 /* tlbivax instruction */
587 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 588 /* PowerPC 4xx dedicated instructions */
05332d70 589 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 590 /* PowerPC 40x ibct instructions */
05332d70 591 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 592 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 593 PPC_RFMCI = 0x0400000000000000ULL,
594 /* rfdi instruction */
595 PPC_RFDI = 0x0800000000000000ULL,
596 /* DCR accesses */
597 PPC_DCR = 0x1000000000000000ULL,
598 /* DCR extended accesse */
599 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 600 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 601 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 602};
603
604/*****************************************************************************/
605/* PowerPC instructions table */
3fc6c082
FB		 606#if HOST_LONG_BITS == 64
607#define OPC_ALIGN 8
608#else
609#define OPC_ALIGN 4
610#endif
1b039c09 611#if defined(__APPLE__)
d9bce9d9 612#define OPCODES_SECTION \
3fc6c082 613 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 614#else
d9bce9d9 615#define OPCODES_SECTION \
3fc6c082 616 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 617#endif
618
76a66253 619#if defined(DO_PPC_STATISTICS)
79aceca5 620#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 621OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 622 .opc1 = op1, \
623 .opc2 = op2, \
624 .opc3 = op3, \
18fba28c 625 .pad = { 0, }, \
79aceca5
FB		 626 .handler = { \
627 .inval = invl, \
9a64fbe4 628 .type = _typ, \
79aceca5 629 .handler = &gen_##name, \
76a66253 630 .oname = stringify(name), \
79aceca5 631 }, \
3fc6c082 632 .oname = stringify(name), \
79aceca5 633}
c7697e1f
JM		 634#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
635OPCODES_SECTION opcode_t opc_##name = { \
636 .opc1 = op1, \
637 .opc2 = op2, \
638 .opc3 = op3, \
639 .pad = { 0, }, \
640 .handler = { \
641 .inval = invl, \
642 .type = _typ, \
643 .handler = &gen_##name, \
644 .oname = onam, \
645 }, \
646 .oname = onam, \
647}
76a66253
JM		 648#else
649#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
650OPCODES_SECTION opcode_t opc_##name = { \
651 .opc1 = op1, \
652 .opc2 = op2, \
653 .opc3 = op3, \
654 .pad = { 0, }, \
655 .handler = { \
656 .inval = invl, \
657 .type = _typ, \
658 .handler = &gen_##name, \
659 }, \
660 .oname = stringify(name), \
661}
c7697e1f
JM		 662#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
663OPCODES_SECTION opcode_t opc_##name = { \
664 .opc1 = op1, \
665 .opc2 = op2, \
666 .opc3 = op3, \
667 .pad = { 0, }, \
668 .handler = { \
669 .inval = invl, \
670 .type = _typ, \
671 .handler = &gen_##name, \
672 }, \
673 .oname = onam, \
674}
76a66253 675#endif
79aceca5
FB		 676
677#define GEN_OPCODE_MARK(name) \
18fba28c 678OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 679 .opc1 = 0xFF, \
680 .opc2 = 0xFF, \
681 .opc3 = 0xFF, \
18fba28c 682 .pad = { 0, }, \
79aceca5
FB		 683 .handler = { \
684 .inval = 0x00000000, \
9a64fbe4 685 .type = 0x00, \
79aceca5
FB		 686 .handler = NULL, \
687 }, \
3fc6c082 688 .oname = stringify(name), \
79aceca5
FB		 689}
690
691/* Start opcode list */
692GEN_OPCODE_MARK(start);
693
694/* Invalid instruction */
9a64fbe4
FB		 695GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
696{
e1833e1f 697 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 698}
699
79aceca5
FB		 700static opc_handler_t invalid_handler = {
701 .inval = 0xFFFFFFFF,
9a64fbe4 702 .type = PPC_NONE,
79aceca5
FB		 703 .handler = gen_invalid,
704};
705
e1571908
AJ		 706/*** Integer comparison ***/
707
ea363694 708static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 709{
710 int l1, l2, l3;
711
269f3e95
AJ		 712 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
713 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 714 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
715
716 l1 = gen_new_label();
717 l2 = gen_new_label();
718 l3 = gen_new_label();
719 if (s) {
ea363694
AJ		 720 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
721 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 722 } else {
ea363694
AJ		 723 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
724 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 725 }
726 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
727 tcg_gen_br(l3);
728 gen_set_label(l1);
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
730 tcg_gen_br(l3);
731 gen_set_label(l2);
732 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
733 gen_set_label(l3);
734}
735
ea363694 736static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 737{
ea363694
AJ		 738 TCGv t0 = tcg_const_local_tl(arg1);
739 gen_op_cmp(arg0, t0, s, crf);
740 tcg_temp_free(t0);
e1571908
AJ		 741}
742
743#if defined(TARGET_PPC64)
ea363694 744static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 745{
ea363694 746 TCGv t0, t1;
a7812ae4
PB		 747 t0 = tcg_temp_local_new();
748 t1 = tcg_temp_local_new();
e1571908 749 if (s) {
ea363694
AJ		 750 tcg_gen_ext32s_tl(t0, arg0);
751 tcg_gen_ext32s_tl(t1, arg1);
e1571908 752 } else {
ea363694
AJ		 753 tcg_gen_ext32u_tl(t0, arg0);
754 tcg_gen_ext32u_tl(t1, arg1);
e1571908 755 }
ea363694
AJ		 756 gen_op_cmp(t0, t1, s, crf);
757 tcg_temp_free(t1);
758 tcg_temp_free(t0);
e1571908
AJ		 759}
760
ea363694 761static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 762{
ea363694
AJ		 763 TCGv t0 = tcg_const_local_tl(arg1);
764 gen_op_cmp32(arg0, t0, s, crf);
765 tcg_temp_free(t0);
e1571908
AJ		 766}
767#endif
768
769static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
770{
771#if defined(TARGET_PPC64)
772 if (!(ctx->sf_mode))
773 gen_op_cmpi32(reg, 0, 1, 0);
774 else
775#endif
776 gen_op_cmpi(reg, 0, 1, 0);
777}
778
779/* cmp */
780GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
781{
782#if defined(TARGET_PPC64)
783 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
784 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
785 1, crfD(ctx->opcode));
786 else
787#endif
788 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
789 1, crfD(ctx->opcode));
790}
791
792/* cmpi */
793GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
794{
795#if defined(TARGET_PPC64)
796 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
797 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
798 1, crfD(ctx->opcode));
799 else
800#endif
801 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
802 1, crfD(ctx->opcode));
803}
804
805/* cmpl */
806GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
807{
808#if defined(TARGET_PPC64)
809 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
810 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
811 0, crfD(ctx->opcode));
812 else
813#endif
814 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
815 0, crfD(ctx->opcode));
816}
817
818/* cmpli */
819GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
820{
821#if defined(TARGET_PPC64)
822 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
823 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
824 0, crfD(ctx->opcode));
825 else
826#endif
827 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
828 0, crfD(ctx->opcode));
829}
830
831/* isel (PowerPC 2.03 specification) */
832GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
833{
834 int l1, l2;
835 uint32_t bi = rC(ctx->opcode);
836 uint32_t mask;
a7812ae4 837 TCGv_i32 t0;
e1571908
AJ		 838
839 l1 = gen_new_label();
840 l2 = gen_new_label();
841
842 mask = 1 << (3 - (bi & 0x03));
a7812ae4 843 t0 = tcg_temp_new_i32();
fea0c503
AJ		 844 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
845 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 846 if (rA(ctx->opcode) == 0)
847 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
848 else
849 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
850 tcg_gen_br(l2);
851 gen_set_label(l1);
852 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
853 gen_set_label(l2);
a7812ae4 854 tcg_temp_free_i32(t0);
e1571908
AJ		 855}
856
79aceca5 857/*** Integer arithmetic ***/
79aceca5 858
74637406
AJ		 859static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
860{
861 int l1;
862 TCGv t0;
79aceca5 863
74637406
AJ		 864 l1 = gen_new_label();
865 /* Start with XER OV disabled, the most likely case */
866 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 867 t0 = tcg_temp_local_new();
74637406
AJ		 868 tcg_gen_xor_tl(t0, arg0, arg1);
869#if defined(TARGET_PPC64)
870 if (!ctx->sf_mode)
871 tcg_gen_ext32s_tl(t0, t0);
872#endif
873 if (sub)
874 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
875 else
876 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
877 tcg_gen_xor_tl(t0, arg1, arg2);
878#if defined(TARGET_PPC64)
879 if (!ctx->sf_mode)
880 tcg_gen_ext32s_tl(t0, t0);
881#endif
882 if (sub)
883 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
884 else
885 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
886 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
887 gen_set_label(l1);
888 tcg_temp_free(t0);
79aceca5
FB		 889}
890
74637406
AJ		 891static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
892{
893 int l1 = gen_new_label();
d9bce9d9
JM		 894
895#if defined(TARGET_PPC64)
74637406
AJ		 896 if (!(ctx->sf_mode)) {
897 TCGv t0, t1;
a7812ae4
PB		 898 t0 = tcg_temp_new();
899 t1 = tcg_temp_new();
d9bce9d9 900
74637406
AJ		 901 tcg_gen_ext32u_tl(t0, arg1);
902 tcg_gen_ext32u_tl(t1, arg2);
903 if (sub) {
904 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 905 } else {
74637406
AJ		 906 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
907 }
a9730017
AJ		 908 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
909 gen_set_label(l1);
910 tcg_temp_free(t0);
911 tcg_temp_free(t1);
74637406
AJ		 912 } else
913#endif
a9730017
AJ		 914 {
915 if (sub) {
916 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
917 } else {
918 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
919 }
920 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
921 gen_set_label(l1);
74637406 922 }
d9bce9d9
JM		 923}
924
74637406
AJ		 925/* Common add function */
926static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
927 int add_ca, int compute_ca, int compute_ov)
928{
929 TCGv t0, t1;
d9bce9d9 930
74637406 931 if ((!compute_ca && !compute_ov) ||
a7812ae4 932 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 933 t0 = ret;
934 } else {
a7812ae4 935 t0 = tcg_temp_local_new();
74637406 936 }
79aceca5 937
74637406 938 if (add_ca) {
a7812ae4 939 t1 = tcg_temp_local_new();
74637406
AJ		 940 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
941 tcg_gen_shri_tl(t1, t1, XER_CA);
942 }
79aceca5 943
74637406
AJ		 944 if (compute_ca && compute_ov) {
945 /* Start with XER CA and OV disabled, the most likely case */
946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
947 } else if (compute_ca) {
948 /* Start with XER CA disabled, the most likely case */
949 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
950 } else if (compute_ov) {
951 /* Start with XER OV disabled, the most likely case */
952 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
953 }
79aceca5 954
74637406
AJ		 955 tcg_gen_add_tl(t0, arg1, arg2);
956
957 if (compute_ca) {
958 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
959 }
960 if (add_ca) {
961 tcg_gen_add_tl(t0, t0, t1);
962 gen_op_arith_compute_ca(ctx, t0, t1, 0);
963 tcg_temp_free(t1);
964 }
965 if (compute_ov) {
966 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
967 }
968
969 if (unlikely(Rc(ctx->opcode) != 0))
970 gen_set_Rc0(ctx, t0);
971
a7812ae4 972 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 973 tcg_gen_mov_tl(ret, t0);
974 tcg_temp_free(t0);
975 }
39dd32ee 976}
74637406
AJ		 977/* Add functions with two operands */
978#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
979GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
980{ \
981 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
982 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
983 add_ca, compute_ca, compute_ov); \
984}
985/* Add functions with one operand and one immediate */
986#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
987 add_ca, compute_ca, compute_ov) \
988GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
989{ \
990 TCGv t0 = tcg_const_local_tl(const_val); \
991 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
992 cpu_gpr[rA(ctx->opcode)], t0, \
993 add_ca, compute_ca, compute_ov); \
994 tcg_temp_free(t0); \
995}
996
997/* add add. addo addo. */
998GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
999GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1000/* addc addc. addco addco. */
1001GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1002GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1003/* adde adde. addeo addeo. */
1004GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1005GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1006/* addme addme. addmeo addmeo. */
1007GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1008GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1009/* addze addze. addzeo addzeo.*/
1010GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1011GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1012/* addi */
1013GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1014{
74637406
AJ		 1015 target_long simm = SIMM(ctx->opcode);
1016
1017 if (rA(ctx->opcode) == 0) {
1018 /* li case */
1019 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1020 } else {
1021 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1022 }
d9bce9d9 1023}
74637406
AJ		 1024/* addic addic.*/
1025static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1026 int compute_Rc0)
d9bce9d9 1027{
74637406
AJ		 1028 target_long simm = SIMM(ctx->opcode);
1029
1030 /* Start with XER CA and OV disabled, the most likely case */
1031 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1032
1033 if (likely(simm != 0)) {
a7812ae4 1034 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1035 tcg_gen_addi_tl(t0, arg1, simm);
1036 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1037 tcg_gen_mov_tl(ret, t0);
1038 tcg_temp_free(t0);
1039 } else {
1040 tcg_gen_mov_tl(ret, arg1);
1041 }
1042 if (compute_Rc0) {
1043 gen_set_Rc0(ctx, ret);
1044 }
d9bce9d9 1045}
74637406 1046GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1047{
74637406 1048 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1049}
74637406 1050GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1051{
74637406 1052 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1053}
74637406
AJ		 1054/* addis */
1055GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1056{
74637406
AJ		 1057 target_long simm = SIMM(ctx->opcode);
1058
1059 if (rA(ctx->opcode) == 0) {
1060 /* lis case */
1061 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1062 } else {
1063 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1064 }
d9bce9d9 1065}
74637406
AJ		 1066
1067static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1068 int sign, int compute_ov)
d9bce9d9 1069{
2ef1b120
AJ		 1070 int l1 = gen_new_label();
1071 int l2 = gen_new_label();
a7812ae4
PB		 1072 TCGv_i32 t0 = tcg_temp_local_new_i32();
1073 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1074
2ef1b120
AJ		 1075 tcg_gen_trunc_tl_i32(t0, arg1);
1076 tcg_gen_trunc_tl_i32(t1, arg2);
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1078 if (sign) {
2ef1b120
AJ		 1079 int l3 = gen_new_label();
1080 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1081 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1082 gen_set_label(l3);
2ef1b120 1083 tcg_gen_div_i32(t0, t0, t1);
74637406 1084 } else {
2ef1b120 1085 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1086 }
1087 if (compute_ov) {
1088 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1089 }
1090 tcg_gen_br(l2);
1091 gen_set_label(l1);
1092 if (sign) {
2ef1b120 1093 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1094 } else {
1095 tcg_gen_movi_i32(t0, 0);
1096 }
1097 if (compute_ov) {
1098 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1099 }
1100 gen_set_label(l2);
2ef1b120 1101 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1102 tcg_temp_free_i32(t0);
1103 tcg_temp_free_i32(t1);
74637406
AJ		 1104 if (unlikely(Rc(ctx->opcode) != 0))
1105 gen_set_Rc0(ctx, ret);
d9bce9d9 1106}
74637406
AJ		 1107/* Div functions */
1108#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1109GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1110{ \
1111 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1112 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1113 sign, compute_ov); \
1114}
1115/* divwu divwu. divwuo divwuo. */
1116GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1117GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1118/* divw divw. divwo divwo. */
1119GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1120GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1121#if defined(TARGET_PPC64)
2ef1b120
AJ		 1122static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1123 int sign, int compute_ov)
d9bce9d9 1124{
2ef1b120
AJ		 1125 int l1 = gen_new_label();
1126 int l2 = gen_new_label();
74637406
AJ		 1127
1128 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1129 if (sign) {
2ef1b120 1130 int l3 = gen_new_label();
74637406
AJ		 1131 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1132 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1133 gen_set_label(l3);
74637406
AJ		 1134 tcg_gen_div_i64(ret, arg1, arg2);
1135 } else {
1136 tcg_gen_divu_i64(ret, arg1, arg2);
1137 }
1138 if (compute_ov) {
1139 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1140 }
1141 tcg_gen_br(l2);
1142 gen_set_label(l1);
1143 if (sign) {
1144 tcg_gen_sari_i64(ret, arg1, 63);
1145 } else {
1146 tcg_gen_movi_i64(ret, 0);
1147 }
1148 if (compute_ov) {
1149 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1150 }
1151 gen_set_label(l2);
1152 if (unlikely(Rc(ctx->opcode) != 0))
1153 gen_set_Rc0(ctx, ret);
d9bce9d9 1154}
74637406
AJ		 1155#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1156GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1157{ \
2ef1b120
AJ		 1158 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1159 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1160 sign, compute_ov); \
74637406
AJ		 1161}
1162/* divwu divwu. divwuo divwuo. */
1163GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1164GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1165/* divw divw. divwo divwo. */
1166GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1167GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1168#endif
74637406
AJ		 1169
1170/* mulhw mulhw. */
1171GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1172{
a7812ae4 1173 TCGv_i64 t0, t1;
74637406 1174
a7812ae4
PB		 1175 t0 = tcg_temp_new_i64();
1176 t1 = tcg_temp_new_i64();
74637406
AJ		 1177#if defined(TARGET_PPC64)
1178 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1179 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1180 tcg_gen_mul_i64(t0, t0, t1);
1181 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1182#else
1183 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1184 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1185 tcg_gen_mul_i64(t0, t0, t1);
1186 tcg_gen_shri_i64(t0, t0, 32);
1187 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1188#endif
a7812ae4
PB		 1189 tcg_temp_free_i64(t0);
1190 tcg_temp_free_i64(t1);
74637406
AJ		 1191 if (unlikely(Rc(ctx->opcode) != 0))
1192 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1193}
74637406
AJ		 1194/* mulhwu mulhwu. */
1195GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1196{
a7812ae4 1197 TCGv_i64 t0, t1;
74637406 1198
a7812ae4
PB		 1199 t0 = tcg_temp_new_i64();
1200 t1 = tcg_temp_new_i64();
d9bce9d9 1201#if defined(TARGET_PPC64)
74637406
AJ		 1202 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1203 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1204 tcg_gen_mul_i64(t0, t0, t1);
1205 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1206#else
1207 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1208 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1209 tcg_gen_mul_i64(t0, t0, t1);
1210 tcg_gen_shri_i64(t0, t0, 32);
1211 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1212#endif
a7812ae4
PB		 1213 tcg_temp_free_i64(t0);
1214 tcg_temp_free_i64(t1);
74637406
AJ		 1215 if (unlikely(Rc(ctx->opcode) != 0))
1216 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1217}
74637406
AJ		 1218/* mullw mullw. */
1219GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1220{
74637406
AJ		 1221 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1222 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1223 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1224 if (unlikely(Rc(ctx->opcode) != 0))
1225 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1226}
74637406
AJ		 1227/* mullwo mullwo. */
1228GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1229{
74637406 1230 int l1;
a7812ae4 1231 TCGv_i64 t0, t1;
74637406 1232
a7812ae4
PB		 1233 t0 = tcg_temp_new_i64();
1234 t1 = tcg_temp_new_i64();
74637406
AJ		 1235 l1 = gen_new_label();
1236 /* Start with XER OV disabled, the most likely case */
1237 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1238#if defined(TARGET_PPC64)
1239 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1240 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1241#else
1242 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1243 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1244#endif
74637406
AJ		 1245 tcg_gen_mul_i64(t0, t0, t1);
1246#if defined(TARGET_PPC64)
1247 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1248 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1249#else
1250 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1251 tcg_gen_ext32s_i64(t1, t0);
1252 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1253#endif
1254 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1255 gen_set_label(l1);
a7812ae4
PB		 1256 tcg_temp_free_i64(t0);
1257 tcg_temp_free_i64(t1);
74637406
AJ		 1258 if (unlikely(Rc(ctx->opcode) != 0))
1259 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1260}
74637406
AJ		 1261/* mulli */
1262GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1263{
74637406
AJ		 1264 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1265 SIMM(ctx->opcode));
d9bce9d9
JM		 1266}
1267#if defined(TARGET_PPC64)
74637406
AJ		 1268#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1269GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1270{ \
a7812ae4 1271 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1272 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1273 if (unlikely(Rc(ctx->opcode) != 0)) \
1274 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1275}
74637406
AJ		 1276/* mulhd mulhd. */
1277GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1278/* mulhdu mulhdu. */
1279GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1280/* mulld mulld. */
1281GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1282{
74637406
AJ		 1283 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1284 cpu_gpr[rB(ctx->opcode)]);
1285 if (unlikely(Rc(ctx->opcode) != 0))
1286 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1287}
74637406
AJ		 1288/* mulldo mulldo. */
1289GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1290#endif
74637406
AJ		 1291
1292/* neg neg. nego nego. */
ec6469a3 1293static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1294{
ec6469a3
AJ		 1295 int l1 = gen_new_label();
1296 int l2 = gen_new_label();
a7812ae4 1297 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1298#if defined(TARGET_PPC64)
74637406 1299 if (ctx->sf_mode) {
741a7444 1300 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1301 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1302 } else
1303#endif
1304 {
1305 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1306 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1307 }
74637406
AJ		 1308 tcg_gen_neg_tl(ret, arg1);
1309 if (ov_check) {
1310 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1311 }
1312 tcg_gen_br(l2);
1313 gen_set_label(l1);
ec6469a3 1314 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1315 if (ov_check) {
1316 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1317 }
1318 gen_set_label(l2);
ec6469a3 1319 tcg_temp_free(t0);
74637406
AJ		 1320 if (unlikely(Rc(ctx->opcode) != 0))
1321 gen_set_Rc0(ctx, ret);
1322}
1323GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1324{
ec6469a3 1325 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1326}
74637406 1327GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1328{
ec6469a3 1329 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1330}
74637406
AJ		 1331
1332/* Common subf function */
1333static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1334 int add_ca, int compute_ca, int compute_ov)
79aceca5 1335{
74637406 1336 TCGv t0, t1;
76a66253 1337
74637406 1338 if ((!compute_ca && !compute_ov) ||
a7812ae4 1339 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1340 t0 = ret;
e864cabd 1341 } else {
a7812ae4 1342 t0 = tcg_temp_local_new();
d9bce9d9 1343 }
76a66253 1344
74637406 1345 if (add_ca) {
a7812ae4 1346 t1 = tcg_temp_local_new();
74637406
AJ		 1347 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1348 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1349 }
79aceca5 1350
74637406
AJ		 1351 if (compute_ca && compute_ov) {
1352 /* Start with XER CA and OV disabled, the most likely case */
1353 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1354 } else if (compute_ca) {
1355 /* Start with XER CA disabled, the most likely case */
1356 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1357 } else if (compute_ov) {
1358 /* Start with XER OV disabled, the most likely case */
1359 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1360 }
1361
1362 if (add_ca) {
1363 tcg_gen_not_tl(t0, arg1);
1364 tcg_gen_add_tl(t0, t0, arg2);
1365 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1366 tcg_gen_add_tl(t0, t0, t1);
1367 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1368 tcg_temp_free(t1);
79aceca5 1369 } else {
74637406
AJ		 1370 tcg_gen_sub_tl(t0, arg2, arg1);
1371 if (compute_ca) {
1372 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1373 }
1374 }
1375 if (compute_ov) {
1376 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1377 }
1378
1379 if (unlikely(Rc(ctx->opcode) != 0))
1380 gen_set_Rc0(ctx, t0);
1381
a7812ae4 1382 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1383 tcg_gen_mov_tl(ret, t0);
1384 tcg_temp_free(t0);
79aceca5 1385 }
79aceca5 1386}
74637406
AJ		 1387/* Sub functions with Two operands functions */
1388#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1389GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1390{ \
1391 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1392 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1393 add_ca, compute_ca, compute_ov); \
1394}
1395/* Sub functions with one operand and one immediate */
1396#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1397 add_ca, compute_ca, compute_ov) \
1398GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1399{ \
1400 TCGv t0 = tcg_const_local_tl(const_val); \
1401 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1402 cpu_gpr[rA(ctx->opcode)], t0, \
1403 add_ca, compute_ca, compute_ov); \
1404 tcg_temp_free(t0); \
1405}
1406/* subf subf. subfo subfo. */
1407GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1408GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1409/* subfc subfc. subfco subfco. */
1410GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1411GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1412/* subfe subfe. subfeo subfo. */
1413GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1414GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1415/* subfme subfme. subfmeo subfmeo. */
1416GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1417GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1418/* subfze subfze. subfzeo subfzeo.*/
1419GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1420GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1421/* subfic */
1422GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1423{
74637406
AJ		 1424 /* Start with XER CA and OV disabled, the most likely case */
1425 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1426 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1427 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1428 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1429 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1430 tcg_temp_free(t1);
1431 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1432 tcg_temp_free(t0);
79aceca5
FB		 1433}
1434
79aceca5 1435/*** Integer logical ***/
26d67362
AJ		 1436#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1437GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1438{ \
26d67362
AJ		 1439 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1440 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1441 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1442 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1443}
79aceca5 1444
26d67362 1445#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1446GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1447{ \
26d67362 1448 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1449 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1450 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1451}
1452
1453/* and & and. */
26d67362 1454GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1455/* andc & andc. */
26d67362 1456GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1457/* andi. */
c7697e1f 1458GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1459{
26d67362
AJ		 1460 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1462}
1463/* andis. */
c7697e1f 1464GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1465{
26d67362
AJ		 1466 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1467 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1468}
79aceca5 1469/* cntlzw */
26d67362
AJ		 1470GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1471{
a7812ae4 1472 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1473 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1474 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1475}
79aceca5 1476/* eqv & eqv. */
26d67362 1477GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1478/* extsb & extsb. */
26d67362 1479GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1480/* extsh & extsh. */
26d67362 1481GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1482/* nand & nand. */
26d67362 1483GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1484/* nor & nor. */
26d67362 1485GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1486/* or & or. */
9a64fbe4
FB		 1487GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1488{
76a66253
JM		 1489 int rs, ra, rb;
1490
1491 rs = rS(ctx->opcode);
1492 ra = rA(ctx->opcode);
1493 rb = rB(ctx->opcode);
1494 /* Optimisation for mr. ri case */
1495 if (rs != ra || rs != rb) {
26d67362
AJ		 1496 if (rs != rb)
1497 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1498 else
1499 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1500 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1501 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1502 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1503 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1504#if defined(TARGET_PPC64)
1505 } else {
26d67362
AJ		 1506 int prio = 0;
1507
c80f84e3
JM		 1508 switch (rs) {
1509 case 1:
1510 /* Set process priority to low */
26d67362 1511 prio = 2;
c80f84e3
JM		 1512 break;
1513 case 6:
1514 /* Set process priority to medium-low */
26d67362 1515 prio = 3;
c80f84e3
JM		 1516 break;
1517 case 2:
1518 /* Set process priority to normal */
26d67362 1519 prio = 4;
c80f84e3 1520 break;
be147d08
JM		 1521#if !defined(CONFIG_USER_ONLY)
1522 case 31:
1523 if (ctx->supervisor > 0) {
1524 /* Set process priority to very low */
26d67362 1525 prio = 1;
be147d08
JM		 1526 }
1527 break;
1528 case 5:
1529 if (ctx->supervisor > 0) {
1530 /* Set process priority to medium-hight */
26d67362 1531 prio = 5;
be147d08
JM		 1532 }
1533 break;
1534 case 3:
1535 if (ctx->supervisor > 0) {
1536 /* Set process priority to high */
26d67362 1537 prio = 6;
be147d08
JM		 1538 }
1539 break;
be147d08
JM		 1540 case 7:
1541 if (ctx->supervisor > 1) {
1542 /* Set process priority to very high */
26d67362 1543 prio = 7;
be147d08
JM		 1544 }
1545 break;
be147d08 1546#endif
c80f84e3
JM		 1547 default:
1548 /* nop */
1549 break;
1550 }
26d67362 1551 if (prio) {
a7812ae4 1552 TCGv t0 = tcg_temp_new();
ea363694
AJ		 1553 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1554 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1555 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1556 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1557 tcg_temp_free(t0);
26d67362 1558 }
c80f84e3 1559#endif
9a64fbe4 1560 }
9a64fbe4 1561}
79aceca5 1562/* orc & orc. */
26d67362 1563GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1564/* xor & xor. */
9a64fbe4
FB		 1565GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1566{
9a64fbe4 1567 /* Optimisation for "set to zero" case */
26d67362 1568 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1569 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1570 else
1571 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1572 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1573 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1574}
79aceca5
FB		 1575/* ori */
1576GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1577{
76a66253 1578 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1579
9a64fbe4
FB		 1580 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1581 /* NOP */
76a66253 1582 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1583 return;
76a66253 1584 }
26d67362 1585 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1586}
1587/* oris */
1588GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1589{
76a66253 1590 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1591
9a64fbe4
FB		 1592 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1593 /* NOP */
1594 return;
76a66253 1595 }
26d67362 1596 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1597}
1598/* xori */
1599GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1600{
76a66253 1601 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1602
1603 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1604 /* NOP */
1605 return;
1606 }
26d67362 1607 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1608}
79aceca5
FB		 1609/* xoris */
1610GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1611{
76a66253 1612 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1613
1614 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1615 /* NOP */
1616 return;
1617 }
26d67362 1618 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1619}
d9bce9d9 1620/* popcntb : PowerPC 2.03 specification */
05332d70 1621GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1622{
d9bce9d9
JM		 1623#if defined(TARGET_PPC64)
1624 if (ctx->sf_mode)
a7812ae4 1625 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1626 else
1627#endif
a7812ae4 1628 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1629}
1630
1631#if defined(TARGET_PPC64)
1632/* extsw & extsw. */
26d67362 1633GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1634/* cntlzd */
26d67362
AJ		 1635GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1636{
a7812ae4 1637 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1638 if (unlikely(Rc(ctx->opcode) != 0))
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640}
d9bce9d9
JM		 1641#endif
1642
79aceca5
FB		 1643/*** Integer rotate ***/
1644/* rlwimi & rlwimi. */
1645GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1646{
76a66253 1647 uint32_t mb, me, sh;
79aceca5
FB		 1648
1649 mb = MB(ctx->opcode);
1650 me = ME(ctx->opcode);
76a66253 1651 sh = SH(ctx->opcode);
d03ef511
AJ		 1652 if (likely(sh == 0 && mb == 0 && me == 31)) {
1653 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1654 } else {
d03ef511 1655 target_ulong mask;
a7812ae4
PB		 1656 TCGv t1;
1657 TCGv t0 = tcg_temp_new();
54843a58 1658#if defined(TARGET_PPC64)
a7812ae4
PB		 1659 TCGv_i32 t2 = tcg_temp_new_i32();
1660 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1661 tcg_gen_rotli_i32(t2, t2, sh);
1662 tcg_gen_extu_i32_i64(t0, t2);
1663 tcg_temp_free_i32(t2);
54843a58
AJ		 1664#else
1665 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1666#endif
76a66253 1667#if defined(TARGET_PPC64)
d03ef511
AJ		 1668 mb += 32;
1669 me += 32;
76a66253 1670#endif
d03ef511 1671 mask = MASK(mb, me);
a7812ae4 1672 t1 = tcg_temp_new();
d03ef511
AJ		 1673 tcg_gen_andi_tl(t0, t0, mask);
1674 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1675 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1676 tcg_temp_free(t0);
1677 tcg_temp_free(t1);
1678 }
76a66253 1679 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1680 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1681}
1682/* rlwinm & rlwinm. */
1683GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1684{
1685 uint32_t mb, me, sh;
3b46e624 1686
79aceca5
FB		 1687 sh = SH(ctx->opcode);
1688 mb = MB(ctx->opcode);
1689 me = ME(ctx->opcode);
d03ef511
AJ		 1690
1691 if (likely(mb == 0 && me == (31 - sh))) {
1692 if (likely(sh == 0)) {
1693 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1694 } else {
a7812ae4 1695 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1696 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1697 tcg_gen_shli_tl(t0, t0, sh);
1698 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1699 tcg_temp_free(t0);
79aceca5 1700 }
d03ef511 1701 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1702 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1703 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1704 tcg_gen_shri_tl(t0, t0, mb);
1705 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1706 tcg_temp_free(t0);
1707 } else {
a7812ae4 1708 TCGv t0 = tcg_temp_new();
54843a58 1709#if defined(TARGET_PPC64)
a7812ae4 1710 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1711 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1712 tcg_gen_rotli_i32(t1, t1, sh);
1713 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1714 tcg_temp_free_i32(t1);
54843a58
AJ		 1715#else
1716 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1717#endif
76a66253 1718#if defined(TARGET_PPC64)
d03ef511
AJ		 1719 mb += 32;
1720 me += 32;
76a66253 1721#endif
d03ef511
AJ		 1722 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1723 tcg_temp_free(t0);
1724 }
76a66253 1725 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1726 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1727}
1728/* rlwnm & rlwnm. */
1729GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1730{
1731 uint32_t mb, me;
54843a58
AJ		 1732 TCGv t0;
1733#if defined(TARGET_PPC64)
a7812ae4 1734 TCGv_i32 t1, t2;
54843a58 1735#endif
79aceca5
FB		 1736
1737 mb = MB(ctx->opcode);
1738 me = ME(ctx->opcode);
a7812ae4 1739 t0 = tcg_temp_new();
d03ef511 1740 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1741#if defined(TARGET_PPC64)
a7812ae4
PB		 1742 t1 = tcg_temp_new_i32();
1743 t2 = tcg_temp_new_i32();
54843a58
AJ		 1744 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1745 tcg_gen_trunc_i64_i32(t2, t0);
1746 tcg_gen_rotl_i32(t1, t1, t2);
1747 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1748 tcg_temp_free_i32(t1);
1749 tcg_temp_free_i32(t2);
54843a58
AJ		 1750#else
1751 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1752#endif
76a66253
JM		 1753 if (unlikely(mb != 0 || me != 31)) {
1754#if defined(TARGET_PPC64)
1755 mb += 32;
1756 me += 32;
1757#endif
54843a58 1758 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1759 } else {
54843a58 1760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1761 }
54843a58 1762 tcg_temp_free(t0);
76a66253 1763 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1765}
1766
d9bce9d9
JM		 1767#if defined(TARGET_PPC64)
1768#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1769GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1770{ \
1771 gen_##name(ctx, 0); \
1772} \
c7697e1f
JM		 1773GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1774 PPC_64B) \
d9bce9d9
JM		 1775{ \
1776 gen_##name(ctx, 1); \
1777}
1778#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1779GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1780{ \
1781 gen_##name(ctx, 0, 0); \
1782} \
c7697e1f
JM		 1783GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1784 PPC_64B) \
d9bce9d9
JM		 1785{ \
1786 gen_##name(ctx, 0, 1); \
1787} \
c7697e1f
JM		 1788GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1789 PPC_64B) \
d9bce9d9
JM		 1790{ \
1791 gen_##name(ctx, 1, 0); \
1792} \
c7697e1f
JM		 1793GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1794 PPC_64B) \
d9bce9d9
JM		 1795{ \
1796 gen_##name(ctx, 1, 1); \
1797}
51789c41 1798
b068d6a7
JM		 1799static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1800 uint32_t me, uint32_t sh)
51789c41 1801{
d03ef511
AJ		 1802 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1803 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1804 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1805 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1806 } else {
a7812ae4 1807 TCGv t0 = tcg_temp_new();
54843a58 1808 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1809 if (likely(mb == 0 && me == 63)) {
54843a58 1810 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1811 } else {
1812 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1813 }
d03ef511 1814 tcg_temp_free(t0);
51789c41 1815 }
51789c41 1816 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1817 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1818}
d9bce9d9 1819/* rldicl - rldicl. */
b068d6a7 1820static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1821{
51789c41 1822 uint32_t sh, mb;
d9bce9d9 1823
9d53c753
JM		 1824 sh = SH(ctx->opcode) | (shn << 5);
1825 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1826 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1827}
51789c41 1828GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1829/* rldicr - rldicr. */
b068d6a7 1830static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1831{
51789c41 1832 uint32_t sh, me;
d9bce9d9 1833
9d53c753
JM		 1834 sh = SH(ctx->opcode) | (shn << 5);
1835 me = MB(ctx->opcode) | (men << 5);
51789c41 1836 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1837}
51789c41 1838GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1839/* rldic - rldic. */
b068d6a7 1840static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1841{
51789c41 1842 uint32_t sh, mb;
d9bce9d9 1843
9d53c753
JM		 1844 sh = SH(ctx->opcode) | (shn << 5);
1845 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1846 gen_rldinm(ctx, mb, 63 - sh, sh);
1847}
1848GEN_PPC64_R4(rldic, 0x1E, 0x04);
1849
b068d6a7
JM		 1850static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1851 uint32_t me)
51789c41 1852{
54843a58 1853 TCGv t0;
d03ef511
AJ		 1854
1855 mb = MB(ctx->opcode);
1856 me = ME(ctx->opcode);
a7812ae4 1857 t0 = tcg_temp_new();
d03ef511 1858 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1859 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1860 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1861 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1862 } else {
1863 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1864 }
1865 tcg_temp_free(t0);
51789c41 1866 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1867 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1868}
51789c41 1869
d9bce9d9 1870/* rldcl - rldcl. */
b068d6a7 1871static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1872{
51789c41 1873 uint32_t mb;
d9bce9d9 1874
9d53c753 1875 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1876 gen_rldnm(ctx, mb, 63);
d9bce9d9 1877}
36081602 1878GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1879/* rldcr - rldcr. */
b068d6a7 1880static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1881{
51789c41 1882 uint32_t me;
d9bce9d9 1883
9d53c753 1884 me = MB(ctx->opcode) | (men << 5);
51789c41 1885 gen_rldnm(ctx, 0, me);
d9bce9d9 1886}
36081602 1887GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1888/* rldimi - rldimi. */
b068d6a7 1889static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1890{
271a916e 1891 uint32_t sh, mb, me;
d9bce9d9 1892
9d53c753
JM		 1893 sh = SH(ctx->opcode) | (shn << 5);
1894 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1895 me = 63 - sh;
d03ef511
AJ		 1896 if (unlikely(sh == 0 && mb == 0)) {
1897 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1898 } else {
1899 TCGv t0, t1;
1900 target_ulong mask;
1901
a7812ae4 1902 t0 = tcg_temp_new();
54843a58 1903 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1904 t1 = tcg_temp_new();
d03ef511
AJ		 1905 mask = MASK(mb, me);
1906 tcg_gen_andi_tl(t0, t0, mask);
1907 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1908 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1909 tcg_temp_free(t0);
1910 tcg_temp_free(t1);
51789c41 1911 }
51789c41 1912 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1914}
36081602 1915GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1916#endif
1917
79aceca5
FB		 1918/*** Integer shift ***/
1919/* slw & slw. */
26d67362
AJ		 1920GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1921{
fea0c503 1922 TCGv t0;
26d67362
AJ		 1923 int l1, l2;
1924 l1 = gen_new_label();
1925 l2 = gen_new_label();
1926
a7812ae4 1927 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1928 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1929 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1930 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1931 tcg_gen_br(l2);
1932 gen_set_label(l1);
fea0c503 1933 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1934 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1935 gen_set_label(l2);
fea0c503 1936 tcg_temp_free(t0);
26d67362
AJ		 1937 if (unlikely(Rc(ctx->opcode) != 0))
1938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1939}
79aceca5 1940/* sraw & sraw. */
26d67362
AJ		 1941GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1942{
a7812ae4
PB		 1943 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1944 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1945 if (unlikely(Rc(ctx->opcode) != 0))
1946 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1947}
79aceca5
FB		 1948/* srawi & srawi. */
1949GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1950{
26d67362
AJ		 1951 int sh = SH(ctx->opcode);
1952 if (sh != 0) {
1953 int l1, l2;
fea0c503 1954 TCGv t0;
26d67362
AJ		 1955 l1 = gen_new_label();
1956 l2 = gen_new_label();
a7812ae4 1957 t0 = tcg_temp_local_new();
fea0c503
AJ		 1958 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1959 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1960 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1961 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1962 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1963 tcg_gen_br(l2);
1964 gen_set_label(l1);
269f3e95 1965 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1966 gen_set_label(l2);
fea0c503
AJ		 1967 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1968 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1969 tcg_temp_free(t0);
26d67362
AJ		 1970 } else {
1971 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1972 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1973 }
76a66253 1974 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1975 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1976}
1977/* srw & srw. */
26d67362
AJ		 1978GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1979{
fea0c503 1980 TCGv t0, t1;
26d67362
AJ		 1981 int l1, l2;
1982 l1 = gen_new_label();
1983 l2 = gen_new_label();
d9bce9d9 1984
a7812ae4 1985 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1986 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1987 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1988 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1989 tcg_gen_br(l2);
1990 gen_set_label(l1);
a7812ae4 1991 t1 = tcg_temp_new();
fea0c503
AJ		 1992 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1993 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1994 tcg_temp_free(t1);
26d67362 1995 gen_set_label(l2);
fea0c503 1996 tcg_temp_free(t0);
26d67362
AJ		 1997 if (unlikely(Rc(ctx->opcode) != 0))
1998 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1999}
d9bce9d9
JM		 2000#if defined(TARGET_PPC64)
2001/* sld & sld. */
26d67362
AJ		 2002GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2003{
fea0c503 2004 TCGv t0;
26d67362
AJ		 2005 int l1, l2;
2006 l1 = gen_new_label();
2007 l2 = gen_new_label();
2008
a7812ae4 2009 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2010 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2011 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2012 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2013 tcg_gen_br(l2);
2014 gen_set_label(l1);
fea0c503 2015 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2016 gen_set_label(l2);
fea0c503 2017 tcg_temp_free(t0);
26d67362
AJ		 2018 if (unlikely(Rc(ctx->opcode) != 0))
2019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2020}
d9bce9d9 2021/* srad & srad. */
26d67362
AJ		 2022GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2023{
a7812ae4
PB		 2024 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2025 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2026 if (unlikely(Rc(ctx->opcode) != 0))
2027 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2028}
d9bce9d9 2029/* sradi & sradi. */
b068d6a7 2030static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2031{
26d67362 2032 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2033 if (sh != 0) {
26d67362 2034 int l1, l2;
fea0c503 2035 TCGv t0;
26d67362
AJ		 2036 l1 = gen_new_label();
2037 l2 = gen_new_label();
a7812ae4 2038 t0 = tcg_temp_local_new();
26d67362 2039 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2040 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2041 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2042 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2043 tcg_gen_br(l2);
2044 gen_set_label(l1);
269f3e95 2045 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2046 gen_set_label(l2);
a9730017 2047 tcg_temp_free(t0);
26d67362
AJ		 2048 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2049 } else {
2050 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2051 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2052 }
d9bce9d9 2053 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2054 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2055}
c7697e1f 2056GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2057{
2058 gen_sradi(ctx, 0);
2059}
c7697e1f 2060GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2061{
2062 gen_sradi(ctx, 1);
2063}
2064/* srd & srd. */
26d67362
AJ		 2065GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2066{
fea0c503 2067 TCGv t0;
26d67362
AJ		 2068 int l1, l2;
2069 l1 = gen_new_label();
2070 l2 = gen_new_label();
2071
a7812ae4 2072 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2073 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2074 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2075 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2076 tcg_gen_br(l2);
2077 gen_set_label(l1);
fea0c503 2078 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2079 gen_set_label(l2);
fea0c503 2080 tcg_temp_free(t0);
26d67362
AJ		 2081 if (unlikely(Rc(ctx->opcode) != 0))
2082 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2083}
d9bce9d9 2084#endif
79aceca5
FB		 2085
2086/*** Floating-Point arithmetic ***/
7c58044c 2087#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2088GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2089{ \
76a66253 2090 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2091 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2092 return; \
2093 } \
7c58044c 2094 gen_reset_fpstatus(); \
af12906f
AJ		 2095 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2096 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2097 if (isfloat) { \
af12906f 2098 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2099 } \
af12906f
AJ		 2100 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2101 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2102}
2103
7c58044c
JM		 2104#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2105_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2106_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2107
7c58044c
JM		 2108#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2109GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2110{ \
76a66253 2111 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2112 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2113 return; \
2114 } \
7c58044c 2115 gen_reset_fpstatus(); \
af12906f
AJ		 2116 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2117 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2118 if (isfloat) { \
af12906f 2119 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2120 } \
af12906f
AJ		 2121 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2122 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2123}
7c58044c
JM		 2124#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2125_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2126_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2127
7c58044c
JM		 2128#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2129GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2130{ \
76a66253 2131 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2132 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2133 return; \
2134 } \
7c58044c 2135 gen_reset_fpstatus(); \
af12906f
AJ		 2136 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2137 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2138 if (isfloat) { \
af12906f 2139 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2140 } \
af12906f
AJ		 2141 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2142 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2143}
7c58044c
JM		 2144#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2145_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2146_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2147
7c58044c 2148#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2149GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2150{ \
76a66253 2151 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2152 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2153 return; \
2154 } \
7c58044c 2155 gen_reset_fpstatus(); \
af12906f
AJ		 2156 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2157 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2158 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2159}
2160
7c58044c 2161#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2162GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2163{ \
76a66253 2164 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2165 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2166 return; \
2167 } \
7c58044c 2168 gen_reset_fpstatus(); \
af12906f
AJ		 2169 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2170 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2171 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2172}
2173
9a64fbe4 2174/* fadd - fadds */
7c58044c 2175GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2176/* fdiv - fdivs */
7c58044c 2177GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2178/* fmul - fmuls */
7c58044c 2179GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2180
d7e4b87e 2181/* fre */
7c58044c 2182GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2183
a750fc0b 2184/* fres */
7c58044c 2185GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2186
a750fc0b 2187/* frsqrte */
7c58044c
JM		 2188GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2189
2190/* frsqrtes */
af12906f 2191GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2192{
af12906f
AJ		 2193 if (unlikely(!ctx->fpu_enabled)) {
2194 GEN_EXCP_NO_FP(ctx);
2195 return;
2196 }
2197 gen_reset_fpstatus();
2198 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2199 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2200 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2201}
79aceca5 2202
a750fc0b 2203/* fsel */
7c58044c 2204_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2205/* fsub - fsubs */
7c58044c 2206GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2207/* Optional: */
2208/* fsqrt */
a750fc0b 2209GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2210{
76a66253 2211 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2212 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2213 return;
2214 }
7c58044c 2215 gen_reset_fpstatus();
af12906f
AJ		 2216 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2217 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2218}
79aceca5 2219
a750fc0b 2220GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2221{
76a66253 2222 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2223 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2224 return;
2225 }
7c58044c 2226 gen_reset_fpstatus();
af12906f
AJ		 2227 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2228 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2229 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2230}
2231
2232/*** Floating-Point multiply-and-add ***/
4ecc3190 2233/* fmadd - fmadds */
7c58044c 2234GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2235/* fmsub - fmsubs */
7c58044c 2236GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2237/* fnmadd - fnmadds */
7c58044c 2238GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2239/* fnmsub - fnmsubs */
7c58044c 2240GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2241
2242/*** Floating-Point round & convert ***/
2243/* fctiw */
7c58044c 2244GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2245/* fctiwz */
7c58044c 2246GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2247/* frsp */
7c58044c 2248GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2249#if defined(TARGET_PPC64)
2250/* fcfid */
7c58044c 2251GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2252/* fctid */
7c58044c 2253GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2254/* fctidz */
7c58044c 2255GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2256#endif
79aceca5 2257
d7e4b87e 2258/* frin */
7c58044c 2259GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2260/* friz */
7c58044c 2261GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2262/* frip */
7c58044c 2263GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2264/* frim */
7c58044c 2265GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2266
79aceca5
FB		 2267/*** Floating-Point compare ***/
2268/* fcmpo */
76a66253 2269GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2270{
76a66253 2271 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2272 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2273 return;
2274 }
7c58044c 2275 gen_reset_fpstatus();
af12906f
AJ		 2276 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2277 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2278 gen_helper_float_check_status();
79aceca5
FB		 2279}
2280
2281/* fcmpu */
76a66253 2282GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2283{
76a66253 2284 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2285 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2286 return;
2287 }
7c58044c 2288 gen_reset_fpstatus();
af12906f
AJ		 2289 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2290 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2291 gen_helper_float_check_status();
79aceca5
FB		 2292}
2293
9a64fbe4
FB		 2294/*** Floating-point move ***/
2295/* fabs */
7c58044c
JM		 2296/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2297GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2298
2299/* fmr - fmr. */
7c58044c 2300/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2301GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2302{
76a66253 2303 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2304 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2305 return;
2306 }
af12906f
AJ		 2307 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2308 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2309}
2310
2311/* fnabs */
7c58044c
JM		 2312/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2313GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2314/* fneg */
7c58044c
JM		 2315/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2316GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2317
79aceca5
FB		 2318/*** Floating-Point status & ctrl register ***/
2319/* mcrfs */
2320GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2321{
7c58044c
JM		 2322 int bfa;
2323
76a66253 2324 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2325 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2326 return;
2327 }
7c58044c
JM		 2328 gen_optimize_fprf();
2329 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2330 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2331 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2332 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2333}
2334
2335/* mffs */
2336GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2337{
76a66253 2338 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2339 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2340 return;
2341 }
7c58044c
JM		 2342 gen_optimize_fprf();
2343 gen_reset_fpstatus();
af12906f
AJ		 2344 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2345 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2346}
2347
2348/* mtfsb0 */
2349GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2350{
fb0eaffc 2351 uint8_t crb;
3b46e624 2352
76a66253 2353 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2354 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2355 return;
2356 }
7c58044c
JM		 2357 crb = 32 - (crbD(ctx->opcode) >> 2);
2358 gen_optimize_fprf();
2359 gen_reset_fpstatus();
2360 if (likely(crb != 30 && crb != 29))
af12906f 2361 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
7c58044c 2362 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2363 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2364 }
79aceca5
FB		 2365}
2366
2367/* mtfsb1 */
2368GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2369{
fb0eaffc 2370 uint8_t crb;
3b46e624 2371
76a66253 2372 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2373 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2374 return;
2375 }
7c58044c
JM		 2376 crb = 32 - (crbD(ctx->opcode) >> 2);
2377 gen_optimize_fprf();
2378 gen_reset_fpstatus();
2379 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2380 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
0f2f39c2 2381 TCGv_i32 t0 = tcg_const_i32(crb);
af12906f 2382 gen_helper_fpscr_setbit(t0);
0f2f39c2 2383 tcg_temp_free_i32(t0);
af12906f 2384 }
7c58044c 2385 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2386 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2387 }
2388 /* We can raise a differed exception */
af12906f 2389 gen_helper_float_check_status();
79aceca5
FB		 2390}
2391
2392/* mtfsf */
2393GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2394{
0f2f39c2 2395 TCGv_i32 t0;
af12906f 2396
76a66253 2397 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2398 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2399 return;
2400 }
7c58044c 2401 gen_optimize_fprf();
7c58044c 2402 gen_reset_fpstatus();
af12906f
AJ		 2403 t0 = tcg_const_i32(FM(ctx->opcode));
2404 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2405 tcg_temp_free_i32(t0);
7c58044c 2406 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2407 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2408 }
2409 /* We can raise a differed exception */
af12906f 2410 gen_helper_float_check_status();
79aceca5
FB		 2411}
2412
2413/* mtfsfi */
2414GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2415{
7c58044c 2416 int bf, sh;
0f2f39c2
AJ		 2417 TCGv_i64 t0;
2418 TCGv_i32 t1;
7c58044c 2419
76a66253 2420 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2421 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2422 return;
2423 }
7c58044c
JM		 2424 bf = crbD(ctx->opcode) >> 2;
2425 sh = 7 - bf;
2426 gen_optimize_fprf();
7c58044c 2427 gen_reset_fpstatus();
0f2f39c2 2428 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2429 t1 = tcg_const_i32(1 << sh);
2430 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2431 tcg_temp_free_i64(t0);
2432 tcg_temp_free_i32(t1);
7c58044c 2433 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2434 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2435 }
2436 /* We can raise a differed exception */
af12906f 2437 gen_helper_float_check_status();
79aceca5
FB		 2438}
2439
76a66253
JM		 2440/*** Addressing modes ***/
2441/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2442static always_inline void gen_addr_imm_index (TCGv EA,
2443 DisasContext *ctx,
b068d6a7 2444 target_long maskl)
76a66253
JM		 2445{
2446 target_long simm = SIMM(ctx->opcode);
2447
be147d08 2448 simm &= ~maskl;
e2be8d8d
AJ		 2449 if (rA(ctx->opcode) == 0)
2450 tcg_gen_movi_tl(EA, simm);
2451 else if (likely(simm != 0))
2452 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2453 else
2454 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2455}
2456
e2be8d8d
AJ		 2457static always_inline void gen_addr_reg_index (TCGv EA,
2458 DisasContext *ctx)
76a66253 2459{
e2be8d8d
AJ		 2460 if (rA(ctx->opcode) == 0)
2461 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2462 else
2463 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2464}
2465
e2be8d8d
AJ		 2466static always_inline void gen_addr_register (TCGv EA,
2467 DisasContext *ctx)
76a66253 2468{
e2be8d8d
AJ		 2469 if (rA(ctx->opcode) == 0)
2470 tcg_gen_movi_tl(EA, 0);
2471 else
2472 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2473}
2474
cf360a32
AJ		 2475static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2476{
2477 int l1 = gen_new_label();
2478 TCGv t0 = tcg_temp_new();
2479 TCGv_i32 t1, t2;
2480 /* NIP cannot be restored if the memory exception comes from an helper */
2481 gen_update_nip(ctx, ctx->nip - 4);
2482 tcg_gen_andi_tl(t0, EA, mask);
2483 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2484 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2485 t2 = tcg_const_i32(0);
2486 gen_helper_raise_exception_err(t1, t2);
2487 tcg_temp_free_i32(t1);
2488 tcg_temp_free_i32(t2);
2489 gen_set_label(l1);
2490 tcg_temp_free(t0);
2491}
2492
7863667f
JM		 2493#if defined(TARGET_PPC64)
2494#define _GEN_MEM_FUNCS(name, mode) \
2495 &gen_op_##name##_##mode, \
2496 &gen_op_##name##_le_##mode, \
2497 &gen_op_##name##_64_##mode, \
2498 &gen_op_##name##_le_64_##mode
2499#else
2500#define _GEN_MEM_FUNCS(name, mode) \
2501 &gen_op_##name##_##mode, \
2502 &gen_op_##name##_le_##mode
2503#endif
9a64fbe4 2504#if defined(CONFIG_USER_ONLY)
d9bce9d9 2505#if defined(TARGET_PPC64)
7863667f 2506#define NB_MEM_FUNCS 4
d9bce9d9 2507#else
7863667f 2508#define NB_MEM_FUNCS 2
d9bce9d9 2509#endif
7863667f
JM		 2510#define GEN_MEM_FUNCS(name) \
2511 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2512#else
d9bce9d9 2513#if defined(TARGET_PPC64)
7863667f 2514#define NB_MEM_FUNCS 12
2857068e 2515#else
7863667f 2516#define NB_MEM_FUNCS 6
2857068e 2517#endif
7863667f
JM		 2518#define GEN_MEM_FUNCS(name) \
2519 _GEN_MEM_FUNCS(name, user), \
2520 _GEN_MEM_FUNCS(name, kernel), \
2521 _GEN_MEM_FUNCS(name, hypv)
2522#endif
2523
2524/*** Integer load ***/
b61f2753
AJ		 2525#if defined(TARGET_PPC64)
2526#define GEN_QEMU_LD_PPC64(width) \
2527static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2528{ \
2529 if (likely(flags & 2)) \
2530 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2531 else { \
a7812ae4 2532 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2533 tcg_gen_ext32u_tl(addr, t1); \
2534 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2535 tcg_temp_free(addr); \
2536 } \
2537}
2538GEN_QEMU_LD_PPC64(8u)
2539GEN_QEMU_LD_PPC64(8s)
2540GEN_QEMU_LD_PPC64(16u)
2541GEN_QEMU_LD_PPC64(16s)
2542GEN_QEMU_LD_PPC64(32u)
2543GEN_QEMU_LD_PPC64(32s)
2544GEN_QEMU_LD_PPC64(64)
2545
2546#define GEN_QEMU_ST_PPC64(width) \
2547static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2548{ \
2549 if (likely(flags & 2)) \
2550 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2551 else { \
a7812ae4 2552 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2553 tcg_gen_ext32u_tl(addr, t1); \
2554 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2555 tcg_temp_free(addr); \
2556 } \
2557}
2558GEN_QEMU_ST_PPC64(8)
2559GEN_QEMU_ST_PPC64(16)
2560GEN_QEMU_ST_PPC64(32)
2561GEN_QEMU_ST_PPC64(64)
2562
ea363694 2563static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2564{
ea363694 2565 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2566}
2567
ea363694 2568static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2569{
ea363694 2570 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2571}
2572
ea363694 2573static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2574{
2575 if (unlikely(flags & 1)) {
a7812ae4 2576 TCGv_i32 t0;
ea363694 2577 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2578 t0 = tcg_temp_new_i32();
ea363694
AJ		 2579 tcg_gen_trunc_tl_i32(t0, arg0);
2580 tcg_gen_bswap16_i32(t0, t0);
2581 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2582 tcg_temp_free_i32(t0);
b61f2753 2583 } else
ea363694 2584 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2585}
2586
ea363694 2587static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2588{
2589 if (unlikely(flags & 1)) {
a7812ae4 2590 TCGv_i32 t0;
ea363694 2591 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2592 t0 = tcg_temp_new_i32();
ea363694
AJ		 2593 tcg_gen_trunc_tl_i32(t0, arg0);
2594 tcg_gen_bswap16_i32(t0, t0);
2595 tcg_gen_extu_i32_tl(arg0, t0);
2596 tcg_gen_ext16s_tl(arg0, arg0);
a7812ae4 2597 tcg_temp_free_i32(t0);
b61f2753 2598 } else
ea363694 2599 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2600}
2601
ea363694 2602static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2603{
2604 if (unlikely(flags & 1)) {
a7812ae4 2605 TCGv_i32 t0;
ea363694 2606 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2607 t0 = tcg_temp_new_i32();
ea363694
AJ		 2608 tcg_gen_trunc_tl_i32(t0, arg0);
2609 tcg_gen_bswap_i32(t0, t0);
2610 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2611 tcg_temp_free_i32(t0);
b61f2753 2612 } else
ea363694 2613 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2614}
2615
ea363694 2616static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2617{
2618 if (unlikely(flags & 1)) {
a7812ae4 2619 TCGv_i32 t0;
ea363694 2620 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2621 t0 = tcg_temp_new_i32();
ea363694
AJ		 2622 tcg_gen_trunc_tl_i32(t0, arg0);
2623 tcg_gen_bswap_i32(t0, t0);
2624 tcg_gen_ext_i32_tl(arg0, t0);
a7812ae4 2625 tcg_temp_free_i32(t0);
b61f2753 2626 } else
ea363694 2627 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2628}
2629
ea363694 2630static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2631{
ea363694 2632 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2633 if (unlikely(flags & 1))
ea363694 2634 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2635}
2636
ea363694 2637static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2638{
ea363694 2639 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2640}
2641
ea363694 2642static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2643{
2644 if (unlikely(flags & 1)) {
a7812ae4
PB		 2645 TCGv_i32 t0;
2646 TCGv_i64 t1;
2647 t0 = tcg_temp_new_i32();
ea363694
AJ		 2648 tcg_gen_trunc_tl_i32(t0, arg0);
2649 tcg_gen_ext16u_i32(t0, t0);
2650 tcg_gen_bswap16_i32(t0, t0);
a7812ae4 2651 t1 = tcg_temp_new_i64();
ea363694 2652 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2653 tcg_temp_free_i32(t0);
ea363694 2654 gen_qemu_st16_ppc64(t1, arg1, flags);
a7812ae4 2655 tcg_temp_free_i64(t1);
b61f2753 2656 } else
ea363694 2657 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2658}
2659
ea363694 2660static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2661{
2662 if (unlikely(flags & 1)) {
a7812ae4
PB		 2663 TCGv_i32 t0;
2664 TCGv_i64 t1;
2665 t0 = tcg_temp_new_i32();
ea363694
AJ		 2666 tcg_gen_trunc_tl_i32(t0, arg0);
2667 tcg_gen_bswap_i32(t0, t0);
a7812ae4 2668 t1 = tcg_temp_new_i64();
ea363694 2669 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2670 tcg_temp_free_i32(t0);
ea363694 2671 gen_qemu_st32_ppc64(t1, arg1, flags);
a7812ae4 2672 tcg_temp_free_i64(t1);
b61f2753 2673 } else
ea363694 2674 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2675}
2676
ea363694 2677static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2678{
2679 if (unlikely(flags & 1)) {
a7812ae4 2680 TCGv_i64 t0 = tcg_temp_new_i64();
ea363694
AJ		 2681 tcg_gen_bswap_i64(t0, arg0);
2682 gen_qemu_st64_ppc64(t0, arg1, flags);
a7812ae4 2683 tcg_temp_free_i64(t0);
b61f2753 2684 } else
ea363694 2685 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2686}
2687
2688
2689#else /* defined(TARGET_PPC64) */
a0d7d5a7
AJ		 2690#define GEN_QEMU_LD_PPC32(width) \
2691static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2692{ \
2693 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2694}
2695GEN_QEMU_LD_PPC32(8u)
2696GEN_QEMU_LD_PPC32(8s)
2697GEN_QEMU_LD_PPC32(16u)
2698GEN_QEMU_LD_PPC32(16s)
2699GEN_QEMU_LD_PPC32(32u)
2700GEN_QEMU_LD_PPC32(32s)
a0d7d5a7
AJ		 2701static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2702{
2703 tcg_gen_qemu_ld64(arg0, arg1, flags >> 1);
2704}
b61f2753 2705
a0d7d5a7
AJ		 2706#define GEN_QEMU_ST_PPC32(width) \
2707static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2708{ \
2709 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2710}
2711GEN_QEMU_ST_PPC32(8)
2712GEN_QEMU_ST_PPC32(16)
2713GEN_QEMU_ST_PPC32(32)
a0d7d5a7
AJ		 2714static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2715{
2716 tcg_gen_qemu_st64(arg0, arg1, flags >> 1);
2717}
b61f2753 2718
ea363694 2719static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2720{
ea363694 2721 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2722}
2723
ea363694 2724static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2725{
ea363694 2726 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2727}
2728
ea363694 2729static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2730{
ea363694 2731 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2732 if (unlikely(flags & 1))
ea363694 2733 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2734}
2735
ea363694 2736static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2737{
2738 if (unlikely(flags & 1)) {
ea363694
AJ		 2739 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2740 tcg_gen_bswap16_i32(arg0, arg0);
2741 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2742 } else
ea363694 2743 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2744}
2745
ea363694 2746static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2747{
ea363694 2748 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2749 if (unlikely(flags & 1))
ea363694 2750 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2751}
2752
a0d7d5a7
AJ		 2753static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags)
2754{
2755 gen_qemu_ld64_ppc32(arg0, arg1, flags);
2756 if (unlikely(flags & 1))
2757 tcg_gen_bswap_i64(arg0, arg0);
2758}
2759
ea363694 2760static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2761{
e32ad5c2 2762 gen_qemu_st8_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2763}
2764
ea363694 2765static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2766{
2767 if (unlikely(flags & 1)) {
a7812ae4 2768 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2769 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2770 tcg_gen_bswap16_i32(temp, temp);
e32ad5c2 2771 gen_qemu_st16_ppc32(temp, arg1, flags);
a7812ae4 2772 tcg_temp_free_i32(temp);
b61f2753 2773 } else
e32ad5c2 2774 gen_qemu_st16_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2775}
2776
ea363694 2777static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2778{
2779 if (unlikely(flags & 1)) {
a7812ae4 2780 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2781 tcg_gen_bswap_i32(temp, arg0);
e32ad5c2 2782 gen_qemu_st32_ppc32(temp, arg1, flags);
a7812ae4 2783 tcg_temp_free_i32(temp);
b61f2753 2784 } else
e32ad5c2 2785 gen_qemu_st32_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2786}
2787
a0d7d5a7
AJ		 2788static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags)
2789{
2790 if (unlikely(flags & 1)) {
2791 TCGv_i64 temp = tcg_temp_new_i64();
2792 tcg_gen_bswap_i64(temp, arg0);
2793 gen_qemu_st64_ppc32(temp, arg1, flags);
2794 tcg_temp_free_i64(temp);
2795 } else
2796 gen_qemu_st64_ppc32(arg0, arg1, flags);
2797}
b61f2753
AJ		 2798#endif
2799
0c8aacd4
AJ		 2800#define GEN_LD(name, ldop, opc, type) \
2801GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2802{ \
0c8aacd4 2803 TCGv EA = tcg_temp_new(); \
a7859e89 2804 gen_set_access_type(ACCESS_INT); \
b61f2753 2805 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2806 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2807 tcg_temp_free(EA); \
79aceca5
FB		 2808}
2809
0c8aacd4
AJ		 2810#define GEN_LDU(name, ldop, opc, type) \
2811GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2812{ \
b61f2753 2813 TCGv EA; \
76a66253
JM		 2814 if (unlikely(rA(ctx->opcode) == 0 || \
2815 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2816 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2817 return; \
9a64fbe4 2818 } \
0c8aacd4 2819 EA = tcg_temp_new(); \
a7859e89 2820 gen_set_access_type(ACCESS_INT); \
9d53c753 2821 if (type == PPC_64B) \
b61f2753 2822 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2823 else \
b61f2753 2824 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2825 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2826 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2827 tcg_temp_free(EA); \
79aceca5
FB		 2828}
2829
0c8aacd4
AJ		 2830#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2831GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2832{ \
b61f2753 2833 TCGv EA; \
76a66253
JM		 2834 if (unlikely(rA(ctx->opcode) == 0 || \
2835 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2836 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2837 return; \
9a64fbe4 2838 } \
0c8aacd4 2839 EA = tcg_temp_new(); \
a7859e89 2840 gen_set_access_type(ACCESS_INT); \
b61f2753 2841 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2842 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2843 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2844 tcg_temp_free(EA); \
79aceca5
FB		 2845}
2846
0c8aacd4
AJ		 2847#define GEN_LDX(name, ldop, opc2, opc3, type) \
2848GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2849{ \
0c8aacd4 2850 TCGv EA = tcg_temp_new(); \
a7859e89 2851 gen_set_access_type(ACCESS_INT); \
b61f2753 2852 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2853 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2854 tcg_temp_free(EA); \
79aceca5
FB		 2855}
2856
0c8aacd4
AJ		 2857#define GEN_LDS(name, ldop, op, type) \
2858GEN_LD(name, ldop, op | 0x20, type); \
2859GEN_LDU(name, ldop, op | 0x21, type); \
2860GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2861GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2862
2863/* lbz lbzu lbzux lbzx */
0c8aacd4 2864GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2865/* lha lhau lhaux lhax */
0c8aacd4 2866GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2867/* lhz lhzu lhzux lhzx */
0c8aacd4 2868GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2869/* lwz lwzu lwzux lwzx */
0c8aacd4 2870GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2871#if defined(TARGET_PPC64)
d9bce9d9 2872/* lwaux */
0c8aacd4 2873GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2874/* lwax */
0c8aacd4 2875GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2876/* ldux */
0c8aacd4 2877GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2878/* ldx */
0c8aacd4 2879GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2880GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2881{
b61f2753 2882 TCGv EA;
d9bce9d9
JM		 2883 if (Rc(ctx->opcode)) {
2884 if (unlikely(rA(ctx->opcode) == 0 ||
2885 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2886 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2887 return;
2888 }
2889 }
a7812ae4 2890 EA = tcg_temp_new();
a7859e89 2891 gen_set_access_type(ACCESS_INT);
b61f2753 2892 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2893 if (ctx->opcode & 0x02) {
2894 /* lwa (lwau is undefined) */
b61f2753 2895 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2896 } else {
2897 /* ld - ldu */
b61f2753 2898 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2899 }
d9bce9d9 2900 if (Rc(ctx->opcode))
b61f2753
AJ		 2901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2902 tcg_temp_free(EA);
d9bce9d9 2903}
be147d08
JM		 2904/* lq */
2905GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2906{
2907#if defined(CONFIG_USER_ONLY)
2908 GEN_EXCP_PRIVOPC(ctx);
2909#else
2910 int ra, rd;
b61f2753 2911 TCGv EA;
be147d08
JM		 2912
2913 /* Restore CPU state */
2914 if (unlikely(ctx->supervisor == 0)) {
2915 GEN_EXCP_PRIVOPC(ctx);
2916 return;
2917 }
2918 ra = rA(ctx->opcode);
2919 rd = rD(ctx->opcode);
2920 if (unlikely((rd & 1) || rd == ra)) {
2921 GEN_EXCP_INVAL(ctx);
2922 return;
2923 }
2924 if (unlikely(ctx->mem_idx & 1)) {
2925 /* Little-endian mode is not handled */
2926 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2927 return;
2928 }
a7812ae4 2929 EA = tcg_temp_new();
a7859e89 2930 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 2931 gen_addr_imm_index(EA, ctx, 0x0F);
2932 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2933 tcg_gen_addi_tl(EA, EA, 8);
2934 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2935 tcg_temp_free(EA);
be147d08
JM		 2936#endif
2937}
d9bce9d9 2938#endif
79aceca5
FB		 2939
2940/*** Integer store ***/
0c8aacd4
AJ		 2941#define GEN_ST(name, stop, opc, type) \
2942GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2943{ \
0c8aacd4 2944 TCGv EA = tcg_temp_new(); \
a7859e89 2945 gen_set_access_type(ACCESS_INT); \
b61f2753 2946 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2947 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2948 tcg_temp_free(EA); \
79aceca5
FB		 2949}
2950
0c8aacd4
AJ		 2951#define GEN_STU(name, stop, opc, type) \
2952GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2953{ \
b61f2753 2954 TCGv EA; \
76a66253 2955 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2956 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2957 return; \
9a64fbe4 2958 } \
0c8aacd4 2959 EA = tcg_temp_new(); \
a7859e89 2960 gen_set_access_type(ACCESS_INT); \
9d53c753 2961 if (type == PPC_64B) \
b61f2753 2962 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2963 else \
b61f2753 2964 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2965 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2966 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2967 tcg_temp_free(EA); \
79aceca5
FB		 2968}
2969
0c8aacd4
AJ		 2970#define GEN_STUX(name, stop, opc2, opc3, type) \
2971GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2972{ \
b61f2753 2973 TCGv EA; \
76a66253 2974 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2975 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2976 return; \
9a64fbe4 2977 } \
0c8aacd4 2978 EA = tcg_temp_new(); \
a7859e89 2979 gen_set_access_type(ACCESS_INT); \
b61f2753 2980 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2981 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2982 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2983 tcg_temp_free(EA); \
79aceca5
FB		 2984}
2985
0c8aacd4
AJ		 2986#define GEN_STX(name, stop, opc2, opc3, type) \
2987GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2988{ \
0c8aacd4 2989 TCGv EA = tcg_temp_new(); \
a7859e89 2990 gen_set_access_type(ACCESS_INT); \
b61f2753 2991 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2992 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2993 tcg_temp_free(EA); \
79aceca5
FB		 2994}
2995
0c8aacd4
AJ		 2996#define GEN_STS(name, stop, op, type) \
2997GEN_ST(name, stop, op | 0x20, type); \
2998GEN_STU(name, stop, op | 0x21, type); \
2999GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3000GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 3001
3002/* stb stbu stbux stbx */
0c8aacd4 3003GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 3004/* sth sthu sthux sthx */
0c8aacd4 3005GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 3006/* stw stwu stwux stwx */
0c8aacd4 3007GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 3008#if defined(TARGET_PPC64)
0c8aacd4
AJ		 3009GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3010GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 3011GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 3012{
be147d08 3013 int rs;
b61f2753 3014 TCGv EA;
be147d08
JM		 3015
3016 rs = rS(ctx->opcode);
3017 if ((ctx->opcode & 0x3) == 0x2) {
3018#if defined(CONFIG_USER_ONLY)
3019 GEN_EXCP_PRIVOPC(ctx);
3020#else
3021 /* stq */
3022 if (unlikely(ctx->supervisor == 0)) {
3023 GEN_EXCP_PRIVOPC(ctx);
3024 return;
3025 }
3026 if (unlikely(rs & 1)) {
e1833e1f 3027 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 3028 return;
3029 }
be147d08
JM		 3030 if (unlikely(ctx->mem_idx & 1)) {
3031 /* Little-endian mode is not handled */
3032 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3033 return;
3034 }
a7812ae4 3035 EA = tcg_temp_new();
a7859e89 3036 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3037 gen_addr_imm_index(EA, ctx, 0x03);
3038 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3039 tcg_gen_addi_tl(EA, EA, 8);
3040 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3041 tcg_temp_free(EA);
be147d08
JM		 3042#endif
3043 } else {
3044 /* std / stdu */
3045 if (Rc(ctx->opcode)) {
3046 if (unlikely(rA(ctx->opcode) == 0)) {
3047 GEN_EXCP_INVAL(ctx);
3048 return;
3049 }
3050 }
a7812ae4 3051 EA = tcg_temp_new();
a7859e89 3052 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3053 gen_addr_imm_index(EA, ctx, 0x03);
3054 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 3055 if (Rc(ctx->opcode))
b61f2753
AJ		 3056 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3057 tcg_temp_free(EA);
d9bce9d9 3058 }
d9bce9d9
JM		 3059}
3060#endif
79aceca5
FB		 3061/*** Integer load and store with byte reverse ***/
3062/* lhbrx */
b61f2753
AJ		 3063void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3064{
a7812ae4
PB		 3065 TCGv_i32 temp = tcg_temp_new_i32();
3066 gen_qemu_ld16u(t0, t1, flags);
3067 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3068 tcg_gen_bswap16_i32(temp, temp);
3069 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3070 tcg_temp_free_i32(temp);
b61f2753 3071}
0c8aacd4 3072GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3073
79aceca5 3074/* lwbrx */
b61f2753
AJ		 3075void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3076{
a7812ae4
PB		 3077 TCGv_i32 temp = tcg_temp_new_i32();
3078 gen_qemu_ld32u(t0, t1, flags);
3079 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3080 tcg_gen_bswap_i32(temp, temp);
3081 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3082 tcg_temp_free_i32(temp);
b61f2753 3083}
0c8aacd4 3084GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3085
79aceca5 3086/* sthbrx */
b61f2753
AJ		 3087void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3088{
a7812ae4
PB		 3089 TCGv_i32 temp = tcg_temp_new_i32();
3090 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3091 tcg_gen_trunc_tl_i32(temp, t0);
3092 tcg_gen_ext16u_i32(temp, temp);
3093 tcg_gen_bswap16_i32(temp, temp);
a7812ae4
PB		 3094 tcg_gen_extu_i32_tl(t2, temp);
3095 tcg_temp_free_i32(temp);
3096 gen_qemu_st16(t2, t1, flags);
3097 tcg_temp_free(t2);
b61f2753 3098}
0c8aacd4 3099GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3100
79aceca5 3101/* stwbrx */
b61f2753
AJ		 3102void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3103{
a7812ae4
PB		 3104 TCGv_i32 temp = tcg_temp_new_i32();
3105 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3106 tcg_gen_trunc_tl_i32(temp, t0);
3107 tcg_gen_bswap_i32(temp, temp);
a7812ae4
PB		 3108 tcg_gen_extu_i32_tl(t2, temp);
3109 tcg_temp_free_i32(temp);
87006d13 3110 gen_qemu_st32(t2, t1, flags);
a7812ae4 3111 tcg_temp_free(t2);
b61f2753 3112}
0c8aacd4 3113GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3114
3115/*** Integer load and store multiple ***/
3116/* lmw */
3117GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3118{
ff4a62cd
AJ		 3119 TCGv t0 = tcg_temp_new();
3120 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
76a66253 3121 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3122 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3123 gen_addr_imm_index(t0, ctx, 0);
3124 gen_helper_lmw(t0, t1);
3125 tcg_temp_free(t0);
3126 tcg_temp_free_i32(t1);
79aceca5
FB		 3127}
3128
3129/* stmw */
3130GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3131{
ff4a62cd
AJ		 3132 TCGv t0 = tcg_temp_new();
3133 TCGv_i32 t1 = tcg_const_i32(rS(ctx->opcode));
76a66253 3134 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3135 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3136 gen_addr_imm_index(t0, ctx, 0);
3137 gen_helper_stmw(t0, t1);
3138 tcg_temp_free(t0);
3139 tcg_temp_free_i32(t1);
79aceca5
FB		 3140}
3141
3142/*** Integer load and store strings ***/
3143/* lswi */
3fc6c082 3144/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3145 * rA is in the range of registers to be loaded.
3146 * In an other hand, IBM says this is valid, but rA won't be loaded.
3147 * For now, I'll follow the spec...
3148 */
05332d70 3149GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3150{
dfbc799d
AJ		 3151 TCGv t0;
3152 TCGv_i32 t1, t2;
79aceca5
FB		 3153 int nb = NB(ctx->opcode);
3154 int start = rD(ctx->opcode);
9a64fbe4 3155 int ra = rA(ctx->opcode);
79aceca5
FB		 3156 int nr;
3157
3158 if (nb == 0)
3159 nb = 32;
3160 nr = nb / 4;
76a66253
JM		 3161 if (unlikely(((start + nr) > 32 &&
3162 start <= ra && (start + nr - 32) > ra) ||
3163 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3164 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3165 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3166 return;
297d8e62 3167 }
8dd4983c 3168 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3169 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3170 t0 = tcg_temp_new();
3171 gen_addr_register(t0, ctx);
3172 t1 = tcg_const_i32(nb);
3173 t2 = tcg_const_i32(start);
3174 gen_helper_lsw(t0, t1, t2);
3175 tcg_temp_free(t0);
3176 tcg_temp_free_i32(t1);
3177 tcg_temp_free_i32(t2);
79aceca5
FB		 3178}
3179
3180/* lswx */
05332d70 3181GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3182{
dfbc799d
AJ		 3183 TCGv t0 = tcg_temp_new();
3184 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
3185 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
3186 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 3187 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3188 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3189 gen_addr_reg_index(t0, ctx);
3190 gen_helper_lswx(t0, t1, t2, t3);
3191 tcg_temp_free(t0);
3192 tcg_temp_free_i32(t1);
3193 tcg_temp_free_i32(t2);
3194 tcg_temp_free_i32(t3);
79aceca5
FB		 3195}
3196
3197/* stswi */
05332d70 3198GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3199{
4b3686fa 3200 int nb = NB(ctx->opcode);
dfbc799d
AJ		 3201 TCGv t0 = tcg_temp_new();
3202 TCGv_i32 t1;
3203 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
76a66253 3204 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3205 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3206 gen_addr_register(t0, ctx);
4b3686fa
FB		 3207 if (nb == 0)
3208 nb = 32;
dfbc799d
AJ		 3209 t1 = tcg_const_i32(nb);
3210 gen_helper_stsw(t0, t1, t2);
3211 tcg_temp_free(t0);
3212 tcg_temp_free_i32(t1);
3213 tcg_temp_free_i32(t2);
79aceca5
FB		 3214}
3215
3216/* stswx */
05332d70 3217GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3218{
dfbc799d
AJ		 3219 TCGv t0 = tcg_temp_new();
3220 TCGv_i32 t1 = tcg_temp_new_i32();
3221 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
8dd4983c 3222 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3223 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3224 gen_addr_reg_index(t0, ctx);
3225 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3226 tcg_gen_andi_i32(t1, t1, 0x7F);
3227 gen_helper_stsw(t0, t1, t2);
3228 tcg_temp_free(t0);
3229 tcg_temp_free_i32(t1);
3230 tcg_temp_free_i32(t2);
79aceca5
FB		 3231}
3232
3233/*** Memory synchronisation ***/
3234/* eieio */
0db1b20e 3235GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3236{
79aceca5
FB		 3237}
3238
3239/* isync */
0db1b20e 3240GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3241{
e1833e1f 3242 GEN_STOP(ctx);
79aceca5
FB		 3243}
3244
111bfab3 3245/* lwarx */
76a66253 3246GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3247{
cf360a32 3248 TCGv t0 = tcg_temp_local_new();
a7859e89 3249 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3250 gen_addr_reg_index(t0, ctx);
3251 gen_check_align(ctx, t0, 0x03);
3252#if defined(TARGET_PPC64)
3253 if (!ctx->sf_mode)
3254 tcg_gen_ext32u_tl(t0, t0);
3255#endif
3256 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3257 tcg_gen_mov_tl(cpu_reserve, t0);
3258 tcg_temp_free(t0);
79aceca5
FB		 3259}
3260
3261/* stwcx. */
c7697e1f 3262GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3263{
cf360a32
AJ		 3264 int l1 = gen_new_label();
3265 TCGv t0 = tcg_temp_local_new();
a7859e89 3266 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3267 gen_addr_reg_index(t0, ctx);
3268 gen_check_align(ctx, t0, 0x03);
3269#if defined(TARGET_PPC64)
3270 if (!ctx->sf_mode)
3271 tcg_gen_ext32u_tl(t0, t0);
3272#endif
3273 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3274 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3275 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3276 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3277 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3278 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3279 gen_set_label(l1);
3280 tcg_gen_movi_tl(cpu_reserve, -1);
3281 tcg_temp_free(t0);
79aceca5
FB		 3282}
3283
426613db 3284#if defined(TARGET_PPC64)
426613db 3285/* ldarx */
a750fc0b 3286GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3287{
cf360a32 3288 TCGv t0 = tcg_temp_local_new();
a7859e89 3289 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3290 gen_addr_reg_index(t0, ctx);
3291 gen_check_align(ctx, t0, 0x07);
3292 if (!ctx->sf_mode)
3293 tcg_gen_ext32u_tl(t0, t0);
3294 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3295 tcg_gen_mov_tl(cpu_reserve, t0);
3296 tcg_temp_free(t0);
426613db
JM		 3297}
3298
3299/* stdcx. */
c7697e1f 3300GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3301{
cf360a32
AJ		 3302 int l1 = gen_new_label();
3303 TCGv t0 = tcg_temp_local_new();
a7859e89 3304 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3305 gen_addr_reg_index(t0, ctx);
3306 gen_check_align(ctx, t0, 0x07);
3307 if (!ctx->sf_mode)
3308 tcg_gen_ext32u_tl(t0, t0);
3309 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3310 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3311 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3312 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3313 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3314 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3315 gen_set_label(l1);
3316 tcg_gen_movi_tl(cpu_reserve, -1);
3317 tcg_temp_free(t0);
426613db
JM		 3318}
3319#endif /* defined(TARGET_PPC64) */
3320
79aceca5 3321/* sync */
a902d886 3322GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3323{
79aceca5
FB		 3324}
3325
0db1b20e
JM		 3326/* wait */
3327GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3328{
931ff272
AJ		 3329 TCGv_i32 t0 = tcg_temp_new_i32();
3330 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3331 tcg_temp_free_i32(t0);
0db1b20e 3332 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08 3333 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3334}
3335
79aceca5 3336/*** Floating-point load ***/
a0d7d5a7
AJ		 3337#define GEN_LDF(name, ldop, opc, type) \
3338GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3339{ \
a0d7d5a7 3340 TCGv EA; \
76a66253 3341 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3342 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3343 return; \
3344 } \
a7859e89 3345 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3346 EA = tcg_temp_new(); \
3347 gen_addr_imm_index(EA, ctx, 0); \
3348 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3349 tcg_temp_free(EA); \
79aceca5
FB		 3350}
3351
a0d7d5a7
AJ		 3352#define GEN_LDUF(name, ldop, opc, type) \
3353GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3354{ \
a0d7d5a7 3355 TCGv EA; \
76a66253 3356 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3357 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3358 return; \
3359 } \
76a66253 3360 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3361 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3362 return; \
9a64fbe4 3363 } \
a7859e89 3364 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3365 EA = tcg_temp_new(); \
3366 gen_addr_imm_index(EA, ctx, 0); \
3367 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3368 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3369 tcg_temp_free(EA); \
79aceca5
FB		 3370}
3371
a0d7d5a7
AJ		 3372#define GEN_LDUXF(name, ldop, opc, type) \
3373GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3374{ \
a0d7d5a7 3375 TCGv EA; \
76a66253 3376 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3377 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3378 return; \
3379 } \
76a66253 3380 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3381 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3382 return; \
9a64fbe4 3383 } \
a7859e89 3384 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3385 EA = tcg_temp_new(); \
3386 gen_addr_reg_index(EA, ctx); \
3387 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3388 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3389 tcg_temp_free(EA); \
79aceca5
FB		 3390}
3391
a0d7d5a7
AJ		 3392#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3393GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3394{ \
a0d7d5a7 3395 TCGv EA; \
76a66253 3396 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3397 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3398 return; \
3399 } \
a7859e89 3400 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3401 EA = tcg_temp_new(); \
3402 gen_addr_reg_index(EA, ctx); \
3403 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3404 tcg_temp_free(EA); \
79aceca5
FB		 3405}
3406
a0d7d5a7
AJ		 3407#define GEN_LDFS(name, ldop, op, type) \
3408GEN_LDF(name, ldop, op | 0x20, type); \
3409GEN_LDUF(name, ldop, op | 0x21, type); \
3410GEN_LDUXF(name, ldop, op | 0x01, type); \
3411GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3412
3413static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3414{
3415 TCGv t0 = tcg_temp_new();
3416 TCGv_i32 t1 = tcg_temp_new_i32();
3417 gen_qemu_ld32u(t0, arg2, flags);
3418 tcg_gen_trunc_tl_i32(t1, t0);
3419 tcg_temp_free(t0);
3420 gen_helper_float32_to_float64(arg1, t1);
3421 tcg_temp_free_i32(t1);
3422}
79aceca5 3423
a0d7d5a7
AJ		 3424 /* lfd lfdu lfdux lfdx */
3425GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3426 /* lfs lfsu lfsux lfsx */
3427GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3428
3429/*** Floating-point store ***/
a0d7d5a7
AJ		 3430#define GEN_STF(name, stop, opc, type) \
3431GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3432{ \
a0d7d5a7 3433 TCGv EA; \
76a66253 3434 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3435 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3436 return; \
3437 } \
a7859e89 3438 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3439 EA = tcg_temp_new(); \
3440 gen_addr_imm_index(EA, ctx, 0); \
3441 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3442 tcg_temp_free(EA); \
79aceca5
FB		 3443}
3444
a0d7d5a7
AJ		 3445#define GEN_STUF(name, stop, opc, type) \
3446GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3447{ \
a0d7d5a7 3448 TCGv EA; \
76a66253 3449 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3450 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3451 return; \
3452 } \
76a66253 3453 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3454 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3455 return; \
9a64fbe4 3456 } \
a7859e89 3457 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3458 EA = tcg_temp_new(); \
3459 gen_addr_imm_index(EA, ctx, 0); \
3460 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3461 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3462 tcg_temp_free(EA); \
79aceca5
FB		 3463}
3464
a0d7d5a7
AJ		 3465#define GEN_STUXF(name, stop, opc, type) \
3466GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3467{ \
a0d7d5a7 3468 TCGv EA; \
76a66253 3469 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3470 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3471 return; \
3472 } \
76a66253 3473 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3474 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3475 return; \
9a64fbe4 3476 } \
a7859e89 3477 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3478 EA = tcg_temp_new(); \
3479 gen_addr_reg_index(EA, ctx); \
3480 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3481 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3482 tcg_temp_free(EA); \
79aceca5
FB		 3483}
3484
a0d7d5a7
AJ		 3485#define GEN_STXF(name, stop, opc2, opc3, type) \
3486GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3487{ \
a0d7d5a7 3488 TCGv EA; \
76a66253 3489 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3490 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3491 return; \
3492 } \
a7859e89 3493 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3494 EA = tcg_temp_new(); \
3495 gen_addr_reg_index(EA, ctx); \
3496 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3497 tcg_temp_free(EA); \
79aceca5
FB		 3498}
3499
a0d7d5a7
AJ		 3500#define GEN_STFS(name, stop, op, type) \
3501GEN_STF(name, stop, op | 0x20, type); \
3502GEN_STUF(name, stop, op | 0x21, type); \
3503GEN_STUXF(name, stop, op | 0x01, type); \
3504GEN_STXF(name, stop, 0x17, op | 0x00, type)
3505
3506static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3507{
3508 TCGv_i32 t0 = tcg_temp_new_i32();
3509 TCGv t1 = tcg_temp_new();
3510 gen_helper_float64_to_float32(t0, arg1);
3511 tcg_gen_extu_i32_tl(t1, t0);
3512 tcg_temp_free_i32(t0);
3513 gen_qemu_st32(t1, arg2, flags);
3514 tcg_temp_free(t1);
3515}
79aceca5
FB		 3516
3517/* stfd stfdu stfdux stfdx */
a0d7d5a7 3518GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3519/* stfs stfsu stfsux stfsx */
a0d7d5a7 3520GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3521
3522/* Optional: */
a0d7d5a7
AJ		 3523static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags)
3524{
3525 TCGv t0 = tcg_temp_new();
3526 tcg_gen_trunc_i64_tl(t0, arg1),
3527 gen_qemu_st32(t0, arg2, flags);
3528 tcg_temp_free(t0);
3529}
79aceca5 3530/* stfiwx */
a0d7d5a7 3531GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3532
3533/*** Branch ***/
b068d6a7
JM		 3534static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3535 target_ulong dest)
c1942362
FB		 3536{
3537 TranslationBlock *tb;
3538 tb = ctx->tb;
a2ffb812
AJ		 3539#if defined(TARGET_PPC64)
3540 if (!ctx->sf_mode)
3541 dest = (uint32_t) dest;
3542#endif
57fec1fe 3543 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3544 likely(!ctx->singlestep_enabled)) {
57fec1fe 3545 tcg_gen_goto_tb(n);
a2ffb812 3546 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3547 tcg_gen_exit_tb((long)tb + n);
c1942362 3548 } else {
a2ffb812 3549 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3550 if (unlikely(ctx->singlestep_enabled)) {
3551 if ((ctx->singlestep_enabled &
bdc4e053 3552 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3553 ctx->exception == POWERPC_EXCP_BRANCH) {
3554 target_ulong tmp = ctx->nip;
3555 ctx->nip = dest;
3556 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3557 ctx->nip = tmp;
3558 }
3559 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3560 gen_update_nip(ctx, dest);
64adab3f 3561 gen_helper_raise_debug();
8cbcb4fa
AJ		 3562 }
3563 }
57fec1fe 3564 tcg_gen_exit_tb(0);
c1942362 3565 }
c53be334
FB		 3566}
3567
b068d6a7 3568static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3569{
3570#if defined(TARGET_PPC64)
a2ffb812
AJ		 3571 if (ctx->sf_mode == 0)
3572 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3573 else
3574#endif
a2ffb812 3575 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3576}
3577
79aceca5
FB		 3578/* b ba bl bla */
3579GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3580{
76a66253 3581 target_ulong li, target;
38a64f9d 3582
8cbcb4fa 3583 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3584 /* sign extend LI */
76a66253 3585#if defined(TARGET_PPC64)
d9bce9d9
JM		 3586 if (ctx->sf_mode)
3587 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3588 else
76a66253 3589#endif
d9bce9d9 3590 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3591 if (likely(AA(ctx->opcode) == 0))
046d6672 3592 target = ctx->nip + li - 4;
79aceca5 3593 else
9a64fbe4 3594 target = li;
e1833e1f
JM		 3595 if (LK(ctx->opcode))
3596 gen_setlr(ctx, ctx->nip);
c1942362 3597 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3598}
3599
e98a6e40
FB		 3600#define BCOND_IM 0
3601#define BCOND_LR 1
3602#define BCOND_CTR 2
3603
b068d6a7 3604static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3605{
d9bce9d9 3606 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3607 int l1 = gen_new_label();
3608 TCGv target;
e98a6e40 3609
8cbcb4fa 3610 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3611 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3612 target = tcg_temp_local_new();
a2ffb812
AJ		 3613 if (type == BCOND_CTR)
3614 tcg_gen_mov_tl(target, cpu_ctr);
3615 else
3616 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3617 }
e1833e1f
JM		 3618 if (LK(ctx->opcode))
3619 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3620 l1 = gen_new_label();
3621 if ((bo & 0x4) == 0) {
3622 /* Decrement and test CTR */
a7812ae4 3623 TCGv temp = tcg_temp_new();
a2ffb812
AJ		 3624 if (unlikely(type == BCOND_CTR)) {
3625 GEN_EXCP_INVAL(ctx);
3626 return;
3627 }
3628 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3629#if defined(TARGET_PPC64)
a2ffb812
AJ		 3630 if (!ctx->sf_mode)
3631 tcg_gen_ext32u_tl(temp, cpu_ctr);
3632 else
d9bce9d9 3633#endif
a2ffb812
AJ		 3634 tcg_gen_mov_tl(temp, cpu_ctr);
3635 if (bo & 0x2) {
3636 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3637 } else {
3638 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3639 }
a7812ae4 3640 tcg_temp_free(temp);
a2ffb812
AJ		 3641 }
3642 if ((bo & 0x10) == 0) {
3643 /* Test CR */
3644 uint32_t bi = BI(ctx->opcode);
3645 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3646 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3647
d9bce9d9 3648 if (bo & 0x8) {
a2ffb812
AJ		 3649 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3650 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3651 } else {
a2ffb812
AJ		 3652 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3653 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3654 }
a7812ae4 3655 tcg_temp_free_i32(temp);
d9bce9d9 3656 }
e98a6e40 3657 if (type == BCOND_IM) {
a2ffb812
AJ		 3658 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3659 if (likely(AA(ctx->opcode) == 0)) {
3660 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3661 } else {
3662 gen_goto_tb(ctx, 0, li);
3663 }
c53be334 3664 gen_set_label(l1);
c1942362 3665 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3666 } else {
d9bce9d9 3667#if defined(TARGET_PPC64)
a2ffb812
AJ		 3668 if (!(ctx->sf_mode))
3669 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3670 else
3671#endif
3672 tcg_gen_andi_tl(cpu_nip, target, ~3);
3673 tcg_gen_exit_tb(0);
3674 gen_set_label(l1);
3675#if defined(TARGET_PPC64)
3676 if (!(ctx->sf_mode))
3677 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3678 else
3679#endif
a2ffb812 3680 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3681 tcg_gen_exit_tb(0);
08e46e54 3682 }
e98a6e40
FB		 3683}
3684
3685GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3686{
e98a6e40
FB		 3687 gen_bcond(ctx, BCOND_IM);
3688}
3689
3690GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3691{
e98a6e40
FB		 3692 gen_bcond(ctx, BCOND_CTR);
3693}
3694
3695GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3696{
e98a6e40
FB		 3697 gen_bcond(ctx, BCOND_LR);
3698}
79aceca5
FB		 3699
3700/*** Condition register logical ***/
e1571908
AJ		 3701#define GEN_CRLOGIC(name, tcg_op, opc) \
3702GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3703{ \
fc0d441e
JM		 3704 uint8_t bitmask; \
3705 int sh; \
a7812ae4 3706 TCGv_i32 t0, t1; \
fc0d441e 3707 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3708 t0 = tcg_temp_new_i32(); \
fc0d441e 3709 if (sh > 0) \
fea0c503 3710 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3711 else if (sh < 0) \
fea0c503 3712 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3713 else \
fea0c503 3714 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3715 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3716 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3717 if (sh > 0) \
fea0c503 3718 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3719 else if (sh < 0) \
fea0c503 3720 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3721 else \
fea0c503
AJ		 3722 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3723 tcg_op(t0, t0, t1); \
fc0d441e 3724 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3725 tcg_gen_andi_i32(t0, t0, bitmask); \
3726 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3727 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3728 tcg_temp_free_i32(t0); \
3729 tcg_temp_free_i32(t1); \
79aceca5
FB		 3730}
3731
3732/* crand */
e1571908 3733GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3734/* crandc */
e1571908 3735GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3736/* creqv */
e1571908 3737GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3738/* crnand */
e1571908 3739GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3740/* crnor */
e1571908 3741GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3742/* cror */
e1571908 3743GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3744/* crorc */
e1571908 3745GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3746/* crxor */
e1571908 3747GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3748/* mcrf */
3749GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3750{
47e4661c 3751 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3752}
3753
3754/*** System linkage ***/
3755/* rfi (supervisor only) */
76a66253 3756GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3757{
9a64fbe4 3758#if defined(CONFIG_USER_ONLY)
e1833e1f 3759 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3760#else
3761 /* Restore CPU state */
76a66253 3762 if (unlikely(!ctx->supervisor)) {
e1833e1f 3763 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3764 return;
9a64fbe4 3765 }
a42bd6cc 3766 gen_op_rfi();
e1833e1f 3767 GEN_SYNC(ctx);
9a64fbe4 3768#endif
79aceca5
FB		 3769}
3770
426613db 3771#if defined(TARGET_PPC64)
a750fc0b 3772GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3773{
3774#if defined(CONFIG_USER_ONLY)
e1833e1f 3775 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3776#else
3777 /* Restore CPU state */
3778 if (unlikely(!ctx->supervisor)) {
e1833e1f 3779 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3780 return;
3781 }
a42bd6cc 3782 gen_op_rfid();
e1833e1f 3783 GEN_SYNC(ctx);
426613db
JM		 3784#endif
3785}
426613db 3786
5b8105fa 3787GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3788{
3789#if defined(CONFIG_USER_ONLY)
3790 GEN_EXCP_PRIVOPC(ctx);
3791#else
3792 /* Restore CPU state */
3793 if (unlikely(ctx->supervisor <= 1)) {
3794 GEN_EXCP_PRIVOPC(ctx);
3795 return;
3796 }
3797 gen_op_hrfid();
3798 GEN_SYNC(ctx);
3799#endif
3800}
3801#endif
3802
79aceca5 3803/* sc */
417bf010
JM		 3804#if defined(CONFIG_USER_ONLY)
3805#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3806#else
3807#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3808#endif
e1833e1f 3809GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3810{
e1833e1f
JM		 3811 uint32_t lev;
3812
3813 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3814 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3815}
3816
3817/*** Trap ***/
3818/* tw */
76a66253 3819GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3820{
cab3bee2 3821 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3822 /* Update the nip since this might generate a trap exception */
d9bce9d9 3823 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3824 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3825 tcg_temp_free_i32(t0);
79aceca5
FB		 3826}
3827
3828/* twi */
3829GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3830{
cab3bee2
AJ		 3831 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3832 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3833 /* Update the nip since this might generate a trap exception */
3834 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3835 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3836 tcg_temp_free(t0);
3837 tcg_temp_free_i32(t1);
79aceca5
FB		 3838}
3839
d9bce9d9
JM		 3840#if defined(TARGET_PPC64)
3841/* td */
3842GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3843{
cab3bee2 3844 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3845 /* Update the nip since this might generate a trap exception */
3846 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3847 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3848 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3849}
3850
3851/* tdi */
3852GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3853{
cab3bee2
AJ		 3854 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3855 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3856 /* Update the nip since this might generate a trap exception */
3857 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3858 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3859 tcg_temp_free(t0);
3860 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3861}
3862#endif
3863
79aceca5 3864/*** Processor control ***/
79aceca5
FB		 3865/* mcrxr */
3866GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3867{
3d7b417e
AJ		 3868 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3869 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3870 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3871}
3872
3873/* mfcr */
76a66253 3874GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3875{
76a66253 3876 uint32_t crm, crn;
3b46e624 3877
76a66253
JM		 3878 if (likely(ctx->opcode & 0x00100000)) {
3879 crm = CRM(ctx->opcode);
3880 if (likely((crm ^ (crm - 1)) == 0)) {
3881 crn = ffs(crm);
e1571908 3882 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3883 }
d9bce9d9 3884 } else {
a7812ae4 3885 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3886 }
79aceca5
FB		 3887}
3888
3889/* mfmsr */
3890GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3891{
9a64fbe4 3892#if defined(CONFIG_USER_ONLY)
e1833e1f 3893 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3894#else
76a66253 3895 if (unlikely(!ctx->supervisor)) {
e1833e1f 3896 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3897 return;
9a64fbe4 3898 }
6676f424 3899 gen_op_load_msr();
f78fb44e 3900 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3901#endif
79aceca5
FB		 3902}
3903
a11b8151 3904#if 1
6f2d8978 3905#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3906#else
3907static void spr_noaccess (void *opaque, int sprn)
3908{
3909 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3910 printf("ERROR: try to access SPR %d !\n", sprn);
3911}
3912#define SPR_NOACCESS (&spr_noaccess)
3913#endif
3914
79aceca5 3915/* mfspr */
b068d6a7 3916static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3917{
3fc6c082 3918 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3919 uint32_t sprn = SPR(ctx->opcode);
3920
3fc6c082 3921#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3922 if (ctx->supervisor == 2)
3923 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3924 else if (ctx->supervisor)
3fc6c082
FB		 3925 read_cb = ctx->spr_cb[sprn].oea_read;
3926 else
9a64fbe4 3927#endif
3fc6c082 3928 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3929 if (likely(read_cb != NULL)) {
3930 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3931 (*read_cb)(ctx, sprn);
f78fb44e 3932 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3933 } else {
3934 /* Privilege exception */
9fceefa7
JM		 3935 /* This is a hack to avoid warnings when running Linux:
3936 * this OS breaks the PowerPC virtualisation model,
3937 * allowing userland application to read the PVR
3938 */
3939 if (sprn != SPR_PVR) {
3940 if (loglevel != 0) {
6b542af7 3941 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3942 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3943 }
077fc206
JM		 3944 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3945 sprn, sprn, ctx->nip);
f24e5695 3946 }
e1833e1f 3947 GEN_EXCP_PRIVREG(ctx);
79aceca5 3948 }
3fc6c082
FB		 3949 } else {
3950 /* Not defined */
4a057712 3951 if (loglevel != 0) {
077fc206
JM		 3952 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3953 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3954 }
077fc206
JM		 3955 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3956 sprn, sprn, ctx->nip);
e1833e1f
JM		 3957 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3958 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3959 }
79aceca5
FB		 3960}
3961
3fc6c082 3962GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3963{
3fc6c082 3964 gen_op_mfspr(ctx);
76a66253 3965}
3fc6c082
FB		 3966
3967/* mftb */
a750fc0b 3968GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3969{
3970 gen_op_mfspr(ctx);
79aceca5
FB		 3971}
3972
3973/* mtcrf */
8dd4983c 3974GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3975{
76a66253 3976 uint32_t crm, crn;
3b46e624 3977
76a66253
JM		 3978 crm = CRM(ctx->opcode);
3979 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3980 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3981 crn = ffs(crm);
a7812ae4
PB		 3982 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3983 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3984 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3985 tcg_temp_free_i32(temp);
76a66253 3986 } else {
a7812ae4
PB		 3987 TCGv_i32 temp = tcg_const_i32(crm);
3988 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3989 tcg_temp_free_i32(temp);
76a66253 3990 }
79aceca5
FB		 3991}
3992
3993/* mtmsr */
426613db 3994#if defined(TARGET_PPC64)
be147d08 3995GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3996{
3997#if defined(CONFIG_USER_ONLY)
e1833e1f 3998 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3999#else
4000 if (unlikely(!ctx->supervisor)) {
e1833e1f 4001 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 4002 return;
4003 }
f78fb44e 4004 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4005 if (ctx->opcode & 0x00010000) {
4006 /* Special form that does not need any synchronisation */
4007 gen_op_update_riee();
4008 } else {
056b05f8
JM		 4009 /* XXX: we need to update nip before the store
4010 * if we enter power saving mode, we will exit the loop
4011 * directly from ppc_store_msr
4012 */
be147d08 4013 gen_update_nip(ctx, ctx->nip);
6676f424 4014 gen_op_store_msr();
be147d08
JM		 4015 /* Must stop the translation as machine state (may have) changed */
4016 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 4017 ctx->exception = POWERPC_EXCP_STOP;
be147d08 4018 }
426613db
JM		 4019#endif
4020}
4021#endif
4022
79aceca5
FB		 4023GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
4024{
9a64fbe4 4025#if defined(CONFIG_USER_ONLY)
e1833e1f 4026 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4027#else
76a66253 4028 if (unlikely(!ctx->supervisor)) {
e1833e1f 4029 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4030 return;
9a64fbe4 4031 }
f78fb44e 4032 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4033 if (ctx->opcode & 0x00010000) {
4034 /* Special form that does not need any synchronisation */
4035 gen_op_update_riee();
4036 } else {
056b05f8
JM		 4037 /* XXX: we need to update nip before the store
4038 * if we enter power saving mode, we will exit the loop
4039 * directly from ppc_store_msr
4040 */
be147d08 4041 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4042#if defined(TARGET_PPC64)
be147d08 4043 if (!ctx->sf_mode)
6676f424 4044 gen_op_store_msr_32();
be147d08 4045 else
d9bce9d9 4046#endif
6676f424 4047 gen_op_store_msr();
be147d08
JM		 4048 /* Must stop the translation as machine state (may have) changed */
4049 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 4050 ctx->exception = POWERPC_EXCP_STOP;
be147d08 4051 }
9a64fbe4 4052#endif
79aceca5
FB		 4053}
4054
4055/* mtspr */
4056GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4057{
3fc6c082 4058 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 4059 uint32_t sprn = SPR(ctx->opcode);
4060
3fc6c082 4061#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 4062 if (ctx->supervisor == 2)
4063 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 4064 else if (ctx->supervisor)
3fc6c082
FB		 4065 write_cb = ctx->spr_cb[sprn].oea_write;
4066 else
9a64fbe4 4067#endif
3fc6c082 4068 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4069 if (likely(write_cb != NULL)) {
4070 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 4071 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 4072 (*write_cb)(ctx, sprn);
4073 } else {
4074 /* Privilege exception */
4a057712 4075 if (loglevel != 0) {
077fc206
JM		 4076 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4077 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4078 }
077fc206
JM		 4079 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4080 sprn, sprn, ctx->nip);
e1833e1f 4081 GEN_EXCP_PRIVREG(ctx);
76a66253 4082 }
3fc6c082
FB		 4083 } else {
4084 /* Not defined */
4a057712 4085 if (loglevel != 0) {
077fc206
JM		 4086 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4087 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4088 }
077fc206
JM		 4089 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4090 sprn, sprn, ctx->nip);
e1833e1f
JM		 4091 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4092 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 4093 }
79aceca5
FB		 4094}
4095
4096/*** Cache management ***/
79aceca5 4097/* dcbf */
0db1b20e 4098GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4099{
dac454af 4100 /* XXX: specification says this is treated as a load by the MMU */
a7812ae4 4101 TCGv t0 = tcg_temp_new();
a7859e89 4102 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4103 gen_addr_reg_index(t0, ctx);
4104 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4105 tcg_temp_free(t0);
79aceca5
FB		 4106}
4107
4108/* dcbi (Supervisor only) */
9a64fbe4 4109GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4110{
a541f297 4111#if defined(CONFIG_USER_ONLY)
e1833e1f 4112 GEN_EXCP_PRIVOPC(ctx);
a541f297 4113#else
b61f2753 4114 TCGv EA, val;
76a66253 4115 if (unlikely(!ctx->supervisor)) {
e1833e1f 4116 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4117 return;
9a64fbe4 4118 }
a7812ae4 4119 EA = tcg_temp_new();
a7859e89 4120 gen_set_access_type(ACCESS_CACHE);
b61f2753 4121 gen_addr_reg_index(EA, ctx);
a7812ae4 4122 val = tcg_temp_new();
76a66253 4123 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 4124 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4125 gen_qemu_st8(val, EA, ctx->mem_idx);
4126 tcg_temp_free(val);
4127 tcg_temp_free(EA);
a541f297 4128#endif
79aceca5
FB		 4129}
4130
4131/* dcdst */
9a64fbe4 4132GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4133{
76a66253 4134 /* XXX: specification say this is treated as a load by the MMU */
a7812ae4 4135 TCGv t0 = tcg_temp_new();
a7859e89 4136 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4137 gen_addr_reg_index(t0, ctx);
4138 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4139 tcg_temp_free(t0);
79aceca5
FB		 4140}
4141
4142/* dcbt */
0db1b20e 4143GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4144{
0db1b20e 4145 /* interpreted as no-op */
76a66253
JM		 4146 /* XXX: specification say this is treated as a load by the MMU
4147 * but does not generate any exception
4148 */
79aceca5
FB		 4149}
4150
4151/* dcbtst */
0db1b20e 4152GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4153{
0db1b20e 4154 /* interpreted as no-op */
76a66253
JM		 4155 /* XXX: specification say this is treated as a load by the MMU
4156 * but does not generate any exception
4157 */
79aceca5
FB		 4158}
4159
4160/* dcbz */
d63001d1 4161GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4162{
799a8c8d
AJ		 4163 TCGv t0 = tcg_temp_new();
4164 gen_addr_reg_index(t0, ctx);
4165 /* NIP cannot be restored if the memory exception comes from an helper */
4166 gen_update_nip(ctx, ctx->nip - 4);
4167 gen_helper_dcbz(t0);
4168 tcg_temp_free(t0);
d63001d1
JM		 4169}
4170
c7697e1f 4171GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4172{
799a8c8d
AJ		 4173 TCGv t0 = tcg_temp_new();
4174 gen_addr_reg_index(t0, ctx);
4175 /* NIP cannot be restored if the memory exception comes from an helper */
4176 gen_update_nip(ctx, ctx->nip - 4);
d63001d1 4177 if (ctx->opcode & 0x00200000)
799a8c8d 4178 gen_helper_dcbz(t0);
d63001d1 4179 else
799a8c8d
AJ		 4180 gen_helper_dcbz_970(t0);
4181 tcg_temp_free(t0);
79aceca5
FB		 4182}
4183
4184/* icbi */
1b413d55 4185GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4186{
37d269df 4187 TCGv t0 = tcg_temp_new();
30032c94
JM		 4188 /* NIP cannot be restored if the memory exception comes from an helper */
4189 gen_update_nip(ctx, ctx->nip - 4);
37d269df
AJ		 4190 gen_addr_reg_index(t0, ctx);
4191 gen_helper_icbi(t0);
4192 tcg_temp_free(t0);
79aceca5
FB		 4193}
4194
4195/* Optional: */
4196/* dcba */
a750fc0b 4197GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4198{
0db1b20e
JM		 4199 /* interpreted as no-op */
4200 /* XXX: specification say this is treated as a store by the MMU
4201 * but does not generate any exception
4202 */
79aceca5
FB		 4203}
4204
4205/*** Segment register manipulation ***/
4206/* Supervisor only: */
4207/* mfsr */
4208GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4209{
9a64fbe4 4210#if defined(CONFIG_USER_ONLY)
e1833e1f 4211 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4212#else
76a66253 4213 if (unlikely(!ctx->supervisor)) {
e1833e1f 4214 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4215 return;
9a64fbe4 4216 }
86c581dc 4217 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4218 gen_op_load_sr();
f78fb44e 4219 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4220#endif
79aceca5
FB		 4221}
4222
4223/* mfsrin */
9a64fbe4 4224GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4225{
9a64fbe4 4226#if defined(CONFIG_USER_ONLY)
e1833e1f 4227 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4228#else
76a66253 4229 if (unlikely(!ctx->supervisor)) {
e1833e1f 4230 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4231 return;
9a64fbe4 4232 }
f78fb44e 4233 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4234 gen_op_srli_T1(28);
4235 gen_op_load_sr();
f78fb44e 4236 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4237#endif
79aceca5
FB		 4238}
4239
4240/* mtsr */
e63c59cb 4241GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4242{
9a64fbe4 4243#if defined(CONFIG_USER_ONLY)
e1833e1f 4244 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4245#else
76a66253 4246 if (unlikely(!ctx->supervisor)) {
e1833e1f 4247 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4248 return;
9a64fbe4 4249 }
f78fb44e 4250 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4251 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4252 gen_op_store_sr();
9a64fbe4 4253#endif
79aceca5
FB		 4254}
4255
4256/* mtsrin */
9a64fbe4 4257GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4258{
9a64fbe4 4259#if defined(CONFIG_USER_ONLY)
e1833e1f 4260 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4261#else
76a66253 4262 if (unlikely(!ctx->supervisor)) {
e1833e1f 4263 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4264 return;
9a64fbe4 4265 }
f78fb44e
AJ		 4266 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4267 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4268 gen_op_srli_T1(28);
4269 gen_op_store_sr();
9a64fbe4 4270#endif
79aceca5
FB		 4271}
4272
12de9a39
JM		 4273#if defined(TARGET_PPC64)
4274/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4275/* mfsr */
c7697e1f 4276GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4277{
4278#if defined(CONFIG_USER_ONLY)
4279 GEN_EXCP_PRIVREG(ctx);
4280#else
4281 if (unlikely(!ctx->supervisor)) {
4282 GEN_EXCP_PRIVREG(ctx);
4283 return;
4284 }
86c581dc 4285 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4286 gen_op_load_slb();
f78fb44e 4287 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4288#endif
4289}
4290
4291/* mfsrin */
c7697e1f
JM		 4292GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4293 PPC_SEGMENT_64B)
12de9a39
JM		 4294{
4295#if defined(CONFIG_USER_ONLY)
4296 GEN_EXCP_PRIVREG(ctx);
4297#else
4298 if (unlikely(!ctx->supervisor)) {
4299 GEN_EXCP_PRIVREG(ctx);
4300 return;
4301 }
f78fb44e 4302 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4303 gen_op_srli_T1(28);
4304 gen_op_load_slb();
f78fb44e 4305 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4306#endif
4307}
4308
4309/* mtsr */
c7697e1f 4310GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4311{
4312#if defined(CONFIG_USER_ONLY)
4313 GEN_EXCP_PRIVREG(ctx);
4314#else
4315 if (unlikely(!ctx->supervisor)) {
4316 GEN_EXCP_PRIVREG(ctx);
4317 return;
4318 }
f78fb44e 4319 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4320 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4321 gen_op_store_slb();
4322#endif
4323}
4324
4325/* mtsrin */
c7697e1f
JM		 4326GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4327 PPC_SEGMENT_64B)
12de9a39
JM		 4328{
4329#if defined(CONFIG_USER_ONLY)
4330 GEN_EXCP_PRIVREG(ctx);
4331#else
4332 if (unlikely(!ctx->supervisor)) {
4333 GEN_EXCP_PRIVREG(ctx);
4334 return;
4335 }
f78fb44e
AJ		 4336 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4337 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4338 gen_op_srli_T1(28);
4339 gen_op_store_slb();
4340#endif
4341}
4342#endif /* defined(TARGET_PPC64) */
4343
79aceca5
FB		 4344/*** Lookaside buffer management ***/
4345/* Optional & supervisor only: */
4346/* tlbia */
3fc6c082 4347GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4348{
9a64fbe4 4349#if defined(CONFIG_USER_ONLY)
e1833e1f 4350 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4351#else
76a66253 4352 if (unlikely(!ctx->supervisor)) {
e1833e1f 4353 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4354 return;
9a64fbe4
FB		 4355 }
4356 gen_op_tlbia();
4357#endif
79aceca5
FB		 4358}
4359
4360/* tlbie */
76a66253 4361GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4362{
9a64fbe4 4363#if defined(CONFIG_USER_ONLY)
e1833e1f 4364 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4365#else
76a66253 4366 if (unlikely(!ctx->supervisor)) {
e1833e1f 4367 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4368 return;
9a64fbe4 4369 }
f78fb44e 4370 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4371#if defined(TARGET_PPC64)
4372 if (ctx->sf_mode)
4373 gen_op_tlbie_64();
4374 else
4375#endif
4376 gen_op_tlbie();
9a64fbe4 4377#endif
79aceca5
FB		 4378}
4379
4380/* tlbsync */
76a66253 4381GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4382{
9a64fbe4 4383#if defined(CONFIG_USER_ONLY)
e1833e1f 4384 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4385#else
76a66253 4386 if (unlikely(!ctx->supervisor)) {
e1833e1f 4387 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4388 return;
9a64fbe4
FB		 4389 }
4390 /* This has no effect: it should ensure that all previous
4391 * tlbie have completed
4392 */
e1833e1f 4393 GEN_STOP(ctx);
9a64fbe4 4394#endif
79aceca5
FB		 4395}
4396
426613db
JM		 4397#if defined(TARGET_PPC64)
4398/* slbia */
4399GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4400{
4401#if defined(CONFIG_USER_ONLY)
e1833e1f 4402 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4403#else
4404 if (unlikely(!ctx->supervisor)) {
e1833e1f 4405 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4406 return;
4407 }
4408 gen_op_slbia();
426613db
JM		 4409#endif
4410}
4411
4412/* slbie */
4413GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4414{
4415#if defined(CONFIG_USER_ONLY)
e1833e1f 4416 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4417#else
4418 if (unlikely(!ctx->supervisor)) {
e1833e1f 4419 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4420 return;
4421 }
f78fb44e 4422 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4423 gen_op_slbie();
426613db
JM		 4424#endif
4425}
4426#endif
4427
79aceca5
FB		 4428/*** External control ***/
4429/* Optional: */
9a64fbe4
FB		 4430#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4431#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4432static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4433 GEN_MEM_FUNCS(eciwx),
111bfab3 4434};
7863667f
JM		 4435static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4436 GEN_MEM_FUNCS(ecowx),
111bfab3 4437};
9a64fbe4 4438
111bfab3 4439/* eciwx */
79aceca5
FB		 4440GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4441{
9a64fbe4 4442 /* Should check EAR[E] & alignment ! */
a7859e89 4443 gen_set_access_type(ACCESS_RES);
e2be8d8d 4444 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4445 op_eciwx();
f78fb44e 4446 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4447}
4448
4449/* ecowx */
4450GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4451{
4452 /* Should check EAR[E] & alignment ! */
e2be8d8d 4453 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4454 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4455 op_ecowx();
4456}
4457
4458/* PowerPC 601 specific instructions */
4459/* abs - abs. */
4460GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4461{
f78fb44e 4462 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4463 gen_op_POWER_abs();
f78fb44e 4464 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4465 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4466 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4467}
4468
4469/* abso - abso. */
4470GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4471{
f78fb44e 4472 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4473 gen_op_POWER_abso();
f78fb44e 4474 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4475 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4476 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4477}
4478
4479/* clcs */
a750fc0b 4480GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4481{
f78fb44e 4482 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4483 gen_op_POWER_clcs();
c7697e1f 4484 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4485 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4486}
4487
4488/* div - div. */
4489GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4490{
f78fb44e
AJ		 4491 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4492 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4493 gen_op_POWER_div();
f78fb44e 4494 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4495 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4496 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4497}
4498
4499/* divo - divo. */
4500GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4501{
f78fb44e
AJ		 4502 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4503 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4504 gen_op_POWER_divo();
f78fb44e 4505 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4506 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4507 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4508}
4509
4510/* divs - divs. */
4511GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4512{
f78fb44e
AJ		 4513 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4514 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4515 gen_op_POWER_divs();
f78fb44e 4516 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4517 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4518 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4519}
4520
4521/* divso - divso. */
4522GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4523{
f78fb44e
AJ		 4524 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4525 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4526 gen_op_POWER_divso();
f78fb44e 4527 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4528 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4529 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4530}
4531
4532/* doz - doz. */
4533GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4534{
f78fb44e
AJ		 4535 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4536 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4537 gen_op_POWER_doz();
f78fb44e 4538 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4539 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4540 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4541}
4542
4543/* dozo - dozo. */
4544GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4545{
f78fb44e
AJ		 4546 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4547 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4548 gen_op_POWER_dozo();
f78fb44e 4549 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4550 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4551 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4552}
4553
4554/* dozi */
4555GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4556{
f78fb44e 4557 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4558 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4559 gen_op_POWER_doz();
f78fb44e 4560 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4561}
4562
76a66253
JM		 4563/* lscbx - lscbx. */
4564GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4565{
bdb4b689
AJ		 4566 TCGv t0 = tcg_temp_new();
4567 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4568 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4569 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4570
bdb4b689 4571 gen_addr_reg_index(t0, ctx);
76a66253 4572 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4573 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4574 gen_helper_lscbx(t0, t0, t1, t2, t3);
4575 tcg_temp_free_i32(t1);
4576 tcg_temp_free_i32(t2);
4577 tcg_temp_free_i32(t3);
3d7b417e 4578 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4579 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4580 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4581 gen_set_Rc0(ctx, t0);
4582 tcg_temp_free(t0);
76a66253
JM		 4583}
4584
4585/* maskg - maskg. */
4586GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4587{
f78fb44e
AJ		 4588 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4589 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4590 gen_op_POWER_maskg();
f78fb44e 4591 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4592 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4593 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4594}
4595
4596/* maskir - maskir. */
4597GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4598{
f78fb44e
AJ		 4599 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4600 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4601 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4602 gen_op_POWER_maskir();
f78fb44e 4603 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4604 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4605 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4606}
4607
4608/* mul - mul. */
4609GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4610{
f78fb44e
AJ		 4611 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4612 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4613 gen_op_POWER_mul();
f78fb44e 4614 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4615 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4616 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4617}
4618
4619/* mulo - mulo. */
4620GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4621{
f78fb44e
AJ		 4622 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4623 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4624 gen_op_POWER_mulo();
f78fb44e 4625 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4626 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4627 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4628}
4629
4630/* nabs - nabs. */
4631GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4632{
f78fb44e 4633 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4634 gen_op_POWER_nabs();
f78fb44e 4635 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4636 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4637 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4638}
4639
4640/* nabso - nabso. */
4641GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4642{
f78fb44e 4643 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4644 gen_op_POWER_nabso();
f78fb44e 4645 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4646 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4647 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4648}
4649
4650/* rlmi - rlmi. */
4651GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4652{
4653 uint32_t mb, me;
4654
4655 mb = MB(ctx->opcode);
4656 me = ME(ctx->opcode);
f78fb44e
AJ		 4657 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4658 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4659 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4660 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4661 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4662 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4663 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4664}
4665
4666/* rrib - rrib. */
4667GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4668{
f78fb44e
AJ		 4669 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4670 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4671 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4672 gen_op_POWER_rrib();
f78fb44e 4673 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4674 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4675 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4676}
4677
4678/* sle - sle. */
4679GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4680{
f78fb44e
AJ		 4681 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4682 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4683 gen_op_POWER_sle();
f78fb44e 4684 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4685 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4686 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4687}
4688
4689/* sleq - sleq. */
4690GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4691{
f78fb44e
AJ		 4692 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4693 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4694 gen_op_POWER_sleq();
f78fb44e 4695 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4696 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4697 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4698}
4699
4700/* sliq - sliq. */
4701GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4702{
f78fb44e 4703 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4704 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4705 gen_op_POWER_sle();
f78fb44e 4706 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4707 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4708 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4709}
4710
4711/* slliq - slliq. */
4712GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4713{
f78fb44e 4714 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4715 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4716 gen_op_POWER_sleq();
f78fb44e 4717 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4718 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4719 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4720}
4721
4722/* sllq - sllq. */
4723GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4724{
f78fb44e
AJ		 4725 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4726 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4727 gen_op_POWER_sllq();
f78fb44e 4728 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4729 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4730 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4731}
4732
4733/* slq - slq. */
4734GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4735{
f78fb44e
AJ		 4736 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4737 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4738 gen_op_POWER_slq();
f78fb44e 4739 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4740 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4741 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4742}
4743
d9bce9d9 4744/* sraiq - sraiq. */
76a66253
JM		 4745GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4746{
f78fb44e 4747 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4748 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4749 gen_op_POWER_sraq();
f78fb44e 4750 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4751 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4752 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4753}
4754
4755/* sraq - sraq. */
4756GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4757{
f78fb44e
AJ		 4758 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4759 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4760 gen_op_POWER_sraq();
f78fb44e 4761 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4762 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4763 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4764}
4765
4766/* sre - sre. */
4767GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4768{
f78fb44e
AJ		 4769 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4770 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4771 gen_op_POWER_sre();
f78fb44e 4772 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4773 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4774 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4775}
4776
4777/* srea - srea. */
4778GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4779{
f78fb44e
AJ		 4780 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4781 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4782 gen_op_POWER_srea();
f78fb44e 4783 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4784 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4785 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4786}
4787
4788/* sreq */
4789GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4790{
f78fb44e
AJ		 4791 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4792 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4793 gen_op_POWER_sreq();
f78fb44e 4794 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4795 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4796 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4797}
4798
4799/* sriq */
4800GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4801{
f78fb44e 4802 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4803 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4804 gen_op_POWER_srq();
f78fb44e 4805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4806 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4807 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4808}
4809
4810/* srliq */
4811GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4812{
f78fb44e
AJ		 4813 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4814 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4815 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4816 gen_op_POWER_srlq();
f78fb44e 4817 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4818 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4819 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4820}
4821
4822/* srlq */
4823GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4824{
f78fb44e
AJ		 4825 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4826 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4827 gen_op_POWER_srlq();
f78fb44e 4828 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4829 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4830 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4831}
4832
4833/* srq */
4834GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4835{
f78fb44e
AJ		 4836 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4837 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4838 gen_op_POWER_srq();
f78fb44e 4839 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4840 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4841 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4842}
4843
4844/* PowerPC 602 specific instructions */
4845/* dsa */
4846GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4847{
4848 /* XXX: TODO */
e1833e1f 4849 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4850}
4851
4852/* esa */
4853GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4854{
4855 /* XXX: TODO */
e1833e1f 4856 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4857}
4858
4859/* mfrom */
4860GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4861{
4862#if defined(CONFIG_USER_ONLY)
e1833e1f 4863 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4864#else
4865 if (unlikely(!ctx->supervisor)) {
e1833e1f 4866 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4867 return;
4868 }
cf02a65c 4869 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4870#endif
4871}
4872
4873/* 602 - 603 - G2 TLB management */
4874/* tlbld */
c7697e1f 4875GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4876{
4877#if defined(CONFIG_USER_ONLY)
e1833e1f 4878 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4879#else
4880 if (unlikely(!ctx->supervisor)) {
e1833e1f 4881 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4882 return;
4883 }
0f3955e2 4884 gen_helper_load_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4885#endif
4886}
4887
4888/* tlbli */
c7697e1f 4889GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4890{
4891#if defined(CONFIG_USER_ONLY)
e1833e1f 4892 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4893#else
4894 if (unlikely(!ctx->supervisor)) {
e1833e1f 4895 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4896 return;
4897 }
0f3955e2 4898 gen_helper_load_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4899#endif
4900}
4901
7dbe11ac
JM		 4902/* 74xx TLB management */
4903/* tlbld */
c7697e1f 4904GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4905{
4906#if defined(CONFIG_USER_ONLY)
4907 GEN_EXCP_PRIVOPC(ctx);
4908#else
4909 if (unlikely(!ctx->supervisor)) {
4910 GEN_EXCP_PRIVOPC(ctx);
4911 return;
4912 }
0f3955e2 4913 gen_helper_load_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4914#endif
4915}
4916
4917/* tlbli */
c7697e1f 4918GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4919{
4920#if defined(CONFIG_USER_ONLY)
4921 GEN_EXCP_PRIVOPC(ctx);
4922#else
4923 if (unlikely(!ctx->supervisor)) {
4924 GEN_EXCP_PRIVOPC(ctx);
4925 return;
4926 }
0f3955e2 4927 gen_helper_load_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4928#endif
4929}
4930
76a66253
JM		 4931/* POWER instructions not in PowerPC 601 */
4932/* clf */
4933GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4934{
4935 /* Cache line flush: implemented as no-op */
4936}
4937
4938/* cli */
4939GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4940{
7f75ffd3 4941 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4942#if defined(CONFIG_USER_ONLY)
e1833e1f 4943 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4944#else
4945 if (unlikely(!ctx->supervisor)) {
e1833e1f 4946 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4947 return;
4948 }
4949#endif
4950}
4951
4952/* dclst */
4953GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4954{
4955 /* Data cache line store: treated as no-op */
4956}
4957
4958GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4959{
4960#if defined(CONFIG_USER_ONLY)
e1833e1f 4961 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4962#else
4963 if (unlikely(!ctx->supervisor)) {
e1833e1f 4964 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4965 return;
4966 }
4967 int ra = rA(ctx->opcode);
4968 int rd = rD(ctx->opcode);
4969
e2be8d8d 4970 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4971 gen_op_POWER_mfsri();
f78fb44e 4972 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4973 if (ra != 0 && ra != rd)
f78fb44e 4974 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4975#endif
4976}
4977
4978GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4979{
4980#if defined(CONFIG_USER_ONLY)
e1833e1f 4981 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4982#else
4983 if (unlikely(!ctx->supervisor)) {
e1833e1f 4984 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4985 return;
4986 }
e2be8d8d 4987 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4988 gen_op_POWER_rac();
f78fb44e 4989 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4990#endif
4991}
4992
4993GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4994{
4995#if defined(CONFIG_USER_ONLY)
e1833e1f 4996 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4997#else
4998 if (unlikely(!ctx->supervisor)) {
e1833e1f 4999 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5000 return;
5001 }
5002 gen_op_POWER_rfsvc();
e1833e1f 5003 GEN_SYNC(ctx);
76a66253
JM		 5004#endif
5005}
5006
5007/* svc is not implemented for now */
5008
5009/* POWER2 specific instructions */
5010/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5011
5012/* lfq */
5013GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5014{
01a4afeb
AJ		 5015 int rd = rD(ctx->opcode);
5016 TCGv t0 = tcg_temp_new();
5017 gen_addr_imm_index(t0, ctx, 0);
5018 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5019 tcg_gen_addi_tl(t0, t0, 8);
5020 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5021 tcg_temp_free(t0);
76a66253
JM		 5022}
5023
5024/* lfqu */
5025GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5026{
5027 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5028 int rd = rD(ctx->opcode);
5029 TCGv t0 = tcg_temp_new();
5030 TCGv t1 = tcg_temp_new();
5031 gen_addr_imm_index(t0, ctx, 0);
5032 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5033 tcg_gen_addi_tl(t1, t0, 8);
5034 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5035 if (ra != 0)
01a4afeb
AJ		 5036 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5037 tcg_temp_free(t0);
5038 tcg_temp_free(t1);
76a66253
JM		 5039}
5040
5041/* lfqux */
5042GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5043{
5044 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5045 int rd = rD(ctx->opcode);
5046 TCGv t0 = tcg_temp_new();
5047 TCGv t1 = tcg_temp_new();
5048 gen_addr_reg_index(t0, ctx);
5049 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5050 tcg_gen_addi_tl(t1, t0, 8);
5051 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5052 if (ra != 0)
01a4afeb
AJ		 5053 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5054 tcg_temp_free(t0);
5055 tcg_temp_free(t1);
76a66253
JM		 5056}
5057
5058/* lfqx */
5059GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5060{
01a4afeb
AJ		 5061 int rd = rD(ctx->opcode);
5062 TCGv t0 = tcg_temp_new();
5063 gen_addr_reg_index(t0, ctx);
5064 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5065 tcg_gen_addi_tl(t0, t0, 8);
5066 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5067 tcg_temp_free(t0);
76a66253
JM		 5068}
5069
5070/* stfq */
5071GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5072{
01a4afeb
AJ		 5073 int rd = rD(ctx->opcode);
5074 TCGv t0 = tcg_temp_new();
5075 gen_addr_imm_index(t0, ctx, 0);
5076 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5077 tcg_gen_addi_tl(t0, t0, 8);
5078 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5079 tcg_temp_free(t0);
76a66253
JM		 5080}
5081
5082/* stfqu */
5083GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5084{
5085 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5086 int rd = rD(ctx->opcode);
5087 TCGv t0 = tcg_temp_new();
5088 TCGv t1 = tcg_temp_new();
5089 gen_addr_imm_index(t0, ctx, 0);
5090 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5091 tcg_gen_addi_tl(t1, t0, 8);
5092 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5093 if (ra != 0)
01a4afeb
AJ		 5094 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5095 tcg_temp_free(t0);
5096 tcg_temp_free(t1);
76a66253
JM		 5097}
5098
5099/* stfqux */
5100GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5101{
5102 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5103 int rd = rD(ctx->opcode);
5104 TCGv t0 = tcg_temp_new();
5105 TCGv t1 = tcg_temp_new();
5106 gen_addr_reg_index(t0, ctx);
5107 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5108 tcg_gen_addi_tl(t1, t0, 8);
5109 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5110 if (ra != 0)
01a4afeb
AJ		 5111 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5112 tcg_temp_free(t0);
5113 tcg_temp_free(t1);
76a66253
JM		 5114}
5115
5116/* stfqx */
5117GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5118{
01a4afeb
AJ		 5119 int rd = rD(ctx->opcode);
5120 TCGv t0 = tcg_temp_new();
5121 gen_addr_reg_index(t0, ctx);
5122 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5123 tcg_gen_addi_tl(t0, t0, 8);
5124 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5125 tcg_temp_free(t0);
76a66253
JM		 5126}
5127
5128/* BookE specific instructions */
2662a059 5129/* XXX: not implemented on 440 ? */
05332d70 5130GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5131{
5132 /* XXX: TODO */
e1833e1f 5133 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5134}
5135
2662a059 5136/* XXX: not implemented on 440 ? */
05332d70 5137GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5138{
5139#if defined(CONFIG_USER_ONLY)
e1833e1f 5140 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5141#else
5142 if (unlikely(!ctx->supervisor)) {
e1833e1f 5143 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5144 return;
5145 }
e2be8d8d 5146 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5147 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5148#if defined(TARGET_PPC64)
5149 if (ctx->sf_mode)
5150 gen_op_tlbie_64();
5151 else
5152#endif
5153 gen_op_tlbie();
76a66253
JM		 5154#endif
5155}
5156
5157/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5158static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5159 int opc2, int opc3,
5160 int ra, int rb, int rt, int Rc)
76a66253 5161{
182608d4
AJ		 5162 TCGv t0, t1;
5163
a7812ae4
PB		 5164 t0 = tcg_temp_local_new();
5165 t1 = tcg_temp_local_new();
182608d4 5166
76a66253
JM		 5167 switch (opc3 & 0x0D) {
5168 case 0x05:
5169 /* macchw - macchw. - macchwo - macchwo. */
5170 /* macchws - macchws. - macchwso - macchwso. */
5171 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5172 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5173 /* mulchw - mulchw. */
182608d4
AJ		 5174 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5175 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5176 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5177 break;
5178 case 0x04:
5179 /* macchwu - macchwu. - macchwuo - macchwuo. */
5180 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5181 /* mulchwu - mulchwu. */
182608d4
AJ		 5182 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5183 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5184 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5185 break;
5186 case 0x01:
5187 /* machhw - machhw. - machhwo - machhwo. */
5188 /* machhws - machhws. - machhwso - machhwso. */
5189 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5190 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5191 /* mulhhw - mulhhw. */
182608d4
AJ		 5192 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5193 tcg_gen_ext16s_tl(t0, t0);
5194 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5195 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5196 break;
5197 case 0x00:
5198 /* machhwu - machhwu. - machhwuo - machhwuo. */
5199 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5200 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5201 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5202 tcg_gen_ext16u_tl(t0, t0);
5203 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5204 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5205 break;
5206 case 0x0D:
5207 /* maclhw - maclhw. - maclhwo - maclhwo. */
5208 /* maclhws - maclhws. - maclhwso - maclhwso. */
5209 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5210 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5211 /* mullhw - mullhw. */
182608d4
AJ		 5212 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5213 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5214 break;
5215 case 0x0C:
5216 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5217 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5218 /* mullhwu - mullhwu. */
182608d4
AJ		 5219 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5220 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5221 break;
5222 }
76a66253 5223 if (opc2 & 0x04) {
182608d4
AJ		 5224 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5225 tcg_gen_mul_tl(t1, t0, t1);
5226 if (opc2 & 0x02) {
5227 /* nmultiply-and-accumulate (0x0E) */
5228 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5229 } else {
5230 /* multiply-and-accumulate (0x0C) */
5231 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5232 }
5233
5234 if (opc3 & 0x12) {
5235 /* Check overflow and/or saturate */
5236 int l1 = gen_new_label();
5237
5238 if (opc3 & 0x10) {
5239 /* Start with XER OV disabled, the most likely case */
5240 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5241 }
5242 if (opc3 & 0x01) {
5243 /* Signed */
5244 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5245 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5246 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5247 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5248 if (opc3 & 0x02) {
182608d4
AJ		 5249 /* Saturate */
5250 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5251 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5252 }
5253 } else {
5254 /* Unsigned */
5255 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5256 if (opc3 & 0x02) {
182608d4
AJ		 5257 /* Saturate */
5258 tcg_gen_movi_tl(t0, UINT32_MAX);
5259 }
5260 }
5261 if (opc3 & 0x10) {
5262 /* Check overflow */
5263 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5264 }
5265 gen_set_label(l1);
5266 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5267 }
5268 } else {
5269 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5270 }
182608d4
AJ		 5271 tcg_temp_free(t0);
5272 tcg_temp_free(t1);
76a66253
JM		 5273 if (unlikely(Rc) != 0) {
5274 /* Update Rc0 */
182608d4 5275 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5276 }
5277}
5278
a750fc0b
JM		 5279#define GEN_MAC_HANDLER(name, opc2, opc3) \
5280GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5281{ \
5282 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5283 rD(ctx->opcode), Rc(ctx->opcode)); \
5284}
5285
5286/* macchw - macchw. */
a750fc0b 5287GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5288/* macchwo - macchwo. */
a750fc0b 5289GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5290/* macchws - macchws. */
a750fc0b 5291GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5292/* macchwso - macchwso. */
a750fc0b 5293GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5294/* macchwsu - macchwsu. */
a750fc0b 5295GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5296/* macchwsuo - macchwsuo. */
a750fc0b 5297GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5298/* macchwu - macchwu. */
a750fc0b 5299GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5300/* macchwuo - macchwuo. */
a750fc0b 5301GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5302/* machhw - machhw. */
a750fc0b 5303GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5304/* machhwo - machhwo. */
a750fc0b 5305GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5306/* machhws - machhws. */
a750fc0b 5307GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5308/* machhwso - machhwso. */
a750fc0b 5309GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5310/* machhwsu - machhwsu. */
a750fc0b 5311GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5312/* machhwsuo - machhwsuo. */
a750fc0b 5313GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5314/* machhwu - machhwu. */
a750fc0b 5315GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5316/* machhwuo - machhwuo. */
a750fc0b 5317GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5318/* maclhw - maclhw. */
a750fc0b 5319GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5320/* maclhwo - maclhwo. */
a750fc0b 5321GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5322/* maclhws - maclhws. */
a750fc0b 5323GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5324/* maclhwso - maclhwso. */
a750fc0b 5325GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5326/* maclhwu - maclhwu. */
a750fc0b 5327GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5328/* maclhwuo - maclhwuo. */
a750fc0b 5329GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5330/* maclhwsu - maclhwsu. */
a750fc0b 5331GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5332/* maclhwsuo - maclhwsuo. */
a750fc0b 5333GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5334/* nmacchw - nmacchw. */
a750fc0b 5335GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5336/* nmacchwo - nmacchwo. */
a750fc0b 5337GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5338/* nmacchws - nmacchws. */
a750fc0b 5339GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5340/* nmacchwso - nmacchwso. */
a750fc0b 5341GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5342/* nmachhw - nmachhw. */
a750fc0b 5343GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5344/* nmachhwo - nmachhwo. */
a750fc0b 5345GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5346/* nmachhws - nmachhws. */
a750fc0b 5347GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5348/* nmachhwso - nmachhwso. */
a750fc0b 5349GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5350/* nmaclhw - nmaclhw. */
a750fc0b 5351GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5352/* nmaclhwo - nmaclhwo. */
a750fc0b 5353GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5354/* nmaclhws - nmaclhws. */
a750fc0b 5355GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5356/* nmaclhwso - nmaclhwso. */
a750fc0b 5357GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5358
5359/* mulchw - mulchw. */
a750fc0b 5360GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5361/* mulchwu - mulchwu. */
a750fc0b 5362GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5363/* mulhhw - mulhhw. */
a750fc0b 5364GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5365/* mulhhwu - mulhhwu. */
a750fc0b 5366GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5367/* mullhw - mullhw. */
a750fc0b 5368GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5369/* mullhwu - mullhwu. */
a750fc0b 5370GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5371
5372/* mfdcr */
05332d70 5373GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5374{
5375#if defined(CONFIG_USER_ONLY)
e1833e1f 5376 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5377#else
5378 uint32_t dcrn = SPR(ctx->opcode);
5379
5380 if (unlikely(!ctx->supervisor)) {
e1833e1f 5381 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5382 return;
5383 }
86c581dc 5384 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5385 gen_op_load_dcr();
f78fb44e 5386 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5387#endif
5388}
5389
5390/* mtdcr */
05332d70 5391GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5392{
5393#if defined(CONFIG_USER_ONLY)
e1833e1f 5394 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5395#else
5396 uint32_t dcrn = SPR(ctx->opcode);
5397
5398 if (unlikely(!ctx->supervisor)) {
e1833e1f 5399 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5400 return;
5401 }
86c581dc 5402 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5403 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5404 gen_op_store_dcr();
5405#endif
5406}
5407
5408/* mfdcrx */
2662a059 5409/* XXX: not implemented on 440 ? */
05332d70 5410GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5411{
5412#if defined(CONFIG_USER_ONLY)
e1833e1f 5413 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5414#else
5415 if (unlikely(!ctx->supervisor)) {
e1833e1f 5416 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5417 return;
5418 }
f78fb44e 5419 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5420 gen_op_load_dcr();
f78fb44e 5421 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5422 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5423#endif
5424}
5425
5426/* mtdcrx */
2662a059 5427/* XXX: not implemented on 440 ? */
05332d70 5428GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5429{
5430#if defined(CONFIG_USER_ONLY)
e1833e1f 5431 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5432#else
5433 if (unlikely(!ctx->supervisor)) {
e1833e1f 5434 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5435 return;
5436 }
f78fb44e
AJ		 5437 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5438 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5439 gen_op_store_dcr();
a750fc0b 5440 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5441#endif
5442}
5443
a750fc0b
JM		 5444/* mfdcrux (PPC 460) : user-mode access to DCR */
5445GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5446{
f78fb44e 5447 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5448 gen_op_load_dcr();
f78fb44e 5449 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5450 /* Note: Rc update flag set leads to undefined state of Rc0 */
5451}
5452
5453/* mtdcrux (PPC 460) : user-mode access to DCR */
5454GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5455{
f78fb44e
AJ		 5456 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5457 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5458 gen_op_store_dcr();
5459 /* Note: Rc update flag set leads to undefined state of Rc0 */
5460}
5461
76a66253
JM		 5462/* dccci */
5463GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5464{
5465#if defined(CONFIG_USER_ONLY)
e1833e1f 5466 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5467#else
5468 if (unlikely(!ctx->supervisor)) {
e1833e1f 5469 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5470 return;
5471 }
5472 /* interpreted as no-op */
5473#endif
5474}
5475
5476/* dcread */
5477GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5478{
5479#if defined(CONFIG_USER_ONLY)
e1833e1f 5480 GEN_EXCP_PRIVOPC(ctx);
76a66253 5481#else
b61f2753 5482 TCGv EA, val;
76a66253 5483 if (unlikely(!ctx->supervisor)) {
e1833e1f 5484 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5485 return;
5486 }
a7812ae4 5487 EA = tcg_temp_new();
a7859e89 5488 gen_set_access_type(ACCESS_CACHE);
b61f2753 5489 gen_addr_reg_index(EA, ctx);
a7812ae4 5490 val = tcg_temp_new();
b61f2753
AJ		 5491 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5492 tcg_temp_free(val);
5493 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5494 tcg_temp_free(EA);
76a66253
JM		 5495#endif
5496}
5497
5498/* icbt */
c7697e1f 5499GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5500{
5501 /* interpreted as no-op */
5502 /* XXX: specification say this is treated as a load by the MMU
5503 * but does not generate any exception
5504 */
5505}
5506
5507/* iccci */
5508GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5509{
5510#if defined(CONFIG_USER_ONLY)
e1833e1f 5511 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5512#else
5513 if (unlikely(!ctx->supervisor)) {
e1833e1f 5514 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5515 return;
5516 }
5517 /* interpreted as no-op */
5518#endif
5519}
5520
5521/* icread */
5522GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5523{
5524#if defined(CONFIG_USER_ONLY)
e1833e1f 5525 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5526#else
5527 if (unlikely(!ctx->supervisor)) {
e1833e1f 5528 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5529 return;
5530 }
5531 /* interpreted as no-op */
5532#endif
5533}
5534
5535/* rfci (supervisor only) */
c7697e1f 5536GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5537{
5538#if defined(CONFIG_USER_ONLY)
e1833e1f 5539 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5540#else
5541 if (unlikely(!ctx->supervisor)) {
e1833e1f 5542 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5543 return;
5544 }
5545 /* Restore CPU state */
5546 gen_op_40x_rfci();
e1833e1f 5547 GEN_SYNC(ctx);
a42bd6cc
JM		 5548#endif
5549}
5550
5551GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5552{
5553#if defined(CONFIG_USER_ONLY)
e1833e1f 5554 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5555#else
5556 if (unlikely(!ctx->supervisor)) {
e1833e1f 5557 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5558 return;
5559 }
5560 /* Restore CPU state */
5561 gen_op_rfci();
e1833e1f 5562 GEN_SYNC(ctx);
a42bd6cc
JM		 5563#endif
5564}
5565
5566/* BookE specific */
2662a059 5567/* XXX: not implemented on 440 ? */
05332d70 5568GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5569{
5570#if defined(CONFIG_USER_ONLY)
e1833e1f 5571 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5572#else
5573 if (unlikely(!ctx->supervisor)) {
e1833e1f 5574 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5575 return;
5576 }
5577 /* Restore CPU state */
a42bd6cc 5578 gen_op_rfdi();
e1833e1f 5579 GEN_SYNC(ctx);
76a66253
JM		 5580#endif
5581}
5582
2662a059 5583/* XXX: not implemented on 440 ? */
a750fc0b 5584GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5585{
5586#if defined(CONFIG_USER_ONLY)
e1833e1f 5587 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5588#else
5589 if (unlikely(!ctx->supervisor)) {
e1833e1f 5590 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5591 return;
5592 }
5593 /* Restore CPU state */
5594 gen_op_rfmci();
e1833e1f 5595 GEN_SYNC(ctx);
a42bd6cc
JM		 5596#endif
5597}
5eb7995e 5598
d9bce9d9 5599/* TLB management - PowerPC 405 implementation */
76a66253 5600/* tlbre */
c7697e1f 5601GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5602{
5603#if defined(CONFIG_USER_ONLY)
e1833e1f 5604 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5605#else
5606 if (unlikely(!ctx->supervisor)) {
e1833e1f 5607 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5608 return;
5609 }
5610 switch (rB(ctx->opcode)) {
5611 case 0:
f78fb44e 5612 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5613 gen_op_4xx_tlbre_hi();
f78fb44e 5614 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5615 break;
5616 case 1:
f78fb44e 5617 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5618 gen_op_4xx_tlbre_lo();
f78fb44e 5619 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5620 break;
5621 default:
e1833e1f 5622 GEN_EXCP_INVAL(ctx);
76a66253 5623 break;
9a64fbe4 5624 }
76a66253
JM		 5625#endif
5626}
5627
d9bce9d9 5628/* tlbsx - tlbsx. */
c7697e1f 5629GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5630{
5631#if defined(CONFIG_USER_ONLY)
e1833e1f 5632 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5633#else
5634 if (unlikely(!ctx->supervisor)) {
e1833e1f 5635 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5636 return;
5637 }
e2be8d8d 5638 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5639 gen_op_4xx_tlbsx();
76a66253 5640 if (Rc(ctx->opcode))
daf4f96e 5641 gen_op_4xx_tlbsx_check();
f78fb44e 5642 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5643#endif
79aceca5
FB		 5644}
5645
76a66253 5646/* tlbwe */
c7697e1f 5647GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5648{
76a66253 5649#if defined(CONFIG_USER_ONLY)
e1833e1f 5650 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5651#else
5652 if (unlikely(!ctx->supervisor)) {
e1833e1f 5653 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5654 return;
5655 }
5656 switch (rB(ctx->opcode)) {
5657 case 0:
f78fb44e
AJ		 5658 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5659 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5660 gen_op_4xx_tlbwe_hi();
5661 break;
5662 case 1:
f78fb44e
AJ		 5663 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5664 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5665 gen_op_4xx_tlbwe_lo();
5666 break;
5667 default:
e1833e1f 5668 GEN_EXCP_INVAL(ctx);
76a66253 5669 break;
9a64fbe4 5670 }
76a66253
JM		 5671#endif
5672}
5673
a4bb6c3e 5674/* TLB management - PowerPC 440 implementation */
5eb7995e 5675/* tlbre */
c7697e1f 5676GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5677{
5678#if defined(CONFIG_USER_ONLY)
e1833e1f 5679 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5680#else
5681 if (unlikely(!ctx->supervisor)) {
e1833e1f 5682 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5683 return;
5684 }
5685 switch (rB(ctx->opcode)) {
5686 case 0:
5eb7995e 5687 case 1:
5eb7995e 5688 case 2:
f78fb44e 5689 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5690 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5691 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5692 break;
5693 default:
e1833e1f 5694 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5695 break;
5696 }
5697#endif
5698}
5699
5700/* tlbsx - tlbsx. */
c7697e1f 5701GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5702{
5703#if defined(CONFIG_USER_ONLY)
e1833e1f 5704 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5705#else
5706 if (unlikely(!ctx->supervisor)) {
e1833e1f 5707 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5708 return;
5709 }
e2be8d8d 5710 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5711 gen_op_440_tlbsx();
5eb7995e 5712 if (Rc(ctx->opcode))
daf4f96e 5713 gen_op_4xx_tlbsx_check();
f78fb44e 5714 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5715#endif
5716}
5717
5718/* tlbwe */
c7697e1f 5719GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5720{
5721#if defined(CONFIG_USER_ONLY)
e1833e1f 5722 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5723#else
5724 if (unlikely(!ctx->supervisor)) {
e1833e1f 5725 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5726 return;
5727 }
5728 switch (rB(ctx->opcode)) {
5729 case 0:
5eb7995e 5730 case 1:
5eb7995e 5731 case 2:
f78fb44e
AJ		 5732 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5733 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5734 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5735 break;
5736 default:
e1833e1f 5737 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5738 break;
5739 }
5740#endif
5741}
5742
76a66253 5743/* wrtee */
05332d70 5744GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5745{
5746#if defined(CONFIG_USER_ONLY)
e1833e1f 5747 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5748#else
5749 if (unlikely(!ctx->supervisor)) {
e1833e1f 5750 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5751 return;
5752 }
f78fb44e 5753 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5754 gen_op_wrte();
dee96f6c
JM		 5755 /* Stop translation to have a chance to raise an exception
5756 * if we just set msr_ee to 1
5757 */
e1833e1f 5758 GEN_STOP(ctx);
76a66253
JM		 5759#endif
5760}
5761
5762/* wrteei */
05332d70 5763GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5764{
5765#if defined(CONFIG_USER_ONLY)
e1833e1f 5766 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5767#else
5768 if (unlikely(!ctx->supervisor)) {
e1833e1f 5769 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5770 return;
5771 }
86c581dc 5772 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5773 gen_op_wrte();
dee96f6c
JM		 5774 /* Stop translation to have a chance to raise an exception
5775 * if we just set msr_ee to 1
5776 */
e1833e1f 5777 GEN_STOP(ctx);
76a66253
JM		 5778#endif
5779}
5780
08e46e54 5781/* PowerPC 440 specific instructions */
76a66253
JM		 5782/* dlmzb */
5783GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5784{
f78fb44e
AJ		 5785 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5786 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5787 gen_op_440_dlmzb();
f78fb44e 5788 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5789 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5790 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5791 if (Rc(ctx->opcode)) {
5792 gen_op_440_dlmzb_update_Rc();
a7812ae4
PB		 5793 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_T[0]);
5794 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 0xf);
76a66253
JM		 5795 }
5796}
5797
5798/* mbar replaces eieio on 440 */
5799GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5800{
5801 /* interpreted as no-op */
5802}
5803
5804/* msync replaces sync on 440 */
0db1b20e 5805GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5806{
5807 /* interpreted as no-op */
5808}
5809
5810/* icbt */
c7697e1f 5811GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5812{
5813 /* interpreted as no-op */
5814 /* XXX: specification say this is treated as a load by the MMU
5815 * but does not generate any exception
5816 */
79aceca5
FB		 5817}
5818
a9d9eb8f
JM		 5819/*** Altivec vector extension ***/
5820/* Altivec registers moves */
a9d9eb8f 5821
a9d9eb8f 5822#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 5823GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 5824{ \
fe1e5c53 5825 TCGv EA; \
a9d9eb8f
JM		 5826 if (unlikely(!ctx->altivec_enabled)) { \
5827 GEN_EXCP_NO_VR(ctx); \
5828 return; \
5829 } \
fe1e5c53
AJ		 5830 EA = tcg_temp_new(); \
5831 gen_addr_reg_index(EA, ctx); \
5832 tcg_gen_andi_tl(EA, EA, ~0xf); \
5833 if (ctx->mem_idx & 1) { \
5834 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5835 tcg_gen_addi_tl(EA, EA, 8); \
5836 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5837 } else { \
5838 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5839 tcg_gen_addi_tl(EA, EA, 8); \
5840 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5841 } \
5842 tcg_temp_free(EA); \
a9d9eb8f
JM		 5843}
5844
5845#define GEN_VR_STX(name, opc2, opc3) \
5846GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5847{ \
fe1e5c53 5848 TCGv EA; \
a9d9eb8f
JM		 5849 if (unlikely(!ctx->altivec_enabled)) { \
5850 GEN_EXCP_NO_VR(ctx); \
5851 return; \
5852 } \
fe1e5c53
AJ		 5853 EA = tcg_temp_new(); \
5854 gen_addr_reg_index(EA, ctx); \
5855 tcg_gen_andi_tl(EA, EA, ~0xf); \
5856 if (ctx->mem_idx & 1) { \
5857 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5858 tcg_gen_addi_tl(EA, EA, 8); \
5859 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5860 } else { \
5861 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5862 tcg_gen_addi_tl(EA, EA, 8); \
5863 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5864 } \
5865 tcg_temp_free(EA); \
a9d9eb8f
JM		 5866}
5867
fe1e5c53 5868GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 5869/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 5870GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 5871
fe1e5c53 5872GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 5873/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 5874GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 5875
0487d6a8 5876/*** SPE extension ***/
0487d6a8 5877/* Register moves */
3cd7d1dd 5878
a7812ae4 5879static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 5880#if defined(TARGET_PPC64)
5881 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5882#else
36aa55dc 5883 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5884#endif
f78fb44e 5885}
3cd7d1dd 5886
a7812ae4 5887static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 5888#if defined(TARGET_PPC64)
5889 tcg_gen_mov_i64(cpu_gpr[reg], t);
5890#else
a7812ae4 5891 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 5892 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 5893 tcg_gen_shri_i64(tmp, t, 32);
5894 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 5895 tcg_temp_free_i64(tmp);
3cd7d1dd 5896#endif
f78fb44e 5897}
3cd7d1dd 5898
0487d6a8
JM		 5899#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5900GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5901{ \
5902 if (Rc(ctx->opcode)) \
5903 gen_##name1(ctx); \
5904 else \
5905 gen_##name0(ctx); \
5906}
5907
5908/* Handler for undefined SPE opcodes */
b068d6a7 5909static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5910{
e1833e1f 5911 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5912}
5913
57951c27
AJ		 5914/* SPE logic */
5915#if defined(TARGET_PPC64)
5916#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 5917static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5918{ \
5919 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5920 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5921 return; \
5922 } \
57951c27
AJ		 5923 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5924 cpu_gpr[rB(ctx->opcode)]); \
5925}
5926#else
5927#define GEN_SPEOP_LOGIC2(name, tcg_op) \
5928static always_inline void gen_##name (DisasContext *ctx) \
5929{ \
5930 if (unlikely(!ctx->spe_enabled)) { \
5931 GEN_EXCP_NO_AP(ctx); \
5932 return; \
5933 } \
5934 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5935 cpu_gpr[rB(ctx->opcode)]); \
5936 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
5937 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 5938}
57951c27
AJ		 5939#endif
5940
5941GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
5942GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
5943GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
5944GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
5945GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
5946GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
5947GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
5948GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 5949
57951c27
AJ		 5950/* SPE logic immediate */
5951#if defined(TARGET_PPC64)
5952#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 5953static always_inline void gen_##name (DisasContext *ctx) \
5954{ \
5955 if (unlikely(!ctx->spe_enabled)) { \
5956 GEN_EXCP_NO_AP(ctx); \
5957 return; \
5958 } \
a7812ae4
PB		 5959 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
5960 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
5961 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 5962 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
5963 tcg_opi(t0, t0, rB(ctx->opcode)); \
5964 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
5965 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 5966 tcg_temp_free_i64(t2); \
57951c27
AJ		 5967 tcg_opi(t1, t1, rB(ctx->opcode)); \
5968 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 5969 tcg_temp_free_i32(t0); \
5970 tcg_temp_free_i32(t1); \
3d3a6a0a 5971}
57951c27
AJ		 5972#else
5973#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 5974static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5975{ \
5976 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5977 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5978 return; \
5979 } \
57951c27
AJ		 5980 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5981 rB(ctx->opcode)); \
5982 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
5983 rB(ctx->opcode)); \
0487d6a8 5984}
57951c27
AJ		 5985#endif
5986GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
5987GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
5988GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
5989GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 5990
57951c27
AJ		 5991/* SPE arithmetic */
5992#if defined(TARGET_PPC64)
5993#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 5994static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5995{ \
5996 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5997 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5998 return; \
5999 } \
a7812ae4
PB		 6000 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6001 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6002 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6003 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6004 tcg_op(t0, t0); \
6005 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6006 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6007 tcg_temp_free_i64(t2); \
57951c27
AJ		 6008 tcg_op(t1, t1); \
6009 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6010 tcg_temp_free_i32(t0); \
6011 tcg_temp_free_i32(t1); \
0487d6a8 6012}
57951c27 6013#else
a7812ae4 6014#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6015static always_inline void gen_##name (DisasContext *ctx) \
6016{ \
6017 if (unlikely(!ctx->spe_enabled)) { \
6018 GEN_EXCP_NO_AP(ctx); \
6019 return; \
6020 } \
6021 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6022 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6023}
6024#endif
0487d6a8 6025
a7812ae4 6026static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6027{
6028 int l1 = gen_new_label();
6029 int l2 = gen_new_label();
0487d6a8 6030
57951c27
AJ		 6031 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6032 tcg_gen_neg_i32(ret, arg1);
6033 tcg_gen_br(l2);
6034 gen_set_label(l1);
a7812ae4 6035 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6036 gen_set_label(l2);
6037}
6038GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6039GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6040GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6041GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6042static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6043{
57951c27
AJ		 6044 tcg_gen_addi_i32(ret, arg1, 0x8000);
6045 tcg_gen_ext16u_i32(ret, ret);
6046}
6047GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6048GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6049GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6050
57951c27
AJ		 6051#if defined(TARGET_PPC64)
6052#define GEN_SPEOP_ARITH2(name, tcg_op) \
6053static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6054{ \
6055 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6056 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6057 return; \
6058 } \
a7812ae4
PB		 6059 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6060 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6061 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6062 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
57951c27
AJ		 6063 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6064 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6065 tcg_op(t0, t0, t2); \
6066 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6067 tcg_gen_trunc_i64_i32(t1, t3); \
6068 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6069 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6070 tcg_temp_free_i64(t3); \
57951c27 6071 tcg_op(t1, t1, t2); \
a7812ae4 6072 tcg_temp_free_i32(t2); \
57951c27 6073 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6074 tcg_temp_free_i32(t0); \
6075 tcg_temp_free_i32(t1); \
0487d6a8 6076}
57951c27
AJ		 6077#else
6078#define GEN_SPEOP_ARITH2(name, tcg_op) \
6079static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6080{ \
6081 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6082 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6083 return; \
6084 } \
57951c27
AJ		 6085 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6086 cpu_gpr[rB(ctx->opcode)]); \
6087 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6088 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6089}
57951c27 6090#endif
0487d6a8 6091
a7812ae4 6092static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6093{
a7812ae4 6094 TCGv_i32 t0;
57951c27 6095 int l1, l2;
0487d6a8 6096
57951c27
AJ		 6097 l1 = gen_new_label();
6098 l2 = gen_new_label();
a7812ae4 6099 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6100 /* No error here: 6 bits are used */
6101 tcg_gen_andi_i32(t0, arg2, 0x3F);
6102 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6103 tcg_gen_shr_i32(ret, arg1, t0);
6104 tcg_gen_br(l2);
6105 gen_set_label(l1);
6106 tcg_gen_movi_i32(ret, 0);
6107 tcg_gen_br(l2);
a7812ae4 6108 tcg_temp_free_i32(t0);
57951c27
AJ		 6109}
6110GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6111static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6112{
a7812ae4 6113 TCGv_i32 t0;
57951c27
AJ		 6114 int l1, l2;
6115
6116 l1 = gen_new_label();
6117 l2 = gen_new_label();
a7812ae4 6118 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6119 /* No error here: 6 bits are used */
6120 tcg_gen_andi_i32(t0, arg2, 0x3F);
6121 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6122 tcg_gen_sar_i32(ret, arg1, t0);
6123 tcg_gen_br(l2);
6124 gen_set_label(l1);
6125 tcg_gen_movi_i32(ret, 0);
6126 tcg_gen_br(l2);
a7812ae4 6127 tcg_temp_free_i32(t0);
57951c27
AJ		 6128}
6129GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6130static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6131{
a7812ae4 6132 TCGv_i32 t0;
57951c27
AJ		 6133 int l1, l2;
6134
6135 l1 = gen_new_label();
6136 l2 = gen_new_label();
a7812ae4 6137 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6138 /* No error here: 6 bits are used */
6139 tcg_gen_andi_i32(t0, arg2, 0x3F);
6140 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6141 tcg_gen_shl_i32(ret, arg1, t0);
6142 tcg_gen_br(l2);
6143 gen_set_label(l1);
6144 tcg_gen_movi_i32(ret, 0);
6145 tcg_gen_br(l2);
a7812ae4 6146 tcg_temp_free_i32(t0);
57951c27
AJ		 6147}
6148GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6149static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6150{
a7812ae4 6151 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6152 tcg_gen_andi_i32(t0, arg2, 0x1F);
6153 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6154 tcg_temp_free_i32(t0);
57951c27
AJ		 6155}
6156GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6157static always_inline void gen_evmergehi (DisasContext *ctx)
6158{
6159 if (unlikely(!ctx->spe_enabled)) {
6160 GEN_EXCP_NO_AP(ctx);
6161 return;
6162 }
6163#if defined(TARGET_PPC64)
a7812ae4
PB		 6164 TCGv t0 = tcg_temp_new();
6165 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6166 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6167 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6168 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6169 tcg_temp_free(t0);
6170 tcg_temp_free(t1);
6171#else
6172 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6173 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6174#endif
6175}
6176GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6177static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6178{
57951c27
AJ		 6179 tcg_gen_sub_i32(ret, arg2, arg1);
6180}
6181GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6182
57951c27
AJ		 6183/* SPE arithmetic immediate */
6184#if defined(TARGET_PPC64)
6185#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6186static always_inline void gen_##name (DisasContext *ctx) \
6187{ \
6188 if (unlikely(!ctx->spe_enabled)) { \
6189 GEN_EXCP_NO_AP(ctx); \
6190 return; \
6191 } \
a7812ae4
PB		 6192 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6193 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6194 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6195 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6196 tcg_op(t0, t0, rA(ctx->opcode)); \
6197 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6198 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6199 tcg_temp_free_i64(t2); \
57951c27
AJ		 6200 tcg_op(t1, t1, rA(ctx->opcode)); \
6201 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6202 tcg_temp_free_i32(t0); \
6203 tcg_temp_free_i32(t1); \
57951c27
AJ		 6204}
6205#else
6206#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6207static always_inline void gen_##name (DisasContext *ctx) \
6208{ \
6209 if (unlikely(!ctx->spe_enabled)) { \
6210 GEN_EXCP_NO_AP(ctx); \
6211 return; \
6212 } \
6213 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6214 rA(ctx->opcode)); \
6215 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6216 rA(ctx->opcode)); \
6217}
6218#endif
6219GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6220GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6221
6222/* SPE comparison */
6223#if defined(TARGET_PPC64)
6224#define GEN_SPEOP_COMP(name, tcg_cond) \
6225static always_inline void gen_##name (DisasContext *ctx) \
6226{ \
6227 if (unlikely(!ctx->spe_enabled)) { \
6228 GEN_EXCP_NO_AP(ctx); \
6229 return; \
6230 } \
6231 int l1 = gen_new_label(); \
6232 int l2 = gen_new_label(); \
6233 int l3 = gen_new_label(); \
6234 int l4 = gen_new_label(); \
a7812ae4
PB		 6235 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6236 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6237 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6238 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6239 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6240 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6241 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6242 tcg_gen_br(l2); \
6243 gen_set_label(l1); \
6244 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6245 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6246 gen_set_label(l2); \
6247 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6248 tcg_gen_trunc_i64_i32(t0, t2); \
6249 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6250 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6251 tcg_temp_free_i64(t2); \
57951c27
AJ		 6252 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6253 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6254 ~(CRF_CH | CRF_CH_AND_CL)); \
6255 tcg_gen_br(l4); \
6256 gen_set_label(l3); \
6257 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6258 CRF_CH | CRF_CH_OR_CL); \
6259 gen_set_label(l4); \
a7812ae4
PB		 6260 tcg_temp_free_i32(t0); \
6261 tcg_temp_free_i32(t1); \
57951c27
AJ		 6262}
6263#else
6264#define GEN_SPEOP_COMP(name, tcg_cond) \
6265static always_inline void gen_##name (DisasContext *ctx) \
6266{ \
6267 if (unlikely(!ctx->spe_enabled)) { \
6268 GEN_EXCP_NO_AP(ctx); \
6269 return; \
6270 } \
6271 int l1 = gen_new_label(); \
6272 int l2 = gen_new_label(); \
6273 int l3 = gen_new_label(); \
6274 int l4 = gen_new_label(); \
6275 \
6276 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6277 cpu_gpr[rB(ctx->opcode)], l1); \
6278 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6279 tcg_gen_br(l2); \
6280 gen_set_label(l1); \
6281 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6282 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6283 gen_set_label(l2); \
6284 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6285 cpu_gprh[rB(ctx->opcode)], l3); \
6286 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6287 ~(CRF_CH | CRF_CH_AND_CL)); \
6288 tcg_gen_br(l4); \
6289 gen_set_label(l3); \
6290 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6291 CRF_CH | CRF_CH_OR_CL); \
6292 gen_set_label(l4); \
6293}
6294#endif
6295GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6296GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6297GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6298GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6299GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6300
6301/* SPE misc */
6302static always_inline void gen_brinc (DisasContext *ctx)
6303{
6304 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6305 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6306 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6307}
57951c27
AJ		 6308static always_inline void gen_evmergelo (DisasContext *ctx)
6309{
6310 if (unlikely(!ctx->spe_enabled)) {
6311 GEN_EXCP_NO_AP(ctx);
6312 return;
6313 }
6314#if defined(TARGET_PPC64)
a7812ae4
PB		 6315 TCGv t0 = tcg_temp_new();
6316 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6317 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6318 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6319 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6320 tcg_temp_free(t0);
6321 tcg_temp_free(t1);
6322#else
6323 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6324 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6325#endif
6326}
6327static always_inline void gen_evmergehilo (DisasContext *ctx)
6328{
6329 if (unlikely(!ctx->spe_enabled)) {
6330 GEN_EXCP_NO_AP(ctx);
6331 return;
6332 }
6333#if defined(TARGET_PPC64)
a7812ae4
PB		 6334 TCGv t0 = tcg_temp_new();
6335 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6336 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6337 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6338 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6339 tcg_temp_free(t0);
6340 tcg_temp_free(t1);
6341#else
6342 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6343 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6344#endif
6345}
6346static always_inline void gen_evmergelohi (DisasContext *ctx)
6347{
6348 if (unlikely(!ctx->spe_enabled)) {
6349 GEN_EXCP_NO_AP(ctx);
6350 return;
6351 }
6352#if defined(TARGET_PPC64)
a7812ae4
PB		 6353 TCGv t0 = tcg_temp_new();
6354 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6355 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6356 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6357 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6358 tcg_temp_free(t0);
6359 tcg_temp_free(t1);
6360#else
6361 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6362 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6363#endif
6364}
6365static always_inline void gen_evsplati (DisasContext *ctx)
6366{
38d14952 6367 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 6368
57951c27 6369#if defined(TARGET_PPC64)
38d14952 6370 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6371#else
6372 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6373 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6374#endif
6375}
b068d6a7 6376static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 6377{
38d14952 6378 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 6379
57951c27 6380#if defined(TARGET_PPC64)
38d14952 6381 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6382#else
6383 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6384 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6385#endif
0487d6a8
JM		 6386}
6387
57951c27
AJ		 6388static always_inline void gen_evsel (DisasContext *ctx)
6389{
6390 int l1 = gen_new_label();
6391 int l2 = gen_new_label();
6392 int l3 = gen_new_label();
6393 int l4 = gen_new_label();
a7812ae4 6394 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 6395#if defined(TARGET_PPC64)
a7812ae4
PB		 6396 TCGv t1 = tcg_temp_local_new();
6397 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 6398#endif
6399 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6400 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6401#if defined(TARGET_PPC64)
6402 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6403#else
6404 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6405#endif
6406 tcg_gen_br(l2);
6407 gen_set_label(l1);
6408#if defined(TARGET_PPC64)
6409 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6410#else
6411 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6412#endif
6413 gen_set_label(l2);
6414 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6415 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6416#if defined(TARGET_PPC64)
6417 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6418#else
6419 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6420#endif
6421 tcg_gen_br(l4);
6422 gen_set_label(l3);
6423#if defined(TARGET_PPC64)
6424 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6425#else
6426 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6427#endif
6428 gen_set_label(l4);
a7812ae4 6429 tcg_temp_free_i32(t0);
57951c27
AJ		 6430#if defined(TARGET_PPC64)
6431 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6432 tcg_temp_free(t1);
6433 tcg_temp_free(t2);
6434#endif
6435}
6436GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6437{
6438 gen_evsel(ctx);
6439}
6440GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6441{
6442 gen_evsel(ctx);
6443}
6444GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6445{
6446 gen_evsel(ctx);
6447}
6448GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6449{
6450 gen_evsel(ctx);
6451}
0487d6a8
JM		 6452
6453GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6454GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6455GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6456GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6457GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6458GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6459GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6460GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6461GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6462GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6463GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6464GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6465GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6466GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6467GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6468GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6469GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6470GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6471GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6472GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6473GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6474GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6475GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6476GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6477GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6478
6a6ae23f
AJ		 6479/* SPE load and stores */
6480static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
6481{
6482 target_ulong uimm = rB(ctx->opcode);
6483
6484 if (rA(ctx->opcode) == 0)
6485 tcg_gen_movi_tl(EA, uimm << sh);
6486 else
6487 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
0487d6a8 6488}
6a6ae23f
AJ		 6489
6490static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6491{
6492#if defined(TARGET_PPC64)
6493 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6494#else
6495 TCGv_i64 t0 = tcg_temp_new_i64();
6496 gen_qemu_ld64(t0, addr, ctx->mem_idx);
6497 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6498 tcg_gen_shri_i64(t0, t0, 32);
6499 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6500 tcg_temp_free_i64(t0);
6501#endif
0487d6a8 6502}
6a6ae23f
AJ		 6503
6504static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6505{
0487d6a8 6506#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6507 TCGv t0 = tcg_temp_new();
6508 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6509 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6510 tcg_gen_addi_tl(addr, addr, 4);
6511 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6512 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6513 tcg_temp_free(t0);
6514#else
6515 gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6516 tcg_gen_addi_tl(addr, addr, 4);
6517 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6518#endif
0487d6a8 6519}
6a6ae23f
AJ		 6520
6521static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6522{
6523 TCGv t0 = tcg_temp_new();
6524#if defined(TARGET_PPC64)
6525 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6526 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6527 tcg_gen_addi_tl(addr, addr, 2);
6528 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6529 tcg_gen_shli_tl(t0, t0, 32);
6530 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6531 tcg_gen_addi_tl(addr, addr, 2);
6532 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6533 tcg_gen_shli_tl(t0, t0, 16);
6534 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6535 tcg_gen_addi_tl(addr, addr, 2);
6536 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6537 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6538#else
6a6ae23f
AJ		 6539 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6540 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6541 tcg_gen_addi_tl(addr, addr, 2);
6542 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6543 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6544 tcg_gen_addi_tl(addr, addr, 2);
6545 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6546 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6547 tcg_gen_addi_tl(addr, addr, 2);
6548 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6549 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6550#endif
6a6ae23f 6551 tcg_temp_free(t0);
0487d6a8
JM		 6552}
6553
6a6ae23f
AJ		 6554static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6555{
6556 TCGv t0 = tcg_temp_new();
6557 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6558#if defined(TARGET_PPC64)
6559 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6560 tcg_gen_shli_tl(t0, t0, 16);
6561 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6562#else
6563 tcg_gen_shli_tl(t0, t0, 16);
6564 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6565 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6566#endif
6567 tcg_temp_free(t0);
0487d6a8
JM		 6568}
6569
6a6ae23f
AJ		 6570static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6571{
6572 TCGv t0 = tcg_temp_new();
6573 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6574#if defined(TARGET_PPC64)
6575 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6576 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6577#else
6578 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6579 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6580#endif
6581 tcg_temp_free(t0);
0487d6a8
JM		 6582}
6583
6a6ae23f
AJ		 6584static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6585{
6586 TCGv t0 = tcg_temp_new();
6587 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6588#if defined(TARGET_PPC64)
6589 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6590 tcg_gen_ext32u_tl(t0, t0);
6591 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6592#else
6593 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6594 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6595#endif
6596 tcg_temp_free(t0);
6597}
6598
6599static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6600{
6601 TCGv t0 = tcg_temp_new();
6602#if defined(TARGET_PPC64)
6603 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6604 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6605 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6606 tcg_gen_shli_tl(t0, t0, 16);
6607 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6608#else
6609 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6610 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6611 tcg_gen_addi_tl(addr, addr, 2);
6612 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6613 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6614#endif
6615 tcg_temp_free(t0);
6616}
6617
6618static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6619{
6620#if defined(TARGET_PPC64)
6621 TCGv t0 = tcg_temp_new();
6622 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6623 tcg_gen_addi_tl(addr, addr, 2);
6624 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6625 tcg_gen_shli_tl(t0, t0, 32);
6626 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6627 tcg_temp_free(t0);
6628#else
6629 gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6630 tcg_gen_addi_tl(addr, addr, 2);
6631 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6632#endif
6633}
6634
6635static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6636{
6637#if defined(TARGET_PPC64)
6638 TCGv t0 = tcg_temp_new();
6639 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6640 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6641 tcg_gen_addi_tl(addr, addr, 2);
6642 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6643 tcg_gen_shli_tl(t0, t0, 32);
6644 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6645 tcg_temp_free(t0);
6646#else
6647 gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6648 tcg_gen_addi_tl(addr, addr, 2);
6649 gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6650#endif
6651}
6652
6653static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6654{
6655 TCGv t0 = tcg_temp_new();
6656 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
0487d6a8 6657#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6658 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6659 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6660#else
6661 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6662 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6663#endif
6664 tcg_temp_free(t0);
6665}
6666
6667static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6668{
6669 TCGv t0 = tcg_temp_new();
6670#if defined(TARGET_PPC64)
6671 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6672 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6673 tcg_gen_shli_tl(t0, t0, 32);
6674 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6675 tcg_gen_addi_tl(addr, addr, 2);
6676 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6677 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6678 tcg_gen_shli_tl(t0, t0, 16);
6679 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6680#else
6681 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6682 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6683 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6684 tcg_gen_addi_tl(addr, addr, 2);
6685 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6686 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6687 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 6688#endif
6a6ae23f
AJ		 6689 tcg_temp_free(t0);
6690}
6691
6692static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6693{
6694#if defined(TARGET_PPC64)
6695 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
0487d6a8 6696#else
6a6ae23f
AJ		 6697 TCGv_i64 t0 = tcg_temp_new_i64();
6698 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6699 gen_qemu_st64(t0, addr, ctx->mem_idx);
6700 tcg_temp_free_i64(t0);
6701#endif
6702}
6703
6704static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6705{
0487d6a8 6706#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6707 TCGv t0 = tcg_temp_new();
6708 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6709 gen_qemu_st32(t0, addr, ctx->mem_idx);
6710 tcg_temp_free(t0);
6711#else
6712 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6713#endif
6714 tcg_gen_addi_tl(addr, addr, 4);
6715 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6716}
6717
6718static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6719{
6720 TCGv t0 = tcg_temp_new();
6721#if defined(TARGET_PPC64)
6722 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6723#else
6724 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6725#endif
6726 gen_qemu_st16(t0, addr, ctx->mem_idx);
6727 tcg_gen_addi_tl(addr, addr, 2);
6728#if defined(TARGET_PPC64)
6729 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6730 gen_qemu_st16(t0, addr, ctx->mem_idx);
6731#else
6732 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6733#endif
6734 tcg_gen_addi_tl(addr, addr, 2);
6735 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6736 gen_qemu_st16(t0, addr, ctx->mem_idx);
6737 tcg_temp_free(t0);
6738 tcg_gen_addi_tl(addr, addr, 2);
6739 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6740}
6741
6742static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6743{
6744 TCGv t0 = tcg_temp_new();
6745#if defined(TARGET_PPC64)
6746 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6747#else
6748 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6749#endif
6750 gen_qemu_st16(t0, addr, ctx->mem_idx);
6751 tcg_gen_addi_tl(addr, addr, 2);
6752 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6753 gen_qemu_st16(t0, addr, ctx->mem_idx);
6754 tcg_temp_free(t0);
6755}
6756
6757static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6758{
6759#if defined(TARGET_PPC64)
6760 TCGv t0 = tcg_temp_new();
6761 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6762 gen_qemu_st16(t0, addr, ctx->mem_idx);
6763 tcg_temp_free(t0);
6764#else
6765 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6766#endif
6767 tcg_gen_addi_tl(addr, addr, 2);
6768 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6769}
6770
6771static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6772{
6773#if defined(TARGET_PPC64)
6774 TCGv t0 = tcg_temp_new();
6775 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6776 gen_qemu_st32(t0, addr, ctx->mem_idx);
6777 tcg_temp_free(t0);
6778#else
6779 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6780#endif
6781}
6782
6783static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6784{
6785 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6786}
6787
6788#define GEN_SPEOP_LDST(name, opc2, sh) \
6789GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6790{ \
6791 TCGv t0; \
6792 if (unlikely(!ctx->spe_enabled)) { \
6793 GEN_EXCP_NO_AP(ctx); \
6794 return; \
6795 } \
6796 t0 = tcg_temp_new(); \
6797 if (Rc(ctx->opcode)) { \
6798 gen_addr_spe_imm_index(t0, ctx, sh); \
6799 } else { \
6800 gen_addr_reg_index(t0, ctx); \
6801 } \
6802 gen_op_##name(ctx, t0); \
6803 tcg_temp_free(t0); \
6804}
6805
6806GEN_SPEOP_LDST(evldd, 0x00, 3);
6807GEN_SPEOP_LDST(evldw, 0x01, 3);
6808GEN_SPEOP_LDST(evldh, 0x02, 3);
6809GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
6810GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
6811GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
6812GEN_SPEOP_LDST(evlwhe, 0x08, 2);
6813GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
6814GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
6815GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
6816GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
6817
6818GEN_SPEOP_LDST(evstdd, 0x10, 3);
6819GEN_SPEOP_LDST(evstdw, 0x11, 3);
6820GEN_SPEOP_LDST(evstdh, 0x12, 3);
6821GEN_SPEOP_LDST(evstwhe, 0x18, 2);
6822GEN_SPEOP_LDST(evstwho, 0x1A, 2);
6823GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
6824GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 6825
6826/* Multiply and add - TODO */
6827#if 0
6828GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6829GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6830GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6831GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6832GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6833GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6834GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6835GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6836GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6837GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6838GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6839GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6840
6841GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6842GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6843GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6844GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6845GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6846GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6847GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6848GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6849GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6850GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6851GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6852GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6853GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6854GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6855
6856GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6857GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6858GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6859GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6860GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6861GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6862
6863GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6864GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6865GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6866GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6867GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6868GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6869GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6870GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6871GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6872GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6873GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6874GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6875
6876GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6877GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6878GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6879GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6880GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6881
6882GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6883GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6884GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6885GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6886GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6887GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6888GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6889GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6890GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6891GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6892GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6893GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6894
6895GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6896GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6897GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6898GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6899GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6900#endif
6901
6902/*** SPE floating-point extension ***/
1c97856d
AJ		 6903#if defined(TARGET_PPC64)
6904#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 6905static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6906{ \
1c97856d
AJ		 6907 TCGv_i32 t0; \
6908 TCGv t1; \
6909 t0 = tcg_temp_new_i32(); \
6910 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6911 gen_helper_##name(t0, t0); \
6912 t1 = tcg_temp_new(); \
6913 tcg_gen_extu_i32_tl(t1, t0); \
6914 tcg_temp_free_i32(t0); \
6915 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6916 0xFFFFFFFF00000000ULL); \
6917 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6918 tcg_temp_free(t1); \
0487d6a8 6919}
1c97856d
AJ		 6920#define GEN_SPEFPUOP_CONV_32_64(name) \
6921static always_inline void gen_##name (DisasContext *ctx) \
6922{ \
6923 TCGv_i32 t0; \
6924 TCGv t1; \
6925 t0 = tcg_temp_new_i32(); \
6926 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
6927 t1 = tcg_temp_new(); \
6928 tcg_gen_extu_i32_tl(t1, t0); \
6929 tcg_temp_free_i32(t0); \
6930 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6931 0xFFFFFFFF00000000ULL); \
6932 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6933 tcg_temp_free(t1); \
6934}
6935#define GEN_SPEFPUOP_CONV_64_32(name) \
6936static always_inline void gen_##name (DisasContext *ctx) \
6937{ \
6938 TCGv_i32 t0 = tcg_temp_new_i32(); \
6939 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6940 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
6941 tcg_temp_free_i32(t0); \
6942}
6943#define GEN_SPEFPUOP_CONV_64_64(name) \
6944static always_inline void gen_##name (DisasContext *ctx) \
6945{ \
6946 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6947}
6948#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 6949static always_inline void gen_##name (DisasContext *ctx) \
6950{ \
1c97856d
AJ		 6951 TCGv_i32 t0, t1; \
6952 TCGv_i64 t2; \
57951c27
AJ		 6953 if (unlikely(!ctx->spe_enabled)) { \
6954 GEN_EXCP_NO_AP(ctx); \
6955 return; \
6956 } \
1c97856d
AJ		 6957 t0 = tcg_temp_new_i32(); \
6958 t1 = tcg_temp_new_i32(); \
6959 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6960 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6961 gen_helper_##name(t0, t0, t1); \
6962 tcg_temp_free_i32(t1); \
6963 t2 = tcg_temp_new(); \
6964 tcg_gen_extu_i32_tl(t2, t0); \
6965 tcg_temp_free_i32(t0); \
6966 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6967 0xFFFFFFFF00000000ULL); \
6968 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
6969 tcg_temp_free(t2); \
57951c27 6970}
1c97856d 6971#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 6972static always_inline void gen_##name (DisasContext *ctx) \
6973{ \
6974 if (unlikely(!ctx->spe_enabled)) { \
6975 GEN_EXCP_NO_AP(ctx); \
6976 return; \
6977 } \
1c97856d
AJ		 6978 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6979 cpu_gpr[rB(ctx->opcode)]); \
57951c27 6980}
1c97856d 6981#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 6982static always_inline void gen_##name (DisasContext *ctx) \
6983{ \
1c97856d 6984 TCGv_i32 t0, t1; \
57951c27
AJ		 6985 if (unlikely(!ctx->spe_enabled)) { \
6986 GEN_EXCP_NO_AP(ctx); \
6987 return; \
6988 } \
1c97856d
AJ		 6989 t0 = tcg_temp_new_i32(); \
6990 t1 = tcg_temp_new_i32(); \
6991 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6992 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6993 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
6994 tcg_temp_free_i32(t0); \
6995 tcg_temp_free_i32(t1); \
6996}
6997#define GEN_SPEFPUOP_COMP_64(name) \
6998static always_inline void gen_##name (DisasContext *ctx) \
6999{ \
7000 if (unlikely(!ctx->spe_enabled)) { \
7001 GEN_EXCP_NO_AP(ctx); \
7002 return; \
7003 } \
7004 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7005 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7006}
7007#else
7008#define GEN_SPEFPUOP_CONV_32_32(name) \
7009static always_inline void gen_##name (DisasContext *ctx) \
7010{ \
7011 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7012}
1c97856d
AJ		 7013#define GEN_SPEFPUOP_CONV_32_64(name) \
7014static always_inline void gen_##name (DisasContext *ctx) \
7015{ \
7016 TCGv_i64 t0 = tcg_temp_new_i64(); \
7017 gen_load_gpr64(t0, rB(ctx->opcode)); \
7018 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7019 tcg_temp_free_i64(t0); \
7020}
7021#define GEN_SPEFPUOP_CONV_64_32(name) \
7022static always_inline void gen_##name (DisasContext *ctx) \
7023{ \
7024 TCGv_i64 t0 = tcg_temp_new_i64(); \
7025 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7026 gen_store_gpr64(rD(ctx->opcode), t0); \
7027 tcg_temp_free_i64(t0); \
7028}
7029#define GEN_SPEFPUOP_CONV_64_64(name) \
7030static always_inline void gen_##name (DisasContext *ctx) \
7031{ \
7032 TCGv_i64 t0 = tcg_temp_new_i64(); \
7033 gen_load_gpr64(t0, rB(ctx->opcode)); \
7034 gen_helper_##name(t0, t0); \
7035 gen_store_gpr64(rD(ctx->opcode), t0); \
7036 tcg_temp_free_i64(t0); \
7037}
7038#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7039static always_inline void gen_##name (DisasContext *ctx) \
7040{ \
7041 if (unlikely(!ctx->spe_enabled)) { \
7042 GEN_EXCP_NO_AP(ctx); \
7043 return; \
7044 } \
7045 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7046 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7047}
7048#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7049static always_inline void gen_##name (DisasContext *ctx) \
7050{ \
7051 TCGv_i64 t0, t1; \
7052 if (unlikely(!ctx->spe_enabled)) { \
7053 GEN_EXCP_NO_AP(ctx); \
7054 return; \
7055 } \
7056 t0 = tcg_temp_new_i64(); \
7057 t1 = tcg_temp_new_i64(); \
7058 gen_load_gpr64(t0, rA(ctx->opcode)); \
7059 gen_load_gpr64(t1, rB(ctx->opcode)); \
7060 gen_helper_##name(t0, t0, t1); \
7061 gen_store_gpr64(rD(ctx->opcode), t0); \
7062 tcg_temp_free_i64(t0); \
7063 tcg_temp_free_i64(t1); \
7064}
7065#define GEN_SPEFPUOP_COMP_32(name) \
7066static always_inline void gen_##name (DisasContext *ctx) \
7067{ \
7068 if (unlikely(!ctx->spe_enabled)) { \
7069 GEN_EXCP_NO_AP(ctx); \
7070 return; \
7071 } \
7072 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7073 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7074}
7075#define GEN_SPEFPUOP_COMP_64(name) \
7076static always_inline void gen_##name (DisasContext *ctx) \
7077{ \
7078 TCGv_i64 t0, t1; \
7079 if (unlikely(!ctx->spe_enabled)) { \
7080 GEN_EXCP_NO_AP(ctx); \
7081 return; \
7082 } \
7083 t0 = tcg_temp_new_i64(); \
7084 t1 = tcg_temp_new_i64(); \
7085 gen_load_gpr64(t0, rA(ctx->opcode)); \
7086 gen_load_gpr64(t1, rB(ctx->opcode)); \
7087 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7088 tcg_temp_free_i64(t0); \
7089 tcg_temp_free_i64(t1); \
7090}
7091#endif
57951c27 7092
0487d6a8
JM		 7093/* Single precision floating-point vectors operations */
7094/* Arithmetic */
1c97856d
AJ		 7095GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7096GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7097GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7098GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7099static always_inline void gen_evfsabs (DisasContext *ctx)
7100{
7101 if (unlikely(!ctx->spe_enabled)) {
7102 GEN_EXCP_NO_AP(ctx);
7103 return;
7104 }
7105#if defined(TARGET_PPC64)
7106 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7107#else
7108 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7109 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7110#endif
7111}
7112static always_inline void gen_evfsnabs (DisasContext *ctx)
7113{
7114 if (unlikely(!ctx->spe_enabled)) {
7115 GEN_EXCP_NO_AP(ctx);
7116 return;
7117 }
7118#if defined(TARGET_PPC64)
7119 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7120#else
7121 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7122 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7123#endif
7124}
7125static always_inline void gen_evfsneg (DisasContext *ctx)
7126{
7127 if (unlikely(!ctx->spe_enabled)) {
7128 GEN_EXCP_NO_AP(ctx);
7129 return;
7130 }
7131#if defined(TARGET_PPC64)
7132 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7133#else
7134 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7135 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7136#endif
7137}
7138
0487d6a8 7139/* Conversion */
1c97856d
AJ		 7140GEN_SPEFPUOP_CONV_64_64(evfscfui);
7141GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7142GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7143GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7144GEN_SPEFPUOP_CONV_64_64(evfsctui);
7145GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7146GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7147GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7148GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7149GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7150
0487d6a8 7151/* Comparison */
1c97856d
AJ		 7152GEN_SPEFPUOP_COMP_64(evfscmpgt);
7153GEN_SPEFPUOP_COMP_64(evfscmplt);
7154GEN_SPEFPUOP_COMP_64(evfscmpeq);
7155GEN_SPEFPUOP_COMP_64(evfststgt);
7156GEN_SPEFPUOP_COMP_64(evfststlt);
7157GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7158
7159/* Opcodes definitions */
7160GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7161GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7162GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7163GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7164GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7165GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7166GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7167GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7168GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7169GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7170GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7171GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7172GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7173GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7174
7175/* Single precision floating-point operations */
7176/* Arithmetic */
1c97856d
AJ		 7177GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7178GEN_SPEFPUOP_ARITH2_32_32(efssub);
7179GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7180GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7181static always_inline void gen_efsabs (DisasContext *ctx)
7182{
7183 if (unlikely(!ctx->spe_enabled)) {
7184 GEN_EXCP_NO_AP(ctx);
7185 return;
7186 }
7187 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7188}
7189static always_inline void gen_efsnabs (DisasContext *ctx)
7190{
7191 if (unlikely(!ctx->spe_enabled)) {
7192 GEN_EXCP_NO_AP(ctx);
7193 return;
7194 }
7195 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7196}
7197static always_inline void gen_efsneg (DisasContext *ctx)
7198{
7199 if (unlikely(!ctx->spe_enabled)) {
7200 GEN_EXCP_NO_AP(ctx);
7201 return;
7202 }
7203 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7204}
7205
0487d6a8 7206/* Conversion */
1c97856d
AJ		 7207GEN_SPEFPUOP_CONV_32_32(efscfui);
7208GEN_SPEFPUOP_CONV_32_32(efscfsi);
7209GEN_SPEFPUOP_CONV_32_32(efscfuf);
7210GEN_SPEFPUOP_CONV_32_32(efscfsf);
7211GEN_SPEFPUOP_CONV_32_32(efsctui);
7212GEN_SPEFPUOP_CONV_32_32(efsctsi);
7213GEN_SPEFPUOP_CONV_32_32(efsctuf);
7214GEN_SPEFPUOP_CONV_32_32(efsctsf);
7215GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7216GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7217GEN_SPEFPUOP_CONV_32_64(efscfd);
7218
0487d6a8 7219/* Comparison */
1c97856d
AJ		 7220GEN_SPEFPUOP_COMP_32(efscmpgt);
7221GEN_SPEFPUOP_COMP_32(efscmplt);
7222GEN_SPEFPUOP_COMP_32(efscmpeq);
7223GEN_SPEFPUOP_COMP_32(efststgt);
7224GEN_SPEFPUOP_COMP_32(efststlt);
7225GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7226
7227/* Opcodes definitions */
05332d70 7228GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7229GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7230GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7231GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7232GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7233GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7234GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7235GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7236GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7237GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7238GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7239GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7240GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7241GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7242
7243/* Double precision floating-point operations */
7244/* Arithmetic */
1c97856d
AJ		 7245GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7246GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7247GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7248GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7249static always_inline void gen_efdabs (DisasContext *ctx)
7250{
7251 if (unlikely(!ctx->spe_enabled)) {
7252 GEN_EXCP_NO_AP(ctx);
7253 return;
7254 }
7255#if defined(TARGET_PPC64)
7256 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7257#else
7258 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7259#endif
7260}
7261static always_inline void gen_efdnabs (DisasContext *ctx)
7262{
7263 if (unlikely(!ctx->spe_enabled)) {
7264 GEN_EXCP_NO_AP(ctx);
7265 return;
7266 }
7267#if defined(TARGET_PPC64)
7268 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7269#else
7270 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7271#endif
7272}
7273static always_inline void gen_efdneg (DisasContext *ctx)
7274{
7275 if (unlikely(!ctx->spe_enabled)) {
7276 GEN_EXCP_NO_AP(ctx);
7277 return;
7278 }
7279#if defined(TARGET_PPC64)
7280 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7281#else
7282 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7283#endif
7284}
7285
0487d6a8 7286/* Conversion */
1c97856d
AJ		 7287GEN_SPEFPUOP_CONV_64_32(efdcfui);
7288GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7289GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7290GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7291GEN_SPEFPUOP_CONV_32_64(efdctui);
7292GEN_SPEFPUOP_CONV_32_64(efdctsi);
7293GEN_SPEFPUOP_CONV_32_64(efdctuf);
7294GEN_SPEFPUOP_CONV_32_64(efdctsf);
7295GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7296GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7297GEN_SPEFPUOP_CONV_64_32(efdcfs);
7298GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7299GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7300GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7301GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 7302
0487d6a8 7303/* Comparison */
1c97856d
AJ		 7304GEN_SPEFPUOP_COMP_64(efdcmpgt);
7305GEN_SPEFPUOP_COMP_64(efdcmplt);
7306GEN_SPEFPUOP_COMP_64(efdcmpeq);
7307GEN_SPEFPUOP_COMP_64(efdtstgt);
7308GEN_SPEFPUOP_COMP_64(efdtstlt);
7309GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 7310
7311/* Opcodes definitions */
7312GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7313GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7314GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7315GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7316GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7317GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7318GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7319GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7320GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7321GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7322GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7323GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7324GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7325GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7326GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7327GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 7328
79aceca5
FB		 7329/* End opcode list */
7330GEN_OPCODE_MARK(end);
7331
3fc6c082 7332#include "translate_init.c"
0411a972 7333#include "helper_regs.h"
79aceca5 7334
9a64fbe4 7335/*****************************************************************************/
3fc6c082 7336/* Misc PowerPC helpers */
36081602
JM		 7337void cpu_dump_state (CPUState *env, FILE *f,
7338 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7339 int flags)
79aceca5 7340{
3fc6c082
FB		 7341#define RGPL 4
7342#define RFPL 4
3fc6c082 7343
79aceca5
FB		 7344 int i;
7345
077fc206 7346 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 7347 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 7348 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7349 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 7350#if !defined(NO_TIMER_DUMP)
077fc206 7351 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 7352#if !defined(CONFIG_USER_ONLY)
7353 "DECR %08x"
7354#endif
7355 "\n",
077fc206 7356 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 7357#if !defined(CONFIG_USER_ONLY)
7358 , cpu_ppc_load_decr(env)
7359#endif
7360 );
077fc206 7361#endif
76a66253 7362 for (i = 0; i < 32; i++) {
3fc6c082
FB		 7363 if ((i & (RGPL - 1)) == 0)
7364 cpu_fprintf(f, "GPR%02d", i);
6b542af7 7365 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 7366 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 7367 cpu_fprintf(f, "\n");
76a66253 7368 }
3fc6c082 7369 cpu_fprintf(f, "CR ");
76a66253 7370 for (i = 0; i < 8; i++)
7fe48483
FB		 7371 cpu_fprintf(f, "%01x", env->crf[i]);
7372 cpu_fprintf(f, " [");
76a66253
JM		 7373 for (i = 0; i < 8; i++) {
7374 char a = '-';
7375 if (env->crf[i] & 0x08)
7376 a = 'L';
7377 else if (env->crf[i] & 0x04)
7378 a = 'G';
7379 else if (env->crf[i] & 0x02)
7380 a = 'E';
7fe48483 7381 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 7382 }
6b542af7 7383 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 7384 for (i = 0; i < 32; i++) {
7385 if ((i & (RFPL - 1)) == 0)
7386 cpu_fprintf(f, "FPR%02d", i);
26a76461 7387 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 7388 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 7389 cpu_fprintf(f, "\n");
79aceca5 7390 }
f2e63a42 7391#if !defined(CONFIG_USER_ONLY)
6b542af7 7392 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 7393 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 7394#endif
79aceca5 7395
3fc6c082
FB		 7396#undef RGPL
7397#undef RFPL
79aceca5
FB		 7398}
7399
76a66253
JM		 7400void cpu_dump_statistics (CPUState *env, FILE*f,
7401 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7402 int flags)
7403{
7404#if defined(DO_PPC_STATISTICS)
7405 opc_handler_t **t1, **t2, **t3, *handler;
7406 int op1, op2, op3;
7407
7408 t1 = env->opcodes;
7409 for (op1 = 0; op1 < 64; op1++) {
7410 handler = t1[op1];
7411 if (is_indirect_opcode(handler)) {
7412 t2 = ind_table(handler);
7413 for (op2 = 0; op2 < 32; op2++) {
7414 handler = t2[op2];
7415 if (is_indirect_opcode(handler)) {
7416 t3 = ind_table(handler);
7417 for (op3 = 0; op3 < 32; op3++) {
7418 handler = t3[op3];
7419 if (handler->count == 0)
7420 continue;
7421 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7422 "%016llx %lld\n",
7423 op1, op2, op3, op1, (op3 << 5) | op2,
7424 handler->oname,
7425 handler->count, handler->count);
7426 }
7427 } else {
7428 if (handler->count == 0)
7429 continue;
7430 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7431 "%016llx %lld\n",
7432 op1, op2, op1, op2, handler->oname,
7433 handler->count, handler->count);
7434 }
7435 }
7436 } else {
7437 if (handler->count == 0)
7438 continue;
7439 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7440 op1, op1, handler->oname,
7441 handler->count, handler->count);
7442 }
7443 }
7444#endif
7445}
7446
9a64fbe4 7447/*****************************************************************************/
2cfc5f17
TS		 7448static always_inline void gen_intermediate_code_internal (CPUState *env,
7449 TranslationBlock *tb,
7450 int search_pc)
79aceca5 7451{
9fddaa0c 7452 DisasContext ctx, *ctxp = &ctx;
79aceca5 7453 opc_handler_t **table, *handler;
0fa85d43 7454 target_ulong pc_start;
79aceca5 7455 uint16_t *gen_opc_end;
056401ea 7456 int supervisor, little_endian;
a1d1bb31 7457 CPUBreakpoint *bp;
79aceca5 7458 int j, lj = -1;
2e70f6ef
PB		 7459 int num_insns;
7460 int max_insns;
79aceca5
FB		 7461
7462 pc_start = tb->pc;
79aceca5 7463 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 7464#if defined(OPTIMIZE_FPRF_UPDATE)
7465 gen_fprf_ptr = gen_fprf_buf;
7466#endif
046d6672 7467 ctx.nip = pc_start;
79aceca5 7468 ctx.tb = tb;
e1833e1f 7469 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 7470 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 7471 supervisor = env->mmu_idx;
7472#if !defined(CONFIG_USER_ONLY)
2857068e 7473 ctx.supervisor = supervisor;
d9bce9d9 7474#endif
056401ea 7475 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 7476#if defined(TARGET_PPC64)
7477 ctx.sf_mode = msr_sf;
056401ea 7478 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 7479#else
056401ea 7480 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 7481#endif
3cc62370 7482 ctx.fpu_enabled = msr_fp;
a9d9eb8f 7483 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 7484 ctx.spe_enabled = msr_spe;
7485 else
7486 ctx.spe_enabled = 0;
a9d9eb8f
JM		 7487 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7488 ctx.altivec_enabled = msr_vr;
7489 else
7490 ctx.altivec_enabled = 0;
d26bfc9a 7491 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 7492 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 7493 else
8cbcb4fa 7494 ctx.singlestep_enabled = 0;
d26bfc9a 7495 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 7496 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7497 if (unlikely(env->singlestep_enabled))
7498 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 7499#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 7500 /* Single step trace mode */
7501 msr_se = 1;
7502#endif
2e70f6ef
PB		 7503 num_insns = 0;
7504 max_insns = tb->cflags & CF_COUNT_MASK;
7505 if (max_insns == 0)
7506 max_insns = CF_COUNT_MASK;
7507
7508 gen_icount_start();
9a64fbe4 7509 /* Set env in case of segfault during code fetch */
e1833e1f 7510 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 7511 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7512 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 7513 if (bp->pc == ctx.nip) {
5fafdf24 7514 gen_update_nip(&ctx, ctx.nip);
64adab3f 7515 gen_helper_raise_debug();
ea4e754f
FB		 7516 break;
7517 }
7518 }
7519 }
76a66253 7520 if (unlikely(search_pc)) {
79aceca5
FB		 7521 j = gen_opc_ptr - gen_opc_buf;
7522 if (lj < j) {
7523 lj++;
7524 while (lj < j)
7525 gen_opc_instr_start[lj++] = 0;
046d6672 7526 gen_opc_pc[lj] = ctx.nip;
79aceca5 7527 gen_opc_instr_start[lj] = 1;
2e70f6ef 7528 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 7529 }
7530 }
9fddaa0c
FB		 7531#if defined PPC_DEBUG_DISAS
7532 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 7533 fprintf(logfile, "----------------\n");
1b9eb036 7534 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 7535 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 7536 }
7537#endif
2e70f6ef
PB		 7538 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7539 gen_io_start();
056401ea
JM		 7540 if (unlikely(little_endian)) {
7541 ctx.opcode = bswap32(ldl_code(ctx.nip));
7542 } else {
7543 ctx.opcode = ldl_code(ctx.nip);
111bfab3 7544 }
9fddaa0c
FB		 7545#if defined PPC_DEBUG_DISAS
7546 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 7547 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 7548 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 7549 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 7550 }
7551#endif
046d6672 7552 ctx.nip += 4;
3fc6c082 7553 table = env->opcodes;
2e70f6ef 7554 num_insns++;
79aceca5
FB		 7555 handler = table[opc1(ctx.opcode)];
7556 if (is_indirect_opcode(handler)) {
7557 table = ind_table(handler);
7558 handler = table[opc2(ctx.opcode)];
7559 if (is_indirect_opcode(handler)) {
7560 table = ind_table(handler);
7561 handler = table[opc3(ctx.opcode)];
7562 }
7563 }
7564 /* Is opcode *REALLY* valid ? */
76a66253 7565 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7566 if (loglevel != 0) {
76a66253 7567 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 7568 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 7569 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7570 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7571 } else {
7572 printf("invalid/unsupported opcode: "
6b542af7 7573 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 7574 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7575 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7576 }
76a66253
JM		 7577 } else {
7578 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7579 if (loglevel != 0) {
79aceca5 7580 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 7581 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 7582 ctx.opcode & handler->inval, opc1(ctx.opcode),
7583 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7584 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7585 } else {
7586 printf("invalid bits: %08x for opcode: "
6b542af7 7587 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 7588 ctx.opcode & handler->inval, opc1(ctx.opcode),
7589 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7590 ctx.opcode, ctx.nip - 4);
76a66253 7591 }
e1833e1f 7592 GEN_EXCP_INVAL(ctxp);
4b3686fa 7593 break;
79aceca5 7594 }
79aceca5 7595 }
4b3686fa 7596 (*(handler->handler))(&ctx);
76a66253
JM		 7597#if defined(DO_PPC_STATISTICS)
7598 handler->count++;
7599#endif
9a64fbe4 7600 /* Check trace mode exceptions */
8cbcb4fa
AJ		 7601 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7602 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7603 ctx.exception != POWERPC_SYSCALL &&
7604 ctx.exception != POWERPC_EXCP_TRAP &&
7605 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 7606 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 7607 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 7608 (env->singlestep_enabled) ||
7609 num_insns >= max_insns)) {
d26bfc9a
JM		 7610 /* if we reach a page boundary or are single stepping, stop
7611 * generation
7612 */
8dd4983c 7613 break;
76a66253 7614 }
3fc6c082
FB		 7615#if defined (DO_SINGLE_STEP)
7616 break;
7617#endif
7618 }
2e70f6ef
PB		 7619 if (tb->cflags & CF_LAST_IO)
7620 gen_io_end();
e1833e1f 7621 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7622 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7623 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 7624 if (unlikely(env->singlestep_enabled)) {
7625 gen_update_nip(&ctx, ctx.nip);
64adab3f 7626 gen_helper_raise_debug();
8cbcb4fa 7627 }
76a66253 7628 /* Generate the return instruction */
57fec1fe 7629 tcg_gen_exit_tb(0);
9a64fbe4 7630 }
2e70f6ef 7631 gen_icount_end(tb, num_insns);
79aceca5 7632 *gen_opc_ptr = INDEX_op_end;
76a66253 7633 if (unlikely(search_pc)) {
9a64fbe4
FB		 7634 j = gen_opc_ptr - gen_opc_buf;
7635 lj++;
7636 while (lj <= j)
7637 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7638 } else {
046d6672 7639 tb->size = ctx.nip - pc_start;
2e70f6ef 7640 tb->icount = num_insns;
9a64fbe4 7641 }
d9bce9d9 7642#if defined(DEBUG_DISAS)
9fddaa0c 7643 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7644 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7645 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7646 }
7647 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7648 int flags;
237c0af0 7649 flags = env->bfd_mach;
056401ea 7650 flags |= little_endian << 16;
0fa85d43 7651 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7652 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7653 fprintf(logfile, "\n");
9fddaa0c 7654 }
79aceca5 7655#endif
79aceca5
FB		 7656}
7657
2cfc5f17 7658void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 7659{
2cfc5f17 7660 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 7661}
7662
2cfc5f17 7663void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7664{
2cfc5f17 7665 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7666}
d2856f1a
AJ		 7667
7668void gen_pc_load(CPUState *env, TranslationBlock *tb,
7669 unsigned long searched_pc, int pc_pos, void *puc)
7670{
d2856f1a 7671 env->nip = gen_opc_pc[pc_pos];
d2856f1a 7672}
Qemu copy for testing