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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
f10dc08e 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
79aceca5 32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
79aceca5 38//#define DO_SINGLE_STEP
9fddaa0c 39//#define PPC_DEBUG_DISAS
76a66253 40//#define DO_PPC_STATISTICS
7c58044c 41//#define OPTIMIZE_FPRF_UPDATE
79aceca5 42
a750fc0b
JM		 43/*****************************************************************************/
44/* Code translation helpers */
c53be334 45
f78fb44e
AJ		 46/* global register indexes */
47static TCGv cpu_env;
1d542695 48static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 49#if !defined(TARGET_PPC64)
1d542695 50 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 51#endif
a5e26afa 52 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
f78fb44e
AJ		 55static TCGv cpu_gpr[32];
56#if !defined(TARGET_PPC64)
57static TCGv cpu_gprh[32];
58#endif
a5e26afa 59static TCGv cpu_fpr[32];
1d542695 60static TCGv cpu_avrh[32], cpu_avrl[32];
47e4661c 61static TCGv cpu_crf[8];
bd568f18 62static TCGv cpu_nip;
cfdcd37a
AJ		 63static TCGv cpu_ctr;
64static TCGv cpu_lr;
f78fb44e
AJ		 65
66/* dyngen register indexes */
67static TCGv cpu_T[3];
68#if defined(TARGET_PPC64)
69#define cpu_T64 cpu_T
70#else
71static TCGv cpu_T64[3];
72#endif
a5e26afa 73static TCGv cpu_FT[3];
1d542695 74static TCGv cpu_AVRh[3], cpu_AVRl[3];
2e70f6ef
PB		 75
76#include "gen-icount.h"
77
78void ppc_translate_init(void)
79{
f78fb44e
AJ		 80 int i;
81 char* p;
b2437bf2 82 static int done_init = 0;
f78fb44e 83
2e70f6ef
PB		 84 if (done_init)
85 return;
f78fb44e 86
2e70f6ef 87 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
1c73fe5b
AJ		 88#if TARGET_LONG_BITS > HOST_LONG_BITS
89 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
90 TCG_AREG0, offsetof(CPUState, t0), "T0");
91 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
92 TCG_AREG0, offsetof(CPUState, t1), "T1");
93 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
94 TCG_AREG0, offsetof(CPUState, t2), "T2");
95#else
96 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
97 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
98 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
99#endif
f78fb44e
AJ		 100#if !defined(TARGET_PPC64)
101 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 102 TCG_AREG0, offsetof(CPUState, t0_64),
f78fb44e
AJ		 103 "T0_64");
104 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 105 TCG_AREG0, offsetof(CPUState, t1_64),
f78fb44e
AJ		 106 "T1_64");
107 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 108 TCG_AREG0, offsetof(CPUState, t2_64),
f78fb44e
AJ		 109 "T2_64");
110#endif
a5e26afa
AJ		 111
112 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
113 offsetof(CPUState, ft0), "FT0");
114 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
115 offsetof(CPUState, ft1), "FT1");
116 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
117 offsetof(CPUState, ft2), "FT2");
118
1d542695
AJ		 119 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
120 offsetof(CPUState, avr0.u64[0]), "AVR0H");
121 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
122 offsetof(CPUState, avr0.u64[1]), "AVR0L");
123 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124 offsetof(CPUState, avr1.u64[0]), "AVR1H");
125 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126 offsetof(CPUState, avr1.u64[1]), "AVR1L");
127 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128 offsetof(CPUState, avr2.u64[0]), "AVR2H");
129 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
130 offsetof(CPUState, avr2.u64[1]), "AVR2L");
131
f78fb44e 132 p = cpu_reg_names;
47e4661c
AJ		 133
134 for (i = 0; i < 8; i++) {
135 sprintf(p, "crf%d", i);
136 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
137 offsetof(CPUState, crf[i]), p);
138 p += 5;
139 }
140
f78fb44e
AJ		 141 for (i = 0; i < 32; i++) {
142 sprintf(p, "r%d", i);
143 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
144 offsetof(CPUState, gpr[i]), p);
145 p += (i < 10) ? 3 : 4;
146#if !defined(TARGET_PPC64)
147 sprintf(p, "r%dH", i);
148 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
149 offsetof(CPUState, gprh[i]), p);
150 p += (i < 10) ? 4 : 5;
151#endif
1d542695 152
a5e26afa
AJ		 153 sprintf(p, "fp%d", i);
154 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
155 offsetof(CPUState, fpr[i]), p);
ec1ac72d 156 p += (i < 10) ? 4 : 5;
a5e26afa 157
1d542695
AJ		 158 sprintf(p, "avr%dH", i);
159 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
160 offsetof(CPUState, avr[i].u64[0]), p);
161 p += (i < 10) ? 6 : 7;
ec1ac72d 162
1d542695
AJ		 163 sprintf(p, "avr%dL", i);
164 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
165 offsetof(CPUState, avr[i].u64[1]), p);
166 p += (i < 10) ? 6 : 7;
f78fb44e 167 }
f10dc08e 168
bd568f18
AJ		 169 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
170 offsetof(CPUState, nip), "nip");
171
cfdcd37a
AJ		 172 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
173 offsetof(CPUState, ctr), "ctr");
174
175 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
176 offsetof(CPUState, lr), "lr");
177
f10dc08e
AJ		 178 /* register helpers */
179#undef DEF_HELPER
180#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
181#include "helper.h"
182
2e70f6ef
PB		 183 done_init = 1;
184}
185
7c58044c
JM		 186#if defined(OPTIMIZE_FPRF_UPDATE)
187static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
188static uint16_t **gen_fprf_ptr;
189#endif
79aceca5 190
79aceca5
FB		 191/* internal defines */
192typedef struct DisasContext {
193 struct TranslationBlock *tb;
0fa85d43 194 target_ulong nip;
79aceca5 195 uint32_t opcode;
9a64fbe4 196 uint32_t exception;
3cc62370
FB		 197 /* Routine used to access memory */
198 int mem_idx;
199 /* Translation flags */
9a64fbe4 200#if !defined(CONFIG_USER_ONLY)
79aceca5 201 int supervisor;
d9bce9d9
JM		 202#endif
203#if defined(TARGET_PPC64)
204 int sf_mode;
9a64fbe4 205#endif
3cc62370 206 int fpu_enabled;
a9d9eb8f 207 int altivec_enabled;
0487d6a8 208 int spe_enabled;
3fc6c082 209 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 210 int singlestep_enabled;
d63001d1 211 int dcache_line_size;
79aceca5
FB		 212} DisasContext;
213
3fc6c082 214struct opc_handler_t {
79aceca5
FB		 215 /* invalid bits */
216 uint32_t inval;
9a64fbe4 217 /* instruction type */
0487d6a8 218 uint64_t type;
79aceca5
FB		 219 /* handler */
220 void (*handler)(DisasContext *ctx);
a750fc0b 221#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 222 const char *oname;
a750fc0b
JM		 223#endif
224#if defined(DO_PPC_STATISTICS)
76a66253
JM		 225 uint64_t count;
226#endif
3fc6c082 227};
79aceca5 228
b068d6a7 229static always_inline void gen_set_Rc0 (DisasContext *ctx)
76a66253 230{
d9bce9d9
JM		 231#if defined(TARGET_PPC64)
232 if (ctx->sf_mode)
233 gen_op_cmpi_64(0);
234 else
235#endif
236 gen_op_cmpi(0);
76a66253
JM		 237 gen_op_set_Rc0();
238}
239
7c58044c
JM		 240static always_inline void gen_reset_fpstatus (void)
241{
242#ifdef CONFIG_SOFTFLOAT
243 gen_op_reset_fpstatus();
244#endif
245}
246
247static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
248{
249 if (set_fprf != 0) {
250 /* This case might be optimized later */
251#if defined(OPTIMIZE_FPRF_UPDATE)
252 *gen_fprf_ptr++ = gen_opc_ptr;
253#endif
254 gen_op_compute_fprf(1);
255 if (unlikely(set_rc))
47e4661c 256 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 257 gen_op_float_check_status();
258 } else if (unlikely(set_rc)) {
259 /* We always need to compute fpcc */
260 gen_op_compute_fprf(0);
47e4661c 261 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 262 if (set_fprf)
263 gen_op_float_check_status();
264 }
265}
266
267static always_inline void gen_optimize_fprf (void)
268{
269#if defined(OPTIMIZE_FPRF_UPDATE)
270 uint16_t **ptr;
271
272 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
273 *ptr = INDEX_op_nop1;
274 gen_fprf_ptr = gen_fprf_buf;
275#endif
276}
277
b068d6a7 278static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 279{
280#if defined(TARGET_PPC64)
281 if (ctx->sf_mode)
bd568f18 282 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 283 else
284#endif
bd568f18 285 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 286}
287
e1833e1f 288#define GEN_EXCP(ctx, excp, error) \
79aceca5 289do { \
e1833e1f 290 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 291 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 292 } \
293 gen_op_raise_exception_err((excp), (error)); \
294 ctx->exception = (excp); \
79aceca5
FB		 295} while (0)
296
e1833e1f
JM		 297#define GEN_EXCP_INVAL(ctx) \
298GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
299 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 300
e1833e1f
JM		 301#define GEN_EXCP_PRIVOPC(ctx) \
302GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
303 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 304
e1833e1f
JM		 305#define GEN_EXCP_PRIVREG(ctx) \
306GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
307 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
308
309#define GEN_EXCP_NO_FP(ctx) \
310GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
311
312#define GEN_EXCP_NO_AP(ctx) \
313GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 314
a9d9eb8f
JM		 315#define GEN_EXCP_NO_VR(ctx) \
316GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
317
f24e5695 318/* Stop translation */
b068d6a7 319static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 320{
d9bce9d9 321 gen_update_nip(ctx, ctx->nip);
e1833e1f 322 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 323}
324
f24e5695 325/* No need to update nip here, as execution flow will change */
b068d6a7 326static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 327{
e1833e1f 328 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 329}
330
79aceca5
FB		 331#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
332static void gen_##name (DisasContext *ctx); \
333GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
334static void gen_##name (DisasContext *ctx)
335
c7697e1f
JM		 336#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
337static void gen_##name (DisasContext *ctx); \
338GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
339static void gen_##name (DisasContext *ctx)
340
79aceca5
FB		 341typedef struct opcode_t {
342 unsigned char opc1, opc2, opc3;
1235fc06 343#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 344 unsigned char pad[5];
345#else
346 unsigned char pad[1];
347#endif
79aceca5 348 opc_handler_t handler;
b55266b5 349 const char *oname;
79aceca5
FB		 350} opcode_t;
351
a750fc0b 352/*****************************************************************************/
79aceca5
FB		 353/*** Instruction decoding ***/
354#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 355static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 356{ \
357 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
358}
359
360#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 361static always_inline int32_t name (uint32_t opcode) \
79aceca5 362{ \
18fba28c 363 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 364}
365
366/* Opcode part 1 */
367EXTRACT_HELPER(opc1, 26, 6);
368/* Opcode part 2 */
369EXTRACT_HELPER(opc2, 1, 5);
370/* Opcode part 3 */
371EXTRACT_HELPER(opc3, 6, 5);
372/* Update Cr0 flags */
373EXTRACT_HELPER(Rc, 0, 1);
374/* Destination */
375EXTRACT_HELPER(rD, 21, 5);
376/* Source */
377EXTRACT_HELPER(rS, 21, 5);
378/* First operand */
379EXTRACT_HELPER(rA, 16, 5);
380/* Second operand */
381EXTRACT_HELPER(rB, 11, 5);
382/* Third operand */
383EXTRACT_HELPER(rC, 6, 5);
384/*** Get CRn ***/
385EXTRACT_HELPER(crfD, 23, 3);
386EXTRACT_HELPER(crfS, 18, 3);
387EXTRACT_HELPER(crbD, 21, 5);
388EXTRACT_HELPER(crbA, 16, 5);
389EXTRACT_HELPER(crbB, 11, 5);
390/* SPR / TBL */
3fc6c082 391EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 392static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 393{
394 uint32_t sprn = _SPR(opcode);
395
396 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
397}
79aceca5
FB		 398/*** Get constants ***/
399EXTRACT_HELPER(IMM, 12, 8);
400/* 16 bits signed immediate value */
401EXTRACT_SHELPER(SIMM, 0, 16);
402/* 16 bits unsigned immediate value */
403EXTRACT_HELPER(UIMM, 0, 16);
404/* Bit count */
405EXTRACT_HELPER(NB, 11, 5);
406/* Shift count */
407EXTRACT_HELPER(SH, 11, 5);
408/* Mask start */
409EXTRACT_HELPER(MB, 6, 5);
410/* Mask end */
411EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 412/* Trap operand */
413EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 414
415EXTRACT_HELPER(CRM, 12, 8);
416EXTRACT_HELPER(FM, 17, 8);
417EXTRACT_HELPER(SR, 16, 4);
e4bb997e 418EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 419
79aceca5
FB		 420/*** Jump target decoding ***/
421/* Displacement */
422EXTRACT_SHELPER(d, 0, 16);
423/* Immediate address */
b068d6a7 424static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 425{
426 return (opcode >> 0) & 0x03FFFFFC;
427}
428
b068d6a7 429static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 430{
431 return (opcode >> 0) & 0xFFFC;
432}
433
434EXTRACT_HELPER(BO, 21, 5);
435EXTRACT_HELPER(BI, 16, 5);
436/* Absolute/relative address */
437EXTRACT_HELPER(AA, 1, 1);
438/* Link */
439EXTRACT_HELPER(LK, 0, 1);
440
441/* Create a mask between <start> and <end> bits */
b068d6a7 442static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 443{
76a66253 444 target_ulong ret;
79aceca5 445
76a66253
JM		 446#if defined(TARGET_PPC64)
447 if (likely(start == 0)) {
6f2d8978 448 ret = UINT64_MAX << (63 - end);
76a66253 449 } else if (likely(end == 63)) {
6f2d8978 450 ret = UINT64_MAX >> start;
76a66253
JM		 451 }
452#else
453 if (likely(start == 0)) {
6f2d8978 454 ret = UINT32_MAX << (31 - end);
76a66253 455 } else if (likely(end == 31)) {
6f2d8978 456 ret = UINT32_MAX >> start;
76a66253
JM		 457 }
458#endif
459 else {
460 ret = (((target_ulong)(-1ULL)) >> (start)) ^
461 (((target_ulong)(-1ULL) >> (end)) >> 1);
462 if (unlikely(start > end))
463 return ~ret;
464 }
79aceca5
FB		 465
466 return ret;
467}
468
a750fc0b
JM		 469/*****************************************************************************/
470/* PowerPC Instructions types definitions */
471enum {
1b413d55 472 PPC_NONE = 0x0000000000000000ULL,
12de9a39 473 /* PowerPC base instructions set */
1b413d55
JM		 474 PPC_INSNS_BASE = 0x0000000000000001ULL,
475 /* integer operations instructions */
a750fc0b 476#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 477 /* flow control instructions */
a750fc0b 478#define PPC_FLOW PPC_INSNS_BASE
1b413d55 479 /* virtual memory instructions */
a750fc0b 480#define PPC_MEM PPC_INSNS_BASE
1b413d55 481 /* ld/st with reservation instructions */
a750fc0b 482#define PPC_RES PPC_INSNS_BASE
1b413d55 483 /* spr/msr access instructions */
a750fc0b 484#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 485 /* Deprecated instruction sets */
486 /* Original POWER instruction set */
f610349f 487 PPC_POWER = 0x0000000000000002ULL,
1b413d55 488 /* POWER2 instruction set extension */
f610349f 489 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 490 /* Power RTC support */
f610349f 491 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 492 /* Power-to-PowerPC bridge (601) */
f610349f 493 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 494 /* 64 bits PowerPC instruction set */
f610349f 495 PPC_64B = 0x0000000000000020ULL,
1b413d55 496 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 497 PPC_64BX = 0x0000000000000040ULL,
1b413d55 498 /* 64 bits hypervisor extensions */
f610349f 499 PPC_64H = 0x0000000000000080ULL,
1b413d55 500 /* New wait instruction (PowerPC 2.0x) */
f610349f 501 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 502 /* Time base mftb instruction */
f610349f 503 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 504
505 /* Fixed-point unit extensions */
506 /* PowerPC 602 specific */
f610349f 507 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 508 /* isel instruction */
509 PPC_ISEL = 0x0000000000000800ULL,
510 /* popcntb instruction */
511 PPC_POPCNTB = 0x0000000000001000ULL,
512 /* string load / store */
513 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 514
515 /* Floating-point unit extensions */
516 /* Optional floating point instructions */
517 PPC_FLOAT = 0x0000000000010000ULL,
518 /* New floating-point extensions (PowerPC 2.0x) */
519 PPC_FLOAT_EXT = 0x0000000000020000ULL,
520 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
521 PPC_FLOAT_FRES = 0x0000000000080000ULL,
522 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
523 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
524 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
525 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
526
527 /* Vector/SIMD extensions */
528 /* Altivec support */
529 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 530 /* PowerPC 2.03 SPE extension */
05332d70 531 PPC_SPE = 0x0000000002000000ULL,
1b413d55 532 /* PowerPC 2.03 SPE floating-point extension */
05332d70 533 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 534
12de9a39 535 /* Optional memory control instructions */
1b413d55
JM		 536 PPC_MEM_TLBIA = 0x0000000010000000ULL,
537 PPC_MEM_TLBIE = 0x0000000020000000ULL,
538 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
539 /* sync instruction */
540 PPC_MEM_SYNC = 0x0000000080000000ULL,
541 /* eieio instruction */
542 PPC_MEM_EIEIO = 0x0000000100000000ULL,
543
544 /* Cache control instructions */
c8623f2e 545 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 546 /* icbi instruction */
05332d70 547 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 548 /* dcbz instruction with fixed cache line size */
05332d70 549 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 550 /* dcbz instruction with tunable cache line size */
05332d70 551 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 552 /* dcba instruction */
05332d70
JM		 553 PPC_CACHE_DCBA = 0x0000002000000000ULL,
554 /* Freescale cache locking instructions */
555 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 556
557 /* MMU related extensions */
558 /* external control instructions */
05332d70 559 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 560 /* segment register access instructions */
05332d70 561 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 562 /* PowerPC 6xx TLB management instructions */
05332d70 563 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 564 /* PowerPC 74xx TLB management instructions */
05332d70 565 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 566 /* PowerPC 40x TLB management instructions */
05332d70 567 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 568 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 569 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 570 /* SLB management */
05332d70 571 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 572
12de9a39 573 /* Embedded PowerPC dedicated instructions */
05332d70 574 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 575 /* PowerPC 40x exception model */
05332d70 576 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 577 /* PowerPC 405 Mac instructions */
05332d70 578 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 579 /* PowerPC 440 specific instructions */
05332d70 580 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 581 /* BookE (embedded) PowerPC specification */
05332d70
JM		 582 PPC_BOOKE = 0x0010000000000000ULL,
583 /* mfapidi instruction */
584 PPC_MFAPIDI = 0x0020000000000000ULL,
585 /* tlbiva instruction */
586 PPC_TLBIVA = 0x0040000000000000ULL,
587 /* tlbivax instruction */
588 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 589 /* PowerPC 4xx dedicated instructions */
05332d70 590 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 591 /* PowerPC 40x ibct instructions */
05332d70 592 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 593 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 594 PPC_RFMCI = 0x0400000000000000ULL,
595 /* rfdi instruction */
596 PPC_RFDI = 0x0800000000000000ULL,
597 /* DCR accesses */
598 PPC_DCR = 0x1000000000000000ULL,
599 /* DCR extended accesse */
600 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 601 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 602 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 603};
604
605/*****************************************************************************/
606/* PowerPC instructions table */
3fc6c082
FB		 607#if HOST_LONG_BITS == 64
608#define OPC_ALIGN 8
609#else
610#define OPC_ALIGN 4
611#endif
1b039c09 612#if defined(__APPLE__)
d9bce9d9 613#define OPCODES_SECTION \
3fc6c082 614 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 615#else
d9bce9d9 616#define OPCODES_SECTION \
3fc6c082 617 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 618#endif
619
76a66253 620#if defined(DO_PPC_STATISTICS)
79aceca5 621#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 622OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 623 .opc1 = op1, \
624 .opc2 = op2, \
625 .opc3 = op3, \
18fba28c 626 .pad = { 0, }, \
79aceca5
FB		 627 .handler = { \
628 .inval = invl, \
9a64fbe4 629 .type = _typ, \
79aceca5 630 .handler = &gen_##name, \
76a66253 631 .oname = stringify(name), \
79aceca5 632 }, \
3fc6c082 633 .oname = stringify(name), \
79aceca5 634}
c7697e1f
JM		 635#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
636OPCODES_SECTION opcode_t opc_##name = { \
637 .opc1 = op1, \
638 .opc2 = op2, \
639 .opc3 = op3, \
640 .pad = { 0, }, \
641 .handler = { \
642 .inval = invl, \
643 .type = _typ, \
644 .handler = &gen_##name, \
645 .oname = onam, \
646 }, \
647 .oname = onam, \
648}
76a66253
JM		 649#else
650#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
651OPCODES_SECTION opcode_t opc_##name = { \
652 .opc1 = op1, \
653 .opc2 = op2, \
654 .opc3 = op3, \
655 .pad = { 0, }, \
656 .handler = { \
657 .inval = invl, \
658 .type = _typ, \
659 .handler = &gen_##name, \
660 }, \
661 .oname = stringify(name), \
662}
c7697e1f
JM		 663#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
664OPCODES_SECTION opcode_t opc_##name = { \
665 .opc1 = op1, \
666 .opc2 = op2, \
667 .opc3 = op3, \
668 .pad = { 0, }, \
669 .handler = { \
670 .inval = invl, \
671 .type = _typ, \
672 .handler = &gen_##name, \
673 }, \
674 .oname = onam, \
675}
76a66253 676#endif
79aceca5
FB		 677
678#define GEN_OPCODE_MARK(name) \
18fba28c 679OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 680 .opc1 = 0xFF, \
681 .opc2 = 0xFF, \
682 .opc3 = 0xFF, \
18fba28c 683 .pad = { 0, }, \
79aceca5
FB		 684 .handler = { \
685 .inval = 0x00000000, \
9a64fbe4 686 .type = 0x00, \
79aceca5
FB		 687 .handler = NULL, \
688 }, \
3fc6c082 689 .oname = stringify(name), \
79aceca5
FB		 690}
691
692/* Start opcode list */
693GEN_OPCODE_MARK(start);
694
695/* Invalid instruction */
9a64fbe4
FB		 696GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
697{
e1833e1f 698 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 699}
700
79aceca5
FB		 701static opc_handler_t invalid_handler = {
702 .inval = 0xFFFFFFFF,
9a64fbe4 703 .type = PPC_NONE,
79aceca5
FB		 704 .handler = gen_invalid,
705};
706
707/*** Integer arithmetic ***/
d9bce9d9
JM		 708#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
709GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 710{ \
f78fb44e
AJ		 711 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
712 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 713 gen_op_##name(); \
f78fb44e 714 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 715 if (unlikely(Rc(ctx->opcode) != 0)) \
716 gen_set_Rc0(ctx); \
79aceca5
FB		 717}
718
d9bce9d9
JM		 719#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
720GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 721{ \
f78fb44e
AJ		 722 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
723 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 724 gen_op_##name(); \
f78fb44e 725 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 726 if (unlikely(Rc(ctx->opcode) != 0)) \
727 gen_set_Rc0(ctx); \
79aceca5
FB		 728}
729
d9bce9d9
JM		 730#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
731GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 732{ \
f78fb44e 733 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 734 gen_op_##name(); \
f78fb44e 735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 736 if (unlikely(Rc(ctx->opcode) != 0)) \
737 gen_set_Rc0(ctx); \
79aceca5 738}
d9bce9d9
JM		 739#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
740GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 741{ \
f78fb44e 742 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 743 gen_op_##name(); \
f78fb44e 744 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 745 if (unlikely(Rc(ctx->opcode) != 0)) \
746 gen_set_Rc0(ctx); \
79aceca5
FB		 747}
748
749/* Two operands arithmetic functions */
d9bce9d9
JM		 750#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
751__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
752__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
753
754/* Two operands arithmetic functions with no overflow allowed */
755#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
756__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
757
758/* One operand arithmetic functions */
759#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
760__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
761__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
762
763#if defined(TARGET_PPC64)
764#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
765GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
766{ \
f78fb44e
AJ		 767 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
768 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 769 if (ctx->sf_mode) \
770 gen_op_##name##_64(); \
771 else \
772 gen_op_##name(); \
f78fb44e 773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 774 if (unlikely(Rc(ctx->opcode) != 0)) \
775 gen_set_Rc0(ctx); \
776}
777
778#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
779GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
780{ \
f78fb44e
AJ		 781 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
782 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 783 if (ctx->sf_mode) \
784 gen_op_##name##_64(); \
785 else \
786 gen_op_##name(); \
f78fb44e 787 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 788 if (unlikely(Rc(ctx->opcode) != 0)) \
789 gen_set_Rc0(ctx); \
790}
791
792#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
793GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
794{ \
f78fb44e 795 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 796 if (ctx->sf_mode) \
797 gen_op_##name##_64(); \
798 else \
799 gen_op_##name(); \
f78fb44e 800 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 801 if (unlikely(Rc(ctx->opcode) != 0)) \
802 gen_set_Rc0(ctx); \
803}
804#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
805GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
806{ \
f78fb44e 807 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 808 if (ctx->sf_mode) \
809 gen_op_##name##_64(); \
810 else \
811 gen_op_##name(); \
f78fb44e 812 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 813 if (unlikely(Rc(ctx->opcode) != 0)) \
814 gen_set_Rc0(ctx); \
815}
816
817/* Two operands arithmetic functions */
818#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
819__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
820__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 821
822/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 823#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
824__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 825
826/* One operand arithmetic functions */
d9bce9d9
JM		 827#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
828__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
829__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
830#else
831#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
832#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
833#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
834#endif
79aceca5
FB		 835
836/* add add. addo addo. */
39dd32ee
AJ		 837static always_inline void gen_op_add (void)
838{
839 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
840}
b068d6a7 841static always_inline void gen_op_addo (void)
d9bce9d9 842{
e55fd934 843 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 844 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 845 gen_op_check_addo();
846}
847#if defined(TARGET_PPC64)
848#define gen_op_add_64 gen_op_add
b068d6a7 849static always_inline void gen_op_addo_64 (void)
d9bce9d9 850{
e55fd934 851 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 852 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 853 gen_op_check_addo_64();
854}
855#endif
856GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 857/* addc addc. addco addco. */
b068d6a7 858static always_inline void gen_op_addc (void)
d9bce9d9 859{
e55fd934 860 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 861 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 862 gen_op_check_addc();
863}
b068d6a7 864static always_inline void gen_op_addco (void)
d9bce9d9 865{
e55fd934 866 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 867 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 868 gen_op_check_addc();
869 gen_op_check_addo();
870}
871#if defined(TARGET_PPC64)
b068d6a7 872static always_inline void gen_op_addc_64 (void)
d9bce9d9 873{
e55fd934 874 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 875 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 876 gen_op_check_addc_64();
877}
b068d6a7 878static always_inline void gen_op_addco_64 (void)
d9bce9d9 879{
e55fd934 880 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 881 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 882 gen_op_check_addc_64();
883 gen_op_check_addo_64();
884}
885#endif
886GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 887/* adde adde. addeo addeo. */
b068d6a7 888static always_inline void gen_op_addeo (void)
d9bce9d9 889{
e55fd934 890 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 891 gen_op_adde();
892 gen_op_check_addo();
893}
894#if defined(TARGET_PPC64)
b068d6a7 895static always_inline void gen_op_addeo_64 (void)
d9bce9d9 896{
e55fd934 897 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 898 gen_op_adde_64();
899 gen_op_check_addo_64();
900}
901#endif
902GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 903/* addme addme. addmeo addmeo. */
b068d6a7 904static always_inline void gen_op_addme (void)
d9bce9d9 905{
e55fd934 906 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 907 gen_op_add_me();
908}
909#if defined(TARGET_PPC64)
b068d6a7 910static always_inline void gen_op_addme_64 (void)
d9bce9d9 911{
e55fd934 912 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 913 gen_op_add_me_64();
914}
915#endif
916GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 917/* addze addze. addzeo addzeo. */
b068d6a7 918static always_inline void gen_op_addze (void)
d9bce9d9 919{
e55fd934 920 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 921 gen_op_add_ze();
922 gen_op_check_addc();
923}
b068d6a7 924static always_inline void gen_op_addzeo (void)
d9bce9d9 925{
e55fd934 926 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 927 gen_op_add_ze();
928 gen_op_check_addc();
929 gen_op_check_addo();
930}
931#if defined(TARGET_PPC64)
b068d6a7 932static always_inline void gen_op_addze_64 (void)
d9bce9d9 933{
e55fd934 934 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 935 gen_op_add_ze();
936 gen_op_check_addc_64();
937}
b068d6a7 938static always_inline void gen_op_addzeo_64 (void)
d9bce9d9 939{
e55fd934 940 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 941 gen_op_add_ze();
942 gen_op_check_addc_64();
943 gen_op_check_addo_64();
944}
945#endif
946GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 947/* divw divw. divwo divwo. */
d9bce9d9 948GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 949/* divwu divwu. divwuo divwuo. */
d9bce9d9 950GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 951/* mulhw mulhw. */
d9bce9d9 952GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 953/* mulhwu mulhwu. */
d9bce9d9 954GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 955/* mullw mullw. mullwo mullwo. */
d9bce9d9 956GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 957/* neg neg. nego nego. */
d9bce9d9 958GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 959/* subf subf. subfo subfo. */
7c417963
AJ		 960static always_inline void gen_op_subf (void)
961{
962 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
963}
b068d6a7 964static always_inline void gen_op_subfo (void)
d9bce9d9 965{
f0413473 966 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 967 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 968 gen_op_check_addo();
d9bce9d9
JM		 969}
970#if defined(TARGET_PPC64)
971#define gen_op_subf_64 gen_op_subf
b068d6a7 972static always_inline void gen_op_subfo_64 (void)
d9bce9d9 973{
f0413473 974 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 975 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 976 gen_op_check_addo_64();
d9bce9d9
JM		 977}
978#endif
979GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 980/* subfc subfc. subfco subfco. */
b068d6a7 981static always_inline void gen_op_subfc (void)
d9bce9d9 982{
7c417963 983 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 984 gen_op_check_subfc();
985}
b068d6a7 986static always_inline void gen_op_subfco (void)
d9bce9d9 987{
f0413473 988 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 989 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 990 gen_op_check_subfc();
c3e10c7b 991 gen_op_check_addo();
d9bce9d9
JM		 992}
993#if defined(TARGET_PPC64)
b068d6a7 994static always_inline void gen_op_subfc_64 (void)
d9bce9d9 995{
7c417963 996 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 997 gen_op_check_subfc_64();
998}
b068d6a7 999static always_inline void gen_op_subfco_64 (void)
d9bce9d9 1000{
f0413473 1001 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 1002 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 1003 gen_op_check_subfc_64();
c3e10c7b 1004 gen_op_check_addo_64();
d9bce9d9
JM		 1005}
1006#endif
1007GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 1008/* subfe subfe. subfeo subfeo. */
b068d6a7 1009static always_inline void gen_op_subfeo (void)
d9bce9d9 1010{
f0413473 1011 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
d9bce9d9 1012 gen_op_subfe();
c3e10c7b 1013 gen_op_check_addo();
d9bce9d9
JM		 1014}
1015#if defined(TARGET_PPC64)
1016#define gen_op_subfe_64 gen_op_subfe
b068d6a7 1017static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 1018{
f0413473 1019 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
d9bce9d9 1020 gen_op_subfe_64();
c3e10c7b 1021 gen_op_check_addo_64();
d9bce9d9
JM		 1022}
1023#endif
1024GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 1025/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 1026GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 1027/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 1028GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 1029/* addi */
1030GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1031{
76a66253 1032 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1033
1034 if (rA(ctx->opcode) == 0) {
76a66253 1035 /* li case */
02f4f6c2 1036 tcg_gen_movi_tl(cpu_T[0], simm);
79aceca5 1037 } else {
f78fb44e 1038 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1039 if (likely(simm != 0))
39dd32ee 1040 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
79aceca5 1041 }
f78fb44e 1042 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1043}
1044/* addic */
1045GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1046{
76a66253
JM		 1047 target_long simm = SIMM(ctx->opcode);
1048
f78fb44e 1049 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1050 if (likely(simm != 0)) {
e55fd934 1051 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1052 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1053#if defined(TARGET_PPC64)
1054 if (ctx->sf_mode)
1055 gen_op_check_addc_64();
1056 else
1057#endif
1058 gen_op_check_addc();
e864cabd
JM		 1059 } else {
1060 gen_op_clear_xer_ca();
d9bce9d9 1061 }
f78fb44e 1062 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1063}
1064/* addic. */
c7697e1f 1065GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1066{
76a66253
JM		 1067 target_long simm = SIMM(ctx->opcode);
1068
f78fb44e 1069 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1070 if (likely(simm != 0)) {
e55fd934 1071 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1072 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1073#if defined(TARGET_PPC64)
1074 if (ctx->sf_mode)
1075 gen_op_check_addc_64();
1076 else
1077#endif
1078 gen_op_check_addc();
966439a6
JM		 1079 } else {
1080 gen_op_clear_xer_ca();
d9bce9d9 1081 }
f78fb44e 1082 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 1083 gen_set_Rc0(ctx);
79aceca5
FB		 1084}
1085/* addis */
1086GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1087{
76a66253 1088 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1089
1090 if (rA(ctx->opcode) == 0) {
76a66253 1091 /* lis case */
02f4f6c2 1092 tcg_gen_movi_tl(cpu_T[0], simm << 16);
79aceca5 1093 } else {
f78fb44e 1094 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1095 if (likely(simm != 0))
39dd32ee 1096 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16);
79aceca5 1097 }
f78fb44e 1098 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1099}
1100/* mulli */
1101GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1102{
f78fb44e 1103 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
79aceca5 1104 gen_op_mulli(SIMM(ctx->opcode));
f78fb44e 1105 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1106}
1107/* subfic */
1108GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1109{
f78fb44e 1110 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9
JM		 1111#if defined(TARGET_PPC64)
1112 if (ctx->sf_mode)
1113 gen_op_subfic_64(SIMM(ctx->opcode));
1114 else
1115#endif
1116 gen_op_subfic(SIMM(ctx->opcode));
f78fb44e 1117 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1118}
1119
d9bce9d9
JM		 1120#if defined(TARGET_PPC64)
1121/* mulhd mulhd. */
a750fc0b 1122GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1123/* mulhdu mulhdu. */
a750fc0b 1124GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1125/* mulld mulld. mulldo mulldo. */
a750fc0b 1126GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1127/* divd divd. divdo divdo. */
a750fc0b 1128GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1129/* divdu divdu. divduo divduo. */
a750fc0b 1130GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1131#endif
1132
79aceca5 1133/*** Integer comparison ***/
d9bce9d9
JM		 1134#if defined(TARGET_PPC64)
1135#define GEN_CMP(name, opc, type) \
1136GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1137{ \
f78fb44e
AJ		 1138 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
1139 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
e3878283 1140 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
d9bce9d9
JM		 1141 gen_op_##name##_64(); \
1142 else \
1143 gen_op_##name(); \
47e4661c 1144 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
d9bce9d9
JM		 1145}
1146#else
1147#define GEN_CMP(name, opc, type) \
1148GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
79aceca5 1149{ \
f78fb44e
AJ		 1150 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
1151 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 1152 gen_op_##name(); \
47e4661c 1153 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
79aceca5 1154}
d9bce9d9 1155#endif
79aceca5
FB		 1156
1157/* cmp */
d9bce9d9 1158GEN_CMP(cmp, 0x00, PPC_INTEGER);
79aceca5
FB		 1159/* cmpi */
1160GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1161{
f78fb44e 1162 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1163#if defined(TARGET_PPC64)
e3878283 1164 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1165 gen_op_cmpi_64(SIMM(ctx->opcode));
1166 else
1167#endif
1168 gen_op_cmpi(SIMM(ctx->opcode));
47e4661c 1169 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
79aceca5
FB		 1170}
1171/* cmpl */
d9bce9d9 1172GEN_CMP(cmpl, 0x01, PPC_INTEGER);
79aceca5
FB		 1173/* cmpli */
1174GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1175{
f78fb44e 1176 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1177#if defined(TARGET_PPC64)
e3878283 1178 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1179 gen_op_cmpli_64(UIMM(ctx->opcode));
1180 else
1181#endif
1182 gen_op_cmpli(UIMM(ctx->opcode));
47e4661c 1183 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
79aceca5
FB		 1184}
1185
d9bce9d9 1186/* isel (PowerPC 2.03 specification) */
fd501a05 1187GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
d9bce9d9
JM		 1188{
1189 uint32_t bi = rC(ctx->opcode);
1190 uint32_t mask;
1191
1192 if (rA(ctx->opcode) == 0) {
02f4f6c2 1193 tcg_gen_movi_tl(cpu_T[0], 0);
d9bce9d9 1194 } else {
f78fb44e 1195 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1196 }
f78fb44e 1197 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1198 mask = 1 << (3 - (bi & 0x03));
47e4661c 1199 tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]);
d9bce9d9
JM		 1200 gen_op_test_true(mask);
1201 gen_op_isel();
f78fb44e 1202 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1203}
1204
79aceca5 1205/*** Integer logical ***/
d9bce9d9
JM		 1206#define __GEN_LOGICAL2(name, opc2, opc3, type) \
1207GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
79aceca5 1208{ \
f78fb44e
AJ		 1209 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
1210 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 1211 gen_op_##name(); \
f78fb44e 1212 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 1213 if (unlikely(Rc(ctx->opcode) != 0)) \
1214 gen_set_Rc0(ctx); \
79aceca5 1215}
d9bce9d9
JM		 1216#define GEN_LOGICAL2(name, opc, type) \
1217__GEN_LOGICAL2(name, 0x1C, opc, type)
79aceca5 1218
d9bce9d9
JM		 1219#define GEN_LOGICAL1(name, opc, type) \
1220GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1221{ \
f78fb44e 1222 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
79aceca5 1223 gen_op_##name(); \
f78fb44e 1224 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 1225 if (unlikely(Rc(ctx->opcode) != 0)) \
1226 gen_set_Rc0(ctx); \
79aceca5
FB		 1227}
1228
1229/* and & and. */
d9bce9d9 1230GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
79aceca5 1231/* andc & andc. */
d9bce9d9 1232GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
79aceca5 1233/* andi. */
c7697e1f 1234GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1235{
f78fb44e 1236 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
0df5bdbe 1237 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
f78fb44e 1238 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1239 gen_set_Rc0(ctx);
79aceca5
FB		 1240}
1241/* andis. */
c7697e1f 1242GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1243{
f78fb44e 1244 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
0df5bdbe 1245 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
f78fb44e 1246 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1247 gen_set_Rc0(ctx);
79aceca5
FB		 1248}
1249
1250/* cntlzw */
d9bce9d9 1251GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
79aceca5 1252/* eqv & eqv. */
d9bce9d9 1253GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
79aceca5 1254/* extsb & extsb. */
d9bce9d9 1255GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
79aceca5 1256/* extsh & extsh. */
d9bce9d9 1257GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
79aceca5 1258/* nand & nand. */
d9bce9d9 1259GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
79aceca5 1260/* nor & nor. */
d9bce9d9 1261GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
9a64fbe4 1262
79aceca5 1263/* or & or. */
9a64fbe4
FB		 1264GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1265{
76a66253
JM		 1266 int rs, ra, rb;
1267
1268 rs = rS(ctx->opcode);
1269 ra = rA(ctx->opcode);
1270 rb = rB(ctx->opcode);
1271 /* Optimisation for mr. ri case */
1272 if (rs != ra || rs != rb) {
f78fb44e 1273 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
76a66253 1274 if (rs != rb) {
f78fb44e 1275 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 1276 gen_op_or();
1277 }
f78fb44e 1278 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 1279 if (unlikely(Rc(ctx->opcode) != 0))
1280 gen_set_Rc0(ctx);
1281 } else if (unlikely(Rc(ctx->opcode) != 0)) {
f78fb44e 1282 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
76a66253 1283 gen_set_Rc0(ctx);
c80f84e3
JM		 1284#if defined(TARGET_PPC64)
1285 } else {
1286 switch (rs) {
1287 case 1:
1288 /* Set process priority to low */
1289 gen_op_store_pri(2);
1290 break;
1291 case 6:
1292 /* Set process priority to medium-low */
1293 gen_op_store_pri(3);
1294 break;
1295 case 2:
1296 /* Set process priority to normal */
1297 gen_op_store_pri(4);
1298 break;
be147d08
JM		 1299#if !defined(CONFIG_USER_ONLY)
1300 case 31:
1301 if (ctx->supervisor > 0) {
1302 /* Set process priority to very low */
1303 gen_op_store_pri(1);
1304 }
1305 break;
1306 case 5:
1307 if (ctx->supervisor > 0) {
1308 /* Set process priority to medium-hight */
1309 gen_op_store_pri(5);
1310 }
1311 break;
1312 case 3:
1313 if (ctx->supervisor > 0) {
1314 /* Set process priority to high */
1315 gen_op_store_pri(6);
1316 }
1317 break;
be147d08
JM		 1318 case 7:
1319 if (ctx->supervisor > 1) {
1320 /* Set process priority to very high */
1321 gen_op_store_pri(7);
1322 }
1323 break;
be147d08 1324#endif
c80f84e3
JM		 1325 default:
1326 /* nop */
1327 break;
1328 }
1329#endif
9a64fbe4 1330 }
9a64fbe4
FB		 1331}
1332
79aceca5 1333/* orc & orc. */
d9bce9d9 1334GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
79aceca5 1335/* xor & xor. */
9a64fbe4
FB		 1336GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1337{
f78fb44e 1338 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4
FB		 1339 /* Optimisation for "set to zero" case */
1340 if (rS(ctx->opcode) != rB(ctx->opcode)) {
f78fb44e 1341 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
9a64fbe4
FB		 1342 gen_op_xor();
1343 } else {
86c581dc 1344 tcg_gen_movi_tl(cpu_T[0], 0);
9a64fbe4 1345 }
f78fb44e 1346 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1347 if (unlikely(Rc(ctx->opcode) != 0))
1348 gen_set_Rc0(ctx);
9a64fbe4 1349}
79aceca5
FB		 1350/* ori */
1351GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1352{
76a66253 1353 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1354
9a64fbe4
FB		 1355 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1356 /* NOP */
76a66253 1357 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1358 return;
76a66253 1359 }
f78fb44e 1360 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253 1361 if (likely(uimm != 0))
79aceca5 1362 gen_op_ori(uimm);
f78fb44e 1363 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1364}
1365/* oris */
1366GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1367{
76a66253 1368 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1369
9a64fbe4
FB		 1370 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1371 /* NOP */
1372 return;
76a66253 1373 }
f78fb44e 1374 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253 1375 if (likely(uimm != 0))
79aceca5 1376 gen_op_ori(uimm << 16);
f78fb44e 1377 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1378}
1379/* xori */
1380GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1381{
76a66253 1382 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1383
1384 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1385 /* NOP */
1386 return;
1387 }
f78fb44e 1388 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1389 if (likely(uimm != 0))
1390 gen_op_xori(uimm);
f78fb44e 1391 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1392}
1393
1394/* xoris */
1395GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1396{
76a66253 1397 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1398
1399 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1400 /* NOP */
1401 return;
1402 }
f78fb44e 1403 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1404 if (likely(uimm != 0))
1405 gen_op_xori(uimm << 16);
f78fb44e 1406 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1407}
1408
d9bce9d9 1409/* popcntb : PowerPC 2.03 specification */
05332d70 1410GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1411{
f78fb44e 1412 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1413#if defined(TARGET_PPC64)
1414 if (ctx->sf_mode)
6676f424 1415 gen_op_popcntb_64();
d9bce9d9
JM		 1416 else
1417#endif
6676f424 1418 gen_op_popcntb();
f78fb44e 1419 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1420}
1421
1422#if defined(TARGET_PPC64)
1423/* extsw & extsw. */
1424GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1425/* cntlzd */
1426GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1427#endif
1428
79aceca5
FB		 1429/*** Integer rotate ***/
1430/* rlwimi & rlwimi. */
1431GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1432{
76a66253
JM		 1433 target_ulong mask;
1434 uint32_t mb, me, sh;
79aceca5
FB		 1435
1436 mb = MB(ctx->opcode);
1437 me = ME(ctx->opcode);
76a66253 1438 sh = SH(ctx->opcode);
76a66253
JM		 1439 if (likely(sh == 0)) {
1440 if (likely(mb == 0 && me == 31)) {
f78fb44e 1441 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1442 goto do_store;
1443 } else if (likely(mb == 31 && me == 0)) {
f78fb44e 1444 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1445 goto do_store;
1446 }
f78fb44e
AJ		 1447 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1448 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1449 goto do_mask;
1450 }
f78fb44e
AJ		 1451 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1452 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1453 gen_op_rotli32_T0(SH(ctx->opcode));
1454 do_mask:
1455#if defined(TARGET_PPC64)
1456 mb += 32;
1457 me += 32;
1458#endif
1459 mask = MASK(mb, me);
0df5bdbe
AJ		 1460 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1461 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
76a66253
JM		 1462 gen_op_or();
1463 do_store:
f78fb44e 1464 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1465 if (unlikely(Rc(ctx->opcode) != 0))
1466 gen_set_Rc0(ctx);
79aceca5
FB		 1467}
1468/* rlwinm & rlwinm. */
1469GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1470{
1471 uint32_t mb, me, sh;
3b46e624 1472
79aceca5
FB		 1473 sh = SH(ctx->opcode);
1474 mb = MB(ctx->opcode);
1475 me = ME(ctx->opcode);
f78fb44e 1476 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1477 if (likely(sh == 0)) {
1478 goto do_mask;
1479 }
1480 if (likely(mb == 0)) {
1481 if (likely(me == 31)) {
1482 gen_op_rotli32_T0(sh);
1483 goto do_store;
1484 } else if (likely(me == (31 - sh))) {
1485 gen_op_sli_T0(sh);
1486 goto do_store;
79aceca5 1487 }
76a66253
JM		 1488 } else if (likely(me == 31)) {
1489 if (likely(sh == (32 - mb))) {
1490 gen_op_srli_T0(mb);
1491 goto do_store;
79aceca5
FB		 1492 }
1493 }
76a66253
JM		 1494 gen_op_rotli32_T0(sh);
1495 do_mask:
1496#if defined(TARGET_PPC64)
1497 mb += 32;
1498 me += 32;
1499#endif
0df5bdbe 1500 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
76a66253 1501 do_store:
f78fb44e 1502 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1503 if (unlikely(Rc(ctx->opcode) != 0))
1504 gen_set_Rc0(ctx);
79aceca5
FB		 1505}
1506/* rlwnm & rlwnm. */
1507GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1508{
1509 uint32_t mb, me;
1510
1511 mb = MB(ctx->opcode);
1512 me = ME(ctx->opcode);
f78fb44e
AJ		 1513 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1514 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 1515 gen_op_rotl32_T0_T1();
1516 if (unlikely(mb != 0 || me != 31)) {
1517#if defined(TARGET_PPC64)
1518 mb += 32;
1519 me += 32;
1520#endif
0df5bdbe 1521 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
79aceca5 1522 }
f78fb44e 1523 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1524 if (unlikely(Rc(ctx->opcode) != 0))
1525 gen_set_Rc0(ctx);
79aceca5
FB		 1526}
1527
d9bce9d9
JM		 1528#if defined(TARGET_PPC64)
1529#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1530GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1531{ \
1532 gen_##name(ctx, 0); \
1533} \
c7697e1f
JM		 1534GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1535 PPC_64B) \
d9bce9d9
JM		 1536{ \
1537 gen_##name(ctx, 1); \
1538}
1539#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1540GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1541{ \
1542 gen_##name(ctx, 0, 0); \
1543} \
c7697e1f
JM		 1544GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1545 PPC_64B) \
d9bce9d9
JM		 1546{ \
1547 gen_##name(ctx, 0, 1); \
1548} \
c7697e1f
JM		 1549GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1550 PPC_64B) \
d9bce9d9
JM		 1551{ \
1552 gen_##name(ctx, 1, 0); \
1553} \
c7697e1f
JM		 1554GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1555 PPC_64B) \
d9bce9d9
JM		 1556{ \
1557 gen_##name(ctx, 1, 1); \
1558}
51789c41 1559
b068d6a7
JM		 1560static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1561 uint32_t me, uint32_t sh)
51789c41 1562{
f78fb44e 1563 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41
JM		 1564 if (likely(sh == 0)) {
1565 goto do_mask;
1566 }
1567 if (likely(mb == 0)) {
1568 if (likely(me == 63)) {
40d0591e 1569 gen_op_rotli64_T0(sh);
51789c41
JM		 1570 goto do_store;
1571 } else if (likely(me == (63 - sh))) {
1572 gen_op_sli_T0(sh);
1573 goto do_store;
1574 }
1575 } else if (likely(me == 63)) {
1576 if (likely(sh == (64 - mb))) {
40d0591e 1577 gen_op_srli_T0_64(mb);
51789c41
JM		 1578 goto do_store;
1579 }
1580 }
1581 gen_op_rotli64_T0(sh);
1582 do_mask:
0df5bdbe 1583 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1584 do_store:
f78fb44e 1585 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41
JM		 1586 if (unlikely(Rc(ctx->opcode) != 0))
1587 gen_set_Rc0(ctx);
1588}
d9bce9d9 1589/* rldicl - rldicl. */
b068d6a7 1590static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1591{
51789c41 1592 uint32_t sh, mb;
d9bce9d9 1593
9d53c753
JM		 1594 sh = SH(ctx->opcode) | (shn << 5);
1595 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1596 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1597}
51789c41 1598GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1599/* rldicr - rldicr. */
b068d6a7 1600static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1601{
51789c41 1602 uint32_t sh, me;
d9bce9d9 1603
9d53c753
JM		 1604 sh = SH(ctx->opcode) | (shn << 5);
1605 me = MB(ctx->opcode) | (men << 5);
51789c41 1606 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1607}
51789c41 1608GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1609/* rldic - rldic. */
b068d6a7 1610static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1611{
51789c41 1612 uint32_t sh, mb;
d9bce9d9 1613
9d53c753
JM		 1614 sh = SH(ctx->opcode) | (shn << 5);
1615 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1616 gen_rldinm(ctx, mb, 63 - sh, sh);
1617}
1618GEN_PPC64_R4(rldic, 0x1E, 0x04);
1619
b068d6a7
JM		 1620static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1621 uint32_t me)
51789c41 1622{
f78fb44e
AJ		 1623 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1624 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
51789c41
JM		 1625 gen_op_rotl64_T0_T1();
1626 if (unlikely(mb != 0 || me != 63)) {
0df5bdbe 1627 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1628 }
f78fb44e 1629 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41
JM		 1630 if (unlikely(Rc(ctx->opcode) != 0))
1631 gen_set_Rc0(ctx);
d9bce9d9 1632}
51789c41 1633
d9bce9d9 1634/* rldcl - rldcl. */
b068d6a7 1635static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1636{
51789c41 1637 uint32_t mb;
d9bce9d9 1638
9d53c753 1639 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1640 gen_rldnm(ctx, mb, 63);
d9bce9d9 1641}
36081602 1642GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1643/* rldcr - rldcr. */
b068d6a7 1644static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1645{
51789c41 1646 uint32_t me;
d9bce9d9 1647
9d53c753 1648 me = MB(ctx->opcode) | (men << 5);
51789c41 1649 gen_rldnm(ctx, 0, me);
d9bce9d9 1650}
36081602 1651GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1652/* rldimi - rldimi. */
b068d6a7 1653static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1654{
51789c41 1655 uint64_t mask;
271a916e 1656 uint32_t sh, mb, me;
d9bce9d9 1657
9d53c753
JM		 1658 sh = SH(ctx->opcode) | (shn << 5);
1659 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1660 me = 63 - sh;
51789c41
JM		 1661 if (likely(sh == 0)) {
1662 if (likely(mb == 0)) {
f78fb44e 1663 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41 1664 goto do_store;
51789c41 1665 }
f78fb44e
AJ		 1666 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1667 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
51789c41
JM		 1668 goto do_mask;
1669 }
f78fb44e
AJ		 1670 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1671 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
40d0591e 1672 gen_op_rotli64_T0(sh);
51789c41 1673 do_mask:
271a916e 1674 mask = MASK(mb, me);
0df5bdbe
AJ		 1675 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1676 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
51789c41
JM		 1677 gen_op_or();
1678 do_store:
f78fb44e 1679 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41
JM		 1680 if (unlikely(Rc(ctx->opcode) != 0))
1681 gen_set_Rc0(ctx);
d9bce9d9 1682}
36081602 1683GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1684#endif
1685
79aceca5
FB		 1686/*** Integer shift ***/
1687/* slw & slw. */
d9bce9d9 1688__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
79aceca5 1689/* sraw & sraw. */
d9bce9d9 1690__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
79aceca5
FB		 1691/* srawi & srawi. */
1692GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1693{
d9bce9d9 1694 int mb, me;
f78fb44e 1695 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1696 if (SH(ctx->opcode) != 0) {
e55fd934 1697 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1698 mb = 32 - SH(ctx->opcode);
1699 me = 31;
1700#if defined(TARGET_PPC64)
1701 mb += 32;
1702 me += 32;
1703#endif
1704 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1705 }
f78fb44e 1706 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1707 if (unlikely(Rc(ctx->opcode) != 0))
1708 gen_set_Rc0(ctx);
79aceca5
FB		 1709}
1710/* srw & srw. */
d9bce9d9
JM		 1711__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1712
1713#if defined(TARGET_PPC64)
1714/* sld & sld. */
1715__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1716/* srad & srad. */
1717__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1718/* sradi & sradi. */
b068d6a7 1719static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9
JM		 1720{
1721 uint64_t mask;
1722 int sh, mb, me;
1723
f78fb44e 1724 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1725 sh = SH(ctx->opcode) + (n << 5);
1726 if (sh != 0) {
e55fd934 1727 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1728 mb = 64 - SH(ctx->opcode);
1729 me = 63;
1730 mask = MASK(mb, me);
1731 gen_op_sradi(sh, mask >> 32, mask);
1732 }
f78fb44e 1733 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1734 if (unlikely(Rc(ctx->opcode) != 0))
1735 gen_set_Rc0(ctx);
1736}
c7697e1f 1737GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1738{
1739 gen_sradi(ctx, 0);
1740}
c7697e1f 1741GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1742{
1743 gen_sradi(ctx, 1);
1744}
1745/* srd & srd. */
1746__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1747#endif
79aceca5
FB		 1748
1749/*** Floating-Point arithmetic ***/
7c58044c 1750#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1751GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1752{ \
76a66253 1753 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1754 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1755 return; \
1756 } \
a5e26afa
AJ		 1757 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1758 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
1759 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1760 gen_reset_fpstatus(); \
4ecc3190
FB		 1761 gen_op_f##op(); \
1762 if (isfloat) { \
1763 gen_op_frsp(); \
1764 } \
a5e26afa 1765 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1766 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1767}
1768
7c58044c
JM		 1769#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1770_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1771_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1772
7c58044c
JM		 1773#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1774GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1775{ \
76a66253 1776 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1777 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1778 return; \
1779 } \
a5e26afa
AJ		 1780 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1781 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1782 gen_reset_fpstatus(); \
4ecc3190
FB		 1783 gen_op_f##op(); \
1784 if (isfloat) { \
1785 gen_op_frsp(); \
1786 } \
a5e26afa 1787 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1788 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1789}
7c58044c
JM		 1790#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1791_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1792_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1793
7c58044c
JM		 1794#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1795GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1796{ \
76a66253 1797 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1798 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1799 return; \
1800 } \
a5e26afa
AJ		 1801 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1802 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
7c58044c 1803 gen_reset_fpstatus(); \
4ecc3190
FB		 1804 gen_op_f##op(); \
1805 if (isfloat) { \
1806 gen_op_frsp(); \
1807 } \
a5e26afa 1808 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1809 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1810}
7c58044c
JM		 1811#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1812_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1813_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1814
7c58044c 1815#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 1816GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 1817{ \
76a66253 1818 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1819 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1820 return; \
1821 } \
a5e26afa 1822 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1823 gen_reset_fpstatus(); \
9a64fbe4 1824 gen_op_f##name(); \
a5e26afa 1825 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1826 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1827}
1828
7c58044c 1829#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 1830GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 1831{ \
76a66253 1832 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1833 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1834 return; \
1835 } \
a5e26afa 1836 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1837 gen_reset_fpstatus(); \
9a64fbe4 1838 gen_op_f##name(); \
a5e26afa 1839 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1840 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1841}
1842
9a64fbe4 1843/* fadd - fadds */
7c58044c 1844GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1845/* fdiv - fdivs */
7c58044c 1846GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1847/* fmul - fmuls */
7c58044c 1848GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 1849
d7e4b87e 1850/* fre */
7c58044c 1851GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 1852
a750fc0b 1853/* fres */
7c58044c 1854GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 1855
a750fc0b 1856/* frsqrte */
7c58044c
JM		 1857GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1858
1859/* frsqrtes */
1860static always_inline void gen_op_frsqrtes (void)
1861{
1862 gen_op_frsqrte();
1863 gen_op_frsp();
1864}
1b413d55 1865GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 1866
a750fc0b 1867/* fsel */
7c58044c 1868_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 1869/* fsub - fsubs */
7c58044c 1870GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 1871/* Optional: */
1872/* fsqrt */
a750fc0b 1873GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 1874{
76a66253 1875 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1876 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 1877 return;
1878 }
a5e26afa 1879 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1880 gen_reset_fpstatus();
c7d344af 1881 gen_op_fsqrt();
a5e26afa 1882 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1883 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 1884}
79aceca5 1885
a750fc0b 1886GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 1887{
76a66253 1888 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1889 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1890 return;
1891 }
a5e26afa 1892 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1893 gen_reset_fpstatus();
4ecc3190
FB		 1894 gen_op_fsqrt();
1895 gen_op_frsp();
a5e26afa 1896 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1897 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 1898}
1899
1900/*** Floating-Point multiply-and-add ***/
4ecc3190 1901/* fmadd - fmadds */
7c58044c 1902GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 1903/* fmsub - fmsubs */
7c58044c 1904GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 1905/* fnmadd - fnmadds */
7c58044c 1906GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 1907/* fnmsub - fnmsubs */
7c58044c 1908GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 1909
1910/*** Floating-Point round & convert ***/
1911/* fctiw */
7c58044c 1912GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 1913/* fctiwz */
7c58044c 1914GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 1915/* frsp */
7c58044c 1916GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 1917#if defined(TARGET_PPC64)
1918/* fcfid */
7c58044c 1919GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 1920/* fctid */
7c58044c 1921GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 1922/* fctidz */
7c58044c 1923GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 1924#endif
79aceca5 1925
d7e4b87e 1926/* frin */
7c58044c 1927GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 1928/* friz */
7c58044c 1929GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 1930/* frip */
7c58044c 1931GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 1932/* frim */
7c58044c 1933GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 1934
79aceca5
FB		 1935/*** Floating-Point compare ***/
1936/* fcmpo */
76a66253 1937GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 1938{
76a66253 1939 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1940 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1941 return;
1942 }
a5e26afa
AJ		 1943 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
1944 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1945 gen_reset_fpstatus();
9a64fbe4 1946 gen_op_fcmpo();
47e4661c 1947 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
7c58044c 1948 gen_op_float_check_status();
79aceca5
FB		 1949}
1950
1951/* fcmpu */
76a66253 1952GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 1953{
76a66253 1954 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1955 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1956 return;
1957 }
a5e26afa
AJ		 1958 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
1959 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1960 gen_reset_fpstatus();
9a64fbe4 1961 gen_op_fcmpu();
47e4661c 1962 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
7c58044c 1963 gen_op_float_check_status();
79aceca5
FB		 1964}
1965
9a64fbe4
FB		 1966/*** Floating-point move ***/
1967/* fabs */
7c58044c
JM		 1968/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1969GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 1970
1971/* fmr - fmr. */
7c58044c 1972/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 1973GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1974{
76a66253 1975 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1976 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1977 return;
1978 }
a5e26afa
AJ		 1979 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
1980 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1981 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 1982}
1983
1984/* fnabs */
7c58044c
JM		 1985/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1986GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 1987/* fneg */
7c58044c
JM		 1988/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1989GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 1990
79aceca5
FB		 1991/*** Floating-Point status & ctrl register ***/
1992/* mcrfs */
1993GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1994{
7c58044c
JM		 1995 int bfa;
1996
76a66253 1997 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1998 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1999 return;
2000 }
7c58044c
JM		 2001 gen_optimize_fprf();
2002 bfa = 4 * (7 - crfS(ctx->opcode));
2003 gen_op_load_fpscr_T0(bfa);
47e4661c 2004 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
7c58044c 2005 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 2006}
2007
2008/* mffs */
2009GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2010{
76a66253 2011 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2012 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2013 return;
2014 }
7c58044c
JM		 2015 gen_optimize_fprf();
2016 gen_reset_fpstatus();
2017 gen_op_load_fpscr_FT0();
a5e26afa 2018 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2019 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2020}
2021
2022/* mtfsb0 */
2023GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2024{
fb0eaffc 2025 uint8_t crb;
3b46e624 2026
76a66253 2027 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2028 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2029 return;
2030 }
7c58044c
JM		 2031 crb = 32 - (crbD(ctx->opcode) >> 2);
2032 gen_optimize_fprf();
2033 gen_reset_fpstatus();
2034 if (likely(crb != 30 && crb != 29))
2035 gen_op_fpscr_resetbit(~(1 << crb));
2036 if (unlikely(Rc(ctx->opcode) != 0)) {
2037 gen_op_load_fpcc();
2038 gen_op_set_Rc0();
2039 }
79aceca5
FB		 2040}
2041
2042/* mtfsb1 */
2043GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2044{
fb0eaffc 2045 uint8_t crb;
3b46e624 2046
76a66253 2047 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2048 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2049 return;
2050 }
7c58044c
JM		 2051 crb = 32 - (crbD(ctx->opcode) >> 2);
2052 gen_optimize_fprf();
2053 gen_reset_fpstatus();
2054 /* XXX: we pretend we can only do IEEE floating-point computations */
2055 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2056 gen_op_fpscr_setbit(crb);
2057 if (unlikely(Rc(ctx->opcode) != 0)) {
2058 gen_op_load_fpcc();
2059 gen_op_set_Rc0();
2060 }
2061 /* We can raise a differed exception */
2062 gen_op_float_check_status();
79aceca5
FB		 2063}
2064
2065/* mtfsf */
2066GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2067{
76a66253 2068 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2069 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2070 return;
2071 }
7c58044c 2072 gen_optimize_fprf();
a5e26afa 2073 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2074 gen_reset_fpstatus();
28b6751f 2075 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c
JM		 2076 if (unlikely(Rc(ctx->opcode) != 0)) {
2077 gen_op_load_fpcc();
2078 gen_op_set_Rc0();
2079 }
2080 /* We can raise a differed exception */
2081 gen_op_float_check_status();
79aceca5
FB		 2082}
2083
2084/* mtfsfi */
2085GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2086{
7c58044c
JM		 2087 int bf, sh;
2088
76a66253 2089 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2090 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2091 return;
2092 }
7c58044c
JM		 2093 bf = crbD(ctx->opcode) >> 2;
2094 sh = 7 - bf;
2095 gen_optimize_fprf();
489251fa 2096 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
7c58044c
JM		 2097 gen_reset_fpstatus();
2098 gen_op_store_fpscr(1 << sh);
2099 if (unlikely(Rc(ctx->opcode) != 0)) {
2100 gen_op_load_fpcc();
2101 gen_op_set_Rc0();
2102 }
2103 /* We can raise a differed exception */
2104 gen_op_float_check_status();
79aceca5
FB		 2105}
2106
76a66253
JM		 2107/*** Addressing modes ***/
2108/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2109static always_inline void gen_addr_imm_index (TCGv EA,
2110 DisasContext *ctx,
b068d6a7 2111 target_long maskl)
76a66253
JM		 2112{
2113 target_long simm = SIMM(ctx->opcode);
2114
be147d08 2115 simm &= ~maskl;
e2be8d8d
AJ		 2116 if (rA(ctx->opcode) == 0)
2117 tcg_gen_movi_tl(EA, simm);
2118 else if (likely(simm != 0))
2119 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2120 else
2121 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2122}
2123
e2be8d8d
AJ		 2124static always_inline void gen_addr_reg_index (TCGv EA,
2125 DisasContext *ctx)
76a66253 2126{
e2be8d8d
AJ		 2127 if (rA(ctx->opcode) == 0)
2128 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2129 else
2130 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2131}
2132
e2be8d8d
AJ		 2133static always_inline void gen_addr_register (TCGv EA,
2134 DisasContext *ctx)
76a66253 2135{
e2be8d8d
AJ		 2136 if (rA(ctx->opcode) == 0)
2137 tcg_gen_movi_tl(EA, 0);
2138 else
2139 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2140}
2141
7863667f
JM		 2142#if defined(TARGET_PPC64)
2143#define _GEN_MEM_FUNCS(name, mode) \
2144 &gen_op_##name##_##mode, \
2145 &gen_op_##name##_le_##mode, \
2146 &gen_op_##name##_64_##mode, \
2147 &gen_op_##name##_le_64_##mode
2148#else
2149#define _GEN_MEM_FUNCS(name, mode) \
2150 &gen_op_##name##_##mode, \
2151 &gen_op_##name##_le_##mode
2152#endif
9a64fbe4 2153#if defined(CONFIG_USER_ONLY)
d9bce9d9 2154#if defined(TARGET_PPC64)
7863667f 2155#define NB_MEM_FUNCS 4
d9bce9d9 2156#else
7863667f 2157#define NB_MEM_FUNCS 2
d9bce9d9 2158#endif
7863667f
JM		 2159#define GEN_MEM_FUNCS(name) \
2160 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2161#else
d9bce9d9 2162#if defined(TARGET_PPC64)
7863667f 2163#define NB_MEM_FUNCS 12
2857068e 2164#else
7863667f 2165#define NB_MEM_FUNCS 6
2857068e 2166#endif
7863667f
JM		 2167#define GEN_MEM_FUNCS(name) \
2168 _GEN_MEM_FUNCS(name, user), \
2169 _GEN_MEM_FUNCS(name, kernel), \
2170 _GEN_MEM_FUNCS(name, hypv)
2171#endif
2172
2173/*** Integer load ***/
2174#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
d9bce9d9 2175#define OP_LD_TABLE(width) \
7863667f
JM		 2176static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2177 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2178};
2179#define OP_ST_TABLE(width) \
7863667f
JM		 2180static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2181 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2182};
9a64fbe4 2183
b61f2753
AJ		 2184
2185#if defined(TARGET_PPC64)
2186#define GEN_QEMU_LD_PPC64(width) \
2187static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2188{ \
2189 if (likely(flags & 2)) \
2190 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2191 else { \
2192 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2193 tcg_gen_ext32u_tl(addr, t1); \
2194 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2195 tcg_temp_free(addr); \
2196 } \
2197}
2198GEN_QEMU_LD_PPC64(8u)
2199GEN_QEMU_LD_PPC64(8s)
2200GEN_QEMU_LD_PPC64(16u)
2201GEN_QEMU_LD_PPC64(16s)
2202GEN_QEMU_LD_PPC64(32u)
2203GEN_QEMU_LD_PPC64(32s)
2204GEN_QEMU_LD_PPC64(64)
2205
2206#define GEN_QEMU_ST_PPC64(width) \
2207static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2208{ \
2209 if (likely(flags & 2)) \
2210 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2211 else { \
2212 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2213 tcg_gen_ext32u_tl(addr, t1); \
2214 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2215 tcg_temp_free(addr); \
2216 } \
2217}
2218GEN_QEMU_ST_PPC64(8)
2219GEN_QEMU_ST_PPC64(16)
2220GEN_QEMU_ST_PPC64(32)
2221GEN_QEMU_ST_PPC64(64)
2222
2223static always_inline void gen_qemu_ld8u(TCGv t0, TCGv t1, int flags)
2224{
2225 gen_qemu_ld8u_ppc64(t0, t1, flags);
2226}
2227
2228static always_inline void gen_qemu_ld8s(TCGv t0, TCGv t1, int flags)
2229{
2230 gen_qemu_ld8s_ppc64(t0, t1, flags);
2231}
2232
2233static always_inline void gen_qemu_ld16u(TCGv t0, TCGv t1, int flags)
2234{
2235 if (unlikely(flags & 1)) {
2236 TCGv t0_32;
2237 gen_qemu_ld16u_ppc64(t0, t1, flags);
2238 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2239 tcg_gen_trunc_tl_i32(t0_32, t0);
2240 tcg_gen_bswap16_i32(t0_32, t0_32);
2241 tcg_gen_extu_i32_tl(t0, t0_32);
2242 tcg_temp_free(t0_32);
2243 } else
2244 gen_qemu_ld16u_ppc64(t0, t1, flags);
2245}
2246
2247static always_inline void gen_qemu_ld16s(TCGv t0, TCGv t1, int flags)
2248{
2249 if (unlikely(flags & 1)) {
2250 TCGv t0_32;
2251 gen_qemu_ld16u_ppc64(t0, t1, flags);
2252 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2253 tcg_gen_trunc_tl_i32(t0_32, t0);
2254 tcg_gen_bswap16_i32(t0_32, t0_32);
2255 tcg_gen_extu_i32_tl(t0, t0_32);
2256 tcg_gen_ext16s_tl(t0, t0);
2257 tcg_temp_free(t0_32);
2258 } else
2259 gen_qemu_ld16s_ppc64(t0, t1, flags);
2260}
2261
2262static always_inline void gen_qemu_ld32u(TCGv t0, TCGv t1, int flags)
2263{
2264 if (unlikely(flags & 1)) {
2265 TCGv t0_32;
2266 gen_qemu_ld32u_ppc64(t0, t1, flags);
2267 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2268 tcg_gen_trunc_tl_i32(t0_32, t0);
2269 tcg_gen_bswap_i32(t0_32, t0_32);
2270 tcg_gen_extu_i32_tl(t0, t0_32);
2271 tcg_temp_free(t0_32);
2272 } else
2273 gen_qemu_ld32u_ppc64(t0, t1, flags);
2274}
2275
2276static always_inline void gen_qemu_ld32s(TCGv t0, TCGv t1, int flags)
2277{
2278 if (unlikely(flags & 1)) {
2279 TCGv t0_32;
2280 gen_qemu_ld32u_ppc64(t0, t1, flags);
2281 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2282 tcg_gen_trunc_tl_i32(t0_32, t0);
2283 tcg_gen_bswap_i32(t0_32, t0_32);
2284 tcg_gen_ext_i32_tl(t0, t0_32);
2285 tcg_temp_free(t0_32);
2286 } else
2287 gen_qemu_ld32s_ppc64(t0, t1, flags);
2288}
2289
2290static always_inline void gen_qemu_ld64(TCGv t0, TCGv t1, int flags)
2291{
2292 gen_qemu_ld64_ppc64(t0, t1, flags);
2293 if (unlikely(flags & 1))
2294 tcg_gen_bswap_i64(t0, t0);
2295}
2296
2297static always_inline void gen_qemu_st8(TCGv t0, TCGv t1, int flags)
2298{
2299 gen_qemu_st8_ppc64(t0, t1, flags);
2300}
2301
2302static always_inline void gen_qemu_st16(TCGv t0, TCGv t1, int flags)
2303{
2304 if (unlikely(flags & 1)) {
2305 TCGv temp1, temp2;
2306 temp1 = tcg_temp_new(TCG_TYPE_I32);
2307 tcg_gen_trunc_tl_i32(temp1, t0);
2308 tcg_gen_ext16u_i32(temp1, temp1);
2309 tcg_gen_bswap16_i32(temp1, temp1);
2310 temp2 = tcg_temp_new(TCG_TYPE_I64);
2311 tcg_gen_extu_i32_tl(temp2, temp1);
2312 tcg_temp_free(temp1);
2313 gen_qemu_st16_ppc64(temp2, t1, flags);
2314 tcg_temp_free(temp2);
2315 } else
2316 gen_qemu_st16_ppc64(t0, t1, flags);
2317}
2318
2319static always_inline void gen_qemu_st32(TCGv t0, TCGv t1, int flags)
2320{
2321 if (unlikely(flags & 1)) {
2322 TCGv temp1, temp2;
2323 temp1 = tcg_temp_new(TCG_TYPE_I32);
2324 tcg_gen_trunc_tl_i32(temp1, t0);
2325 tcg_gen_bswap_i32(temp1, temp1);
2326 temp2 = tcg_temp_new(TCG_TYPE_I64);
2327 tcg_gen_extu_i32_tl(temp2, temp1);
2328 tcg_temp_free(temp1);
2329 gen_qemu_st32_ppc64(temp2, t1, flags);
2330 tcg_temp_free(temp2);
2331 } else
2332 gen_qemu_st32_ppc64(t0, t1, flags);
2333}
2334
2335static always_inline void gen_qemu_st64(TCGv t0, TCGv t1, int flags)
2336{
2337 if (unlikely(flags & 1)) {
2338 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2339 tcg_gen_bswap_i64(temp, t0);
2340 gen_qemu_st64_ppc64(temp, t1, flags);
2341 tcg_temp_free(temp);
2342 } else
2343 gen_qemu_st64_ppc64(t0, t1, flags);
2344}
2345
2346
2347#else /* defined(TARGET_PPC64) */
2348#define GEN_QEMU_LD_PPC32(width) \
2349static always_inline void gen_qemu_ld##width##_ppc32(TCGv t0, TCGv t1, int flags)\
2350{ \
2351 tcg_gen_qemu_ld##width(t0, t1, flags >> 1); \
2352}
2353GEN_QEMU_LD_PPC32(8u)
2354GEN_QEMU_LD_PPC32(8s)
2355GEN_QEMU_LD_PPC32(16u)
2356GEN_QEMU_LD_PPC32(16s)
2357GEN_QEMU_LD_PPC32(32u)
2358GEN_QEMU_LD_PPC32(32s)
2359GEN_QEMU_LD_PPC32(64)
2360
2361#define GEN_QEMU_ST_PPC32(width) \
2362static always_inline void gen_qemu_st##width##_ppc32(TCGv t0, TCGv t1, int flags)\
2363{ \
2364 tcg_gen_qemu_st##width(t0, t1, flags >> 1); \
2365}
2366GEN_QEMU_ST_PPC32(8)
2367GEN_QEMU_ST_PPC32(16)
2368GEN_QEMU_ST_PPC32(32)
2369GEN_QEMU_ST_PPC32(64)
2370
2371static always_inline void gen_qemu_ld8u(TCGv t0, TCGv t1, int flags)
2372{
2373 gen_qemu_ld8u_ppc32(t0, t1, flags >> 1);
2374}
2375
2376static always_inline void gen_qemu_ld8s(TCGv t0, TCGv t1, int flags)
2377{
2378 gen_qemu_ld8s_ppc32(t0, t1, flags >> 1);
2379}
2380
2381static always_inline void gen_qemu_ld16u(TCGv t0, TCGv t1, int flags)
2382{
2383 gen_qemu_ld16u_ppc32(t0, t1, flags >> 1);
2384 if (unlikely(flags & 1))
2385 tcg_gen_bswap16_i32(t0, t0);
2386}
2387
2388static always_inline void gen_qemu_ld16s(TCGv t0, TCGv t1, int flags)
2389{
2390 if (unlikely(flags & 1)) {
2391 gen_qemu_ld16u_ppc32(t0, t1, flags);
2392 tcg_gen_bswap16_i32(t0, t0);
2393 tcg_gen_ext16s_i32(t0, t0);
2394 } else
2395 gen_qemu_ld16s_ppc32(t0, t1, flags);
2396}
2397
2398static always_inline void gen_qemu_ld32u(TCGv t0, TCGv t1, int flags)
2399{
2400 gen_qemu_ld32u_ppc32(t0, t1, flags);
2401 if (unlikely(flags & 1))
2402 tcg_gen_bswap_i32(t0, t0);
2403}
2404
2405static always_inline void gen_qemu_ld64(TCGv t0, TCGv t1, int flags)
2406{
2407 gen_qemu_ld64_ppc32(t0, t1, flags);
2408 if (unlikely(flags & 1))
2409 tcg_gen_bswap_i64(t0, t0);
2410}
2411
2412static always_inline void gen_qemu_st8(TCGv t0, TCGv t1, int flags)
2413{
2414 gen_qemu_st8_ppc32(t0, t1, flags >> 1);
2415}
2416
2417static always_inline void gen_qemu_st16(TCGv t0, TCGv t1, int flags)
2418{
2419 if (unlikely(flags & 1)) {
2420 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2421 tcg_gen_ext16u_i32(temp, t0);
2422 tcg_gen_bswap16_i32(temp, temp);
2423 gen_qemu_st16_ppc32(temp, t1, flags >> 1);
2424 tcg_temp_free(temp);
2425 } else
2426 gen_qemu_st16_ppc32(t0, t1, flags >> 1);
2427}
2428
2429static always_inline void gen_qemu_st32(TCGv t0, TCGv t1, int flags)
2430{
2431 if (unlikely(flags & 1)) {
2432 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2433 tcg_gen_bswap_i32(temp, t0);
2434 gen_qemu_st32_ppc32(temp, t1, flags >> 1);
2435 tcg_temp_free(temp);
2436 } else
2437 gen_qemu_st32_ppc32(t0, t1, flags >> 1);
2438}
2439
2440static always_inline void gen_qemu_st64(TCGv t0, TCGv t1, int flags)
2441{
2442 if (unlikely(flags & 1)) {
2443 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2444 tcg_gen_bswap_i64(temp, t0);
2445 gen_qemu_st64_ppc32(temp, t1, flags >> 1);
2446 tcg_temp_free(temp);
2447 } else
2448 gen_qemu_st64_ppc32(t0, t1, flags >> 1);
2449}
2450
2451#endif
2452
d9bce9d9
JM		 2453#define GEN_LD(width, opc, type) \
2454GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2455{ \
b61f2753
AJ		 2456 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2457 gen_addr_imm_index(EA, ctx, 0); \
2458 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2459 tcg_temp_free(EA); \
79aceca5
FB		 2460}
2461
d9bce9d9
JM		 2462#define GEN_LDU(width, opc, type) \
2463GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2464{ \
b61f2753 2465 TCGv EA; \
76a66253
JM		 2466 if (unlikely(rA(ctx->opcode) == 0 || \
2467 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2468 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2469 return; \
9a64fbe4 2470 } \
b61f2753 2471 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2472 if (type == PPC_64B) \
b61f2753 2473 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2474 else \
b61f2753
AJ		 2475 gen_addr_imm_index(EA, ctx, 0); \
2476 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2477 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2478 tcg_temp_free(EA); \
79aceca5
FB		 2479}
2480
d9bce9d9
JM		 2481#define GEN_LDUX(width, opc2, opc3, type) \
2482GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2483{ \
b61f2753 2484 TCGv EA; \
76a66253
JM		 2485 if (unlikely(rA(ctx->opcode) == 0 || \
2486 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2487 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2488 return; \
9a64fbe4 2489 } \
b61f2753
AJ		 2490 EA = tcg_temp_new(TCG_TYPE_TL); \
2491 gen_addr_reg_index(EA, ctx); \
2492 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2493 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2494 tcg_temp_free(EA); \
79aceca5
FB		 2495}
2496
d9bce9d9
JM		 2497#define GEN_LDX(width, opc2, opc3, type) \
2498GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2499{ \
b61f2753
AJ		 2500 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2501 gen_addr_reg_index(EA, ctx); \
2502 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2503 tcg_temp_free(EA); \
79aceca5
FB		 2504}
2505
d9bce9d9 2506#define GEN_LDS(width, op, type) \
d9bce9d9
JM		 2507GEN_LD(width, op | 0x20, type); \
2508GEN_LDU(width, op | 0x21, type); \
2509GEN_LDUX(width, 0x17, op | 0x01, type); \
2510GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2511
2512/* lbz lbzu lbzux lbzx */
b61f2753 2513GEN_LDS(8u, 0x02, PPC_INTEGER);
79aceca5 2514/* lha lhau lhaux lhax */
b61f2753 2515GEN_LDS(16s, 0x0A, PPC_INTEGER);
79aceca5 2516/* lhz lhzu lhzux lhzx */
b61f2753 2517GEN_LDS(16u, 0x08, PPC_INTEGER);
79aceca5 2518/* lwz lwzu lwzux lwzx */
b61f2753 2519GEN_LDS(32u, 0x00, PPC_INTEGER);
d9bce9d9 2520#if defined(TARGET_PPC64)
d9bce9d9 2521/* lwaux */
b61f2753 2522GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2523/* lwax */
b61f2753 2524GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2525/* ldux */
b61f2753 2526GEN_LDUX(64, 0x15, 0x01, PPC_64B);
d9bce9d9 2527/* ldx */
b61f2753 2528GEN_LDX(64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2529GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2530{
b61f2753 2531 TCGv EA;
d9bce9d9
JM		 2532 if (Rc(ctx->opcode)) {
2533 if (unlikely(rA(ctx->opcode) == 0 ||
2534 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2535 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2536 return;
2537 }
2538 }
b61f2753
AJ		 2539 EA = tcg_temp_new(TCG_TYPE_TL);
2540 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2541 if (ctx->opcode & 0x02) {
2542 /* lwa (lwau is undefined) */
b61f2753 2543 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2544 } else {
2545 /* ld - ldu */
b61f2753 2546 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2547 }
d9bce9d9 2548 if (Rc(ctx->opcode))
b61f2753
AJ		 2549 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2550 tcg_temp_free(EA);
d9bce9d9 2551}
be147d08
JM		 2552/* lq */
2553GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2554{
2555#if defined(CONFIG_USER_ONLY)
2556 GEN_EXCP_PRIVOPC(ctx);
2557#else
2558 int ra, rd;
b61f2753 2559 TCGv EA;
be147d08
JM		 2560
2561 /* Restore CPU state */
2562 if (unlikely(ctx->supervisor == 0)) {
2563 GEN_EXCP_PRIVOPC(ctx);
2564 return;
2565 }
2566 ra = rA(ctx->opcode);
2567 rd = rD(ctx->opcode);
2568 if (unlikely((rd & 1) || rd == ra)) {
2569 GEN_EXCP_INVAL(ctx);
2570 return;
2571 }
2572 if (unlikely(ctx->mem_idx & 1)) {
2573 /* Little-endian mode is not handled */
2574 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2575 return;
2576 }
b61f2753
AJ		 2577 EA = tcg_temp_new(TCG_TYPE_TL);
2578 gen_addr_imm_index(EA, ctx, 0x0F);
2579 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2580 tcg_gen_addi_tl(EA, EA, 8);
2581 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2582 tcg_temp_free(EA);
be147d08
JM		 2583#endif
2584}
d9bce9d9 2585#endif
79aceca5
FB		 2586
2587/*** Integer store ***/
d9bce9d9
JM		 2588#define GEN_ST(width, opc, type) \
2589GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2590{ \
b61f2753
AJ		 2591 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2592 gen_addr_imm_index(EA, ctx, 0); \
2593 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2594 tcg_temp_free(EA); \
79aceca5
FB		 2595}
2596
d9bce9d9
JM		 2597#define GEN_STU(width, opc, type) \
2598GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2599{ \
b61f2753 2600 TCGv EA; \
76a66253 2601 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2602 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2603 return; \
9a64fbe4 2604 } \
b61f2753 2605 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2606 if (type == PPC_64B) \
b61f2753 2607 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2608 else \
b61f2753
AJ		 2609 gen_addr_imm_index(EA, ctx, 0); \
2610 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2611 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2612 tcg_temp_free(EA); \
79aceca5
FB		 2613}
2614
d9bce9d9
JM		 2615#define GEN_STUX(width, opc2, opc3, type) \
2616GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2617{ \
b61f2753 2618 TCGv EA; \
76a66253 2619 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2620 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2621 return; \
9a64fbe4 2622 } \
b61f2753
AJ		 2623 EA = tcg_temp_new(TCG_TYPE_TL); \
2624 gen_addr_reg_index(EA, ctx); \
2625 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2626 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2627 tcg_temp_free(EA); \
79aceca5
FB		 2628}
2629
d9bce9d9
JM		 2630#define GEN_STX(width, opc2, opc3, type) \
2631GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2632{ \
b61f2753
AJ		 2633 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2634 gen_addr_reg_index(EA, ctx); \
2635 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2636 tcg_temp_free(EA); \
79aceca5
FB		 2637}
2638
d9bce9d9 2639#define GEN_STS(width, op, type) \
d9bce9d9
JM		 2640GEN_ST(width, op | 0x20, type); \
2641GEN_STU(width, op | 0x21, type); \
2642GEN_STUX(width, 0x17, op | 0x01, type); \
2643GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2644
2645/* stb stbu stbux stbx */
b61f2753 2646GEN_STS(8, 0x06, PPC_INTEGER);
79aceca5 2647/* sth sthu sthux sthx */
b61f2753 2648GEN_STS(16, 0x0C, PPC_INTEGER);
79aceca5 2649/* stw stwu stwux stwx */
b61f2753 2650GEN_STS(32, 0x04, PPC_INTEGER);
d9bce9d9 2651#if defined(TARGET_PPC64)
b61f2753
AJ		 2652GEN_STUX(64, 0x15, 0x05, PPC_64B);
2653GEN_STX(64, 0x15, 0x04, PPC_64B);
be147d08 2654GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2655{
be147d08 2656 int rs;
b61f2753 2657 TCGv EA;
be147d08
JM		 2658
2659 rs = rS(ctx->opcode);
2660 if ((ctx->opcode & 0x3) == 0x2) {
2661#if defined(CONFIG_USER_ONLY)
2662 GEN_EXCP_PRIVOPC(ctx);
2663#else
2664 /* stq */
2665 if (unlikely(ctx->supervisor == 0)) {
2666 GEN_EXCP_PRIVOPC(ctx);
2667 return;
2668 }
2669 if (unlikely(rs & 1)) {
e1833e1f 2670 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2671 return;
2672 }
be147d08
JM		 2673 if (unlikely(ctx->mem_idx & 1)) {
2674 /* Little-endian mode is not handled */
2675 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2676 return;
2677 }
b61f2753
AJ		 2678 EA = tcg_temp_new(TCG_TYPE_TL);
2679 gen_addr_imm_index(EA, ctx, 0x03);
2680 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
2681 tcg_gen_addi_tl(EA, EA, 8);
2682 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
2683 tcg_temp_free(EA);
be147d08
JM		 2684#endif
2685 } else {
2686 /* std / stdu */
2687 if (Rc(ctx->opcode)) {
2688 if (unlikely(rA(ctx->opcode) == 0)) {
2689 GEN_EXCP_INVAL(ctx);
2690 return;
2691 }
2692 }
b61f2753
AJ		 2693 EA = tcg_temp_new(TCG_TYPE_TL);
2694 gen_addr_imm_index(EA, ctx, 0x03);
2695 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 2696 if (Rc(ctx->opcode))
b61f2753
AJ		 2697 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2698 tcg_temp_free(EA);
d9bce9d9 2699 }
d9bce9d9
JM		 2700}
2701#endif
79aceca5
FB		 2702/*** Integer load and store with byte reverse ***/
2703/* lhbrx */
b61f2753
AJ		 2704void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
2705{
2706 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2707 gen_qemu_ld16u(temp, t1, flags);
2708 tcg_gen_bswap16_i32(temp, temp);
2709 tcg_gen_extu_i32_tl(t0, temp);
2710 tcg_temp_free(temp);
2711}
2712GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
2713
79aceca5 2714/* lwbrx */
b61f2753
AJ		 2715void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
2716{
2717 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2718 gen_qemu_ld32u(temp, t1, flags);
2719 tcg_gen_bswap_i32(temp, temp);
2720 tcg_gen_extu_i32_tl(t0, temp);
2721 tcg_temp_free(temp);
2722}
2723GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
2724
79aceca5 2725/* sthbrx */
b61f2753
AJ		 2726void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
2727{
2728 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2729 tcg_gen_trunc_tl_i32(temp, t0);
2730 tcg_gen_ext16u_i32(temp, temp);
2731 tcg_gen_bswap16_i32(temp, temp);
2732 gen_qemu_st16(temp, t1, flags);
2733 tcg_temp_free(temp);
2734}
2735GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
2736
79aceca5 2737/* stwbrx */
b61f2753
AJ		 2738void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
2739{
2740 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2741 tcg_gen_trunc_tl_i32(temp, t0);
2742 tcg_gen_bswap_i32(temp, temp);
2743 gen_qemu_st32(temp, t1, flags);
2744 tcg_temp_free(temp);
2745}
2746GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2747
2748/*** Integer load and store multiple ***/
111bfab3 2749#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 2750static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2751 GEN_MEM_FUNCS(lmw),
d9bce9d9 2752};
7863667f
JM		 2753static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2754 GEN_MEM_FUNCS(stmw),
d9bce9d9 2755};
9a64fbe4 2756
79aceca5
FB		 2757/* lmw */
2758GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2759{
76a66253 2760 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2761 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2762 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2763 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2764}
2765
2766/* stmw */
2767GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2768{
76a66253 2769 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2770 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2771 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2772 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2773}
2774
2775/*** Integer load and store strings ***/
9a64fbe4
FB		 2776#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2777#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 2778/* string load & stores are by definition endian-safe */
2779#define gen_op_lswi_le_raw gen_op_lswi_raw
2780#define gen_op_lswi_le_user gen_op_lswi_user
2781#define gen_op_lswi_le_kernel gen_op_lswi_kernel
2782#define gen_op_lswi_le_hypv gen_op_lswi_hypv
2783#define gen_op_lswi_le_64_raw gen_op_lswi_raw
2784#define gen_op_lswi_le_64_user gen_op_lswi_user
2785#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2786#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 2787static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2788 GEN_MEM_FUNCS(lswi),
d9bce9d9 2789};
e7c24003
JM		 2790#define gen_op_lswx_le_raw gen_op_lswx_raw
2791#define gen_op_lswx_le_user gen_op_lswx_user
2792#define gen_op_lswx_le_kernel gen_op_lswx_kernel
2793#define gen_op_lswx_le_hypv gen_op_lswx_hypv
2794#define gen_op_lswx_le_64_raw gen_op_lswx_raw
2795#define gen_op_lswx_le_64_user gen_op_lswx_user
2796#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2797#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 2798static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2799 GEN_MEM_FUNCS(lswx),
d9bce9d9 2800};
e7c24003
JM		 2801#define gen_op_stsw_le_raw gen_op_stsw_raw
2802#define gen_op_stsw_le_user gen_op_stsw_user
2803#define gen_op_stsw_le_kernel gen_op_stsw_kernel
2804#define gen_op_stsw_le_hypv gen_op_stsw_hypv
2805#define gen_op_stsw_le_64_raw gen_op_stsw_raw
2806#define gen_op_stsw_le_64_user gen_op_stsw_user
2807#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2808#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 2809static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2810 GEN_MEM_FUNCS(stsw),
9a64fbe4 2811};
9a64fbe4 2812
79aceca5 2813/* lswi */
3fc6c082 2814/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2815 * rA is in the range of registers to be loaded.
2816 * In an other hand, IBM says this is valid, but rA won't be loaded.
2817 * For now, I'll follow the spec...
2818 */
05332d70 2819GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 2820{
2821 int nb = NB(ctx->opcode);
2822 int start = rD(ctx->opcode);
9a64fbe4 2823 int ra = rA(ctx->opcode);
79aceca5
FB		 2824 int nr;
2825
2826 if (nb == 0)
2827 nb = 32;
2828 nr = nb / 4;
76a66253
JM		 2829 if (unlikely(((start + nr) > 32 &&
2830 start <= ra && (start + nr - 32) > ra) ||
2831 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 2832 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2833 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2834 return;
297d8e62 2835 }
8dd4983c 2836 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2837 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2838 gen_addr_register(cpu_T[0], ctx);
86c581dc 2839 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 2840 op_ldsts(lswi, start);
79aceca5
FB		 2841}
2842
2843/* lswx */
05332d70 2844GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 2845{
9a64fbe4
FB		 2846 int ra = rA(ctx->opcode);
2847 int rb = rB(ctx->opcode);
2848
76a66253 2849 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2850 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2851 gen_addr_reg_index(cpu_T[0], ctx);
9a64fbe4 2852 if (ra == 0) {
9a64fbe4 2853 ra = rb;
79aceca5 2854 }
9a64fbe4
FB		 2855 gen_op_load_xer_bc();
2856 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 2857}
2858
2859/* stswi */
05332d70 2860GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 2861{
4b3686fa
FB		 2862 int nb = NB(ctx->opcode);
2863
76a66253 2864 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2865 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2866 gen_addr_register(cpu_T[0], ctx);
4b3686fa
FB		 2867 if (nb == 0)
2868 nb = 32;
86c581dc 2869 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 2870 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2871}
2872
2873/* stswx */
05332d70 2874GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 2875{
8dd4983c 2876 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 2877 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2878 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 2879 gen_op_load_xer_bc();
9a64fbe4 2880 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2881}
2882
2883/*** Memory synchronisation ***/
2884/* eieio */
0db1b20e 2885GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 2886{
79aceca5
FB		 2887}
2888
2889/* isync */
0db1b20e 2890GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 2891{
e1833e1f 2892 GEN_STOP(ctx);
79aceca5
FB		 2893}
2894
111bfab3
FB		 2895#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2896#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 2897static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2898 GEN_MEM_FUNCS(lwarx),
111bfab3 2899};
7863667f
JM		 2900static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2901 GEN_MEM_FUNCS(stwcx),
985a19d6 2902};
9a64fbe4 2903
111bfab3 2904/* lwarx */
76a66253 2905GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 2906{
30032c94
JM		 2907 /* NIP cannot be restored if the memory exception comes from an helper */
2908 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2909 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 2910 op_lwarx();
f78fb44e 2911 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 2912}
2913
2914/* stwcx. */
c7697e1f 2915GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 2916{
30032c94
JM		 2917 /* NIP cannot be restored if the memory exception comes from an helper */
2918 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2919 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 2920 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 2921 op_stwcx();
79aceca5
FB		 2922}
2923
426613db
JM		 2924#if defined(TARGET_PPC64)
2925#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2926#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 2927static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2928 GEN_MEM_FUNCS(ldarx),
426613db 2929};
7863667f
JM		 2930static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2931 GEN_MEM_FUNCS(stdcx),
426613db 2932};
426613db
JM		 2933
2934/* ldarx */
a750fc0b 2935GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 2936{
30032c94
JM		 2937 /* NIP cannot be restored if the memory exception comes from an helper */
2938 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2939 gen_addr_reg_index(cpu_T[0], ctx);
426613db 2940 op_ldarx();
f78fb44e 2941 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 2942}
2943
2944/* stdcx. */
c7697e1f 2945GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 2946{
30032c94
JM		 2947 /* NIP cannot be restored if the memory exception comes from an helper */
2948 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2949 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 2950 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 2951 op_stdcx();
2952}
2953#endif /* defined(TARGET_PPC64) */
2954
79aceca5 2955/* sync */
a902d886 2956GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 2957{
79aceca5
FB		 2958}
2959
0db1b20e
JM		 2960/* wait */
2961GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2962{
2963 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 2964 gen_op_wait();
2965 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 2966}
2967
79aceca5 2968/*** Floating-point load ***/
477023a6
JM		 2969#define GEN_LDF(width, opc, type) \
2970GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2971{ \
76a66253 2972 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2973 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2974 return; \
2975 } \
e2be8d8d 2976 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 2977 op_ldst(l##width); \
a5e26afa 2978 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 2979}
2980
477023a6
JM		 2981#define GEN_LDUF(width, opc, type) \
2982GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2983{ \
76a66253 2984 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2985 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2986 return; \
2987 } \
76a66253 2988 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2989 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2990 return; \
9a64fbe4 2991 } \
e2be8d8d 2992 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 2993 op_ldst(l##width); \
a5e26afa 2994 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 2995 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2996}
2997
477023a6
JM		 2998#define GEN_LDUXF(width, opc, type) \
2999GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3000{ \
76a66253 3001 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3002 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3003 return; \
3004 } \
76a66253 3005 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3006 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3007 return; \
9a64fbe4 3008 } \
e2be8d8d 3009 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3010 op_ldst(l##width); \
a5e26afa 3011 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3012 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3013}
3014
477023a6
JM		 3015#define GEN_LDXF(width, opc2, opc3, type) \
3016GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3017{ \
76a66253 3018 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3019 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3020 return; \
3021 } \
e2be8d8d 3022 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3023 op_ldst(l##width); \
a5e26afa 3024 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3025}
3026
477023a6 3027#define GEN_LDFS(width, op, type) \
9a64fbe4 3028OP_LD_TABLE(width); \
477023a6
JM		 3029GEN_LDF(width, op | 0x20, type); \
3030GEN_LDUF(width, op | 0x21, type); \
3031GEN_LDUXF(width, op | 0x01, type); \
3032GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3033
3034/* lfd lfdu lfdux lfdx */
477023a6 3035GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 3036/* lfs lfsu lfsux lfsx */
477023a6 3037GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3038
3039/*** Floating-point store ***/
477023a6
JM		 3040#define GEN_STF(width, opc, type) \
3041GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3042{ \
76a66253 3043 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3044 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3045 return; \
3046 } \
e2be8d8d 3047 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3048 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3049 op_ldst(st##width); \
79aceca5
FB		 3050}
3051
477023a6
JM		 3052#define GEN_STUF(width, opc, type) \
3053GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3054{ \
76a66253 3055 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3056 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3057 return; \
3058 } \
76a66253 3059 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3060 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3061 return; \
9a64fbe4 3062 } \
e2be8d8d 3063 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3064 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3065 op_ldst(st##width); \
f78fb44e 3066 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3067}
3068
477023a6
JM		 3069#define GEN_STUXF(width, opc, type) \
3070GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3071{ \
76a66253 3072 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3073 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3074 return; \
3075 } \
76a66253 3076 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3077 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3078 return; \
9a64fbe4 3079 } \
e2be8d8d 3080 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3081 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3082 op_ldst(st##width); \
f78fb44e 3083 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3084}
3085
477023a6
JM		 3086#define GEN_STXF(width, opc2, opc3, type) \
3087GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3088{ \
76a66253 3089 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3090 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3091 return; \
3092 } \
e2be8d8d 3093 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3094 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3095 op_ldst(st##width); \
79aceca5
FB		 3096}
3097
477023a6 3098#define GEN_STFS(width, op, type) \
9a64fbe4 3099OP_ST_TABLE(width); \
477023a6
JM		 3100GEN_STF(width, op | 0x20, type); \
3101GEN_STUF(width, op | 0x21, type); \
3102GEN_STUXF(width, op | 0x01, type); \
3103GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3104
3105/* stfd stfdu stfdux stfdx */
477023a6 3106GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 3107/* stfs stfsu stfsux stfsx */
477023a6 3108GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3109
3110/* Optional: */
3111/* stfiwx */
5b8105fa
JM		 3112OP_ST_TABLE(fiw);
3113GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3114
3115/*** Branch ***/
b068d6a7
JM		 3116static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3117 target_ulong dest)
c1942362
FB		 3118{
3119 TranslationBlock *tb;
3120 tb = ctx->tb;
57fec1fe 3121 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3122 likely(!ctx->singlestep_enabled)) {
57fec1fe 3123 tcg_gen_goto_tb(n);
02f4f6c2 3124 tcg_gen_movi_tl(cpu_T[1], dest);
d9bce9d9
JM		 3125#if defined(TARGET_PPC64)
3126 if (ctx->sf_mode)
bd568f18 3127 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 3128 else
3129#endif
bd568f18 3130 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
57fec1fe 3131 tcg_gen_exit_tb((long)tb + n);
c1942362 3132 } else {
02f4f6c2 3133 tcg_gen_movi_tl(cpu_T[1], dest);
d9bce9d9
JM		 3134#if defined(TARGET_PPC64)
3135 if (ctx->sf_mode)
bd568f18 3136 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 3137 else
3138#endif
bd568f18 3139 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
8cbcb4fa
AJ		 3140 if (unlikely(ctx->singlestep_enabled)) {
3141 if ((ctx->singlestep_enabled &
3142 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3143 ctx->exception == POWERPC_EXCP_BRANCH) {
3144 target_ulong tmp = ctx->nip;
3145 ctx->nip = dest;
3146 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3147 ctx->nip = tmp;
3148 }
3149 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3150 gen_update_nip(ctx, dest);
3151 gen_op_debug();
3152 }
3153 }
57fec1fe 3154 tcg_gen_exit_tb(0);
c1942362 3155 }
c53be334
FB		 3156}
3157
b068d6a7 3158static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3159{
3160#if defined(TARGET_PPC64)
3161 if (ctx->sf_mode != 0 && (nip >> 32))
3162 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3163 else
3164#endif
3165 gen_op_setlr(ctx->nip);
3166}
3167
79aceca5
FB		 3168/* b ba bl bla */
3169GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3170{
76a66253 3171 target_ulong li, target;
38a64f9d 3172
8cbcb4fa 3173 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3174 /* sign extend LI */
76a66253 3175#if defined(TARGET_PPC64)
d9bce9d9
JM		 3176 if (ctx->sf_mode)
3177 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3178 else
76a66253 3179#endif
d9bce9d9 3180 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3181 if (likely(AA(ctx->opcode) == 0))
046d6672 3182 target = ctx->nip + li - 4;
79aceca5 3183 else
9a64fbe4 3184 target = li;
d9bce9d9 3185#if defined(TARGET_PPC64)
e1833e1f
JM		 3186 if (!ctx->sf_mode)
3187 target = (uint32_t)target;
d9bce9d9 3188#endif
e1833e1f
JM		 3189 if (LK(ctx->opcode))
3190 gen_setlr(ctx, ctx->nip);
c1942362 3191 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3192}
3193
e98a6e40
FB		 3194#define BCOND_IM 0
3195#define BCOND_LR 1
3196#define BCOND_CTR 2
3197
b068d6a7 3198static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3199{
76a66253
JM		 3200 target_ulong target = 0;
3201 target_ulong li;
d9bce9d9
JM		 3202 uint32_t bo = BO(ctx->opcode);
3203 uint32_t bi = BI(ctx->opcode);
3204 uint32_t mask;
e98a6e40 3205
8cbcb4fa 3206 ctx->exception = POWERPC_EXCP_BRANCH;
e98a6e40 3207 if ((bo & 0x4) == 0)
d9bce9d9 3208 gen_op_dec_ctr();
e98a6e40
FB		 3209 switch(type) {
3210 case BCOND_IM:
76a66253
JM		 3211 li = (target_long)((int16_t)(BD(ctx->opcode)));
3212 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3213 target = ctx->nip + li - 4;
e98a6e40
FB		 3214 } else {
3215 target = li;
3216 }
e1833e1f
JM		 3217#if defined(TARGET_PPC64)
3218 if (!ctx->sf_mode)
3219 target = (uint32_t)target;
3220#endif
e98a6e40
FB		 3221 break;
3222 case BCOND_CTR:
3223 gen_op_movl_T1_ctr();
3224 break;
3225 default:
3226 case BCOND_LR:
3227 gen_op_movl_T1_lr();
3228 break;
3229 }
e1833e1f
JM		 3230 if (LK(ctx->opcode))
3231 gen_setlr(ctx, ctx->nip);
e98a6e40 3232 if (bo & 0x10) {
d9bce9d9
JM		 3233 /* No CR condition */
3234 switch (bo & 0x6) {
3235 case 0:
3236#if defined(TARGET_PPC64)
3237 if (ctx->sf_mode)
3238 gen_op_test_ctr_64();
3239 else
3240#endif
3241 gen_op_test_ctr();
3242 break;
3243 case 2:
3244#if defined(TARGET_PPC64)
3245 if (ctx->sf_mode)
3246 gen_op_test_ctrz_64();
3247 else
3248#endif
3249 gen_op_test_ctrz();
e98a6e40 3250 break;
e98a6e40 3251 default:
d9bce9d9
JM		 3252 case 4:
3253 case 6:
e98a6e40 3254 if (type == BCOND_IM) {
c1942362 3255 gen_goto_tb(ctx, 0, target);
8cbcb4fa 3256 return;
e98a6e40 3257 } else {
d9bce9d9
JM		 3258#if defined(TARGET_PPC64)
3259 if (ctx->sf_mode)
bd568f18 3260 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 3261 else
3262#endif
bd568f18 3263 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
056b05f8 3264 goto no_test;
e98a6e40 3265 }
056b05f8 3266 break;
e98a6e40 3267 }
d9bce9d9
JM		 3268 } else {
3269 mask = 1 << (3 - (bi & 0x03));
47e4661c 3270 tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]);
d9bce9d9
JM		 3271 if (bo & 0x8) {
3272 switch (bo & 0x6) {
3273 case 0:
3274#if defined(TARGET_PPC64)
3275 if (ctx->sf_mode)
3276 gen_op_test_ctr_true_64(mask);
3277 else
3278#endif
3279 gen_op_test_ctr_true(mask);
3280 break;
3281 case 2:
3282#if defined(TARGET_PPC64)
3283 if (ctx->sf_mode)
3284 gen_op_test_ctrz_true_64(mask);
3285 else
3286#endif
3287 gen_op_test_ctrz_true(mask);
3288 break;
3289 default:
3290 case 4:
3291 case 6:
e98a6e40 3292 gen_op_test_true(mask);
d9bce9d9
JM		 3293 break;
3294 }
3295 } else {
3296 switch (bo & 0x6) {
3297 case 0:
3298#if defined(TARGET_PPC64)
3299 if (ctx->sf_mode)
3300 gen_op_test_ctr_false_64(mask);
3301 else
3302#endif
3303 gen_op_test_ctr_false(mask);
3b46e624 3304 break;
d9bce9d9
JM		 3305 case 2:
3306#if defined(TARGET_PPC64)
3307 if (ctx->sf_mode)
3308 gen_op_test_ctrz_false_64(mask);
3309 else
3310#endif
3311 gen_op_test_ctrz_false(mask);
3312 break;
e98a6e40 3313 default:
d9bce9d9
JM		 3314 case 4:
3315 case 6:
e98a6e40 3316 gen_op_test_false(mask);
d9bce9d9
JM		 3317 break;
3318 }
3319 }
3320 }
e98a6e40 3321 if (type == BCOND_IM) {
c53be334
FB		 3322 int l1 = gen_new_label();
3323 gen_op_jz_T0(l1);
c1942362 3324 gen_goto_tb(ctx, 0, target);
c53be334 3325 gen_set_label(l1);
c1942362 3326 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3327 } else {
d9bce9d9
JM		 3328#if defined(TARGET_PPC64)
3329 if (ctx->sf_mode)
3330 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3331 else
3332#endif
3333 gen_op_btest_T1(ctx->nip);
36081602 3334 no_test:
57fec1fe 3335 tcg_gen_exit_tb(0);
08e46e54 3336 }
e98a6e40
FB		 3337}
3338
3339GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3340{
e98a6e40
FB		 3341 gen_bcond(ctx, BCOND_IM);
3342}
3343
3344GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3345{
e98a6e40
FB		 3346 gen_bcond(ctx, BCOND_CTR);
3347}
3348
3349GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3350{
e98a6e40
FB		 3351 gen_bcond(ctx, BCOND_LR);
3352}
79aceca5
FB		 3353
3354/*** Condition register logical ***/
3355#define GEN_CRLOGIC(op, opc) \
3356GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3357{ \
fc0d441e
JM		 3358 uint8_t bitmask; \
3359 int sh; \
47e4661c 3360 tcg_gen_mov_i32(cpu_T[0], cpu_crf[crbA(ctx->opcode) >> 2]); \
fc0d441e
JM		 3361 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3362 if (sh > 0) \
3363 gen_op_srli_T0(sh); \
3364 else if (sh < 0) \
3365 gen_op_sli_T0(-sh); \
47e4661c 3366 tcg_gen_mov_i32(cpu_T[1], cpu_crf[crbB(ctx->opcode) >> 2]); \
fc0d441e
JM		 3367 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3368 if (sh > 0) \
3369 gen_op_srli_T1(sh); \
3370 else if (sh < 0) \
3371 gen_op_sli_T1(-sh); \
79aceca5 3372 gen_op_##op(); \
fc0d441e 3373 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
0df5bdbe 3374 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], bitmask); \
47e4661c 3375 tcg_gen_andi_i32(cpu_T[1], cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
fc0d441e 3376 gen_op_or(); \
47e4661c 3377 tcg_gen_andi_i32(cpu_crf[crbD(ctx->opcode) >> 2], cpu_T[0], 0xf); \
79aceca5
FB		 3378}
3379
3380/* crand */
76a66253 3381GEN_CRLOGIC(and, 0x08);
79aceca5 3382/* crandc */
76a66253 3383GEN_CRLOGIC(andc, 0x04);
79aceca5 3384/* creqv */
76a66253 3385GEN_CRLOGIC(eqv, 0x09);
79aceca5 3386/* crnand */
76a66253 3387GEN_CRLOGIC(nand, 0x07);
79aceca5 3388/* crnor */
76a66253 3389GEN_CRLOGIC(nor, 0x01);
79aceca5 3390/* cror */
76a66253 3391GEN_CRLOGIC(or, 0x0E);
79aceca5 3392/* crorc */
76a66253 3393GEN_CRLOGIC(orc, 0x0D);
79aceca5 3394/* crxor */
76a66253 3395GEN_CRLOGIC(xor, 0x06);
79aceca5
FB		 3396/* mcrf */
3397GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3398{
47e4661c 3399 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3400}
3401
3402/*** System linkage ***/
3403/* rfi (supervisor only) */
76a66253 3404GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3405{
9a64fbe4 3406#if defined(CONFIG_USER_ONLY)
e1833e1f 3407 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3408#else
3409 /* Restore CPU state */
76a66253 3410 if (unlikely(!ctx->supervisor)) {
e1833e1f 3411 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3412 return;
9a64fbe4 3413 }
a42bd6cc 3414 gen_op_rfi();
e1833e1f 3415 GEN_SYNC(ctx);
9a64fbe4 3416#endif
79aceca5
FB		 3417}
3418
426613db 3419#if defined(TARGET_PPC64)
a750fc0b 3420GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3421{
3422#if defined(CONFIG_USER_ONLY)
e1833e1f 3423 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3424#else
3425 /* Restore CPU state */
3426 if (unlikely(!ctx->supervisor)) {
e1833e1f 3427 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3428 return;
3429 }
a42bd6cc 3430 gen_op_rfid();
e1833e1f 3431 GEN_SYNC(ctx);
426613db
JM		 3432#endif
3433}
426613db 3434
5b8105fa 3435GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3436{
3437#if defined(CONFIG_USER_ONLY)
3438 GEN_EXCP_PRIVOPC(ctx);
3439#else
3440 /* Restore CPU state */
3441 if (unlikely(ctx->supervisor <= 1)) {
3442 GEN_EXCP_PRIVOPC(ctx);
3443 return;
3444 }
3445 gen_op_hrfid();
3446 GEN_SYNC(ctx);
3447#endif
3448}
3449#endif
3450
79aceca5 3451/* sc */
417bf010
JM		 3452#if defined(CONFIG_USER_ONLY)
3453#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3454#else
3455#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3456#endif
e1833e1f 3457GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3458{
e1833e1f
JM		 3459 uint32_t lev;
3460
3461 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3462 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3463}
3464
3465/*** Trap ***/
3466/* tw */
76a66253 3467GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3468{
f78fb44e
AJ		 3469 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3470 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
a0ae05aa 3471 /* Update the nip since this might generate a trap exception */
d9bce9d9 3472 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3473 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3474}
3475
3476/* twi */
3477GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3478{
f78fb44e 3479 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3480 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3481 /* Update the nip since this might generate a trap exception */
3482 gen_update_nip(ctx, ctx->nip);
76a66253 3483 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3484}
3485
d9bce9d9
JM		 3486#if defined(TARGET_PPC64)
3487/* td */
3488GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3489{
f78fb44e
AJ		 3490 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3491 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3492 /* Update the nip since this might generate a trap exception */
3493 gen_update_nip(ctx, ctx->nip);
3494 gen_op_td(TO(ctx->opcode));
3495}
3496
3497/* tdi */
3498GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3499{
f78fb44e 3500 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3501 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3502 /* Update the nip since this might generate a trap exception */
3503 gen_update_nip(ctx, ctx->nip);
3504 gen_op_td(TO(ctx->opcode));
3505}
3506#endif
3507
79aceca5 3508/*** Processor control ***/
79aceca5
FB		 3509/* mcrxr */
3510GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3511{
3512 gen_op_load_xer_cr();
47e4661c 3513 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
e864cabd
JM		 3514 gen_op_clear_xer_ov();
3515 gen_op_clear_xer_ca();
79aceca5
FB		 3516}
3517
3518/* mfcr */
76a66253 3519GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3520{
76a66253 3521 uint32_t crm, crn;
3b46e624 3522
76a66253
JM		 3523 if (likely(ctx->opcode & 0x00100000)) {
3524 crm = CRM(ctx->opcode);
3525 if (likely((crm ^ (crm - 1)) == 0)) {
3526 crn = ffs(crm);
47e4661c 3527 tcg_gen_mov_i32(cpu_T[0], cpu_crf[7 - crn]);
76a66253 3528 }
d9bce9d9 3529 } else {
6676f424 3530 gen_op_load_cr();
d9bce9d9 3531 }
f78fb44e 3532 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 3533}
3534
3535/* mfmsr */
3536GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3537{
9a64fbe4 3538#if defined(CONFIG_USER_ONLY)
e1833e1f 3539 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3540#else
76a66253 3541 if (unlikely(!ctx->supervisor)) {
e1833e1f 3542 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3543 return;
9a64fbe4 3544 }
6676f424 3545 gen_op_load_msr();
f78fb44e 3546 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3547#endif
79aceca5
FB		 3548}
3549
a11b8151 3550#if 1
6f2d8978 3551#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3552#else
3553static void spr_noaccess (void *opaque, int sprn)
3554{
3555 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3556 printf("ERROR: try to access SPR %d !\n", sprn);
3557}
3558#define SPR_NOACCESS (&spr_noaccess)
3559#endif
3560
79aceca5 3561/* mfspr */
b068d6a7 3562static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3563{
3fc6c082 3564 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3565 uint32_t sprn = SPR(ctx->opcode);
3566
3fc6c082 3567#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3568 if (ctx->supervisor == 2)
3569 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3570 else if (ctx->supervisor)
3fc6c082
FB		 3571 read_cb = ctx->spr_cb[sprn].oea_read;
3572 else
9a64fbe4 3573#endif
3fc6c082 3574 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3575 if (likely(read_cb != NULL)) {
3576 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3577 (*read_cb)(ctx, sprn);
f78fb44e 3578 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3579 } else {
3580 /* Privilege exception */
9fceefa7
JM		 3581 /* This is a hack to avoid warnings when running Linux:
3582 * this OS breaks the PowerPC virtualisation model,
3583 * allowing userland application to read the PVR
3584 */
3585 if (sprn != SPR_PVR) {
3586 if (loglevel != 0) {
6b542af7 3587 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3588 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3589 }
077fc206
JM		 3590 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3591 sprn, sprn, ctx->nip);
f24e5695 3592 }
e1833e1f 3593 GEN_EXCP_PRIVREG(ctx);
79aceca5 3594 }
3fc6c082
FB		 3595 } else {
3596 /* Not defined */
4a057712 3597 if (loglevel != 0) {
077fc206
JM		 3598 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3599 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3600 }
077fc206
JM		 3601 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3602 sprn, sprn, ctx->nip);
e1833e1f
JM		 3603 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3604 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3605 }
79aceca5
FB		 3606}
3607
3fc6c082 3608GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3609{
3fc6c082 3610 gen_op_mfspr(ctx);
76a66253 3611}
3fc6c082
FB		 3612
3613/* mftb */
a750fc0b 3614GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3615{
3616 gen_op_mfspr(ctx);
79aceca5
FB		 3617}
3618
3619/* mtcrf */
8dd4983c 3620GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3621{
76a66253 3622 uint32_t crm, crn;
3b46e624 3623
f78fb44e 3624 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 3625 crm = CRM(ctx->opcode);
3626 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3627 crn = ffs(crm);
3628 gen_op_srli_T0(crn * 4);
47e4661c 3629 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_T[0], 0xf);
76a66253 3630 } else {
6676f424 3631 gen_op_store_cr(crm);
76a66253 3632 }
79aceca5
FB		 3633}
3634
3635/* mtmsr */
426613db 3636#if defined(TARGET_PPC64)
be147d08 3637GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3638{
3639#if defined(CONFIG_USER_ONLY)
e1833e1f 3640 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3641#else
3642 if (unlikely(!ctx->supervisor)) {
e1833e1f 3643 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3644 return;
3645 }
f78fb44e 3646 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3647 if (ctx->opcode & 0x00010000) {
3648 /* Special form that does not need any synchronisation */
3649 gen_op_update_riee();
3650 } else {
056b05f8
JM		 3651 /* XXX: we need to update nip before the store
3652 * if we enter power saving mode, we will exit the loop
3653 * directly from ppc_store_msr
3654 */
be147d08 3655 gen_update_nip(ctx, ctx->nip);
6676f424 3656 gen_op_store_msr();
be147d08
JM		 3657 /* Must stop the translation as machine state (may have) changed */
3658 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3659 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3660 }
426613db
JM		 3661#endif
3662}
3663#endif
3664
79aceca5
FB		 3665GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3666{
9a64fbe4 3667#if defined(CONFIG_USER_ONLY)
e1833e1f 3668 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3669#else
76a66253 3670 if (unlikely(!ctx->supervisor)) {
e1833e1f 3671 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3672 return;
9a64fbe4 3673 }
f78fb44e 3674 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3675 if (ctx->opcode & 0x00010000) {
3676 /* Special form that does not need any synchronisation */
3677 gen_op_update_riee();
3678 } else {
056b05f8
JM		 3679 /* XXX: we need to update nip before the store
3680 * if we enter power saving mode, we will exit the loop
3681 * directly from ppc_store_msr
3682 */
be147d08 3683 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3684#if defined(TARGET_PPC64)
be147d08 3685 if (!ctx->sf_mode)
6676f424 3686 gen_op_store_msr_32();
be147d08 3687 else
d9bce9d9 3688#endif
6676f424 3689 gen_op_store_msr();
be147d08
JM		 3690 /* Must stop the translation as machine state (may have) changed */
3691 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3692 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3693 }
9a64fbe4 3694#endif
79aceca5
FB		 3695}
3696
3697/* mtspr */
3698GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3699{
3fc6c082 3700 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3701 uint32_t sprn = SPR(ctx->opcode);
3702
3fc6c082 3703#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3704 if (ctx->supervisor == 2)
3705 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3706 else if (ctx->supervisor)
3fc6c082
FB		 3707 write_cb = ctx->spr_cb[sprn].oea_write;
3708 else
9a64fbe4 3709#endif
3fc6c082 3710 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3711 if (likely(write_cb != NULL)) {
3712 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 3713 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 3714 (*write_cb)(ctx, sprn);
3715 } else {
3716 /* Privilege exception */
4a057712 3717 if (loglevel != 0) {
077fc206
JM		 3718 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3719 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3720 }
077fc206
JM		 3721 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3722 sprn, sprn, ctx->nip);
e1833e1f 3723 GEN_EXCP_PRIVREG(ctx);
76a66253 3724 }
3fc6c082
FB		 3725 } else {
3726 /* Not defined */
4a057712 3727 if (loglevel != 0) {
077fc206
JM		 3728 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3729 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3730 }
077fc206
JM		 3731 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3732 sprn, sprn, ctx->nip);
e1833e1f
JM		 3733 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3734 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3735 }
79aceca5
FB		 3736}
3737
3738/*** Cache management ***/
79aceca5 3739/* dcbf */
0db1b20e 3740GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3741{
dac454af 3742 /* XXX: specification says this is treated as a load by the MMU */
b61f2753
AJ		 3743 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3744 gen_addr_reg_index(temp, ctx);
3745 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3746 tcg_temp_free(temp);
79aceca5
FB		 3747}
3748
3749/* dcbi (Supervisor only) */
9a64fbe4 3750GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3751{
a541f297 3752#if defined(CONFIG_USER_ONLY)
e1833e1f 3753 GEN_EXCP_PRIVOPC(ctx);
a541f297 3754#else
b61f2753 3755 TCGv EA, val;
76a66253 3756 if (unlikely(!ctx->supervisor)) {
e1833e1f 3757 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3758 return;
9a64fbe4 3759 }
b61f2753
AJ		 3760 EA = tcg_temp_new(TCG_TYPE_TL);
3761 gen_addr_reg_index(EA, ctx);
ed69522c 3762 val = tcg_temp_new(TCG_TYPE_TL);
76a66253 3763 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 3764 gen_qemu_ld8u(val, EA, ctx->mem_idx);
3765 gen_qemu_st8(val, EA, ctx->mem_idx);
3766 tcg_temp_free(val);
3767 tcg_temp_free(EA);
a541f297 3768#endif
79aceca5
FB		 3769}
3770
3771/* dcdst */
9a64fbe4 3772GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3773{
76a66253 3774 /* XXX: specification say this is treated as a load by the MMU */
b61f2753
AJ		 3775 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3776 gen_addr_reg_index(temp, ctx);
3777 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3778 tcg_temp_free(temp);
79aceca5
FB		 3779}
3780
3781/* dcbt */
0db1b20e 3782GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3783{
0db1b20e 3784 /* interpreted as no-op */
76a66253
JM		 3785 /* XXX: specification say this is treated as a load by the MMU
3786 * but does not generate any exception
3787 */
79aceca5
FB		 3788}
3789
3790/* dcbtst */
0db1b20e 3791GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3792{
0db1b20e 3793 /* interpreted as no-op */
76a66253
JM		 3794 /* XXX: specification say this is treated as a load by the MMU
3795 * but does not generate any exception
3796 */
79aceca5
FB		 3797}
3798
3799/* dcbz */
d63001d1 3800#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 3801static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3802 /* 32 bytes cache line size */
d63001d1 3803 {
7863667f
JM		 3804#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3805#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3806#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3807#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3808#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3809#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3810#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3811#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3812 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 3813 },
7863667f 3814 /* 64 bytes cache line size */
d63001d1 3815 {
7863667f
JM		 3816#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3817#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3818#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3819#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3820#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3821#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3822#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3823#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3824 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 3825 },
7863667f 3826 /* 128 bytes cache line size */
d63001d1 3827 {
7863667f
JM		 3828#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3829#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3830#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3831#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3832#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3833#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3834#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3835#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3836 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 3837 },
7863667f 3838 /* tunable cache line size */
d63001d1 3839 {
7863667f
JM		 3840#define gen_op_dcbz_le_raw gen_op_dcbz_raw
3841#define gen_op_dcbz_le_user gen_op_dcbz_user
3842#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3843#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3844#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3845#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3846#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3847#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3848 GEN_MEM_FUNCS(dcbz),
d63001d1 3849 },
76a66253 3850};
9a64fbe4 3851
b068d6a7
JM		 3852static always_inline void handler_dcbz (DisasContext *ctx,
3853 int dcache_line_size)
d63001d1
JM		 3854{
3855 int n;
3856
3857 switch (dcache_line_size) {
3858 case 32:
3859 n = 0;
3860 break;
3861 case 64:
3862 n = 1;
3863 break;
3864 case 128:
3865 n = 2;
3866 break;
3867 default:
3868 n = 3;
3869 break;
3870 }
3871 op_dcbz(n);
3872}
3873
3874GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 3875{
e2be8d8d 3876 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 3877 handler_dcbz(ctx, ctx->dcache_line_size);
3878 gen_op_check_reservation();
3879}
3880
c7697e1f 3881GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 3882{
e2be8d8d 3883 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 3884 if (ctx->opcode & 0x00200000)
3885 handler_dcbz(ctx, ctx->dcache_line_size);
3886 else
3887 handler_dcbz(ctx, -1);
4b3686fa 3888 gen_op_check_reservation();
79aceca5
FB		 3889}
3890
3891/* icbi */
36f69651 3892#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 3893#define gen_op_icbi_le_raw gen_op_icbi_raw
3894#define gen_op_icbi_le_user gen_op_icbi_user
3895#define gen_op_icbi_le_kernel gen_op_icbi_kernel
3896#define gen_op_icbi_le_hypv gen_op_icbi_hypv
3897#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3898#define gen_op_icbi_le_64_user gen_op_icbi_64_user
3899#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3900#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3901static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3902 GEN_MEM_FUNCS(icbi),
36f69651 3903};
e1833e1f 3904
1b413d55 3905GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 3906{
30032c94
JM		 3907 /* NIP cannot be restored if the memory exception comes from an helper */
3908 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3909 gen_addr_reg_index(cpu_T[0], ctx);
36f69651 3910 op_icbi();
79aceca5
FB		 3911}
3912
3913/* Optional: */
3914/* dcba */
a750fc0b 3915GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 3916{
0db1b20e
JM		 3917 /* interpreted as no-op */
3918 /* XXX: specification say this is treated as a store by the MMU
3919 * but does not generate any exception
3920 */
79aceca5
FB		 3921}
3922
3923/*** Segment register manipulation ***/
3924/* Supervisor only: */
3925/* mfsr */
3926GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3927{
9a64fbe4 3928#if defined(CONFIG_USER_ONLY)
e1833e1f 3929 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3930#else
76a66253 3931 if (unlikely(!ctx->supervisor)) {
e1833e1f 3932 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3933 return;
9a64fbe4 3934 }
86c581dc 3935 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 3936 gen_op_load_sr();
f78fb44e 3937 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3938#endif
79aceca5
FB		 3939}
3940
3941/* mfsrin */
9a64fbe4 3942GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 3943{
9a64fbe4 3944#if defined(CONFIG_USER_ONLY)
e1833e1f 3945 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3946#else
76a66253 3947 if (unlikely(!ctx->supervisor)) {
e1833e1f 3948 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3949 return;
9a64fbe4 3950 }
f78fb44e 3951 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 3952 gen_op_srli_T1(28);
3953 gen_op_load_sr();
f78fb44e 3954 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3955#endif
79aceca5
FB		 3956}
3957
3958/* mtsr */
e63c59cb 3959GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 3960{
9a64fbe4 3961#if defined(CONFIG_USER_ONLY)
e1833e1f 3962 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3963#else
76a66253 3964 if (unlikely(!ctx->supervisor)) {
e1833e1f 3965 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3966 return;
9a64fbe4 3967 }
f78fb44e 3968 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 3969 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 3970 gen_op_store_sr();
9a64fbe4 3971#endif
79aceca5
FB		 3972}
3973
3974/* mtsrin */
9a64fbe4 3975GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 3976{
9a64fbe4 3977#if defined(CONFIG_USER_ONLY)
e1833e1f 3978 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3979#else
76a66253 3980 if (unlikely(!ctx->supervisor)) {
e1833e1f 3981 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3982 return;
9a64fbe4 3983 }
f78fb44e
AJ		 3984 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3985 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 3986 gen_op_srli_T1(28);
3987 gen_op_store_sr();
9a64fbe4 3988#endif
79aceca5
FB		 3989}
3990
12de9a39
JM		 3991#if defined(TARGET_PPC64)
3992/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3993/* mfsr */
c7697e1f 3994GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 3995{
3996#if defined(CONFIG_USER_ONLY)
3997 GEN_EXCP_PRIVREG(ctx);
3998#else
3999 if (unlikely(!ctx->supervisor)) {
4000 GEN_EXCP_PRIVREG(ctx);
4001 return;
4002 }
86c581dc 4003 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4004 gen_op_load_slb();
f78fb44e 4005 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4006#endif
4007}
4008
4009/* mfsrin */
c7697e1f
JM		 4010GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4011 PPC_SEGMENT_64B)
12de9a39
JM		 4012{
4013#if defined(CONFIG_USER_ONLY)
4014 GEN_EXCP_PRIVREG(ctx);
4015#else
4016 if (unlikely(!ctx->supervisor)) {
4017 GEN_EXCP_PRIVREG(ctx);
4018 return;
4019 }
f78fb44e 4020 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4021 gen_op_srli_T1(28);
4022 gen_op_load_slb();
f78fb44e 4023 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4024#endif
4025}
4026
4027/* mtsr */
c7697e1f 4028GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4029{
4030#if defined(CONFIG_USER_ONLY)
4031 GEN_EXCP_PRIVREG(ctx);
4032#else
4033 if (unlikely(!ctx->supervisor)) {
4034 GEN_EXCP_PRIVREG(ctx);
4035 return;
4036 }
f78fb44e 4037 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4038 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4039 gen_op_store_slb();
4040#endif
4041}
4042
4043/* mtsrin */
c7697e1f
JM		 4044GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4045 PPC_SEGMENT_64B)
12de9a39
JM		 4046{
4047#if defined(CONFIG_USER_ONLY)
4048 GEN_EXCP_PRIVREG(ctx);
4049#else
4050 if (unlikely(!ctx->supervisor)) {
4051 GEN_EXCP_PRIVREG(ctx);
4052 return;
4053 }
f78fb44e
AJ		 4054 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4055 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4056 gen_op_srli_T1(28);
4057 gen_op_store_slb();
4058#endif
4059}
4060#endif /* defined(TARGET_PPC64) */
4061
79aceca5
FB		 4062/*** Lookaside buffer management ***/
4063/* Optional & supervisor only: */
4064/* tlbia */
3fc6c082 4065GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4066{
9a64fbe4 4067#if defined(CONFIG_USER_ONLY)
e1833e1f 4068 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4069#else
76a66253 4070 if (unlikely(!ctx->supervisor)) {
e1833e1f 4071 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4072 return;
9a64fbe4
FB		 4073 }
4074 gen_op_tlbia();
4075#endif
79aceca5
FB		 4076}
4077
4078/* tlbie */
76a66253 4079GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4080{
9a64fbe4 4081#if defined(CONFIG_USER_ONLY)
e1833e1f 4082 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4083#else
76a66253 4084 if (unlikely(!ctx->supervisor)) {
e1833e1f 4085 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4086 return;
9a64fbe4 4087 }
f78fb44e 4088 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4089#if defined(TARGET_PPC64)
4090 if (ctx->sf_mode)
4091 gen_op_tlbie_64();
4092 else
4093#endif
4094 gen_op_tlbie();
9a64fbe4 4095#endif
79aceca5
FB		 4096}
4097
4098/* tlbsync */
76a66253 4099GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4100{
9a64fbe4 4101#if defined(CONFIG_USER_ONLY)
e1833e1f 4102 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4103#else
76a66253 4104 if (unlikely(!ctx->supervisor)) {
e1833e1f 4105 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4106 return;
9a64fbe4
FB		 4107 }
4108 /* This has no effect: it should ensure that all previous
4109 * tlbie have completed
4110 */
e1833e1f 4111 GEN_STOP(ctx);
9a64fbe4 4112#endif
79aceca5
FB		 4113}
4114
426613db
JM		 4115#if defined(TARGET_PPC64)
4116/* slbia */
4117GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4118{
4119#if defined(CONFIG_USER_ONLY)
e1833e1f 4120 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4121#else
4122 if (unlikely(!ctx->supervisor)) {
e1833e1f 4123 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4124 return;
4125 }
4126 gen_op_slbia();
426613db
JM		 4127#endif
4128}
4129
4130/* slbie */
4131GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4132{
4133#if defined(CONFIG_USER_ONLY)
e1833e1f 4134 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4135#else
4136 if (unlikely(!ctx->supervisor)) {
e1833e1f 4137 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4138 return;
4139 }
f78fb44e 4140 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4141 gen_op_slbie();
426613db
JM		 4142#endif
4143}
4144#endif
4145
79aceca5
FB		 4146/*** External control ***/
4147/* Optional: */
9a64fbe4
FB		 4148#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4149#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4150static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4151 GEN_MEM_FUNCS(eciwx),
111bfab3 4152};
7863667f
JM		 4153static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4154 GEN_MEM_FUNCS(ecowx),
111bfab3 4155};
9a64fbe4 4156
111bfab3 4157/* eciwx */
79aceca5
FB		 4158GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4159{
9a64fbe4 4160 /* Should check EAR[E] & alignment ! */
e2be8d8d 4161 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4162 op_eciwx();
f78fb44e 4163 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4164}
4165
4166/* ecowx */
4167GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4168{
4169 /* Should check EAR[E] & alignment ! */
e2be8d8d 4170 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4171 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4172 op_ecowx();
4173}
4174
4175/* PowerPC 601 specific instructions */
4176/* abs - abs. */
4177GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4178{
f78fb44e 4179 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4180 gen_op_POWER_abs();
f78fb44e 4181 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4182 if (unlikely(Rc(ctx->opcode) != 0))
4183 gen_set_Rc0(ctx);
4184}
4185
4186/* abso - abso. */
4187GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4188{
f78fb44e 4189 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4190 gen_op_POWER_abso();
f78fb44e 4191 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4192 if (unlikely(Rc(ctx->opcode) != 0))
4193 gen_set_Rc0(ctx);
4194}
4195
4196/* clcs */
a750fc0b 4197GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4198{
f78fb44e 4199 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4200 gen_op_POWER_clcs();
c7697e1f 4201 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4202 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4203}
4204
4205/* div - div. */
4206GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4207{
f78fb44e
AJ		 4208 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4209 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4210 gen_op_POWER_div();
f78fb44e 4211 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4212 if (unlikely(Rc(ctx->opcode) != 0))
4213 gen_set_Rc0(ctx);
4214}
4215
4216/* divo - divo. */
4217GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4218{
f78fb44e
AJ		 4219 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4220 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4221 gen_op_POWER_divo();
f78fb44e 4222 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4223 if (unlikely(Rc(ctx->opcode) != 0))
4224 gen_set_Rc0(ctx);
4225}
4226
4227/* divs - divs. */
4228GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4229{
f78fb44e
AJ		 4230 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4231 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4232 gen_op_POWER_divs();
f78fb44e 4233 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4234 if (unlikely(Rc(ctx->opcode) != 0))
4235 gen_set_Rc0(ctx);
4236}
4237
4238/* divso - divso. */
4239GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4240{
f78fb44e
AJ		 4241 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4242 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4243 gen_op_POWER_divso();
f78fb44e 4244 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4245 if (unlikely(Rc(ctx->opcode) != 0))
4246 gen_set_Rc0(ctx);
4247}
4248
4249/* doz - doz. */
4250GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4251{
f78fb44e
AJ		 4252 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4253 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4254 gen_op_POWER_doz();
f78fb44e 4255 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4256 if (unlikely(Rc(ctx->opcode) != 0))
4257 gen_set_Rc0(ctx);
4258}
4259
4260/* dozo - dozo. */
4261GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4262{
f78fb44e
AJ		 4263 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4264 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4265 gen_op_POWER_dozo();
f78fb44e 4266 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4267 if (unlikely(Rc(ctx->opcode) != 0))
4268 gen_set_Rc0(ctx);
4269}
4270
4271/* dozi */
4272GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4273{
f78fb44e 4274 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4275 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4276 gen_op_POWER_doz();
f78fb44e 4277 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4278}
4279
7863667f
JM		 4280/* As lscbx load from memory byte after byte, it's always endian safe.
4281 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4282 */
2857068e 4283#define op_POWER_lscbx(start, ra, rb) \
76a66253 4284(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 4285#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4286#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4287#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4288#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4289#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4290#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4291#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4292#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4293#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4294#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4295#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4296#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4297static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4298 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4299};
76a66253
JM		 4300
4301/* lscbx - lscbx. */
4302GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4303{
4304 int ra = rA(ctx->opcode);
4305 int rb = rB(ctx->opcode);
4306
e2be8d8d 4307 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4308 if (ra == 0) {
4309 ra = rb;
4310 }
4311 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4312 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4313 gen_op_load_xer_bc();
4314 gen_op_load_xer_cmp();
4315 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4316 gen_op_store_xer_bc();
4317 if (unlikely(Rc(ctx->opcode) != 0))
4318 gen_set_Rc0(ctx);
4319}
4320
4321/* maskg - maskg. */
4322GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4323{
f78fb44e
AJ		 4324 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4325 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4326 gen_op_POWER_maskg();
f78fb44e 4327 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4328 if (unlikely(Rc(ctx->opcode) != 0))
4329 gen_set_Rc0(ctx);
4330}
4331
4332/* maskir - maskir. */
4333GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4334{
f78fb44e
AJ		 4335 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4336 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4337 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4338 gen_op_POWER_maskir();
f78fb44e 4339 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4340 if (unlikely(Rc(ctx->opcode) != 0))
4341 gen_set_Rc0(ctx);
4342}
4343
4344/* mul - mul. */
4345GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4346{
f78fb44e
AJ		 4347 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4348 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4349 gen_op_POWER_mul();
f78fb44e 4350 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4351 if (unlikely(Rc(ctx->opcode) != 0))
4352 gen_set_Rc0(ctx);
4353}
4354
4355/* mulo - mulo. */
4356GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4357{
f78fb44e
AJ		 4358 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4359 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4360 gen_op_POWER_mulo();
f78fb44e 4361 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4362 if (unlikely(Rc(ctx->opcode) != 0))
4363 gen_set_Rc0(ctx);
4364}
4365
4366/* nabs - nabs. */
4367GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4368{
f78fb44e 4369 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4370 gen_op_POWER_nabs();
f78fb44e 4371 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4372 if (unlikely(Rc(ctx->opcode) != 0))
4373 gen_set_Rc0(ctx);
4374}
4375
4376/* nabso - nabso. */
4377GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4378{
f78fb44e 4379 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4380 gen_op_POWER_nabso();
f78fb44e 4381 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4382 if (unlikely(Rc(ctx->opcode) != 0))
4383 gen_set_Rc0(ctx);
4384}
4385
4386/* rlmi - rlmi. */
4387GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4388{
4389 uint32_t mb, me;
4390
4391 mb = MB(ctx->opcode);
4392 me = ME(ctx->opcode);
f78fb44e
AJ		 4393 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4394 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4395 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4396 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4397 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4398 if (unlikely(Rc(ctx->opcode) != 0))
4399 gen_set_Rc0(ctx);
4400}
4401
4402/* rrib - rrib. */
4403GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4404{
f78fb44e
AJ		 4405 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4406 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4407 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4408 gen_op_POWER_rrib();
f78fb44e 4409 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4410 if (unlikely(Rc(ctx->opcode) != 0))
4411 gen_set_Rc0(ctx);
4412}
4413
4414/* sle - sle. */
4415GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4416{
f78fb44e
AJ		 4417 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4418 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4419 gen_op_POWER_sle();
f78fb44e 4420 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4421 if (unlikely(Rc(ctx->opcode) != 0))
4422 gen_set_Rc0(ctx);
4423}
4424
4425/* sleq - sleq. */
4426GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4427{
f78fb44e
AJ		 4428 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4429 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4430 gen_op_POWER_sleq();
f78fb44e 4431 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4432 if (unlikely(Rc(ctx->opcode) != 0))
4433 gen_set_Rc0(ctx);
4434}
4435
4436/* sliq - sliq. */
4437GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4438{
f78fb44e 4439 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4440 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4441 gen_op_POWER_sle();
f78fb44e 4442 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4443 if (unlikely(Rc(ctx->opcode) != 0))
4444 gen_set_Rc0(ctx);
4445}
4446
4447/* slliq - slliq. */
4448GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4449{
f78fb44e 4450 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4451 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4452 gen_op_POWER_sleq();
f78fb44e 4453 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4454 if (unlikely(Rc(ctx->opcode) != 0))
4455 gen_set_Rc0(ctx);
4456}
4457
4458/* sllq - sllq. */
4459GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4460{
f78fb44e
AJ		 4461 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4462 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4463 gen_op_POWER_sllq();
f78fb44e 4464 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4465 if (unlikely(Rc(ctx->opcode) != 0))
4466 gen_set_Rc0(ctx);
4467}
4468
4469/* slq - slq. */
4470GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4471{
f78fb44e
AJ		 4472 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4473 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4474 gen_op_POWER_slq();
f78fb44e 4475 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4476 if (unlikely(Rc(ctx->opcode) != 0))
4477 gen_set_Rc0(ctx);
4478}
4479
d9bce9d9 4480/* sraiq - sraiq. */
76a66253
JM		 4481GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4482{
f78fb44e 4483 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4484 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4485 gen_op_POWER_sraq();
f78fb44e 4486 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4487 if (unlikely(Rc(ctx->opcode) != 0))
4488 gen_set_Rc0(ctx);
4489}
4490
4491/* sraq - sraq. */
4492GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4493{
f78fb44e
AJ		 4494 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4495 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4496 gen_op_POWER_sraq();
f78fb44e 4497 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4498 if (unlikely(Rc(ctx->opcode) != 0))
4499 gen_set_Rc0(ctx);
4500}
4501
4502/* sre - sre. */
4503GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4504{
f78fb44e
AJ		 4505 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4506 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4507 gen_op_POWER_sre();
f78fb44e 4508 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4509 if (unlikely(Rc(ctx->opcode) != 0))
4510 gen_set_Rc0(ctx);
4511}
4512
4513/* srea - srea. */
4514GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4515{
f78fb44e
AJ		 4516 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4517 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4518 gen_op_POWER_srea();
f78fb44e 4519 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4520 if (unlikely(Rc(ctx->opcode) != 0))
4521 gen_set_Rc0(ctx);
4522}
4523
4524/* sreq */
4525GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4526{
f78fb44e
AJ		 4527 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4528 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4529 gen_op_POWER_sreq();
f78fb44e 4530 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4531 if (unlikely(Rc(ctx->opcode) != 0))
4532 gen_set_Rc0(ctx);
4533}
4534
4535/* sriq */
4536GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4537{
f78fb44e 4538 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4539 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4540 gen_op_POWER_srq();
f78fb44e 4541 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4542 if (unlikely(Rc(ctx->opcode) != 0))
4543 gen_set_Rc0(ctx);
4544}
4545
4546/* srliq */
4547GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4548{
f78fb44e
AJ		 4549 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4550 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4551 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4552 gen_op_POWER_srlq();
f78fb44e 4553 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4554 if (unlikely(Rc(ctx->opcode) != 0))
4555 gen_set_Rc0(ctx);
4556}
4557
4558/* srlq */
4559GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4560{
f78fb44e
AJ		 4561 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4562 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4563 gen_op_POWER_srlq();
f78fb44e 4564 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4565 if (unlikely(Rc(ctx->opcode) != 0))
4566 gen_set_Rc0(ctx);
4567}
4568
4569/* srq */
4570GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4571{
f78fb44e
AJ		 4572 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4573 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4574 gen_op_POWER_srq();
f78fb44e 4575 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4576 if (unlikely(Rc(ctx->opcode) != 0))
4577 gen_set_Rc0(ctx);
4578}
4579
4580/* PowerPC 602 specific instructions */
4581/* dsa */
4582GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4583{
4584 /* XXX: TODO */
e1833e1f 4585 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4586}
4587
4588/* esa */
4589GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4590{
4591 /* XXX: TODO */
e1833e1f 4592 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4593}
4594
4595/* mfrom */
4596GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4597{
4598#if defined(CONFIG_USER_ONLY)
e1833e1f 4599 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4600#else
4601 if (unlikely(!ctx->supervisor)) {
e1833e1f 4602 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4603 return;
4604 }
f78fb44e 4605 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4606 gen_op_602_mfrom();
f78fb44e 4607 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4608#endif
4609}
4610
4611/* 602 - 603 - G2 TLB management */
4612/* tlbld */
c7697e1f 4613GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4614{
4615#if defined(CONFIG_USER_ONLY)
e1833e1f 4616 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4617#else
4618 if (unlikely(!ctx->supervisor)) {
e1833e1f 4619 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4620 return;
4621 }
f78fb44e 4622 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4623 gen_op_6xx_tlbld();
76a66253
JM		 4624#endif
4625}
4626
4627/* tlbli */
c7697e1f 4628GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4629{
4630#if defined(CONFIG_USER_ONLY)
e1833e1f 4631 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4632#else
4633 if (unlikely(!ctx->supervisor)) {
e1833e1f 4634 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4635 return;
4636 }
f78fb44e 4637 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4638 gen_op_6xx_tlbli();
76a66253
JM		 4639#endif
4640}
4641
7dbe11ac
JM		 4642/* 74xx TLB management */
4643/* tlbld */
c7697e1f 4644GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4645{
4646#if defined(CONFIG_USER_ONLY)
4647 GEN_EXCP_PRIVOPC(ctx);
4648#else
4649 if (unlikely(!ctx->supervisor)) {
4650 GEN_EXCP_PRIVOPC(ctx);
4651 return;
4652 }
f78fb44e 4653 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4654 gen_op_74xx_tlbld();
4655#endif
4656}
4657
4658/* tlbli */
c7697e1f 4659GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4660{
4661#if defined(CONFIG_USER_ONLY)
4662 GEN_EXCP_PRIVOPC(ctx);
4663#else
4664 if (unlikely(!ctx->supervisor)) {
4665 GEN_EXCP_PRIVOPC(ctx);
4666 return;
4667 }
f78fb44e 4668 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4669 gen_op_74xx_tlbli();
4670#endif
4671}
4672
76a66253
JM		 4673/* POWER instructions not in PowerPC 601 */
4674/* clf */
4675GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4676{
4677 /* Cache line flush: implemented as no-op */
4678}
4679
4680/* cli */
4681GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4682{
7f75ffd3 4683 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4684#if defined(CONFIG_USER_ONLY)
e1833e1f 4685 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4686#else
4687 if (unlikely(!ctx->supervisor)) {
e1833e1f 4688 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4689 return;
4690 }
4691#endif
4692}
4693
4694/* dclst */
4695GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4696{
4697 /* Data cache line store: treated as no-op */
4698}
4699
4700GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4701{
4702#if defined(CONFIG_USER_ONLY)
e1833e1f 4703 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4704#else
4705 if (unlikely(!ctx->supervisor)) {
e1833e1f 4706 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4707 return;
4708 }
4709 int ra = rA(ctx->opcode);
4710 int rd = rD(ctx->opcode);
4711
e2be8d8d 4712 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4713 gen_op_POWER_mfsri();
f78fb44e 4714 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4715 if (ra != 0 && ra != rd)
f78fb44e 4716 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4717#endif
4718}
4719
4720GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4721{
4722#if defined(CONFIG_USER_ONLY)
e1833e1f 4723 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4724#else
4725 if (unlikely(!ctx->supervisor)) {
e1833e1f 4726 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4727 return;
4728 }
e2be8d8d 4729 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4730 gen_op_POWER_rac();
f78fb44e 4731 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4732#endif
4733}
4734
4735GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4736{
4737#if defined(CONFIG_USER_ONLY)
e1833e1f 4738 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4739#else
4740 if (unlikely(!ctx->supervisor)) {
e1833e1f 4741 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4742 return;
4743 }
4744 gen_op_POWER_rfsvc();
e1833e1f 4745 GEN_SYNC(ctx);
76a66253
JM		 4746#endif
4747}
4748
4749/* svc is not implemented for now */
4750
4751/* POWER2 specific instructions */
4752/* Quad manipulation (load/store two floats at a time) */
7863667f 4753/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 4754#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4755#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 4756#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4757#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4758#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4759#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4760#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4761#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4762#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4763#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4764#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4765#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4766#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4767#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4768#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4769#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4770#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4771#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4772static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4773 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 4774};
7863667f
JM		 4775static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4776 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 4777};
76a66253
JM		 4778
4779/* lfq */
4780GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4781{
4782 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4783 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4784 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4785 op_POWER2_lfq();
a5e26afa
AJ		 4786 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4787 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4788}
4789
4790/* lfqu */
4791GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4792{
4793 int ra = rA(ctx->opcode);
4794
4795 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4796 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4797 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4798 op_POWER2_lfq();
a5e26afa
AJ		 4799 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4800 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4801 if (ra != 0)
f78fb44e 4802 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4803}
4804
4805/* lfqux */
4806GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4807{
4808 int ra = rA(ctx->opcode);
4809
4810 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4811 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4812 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4813 op_POWER2_lfq();
a5e26afa
AJ		 4814 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4815 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4816 if (ra != 0)
f78fb44e 4817 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4818}
4819
4820/* lfqx */
4821GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4822{
4823 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4824 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4825 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4826 op_POWER2_lfq();
a5e26afa
AJ		 4827 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4828 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4829}
4830
4831/* stfq */
4832GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4833{
4834 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4835 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4836 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4837 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4838 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4839 op_POWER2_stfq();
4840}
4841
4842/* stfqu */
4843GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4844{
4845 int ra = rA(ctx->opcode);
4846
4847 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4848 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4849 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4850 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4851 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4852 op_POWER2_stfq();
4853 if (ra != 0)
f78fb44e 4854 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4855}
4856
4857/* stfqux */
4858GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4859{
4860 int ra = rA(ctx->opcode);
4861
4862 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4863 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4864 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 4865 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4866 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4867 op_POWER2_stfq();
4868 if (ra != 0)
f78fb44e 4869 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4870}
4871
4872/* stfqx */
4873GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4874{
4875 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4876 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4877 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 4878 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4879 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4880 op_POWER2_stfq();
4881}
4882
4883/* BookE specific instructions */
2662a059 4884/* XXX: not implemented on 440 ? */
05332d70 4885GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 4886{
4887 /* XXX: TODO */
e1833e1f 4888 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4889}
4890
2662a059 4891/* XXX: not implemented on 440 ? */
05332d70 4892GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 4893{
4894#if defined(CONFIG_USER_ONLY)
e1833e1f 4895 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4896#else
4897 if (unlikely(!ctx->supervisor)) {
e1833e1f 4898 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4899 return;
4900 }
e2be8d8d 4901 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4902 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 4903#if defined(TARGET_PPC64)
4904 if (ctx->sf_mode)
4905 gen_op_tlbie_64();
4906 else
4907#endif
4908 gen_op_tlbie();
76a66253
JM		 4909#endif
4910}
4911
4912/* All 405 MAC instructions are translated here */
b068d6a7
JM		 4913static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4914 int opc2, int opc3,
4915 int ra, int rb, int rt, int Rc)
76a66253 4916{
f78fb44e
AJ		 4917 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
4918 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 4919 switch (opc3 & 0x0D) {
4920 case 0x05:
4921 /* macchw - macchw. - macchwo - macchwo. */
4922 /* macchws - macchws. - macchwso - macchwso. */
4923 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4924 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4925 /* mulchw - mulchw. */
4926 gen_op_405_mulchw();
4927 break;
4928 case 0x04:
4929 /* macchwu - macchwu. - macchwuo - macchwuo. */
4930 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4931 /* mulchwu - mulchwu. */
4932 gen_op_405_mulchwu();
4933 break;
4934 case 0x01:
4935 /* machhw - machhw. - machhwo - machhwo. */
4936 /* machhws - machhws. - machhwso - machhwso. */
4937 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4938 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4939 /* mulhhw - mulhhw. */
4940 gen_op_405_mulhhw();
4941 break;
4942 case 0x00:
4943 /* machhwu - machhwu. - machhwuo - machhwuo. */
4944 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4945 /* mulhhwu - mulhhwu. */
4946 gen_op_405_mulhhwu();
4947 break;
4948 case 0x0D:
4949 /* maclhw - maclhw. - maclhwo - maclhwo. */
4950 /* maclhws - maclhws. - maclhwso - maclhwso. */
4951 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4952 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4953 /* mullhw - mullhw. */
4954 gen_op_405_mullhw();
4955 break;
4956 case 0x0C:
4957 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4958 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4959 /* mullhwu - mullhwu. */
4960 gen_op_405_mullhwu();
4961 break;
4962 }
4963 if (opc2 & 0x02) {
4964 /* nmultiply-and-accumulate (0x0E) */
4965 gen_op_neg();
4966 }
4967 if (opc2 & 0x04) {
4968 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
f78fb44e 4969 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
e55fd934 4970 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
76a66253
JM		 4971 gen_op_405_add_T0_T2();
4972 }
4973 if (opc3 & 0x10) {
4974 /* Check overflow */
4975 if (opc3 & 0x01)
c3e10c7b 4976 gen_op_check_addo();
76a66253
JM		 4977 else
4978 gen_op_405_check_ovu();
4979 }
4980 if (opc3 & 0x02) {
4981 /* Saturate */
4982 if (opc3 & 0x01)
4983 gen_op_405_check_sat();
4984 else
4985 gen_op_405_check_satu();
4986 }
f78fb44e 4987 tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
76a66253
JM		 4988 if (unlikely(Rc) != 0) {
4989 /* Update Rc0 */
4990 gen_set_Rc0(ctx);
4991 }
4992}
4993
a750fc0b
JM		 4994#define GEN_MAC_HANDLER(name, opc2, opc3) \
4995GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 4996{ \
4997 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4998 rD(ctx->opcode), Rc(ctx->opcode)); \
4999}
5000
5001/* macchw - macchw. */
a750fc0b 5002GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5003/* macchwo - macchwo. */
a750fc0b 5004GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5005/* macchws - macchws. */
a750fc0b 5006GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5007/* macchwso - macchwso. */
a750fc0b 5008GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5009/* macchwsu - macchwsu. */
a750fc0b 5010GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5011/* macchwsuo - macchwsuo. */
a750fc0b 5012GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5013/* macchwu - macchwu. */
a750fc0b 5014GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5015/* macchwuo - macchwuo. */
a750fc0b 5016GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5017/* machhw - machhw. */
a750fc0b 5018GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5019/* machhwo - machhwo. */
a750fc0b 5020GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5021/* machhws - machhws. */
a750fc0b 5022GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5023/* machhwso - machhwso. */
a750fc0b 5024GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5025/* machhwsu - machhwsu. */
a750fc0b 5026GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5027/* machhwsuo - machhwsuo. */
a750fc0b 5028GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5029/* machhwu - machhwu. */
a750fc0b 5030GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5031/* machhwuo - machhwuo. */
a750fc0b 5032GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5033/* maclhw - maclhw. */
a750fc0b 5034GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5035/* maclhwo - maclhwo. */
a750fc0b 5036GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5037/* maclhws - maclhws. */
a750fc0b 5038GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5039/* maclhwso - maclhwso. */
a750fc0b 5040GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5041/* maclhwu - maclhwu. */
a750fc0b 5042GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5043/* maclhwuo - maclhwuo. */
a750fc0b 5044GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5045/* maclhwsu - maclhwsu. */
a750fc0b 5046GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5047/* maclhwsuo - maclhwsuo. */
a750fc0b 5048GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5049/* nmacchw - nmacchw. */
a750fc0b 5050GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5051/* nmacchwo - nmacchwo. */
a750fc0b 5052GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5053/* nmacchws - nmacchws. */
a750fc0b 5054GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5055/* nmacchwso - nmacchwso. */
a750fc0b 5056GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5057/* nmachhw - nmachhw. */
a750fc0b 5058GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5059/* nmachhwo - nmachhwo. */
a750fc0b 5060GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5061/* nmachhws - nmachhws. */
a750fc0b 5062GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5063/* nmachhwso - nmachhwso. */
a750fc0b 5064GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5065/* nmaclhw - nmaclhw. */
a750fc0b 5066GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5067/* nmaclhwo - nmaclhwo. */
a750fc0b 5068GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5069/* nmaclhws - nmaclhws. */
a750fc0b 5070GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5071/* nmaclhwso - nmaclhwso. */
a750fc0b 5072GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5073
5074/* mulchw - mulchw. */
a750fc0b 5075GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5076/* mulchwu - mulchwu. */
a750fc0b 5077GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5078/* mulhhw - mulhhw. */
a750fc0b 5079GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5080/* mulhhwu - mulhhwu. */
a750fc0b 5081GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5082/* mullhw - mullhw. */
a750fc0b 5083GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5084/* mullhwu - mullhwu. */
a750fc0b 5085GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5086
5087/* mfdcr */
05332d70 5088GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5089{
5090#if defined(CONFIG_USER_ONLY)
e1833e1f 5091 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5092#else
5093 uint32_t dcrn = SPR(ctx->opcode);
5094
5095 if (unlikely(!ctx->supervisor)) {
e1833e1f 5096 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5097 return;
5098 }
86c581dc 5099 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5100 gen_op_load_dcr();
f78fb44e 5101 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5102#endif
5103}
5104
5105/* mtdcr */
05332d70 5106GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5107{
5108#if defined(CONFIG_USER_ONLY)
e1833e1f 5109 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5110#else
5111 uint32_t dcrn = SPR(ctx->opcode);
5112
5113 if (unlikely(!ctx->supervisor)) {
e1833e1f 5114 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5115 return;
5116 }
86c581dc 5117 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5118 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5119 gen_op_store_dcr();
5120#endif
5121}
5122
5123/* mfdcrx */
2662a059 5124/* XXX: not implemented on 440 ? */
05332d70 5125GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5126{
5127#if defined(CONFIG_USER_ONLY)
e1833e1f 5128 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5129#else
5130 if (unlikely(!ctx->supervisor)) {
e1833e1f 5131 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5132 return;
5133 }
f78fb44e 5134 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5135 gen_op_load_dcr();
f78fb44e 5136 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5137 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5138#endif
5139}
5140
5141/* mtdcrx */
2662a059 5142/* XXX: not implemented on 440 ? */
05332d70 5143GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5144{
5145#if defined(CONFIG_USER_ONLY)
e1833e1f 5146 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5147#else
5148 if (unlikely(!ctx->supervisor)) {
e1833e1f 5149 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5150 return;
5151 }
f78fb44e
AJ		 5152 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5153 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5154 gen_op_store_dcr();
a750fc0b 5155 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5156#endif
5157}
5158
a750fc0b
JM		 5159/* mfdcrux (PPC 460) : user-mode access to DCR */
5160GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5161{
f78fb44e 5162 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5163 gen_op_load_dcr();
f78fb44e 5164 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5165 /* Note: Rc update flag set leads to undefined state of Rc0 */
5166}
5167
5168/* mtdcrux (PPC 460) : user-mode access to DCR */
5169GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5170{
f78fb44e
AJ		 5171 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5172 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5173 gen_op_store_dcr();
5174 /* Note: Rc update flag set leads to undefined state of Rc0 */
5175}
5176
76a66253
JM		 5177/* dccci */
5178GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5179{
5180#if defined(CONFIG_USER_ONLY)
e1833e1f 5181 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5182#else
5183 if (unlikely(!ctx->supervisor)) {
e1833e1f 5184 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5185 return;
5186 }
5187 /* interpreted as no-op */
5188#endif
5189}
5190
5191/* dcread */
5192GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5193{
5194#if defined(CONFIG_USER_ONLY)
e1833e1f 5195 GEN_EXCP_PRIVOPC(ctx);
76a66253 5196#else
b61f2753 5197 TCGv EA, val;
76a66253 5198 if (unlikely(!ctx->supervisor)) {
e1833e1f 5199 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5200 return;
5201 }
b61f2753
AJ		 5202 EA = tcg_temp_new(TCG_TYPE_TL);
5203 gen_addr_reg_index(EA, ctx);
5204 val = tcg_temp_new(TCG_TYPE_TL);
5205 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5206 tcg_temp_free(val);
5207 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5208 tcg_temp_free(EA);
76a66253
JM		 5209#endif
5210}
5211
5212/* icbt */
c7697e1f 5213GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5214{
5215 /* interpreted as no-op */
5216 /* XXX: specification say this is treated as a load by the MMU
5217 * but does not generate any exception
5218 */
5219}
5220
5221/* iccci */
5222GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5223{
5224#if defined(CONFIG_USER_ONLY)
e1833e1f 5225 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5226#else
5227 if (unlikely(!ctx->supervisor)) {
e1833e1f 5228 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5229 return;
5230 }
5231 /* interpreted as no-op */
5232#endif
5233}
5234
5235/* icread */
5236GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5237{
5238#if defined(CONFIG_USER_ONLY)
e1833e1f 5239 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5240#else
5241 if (unlikely(!ctx->supervisor)) {
e1833e1f 5242 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5243 return;
5244 }
5245 /* interpreted as no-op */
5246#endif
5247}
5248
5249/* rfci (supervisor only) */
c7697e1f 5250GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5251{
5252#if defined(CONFIG_USER_ONLY)
e1833e1f 5253 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5254#else
5255 if (unlikely(!ctx->supervisor)) {
e1833e1f 5256 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5257 return;
5258 }
5259 /* Restore CPU state */
5260 gen_op_40x_rfci();
e1833e1f 5261 GEN_SYNC(ctx);
a42bd6cc
JM		 5262#endif
5263}
5264
5265GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5266{
5267#if defined(CONFIG_USER_ONLY)
e1833e1f 5268 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5269#else
5270 if (unlikely(!ctx->supervisor)) {
e1833e1f 5271 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5272 return;
5273 }
5274 /* Restore CPU state */
5275 gen_op_rfci();
e1833e1f 5276 GEN_SYNC(ctx);
a42bd6cc
JM		 5277#endif
5278}
5279
5280/* BookE specific */
2662a059 5281/* XXX: not implemented on 440 ? */
05332d70 5282GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5283{
5284#if defined(CONFIG_USER_ONLY)
e1833e1f 5285 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5286#else
5287 if (unlikely(!ctx->supervisor)) {
e1833e1f 5288 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5289 return;
5290 }
5291 /* Restore CPU state */
a42bd6cc 5292 gen_op_rfdi();
e1833e1f 5293 GEN_SYNC(ctx);
76a66253
JM		 5294#endif
5295}
5296
2662a059 5297/* XXX: not implemented on 440 ? */
a750fc0b 5298GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5299{
5300#if defined(CONFIG_USER_ONLY)
e1833e1f 5301 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5302#else
5303 if (unlikely(!ctx->supervisor)) {
e1833e1f 5304 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5305 return;
5306 }
5307 /* Restore CPU state */
5308 gen_op_rfmci();
e1833e1f 5309 GEN_SYNC(ctx);
a42bd6cc
JM		 5310#endif
5311}
5eb7995e 5312
d9bce9d9 5313/* TLB management - PowerPC 405 implementation */
76a66253 5314/* tlbre */
c7697e1f 5315GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5316{
5317#if defined(CONFIG_USER_ONLY)
e1833e1f 5318 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5319#else
5320 if (unlikely(!ctx->supervisor)) {
e1833e1f 5321 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5322 return;
5323 }
5324 switch (rB(ctx->opcode)) {
5325 case 0:
f78fb44e 5326 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5327 gen_op_4xx_tlbre_hi();
f78fb44e 5328 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5329 break;
5330 case 1:
f78fb44e 5331 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5332 gen_op_4xx_tlbre_lo();
f78fb44e 5333 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5334 break;
5335 default:
e1833e1f 5336 GEN_EXCP_INVAL(ctx);
76a66253 5337 break;
9a64fbe4 5338 }
76a66253
JM		 5339#endif
5340}
5341
d9bce9d9 5342/* tlbsx - tlbsx. */
c7697e1f 5343GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5344{
5345#if defined(CONFIG_USER_ONLY)
e1833e1f 5346 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5347#else
5348 if (unlikely(!ctx->supervisor)) {
e1833e1f 5349 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5350 return;
5351 }
e2be8d8d 5352 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5353 gen_op_4xx_tlbsx();
76a66253 5354 if (Rc(ctx->opcode))
daf4f96e 5355 gen_op_4xx_tlbsx_check();
f78fb44e 5356 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5357#endif
79aceca5
FB		 5358}
5359
76a66253 5360/* tlbwe */
c7697e1f 5361GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5362{
76a66253 5363#if defined(CONFIG_USER_ONLY)
e1833e1f 5364 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5365#else
5366 if (unlikely(!ctx->supervisor)) {
e1833e1f 5367 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5368 return;
5369 }
5370 switch (rB(ctx->opcode)) {
5371 case 0:
f78fb44e
AJ		 5372 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5373 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5374 gen_op_4xx_tlbwe_hi();
5375 break;
5376 case 1:
f78fb44e
AJ		 5377 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5378 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5379 gen_op_4xx_tlbwe_lo();
5380 break;
5381 default:
e1833e1f 5382 GEN_EXCP_INVAL(ctx);
76a66253 5383 break;
9a64fbe4 5384 }
76a66253
JM		 5385#endif
5386}
5387
a4bb6c3e 5388/* TLB management - PowerPC 440 implementation */
5eb7995e 5389/* tlbre */
c7697e1f 5390GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5391{
5392#if defined(CONFIG_USER_ONLY)
e1833e1f 5393 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5394#else
5395 if (unlikely(!ctx->supervisor)) {
e1833e1f 5396 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5397 return;
5398 }
5399 switch (rB(ctx->opcode)) {
5400 case 0:
5eb7995e 5401 case 1:
5eb7995e 5402 case 2:
f78fb44e 5403 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5404 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5405 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5406 break;
5407 default:
e1833e1f 5408 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5409 break;
5410 }
5411#endif
5412}
5413
5414/* tlbsx - tlbsx. */
c7697e1f 5415GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5416{
5417#if defined(CONFIG_USER_ONLY)
e1833e1f 5418 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5419#else
5420 if (unlikely(!ctx->supervisor)) {
e1833e1f 5421 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5422 return;
5423 }
e2be8d8d 5424 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5425 gen_op_440_tlbsx();
5eb7995e 5426 if (Rc(ctx->opcode))
daf4f96e 5427 gen_op_4xx_tlbsx_check();
f78fb44e 5428 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5429#endif
5430}
5431
5432/* tlbwe */
c7697e1f 5433GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5434{
5435#if defined(CONFIG_USER_ONLY)
e1833e1f 5436 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5437#else
5438 if (unlikely(!ctx->supervisor)) {
e1833e1f 5439 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5440 return;
5441 }
5442 switch (rB(ctx->opcode)) {
5443 case 0:
5eb7995e 5444 case 1:
5eb7995e 5445 case 2:
f78fb44e
AJ		 5446 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5447 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5448 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5449 break;
5450 default:
e1833e1f 5451 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5452 break;
5453 }
5454#endif
5455}
5456
76a66253 5457/* wrtee */
05332d70 5458GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5459{
5460#if defined(CONFIG_USER_ONLY)
e1833e1f 5461 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5462#else
5463 if (unlikely(!ctx->supervisor)) {
e1833e1f 5464 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5465 return;
5466 }
f78fb44e 5467 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5468 gen_op_wrte();
dee96f6c
JM		 5469 /* Stop translation to have a chance to raise an exception
5470 * if we just set msr_ee to 1
5471 */
e1833e1f 5472 GEN_STOP(ctx);
76a66253
JM		 5473#endif
5474}
5475
5476/* wrteei */
05332d70 5477GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5478{
5479#if defined(CONFIG_USER_ONLY)
e1833e1f 5480 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5481#else
5482 if (unlikely(!ctx->supervisor)) {
e1833e1f 5483 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5484 return;
5485 }
86c581dc 5486 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5487 gen_op_wrte();
dee96f6c
JM		 5488 /* Stop translation to have a chance to raise an exception
5489 * if we just set msr_ee to 1
5490 */
e1833e1f 5491 GEN_STOP(ctx);
76a66253
JM		 5492#endif
5493}
5494
08e46e54 5495/* PowerPC 440 specific instructions */
76a66253
JM		 5496/* dlmzb */
5497GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5498{
f78fb44e
AJ		 5499 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5500 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5501 gen_op_440_dlmzb();
f78fb44e 5502 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5503 gen_op_store_xer_bc();
5504 if (Rc(ctx->opcode)) {
5505 gen_op_440_dlmzb_update_Rc();
47e4661c 5506 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
76a66253
JM		 5507 }
5508}
5509
5510/* mbar replaces eieio on 440 */
5511GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5512{
5513 /* interpreted as no-op */
5514}
5515
5516/* msync replaces sync on 440 */
0db1b20e 5517GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5518{
5519 /* interpreted as no-op */
5520}
5521
5522/* icbt */
c7697e1f 5523GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5524{
5525 /* interpreted as no-op */
5526 /* XXX: specification say this is treated as a load by the MMU
5527 * but does not generate any exception
5528 */
79aceca5
FB		 5529}
5530
a9d9eb8f
JM		 5531/*** Altivec vector extension ***/
5532/* Altivec registers moves */
a9d9eb8f 5533
1d542695
AJ		 5534static always_inline void gen_load_avr(int t, int reg) {
5535 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5536 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5537}
5538
5539static always_inline void gen_store_avr(int reg, int t) {
5540 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5541 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5542}
a9d9eb8f
JM		 5543
5544#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5545#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5546static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5547 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5548};
5549#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5550static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5551 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5552};
a9d9eb8f
JM		 5553
5554#define GEN_VR_LDX(name, opc2, opc3) \
5555GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5556{ \
5557 if (unlikely(!ctx->altivec_enabled)) { \
5558 GEN_EXCP_NO_VR(ctx); \
5559 return; \
5560 } \
e2be8d8d 5561 gen_addr_reg_index(cpu_T[0], ctx); \
a9d9eb8f 5562 op_vr_ldst(vr_l##name); \
1d542695 5563 gen_store_avr(rD(ctx->opcode), 0); \
a9d9eb8f
JM		 5564}
5565
5566#define GEN_VR_STX(name, opc2, opc3) \
5567GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5568{ \
5569 if (unlikely(!ctx->altivec_enabled)) { \
5570 GEN_EXCP_NO_VR(ctx); \
5571 return; \
5572 } \
e2be8d8d 5573 gen_addr_reg_index(cpu_T[0], ctx); \
1d542695 5574 gen_load_avr(0, rS(ctx->opcode)); \
a9d9eb8f
JM		 5575 op_vr_ldst(vr_st##name); \
5576}
5577
5578OP_VR_LD_TABLE(vx);
5579GEN_VR_LDX(vx, 0x07, 0x03);
5580/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5581#define gen_op_vr_lvxl gen_op_vr_lvx
5582GEN_VR_LDX(vxl, 0x07, 0x0B);
5583
5584OP_VR_ST_TABLE(vx);
5585GEN_VR_STX(vx, 0x07, 0x07);
5586/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5587#define gen_op_vr_stvxl gen_op_vr_stvx
5588GEN_VR_STX(vxl, 0x07, 0x0F);
5589
0487d6a8 5590/*** SPE extension ***/
0487d6a8 5591/* Register moves */
3cd7d1dd 5592
f78fb44e
AJ		 5593static always_inline void gen_load_gpr64(TCGv t, int reg) {
5594#if defined(TARGET_PPC64)
5595 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5596#else
36aa55dc 5597 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5598#endif
f78fb44e 5599}
3cd7d1dd 5600
f78fb44e
AJ		 5601static always_inline void gen_store_gpr64(int reg, TCGv t) {
5602#if defined(TARGET_PPC64)
5603 tcg_gen_mov_i64(cpu_gpr[reg], t);
5604#else
5605 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
19f98ff6 5606 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
f78fb44e
AJ		 5607 tcg_gen_shri_i64(tmp, t, 32);
5608 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5609 tcg_temp_free(tmp);
3cd7d1dd 5610#endif
f78fb44e 5611}
3cd7d1dd 5612
0487d6a8
JM		 5613#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5614GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5615{ \
5616 if (Rc(ctx->opcode)) \
5617 gen_##name1(ctx); \
5618 else \
5619 gen_##name0(ctx); \
5620}
5621
5622/* Handler for undefined SPE opcodes */
b068d6a7 5623static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5624{
e1833e1f 5625 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5626}
5627
5628/* SPE load and stores */
f0aabd1a 5629static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
0487d6a8
JM		 5630{
5631 target_long simm = rB(ctx->opcode);
5632
f0aabd1a
AJ		 5633 if (rA(ctx->opcode) == 0)
5634 tcg_gen_movi_tl(EA, simm << sh);
5635 else if (likely(simm != 0))
5636 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5637 else
5638 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
0487d6a8
JM		 5639}
5640
5641#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5642#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5643static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5644 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5645};
5646#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5647static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5648 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5649};
0487d6a8
JM		 5650
5651#define GEN_SPE_LD(name, sh) \
b068d6a7 5652static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5653{ \
5654 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5655 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5656 return; \
5657 } \
f0aabd1a 5658 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
0487d6a8 5659 op_spe_ldst(spe_l##name); \
f78fb44e 5660 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5661}
5662
5663#define GEN_SPE_LDX(name) \
b068d6a7 5664static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 5665{ \
5666 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5667 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5668 return; \
5669 } \
e2be8d8d 5670 gen_addr_reg_index(cpu_T[0], ctx); \
0487d6a8 5671 op_spe_ldst(spe_l##name); \
f78fb44e 5672 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5673}
5674
5675#define GEN_SPEOP_LD(name, sh) \
5676OP_SPE_LD_TABLE(name); \
5677GEN_SPE_LD(name, sh); \
5678GEN_SPE_LDX(name)
5679
5680#define GEN_SPE_ST(name, sh) \
b068d6a7 5681static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 5682{ \
5683 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5684 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5685 return; \
5686 } \
f0aabd1a 5687 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
f78fb44e 5688 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5689 op_spe_ldst(spe_st##name); \
5690}
5691
5692#define GEN_SPE_STX(name) \
b068d6a7 5693static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 5694{ \
5695 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5696 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5697 return; \
5698 } \
e2be8d8d 5699 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 5700 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5701 op_spe_ldst(spe_st##name); \
5702}
5703
5704#define GEN_SPEOP_ST(name, sh) \
5705OP_SPE_ST_TABLE(name); \
5706GEN_SPE_ST(name, sh); \
5707GEN_SPE_STX(name)
5708
5709#define GEN_SPEOP_LDST(name, sh) \
5710GEN_SPEOP_LD(name, sh); \
5711GEN_SPEOP_ST(name, sh)
5712
5713/* SPE arithmetic and logic */
5714#define GEN_SPEOP_ARITH2(name) \
b068d6a7 5715static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5716{ \
5717 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5718 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5719 return; \
5720 } \
f78fb44e
AJ		 5721 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5722 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5723 gen_op_##name(); \
f78fb44e 5724 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5725}
5726
3d3a6a0a
AJ		 5727#define GEN_SPEOP_TCG_ARITH2(name) \
5728static always_inline void gen_##name (DisasContext *ctx) \
5729{ \
5730 if (unlikely(!ctx->spe_enabled)) { \
5731 GEN_EXCP_NO_AP(ctx); \
5732 return; \
5733 } \
5734 TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \
5735 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
5736 gen_load_gpr64(t0, rA(ctx->opcode)); \
5737 gen_load_gpr64(t1, rB(ctx->opcode)); \
5738 gen_op_##name(t0, t1); \
5739 gen_store_gpr64(rD(ctx->opcode), t0); \
5740 tcg_temp_free(t0); \
5741 tcg_temp_free(t1); \
5742}
5743
0487d6a8 5744#define GEN_SPEOP_ARITH1(name) \
b068d6a7 5745static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5746{ \
5747 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5748 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5749 return; \
5750 } \
f78fb44e 5751 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8 5752 gen_op_##name(); \
f78fb44e 5753 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5754}
5755
5756#define GEN_SPEOP_COMP(name) \
b068d6a7 5757static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5758{ \
5759 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5760 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5761 return; \
5762 } \
f78fb44e
AJ		 5763 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5764 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5765 gen_op_##name(); \
47e4661c 5766 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
0487d6a8
JM		 5767}
5768
5769/* Logical */
3d3a6a0a
AJ		 5770static always_inline void gen_op_evand (TCGv t0, TCGv t1)
5771{
5772 tcg_gen_and_i64(t0, t0, t1);
5773}
5774
5775static always_inline void gen_op_evandc (TCGv t0, TCGv t1)
5776{
5777 tcg_gen_not_i64(t1, t1);
5778 tcg_gen_and_i64(t0, t0, t1);
5779}
5780
5781static always_inline void gen_op_evxor (TCGv t0, TCGv t1)
5782{
5783 tcg_gen_xor_i64(t0, t0, t1);
5784}
5785
5786static always_inline void gen_op_evor (TCGv t0, TCGv t1)
5787{
5788 tcg_gen_or_i64(t0, t0, t1);
5789}
5790
5791static always_inline void gen_op_evnor (TCGv t0, TCGv t1)
5792{
5793 tcg_gen_or_i64(t0, t0, t1);
5794 tcg_gen_not_i64(t0, t0);
5795}
5796
5797static always_inline void gen_op_eveqv (TCGv t0, TCGv t1)
5798{
5799 tcg_gen_xor_i64(t0, t0, t1);
5800 tcg_gen_not_i64(t0, t0);
5801}
5802
5803static always_inline void gen_op_evorc (TCGv t0, TCGv t1)
5804{
5805 tcg_gen_not_i64(t1, t1);
5806 tcg_gen_or_i64(t0, t0, t1);
5807}
5808
5809static always_inline void gen_op_evnand (TCGv t0, TCGv t1)
5810{
5811 tcg_gen_and_i64(t0, t0, t1);
5812 tcg_gen_not_i64(t0, t0);
5813}
5814
5815GEN_SPEOP_TCG_ARITH2(evand);
5816GEN_SPEOP_TCG_ARITH2(evandc);
5817GEN_SPEOP_TCG_ARITH2(evxor);
5818GEN_SPEOP_TCG_ARITH2(evor);
5819GEN_SPEOP_TCG_ARITH2(evnor);
5820GEN_SPEOP_TCG_ARITH2(eveqv);
5821GEN_SPEOP_TCG_ARITH2(evorc);
5822GEN_SPEOP_TCG_ARITH2(evnand);
0487d6a8
JM		 5823GEN_SPEOP_ARITH2(evsrwu);
5824GEN_SPEOP_ARITH2(evsrws);
5825GEN_SPEOP_ARITH2(evslw);
5826GEN_SPEOP_ARITH2(evrlw);
5827GEN_SPEOP_ARITH2(evmergehi);
5828GEN_SPEOP_ARITH2(evmergelo);
5829GEN_SPEOP_ARITH2(evmergehilo);
5830GEN_SPEOP_ARITH2(evmergelohi);
5831
5832/* Arithmetic */
5833GEN_SPEOP_ARITH2(evaddw);
5834GEN_SPEOP_ARITH2(evsubfw);
5835GEN_SPEOP_ARITH1(evabs);
5836GEN_SPEOP_ARITH1(evneg);
5837GEN_SPEOP_ARITH1(evextsb);
5838GEN_SPEOP_ARITH1(evextsh);
5839GEN_SPEOP_ARITH1(evrndw);
5840GEN_SPEOP_ARITH1(evcntlzw);
5841GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 5842static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 5843{
5844 /* Note: brinc is usable even if SPE is disabled */
f78fb44e
AJ		 5845 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5846 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 5847 gen_op_brinc();
f78fb44e 5848 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
0487d6a8
JM		 5849}
5850
5851#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 5852static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5853{ \
5854 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5855 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5856 return; \
5857 } \
f78fb44e 5858 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8
JM		 5859 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5860 gen_op_##name(); \
f78fb44e 5861 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5862}
5863
5864#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 5865static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5866{ \
5867 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5868 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5869 return; \
5870 } \
f78fb44e 5871 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8
JM		 5872 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5873 gen_op_##name(); \
f78fb44e 5874 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5875}
5876
5877GEN_SPEOP_ARITH_IMM2(evaddw);
5878#define gen_evaddiw gen_evaddwi
5879GEN_SPEOP_ARITH_IMM2(evsubfw);
5880#define gen_evsubifw gen_evsubfwi
5881GEN_SPEOP_LOGIC_IMM2(evslw);
5882GEN_SPEOP_LOGIC_IMM2(evsrwu);
5883#define gen_evsrwis gen_evsrwsi
5884GEN_SPEOP_LOGIC_IMM2(evsrws);
5885#define gen_evsrwiu gen_evsrwui
5886GEN_SPEOP_LOGIC_IMM2(evrlw);
5887
b068d6a7 5888static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 5889{
5890 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5891
5892 gen_op_splatwi_T0_64(imm);
f78fb44e 5893 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5894}
5895
b068d6a7 5896static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 5897{
5898 uint32_t imm = rA(ctx->opcode) << 27;
5899
5900 gen_op_splatwi_T0_64(imm);
f78fb44e 5901 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5902}
5903
5904/* Comparison */
5905GEN_SPEOP_COMP(evcmpgtu);
5906GEN_SPEOP_COMP(evcmpgts);
5907GEN_SPEOP_COMP(evcmpltu);
5908GEN_SPEOP_COMP(evcmplts);
5909GEN_SPEOP_COMP(evcmpeq);
5910
5911GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5912GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5913GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5914GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5915GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5916GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5917GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5918GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5919GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5920GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5921GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5922GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5923GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5924GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5925GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5926GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5927GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5928GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5929GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5930GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5931GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5932GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5933GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5934GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5935GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5936
b068d6a7 5937static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 5938{
5939 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 5940 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 5941 return;
5942 }
47e4661c 5943 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
f78fb44e
AJ		 5944 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
5945 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
0487d6a8 5946 gen_op_evsel();
f78fb44e 5947 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5948}
5949
c7697e1f 5950GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5951{
5952 gen_evsel(ctx);
5953}
c7697e1f 5954GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5955{
5956 gen_evsel(ctx);
5957}
c7697e1f 5958GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5959{
5960 gen_evsel(ctx);
5961}
c7697e1f 5962GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5963{
5964 gen_evsel(ctx);
5965}
5966
5967/* Load and stores */
0487d6a8
JM		 5968GEN_SPEOP_LDST(dd, 3);
5969GEN_SPEOP_LDST(dw, 3);
5970GEN_SPEOP_LDST(dh, 3);
5971GEN_SPEOP_LDST(whe, 2);
5972GEN_SPEOP_LD(whou, 2);
5973GEN_SPEOP_LD(whos, 2);
5974GEN_SPEOP_ST(who, 2);
5975
0487d6a8 5976#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 5977static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 5978{ \
5979 gen_op_srli32_T1_64(); \
5980 gen_op_spe_stwwo_##suffix(); \
5981}
5982#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 5983static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 5984{ \
5985 gen_op_srli32_T1_64(); \
5986 gen_op_spe_stwwo_le_##suffix(); \
5987}
5988#if defined(TARGET_PPC64)
5989#define GEN_OP_SPE_STWWE(suffix) \
5990_GEN_OP_SPE_STWWE(suffix); \
5991_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 5992static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 5993{ \
5994 gen_op_srli32_T1_64(); \
5995 gen_op_spe_stwwo_64_##suffix(); \
5996} \
b068d6a7 5997static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 5998{ \
5999 gen_op_srli32_T1_64(); \
6000 gen_op_spe_stwwo_le_64_##suffix(); \
6001}
6002#else
6003#define GEN_OP_SPE_STWWE(suffix) \
6004_GEN_OP_SPE_STWWE(suffix); \
6005_GEN_OP_SPE_STWWE_LE(suffix)
6006#endif
6007#if defined(CONFIG_USER_ONLY)
6008GEN_OP_SPE_STWWE(raw);
6009#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 6010GEN_OP_SPE_STWWE(user);
7863667f
JM		 6011GEN_OP_SPE_STWWE(kernel);
6012GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 6013#endif /* defined(CONFIG_USER_ONLY) */
6014GEN_SPEOP_ST(wwe, 2);
6015GEN_SPEOP_ST(wwo, 2);
6016
6017#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 6018static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 6019{ \
6020 gen_op_##op##_##suffix(); \
6021 gen_op_splatw_T1_64(); \
6022}
6023
6024#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 6025static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 6026{ \
6027 gen_op_spe_lh_##suffix(); \
6028 gen_op_sli16_T1_64(); \
6029}
6030
6031#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 6032static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 6033{ \
6034 gen_op_spe_lh_##suffix(); \
6035 gen_op_extsh_T1_64(); \
6036}
6037
6038#if defined(CONFIG_USER_ONLY)
6039GEN_OP_SPE_LHE(raw);
6040GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6041GEN_OP_SPE_LHE(le_raw);
6042GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6043GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6044GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6045GEN_OP_SPE_LHX(raw);
6046GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6047GEN_OP_SPE_LHX(le_raw);
6048GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6049#if defined(TARGET_PPC64)
6050GEN_OP_SPE_LHE(64_raw);
6051GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6052GEN_OP_SPE_LHE(le_64_raw);
6053GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6054GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6055GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6056GEN_OP_SPE_LHX(64_raw);
6057GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6058GEN_OP_SPE_LHX(le_64_raw);
6059GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6060#endif
6061#else
0487d6a8 6062GEN_OP_SPE_LHE(user);
7863667f
JM		 6063GEN_OP_SPE_LHE(kernel);
6064GEN_OP_SPE_LHE(hypv);
0487d6a8 6065GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 6066GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6067GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 6068GEN_OP_SPE_LHE(le_user);
7863667f
JM		 6069GEN_OP_SPE_LHE(le_kernel);
6070GEN_OP_SPE_LHE(le_hypv);
0487d6a8 6071GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 6072GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6073GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 6074GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 6075GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6076GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 6077GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 6078GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6079GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 6080GEN_OP_SPE_LHX(user);
7863667f
JM		 6081GEN_OP_SPE_LHX(kernel);
6082GEN_OP_SPE_LHX(hypv);
0487d6a8 6083GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 6084GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6085GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 6086GEN_OP_SPE_LHX(le_user);
7863667f
JM		 6087GEN_OP_SPE_LHX(le_kernel);
6088GEN_OP_SPE_LHX(le_hypv);
0487d6a8 6089GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 6090GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6091GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 6092#if defined(TARGET_PPC64)
0487d6a8 6093GEN_OP_SPE_LHE(64_user);
7863667f
JM		 6094GEN_OP_SPE_LHE(64_kernel);
6095GEN_OP_SPE_LHE(64_hypv);
0487d6a8 6096GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 6097GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6098GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 6099GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 6100GEN_OP_SPE_LHE(le_64_kernel);
6101GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 6102GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 6103GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6104GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 6105GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 6106GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6107GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 6108GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 6109GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6110GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 6111GEN_OP_SPE_LHX(64_user);
7863667f
JM		 6112GEN_OP_SPE_LHX(64_kernel);
6113GEN_OP_SPE_LHX(64_hypv);
0487d6a8 6114GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 6115GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6116GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 6117GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 6118GEN_OP_SPE_LHX(le_64_kernel);
6119GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 6120GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 6121GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6122GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 6123#endif
6124#endif
6125GEN_SPEOP_LD(hhesplat, 1);
6126GEN_SPEOP_LD(hhousplat, 1);
6127GEN_SPEOP_LD(hhossplat, 1);
6128GEN_SPEOP_LD(wwsplat, 2);
6129GEN_SPEOP_LD(whsplat, 2);
6130
6131GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6132GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6133GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6134GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6135GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6136GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6137GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6138GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6139GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6140GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6141GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6142GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6143GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6144GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6145GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6146GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6147GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6148GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6149
6150/* Multiply and add - TODO */
6151#if 0
6152GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6153GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6154GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6155GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6156GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6157GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6158GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6159GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6160GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6161GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6162GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6163GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6164
6165GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6166GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6167GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6168GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6169GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6170GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6171GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6172GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6173GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6174GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6175GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6176GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6177GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6178GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6179
6180GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6181GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6182GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6183GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6184GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6185GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6186
6187GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6188GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6189GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6190GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6191GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6192GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6193GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6194GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6195GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6196GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6197GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6198GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6199
6200GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6201GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6202GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6203GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6204GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6205
6206GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6207GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6208GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6209GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6210GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6211GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6212GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6213GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6214GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6215GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6216GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6217GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6218
6219GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6220GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6221GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6222GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6223GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6224#endif
6225
6226/*** SPE floating-point extension ***/
6227#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 6228static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6229{ \
f78fb44e 6230 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8 6231 gen_op_##name(); \
f78fb44e 6232 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6233}
6234
6235/* Single precision floating-point vectors operations */
6236/* Arithmetic */
6237GEN_SPEOP_ARITH2(evfsadd);
6238GEN_SPEOP_ARITH2(evfssub);
6239GEN_SPEOP_ARITH2(evfsmul);
6240GEN_SPEOP_ARITH2(evfsdiv);
6241GEN_SPEOP_ARITH1(evfsabs);
6242GEN_SPEOP_ARITH1(evfsnabs);
6243GEN_SPEOP_ARITH1(evfsneg);
6244/* Conversion */
6245GEN_SPEFPUOP_CONV(evfscfui);
6246GEN_SPEFPUOP_CONV(evfscfsi);
6247GEN_SPEFPUOP_CONV(evfscfuf);
6248GEN_SPEFPUOP_CONV(evfscfsf);
6249GEN_SPEFPUOP_CONV(evfsctui);
6250GEN_SPEFPUOP_CONV(evfsctsi);
6251GEN_SPEFPUOP_CONV(evfsctuf);
6252GEN_SPEFPUOP_CONV(evfsctsf);
6253GEN_SPEFPUOP_CONV(evfsctuiz);
6254GEN_SPEFPUOP_CONV(evfsctsiz);
6255/* Comparison */
6256GEN_SPEOP_COMP(evfscmpgt);
6257GEN_SPEOP_COMP(evfscmplt);
6258GEN_SPEOP_COMP(evfscmpeq);
6259GEN_SPEOP_COMP(evfststgt);
6260GEN_SPEOP_COMP(evfststlt);
6261GEN_SPEOP_COMP(evfststeq);
6262
6263/* Opcodes definitions */
6264GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6265GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6266GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6267GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6268GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6269GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6270GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6271GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6272GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6273GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6274GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6275GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6276GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6277GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6278
6279/* Single precision floating-point operations */
6280/* Arithmetic */
6281GEN_SPEOP_ARITH2(efsadd);
6282GEN_SPEOP_ARITH2(efssub);
6283GEN_SPEOP_ARITH2(efsmul);
6284GEN_SPEOP_ARITH2(efsdiv);
6285GEN_SPEOP_ARITH1(efsabs);
6286GEN_SPEOP_ARITH1(efsnabs);
6287GEN_SPEOP_ARITH1(efsneg);
6288/* Conversion */
6289GEN_SPEFPUOP_CONV(efscfui);
6290GEN_SPEFPUOP_CONV(efscfsi);
6291GEN_SPEFPUOP_CONV(efscfuf);
6292GEN_SPEFPUOP_CONV(efscfsf);
6293GEN_SPEFPUOP_CONV(efsctui);
6294GEN_SPEFPUOP_CONV(efsctsi);
6295GEN_SPEFPUOP_CONV(efsctuf);
6296GEN_SPEFPUOP_CONV(efsctsf);
6297GEN_SPEFPUOP_CONV(efsctuiz);
6298GEN_SPEFPUOP_CONV(efsctsiz);
6299GEN_SPEFPUOP_CONV(efscfd);
6300/* Comparison */
6301GEN_SPEOP_COMP(efscmpgt);
6302GEN_SPEOP_COMP(efscmplt);
6303GEN_SPEOP_COMP(efscmpeq);
6304GEN_SPEOP_COMP(efststgt);
6305GEN_SPEOP_COMP(efststlt);
6306GEN_SPEOP_COMP(efststeq);
6307
6308/* Opcodes definitions */
05332d70 6309GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 6310GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6311GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6312GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6313GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6314GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6315GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6316GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6317GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6318GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 6319GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6320GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 6321GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6322GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6323
6324/* Double precision floating-point operations */
6325/* Arithmetic */
6326GEN_SPEOP_ARITH2(efdadd);
6327GEN_SPEOP_ARITH2(efdsub);
6328GEN_SPEOP_ARITH2(efdmul);
6329GEN_SPEOP_ARITH2(efddiv);
6330GEN_SPEOP_ARITH1(efdabs);
6331GEN_SPEOP_ARITH1(efdnabs);
6332GEN_SPEOP_ARITH1(efdneg);
6333/* Conversion */
6334
6335GEN_SPEFPUOP_CONV(efdcfui);
6336GEN_SPEFPUOP_CONV(efdcfsi);
6337GEN_SPEFPUOP_CONV(efdcfuf);
6338GEN_SPEFPUOP_CONV(efdcfsf);
6339GEN_SPEFPUOP_CONV(efdctui);
6340GEN_SPEFPUOP_CONV(efdctsi);
6341GEN_SPEFPUOP_CONV(efdctuf);
6342GEN_SPEFPUOP_CONV(efdctsf);
6343GEN_SPEFPUOP_CONV(efdctuiz);
6344GEN_SPEFPUOP_CONV(efdctsiz);
6345GEN_SPEFPUOP_CONV(efdcfs);
6346GEN_SPEFPUOP_CONV(efdcfuid);
6347GEN_SPEFPUOP_CONV(efdcfsid);
6348GEN_SPEFPUOP_CONV(efdctuidz);
6349GEN_SPEFPUOP_CONV(efdctsidz);
6350/* Comparison */
6351GEN_SPEOP_COMP(efdcmpgt);
6352GEN_SPEOP_COMP(efdcmplt);
6353GEN_SPEOP_COMP(efdcmpeq);
6354GEN_SPEOP_COMP(efdtstgt);
6355GEN_SPEOP_COMP(efdtstlt);
6356GEN_SPEOP_COMP(efdtsteq);
6357
6358/* Opcodes definitions */
6359GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6360GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6361GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6362GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6363GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6364GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6365GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6366GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6367GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6368GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6369GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6370GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6371GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6372GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6373GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6374GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6375
79aceca5
FB		 6376/* End opcode list */
6377GEN_OPCODE_MARK(end);
6378
3fc6c082 6379#include "translate_init.c"
0411a972 6380#include "helper_regs.h"
79aceca5 6381
9a64fbe4 6382/*****************************************************************************/
3fc6c082 6383/* Misc PowerPC helpers */
36081602
JM		 6384void cpu_dump_state (CPUState *env, FILE *f,
6385 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6386 int flags)
79aceca5 6387{
3fc6c082
FB		 6388#define RGPL 4
6389#define RFPL 4
3fc6c082 6390
79aceca5
FB		 6391 int i;
6392
077fc206
JM		 6393 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6394 env->nip, env->lr, env->ctr, hreg_load_xer(env));
6b542af7
JM		 6395 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6396 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 6397#if !defined(NO_TIMER_DUMP)
077fc206 6398 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6399#if !defined(CONFIG_USER_ONLY)
6400 "DECR %08x"
6401#endif
6402 "\n",
077fc206 6403 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6404#if !defined(CONFIG_USER_ONLY)
6405 , cpu_ppc_load_decr(env)
6406#endif
6407 );
077fc206 6408#endif
76a66253 6409 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6410 if ((i & (RGPL - 1)) == 0)
6411 cpu_fprintf(f, "GPR%02d", i);
6b542af7 6412 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 6413 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6414 cpu_fprintf(f, "\n");
76a66253 6415 }
3fc6c082 6416 cpu_fprintf(f, "CR ");
76a66253 6417 for (i = 0; i < 8; i++)
7fe48483
FB		 6418 cpu_fprintf(f, "%01x", env->crf[i]);
6419 cpu_fprintf(f, " [");
76a66253
JM		 6420 for (i = 0; i < 8; i++) {
6421 char a = '-';
6422 if (env->crf[i] & 0x08)
6423 a = 'L';
6424 else if (env->crf[i] & 0x04)
6425 a = 'G';
6426 else if (env->crf[i] & 0x02)
6427 a = 'E';
7fe48483 6428 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6429 }
6b542af7 6430 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 6431 for (i = 0; i < 32; i++) {
6432 if ((i & (RFPL - 1)) == 0)
6433 cpu_fprintf(f, "FPR%02d", i);
26a76461 6434 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6435 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6436 cpu_fprintf(f, "\n");
79aceca5 6437 }
f2e63a42 6438#if !defined(CONFIG_USER_ONLY)
6b542af7 6439 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 6440 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6441#endif
79aceca5 6442
3fc6c082
FB		 6443#undef RGPL
6444#undef RFPL
79aceca5
FB		 6445}
6446
76a66253
JM		 6447void cpu_dump_statistics (CPUState *env, FILE*f,
6448 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6449 int flags)
6450{
6451#if defined(DO_PPC_STATISTICS)
6452 opc_handler_t **t1, **t2, **t3, *handler;
6453 int op1, op2, op3;
6454
6455 t1 = env->opcodes;
6456 for (op1 = 0; op1 < 64; op1++) {
6457 handler = t1[op1];
6458 if (is_indirect_opcode(handler)) {
6459 t2 = ind_table(handler);
6460 for (op2 = 0; op2 < 32; op2++) {
6461 handler = t2[op2];
6462 if (is_indirect_opcode(handler)) {
6463 t3 = ind_table(handler);
6464 for (op3 = 0; op3 < 32; op3++) {
6465 handler = t3[op3];
6466 if (handler->count == 0)
6467 continue;
6468 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6469 "%016llx %lld\n",
6470 op1, op2, op3, op1, (op3 << 5) | op2,
6471 handler->oname,
6472 handler->count, handler->count);
6473 }
6474 } else {
6475 if (handler->count == 0)
6476 continue;
6477 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6478 "%016llx %lld\n",
6479 op1, op2, op1, op2, handler->oname,
6480 handler->count, handler->count);
6481 }
6482 }
6483 } else {
6484 if (handler->count == 0)
6485 continue;
6486 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6487 op1, op1, handler->oname,
6488 handler->count, handler->count);
6489 }
6490 }
6491#endif
6492}
6493
9a64fbe4 6494/*****************************************************************************/
2cfc5f17
TS		 6495static always_inline void gen_intermediate_code_internal (CPUState *env,
6496 TranslationBlock *tb,
6497 int search_pc)
79aceca5 6498{
9fddaa0c 6499 DisasContext ctx, *ctxp = &ctx;
79aceca5 6500 opc_handler_t **table, *handler;
0fa85d43 6501 target_ulong pc_start;
79aceca5 6502 uint16_t *gen_opc_end;
056401ea 6503 int supervisor, little_endian;
79aceca5 6504 int j, lj = -1;
2e70f6ef
PB		 6505 int num_insns;
6506 int max_insns;
79aceca5
FB		 6507
6508 pc_start = tb->pc;
79aceca5 6509 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 6510#if defined(OPTIMIZE_FPRF_UPDATE)
6511 gen_fprf_ptr = gen_fprf_buf;
6512#endif
046d6672 6513 ctx.nip = pc_start;
79aceca5 6514 ctx.tb = tb;
e1833e1f 6515 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6516 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6517 supervisor = env->mmu_idx;
6518#if !defined(CONFIG_USER_ONLY)
2857068e 6519 ctx.supervisor = supervisor;
d9bce9d9 6520#endif
056401ea 6521 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6522#if defined(TARGET_PPC64)
6523 ctx.sf_mode = msr_sf;
056401ea 6524 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6525#else
056401ea 6526 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6527#endif
d63001d1 6528 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6529 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6530 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6531 ctx.spe_enabled = msr_spe;
6532 else
6533 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6534 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6535 ctx.altivec_enabled = msr_vr;
6536 else
6537 ctx.altivec_enabled = 0;
d26bfc9a 6538 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 6539 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 6540 else
8cbcb4fa 6541 ctx.singlestep_enabled = 0;
d26bfc9a 6542 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 6543 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6544 if (unlikely(env->singlestep_enabled))
6545 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 6546#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6547 /* Single step trace mode */
6548 msr_se = 1;
6549#endif
2e70f6ef
PB		 6550 num_insns = 0;
6551 max_insns = tb->cflags & CF_COUNT_MASK;
6552 if (max_insns == 0)
6553 max_insns = CF_COUNT_MASK;
6554
6555 gen_icount_start();
9a64fbe4 6556 /* Set env in case of segfault during code fetch */
e1833e1f 6557 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6558 if (unlikely(env->nb_breakpoints > 0)) {
6559 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6560 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6561 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6562 gen_op_debug();
6563 break;
6564 }
6565 }
6566 }
76a66253 6567 if (unlikely(search_pc)) {
79aceca5
FB		 6568 j = gen_opc_ptr - gen_opc_buf;
6569 if (lj < j) {
6570 lj++;
6571 while (lj < j)
6572 gen_opc_instr_start[lj++] = 0;
046d6672 6573 gen_opc_pc[lj] = ctx.nip;
79aceca5 6574 gen_opc_instr_start[lj] = 1;
2e70f6ef 6575 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 6576 }
6577 }
9fddaa0c
FB		 6578#if defined PPC_DEBUG_DISAS
6579 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6580 fprintf(logfile, "----------------\n");
1b9eb036 6581 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6582 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6583 }
6584#endif
2e70f6ef
PB		 6585 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6586 gen_io_start();
056401ea
JM		 6587 if (unlikely(little_endian)) {
6588 ctx.opcode = bswap32(ldl_code(ctx.nip));
6589 } else {
6590 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6591 }
9fddaa0c
FB		 6592#if defined PPC_DEBUG_DISAS
6593 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6594 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6595 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6596 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6597 }
6598#endif
046d6672 6599 ctx.nip += 4;
3fc6c082 6600 table = env->opcodes;
2e70f6ef 6601 num_insns++;
79aceca5
FB		 6602 handler = table[opc1(ctx.opcode)];
6603 if (is_indirect_opcode(handler)) {
6604 table = ind_table(handler);
6605 handler = table[opc2(ctx.opcode)];
6606 if (is_indirect_opcode(handler)) {
6607 table = ind_table(handler);
6608 handler = table[opc3(ctx.opcode)];
6609 }
6610 }
6611 /* Is opcode *REALLY* valid ? */
76a66253 6612 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6613 if (loglevel != 0) {
76a66253 6614 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 6615 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 6616 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6617 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6618 } else {
6619 printf("invalid/unsupported opcode: "
6b542af7 6620 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 6621 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6622 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6623 }
76a66253
JM		 6624 } else {
6625 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6626 if (loglevel != 0) {
79aceca5 6627 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 6628 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 6629 ctx.opcode & handler->inval, opc1(ctx.opcode),
6630 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6631 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6632 } else {
6633 printf("invalid bits: %08x for opcode: "
6b542af7 6634 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 6635 ctx.opcode & handler->inval, opc1(ctx.opcode),
6636 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6637 ctx.opcode, ctx.nip - 4);
76a66253 6638 }
e1833e1f 6639 GEN_EXCP_INVAL(ctxp);
4b3686fa 6640 break;
79aceca5 6641 }
79aceca5 6642 }
4b3686fa 6643 (*(handler->handler))(&ctx);
76a66253
JM		 6644#if defined(DO_PPC_STATISTICS)
6645 handler->count++;
6646#endif
9a64fbe4 6647 /* Check trace mode exceptions */
8cbcb4fa
AJ		 6648 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6649 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6650 ctx.exception != POWERPC_SYSCALL &&
6651 ctx.exception != POWERPC_EXCP_TRAP &&
6652 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 6653 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 6654 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 6655 (env->singlestep_enabled) ||
6656 num_insns >= max_insns)) {
d26bfc9a
JM		 6657 /* if we reach a page boundary or are single stepping, stop
6658 * generation
6659 */
8dd4983c 6660 break;
76a66253 6661 }
3fc6c082
FB		 6662#if defined (DO_SINGLE_STEP)
6663 break;
6664#endif
6665 }
2e70f6ef
PB		 6666 if (tb->cflags & CF_LAST_IO)
6667 gen_io_end();
e1833e1f 6668 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6669 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6670 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 6671 if (unlikely(env->singlestep_enabled)) {
6672 gen_update_nip(&ctx, ctx.nip);
6673 gen_op_debug();
6674 }
76a66253 6675 /* Generate the return instruction */
57fec1fe 6676 tcg_gen_exit_tb(0);
9a64fbe4 6677 }
2e70f6ef 6678 gen_icount_end(tb, num_insns);
79aceca5 6679 *gen_opc_ptr = INDEX_op_end;
76a66253 6680 if (unlikely(search_pc)) {
9a64fbe4
FB		 6681 j = gen_opc_ptr - gen_opc_buf;
6682 lj++;
6683 while (lj <= j)
6684 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6685 } else {
046d6672 6686 tb->size = ctx.nip - pc_start;
2e70f6ef 6687 tb->icount = num_insns;
9a64fbe4 6688 }
d9bce9d9 6689#if defined(DEBUG_DISAS)
9fddaa0c 6690 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6691 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6692 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6693 }
6694 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6695 int flags;
237c0af0 6696 flags = env->bfd_mach;
056401ea 6697 flags |= little_endian << 16;
0fa85d43 6698 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6699 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6700 fprintf(logfile, "\n");
9fddaa0c 6701 }
79aceca5 6702#endif
79aceca5
FB		 6703}
6704
2cfc5f17 6705void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 6706{
2cfc5f17 6707 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 6708}
6709
2cfc5f17 6710void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 6711{
2cfc5f17 6712 gen_intermediate_code_internal(env, tb, 1);
79aceca5 6713}
d2856f1a
AJ		 6714
6715void gen_pc_load(CPUState *env, TranslationBlock *tb,
6716 unsigned long searched_pc, int pc_pos, void *puc)
6717{
6718 int type, c;
6719 /* for PPC, we need to look at the micro operation to get the
6720 * access type */
6721 env->nip = gen_opc_pc[pc_pos];
6722 c = gen_opc_buf[pc_pos];
6723 switch(c) {
6724#if defined(CONFIG_USER_ONLY)
6725#define CASE3(op)\
6726 case INDEX_op_ ## op ## _raw
6727#else
6728#define CASE3(op)\
6729 case INDEX_op_ ## op ## _user:\
6730 case INDEX_op_ ## op ## _kernel:\
6731 case INDEX_op_ ## op ## _hypv
6732#endif
6733
6734 CASE3(stfd):
6735 CASE3(stfs):
6736 CASE3(lfd):
6737 CASE3(lfs):
6738 type = ACCESS_FLOAT;
6739 break;
6740 CASE3(lwarx):
6741 type = ACCESS_RES;
6742 break;
6743 CASE3(stwcx):
6744 type = ACCESS_RES;
6745 break;
6746 CASE3(eciwx):
6747 CASE3(ecowx):
6748 type = ACCESS_EXT;
6749 break;
6750 default:
6751 type = ACCESS_INT;
6752 break;
6753 }
6754 env->access_type = type;
6755}
Qemu copy for testing