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target-ppc: convert load/store string instructions to TCG
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
79aceca5 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
7c58044c 44//#define OPTIMIZE_FPRF_UPDATE
79aceca5 45
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 52#if !defined(TARGET_PPC64)
1d542695 53 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 54#endif
a5e26afa 55 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
f78fb44e
AJ		 58static TCGv cpu_gpr[32];
59#if !defined(TARGET_PPC64)
60static TCGv cpu_gprh[32];
61#endif
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64static TCGv_i32 cpu_crf[8];
bd568f18 65static TCGv cpu_nip;
cfdcd37a
AJ		 66static TCGv cpu_ctr;
67static TCGv cpu_lr;
3d7b417e 68static TCGv cpu_xer;
a7812ae4 69static TCGv_i32 cpu_fpscr;
a7859e89 70static TCGv_i32 cpu_access_type;
f78fb44e
AJ		 71
72/* dyngen register indexes */
73static TCGv cpu_T[3];
2e70f6ef
PB		 74
75#include "gen-icount.h"
76
77void ppc_translate_init(void)
78{
f78fb44e
AJ		 79 int i;
80 char* p;
b2437bf2 81 static int done_init = 0;
f78fb44e 82
2e70f6ef
PB		 83 if (done_init)
84 return;
f78fb44e 85
a7812ae4 86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1c73fe5b 87#if TARGET_LONG_BITS > HOST_LONG_BITS
a7812ae4
PB		 88 cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");
89 cpu_T[1] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t1), "T1");
90 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
1c73fe5b 91#else
a7812ae4
PB		 92 cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");
93 cpu_T[1] = tcg_global_reg_new(TCG_AREG2, "T1");
4870167d
AJ		 94#ifdef HOST_I386
95 /* XXX: This is a temporary workaround for i386.
96 * On i386 qemu_st32 runs out of registers.
97 * The proper fix is to remove cpu_T.
98 */
a7812ae4 99 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
4870167d 100#else
a7812ae4 101 cpu_T[2] = tcg_global_reg_new(TCG_AREG3, "T2");
1c73fe5b 102#endif
a7812ae4
PB		 103#endif
104
f78fb44e 105 p = cpu_reg_names;
47e4661c
AJ		 106
107 for (i = 0; i < 8; i++) {
108 sprintf(p, "crf%d", i);
a7812ae4
PB		 109 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 111 p += 5;
112 }
113
f78fb44e
AJ		 114 for (i = 0; i < 32; i++) {
115 sprintf(p, "r%d", i);
a7812ae4 116 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 117 offsetof(CPUState, gpr[i]), p);
118 p += (i < 10) ? 3 : 4;
119#if !defined(TARGET_PPC64)
120 sprintf(p, "r%dH", i);
a7812ae4
PB		 121 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 123 p += (i < 10) ? 4 : 5;
124#endif
1d542695 125
a5e26afa 126 sprintf(p, "fp%d", i);
a7812ae4
PB		 127 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
128 offsetof(CPUState, fpr[i]), p);
ec1ac72d 129 p += (i < 10) ? 4 : 5;
a5e26afa 130
1d542695 131 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 132#ifdef WORDS_BIGENDIAN
133 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
134 offsetof(CPUState, avr[i].u64[0]), p);
135#else
a7812ae4 136 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 137 offsetof(CPUState, avr[i].u64[1]), p);
138#endif
1d542695 139 p += (i < 10) ? 6 : 7;
ec1ac72d 140
1d542695 141 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 142#ifdef WORDS_BIGENDIAN
143 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUState, avr[i].u64[1]), p);
145#else
a7812ae4 146 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 147 offsetof(CPUState, avr[i].u64[0]), p);
148#endif
1d542695 149 p += (i < 10) ? 6 : 7;
f78fb44e 150 }
f10dc08e 151
a7812ae4 152 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 153 offsetof(CPUState, nip), "nip");
154
a7812ae4 155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 156 offsetof(CPUState, ctr), "ctr");
157
a7812ae4 158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 159 offsetof(CPUState, lr), "lr");
160
a7812ae4 161 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 162 offsetof(CPUState, xer), "xer");
163
a7812ae4
PB		 164 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
165 offsetof(CPUState, fpscr), "fpscr");
e1571908 166
a7859e89
AJ		 167 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
168 offsetof(CPUState, access_type), "access_type");
169
f10dc08e 170 /* register helpers */
a7812ae4 171#define GEN_HELPER 2
f10dc08e
AJ		 172#include "helper.h"
173
2e70f6ef
PB		 174 done_init = 1;
175}
176
7c58044c
JM		 177#if defined(OPTIMIZE_FPRF_UPDATE)
178static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
179static uint16_t **gen_fprf_ptr;
180#endif
79aceca5 181
79aceca5
FB		 182/* internal defines */
183typedef struct DisasContext {
184 struct TranslationBlock *tb;
0fa85d43 185 target_ulong nip;
79aceca5 186 uint32_t opcode;
9a64fbe4 187 uint32_t exception;
3cc62370
FB		 188 /* Routine used to access memory */
189 int mem_idx;
190 /* Translation flags */
9a64fbe4 191#if !defined(CONFIG_USER_ONLY)
79aceca5 192 int supervisor;
d9bce9d9
JM		 193#endif
194#if defined(TARGET_PPC64)
195 int sf_mode;
9a64fbe4 196#endif
3cc62370 197 int fpu_enabled;
a9d9eb8f 198 int altivec_enabled;
0487d6a8 199 int spe_enabled;
3fc6c082 200 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 201 int singlestep_enabled;
79aceca5
FB		 202} DisasContext;
203
3fc6c082 204struct opc_handler_t {
79aceca5
FB		 205 /* invalid bits */
206 uint32_t inval;
9a64fbe4 207 /* instruction type */
0487d6a8 208 uint64_t type;
79aceca5
FB		 209 /* handler */
210 void (*handler)(DisasContext *ctx);
a750fc0b 211#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 212 const char *oname;
a750fc0b
JM		 213#endif
214#if defined(DO_PPC_STATISTICS)
76a66253
JM		 215 uint64_t count;
216#endif
3fc6c082 217};
79aceca5 218
7c58044c
JM		 219static always_inline void gen_reset_fpstatus (void)
220{
221#ifdef CONFIG_SOFTFLOAT
222 gen_op_reset_fpstatus();
223#endif
224}
225
0f2f39c2 226static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 227{
0f2f39c2 228 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 229
7c58044c
JM		 230 if (set_fprf != 0) {
231 /* This case might be optimized later */
232#if defined(OPTIMIZE_FPRF_UPDATE)
233 *gen_fprf_ptr++ = gen_opc_ptr;
234#endif
0f2f39c2 235 tcg_gen_movi_i32(t0, 1);
af12906f 236 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 237 if (unlikely(set_rc)) {
0f2f39c2 238 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 239 }
af12906f 240 gen_helper_float_check_status();
7c58044c
JM		 241 } else if (unlikely(set_rc)) {
242 /* We always need to compute fpcc */
0f2f39c2 243 tcg_gen_movi_i32(t0, 0);
af12906f 244 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 245 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 246 if (set_fprf)
af12906f 247 gen_helper_float_check_status();
7c58044c 248 }
af12906f 249
0f2f39c2 250 tcg_temp_free_i32(t0);
7c58044c
JM		 251}
252
253static always_inline void gen_optimize_fprf (void)
254{
255#if defined(OPTIMIZE_FPRF_UPDATE)
256 uint16_t **ptr;
257
258 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
259 *ptr = INDEX_op_nop1;
260 gen_fprf_ptr = gen_fprf_buf;
261#endif
262}
263
a7859e89
AJ		 264static always_inline void gen_set_access_type(int access_type)
265{
266 tcg_gen_movi_i32(cpu_access_type, access_type);
267}
268
b068d6a7 269static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 270{
271#if defined(TARGET_PPC64)
272 if (ctx->sf_mode)
bd568f18 273 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 274 else
275#endif
bd568f18 276 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 277}
278
e1833e1f 279#define GEN_EXCP(ctx, excp, error) \
79aceca5 280do { \
64adab3f
AJ		 281 TCGv_i32 t0 = tcg_const_i32(excp); \
282 TCGv_i32 t1 = tcg_const_i32(error); \
e1833e1f 283 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 284 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c 285 } \
64adab3f
AJ		 286 gen_helper_raise_exception_err(t0, t1); \
287 tcg_temp_free_i32(t0); \
288 tcg_temp_free_i32(t1); \
9fddaa0c 289 ctx->exception = (excp); \
79aceca5
FB		 290} while (0)
291
e1833e1f
JM		 292#define GEN_EXCP_INVAL(ctx) \
293GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
294 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 295
e1833e1f
JM		 296#define GEN_EXCP_PRIVOPC(ctx) \
297GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
298 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 299
e1833e1f
JM		 300#define GEN_EXCP_PRIVREG(ctx) \
301GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
302 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
303
304#define GEN_EXCP_NO_FP(ctx) \
305GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
306
307#define GEN_EXCP_NO_AP(ctx) \
308GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 309
a9d9eb8f
JM		 310#define GEN_EXCP_NO_VR(ctx) \
311GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
312
f24e5695 313/* Stop translation */
b068d6a7 314static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 315{
d9bce9d9 316 gen_update_nip(ctx, ctx->nip);
e1833e1f 317 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 318}
319
f24e5695 320/* No need to update nip here, as execution flow will change */
b068d6a7 321static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 322{
e1833e1f 323 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 324}
325
79aceca5
FB		 326#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
327static void gen_##name (DisasContext *ctx); \
328GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
329static void gen_##name (DisasContext *ctx)
330
c7697e1f
JM		 331#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
332static void gen_##name (DisasContext *ctx); \
333GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
334static void gen_##name (DisasContext *ctx)
335
79aceca5
FB		 336typedef struct opcode_t {
337 unsigned char opc1, opc2, opc3;
1235fc06 338#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 339 unsigned char pad[5];
340#else
341 unsigned char pad[1];
342#endif
79aceca5 343 opc_handler_t handler;
b55266b5 344 const char *oname;
79aceca5
FB		 345} opcode_t;
346
a750fc0b 347/*****************************************************************************/
79aceca5
FB		 348/*** Instruction decoding ***/
349#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 350static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 351{ \
352 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
353}
354
355#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 356static always_inline int32_t name (uint32_t opcode) \
79aceca5 357{ \
18fba28c 358 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 359}
360
361/* Opcode part 1 */
362EXTRACT_HELPER(opc1, 26, 6);
363/* Opcode part 2 */
364EXTRACT_HELPER(opc2, 1, 5);
365/* Opcode part 3 */
366EXTRACT_HELPER(opc3, 6, 5);
367/* Update Cr0 flags */
368EXTRACT_HELPER(Rc, 0, 1);
369/* Destination */
370EXTRACT_HELPER(rD, 21, 5);
371/* Source */
372EXTRACT_HELPER(rS, 21, 5);
373/* First operand */
374EXTRACT_HELPER(rA, 16, 5);
375/* Second operand */
376EXTRACT_HELPER(rB, 11, 5);
377/* Third operand */
378EXTRACT_HELPER(rC, 6, 5);
379/*** Get CRn ***/
380EXTRACT_HELPER(crfD, 23, 3);
381EXTRACT_HELPER(crfS, 18, 3);
382EXTRACT_HELPER(crbD, 21, 5);
383EXTRACT_HELPER(crbA, 16, 5);
384EXTRACT_HELPER(crbB, 11, 5);
385/* SPR / TBL */
3fc6c082 386EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 387static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 388{
389 uint32_t sprn = _SPR(opcode);
390
391 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
392}
79aceca5
FB		 393/*** Get constants ***/
394EXTRACT_HELPER(IMM, 12, 8);
395/* 16 bits signed immediate value */
396EXTRACT_SHELPER(SIMM, 0, 16);
397/* 16 bits unsigned immediate value */
398EXTRACT_HELPER(UIMM, 0, 16);
399/* Bit count */
400EXTRACT_HELPER(NB, 11, 5);
401/* Shift count */
402EXTRACT_HELPER(SH, 11, 5);
403/* Mask start */
404EXTRACT_HELPER(MB, 6, 5);
405/* Mask end */
406EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 407/* Trap operand */
408EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 409
410EXTRACT_HELPER(CRM, 12, 8);
411EXTRACT_HELPER(FM, 17, 8);
412EXTRACT_HELPER(SR, 16, 4);
e4bb997e 413EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 414
79aceca5
FB		 415/*** Jump target decoding ***/
416/* Displacement */
417EXTRACT_SHELPER(d, 0, 16);
418/* Immediate address */
b068d6a7 419static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 420{
421 return (opcode >> 0) & 0x03FFFFFC;
422}
423
b068d6a7 424static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 425{
426 return (opcode >> 0) & 0xFFFC;
427}
428
429EXTRACT_HELPER(BO, 21, 5);
430EXTRACT_HELPER(BI, 16, 5);
431/* Absolute/relative address */
432EXTRACT_HELPER(AA, 1, 1);
433/* Link */
434EXTRACT_HELPER(LK, 0, 1);
435
436/* Create a mask between <start> and <end> bits */
b068d6a7 437static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 438{
76a66253 439 target_ulong ret;
79aceca5 440
76a66253
JM		 441#if defined(TARGET_PPC64)
442 if (likely(start == 0)) {
6f2d8978 443 ret = UINT64_MAX << (63 - end);
76a66253 444 } else if (likely(end == 63)) {
6f2d8978 445 ret = UINT64_MAX >> start;
76a66253
JM		 446 }
447#else
448 if (likely(start == 0)) {
6f2d8978 449 ret = UINT32_MAX << (31 - end);
76a66253 450 } else if (likely(end == 31)) {
6f2d8978 451 ret = UINT32_MAX >> start;
76a66253
JM		 452 }
453#endif
454 else {
455 ret = (((target_ulong)(-1ULL)) >> (start)) ^
456 (((target_ulong)(-1ULL) >> (end)) >> 1);
457 if (unlikely(start > end))
458 return ~ret;
459 }
79aceca5
FB		 460
461 return ret;
462}
463
a750fc0b
JM		 464/*****************************************************************************/
465/* PowerPC Instructions types definitions */
466enum {
1b413d55 467 PPC_NONE = 0x0000000000000000ULL,
12de9a39 468 /* PowerPC base instructions set */
1b413d55
JM		 469 PPC_INSNS_BASE = 0x0000000000000001ULL,
470 /* integer operations instructions */
a750fc0b 471#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 472 /* flow control instructions */
a750fc0b 473#define PPC_FLOW PPC_INSNS_BASE
1b413d55 474 /* virtual memory instructions */
a750fc0b 475#define PPC_MEM PPC_INSNS_BASE
1b413d55 476 /* ld/st with reservation instructions */
a750fc0b 477#define PPC_RES PPC_INSNS_BASE
1b413d55 478 /* spr/msr access instructions */
a750fc0b 479#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 480 /* Deprecated instruction sets */
481 /* Original POWER instruction set */
f610349f 482 PPC_POWER = 0x0000000000000002ULL,
1b413d55 483 /* POWER2 instruction set extension */
f610349f 484 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 485 /* Power RTC support */
f610349f 486 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 487 /* Power-to-PowerPC bridge (601) */
f610349f 488 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 489 /* 64 bits PowerPC instruction set */
f610349f 490 PPC_64B = 0x0000000000000020ULL,
1b413d55 491 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 492 PPC_64BX = 0x0000000000000040ULL,
1b413d55 493 /* 64 bits hypervisor extensions */
f610349f 494 PPC_64H = 0x0000000000000080ULL,
1b413d55 495 /* New wait instruction (PowerPC 2.0x) */
f610349f 496 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 497 /* Time base mftb instruction */
f610349f 498 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 499
500 /* Fixed-point unit extensions */
501 /* PowerPC 602 specific */
f610349f 502 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 503 /* isel instruction */
504 PPC_ISEL = 0x0000000000000800ULL,
505 /* popcntb instruction */
506 PPC_POPCNTB = 0x0000000000001000ULL,
507 /* string load / store */
508 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 509
510 /* Floating-point unit extensions */
511 /* Optional floating point instructions */
512 PPC_FLOAT = 0x0000000000010000ULL,
513 /* New floating-point extensions (PowerPC 2.0x) */
514 PPC_FLOAT_EXT = 0x0000000000020000ULL,
515 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
516 PPC_FLOAT_FRES = 0x0000000000080000ULL,
517 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
518 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
519 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
520 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
521
522 /* Vector/SIMD extensions */
523 /* Altivec support */
524 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 525 /* PowerPC 2.03 SPE extension */
05332d70 526 PPC_SPE = 0x0000000002000000ULL,
1b413d55 527 /* PowerPC 2.03 SPE floating-point extension */
05332d70 528 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 529
12de9a39 530 /* Optional memory control instructions */
1b413d55
JM		 531 PPC_MEM_TLBIA = 0x0000000010000000ULL,
532 PPC_MEM_TLBIE = 0x0000000020000000ULL,
533 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
534 /* sync instruction */
535 PPC_MEM_SYNC = 0x0000000080000000ULL,
536 /* eieio instruction */
537 PPC_MEM_EIEIO = 0x0000000100000000ULL,
538
539 /* Cache control instructions */
c8623f2e 540 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 541 /* icbi instruction */
05332d70 542 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 543 /* dcbz instruction with fixed cache line size */
05332d70 544 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 545 /* dcbz instruction with tunable cache line size */
05332d70 546 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 547 /* dcba instruction */
05332d70
JM		 548 PPC_CACHE_DCBA = 0x0000002000000000ULL,
549 /* Freescale cache locking instructions */
550 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 551
552 /* MMU related extensions */
553 /* external control instructions */
05332d70 554 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 555 /* segment register access instructions */
05332d70 556 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 557 /* PowerPC 6xx TLB management instructions */
05332d70 558 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 559 /* PowerPC 74xx TLB management instructions */
05332d70 560 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 561 /* PowerPC 40x TLB management instructions */
05332d70 562 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 563 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 564 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 565 /* SLB management */
05332d70 566 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 567
12de9a39 568 /* Embedded PowerPC dedicated instructions */
05332d70 569 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 570 /* PowerPC 40x exception model */
05332d70 571 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 572 /* PowerPC 405 Mac instructions */
05332d70 573 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 574 /* PowerPC 440 specific instructions */
05332d70 575 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 576 /* BookE (embedded) PowerPC specification */
05332d70
JM		 577 PPC_BOOKE = 0x0010000000000000ULL,
578 /* mfapidi instruction */
579 PPC_MFAPIDI = 0x0020000000000000ULL,
580 /* tlbiva instruction */
581 PPC_TLBIVA = 0x0040000000000000ULL,
582 /* tlbivax instruction */
583 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 584 /* PowerPC 4xx dedicated instructions */
05332d70 585 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 586 /* PowerPC 40x ibct instructions */
05332d70 587 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 588 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 589 PPC_RFMCI = 0x0400000000000000ULL,
590 /* rfdi instruction */
591 PPC_RFDI = 0x0800000000000000ULL,
592 /* DCR accesses */
593 PPC_DCR = 0x1000000000000000ULL,
594 /* DCR extended accesse */
595 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 596 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 597 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 598};
599
600/*****************************************************************************/
601/* PowerPC instructions table */
3fc6c082
FB		 602#if HOST_LONG_BITS == 64
603#define OPC_ALIGN 8
604#else
605#define OPC_ALIGN 4
606#endif
1b039c09 607#if defined(__APPLE__)
d9bce9d9 608#define OPCODES_SECTION \
3fc6c082 609 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 610#else
d9bce9d9 611#define OPCODES_SECTION \
3fc6c082 612 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 613#endif
614
76a66253 615#if defined(DO_PPC_STATISTICS)
79aceca5 616#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 617OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 618 .opc1 = op1, \
619 .opc2 = op2, \
620 .opc3 = op3, \
18fba28c 621 .pad = { 0, }, \
79aceca5
FB		 622 .handler = { \
623 .inval = invl, \
9a64fbe4 624 .type = _typ, \
79aceca5 625 .handler = &gen_##name, \
76a66253 626 .oname = stringify(name), \
79aceca5 627 }, \
3fc6c082 628 .oname = stringify(name), \
79aceca5 629}
c7697e1f
JM		 630#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
631OPCODES_SECTION opcode_t opc_##name = { \
632 .opc1 = op1, \
633 .opc2 = op2, \
634 .opc3 = op3, \
635 .pad = { 0, }, \
636 .handler = { \
637 .inval = invl, \
638 .type = _typ, \
639 .handler = &gen_##name, \
640 .oname = onam, \
641 }, \
642 .oname = onam, \
643}
76a66253
JM		 644#else
645#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
646OPCODES_SECTION opcode_t opc_##name = { \
647 .opc1 = op1, \
648 .opc2 = op2, \
649 .opc3 = op3, \
650 .pad = { 0, }, \
651 .handler = { \
652 .inval = invl, \
653 .type = _typ, \
654 .handler = &gen_##name, \
655 }, \
656 .oname = stringify(name), \
657}
c7697e1f
JM		 658#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
659OPCODES_SECTION opcode_t opc_##name = { \
660 .opc1 = op1, \
661 .opc2 = op2, \
662 .opc3 = op3, \
663 .pad = { 0, }, \
664 .handler = { \
665 .inval = invl, \
666 .type = _typ, \
667 .handler = &gen_##name, \
668 }, \
669 .oname = onam, \
670}
76a66253 671#endif
79aceca5
FB		 672
673#define GEN_OPCODE_MARK(name) \
18fba28c 674OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 675 .opc1 = 0xFF, \
676 .opc2 = 0xFF, \
677 .opc3 = 0xFF, \
18fba28c 678 .pad = { 0, }, \
79aceca5
FB		 679 .handler = { \
680 .inval = 0x00000000, \
9a64fbe4 681 .type = 0x00, \
79aceca5
FB		 682 .handler = NULL, \
683 }, \
3fc6c082 684 .oname = stringify(name), \
79aceca5
FB		 685}
686
687/* Start opcode list */
688GEN_OPCODE_MARK(start);
689
690/* Invalid instruction */
9a64fbe4
FB		 691GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
692{
e1833e1f 693 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 694}
695
79aceca5
FB		 696static opc_handler_t invalid_handler = {
697 .inval = 0xFFFFFFFF,
9a64fbe4 698 .type = PPC_NONE,
79aceca5
FB		 699 .handler = gen_invalid,
700};
701
e1571908
AJ		 702/*** Integer comparison ***/
703
ea363694 704static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 705{
706 int l1, l2, l3;
707
269f3e95
AJ		 708 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
709 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 710 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
711
712 l1 = gen_new_label();
713 l2 = gen_new_label();
714 l3 = gen_new_label();
715 if (s) {
ea363694
AJ		 716 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
717 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 718 } else {
ea363694
AJ		 719 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
720 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 721 }
722 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
723 tcg_gen_br(l3);
724 gen_set_label(l1);
725 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
726 tcg_gen_br(l3);
727 gen_set_label(l2);
728 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
729 gen_set_label(l3);
730}
731
ea363694 732static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 733{
ea363694
AJ		 734 TCGv t0 = tcg_const_local_tl(arg1);
735 gen_op_cmp(arg0, t0, s, crf);
736 tcg_temp_free(t0);
e1571908
AJ		 737}
738
739#if defined(TARGET_PPC64)
ea363694 740static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 741{
ea363694 742 TCGv t0, t1;
a7812ae4
PB		 743 t0 = tcg_temp_local_new();
744 t1 = tcg_temp_local_new();
e1571908 745 if (s) {
ea363694
AJ		 746 tcg_gen_ext32s_tl(t0, arg0);
747 tcg_gen_ext32s_tl(t1, arg1);
e1571908 748 } else {
ea363694
AJ		 749 tcg_gen_ext32u_tl(t0, arg0);
750 tcg_gen_ext32u_tl(t1, arg1);
e1571908 751 }
ea363694
AJ		 752 gen_op_cmp(t0, t1, s, crf);
753 tcg_temp_free(t1);
754 tcg_temp_free(t0);
e1571908
AJ		 755}
756
ea363694 757static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 758{
ea363694
AJ		 759 TCGv t0 = tcg_const_local_tl(arg1);
760 gen_op_cmp32(arg0, t0, s, crf);
761 tcg_temp_free(t0);
e1571908
AJ		 762}
763#endif
764
765static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
766{
767#if defined(TARGET_PPC64)
768 if (!(ctx->sf_mode))
769 gen_op_cmpi32(reg, 0, 1, 0);
770 else
771#endif
772 gen_op_cmpi(reg, 0, 1, 0);
773}
774
775/* cmp */
776GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
777{
778#if defined(TARGET_PPC64)
779 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
780 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
781 1, crfD(ctx->opcode));
782 else
783#endif
784 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
785 1, crfD(ctx->opcode));
786}
787
788/* cmpi */
789GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
790{
791#if defined(TARGET_PPC64)
792 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
793 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
794 1, crfD(ctx->opcode));
795 else
796#endif
797 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
798 1, crfD(ctx->opcode));
799}
800
801/* cmpl */
802GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
803{
804#if defined(TARGET_PPC64)
805 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
806 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
807 0, crfD(ctx->opcode));
808 else
809#endif
810 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
811 0, crfD(ctx->opcode));
812}
813
814/* cmpli */
815GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
816{
817#if defined(TARGET_PPC64)
818 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
819 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
820 0, crfD(ctx->opcode));
821 else
822#endif
823 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
824 0, crfD(ctx->opcode));
825}
826
827/* isel (PowerPC 2.03 specification) */
828GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
829{
830 int l1, l2;
831 uint32_t bi = rC(ctx->opcode);
832 uint32_t mask;
a7812ae4 833 TCGv_i32 t0;
e1571908
AJ		 834
835 l1 = gen_new_label();
836 l2 = gen_new_label();
837
838 mask = 1 << (3 - (bi & 0x03));
a7812ae4 839 t0 = tcg_temp_new_i32();
fea0c503
AJ		 840 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
841 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 842 if (rA(ctx->opcode) == 0)
843 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
844 else
845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
846 tcg_gen_br(l2);
847 gen_set_label(l1);
848 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
849 gen_set_label(l2);
a7812ae4 850 tcg_temp_free_i32(t0);
e1571908
AJ		 851}
852
79aceca5 853/*** Integer arithmetic ***/
79aceca5 854
74637406
AJ		 855static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
856{
857 int l1;
858 TCGv t0;
79aceca5 859
74637406
AJ		 860 l1 = gen_new_label();
861 /* Start with XER OV disabled, the most likely case */
862 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 863 t0 = tcg_temp_local_new();
74637406
AJ		 864 tcg_gen_xor_tl(t0, arg0, arg1);
865#if defined(TARGET_PPC64)
866 if (!ctx->sf_mode)
867 tcg_gen_ext32s_tl(t0, t0);
868#endif
869 if (sub)
870 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
871 else
872 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
873 tcg_gen_xor_tl(t0, arg1, arg2);
874#if defined(TARGET_PPC64)
875 if (!ctx->sf_mode)
876 tcg_gen_ext32s_tl(t0, t0);
877#endif
878 if (sub)
879 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
880 else
881 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
882 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
883 gen_set_label(l1);
884 tcg_temp_free(t0);
79aceca5
FB		 885}
886
74637406
AJ		 887static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
888{
889 int l1 = gen_new_label();
d9bce9d9
JM		 890
891#if defined(TARGET_PPC64)
74637406
AJ		 892 if (!(ctx->sf_mode)) {
893 TCGv t0, t1;
a7812ae4
PB		 894 t0 = tcg_temp_new();
895 t1 = tcg_temp_new();
d9bce9d9 896
74637406
AJ		 897 tcg_gen_ext32u_tl(t0, arg1);
898 tcg_gen_ext32u_tl(t1, arg2);
899 if (sub) {
900 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 901 } else {
74637406
AJ		 902 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
903 }
a9730017
AJ		 904 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
905 gen_set_label(l1);
906 tcg_temp_free(t0);
907 tcg_temp_free(t1);
74637406
AJ		 908 } else
909#endif
a9730017
AJ		 910 {
911 if (sub) {
912 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
913 } else {
914 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
915 }
916 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
917 gen_set_label(l1);
74637406 918 }
d9bce9d9
JM		 919}
920
74637406
AJ		 921/* Common add function */
922static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
923 int add_ca, int compute_ca, int compute_ov)
924{
925 TCGv t0, t1;
d9bce9d9 926
74637406 927 if ((!compute_ca && !compute_ov) ||
a7812ae4 928 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 929 t0 = ret;
930 } else {
a7812ae4 931 t0 = tcg_temp_local_new();
74637406 932 }
79aceca5 933
74637406 934 if (add_ca) {
a7812ae4 935 t1 = tcg_temp_local_new();
74637406
AJ		 936 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
937 tcg_gen_shri_tl(t1, t1, XER_CA);
938 }
79aceca5 939
74637406
AJ		 940 if (compute_ca && compute_ov) {
941 /* Start with XER CA and OV disabled, the most likely case */
942 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
943 } else if (compute_ca) {
944 /* Start with XER CA disabled, the most likely case */
945 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
946 } else if (compute_ov) {
947 /* Start with XER OV disabled, the most likely case */
948 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
949 }
79aceca5 950
74637406
AJ		 951 tcg_gen_add_tl(t0, arg1, arg2);
952
953 if (compute_ca) {
954 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
955 }
956 if (add_ca) {
957 tcg_gen_add_tl(t0, t0, t1);
958 gen_op_arith_compute_ca(ctx, t0, t1, 0);
959 tcg_temp_free(t1);
960 }
961 if (compute_ov) {
962 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
963 }
964
965 if (unlikely(Rc(ctx->opcode) != 0))
966 gen_set_Rc0(ctx, t0);
967
a7812ae4 968 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 969 tcg_gen_mov_tl(ret, t0);
970 tcg_temp_free(t0);
971 }
39dd32ee 972}
74637406
AJ		 973/* Add functions with two operands */
974#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
975GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
976{ \
977 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 add_ca, compute_ca, compute_ov); \
980}
981/* Add functions with one operand and one immediate */
982#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
983 add_ca, compute_ca, compute_ov) \
984GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
985{ \
986 TCGv t0 = tcg_const_local_tl(const_val); \
987 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
988 cpu_gpr[rA(ctx->opcode)], t0, \
989 add_ca, compute_ca, compute_ov); \
990 tcg_temp_free(t0); \
991}
992
993/* add add. addo addo. */
994GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
995GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
996/* addc addc. addco addco. */
997GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
998GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
999/* adde adde. addeo addeo. */
1000GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1001GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1002/* addme addme. addmeo addmeo. */
1003GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1004GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1005/* addze addze. addzeo addzeo.*/
1006GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1007GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1008/* addi */
1009GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1010{
74637406
AJ		 1011 target_long simm = SIMM(ctx->opcode);
1012
1013 if (rA(ctx->opcode) == 0) {
1014 /* li case */
1015 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1016 } else {
1017 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1018 }
d9bce9d9 1019}
74637406
AJ		 1020/* addic addic.*/
1021static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1022 int compute_Rc0)
d9bce9d9 1023{
74637406
AJ		 1024 target_long simm = SIMM(ctx->opcode);
1025
1026 /* Start with XER CA and OV disabled, the most likely case */
1027 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1028
1029 if (likely(simm != 0)) {
a7812ae4 1030 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1031 tcg_gen_addi_tl(t0, arg1, simm);
1032 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1033 tcg_gen_mov_tl(ret, t0);
1034 tcg_temp_free(t0);
1035 } else {
1036 tcg_gen_mov_tl(ret, arg1);
1037 }
1038 if (compute_Rc0) {
1039 gen_set_Rc0(ctx, ret);
1040 }
d9bce9d9 1041}
74637406 1042GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1043{
74637406 1044 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1045}
74637406 1046GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1047{
74637406 1048 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1049}
74637406
AJ		 1050/* addis */
1051GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1052{
74637406
AJ		 1053 target_long simm = SIMM(ctx->opcode);
1054
1055 if (rA(ctx->opcode) == 0) {
1056 /* lis case */
1057 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1058 } else {
1059 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1060 }
d9bce9d9 1061}
74637406
AJ		 1062
1063static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1064 int sign, int compute_ov)
d9bce9d9 1065{
2ef1b120
AJ		 1066 int l1 = gen_new_label();
1067 int l2 = gen_new_label();
a7812ae4
PB		 1068 TCGv_i32 t0 = tcg_temp_local_new_i32();
1069 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1070
2ef1b120
AJ		 1071 tcg_gen_trunc_tl_i32(t0, arg1);
1072 tcg_gen_trunc_tl_i32(t1, arg2);
1073 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1074 if (sign) {
2ef1b120
AJ		 1075 int l3 = gen_new_label();
1076 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1078 gen_set_label(l3);
2ef1b120 1079 tcg_gen_div_i32(t0, t0, t1);
74637406 1080 } else {
2ef1b120 1081 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1082 }
1083 if (compute_ov) {
1084 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1085 }
1086 tcg_gen_br(l2);
1087 gen_set_label(l1);
1088 if (sign) {
2ef1b120 1089 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1090 } else {
1091 tcg_gen_movi_i32(t0, 0);
1092 }
1093 if (compute_ov) {
1094 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1095 }
1096 gen_set_label(l2);
2ef1b120 1097 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1098 tcg_temp_free_i32(t0);
1099 tcg_temp_free_i32(t1);
74637406
AJ		 1100 if (unlikely(Rc(ctx->opcode) != 0))
1101 gen_set_Rc0(ctx, ret);
d9bce9d9 1102}
74637406
AJ		 1103/* Div functions */
1104#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1105GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1106{ \
1107 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1108 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1109 sign, compute_ov); \
1110}
1111/* divwu divwu. divwuo divwuo. */
1112GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1113GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1114/* divw divw. divwo divwo. */
1115GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1116GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1117#if defined(TARGET_PPC64)
2ef1b120
AJ		 1118static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1119 int sign, int compute_ov)
d9bce9d9 1120{
2ef1b120
AJ		 1121 int l1 = gen_new_label();
1122 int l2 = gen_new_label();
74637406
AJ		 1123
1124 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1125 if (sign) {
2ef1b120 1126 int l3 = gen_new_label();
74637406
AJ		 1127 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1128 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1129 gen_set_label(l3);
74637406
AJ		 1130 tcg_gen_div_i64(ret, arg1, arg2);
1131 } else {
1132 tcg_gen_divu_i64(ret, arg1, arg2);
1133 }
1134 if (compute_ov) {
1135 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1136 }
1137 tcg_gen_br(l2);
1138 gen_set_label(l1);
1139 if (sign) {
1140 tcg_gen_sari_i64(ret, arg1, 63);
1141 } else {
1142 tcg_gen_movi_i64(ret, 0);
1143 }
1144 if (compute_ov) {
1145 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1146 }
1147 gen_set_label(l2);
1148 if (unlikely(Rc(ctx->opcode) != 0))
1149 gen_set_Rc0(ctx, ret);
d9bce9d9 1150}
74637406
AJ		 1151#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1152GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1153{ \
2ef1b120
AJ		 1154 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1155 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1156 sign, compute_ov); \
74637406
AJ		 1157}
1158/* divwu divwu. divwuo divwuo. */
1159GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1160GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1161/* divw divw. divwo divwo. */
1162GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1163GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1164#endif
74637406
AJ		 1165
1166/* mulhw mulhw. */
1167GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1168{
a7812ae4 1169 TCGv_i64 t0, t1;
74637406 1170
a7812ae4
PB		 1171 t0 = tcg_temp_new_i64();
1172 t1 = tcg_temp_new_i64();
74637406
AJ		 1173#if defined(TARGET_PPC64)
1174 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1175 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1176 tcg_gen_mul_i64(t0, t0, t1);
1177 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1178#else
1179 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(t0, t0, 32);
1183 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1184#endif
a7812ae4
PB		 1185 tcg_temp_free_i64(t0);
1186 tcg_temp_free_i64(t1);
74637406
AJ		 1187 if (unlikely(Rc(ctx->opcode) != 0))
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1189}
74637406
AJ		 1190/* mulhwu mulhwu. */
1191GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1192{
a7812ae4 1193 TCGv_i64 t0, t1;
74637406 1194
a7812ae4
PB		 1195 t0 = tcg_temp_new_i64();
1196 t1 = tcg_temp_new_i64();
d9bce9d9 1197#if defined(TARGET_PPC64)
74637406
AJ		 1198 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1199 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1200 tcg_gen_mul_i64(t0, t0, t1);
1201 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1202#else
1203 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(t0, t0, 32);
1207 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1208#endif
a7812ae4
PB		 1209 tcg_temp_free_i64(t0);
1210 tcg_temp_free_i64(t1);
74637406
AJ		 1211 if (unlikely(Rc(ctx->opcode) != 0))
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1213}
74637406
AJ		 1214/* mullw mullw. */
1215GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1216{
74637406
AJ		 1217 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1218 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1219 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1220 if (unlikely(Rc(ctx->opcode) != 0))
1221 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1222}
74637406
AJ		 1223/* mullwo mullwo. */
1224GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1225{
74637406 1226 int l1;
a7812ae4 1227 TCGv_i64 t0, t1;
74637406 1228
a7812ae4
PB		 1229 t0 = tcg_temp_new_i64();
1230 t1 = tcg_temp_new_i64();
74637406
AJ		 1231 l1 = gen_new_label();
1232 /* Start with XER OV disabled, the most likely case */
1233 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1234#if defined(TARGET_PPC64)
1235 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1236 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1237#else
1238 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1239 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1240#endif
74637406
AJ		 1241 tcg_gen_mul_i64(t0, t0, t1);
1242#if defined(TARGET_PPC64)
1243 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1244 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1245#else
1246 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1247 tcg_gen_ext32s_i64(t1, t0);
1248 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1249#endif
1250 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1251 gen_set_label(l1);
a7812ae4
PB		 1252 tcg_temp_free_i64(t0);
1253 tcg_temp_free_i64(t1);
74637406
AJ		 1254 if (unlikely(Rc(ctx->opcode) != 0))
1255 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1256}
74637406
AJ		 1257/* mulli */
1258GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1259{
74637406
AJ		 1260 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1261 SIMM(ctx->opcode));
d9bce9d9
JM		 1262}
1263#if defined(TARGET_PPC64)
74637406
AJ		 1264#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1265GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1266{ \
a7812ae4 1267 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1268 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1269 if (unlikely(Rc(ctx->opcode) != 0)) \
1270 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1271}
74637406
AJ		 1272/* mulhd mulhd. */
1273GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1274/* mulhdu mulhdu. */
1275GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1276/* mulld mulld. */
1277GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1278{
74637406
AJ		 1279 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1280 cpu_gpr[rB(ctx->opcode)]);
1281 if (unlikely(Rc(ctx->opcode) != 0))
1282 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1283}
74637406
AJ		 1284/* mulldo mulldo. */
1285GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1286#endif
74637406
AJ		 1287
1288/* neg neg. nego nego. */
ec6469a3 1289static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1290{
ec6469a3
AJ		 1291 int l1 = gen_new_label();
1292 int l2 = gen_new_label();
a7812ae4 1293 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1294#if defined(TARGET_PPC64)
74637406 1295 if (ctx->sf_mode) {
741a7444 1296 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1297 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1298 } else
1299#endif
1300 {
1301 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1303 }
74637406
AJ		 1304 tcg_gen_neg_tl(ret, arg1);
1305 if (ov_check) {
1306 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1307 }
1308 tcg_gen_br(l2);
1309 gen_set_label(l1);
ec6469a3 1310 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1311 if (ov_check) {
1312 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1313 }
1314 gen_set_label(l2);
ec6469a3 1315 tcg_temp_free(t0);
74637406
AJ		 1316 if (unlikely(Rc(ctx->opcode) != 0))
1317 gen_set_Rc0(ctx, ret);
1318}
1319GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1320{
ec6469a3 1321 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1322}
74637406 1323GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1324{
ec6469a3 1325 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1326}
74637406
AJ		 1327
1328/* Common subf function */
1329static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1330 int add_ca, int compute_ca, int compute_ov)
79aceca5 1331{
74637406 1332 TCGv t0, t1;
76a66253 1333
74637406 1334 if ((!compute_ca && !compute_ov) ||
a7812ae4 1335 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1336 t0 = ret;
e864cabd 1337 } else {
a7812ae4 1338 t0 = tcg_temp_local_new();
d9bce9d9 1339 }
76a66253 1340
74637406 1341 if (add_ca) {
a7812ae4 1342 t1 = tcg_temp_local_new();
74637406
AJ		 1343 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1344 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1345 }
79aceca5 1346
74637406
AJ		 1347 if (compute_ca && compute_ov) {
1348 /* Start with XER CA and OV disabled, the most likely case */
1349 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1350 } else if (compute_ca) {
1351 /* Start with XER CA disabled, the most likely case */
1352 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1353 } else if (compute_ov) {
1354 /* Start with XER OV disabled, the most likely case */
1355 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1356 }
1357
1358 if (add_ca) {
1359 tcg_gen_not_tl(t0, arg1);
1360 tcg_gen_add_tl(t0, t0, arg2);
1361 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1362 tcg_gen_add_tl(t0, t0, t1);
1363 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1364 tcg_temp_free(t1);
79aceca5 1365 } else {
74637406
AJ		 1366 tcg_gen_sub_tl(t0, arg2, arg1);
1367 if (compute_ca) {
1368 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1369 }
1370 }
1371 if (compute_ov) {
1372 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1373 }
1374
1375 if (unlikely(Rc(ctx->opcode) != 0))
1376 gen_set_Rc0(ctx, t0);
1377
a7812ae4 1378 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1379 tcg_gen_mov_tl(ret, t0);
1380 tcg_temp_free(t0);
79aceca5 1381 }
79aceca5 1382}
74637406
AJ		 1383/* Sub functions with Two operands functions */
1384#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1385GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1386{ \
1387 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1388 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1389 add_ca, compute_ca, compute_ov); \
1390}
1391/* Sub functions with one operand and one immediate */
1392#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1393 add_ca, compute_ca, compute_ov) \
1394GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1395{ \
1396 TCGv t0 = tcg_const_local_tl(const_val); \
1397 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1398 cpu_gpr[rA(ctx->opcode)], t0, \
1399 add_ca, compute_ca, compute_ov); \
1400 tcg_temp_free(t0); \
1401}
1402/* subf subf. subfo subfo. */
1403GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1404GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1405/* subfc subfc. subfco subfco. */
1406GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1407GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1408/* subfe subfe. subfeo subfo. */
1409GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1410GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1411/* subfme subfme. subfmeo subfmeo. */
1412GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1413GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1414/* subfze subfze. subfzeo subfzeo.*/
1415GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1416GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1417/* subfic */
1418GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1419{
74637406
AJ		 1420 /* Start with XER CA and OV disabled, the most likely case */
1421 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1422 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1423 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1424 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1425 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1426 tcg_temp_free(t1);
1427 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1428 tcg_temp_free(t0);
79aceca5
FB		 1429}
1430
79aceca5 1431/*** Integer logical ***/
26d67362
AJ		 1432#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1433GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1434{ \
26d67362
AJ		 1435 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1436 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1437 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1438 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1439}
79aceca5 1440
26d67362 1441#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1442GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1443{ \
26d67362 1444 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1445 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1446 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1447}
1448
1449/* and & and. */
26d67362 1450GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1451/* andc & andc. */
26d67362 1452GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1453/* andi. */
c7697e1f 1454GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1455{
26d67362
AJ		 1456 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1457 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1458}
1459/* andis. */
c7697e1f 1460GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1461{
26d67362
AJ		 1462 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1463 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1464}
79aceca5 1465/* cntlzw */
26d67362
AJ		 1466GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1467{
a7812ae4 1468 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1469 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1470 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1471}
79aceca5 1472/* eqv & eqv. */
26d67362 1473GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1474/* extsb & extsb. */
26d67362 1475GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1476/* extsh & extsh. */
26d67362 1477GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1478/* nand & nand. */
26d67362 1479GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1480/* nor & nor. */
26d67362 1481GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1482/* or & or. */
9a64fbe4
FB		 1483GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1484{
76a66253
JM		 1485 int rs, ra, rb;
1486
1487 rs = rS(ctx->opcode);
1488 ra = rA(ctx->opcode);
1489 rb = rB(ctx->opcode);
1490 /* Optimisation for mr. ri case */
1491 if (rs != ra || rs != rb) {
26d67362
AJ		 1492 if (rs != rb)
1493 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1494 else
1495 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1496 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1497 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1498 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1499 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1500#if defined(TARGET_PPC64)
1501 } else {
26d67362
AJ		 1502 int prio = 0;
1503
c80f84e3
JM		 1504 switch (rs) {
1505 case 1:
1506 /* Set process priority to low */
26d67362 1507 prio = 2;
c80f84e3
JM		 1508 break;
1509 case 6:
1510 /* Set process priority to medium-low */
26d67362 1511 prio = 3;
c80f84e3
JM		 1512 break;
1513 case 2:
1514 /* Set process priority to normal */
26d67362 1515 prio = 4;
c80f84e3 1516 break;
be147d08
JM		 1517#if !defined(CONFIG_USER_ONLY)
1518 case 31:
1519 if (ctx->supervisor > 0) {
1520 /* Set process priority to very low */
26d67362 1521 prio = 1;
be147d08
JM		 1522 }
1523 break;
1524 case 5:
1525 if (ctx->supervisor > 0) {
1526 /* Set process priority to medium-hight */
26d67362 1527 prio = 5;
be147d08
JM		 1528 }
1529 break;
1530 case 3:
1531 if (ctx->supervisor > 0) {
1532 /* Set process priority to high */
26d67362 1533 prio = 6;
be147d08
JM		 1534 }
1535 break;
be147d08
JM		 1536 case 7:
1537 if (ctx->supervisor > 1) {
1538 /* Set process priority to very high */
26d67362 1539 prio = 7;
be147d08
JM		 1540 }
1541 break;
be147d08 1542#endif
c80f84e3
JM		 1543 default:
1544 /* nop */
1545 break;
1546 }
26d67362 1547 if (prio) {
a7812ae4 1548 TCGv t0 = tcg_temp_new();
ea363694
AJ		 1549 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1550 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1551 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1552 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1553 tcg_temp_free(t0);
26d67362 1554 }
c80f84e3 1555#endif
9a64fbe4 1556 }
9a64fbe4 1557}
79aceca5 1558/* orc & orc. */
26d67362 1559GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1560/* xor & xor. */
9a64fbe4
FB		 1561GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1562{
9a64fbe4 1563 /* Optimisation for "set to zero" case */
26d67362 1564 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1565 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1566 else
1567 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1568 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1570}
79aceca5
FB		 1571/* ori */
1572GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1573{
76a66253 1574 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1575
9a64fbe4
FB		 1576 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1577 /* NOP */
76a66253 1578 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1579 return;
76a66253 1580 }
26d67362 1581 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1582}
1583/* oris */
1584GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1585{
76a66253 1586 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1587
9a64fbe4
FB		 1588 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1589 /* NOP */
1590 return;
76a66253 1591 }
26d67362 1592 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1593}
1594/* xori */
1595GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1596{
76a66253 1597 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1598
1599 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1600 /* NOP */
1601 return;
1602 }
26d67362 1603 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1604}
79aceca5
FB		 1605/* xoris */
1606GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1607{
76a66253 1608 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1609
1610 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1611 /* NOP */
1612 return;
1613 }
26d67362 1614 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1615}
d9bce9d9 1616/* popcntb : PowerPC 2.03 specification */
05332d70 1617GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1618{
d9bce9d9
JM		 1619#if defined(TARGET_PPC64)
1620 if (ctx->sf_mode)
a7812ae4 1621 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1622 else
1623#endif
a7812ae4 1624 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1625}
1626
1627#if defined(TARGET_PPC64)
1628/* extsw & extsw. */
26d67362 1629GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1630/* cntlzd */
26d67362
AJ		 1631GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1632{
a7812ae4 1633 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1634 if (unlikely(Rc(ctx->opcode) != 0))
1635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1636}
d9bce9d9
JM		 1637#endif
1638
79aceca5
FB		 1639/*** Integer rotate ***/
1640/* rlwimi & rlwimi. */
1641GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1642{
76a66253 1643 uint32_t mb, me, sh;
79aceca5
FB		 1644
1645 mb = MB(ctx->opcode);
1646 me = ME(ctx->opcode);
76a66253 1647 sh = SH(ctx->opcode);
d03ef511
AJ		 1648 if (likely(sh == 0 && mb == 0 && me == 31)) {
1649 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1650 } else {
d03ef511 1651 target_ulong mask;
a7812ae4
PB		 1652 TCGv t1;
1653 TCGv t0 = tcg_temp_new();
54843a58 1654#if defined(TARGET_PPC64)
a7812ae4
PB		 1655 TCGv_i32 t2 = tcg_temp_new_i32();
1656 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1657 tcg_gen_rotli_i32(t2, t2, sh);
1658 tcg_gen_extu_i32_i64(t0, t2);
1659 tcg_temp_free_i32(t2);
54843a58
AJ		 1660#else
1661 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1662#endif
76a66253 1663#if defined(TARGET_PPC64)
d03ef511
AJ		 1664 mb += 32;
1665 me += 32;
76a66253 1666#endif
d03ef511 1667 mask = MASK(mb, me);
a7812ae4 1668 t1 = tcg_temp_new();
d03ef511
AJ		 1669 tcg_gen_andi_tl(t0, t0, mask);
1670 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1671 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1672 tcg_temp_free(t0);
1673 tcg_temp_free(t1);
1674 }
76a66253 1675 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1676 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1677}
1678/* rlwinm & rlwinm. */
1679GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1680{
1681 uint32_t mb, me, sh;
3b46e624 1682
79aceca5
FB		 1683 sh = SH(ctx->opcode);
1684 mb = MB(ctx->opcode);
1685 me = ME(ctx->opcode);
d03ef511
AJ		 1686
1687 if (likely(mb == 0 && me == (31 - sh))) {
1688 if (likely(sh == 0)) {
1689 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1690 } else {
a7812ae4 1691 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1692 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1693 tcg_gen_shli_tl(t0, t0, sh);
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1695 tcg_temp_free(t0);
79aceca5 1696 }
d03ef511 1697 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1698 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1699 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1700 tcg_gen_shri_tl(t0, t0, mb);
1701 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1702 tcg_temp_free(t0);
1703 } else {
a7812ae4 1704 TCGv t0 = tcg_temp_new();
54843a58 1705#if defined(TARGET_PPC64)
a7812ae4 1706 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1707 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1708 tcg_gen_rotli_i32(t1, t1, sh);
1709 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1710 tcg_temp_free_i32(t1);
54843a58
AJ		 1711#else
1712 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1713#endif
76a66253 1714#if defined(TARGET_PPC64)
d03ef511
AJ		 1715 mb += 32;
1716 me += 32;
76a66253 1717#endif
d03ef511
AJ		 1718 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1719 tcg_temp_free(t0);
1720 }
76a66253 1721 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1722 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1723}
1724/* rlwnm & rlwnm. */
1725GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1726{
1727 uint32_t mb, me;
54843a58
AJ		 1728 TCGv t0;
1729#if defined(TARGET_PPC64)
a7812ae4 1730 TCGv_i32 t1, t2;
54843a58 1731#endif
79aceca5
FB		 1732
1733 mb = MB(ctx->opcode);
1734 me = ME(ctx->opcode);
a7812ae4 1735 t0 = tcg_temp_new();
d03ef511 1736 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1737#if defined(TARGET_PPC64)
a7812ae4
PB		 1738 t1 = tcg_temp_new_i32();
1739 t2 = tcg_temp_new_i32();
54843a58
AJ		 1740 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1741 tcg_gen_trunc_i64_i32(t2, t0);
1742 tcg_gen_rotl_i32(t1, t1, t2);
1743 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1744 tcg_temp_free_i32(t1);
1745 tcg_temp_free_i32(t2);
54843a58
AJ		 1746#else
1747 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1748#endif
76a66253
JM		 1749 if (unlikely(mb != 0 || me != 31)) {
1750#if defined(TARGET_PPC64)
1751 mb += 32;
1752 me += 32;
1753#endif
54843a58 1754 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1755 } else {
54843a58 1756 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1757 }
54843a58 1758 tcg_temp_free(t0);
76a66253 1759 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1760 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1761}
1762
d9bce9d9
JM		 1763#if defined(TARGET_PPC64)
1764#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1765GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1766{ \
1767 gen_##name(ctx, 0); \
1768} \
c7697e1f
JM		 1769GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1770 PPC_64B) \
d9bce9d9
JM		 1771{ \
1772 gen_##name(ctx, 1); \
1773}
1774#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1775GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1776{ \
1777 gen_##name(ctx, 0, 0); \
1778} \
c7697e1f
JM		 1779GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1780 PPC_64B) \
d9bce9d9
JM		 1781{ \
1782 gen_##name(ctx, 0, 1); \
1783} \
c7697e1f
JM		 1784GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1785 PPC_64B) \
d9bce9d9
JM		 1786{ \
1787 gen_##name(ctx, 1, 0); \
1788} \
c7697e1f
JM		 1789GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1790 PPC_64B) \
d9bce9d9
JM		 1791{ \
1792 gen_##name(ctx, 1, 1); \
1793}
51789c41 1794
b068d6a7
JM		 1795static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1796 uint32_t me, uint32_t sh)
51789c41 1797{
d03ef511
AJ		 1798 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1799 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1800 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1801 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1802 } else {
a7812ae4 1803 TCGv t0 = tcg_temp_new();
54843a58 1804 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1805 if (likely(mb == 0 && me == 63)) {
54843a58 1806 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1807 } else {
1808 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1809 }
d03ef511 1810 tcg_temp_free(t0);
51789c41 1811 }
51789c41 1812 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1814}
d9bce9d9 1815/* rldicl - rldicl. */
b068d6a7 1816static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1817{
51789c41 1818 uint32_t sh, mb;
d9bce9d9 1819
9d53c753
JM		 1820 sh = SH(ctx->opcode) | (shn << 5);
1821 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1822 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1823}
51789c41 1824GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1825/* rldicr - rldicr. */
b068d6a7 1826static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1827{
51789c41 1828 uint32_t sh, me;
d9bce9d9 1829
9d53c753
JM		 1830 sh = SH(ctx->opcode) | (shn << 5);
1831 me = MB(ctx->opcode) | (men << 5);
51789c41 1832 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1833}
51789c41 1834GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1835/* rldic - rldic. */
b068d6a7 1836static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1837{
51789c41 1838 uint32_t sh, mb;
d9bce9d9 1839
9d53c753
JM		 1840 sh = SH(ctx->opcode) | (shn << 5);
1841 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1842 gen_rldinm(ctx, mb, 63 - sh, sh);
1843}
1844GEN_PPC64_R4(rldic, 0x1E, 0x04);
1845
b068d6a7
JM		 1846static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1847 uint32_t me)
51789c41 1848{
54843a58 1849 TCGv t0;
d03ef511
AJ		 1850
1851 mb = MB(ctx->opcode);
1852 me = ME(ctx->opcode);
a7812ae4 1853 t0 = tcg_temp_new();
d03ef511 1854 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1855 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1856 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1857 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1858 } else {
1859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1860 }
1861 tcg_temp_free(t0);
51789c41 1862 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1863 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1864}
51789c41 1865
d9bce9d9 1866/* rldcl - rldcl. */
b068d6a7 1867static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1868{
51789c41 1869 uint32_t mb;
d9bce9d9 1870
9d53c753 1871 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1872 gen_rldnm(ctx, mb, 63);
d9bce9d9 1873}
36081602 1874GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1875/* rldcr - rldcr. */
b068d6a7 1876static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1877{
51789c41 1878 uint32_t me;
d9bce9d9 1879
9d53c753 1880 me = MB(ctx->opcode) | (men << 5);
51789c41 1881 gen_rldnm(ctx, 0, me);
d9bce9d9 1882}
36081602 1883GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1884/* rldimi - rldimi. */
b068d6a7 1885static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1886{
271a916e 1887 uint32_t sh, mb, me;
d9bce9d9 1888
9d53c753
JM		 1889 sh = SH(ctx->opcode) | (shn << 5);
1890 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1891 me = 63 - sh;
d03ef511
AJ		 1892 if (unlikely(sh == 0 && mb == 0)) {
1893 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1894 } else {
1895 TCGv t0, t1;
1896 target_ulong mask;
1897
a7812ae4 1898 t0 = tcg_temp_new();
54843a58 1899 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1900 t1 = tcg_temp_new();
d03ef511
AJ		 1901 mask = MASK(mb, me);
1902 tcg_gen_andi_tl(t0, t0, mask);
1903 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1904 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1905 tcg_temp_free(t0);
1906 tcg_temp_free(t1);
51789c41 1907 }
51789c41 1908 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1910}
36081602 1911GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1912#endif
1913
79aceca5
FB		 1914/*** Integer shift ***/
1915/* slw & slw. */
26d67362
AJ		 1916GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1917{
fea0c503 1918 TCGv t0;
26d67362
AJ		 1919 int l1, l2;
1920 l1 = gen_new_label();
1921 l2 = gen_new_label();
1922
a7812ae4 1923 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1924 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1925 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1926 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1927 tcg_gen_br(l2);
1928 gen_set_label(l1);
fea0c503 1929 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1930 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1931 gen_set_label(l2);
fea0c503 1932 tcg_temp_free(t0);
26d67362
AJ		 1933 if (unlikely(Rc(ctx->opcode) != 0))
1934 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1935}
79aceca5 1936/* sraw & sraw. */
26d67362
AJ		 1937GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1938{
a7812ae4
PB		 1939 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1940 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1941 if (unlikely(Rc(ctx->opcode) != 0))
1942 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1943}
79aceca5
FB		 1944/* srawi & srawi. */
1945GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1946{
26d67362
AJ		 1947 int sh = SH(ctx->opcode);
1948 if (sh != 0) {
1949 int l1, l2;
fea0c503 1950 TCGv t0;
26d67362
AJ		 1951 l1 = gen_new_label();
1952 l2 = gen_new_label();
a7812ae4 1953 t0 = tcg_temp_local_new();
fea0c503
AJ		 1954 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1955 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1956 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1957 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1958 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1959 tcg_gen_br(l2);
1960 gen_set_label(l1);
269f3e95 1961 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1962 gen_set_label(l2);
fea0c503
AJ		 1963 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1964 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1965 tcg_temp_free(t0);
26d67362
AJ		 1966 } else {
1967 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1968 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1969 }
76a66253 1970 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1972}
1973/* srw & srw. */
26d67362
AJ		 1974GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1975{
fea0c503 1976 TCGv t0, t1;
26d67362
AJ		 1977 int l1, l2;
1978 l1 = gen_new_label();
1979 l2 = gen_new_label();
d9bce9d9 1980
a7812ae4 1981 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1982 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1983 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1984 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1985 tcg_gen_br(l2);
1986 gen_set_label(l1);
a7812ae4 1987 t1 = tcg_temp_new();
fea0c503
AJ		 1988 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1989 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1990 tcg_temp_free(t1);
26d67362 1991 gen_set_label(l2);
fea0c503 1992 tcg_temp_free(t0);
26d67362
AJ		 1993 if (unlikely(Rc(ctx->opcode) != 0))
1994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1995}
d9bce9d9
JM		 1996#if defined(TARGET_PPC64)
1997/* sld & sld. */
26d67362
AJ		 1998GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1999{
fea0c503 2000 TCGv t0;
26d67362
AJ		 2001 int l1, l2;
2002 l1 = gen_new_label();
2003 l2 = gen_new_label();
2004
a7812ae4 2005 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2006 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2007 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2008 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2009 tcg_gen_br(l2);
2010 gen_set_label(l1);
fea0c503 2011 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2012 gen_set_label(l2);
fea0c503 2013 tcg_temp_free(t0);
26d67362
AJ		 2014 if (unlikely(Rc(ctx->opcode) != 0))
2015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2016}
d9bce9d9 2017/* srad & srad. */
26d67362
AJ		 2018GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2019{
a7812ae4
PB		 2020 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2021 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2022 if (unlikely(Rc(ctx->opcode) != 0))
2023 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2024}
d9bce9d9 2025/* sradi & sradi. */
b068d6a7 2026static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2027{
26d67362 2028 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2029 if (sh != 0) {
26d67362 2030 int l1, l2;
fea0c503 2031 TCGv t0;
26d67362
AJ		 2032 l1 = gen_new_label();
2033 l2 = gen_new_label();
a7812ae4 2034 t0 = tcg_temp_local_new();
26d67362 2035 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2036 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2037 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2038 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2039 tcg_gen_br(l2);
2040 gen_set_label(l1);
269f3e95 2041 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2042 gen_set_label(l2);
a9730017 2043 tcg_temp_free(t0);
26d67362
AJ		 2044 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2045 } else {
2046 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2047 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2048 }
d9bce9d9 2049 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2050 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2051}
c7697e1f 2052GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2053{
2054 gen_sradi(ctx, 0);
2055}
c7697e1f 2056GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2057{
2058 gen_sradi(ctx, 1);
2059}
2060/* srd & srd. */
26d67362
AJ		 2061GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2062{
fea0c503 2063 TCGv t0;
26d67362
AJ		 2064 int l1, l2;
2065 l1 = gen_new_label();
2066 l2 = gen_new_label();
2067
a7812ae4 2068 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2069 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2070 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2071 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2072 tcg_gen_br(l2);
2073 gen_set_label(l1);
fea0c503 2074 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2075 gen_set_label(l2);
fea0c503 2076 tcg_temp_free(t0);
26d67362
AJ		 2077 if (unlikely(Rc(ctx->opcode) != 0))
2078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2079}
d9bce9d9 2080#endif
79aceca5
FB		 2081
2082/*** Floating-Point arithmetic ***/
7c58044c 2083#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2084GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2085{ \
76a66253 2086 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2087 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2088 return; \
2089 } \
7c58044c 2090 gen_reset_fpstatus(); \
af12906f
AJ		 2091 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2092 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2093 if (isfloat) { \
af12906f 2094 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2095 } \
af12906f
AJ		 2096 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2097 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2098}
2099
7c58044c
JM		 2100#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2101_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2102_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2103
7c58044c
JM		 2104#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2105GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2106{ \
76a66253 2107 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2108 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2109 return; \
2110 } \
7c58044c 2111 gen_reset_fpstatus(); \
af12906f
AJ		 2112 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2113 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2114 if (isfloat) { \
af12906f 2115 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2116 } \
af12906f
AJ		 2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2118 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2119}
7c58044c
JM		 2120#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2121_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2122_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2123
7c58044c
JM		 2124#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2125GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2126{ \
76a66253 2127 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2128 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2129 return; \
2130 } \
7c58044c 2131 gen_reset_fpstatus(); \
af12906f
AJ		 2132 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2133 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2134 if (isfloat) { \
af12906f 2135 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2136 } \
af12906f
AJ		 2137 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2138 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2139}
7c58044c
JM		 2140#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2141_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2142_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2143
7c58044c 2144#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2145GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2146{ \
76a66253 2147 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2148 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2149 return; \
2150 } \
7c58044c 2151 gen_reset_fpstatus(); \
af12906f
AJ		 2152 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2153 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2154 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2155}
2156
7c58044c 2157#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2158GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2159{ \
76a66253 2160 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2161 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2162 return; \
2163 } \
7c58044c 2164 gen_reset_fpstatus(); \
af12906f
AJ		 2165 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2167 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2168}
2169
9a64fbe4 2170/* fadd - fadds */
7c58044c 2171GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2172/* fdiv - fdivs */
7c58044c 2173GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2174/* fmul - fmuls */
7c58044c 2175GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2176
d7e4b87e 2177/* fre */
7c58044c 2178GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2179
a750fc0b 2180/* fres */
7c58044c 2181GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2182
a750fc0b 2183/* frsqrte */
7c58044c
JM		 2184GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2185
2186/* frsqrtes */
af12906f 2187GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2188{
af12906f
AJ		 2189 if (unlikely(!ctx->fpu_enabled)) {
2190 GEN_EXCP_NO_FP(ctx);
2191 return;
2192 }
2193 gen_reset_fpstatus();
2194 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2195 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2196 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2197}
79aceca5 2198
a750fc0b 2199/* fsel */
7c58044c 2200_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2201/* fsub - fsubs */
7c58044c 2202GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2203/* Optional: */
2204/* fsqrt */
a750fc0b 2205GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2206{
76a66253 2207 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2208 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2209 return;
2210 }
7c58044c 2211 gen_reset_fpstatus();
af12906f
AJ		 2212 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2214}
79aceca5 2215
a750fc0b 2216GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2217{
76a66253 2218 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2219 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2220 return;
2221 }
7c58044c 2222 gen_reset_fpstatus();
af12906f
AJ		 2223 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2224 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2225 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2226}
2227
2228/*** Floating-Point multiply-and-add ***/
4ecc3190 2229/* fmadd - fmadds */
7c58044c 2230GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2231/* fmsub - fmsubs */
7c58044c 2232GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2233/* fnmadd - fnmadds */
7c58044c 2234GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2235/* fnmsub - fnmsubs */
7c58044c 2236GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2237
2238/*** Floating-Point round & convert ***/
2239/* fctiw */
7c58044c 2240GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2241/* fctiwz */
7c58044c 2242GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2243/* frsp */
7c58044c 2244GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2245#if defined(TARGET_PPC64)
2246/* fcfid */
7c58044c 2247GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2248/* fctid */
7c58044c 2249GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2250/* fctidz */
7c58044c 2251GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2252#endif
79aceca5 2253
d7e4b87e 2254/* frin */
7c58044c 2255GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2256/* friz */
7c58044c 2257GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2258/* frip */
7c58044c 2259GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2260/* frim */
7c58044c 2261GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2262
79aceca5
FB		 2263/*** Floating-Point compare ***/
2264/* fcmpo */
76a66253 2265GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2266{
76a66253 2267 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2268 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2269 return;
2270 }
7c58044c 2271 gen_reset_fpstatus();
af12906f
AJ		 2272 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2273 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2274 gen_helper_float_check_status();
79aceca5
FB		 2275}
2276
2277/* fcmpu */
76a66253 2278GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2279{
76a66253 2280 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2281 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2282 return;
2283 }
7c58044c 2284 gen_reset_fpstatus();
af12906f
AJ		 2285 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2286 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2287 gen_helper_float_check_status();
79aceca5
FB		 2288}
2289
9a64fbe4
FB		 2290/*** Floating-point move ***/
2291/* fabs */
7c58044c
JM		 2292/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2293GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2294
2295/* fmr - fmr. */
7c58044c 2296/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2297GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2298{
76a66253 2299 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2300 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2301 return;
2302 }
af12906f
AJ		 2303 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2304 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2305}
2306
2307/* fnabs */
7c58044c
JM		 2308/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2309GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2310/* fneg */
7c58044c
JM		 2311/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2312GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2313
79aceca5
FB		 2314/*** Floating-Point status & ctrl register ***/
2315/* mcrfs */
2316GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2317{
7c58044c
JM		 2318 int bfa;
2319
76a66253 2320 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2321 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2322 return;
2323 }
7c58044c
JM		 2324 gen_optimize_fprf();
2325 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2326 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2327 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2328 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2329}
2330
2331/* mffs */
2332GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2333{
76a66253 2334 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2335 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2336 return;
2337 }
7c58044c
JM		 2338 gen_optimize_fprf();
2339 gen_reset_fpstatus();
af12906f
AJ		 2340 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2341 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2342}
2343
2344/* mtfsb0 */
2345GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2346{
fb0eaffc 2347 uint8_t crb;
3b46e624 2348
76a66253 2349 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2350 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2351 return;
2352 }
7c58044c
JM		 2353 crb = 32 - (crbD(ctx->opcode) >> 2);
2354 gen_optimize_fprf();
2355 gen_reset_fpstatus();
2356 if (likely(crb != 30 && crb != 29))
af12906f 2357 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
7c58044c 2358 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2359 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2360 }
79aceca5
FB		 2361}
2362
2363/* mtfsb1 */
2364GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2365{
fb0eaffc 2366 uint8_t crb;
3b46e624 2367
76a66253 2368 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2369 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2370 return;
2371 }
7c58044c
JM		 2372 crb = 32 - (crbD(ctx->opcode) >> 2);
2373 gen_optimize_fprf();
2374 gen_reset_fpstatus();
2375 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2376 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
0f2f39c2 2377 TCGv_i32 t0 = tcg_const_i32(crb);
af12906f 2378 gen_helper_fpscr_setbit(t0);
0f2f39c2 2379 tcg_temp_free_i32(t0);
af12906f 2380 }
7c58044c 2381 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2382 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2383 }
2384 /* We can raise a differed exception */
af12906f 2385 gen_helper_float_check_status();
79aceca5
FB		 2386}
2387
2388/* mtfsf */
2389GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2390{
0f2f39c2 2391 TCGv_i32 t0;
af12906f 2392
76a66253 2393 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2394 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2395 return;
2396 }
7c58044c 2397 gen_optimize_fprf();
7c58044c 2398 gen_reset_fpstatus();
af12906f
AJ		 2399 t0 = tcg_const_i32(FM(ctx->opcode));
2400 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2401 tcg_temp_free_i32(t0);
7c58044c 2402 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2403 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2404 }
2405 /* We can raise a differed exception */
af12906f 2406 gen_helper_float_check_status();
79aceca5
FB		 2407}
2408
2409/* mtfsfi */
2410GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2411{
7c58044c 2412 int bf, sh;
0f2f39c2
AJ		 2413 TCGv_i64 t0;
2414 TCGv_i32 t1;
7c58044c 2415
76a66253 2416 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2417 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2418 return;
2419 }
7c58044c
JM		 2420 bf = crbD(ctx->opcode) >> 2;
2421 sh = 7 - bf;
2422 gen_optimize_fprf();
7c58044c 2423 gen_reset_fpstatus();
0f2f39c2 2424 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2425 t1 = tcg_const_i32(1 << sh);
2426 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2427 tcg_temp_free_i64(t0);
2428 tcg_temp_free_i32(t1);
7c58044c 2429 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2430 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2431 }
2432 /* We can raise a differed exception */
af12906f 2433 gen_helper_float_check_status();
79aceca5
FB		 2434}
2435
76a66253
JM		 2436/*** Addressing modes ***/
2437/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2438static always_inline void gen_addr_imm_index (TCGv EA,
2439 DisasContext *ctx,
b068d6a7 2440 target_long maskl)
76a66253
JM		 2441{
2442 target_long simm = SIMM(ctx->opcode);
2443
be147d08 2444 simm &= ~maskl;
e2be8d8d
AJ		 2445 if (rA(ctx->opcode) == 0)
2446 tcg_gen_movi_tl(EA, simm);
2447 else if (likely(simm != 0))
2448 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2449 else
2450 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2451}
2452
e2be8d8d
AJ		 2453static always_inline void gen_addr_reg_index (TCGv EA,
2454 DisasContext *ctx)
76a66253 2455{
e2be8d8d
AJ		 2456 if (rA(ctx->opcode) == 0)
2457 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2458 else
2459 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2460}
2461
e2be8d8d
AJ		 2462static always_inline void gen_addr_register (TCGv EA,
2463 DisasContext *ctx)
76a66253 2464{
e2be8d8d
AJ		 2465 if (rA(ctx->opcode) == 0)
2466 tcg_gen_movi_tl(EA, 0);
2467 else
2468 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2469}
2470
7863667f
JM		 2471#if defined(TARGET_PPC64)
2472#define _GEN_MEM_FUNCS(name, mode) \
2473 &gen_op_##name##_##mode, \
2474 &gen_op_##name##_le_##mode, \
2475 &gen_op_##name##_64_##mode, \
2476 &gen_op_##name##_le_64_##mode
2477#else
2478#define _GEN_MEM_FUNCS(name, mode) \
2479 &gen_op_##name##_##mode, \
2480 &gen_op_##name##_le_##mode
2481#endif
9a64fbe4 2482#if defined(CONFIG_USER_ONLY)
d9bce9d9 2483#if defined(TARGET_PPC64)
7863667f 2484#define NB_MEM_FUNCS 4
d9bce9d9 2485#else
7863667f 2486#define NB_MEM_FUNCS 2
d9bce9d9 2487#endif
7863667f
JM		 2488#define GEN_MEM_FUNCS(name) \
2489 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2490#else
d9bce9d9 2491#if defined(TARGET_PPC64)
7863667f 2492#define NB_MEM_FUNCS 12
2857068e 2493#else
7863667f 2494#define NB_MEM_FUNCS 6
2857068e 2495#endif
7863667f
JM		 2496#define GEN_MEM_FUNCS(name) \
2497 _GEN_MEM_FUNCS(name, user), \
2498 _GEN_MEM_FUNCS(name, kernel), \
2499 _GEN_MEM_FUNCS(name, hypv)
2500#endif
2501
2502/*** Integer load ***/
b61f2753
AJ		 2503#if defined(TARGET_PPC64)
2504#define GEN_QEMU_LD_PPC64(width) \
2505static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2506{ \
2507 if (likely(flags & 2)) \
2508 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2509 else { \
a7812ae4 2510 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2511 tcg_gen_ext32u_tl(addr, t1); \
2512 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2513 tcg_temp_free(addr); \
2514 } \
2515}
2516GEN_QEMU_LD_PPC64(8u)
2517GEN_QEMU_LD_PPC64(8s)
2518GEN_QEMU_LD_PPC64(16u)
2519GEN_QEMU_LD_PPC64(16s)
2520GEN_QEMU_LD_PPC64(32u)
2521GEN_QEMU_LD_PPC64(32s)
2522GEN_QEMU_LD_PPC64(64)
2523
2524#define GEN_QEMU_ST_PPC64(width) \
2525static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2526{ \
2527 if (likely(flags & 2)) \
2528 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2529 else { \
a7812ae4 2530 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2531 tcg_gen_ext32u_tl(addr, t1); \
2532 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2533 tcg_temp_free(addr); \
2534 } \
2535}
2536GEN_QEMU_ST_PPC64(8)
2537GEN_QEMU_ST_PPC64(16)
2538GEN_QEMU_ST_PPC64(32)
2539GEN_QEMU_ST_PPC64(64)
2540
ea363694 2541static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2542{
ea363694 2543 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2544}
2545
ea363694 2546static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2547{
ea363694 2548 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2549}
2550
ea363694 2551static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2552{
2553 if (unlikely(flags & 1)) {
a7812ae4 2554 TCGv_i32 t0;
ea363694 2555 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2556 t0 = tcg_temp_new_i32();
ea363694
AJ		 2557 tcg_gen_trunc_tl_i32(t0, arg0);
2558 tcg_gen_bswap16_i32(t0, t0);
2559 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2560 tcg_temp_free_i32(t0);
b61f2753 2561 } else
ea363694 2562 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2563}
2564
ea363694 2565static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2566{
2567 if (unlikely(flags & 1)) {
a7812ae4 2568 TCGv_i32 t0;
ea363694 2569 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2570 t0 = tcg_temp_new_i32();
ea363694
AJ		 2571 tcg_gen_trunc_tl_i32(t0, arg0);
2572 tcg_gen_bswap16_i32(t0, t0);
2573 tcg_gen_extu_i32_tl(arg0, t0);
2574 tcg_gen_ext16s_tl(arg0, arg0);
a7812ae4 2575 tcg_temp_free_i32(t0);
b61f2753 2576 } else
ea363694 2577 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2578}
2579
ea363694 2580static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2581{
2582 if (unlikely(flags & 1)) {
a7812ae4 2583 TCGv_i32 t0;
ea363694 2584 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2585 t0 = tcg_temp_new_i32();
ea363694
AJ		 2586 tcg_gen_trunc_tl_i32(t0, arg0);
2587 tcg_gen_bswap_i32(t0, t0);
2588 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2589 tcg_temp_free_i32(t0);
b61f2753 2590 } else
ea363694 2591 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2592}
2593
ea363694 2594static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2595{
2596 if (unlikely(flags & 1)) {
a7812ae4 2597 TCGv_i32 t0;
ea363694 2598 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2599 t0 = tcg_temp_new_i32();
ea363694
AJ		 2600 tcg_gen_trunc_tl_i32(t0, arg0);
2601 tcg_gen_bswap_i32(t0, t0);
2602 tcg_gen_ext_i32_tl(arg0, t0);
a7812ae4 2603 tcg_temp_free_i32(t0);
b61f2753 2604 } else
ea363694 2605 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2606}
2607
ea363694 2608static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2609{
ea363694 2610 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2611 if (unlikely(flags & 1))
ea363694 2612 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2613}
2614
ea363694 2615static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2616{
ea363694 2617 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2618}
2619
ea363694 2620static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2621{
2622 if (unlikely(flags & 1)) {
a7812ae4
PB		 2623 TCGv_i32 t0;
2624 TCGv_i64 t1;
2625 t0 = tcg_temp_new_i32();
ea363694
AJ		 2626 tcg_gen_trunc_tl_i32(t0, arg0);
2627 tcg_gen_ext16u_i32(t0, t0);
2628 tcg_gen_bswap16_i32(t0, t0);
a7812ae4 2629 t1 = tcg_temp_new_i64();
ea363694 2630 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2631 tcg_temp_free_i32(t0);
ea363694 2632 gen_qemu_st16_ppc64(t1, arg1, flags);
a7812ae4 2633 tcg_temp_free_i64(t1);
b61f2753 2634 } else
ea363694 2635 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2636}
2637
ea363694 2638static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2639{
2640 if (unlikely(flags & 1)) {
a7812ae4
PB		 2641 TCGv_i32 t0;
2642 TCGv_i64 t1;
2643 t0 = tcg_temp_new_i32();
ea363694
AJ		 2644 tcg_gen_trunc_tl_i32(t0, arg0);
2645 tcg_gen_bswap_i32(t0, t0);
a7812ae4 2646 t1 = tcg_temp_new_i64();
ea363694 2647 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2648 tcg_temp_free_i32(t0);
ea363694 2649 gen_qemu_st32_ppc64(t1, arg1, flags);
a7812ae4 2650 tcg_temp_free_i64(t1);
b61f2753 2651 } else
ea363694 2652 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2653}
2654
ea363694 2655static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2656{
2657 if (unlikely(flags & 1)) {
a7812ae4 2658 TCGv_i64 t0 = tcg_temp_new_i64();
ea363694
AJ		 2659 tcg_gen_bswap_i64(t0, arg0);
2660 gen_qemu_st64_ppc64(t0, arg1, flags);
a7812ae4 2661 tcg_temp_free_i64(t0);
b61f2753 2662 } else
ea363694 2663 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2664}
2665
2666
2667#else /* defined(TARGET_PPC64) */
a0d7d5a7
AJ		 2668#define GEN_QEMU_LD_PPC32(width) \
2669static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2670{ \
2671 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2672}
2673GEN_QEMU_LD_PPC32(8u)
2674GEN_QEMU_LD_PPC32(8s)
2675GEN_QEMU_LD_PPC32(16u)
2676GEN_QEMU_LD_PPC32(16s)
2677GEN_QEMU_LD_PPC32(32u)
2678GEN_QEMU_LD_PPC32(32s)
a0d7d5a7
AJ		 2679static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2680{
2681 tcg_gen_qemu_ld64(arg0, arg1, flags >> 1);
2682}
b61f2753 2683
a0d7d5a7
AJ		 2684#define GEN_QEMU_ST_PPC32(width) \
2685static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2686{ \
2687 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2688}
2689GEN_QEMU_ST_PPC32(8)
2690GEN_QEMU_ST_PPC32(16)
2691GEN_QEMU_ST_PPC32(32)
a0d7d5a7
AJ		 2692static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2693{
2694 tcg_gen_qemu_st64(arg0, arg1, flags >> 1);
2695}
b61f2753 2696
ea363694 2697static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2698{
ea363694 2699 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2700}
2701
ea363694 2702static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2703{
ea363694 2704 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2705}
2706
ea363694 2707static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2708{
ea363694 2709 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2710 if (unlikely(flags & 1))
ea363694 2711 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2712}
2713
ea363694 2714static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2715{
2716 if (unlikely(flags & 1)) {
ea363694
AJ		 2717 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2718 tcg_gen_bswap16_i32(arg0, arg0);
2719 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2720 } else
ea363694 2721 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2722}
2723
ea363694 2724static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2725{
ea363694 2726 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2727 if (unlikely(flags & 1))
ea363694 2728 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2729}
2730
a0d7d5a7
AJ		 2731static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags)
2732{
2733 gen_qemu_ld64_ppc32(arg0, arg1, flags);
2734 if (unlikely(flags & 1))
2735 tcg_gen_bswap_i64(arg0, arg0);
2736}
2737
ea363694 2738static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2739{
e32ad5c2 2740 gen_qemu_st8_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2741}
2742
ea363694 2743static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2744{
2745 if (unlikely(flags & 1)) {
a7812ae4 2746 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2747 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2748 tcg_gen_bswap16_i32(temp, temp);
e32ad5c2 2749 gen_qemu_st16_ppc32(temp, arg1, flags);
a7812ae4 2750 tcg_temp_free_i32(temp);
b61f2753 2751 } else
e32ad5c2 2752 gen_qemu_st16_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2753}
2754
ea363694 2755static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2756{
2757 if (unlikely(flags & 1)) {
a7812ae4 2758 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2759 tcg_gen_bswap_i32(temp, arg0);
e32ad5c2 2760 gen_qemu_st32_ppc32(temp, arg1, flags);
a7812ae4 2761 tcg_temp_free_i32(temp);
b61f2753 2762 } else
e32ad5c2 2763 gen_qemu_st32_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2764}
2765
a0d7d5a7
AJ		 2766static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags)
2767{
2768 if (unlikely(flags & 1)) {
2769 TCGv_i64 temp = tcg_temp_new_i64();
2770 tcg_gen_bswap_i64(temp, arg0);
2771 gen_qemu_st64_ppc32(temp, arg1, flags);
2772 tcg_temp_free_i64(temp);
2773 } else
2774 gen_qemu_st64_ppc32(arg0, arg1, flags);
2775}
b61f2753
AJ		 2776#endif
2777
0c8aacd4
AJ		 2778#define GEN_LD(name, ldop, opc, type) \
2779GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2780{ \
0c8aacd4 2781 TCGv EA = tcg_temp_new(); \
a7859e89 2782 gen_set_access_type(ACCESS_INT); \
b61f2753 2783 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2784 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2785 tcg_temp_free(EA); \
79aceca5
FB		 2786}
2787
0c8aacd4
AJ		 2788#define GEN_LDU(name, ldop, opc, type) \
2789GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2790{ \
b61f2753 2791 TCGv EA; \
76a66253
JM		 2792 if (unlikely(rA(ctx->opcode) == 0 || \
2793 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2794 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2795 return; \
9a64fbe4 2796 } \
0c8aacd4 2797 EA = tcg_temp_new(); \
a7859e89 2798 gen_set_access_type(ACCESS_INT); \
9d53c753 2799 if (type == PPC_64B) \
b61f2753 2800 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2801 else \
b61f2753 2802 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2803 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2805 tcg_temp_free(EA); \
79aceca5
FB		 2806}
2807
0c8aacd4
AJ		 2808#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2809GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2810{ \
b61f2753 2811 TCGv EA; \
76a66253
JM		 2812 if (unlikely(rA(ctx->opcode) == 0 || \
2813 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2814 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2815 return; \
9a64fbe4 2816 } \
0c8aacd4 2817 EA = tcg_temp_new(); \
a7859e89 2818 gen_set_access_type(ACCESS_INT); \
b61f2753 2819 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2820 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2822 tcg_temp_free(EA); \
79aceca5
FB		 2823}
2824
0c8aacd4
AJ		 2825#define GEN_LDX(name, ldop, opc2, opc3, type) \
2826GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2827{ \
0c8aacd4 2828 TCGv EA = tcg_temp_new(); \
a7859e89 2829 gen_set_access_type(ACCESS_INT); \
b61f2753 2830 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2831 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2832 tcg_temp_free(EA); \
79aceca5
FB		 2833}
2834
0c8aacd4
AJ		 2835#define GEN_LDS(name, ldop, op, type) \
2836GEN_LD(name, ldop, op | 0x20, type); \
2837GEN_LDU(name, ldop, op | 0x21, type); \
2838GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2839GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2840
2841/* lbz lbzu lbzux lbzx */
0c8aacd4 2842GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2843/* lha lhau lhaux lhax */
0c8aacd4 2844GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2845/* lhz lhzu lhzux lhzx */
0c8aacd4 2846GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2847/* lwz lwzu lwzux lwzx */
0c8aacd4 2848GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2849#if defined(TARGET_PPC64)
d9bce9d9 2850/* lwaux */
0c8aacd4 2851GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2852/* lwax */
0c8aacd4 2853GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2854/* ldux */
0c8aacd4 2855GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2856/* ldx */
0c8aacd4 2857GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2858GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2859{
b61f2753 2860 TCGv EA;
d9bce9d9
JM		 2861 if (Rc(ctx->opcode)) {
2862 if (unlikely(rA(ctx->opcode) == 0 ||
2863 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2864 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2865 return;
2866 }
2867 }
a7812ae4 2868 EA = tcg_temp_new();
a7859e89 2869 gen_set_access_type(ACCESS_INT);
b61f2753 2870 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2871 if (ctx->opcode & 0x02) {
2872 /* lwa (lwau is undefined) */
b61f2753 2873 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2874 } else {
2875 /* ld - ldu */
b61f2753 2876 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2877 }
d9bce9d9 2878 if (Rc(ctx->opcode))
b61f2753
AJ		 2879 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2880 tcg_temp_free(EA);
d9bce9d9 2881}
be147d08
JM		 2882/* lq */
2883GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2884{
2885#if defined(CONFIG_USER_ONLY)
2886 GEN_EXCP_PRIVOPC(ctx);
2887#else
2888 int ra, rd;
b61f2753 2889 TCGv EA;
be147d08
JM		 2890
2891 /* Restore CPU state */
2892 if (unlikely(ctx->supervisor == 0)) {
2893 GEN_EXCP_PRIVOPC(ctx);
2894 return;
2895 }
2896 ra = rA(ctx->opcode);
2897 rd = rD(ctx->opcode);
2898 if (unlikely((rd & 1) || rd == ra)) {
2899 GEN_EXCP_INVAL(ctx);
2900 return;
2901 }
2902 if (unlikely(ctx->mem_idx & 1)) {
2903 /* Little-endian mode is not handled */
2904 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2905 return;
2906 }
a7812ae4 2907 EA = tcg_temp_new();
a7859e89 2908 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 2909 gen_addr_imm_index(EA, ctx, 0x0F);
2910 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2911 tcg_gen_addi_tl(EA, EA, 8);
2912 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2913 tcg_temp_free(EA);
be147d08
JM		 2914#endif
2915}
d9bce9d9 2916#endif
79aceca5
FB		 2917
2918/*** Integer store ***/
0c8aacd4
AJ		 2919#define GEN_ST(name, stop, opc, type) \
2920GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2921{ \
0c8aacd4 2922 TCGv EA = tcg_temp_new(); \
a7859e89 2923 gen_set_access_type(ACCESS_INT); \
b61f2753 2924 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2925 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2926 tcg_temp_free(EA); \
79aceca5
FB		 2927}
2928
0c8aacd4
AJ		 2929#define GEN_STU(name, stop, opc, type) \
2930GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2931{ \
b61f2753 2932 TCGv EA; \
76a66253 2933 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2934 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2935 return; \
9a64fbe4 2936 } \
0c8aacd4 2937 EA = tcg_temp_new(); \
a7859e89 2938 gen_set_access_type(ACCESS_INT); \
9d53c753 2939 if (type == PPC_64B) \
b61f2753 2940 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2941 else \
b61f2753 2942 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2943 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2944 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2945 tcg_temp_free(EA); \
79aceca5
FB		 2946}
2947
0c8aacd4
AJ		 2948#define GEN_STUX(name, stop, opc2, opc3, type) \
2949GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2950{ \
b61f2753 2951 TCGv EA; \
76a66253 2952 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2953 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2954 return; \
9a64fbe4 2955 } \
0c8aacd4 2956 EA = tcg_temp_new(); \
a7859e89 2957 gen_set_access_type(ACCESS_INT); \
b61f2753 2958 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2959 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2960 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2961 tcg_temp_free(EA); \
79aceca5
FB		 2962}
2963
0c8aacd4
AJ		 2964#define GEN_STX(name, stop, opc2, opc3, type) \
2965GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2966{ \
0c8aacd4 2967 TCGv EA = tcg_temp_new(); \
a7859e89 2968 gen_set_access_type(ACCESS_INT); \
b61f2753 2969 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2970 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2971 tcg_temp_free(EA); \
79aceca5
FB		 2972}
2973
0c8aacd4
AJ		 2974#define GEN_STS(name, stop, op, type) \
2975GEN_ST(name, stop, op | 0x20, type); \
2976GEN_STU(name, stop, op | 0x21, type); \
2977GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2978GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2979
2980/* stb stbu stbux stbx */
0c8aacd4 2981GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2982/* sth sthu sthux sthx */
0c8aacd4 2983GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2984/* stw stwu stwux stwx */
0c8aacd4 2985GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2986#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2987GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2988GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2989GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2990{
be147d08 2991 int rs;
b61f2753 2992 TCGv EA;
be147d08
JM		 2993
2994 rs = rS(ctx->opcode);
2995 if ((ctx->opcode & 0x3) == 0x2) {
2996#if defined(CONFIG_USER_ONLY)
2997 GEN_EXCP_PRIVOPC(ctx);
2998#else
2999 /* stq */
3000 if (unlikely(ctx->supervisor == 0)) {
3001 GEN_EXCP_PRIVOPC(ctx);
3002 return;
3003 }
3004 if (unlikely(rs & 1)) {
e1833e1f 3005 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 3006 return;
3007 }
be147d08
JM		 3008 if (unlikely(ctx->mem_idx & 1)) {
3009 /* Little-endian mode is not handled */
3010 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3011 return;
3012 }
a7812ae4 3013 EA = tcg_temp_new();
a7859e89 3014 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3015 gen_addr_imm_index(EA, ctx, 0x03);
3016 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3017 tcg_gen_addi_tl(EA, EA, 8);
3018 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3019 tcg_temp_free(EA);
be147d08
JM		 3020#endif
3021 } else {
3022 /* std / stdu */
3023 if (Rc(ctx->opcode)) {
3024 if (unlikely(rA(ctx->opcode) == 0)) {
3025 GEN_EXCP_INVAL(ctx);
3026 return;
3027 }
3028 }
a7812ae4 3029 EA = tcg_temp_new();
a7859e89 3030 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3031 gen_addr_imm_index(EA, ctx, 0x03);
3032 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 3033 if (Rc(ctx->opcode))
b61f2753
AJ		 3034 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3035 tcg_temp_free(EA);
d9bce9d9 3036 }
d9bce9d9
JM		 3037}
3038#endif
79aceca5
FB		 3039/*** Integer load and store with byte reverse ***/
3040/* lhbrx */
b61f2753
AJ		 3041void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3042{
a7812ae4
PB		 3043 TCGv_i32 temp = tcg_temp_new_i32();
3044 gen_qemu_ld16u(t0, t1, flags);
3045 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3046 tcg_gen_bswap16_i32(temp, temp);
3047 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3048 tcg_temp_free_i32(temp);
b61f2753 3049}
0c8aacd4 3050GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3051
79aceca5 3052/* lwbrx */
b61f2753
AJ		 3053void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3054{
a7812ae4
PB		 3055 TCGv_i32 temp = tcg_temp_new_i32();
3056 gen_qemu_ld32u(t0, t1, flags);
3057 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3058 tcg_gen_bswap_i32(temp, temp);
3059 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3060 tcg_temp_free_i32(temp);
b61f2753 3061}
0c8aacd4 3062GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3063
79aceca5 3064/* sthbrx */
b61f2753
AJ		 3065void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3066{
a7812ae4
PB		 3067 TCGv_i32 temp = tcg_temp_new_i32();
3068 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3069 tcg_gen_trunc_tl_i32(temp, t0);
3070 tcg_gen_ext16u_i32(temp, temp);
3071 tcg_gen_bswap16_i32(temp, temp);
a7812ae4
PB		 3072 tcg_gen_extu_i32_tl(t2, temp);
3073 tcg_temp_free_i32(temp);
3074 gen_qemu_st16(t2, t1, flags);
3075 tcg_temp_free(t2);
b61f2753 3076}
0c8aacd4 3077GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3078
79aceca5 3079/* stwbrx */
b61f2753
AJ		 3080void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3081{
a7812ae4
PB		 3082 TCGv_i32 temp = tcg_temp_new_i32();
3083 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3084 tcg_gen_trunc_tl_i32(temp, t0);
3085 tcg_gen_bswap_i32(temp, temp);
a7812ae4
PB		 3086 tcg_gen_extu_i32_tl(t2, temp);
3087 tcg_temp_free_i32(temp);
87006d13 3088 gen_qemu_st32(t2, t1, flags);
a7812ae4 3089 tcg_temp_free(t2);
b61f2753 3090}
0c8aacd4 3091GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3092
3093/*** Integer load and store multiple ***/
3094/* lmw */
3095GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3096{
ff4a62cd
AJ		 3097 TCGv t0 = tcg_temp_new();
3098 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
76a66253 3099 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3100 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3101 gen_addr_imm_index(t0, ctx, 0);
3102 gen_helper_lmw(t0, t1);
3103 tcg_temp_free(t0);
3104 tcg_temp_free_i32(t1);
79aceca5
FB		 3105}
3106
3107/* stmw */
3108GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3109{
ff4a62cd
AJ		 3110 TCGv t0 = tcg_temp_new();
3111 TCGv_i32 t1 = tcg_const_i32(rS(ctx->opcode));
76a66253 3112 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3113 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3114 gen_addr_imm_index(t0, ctx, 0);
3115 gen_helper_stmw(t0, t1);
3116 tcg_temp_free(t0);
3117 tcg_temp_free_i32(t1);
79aceca5
FB		 3118}
3119
3120/*** Integer load and store strings ***/
3121/* lswi */
3fc6c082 3122/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3123 * rA is in the range of registers to be loaded.
3124 * In an other hand, IBM says this is valid, but rA won't be loaded.
3125 * For now, I'll follow the spec...
3126 */
05332d70 3127GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3128{
dfbc799d
AJ		 3129 TCGv t0;
3130 TCGv_i32 t1, t2;
79aceca5
FB		 3131 int nb = NB(ctx->opcode);
3132 int start = rD(ctx->opcode);
9a64fbe4 3133 int ra = rA(ctx->opcode);
79aceca5
FB		 3134 int nr;
3135
3136 if (nb == 0)
3137 nb = 32;
3138 nr = nb / 4;
76a66253
JM		 3139 if (unlikely(((start + nr) > 32 &&
3140 start <= ra && (start + nr - 32) > ra) ||
3141 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3142 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3143 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3144 return;
297d8e62 3145 }
8dd4983c 3146 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3147 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3148 t0 = tcg_temp_new();
3149 gen_addr_register(t0, ctx);
3150 t1 = tcg_const_i32(nb);
3151 t2 = tcg_const_i32(start);
3152 gen_helper_lsw(t0, t1, t2);
3153 tcg_temp_free(t0);
3154 tcg_temp_free_i32(t1);
3155 tcg_temp_free_i32(t2);
79aceca5
FB		 3156}
3157
3158/* lswx */
05332d70 3159GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3160{
dfbc799d
AJ		 3161 TCGv t0 = tcg_temp_new();
3162 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
3163 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
3164 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 3165 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3166 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3167 gen_addr_reg_index(t0, ctx);
3168 gen_helper_lswx(t0, t1, t2, t3);
3169 tcg_temp_free(t0);
3170 tcg_temp_free_i32(t1);
3171 tcg_temp_free_i32(t2);
3172 tcg_temp_free_i32(t3);
79aceca5
FB		 3173}
3174
3175/* stswi */
05332d70 3176GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3177{
4b3686fa 3178 int nb = NB(ctx->opcode);
dfbc799d
AJ		 3179 TCGv t0 = tcg_temp_new();
3180 TCGv_i32 t1;
3181 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
76a66253 3182 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3183 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3184 gen_addr_register(t0, ctx);
4b3686fa
FB		 3185 if (nb == 0)
3186 nb = 32;
dfbc799d
AJ		 3187 t1 = tcg_const_i32(nb);
3188 gen_helper_stsw(t0, t1, t2);
3189 tcg_temp_free(t0);
3190 tcg_temp_free_i32(t1);
3191 tcg_temp_free_i32(t2);
79aceca5
FB		 3192}
3193
3194/* stswx */
05332d70 3195GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3196{
dfbc799d
AJ		 3197 TCGv t0 = tcg_temp_new();
3198 TCGv_i32 t1 = tcg_temp_new_i32();
3199 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
8dd4983c 3200 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3201 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3202 gen_addr_reg_index(t0, ctx);
3203 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3204 tcg_gen_andi_i32(t1, t1, 0x7F);
3205 gen_helper_stsw(t0, t1, t2);
3206 tcg_temp_free(t0);
3207 tcg_temp_free_i32(t1);
3208 tcg_temp_free_i32(t2);
79aceca5
FB		 3209}
3210
3211/*** Memory synchronisation ***/
3212/* eieio */
0db1b20e 3213GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3214{
79aceca5
FB		 3215}
3216
3217/* isync */
0db1b20e 3218GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3219{
e1833e1f 3220 GEN_STOP(ctx);
79aceca5
FB		 3221}
3222
111bfab3
FB		 3223#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3224#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 3225static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3226 GEN_MEM_FUNCS(lwarx),
111bfab3 3227};
7863667f
JM		 3228static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3229 GEN_MEM_FUNCS(stwcx),
985a19d6 3230};
9a64fbe4 3231
111bfab3 3232/* lwarx */
76a66253 3233GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3234{
30032c94
JM		 3235 /* NIP cannot be restored if the memory exception comes from an helper */
3236 gen_update_nip(ctx, ctx->nip - 4);
a7859e89 3237 gen_set_access_type(ACCESS_RES);
e2be8d8d 3238 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 3239 op_lwarx();
f78fb44e 3240 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 3241}
3242
3243/* stwcx. */
c7697e1f 3244GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3245{
30032c94
JM		 3246 /* NIP cannot be restored if the memory exception comes from an helper */
3247 gen_update_nip(ctx, ctx->nip - 4);
a7859e89 3248 gen_set_access_type(ACCESS_RES);
e2be8d8d 3249 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3250 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 3251 op_stwcx();
79aceca5
FB		 3252}
3253
426613db
JM		 3254#if defined(TARGET_PPC64)
3255#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3256#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 3257static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3258 GEN_MEM_FUNCS(ldarx),
426613db 3259};
7863667f
JM		 3260static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3261 GEN_MEM_FUNCS(stdcx),
426613db 3262};
426613db
JM		 3263
3264/* ldarx */
a750fc0b 3265GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3266{
30032c94
JM		 3267 /* NIP cannot be restored if the memory exception comes from an helper */
3268 gen_update_nip(ctx, ctx->nip - 4);
a7859e89 3269 gen_set_access_type(ACCESS_RES);
e2be8d8d 3270 gen_addr_reg_index(cpu_T[0], ctx);
426613db 3271 op_ldarx();
f78fb44e 3272 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 3273}
3274
3275/* stdcx. */
c7697e1f 3276GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3277{
30032c94
JM		 3278 /* NIP cannot be restored if the memory exception comes from an helper */
3279 gen_update_nip(ctx, ctx->nip - 4);
a7859e89 3280 gen_set_access_type(ACCESS_RES);
e2be8d8d 3281 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3282 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 3283 op_stdcx();
3284}
3285#endif /* defined(TARGET_PPC64) */
3286
79aceca5 3287/* sync */
a902d886 3288GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3289{
79aceca5
FB		 3290}
3291
0db1b20e
JM		 3292/* wait */
3293GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3294{
931ff272
AJ		 3295 TCGv_i32 t0 = tcg_temp_new_i32();
3296 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3297 tcg_temp_free_i32(t0);
0db1b20e 3298 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08 3299 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3300}
3301
79aceca5 3302/*** Floating-point load ***/
a0d7d5a7
AJ		 3303#define GEN_LDF(name, ldop, opc, type) \
3304GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3305{ \
a0d7d5a7 3306 TCGv EA; \
76a66253 3307 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3308 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3309 return; \
3310 } \
a7859e89 3311 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3312 EA = tcg_temp_new(); \
3313 gen_addr_imm_index(EA, ctx, 0); \
3314 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3315 tcg_temp_free(EA); \
79aceca5
FB		 3316}
3317
a0d7d5a7
AJ		 3318#define GEN_LDUF(name, ldop, opc, type) \
3319GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3320{ \
a0d7d5a7 3321 TCGv EA; \
76a66253 3322 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3323 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3324 return; \
3325 } \
76a66253 3326 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3327 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3328 return; \
9a64fbe4 3329 } \
a7859e89 3330 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3331 EA = tcg_temp_new(); \
3332 gen_addr_imm_index(EA, ctx, 0); \
3333 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3334 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3335 tcg_temp_free(EA); \
79aceca5
FB		 3336}
3337
a0d7d5a7
AJ		 3338#define GEN_LDUXF(name, ldop, opc, type) \
3339GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3340{ \
a0d7d5a7 3341 TCGv EA; \
76a66253 3342 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3343 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3344 return; \
3345 } \
76a66253 3346 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3347 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3348 return; \
9a64fbe4 3349 } \
a7859e89 3350 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3351 EA = tcg_temp_new(); \
3352 gen_addr_reg_index(EA, ctx); \
3353 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3354 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3355 tcg_temp_free(EA); \
79aceca5
FB		 3356}
3357
a0d7d5a7
AJ		 3358#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3359GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3360{ \
a0d7d5a7 3361 TCGv EA; \
76a66253 3362 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3363 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3364 return; \
3365 } \
a7859e89 3366 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3367 EA = tcg_temp_new(); \
3368 gen_addr_reg_index(EA, ctx); \
3369 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3370 tcg_temp_free(EA); \
79aceca5
FB		 3371}
3372
a0d7d5a7
AJ		 3373#define GEN_LDFS(name, ldop, op, type) \
3374GEN_LDF(name, ldop, op | 0x20, type); \
3375GEN_LDUF(name, ldop, op | 0x21, type); \
3376GEN_LDUXF(name, ldop, op | 0x01, type); \
3377GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3378
3379static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3380{
3381 TCGv t0 = tcg_temp_new();
3382 TCGv_i32 t1 = tcg_temp_new_i32();
3383 gen_qemu_ld32u(t0, arg2, flags);
3384 tcg_gen_trunc_tl_i32(t1, t0);
3385 tcg_temp_free(t0);
3386 gen_helper_float32_to_float64(arg1, t1);
3387 tcg_temp_free_i32(t1);
3388}
79aceca5 3389
a0d7d5a7
AJ		 3390 /* lfd lfdu lfdux lfdx */
3391GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3392 /* lfs lfsu lfsux lfsx */
3393GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3394
3395/*** Floating-point store ***/
a0d7d5a7
AJ		 3396#define GEN_STF(name, stop, opc, type) \
3397GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3398{ \
a0d7d5a7 3399 TCGv EA; \
76a66253 3400 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3401 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3402 return; \
3403 } \
a7859e89 3404 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3405 EA = tcg_temp_new(); \
3406 gen_addr_imm_index(EA, ctx, 0); \
3407 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3408 tcg_temp_free(EA); \
79aceca5
FB		 3409}
3410
a0d7d5a7
AJ		 3411#define GEN_STUF(name, stop, opc, type) \
3412GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3413{ \
a0d7d5a7 3414 TCGv EA; \
76a66253 3415 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3416 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3417 return; \
3418 } \
76a66253 3419 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3420 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3421 return; \
9a64fbe4 3422 } \
a7859e89 3423 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3424 EA = tcg_temp_new(); \
3425 gen_addr_imm_index(EA, ctx, 0); \
3426 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3427 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3428 tcg_temp_free(EA); \
79aceca5
FB		 3429}
3430
a0d7d5a7
AJ		 3431#define GEN_STUXF(name, stop, opc, type) \
3432GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3433{ \
a0d7d5a7 3434 TCGv EA; \
76a66253 3435 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3436 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3437 return; \
3438 } \
76a66253 3439 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3440 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3441 return; \
9a64fbe4 3442 } \
a7859e89 3443 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3444 EA = tcg_temp_new(); \
3445 gen_addr_reg_index(EA, ctx); \
3446 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3447 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3448 tcg_temp_free(EA); \
79aceca5
FB		 3449}
3450
a0d7d5a7
AJ		 3451#define GEN_STXF(name, stop, opc2, opc3, type) \
3452GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3453{ \
a0d7d5a7 3454 TCGv EA; \
76a66253 3455 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3456 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3457 return; \
3458 } \
a7859e89 3459 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3460 EA = tcg_temp_new(); \
3461 gen_addr_reg_index(EA, ctx); \
3462 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3463 tcg_temp_free(EA); \
79aceca5
FB		 3464}
3465
a0d7d5a7
AJ		 3466#define GEN_STFS(name, stop, op, type) \
3467GEN_STF(name, stop, op | 0x20, type); \
3468GEN_STUF(name, stop, op | 0x21, type); \
3469GEN_STUXF(name, stop, op | 0x01, type); \
3470GEN_STXF(name, stop, 0x17, op | 0x00, type)
3471
3472static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3473{
3474 TCGv_i32 t0 = tcg_temp_new_i32();
3475 TCGv t1 = tcg_temp_new();
3476 gen_helper_float64_to_float32(t0, arg1);
3477 tcg_gen_extu_i32_tl(t1, t0);
3478 tcg_temp_free_i32(t0);
3479 gen_qemu_st32(t1, arg2, flags);
3480 tcg_temp_free(t1);
3481}
79aceca5
FB		 3482
3483/* stfd stfdu stfdux stfdx */
a0d7d5a7 3484GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3485/* stfs stfsu stfsux stfsx */
a0d7d5a7 3486GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3487
3488/* Optional: */
a0d7d5a7
AJ		 3489static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags)
3490{
3491 TCGv t0 = tcg_temp_new();
3492 tcg_gen_trunc_i64_tl(t0, arg1),
3493 gen_qemu_st32(t0, arg2, flags);
3494 tcg_temp_free(t0);
3495}
79aceca5 3496/* stfiwx */
a0d7d5a7 3497GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3498
3499/*** Branch ***/
b068d6a7
JM		 3500static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3501 target_ulong dest)
c1942362
FB		 3502{
3503 TranslationBlock *tb;
3504 tb = ctx->tb;
a2ffb812
AJ		 3505#if defined(TARGET_PPC64)
3506 if (!ctx->sf_mode)
3507 dest = (uint32_t) dest;
3508#endif
57fec1fe 3509 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3510 likely(!ctx->singlestep_enabled)) {
57fec1fe 3511 tcg_gen_goto_tb(n);
a2ffb812 3512 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3513 tcg_gen_exit_tb((long)tb + n);
c1942362 3514 } else {
a2ffb812 3515 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3516 if (unlikely(ctx->singlestep_enabled)) {
3517 if ((ctx->singlestep_enabled &
bdc4e053 3518 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3519 ctx->exception == POWERPC_EXCP_BRANCH) {
3520 target_ulong tmp = ctx->nip;
3521 ctx->nip = dest;
3522 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3523 ctx->nip = tmp;
3524 }
3525 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3526 gen_update_nip(ctx, dest);
64adab3f 3527 gen_helper_raise_debug();
8cbcb4fa
AJ		 3528 }
3529 }
57fec1fe 3530 tcg_gen_exit_tb(0);
c1942362 3531 }
c53be334
FB		 3532}
3533
b068d6a7 3534static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3535{
3536#if defined(TARGET_PPC64)
a2ffb812
AJ		 3537 if (ctx->sf_mode == 0)
3538 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3539 else
3540#endif
a2ffb812 3541 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3542}
3543
79aceca5
FB		 3544/* b ba bl bla */
3545GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3546{
76a66253 3547 target_ulong li, target;
38a64f9d 3548
8cbcb4fa 3549 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3550 /* sign extend LI */
76a66253 3551#if defined(TARGET_PPC64)
d9bce9d9
JM		 3552 if (ctx->sf_mode)
3553 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3554 else
76a66253 3555#endif
d9bce9d9 3556 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3557 if (likely(AA(ctx->opcode) == 0))
046d6672 3558 target = ctx->nip + li - 4;
79aceca5 3559 else
9a64fbe4 3560 target = li;
e1833e1f
JM		 3561 if (LK(ctx->opcode))
3562 gen_setlr(ctx, ctx->nip);
c1942362 3563 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3564}
3565
e98a6e40
FB		 3566#define BCOND_IM 0
3567#define BCOND_LR 1
3568#define BCOND_CTR 2
3569
b068d6a7 3570static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3571{
d9bce9d9 3572 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3573 int l1 = gen_new_label();
3574 TCGv target;
e98a6e40 3575
8cbcb4fa 3576 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3577 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3578 target = tcg_temp_local_new();
a2ffb812
AJ		 3579 if (type == BCOND_CTR)
3580 tcg_gen_mov_tl(target, cpu_ctr);
3581 else
3582 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3583 }
e1833e1f
JM		 3584 if (LK(ctx->opcode))
3585 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3586 l1 = gen_new_label();
3587 if ((bo & 0x4) == 0) {
3588 /* Decrement and test CTR */
a7812ae4 3589 TCGv temp = tcg_temp_new();
a2ffb812
AJ		 3590 if (unlikely(type == BCOND_CTR)) {
3591 GEN_EXCP_INVAL(ctx);
3592 return;
3593 }
3594 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3595#if defined(TARGET_PPC64)
a2ffb812
AJ		 3596 if (!ctx->sf_mode)
3597 tcg_gen_ext32u_tl(temp, cpu_ctr);
3598 else
d9bce9d9 3599#endif
a2ffb812
AJ		 3600 tcg_gen_mov_tl(temp, cpu_ctr);
3601 if (bo & 0x2) {
3602 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3603 } else {
3604 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3605 }
a7812ae4 3606 tcg_temp_free(temp);
a2ffb812
AJ		 3607 }
3608 if ((bo & 0x10) == 0) {
3609 /* Test CR */
3610 uint32_t bi = BI(ctx->opcode);
3611 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3612 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3613
d9bce9d9 3614 if (bo & 0x8) {
a2ffb812
AJ		 3615 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3616 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3617 } else {
a2ffb812
AJ		 3618 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3619 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3620 }
a7812ae4 3621 tcg_temp_free_i32(temp);
d9bce9d9 3622 }
e98a6e40 3623 if (type == BCOND_IM) {
a2ffb812
AJ		 3624 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3625 if (likely(AA(ctx->opcode) == 0)) {
3626 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3627 } else {
3628 gen_goto_tb(ctx, 0, li);
3629 }
c53be334 3630 gen_set_label(l1);
c1942362 3631 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3632 } else {
d9bce9d9 3633#if defined(TARGET_PPC64)
a2ffb812
AJ		 3634 if (!(ctx->sf_mode))
3635 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3636 else
3637#endif
3638 tcg_gen_andi_tl(cpu_nip, target, ~3);
3639 tcg_gen_exit_tb(0);
3640 gen_set_label(l1);
3641#if defined(TARGET_PPC64)
3642 if (!(ctx->sf_mode))
3643 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3644 else
3645#endif
a2ffb812 3646 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3647 tcg_gen_exit_tb(0);
08e46e54 3648 }
e98a6e40
FB		 3649}
3650
3651GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3652{
e98a6e40
FB		 3653 gen_bcond(ctx, BCOND_IM);
3654}
3655
3656GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3657{
e98a6e40
FB		 3658 gen_bcond(ctx, BCOND_CTR);
3659}
3660
3661GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3662{
e98a6e40
FB		 3663 gen_bcond(ctx, BCOND_LR);
3664}
79aceca5
FB		 3665
3666/*** Condition register logical ***/
e1571908
AJ		 3667#define GEN_CRLOGIC(name, tcg_op, opc) \
3668GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3669{ \
fc0d441e
JM		 3670 uint8_t bitmask; \
3671 int sh; \
a7812ae4 3672 TCGv_i32 t0, t1; \
fc0d441e 3673 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3674 t0 = tcg_temp_new_i32(); \
fc0d441e 3675 if (sh > 0) \
fea0c503 3676 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3677 else if (sh < 0) \
fea0c503 3678 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3679 else \
fea0c503 3680 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3681 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3682 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3683 if (sh > 0) \
fea0c503 3684 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3685 else if (sh < 0) \
fea0c503 3686 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3687 else \
fea0c503
AJ		 3688 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3689 tcg_op(t0, t0, t1); \
fc0d441e 3690 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3691 tcg_gen_andi_i32(t0, t0, bitmask); \
3692 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3693 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3694 tcg_temp_free_i32(t0); \
3695 tcg_temp_free_i32(t1); \
79aceca5
FB		 3696}
3697
3698/* crand */
e1571908 3699GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3700/* crandc */
e1571908 3701GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3702/* creqv */
e1571908 3703GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3704/* crnand */
e1571908 3705GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3706/* crnor */
e1571908 3707GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3708/* cror */
e1571908 3709GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3710/* crorc */
e1571908 3711GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3712/* crxor */
e1571908 3713GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3714/* mcrf */
3715GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3716{
47e4661c 3717 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3718}
3719
3720/*** System linkage ***/
3721/* rfi (supervisor only) */
76a66253 3722GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3723{
9a64fbe4 3724#if defined(CONFIG_USER_ONLY)
e1833e1f 3725 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3726#else
3727 /* Restore CPU state */
76a66253 3728 if (unlikely(!ctx->supervisor)) {
e1833e1f 3729 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3730 return;
9a64fbe4 3731 }
a42bd6cc 3732 gen_op_rfi();
e1833e1f 3733 GEN_SYNC(ctx);
9a64fbe4 3734#endif
79aceca5
FB		 3735}
3736
426613db 3737#if defined(TARGET_PPC64)
a750fc0b 3738GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3739{
3740#if defined(CONFIG_USER_ONLY)
e1833e1f 3741 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3742#else
3743 /* Restore CPU state */
3744 if (unlikely(!ctx->supervisor)) {
e1833e1f 3745 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3746 return;
3747 }
a42bd6cc 3748 gen_op_rfid();
e1833e1f 3749 GEN_SYNC(ctx);
426613db
JM		 3750#endif
3751}
426613db 3752
5b8105fa 3753GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3754{
3755#if defined(CONFIG_USER_ONLY)
3756 GEN_EXCP_PRIVOPC(ctx);
3757#else
3758 /* Restore CPU state */
3759 if (unlikely(ctx->supervisor <= 1)) {
3760 GEN_EXCP_PRIVOPC(ctx);
3761 return;
3762 }
3763 gen_op_hrfid();
3764 GEN_SYNC(ctx);
3765#endif
3766}
3767#endif
3768
79aceca5 3769/* sc */
417bf010
JM		 3770#if defined(CONFIG_USER_ONLY)
3771#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3772#else
3773#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3774#endif
e1833e1f 3775GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3776{
e1833e1f
JM		 3777 uint32_t lev;
3778
3779 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3780 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3781}
3782
3783/*** Trap ***/
3784/* tw */
76a66253 3785GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3786{
cab3bee2 3787 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3788 /* Update the nip since this might generate a trap exception */
d9bce9d9 3789 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3790 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3791 tcg_temp_free_i32(t0);
79aceca5
FB		 3792}
3793
3794/* twi */
3795GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3796{
cab3bee2
AJ		 3797 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3798 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3799 /* Update the nip since this might generate a trap exception */
3800 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3801 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3802 tcg_temp_free(t0);
3803 tcg_temp_free_i32(t1);
79aceca5
FB		 3804}
3805
d9bce9d9
JM		 3806#if defined(TARGET_PPC64)
3807/* td */
3808GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3809{
cab3bee2 3810 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3811 /* Update the nip since this might generate a trap exception */
3812 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3813 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3814 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3815}
3816
3817/* tdi */
3818GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3819{
cab3bee2
AJ		 3820 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3821 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3822 /* Update the nip since this might generate a trap exception */
3823 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3824 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3825 tcg_temp_free(t0);
3826 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3827}
3828#endif
3829
79aceca5 3830/*** Processor control ***/
79aceca5
FB		 3831/* mcrxr */
3832GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3833{
3d7b417e
AJ		 3834 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3835 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3836 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3837}
3838
3839/* mfcr */
76a66253 3840GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3841{
76a66253 3842 uint32_t crm, crn;
3b46e624 3843
76a66253
JM		 3844 if (likely(ctx->opcode & 0x00100000)) {
3845 crm = CRM(ctx->opcode);
3846 if (likely((crm ^ (crm - 1)) == 0)) {
3847 crn = ffs(crm);
e1571908 3848 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3849 }
d9bce9d9 3850 } else {
a7812ae4 3851 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3852 }
79aceca5
FB		 3853}
3854
3855/* mfmsr */
3856GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3857{
9a64fbe4 3858#if defined(CONFIG_USER_ONLY)
e1833e1f 3859 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3860#else
76a66253 3861 if (unlikely(!ctx->supervisor)) {
e1833e1f 3862 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3863 return;
9a64fbe4 3864 }
6676f424 3865 gen_op_load_msr();
f78fb44e 3866 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3867#endif
79aceca5
FB		 3868}
3869
a11b8151 3870#if 1
6f2d8978 3871#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3872#else
3873static void spr_noaccess (void *opaque, int sprn)
3874{
3875 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3876 printf("ERROR: try to access SPR %d !\n", sprn);
3877}
3878#define SPR_NOACCESS (&spr_noaccess)
3879#endif
3880
79aceca5 3881/* mfspr */
b068d6a7 3882static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3883{
3fc6c082 3884 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3885 uint32_t sprn = SPR(ctx->opcode);
3886
3fc6c082 3887#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3888 if (ctx->supervisor == 2)
3889 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3890 else if (ctx->supervisor)
3fc6c082
FB		 3891 read_cb = ctx->spr_cb[sprn].oea_read;
3892 else
9a64fbe4 3893#endif
3fc6c082 3894 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3895 if (likely(read_cb != NULL)) {
3896 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3897 (*read_cb)(ctx, sprn);
f78fb44e 3898 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3899 } else {
3900 /* Privilege exception */
9fceefa7
JM		 3901 /* This is a hack to avoid warnings when running Linux:
3902 * this OS breaks the PowerPC virtualisation model,
3903 * allowing userland application to read the PVR
3904 */
3905 if (sprn != SPR_PVR) {
3906 if (loglevel != 0) {
6b542af7 3907 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3908 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3909 }
077fc206
JM		 3910 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3911 sprn, sprn, ctx->nip);
f24e5695 3912 }
e1833e1f 3913 GEN_EXCP_PRIVREG(ctx);
79aceca5 3914 }
3fc6c082
FB		 3915 } else {
3916 /* Not defined */
4a057712 3917 if (loglevel != 0) {
077fc206
JM		 3918 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3919 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3920 }
077fc206
JM		 3921 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3922 sprn, sprn, ctx->nip);
e1833e1f
JM		 3923 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3924 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3925 }
79aceca5
FB		 3926}
3927
3fc6c082 3928GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3929{
3fc6c082 3930 gen_op_mfspr(ctx);
76a66253 3931}
3fc6c082
FB		 3932
3933/* mftb */
a750fc0b 3934GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3935{
3936 gen_op_mfspr(ctx);
79aceca5
FB		 3937}
3938
3939/* mtcrf */
8dd4983c 3940GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3941{
76a66253 3942 uint32_t crm, crn;
3b46e624 3943
76a66253
JM		 3944 crm = CRM(ctx->opcode);
3945 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3946 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3947 crn = ffs(crm);
a7812ae4
PB		 3948 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3949 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3950 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3951 tcg_temp_free_i32(temp);
76a66253 3952 } else {
a7812ae4
PB		 3953 TCGv_i32 temp = tcg_const_i32(crm);
3954 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3955 tcg_temp_free_i32(temp);
76a66253 3956 }
79aceca5
FB		 3957}
3958
3959/* mtmsr */
426613db 3960#if defined(TARGET_PPC64)
be147d08 3961GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3962{
3963#if defined(CONFIG_USER_ONLY)
e1833e1f 3964 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3965#else
3966 if (unlikely(!ctx->supervisor)) {
e1833e1f 3967 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3968 return;
3969 }
f78fb44e 3970 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3971 if (ctx->opcode & 0x00010000) {
3972 /* Special form that does not need any synchronisation */
3973 gen_op_update_riee();
3974 } else {
056b05f8
JM		 3975 /* XXX: we need to update nip before the store
3976 * if we enter power saving mode, we will exit the loop
3977 * directly from ppc_store_msr
3978 */
be147d08 3979 gen_update_nip(ctx, ctx->nip);
6676f424 3980 gen_op_store_msr();
be147d08
JM		 3981 /* Must stop the translation as machine state (may have) changed */
3982 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3983 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3984 }
426613db
JM		 3985#endif
3986}
3987#endif
3988
79aceca5
FB		 3989GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3990{
9a64fbe4 3991#if defined(CONFIG_USER_ONLY)
e1833e1f 3992 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3993#else
76a66253 3994 if (unlikely(!ctx->supervisor)) {
e1833e1f 3995 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3996 return;
9a64fbe4 3997 }
f78fb44e 3998 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3999 if (ctx->opcode & 0x00010000) {
4000 /* Special form that does not need any synchronisation */
4001 gen_op_update_riee();
4002 } else {
056b05f8
JM		 4003 /* XXX: we need to update nip before the store
4004 * if we enter power saving mode, we will exit the loop
4005 * directly from ppc_store_msr
4006 */
be147d08 4007 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4008#if defined(TARGET_PPC64)
be147d08 4009 if (!ctx->sf_mode)
6676f424 4010 gen_op_store_msr_32();
be147d08 4011 else
d9bce9d9 4012#endif
6676f424 4013 gen_op_store_msr();
be147d08
JM		 4014 /* Must stop the translation as machine state (may have) changed */
4015 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 4016 ctx->exception = POWERPC_EXCP_STOP;
be147d08 4017 }
9a64fbe4 4018#endif
79aceca5
FB		 4019}
4020
4021/* mtspr */
4022GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4023{
3fc6c082 4024 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 4025 uint32_t sprn = SPR(ctx->opcode);
4026
3fc6c082 4027#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 4028 if (ctx->supervisor == 2)
4029 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 4030 else if (ctx->supervisor)
3fc6c082
FB		 4031 write_cb = ctx->spr_cb[sprn].oea_write;
4032 else
9a64fbe4 4033#endif
3fc6c082 4034 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4035 if (likely(write_cb != NULL)) {
4036 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 4037 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 4038 (*write_cb)(ctx, sprn);
4039 } else {
4040 /* Privilege exception */
4a057712 4041 if (loglevel != 0) {
077fc206
JM		 4042 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4043 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4044 }
077fc206
JM		 4045 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4046 sprn, sprn, ctx->nip);
e1833e1f 4047 GEN_EXCP_PRIVREG(ctx);
76a66253 4048 }
3fc6c082
FB		 4049 } else {
4050 /* Not defined */
4a057712 4051 if (loglevel != 0) {
077fc206
JM		 4052 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4053 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4054 }
077fc206
JM		 4055 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4056 sprn, sprn, ctx->nip);
e1833e1f
JM		 4057 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4058 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 4059 }
79aceca5
FB		 4060}
4061
4062/*** Cache management ***/
79aceca5 4063/* dcbf */
0db1b20e 4064GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4065{
dac454af 4066 /* XXX: specification says this is treated as a load by the MMU */
a7812ae4 4067 TCGv t0 = tcg_temp_new();
a7859e89 4068 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4069 gen_addr_reg_index(t0, ctx);
4070 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4071 tcg_temp_free(t0);
79aceca5
FB		 4072}
4073
4074/* dcbi (Supervisor only) */
9a64fbe4 4075GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4076{
a541f297 4077#if defined(CONFIG_USER_ONLY)
e1833e1f 4078 GEN_EXCP_PRIVOPC(ctx);
a541f297 4079#else
b61f2753 4080 TCGv EA, val;
76a66253 4081 if (unlikely(!ctx->supervisor)) {
e1833e1f 4082 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4083 return;
9a64fbe4 4084 }
a7812ae4 4085 EA = tcg_temp_new();
a7859e89 4086 gen_set_access_type(ACCESS_CACHE);
b61f2753 4087 gen_addr_reg_index(EA, ctx);
a7812ae4 4088 val = tcg_temp_new();
76a66253 4089 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 4090 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4091 gen_qemu_st8(val, EA, ctx->mem_idx);
4092 tcg_temp_free(val);
4093 tcg_temp_free(EA);
a541f297 4094#endif
79aceca5
FB		 4095}
4096
4097/* dcdst */
9a64fbe4 4098GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4099{
76a66253 4100 /* XXX: specification say this is treated as a load by the MMU */
a7812ae4 4101 TCGv t0 = tcg_temp_new();
a7859e89 4102 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4103 gen_addr_reg_index(t0, ctx);
4104 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4105 tcg_temp_free(t0);
79aceca5
FB		 4106}
4107
4108/* dcbt */
0db1b20e 4109GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4110{
0db1b20e 4111 /* interpreted as no-op */
76a66253
JM		 4112 /* XXX: specification say this is treated as a load by the MMU
4113 * but does not generate any exception
4114 */
79aceca5
FB		 4115}
4116
4117/* dcbtst */
0db1b20e 4118GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4119{
0db1b20e 4120 /* interpreted as no-op */
76a66253
JM		 4121 /* XXX: specification say this is treated as a load by the MMU
4122 * but does not generate any exception
4123 */
79aceca5
FB		 4124}
4125
4126/* dcbz */
d63001d1 4127GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4128{
799a8c8d
AJ		 4129 TCGv t0 = tcg_temp_new();
4130 gen_addr_reg_index(t0, ctx);
4131 /* NIP cannot be restored if the memory exception comes from an helper */
4132 gen_update_nip(ctx, ctx->nip - 4);
4133 gen_helper_dcbz(t0);
4134 tcg_temp_free(t0);
d63001d1
JM		 4135}
4136
c7697e1f 4137GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4138{
799a8c8d
AJ		 4139 TCGv t0 = tcg_temp_new();
4140 gen_addr_reg_index(t0, ctx);
4141 /* NIP cannot be restored if the memory exception comes from an helper */
4142 gen_update_nip(ctx, ctx->nip - 4);
d63001d1 4143 if (ctx->opcode & 0x00200000)
799a8c8d 4144 gen_helper_dcbz(t0);
d63001d1 4145 else
799a8c8d
AJ		 4146 gen_helper_dcbz_970(t0);
4147 tcg_temp_free(t0);
79aceca5
FB		 4148}
4149
4150/* icbi */
1b413d55 4151GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4152{
37d269df 4153 TCGv t0 = tcg_temp_new();
30032c94
JM		 4154 /* NIP cannot be restored if the memory exception comes from an helper */
4155 gen_update_nip(ctx, ctx->nip - 4);
37d269df
AJ		 4156 gen_addr_reg_index(t0, ctx);
4157 gen_helper_icbi(t0);
4158 tcg_temp_free(t0);
79aceca5
FB		 4159}
4160
4161/* Optional: */
4162/* dcba */
a750fc0b 4163GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4164{
0db1b20e
JM		 4165 /* interpreted as no-op */
4166 /* XXX: specification say this is treated as a store by the MMU
4167 * but does not generate any exception
4168 */
79aceca5
FB		 4169}
4170
4171/*** Segment register manipulation ***/
4172/* Supervisor only: */
4173/* mfsr */
4174GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4175{
9a64fbe4 4176#if defined(CONFIG_USER_ONLY)
e1833e1f 4177 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4178#else
76a66253 4179 if (unlikely(!ctx->supervisor)) {
e1833e1f 4180 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4181 return;
9a64fbe4 4182 }
86c581dc 4183 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4184 gen_op_load_sr();
f78fb44e 4185 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4186#endif
79aceca5
FB		 4187}
4188
4189/* mfsrin */
9a64fbe4 4190GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4191{
9a64fbe4 4192#if defined(CONFIG_USER_ONLY)
e1833e1f 4193 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4194#else
76a66253 4195 if (unlikely(!ctx->supervisor)) {
e1833e1f 4196 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4197 return;
9a64fbe4 4198 }
f78fb44e 4199 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4200 gen_op_srli_T1(28);
4201 gen_op_load_sr();
f78fb44e 4202 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4203#endif
79aceca5
FB		 4204}
4205
4206/* mtsr */
e63c59cb 4207GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4208{
9a64fbe4 4209#if defined(CONFIG_USER_ONLY)
e1833e1f 4210 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4211#else
76a66253 4212 if (unlikely(!ctx->supervisor)) {
e1833e1f 4213 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4214 return;
9a64fbe4 4215 }
f78fb44e 4216 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4217 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4218 gen_op_store_sr();
9a64fbe4 4219#endif
79aceca5
FB		 4220}
4221
4222/* mtsrin */
9a64fbe4 4223GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4224{
9a64fbe4 4225#if defined(CONFIG_USER_ONLY)
e1833e1f 4226 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4227#else
76a66253 4228 if (unlikely(!ctx->supervisor)) {
e1833e1f 4229 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4230 return;
9a64fbe4 4231 }
f78fb44e
AJ		 4232 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4233 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4234 gen_op_srli_T1(28);
4235 gen_op_store_sr();
9a64fbe4 4236#endif
79aceca5
FB		 4237}
4238
12de9a39
JM		 4239#if defined(TARGET_PPC64)
4240/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4241/* mfsr */
c7697e1f 4242GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4243{
4244#if defined(CONFIG_USER_ONLY)
4245 GEN_EXCP_PRIVREG(ctx);
4246#else
4247 if (unlikely(!ctx->supervisor)) {
4248 GEN_EXCP_PRIVREG(ctx);
4249 return;
4250 }
86c581dc 4251 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4252 gen_op_load_slb();
f78fb44e 4253 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4254#endif
4255}
4256
4257/* mfsrin */
c7697e1f
JM		 4258GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4259 PPC_SEGMENT_64B)
12de9a39
JM		 4260{
4261#if defined(CONFIG_USER_ONLY)
4262 GEN_EXCP_PRIVREG(ctx);
4263#else
4264 if (unlikely(!ctx->supervisor)) {
4265 GEN_EXCP_PRIVREG(ctx);
4266 return;
4267 }
f78fb44e 4268 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4269 gen_op_srli_T1(28);
4270 gen_op_load_slb();
f78fb44e 4271 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4272#endif
4273}
4274
4275/* mtsr */
c7697e1f 4276GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4277{
4278#if defined(CONFIG_USER_ONLY)
4279 GEN_EXCP_PRIVREG(ctx);
4280#else
4281 if (unlikely(!ctx->supervisor)) {
4282 GEN_EXCP_PRIVREG(ctx);
4283 return;
4284 }
f78fb44e 4285 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4286 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4287 gen_op_store_slb();
4288#endif
4289}
4290
4291/* mtsrin */
c7697e1f
JM		 4292GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4293 PPC_SEGMENT_64B)
12de9a39
JM		 4294{
4295#if defined(CONFIG_USER_ONLY)
4296 GEN_EXCP_PRIVREG(ctx);
4297#else
4298 if (unlikely(!ctx->supervisor)) {
4299 GEN_EXCP_PRIVREG(ctx);
4300 return;
4301 }
f78fb44e
AJ		 4302 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4303 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4304 gen_op_srli_T1(28);
4305 gen_op_store_slb();
4306#endif
4307}
4308#endif /* defined(TARGET_PPC64) */
4309
79aceca5
FB		 4310/*** Lookaside buffer management ***/
4311/* Optional & supervisor only: */
4312/* tlbia */
3fc6c082 4313GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4314{
9a64fbe4 4315#if defined(CONFIG_USER_ONLY)
e1833e1f 4316 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4317#else
76a66253 4318 if (unlikely(!ctx->supervisor)) {
e1833e1f 4319 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4320 return;
9a64fbe4
FB		 4321 }
4322 gen_op_tlbia();
4323#endif
79aceca5
FB		 4324}
4325
4326/* tlbie */
76a66253 4327GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4328{
9a64fbe4 4329#if defined(CONFIG_USER_ONLY)
e1833e1f 4330 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4331#else
76a66253 4332 if (unlikely(!ctx->supervisor)) {
e1833e1f 4333 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4334 return;
9a64fbe4 4335 }
f78fb44e 4336 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4337#if defined(TARGET_PPC64)
4338 if (ctx->sf_mode)
4339 gen_op_tlbie_64();
4340 else
4341#endif
4342 gen_op_tlbie();
9a64fbe4 4343#endif
79aceca5
FB		 4344}
4345
4346/* tlbsync */
76a66253 4347GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4348{
9a64fbe4 4349#if defined(CONFIG_USER_ONLY)
e1833e1f 4350 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4351#else
76a66253 4352 if (unlikely(!ctx->supervisor)) {
e1833e1f 4353 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4354 return;
9a64fbe4
FB		 4355 }
4356 /* This has no effect: it should ensure that all previous
4357 * tlbie have completed
4358 */
e1833e1f 4359 GEN_STOP(ctx);
9a64fbe4 4360#endif
79aceca5
FB		 4361}
4362
426613db
JM		 4363#if defined(TARGET_PPC64)
4364/* slbia */
4365GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4366{
4367#if defined(CONFIG_USER_ONLY)
e1833e1f 4368 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4369#else
4370 if (unlikely(!ctx->supervisor)) {
e1833e1f 4371 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4372 return;
4373 }
4374 gen_op_slbia();
426613db
JM		 4375#endif
4376}
4377
4378/* slbie */
4379GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4380{
4381#if defined(CONFIG_USER_ONLY)
e1833e1f 4382 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4383#else
4384 if (unlikely(!ctx->supervisor)) {
e1833e1f 4385 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4386 return;
4387 }
f78fb44e 4388 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4389 gen_op_slbie();
426613db
JM		 4390#endif
4391}
4392#endif
4393
79aceca5
FB		 4394/*** External control ***/
4395/* Optional: */
9a64fbe4
FB		 4396#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4397#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4398static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4399 GEN_MEM_FUNCS(eciwx),
111bfab3 4400};
7863667f
JM		 4401static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4402 GEN_MEM_FUNCS(ecowx),
111bfab3 4403};
9a64fbe4 4404
111bfab3 4405/* eciwx */
79aceca5
FB		 4406GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4407{
9a64fbe4 4408 /* Should check EAR[E] & alignment ! */
a7859e89 4409 gen_set_access_type(ACCESS_RES);
e2be8d8d 4410 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4411 op_eciwx();
f78fb44e 4412 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4413}
4414
4415/* ecowx */
4416GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4417{
4418 /* Should check EAR[E] & alignment ! */
e2be8d8d 4419 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4420 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4421 op_ecowx();
4422}
4423
4424/* PowerPC 601 specific instructions */
4425/* abs - abs. */
4426GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4427{
f78fb44e 4428 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4429 gen_op_POWER_abs();
f78fb44e 4430 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4431 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4432 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4433}
4434
4435/* abso - abso. */
4436GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4437{
f78fb44e 4438 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4439 gen_op_POWER_abso();
f78fb44e 4440 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4441 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4442 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4443}
4444
4445/* clcs */
a750fc0b 4446GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4447{
f78fb44e 4448 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4449 gen_op_POWER_clcs();
c7697e1f 4450 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4451 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4452}
4453
4454/* div - div. */
4455GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4456{
f78fb44e
AJ		 4457 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4458 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4459 gen_op_POWER_div();
f78fb44e 4460 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4461 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4462 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4463}
4464
4465/* divo - divo. */
4466GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4467{
f78fb44e
AJ		 4468 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4469 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4470 gen_op_POWER_divo();
f78fb44e 4471 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4472 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4473 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4474}
4475
4476/* divs - divs. */
4477GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4478{
f78fb44e
AJ		 4479 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4480 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4481 gen_op_POWER_divs();
f78fb44e 4482 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4483 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4484 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4485}
4486
4487/* divso - divso. */
4488GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4489{
f78fb44e
AJ		 4490 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4491 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4492 gen_op_POWER_divso();
f78fb44e 4493 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4494 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4495 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4496}
4497
4498/* doz - doz. */
4499GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4500{
f78fb44e
AJ		 4501 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4502 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4503 gen_op_POWER_doz();
f78fb44e 4504 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4505 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4506 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4507}
4508
4509/* dozo - dozo. */
4510GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4511{
f78fb44e
AJ		 4512 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4513 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4514 gen_op_POWER_dozo();
f78fb44e 4515 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4516 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4517 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4518}
4519
4520/* dozi */
4521GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4522{
f78fb44e 4523 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4524 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4525 gen_op_POWER_doz();
f78fb44e 4526 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4527}
4528
7863667f
JM		 4529/* As lscbx load from memory byte after byte, it's always endian safe.
4530 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4531 */
2857068e 4532#define op_POWER_lscbx(start, ra, rb) \
76a66253 4533(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 4534#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4535#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4536#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4537#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4538#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4539#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4540#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4541#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4542#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4543#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4544#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4545#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4546static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4547 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4548};
76a66253
JM		 4549
4550/* lscbx - lscbx. */
4551GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4552{
4553 int ra = rA(ctx->opcode);
4554 int rb = rB(ctx->opcode);
4555
e2be8d8d 4556 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4557 if (ra == 0) {
4558 ra = rb;
4559 }
4560 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4561 gen_update_nip(ctx, ctx->nip - 4);
3d7b417e
AJ		 4562 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4563 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4564 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
76a66253 4565 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3d7b417e
AJ		 4566 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4567 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253 4568 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4569 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4570}
4571
4572/* maskg - maskg. */
4573GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4574{
f78fb44e
AJ		 4575 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4576 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4577 gen_op_POWER_maskg();
f78fb44e 4578 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4579 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4580 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4581}
4582
4583/* maskir - maskir. */
4584GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4585{
f78fb44e
AJ		 4586 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4587 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4588 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4589 gen_op_POWER_maskir();
f78fb44e 4590 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4591 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4592 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4593}
4594
4595/* mul - mul. */
4596GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4597{
f78fb44e
AJ		 4598 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4599 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4600 gen_op_POWER_mul();
f78fb44e 4601 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4602 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4603 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4604}
4605
4606/* mulo - mulo. */
4607GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4608{
f78fb44e
AJ		 4609 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4610 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4611 gen_op_POWER_mulo();
f78fb44e 4612 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4613 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4614 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4615}
4616
4617/* nabs - nabs. */
4618GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4619{
f78fb44e 4620 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4621 gen_op_POWER_nabs();
f78fb44e 4622 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4623 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4624 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4625}
4626
4627/* nabso - nabso. */
4628GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4629{
f78fb44e 4630 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4631 gen_op_POWER_nabso();
f78fb44e 4632 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4633 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4634 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4635}
4636
4637/* rlmi - rlmi. */
4638GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4639{
4640 uint32_t mb, me;
4641
4642 mb = MB(ctx->opcode);
4643 me = ME(ctx->opcode);
f78fb44e
AJ		 4644 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4645 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4646 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4647 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4648 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4649 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4650 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4651}
4652
4653/* rrib - rrib. */
4654GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4655{
f78fb44e
AJ		 4656 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4657 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4658 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4659 gen_op_POWER_rrib();
f78fb44e 4660 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4661 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4662 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4663}
4664
4665/* sle - sle. */
4666GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4667{
f78fb44e
AJ		 4668 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4669 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4670 gen_op_POWER_sle();
f78fb44e 4671 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4672 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4673 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4674}
4675
4676/* sleq - sleq. */
4677GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4678{
f78fb44e
AJ		 4679 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4680 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4681 gen_op_POWER_sleq();
f78fb44e 4682 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4683 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4684 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4685}
4686
4687/* sliq - sliq. */
4688GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4689{
f78fb44e 4690 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4691 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4692 gen_op_POWER_sle();
f78fb44e 4693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4694 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4695 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4696}
4697
4698/* slliq - slliq. */
4699GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4700{
f78fb44e 4701 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4702 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4703 gen_op_POWER_sleq();
f78fb44e 4704 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4705 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4706 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4707}
4708
4709/* sllq - sllq. */
4710GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4711{
f78fb44e
AJ		 4712 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4713 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4714 gen_op_POWER_sllq();
f78fb44e 4715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4716 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4717 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4718}
4719
4720/* slq - slq. */
4721GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4722{
f78fb44e
AJ		 4723 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4724 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4725 gen_op_POWER_slq();
f78fb44e 4726 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4727 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4728 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4729}
4730
d9bce9d9 4731/* sraiq - sraiq. */
76a66253
JM		 4732GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4733{
f78fb44e 4734 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4735 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4736 gen_op_POWER_sraq();
f78fb44e 4737 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4738 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4739 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4740}
4741
4742/* sraq - sraq. */
4743GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4744{
f78fb44e
AJ		 4745 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4746 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4747 gen_op_POWER_sraq();
f78fb44e 4748 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4749 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4750 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4751}
4752
4753/* sre - sre. */
4754GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4755{
f78fb44e
AJ		 4756 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4757 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4758 gen_op_POWER_sre();
f78fb44e 4759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4760 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4761 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4762}
4763
4764/* srea - srea. */
4765GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4766{
f78fb44e
AJ		 4767 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4768 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4769 gen_op_POWER_srea();
f78fb44e 4770 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4771 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4772 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4773}
4774
4775/* sreq */
4776GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4777{
f78fb44e
AJ		 4778 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4779 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4780 gen_op_POWER_sreq();
f78fb44e 4781 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4782 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4783 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4784}
4785
4786/* sriq */
4787GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4788{
f78fb44e 4789 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4790 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4791 gen_op_POWER_srq();
f78fb44e 4792 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4793 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4794 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4795}
4796
4797/* srliq */
4798GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4799{
f78fb44e
AJ		 4800 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4801 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4802 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4803 gen_op_POWER_srlq();
f78fb44e 4804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4805 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4806 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4807}
4808
4809/* srlq */
4810GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4811{
f78fb44e
AJ		 4812 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4813 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4814 gen_op_POWER_srlq();
f78fb44e 4815 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4816 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4817 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4818}
4819
4820/* srq */
4821GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4822{
f78fb44e
AJ		 4823 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4824 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4825 gen_op_POWER_srq();
f78fb44e 4826 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4827 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4828 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4829}
4830
4831/* PowerPC 602 specific instructions */
4832/* dsa */
4833GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4834{
4835 /* XXX: TODO */
e1833e1f 4836 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4837}
4838
4839/* esa */
4840GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4841{
4842 /* XXX: TODO */
e1833e1f 4843 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4844}
4845
4846/* mfrom */
4847GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4848{
4849#if defined(CONFIG_USER_ONLY)
e1833e1f 4850 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4851#else
4852 if (unlikely(!ctx->supervisor)) {
e1833e1f 4853 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4854 return;
4855 }
cf02a65c 4856 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4857#endif
4858}
4859
4860/* 602 - 603 - G2 TLB management */
4861/* tlbld */
c7697e1f 4862GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4863{
4864#if defined(CONFIG_USER_ONLY)
e1833e1f 4865 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4866#else
4867 if (unlikely(!ctx->supervisor)) {
e1833e1f 4868 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4869 return;
4870 }
0f3955e2 4871 gen_helper_load_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4872#endif
4873}
4874
4875/* tlbli */
c7697e1f 4876GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4877{
4878#if defined(CONFIG_USER_ONLY)
e1833e1f 4879 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4880#else
4881 if (unlikely(!ctx->supervisor)) {
e1833e1f 4882 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4883 return;
4884 }
0f3955e2 4885 gen_helper_load_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4886#endif
4887}
4888
7dbe11ac
JM		 4889/* 74xx TLB management */
4890/* tlbld */
c7697e1f 4891GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4892{
4893#if defined(CONFIG_USER_ONLY)
4894 GEN_EXCP_PRIVOPC(ctx);
4895#else
4896 if (unlikely(!ctx->supervisor)) {
4897 GEN_EXCP_PRIVOPC(ctx);
4898 return;
4899 }
0f3955e2 4900 gen_helper_load_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4901#endif
4902}
4903
4904/* tlbli */
c7697e1f 4905GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4906{
4907#if defined(CONFIG_USER_ONLY)
4908 GEN_EXCP_PRIVOPC(ctx);
4909#else
4910 if (unlikely(!ctx->supervisor)) {
4911 GEN_EXCP_PRIVOPC(ctx);
4912 return;
4913 }
0f3955e2 4914 gen_helper_load_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4915#endif
4916}
4917
76a66253
JM		 4918/* POWER instructions not in PowerPC 601 */
4919/* clf */
4920GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4921{
4922 /* Cache line flush: implemented as no-op */
4923}
4924
4925/* cli */
4926GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4927{
7f75ffd3 4928 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4929#if defined(CONFIG_USER_ONLY)
e1833e1f 4930 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4931#else
4932 if (unlikely(!ctx->supervisor)) {
e1833e1f 4933 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4934 return;
4935 }
4936#endif
4937}
4938
4939/* dclst */
4940GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4941{
4942 /* Data cache line store: treated as no-op */
4943}
4944
4945GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4946{
4947#if defined(CONFIG_USER_ONLY)
e1833e1f 4948 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4949#else
4950 if (unlikely(!ctx->supervisor)) {
e1833e1f 4951 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4952 return;
4953 }
4954 int ra = rA(ctx->opcode);
4955 int rd = rD(ctx->opcode);
4956
e2be8d8d 4957 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4958 gen_op_POWER_mfsri();
f78fb44e 4959 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4960 if (ra != 0 && ra != rd)
f78fb44e 4961 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4962#endif
4963}
4964
4965GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4966{
4967#if defined(CONFIG_USER_ONLY)
e1833e1f 4968 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4969#else
4970 if (unlikely(!ctx->supervisor)) {
e1833e1f 4971 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4972 return;
4973 }
e2be8d8d 4974 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4975 gen_op_POWER_rac();
f78fb44e 4976 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4977#endif
4978}
4979
4980GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4981{
4982#if defined(CONFIG_USER_ONLY)
e1833e1f 4983 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4984#else
4985 if (unlikely(!ctx->supervisor)) {
e1833e1f 4986 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4987 return;
4988 }
4989 gen_op_POWER_rfsvc();
e1833e1f 4990 GEN_SYNC(ctx);
76a66253
JM		 4991#endif
4992}
4993
4994/* svc is not implemented for now */
4995
4996/* POWER2 specific instructions */
4997/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 4998
4999/* lfq */
5000GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5001{
01a4afeb
AJ		 5002 int rd = rD(ctx->opcode);
5003 TCGv t0 = tcg_temp_new();
5004 gen_addr_imm_index(t0, ctx, 0);
5005 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5006 tcg_gen_addi_tl(t0, t0, 8);
5007 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5008 tcg_temp_free(t0);
76a66253
JM		 5009}
5010
5011/* lfqu */
5012GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5013{
5014 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5015 int rd = rD(ctx->opcode);
5016 TCGv t0 = tcg_temp_new();
5017 TCGv t1 = tcg_temp_new();
5018 gen_addr_imm_index(t0, ctx, 0);
5019 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5020 tcg_gen_addi_tl(t1, t0, 8);
5021 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5022 if (ra != 0)
01a4afeb
AJ		 5023 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5024 tcg_temp_free(t0);
5025 tcg_temp_free(t1);
76a66253
JM		 5026}
5027
5028/* lfqux */
5029GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5030{
5031 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5032 int rd = rD(ctx->opcode);
5033 TCGv t0 = tcg_temp_new();
5034 TCGv t1 = tcg_temp_new();
5035 gen_addr_reg_index(t0, ctx);
5036 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5037 tcg_gen_addi_tl(t1, t0, 8);
5038 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5039 if (ra != 0)
01a4afeb
AJ		 5040 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5041 tcg_temp_free(t0);
5042 tcg_temp_free(t1);
76a66253
JM		 5043}
5044
5045/* lfqx */
5046GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5047{
01a4afeb
AJ		 5048 int rd = rD(ctx->opcode);
5049 TCGv t0 = tcg_temp_new();
5050 gen_addr_reg_index(t0, ctx);
5051 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5052 tcg_gen_addi_tl(t0, t0, 8);
5053 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5054 tcg_temp_free(t0);
76a66253
JM		 5055}
5056
5057/* stfq */
5058GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5059{
01a4afeb
AJ		 5060 int rd = rD(ctx->opcode);
5061 TCGv t0 = tcg_temp_new();
5062 gen_addr_imm_index(t0, ctx, 0);
5063 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5064 tcg_gen_addi_tl(t0, t0, 8);
5065 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5066 tcg_temp_free(t0);
76a66253
JM		 5067}
5068
5069/* stfqu */
5070GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5071{
5072 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5073 int rd = rD(ctx->opcode);
5074 TCGv t0 = tcg_temp_new();
5075 TCGv t1 = tcg_temp_new();
5076 gen_addr_imm_index(t0, ctx, 0);
5077 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5078 tcg_gen_addi_tl(t1, t0, 8);
5079 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5080 if (ra != 0)
01a4afeb
AJ		 5081 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5082 tcg_temp_free(t0);
5083 tcg_temp_free(t1);
76a66253
JM		 5084}
5085
5086/* stfqux */
5087GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5088{
5089 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5090 int rd = rD(ctx->opcode);
5091 TCGv t0 = tcg_temp_new();
5092 TCGv t1 = tcg_temp_new();
5093 gen_addr_reg_index(t0, ctx);
5094 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5095 tcg_gen_addi_tl(t1, t0, 8);
5096 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5097 if (ra != 0)
01a4afeb
AJ		 5098 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5099 tcg_temp_free(t0);
5100 tcg_temp_free(t1);
76a66253
JM		 5101}
5102
5103/* stfqx */
5104GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5105{
01a4afeb
AJ		 5106 int rd = rD(ctx->opcode);
5107 TCGv t0 = tcg_temp_new();
5108 gen_addr_reg_index(t0, ctx);
5109 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5110 tcg_gen_addi_tl(t0, t0, 8);
5111 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5112 tcg_temp_free(t0);
76a66253
JM		 5113}
5114
5115/* BookE specific instructions */
2662a059 5116/* XXX: not implemented on 440 ? */
05332d70 5117GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5118{
5119 /* XXX: TODO */
e1833e1f 5120 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5121}
5122
2662a059 5123/* XXX: not implemented on 440 ? */
05332d70 5124GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5125{
5126#if defined(CONFIG_USER_ONLY)
e1833e1f 5127 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5128#else
5129 if (unlikely(!ctx->supervisor)) {
e1833e1f 5130 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5131 return;
5132 }
e2be8d8d 5133 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5134 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5135#if defined(TARGET_PPC64)
5136 if (ctx->sf_mode)
5137 gen_op_tlbie_64();
5138 else
5139#endif
5140 gen_op_tlbie();
76a66253
JM		 5141#endif
5142}
5143
5144/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5145static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5146 int opc2, int opc3,
5147 int ra, int rb, int rt, int Rc)
76a66253 5148{
182608d4
AJ		 5149 TCGv t0, t1;
5150
a7812ae4
PB		 5151 t0 = tcg_temp_local_new();
5152 t1 = tcg_temp_local_new();
182608d4 5153
76a66253
JM		 5154 switch (opc3 & 0x0D) {
5155 case 0x05:
5156 /* macchw - macchw. - macchwo - macchwo. */
5157 /* macchws - macchws. - macchwso - macchwso. */
5158 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5159 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5160 /* mulchw - mulchw. */
182608d4
AJ		 5161 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5162 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5163 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5164 break;
5165 case 0x04:
5166 /* macchwu - macchwu. - macchwuo - macchwuo. */
5167 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5168 /* mulchwu - mulchwu. */
182608d4
AJ		 5169 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5170 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5171 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5172 break;
5173 case 0x01:
5174 /* machhw - machhw. - machhwo - machhwo. */
5175 /* machhws - machhws. - machhwso - machhwso. */
5176 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5177 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5178 /* mulhhw - mulhhw. */
182608d4
AJ		 5179 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5180 tcg_gen_ext16s_tl(t0, t0);
5181 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5182 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5183 break;
5184 case 0x00:
5185 /* machhwu - machhwu. - machhwuo - machhwuo. */
5186 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5187 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5188 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5189 tcg_gen_ext16u_tl(t0, t0);
5190 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5191 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5192 break;
5193 case 0x0D:
5194 /* maclhw - maclhw. - maclhwo - maclhwo. */
5195 /* maclhws - maclhws. - maclhwso - maclhwso. */
5196 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5197 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5198 /* mullhw - mullhw. */
182608d4
AJ		 5199 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5200 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5201 break;
5202 case 0x0C:
5203 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5204 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5205 /* mullhwu - mullhwu. */
182608d4
AJ		 5206 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5207 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5208 break;
5209 }
76a66253 5210 if (opc2 & 0x04) {
182608d4
AJ		 5211 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5212 tcg_gen_mul_tl(t1, t0, t1);
5213 if (opc2 & 0x02) {
5214 /* nmultiply-and-accumulate (0x0E) */
5215 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5216 } else {
5217 /* multiply-and-accumulate (0x0C) */
5218 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5219 }
5220
5221 if (opc3 & 0x12) {
5222 /* Check overflow and/or saturate */
5223 int l1 = gen_new_label();
5224
5225 if (opc3 & 0x10) {
5226 /* Start with XER OV disabled, the most likely case */
5227 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5228 }
5229 if (opc3 & 0x01) {
5230 /* Signed */
5231 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5232 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5233 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5234 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5235 if (opc3 & 0x02) {
182608d4
AJ		 5236 /* Saturate */
5237 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5238 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5239 }
5240 } else {
5241 /* Unsigned */
5242 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5243 if (opc3 & 0x02) {
182608d4
AJ		 5244 /* Saturate */
5245 tcg_gen_movi_tl(t0, UINT32_MAX);
5246 }
5247 }
5248 if (opc3 & 0x10) {
5249 /* Check overflow */
5250 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5251 }
5252 gen_set_label(l1);
5253 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5254 }
5255 } else {
5256 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5257 }
182608d4
AJ		 5258 tcg_temp_free(t0);
5259 tcg_temp_free(t1);
76a66253
JM		 5260 if (unlikely(Rc) != 0) {
5261 /* Update Rc0 */
182608d4 5262 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5263 }
5264}
5265
a750fc0b
JM		 5266#define GEN_MAC_HANDLER(name, opc2, opc3) \
5267GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5268{ \
5269 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5270 rD(ctx->opcode), Rc(ctx->opcode)); \
5271}
5272
5273/* macchw - macchw. */
a750fc0b 5274GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5275/* macchwo - macchwo. */
a750fc0b 5276GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5277/* macchws - macchws. */
a750fc0b 5278GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5279/* macchwso - macchwso. */
a750fc0b 5280GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5281/* macchwsu - macchwsu. */
a750fc0b 5282GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5283/* macchwsuo - macchwsuo. */
a750fc0b 5284GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5285/* macchwu - macchwu. */
a750fc0b 5286GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5287/* macchwuo - macchwuo. */
a750fc0b 5288GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5289/* machhw - machhw. */
a750fc0b 5290GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5291/* machhwo - machhwo. */
a750fc0b 5292GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5293/* machhws - machhws. */
a750fc0b 5294GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5295/* machhwso - machhwso. */
a750fc0b 5296GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5297/* machhwsu - machhwsu. */
a750fc0b 5298GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5299/* machhwsuo - machhwsuo. */
a750fc0b 5300GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5301/* machhwu - machhwu. */
a750fc0b 5302GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5303/* machhwuo - machhwuo. */
a750fc0b 5304GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5305/* maclhw - maclhw. */
a750fc0b 5306GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5307/* maclhwo - maclhwo. */
a750fc0b 5308GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5309/* maclhws - maclhws. */
a750fc0b 5310GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5311/* maclhwso - maclhwso. */
a750fc0b 5312GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5313/* maclhwu - maclhwu. */
a750fc0b 5314GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5315/* maclhwuo - maclhwuo. */
a750fc0b 5316GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5317/* maclhwsu - maclhwsu. */
a750fc0b 5318GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5319/* maclhwsuo - maclhwsuo. */
a750fc0b 5320GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5321/* nmacchw - nmacchw. */
a750fc0b 5322GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5323/* nmacchwo - nmacchwo. */
a750fc0b 5324GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5325/* nmacchws - nmacchws. */
a750fc0b 5326GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5327/* nmacchwso - nmacchwso. */
a750fc0b 5328GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5329/* nmachhw - nmachhw. */
a750fc0b 5330GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5331/* nmachhwo - nmachhwo. */
a750fc0b 5332GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5333/* nmachhws - nmachhws. */
a750fc0b 5334GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5335/* nmachhwso - nmachhwso. */
a750fc0b 5336GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5337/* nmaclhw - nmaclhw. */
a750fc0b 5338GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5339/* nmaclhwo - nmaclhwo. */
a750fc0b 5340GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5341/* nmaclhws - nmaclhws. */
a750fc0b 5342GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5343/* nmaclhwso - nmaclhwso. */
a750fc0b 5344GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5345
5346/* mulchw - mulchw. */
a750fc0b 5347GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5348/* mulchwu - mulchwu. */
a750fc0b 5349GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5350/* mulhhw - mulhhw. */
a750fc0b 5351GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5352/* mulhhwu - mulhhwu. */
a750fc0b 5353GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5354/* mullhw - mullhw. */
a750fc0b 5355GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5356/* mullhwu - mullhwu. */
a750fc0b 5357GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5358
5359/* mfdcr */
05332d70 5360GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5361{
5362#if defined(CONFIG_USER_ONLY)
e1833e1f 5363 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5364#else
5365 uint32_t dcrn = SPR(ctx->opcode);
5366
5367 if (unlikely(!ctx->supervisor)) {
e1833e1f 5368 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5369 return;
5370 }
86c581dc 5371 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5372 gen_op_load_dcr();
f78fb44e 5373 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5374#endif
5375}
5376
5377/* mtdcr */
05332d70 5378GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5379{
5380#if defined(CONFIG_USER_ONLY)
e1833e1f 5381 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5382#else
5383 uint32_t dcrn = SPR(ctx->opcode);
5384
5385 if (unlikely(!ctx->supervisor)) {
e1833e1f 5386 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5387 return;
5388 }
86c581dc 5389 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5390 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5391 gen_op_store_dcr();
5392#endif
5393}
5394
5395/* mfdcrx */
2662a059 5396/* XXX: not implemented on 440 ? */
05332d70 5397GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5398{
5399#if defined(CONFIG_USER_ONLY)
e1833e1f 5400 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5401#else
5402 if (unlikely(!ctx->supervisor)) {
e1833e1f 5403 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5404 return;
5405 }
f78fb44e 5406 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5407 gen_op_load_dcr();
f78fb44e 5408 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5409 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5410#endif
5411}
5412
5413/* mtdcrx */
2662a059 5414/* XXX: not implemented on 440 ? */
05332d70 5415GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5416{
5417#if defined(CONFIG_USER_ONLY)
e1833e1f 5418 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5419#else
5420 if (unlikely(!ctx->supervisor)) {
e1833e1f 5421 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5422 return;
5423 }
f78fb44e
AJ		 5424 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5425 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5426 gen_op_store_dcr();
a750fc0b 5427 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5428#endif
5429}
5430
a750fc0b
JM		 5431/* mfdcrux (PPC 460) : user-mode access to DCR */
5432GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5433{
f78fb44e 5434 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5435 gen_op_load_dcr();
f78fb44e 5436 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5437 /* Note: Rc update flag set leads to undefined state of Rc0 */
5438}
5439
5440/* mtdcrux (PPC 460) : user-mode access to DCR */
5441GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5442{
f78fb44e
AJ		 5443 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5444 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5445 gen_op_store_dcr();
5446 /* Note: Rc update flag set leads to undefined state of Rc0 */
5447}
5448
76a66253
JM		 5449/* dccci */
5450GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5451{
5452#if defined(CONFIG_USER_ONLY)
e1833e1f 5453 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5454#else
5455 if (unlikely(!ctx->supervisor)) {
e1833e1f 5456 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5457 return;
5458 }
5459 /* interpreted as no-op */
5460#endif
5461}
5462
5463/* dcread */
5464GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5465{
5466#if defined(CONFIG_USER_ONLY)
e1833e1f 5467 GEN_EXCP_PRIVOPC(ctx);
76a66253 5468#else
b61f2753 5469 TCGv EA, val;
76a66253 5470 if (unlikely(!ctx->supervisor)) {
e1833e1f 5471 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5472 return;
5473 }
a7812ae4 5474 EA = tcg_temp_new();
a7859e89 5475 gen_set_access_type(ACCESS_CACHE);
b61f2753 5476 gen_addr_reg_index(EA, ctx);
a7812ae4 5477 val = tcg_temp_new();
b61f2753
AJ		 5478 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5479 tcg_temp_free(val);
5480 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5481 tcg_temp_free(EA);
76a66253
JM		 5482#endif
5483}
5484
5485/* icbt */
c7697e1f 5486GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5487{
5488 /* interpreted as no-op */
5489 /* XXX: specification say this is treated as a load by the MMU
5490 * but does not generate any exception
5491 */
5492}
5493
5494/* iccci */
5495GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5496{
5497#if defined(CONFIG_USER_ONLY)
e1833e1f 5498 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5499#else
5500 if (unlikely(!ctx->supervisor)) {
e1833e1f 5501 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5502 return;
5503 }
5504 /* interpreted as no-op */
5505#endif
5506}
5507
5508/* icread */
5509GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5510{
5511#if defined(CONFIG_USER_ONLY)
e1833e1f 5512 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5513#else
5514 if (unlikely(!ctx->supervisor)) {
e1833e1f 5515 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5516 return;
5517 }
5518 /* interpreted as no-op */
5519#endif
5520}
5521
5522/* rfci (supervisor only) */
c7697e1f 5523GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5524{
5525#if defined(CONFIG_USER_ONLY)
e1833e1f 5526 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5527#else
5528 if (unlikely(!ctx->supervisor)) {
e1833e1f 5529 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5530 return;
5531 }
5532 /* Restore CPU state */
5533 gen_op_40x_rfci();
e1833e1f 5534 GEN_SYNC(ctx);
a42bd6cc
JM		 5535#endif
5536}
5537
5538GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5539{
5540#if defined(CONFIG_USER_ONLY)
e1833e1f 5541 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5542#else
5543 if (unlikely(!ctx->supervisor)) {
e1833e1f 5544 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5545 return;
5546 }
5547 /* Restore CPU state */
5548 gen_op_rfci();
e1833e1f 5549 GEN_SYNC(ctx);
a42bd6cc
JM		 5550#endif
5551}
5552
5553/* BookE specific */
2662a059 5554/* XXX: not implemented on 440 ? */
05332d70 5555GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5556{
5557#if defined(CONFIG_USER_ONLY)
e1833e1f 5558 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5559#else
5560 if (unlikely(!ctx->supervisor)) {
e1833e1f 5561 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5562 return;
5563 }
5564 /* Restore CPU state */
a42bd6cc 5565 gen_op_rfdi();
e1833e1f 5566 GEN_SYNC(ctx);
76a66253
JM		 5567#endif
5568}
5569
2662a059 5570/* XXX: not implemented on 440 ? */
a750fc0b 5571GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5572{
5573#if defined(CONFIG_USER_ONLY)
e1833e1f 5574 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5575#else
5576 if (unlikely(!ctx->supervisor)) {
e1833e1f 5577 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5578 return;
5579 }
5580 /* Restore CPU state */
5581 gen_op_rfmci();
e1833e1f 5582 GEN_SYNC(ctx);
a42bd6cc
JM		 5583#endif
5584}
5eb7995e 5585
d9bce9d9 5586/* TLB management - PowerPC 405 implementation */
76a66253 5587/* tlbre */
c7697e1f 5588GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5589{
5590#if defined(CONFIG_USER_ONLY)
e1833e1f 5591 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5592#else
5593 if (unlikely(!ctx->supervisor)) {
e1833e1f 5594 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5595 return;
5596 }
5597 switch (rB(ctx->opcode)) {
5598 case 0:
f78fb44e 5599 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5600 gen_op_4xx_tlbre_hi();
f78fb44e 5601 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5602 break;
5603 case 1:
f78fb44e 5604 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5605 gen_op_4xx_tlbre_lo();
f78fb44e 5606 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5607 break;
5608 default:
e1833e1f 5609 GEN_EXCP_INVAL(ctx);
76a66253 5610 break;
9a64fbe4 5611 }
76a66253
JM		 5612#endif
5613}
5614
d9bce9d9 5615/* tlbsx - tlbsx. */
c7697e1f 5616GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5617{
5618#if defined(CONFIG_USER_ONLY)
e1833e1f 5619 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5620#else
5621 if (unlikely(!ctx->supervisor)) {
e1833e1f 5622 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5623 return;
5624 }
e2be8d8d 5625 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5626 gen_op_4xx_tlbsx();
76a66253 5627 if (Rc(ctx->opcode))
daf4f96e 5628 gen_op_4xx_tlbsx_check();
f78fb44e 5629 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5630#endif
79aceca5
FB		 5631}
5632
76a66253 5633/* tlbwe */
c7697e1f 5634GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5635{
76a66253 5636#if defined(CONFIG_USER_ONLY)
e1833e1f 5637 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5638#else
5639 if (unlikely(!ctx->supervisor)) {
e1833e1f 5640 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5641 return;
5642 }
5643 switch (rB(ctx->opcode)) {
5644 case 0:
f78fb44e
AJ		 5645 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5646 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5647 gen_op_4xx_tlbwe_hi();
5648 break;
5649 case 1:
f78fb44e
AJ		 5650 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5651 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5652 gen_op_4xx_tlbwe_lo();
5653 break;
5654 default:
e1833e1f 5655 GEN_EXCP_INVAL(ctx);
76a66253 5656 break;
9a64fbe4 5657 }
76a66253
JM		 5658#endif
5659}
5660
a4bb6c3e 5661/* TLB management - PowerPC 440 implementation */
5eb7995e 5662/* tlbre */
c7697e1f 5663GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5664{
5665#if defined(CONFIG_USER_ONLY)
e1833e1f 5666 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5667#else
5668 if (unlikely(!ctx->supervisor)) {
e1833e1f 5669 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5670 return;
5671 }
5672 switch (rB(ctx->opcode)) {
5673 case 0:
5eb7995e 5674 case 1:
5eb7995e 5675 case 2:
f78fb44e 5676 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5677 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5678 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5679 break;
5680 default:
e1833e1f 5681 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5682 break;
5683 }
5684#endif
5685}
5686
5687/* tlbsx - tlbsx. */
c7697e1f 5688GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5689{
5690#if defined(CONFIG_USER_ONLY)
e1833e1f 5691 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5692#else
5693 if (unlikely(!ctx->supervisor)) {
e1833e1f 5694 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5695 return;
5696 }
e2be8d8d 5697 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5698 gen_op_440_tlbsx();
5eb7995e 5699 if (Rc(ctx->opcode))
daf4f96e 5700 gen_op_4xx_tlbsx_check();
f78fb44e 5701 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5702#endif
5703}
5704
5705/* tlbwe */
c7697e1f 5706GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5707{
5708#if defined(CONFIG_USER_ONLY)
e1833e1f 5709 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5710#else
5711 if (unlikely(!ctx->supervisor)) {
e1833e1f 5712 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5713 return;
5714 }
5715 switch (rB(ctx->opcode)) {
5716 case 0:
5eb7995e 5717 case 1:
5eb7995e 5718 case 2:
f78fb44e
AJ		 5719 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5720 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5721 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5722 break;
5723 default:
e1833e1f 5724 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5725 break;
5726 }
5727#endif
5728}
5729
76a66253 5730/* wrtee */
05332d70 5731GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5732{
5733#if defined(CONFIG_USER_ONLY)
e1833e1f 5734 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5735#else
5736 if (unlikely(!ctx->supervisor)) {
e1833e1f 5737 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5738 return;
5739 }
f78fb44e 5740 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5741 gen_op_wrte();
dee96f6c
JM		 5742 /* Stop translation to have a chance to raise an exception
5743 * if we just set msr_ee to 1
5744 */
e1833e1f 5745 GEN_STOP(ctx);
76a66253
JM		 5746#endif
5747}
5748
5749/* wrteei */
05332d70 5750GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5751{
5752#if defined(CONFIG_USER_ONLY)
e1833e1f 5753 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5754#else
5755 if (unlikely(!ctx->supervisor)) {
e1833e1f 5756 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5757 return;
5758 }
86c581dc 5759 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5760 gen_op_wrte();
dee96f6c
JM		 5761 /* Stop translation to have a chance to raise an exception
5762 * if we just set msr_ee to 1
5763 */
e1833e1f 5764 GEN_STOP(ctx);
76a66253
JM		 5765#endif
5766}
5767
08e46e54 5768/* PowerPC 440 specific instructions */
76a66253
JM		 5769/* dlmzb */
5770GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5771{
f78fb44e
AJ		 5772 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5773 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5774 gen_op_440_dlmzb();
f78fb44e 5775 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5776 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5777 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5778 if (Rc(ctx->opcode)) {
5779 gen_op_440_dlmzb_update_Rc();
a7812ae4
PB		 5780 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_T[0]);
5781 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 0xf);
76a66253
JM		 5782 }
5783}
5784
5785/* mbar replaces eieio on 440 */
5786GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5787{
5788 /* interpreted as no-op */
5789}
5790
5791/* msync replaces sync on 440 */
0db1b20e 5792GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5793{
5794 /* interpreted as no-op */
5795}
5796
5797/* icbt */
c7697e1f 5798GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5799{
5800 /* interpreted as no-op */
5801 /* XXX: specification say this is treated as a load by the MMU
5802 * but does not generate any exception
5803 */
79aceca5
FB		 5804}
5805
a9d9eb8f
JM		 5806/*** Altivec vector extension ***/
5807/* Altivec registers moves */
a9d9eb8f 5808
a9d9eb8f 5809#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 5810GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 5811{ \
fe1e5c53 5812 TCGv EA; \
a9d9eb8f
JM		 5813 if (unlikely(!ctx->altivec_enabled)) { \
5814 GEN_EXCP_NO_VR(ctx); \
5815 return; \
5816 } \
fe1e5c53
AJ		 5817 EA = tcg_temp_new(); \
5818 gen_addr_reg_index(EA, ctx); \
5819 tcg_gen_andi_tl(EA, EA, ~0xf); \
5820 if (ctx->mem_idx & 1) { \
5821 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5822 tcg_gen_addi_tl(EA, EA, 8); \
5823 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5824 } else { \
5825 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5826 tcg_gen_addi_tl(EA, EA, 8); \
5827 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5828 } \
5829 tcg_temp_free(EA); \
a9d9eb8f
JM		 5830}
5831
5832#define GEN_VR_STX(name, opc2, opc3) \
5833GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5834{ \
fe1e5c53 5835 TCGv EA; \
a9d9eb8f
JM		 5836 if (unlikely(!ctx->altivec_enabled)) { \
5837 GEN_EXCP_NO_VR(ctx); \
5838 return; \
5839 } \
fe1e5c53
AJ		 5840 EA = tcg_temp_new(); \
5841 gen_addr_reg_index(EA, ctx); \
5842 tcg_gen_andi_tl(EA, EA, ~0xf); \
5843 if (ctx->mem_idx & 1) { \
5844 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5845 tcg_gen_addi_tl(EA, EA, 8); \
5846 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5847 } else { \
5848 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5849 tcg_gen_addi_tl(EA, EA, 8); \
5850 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5851 } \
5852 tcg_temp_free(EA); \
a9d9eb8f
JM		 5853}
5854
fe1e5c53 5855GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 5856/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 5857GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 5858
fe1e5c53 5859GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 5860/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 5861GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 5862
0487d6a8 5863/*** SPE extension ***/
0487d6a8 5864/* Register moves */
3cd7d1dd 5865
a7812ae4 5866static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 5867#if defined(TARGET_PPC64)
5868 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5869#else
36aa55dc 5870 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5871#endif
f78fb44e 5872}
3cd7d1dd 5873
a7812ae4 5874static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 5875#if defined(TARGET_PPC64)
5876 tcg_gen_mov_i64(cpu_gpr[reg], t);
5877#else
a7812ae4 5878 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 5879 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 5880 tcg_gen_shri_i64(tmp, t, 32);
5881 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 5882 tcg_temp_free_i64(tmp);
3cd7d1dd 5883#endif
f78fb44e 5884}
3cd7d1dd 5885
0487d6a8
JM		 5886#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5887GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5888{ \
5889 if (Rc(ctx->opcode)) \
5890 gen_##name1(ctx); \
5891 else \
5892 gen_##name0(ctx); \
5893}
5894
5895/* Handler for undefined SPE opcodes */
b068d6a7 5896static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5897{
e1833e1f 5898 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5899}
5900
57951c27
AJ		 5901/* SPE logic */
5902#if defined(TARGET_PPC64)
5903#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 5904static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5905{ \
5906 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5907 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5908 return; \
5909 } \
57951c27
AJ		 5910 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5911 cpu_gpr[rB(ctx->opcode)]); \
5912}
5913#else
5914#define GEN_SPEOP_LOGIC2(name, tcg_op) \
5915static always_inline void gen_##name (DisasContext *ctx) \
5916{ \
5917 if (unlikely(!ctx->spe_enabled)) { \
5918 GEN_EXCP_NO_AP(ctx); \
5919 return; \
5920 } \
5921 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5922 cpu_gpr[rB(ctx->opcode)]); \
5923 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
5924 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 5925}
57951c27
AJ		 5926#endif
5927
5928GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
5929GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
5930GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
5931GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
5932GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
5933GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
5934GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
5935GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 5936
57951c27
AJ		 5937/* SPE logic immediate */
5938#if defined(TARGET_PPC64)
5939#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 5940static always_inline void gen_##name (DisasContext *ctx) \
5941{ \
5942 if (unlikely(!ctx->spe_enabled)) { \
5943 GEN_EXCP_NO_AP(ctx); \
5944 return; \
5945 } \
a7812ae4
PB		 5946 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
5947 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
5948 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 5949 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
5950 tcg_opi(t0, t0, rB(ctx->opcode)); \
5951 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
5952 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 5953 tcg_temp_free_i64(t2); \
57951c27
AJ		 5954 tcg_opi(t1, t1, rB(ctx->opcode)); \
5955 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 5956 tcg_temp_free_i32(t0); \
5957 tcg_temp_free_i32(t1); \
3d3a6a0a 5958}
57951c27
AJ		 5959#else
5960#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 5961static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5962{ \
5963 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5964 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5965 return; \
5966 } \
57951c27
AJ		 5967 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5968 rB(ctx->opcode)); \
5969 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
5970 rB(ctx->opcode)); \
0487d6a8 5971}
57951c27
AJ		 5972#endif
5973GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
5974GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
5975GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
5976GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 5977
57951c27
AJ		 5978/* SPE arithmetic */
5979#if defined(TARGET_PPC64)
5980#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 5981static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5982{ \
5983 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5984 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5985 return; \
5986 } \
a7812ae4
PB		 5987 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
5988 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
5989 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 5990 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
5991 tcg_op(t0, t0); \
5992 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
5993 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 5994 tcg_temp_free_i64(t2); \
57951c27
AJ		 5995 tcg_op(t1, t1); \
5996 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 5997 tcg_temp_free_i32(t0); \
5998 tcg_temp_free_i32(t1); \
0487d6a8 5999}
57951c27 6000#else
a7812ae4 6001#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6002static always_inline void gen_##name (DisasContext *ctx) \
6003{ \
6004 if (unlikely(!ctx->spe_enabled)) { \
6005 GEN_EXCP_NO_AP(ctx); \
6006 return; \
6007 } \
6008 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6009 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6010}
6011#endif
0487d6a8 6012
a7812ae4 6013static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6014{
6015 int l1 = gen_new_label();
6016 int l2 = gen_new_label();
0487d6a8 6017
57951c27
AJ		 6018 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6019 tcg_gen_neg_i32(ret, arg1);
6020 tcg_gen_br(l2);
6021 gen_set_label(l1);
a7812ae4 6022 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6023 gen_set_label(l2);
6024}
6025GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6026GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6027GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6028GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6029static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6030{
57951c27
AJ		 6031 tcg_gen_addi_i32(ret, arg1, 0x8000);
6032 tcg_gen_ext16u_i32(ret, ret);
6033}
6034GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6035GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6036GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6037
57951c27
AJ		 6038#if defined(TARGET_PPC64)
6039#define GEN_SPEOP_ARITH2(name, tcg_op) \
6040static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6041{ \
6042 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6043 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6044 return; \
6045 } \
a7812ae4
PB		 6046 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6047 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6048 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6049 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
57951c27
AJ		 6050 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6051 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6052 tcg_op(t0, t0, t2); \
6053 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6054 tcg_gen_trunc_i64_i32(t1, t3); \
6055 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6056 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6057 tcg_temp_free_i64(t3); \
57951c27 6058 tcg_op(t1, t1, t2); \
a7812ae4 6059 tcg_temp_free_i32(t2); \
57951c27 6060 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6061 tcg_temp_free_i32(t0); \
6062 tcg_temp_free_i32(t1); \
0487d6a8 6063}
57951c27
AJ		 6064#else
6065#define GEN_SPEOP_ARITH2(name, tcg_op) \
6066static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6067{ \
6068 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6069 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6070 return; \
6071 } \
57951c27
AJ		 6072 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6073 cpu_gpr[rB(ctx->opcode)]); \
6074 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6075 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6076}
57951c27 6077#endif
0487d6a8 6078
a7812ae4 6079static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6080{
a7812ae4 6081 TCGv_i32 t0;
57951c27 6082 int l1, l2;
0487d6a8 6083
57951c27
AJ		 6084 l1 = gen_new_label();
6085 l2 = gen_new_label();
a7812ae4 6086 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6087 /* No error here: 6 bits are used */
6088 tcg_gen_andi_i32(t0, arg2, 0x3F);
6089 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6090 tcg_gen_shr_i32(ret, arg1, t0);
6091 tcg_gen_br(l2);
6092 gen_set_label(l1);
6093 tcg_gen_movi_i32(ret, 0);
6094 tcg_gen_br(l2);
a7812ae4 6095 tcg_temp_free_i32(t0);
57951c27
AJ		 6096}
6097GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6098static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6099{
a7812ae4 6100 TCGv_i32 t0;
57951c27
AJ		 6101 int l1, l2;
6102
6103 l1 = gen_new_label();
6104 l2 = gen_new_label();
a7812ae4 6105 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6106 /* No error here: 6 bits are used */
6107 tcg_gen_andi_i32(t0, arg2, 0x3F);
6108 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6109 tcg_gen_sar_i32(ret, arg1, t0);
6110 tcg_gen_br(l2);
6111 gen_set_label(l1);
6112 tcg_gen_movi_i32(ret, 0);
6113 tcg_gen_br(l2);
a7812ae4 6114 tcg_temp_free_i32(t0);
57951c27
AJ		 6115}
6116GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6117static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6118{
a7812ae4 6119 TCGv_i32 t0;
57951c27
AJ		 6120 int l1, l2;
6121
6122 l1 = gen_new_label();
6123 l2 = gen_new_label();
a7812ae4 6124 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6125 /* No error here: 6 bits are used */
6126 tcg_gen_andi_i32(t0, arg2, 0x3F);
6127 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6128 tcg_gen_shl_i32(ret, arg1, t0);
6129 tcg_gen_br(l2);
6130 gen_set_label(l1);
6131 tcg_gen_movi_i32(ret, 0);
6132 tcg_gen_br(l2);
a7812ae4 6133 tcg_temp_free_i32(t0);
57951c27
AJ		 6134}
6135GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6136static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6137{
a7812ae4 6138 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6139 tcg_gen_andi_i32(t0, arg2, 0x1F);
6140 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6141 tcg_temp_free_i32(t0);
57951c27
AJ		 6142}
6143GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6144static always_inline void gen_evmergehi (DisasContext *ctx)
6145{
6146 if (unlikely(!ctx->spe_enabled)) {
6147 GEN_EXCP_NO_AP(ctx);
6148 return;
6149 }
6150#if defined(TARGET_PPC64)
a7812ae4
PB		 6151 TCGv t0 = tcg_temp_new();
6152 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6153 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6154 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6155 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6156 tcg_temp_free(t0);
6157 tcg_temp_free(t1);
6158#else
6159 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6160 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6161#endif
6162}
6163GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6164static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6165{
57951c27
AJ		 6166 tcg_gen_sub_i32(ret, arg2, arg1);
6167}
6168GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6169
57951c27
AJ		 6170/* SPE arithmetic immediate */
6171#if defined(TARGET_PPC64)
6172#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6173static always_inline void gen_##name (DisasContext *ctx) \
6174{ \
6175 if (unlikely(!ctx->spe_enabled)) { \
6176 GEN_EXCP_NO_AP(ctx); \
6177 return; \
6178 } \
a7812ae4
PB		 6179 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6180 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6181 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6182 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6183 tcg_op(t0, t0, rA(ctx->opcode)); \
6184 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6185 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6186 tcg_temp_free_i64(t2); \
57951c27
AJ		 6187 tcg_op(t1, t1, rA(ctx->opcode)); \
6188 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6189 tcg_temp_free_i32(t0); \
6190 tcg_temp_free_i32(t1); \
57951c27
AJ		 6191}
6192#else
6193#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6194static always_inline void gen_##name (DisasContext *ctx) \
6195{ \
6196 if (unlikely(!ctx->spe_enabled)) { \
6197 GEN_EXCP_NO_AP(ctx); \
6198 return; \
6199 } \
6200 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6201 rA(ctx->opcode)); \
6202 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6203 rA(ctx->opcode)); \
6204}
6205#endif
6206GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6207GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6208
6209/* SPE comparison */
6210#if defined(TARGET_PPC64)
6211#define GEN_SPEOP_COMP(name, tcg_cond) \
6212static always_inline void gen_##name (DisasContext *ctx) \
6213{ \
6214 if (unlikely(!ctx->spe_enabled)) { \
6215 GEN_EXCP_NO_AP(ctx); \
6216 return; \
6217 } \
6218 int l1 = gen_new_label(); \
6219 int l2 = gen_new_label(); \
6220 int l3 = gen_new_label(); \
6221 int l4 = gen_new_label(); \
a7812ae4
PB		 6222 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6223 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6224 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6225 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6226 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6227 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6228 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6229 tcg_gen_br(l2); \
6230 gen_set_label(l1); \
6231 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6232 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6233 gen_set_label(l2); \
6234 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6235 tcg_gen_trunc_i64_i32(t0, t2); \
6236 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6237 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6238 tcg_temp_free_i64(t2); \
57951c27
AJ		 6239 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6240 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6241 ~(CRF_CH | CRF_CH_AND_CL)); \
6242 tcg_gen_br(l4); \
6243 gen_set_label(l3); \
6244 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6245 CRF_CH | CRF_CH_OR_CL); \
6246 gen_set_label(l4); \
a7812ae4
PB		 6247 tcg_temp_free_i32(t0); \
6248 tcg_temp_free_i32(t1); \
57951c27
AJ		 6249}
6250#else
6251#define GEN_SPEOP_COMP(name, tcg_cond) \
6252static always_inline void gen_##name (DisasContext *ctx) \
6253{ \
6254 if (unlikely(!ctx->spe_enabled)) { \
6255 GEN_EXCP_NO_AP(ctx); \
6256 return; \
6257 } \
6258 int l1 = gen_new_label(); \
6259 int l2 = gen_new_label(); \
6260 int l3 = gen_new_label(); \
6261 int l4 = gen_new_label(); \
6262 \
6263 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6264 cpu_gpr[rB(ctx->opcode)], l1); \
6265 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6266 tcg_gen_br(l2); \
6267 gen_set_label(l1); \
6268 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6269 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6270 gen_set_label(l2); \
6271 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6272 cpu_gprh[rB(ctx->opcode)], l3); \
6273 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6274 ~(CRF_CH | CRF_CH_AND_CL)); \
6275 tcg_gen_br(l4); \
6276 gen_set_label(l3); \
6277 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6278 CRF_CH | CRF_CH_OR_CL); \
6279 gen_set_label(l4); \
6280}
6281#endif
6282GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6283GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6284GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6285GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6286GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6287
6288/* SPE misc */
6289static always_inline void gen_brinc (DisasContext *ctx)
6290{
6291 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6292 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6293 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6294}
57951c27
AJ		 6295static always_inline void gen_evmergelo (DisasContext *ctx)
6296{
6297 if (unlikely(!ctx->spe_enabled)) {
6298 GEN_EXCP_NO_AP(ctx);
6299 return;
6300 }
6301#if defined(TARGET_PPC64)
a7812ae4
PB		 6302 TCGv t0 = tcg_temp_new();
6303 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6304 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6305 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6306 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6307 tcg_temp_free(t0);
6308 tcg_temp_free(t1);
6309#else
6310 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6311 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6312#endif
6313}
6314static always_inline void gen_evmergehilo (DisasContext *ctx)
6315{
6316 if (unlikely(!ctx->spe_enabled)) {
6317 GEN_EXCP_NO_AP(ctx);
6318 return;
6319 }
6320#if defined(TARGET_PPC64)
a7812ae4
PB		 6321 TCGv t0 = tcg_temp_new();
6322 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6323 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6324 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6325 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6326 tcg_temp_free(t0);
6327 tcg_temp_free(t1);
6328#else
6329 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6330 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6331#endif
6332}
6333static always_inline void gen_evmergelohi (DisasContext *ctx)
6334{
6335 if (unlikely(!ctx->spe_enabled)) {
6336 GEN_EXCP_NO_AP(ctx);
6337 return;
6338 }
6339#if defined(TARGET_PPC64)
a7812ae4
PB		 6340 TCGv t0 = tcg_temp_new();
6341 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6342 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6343 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6344 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6345 tcg_temp_free(t0);
6346 tcg_temp_free(t1);
6347#else
6348 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6349 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6350#endif
6351}
6352static always_inline void gen_evsplati (DisasContext *ctx)
6353{
38d14952 6354 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 6355
57951c27 6356#if defined(TARGET_PPC64)
38d14952 6357 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6358#else
6359 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6360 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6361#endif
6362}
b068d6a7 6363static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 6364{
38d14952 6365 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 6366
57951c27 6367#if defined(TARGET_PPC64)
38d14952 6368 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6369#else
6370 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6371 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6372#endif
0487d6a8
JM		 6373}
6374
57951c27
AJ		 6375static always_inline void gen_evsel (DisasContext *ctx)
6376{
6377 int l1 = gen_new_label();
6378 int l2 = gen_new_label();
6379 int l3 = gen_new_label();
6380 int l4 = gen_new_label();
a7812ae4 6381 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 6382#if defined(TARGET_PPC64)
a7812ae4
PB		 6383 TCGv t1 = tcg_temp_local_new();
6384 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 6385#endif
6386 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6387 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6388#if defined(TARGET_PPC64)
6389 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6390#else
6391 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6392#endif
6393 tcg_gen_br(l2);
6394 gen_set_label(l1);
6395#if defined(TARGET_PPC64)
6396 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6397#else
6398 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6399#endif
6400 gen_set_label(l2);
6401 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6402 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6403#if defined(TARGET_PPC64)
6404 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6405#else
6406 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6407#endif
6408 tcg_gen_br(l4);
6409 gen_set_label(l3);
6410#if defined(TARGET_PPC64)
6411 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6412#else
6413 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6414#endif
6415 gen_set_label(l4);
a7812ae4 6416 tcg_temp_free_i32(t0);
57951c27
AJ		 6417#if defined(TARGET_PPC64)
6418 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6419 tcg_temp_free(t1);
6420 tcg_temp_free(t2);
6421#endif
6422}
6423GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6424{
6425 gen_evsel(ctx);
6426}
6427GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6428{
6429 gen_evsel(ctx);
6430}
6431GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6432{
6433 gen_evsel(ctx);
6434}
6435GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6436{
6437 gen_evsel(ctx);
6438}
0487d6a8
JM		 6439
6440GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6441GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6442GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6443GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6444GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6445GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6446GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6447GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6448GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6449GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6450GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6451GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6452GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6453GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6454GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6455GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6456GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6457GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6458GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6459GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6460GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6461GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6462GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6463GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6464GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6465
6a6ae23f
AJ		 6466/* SPE load and stores */
6467static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
6468{
6469 target_ulong uimm = rB(ctx->opcode);
6470
6471 if (rA(ctx->opcode) == 0)
6472 tcg_gen_movi_tl(EA, uimm << sh);
6473 else
6474 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
0487d6a8 6475}
6a6ae23f
AJ		 6476
6477static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6478{
6479#if defined(TARGET_PPC64)
6480 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6481#else
6482 TCGv_i64 t0 = tcg_temp_new_i64();
6483 gen_qemu_ld64(t0, addr, ctx->mem_idx);
6484 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6485 tcg_gen_shri_i64(t0, t0, 32);
6486 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6487 tcg_temp_free_i64(t0);
6488#endif
0487d6a8 6489}
6a6ae23f
AJ		 6490
6491static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6492{
0487d6a8 6493#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6494 TCGv t0 = tcg_temp_new();
6495 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6496 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6497 tcg_gen_addi_tl(addr, addr, 4);
6498 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6499 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6500 tcg_temp_free(t0);
6501#else
6502 gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6503 tcg_gen_addi_tl(addr, addr, 4);
6504 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6505#endif
0487d6a8 6506}
6a6ae23f
AJ		 6507
6508static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6509{
6510 TCGv t0 = tcg_temp_new();
6511#if defined(TARGET_PPC64)
6512 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6513 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6514 tcg_gen_addi_tl(addr, addr, 2);
6515 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6516 tcg_gen_shli_tl(t0, t0, 32);
6517 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6518 tcg_gen_addi_tl(addr, addr, 2);
6519 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6520 tcg_gen_shli_tl(t0, t0, 16);
6521 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6522 tcg_gen_addi_tl(addr, addr, 2);
6523 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6524 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6525#else
6a6ae23f
AJ		 6526 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6527 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6528 tcg_gen_addi_tl(addr, addr, 2);
6529 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6530 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6531 tcg_gen_addi_tl(addr, addr, 2);
6532 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6533 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6534 tcg_gen_addi_tl(addr, addr, 2);
6535 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6536 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6537#endif
6a6ae23f 6538 tcg_temp_free(t0);
0487d6a8
JM		 6539}
6540
6a6ae23f
AJ		 6541static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6542{
6543 TCGv t0 = tcg_temp_new();
6544 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6545#if defined(TARGET_PPC64)
6546 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6547 tcg_gen_shli_tl(t0, t0, 16);
6548 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6549#else
6550 tcg_gen_shli_tl(t0, t0, 16);
6551 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6552 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6553#endif
6554 tcg_temp_free(t0);
0487d6a8
JM		 6555}
6556
6a6ae23f
AJ		 6557static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6558{
6559 TCGv t0 = tcg_temp_new();
6560 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6561#if defined(TARGET_PPC64)
6562 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6563 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6564#else
6565 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6566 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6567#endif
6568 tcg_temp_free(t0);
0487d6a8
JM		 6569}
6570
6a6ae23f
AJ		 6571static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6572{
6573 TCGv t0 = tcg_temp_new();
6574 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6575#if defined(TARGET_PPC64)
6576 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6577 tcg_gen_ext32u_tl(t0, t0);
6578 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6579#else
6580 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6581 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6582#endif
6583 tcg_temp_free(t0);
6584}
6585
6586static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6587{
6588 TCGv t0 = tcg_temp_new();
6589#if defined(TARGET_PPC64)
6590 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6591 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6592 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6593 tcg_gen_shli_tl(t0, t0, 16);
6594 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6595#else
6596 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6597 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6598 tcg_gen_addi_tl(addr, addr, 2);
6599 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6600 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6601#endif
6602 tcg_temp_free(t0);
6603}
6604
6605static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6606{
6607#if defined(TARGET_PPC64)
6608 TCGv t0 = tcg_temp_new();
6609 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6610 tcg_gen_addi_tl(addr, addr, 2);
6611 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6612 tcg_gen_shli_tl(t0, t0, 32);
6613 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6614 tcg_temp_free(t0);
6615#else
6616 gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6617 tcg_gen_addi_tl(addr, addr, 2);
6618 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6619#endif
6620}
6621
6622static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6623{
6624#if defined(TARGET_PPC64)
6625 TCGv t0 = tcg_temp_new();
6626 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6627 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6628 tcg_gen_addi_tl(addr, addr, 2);
6629 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6630 tcg_gen_shli_tl(t0, t0, 32);
6631 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6632 tcg_temp_free(t0);
6633#else
6634 gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6635 tcg_gen_addi_tl(addr, addr, 2);
6636 gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6637#endif
6638}
6639
6640static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6641{
6642 TCGv t0 = tcg_temp_new();
6643 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
0487d6a8 6644#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6645 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6646 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6647#else
6648 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6649 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6650#endif
6651 tcg_temp_free(t0);
6652}
6653
6654static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6655{
6656 TCGv t0 = tcg_temp_new();
6657#if defined(TARGET_PPC64)
6658 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6659 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6660 tcg_gen_shli_tl(t0, t0, 32);
6661 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6662 tcg_gen_addi_tl(addr, addr, 2);
6663 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6664 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6665 tcg_gen_shli_tl(t0, t0, 16);
6666 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6667#else
6668 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6669 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6670 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6671 tcg_gen_addi_tl(addr, addr, 2);
6672 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6673 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6674 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 6675#endif
6a6ae23f
AJ		 6676 tcg_temp_free(t0);
6677}
6678
6679static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6680{
6681#if defined(TARGET_PPC64)
6682 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
0487d6a8 6683#else
6a6ae23f
AJ		 6684 TCGv_i64 t0 = tcg_temp_new_i64();
6685 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6686 gen_qemu_st64(t0, addr, ctx->mem_idx);
6687 tcg_temp_free_i64(t0);
6688#endif
6689}
6690
6691static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6692{
0487d6a8 6693#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6694 TCGv t0 = tcg_temp_new();
6695 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6696 gen_qemu_st32(t0, addr, ctx->mem_idx);
6697 tcg_temp_free(t0);
6698#else
6699 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6700#endif
6701 tcg_gen_addi_tl(addr, addr, 4);
6702 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6703}
6704
6705static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6706{
6707 TCGv t0 = tcg_temp_new();
6708#if defined(TARGET_PPC64)
6709 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6710#else
6711 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6712#endif
6713 gen_qemu_st16(t0, addr, ctx->mem_idx);
6714 tcg_gen_addi_tl(addr, addr, 2);
6715#if defined(TARGET_PPC64)
6716 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6717 gen_qemu_st16(t0, addr, ctx->mem_idx);
6718#else
6719 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6720#endif
6721 tcg_gen_addi_tl(addr, addr, 2);
6722 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6723 gen_qemu_st16(t0, addr, ctx->mem_idx);
6724 tcg_temp_free(t0);
6725 tcg_gen_addi_tl(addr, addr, 2);
6726 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6727}
6728
6729static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6730{
6731 TCGv t0 = tcg_temp_new();
6732#if defined(TARGET_PPC64)
6733 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6734#else
6735 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6736#endif
6737 gen_qemu_st16(t0, addr, ctx->mem_idx);
6738 tcg_gen_addi_tl(addr, addr, 2);
6739 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6740 gen_qemu_st16(t0, addr, ctx->mem_idx);
6741 tcg_temp_free(t0);
6742}
6743
6744static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6745{
6746#if defined(TARGET_PPC64)
6747 TCGv t0 = tcg_temp_new();
6748 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6749 gen_qemu_st16(t0, addr, ctx->mem_idx);
6750 tcg_temp_free(t0);
6751#else
6752 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6753#endif
6754 tcg_gen_addi_tl(addr, addr, 2);
6755 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6756}
6757
6758static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6759{
6760#if defined(TARGET_PPC64)
6761 TCGv t0 = tcg_temp_new();
6762 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6763 gen_qemu_st32(t0, addr, ctx->mem_idx);
6764 tcg_temp_free(t0);
6765#else
6766 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6767#endif
6768}
6769
6770static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6771{
6772 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6773}
6774
6775#define GEN_SPEOP_LDST(name, opc2, sh) \
6776GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6777{ \
6778 TCGv t0; \
6779 if (unlikely(!ctx->spe_enabled)) { \
6780 GEN_EXCP_NO_AP(ctx); \
6781 return; \
6782 } \
6783 t0 = tcg_temp_new(); \
6784 if (Rc(ctx->opcode)) { \
6785 gen_addr_spe_imm_index(t0, ctx, sh); \
6786 } else { \
6787 gen_addr_reg_index(t0, ctx); \
6788 } \
6789 gen_op_##name(ctx, t0); \
6790 tcg_temp_free(t0); \
6791}
6792
6793GEN_SPEOP_LDST(evldd, 0x00, 3);
6794GEN_SPEOP_LDST(evldw, 0x01, 3);
6795GEN_SPEOP_LDST(evldh, 0x02, 3);
6796GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
6797GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
6798GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
6799GEN_SPEOP_LDST(evlwhe, 0x08, 2);
6800GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
6801GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
6802GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
6803GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
6804
6805GEN_SPEOP_LDST(evstdd, 0x10, 3);
6806GEN_SPEOP_LDST(evstdw, 0x11, 3);
6807GEN_SPEOP_LDST(evstdh, 0x12, 3);
6808GEN_SPEOP_LDST(evstwhe, 0x18, 2);
6809GEN_SPEOP_LDST(evstwho, 0x1A, 2);
6810GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
6811GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 6812
6813/* Multiply and add - TODO */
6814#if 0
6815GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6816GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6817GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6818GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6819GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6820GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6821GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6822GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6823GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6824GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6825GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6826GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6827
6828GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6829GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6830GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6831GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6832GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6833GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6834GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6835GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6836GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6837GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6838GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6839GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6840GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6841GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6842
6843GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6844GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6845GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6846GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6847GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6848GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6849
6850GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6851GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6852GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6853GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6854GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6855GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6856GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6857GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6858GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6859GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6860GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6861GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6862
6863GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6864GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6865GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6866GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6867GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6868
6869GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6870GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6871GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6872GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6873GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6874GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6875GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6876GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6877GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6878GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6879GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6880GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6881
6882GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6883GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6884GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6885GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6886GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6887#endif
6888
6889/*** SPE floating-point extension ***/
1c97856d
AJ		 6890#if defined(TARGET_PPC64)
6891#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 6892static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6893{ \
1c97856d
AJ		 6894 TCGv_i32 t0; \
6895 TCGv t1; \
6896 t0 = tcg_temp_new_i32(); \
6897 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6898 gen_helper_##name(t0, t0); \
6899 t1 = tcg_temp_new(); \
6900 tcg_gen_extu_i32_tl(t1, t0); \
6901 tcg_temp_free_i32(t0); \
6902 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6903 0xFFFFFFFF00000000ULL); \
6904 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6905 tcg_temp_free(t1); \
0487d6a8 6906}
1c97856d
AJ		 6907#define GEN_SPEFPUOP_CONV_32_64(name) \
6908static always_inline void gen_##name (DisasContext *ctx) \
6909{ \
6910 TCGv_i32 t0; \
6911 TCGv t1; \
6912 t0 = tcg_temp_new_i32(); \
6913 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
6914 t1 = tcg_temp_new(); \
6915 tcg_gen_extu_i32_tl(t1, t0); \
6916 tcg_temp_free_i32(t0); \
6917 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6918 0xFFFFFFFF00000000ULL); \
6919 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6920 tcg_temp_free(t1); \
6921}
6922#define GEN_SPEFPUOP_CONV_64_32(name) \
6923static always_inline void gen_##name (DisasContext *ctx) \
6924{ \
6925 TCGv_i32 t0 = tcg_temp_new_i32(); \
6926 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6927 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
6928 tcg_temp_free_i32(t0); \
6929}
6930#define GEN_SPEFPUOP_CONV_64_64(name) \
6931static always_inline void gen_##name (DisasContext *ctx) \
6932{ \
6933 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6934}
6935#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 6936static always_inline void gen_##name (DisasContext *ctx) \
6937{ \
1c97856d
AJ		 6938 TCGv_i32 t0, t1; \
6939 TCGv_i64 t2; \
57951c27
AJ		 6940 if (unlikely(!ctx->spe_enabled)) { \
6941 GEN_EXCP_NO_AP(ctx); \
6942 return; \
6943 } \
1c97856d
AJ		 6944 t0 = tcg_temp_new_i32(); \
6945 t1 = tcg_temp_new_i32(); \
6946 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6947 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6948 gen_helper_##name(t0, t0, t1); \
6949 tcg_temp_free_i32(t1); \
6950 t2 = tcg_temp_new(); \
6951 tcg_gen_extu_i32_tl(t2, t0); \
6952 tcg_temp_free_i32(t0); \
6953 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6954 0xFFFFFFFF00000000ULL); \
6955 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
6956 tcg_temp_free(t2); \
57951c27 6957}
1c97856d 6958#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 6959static always_inline void gen_##name (DisasContext *ctx) \
6960{ \
6961 if (unlikely(!ctx->spe_enabled)) { \
6962 GEN_EXCP_NO_AP(ctx); \
6963 return; \
6964 } \
1c97856d
AJ		 6965 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6966 cpu_gpr[rB(ctx->opcode)]); \
57951c27 6967}
1c97856d 6968#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 6969static always_inline void gen_##name (DisasContext *ctx) \
6970{ \
1c97856d 6971 TCGv_i32 t0, t1; \
57951c27
AJ		 6972 if (unlikely(!ctx->spe_enabled)) { \
6973 GEN_EXCP_NO_AP(ctx); \
6974 return; \
6975 } \
1c97856d
AJ		 6976 t0 = tcg_temp_new_i32(); \
6977 t1 = tcg_temp_new_i32(); \
6978 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6979 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6980 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
6981 tcg_temp_free_i32(t0); \
6982 tcg_temp_free_i32(t1); \
6983}
6984#define GEN_SPEFPUOP_COMP_64(name) \
6985static always_inline void gen_##name (DisasContext *ctx) \
6986{ \
6987 if (unlikely(!ctx->spe_enabled)) { \
6988 GEN_EXCP_NO_AP(ctx); \
6989 return; \
6990 } \
6991 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
6992 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6993}
6994#else
6995#define GEN_SPEFPUOP_CONV_32_32(name) \
6996static always_inline void gen_##name (DisasContext *ctx) \
6997{ \
6998 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 6999}
1c97856d
AJ		 7000#define GEN_SPEFPUOP_CONV_32_64(name) \
7001static always_inline void gen_##name (DisasContext *ctx) \
7002{ \
7003 TCGv_i64 t0 = tcg_temp_new_i64(); \
7004 gen_load_gpr64(t0, rB(ctx->opcode)); \
7005 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7006 tcg_temp_free_i64(t0); \
7007}
7008#define GEN_SPEFPUOP_CONV_64_32(name) \
7009static always_inline void gen_##name (DisasContext *ctx) \
7010{ \
7011 TCGv_i64 t0 = tcg_temp_new_i64(); \
7012 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7013 gen_store_gpr64(rD(ctx->opcode), t0); \
7014 tcg_temp_free_i64(t0); \
7015}
7016#define GEN_SPEFPUOP_CONV_64_64(name) \
7017static always_inline void gen_##name (DisasContext *ctx) \
7018{ \
7019 TCGv_i64 t0 = tcg_temp_new_i64(); \
7020 gen_load_gpr64(t0, rB(ctx->opcode)); \
7021 gen_helper_##name(t0, t0); \
7022 gen_store_gpr64(rD(ctx->opcode), t0); \
7023 tcg_temp_free_i64(t0); \
7024}
7025#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7026static always_inline void gen_##name (DisasContext *ctx) \
7027{ \
7028 if (unlikely(!ctx->spe_enabled)) { \
7029 GEN_EXCP_NO_AP(ctx); \
7030 return; \
7031 } \
7032 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7033 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7034}
7035#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7036static always_inline void gen_##name (DisasContext *ctx) \
7037{ \
7038 TCGv_i64 t0, t1; \
7039 if (unlikely(!ctx->spe_enabled)) { \
7040 GEN_EXCP_NO_AP(ctx); \
7041 return; \
7042 } \
7043 t0 = tcg_temp_new_i64(); \
7044 t1 = tcg_temp_new_i64(); \
7045 gen_load_gpr64(t0, rA(ctx->opcode)); \
7046 gen_load_gpr64(t1, rB(ctx->opcode)); \
7047 gen_helper_##name(t0, t0, t1); \
7048 gen_store_gpr64(rD(ctx->opcode), t0); \
7049 tcg_temp_free_i64(t0); \
7050 tcg_temp_free_i64(t1); \
7051}
7052#define GEN_SPEFPUOP_COMP_32(name) \
7053static always_inline void gen_##name (DisasContext *ctx) \
7054{ \
7055 if (unlikely(!ctx->spe_enabled)) { \
7056 GEN_EXCP_NO_AP(ctx); \
7057 return; \
7058 } \
7059 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7060 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7061}
7062#define GEN_SPEFPUOP_COMP_64(name) \
7063static always_inline void gen_##name (DisasContext *ctx) \
7064{ \
7065 TCGv_i64 t0, t1; \
7066 if (unlikely(!ctx->spe_enabled)) { \
7067 GEN_EXCP_NO_AP(ctx); \
7068 return; \
7069 } \
7070 t0 = tcg_temp_new_i64(); \
7071 t1 = tcg_temp_new_i64(); \
7072 gen_load_gpr64(t0, rA(ctx->opcode)); \
7073 gen_load_gpr64(t1, rB(ctx->opcode)); \
7074 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7075 tcg_temp_free_i64(t0); \
7076 tcg_temp_free_i64(t1); \
7077}
7078#endif
57951c27 7079
0487d6a8
JM		 7080/* Single precision floating-point vectors operations */
7081/* Arithmetic */
1c97856d
AJ		 7082GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7083GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7084GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7085GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7086static always_inline void gen_evfsabs (DisasContext *ctx)
7087{
7088 if (unlikely(!ctx->spe_enabled)) {
7089 GEN_EXCP_NO_AP(ctx);
7090 return;
7091 }
7092#if defined(TARGET_PPC64)
7093 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7094#else
7095 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7096 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7097#endif
7098}
7099static always_inline void gen_evfsnabs (DisasContext *ctx)
7100{
7101 if (unlikely(!ctx->spe_enabled)) {
7102 GEN_EXCP_NO_AP(ctx);
7103 return;
7104 }
7105#if defined(TARGET_PPC64)
7106 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7107#else
7108 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7109 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7110#endif
7111}
7112static always_inline void gen_evfsneg (DisasContext *ctx)
7113{
7114 if (unlikely(!ctx->spe_enabled)) {
7115 GEN_EXCP_NO_AP(ctx);
7116 return;
7117 }
7118#if defined(TARGET_PPC64)
7119 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7120#else
7121 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7122 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7123#endif
7124}
7125
0487d6a8 7126/* Conversion */
1c97856d
AJ		 7127GEN_SPEFPUOP_CONV_64_64(evfscfui);
7128GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7129GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7130GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7131GEN_SPEFPUOP_CONV_64_64(evfsctui);
7132GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7133GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7134GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7135GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7136GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7137
0487d6a8 7138/* Comparison */
1c97856d
AJ		 7139GEN_SPEFPUOP_COMP_64(evfscmpgt);
7140GEN_SPEFPUOP_COMP_64(evfscmplt);
7141GEN_SPEFPUOP_COMP_64(evfscmpeq);
7142GEN_SPEFPUOP_COMP_64(evfststgt);
7143GEN_SPEFPUOP_COMP_64(evfststlt);
7144GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7145
7146/* Opcodes definitions */
7147GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7148GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7149GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7150GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7151GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7152GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7153GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7154GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7155GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7156GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7157GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7158GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7159GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7160GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7161
7162/* Single precision floating-point operations */
7163/* Arithmetic */
1c97856d
AJ		 7164GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7165GEN_SPEFPUOP_ARITH2_32_32(efssub);
7166GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7167GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7168static always_inline void gen_efsabs (DisasContext *ctx)
7169{
7170 if (unlikely(!ctx->spe_enabled)) {
7171 GEN_EXCP_NO_AP(ctx);
7172 return;
7173 }
7174 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7175}
7176static always_inline void gen_efsnabs (DisasContext *ctx)
7177{
7178 if (unlikely(!ctx->spe_enabled)) {
7179 GEN_EXCP_NO_AP(ctx);
7180 return;
7181 }
7182 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7183}
7184static always_inline void gen_efsneg (DisasContext *ctx)
7185{
7186 if (unlikely(!ctx->spe_enabled)) {
7187 GEN_EXCP_NO_AP(ctx);
7188 return;
7189 }
7190 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7191}
7192
0487d6a8 7193/* Conversion */
1c97856d
AJ		 7194GEN_SPEFPUOP_CONV_32_32(efscfui);
7195GEN_SPEFPUOP_CONV_32_32(efscfsi);
7196GEN_SPEFPUOP_CONV_32_32(efscfuf);
7197GEN_SPEFPUOP_CONV_32_32(efscfsf);
7198GEN_SPEFPUOP_CONV_32_32(efsctui);
7199GEN_SPEFPUOP_CONV_32_32(efsctsi);
7200GEN_SPEFPUOP_CONV_32_32(efsctuf);
7201GEN_SPEFPUOP_CONV_32_32(efsctsf);
7202GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7203GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7204GEN_SPEFPUOP_CONV_32_64(efscfd);
7205
0487d6a8 7206/* Comparison */
1c97856d
AJ		 7207GEN_SPEFPUOP_COMP_32(efscmpgt);
7208GEN_SPEFPUOP_COMP_32(efscmplt);
7209GEN_SPEFPUOP_COMP_32(efscmpeq);
7210GEN_SPEFPUOP_COMP_32(efststgt);
7211GEN_SPEFPUOP_COMP_32(efststlt);
7212GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7213
7214/* Opcodes definitions */
05332d70 7215GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7216GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7217GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7218GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7219GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7220GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7221GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7222GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7223GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7224GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7225GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7226GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7227GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7228GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7229
7230/* Double precision floating-point operations */
7231/* Arithmetic */
1c97856d
AJ		 7232GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7233GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7234GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7235GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7236static always_inline void gen_efdabs (DisasContext *ctx)
7237{
7238 if (unlikely(!ctx->spe_enabled)) {
7239 GEN_EXCP_NO_AP(ctx);
7240 return;
7241 }
7242#if defined(TARGET_PPC64)
7243 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7244#else
7245 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7246#endif
7247}
7248static always_inline void gen_efdnabs (DisasContext *ctx)
7249{
7250 if (unlikely(!ctx->spe_enabled)) {
7251 GEN_EXCP_NO_AP(ctx);
7252 return;
7253 }
7254#if defined(TARGET_PPC64)
7255 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7256#else
7257 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7258#endif
7259}
7260static always_inline void gen_efdneg (DisasContext *ctx)
7261{
7262 if (unlikely(!ctx->spe_enabled)) {
7263 GEN_EXCP_NO_AP(ctx);
7264 return;
7265 }
7266#if defined(TARGET_PPC64)
7267 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7268#else
7269 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7270#endif
7271}
7272
0487d6a8 7273/* Conversion */
1c97856d
AJ		 7274GEN_SPEFPUOP_CONV_64_32(efdcfui);
7275GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7276GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7277GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7278GEN_SPEFPUOP_CONV_32_64(efdctui);
7279GEN_SPEFPUOP_CONV_32_64(efdctsi);
7280GEN_SPEFPUOP_CONV_32_64(efdctuf);
7281GEN_SPEFPUOP_CONV_32_64(efdctsf);
7282GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7283GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7284GEN_SPEFPUOP_CONV_64_32(efdcfs);
7285GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7286GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7287GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7288GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 7289
0487d6a8 7290/* Comparison */
1c97856d
AJ		 7291GEN_SPEFPUOP_COMP_64(efdcmpgt);
7292GEN_SPEFPUOP_COMP_64(efdcmplt);
7293GEN_SPEFPUOP_COMP_64(efdcmpeq);
7294GEN_SPEFPUOP_COMP_64(efdtstgt);
7295GEN_SPEFPUOP_COMP_64(efdtstlt);
7296GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 7297
7298/* Opcodes definitions */
7299GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7300GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7301GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7302GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7303GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7304GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7305GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7306GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7307GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7308GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7309GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7310GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7311GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7312GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7313GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7314GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 7315
79aceca5
FB		 7316/* End opcode list */
7317GEN_OPCODE_MARK(end);
7318
3fc6c082 7319#include "translate_init.c"
0411a972 7320#include "helper_regs.h"
79aceca5 7321
9a64fbe4 7322/*****************************************************************************/
3fc6c082 7323/* Misc PowerPC helpers */
36081602
JM		 7324void cpu_dump_state (CPUState *env, FILE *f,
7325 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7326 int flags)
79aceca5 7327{
3fc6c082
FB		 7328#define RGPL 4
7329#define RFPL 4
3fc6c082 7330
79aceca5
FB		 7331 int i;
7332
077fc206 7333 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 7334 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 7335 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7336 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 7337#if !defined(NO_TIMER_DUMP)
077fc206 7338 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 7339#if !defined(CONFIG_USER_ONLY)
7340 "DECR %08x"
7341#endif
7342 "\n",
077fc206 7343 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 7344#if !defined(CONFIG_USER_ONLY)
7345 , cpu_ppc_load_decr(env)
7346#endif
7347 );
077fc206 7348#endif
76a66253 7349 for (i = 0; i < 32; i++) {
3fc6c082
FB		 7350 if ((i & (RGPL - 1)) == 0)
7351 cpu_fprintf(f, "GPR%02d", i);
6b542af7 7352 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 7353 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 7354 cpu_fprintf(f, "\n");
76a66253 7355 }
3fc6c082 7356 cpu_fprintf(f, "CR ");
76a66253 7357 for (i = 0; i < 8; i++)
7fe48483
FB		 7358 cpu_fprintf(f, "%01x", env->crf[i]);
7359 cpu_fprintf(f, " [");
76a66253
JM		 7360 for (i = 0; i < 8; i++) {
7361 char a = '-';
7362 if (env->crf[i] & 0x08)
7363 a = 'L';
7364 else if (env->crf[i] & 0x04)
7365 a = 'G';
7366 else if (env->crf[i] & 0x02)
7367 a = 'E';
7fe48483 7368 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 7369 }
6b542af7 7370 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 7371 for (i = 0; i < 32; i++) {
7372 if ((i & (RFPL - 1)) == 0)
7373 cpu_fprintf(f, "FPR%02d", i);
26a76461 7374 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 7375 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 7376 cpu_fprintf(f, "\n");
79aceca5 7377 }
f2e63a42 7378#if !defined(CONFIG_USER_ONLY)
6b542af7 7379 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 7380 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 7381#endif
79aceca5 7382
3fc6c082
FB		 7383#undef RGPL
7384#undef RFPL
79aceca5
FB		 7385}
7386
76a66253
JM		 7387void cpu_dump_statistics (CPUState *env, FILE*f,
7388 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7389 int flags)
7390{
7391#if defined(DO_PPC_STATISTICS)
7392 opc_handler_t **t1, **t2, **t3, *handler;
7393 int op1, op2, op3;
7394
7395 t1 = env->opcodes;
7396 for (op1 = 0; op1 < 64; op1++) {
7397 handler = t1[op1];
7398 if (is_indirect_opcode(handler)) {
7399 t2 = ind_table(handler);
7400 for (op2 = 0; op2 < 32; op2++) {
7401 handler = t2[op2];
7402 if (is_indirect_opcode(handler)) {
7403 t3 = ind_table(handler);
7404 for (op3 = 0; op3 < 32; op3++) {
7405 handler = t3[op3];
7406 if (handler->count == 0)
7407 continue;
7408 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7409 "%016llx %lld\n",
7410 op1, op2, op3, op1, (op3 << 5) | op2,
7411 handler->oname,
7412 handler->count, handler->count);
7413 }
7414 } else {
7415 if (handler->count == 0)
7416 continue;
7417 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7418 "%016llx %lld\n",
7419 op1, op2, op1, op2, handler->oname,
7420 handler->count, handler->count);
7421 }
7422 }
7423 } else {
7424 if (handler->count == 0)
7425 continue;
7426 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7427 op1, op1, handler->oname,
7428 handler->count, handler->count);
7429 }
7430 }
7431#endif
7432}
7433
9a64fbe4 7434/*****************************************************************************/
2cfc5f17
TS		 7435static always_inline void gen_intermediate_code_internal (CPUState *env,
7436 TranslationBlock *tb,
7437 int search_pc)
79aceca5 7438{
9fddaa0c 7439 DisasContext ctx, *ctxp = &ctx;
79aceca5 7440 opc_handler_t **table, *handler;
0fa85d43 7441 target_ulong pc_start;
79aceca5 7442 uint16_t *gen_opc_end;
056401ea 7443 int supervisor, little_endian;
a1d1bb31 7444 CPUBreakpoint *bp;
79aceca5 7445 int j, lj = -1;
2e70f6ef
PB		 7446 int num_insns;
7447 int max_insns;
79aceca5
FB		 7448
7449 pc_start = tb->pc;
79aceca5 7450 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 7451#if defined(OPTIMIZE_FPRF_UPDATE)
7452 gen_fprf_ptr = gen_fprf_buf;
7453#endif
046d6672 7454 ctx.nip = pc_start;
79aceca5 7455 ctx.tb = tb;
e1833e1f 7456 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 7457 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 7458 supervisor = env->mmu_idx;
7459#if !defined(CONFIG_USER_ONLY)
2857068e 7460 ctx.supervisor = supervisor;
d9bce9d9 7461#endif
056401ea 7462 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 7463#if defined(TARGET_PPC64)
7464 ctx.sf_mode = msr_sf;
056401ea 7465 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 7466#else
056401ea 7467 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 7468#endif
3cc62370 7469 ctx.fpu_enabled = msr_fp;
a9d9eb8f 7470 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 7471 ctx.spe_enabled = msr_spe;
7472 else
7473 ctx.spe_enabled = 0;
a9d9eb8f
JM		 7474 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7475 ctx.altivec_enabled = msr_vr;
7476 else
7477 ctx.altivec_enabled = 0;
d26bfc9a 7478 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 7479 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 7480 else
8cbcb4fa 7481 ctx.singlestep_enabled = 0;
d26bfc9a 7482 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 7483 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7484 if (unlikely(env->singlestep_enabled))
7485 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 7486#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 7487 /* Single step trace mode */
7488 msr_se = 1;
7489#endif
2e70f6ef
PB		 7490 num_insns = 0;
7491 max_insns = tb->cflags & CF_COUNT_MASK;
7492 if (max_insns == 0)
7493 max_insns = CF_COUNT_MASK;
7494
7495 gen_icount_start();
9a64fbe4 7496 /* Set env in case of segfault during code fetch */
e1833e1f 7497 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 7498 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7499 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 7500 if (bp->pc == ctx.nip) {
5fafdf24 7501 gen_update_nip(&ctx, ctx.nip);
64adab3f 7502 gen_helper_raise_debug();
ea4e754f
FB		 7503 break;
7504 }
7505 }
7506 }
76a66253 7507 if (unlikely(search_pc)) {
79aceca5
FB		 7508 j = gen_opc_ptr - gen_opc_buf;
7509 if (lj < j) {
7510 lj++;
7511 while (lj < j)
7512 gen_opc_instr_start[lj++] = 0;
046d6672 7513 gen_opc_pc[lj] = ctx.nip;
79aceca5 7514 gen_opc_instr_start[lj] = 1;
2e70f6ef 7515 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 7516 }
7517 }
9fddaa0c
FB		 7518#if defined PPC_DEBUG_DISAS
7519 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 7520 fprintf(logfile, "----------------\n");
1b9eb036 7521 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 7522 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 7523 }
7524#endif
2e70f6ef
PB		 7525 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7526 gen_io_start();
056401ea
JM		 7527 if (unlikely(little_endian)) {
7528 ctx.opcode = bswap32(ldl_code(ctx.nip));
7529 } else {
7530 ctx.opcode = ldl_code(ctx.nip);
111bfab3 7531 }
9fddaa0c
FB		 7532#if defined PPC_DEBUG_DISAS
7533 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 7534 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 7535 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 7536 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 7537 }
7538#endif
046d6672 7539 ctx.nip += 4;
3fc6c082 7540 table = env->opcodes;
2e70f6ef 7541 num_insns++;
79aceca5
FB		 7542 handler = table[opc1(ctx.opcode)];
7543 if (is_indirect_opcode(handler)) {
7544 table = ind_table(handler);
7545 handler = table[opc2(ctx.opcode)];
7546 if (is_indirect_opcode(handler)) {
7547 table = ind_table(handler);
7548 handler = table[opc3(ctx.opcode)];
7549 }
7550 }
7551 /* Is opcode *REALLY* valid ? */
76a66253 7552 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7553 if (loglevel != 0) {
76a66253 7554 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 7555 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 7556 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7557 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7558 } else {
7559 printf("invalid/unsupported opcode: "
6b542af7 7560 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 7561 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7562 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7563 }
76a66253
JM		 7564 } else {
7565 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7566 if (loglevel != 0) {
79aceca5 7567 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 7568 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 7569 ctx.opcode & handler->inval, opc1(ctx.opcode),
7570 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7571 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7572 } else {
7573 printf("invalid bits: %08x for opcode: "
6b542af7 7574 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 7575 ctx.opcode & handler->inval, opc1(ctx.opcode),
7576 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7577 ctx.opcode, ctx.nip - 4);
76a66253 7578 }
e1833e1f 7579 GEN_EXCP_INVAL(ctxp);
4b3686fa 7580 break;
79aceca5 7581 }
79aceca5 7582 }
4b3686fa 7583 (*(handler->handler))(&ctx);
76a66253
JM		 7584#if defined(DO_PPC_STATISTICS)
7585 handler->count++;
7586#endif
9a64fbe4 7587 /* Check trace mode exceptions */
8cbcb4fa
AJ		 7588 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7589 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7590 ctx.exception != POWERPC_SYSCALL &&
7591 ctx.exception != POWERPC_EXCP_TRAP &&
7592 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 7593 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 7594 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 7595 (env->singlestep_enabled) ||
7596 num_insns >= max_insns)) {
d26bfc9a
JM		 7597 /* if we reach a page boundary or are single stepping, stop
7598 * generation
7599 */
8dd4983c 7600 break;
76a66253 7601 }
3fc6c082
FB		 7602#if defined (DO_SINGLE_STEP)
7603 break;
7604#endif
7605 }
2e70f6ef
PB		 7606 if (tb->cflags & CF_LAST_IO)
7607 gen_io_end();
e1833e1f 7608 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7609 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7610 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 7611 if (unlikely(env->singlestep_enabled)) {
7612 gen_update_nip(&ctx, ctx.nip);
64adab3f 7613 gen_helper_raise_debug();
8cbcb4fa 7614 }
76a66253 7615 /* Generate the return instruction */
57fec1fe 7616 tcg_gen_exit_tb(0);
9a64fbe4 7617 }
2e70f6ef 7618 gen_icount_end(tb, num_insns);
79aceca5 7619 *gen_opc_ptr = INDEX_op_end;
76a66253 7620 if (unlikely(search_pc)) {
9a64fbe4
FB		 7621 j = gen_opc_ptr - gen_opc_buf;
7622 lj++;
7623 while (lj <= j)
7624 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7625 } else {
046d6672 7626 tb->size = ctx.nip - pc_start;
2e70f6ef 7627 tb->icount = num_insns;
9a64fbe4 7628 }
d9bce9d9 7629#if defined(DEBUG_DISAS)
9fddaa0c 7630 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7631 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7632 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7633 }
7634 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7635 int flags;
237c0af0 7636 flags = env->bfd_mach;
056401ea 7637 flags |= little_endian << 16;
0fa85d43 7638 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7639 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7640 fprintf(logfile, "\n");
9fddaa0c 7641 }
79aceca5 7642#endif
79aceca5
FB		 7643}
7644
2cfc5f17 7645void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 7646{
2cfc5f17 7647 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 7648}
7649
2cfc5f17 7650void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7651{
2cfc5f17 7652 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7653}
d2856f1a
AJ		 7654
7655void gen_pc_load(CPUState *env, TranslationBlock *tb,
7656 unsigned long searched_pc, int pc_pos, void *puc)
7657{
d2856f1a 7658 env->nip = gen_opc_pc[pc_pos];
d2856f1a 7659}
Qemu copy for testing