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PPC: convert effective address computation to TCG
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
f10dc08e 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
79aceca5 32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
79aceca5 38//#define DO_SINGLE_STEP
9fddaa0c 39//#define PPC_DEBUG_DISAS
76a66253 40//#define DO_PPC_STATISTICS
7c58044c 41//#define OPTIMIZE_FPRF_UPDATE
79aceca5 42
a750fc0b
JM		 43/*****************************************************************************/
44/* Code translation helpers */
c53be334 45
f78fb44e
AJ		 46/* global register indexes */
47static TCGv cpu_env;
1d542695 48static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 49#if !defined(TARGET_PPC64)
1d542695 50 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 51#endif
a5e26afa 52 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
f78fb44e
AJ		 55static TCGv cpu_gpr[32];
56#if !defined(TARGET_PPC64)
57static TCGv cpu_gprh[32];
58#endif
a5e26afa 59static TCGv cpu_fpr[32];
1d542695 60static TCGv cpu_avrh[32], cpu_avrl[32];
47e4661c 61static TCGv cpu_crf[8];
bd568f18 62static TCGv cpu_nip;
cfdcd37a
AJ		 63static TCGv cpu_ctr;
64static TCGv cpu_lr;
f78fb44e
AJ		 65
66/* dyngen register indexes */
67static TCGv cpu_T[3];
68#if defined(TARGET_PPC64)
69#define cpu_T64 cpu_T
70#else
71static TCGv cpu_T64[3];
72#endif
a5e26afa 73static TCGv cpu_FT[3];
1d542695 74static TCGv cpu_AVRh[3], cpu_AVRl[3];
2e70f6ef
PB		 75
76#include "gen-icount.h"
77
78void ppc_translate_init(void)
79{
f78fb44e
AJ		 80 int i;
81 char* p;
b2437bf2 82 static int done_init = 0;
f78fb44e 83
2e70f6ef
PB		 84 if (done_init)
85 return;
f78fb44e 86
2e70f6ef 87 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
1c73fe5b
AJ		 88#if TARGET_LONG_BITS > HOST_LONG_BITS
89 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
90 TCG_AREG0, offsetof(CPUState, t0), "T0");
91 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
92 TCG_AREG0, offsetof(CPUState, t1), "T1");
93 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
94 TCG_AREG0, offsetof(CPUState, t2), "T2");
95#else
96 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
97 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
98 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
99#endif
f78fb44e
AJ		 100#if !defined(TARGET_PPC64)
101 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 102 TCG_AREG0, offsetof(CPUState, t0_64),
f78fb44e
AJ		 103 "T0_64");
104 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 105 TCG_AREG0, offsetof(CPUState, t1_64),
f78fb44e
AJ		 106 "T1_64");
107 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 108 TCG_AREG0, offsetof(CPUState, t2_64),
f78fb44e
AJ		 109 "T2_64");
110#endif
a5e26afa
AJ		 111
112 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
113 offsetof(CPUState, ft0), "FT0");
114 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
115 offsetof(CPUState, ft1), "FT1");
116 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
117 offsetof(CPUState, ft2), "FT2");
118
1d542695
AJ		 119 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
120 offsetof(CPUState, avr0.u64[0]), "AVR0H");
121 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
122 offsetof(CPUState, avr0.u64[1]), "AVR0L");
123 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124 offsetof(CPUState, avr1.u64[0]), "AVR1H");
125 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126 offsetof(CPUState, avr1.u64[1]), "AVR1L");
127 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128 offsetof(CPUState, avr2.u64[0]), "AVR2H");
129 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
130 offsetof(CPUState, avr2.u64[1]), "AVR2L");
131
f78fb44e 132 p = cpu_reg_names;
47e4661c
AJ		 133
134 for (i = 0; i < 8; i++) {
135 sprintf(p, "crf%d", i);
136 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
137 offsetof(CPUState, crf[i]), p);
138 p += 5;
139 }
140
f78fb44e
AJ		 141 for (i = 0; i < 32; i++) {
142 sprintf(p, "r%d", i);
143 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
144 offsetof(CPUState, gpr[i]), p);
145 p += (i < 10) ? 3 : 4;
146#if !defined(TARGET_PPC64)
147 sprintf(p, "r%dH", i);
148 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
149 offsetof(CPUState, gprh[i]), p);
150 p += (i < 10) ? 4 : 5;
151#endif
1d542695 152
a5e26afa
AJ		 153 sprintf(p, "fp%d", i);
154 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
155 offsetof(CPUState, fpr[i]), p);
ec1ac72d 156 p += (i < 10) ? 4 : 5;
a5e26afa 157
1d542695
AJ		 158 sprintf(p, "avr%dH", i);
159 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
160 offsetof(CPUState, avr[i].u64[0]), p);
161 p += (i < 10) ? 6 : 7;
ec1ac72d 162
1d542695
AJ		 163 sprintf(p, "avr%dL", i);
164 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
165 offsetof(CPUState, avr[i].u64[1]), p);
166 p += (i < 10) ? 6 : 7;
f78fb44e 167 }
f10dc08e 168
bd568f18
AJ		 169 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
170 offsetof(CPUState, nip), "nip");
171
cfdcd37a
AJ		 172 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
173 offsetof(CPUState, ctr), "ctr");
174
175 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
176 offsetof(CPUState, lr), "lr");
177
f10dc08e
AJ		 178 /* register helpers */
179#undef DEF_HELPER
180#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
181#include "helper.h"
182
2e70f6ef
PB		 183 done_init = 1;
184}
185
7c58044c
JM		 186#if defined(OPTIMIZE_FPRF_UPDATE)
187static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
188static uint16_t **gen_fprf_ptr;
189#endif
79aceca5 190
79aceca5
FB		 191/* internal defines */
192typedef struct DisasContext {
193 struct TranslationBlock *tb;
0fa85d43 194 target_ulong nip;
79aceca5 195 uint32_t opcode;
9a64fbe4 196 uint32_t exception;
3cc62370
FB		 197 /* Routine used to access memory */
198 int mem_idx;
199 /* Translation flags */
9a64fbe4 200#if !defined(CONFIG_USER_ONLY)
79aceca5 201 int supervisor;
d9bce9d9
JM		 202#endif
203#if defined(TARGET_PPC64)
204 int sf_mode;
9a64fbe4 205#endif
3cc62370 206 int fpu_enabled;
a9d9eb8f 207 int altivec_enabled;
0487d6a8 208 int spe_enabled;
3fc6c082 209 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 210 int singlestep_enabled;
d63001d1 211 int dcache_line_size;
79aceca5
FB		 212} DisasContext;
213
3fc6c082 214struct opc_handler_t {
79aceca5
FB		 215 /* invalid bits */
216 uint32_t inval;
9a64fbe4 217 /* instruction type */
0487d6a8 218 uint64_t type;
79aceca5
FB		 219 /* handler */
220 void (*handler)(DisasContext *ctx);
a750fc0b 221#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 222 const char *oname;
a750fc0b
JM		 223#endif
224#if defined(DO_PPC_STATISTICS)
76a66253
JM		 225 uint64_t count;
226#endif
3fc6c082 227};
79aceca5 228
b068d6a7 229static always_inline void gen_set_Rc0 (DisasContext *ctx)
76a66253 230{
d9bce9d9
JM		 231#if defined(TARGET_PPC64)
232 if (ctx->sf_mode)
233 gen_op_cmpi_64(0);
234 else
235#endif
236 gen_op_cmpi(0);
76a66253
JM		 237 gen_op_set_Rc0();
238}
239
7c58044c
JM		 240static always_inline void gen_reset_fpstatus (void)
241{
242#ifdef CONFIG_SOFTFLOAT
243 gen_op_reset_fpstatus();
244#endif
245}
246
247static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
248{
249 if (set_fprf != 0) {
250 /* This case might be optimized later */
251#if defined(OPTIMIZE_FPRF_UPDATE)
252 *gen_fprf_ptr++ = gen_opc_ptr;
253#endif
254 gen_op_compute_fprf(1);
255 if (unlikely(set_rc))
47e4661c 256 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 257 gen_op_float_check_status();
258 } else if (unlikely(set_rc)) {
259 /* We always need to compute fpcc */
260 gen_op_compute_fprf(0);
47e4661c 261 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 262 if (set_fprf)
263 gen_op_float_check_status();
264 }
265}
266
267static always_inline void gen_optimize_fprf (void)
268{
269#if defined(OPTIMIZE_FPRF_UPDATE)
270 uint16_t **ptr;
271
272 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
273 *ptr = INDEX_op_nop1;
274 gen_fprf_ptr = gen_fprf_buf;
275#endif
276}
277
b068d6a7 278static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 279{
280#if defined(TARGET_PPC64)
281 if (ctx->sf_mode)
bd568f18 282 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 283 else
284#endif
bd568f18 285 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 286}
287
e1833e1f 288#define GEN_EXCP(ctx, excp, error) \
79aceca5 289do { \
e1833e1f 290 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 291 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 292 } \
293 gen_op_raise_exception_err((excp), (error)); \
294 ctx->exception = (excp); \
79aceca5
FB		 295} while (0)
296
e1833e1f
JM		 297#define GEN_EXCP_INVAL(ctx) \
298GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
299 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 300
e1833e1f
JM		 301#define GEN_EXCP_PRIVOPC(ctx) \
302GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
303 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 304
e1833e1f
JM		 305#define GEN_EXCP_PRIVREG(ctx) \
306GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
307 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
308
309#define GEN_EXCP_NO_FP(ctx) \
310GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
311
312#define GEN_EXCP_NO_AP(ctx) \
313GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 314
a9d9eb8f
JM		 315#define GEN_EXCP_NO_VR(ctx) \
316GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
317
f24e5695 318/* Stop translation */
b068d6a7 319static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 320{
d9bce9d9 321 gen_update_nip(ctx, ctx->nip);
e1833e1f 322 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 323}
324
f24e5695 325/* No need to update nip here, as execution flow will change */
b068d6a7 326static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 327{
e1833e1f 328 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 329}
330
79aceca5
FB		 331#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
332static void gen_##name (DisasContext *ctx); \
333GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
334static void gen_##name (DisasContext *ctx)
335
c7697e1f
JM		 336#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
337static void gen_##name (DisasContext *ctx); \
338GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
339static void gen_##name (DisasContext *ctx)
340
79aceca5
FB		 341typedef struct opcode_t {
342 unsigned char opc1, opc2, opc3;
1235fc06 343#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 344 unsigned char pad[5];
345#else
346 unsigned char pad[1];
347#endif
79aceca5 348 opc_handler_t handler;
b55266b5 349 const char *oname;
79aceca5
FB		 350} opcode_t;
351
a750fc0b 352/*****************************************************************************/
79aceca5
FB		 353/*** Instruction decoding ***/
354#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 355static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 356{ \
357 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
358}
359
360#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 361static always_inline int32_t name (uint32_t opcode) \
79aceca5 362{ \
18fba28c 363 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 364}
365
366/* Opcode part 1 */
367EXTRACT_HELPER(opc1, 26, 6);
368/* Opcode part 2 */
369EXTRACT_HELPER(opc2, 1, 5);
370/* Opcode part 3 */
371EXTRACT_HELPER(opc3, 6, 5);
372/* Update Cr0 flags */
373EXTRACT_HELPER(Rc, 0, 1);
374/* Destination */
375EXTRACT_HELPER(rD, 21, 5);
376/* Source */
377EXTRACT_HELPER(rS, 21, 5);
378/* First operand */
379EXTRACT_HELPER(rA, 16, 5);
380/* Second operand */
381EXTRACT_HELPER(rB, 11, 5);
382/* Third operand */
383EXTRACT_HELPER(rC, 6, 5);
384/*** Get CRn ***/
385EXTRACT_HELPER(crfD, 23, 3);
386EXTRACT_HELPER(crfS, 18, 3);
387EXTRACT_HELPER(crbD, 21, 5);
388EXTRACT_HELPER(crbA, 16, 5);
389EXTRACT_HELPER(crbB, 11, 5);
390/* SPR / TBL */
3fc6c082 391EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 392static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 393{
394 uint32_t sprn = _SPR(opcode);
395
396 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
397}
79aceca5
FB		 398/*** Get constants ***/
399EXTRACT_HELPER(IMM, 12, 8);
400/* 16 bits signed immediate value */
401EXTRACT_SHELPER(SIMM, 0, 16);
402/* 16 bits unsigned immediate value */
403EXTRACT_HELPER(UIMM, 0, 16);
404/* Bit count */
405EXTRACT_HELPER(NB, 11, 5);
406/* Shift count */
407EXTRACT_HELPER(SH, 11, 5);
408/* Mask start */
409EXTRACT_HELPER(MB, 6, 5);
410/* Mask end */
411EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 412/* Trap operand */
413EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 414
415EXTRACT_HELPER(CRM, 12, 8);
416EXTRACT_HELPER(FM, 17, 8);
417EXTRACT_HELPER(SR, 16, 4);
e4bb997e 418EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 419
79aceca5
FB		 420/*** Jump target decoding ***/
421/* Displacement */
422EXTRACT_SHELPER(d, 0, 16);
423/* Immediate address */
b068d6a7 424static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 425{
426 return (opcode >> 0) & 0x03FFFFFC;
427}
428
b068d6a7 429static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 430{
431 return (opcode >> 0) & 0xFFFC;
432}
433
434EXTRACT_HELPER(BO, 21, 5);
435EXTRACT_HELPER(BI, 16, 5);
436/* Absolute/relative address */
437EXTRACT_HELPER(AA, 1, 1);
438/* Link */
439EXTRACT_HELPER(LK, 0, 1);
440
441/* Create a mask between <start> and <end> bits */
b068d6a7 442static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 443{
76a66253 444 target_ulong ret;
79aceca5 445
76a66253
JM		 446#if defined(TARGET_PPC64)
447 if (likely(start == 0)) {
6f2d8978 448 ret = UINT64_MAX << (63 - end);
76a66253 449 } else if (likely(end == 63)) {
6f2d8978 450 ret = UINT64_MAX >> start;
76a66253
JM		 451 }
452#else
453 if (likely(start == 0)) {
6f2d8978 454 ret = UINT32_MAX << (31 - end);
76a66253 455 } else if (likely(end == 31)) {
6f2d8978 456 ret = UINT32_MAX >> start;
76a66253
JM		 457 }
458#endif
459 else {
460 ret = (((target_ulong)(-1ULL)) >> (start)) ^
461 (((target_ulong)(-1ULL) >> (end)) >> 1);
462 if (unlikely(start > end))
463 return ~ret;
464 }
79aceca5
FB		 465
466 return ret;
467}
468
a750fc0b
JM		 469/*****************************************************************************/
470/* PowerPC Instructions types definitions */
471enum {
1b413d55 472 PPC_NONE = 0x0000000000000000ULL,
12de9a39 473 /* PowerPC base instructions set */
1b413d55
JM		 474 PPC_INSNS_BASE = 0x0000000000000001ULL,
475 /* integer operations instructions */
a750fc0b 476#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 477 /* flow control instructions */
a750fc0b 478#define PPC_FLOW PPC_INSNS_BASE
1b413d55 479 /* virtual memory instructions */
a750fc0b 480#define PPC_MEM PPC_INSNS_BASE
1b413d55 481 /* ld/st with reservation instructions */
a750fc0b 482#define PPC_RES PPC_INSNS_BASE
1b413d55 483 /* spr/msr access instructions */
a750fc0b 484#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 485 /* Deprecated instruction sets */
486 /* Original POWER instruction set */
f610349f 487 PPC_POWER = 0x0000000000000002ULL,
1b413d55 488 /* POWER2 instruction set extension */
f610349f 489 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 490 /* Power RTC support */
f610349f 491 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 492 /* Power-to-PowerPC bridge (601) */
f610349f 493 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 494 /* 64 bits PowerPC instruction set */
f610349f 495 PPC_64B = 0x0000000000000020ULL,
1b413d55 496 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 497 PPC_64BX = 0x0000000000000040ULL,
1b413d55 498 /* 64 bits hypervisor extensions */
f610349f 499 PPC_64H = 0x0000000000000080ULL,
1b413d55 500 /* New wait instruction (PowerPC 2.0x) */
f610349f 501 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 502 /* Time base mftb instruction */
f610349f 503 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 504
505 /* Fixed-point unit extensions */
506 /* PowerPC 602 specific */
f610349f 507 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 508 /* isel instruction */
509 PPC_ISEL = 0x0000000000000800ULL,
510 /* popcntb instruction */
511 PPC_POPCNTB = 0x0000000000001000ULL,
512 /* string load / store */
513 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 514
515 /* Floating-point unit extensions */
516 /* Optional floating point instructions */
517 PPC_FLOAT = 0x0000000000010000ULL,
518 /* New floating-point extensions (PowerPC 2.0x) */
519 PPC_FLOAT_EXT = 0x0000000000020000ULL,
520 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
521 PPC_FLOAT_FRES = 0x0000000000080000ULL,
522 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
523 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
524 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
525 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
526
527 /* Vector/SIMD extensions */
528 /* Altivec support */
529 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 530 /* PowerPC 2.03 SPE extension */
05332d70 531 PPC_SPE = 0x0000000002000000ULL,
1b413d55 532 /* PowerPC 2.03 SPE floating-point extension */
05332d70 533 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 534
12de9a39 535 /* Optional memory control instructions */
1b413d55
JM		 536 PPC_MEM_TLBIA = 0x0000000010000000ULL,
537 PPC_MEM_TLBIE = 0x0000000020000000ULL,
538 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
539 /* sync instruction */
540 PPC_MEM_SYNC = 0x0000000080000000ULL,
541 /* eieio instruction */
542 PPC_MEM_EIEIO = 0x0000000100000000ULL,
543
544 /* Cache control instructions */
c8623f2e 545 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 546 /* icbi instruction */
05332d70 547 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 548 /* dcbz instruction with fixed cache line size */
05332d70 549 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 550 /* dcbz instruction with tunable cache line size */
05332d70 551 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 552 /* dcba instruction */
05332d70
JM		 553 PPC_CACHE_DCBA = 0x0000002000000000ULL,
554 /* Freescale cache locking instructions */
555 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 556
557 /* MMU related extensions */
558 /* external control instructions */
05332d70 559 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 560 /* segment register access instructions */
05332d70 561 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 562 /* PowerPC 6xx TLB management instructions */
05332d70 563 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 564 /* PowerPC 74xx TLB management instructions */
05332d70 565 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 566 /* PowerPC 40x TLB management instructions */
05332d70 567 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 568 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 569 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 570 /* SLB management */
05332d70 571 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 572
12de9a39 573 /* Embedded PowerPC dedicated instructions */
05332d70 574 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 575 /* PowerPC 40x exception model */
05332d70 576 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 577 /* PowerPC 405 Mac instructions */
05332d70 578 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 579 /* PowerPC 440 specific instructions */
05332d70 580 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 581 /* BookE (embedded) PowerPC specification */
05332d70
JM		 582 PPC_BOOKE = 0x0010000000000000ULL,
583 /* mfapidi instruction */
584 PPC_MFAPIDI = 0x0020000000000000ULL,
585 /* tlbiva instruction */
586 PPC_TLBIVA = 0x0040000000000000ULL,
587 /* tlbivax instruction */
588 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 589 /* PowerPC 4xx dedicated instructions */
05332d70 590 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 591 /* PowerPC 40x ibct instructions */
05332d70 592 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 593 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 594 PPC_RFMCI = 0x0400000000000000ULL,
595 /* rfdi instruction */
596 PPC_RFDI = 0x0800000000000000ULL,
597 /* DCR accesses */
598 PPC_DCR = 0x1000000000000000ULL,
599 /* DCR extended accesse */
600 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 601 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 602 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 603};
604
605/*****************************************************************************/
606/* PowerPC instructions table */
3fc6c082
FB		 607#if HOST_LONG_BITS == 64
608#define OPC_ALIGN 8
609#else
610#define OPC_ALIGN 4
611#endif
1b039c09 612#if defined(__APPLE__)
d9bce9d9 613#define OPCODES_SECTION \
3fc6c082 614 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 615#else
d9bce9d9 616#define OPCODES_SECTION \
3fc6c082 617 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 618#endif
619
76a66253 620#if defined(DO_PPC_STATISTICS)
79aceca5 621#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 622OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 623 .opc1 = op1, \
624 .opc2 = op2, \
625 .opc3 = op3, \
18fba28c 626 .pad = { 0, }, \
79aceca5
FB		 627 .handler = { \
628 .inval = invl, \
9a64fbe4 629 .type = _typ, \
79aceca5 630 .handler = &gen_##name, \
76a66253 631 .oname = stringify(name), \
79aceca5 632 }, \
3fc6c082 633 .oname = stringify(name), \
79aceca5 634}
c7697e1f
JM		 635#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
636OPCODES_SECTION opcode_t opc_##name = { \
637 .opc1 = op1, \
638 .opc2 = op2, \
639 .opc3 = op3, \
640 .pad = { 0, }, \
641 .handler = { \
642 .inval = invl, \
643 .type = _typ, \
644 .handler = &gen_##name, \
645 .oname = onam, \
646 }, \
647 .oname = onam, \
648}
76a66253
JM		 649#else
650#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
651OPCODES_SECTION opcode_t opc_##name = { \
652 .opc1 = op1, \
653 .opc2 = op2, \
654 .opc3 = op3, \
655 .pad = { 0, }, \
656 .handler = { \
657 .inval = invl, \
658 .type = _typ, \
659 .handler = &gen_##name, \
660 }, \
661 .oname = stringify(name), \
662}
c7697e1f
JM		 663#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
664OPCODES_SECTION opcode_t opc_##name = { \
665 .opc1 = op1, \
666 .opc2 = op2, \
667 .opc3 = op3, \
668 .pad = { 0, }, \
669 .handler = { \
670 .inval = invl, \
671 .type = _typ, \
672 .handler = &gen_##name, \
673 }, \
674 .oname = onam, \
675}
76a66253 676#endif
79aceca5
FB		 677
678#define GEN_OPCODE_MARK(name) \
18fba28c 679OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 680 .opc1 = 0xFF, \
681 .opc2 = 0xFF, \
682 .opc3 = 0xFF, \
18fba28c 683 .pad = { 0, }, \
79aceca5
FB		 684 .handler = { \
685 .inval = 0x00000000, \
9a64fbe4 686 .type = 0x00, \
79aceca5
FB		 687 .handler = NULL, \
688 }, \
3fc6c082 689 .oname = stringify(name), \
79aceca5
FB		 690}
691
692/* Start opcode list */
693GEN_OPCODE_MARK(start);
694
695/* Invalid instruction */
9a64fbe4
FB		 696GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
697{
e1833e1f 698 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 699}
700
79aceca5
FB		 701static opc_handler_t invalid_handler = {
702 .inval = 0xFFFFFFFF,
9a64fbe4 703 .type = PPC_NONE,
79aceca5
FB		 704 .handler = gen_invalid,
705};
706
707/*** Integer arithmetic ***/
d9bce9d9
JM		 708#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
709GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 710{ \
f78fb44e
AJ		 711 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
712 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 713 gen_op_##name(); \
f78fb44e 714 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 715 if (unlikely(Rc(ctx->opcode) != 0)) \
716 gen_set_Rc0(ctx); \
79aceca5
FB		 717}
718
d9bce9d9
JM		 719#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
720GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 721{ \
f78fb44e
AJ		 722 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
723 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 724 gen_op_##name(); \
f78fb44e 725 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 726 if (unlikely(Rc(ctx->opcode) != 0)) \
727 gen_set_Rc0(ctx); \
79aceca5
FB		 728}
729
d9bce9d9
JM		 730#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
731GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 732{ \
f78fb44e 733 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 734 gen_op_##name(); \
f78fb44e 735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 736 if (unlikely(Rc(ctx->opcode) != 0)) \
737 gen_set_Rc0(ctx); \
79aceca5 738}
d9bce9d9
JM		 739#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
740GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 741{ \
f78fb44e 742 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 743 gen_op_##name(); \
f78fb44e 744 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 745 if (unlikely(Rc(ctx->opcode) != 0)) \
746 gen_set_Rc0(ctx); \
79aceca5
FB		 747}
748
749/* Two operands arithmetic functions */
d9bce9d9
JM		 750#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
751__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
752__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
753
754/* Two operands arithmetic functions with no overflow allowed */
755#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
756__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
757
758/* One operand arithmetic functions */
759#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
760__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
761__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
762
763#if defined(TARGET_PPC64)
764#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
765GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
766{ \
f78fb44e
AJ		 767 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
768 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 769 if (ctx->sf_mode) \
770 gen_op_##name##_64(); \
771 else \
772 gen_op_##name(); \
f78fb44e 773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 774 if (unlikely(Rc(ctx->opcode) != 0)) \
775 gen_set_Rc0(ctx); \
776}
777
778#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
779GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
780{ \
f78fb44e
AJ		 781 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
782 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 783 if (ctx->sf_mode) \
784 gen_op_##name##_64(); \
785 else \
786 gen_op_##name(); \
f78fb44e 787 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 788 if (unlikely(Rc(ctx->opcode) != 0)) \
789 gen_set_Rc0(ctx); \
790}
791
792#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
793GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
794{ \
f78fb44e 795 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 796 if (ctx->sf_mode) \
797 gen_op_##name##_64(); \
798 else \
799 gen_op_##name(); \
f78fb44e 800 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 801 if (unlikely(Rc(ctx->opcode) != 0)) \
802 gen_set_Rc0(ctx); \
803}
804#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
805GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
806{ \
f78fb44e 807 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 808 if (ctx->sf_mode) \
809 gen_op_##name##_64(); \
810 else \
811 gen_op_##name(); \
f78fb44e 812 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9
JM		 813 if (unlikely(Rc(ctx->opcode) != 0)) \
814 gen_set_Rc0(ctx); \
815}
816
817/* Two operands arithmetic functions */
818#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
819__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
820__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 821
822/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 823#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
824__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 825
826/* One operand arithmetic functions */
d9bce9d9
JM		 827#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
828__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
829__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
830#else
831#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
832#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
833#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
834#endif
79aceca5
FB		 835
836/* add add. addo addo. */
39dd32ee
AJ		 837static always_inline void gen_op_add (void)
838{
839 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
840}
b068d6a7 841static always_inline void gen_op_addo (void)
d9bce9d9 842{
e55fd934 843 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 844 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 845 gen_op_check_addo();
846}
847#if defined(TARGET_PPC64)
848#define gen_op_add_64 gen_op_add
b068d6a7 849static always_inline void gen_op_addo_64 (void)
d9bce9d9 850{
e55fd934 851 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 852 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 853 gen_op_check_addo_64();
854}
855#endif
856GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 857/* addc addc. addco addco. */
b068d6a7 858static always_inline void gen_op_addc (void)
d9bce9d9 859{
e55fd934 860 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 861 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 862 gen_op_check_addc();
863}
b068d6a7 864static always_inline void gen_op_addco (void)
d9bce9d9 865{
e55fd934 866 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 867 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 868 gen_op_check_addc();
869 gen_op_check_addo();
870}
871#if defined(TARGET_PPC64)
b068d6a7 872static always_inline void gen_op_addc_64 (void)
d9bce9d9 873{
e55fd934 874 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 875 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 876 gen_op_check_addc_64();
877}
b068d6a7 878static always_inline void gen_op_addco_64 (void)
d9bce9d9 879{
e55fd934 880 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 881 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 882 gen_op_check_addc_64();
883 gen_op_check_addo_64();
884}
885#endif
886GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 887/* adde adde. addeo addeo. */
b068d6a7 888static always_inline void gen_op_addeo (void)
d9bce9d9 889{
e55fd934 890 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 891 gen_op_adde();
892 gen_op_check_addo();
893}
894#if defined(TARGET_PPC64)
b068d6a7 895static always_inline void gen_op_addeo_64 (void)
d9bce9d9 896{
e55fd934 897 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 898 gen_op_adde_64();
899 gen_op_check_addo_64();
900}
901#endif
902GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 903/* addme addme. addmeo addmeo. */
b068d6a7 904static always_inline void gen_op_addme (void)
d9bce9d9 905{
e55fd934 906 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 907 gen_op_add_me();
908}
909#if defined(TARGET_PPC64)
b068d6a7 910static always_inline void gen_op_addme_64 (void)
d9bce9d9 911{
e55fd934 912 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 913 gen_op_add_me_64();
914}
915#endif
916GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 917/* addze addze. addzeo addzeo. */
b068d6a7 918static always_inline void gen_op_addze (void)
d9bce9d9 919{
e55fd934 920 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 921 gen_op_add_ze();
922 gen_op_check_addc();
923}
b068d6a7 924static always_inline void gen_op_addzeo (void)
d9bce9d9 925{
e55fd934 926 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 927 gen_op_add_ze();
928 gen_op_check_addc();
929 gen_op_check_addo();
930}
931#if defined(TARGET_PPC64)
b068d6a7 932static always_inline void gen_op_addze_64 (void)
d9bce9d9 933{
e55fd934 934 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 935 gen_op_add_ze();
936 gen_op_check_addc_64();
937}
b068d6a7 938static always_inline void gen_op_addzeo_64 (void)
d9bce9d9 939{
e55fd934 940 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 941 gen_op_add_ze();
942 gen_op_check_addc_64();
943 gen_op_check_addo_64();
944}
945#endif
946GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 947/* divw divw. divwo divwo. */
d9bce9d9 948GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 949/* divwu divwu. divwuo divwuo. */
d9bce9d9 950GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 951/* mulhw mulhw. */
d9bce9d9 952GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 953/* mulhwu mulhwu. */
d9bce9d9 954GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 955/* mullw mullw. mullwo mullwo. */
d9bce9d9 956GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 957/* neg neg. nego nego. */
d9bce9d9 958GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 959/* subf subf. subfo subfo. */
7c417963
AJ		 960static always_inline void gen_op_subf (void)
961{
962 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
963}
b068d6a7 964static always_inline void gen_op_subfo (void)
d9bce9d9 965{
f0413473 966 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 967 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 968 gen_op_check_addo();
d9bce9d9
JM		 969}
970#if defined(TARGET_PPC64)
971#define gen_op_subf_64 gen_op_subf
b068d6a7 972static always_inline void gen_op_subfo_64 (void)
d9bce9d9 973{
f0413473 974 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 975 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 976 gen_op_check_addo_64();
d9bce9d9
JM		 977}
978#endif
979GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 980/* subfc subfc. subfco subfco. */
b068d6a7 981static always_inline void gen_op_subfc (void)
d9bce9d9 982{
7c417963 983 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 984 gen_op_check_subfc();
985}
b068d6a7 986static always_inline void gen_op_subfco (void)
d9bce9d9 987{
f0413473 988 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 989 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 990 gen_op_check_subfc();
c3e10c7b 991 gen_op_check_addo();
d9bce9d9
JM		 992}
993#if defined(TARGET_PPC64)
b068d6a7 994static always_inline void gen_op_subfc_64 (void)
d9bce9d9 995{
7c417963 996 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 997 gen_op_check_subfc_64();
998}
b068d6a7 999static always_inline void gen_op_subfco_64 (void)
d9bce9d9 1000{
f0413473 1001 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 1002 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 1003 gen_op_check_subfc_64();
c3e10c7b 1004 gen_op_check_addo_64();
d9bce9d9
JM		 1005}
1006#endif
1007GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 1008/* subfe subfe. subfeo subfeo. */
b068d6a7 1009static always_inline void gen_op_subfeo (void)
d9bce9d9 1010{
f0413473 1011 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
d9bce9d9 1012 gen_op_subfe();
c3e10c7b 1013 gen_op_check_addo();
d9bce9d9
JM		 1014}
1015#if defined(TARGET_PPC64)
1016#define gen_op_subfe_64 gen_op_subfe
b068d6a7 1017static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 1018{
f0413473 1019 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
d9bce9d9 1020 gen_op_subfe_64();
c3e10c7b 1021 gen_op_check_addo_64();
d9bce9d9
JM		 1022}
1023#endif
1024GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 1025/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 1026GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 1027/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 1028GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 1029/* addi */
1030GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1031{
76a66253 1032 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1033
1034 if (rA(ctx->opcode) == 0) {
76a66253 1035 /* li case */
02f4f6c2 1036 tcg_gen_movi_tl(cpu_T[0], simm);
79aceca5 1037 } else {
f78fb44e 1038 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1039 if (likely(simm != 0))
39dd32ee 1040 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
79aceca5 1041 }
f78fb44e 1042 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1043}
1044/* addic */
1045GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1046{
76a66253
JM		 1047 target_long simm = SIMM(ctx->opcode);
1048
f78fb44e 1049 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1050 if (likely(simm != 0)) {
e55fd934 1051 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1052 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1053#if defined(TARGET_PPC64)
1054 if (ctx->sf_mode)
1055 gen_op_check_addc_64();
1056 else
1057#endif
1058 gen_op_check_addc();
e864cabd
JM		 1059 } else {
1060 gen_op_clear_xer_ca();
d9bce9d9 1061 }
f78fb44e 1062 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1063}
1064/* addic. */
c7697e1f 1065GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1066{
76a66253
JM		 1067 target_long simm = SIMM(ctx->opcode);
1068
f78fb44e 1069 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1070 if (likely(simm != 0)) {
e55fd934 1071 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1072 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1073#if defined(TARGET_PPC64)
1074 if (ctx->sf_mode)
1075 gen_op_check_addc_64();
1076 else
1077#endif
1078 gen_op_check_addc();
966439a6
JM		 1079 } else {
1080 gen_op_clear_xer_ca();
d9bce9d9 1081 }
f78fb44e 1082 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 1083 gen_set_Rc0(ctx);
79aceca5
FB		 1084}
1085/* addis */
1086GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1087{
76a66253 1088 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1089
1090 if (rA(ctx->opcode) == 0) {
76a66253 1091 /* lis case */
02f4f6c2 1092 tcg_gen_movi_tl(cpu_T[0], simm << 16);
79aceca5 1093 } else {
f78fb44e 1094 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1095 if (likely(simm != 0))
39dd32ee 1096 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16);
79aceca5 1097 }
f78fb44e 1098 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1099}
1100/* mulli */
1101GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1102{
f78fb44e 1103 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
79aceca5 1104 gen_op_mulli(SIMM(ctx->opcode));
f78fb44e 1105 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1106}
1107/* subfic */
1108GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1109{
f78fb44e 1110 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9
JM		 1111#if defined(TARGET_PPC64)
1112 if (ctx->sf_mode)
1113 gen_op_subfic_64(SIMM(ctx->opcode));
1114 else
1115#endif
1116 gen_op_subfic(SIMM(ctx->opcode));
f78fb44e 1117 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1118}
1119
d9bce9d9
JM		 1120#if defined(TARGET_PPC64)
1121/* mulhd mulhd. */
a750fc0b 1122GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1123/* mulhdu mulhdu. */
a750fc0b 1124GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1125/* mulld mulld. mulldo mulldo. */
a750fc0b 1126GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1127/* divd divd. divdo divdo. */
a750fc0b 1128GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1129/* divdu divdu. divduo divduo. */
a750fc0b 1130GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1131#endif
1132
79aceca5 1133/*** Integer comparison ***/
d9bce9d9
JM		 1134#if defined(TARGET_PPC64)
1135#define GEN_CMP(name, opc, type) \
1136GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1137{ \
f78fb44e
AJ		 1138 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
1139 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
e3878283 1140 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
d9bce9d9
JM		 1141 gen_op_##name##_64(); \
1142 else \
1143 gen_op_##name(); \
47e4661c 1144 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
d9bce9d9
JM		 1145}
1146#else
1147#define GEN_CMP(name, opc, type) \
1148GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
79aceca5 1149{ \
f78fb44e
AJ		 1150 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
1151 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 1152 gen_op_##name(); \
47e4661c 1153 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
79aceca5 1154}
d9bce9d9 1155#endif
79aceca5
FB		 1156
1157/* cmp */
d9bce9d9 1158GEN_CMP(cmp, 0x00, PPC_INTEGER);
79aceca5
FB		 1159/* cmpi */
1160GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1161{
f78fb44e 1162 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1163#if defined(TARGET_PPC64)
e3878283 1164 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1165 gen_op_cmpi_64(SIMM(ctx->opcode));
1166 else
1167#endif
1168 gen_op_cmpi(SIMM(ctx->opcode));
47e4661c 1169 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
79aceca5
FB		 1170}
1171/* cmpl */
d9bce9d9 1172GEN_CMP(cmpl, 0x01, PPC_INTEGER);
79aceca5
FB		 1173/* cmpli */
1174GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1175{
f78fb44e 1176 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1177#if defined(TARGET_PPC64)
e3878283 1178 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1179 gen_op_cmpli_64(UIMM(ctx->opcode));
1180 else
1181#endif
1182 gen_op_cmpli(UIMM(ctx->opcode));
47e4661c 1183 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
79aceca5
FB		 1184}
1185
d9bce9d9 1186/* isel (PowerPC 2.03 specification) */
fd501a05 1187GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
d9bce9d9
JM		 1188{
1189 uint32_t bi = rC(ctx->opcode);
1190 uint32_t mask;
1191
1192 if (rA(ctx->opcode) == 0) {
02f4f6c2 1193 tcg_gen_movi_tl(cpu_T[0], 0);
d9bce9d9 1194 } else {
f78fb44e 1195 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1196 }
f78fb44e 1197 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1198 mask = 1 << (3 - (bi & 0x03));
47e4661c 1199 tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]);
d9bce9d9
JM		 1200 gen_op_test_true(mask);
1201 gen_op_isel();
f78fb44e 1202 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1203}
1204
79aceca5 1205/*** Integer logical ***/
d9bce9d9
JM		 1206#define __GEN_LOGICAL2(name, opc2, opc3, type) \
1207GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
79aceca5 1208{ \
f78fb44e
AJ		 1209 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
1210 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 1211 gen_op_##name(); \
f78fb44e 1212 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 1213 if (unlikely(Rc(ctx->opcode) != 0)) \
1214 gen_set_Rc0(ctx); \
79aceca5 1215}
d9bce9d9
JM		 1216#define GEN_LOGICAL2(name, opc, type) \
1217__GEN_LOGICAL2(name, 0x1C, opc, type)
79aceca5 1218
d9bce9d9
JM		 1219#define GEN_LOGICAL1(name, opc, type) \
1220GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1221{ \
f78fb44e 1222 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
79aceca5 1223 gen_op_##name(); \
f78fb44e 1224 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
76a66253
JM		 1225 if (unlikely(Rc(ctx->opcode) != 0)) \
1226 gen_set_Rc0(ctx); \
79aceca5
FB		 1227}
1228
1229/* and & and. */
d9bce9d9 1230GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
79aceca5 1231/* andc & andc. */
d9bce9d9 1232GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
79aceca5 1233/* andi. */
c7697e1f 1234GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1235{
f78fb44e 1236 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
0df5bdbe 1237 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
f78fb44e 1238 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1239 gen_set_Rc0(ctx);
79aceca5
FB		 1240}
1241/* andis. */
c7697e1f 1242GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1243{
f78fb44e 1244 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
0df5bdbe 1245 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
f78fb44e 1246 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1247 gen_set_Rc0(ctx);
79aceca5
FB		 1248}
1249
1250/* cntlzw */
d9bce9d9 1251GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
79aceca5 1252/* eqv & eqv. */
d9bce9d9 1253GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
79aceca5 1254/* extsb & extsb. */
d9bce9d9 1255GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
79aceca5 1256/* extsh & extsh. */
d9bce9d9 1257GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
79aceca5 1258/* nand & nand. */
d9bce9d9 1259GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
79aceca5 1260/* nor & nor. */
d9bce9d9 1261GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
9a64fbe4 1262
79aceca5 1263/* or & or. */
9a64fbe4
FB		 1264GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1265{
76a66253
JM		 1266 int rs, ra, rb;
1267
1268 rs = rS(ctx->opcode);
1269 ra = rA(ctx->opcode);
1270 rb = rB(ctx->opcode);
1271 /* Optimisation for mr. ri case */
1272 if (rs != ra || rs != rb) {
f78fb44e 1273 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
76a66253 1274 if (rs != rb) {
f78fb44e 1275 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 1276 gen_op_or();
1277 }
f78fb44e 1278 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 1279 if (unlikely(Rc(ctx->opcode) != 0))
1280 gen_set_Rc0(ctx);
1281 } else if (unlikely(Rc(ctx->opcode) != 0)) {
f78fb44e 1282 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
76a66253 1283 gen_set_Rc0(ctx);
c80f84e3
JM		 1284#if defined(TARGET_PPC64)
1285 } else {
1286 switch (rs) {
1287 case 1:
1288 /* Set process priority to low */
1289 gen_op_store_pri(2);
1290 break;
1291 case 6:
1292 /* Set process priority to medium-low */
1293 gen_op_store_pri(3);
1294 break;
1295 case 2:
1296 /* Set process priority to normal */
1297 gen_op_store_pri(4);
1298 break;
be147d08
JM		 1299#if !defined(CONFIG_USER_ONLY)
1300 case 31:
1301 if (ctx->supervisor > 0) {
1302 /* Set process priority to very low */
1303 gen_op_store_pri(1);
1304 }
1305 break;
1306 case 5:
1307 if (ctx->supervisor > 0) {
1308 /* Set process priority to medium-hight */
1309 gen_op_store_pri(5);
1310 }
1311 break;
1312 case 3:
1313 if (ctx->supervisor > 0) {
1314 /* Set process priority to high */
1315 gen_op_store_pri(6);
1316 }
1317 break;
be147d08
JM		 1318 case 7:
1319 if (ctx->supervisor > 1) {
1320 /* Set process priority to very high */
1321 gen_op_store_pri(7);
1322 }
1323 break;
be147d08 1324#endif
c80f84e3
JM		 1325 default:
1326 /* nop */
1327 break;
1328 }
1329#endif
9a64fbe4 1330 }
9a64fbe4
FB		 1331}
1332
79aceca5 1333/* orc & orc. */
d9bce9d9 1334GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
79aceca5 1335/* xor & xor. */
9a64fbe4
FB		 1336GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1337{
f78fb44e 1338 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4
FB		 1339 /* Optimisation for "set to zero" case */
1340 if (rS(ctx->opcode) != rB(ctx->opcode)) {
f78fb44e 1341 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
9a64fbe4
FB		 1342 gen_op_xor();
1343 } else {
86c581dc 1344 tcg_gen_movi_tl(cpu_T[0], 0);
9a64fbe4 1345 }
f78fb44e 1346 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1347 if (unlikely(Rc(ctx->opcode) != 0))
1348 gen_set_Rc0(ctx);
9a64fbe4 1349}
79aceca5
FB		 1350/* ori */
1351GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1352{
76a66253 1353 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1354
9a64fbe4
FB		 1355 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1356 /* NOP */
76a66253 1357 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1358 return;
76a66253 1359 }
f78fb44e 1360 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253 1361 if (likely(uimm != 0))
79aceca5 1362 gen_op_ori(uimm);
f78fb44e 1363 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1364}
1365/* oris */
1366GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1367{
76a66253 1368 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1369
9a64fbe4
FB		 1370 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1371 /* NOP */
1372 return;
76a66253 1373 }
f78fb44e 1374 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253 1375 if (likely(uimm != 0))
79aceca5 1376 gen_op_ori(uimm << 16);
f78fb44e 1377 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1378}
1379/* xori */
1380GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1381{
76a66253 1382 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1383
1384 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1385 /* NOP */
1386 return;
1387 }
f78fb44e 1388 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1389 if (likely(uimm != 0))
1390 gen_op_xori(uimm);
f78fb44e 1391 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1392}
1393
1394/* xoris */
1395GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1396{
76a66253 1397 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1398
1399 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1400 /* NOP */
1401 return;
1402 }
f78fb44e 1403 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1404 if (likely(uimm != 0))
1405 gen_op_xori(uimm << 16);
f78fb44e 1406 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1407}
1408
d9bce9d9 1409/* popcntb : PowerPC 2.03 specification */
05332d70 1410GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1411{
f78fb44e 1412 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1413#if defined(TARGET_PPC64)
1414 if (ctx->sf_mode)
6676f424 1415 gen_op_popcntb_64();
d9bce9d9
JM		 1416 else
1417#endif
6676f424 1418 gen_op_popcntb();
f78fb44e 1419 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1420}
1421
1422#if defined(TARGET_PPC64)
1423/* extsw & extsw. */
1424GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1425/* cntlzd */
1426GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1427#endif
1428
79aceca5
FB		 1429/*** Integer rotate ***/
1430/* rlwimi & rlwimi. */
1431GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1432{
76a66253
JM		 1433 target_ulong mask;
1434 uint32_t mb, me, sh;
79aceca5
FB		 1435
1436 mb = MB(ctx->opcode);
1437 me = ME(ctx->opcode);
76a66253 1438 sh = SH(ctx->opcode);
76a66253
JM		 1439 if (likely(sh == 0)) {
1440 if (likely(mb == 0 && me == 31)) {
f78fb44e 1441 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1442 goto do_store;
1443 } else if (likely(mb == 31 && me == 0)) {
f78fb44e 1444 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1445 goto do_store;
1446 }
f78fb44e
AJ		 1447 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1448 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1449 goto do_mask;
1450 }
f78fb44e
AJ		 1451 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1452 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1453 gen_op_rotli32_T0(SH(ctx->opcode));
1454 do_mask:
1455#if defined(TARGET_PPC64)
1456 mb += 32;
1457 me += 32;
1458#endif
1459 mask = MASK(mb, me);
0df5bdbe
AJ		 1460 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1461 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
76a66253
JM		 1462 gen_op_or();
1463 do_store:
f78fb44e 1464 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1465 if (unlikely(Rc(ctx->opcode) != 0))
1466 gen_set_Rc0(ctx);
79aceca5
FB		 1467}
1468/* rlwinm & rlwinm. */
1469GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1470{
1471 uint32_t mb, me, sh;
3b46e624 1472
79aceca5
FB		 1473 sh = SH(ctx->opcode);
1474 mb = MB(ctx->opcode);
1475 me = ME(ctx->opcode);
f78fb44e 1476 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1477 if (likely(sh == 0)) {
1478 goto do_mask;
1479 }
1480 if (likely(mb == 0)) {
1481 if (likely(me == 31)) {
1482 gen_op_rotli32_T0(sh);
1483 goto do_store;
1484 } else if (likely(me == (31 - sh))) {
1485 gen_op_sli_T0(sh);
1486 goto do_store;
79aceca5 1487 }
76a66253
JM		 1488 } else if (likely(me == 31)) {
1489 if (likely(sh == (32 - mb))) {
1490 gen_op_srli_T0(mb);
1491 goto do_store;
79aceca5
FB		 1492 }
1493 }
76a66253
JM		 1494 gen_op_rotli32_T0(sh);
1495 do_mask:
1496#if defined(TARGET_PPC64)
1497 mb += 32;
1498 me += 32;
1499#endif
0df5bdbe 1500 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
76a66253 1501 do_store:
f78fb44e 1502 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1503 if (unlikely(Rc(ctx->opcode) != 0))
1504 gen_set_Rc0(ctx);
79aceca5
FB		 1505}
1506/* rlwnm & rlwnm. */
1507GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1508{
1509 uint32_t mb, me;
1510
1511 mb = MB(ctx->opcode);
1512 me = ME(ctx->opcode);
f78fb44e
AJ		 1513 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1514 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 1515 gen_op_rotl32_T0_T1();
1516 if (unlikely(mb != 0 || me != 31)) {
1517#if defined(TARGET_PPC64)
1518 mb += 32;
1519 me += 32;
1520#endif
0df5bdbe 1521 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
79aceca5 1522 }
f78fb44e 1523 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1524 if (unlikely(Rc(ctx->opcode) != 0))
1525 gen_set_Rc0(ctx);
79aceca5
FB		 1526}
1527
d9bce9d9
JM		 1528#if defined(TARGET_PPC64)
1529#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1530GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1531{ \
1532 gen_##name(ctx, 0); \
1533} \
c7697e1f
JM		 1534GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1535 PPC_64B) \
d9bce9d9
JM		 1536{ \
1537 gen_##name(ctx, 1); \
1538}
1539#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1540GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1541{ \
1542 gen_##name(ctx, 0, 0); \
1543} \
c7697e1f
JM		 1544GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1545 PPC_64B) \
d9bce9d9
JM		 1546{ \
1547 gen_##name(ctx, 0, 1); \
1548} \
c7697e1f
JM		 1549GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1550 PPC_64B) \
d9bce9d9
JM		 1551{ \
1552 gen_##name(ctx, 1, 0); \
1553} \
c7697e1f
JM		 1554GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1555 PPC_64B) \
d9bce9d9
JM		 1556{ \
1557 gen_##name(ctx, 1, 1); \
1558}
51789c41 1559
b068d6a7
JM		 1560static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1561 uint32_t me, uint32_t sh)
51789c41 1562{
f78fb44e 1563 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41
JM		 1564 if (likely(sh == 0)) {
1565 goto do_mask;
1566 }
1567 if (likely(mb == 0)) {
1568 if (likely(me == 63)) {
40d0591e 1569 gen_op_rotli64_T0(sh);
51789c41
JM		 1570 goto do_store;
1571 } else if (likely(me == (63 - sh))) {
1572 gen_op_sli_T0(sh);
1573 goto do_store;
1574 }
1575 } else if (likely(me == 63)) {
1576 if (likely(sh == (64 - mb))) {
40d0591e 1577 gen_op_srli_T0_64(mb);
51789c41
JM		 1578 goto do_store;
1579 }
1580 }
1581 gen_op_rotli64_T0(sh);
1582 do_mask:
0df5bdbe 1583 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1584 do_store:
f78fb44e 1585 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41
JM		 1586 if (unlikely(Rc(ctx->opcode) != 0))
1587 gen_set_Rc0(ctx);
1588}
d9bce9d9 1589/* rldicl - rldicl. */
b068d6a7 1590static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1591{
51789c41 1592 uint32_t sh, mb;
d9bce9d9 1593
9d53c753
JM		 1594 sh = SH(ctx->opcode) | (shn << 5);
1595 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1596 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1597}
51789c41 1598GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1599/* rldicr - rldicr. */
b068d6a7 1600static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1601{
51789c41 1602 uint32_t sh, me;
d9bce9d9 1603
9d53c753
JM		 1604 sh = SH(ctx->opcode) | (shn << 5);
1605 me = MB(ctx->opcode) | (men << 5);
51789c41 1606 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1607}
51789c41 1608GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1609/* rldic - rldic. */
b068d6a7 1610static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1611{
51789c41 1612 uint32_t sh, mb;
d9bce9d9 1613
9d53c753
JM		 1614 sh = SH(ctx->opcode) | (shn << 5);
1615 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1616 gen_rldinm(ctx, mb, 63 - sh, sh);
1617}
1618GEN_PPC64_R4(rldic, 0x1E, 0x04);
1619
b068d6a7
JM		 1620static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1621 uint32_t me)
51789c41 1622{
f78fb44e
AJ		 1623 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1624 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
51789c41
JM		 1625 gen_op_rotl64_T0_T1();
1626 if (unlikely(mb != 0 || me != 63)) {
0df5bdbe 1627 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1628 }
f78fb44e 1629 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41
JM		 1630 if (unlikely(Rc(ctx->opcode) != 0))
1631 gen_set_Rc0(ctx);
d9bce9d9 1632}
51789c41 1633
d9bce9d9 1634/* rldcl - rldcl. */
b068d6a7 1635static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1636{
51789c41 1637 uint32_t mb;
d9bce9d9 1638
9d53c753 1639 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1640 gen_rldnm(ctx, mb, 63);
d9bce9d9 1641}
36081602 1642GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1643/* rldcr - rldcr. */
b068d6a7 1644static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1645{
51789c41 1646 uint32_t me;
d9bce9d9 1647
9d53c753 1648 me = MB(ctx->opcode) | (men << 5);
51789c41 1649 gen_rldnm(ctx, 0, me);
d9bce9d9 1650}
36081602 1651GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1652/* rldimi - rldimi. */
b068d6a7 1653static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1654{
51789c41 1655 uint64_t mask;
271a916e 1656 uint32_t sh, mb, me;
d9bce9d9 1657
9d53c753
JM		 1658 sh = SH(ctx->opcode) | (shn << 5);
1659 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1660 me = 63 - sh;
51789c41
JM		 1661 if (likely(sh == 0)) {
1662 if (likely(mb == 0)) {
f78fb44e 1663 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41 1664 goto do_store;
51789c41 1665 }
f78fb44e
AJ		 1666 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1667 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
51789c41
JM		 1668 goto do_mask;
1669 }
f78fb44e
AJ		 1670 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1671 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
40d0591e 1672 gen_op_rotli64_T0(sh);
51789c41 1673 do_mask:
271a916e 1674 mask = MASK(mb, me);
0df5bdbe
AJ		 1675 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1676 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
51789c41
JM		 1677 gen_op_or();
1678 do_store:
f78fb44e 1679 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41
JM		 1680 if (unlikely(Rc(ctx->opcode) != 0))
1681 gen_set_Rc0(ctx);
d9bce9d9 1682}
36081602 1683GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1684#endif
1685
79aceca5
FB		 1686/*** Integer shift ***/
1687/* slw & slw. */
d9bce9d9 1688__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
79aceca5 1689/* sraw & sraw. */
d9bce9d9 1690__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
79aceca5
FB		 1691/* srawi & srawi. */
1692GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1693{
d9bce9d9 1694 int mb, me;
f78fb44e 1695 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1696 if (SH(ctx->opcode) != 0) {
e55fd934 1697 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1698 mb = 32 - SH(ctx->opcode);
1699 me = 31;
1700#if defined(TARGET_PPC64)
1701 mb += 32;
1702 me += 32;
1703#endif
1704 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1705 }
f78fb44e 1706 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 1707 if (unlikely(Rc(ctx->opcode) != 0))
1708 gen_set_Rc0(ctx);
79aceca5
FB		 1709}
1710/* srw & srw. */
d9bce9d9
JM		 1711__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1712
1713#if defined(TARGET_PPC64)
1714/* sld & sld. */
1715__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1716/* srad & srad. */
1717__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1718/* sradi & sradi. */
b068d6a7 1719static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9
JM		 1720{
1721 uint64_t mask;
1722 int sh, mb, me;
1723
f78fb44e 1724 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1725 sh = SH(ctx->opcode) + (n << 5);
1726 if (sh != 0) {
e55fd934 1727 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1728 mb = 64 - SH(ctx->opcode);
1729 me = 63;
1730 mask = MASK(mb, me);
1731 gen_op_sradi(sh, mask >> 32, mask);
1732 }
f78fb44e 1733 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1734 if (unlikely(Rc(ctx->opcode) != 0))
1735 gen_set_Rc0(ctx);
1736}
c7697e1f 1737GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1738{
1739 gen_sradi(ctx, 0);
1740}
c7697e1f 1741GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1742{
1743 gen_sradi(ctx, 1);
1744}
1745/* srd & srd. */
1746__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1747#endif
79aceca5
FB		 1748
1749/*** Floating-Point arithmetic ***/
7c58044c 1750#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1751GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1752{ \
76a66253 1753 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1754 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1755 return; \
1756 } \
a5e26afa
AJ		 1757 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1758 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
1759 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1760 gen_reset_fpstatus(); \
4ecc3190
FB		 1761 gen_op_f##op(); \
1762 if (isfloat) { \
1763 gen_op_frsp(); \
1764 } \
a5e26afa 1765 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1766 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1767}
1768
7c58044c
JM		 1769#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1770_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1771_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1772
7c58044c
JM		 1773#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1774GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1775{ \
76a66253 1776 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1777 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1778 return; \
1779 } \
a5e26afa
AJ		 1780 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1781 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1782 gen_reset_fpstatus(); \
4ecc3190
FB		 1783 gen_op_f##op(); \
1784 if (isfloat) { \
1785 gen_op_frsp(); \
1786 } \
a5e26afa 1787 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1788 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1789}
7c58044c
JM		 1790#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1791_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1792_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1793
7c58044c
JM		 1794#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1795GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1796{ \
76a66253 1797 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1798 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1799 return; \
1800 } \
a5e26afa
AJ		 1801 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1802 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
7c58044c 1803 gen_reset_fpstatus(); \
4ecc3190
FB		 1804 gen_op_f##op(); \
1805 if (isfloat) { \
1806 gen_op_frsp(); \
1807 } \
a5e26afa 1808 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1809 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1810}
7c58044c
JM		 1811#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1812_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1813_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1814
7c58044c 1815#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 1816GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 1817{ \
76a66253 1818 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1819 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1820 return; \
1821 } \
a5e26afa 1822 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1823 gen_reset_fpstatus(); \
9a64fbe4 1824 gen_op_f##name(); \
a5e26afa 1825 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1826 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1827}
1828
7c58044c 1829#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 1830GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 1831{ \
76a66253 1832 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1833 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1834 return; \
1835 } \
a5e26afa 1836 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1837 gen_reset_fpstatus(); \
9a64fbe4 1838 gen_op_f##name(); \
a5e26afa 1839 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1840 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1841}
1842
9a64fbe4 1843/* fadd - fadds */
7c58044c 1844GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1845/* fdiv - fdivs */
7c58044c 1846GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1847/* fmul - fmuls */
7c58044c 1848GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 1849
d7e4b87e 1850/* fre */
7c58044c 1851GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 1852
a750fc0b 1853/* fres */
7c58044c 1854GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 1855
a750fc0b 1856/* frsqrte */
7c58044c
JM		 1857GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1858
1859/* frsqrtes */
1860static always_inline void gen_op_frsqrtes (void)
1861{
1862 gen_op_frsqrte();
1863 gen_op_frsp();
1864}
1b413d55 1865GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 1866
a750fc0b 1867/* fsel */
7c58044c 1868_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 1869/* fsub - fsubs */
7c58044c 1870GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 1871/* Optional: */
1872/* fsqrt */
a750fc0b 1873GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 1874{
76a66253 1875 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1876 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 1877 return;
1878 }
a5e26afa 1879 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1880 gen_reset_fpstatus();
c7d344af 1881 gen_op_fsqrt();
a5e26afa 1882 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1883 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 1884}
79aceca5 1885
a750fc0b 1886GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 1887{
76a66253 1888 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1889 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1890 return;
1891 }
a5e26afa 1892 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1893 gen_reset_fpstatus();
4ecc3190
FB		 1894 gen_op_fsqrt();
1895 gen_op_frsp();
a5e26afa 1896 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1897 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 1898}
1899
1900/*** Floating-Point multiply-and-add ***/
4ecc3190 1901/* fmadd - fmadds */
7c58044c 1902GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 1903/* fmsub - fmsubs */
7c58044c 1904GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 1905/* fnmadd - fnmadds */
7c58044c 1906GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 1907/* fnmsub - fnmsubs */
7c58044c 1908GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 1909
1910/*** Floating-Point round & convert ***/
1911/* fctiw */
7c58044c 1912GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 1913/* fctiwz */
7c58044c 1914GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 1915/* frsp */
7c58044c 1916GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 1917#if defined(TARGET_PPC64)
1918/* fcfid */
7c58044c 1919GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 1920/* fctid */
7c58044c 1921GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 1922/* fctidz */
7c58044c 1923GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 1924#endif
79aceca5 1925
d7e4b87e 1926/* frin */
7c58044c 1927GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 1928/* friz */
7c58044c 1929GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 1930/* frip */
7c58044c 1931GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 1932/* frim */
7c58044c 1933GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 1934
79aceca5
FB		 1935/*** Floating-Point compare ***/
1936/* fcmpo */
76a66253 1937GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 1938{
76a66253 1939 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1940 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1941 return;
1942 }
a5e26afa
AJ		 1943 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
1944 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1945 gen_reset_fpstatus();
9a64fbe4 1946 gen_op_fcmpo();
47e4661c 1947 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
7c58044c 1948 gen_op_float_check_status();
79aceca5
FB		 1949}
1950
1951/* fcmpu */
76a66253 1952GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 1953{
76a66253 1954 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1955 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1956 return;
1957 }
a5e26afa
AJ		 1958 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
1959 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1960 gen_reset_fpstatus();
9a64fbe4 1961 gen_op_fcmpu();
47e4661c 1962 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
7c58044c 1963 gen_op_float_check_status();
79aceca5
FB		 1964}
1965
9a64fbe4
FB		 1966/*** Floating-point move ***/
1967/* fabs */
7c58044c
JM		 1968/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1969GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 1970
1971/* fmr - fmr. */
7c58044c 1972/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 1973GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1974{
76a66253 1975 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1976 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1977 return;
1978 }
a5e26afa
AJ		 1979 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
1980 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1981 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 1982}
1983
1984/* fnabs */
7c58044c
JM		 1985/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1986GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 1987/* fneg */
7c58044c
JM		 1988/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1989GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 1990
79aceca5
FB		 1991/*** Floating-Point status & ctrl register ***/
1992/* mcrfs */
1993GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1994{
7c58044c
JM		 1995 int bfa;
1996
76a66253 1997 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1998 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1999 return;
2000 }
7c58044c
JM		 2001 gen_optimize_fprf();
2002 bfa = 4 * (7 - crfS(ctx->opcode));
2003 gen_op_load_fpscr_T0(bfa);
47e4661c 2004 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
7c58044c 2005 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 2006}
2007
2008/* mffs */
2009GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2010{
76a66253 2011 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2012 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2013 return;
2014 }
7c58044c
JM		 2015 gen_optimize_fprf();
2016 gen_reset_fpstatus();
2017 gen_op_load_fpscr_FT0();
a5e26afa 2018 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2019 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2020}
2021
2022/* mtfsb0 */
2023GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2024{
fb0eaffc 2025 uint8_t crb;
3b46e624 2026
76a66253 2027 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2028 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2029 return;
2030 }
7c58044c
JM		 2031 crb = 32 - (crbD(ctx->opcode) >> 2);
2032 gen_optimize_fprf();
2033 gen_reset_fpstatus();
2034 if (likely(crb != 30 && crb != 29))
2035 gen_op_fpscr_resetbit(~(1 << crb));
2036 if (unlikely(Rc(ctx->opcode) != 0)) {
2037 gen_op_load_fpcc();
2038 gen_op_set_Rc0();
2039 }
79aceca5
FB		 2040}
2041
2042/* mtfsb1 */
2043GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2044{
fb0eaffc 2045 uint8_t crb;
3b46e624 2046
76a66253 2047 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2048 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2049 return;
2050 }
7c58044c
JM		 2051 crb = 32 - (crbD(ctx->opcode) >> 2);
2052 gen_optimize_fprf();
2053 gen_reset_fpstatus();
2054 /* XXX: we pretend we can only do IEEE floating-point computations */
2055 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2056 gen_op_fpscr_setbit(crb);
2057 if (unlikely(Rc(ctx->opcode) != 0)) {
2058 gen_op_load_fpcc();
2059 gen_op_set_Rc0();
2060 }
2061 /* We can raise a differed exception */
2062 gen_op_float_check_status();
79aceca5
FB		 2063}
2064
2065/* mtfsf */
2066GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2067{
76a66253 2068 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2069 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2070 return;
2071 }
7c58044c 2072 gen_optimize_fprf();
a5e26afa 2073 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2074 gen_reset_fpstatus();
28b6751f 2075 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c
JM		 2076 if (unlikely(Rc(ctx->opcode) != 0)) {
2077 gen_op_load_fpcc();
2078 gen_op_set_Rc0();
2079 }
2080 /* We can raise a differed exception */
2081 gen_op_float_check_status();
79aceca5
FB		 2082}
2083
2084/* mtfsfi */
2085GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2086{
7c58044c
JM		 2087 int bf, sh;
2088
76a66253 2089 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2090 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2091 return;
2092 }
7c58044c
JM		 2093 bf = crbD(ctx->opcode) >> 2;
2094 sh = 7 - bf;
2095 gen_optimize_fprf();
489251fa 2096 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
7c58044c
JM		 2097 gen_reset_fpstatus();
2098 gen_op_store_fpscr(1 << sh);
2099 if (unlikely(Rc(ctx->opcode) != 0)) {
2100 gen_op_load_fpcc();
2101 gen_op_set_Rc0();
2102 }
2103 /* We can raise a differed exception */
2104 gen_op_float_check_status();
79aceca5
FB		 2105}
2106
76a66253
JM		 2107/*** Addressing modes ***/
2108/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2109static always_inline void gen_addr_imm_index (TCGv EA,
2110 DisasContext *ctx,
b068d6a7 2111 target_long maskl)
76a66253
JM		 2112{
2113 target_long simm = SIMM(ctx->opcode);
2114
be147d08 2115 simm &= ~maskl;
e2be8d8d
AJ		 2116 if (rA(ctx->opcode) == 0)
2117 tcg_gen_movi_tl(EA, simm);
2118 else if (likely(simm != 0))
2119 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2120 else
2121 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2122}
2123
e2be8d8d
AJ		 2124static always_inline void gen_addr_reg_index (TCGv EA,
2125 DisasContext *ctx)
76a66253 2126{
e2be8d8d
AJ		 2127 if (rA(ctx->opcode) == 0)
2128 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2129 else
2130 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2131}
2132
e2be8d8d
AJ		 2133static always_inline void gen_addr_register (TCGv EA,
2134 DisasContext *ctx)
76a66253 2135{
e2be8d8d
AJ		 2136 if (rA(ctx->opcode) == 0)
2137 tcg_gen_movi_tl(EA, 0);
2138 else
2139 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2140}
2141
7863667f
JM		 2142#if defined(TARGET_PPC64)
2143#define _GEN_MEM_FUNCS(name, mode) \
2144 &gen_op_##name##_##mode, \
2145 &gen_op_##name##_le_##mode, \
2146 &gen_op_##name##_64_##mode, \
2147 &gen_op_##name##_le_64_##mode
2148#else
2149#define _GEN_MEM_FUNCS(name, mode) \
2150 &gen_op_##name##_##mode, \
2151 &gen_op_##name##_le_##mode
2152#endif
9a64fbe4 2153#if defined(CONFIG_USER_ONLY)
d9bce9d9 2154#if defined(TARGET_PPC64)
7863667f 2155#define NB_MEM_FUNCS 4
d9bce9d9 2156#else
7863667f 2157#define NB_MEM_FUNCS 2
d9bce9d9 2158#endif
7863667f
JM		 2159#define GEN_MEM_FUNCS(name) \
2160 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2161#else
d9bce9d9 2162#if defined(TARGET_PPC64)
7863667f 2163#define NB_MEM_FUNCS 12
2857068e 2164#else
7863667f 2165#define NB_MEM_FUNCS 6
2857068e 2166#endif
7863667f
JM		 2167#define GEN_MEM_FUNCS(name) \
2168 _GEN_MEM_FUNCS(name, user), \
2169 _GEN_MEM_FUNCS(name, kernel), \
2170 _GEN_MEM_FUNCS(name, hypv)
2171#endif
2172
2173/*** Integer load ***/
2174#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
111bfab3 2175/* Byte access routine are endian safe */
7863667f
JM		 2176#define gen_op_lbz_le_raw gen_op_lbz_raw
2177#define gen_op_lbz_le_user gen_op_lbz_user
2178#define gen_op_lbz_le_kernel gen_op_lbz_kernel
2179#define gen_op_lbz_le_hypv gen_op_lbz_hypv
2180#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2857068e 2181#define gen_op_lbz_le_64_user gen_op_lbz_64_user
d9bce9d9 2182#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
7863667f
JM		 2183#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2184#define gen_op_stb_le_raw gen_op_stb_raw
2185#define gen_op_stb_le_user gen_op_stb_user
2186#define gen_op_stb_le_kernel gen_op_stb_kernel
2187#define gen_op_stb_le_hypv gen_op_stb_hypv
2188#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2189#define gen_op_stb_le_64_user gen_op_stb_64_user
2190#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2191#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
d9bce9d9 2192#define OP_LD_TABLE(width) \
7863667f
JM		 2193static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2194 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2195};
2196#define OP_ST_TABLE(width) \
7863667f
JM		 2197static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2198 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2199};
9a64fbe4 2200
d9bce9d9
JM		 2201#define GEN_LD(width, opc, type) \
2202GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2203{ \
e2be8d8d 2204 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 2205 op_ldst(l##width); \
f78fb44e 2206 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
79aceca5
FB		 2207}
2208
d9bce9d9
JM		 2209#define GEN_LDU(width, opc, type) \
2210GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2211{ \
76a66253
JM		 2212 if (unlikely(rA(ctx->opcode) == 0 || \
2213 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2214 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2215 return; \
9a64fbe4 2216 } \
9d53c753 2217 if (type == PPC_64B) \
e2be8d8d 2218 gen_addr_imm_index(cpu_T[0], ctx, 0x03); \
9d53c753 2219 else \
e2be8d8d 2220 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 2221 op_ldst(l##width); \
f78fb44e
AJ		 2222 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
2223 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2224}
2225
d9bce9d9
JM		 2226#define GEN_LDUX(width, opc2, opc3, type) \
2227GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2228{ \
76a66253
JM		 2229 if (unlikely(rA(ctx->opcode) == 0 || \
2230 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2231 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2232 return; \
9a64fbe4 2233 } \
e2be8d8d 2234 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 2235 op_ldst(l##width); \
f78fb44e
AJ		 2236 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
2237 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2238}
2239
d9bce9d9
JM		 2240#define GEN_LDX(width, opc2, opc3, type) \
2241GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2242{ \
e2be8d8d 2243 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 2244 op_ldst(l##width); \
f78fb44e 2245 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
79aceca5
FB		 2246}
2247
d9bce9d9 2248#define GEN_LDS(width, op, type) \
9a64fbe4 2249OP_LD_TABLE(width); \
d9bce9d9
JM		 2250GEN_LD(width, op | 0x20, type); \
2251GEN_LDU(width, op | 0x21, type); \
2252GEN_LDUX(width, 0x17, op | 0x01, type); \
2253GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2254
2255/* lbz lbzu lbzux lbzx */
d9bce9d9 2256GEN_LDS(bz, 0x02, PPC_INTEGER);
79aceca5 2257/* lha lhau lhaux lhax */
d9bce9d9 2258GEN_LDS(ha, 0x0A, PPC_INTEGER);
79aceca5 2259/* lhz lhzu lhzux lhzx */
d9bce9d9 2260GEN_LDS(hz, 0x08, PPC_INTEGER);
79aceca5 2261/* lwz lwzu lwzux lwzx */
d9bce9d9
JM		 2262GEN_LDS(wz, 0x00, PPC_INTEGER);
2263#if defined(TARGET_PPC64)
2264OP_LD_TABLE(wa);
2265OP_LD_TABLE(d);
2266/* lwaux */
2267GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2268/* lwax */
2269GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2270/* ldux */
2271GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2272/* ldx */
2273GEN_LDX(d, 0x15, 0x00, PPC_64B);
2274GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2275{
2276 if (Rc(ctx->opcode)) {
2277 if (unlikely(rA(ctx->opcode) == 0 ||
2278 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2279 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2280 return;
2281 }
2282 }
e2be8d8d 2283 gen_addr_imm_index(cpu_T[0], ctx, 0x03);
d9bce9d9
JM		 2284 if (ctx->opcode & 0x02) {
2285 /* lwa (lwau is undefined) */
2286 op_ldst(lwa);
2287 } else {
2288 /* ld - ldu */
2289 op_ldst(ld);
2290 }
f78fb44e 2291 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
d9bce9d9 2292 if (Rc(ctx->opcode))
f78fb44e 2293 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9 2294}
be147d08
JM		 2295/* lq */
2296GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2297{
2298#if defined(CONFIG_USER_ONLY)
2299 GEN_EXCP_PRIVOPC(ctx);
2300#else
2301 int ra, rd;
2302
2303 /* Restore CPU state */
2304 if (unlikely(ctx->supervisor == 0)) {
2305 GEN_EXCP_PRIVOPC(ctx);
2306 return;
2307 }
2308 ra = rA(ctx->opcode);
2309 rd = rD(ctx->opcode);
2310 if (unlikely((rd & 1) || rd == ra)) {
2311 GEN_EXCP_INVAL(ctx);
2312 return;
2313 }
2314 if (unlikely(ctx->mem_idx & 1)) {
2315 /* Little-endian mode is not handled */
2316 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2317 return;
2318 }
e2be8d8d 2319 gen_addr_imm_index(cpu_T[0], ctx, 0x0F);
be147d08 2320 op_ldst(ld);
f78fb44e 2321 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]);
39dd32ee 2322 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8);
be147d08 2323 op_ldst(ld);
f78fb44e 2324 tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]);
be147d08
JM		 2325#endif
2326}
d9bce9d9 2327#endif
79aceca5
FB		 2328
2329/*** Integer store ***/
d9bce9d9
JM		 2330#define GEN_ST(width, opc, type) \
2331GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2332{ \
e2be8d8d 2333 gen_addr_imm_index(cpu_T[0], ctx, 0); \
f78fb44e 2334 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
9a64fbe4 2335 op_ldst(st##width); \
79aceca5
FB		 2336}
2337
d9bce9d9
JM		 2338#define GEN_STU(width, opc, type) \
2339GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2340{ \
76a66253 2341 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2342 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2343 return; \
9a64fbe4 2344 } \
9d53c753 2345 if (type == PPC_64B) \
e2be8d8d 2346 gen_addr_imm_index(cpu_T[0], ctx, 0x03); \
9d53c753 2347 else \
e2be8d8d 2348 gen_addr_imm_index(cpu_T[0], ctx, 0); \
f78fb44e 2349 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
9a64fbe4 2350 op_ldst(st##width); \
f78fb44e 2351 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2352}
2353
d9bce9d9
JM		 2354#define GEN_STUX(width, opc2, opc3, type) \
2355GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2356{ \
76a66253 2357 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2358 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2359 return; \
9a64fbe4 2360 } \
e2be8d8d 2361 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 2362 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
9a64fbe4 2363 op_ldst(st##width); \
f78fb44e 2364 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2365}
2366
d9bce9d9
JM		 2367#define GEN_STX(width, opc2, opc3, type) \
2368GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2369{ \
e2be8d8d 2370 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 2371 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
9a64fbe4 2372 op_ldst(st##width); \
79aceca5
FB		 2373}
2374
d9bce9d9 2375#define GEN_STS(width, op, type) \
9a64fbe4 2376OP_ST_TABLE(width); \
d9bce9d9
JM		 2377GEN_ST(width, op | 0x20, type); \
2378GEN_STU(width, op | 0x21, type); \
2379GEN_STUX(width, 0x17, op | 0x01, type); \
2380GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2381
2382/* stb stbu stbux stbx */
d9bce9d9 2383GEN_STS(b, 0x06, PPC_INTEGER);
79aceca5 2384/* sth sthu sthux sthx */
d9bce9d9 2385GEN_STS(h, 0x0C, PPC_INTEGER);
79aceca5 2386/* stw stwu stwux stwx */
d9bce9d9
JM		 2387GEN_STS(w, 0x04, PPC_INTEGER);
2388#if defined(TARGET_PPC64)
2389OP_ST_TABLE(d);
426613db
JM		 2390GEN_STUX(d, 0x15, 0x05, PPC_64B);
2391GEN_STX(d, 0x15, 0x04, PPC_64B);
be147d08 2392GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2393{
be147d08
JM		 2394 int rs;
2395
2396 rs = rS(ctx->opcode);
2397 if ((ctx->opcode & 0x3) == 0x2) {
2398#if defined(CONFIG_USER_ONLY)
2399 GEN_EXCP_PRIVOPC(ctx);
2400#else
2401 /* stq */
2402 if (unlikely(ctx->supervisor == 0)) {
2403 GEN_EXCP_PRIVOPC(ctx);
2404 return;
2405 }
2406 if (unlikely(rs & 1)) {
e1833e1f 2407 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2408 return;
2409 }
be147d08
JM		 2410 if (unlikely(ctx->mem_idx & 1)) {
2411 /* Little-endian mode is not handled */
2412 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2413 return;
2414 }
e2be8d8d 2415 gen_addr_imm_index(cpu_T[0], ctx, 0x03);
f78fb44e 2416 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
be147d08 2417 op_ldst(std);
39dd32ee 2418 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8);
f78fb44e 2419 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]);
be147d08
JM		 2420 op_ldst(std);
2421#endif
2422 } else {
2423 /* std / stdu */
2424 if (Rc(ctx->opcode)) {
2425 if (unlikely(rA(ctx->opcode) == 0)) {
2426 GEN_EXCP_INVAL(ctx);
2427 return;
2428 }
2429 }
e2be8d8d 2430 gen_addr_imm_index(cpu_T[0], ctx, 0x03);
f78fb44e 2431 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
be147d08
JM		 2432 op_ldst(std);
2433 if (Rc(ctx->opcode))
f78fb44e 2434 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9 2435 }
d9bce9d9
JM		 2436}
2437#endif
79aceca5
FB		 2438/*** Integer load and store with byte reverse ***/
2439/* lhbrx */
9a64fbe4 2440OP_LD_TABLE(hbr);
d9bce9d9 2441GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
79aceca5 2442/* lwbrx */
9a64fbe4 2443OP_LD_TABLE(wbr);
d9bce9d9 2444GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
79aceca5 2445/* sthbrx */
9a64fbe4 2446OP_ST_TABLE(hbr);
d9bce9d9 2447GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
79aceca5 2448/* stwbrx */
9a64fbe4 2449OP_ST_TABLE(wbr);
d9bce9d9 2450GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2451
2452/*** Integer load and store multiple ***/
111bfab3 2453#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 2454static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2455 GEN_MEM_FUNCS(lmw),
d9bce9d9 2456};
7863667f
JM		 2457static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2458 GEN_MEM_FUNCS(stmw),
d9bce9d9 2459};
9a64fbe4 2460
79aceca5
FB		 2461/* lmw */
2462GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2463{
76a66253 2464 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2465 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2466 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2467 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2468}
2469
2470/* stmw */
2471GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2472{
76a66253 2473 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2474 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2475 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2476 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2477}
2478
2479/*** Integer load and store strings ***/
9a64fbe4
FB		 2480#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2481#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 2482/* string load & stores are by definition endian-safe */
2483#define gen_op_lswi_le_raw gen_op_lswi_raw
2484#define gen_op_lswi_le_user gen_op_lswi_user
2485#define gen_op_lswi_le_kernel gen_op_lswi_kernel
2486#define gen_op_lswi_le_hypv gen_op_lswi_hypv
2487#define gen_op_lswi_le_64_raw gen_op_lswi_raw
2488#define gen_op_lswi_le_64_user gen_op_lswi_user
2489#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2490#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 2491static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2492 GEN_MEM_FUNCS(lswi),
d9bce9d9 2493};
e7c24003
JM		 2494#define gen_op_lswx_le_raw gen_op_lswx_raw
2495#define gen_op_lswx_le_user gen_op_lswx_user
2496#define gen_op_lswx_le_kernel gen_op_lswx_kernel
2497#define gen_op_lswx_le_hypv gen_op_lswx_hypv
2498#define gen_op_lswx_le_64_raw gen_op_lswx_raw
2499#define gen_op_lswx_le_64_user gen_op_lswx_user
2500#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2501#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 2502static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2503 GEN_MEM_FUNCS(lswx),
d9bce9d9 2504};
e7c24003
JM		 2505#define gen_op_stsw_le_raw gen_op_stsw_raw
2506#define gen_op_stsw_le_user gen_op_stsw_user
2507#define gen_op_stsw_le_kernel gen_op_stsw_kernel
2508#define gen_op_stsw_le_hypv gen_op_stsw_hypv
2509#define gen_op_stsw_le_64_raw gen_op_stsw_raw
2510#define gen_op_stsw_le_64_user gen_op_stsw_user
2511#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2512#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 2513static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2514 GEN_MEM_FUNCS(stsw),
9a64fbe4 2515};
9a64fbe4 2516
79aceca5 2517/* lswi */
3fc6c082 2518/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2519 * rA is in the range of registers to be loaded.
2520 * In an other hand, IBM says this is valid, but rA won't be loaded.
2521 * For now, I'll follow the spec...
2522 */
05332d70 2523GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 2524{
2525 int nb = NB(ctx->opcode);
2526 int start = rD(ctx->opcode);
9a64fbe4 2527 int ra = rA(ctx->opcode);
79aceca5
FB		 2528 int nr;
2529
2530 if (nb == 0)
2531 nb = 32;
2532 nr = nb / 4;
76a66253
JM		 2533 if (unlikely(((start + nr) > 32 &&
2534 start <= ra && (start + nr - 32) > ra) ||
2535 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 2536 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2537 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2538 return;
297d8e62 2539 }
8dd4983c 2540 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2541 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2542 gen_addr_register(cpu_T[0], ctx);
86c581dc 2543 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 2544 op_ldsts(lswi, start);
79aceca5
FB		 2545}
2546
2547/* lswx */
05332d70 2548GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 2549{
9a64fbe4
FB		 2550 int ra = rA(ctx->opcode);
2551 int rb = rB(ctx->opcode);
2552
76a66253 2553 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2554 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2555 gen_addr_reg_index(cpu_T[0], ctx);
9a64fbe4 2556 if (ra == 0) {
9a64fbe4 2557 ra = rb;
79aceca5 2558 }
9a64fbe4
FB		 2559 gen_op_load_xer_bc();
2560 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 2561}
2562
2563/* stswi */
05332d70 2564GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 2565{
4b3686fa
FB		 2566 int nb = NB(ctx->opcode);
2567
76a66253 2568 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2569 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2570 gen_addr_register(cpu_T[0], ctx);
4b3686fa
FB		 2571 if (nb == 0)
2572 nb = 32;
86c581dc 2573 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 2574 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2575}
2576
2577/* stswx */
05332d70 2578GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 2579{
8dd4983c 2580 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 2581 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2582 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 2583 gen_op_load_xer_bc();
9a64fbe4 2584 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2585}
2586
2587/*** Memory synchronisation ***/
2588/* eieio */
0db1b20e 2589GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 2590{
79aceca5
FB		 2591}
2592
2593/* isync */
0db1b20e 2594GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 2595{
e1833e1f 2596 GEN_STOP(ctx);
79aceca5
FB		 2597}
2598
111bfab3
FB		 2599#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2600#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 2601static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2602 GEN_MEM_FUNCS(lwarx),
111bfab3 2603};
7863667f
JM		 2604static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2605 GEN_MEM_FUNCS(stwcx),
985a19d6 2606};
9a64fbe4 2607
111bfab3 2608/* lwarx */
76a66253 2609GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 2610{
30032c94
JM		 2611 /* NIP cannot be restored if the memory exception comes from an helper */
2612 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2613 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 2614 op_lwarx();
f78fb44e 2615 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 2616}
2617
2618/* stwcx. */
c7697e1f 2619GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 2620{
30032c94
JM		 2621 /* NIP cannot be restored if the memory exception comes from an helper */
2622 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2623 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 2624 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 2625 op_stwcx();
79aceca5
FB		 2626}
2627
426613db
JM		 2628#if defined(TARGET_PPC64)
2629#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2630#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 2631static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2632 GEN_MEM_FUNCS(ldarx),
426613db 2633};
7863667f
JM		 2634static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2635 GEN_MEM_FUNCS(stdcx),
426613db 2636};
426613db
JM		 2637
2638/* ldarx */
a750fc0b 2639GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 2640{
30032c94
JM		 2641 /* NIP cannot be restored if the memory exception comes from an helper */
2642 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2643 gen_addr_reg_index(cpu_T[0], ctx);
426613db 2644 op_ldarx();
f78fb44e 2645 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 2646}
2647
2648/* stdcx. */
c7697e1f 2649GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 2650{
30032c94
JM		 2651 /* NIP cannot be restored if the memory exception comes from an helper */
2652 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2653 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 2654 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 2655 op_stdcx();
2656}
2657#endif /* defined(TARGET_PPC64) */
2658
79aceca5 2659/* sync */
a902d886 2660GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 2661{
79aceca5
FB		 2662}
2663
0db1b20e
JM		 2664/* wait */
2665GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2666{
2667 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 2668 gen_op_wait();
2669 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 2670}
2671
79aceca5 2672/*** Floating-point load ***/
477023a6
JM		 2673#define GEN_LDF(width, opc, type) \
2674GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2675{ \
76a66253 2676 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2677 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2678 return; \
2679 } \
e2be8d8d 2680 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 2681 op_ldst(l##width); \
a5e26afa 2682 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 2683}
2684
477023a6
JM		 2685#define GEN_LDUF(width, opc, type) \
2686GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2687{ \
76a66253 2688 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2689 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2690 return; \
2691 } \
76a66253 2692 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2693 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2694 return; \
9a64fbe4 2695 } \
e2be8d8d 2696 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 2697 op_ldst(l##width); \
a5e26afa 2698 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 2699 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2700}
2701
477023a6
JM		 2702#define GEN_LDUXF(width, opc, type) \
2703GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2704{ \
76a66253 2705 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2706 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2707 return; \
2708 } \
76a66253 2709 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2710 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2711 return; \
9a64fbe4 2712 } \
e2be8d8d 2713 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 2714 op_ldst(l##width); \
a5e26afa 2715 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 2716 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2717}
2718
477023a6
JM		 2719#define GEN_LDXF(width, opc2, opc3, type) \
2720GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2721{ \
76a66253 2722 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2723 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2724 return; \
2725 } \
e2be8d8d 2726 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 2727 op_ldst(l##width); \
a5e26afa 2728 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 2729}
2730
477023a6 2731#define GEN_LDFS(width, op, type) \
9a64fbe4 2732OP_LD_TABLE(width); \
477023a6
JM		 2733GEN_LDF(width, op | 0x20, type); \
2734GEN_LDUF(width, op | 0x21, type); \
2735GEN_LDUXF(width, op | 0x01, type); \
2736GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 2737
2738/* lfd lfdu lfdux lfdx */
477023a6 2739GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 2740/* lfs lfsu lfsux lfsx */
477023a6 2741GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 2742
2743/*** Floating-point store ***/
477023a6
JM		 2744#define GEN_STF(width, opc, type) \
2745GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2746{ \
76a66253 2747 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2748 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2749 return; \
2750 } \
e2be8d8d 2751 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 2752 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 2753 op_ldst(st##width); \
79aceca5
FB		 2754}
2755
477023a6
JM		 2756#define GEN_STUF(width, opc, type) \
2757GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2758{ \
76a66253 2759 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2760 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2761 return; \
2762 } \
76a66253 2763 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2764 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2765 return; \
9a64fbe4 2766 } \
e2be8d8d 2767 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 2768 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 2769 op_ldst(st##width); \
f78fb44e 2770 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2771}
2772
477023a6
JM		 2773#define GEN_STUXF(width, opc, type) \
2774GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2775{ \
76a66253 2776 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2777 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2778 return; \
2779 } \
76a66253 2780 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2781 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2782 return; \
9a64fbe4 2783 } \
e2be8d8d 2784 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 2785 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 2786 op_ldst(st##width); \
f78fb44e 2787 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 2788}
2789
477023a6
JM		 2790#define GEN_STXF(width, opc2, opc3, type) \
2791GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2792{ \
76a66253 2793 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2794 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2795 return; \
2796 } \
e2be8d8d 2797 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 2798 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 2799 op_ldst(st##width); \
79aceca5
FB		 2800}
2801
477023a6 2802#define GEN_STFS(width, op, type) \
9a64fbe4 2803OP_ST_TABLE(width); \
477023a6
JM		 2804GEN_STF(width, op | 0x20, type); \
2805GEN_STUF(width, op | 0x21, type); \
2806GEN_STUXF(width, op | 0x01, type); \
2807GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 2808
2809/* stfd stfdu stfdux stfdx */
477023a6 2810GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 2811/* stfs stfsu stfsux stfsx */
477023a6 2812GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 2813
2814/* Optional: */
2815/* stfiwx */
5b8105fa
JM		 2816OP_ST_TABLE(fiw);
2817GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 2818
2819/*** Branch ***/
b068d6a7
JM		 2820static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2821 target_ulong dest)
c1942362
FB		 2822{
2823 TranslationBlock *tb;
2824 tb = ctx->tb;
57fec1fe 2825 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 2826 likely(!ctx->singlestep_enabled)) {
57fec1fe 2827 tcg_gen_goto_tb(n);
02f4f6c2 2828 tcg_gen_movi_tl(cpu_T[1], dest);
d9bce9d9
JM		 2829#if defined(TARGET_PPC64)
2830 if (ctx->sf_mode)
bd568f18 2831 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 2832 else
2833#endif
bd568f18 2834 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
57fec1fe 2835 tcg_gen_exit_tb((long)tb + n);
c1942362 2836 } else {
02f4f6c2 2837 tcg_gen_movi_tl(cpu_T[1], dest);
d9bce9d9
JM		 2838#if defined(TARGET_PPC64)
2839 if (ctx->sf_mode)
bd568f18 2840 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 2841 else
2842#endif
bd568f18 2843 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
8cbcb4fa
AJ		 2844 if (unlikely(ctx->singlestep_enabled)) {
2845 if ((ctx->singlestep_enabled &
2846 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
2847 ctx->exception == POWERPC_EXCP_BRANCH) {
2848 target_ulong tmp = ctx->nip;
2849 ctx->nip = dest;
2850 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
2851 ctx->nip = tmp;
2852 }
2853 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
2854 gen_update_nip(ctx, dest);
2855 gen_op_debug();
2856 }
2857 }
57fec1fe 2858 tcg_gen_exit_tb(0);
c1942362 2859 }
c53be334
FB		 2860}
2861
b068d6a7 2862static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 2863{
2864#if defined(TARGET_PPC64)
2865 if (ctx->sf_mode != 0 && (nip >> 32))
2866 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2867 else
2868#endif
2869 gen_op_setlr(ctx->nip);
2870}
2871
79aceca5
FB		 2872/* b ba bl bla */
2873GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2874{
76a66253 2875 target_ulong li, target;
38a64f9d 2876
8cbcb4fa 2877 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 2878 /* sign extend LI */
76a66253 2879#if defined(TARGET_PPC64)
d9bce9d9
JM		 2880 if (ctx->sf_mode)
2881 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
2882 else
76a66253 2883#endif
d9bce9d9 2884 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 2885 if (likely(AA(ctx->opcode) == 0))
046d6672 2886 target = ctx->nip + li - 4;
79aceca5 2887 else
9a64fbe4 2888 target = li;
d9bce9d9 2889#if defined(TARGET_PPC64)
e1833e1f
JM		 2890 if (!ctx->sf_mode)
2891 target = (uint32_t)target;
d9bce9d9 2892#endif
e1833e1f
JM		 2893 if (LK(ctx->opcode))
2894 gen_setlr(ctx, ctx->nip);
c1942362 2895 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 2896}
2897
e98a6e40
FB		 2898#define BCOND_IM 0
2899#define BCOND_LR 1
2900#define BCOND_CTR 2
2901
b068d6a7 2902static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 2903{
76a66253
JM		 2904 target_ulong target = 0;
2905 target_ulong li;
d9bce9d9
JM		 2906 uint32_t bo = BO(ctx->opcode);
2907 uint32_t bi = BI(ctx->opcode);
2908 uint32_t mask;
e98a6e40 2909
8cbcb4fa 2910 ctx->exception = POWERPC_EXCP_BRANCH;
e98a6e40 2911 if ((bo & 0x4) == 0)
d9bce9d9 2912 gen_op_dec_ctr();
e98a6e40
FB		 2913 switch(type) {
2914 case BCOND_IM:
76a66253
JM		 2915 li = (target_long)((int16_t)(BD(ctx->opcode)));
2916 if (likely(AA(ctx->opcode) == 0)) {
046d6672 2917 target = ctx->nip + li - 4;
e98a6e40
FB		 2918 } else {
2919 target = li;
2920 }
e1833e1f
JM		 2921#if defined(TARGET_PPC64)
2922 if (!ctx->sf_mode)
2923 target = (uint32_t)target;
2924#endif
e98a6e40
FB		 2925 break;
2926 case BCOND_CTR:
2927 gen_op_movl_T1_ctr();
2928 break;
2929 default:
2930 case BCOND_LR:
2931 gen_op_movl_T1_lr();
2932 break;
2933 }
e1833e1f
JM		 2934 if (LK(ctx->opcode))
2935 gen_setlr(ctx, ctx->nip);
e98a6e40 2936 if (bo & 0x10) {
d9bce9d9
JM		 2937 /* No CR condition */
2938 switch (bo & 0x6) {
2939 case 0:
2940#if defined(TARGET_PPC64)
2941 if (ctx->sf_mode)
2942 gen_op_test_ctr_64();
2943 else
2944#endif
2945 gen_op_test_ctr();
2946 break;
2947 case 2:
2948#if defined(TARGET_PPC64)
2949 if (ctx->sf_mode)
2950 gen_op_test_ctrz_64();
2951 else
2952#endif
2953 gen_op_test_ctrz();
e98a6e40 2954 break;
e98a6e40 2955 default:
d9bce9d9
JM		 2956 case 4:
2957 case 6:
e98a6e40 2958 if (type == BCOND_IM) {
c1942362 2959 gen_goto_tb(ctx, 0, target);
8cbcb4fa 2960 return;
e98a6e40 2961 } else {
d9bce9d9
JM		 2962#if defined(TARGET_PPC64)
2963 if (ctx->sf_mode)
bd568f18 2964 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 2965 else
2966#endif
bd568f18 2967 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
056b05f8 2968 goto no_test;
e98a6e40 2969 }
056b05f8 2970 break;
e98a6e40 2971 }
d9bce9d9
JM		 2972 } else {
2973 mask = 1 << (3 - (bi & 0x03));
47e4661c 2974 tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]);
d9bce9d9
JM		 2975 if (bo & 0x8) {
2976 switch (bo & 0x6) {
2977 case 0:
2978#if defined(TARGET_PPC64)
2979 if (ctx->sf_mode)
2980 gen_op_test_ctr_true_64(mask);
2981 else
2982#endif
2983 gen_op_test_ctr_true(mask);
2984 break;
2985 case 2:
2986#if defined(TARGET_PPC64)
2987 if (ctx->sf_mode)
2988 gen_op_test_ctrz_true_64(mask);
2989 else
2990#endif
2991 gen_op_test_ctrz_true(mask);
2992 break;
2993 default:
2994 case 4:
2995 case 6:
e98a6e40 2996 gen_op_test_true(mask);
d9bce9d9
JM		 2997 break;
2998 }
2999 } else {
3000 switch (bo & 0x6) {
3001 case 0:
3002#if defined(TARGET_PPC64)
3003 if (ctx->sf_mode)
3004 gen_op_test_ctr_false_64(mask);
3005 else
3006#endif
3007 gen_op_test_ctr_false(mask);
3b46e624 3008 break;
d9bce9d9
JM		 3009 case 2:
3010#if defined(TARGET_PPC64)
3011 if (ctx->sf_mode)
3012 gen_op_test_ctrz_false_64(mask);
3013 else
3014#endif
3015 gen_op_test_ctrz_false(mask);
3016 break;
e98a6e40 3017 default:
d9bce9d9
JM		 3018 case 4:
3019 case 6:
e98a6e40 3020 gen_op_test_false(mask);
d9bce9d9
JM		 3021 break;
3022 }
3023 }
3024 }
e98a6e40 3025 if (type == BCOND_IM) {
c53be334
FB		 3026 int l1 = gen_new_label();
3027 gen_op_jz_T0(l1);
c1942362 3028 gen_goto_tb(ctx, 0, target);
c53be334 3029 gen_set_label(l1);
c1942362 3030 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3031 } else {
d9bce9d9
JM		 3032#if defined(TARGET_PPC64)
3033 if (ctx->sf_mode)
3034 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3035 else
3036#endif
3037 gen_op_btest_T1(ctx->nip);
36081602 3038 no_test:
57fec1fe 3039 tcg_gen_exit_tb(0);
08e46e54 3040 }
e98a6e40
FB		 3041}
3042
3043GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3044{
e98a6e40
FB		 3045 gen_bcond(ctx, BCOND_IM);
3046}
3047
3048GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3049{
e98a6e40
FB		 3050 gen_bcond(ctx, BCOND_CTR);
3051}
3052
3053GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3054{
e98a6e40
FB		 3055 gen_bcond(ctx, BCOND_LR);
3056}
79aceca5
FB		 3057
3058/*** Condition register logical ***/
3059#define GEN_CRLOGIC(op, opc) \
3060GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3061{ \
fc0d441e
JM		 3062 uint8_t bitmask; \
3063 int sh; \
47e4661c 3064 tcg_gen_mov_i32(cpu_T[0], cpu_crf[crbA(ctx->opcode) >> 2]); \
fc0d441e
JM		 3065 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3066 if (sh > 0) \
3067 gen_op_srli_T0(sh); \
3068 else if (sh < 0) \
3069 gen_op_sli_T0(-sh); \
47e4661c 3070 tcg_gen_mov_i32(cpu_T[1], cpu_crf[crbB(ctx->opcode) >> 2]); \
fc0d441e
JM		 3071 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3072 if (sh > 0) \
3073 gen_op_srli_T1(sh); \
3074 else if (sh < 0) \
3075 gen_op_sli_T1(-sh); \
79aceca5 3076 gen_op_##op(); \
fc0d441e 3077 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
0df5bdbe 3078 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], bitmask); \
47e4661c 3079 tcg_gen_andi_i32(cpu_T[1], cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
fc0d441e 3080 gen_op_or(); \
47e4661c 3081 tcg_gen_andi_i32(cpu_crf[crbD(ctx->opcode) >> 2], cpu_T[0], 0xf); \
79aceca5
FB		 3082}
3083
3084/* crand */
76a66253 3085GEN_CRLOGIC(and, 0x08);
79aceca5 3086/* crandc */
76a66253 3087GEN_CRLOGIC(andc, 0x04);
79aceca5 3088/* creqv */
76a66253 3089GEN_CRLOGIC(eqv, 0x09);
79aceca5 3090/* crnand */
76a66253 3091GEN_CRLOGIC(nand, 0x07);
79aceca5 3092/* crnor */
76a66253 3093GEN_CRLOGIC(nor, 0x01);
79aceca5 3094/* cror */
76a66253 3095GEN_CRLOGIC(or, 0x0E);
79aceca5 3096/* crorc */
76a66253 3097GEN_CRLOGIC(orc, 0x0D);
79aceca5 3098/* crxor */
76a66253 3099GEN_CRLOGIC(xor, 0x06);
79aceca5
FB		 3100/* mcrf */
3101GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3102{
47e4661c 3103 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3104}
3105
3106/*** System linkage ***/
3107/* rfi (supervisor only) */
76a66253 3108GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3109{
9a64fbe4 3110#if defined(CONFIG_USER_ONLY)
e1833e1f 3111 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3112#else
3113 /* Restore CPU state */
76a66253 3114 if (unlikely(!ctx->supervisor)) {
e1833e1f 3115 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3116 return;
9a64fbe4 3117 }
a42bd6cc 3118 gen_op_rfi();
e1833e1f 3119 GEN_SYNC(ctx);
9a64fbe4 3120#endif
79aceca5
FB		 3121}
3122
426613db 3123#if defined(TARGET_PPC64)
a750fc0b 3124GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3125{
3126#if defined(CONFIG_USER_ONLY)
e1833e1f 3127 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3128#else
3129 /* Restore CPU state */
3130 if (unlikely(!ctx->supervisor)) {
e1833e1f 3131 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3132 return;
3133 }
a42bd6cc 3134 gen_op_rfid();
e1833e1f 3135 GEN_SYNC(ctx);
426613db
JM		 3136#endif
3137}
426613db 3138
5b8105fa 3139GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3140{
3141#if defined(CONFIG_USER_ONLY)
3142 GEN_EXCP_PRIVOPC(ctx);
3143#else
3144 /* Restore CPU state */
3145 if (unlikely(ctx->supervisor <= 1)) {
3146 GEN_EXCP_PRIVOPC(ctx);
3147 return;
3148 }
3149 gen_op_hrfid();
3150 GEN_SYNC(ctx);
3151#endif
3152}
3153#endif
3154
79aceca5 3155/* sc */
417bf010
JM		 3156#if defined(CONFIG_USER_ONLY)
3157#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3158#else
3159#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3160#endif
e1833e1f 3161GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3162{
e1833e1f
JM		 3163 uint32_t lev;
3164
3165 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3166 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3167}
3168
3169/*** Trap ***/
3170/* tw */
76a66253 3171GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3172{
f78fb44e
AJ		 3173 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3174 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
a0ae05aa 3175 /* Update the nip since this might generate a trap exception */
d9bce9d9 3176 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3177 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3178}
3179
3180/* twi */
3181GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3182{
f78fb44e 3183 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3184 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3185 /* Update the nip since this might generate a trap exception */
3186 gen_update_nip(ctx, ctx->nip);
76a66253 3187 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3188}
3189
d9bce9d9
JM		 3190#if defined(TARGET_PPC64)
3191/* td */
3192GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3193{
f78fb44e
AJ		 3194 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3195 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3196 /* Update the nip since this might generate a trap exception */
3197 gen_update_nip(ctx, ctx->nip);
3198 gen_op_td(TO(ctx->opcode));
3199}
3200
3201/* tdi */
3202GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3203{
f78fb44e 3204 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3205 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3206 /* Update the nip since this might generate a trap exception */
3207 gen_update_nip(ctx, ctx->nip);
3208 gen_op_td(TO(ctx->opcode));
3209}
3210#endif
3211
79aceca5 3212/*** Processor control ***/
79aceca5
FB		 3213/* mcrxr */
3214GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3215{
3216 gen_op_load_xer_cr();
47e4661c 3217 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
e864cabd
JM		 3218 gen_op_clear_xer_ov();
3219 gen_op_clear_xer_ca();
79aceca5
FB		 3220}
3221
3222/* mfcr */
76a66253 3223GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3224{
76a66253 3225 uint32_t crm, crn;
3b46e624 3226
76a66253
JM		 3227 if (likely(ctx->opcode & 0x00100000)) {
3228 crm = CRM(ctx->opcode);
3229 if (likely((crm ^ (crm - 1)) == 0)) {
3230 crn = ffs(crm);
47e4661c 3231 tcg_gen_mov_i32(cpu_T[0], cpu_crf[7 - crn]);
76a66253 3232 }
d9bce9d9 3233 } else {
6676f424 3234 gen_op_load_cr();
d9bce9d9 3235 }
f78fb44e 3236 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 3237}
3238
3239/* mfmsr */
3240GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3241{
9a64fbe4 3242#if defined(CONFIG_USER_ONLY)
e1833e1f 3243 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3244#else
76a66253 3245 if (unlikely(!ctx->supervisor)) {
e1833e1f 3246 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3247 return;
9a64fbe4 3248 }
6676f424 3249 gen_op_load_msr();
f78fb44e 3250 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3251#endif
79aceca5
FB		 3252}
3253
a11b8151 3254#if 1
6f2d8978 3255#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3256#else
3257static void spr_noaccess (void *opaque, int sprn)
3258{
3259 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3260 printf("ERROR: try to access SPR %d !\n", sprn);
3261}
3262#define SPR_NOACCESS (&spr_noaccess)
3263#endif
3264
79aceca5 3265/* mfspr */
b068d6a7 3266static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3267{
3fc6c082 3268 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3269 uint32_t sprn = SPR(ctx->opcode);
3270
3fc6c082 3271#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3272 if (ctx->supervisor == 2)
3273 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3274 else if (ctx->supervisor)
3fc6c082
FB		 3275 read_cb = ctx->spr_cb[sprn].oea_read;
3276 else
9a64fbe4 3277#endif
3fc6c082 3278 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3279 if (likely(read_cb != NULL)) {
3280 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3281 (*read_cb)(ctx, sprn);
f78fb44e 3282 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3283 } else {
3284 /* Privilege exception */
9fceefa7
JM		 3285 /* This is a hack to avoid warnings when running Linux:
3286 * this OS breaks the PowerPC virtualisation model,
3287 * allowing userland application to read the PVR
3288 */
3289 if (sprn != SPR_PVR) {
3290 if (loglevel != 0) {
6b542af7 3291 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3292 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3293 }
077fc206
JM		 3294 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3295 sprn, sprn, ctx->nip);
f24e5695 3296 }
e1833e1f 3297 GEN_EXCP_PRIVREG(ctx);
79aceca5 3298 }
3fc6c082
FB		 3299 } else {
3300 /* Not defined */
4a057712 3301 if (loglevel != 0) {
077fc206
JM		 3302 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3303 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3304 }
077fc206
JM		 3305 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3306 sprn, sprn, ctx->nip);
e1833e1f
JM		 3307 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3308 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3309 }
79aceca5
FB		 3310}
3311
3fc6c082 3312GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3313{
3fc6c082 3314 gen_op_mfspr(ctx);
76a66253 3315}
3fc6c082
FB		 3316
3317/* mftb */
a750fc0b 3318GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3319{
3320 gen_op_mfspr(ctx);
79aceca5
FB		 3321}
3322
3323/* mtcrf */
8dd4983c 3324GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3325{
76a66253 3326 uint32_t crm, crn;
3b46e624 3327
f78fb44e 3328 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 3329 crm = CRM(ctx->opcode);
3330 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3331 crn = ffs(crm);
3332 gen_op_srli_T0(crn * 4);
47e4661c 3333 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_T[0], 0xf);
76a66253 3334 } else {
6676f424 3335 gen_op_store_cr(crm);
76a66253 3336 }
79aceca5
FB		 3337}
3338
3339/* mtmsr */
426613db 3340#if defined(TARGET_PPC64)
be147d08 3341GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3342{
3343#if defined(CONFIG_USER_ONLY)
e1833e1f 3344 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3345#else
3346 if (unlikely(!ctx->supervisor)) {
e1833e1f 3347 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3348 return;
3349 }
f78fb44e 3350 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3351 if (ctx->opcode & 0x00010000) {
3352 /* Special form that does not need any synchronisation */
3353 gen_op_update_riee();
3354 } else {
056b05f8
JM		 3355 /* XXX: we need to update nip before the store
3356 * if we enter power saving mode, we will exit the loop
3357 * directly from ppc_store_msr
3358 */
be147d08 3359 gen_update_nip(ctx, ctx->nip);
6676f424 3360 gen_op_store_msr();
be147d08
JM		 3361 /* Must stop the translation as machine state (may have) changed */
3362 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3363 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3364 }
426613db
JM		 3365#endif
3366}
3367#endif
3368
79aceca5
FB		 3369GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3370{
9a64fbe4 3371#if defined(CONFIG_USER_ONLY)
e1833e1f 3372 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3373#else
76a66253 3374 if (unlikely(!ctx->supervisor)) {
e1833e1f 3375 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3376 return;
9a64fbe4 3377 }
f78fb44e 3378 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3379 if (ctx->opcode & 0x00010000) {
3380 /* Special form that does not need any synchronisation */
3381 gen_op_update_riee();
3382 } else {
056b05f8
JM		 3383 /* XXX: we need to update nip before the store
3384 * if we enter power saving mode, we will exit the loop
3385 * directly from ppc_store_msr
3386 */
be147d08 3387 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3388#if defined(TARGET_PPC64)
be147d08 3389 if (!ctx->sf_mode)
6676f424 3390 gen_op_store_msr_32();
be147d08 3391 else
d9bce9d9 3392#endif
6676f424 3393 gen_op_store_msr();
be147d08
JM		 3394 /* Must stop the translation as machine state (may have) changed */
3395 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3396 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3397 }
9a64fbe4 3398#endif
79aceca5
FB		 3399}
3400
3401/* mtspr */
3402GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3403{
3fc6c082 3404 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3405 uint32_t sprn = SPR(ctx->opcode);
3406
3fc6c082 3407#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3408 if (ctx->supervisor == 2)
3409 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3410 else if (ctx->supervisor)
3fc6c082
FB		 3411 write_cb = ctx->spr_cb[sprn].oea_write;
3412 else
9a64fbe4 3413#endif
3fc6c082 3414 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3415 if (likely(write_cb != NULL)) {
3416 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 3417 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 3418 (*write_cb)(ctx, sprn);
3419 } else {
3420 /* Privilege exception */
4a057712 3421 if (loglevel != 0) {
077fc206
JM		 3422 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3423 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3424 }
077fc206
JM		 3425 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3426 sprn, sprn, ctx->nip);
e1833e1f 3427 GEN_EXCP_PRIVREG(ctx);
76a66253 3428 }
3fc6c082
FB		 3429 } else {
3430 /* Not defined */
4a057712 3431 if (loglevel != 0) {
077fc206
JM		 3432 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3433 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3434 }
077fc206
JM		 3435 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3436 sprn, sprn, ctx->nip);
e1833e1f
JM		 3437 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3438 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3439 }
79aceca5
FB		 3440}
3441
3442/*** Cache management ***/
79aceca5 3443/* dcbf */
0db1b20e 3444GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3445{
dac454af 3446 /* XXX: specification says this is treated as a load by the MMU */
e2be8d8d 3447 gen_addr_reg_index(cpu_T[0], ctx);
a541f297 3448 op_ldst(lbz);
79aceca5
FB		 3449}
3450
3451/* dcbi (Supervisor only) */
9a64fbe4 3452GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3453{
a541f297 3454#if defined(CONFIG_USER_ONLY)
e1833e1f 3455 GEN_EXCP_PRIVOPC(ctx);
a541f297 3456#else
76a66253 3457 if (unlikely(!ctx->supervisor)) {
e1833e1f 3458 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3459 return;
9a64fbe4 3460 }
e2be8d8d 3461 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 3462 /* XXX: specification says this should be treated as a store by the MMU */
dac454af 3463 op_ldst(lbz);
a541f297
FB		 3464 op_ldst(stb);
3465#endif
79aceca5
FB		 3466}
3467
3468/* dcdst */
9a64fbe4 3469GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3470{
76a66253 3471 /* XXX: specification say this is treated as a load by the MMU */
e2be8d8d 3472 gen_addr_reg_index(cpu_T[0], ctx);
a541f297 3473 op_ldst(lbz);
79aceca5
FB		 3474}
3475
3476/* dcbt */
0db1b20e 3477GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3478{
0db1b20e 3479 /* interpreted as no-op */
76a66253
JM		 3480 /* XXX: specification say this is treated as a load by the MMU
3481 * but does not generate any exception
3482 */
79aceca5
FB		 3483}
3484
3485/* dcbtst */
0db1b20e 3486GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3487{
0db1b20e 3488 /* interpreted as no-op */
76a66253
JM		 3489 /* XXX: specification say this is treated as a load by the MMU
3490 * but does not generate any exception
3491 */
79aceca5
FB		 3492}
3493
3494/* dcbz */
d63001d1 3495#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 3496static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3497 /* 32 bytes cache line size */
d63001d1 3498 {
7863667f
JM		 3499#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3500#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3501#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3502#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3503#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3504#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3505#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3506#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3507 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 3508 },
7863667f 3509 /* 64 bytes cache line size */
d63001d1 3510 {
7863667f
JM		 3511#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3512#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3513#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3514#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3515#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3516#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3517#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3518#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3519 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 3520 },
7863667f 3521 /* 128 bytes cache line size */
d63001d1 3522 {
7863667f
JM		 3523#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3524#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3525#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3526#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3527#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3528#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3529#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3530#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3531 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 3532 },
7863667f 3533 /* tunable cache line size */
d63001d1 3534 {
7863667f
JM		 3535#define gen_op_dcbz_le_raw gen_op_dcbz_raw
3536#define gen_op_dcbz_le_user gen_op_dcbz_user
3537#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3538#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3539#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3540#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3541#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3542#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3543 GEN_MEM_FUNCS(dcbz),
d63001d1 3544 },
76a66253 3545};
9a64fbe4 3546
b068d6a7
JM		 3547static always_inline void handler_dcbz (DisasContext *ctx,
3548 int dcache_line_size)
d63001d1
JM		 3549{
3550 int n;
3551
3552 switch (dcache_line_size) {
3553 case 32:
3554 n = 0;
3555 break;
3556 case 64:
3557 n = 1;
3558 break;
3559 case 128:
3560 n = 2;
3561 break;
3562 default:
3563 n = 3;
3564 break;
3565 }
3566 op_dcbz(n);
3567}
3568
3569GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 3570{
e2be8d8d 3571 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 3572 handler_dcbz(ctx, ctx->dcache_line_size);
3573 gen_op_check_reservation();
3574}
3575
c7697e1f 3576GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 3577{
e2be8d8d 3578 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 3579 if (ctx->opcode & 0x00200000)
3580 handler_dcbz(ctx, ctx->dcache_line_size);
3581 else
3582 handler_dcbz(ctx, -1);
4b3686fa 3583 gen_op_check_reservation();
79aceca5
FB		 3584}
3585
3586/* icbi */
36f69651 3587#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 3588#define gen_op_icbi_le_raw gen_op_icbi_raw
3589#define gen_op_icbi_le_user gen_op_icbi_user
3590#define gen_op_icbi_le_kernel gen_op_icbi_kernel
3591#define gen_op_icbi_le_hypv gen_op_icbi_hypv
3592#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3593#define gen_op_icbi_le_64_user gen_op_icbi_64_user
3594#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3595#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3596static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3597 GEN_MEM_FUNCS(icbi),
36f69651 3598};
e1833e1f 3599
1b413d55 3600GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 3601{
30032c94
JM		 3602 /* NIP cannot be restored if the memory exception comes from an helper */
3603 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3604 gen_addr_reg_index(cpu_T[0], ctx);
36f69651 3605 op_icbi();
79aceca5
FB		 3606}
3607
3608/* Optional: */
3609/* dcba */
a750fc0b 3610GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 3611{
0db1b20e
JM		 3612 /* interpreted as no-op */
3613 /* XXX: specification say this is treated as a store by the MMU
3614 * but does not generate any exception
3615 */
79aceca5
FB		 3616}
3617
3618/*** Segment register manipulation ***/
3619/* Supervisor only: */
3620/* mfsr */
3621GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3622{
9a64fbe4 3623#if defined(CONFIG_USER_ONLY)
e1833e1f 3624 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3625#else
76a66253 3626 if (unlikely(!ctx->supervisor)) {
e1833e1f 3627 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3628 return;
9a64fbe4 3629 }
86c581dc 3630 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 3631 gen_op_load_sr();
f78fb44e 3632 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3633#endif
79aceca5
FB		 3634}
3635
3636/* mfsrin */
9a64fbe4 3637GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 3638{
9a64fbe4 3639#if defined(CONFIG_USER_ONLY)
e1833e1f 3640 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3641#else
76a66253 3642 if (unlikely(!ctx->supervisor)) {
e1833e1f 3643 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3644 return;
9a64fbe4 3645 }
f78fb44e 3646 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 3647 gen_op_srli_T1(28);
3648 gen_op_load_sr();
f78fb44e 3649 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3650#endif
79aceca5
FB		 3651}
3652
3653/* mtsr */
e63c59cb 3654GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 3655{
9a64fbe4 3656#if defined(CONFIG_USER_ONLY)
e1833e1f 3657 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3658#else
76a66253 3659 if (unlikely(!ctx->supervisor)) {
e1833e1f 3660 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3661 return;
9a64fbe4 3662 }
f78fb44e 3663 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 3664 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 3665 gen_op_store_sr();
9a64fbe4 3666#endif
79aceca5
FB		 3667}
3668
3669/* mtsrin */
9a64fbe4 3670GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 3671{
9a64fbe4 3672#if defined(CONFIG_USER_ONLY)
e1833e1f 3673 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3674#else
76a66253 3675 if (unlikely(!ctx->supervisor)) {
e1833e1f 3676 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3677 return;
9a64fbe4 3678 }
f78fb44e
AJ		 3679 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3680 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 3681 gen_op_srli_T1(28);
3682 gen_op_store_sr();
9a64fbe4 3683#endif
79aceca5
FB		 3684}
3685
12de9a39
JM		 3686#if defined(TARGET_PPC64)
3687/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3688/* mfsr */
c7697e1f 3689GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 3690{
3691#if defined(CONFIG_USER_ONLY)
3692 GEN_EXCP_PRIVREG(ctx);
3693#else
3694 if (unlikely(!ctx->supervisor)) {
3695 GEN_EXCP_PRIVREG(ctx);
3696 return;
3697 }
86c581dc 3698 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 3699 gen_op_load_slb();
f78fb44e 3700 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 3701#endif
3702}
3703
3704/* mfsrin */
c7697e1f
JM		 3705GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3706 PPC_SEGMENT_64B)
12de9a39
JM		 3707{
3708#if defined(CONFIG_USER_ONLY)
3709 GEN_EXCP_PRIVREG(ctx);
3710#else
3711 if (unlikely(!ctx->supervisor)) {
3712 GEN_EXCP_PRIVREG(ctx);
3713 return;
3714 }
f78fb44e 3715 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 3716 gen_op_srli_T1(28);
3717 gen_op_load_slb();
f78fb44e 3718 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 3719#endif
3720}
3721
3722/* mtsr */
c7697e1f 3723GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 3724{
3725#if defined(CONFIG_USER_ONLY)
3726 GEN_EXCP_PRIVREG(ctx);
3727#else
3728 if (unlikely(!ctx->supervisor)) {
3729 GEN_EXCP_PRIVREG(ctx);
3730 return;
3731 }
f78fb44e 3732 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 3733 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 3734 gen_op_store_slb();
3735#endif
3736}
3737
3738/* mtsrin */
c7697e1f
JM		 3739GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3740 PPC_SEGMENT_64B)
12de9a39
JM		 3741{
3742#if defined(CONFIG_USER_ONLY)
3743 GEN_EXCP_PRIVREG(ctx);
3744#else
3745 if (unlikely(!ctx->supervisor)) {
3746 GEN_EXCP_PRIVREG(ctx);
3747 return;
3748 }
f78fb44e
AJ		 3749 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3750 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 3751 gen_op_srli_T1(28);
3752 gen_op_store_slb();
3753#endif
3754}
3755#endif /* defined(TARGET_PPC64) */
3756
79aceca5
FB		 3757/*** Lookaside buffer management ***/
3758/* Optional & supervisor only: */
3759/* tlbia */
3fc6c082 3760GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 3761{
9a64fbe4 3762#if defined(CONFIG_USER_ONLY)
e1833e1f 3763 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3764#else
76a66253 3765 if (unlikely(!ctx->supervisor)) {
e1833e1f 3766 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3767 return;
9a64fbe4
FB		 3768 }
3769 gen_op_tlbia();
3770#endif
79aceca5
FB		 3771}
3772
3773/* tlbie */
76a66253 3774GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 3775{
9a64fbe4 3776#if defined(CONFIG_USER_ONLY)
e1833e1f 3777 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3778#else
76a66253 3779 if (unlikely(!ctx->supervisor)) {
e1833e1f 3780 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3781 return;
9a64fbe4 3782 }
f78fb44e 3783 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3784#if defined(TARGET_PPC64)
3785 if (ctx->sf_mode)
3786 gen_op_tlbie_64();
3787 else
3788#endif
3789 gen_op_tlbie();
9a64fbe4 3790#endif
79aceca5
FB		 3791}
3792
3793/* tlbsync */
76a66253 3794GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 3795{
9a64fbe4 3796#if defined(CONFIG_USER_ONLY)
e1833e1f 3797 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3798#else
76a66253 3799 if (unlikely(!ctx->supervisor)) {
e1833e1f 3800 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3801 return;
9a64fbe4
FB		 3802 }
3803 /* This has no effect: it should ensure that all previous
3804 * tlbie have completed
3805 */
e1833e1f 3806 GEN_STOP(ctx);
9a64fbe4 3807#endif
79aceca5
FB		 3808}
3809
426613db
JM		 3810#if defined(TARGET_PPC64)
3811/* slbia */
3812GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
3813{
3814#if defined(CONFIG_USER_ONLY)
e1833e1f 3815 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3816#else
3817 if (unlikely(!ctx->supervisor)) {
e1833e1f 3818 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3819 return;
3820 }
3821 gen_op_slbia();
426613db
JM		 3822#endif
3823}
3824
3825/* slbie */
3826GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3827{
3828#if defined(CONFIG_USER_ONLY)
e1833e1f 3829 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3830#else
3831 if (unlikely(!ctx->supervisor)) {
e1833e1f 3832 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3833 return;
3834 }
f78fb44e 3835 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 3836 gen_op_slbie();
426613db
JM		 3837#endif
3838}
3839#endif
3840
79aceca5
FB		 3841/*** External control ***/
3842/* Optional: */
9a64fbe4
FB		 3843#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3844#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 3845static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
3846 GEN_MEM_FUNCS(eciwx),
111bfab3 3847};
7863667f
JM		 3848static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
3849 GEN_MEM_FUNCS(ecowx),
111bfab3 3850};
9a64fbe4 3851
111bfab3 3852/* eciwx */
79aceca5
FB		 3853GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
3854{
9a64fbe4 3855 /* Should check EAR[E] & alignment ! */
e2be8d8d 3856 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 3857 op_eciwx();
f78fb44e 3858 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3859}
3860
3861/* ecowx */
3862GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3863{
3864 /* Should check EAR[E] & alignment ! */
e2be8d8d 3865 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3866 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 3867 op_ecowx();
3868}
3869
3870/* PowerPC 601 specific instructions */
3871/* abs - abs. */
3872GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3873{
f78fb44e 3874 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 3875 gen_op_POWER_abs();
f78fb44e 3876 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3877 if (unlikely(Rc(ctx->opcode) != 0))
3878 gen_set_Rc0(ctx);
3879}
3880
3881/* abso - abso. */
3882GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3883{
f78fb44e 3884 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 3885 gen_op_POWER_abso();
f78fb44e 3886 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3887 if (unlikely(Rc(ctx->opcode) != 0))
3888 gen_set_Rc0(ctx);
3889}
3890
3891/* clcs */
a750fc0b 3892GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 3893{
f78fb44e 3894 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 3895 gen_op_POWER_clcs();
c7697e1f 3896 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 3897 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3898}
3899
3900/* div - div. */
3901GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3902{
f78fb44e
AJ		 3903 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3904 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3905 gen_op_POWER_div();
f78fb44e 3906 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3907 if (unlikely(Rc(ctx->opcode) != 0))
3908 gen_set_Rc0(ctx);
3909}
3910
3911/* divo - divo. */
3912GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3913{
f78fb44e
AJ		 3914 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3915 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3916 gen_op_POWER_divo();
f78fb44e 3917 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3918 if (unlikely(Rc(ctx->opcode) != 0))
3919 gen_set_Rc0(ctx);
3920}
3921
3922/* divs - divs. */
3923GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3924{
f78fb44e
AJ		 3925 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3926 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3927 gen_op_POWER_divs();
f78fb44e 3928 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3929 if (unlikely(Rc(ctx->opcode) != 0))
3930 gen_set_Rc0(ctx);
3931}
3932
3933/* divso - divso. */
3934GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3935{
f78fb44e
AJ		 3936 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3937 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3938 gen_op_POWER_divso();
f78fb44e 3939 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3940 if (unlikely(Rc(ctx->opcode) != 0))
3941 gen_set_Rc0(ctx);
3942}
3943
3944/* doz - doz. */
3945GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3946{
f78fb44e
AJ		 3947 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3948 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3949 gen_op_POWER_doz();
f78fb44e 3950 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3951 if (unlikely(Rc(ctx->opcode) != 0))
3952 gen_set_Rc0(ctx);
3953}
3954
3955/* dozo - dozo. */
3956GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3957{
f78fb44e
AJ		 3958 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3959 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 3960 gen_op_POWER_dozo();
f78fb44e 3961 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3962 if (unlikely(Rc(ctx->opcode) != 0))
3963 gen_set_Rc0(ctx);
3964}
3965
3966/* dozi */
3967GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
3968{
f78fb44e 3969 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 3970 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 3971 gen_op_POWER_doz();
f78fb44e 3972 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 3973}
3974
7863667f
JM		 3975/* As lscbx load from memory byte after byte, it's always endian safe.
3976 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3977 */
2857068e 3978#define op_POWER_lscbx(start, ra, rb) \
76a66253 3979(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 3980#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
3981#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
3982#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
3983#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
3984#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
3985#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
3986#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
3987#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
3988#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
3989#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
3990#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
3991#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
3992static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
3993 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 3994};
76a66253
JM		 3995
3996/* lscbx - lscbx. */
3997GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
3998{
3999 int ra = rA(ctx->opcode);
4000 int rb = rB(ctx->opcode);
4001
e2be8d8d 4002 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4003 if (ra == 0) {
4004 ra = rb;
4005 }
4006 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4007 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4008 gen_op_load_xer_bc();
4009 gen_op_load_xer_cmp();
4010 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4011 gen_op_store_xer_bc();
4012 if (unlikely(Rc(ctx->opcode) != 0))
4013 gen_set_Rc0(ctx);
4014}
4015
4016/* maskg - maskg. */
4017GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4018{
f78fb44e
AJ		 4019 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4020 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4021 gen_op_POWER_maskg();
f78fb44e 4022 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4023 if (unlikely(Rc(ctx->opcode) != 0))
4024 gen_set_Rc0(ctx);
4025}
4026
4027/* maskir - maskir. */
4028GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4029{
f78fb44e
AJ		 4030 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4031 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4032 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4033 gen_op_POWER_maskir();
f78fb44e 4034 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4035 if (unlikely(Rc(ctx->opcode) != 0))
4036 gen_set_Rc0(ctx);
4037}
4038
4039/* mul - mul. */
4040GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4041{
f78fb44e
AJ		 4042 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4043 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4044 gen_op_POWER_mul();
f78fb44e 4045 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4046 if (unlikely(Rc(ctx->opcode) != 0))
4047 gen_set_Rc0(ctx);
4048}
4049
4050/* mulo - mulo. */
4051GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4052{
f78fb44e
AJ		 4053 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4054 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4055 gen_op_POWER_mulo();
f78fb44e 4056 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4057 if (unlikely(Rc(ctx->opcode) != 0))
4058 gen_set_Rc0(ctx);
4059}
4060
4061/* nabs - nabs. */
4062GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4063{
f78fb44e 4064 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4065 gen_op_POWER_nabs();
f78fb44e 4066 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4067 if (unlikely(Rc(ctx->opcode) != 0))
4068 gen_set_Rc0(ctx);
4069}
4070
4071/* nabso - nabso. */
4072GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4073{
f78fb44e 4074 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4075 gen_op_POWER_nabso();
f78fb44e 4076 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4077 if (unlikely(Rc(ctx->opcode) != 0))
4078 gen_set_Rc0(ctx);
4079}
4080
4081/* rlmi - rlmi. */
4082GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4083{
4084 uint32_t mb, me;
4085
4086 mb = MB(ctx->opcode);
4087 me = ME(ctx->opcode);
f78fb44e
AJ		 4088 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4089 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4090 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4091 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4092 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4093 if (unlikely(Rc(ctx->opcode) != 0))
4094 gen_set_Rc0(ctx);
4095}
4096
4097/* rrib - rrib. */
4098GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4099{
f78fb44e
AJ		 4100 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4101 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4102 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4103 gen_op_POWER_rrib();
f78fb44e 4104 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4105 if (unlikely(Rc(ctx->opcode) != 0))
4106 gen_set_Rc0(ctx);
4107}
4108
4109/* sle - sle. */
4110GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4111{
f78fb44e
AJ		 4112 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4113 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4114 gen_op_POWER_sle();
f78fb44e 4115 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4116 if (unlikely(Rc(ctx->opcode) != 0))
4117 gen_set_Rc0(ctx);
4118}
4119
4120/* sleq - sleq. */
4121GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4122{
f78fb44e
AJ		 4123 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4124 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4125 gen_op_POWER_sleq();
f78fb44e 4126 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4127 if (unlikely(Rc(ctx->opcode) != 0))
4128 gen_set_Rc0(ctx);
4129}
4130
4131/* sliq - sliq. */
4132GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4133{
f78fb44e 4134 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4135 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4136 gen_op_POWER_sle();
f78fb44e 4137 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4138 if (unlikely(Rc(ctx->opcode) != 0))
4139 gen_set_Rc0(ctx);
4140}
4141
4142/* slliq - slliq. */
4143GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4144{
f78fb44e 4145 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4146 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4147 gen_op_POWER_sleq();
f78fb44e 4148 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4149 if (unlikely(Rc(ctx->opcode) != 0))
4150 gen_set_Rc0(ctx);
4151}
4152
4153/* sllq - sllq. */
4154GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4155{
f78fb44e
AJ		 4156 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4157 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4158 gen_op_POWER_sllq();
f78fb44e 4159 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4160 if (unlikely(Rc(ctx->opcode) != 0))
4161 gen_set_Rc0(ctx);
4162}
4163
4164/* slq - slq. */
4165GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4166{
f78fb44e
AJ		 4167 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4168 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4169 gen_op_POWER_slq();
f78fb44e 4170 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4171 if (unlikely(Rc(ctx->opcode) != 0))
4172 gen_set_Rc0(ctx);
4173}
4174
d9bce9d9 4175/* sraiq - sraiq. */
76a66253
JM		 4176GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4177{
f78fb44e 4178 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4179 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4180 gen_op_POWER_sraq();
f78fb44e 4181 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4182 if (unlikely(Rc(ctx->opcode) != 0))
4183 gen_set_Rc0(ctx);
4184}
4185
4186/* sraq - sraq. */
4187GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4188{
f78fb44e
AJ		 4189 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4190 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4191 gen_op_POWER_sraq();
f78fb44e 4192 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4193 if (unlikely(Rc(ctx->opcode) != 0))
4194 gen_set_Rc0(ctx);
4195}
4196
4197/* sre - sre. */
4198GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4199{
f78fb44e
AJ		 4200 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4201 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4202 gen_op_POWER_sre();
f78fb44e 4203 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4204 if (unlikely(Rc(ctx->opcode) != 0))
4205 gen_set_Rc0(ctx);
4206}
4207
4208/* srea - srea. */
4209GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4210{
f78fb44e
AJ		 4211 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4212 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4213 gen_op_POWER_srea();
f78fb44e 4214 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4215 if (unlikely(Rc(ctx->opcode) != 0))
4216 gen_set_Rc0(ctx);
4217}
4218
4219/* sreq */
4220GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4221{
f78fb44e
AJ		 4222 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4223 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4224 gen_op_POWER_sreq();
f78fb44e 4225 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4226 if (unlikely(Rc(ctx->opcode) != 0))
4227 gen_set_Rc0(ctx);
4228}
4229
4230/* sriq */
4231GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4232{
f78fb44e 4233 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4234 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4235 gen_op_POWER_srq();
f78fb44e 4236 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4237 if (unlikely(Rc(ctx->opcode) != 0))
4238 gen_set_Rc0(ctx);
4239}
4240
4241/* srliq */
4242GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4243{
f78fb44e
AJ		 4244 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4245 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4246 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4247 gen_op_POWER_srlq();
f78fb44e 4248 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4249 if (unlikely(Rc(ctx->opcode) != 0))
4250 gen_set_Rc0(ctx);
4251}
4252
4253/* srlq */
4254GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4255{
f78fb44e
AJ		 4256 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4257 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4258 gen_op_POWER_srlq();
f78fb44e 4259 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4260 if (unlikely(Rc(ctx->opcode) != 0))
4261 gen_set_Rc0(ctx);
4262}
4263
4264/* srq */
4265GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4266{
f78fb44e
AJ		 4267 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4268 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4269 gen_op_POWER_srq();
f78fb44e 4270 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4271 if (unlikely(Rc(ctx->opcode) != 0))
4272 gen_set_Rc0(ctx);
4273}
4274
4275/* PowerPC 602 specific instructions */
4276/* dsa */
4277GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4278{
4279 /* XXX: TODO */
e1833e1f 4280 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4281}
4282
4283/* esa */
4284GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4285{
4286 /* XXX: TODO */
e1833e1f 4287 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4288}
4289
4290/* mfrom */
4291GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4292{
4293#if defined(CONFIG_USER_ONLY)
e1833e1f 4294 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4295#else
4296 if (unlikely(!ctx->supervisor)) {
e1833e1f 4297 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4298 return;
4299 }
f78fb44e 4300 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4301 gen_op_602_mfrom();
f78fb44e 4302 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4303#endif
4304}
4305
4306/* 602 - 603 - G2 TLB management */
4307/* tlbld */
c7697e1f 4308GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4309{
4310#if defined(CONFIG_USER_ONLY)
e1833e1f 4311 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4312#else
4313 if (unlikely(!ctx->supervisor)) {
e1833e1f 4314 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4315 return;
4316 }
f78fb44e 4317 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4318 gen_op_6xx_tlbld();
76a66253
JM		 4319#endif
4320}
4321
4322/* tlbli */
c7697e1f 4323GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4324{
4325#if defined(CONFIG_USER_ONLY)
e1833e1f 4326 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4327#else
4328 if (unlikely(!ctx->supervisor)) {
e1833e1f 4329 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4330 return;
4331 }
f78fb44e 4332 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4333 gen_op_6xx_tlbli();
76a66253
JM		 4334#endif
4335}
4336
7dbe11ac
JM		 4337/* 74xx TLB management */
4338/* tlbld */
c7697e1f 4339GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4340{
4341#if defined(CONFIG_USER_ONLY)
4342 GEN_EXCP_PRIVOPC(ctx);
4343#else
4344 if (unlikely(!ctx->supervisor)) {
4345 GEN_EXCP_PRIVOPC(ctx);
4346 return;
4347 }
f78fb44e 4348 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4349 gen_op_74xx_tlbld();
4350#endif
4351}
4352
4353/* tlbli */
c7697e1f 4354GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4355{
4356#if defined(CONFIG_USER_ONLY)
4357 GEN_EXCP_PRIVOPC(ctx);
4358#else
4359 if (unlikely(!ctx->supervisor)) {
4360 GEN_EXCP_PRIVOPC(ctx);
4361 return;
4362 }
f78fb44e 4363 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4364 gen_op_74xx_tlbli();
4365#endif
4366}
4367
76a66253
JM		 4368/* POWER instructions not in PowerPC 601 */
4369/* clf */
4370GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4371{
4372 /* Cache line flush: implemented as no-op */
4373}
4374
4375/* cli */
4376GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4377{
7f75ffd3 4378 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4379#if defined(CONFIG_USER_ONLY)
e1833e1f 4380 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4381#else
4382 if (unlikely(!ctx->supervisor)) {
e1833e1f 4383 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4384 return;
4385 }
4386#endif
4387}
4388
4389/* dclst */
4390GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4391{
4392 /* Data cache line store: treated as no-op */
4393}
4394
4395GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4396{
4397#if defined(CONFIG_USER_ONLY)
e1833e1f 4398 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4399#else
4400 if (unlikely(!ctx->supervisor)) {
e1833e1f 4401 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4402 return;
4403 }
4404 int ra = rA(ctx->opcode);
4405 int rd = rD(ctx->opcode);
4406
e2be8d8d 4407 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4408 gen_op_POWER_mfsri();
f78fb44e 4409 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4410 if (ra != 0 && ra != rd)
f78fb44e 4411 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4412#endif
4413}
4414
4415GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4416{
4417#if defined(CONFIG_USER_ONLY)
e1833e1f 4418 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4419#else
4420 if (unlikely(!ctx->supervisor)) {
e1833e1f 4421 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4422 return;
4423 }
e2be8d8d 4424 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4425 gen_op_POWER_rac();
f78fb44e 4426 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4427#endif
4428}
4429
4430GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4431{
4432#if defined(CONFIG_USER_ONLY)
e1833e1f 4433 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4434#else
4435 if (unlikely(!ctx->supervisor)) {
e1833e1f 4436 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4437 return;
4438 }
4439 gen_op_POWER_rfsvc();
e1833e1f 4440 GEN_SYNC(ctx);
76a66253
JM		 4441#endif
4442}
4443
4444/* svc is not implemented for now */
4445
4446/* POWER2 specific instructions */
4447/* Quad manipulation (load/store two floats at a time) */
7863667f 4448/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 4449#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4450#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 4451#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4452#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4453#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4454#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4455#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4456#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4457#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4458#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4459#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4460#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4461#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4462#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4463#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4464#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4465#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4466#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4467static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4468 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 4469};
7863667f
JM		 4470static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4471 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 4472};
76a66253
JM		 4473
4474/* lfq */
4475GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4476{
4477 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4478 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4479 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4480 op_POWER2_lfq();
a5e26afa
AJ		 4481 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4482 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4483}
4484
4485/* lfqu */
4486GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4487{
4488 int ra = rA(ctx->opcode);
4489
4490 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4491 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4492 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4493 op_POWER2_lfq();
a5e26afa
AJ		 4494 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4495 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4496 if (ra != 0)
f78fb44e 4497 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4498}
4499
4500/* lfqux */
4501GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4502{
4503 int ra = rA(ctx->opcode);
4504
4505 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4506 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4507 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4508 op_POWER2_lfq();
a5e26afa
AJ		 4509 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4510 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4511 if (ra != 0)
f78fb44e 4512 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4513}
4514
4515/* lfqx */
4516GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4517{
4518 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4519 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4520 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4521 op_POWER2_lfq();
a5e26afa
AJ		 4522 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4523 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4524}
4525
4526/* stfq */
4527GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4528{
4529 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4530 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4531 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4532 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4533 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4534 op_POWER2_stfq();
4535}
4536
4537/* stfqu */
4538GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4539{
4540 int ra = rA(ctx->opcode);
4541
4542 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4543 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4544 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4545 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4546 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4547 op_POWER2_stfq();
4548 if (ra != 0)
f78fb44e 4549 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4550}
4551
4552/* stfqux */
4553GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4554{
4555 int ra = rA(ctx->opcode);
4556
4557 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4558 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4559 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 4560 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4561 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4562 op_POWER2_stfq();
4563 if (ra != 0)
f78fb44e 4564 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4565}
4566
4567/* stfqx */
4568GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4569{
4570 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4571 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4572 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 4573 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4574 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4575 op_POWER2_stfq();
4576}
4577
4578/* BookE specific instructions */
2662a059 4579/* XXX: not implemented on 440 ? */
05332d70 4580GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 4581{
4582 /* XXX: TODO */
e1833e1f 4583 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4584}
4585
2662a059 4586/* XXX: not implemented on 440 ? */
05332d70 4587GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 4588{
4589#if defined(CONFIG_USER_ONLY)
e1833e1f 4590 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4591#else
4592 if (unlikely(!ctx->supervisor)) {
e1833e1f 4593 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4594 return;
4595 }
e2be8d8d 4596 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4597 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 4598#if defined(TARGET_PPC64)
4599 if (ctx->sf_mode)
4600 gen_op_tlbie_64();
4601 else
4602#endif
4603 gen_op_tlbie();
76a66253
JM		 4604#endif
4605}
4606
4607/* All 405 MAC instructions are translated here */
b068d6a7
JM		 4608static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4609 int opc2, int opc3,
4610 int ra, int rb, int rt, int Rc)
76a66253 4611{
f78fb44e
AJ		 4612 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
4613 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 4614 switch (opc3 & 0x0D) {
4615 case 0x05:
4616 /* macchw - macchw. - macchwo - macchwo. */
4617 /* macchws - macchws. - macchwso - macchwso. */
4618 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4619 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4620 /* mulchw - mulchw. */
4621 gen_op_405_mulchw();
4622 break;
4623 case 0x04:
4624 /* macchwu - macchwu. - macchwuo - macchwuo. */
4625 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4626 /* mulchwu - mulchwu. */
4627 gen_op_405_mulchwu();
4628 break;
4629 case 0x01:
4630 /* machhw - machhw. - machhwo - machhwo. */
4631 /* machhws - machhws. - machhwso - machhwso. */
4632 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4633 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4634 /* mulhhw - mulhhw. */
4635 gen_op_405_mulhhw();
4636 break;
4637 case 0x00:
4638 /* machhwu - machhwu. - machhwuo - machhwuo. */
4639 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4640 /* mulhhwu - mulhhwu. */
4641 gen_op_405_mulhhwu();
4642 break;
4643 case 0x0D:
4644 /* maclhw - maclhw. - maclhwo - maclhwo. */
4645 /* maclhws - maclhws. - maclhwso - maclhwso. */
4646 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4647 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4648 /* mullhw - mullhw. */
4649 gen_op_405_mullhw();
4650 break;
4651 case 0x0C:
4652 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4653 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4654 /* mullhwu - mullhwu. */
4655 gen_op_405_mullhwu();
4656 break;
4657 }
4658 if (opc2 & 0x02) {
4659 /* nmultiply-and-accumulate (0x0E) */
4660 gen_op_neg();
4661 }
4662 if (opc2 & 0x04) {
4663 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
f78fb44e 4664 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
e55fd934 4665 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
76a66253
JM		 4666 gen_op_405_add_T0_T2();
4667 }
4668 if (opc3 & 0x10) {
4669 /* Check overflow */
4670 if (opc3 & 0x01)
c3e10c7b 4671 gen_op_check_addo();
76a66253
JM		 4672 else
4673 gen_op_405_check_ovu();
4674 }
4675 if (opc3 & 0x02) {
4676 /* Saturate */
4677 if (opc3 & 0x01)
4678 gen_op_405_check_sat();
4679 else
4680 gen_op_405_check_satu();
4681 }
f78fb44e 4682 tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
76a66253
JM		 4683 if (unlikely(Rc) != 0) {
4684 /* Update Rc0 */
4685 gen_set_Rc0(ctx);
4686 }
4687}
4688
a750fc0b
JM		 4689#define GEN_MAC_HANDLER(name, opc2, opc3) \
4690GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 4691{ \
4692 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4693 rD(ctx->opcode), Rc(ctx->opcode)); \
4694}
4695
4696/* macchw - macchw. */
a750fc0b 4697GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 4698/* macchwo - macchwo. */
a750fc0b 4699GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 4700/* macchws - macchws. */
a750fc0b 4701GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 4702/* macchwso - macchwso. */
a750fc0b 4703GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 4704/* macchwsu - macchwsu. */
a750fc0b 4705GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 4706/* macchwsuo - macchwsuo. */
a750fc0b 4707GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 4708/* macchwu - macchwu. */
a750fc0b 4709GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 4710/* macchwuo - macchwuo. */
a750fc0b 4711GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 4712/* machhw - machhw. */
a750fc0b 4713GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 4714/* machhwo - machhwo. */
a750fc0b 4715GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 4716/* machhws - machhws. */
a750fc0b 4717GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 4718/* machhwso - machhwso. */
a750fc0b 4719GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 4720/* machhwsu - machhwsu. */
a750fc0b 4721GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 4722/* machhwsuo - machhwsuo. */
a750fc0b 4723GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 4724/* machhwu - machhwu. */
a750fc0b 4725GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 4726/* machhwuo - machhwuo. */
a750fc0b 4727GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 4728/* maclhw - maclhw. */
a750fc0b 4729GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 4730/* maclhwo - maclhwo. */
a750fc0b 4731GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 4732/* maclhws - maclhws. */
a750fc0b 4733GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 4734/* maclhwso - maclhwso. */
a750fc0b 4735GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 4736/* maclhwu - maclhwu. */
a750fc0b 4737GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 4738/* maclhwuo - maclhwuo. */
a750fc0b 4739GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 4740/* maclhwsu - maclhwsu. */
a750fc0b 4741GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 4742/* maclhwsuo - maclhwsuo. */
a750fc0b 4743GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 4744/* nmacchw - nmacchw. */
a750fc0b 4745GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 4746/* nmacchwo - nmacchwo. */
a750fc0b 4747GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 4748/* nmacchws - nmacchws. */
a750fc0b 4749GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 4750/* nmacchwso - nmacchwso. */
a750fc0b 4751GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 4752/* nmachhw - nmachhw. */
a750fc0b 4753GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 4754/* nmachhwo - nmachhwo. */
a750fc0b 4755GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 4756/* nmachhws - nmachhws. */
a750fc0b 4757GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 4758/* nmachhwso - nmachhwso. */
a750fc0b 4759GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 4760/* nmaclhw - nmaclhw. */
a750fc0b 4761GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 4762/* nmaclhwo - nmaclhwo. */
a750fc0b 4763GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 4764/* nmaclhws - nmaclhws. */
a750fc0b 4765GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 4766/* nmaclhwso - nmaclhwso. */
a750fc0b 4767GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 4768
4769/* mulchw - mulchw. */
a750fc0b 4770GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 4771/* mulchwu - mulchwu. */
a750fc0b 4772GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 4773/* mulhhw - mulhhw. */
a750fc0b 4774GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 4775/* mulhhwu - mulhhwu. */
a750fc0b 4776GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 4777/* mullhw - mullhw. */
a750fc0b 4778GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 4779/* mullhwu - mullhwu. */
a750fc0b 4780GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 4781
4782/* mfdcr */
05332d70 4783GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 4784{
4785#if defined(CONFIG_USER_ONLY)
e1833e1f 4786 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4787#else
4788 uint32_t dcrn = SPR(ctx->opcode);
4789
4790 if (unlikely(!ctx->supervisor)) {
e1833e1f 4791 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4792 return;
4793 }
86c581dc 4794 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 4795 gen_op_load_dcr();
f78fb44e 4796 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4797#endif
4798}
4799
4800/* mtdcr */
05332d70 4801GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 4802{
4803#if defined(CONFIG_USER_ONLY)
e1833e1f 4804 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4805#else
4806 uint32_t dcrn = SPR(ctx->opcode);
4807
4808 if (unlikely(!ctx->supervisor)) {
e1833e1f 4809 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4810 return;
4811 }
86c581dc 4812 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 4813 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 4814 gen_op_store_dcr();
4815#endif
4816}
4817
4818/* mfdcrx */
2662a059 4819/* XXX: not implemented on 440 ? */
05332d70 4820GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 4821{
4822#if defined(CONFIG_USER_ONLY)
e1833e1f 4823 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4824#else
4825 if (unlikely(!ctx->supervisor)) {
e1833e1f 4826 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4827 return;
4828 }
f78fb44e 4829 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 4830 gen_op_load_dcr();
f78fb44e 4831 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 4832 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 4833#endif
4834}
4835
4836/* mtdcrx */
2662a059 4837/* XXX: not implemented on 440 ? */
05332d70 4838GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 4839{
4840#if defined(CONFIG_USER_ONLY)
e1833e1f 4841 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4842#else
4843 if (unlikely(!ctx->supervisor)) {
e1833e1f 4844 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4845 return;
4846 }
f78fb44e
AJ		 4847 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4848 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 4849 gen_op_store_dcr();
a750fc0b 4850 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 4851#endif
4852}
4853
a750fc0b
JM		 4854/* mfdcrux (PPC 460) : user-mode access to DCR */
4855GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
4856{
f78fb44e 4857 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 4858 gen_op_load_dcr();
f78fb44e 4859 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 4860 /* Note: Rc update flag set leads to undefined state of Rc0 */
4861}
4862
4863/* mtdcrux (PPC 460) : user-mode access to DCR */
4864GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
4865{
f78fb44e
AJ		 4866 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4867 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 4868 gen_op_store_dcr();
4869 /* Note: Rc update flag set leads to undefined state of Rc0 */
4870}
4871
76a66253
JM		 4872/* dccci */
4873GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4874{
4875#if defined(CONFIG_USER_ONLY)
e1833e1f 4876 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4877#else
4878 if (unlikely(!ctx->supervisor)) {
e1833e1f 4879 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4880 return;
4881 }
4882 /* interpreted as no-op */
4883#endif
4884}
4885
4886/* dcread */
4887GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4888{
4889#if defined(CONFIG_USER_ONLY)
e1833e1f 4890 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4891#else
4892 if (unlikely(!ctx->supervisor)) {
e1833e1f 4893 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4894 return;
4895 }
e2be8d8d 4896 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4897 op_ldst(lwz);
f78fb44e 4898 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4899#endif
4900}
4901
4902/* icbt */
c7697e1f 4903GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 4904{
4905 /* interpreted as no-op */
4906 /* XXX: specification say this is treated as a load by the MMU
4907 * but does not generate any exception
4908 */
4909}
4910
4911/* iccci */
4912GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
4913{
4914#if defined(CONFIG_USER_ONLY)
e1833e1f 4915 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4916#else
4917 if (unlikely(!ctx->supervisor)) {
e1833e1f 4918 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4919 return;
4920 }
4921 /* interpreted as no-op */
4922#endif
4923}
4924
4925/* icread */
4926GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
4927{
4928#if defined(CONFIG_USER_ONLY)
e1833e1f 4929 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4930#else
4931 if (unlikely(!ctx->supervisor)) {
e1833e1f 4932 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4933 return;
4934 }
4935 /* interpreted as no-op */
4936#endif
4937}
4938
4939/* rfci (supervisor only) */
c7697e1f 4940GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 4941{
4942#if defined(CONFIG_USER_ONLY)
e1833e1f 4943 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4944#else
4945 if (unlikely(!ctx->supervisor)) {
e1833e1f 4946 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4947 return;
4948 }
4949 /* Restore CPU state */
4950 gen_op_40x_rfci();
e1833e1f 4951 GEN_SYNC(ctx);
a42bd6cc
JM		 4952#endif
4953}
4954
4955GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4956{
4957#if defined(CONFIG_USER_ONLY)
e1833e1f 4958 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4959#else
4960 if (unlikely(!ctx->supervisor)) {
e1833e1f 4961 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4962 return;
4963 }
4964 /* Restore CPU state */
4965 gen_op_rfci();
e1833e1f 4966 GEN_SYNC(ctx);
a42bd6cc
JM		 4967#endif
4968}
4969
4970/* BookE specific */
2662a059 4971/* XXX: not implemented on 440 ? */
05332d70 4972GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 4973{
4974#if defined(CONFIG_USER_ONLY)
e1833e1f 4975 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4976#else
4977 if (unlikely(!ctx->supervisor)) {
e1833e1f 4978 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4979 return;
4980 }
4981 /* Restore CPU state */
a42bd6cc 4982 gen_op_rfdi();
e1833e1f 4983 GEN_SYNC(ctx);
76a66253
JM		 4984#endif
4985}
4986
2662a059 4987/* XXX: not implemented on 440 ? */
a750fc0b 4988GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 4989{
4990#if defined(CONFIG_USER_ONLY)
e1833e1f 4991 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4992#else
4993 if (unlikely(!ctx->supervisor)) {
e1833e1f 4994 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4995 return;
4996 }
4997 /* Restore CPU state */
4998 gen_op_rfmci();
e1833e1f 4999 GEN_SYNC(ctx);
a42bd6cc
JM		 5000#endif
5001}
5eb7995e 5002
d9bce9d9 5003/* TLB management - PowerPC 405 implementation */
76a66253 5004/* tlbre */
c7697e1f 5005GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5006{
5007#if defined(CONFIG_USER_ONLY)
e1833e1f 5008 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5009#else
5010 if (unlikely(!ctx->supervisor)) {
e1833e1f 5011 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5012 return;
5013 }
5014 switch (rB(ctx->opcode)) {
5015 case 0:
f78fb44e 5016 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5017 gen_op_4xx_tlbre_hi();
f78fb44e 5018 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5019 break;
5020 case 1:
f78fb44e 5021 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5022 gen_op_4xx_tlbre_lo();
f78fb44e 5023 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5024 break;
5025 default:
e1833e1f 5026 GEN_EXCP_INVAL(ctx);
76a66253 5027 break;
9a64fbe4 5028 }
76a66253
JM		 5029#endif
5030}
5031
d9bce9d9 5032/* tlbsx - tlbsx. */
c7697e1f 5033GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5034{
5035#if defined(CONFIG_USER_ONLY)
e1833e1f 5036 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5037#else
5038 if (unlikely(!ctx->supervisor)) {
e1833e1f 5039 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5040 return;
5041 }
e2be8d8d 5042 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5043 gen_op_4xx_tlbsx();
76a66253 5044 if (Rc(ctx->opcode))
daf4f96e 5045 gen_op_4xx_tlbsx_check();
f78fb44e 5046 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5047#endif
79aceca5
FB		 5048}
5049
76a66253 5050/* tlbwe */
c7697e1f 5051GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5052{
76a66253 5053#if defined(CONFIG_USER_ONLY)
e1833e1f 5054 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5055#else
5056 if (unlikely(!ctx->supervisor)) {
e1833e1f 5057 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5058 return;
5059 }
5060 switch (rB(ctx->opcode)) {
5061 case 0:
f78fb44e
AJ		 5062 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5063 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5064 gen_op_4xx_tlbwe_hi();
5065 break;
5066 case 1:
f78fb44e
AJ		 5067 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5068 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5069 gen_op_4xx_tlbwe_lo();
5070 break;
5071 default:
e1833e1f 5072 GEN_EXCP_INVAL(ctx);
76a66253 5073 break;
9a64fbe4 5074 }
76a66253
JM		 5075#endif
5076}
5077
a4bb6c3e 5078/* TLB management - PowerPC 440 implementation */
5eb7995e 5079/* tlbre */
c7697e1f 5080GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5081{
5082#if defined(CONFIG_USER_ONLY)
e1833e1f 5083 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5084#else
5085 if (unlikely(!ctx->supervisor)) {
e1833e1f 5086 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5087 return;
5088 }
5089 switch (rB(ctx->opcode)) {
5090 case 0:
5eb7995e 5091 case 1:
5eb7995e 5092 case 2:
f78fb44e 5093 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5094 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5095 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5096 break;
5097 default:
e1833e1f 5098 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5099 break;
5100 }
5101#endif
5102}
5103
5104/* tlbsx - tlbsx. */
c7697e1f 5105GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5106{
5107#if defined(CONFIG_USER_ONLY)
e1833e1f 5108 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5109#else
5110 if (unlikely(!ctx->supervisor)) {
e1833e1f 5111 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5112 return;
5113 }
e2be8d8d 5114 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5115 gen_op_440_tlbsx();
5eb7995e 5116 if (Rc(ctx->opcode))
daf4f96e 5117 gen_op_4xx_tlbsx_check();
f78fb44e 5118 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5119#endif
5120}
5121
5122/* tlbwe */
c7697e1f 5123GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5124{
5125#if defined(CONFIG_USER_ONLY)
e1833e1f 5126 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5127#else
5128 if (unlikely(!ctx->supervisor)) {
e1833e1f 5129 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5130 return;
5131 }
5132 switch (rB(ctx->opcode)) {
5133 case 0:
5eb7995e 5134 case 1:
5eb7995e 5135 case 2:
f78fb44e
AJ		 5136 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5137 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5138 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5139 break;
5140 default:
e1833e1f 5141 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5142 break;
5143 }
5144#endif
5145}
5146
76a66253 5147/* wrtee */
05332d70 5148GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5149{
5150#if defined(CONFIG_USER_ONLY)
e1833e1f 5151 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5152#else
5153 if (unlikely(!ctx->supervisor)) {
e1833e1f 5154 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5155 return;
5156 }
f78fb44e 5157 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5158 gen_op_wrte();
dee96f6c
JM		 5159 /* Stop translation to have a chance to raise an exception
5160 * if we just set msr_ee to 1
5161 */
e1833e1f 5162 GEN_STOP(ctx);
76a66253
JM		 5163#endif
5164}
5165
5166/* wrteei */
05332d70 5167GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5168{
5169#if defined(CONFIG_USER_ONLY)
e1833e1f 5170 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5171#else
5172 if (unlikely(!ctx->supervisor)) {
e1833e1f 5173 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5174 return;
5175 }
86c581dc 5176 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5177 gen_op_wrte();
dee96f6c
JM		 5178 /* Stop translation to have a chance to raise an exception
5179 * if we just set msr_ee to 1
5180 */
e1833e1f 5181 GEN_STOP(ctx);
76a66253
JM		 5182#endif
5183}
5184
08e46e54 5185/* PowerPC 440 specific instructions */
76a66253
JM		 5186/* dlmzb */
5187GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5188{
f78fb44e
AJ		 5189 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5190 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5191 gen_op_440_dlmzb();
f78fb44e 5192 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5193 gen_op_store_xer_bc();
5194 if (Rc(ctx->opcode)) {
5195 gen_op_440_dlmzb_update_Rc();
47e4661c 5196 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
76a66253
JM		 5197 }
5198}
5199
5200/* mbar replaces eieio on 440 */
5201GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5202{
5203 /* interpreted as no-op */
5204}
5205
5206/* msync replaces sync on 440 */
0db1b20e 5207GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5208{
5209 /* interpreted as no-op */
5210}
5211
5212/* icbt */
c7697e1f 5213GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5214{
5215 /* interpreted as no-op */
5216 /* XXX: specification say this is treated as a load by the MMU
5217 * but does not generate any exception
5218 */
79aceca5
FB		 5219}
5220
a9d9eb8f
JM		 5221/*** Altivec vector extension ***/
5222/* Altivec registers moves */
a9d9eb8f 5223
1d542695
AJ		 5224static always_inline void gen_load_avr(int t, int reg) {
5225 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5226 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5227}
5228
5229static always_inline void gen_store_avr(int reg, int t) {
5230 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5231 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5232}
a9d9eb8f
JM		 5233
5234#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5235#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5236static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5237 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5238};
5239#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5240static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5241 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5242};
a9d9eb8f
JM		 5243
5244#define GEN_VR_LDX(name, opc2, opc3) \
5245GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5246{ \
5247 if (unlikely(!ctx->altivec_enabled)) { \
5248 GEN_EXCP_NO_VR(ctx); \
5249 return; \
5250 } \
e2be8d8d 5251 gen_addr_reg_index(cpu_T[0], ctx); \
a9d9eb8f 5252 op_vr_ldst(vr_l##name); \
1d542695 5253 gen_store_avr(rD(ctx->opcode), 0); \
a9d9eb8f
JM		 5254}
5255
5256#define GEN_VR_STX(name, opc2, opc3) \
5257GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5258{ \
5259 if (unlikely(!ctx->altivec_enabled)) { \
5260 GEN_EXCP_NO_VR(ctx); \
5261 return; \
5262 } \
e2be8d8d 5263 gen_addr_reg_index(cpu_T[0], ctx); \
1d542695 5264 gen_load_avr(0, rS(ctx->opcode)); \
a9d9eb8f
JM		 5265 op_vr_ldst(vr_st##name); \
5266}
5267
5268OP_VR_LD_TABLE(vx);
5269GEN_VR_LDX(vx, 0x07, 0x03);
5270/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5271#define gen_op_vr_lvxl gen_op_vr_lvx
5272GEN_VR_LDX(vxl, 0x07, 0x0B);
5273
5274OP_VR_ST_TABLE(vx);
5275GEN_VR_STX(vx, 0x07, 0x07);
5276/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5277#define gen_op_vr_stvxl gen_op_vr_stvx
5278GEN_VR_STX(vxl, 0x07, 0x0F);
5279
0487d6a8 5280/*** SPE extension ***/
0487d6a8 5281/* Register moves */
3cd7d1dd 5282
f78fb44e
AJ		 5283static always_inline void gen_load_gpr64(TCGv t, int reg) {
5284#if defined(TARGET_PPC64)
5285 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5286#else
36aa55dc 5287 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5288#endif
f78fb44e 5289}
3cd7d1dd 5290
f78fb44e
AJ		 5291static always_inline void gen_store_gpr64(int reg, TCGv t) {
5292#if defined(TARGET_PPC64)
5293 tcg_gen_mov_i64(cpu_gpr[reg], t);
5294#else
5295 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
5296 TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64);
5297 tcg_gen_shri_i64(tmp, t, 32);
5298 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5299 tcg_temp_free(tmp);
3cd7d1dd 5300#endif
f78fb44e 5301}
3cd7d1dd 5302
0487d6a8
JM		 5303#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5304GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5305{ \
5306 if (Rc(ctx->opcode)) \
5307 gen_##name1(ctx); \
5308 else \
5309 gen_##name0(ctx); \
5310}
5311
5312/* Handler for undefined SPE opcodes */
b068d6a7 5313static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5314{
e1833e1f 5315 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5316}
5317
5318/* SPE load and stores */
b068d6a7 5319static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
0487d6a8
JM		 5320{
5321 target_long simm = rB(ctx->opcode);
5322
5323 if (rA(ctx->opcode) == 0) {
02f4f6c2 5324 tcg_gen_movi_tl(cpu_T[0], simm << sh);
0487d6a8 5325 } else {
f78fb44e 5326 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
0487d6a8 5327 if (likely(simm != 0))
39dd32ee 5328 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh);
0487d6a8
JM		 5329 }
5330}
5331
5332#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5333#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5334static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5335 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5336};
5337#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5338static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5339 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5340};
0487d6a8
JM		 5341
5342#define GEN_SPE_LD(name, sh) \
b068d6a7 5343static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5344{ \
5345 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5346 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5347 return; \
5348 } \
5349 gen_addr_spe_imm_index(ctx, sh); \
5350 op_spe_ldst(spe_l##name); \
f78fb44e 5351 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5352}
5353
5354#define GEN_SPE_LDX(name) \
b068d6a7 5355static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 5356{ \
5357 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5358 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5359 return; \
5360 } \
e2be8d8d 5361 gen_addr_reg_index(cpu_T[0], ctx); \
0487d6a8 5362 op_spe_ldst(spe_l##name); \
f78fb44e 5363 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5364}
5365
5366#define GEN_SPEOP_LD(name, sh) \
5367OP_SPE_LD_TABLE(name); \
5368GEN_SPE_LD(name, sh); \
5369GEN_SPE_LDX(name)
5370
5371#define GEN_SPE_ST(name, sh) \
b068d6a7 5372static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 5373{ \
5374 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5375 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5376 return; \
5377 } \
5378 gen_addr_spe_imm_index(ctx, sh); \
f78fb44e 5379 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5380 op_spe_ldst(spe_st##name); \
5381}
5382
5383#define GEN_SPE_STX(name) \
b068d6a7 5384static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 5385{ \
5386 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5387 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5388 return; \
5389 } \
e2be8d8d 5390 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 5391 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5392 op_spe_ldst(spe_st##name); \
5393}
5394
5395#define GEN_SPEOP_ST(name, sh) \
5396OP_SPE_ST_TABLE(name); \
5397GEN_SPE_ST(name, sh); \
5398GEN_SPE_STX(name)
5399
5400#define GEN_SPEOP_LDST(name, sh) \
5401GEN_SPEOP_LD(name, sh); \
5402GEN_SPEOP_ST(name, sh)
5403
5404/* SPE arithmetic and logic */
5405#define GEN_SPEOP_ARITH2(name) \
b068d6a7 5406static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5407{ \
5408 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5409 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5410 return; \
5411 } \
f78fb44e
AJ		 5412 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5413 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5414 gen_op_##name(); \
f78fb44e 5415 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5416}
5417
5418#define GEN_SPEOP_ARITH1(name) \
b068d6a7 5419static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5420{ \
5421 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5422 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5423 return; \
5424 } \
f78fb44e 5425 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8 5426 gen_op_##name(); \
f78fb44e 5427 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5428}
5429
5430#define GEN_SPEOP_COMP(name) \
b068d6a7 5431static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5432{ \
5433 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5434 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5435 return; \
5436 } \
f78fb44e
AJ		 5437 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5438 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5439 gen_op_##name(); \
47e4661c 5440 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
0487d6a8
JM		 5441}
5442
5443/* Logical */
5444GEN_SPEOP_ARITH2(evand);
5445GEN_SPEOP_ARITH2(evandc);
5446GEN_SPEOP_ARITH2(evxor);
5447GEN_SPEOP_ARITH2(evor);
5448GEN_SPEOP_ARITH2(evnor);
5449GEN_SPEOP_ARITH2(eveqv);
5450GEN_SPEOP_ARITH2(evorc);
5451GEN_SPEOP_ARITH2(evnand);
5452GEN_SPEOP_ARITH2(evsrwu);
5453GEN_SPEOP_ARITH2(evsrws);
5454GEN_SPEOP_ARITH2(evslw);
5455GEN_SPEOP_ARITH2(evrlw);
5456GEN_SPEOP_ARITH2(evmergehi);
5457GEN_SPEOP_ARITH2(evmergelo);
5458GEN_SPEOP_ARITH2(evmergehilo);
5459GEN_SPEOP_ARITH2(evmergelohi);
5460
5461/* Arithmetic */
5462GEN_SPEOP_ARITH2(evaddw);
5463GEN_SPEOP_ARITH2(evsubfw);
5464GEN_SPEOP_ARITH1(evabs);
5465GEN_SPEOP_ARITH1(evneg);
5466GEN_SPEOP_ARITH1(evextsb);
5467GEN_SPEOP_ARITH1(evextsh);
5468GEN_SPEOP_ARITH1(evrndw);
5469GEN_SPEOP_ARITH1(evcntlzw);
5470GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 5471static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 5472{
5473 /* Note: brinc is usable even if SPE is disabled */
f78fb44e
AJ		 5474 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5475 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 5476 gen_op_brinc();
f78fb44e 5477 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
0487d6a8
JM		 5478}
5479
5480#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 5481static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5482{ \
5483 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5484 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5485 return; \
5486 } \
f78fb44e 5487 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8
JM		 5488 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5489 gen_op_##name(); \
f78fb44e 5490 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5491}
5492
5493#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 5494static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5495{ \
5496 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5497 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5498 return; \
5499 } \
f78fb44e 5500 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8
JM		 5501 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5502 gen_op_##name(); \
f78fb44e 5503 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5504}
5505
5506GEN_SPEOP_ARITH_IMM2(evaddw);
5507#define gen_evaddiw gen_evaddwi
5508GEN_SPEOP_ARITH_IMM2(evsubfw);
5509#define gen_evsubifw gen_evsubfwi
5510GEN_SPEOP_LOGIC_IMM2(evslw);
5511GEN_SPEOP_LOGIC_IMM2(evsrwu);
5512#define gen_evsrwis gen_evsrwsi
5513GEN_SPEOP_LOGIC_IMM2(evsrws);
5514#define gen_evsrwiu gen_evsrwui
5515GEN_SPEOP_LOGIC_IMM2(evrlw);
5516
b068d6a7 5517static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 5518{
5519 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5520
5521 gen_op_splatwi_T0_64(imm);
f78fb44e 5522 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5523}
5524
b068d6a7 5525static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 5526{
5527 uint32_t imm = rA(ctx->opcode) << 27;
5528
5529 gen_op_splatwi_T0_64(imm);
f78fb44e 5530 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5531}
5532
5533/* Comparison */
5534GEN_SPEOP_COMP(evcmpgtu);
5535GEN_SPEOP_COMP(evcmpgts);
5536GEN_SPEOP_COMP(evcmpltu);
5537GEN_SPEOP_COMP(evcmplts);
5538GEN_SPEOP_COMP(evcmpeq);
5539
5540GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5541GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5542GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5543GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5544GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5545GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5546GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5547GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5548GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5549GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5550GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5551GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5552GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5553GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5554GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5555GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5556GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5557GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5558GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5559GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5560GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5561GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5562GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5563GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5564GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5565
b068d6a7 5566static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 5567{
5568 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 5569 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 5570 return;
5571 }
47e4661c 5572 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
f78fb44e
AJ		 5573 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
5574 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
0487d6a8 5575 gen_op_evsel();
f78fb44e 5576 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5577}
5578
c7697e1f 5579GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5580{
5581 gen_evsel(ctx);
5582}
c7697e1f 5583GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5584{
5585 gen_evsel(ctx);
5586}
c7697e1f 5587GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5588{
5589 gen_evsel(ctx);
5590}
c7697e1f 5591GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5592{
5593 gen_evsel(ctx);
5594}
5595
5596/* Load and stores */
5597#if defined(TARGET_PPC64)
5598/* In that case, we already have 64 bits load & stores
5599 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5600 */
7863667f
JM		 5601#define gen_op_spe_ldd_raw gen_op_ld_raw
5602#define gen_op_spe_ldd_user gen_op_ld_user
5603#define gen_op_spe_ldd_kernel gen_op_ld_kernel
5604#define gen_op_spe_ldd_hypv gen_op_ld_hypv
5605#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5606#define gen_op_spe_ldd_64_user gen_op_ld_64_user
5607#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5608#define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
5609#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5610#define gen_op_spe_ldd_le_user gen_op_ld_le_user
5611#define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
5612#define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
5613#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5614#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5615#define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
5616#define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
5617#define gen_op_spe_stdd_raw gen_op_std_raw
5618#define gen_op_spe_stdd_user gen_op_std_user
5619#define gen_op_spe_stdd_kernel gen_op_std_kernel
5620#define gen_op_spe_stdd_hypv gen_op_std_hypv
5621#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5622#define gen_op_spe_stdd_64_user gen_op_std_64_user
5623#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5624#define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
5625#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5626#define gen_op_spe_stdd_le_user gen_op_std_le_user
5627#define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
5628#define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
5629#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5630#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5631#define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
5632#define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
0487d6a8
JM		 5633#endif /* defined(TARGET_PPC64) */
5634GEN_SPEOP_LDST(dd, 3);
5635GEN_SPEOP_LDST(dw, 3);
5636GEN_SPEOP_LDST(dh, 3);
5637GEN_SPEOP_LDST(whe, 2);
5638GEN_SPEOP_LD(whou, 2);
5639GEN_SPEOP_LD(whos, 2);
5640GEN_SPEOP_ST(who, 2);
5641
5642#if defined(TARGET_PPC64)
5643/* In that case, spe_stwwo is equivalent to stw */
7863667f
JM		 5644#define gen_op_spe_stwwo_raw gen_op_stw_raw
5645#define gen_op_spe_stwwo_user gen_op_stw_user
5646#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5647#define gen_op_spe_stwwo_hypv gen_op_stw_hypv
5648#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5649#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5650#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5651#define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
5652#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5653#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5654#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5655#define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
5656#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5657#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
0487d6a8 5658#define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
7863667f 5659#define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
0487d6a8
JM		 5660#endif
5661#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 5662static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 5663{ \
5664 gen_op_srli32_T1_64(); \
5665 gen_op_spe_stwwo_##suffix(); \
5666}
5667#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 5668static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 5669{ \
5670 gen_op_srli32_T1_64(); \
5671 gen_op_spe_stwwo_le_##suffix(); \
5672}
5673#if defined(TARGET_PPC64)
5674#define GEN_OP_SPE_STWWE(suffix) \
5675_GEN_OP_SPE_STWWE(suffix); \
5676_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 5677static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 5678{ \
5679 gen_op_srli32_T1_64(); \
5680 gen_op_spe_stwwo_64_##suffix(); \
5681} \
b068d6a7 5682static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 5683{ \
5684 gen_op_srli32_T1_64(); \
5685 gen_op_spe_stwwo_le_64_##suffix(); \
5686}
5687#else
5688#define GEN_OP_SPE_STWWE(suffix) \
5689_GEN_OP_SPE_STWWE(suffix); \
5690_GEN_OP_SPE_STWWE_LE(suffix)
5691#endif
5692#if defined(CONFIG_USER_ONLY)
5693GEN_OP_SPE_STWWE(raw);
5694#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 5695GEN_OP_SPE_STWWE(user);
7863667f
JM		 5696GEN_OP_SPE_STWWE(kernel);
5697GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 5698#endif /* defined(CONFIG_USER_ONLY) */
5699GEN_SPEOP_ST(wwe, 2);
5700GEN_SPEOP_ST(wwo, 2);
5701
5702#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 5703static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 5704{ \
5705 gen_op_##op##_##suffix(); \
5706 gen_op_splatw_T1_64(); \
5707}
5708
5709#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 5710static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 5711{ \
5712 gen_op_spe_lh_##suffix(); \
5713 gen_op_sli16_T1_64(); \
5714}
5715
5716#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 5717static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 5718{ \
5719 gen_op_spe_lh_##suffix(); \
5720 gen_op_extsh_T1_64(); \
5721}
5722
5723#if defined(CONFIG_USER_ONLY)
5724GEN_OP_SPE_LHE(raw);
5725GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
5726GEN_OP_SPE_LHE(le_raw);
5727GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
5728GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
5729GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
5730GEN_OP_SPE_LHX(raw);
5731GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
5732GEN_OP_SPE_LHX(le_raw);
5733GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
5734#if defined(TARGET_PPC64)
5735GEN_OP_SPE_LHE(64_raw);
5736GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
5737GEN_OP_SPE_LHE(le_64_raw);
5738GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
5739GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
5740GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
5741GEN_OP_SPE_LHX(64_raw);
5742GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
5743GEN_OP_SPE_LHX(le_64_raw);
5744GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
5745#endif
5746#else
0487d6a8 5747GEN_OP_SPE_LHE(user);
7863667f
JM		 5748GEN_OP_SPE_LHE(kernel);
5749GEN_OP_SPE_LHE(hypv);
0487d6a8 5750GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 5751GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
5752GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 5753GEN_OP_SPE_LHE(le_user);
7863667f
JM		 5754GEN_OP_SPE_LHE(le_kernel);
5755GEN_OP_SPE_LHE(le_hypv);
0487d6a8 5756GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 5757GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
5758GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 5759GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 5760GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
5761GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 5762GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 5763GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
5764GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 5765GEN_OP_SPE_LHX(user);
7863667f
JM		 5766GEN_OP_SPE_LHX(kernel);
5767GEN_OP_SPE_LHX(hypv);
0487d6a8 5768GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 5769GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
5770GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 5771GEN_OP_SPE_LHX(le_user);
7863667f
JM		 5772GEN_OP_SPE_LHX(le_kernel);
5773GEN_OP_SPE_LHX(le_hypv);
0487d6a8 5774GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 5775GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
5776GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 5777#if defined(TARGET_PPC64)
0487d6a8 5778GEN_OP_SPE_LHE(64_user);
7863667f
JM		 5779GEN_OP_SPE_LHE(64_kernel);
5780GEN_OP_SPE_LHE(64_hypv);
0487d6a8 5781GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 5782GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
5783GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 5784GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 5785GEN_OP_SPE_LHE(le_64_kernel);
5786GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 5787GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 5788GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
5789GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 5790GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 5791GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
5792GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 5793GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 5794GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
5795GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 5796GEN_OP_SPE_LHX(64_user);
7863667f
JM		 5797GEN_OP_SPE_LHX(64_kernel);
5798GEN_OP_SPE_LHX(64_hypv);
0487d6a8 5799GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 5800GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
5801GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 5802GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 5803GEN_OP_SPE_LHX(le_64_kernel);
5804GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 5805GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 5806GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
5807GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 5808#endif
5809#endif
5810GEN_SPEOP_LD(hhesplat, 1);
5811GEN_SPEOP_LD(hhousplat, 1);
5812GEN_SPEOP_LD(hhossplat, 1);
5813GEN_SPEOP_LD(wwsplat, 2);
5814GEN_SPEOP_LD(whsplat, 2);
5815
5816GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
5817GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
5818GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
5819GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
5820GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
5821GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
5822GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
5823GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
5824GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
5825GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
5826GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
5827GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
5828GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
5829GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
5830GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
5831GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
5832GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
5833GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
5834
5835/* Multiply and add - TODO */
5836#if 0
5837GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
5838GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
5839GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
5840GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
5841GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
5842GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
5843GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
5844GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
5845GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
5846GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
5847GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
5848GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
5849
5850GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
5851GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
5852GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
5853GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
5854GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
5855GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
5856GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
5857GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
5858GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
5859GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
5860GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
5861GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
5862GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
5863GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
5864
5865GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
5866GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
5867GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
5868GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
5869GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
5870GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
5871
5872GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
5873GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
5874GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
5875GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
5876GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
5877GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
5878GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
5879GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
5880GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
5881GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
5882GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
5883GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
5884
5885GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
5886GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
5887GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
5888GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
5889GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
5890
5891GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
5892GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
5893GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
5894GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
5895GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
5896GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
5897GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
5898GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
5899GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
5900GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
5901GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
5902GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
5903
5904GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
5905GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
5906GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
5907GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
5908GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
5909#endif
5910
5911/*** SPE floating-point extension ***/
5912#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 5913static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 5914{ \
f78fb44e 5915 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8 5916 gen_op_##name(); \
f78fb44e 5917 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5918}
5919
5920/* Single precision floating-point vectors operations */
5921/* Arithmetic */
5922GEN_SPEOP_ARITH2(evfsadd);
5923GEN_SPEOP_ARITH2(evfssub);
5924GEN_SPEOP_ARITH2(evfsmul);
5925GEN_SPEOP_ARITH2(evfsdiv);
5926GEN_SPEOP_ARITH1(evfsabs);
5927GEN_SPEOP_ARITH1(evfsnabs);
5928GEN_SPEOP_ARITH1(evfsneg);
5929/* Conversion */
5930GEN_SPEFPUOP_CONV(evfscfui);
5931GEN_SPEFPUOP_CONV(evfscfsi);
5932GEN_SPEFPUOP_CONV(evfscfuf);
5933GEN_SPEFPUOP_CONV(evfscfsf);
5934GEN_SPEFPUOP_CONV(evfsctui);
5935GEN_SPEFPUOP_CONV(evfsctsi);
5936GEN_SPEFPUOP_CONV(evfsctuf);
5937GEN_SPEFPUOP_CONV(evfsctsf);
5938GEN_SPEFPUOP_CONV(evfsctuiz);
5939GEN_SPEFPUOP_CONV(evfsctsiz);
5940/* Comparison */
5941GEN_SPEOP_COMP(evfscmpgt);
5942GEN_SPEOP_COMP(evfscmplt);
5943GEN_SPEOP_COMP(evfscmpeq);
5944GEN_SPEOP_COMP(evfststgt);
5945GEN_SPEOP_COMP(evfststlt);
5946GEN_SPEOP_COMP(evfststeq);
5947
5948/* Opcodes definitions */
5949GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
5950GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
5951GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
5952GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
5953GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
5954GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
5955GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
5956GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
5957GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
5958GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
5959GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
5960GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
5961GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
5962GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
5963
5964/* Single precision floating-point operations */
5965/* Arithmetic */
5966GEN_SPEOP_ARITH2(efsadd);
5967GEN_SPEOP_ARITH2(efssub);
5968GEN_SPEOP_ARITH2(efsmul);
5969GEN_SPEOP_ARITH2(efsdiv);
5970GEN_SPEOP_ARITH1(efsabs);
5971GEN_SPEOP_ARITH1(efsnabs);
5972GEN_SPEOP_ARITH1(efsneg);
5973/* Conversion */
5974GEN_SPEFPUOP_CONV(efscfui);
5975GEN_SPEFPUOP_CONV(efscfsi);
5976GEN_SPEFPUOP_CONV(efscfuf);
5977GEN_SPEFPUOP_CONV(efscfsf);
5978GEN_SPEFPUOP_CONV(efsctui);
5979GEN_SPEFPUOP_CONV(efsctsi);
5980GEN_SPEFPUOP_CONV(efsctuf);
5981GEN_SPEFPUOP_CONV(efsctsf);
5982GEN_SPEFPUOP_CONV(efsctuiz);
5983GEN_SPEFPUOP_CONV(efsctsiz);
5984GEN_SPEFPUOP_CONV(efscfd);
5985/* Comparison */
5986GEN_SPEOP_COMP(efscmpgt);
5987GEN_SPEOP_COMP(efscmplt);
5988GEN_SPEOP_COMP(efscmpeq);
5989GEN_SPEOP_COMP(efststgt);
5990GEN_SPEOP_COMP(efststlt);
5991GEN_SPEOP_COMP(efststeq);
5992
5993/* Opcodes definitions */
05332d70 5994GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 5995GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
5996GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
5997GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
5998GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
5999GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6000GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6001GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6002GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6003GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 6004GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6005GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 6006GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6007GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6008
6009/* Double precision floating-point operations */
6010/* Arithmetic */
6011GEN_SPEOP_ARITH2(efdadd);
6012GEN_SPEOP_ARITH2(efdsub);
6013GEN_SPEOP_ARITH2(efdmul);
6014GEN_SPEOP_ARITH2(efddiv);
6015GEN_SPEOP_ARITH1(efdabs);
6016GEN_SPEOP_ARITH1(efdnabs);
6017GEN_SPEOP_ARITH1(efdneg);
6018/* Conversion */
6019
6020GEN_SPEFPUOP_CONV(efdcfui);
6021GEN_SPEFPUOP_CONV(efdcfsi);
6022GEN_SPEFPUOP_CONV(efdcfuf);
6023GEN_SPEFPUOP_CONV(efdcfsf);
6024GEN_SPEFPUOP_CONV(efdctui);
6025GEN_SPEFPUOP_CONV(efdctsi);
6026GEN_SPEFPUOP_CONV(efdctuf);
6027GEN_SPEFPUOP_CONV(efdctsf);
6028GEN_SPEFPUOP_CONV(efdctuiz);
6029GEN_SPEFPUOP_CONV(efdctsiz);
6030GEN_SPEFPUOP_CONV(efdcfs);
6031GEN_SPEFPUOP_CONV(efdcfuid);
6032GEN_SPEFPUOP_CONV(efdcfsid);
6033GEN_SPEFPUOP_CONV(efdctuidz);
6034GEN_SPEFPUOP_CONV(efdctsidz);
6035/* Comparison */
6036GEN_SPEOP_COMP(efdcmpgt);
6037GEN_SPEOP_COMP(efdcmplt);
6038GEN_SPEOP_COMP(efdcmpeq);
6039GEN_SPEOP_COMP(efdtstgt);
6040GEN_SPEOP_COMP(efdtstlt);
6041GEN_SPEOP_COMP(efdtsteq);
6042
6043/* Opcodes definitions */
6044GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6045GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6046GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6047GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6048GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6049GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6050GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6051GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6052GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6053GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6054GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6055GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6056GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6057GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6058GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6059GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6060
79aceca5
FB		 6061/* End opcode list */
6062GEN_OPCODE_MARK(end);
6063
3fc6c082 6064#include "translate_init.c"
0411a972 6065#include "helper_regs.h"
79aceca5 6066
9a64fbe4 6067/*****************************************************************************/
3fc6c082 6068/* Misc PowerPC helpers */
36081602
JM		 6069void cpu_dump_state (CPUState *env, FILE *f,
6070 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6071 int flags)
79aceca5 6072{
3fc6c082
FB		 6073#define RGPL 4
6074#define RFPL 4
3fc6c082 6075
79aceca5
FB		 6076 int i;
6077
077fc206
JM		 6078 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6079 env->nip, env->lr, env->ctr, hreg_load_xer(env));
6b542af7
JM		 6080 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6081 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 6082#if !defined(NO_TIMER_DUMP)
077fc206 6083 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6084#if !defined(CONFIG_USER_ONLY)
6085 "DECR %08x"
6086#endif
6087 "\n",
077fc206 6088 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6089#if !defined(CONFIG_USER_ONLY)
6090 , cpu_ppc_load_decr(env)
6091#endif
6092 );
077fc206 6093#endif
76a66253 6094 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6095 if ((i & (RGPL - 1)) == 0)
6096 cpu_fprintf(f, "GPR%02d", i);
6b542af7 6097 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 6098 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6099 cpu_fprintf(f, "\n");
76a66253 6100 }
3fc6c082 6101 cpu_fprintf(f, "CR ");
76a66253 6102 for (i = 0; i < 8; i++)
7fe48483
FB		 6103 cpu_fprintf(f, "%01x", env->crf[i]);
6104 cpu_fprintf(f, " [");
76a66253
JM		 6105 for (i = 0; i < 8; i++) {
6106 char a = '-';
6107 if (env->crf[i] & 0x08)
6108 a = 'L';
6109 else if (env->crf[i] & 0x04)
6110 a = 'G';
6111 else if (env->crf[i] & 0x02)
6112 a = 'E';
7fe48483 6113 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6114 }
6b542af7 6115 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 6116 for (i = 0; i < 32; i++) {
6117 if ((i & (RFPL - 1)) == 0)
6118 cpu_fprintf(f, "FPR%02d", i);
26a76461 6119 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6120 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6121 cpu_fprintf(f, "\n");
79aceca5 6122 }
f2e63a42 6123#if !defined(CONFIG_USER_ONLY)
6b542af7 6124 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 6125 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6126#endif
79aceca5 6127
3fc6c082
FB		 6128#undef RGPL
6129#undef RFPL
79aceca5
FB		 6130}
6131
76a66253
JM		 6132void cpu_dump_statistics (CPUState *env, FILE*f,
6133 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6134 int flags)
6135{
6136#if defined(DO_PPC_STATISTICS)
6137 opc_handler_t **t1, **t2, **t3, *handler;
6138 int op1, op2, op3;
6139
6140 t1 = env->opcodes;
6141 for (op1 = 0; op1 < 64; op1++) {
6142 handler = t1[op1];
6143 if (is_indirect_opcode(handler)) {
6144 t2 = ind_table(handler);
6145 for (op2 = 0; op2 < 32; op2++) {
6146 handler = t2[op2];
6147 if (is_indirect_opcode(handler)) {
6148 t3 = ind_table(handler);
6149 for (op3 = 0; op3 < 32; op3++) {
6150 handler = t3[op3];
6151 if (handler->count == 0)
6152 continue;
6153 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6154 "%016llx %lld\n",
6155 op1, op2, op3, op1, (op3 << 5) | op2,
6156 handler->oname,
6157 handler->count, handler->count);
6158 }
6159 } else {
6160 if (handler->count == 0)
6161 continue;
6162 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6163 "%016llx %lld\n",
6164 op1, op2, op1, op2, handler->oname,
6165 handler->count, handler->count);
6166 }
6167 }
6168 } else {
6169 if (handler->count == 0)
6170 continue;
6171 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6172 op1, op1, handler->oname,
6173 handler->count, handler->count);
6174 }
6175 }
6176#endif
6177}
6178
9a64fbe4 6179/*****************************************************************************/
2cfc5f17
TS		 6180static always_inline void gen_intermediate_code_internal (CPUState *env,
6181 TranslationBlock *tb,
6182 int search_pc)
79aceca5 6183{
9fddaa0c 6184 DisasContext ctx, *ctxp = &ctx;
79aceca5 6185 opc_handler_t **table, *handler;
0fa85d43 6186 target_ulong pc_start;
79aceca5 6187 uint16_t *gen_opc_end;
056401ea 6188 int supervisor, little_endian;
79aceca5 6189 int j, lj = -1;
2e70f6ef
PB		 6190 int num_insns;
6191 int max_insns;
79aceca5
FB		 6192
6193 pc_start = tb->pc;
79aceca5 6194 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 6195#if defined(OPTIMIZE_FPRF_UPDATE)
6196 gen_fprf_ptr = gen_fprf_buf;
6197#endif
046d6672 6198 ctx.nip = pc_start;
79aceca5 6199 ctx.tb = tb;
e1833e1f 6200 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6201 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6202 supervisor = env->mmu_idx;
6203#if !defined(CONFIG_USER_ONLY)
2857068e 6204 ctx.supervisor = supervisor;
d9bce9d9 6205#endif
056401ea 6206 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6207#if defined(TARGET_PPC64)
6208 ctx.sf_mode = msr_sf;
056401ea 6209 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6210#else
056401ea 6211 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6212#endif
d63001d1 6213 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6214 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6215 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6216 ctx.spe_enabled = msr_spe;
6217 else
6218 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6219 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6220 ctx.altivec_enabled = msr_vr;
6221 else
6222 ctx.altivec_enabled = 0;
d26bfc9a 6223 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 6224 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 6225 else
8cbcb4fa 6226 ctx.singlestep_enabled = 0;
d26bfc9a 6227 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 6228 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6229 if (unlikely(env->singlestep_enabled))
6230 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 6231#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6232 /* Single step trace mode */
6233 msr_se = 1;
6234#endif
2e70f6ef
PB		 6235 num_insns = 0;
6236 max_insns = tb->cflags & CF_COUNT_MASK;
6237 if (max_insns == 0)
6238 max_insns = CF_COUNT_MASK;
6239
6240 gen_icount_start();
9a64fbe4 6241 /* Set env in case of segfault during code fetch */
e1833e1f 6242 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6243 if (unlikely(env->nb_breakpoints > 0)) {
6244 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6245 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6246 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6247 gen_op_debug();
6248 break;
6249 }
6250 }
6251 }
76a66253 6252 if (unlikely(search_pc)) {
79aceca5
FB		 6253 j = gen_opc_ptr - gen_opc_buf;
6254 if (lj < j) {
6255 lj++;
6256 while (lj < j)
6257 gen_opc_instr_start[lj++] = 0;
046d6672 6258 gen_opc_pc[lj] = ctx.nip;
79aceca5 6259 gen_opc_instr_start[lj] = 1;
2e70f6ef 6260 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 6261 }
6262 }
9fddaa0c
FB		 6263#if defined PPC_DEBUG_DISAS
6264 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6265 fprintf(logfile, "----------------\n");
1b9eb036 6266 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6267 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6268 }
6269#endif
2e70f6ef
PB		 6270 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6271 gen_io_start();
056401ea
JM		 6272 if (unlikely(little_endian)) {
6273 ctx.opcode = bswap32(ldl_code(ctx.nip));
6274 } else {
6275 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6276 }
9fddaa0c
FB		 6277#if defined PPC_DEBUG_DISAS
6278 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6279 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6280 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6281 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6282 }
6283#endif
046d6672 6284 ctx.nip += 4;
3fc6c082 6285 table = env->opcodes;
2e70f6ef 6286 num_insns++;
79aceca5
FB		 6287 handler = table[opc1(ctx.opcode)];
6288 if (is_indirect_opcode(handler)) {
6289 table = ind_table(handler);
6290 handler = table[opc2(ctx.opcode)];
6291 if (is_indirect_opcode(handler)) {
6292 table = ind_table(handler);
6293 handler = table[opc3(ctx.opcode)];
6294 }
6295 }
6296 /* Is opcode *REALLY* valid ? */
76a66253 6297 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6298 if (loglevel != 0) {
76a66253 6299 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 6300 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 6301 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6302 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6303 } else {
6304 printf("invalid/unsupported opcode: "
6b542af7 6305 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 6306 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6307 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6308 }
76a66253
JM		 6309 } else {
6310 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6311 if (loglevel != 0) {
79aceca5 6312 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 6313 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 6314 ctx.opcode & handler->inval, opc1(ctx.opcode),
6315 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6316 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6317 } else {
6318 printf("invalid bits: %08x for opcode: "
6b542af7 6319 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 6320 ctx.opcode & handler->inval, opc1(ctx.opcode),
6321 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6322 ctx.opcode, ctx.nip - 4);
76a66253 6323 }
e1833e1f 6324 GEN_EXCP_INVAL(ctxp);
4b3686fa 6325 break;
79aceca5 6326 }
79aceca5 6327 }
4b3686fa 6328 (*(handler->handler))(&ctx);
76a66253
JM		 6329#if defined(DO_PPC_STATISTICS)
6330 handler->count++;
6331#endif
9a64fbe4 6332 /* Check trace mode exceptions */
8cbcb4fa
AJ		 6333 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6334 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6335 ctx.exception != POWERPC_SYSCALL &&
6336 ctx.exception != POWERPC_EXCP_TRAP &&
6337 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 6338 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 6339 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 6340 (env->singlestep_enabled) ||
6341 num_insns >= max_insns)) {
d26bfc9a
JM		 6342 /* if we reach a page boundary or are single stepping, stop
6343 * generation
6344 */
8dd4983c 6345 break;
76a66253 6346 }
3fc6c082
FB		 6347#if defined (DO_SINGLE_STEP)
6348 break;
6349#endif
6350 }
2e70f6ef
PB		 6351 if (tb->cflags & CF_LAST_IO)
6352 gen_io_end();
e1833e1f 6353 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6354 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6355 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 6356 if (unlikely(env->singlestep_enabled)) {
6357 gen_update_nip(&ctx, ctx.nip);
6358 gen_op_debug();
6359 }
76a66253 6360 /* Generate the return instruction */
57fec1fe 6361 tcg_gen_exit_tb(0);
9a64fbe4 6362 }
2e70f6ef 6363 gen_icount_end(tb, num_insns);
79aceca5 6364 *gen_opc_ptr = INDEX_op_end;
76a66253 6365 if (unlikely(search_pc)) {
9a64fbe4
FB		 6366 j = gen_opc_ptr - gen_opc_buf;
6367 lj++;
6368 while (lj <= j)
6369 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6370 } else {
046d6672 6371 tb->size = ctx.nip - pc_start;
2e70f6ef 6372 tb->icount = num_insns;
9a64fbe4 6373 }
d9bce9d9 6374#if defined(DEBUG_DISAS)
9fddaa0c 6375 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6376 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6377 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6378 }
6379 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6380 int flags;
237c0af0 6381 flags = env->bfd_mach;
056401ea 6382 flags |= little_endian << 16;
0fa85d43 6383 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6384 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6385 fprintf(logfile, "\n");
9fddaa0c 6386 }
79aceca5 6387#endif
79aceca5
FB		 6388}
6389
2cfc5f17 6390void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 6391{
2cfc5f17 6392 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 6393}
6394
2cfc5f17 6395void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 6396{
2cfc5f17 6397 gen_intermediate_code_internal(env, tb, 1);
79aceca5 6398}
d2856f1a
AJ		 6399
6400void gen_pc_load(CPUState *env, TranslationBlock *tb,
6401 unsigned long searched_pc, int pc_pos, void *puc)
6402{
6403 int type, c;
6404 /* for PPC, we need to look at the micro operation to get the
6405 * access type */
6406 env->nip = gen_opc_pc[pc_pos];
6407 c = gen_opc_buf[pc_pos];
6408 switch(c) {
6409#if defined(CONFIG_USER_ONLY)
6410#define CASE3(op)\
6411 case INDEX_op_ ## op ## _raw
6412#else
6413#define CASE3(op)\
6414 case INDEX_op_ ## op ## _user:\
6415 case INDEX_op_ ## op ## _kernel:\
6416 case INDEX_op_ ## op ## _hypv
6417#endif
6418
6419 CASE3(stfd):
6420 CASE3(stfs):
6421 CASE3(lfd):
6422 CASE3(lfs):
6423 type = ACCESS_FLOAT;
6424 break;
6425 CASE3(lwarx):
6426 type = ACCESS_RES;
6427 break;
6428 CASE3(stwcx):
6429 type = ACCESS_RES;
6430 break;
6431 CASE3(eciwx):
6432 CASE3(ecowx):
6433 type = ACCESS_EXT;
6434 break;
6435 default:
6436 type = ACCESS_INT;
6437 break;
6438 }
6439 env->access_type = type;
6440}
Qemu copy for testing