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target-alpha: bug fix: avoid nop to override next instruction
[qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
79aceca5 19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
0cfe11ea 31#include "host-utils.h"
79aceca5 32
a7812ae4
PB		 33#include "helper.h"
34#define GEN_HELPER 1
35#include "helper.h"
36
8cbcb4fa
AJ		 37#define CPU_SINGLE_STEP 0x1
38#define CPU_BRANCH_STEP 0x2
39#define GDBSTUB_SINGLE_STEP 0x4
40
a750fc0b 41/* Include definitions for instructions classes and implementations flags */
e8fc4fa7 42//#define DO_SINGLE_STEP
9fddaa0c 43//#define PPC_DEBUG_DISAS
76a66253 44//#define DO_PPC_STATISTICS
79aceca5 45
d12d51d5 46#ifdef PPC_DEBUG_DISAS
93fcfe39 47# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 48#else
49# define LOG_DISAS(...) do { } while (0)
50#endif
a750fc0b
JM		 51/*****************************************************************************/
52/* Code translation helpers */
c53be334 53
f78fb44e 54/* global register indexes */
a7812ae4 55static TCGv_ptr cpu_env;
1d542695 56static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 57#if !defined(TARGET_PPC64)
1d542695 58 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 59#endif
a5e26afa 60 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 61 + 2*(10*6 + 22*7) /* AVRh, AVRl */
62 + 8*5 /* CRF */];
f78fb44e
AJ		 63static TCGv cpu_gpr[32];
64#if !defined(TARGET_PPC64)
65static TCGv cpu_gprh[32];
66#endif
a7812ae4
PB		 67static TCGv_i64 cpu_fpr[32];
68static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
69static TCGv_i32 cpu_crf[8];
bd568f18 70static TCGv cpu_nip;
6527f6ea 71static TCGv cpu_msr;
cfdcd37a
AJ		 72static TCGv cpu_ctr;
73static TCGv cpu_lr;
3d7b417e 74static TCGv cpu_xer;
cf360a32 75static TCGv cpu_reserve;
a7812ae4 76static TCGv_i32 cpu_fpscr;
a7859e89 77static TCGv_i32 cpu_access_type;
f78fb44e 78
2e70f6ef
PB		 79#include "gen-icount.h"
80
81void ppc_translate_init(void)
82{
f78fb44e
AJ		 83 int i;
84 char* p;
b2437bf2 85 static int done_init = 0;
f78fb44e 86
2e70f6ef
PB		 87 if (done_init)
88 return;
f78fb44e 89
a7812ae4 90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 91
f78fb44e 92 p = cpu_reg_names;
47e4661c
AJ		 93
94 for (i = 0; i < 8; i++) {
95 sprintf(p, "crf%d", i);
a7812ae4
PB		 96 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
97 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 98 p += 5;
99 }
100
f78fb44e
AJ		 101 for (i = 0; i < 32; i++) {
102 sprintf(p, "r%d", i);
a7812ae4 103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 104 offsetof(CPUState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106#if !defined(TARGET_PPC64)
107 sprintf(p, "r%dH", i);
a7812ae4
PB		 108 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
109 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 110 p += (i < 10) ? 4 : 5;
111#endif
1d542695 112
a5e26afa 113 sprintf(p, "fp%d", i);
a7812ae4
PB		 114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUState, fpr[i]), p);
ec1ac72d 116 p += (i < 10) ? 4 : 5;
a5e26afa 117
1d542695 118 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 119#ifdef WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUState, avr[i].u64[0]), p);
122#else
a7812ae4 123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 124 offsetof(CPUState, avr[i].u64[1]), p);
125#endif
1d542695 126 p += (i < 10) ? 6 : 7;
ec1ac72d 127
1d542695 128 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 129#ifdef WORDS_BIGENDIAN
130 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
131 offsetof(CPUState, avr[i].u64[1]), p);
132#else
a7812ae4 133 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 134 offsetof(CPUState, avr[i].u64[0]), p);
135#endif
1d542695 136 p += (i < 10) ? 6 : 7;
f78fb44e 137 }
f10dc08e 138
a7812ae4 139 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 140 offsetof(CPUState, nip), "nip");
141
6527f6ea
AJ		 142 cpu_msr = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUState, msr), "msr");
144
a7812ae4 145 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 146 offsetof(CPUState, ctr), "ctr");
147
a7812ae4 148 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 149 offsetof(CPUState, lr), "lr");
150
a7812ae4 151 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 152 offsetof(CPUState, xer), "xer");
153
cf360a32
AJ		 154 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, reserve), "reserve");
156
a7812ae4
PB		 157 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
158 offsetof(CPUState, fpscr), "fpscr");
e1571908 159
a7859e89
AJ		 160 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
161 offsetof(CPUState, access_type), "access_type");
162
f10dc08e 163 /* register helpers */
a7812ae4 164#define GEN_HELPER 2
f10dc08e
AJ		 165#include "helper.h"
166
2e70f6ef
PB		 167 done_init = 1;
168}
169
79aceca5
FB		 170/* internal defines */
171typedef struct DisasContext {
172 struct TranslationBlock *tb;
0fa85d43 173 target_ulong nip;
79aceca5 174 uint32_t opcode;
9a64fbe4 175 uint32_t exception;
3cc62370
FB		 176 /* Routine used to access memory */
177 int mem_idx;
76db3ba4 178 int access_type;
3cc62370 179 /* Translation flags */
76db3ba4 180 int le_mode;
d9bce9d9
JM		 181#if defined(TARGET_PPC64)
182 int sf_mode;
9a64fbe4 183#endif
3cc62370 184 int fpu_enabled;
a9d9eb8f 185 int altivec_enabled;
0487d6a8 186 int spe_enabled;
3fc6c082 187 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 188 int singlestep_enabled;
79aceca5
FB		 189} DisasContext;
190
3fc6c082 191struct opc_handler_t {
79aceca5
FB		 192 /* invalid bits */
193 uint32_t inval;
9a64fbe4 194 /* instruction type */
0487d6a8 195 uint64_t type;
79aceca5
FB		 196 /* handler */
197 void (*handler)(DisasContext *ctx);
a750fc0b 198#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 199 const char *oname;
a750fc0b
JM		 200#endif
201#if defined(DO_PPC_STATISTICS)
76a66253
JM		 202 uint64_t count;
203#endif
3fc6c082 204};
79aceca5 205
7c58044c
JM		 206static always_inline void gen_reset_fpstatus (void)
207{
208#ifdef CONFIG_SOFTFLOAT
a44d2ce1 209 gen_helper_reset_fpstatus();
7c58044c
JM		 210#endif
211}
212
0f2f39c2 213static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 214{
0f2f39c2 215 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 216
7c58044c
JM		 217 if (set_fprf != 0) {
218 /* This case might be optimized later */
0f2f39c2 219 tcg_gen_movi_i32(t0, 1);
af12906f 220 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 221 if (unlikely(set_rc)) {
0f2f39c2 222 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 223 }
af12906f 224 gen_helper_float_check_status();
7c58044c
JM		 225 } else if (unlikely(set_rc)) {
226 /* We always need to compute fpcc */
0f2f39c2 227 tcg_gen_movi_i32(t0, 0);
af12906f 228 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 229 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 230 }
af12906f 231
0f2f39c2 232 tcg_temp_free_i32(t0);
7c58044c
JM		 233}
234
76db3ba4 235static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
a7859e89 236{
76db3ba4
AJ		 237 if (ctx->access_type != access_type) {
238 tcg_gen_movi_i32(cpu_access_type, access_type);
239 ctx->access_type = access_type;
240 }
a7859e89
AJ		 241}
242
b068d6a7 243static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 244{
245#if defined(TARGET_PPC64)
246 if (ctx->sf_mode)
bd568f18 247 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 248 else
249#endif
bd568f18 250 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 251}
252
e06fcd75
AJ		 253static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
254{
255 TCGv_i32 t0, t1;
256 if (ctx->exception == POWERPC_EXCP_NONE) {
257 gen_update_nip(ctx, ctx->nip);
258 }
259 t0 = tcg_const_i32(excp);
260 t1 = tcg_const_i32(error);
261 gen_helper_raise_exception_err(t0, t1);
262 tcg_temp_free_i32(t0);
263 tcg_temp_free_i32(t1);
264 ctx->exception = (excp);
265}
e1833e1f 266
e06fcd75
AJ		 267static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
268{
269 TCGv_i32 t0;
270 if (ctx->exception == POWERPC_EXCP_NONE) {
271 gen_update_nip(ctx, ctx->nip);
272 }
273 t0 = tcg_const_i32(excp);
274 gen_helper_raise_exception(t0);
275 tcg_temp_free_i32(t0);
276 ctx->exception = (excp);
277}
e1833e1f 278
e06fcd75
AJ		 279static always_inline void gen_debug_exception (DisasContext *ctx)
280{
281 TCGv_i32 t0;
5518f3a6
BS		 282
283 if (ctx->exception != POWERPC_EXCP_BRANCH)
284 gen_update_nip(ctx, ctx->nip);
e06fcd75
AJ		 285 t0 = tcg_const_i32(EXCP_DEBUG);
286 gen_helper_raise_exception(t0);
287 tcg_temp_free_i32(t0);
288}
9a64fbe4 289
e06fcd75
AJ		 290static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
291{
292 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
293}
a9d9eb8f 294
f24e5695 295/* Stop translation */
e06fcd75 296static always_inline void gen_stop_exception (DisasContext *ctx)
3fc6c082 297{
d9bce9d9 298 gen_update_nip(ctx, ctx->nip);
e1833e1f 299 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 300}
301
f24e5695 302/* No need to update nip here, as execution flow will change */
e06fcd75 303static always_inline void gen_sync_exception (DisasContext *ctx)
2be0071f 304{
e1833e1f 305 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 306}
307
79aceca5
FB		 308#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
309static void gen_##name (DisasContext *ctx); \
310GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
311static void gen_##name (DisasContext *ctx)
312
c7697e1f
JM		 313#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
314static void gen_##name (DisasContext *ctx); \
315GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
316static void gen_##name (DisasContext *ctx)
317
79aceca5
FB		 318typedef struct opcode_t {
319 unsigned char opc1, opc2, opc3;
1235fc06 320#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 321 unsigned char pad[5];
322#else
323 unsigned char pad[1];
324#endif
79aceca5 325 opc_handler_t handler;
b55266b5 326 const char *oname;
79aceca5
FB		 327} opcode_t;
328
a750fc0b 329/*****************************************************************************/
79aceca5
FB		 330/*** Instruction decoding ***/
331#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 332static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 333{ \
334 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
335}
336
337#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 338static always_inline int32_t name (uint32_t opcode) \
79aceca5 339{ \
18fba28c 340 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 341}
342
343/* Opcode part 1 */
344EXTRACT_HELPER(opc1, 26, 6);
345/* Opcode part 2 */
346EXTRACT_HELPER(opc2, 1, 5);
347/* Opcode part 3 */
348EXTRACT_HELPER(opc3, 6, 5);
349/* Update Cr0 flags */
350EXTRACT_HELPER(Rc, 0, 1);
351/* Destination */
352EXTRACT_HELPER(rD, 21, 5);
353/* Source */
354EXTRACT_HELPER(rS, 21, 5);
355/* First operand */
356EXTRACT_HELPER(rA, 16, 5);
357/* Second operand */
358EXTRACT_HELPER(rB, 11, 5);
359/* Third operand */
360EXTRACT_HELPER(rC, 6, 5);
361/*** Get CRn ***/
362EXTRACT_HELPER(crfD, 23, 3);
363EXTRACT_HELPER(crfS, 18, 3);
364EXTRACT_HELPER(crbD, 21, 5);
365EXTRACT_HELPER(crbA, 16, 5);
366EXTRACT_HELPER(crbB, 11, 5);
367/* SPR / TBL */
3fc6c082 368EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 369static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 370{
371 uint32_t sprn = _SPR(opcode);
372
373 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
374}
79aceca5
FB		 375/*** Get constants ***/
376EXTRACT_HELPER(IMM, 12, 8);
377/* 16 bits signed immediate value */
378EXTRACT_SHELPER(SIMM, 0, 16);
379/* 16 bits unsigned immediate value */
380EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 381/* 5 bits signed immediate value */
382EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 383/* 5 bits signed immediate value */
384EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 385/* Bit count */
386EXTRACT_HELPER(NB, 11, 5);
387/* Shift count */
388EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 389/* Vector shift count */
390EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 391/* Mask start */
392EXTRACT_HELPER(MB, 6, 5);
393/* Mask end */
394EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 395/* Trap operand */
396EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 397
398EXTRACT_HELPER(CRM, 12, 8);
399EXTRACT_HELPER(FM, 17, 8);
400EXTRACT_HELPER(SR, 16, 4);
e4bb997e 401EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 402
79aceca5
FB		 403/*** Jump target decoding ***/
404/* Displacement */
405EXTRACT_SHELPER(d, 0, 16);
406/* Immediate address */
b068d6a7 407static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 408{
409 return (opcode >> 0) & 0x03FFFFFC;
410}
411
b068d6a7 412static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 413{
414 return (opcode >> 0) & 0xFFFC;
415}
416
417EXTRACT_HELPER(BO, 21, 5);
418EXTRACT_HELPER(BI, 16, 5);
419/* Absolute/relative address */
420EXTRACT_HELPER(AA, 1, 1);
421/* Link */
422EXTRACT_HELPER(LK, 0, 1);
423
424/* Create a mask between <start> and <end> bits */
b068d6a7 425static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 426{
76a66253 427 target_ulong ret;
79aceca5 428
76a66253
JM		 429#if defined(TARGET_PPC64)
430 if (likely(start == 0)) {
6f2d8978 431 ret = UINT64_MAX << (63 - end);
76a66253 432 } else if (likely(end == 63)) {
6f2d8978 433 ret = UINT64_MAX >> start;
76a66253
JM		 434 }
435#else
436 if (likely(start == 0)) {
6f2d8978 437 ret = UINT32_MAX << (31 - end);
76a66253 438 } else if (likely(end == 31)) {
6f2d8978 439 ret = UINT32_MAX >> start;
76a66253
JM		 440 }
441#endif
442 else {
443 ret = (((target_ulong)(-1ULL)) >> (start)) ^
444 (((target_ulong)(-1ULL) >> (end)) >> 1);
445 if (unlikely(start > end))
446 return ~ret;
447 }
79aceca5
FB		 448
449 return ret;
450}
451
a750fc0b
JM		 452/*****************************************************************************/
453/* PowerPC Instructions types definitions */
454enum {
1b413d55 455 PPC_NONE = 0x0000000000000000ULL,
12de9a39 456 /* PowerPC base instructions set */
1b413d55
JM		 457 PPC_INSNS_BASE = 0x0000000000000001ULL,
458 /* integer operations instructions */
a750fc0b 459#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 460 /* flow control instructions */
a750fc0b 461#define PPC_FLOW PPC_INSNS_BASE
1b413d55 462 /* virtual memory instructions */
a750fc0b 463#define PPC_MEM PPC_INSNS_BASE
1b413d55 464 /* ld/st with reservation instructions */
a750fc0b 465#define PPC_RES PPC_INSNS_BASE
1b413d55 466 /* spr/msr access instructions */
a750fc0b 467#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 468 /* Deprecated instruction sets */
469 /* Original POWER instruction set */
f610349f 470 PPC_POWER = 0x0000000000000002ULL,
1b413d55 471 /* POWER2 instruction set extension */
f610349f 472 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 473 /* Power RTC support */
f610349f 474 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 475 /* Power-to-PowerPC bridge (601) */
f610349f 476 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 477 /* 64 bits PowerPC instruction set */
f610349f 478 PPC_64B = 0x0000000000000020ULL,
1b413d55 479 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 480 PPC_64BX = 0x0000000000000040ULL,
1b413d55 481 /* 64 bits hypervisor extensions */
f610349f 482 PPC_64H = 0x0000000000000080ULL,
1b413d55 483 /* New wait instruction (PowerPC 2.0x) */
f610349f 484 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 485 /* Time base mftb instruction */
f610349f 486 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 487
488 /* Fixed-point unit extensions */
489 /* PowerPC 602 specific */
f610349f 490 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 491 /* isel instruction */
492 PPC_ISEL = 0x0000000000000800ULL,
493 /* popcntb instruction */
494 PPC_POPCNTB = 0x0000000000001000ULL,
495 /* string load / store */
496 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 497
498 /* Floating-point unit extensions */
499 /* Optional floating point instructions */
500 PPC_FLOAT = 0x0000000000010000ULL,
501 /* New floating-point extensions (PowerPC 2.0x) */
502 PPC_FLOAT_EXT = 0x0000000000020000ULL,
503 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
504 PPC_FLOAT_FRES = 0x0000000000080000ULL,
505 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
506 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
507 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
508 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
509
510 /* Vector/SIMD extensions */
511 /* Altivec support */
512 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 513 /* PowerPC 2.03 SPE extension */
05332d70 514 PPC_SPE = 0x0000000002000000ULL,
40569b7e
AJ		 515 /* PowerPC 2.03 SPE single-precision floating-point extension */
516 PPC_SPE_SINGLE = 0x0000000004000000ULL,
517 /* PowerPC 2.03 SPE double-precision floating-point extension */
518 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1b413d55 519
12de9a39 520 /* Optional memory control instructions */
1b413d55
JM		 521 PPC_MEM_TLBIA = 0x0000000010000000ULL,
522 PPC_MEM_TLBIE = 0x0000000020000000ULL,
523 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
524 /* sync instruction */
525 PPC_MEM_SYNC = 0x0000000080000000ULL,
526 /* eieio instruction */
527 PPC_MEM_EIEIO = 0x0000000100000000ULL,
528
529 /* Cache control instructions */
c8623f2e 530 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 531 /* icbi instruction */
05332d70 532 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 533 /* dcbz instruction with fixed cache line size */
05332d70 534 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 535 /* dcbz instruction with tunable cache line size */
05332d70 536 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 537 /* dcba instruction */
05332d70
JM		 538 PPC_CACHE_DCBA = 0x0000002000000000ULL,
539 /* Freescale cache locking instructions */
540 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 541
542 /* MMU related extensions */
543 /* external control instructions */
05332d70 544 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 545 /* segment register access instructions */
05332d70 546 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 547 /* PowerPC 6xx TLB management instructions */
05332d70 548 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 549 /* PowerPC 74xx TLB management instructions */
05332d70 550 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 551 /* PowerPC 40x TLB management instructions */
05332d70 552 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 553 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 554 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 555 /* SLB management */
05332d70 556 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 557
12de9a39 558 /* Embedded PowerPC dedicated instructions */
05332d70 559 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 560 /* PowerPC 40x exception model */
05332d70 561 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 562 /* PowerPC 405 Mac instructions */
05332d70 563 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 564 /* PowerPC 440 specific instructions */
05332d70 565 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 566 /* BookE (embedded) PowerPC specification */
05332d70
JM		 567 PPC_BOOKE = 0x0010000000000000ULL,
568 /* mfapidi instruction */
569 PPC_MFAPIDI = 0x0020000000000000ULL,
570 /* tlbiva instruction */
571 PPC_TLBIVA = 0x0040000000000000ULL,
572 /* tlbivax instruction */
573 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 574 /* PowerPC 4xx dedicated instructions */
05332d70 575 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 576 /* PowerPC 40x ibct instructions */
05332d70 577 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 578 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 579 PPC_RFMCI = 0x0400000000000000ULL,
580 /* rfdi instruction */
581 PPC_RFDI = 0x0800000000000000ULL,
582 /* DCR accesses */
583 PPC_DCR = 0x1000000000000000ULL,
584 /* DCR extended accesse */
585 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 586 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 587 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 588};
589
590/*****************************************************************************/
591/* PowerPC instructions table */
3fc6c082
FB		 592#if HOST_LONG_BITS == 64
593#define OPC_ALIGN 8
594#else
595#define OPC_ALIGN 4
596#endif
1b039c09 597#if defined(__APPLE__)
d9bce9d9 598#define OPCODES_SECTION \
3fc6c082 599 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 600#else
d9bce9d9 601#define OPCODES_SECTION \
3fc6c082 602 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 603#endif
604
76a66253 605#if defined(DO_PPC_STATISTICS)
79aceca5 606#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
50773fd2 607extern opcode_t opc_##name; \
18fba28c 608OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 609 .opc1 = op1, \
610 .opc2 = op2, \
611 .opc3 = op3, \
18fba28c 612 .pad = { 0, }, \
79aceca5
FB		 613 .handler = { \
614 .inval = invl, \
9a64fbe4 615 .type = _typ, \
79aceca5 616 .handler = &gen_##name, \
76a66253 617 .oname = stringify(name), \
79aceca5 618 }, \
3fc6c082 619 .oname = stringify(name), \
79aceca5 620}
c7697e1f
JM		 621#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
622OPCODES_SECTION opcode_t opc_##name = { \
623 .opc1 = op1, \
624 .opc2 = op2, \
625 .opc3 = op3, \
626 .pad = { 0, }, \
627 .handler = { \
628 .inval = invl, \
629 .type = _typ, \
630 .handler = &gen_##name, \
631 .oname = onam, \
632 }, \
633 .oname = onam, \
634}
76a66253
JM		 635#else
636#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
50773fd2 637extern opcode_t opc_##name; \
76a66253
JM		 638OPCODES_SECTION opcode_t opc_##name = { \
639 .opc1 = op1, \
640 .opc2 = op2, \
641 .opc3 = op3, \
642 .pad = { 0, }, \
643 .handler = { \
644 .inval = invl, \
645 .type = _typ, \
646 .handler = &gen_##name, \
647 }, \
648 .oname = stringify(name), \
649}
c7697e1f 650#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
50773fd2 651extern opcode_t opc_##name; \
c7697e1f
JM		 652OPCODES_SECTION opcode_t opc_##name = { \
653 .opc1 = op1, \
654 .opc2 = op2, \
655 .opc3 = op3, \
656 .pad = { 0, }, \
657 .handler = { \
658 .inval = invl, \
659 .type = _typ, \
660 .handler = &gen_##name, \
661 }, \
662 .oname = onam, \
663}
76a66253 664#endif
79aceca5
FB		 665
666#define GEN_OPCODE_MARK(name) \
50773fd2 667extern opcode_t opc_##name; \
18fba28c 668OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 669 .opc1 = 0xFF, \
670 .opc2 = 0xFF, \
671 .opc3 = 0xFF, \
18fba28c 672 .pad = { 0, }, \
79aceca5
FB		 673 .handler = { \
674 .inval = 0x00000000, \
9a64fbe4 675 .type = 0x00, \
79aceca5
FB		 676 .handler = NULL, \
677 }, \
3fc6c082 678 .oname = stringify(name), \
79aceca5
FB		 679}
680
54cdcae6
AJ		 681/* SPR load/store helpers */
682static always_inline void gen_load_spr(TCGv t, int reg)
683{
684 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
685}
686
687static always_inline void gen_store_spr(int reg, TCGv t)
688{
689 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
690}
691
79aceca5
FB		 692/* Start opcode list */
693GEN_OPCODE_MARK(start);
694
695/* Invalid instruction */
9a64fbe4
FB		 696GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
697{
e06fcd75 698 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 699}
700
79aceca5
FB		 701static opc_handler_t invalid_handler = {
702 .inval = 0xFFFFFFFF,
9a64fbe4 703 .type = PPC_NONE,
79aceca5
FB		 704 .handler = gen_invalid,
705};
706
e1571908
AJ		 707/*** Integer comparison ***/
708
ea363694 709static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 710{
711 int l1, l2, l3;
712
269f3e95
AJ		 713 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
714 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 715 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
716
717 l1 = gen_new_label();
718 l2 = gen_new_label();
719 l3 = gen_new_label();
720 if (s) {
ea363694
AJ		 721 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 723 } else {
ea363694
AJ		 724 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
725 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 726 }
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
728 tcg_gen_br(l3);
729 gen_set_label(l1);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
731 tcg_gen_br(l3);
732 gen_set_label(l2);
733 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
734 gen_set_label(l3);
735}
736
ea363694 737static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 738{
ea363694
AJ		 739 TCGv t0 = tcg_const_local_tl(arg1);
740 gen_op_cmp(arg0, t0, s, crf);
741 tcg_temp_free(t0);
e1571908
AJ		 742}
743
744#if defined(TARGET_PPC64)
ea363694 745static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 746{
ea363694 747 TCGv t0, t1;
a7812ae4
PB		 748 t0 = tcg_temp_local_new();
749 t1 = tcg_temp_local_new();
e1571908 750 if (s) {
ea363694
AJ		 751 tcg_gen_ext32s_tl(t0, arg0);
752 tcg_gen_ext32s_tl(t1, arg1);
e1571908 753 } else {
ea363694
AJ		 754 tcg_gen_ext32u_tl(t0, arg0);
755 tcg_gen_ext32u_tl(t1, arg1);
e1571908 756 }
ea363694
AJ		 757 gen_op_cmp(t0, t1, s, crf);
758 tcg_temp_free(t1);
759 tcg_temp_free(t0);
e1571908
AJ		 760}
761
ea363694 762static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 763{
ea363694
AJ		 764 TCGv t0 = tcg_const_local_tl(arg1);
765 gen_op_cmp32(arg0, t0, s, crf);
766 tcg_temp_free(t0);
e1571908
AJ		 767}
768#endif
769
770static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
771{
772#if defined(TARGET_PPC64)
773 if (!(ctx->sf_mode))
774 gen_op_cmpi32(reg, 0, 1, 0);
775 else
776#endif
777 gen_op_cmpi(reg, 0, 1, 0);
778}
779
780/* cmp */
781GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
782{
783#if defined(TARGET_PPC64)
784 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
785 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787 else
788#endif
789 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
790 1, crfD(ctx->opcode));
791}
792
793/* cmpi */
794GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
795{
796#if defined(TARGET_PPC64)
797 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
798 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800 else
801#endif
802 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
803 1, crfD(ctx->opcode));
804}
805
806/* cmpl */
807GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
808{
809#if defined(TARGET_PPC64)
810 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
811 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813 else
814#endif
815 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
816 0, crfD(ctx->opcode));
817}
818
819/* cmpli */
820GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
821{
822#if defined(TARGET_PPC64)
823 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
824 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826 else
827#endif
828 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
829 0, crfD(ctx->opcode));
830}
831
832/* isel (PowerPC 2.03 specification) */
833GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
834{
835 int l1, l2;
836 uint32_t bi = rC(ctx->opcode);
837 uint32_t mask;
a7812ae4 838 TCGv_i32 t0;
e1571908
AJ		 839
840 l1 = gen_new_label();
841 l2 = gen_new_label();
842
843 mask = 1 << (3 - (bi & 0x03));
a7812ae4 844 t0 = tcg_temp_new_i32();
fea0c503
AJ		 845 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
846 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 847 if (rA(ctx->opcode) == 0)
848 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
849 else
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
851 tcg_gen_br(l2);
852 gen_set_label(l1);
853 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
854 gen_set_label(l2);
a7812ae4 855 tcg_temp_free_i32(t0);
e1571908
AJ		 856}
857
79aceca5 858/*** Integer arithmetic ***/
79aceca5 859
74637406
AJ		 860static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
861{
862 int l1;
863 TCGv t0;
79aceca5 864
74637406
AJ		 865 l1 = gen_new_label();
866 /* Start with XER OV disabled, the most likely case */
867 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 868 t0 = tcg_temp_local_new();
74637406
AJ		 869 tcg_gen_xor_tl(t0, arg0, arg1);
870#if defined(TARGET_PPC64)
871 if (!ctx->sf_mode)
872 tcg_gen_ext32s_tl(t0, t0);
873#endif
874 if (sub)
875 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
876 else
877 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
878 tcg_gen_xor_tl(t0, arg1, arg2);
879#if defined(TARGET_PPC64)
880 if (!ctx->sf_mode)
881 tcg_gen_ext32s_tl(t0, t0);
882#endif
883 if (sub)
884 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
885 else
886 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
887 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
888 gen_set_label(l1);
889 tcg_temp_free(t0);
79aceca5
FB		 890}
891
74637406
AJ		 892static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
893{
894 int l1 = gen_new_label();
d9bce9d9
JM		 895
896#if defined(TARGET_PPC64)
74637406
AJ		 897 if (!(ctx->sf_mode)) {
898 TCGv t0, t1;
a7812ae4
PB		 899 t0 = tcg_temp_new();
900 t1 = tcg_temp_new();
d9bce9d9 901
74637406
AJ		 902 tcg_gen_ext32u_tl(t0, arg1);
903 tcg_gen_ext32u_tl(t1, arg2);
904 if (sub) {
905 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 906 } else {
74637406
AJ		 907 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
908 }
a9730017
AJ		 909 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
910 gen_set_label(l1);
911 tcg_temp_free(t0);
912 tcg_temp_free(t1);
74637406
AJ		 913 } else
914#endif
a9730017
AJ		 915 {
916 if (sub) {
917 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
918 } else {
919 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
920 }
921 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
922 gen_set_label(l1);
74637406 923 }
d9bce9d9
JM		 924}
925
74637406
AJ		 926/* Common add function */
927static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
928 int add_ca, int compute_ca, int compute_ov)
929{
930 TCGv t0, t1;
d9bce9d9 931
74637406 932 if ((!compute_ca && !compute_ov) ||
a7812ae4 933 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 934 t0 = ret;
935 } else {
a7812ae4 936 t0 = tcg_temp_local_new();
74637406 937 }
79aceca5 938
74637406 939 if (add_ca) {
a7812ae4 940 t1 = tcg_temp_local_new();
74637406
AJ		 941 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
942 tcg_gen_shri_tl(t1, t1, XER_CA);
943 }
79aceca5 944
74637406
AJ		 945 if (compute_ca && compute_ov) {
946 /* Start with XER CA and OV disabled, the most likely case */
947 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
948 } else if (compute_ca) {
949 /* Start with XER CA disabled, the most likely case */
950 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
951 } else if (compute_ov) {
952 /* Start with XER OV disabled, the most likely case */
953 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
954 }
79aceca5 955
74637406
AJ		 956 tcg_gen_add_tl(t0, arg1, arg2);
957
958 if (compute_ca) {
959 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
960 }
961 if (add_ca) {
962 tcg_gen_add_tl(t0, t0, t1);
963 gen_op_arith_compute_ca(ctx, t0, t1, 0);
964 tcg_temp_free(t1);
965 }
966 if (compute_ov) {
967 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
968 }
969
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, t0);
972
a7812ae4 973 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 974 tcg_gen_mov_tl(ret, t0);
975 tcg_temp_free(t0);
976 }
39dd32ee 977}
74637406
AJ		 978/* Add functions with two operands */
979#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
980GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
981{ \
982 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 add_ca, compute_ca, compute_ov); \
985}
986/* Add functions with one operand and one immediate */
987#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
988 add_ca, compute_ca, compute_ov) \
989GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
990{ \
991 TCGv t0 = tcg_const_local_tl(const_val); \
992 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], t0, \
994 add_ca, compute_ca, compute_ov); \
995 tcg_temp_free(t0); \
996}
997
998/* add add. addo addo. */
999GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1000GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1001/* addc addc. addco addco. */
1002GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1003GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1004/* adde adde. addeo addeo. */
1005GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1006GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1007/* addme addme. addmeo addmeo. */
1008GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1009GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1010/* addze addze. addzeo addzeo.*/
1011GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1012GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1013/* addi */
1014GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1015{
74637406
AJ		 1016 target_long simm = SIMM(ctx->opcode);
1017
1018 if (rA(ctx->opcode) == 0) {
1019 /* li case */
1020 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1021 } else {
1022 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1023 }
d9bce9d9 1024}
74637406
AJ		 1025/* addic addic.*/
1026static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1027 int compute_Rc0)
d9bce9d9 1028{
74637406
AJ		 1029 target_long simm = SIMM(ctx->opcode);
1030
1031 /* Start with XER CA and OV disabled, the most likely case */
1032 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1033
1034 if (likely(simm != 0)) {
a7812ae4 1035 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1036 tcg_gen_addi_tl(t0, arg1, simm);
1037 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1038 tcg_gen_mov_tl(ret, t0);
1039 tcg_temp_free(t0);
1040 } else {
1041 tcg_gen_mov_tl(ret, arg1);
1042 }
1043 if (compute_Rc0) {
1044 gen_set_Rc0(ctx, ret);
1045 }
d9bce9d9 1046}
74637406 1047GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1048{
74637406 1049 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1050}
74637406 1051GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1052{
74637406 1053 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1054}
74637406
AJ		 1055/* addis */
1056GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1057{
74637406
AJ		 1058 target_long simm = SIMM(ctx->opcode);
1059
1060 if (rA(ctx->opcode) == 0) {
1061 /* lis case */
1062 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1063 } else {
1064 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1065 }
d9bce9d9 1066}
74637406
AJ		 1067
1068static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1069 int sign, int compute_ov)
d9bce9d9 1070{
2ef1b120
AJ		 1071 int l1 = gen_new_label();
1072 int l2 = gen_new_label();
a7812ae4
PB		 1073 TCGv_i32 t0 = tcg_temp_local_new_i32();
1074 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1075
2ef1b120
AJ		 1076 tcg_gen_trunc_tl_i32(t0, arg1);
1077 tcg_gen_trunc_tl_i32(t1, arg2);
1078 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1079 if (sign) {
2ef1b120
AJ		 1080 int l3 = gen_new_label();
1081 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1082 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1083 gen_set_label(l3);
2ef1b120 1084 tcg_gen_div_i32(t0, t0, t1);
74637406 1085 } else {
2ef1b120 1086 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1087 }
1088 if (compute_ov) {
1089 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1090 }
1091 tcg_gen_br(l2);
1092 gen_set_label(l1);
1093 if (sign) {
2ef1b120 1094 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1095 } else {
1096 tcg_gen_movi_i32(t0, 0);
1097 }
1098 if (compute_ov) {
1099 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1100 }
1101 gen_set_label(l2);
2ef1b120 1102 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1103 tcg_temp_free_i32(t0);
1104 tcg_temp_free_i32(t1);
74637406
AJ		 1105 if (unlikely(Rc(ctx->opcode) != 0))
1106 gen_set_Rc0(ctx, ret);
d9bce9d9 1107}
74637406
AJ		 1108/* Div functions */
1109#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1110GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1111{ \
1112 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1114 sign, compute_ov); \
1115}
1116/* divwu divwu. divwuo divwuo. */
1117GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1118GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1119/* divw divw. divwo divwo. */
1120GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1121GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1122#if defined(TARGET_PPC64)
2ef1b120
AJ		 1123static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1124 int sign, int compute_ov)
d9bce9d9 1125{
2ef1b120
AJ		 1126 int l1 = gen_new_label();
1127 int l2 = gen_new_label();
74637406
AJ		 1128
1129 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1130 if (sign) {
2ef1b120 1131 int l3 = gen_new_label();
74637406
AJ		 1132 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1133 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1134 gen_set_label(l3);
74637406
AJ		 1135 tcg_gen_div_i64(ret, arg1, arg2);
1136 } else {
1137 tcg_gen_divu_i64(ret, arg1, arg2);
1138 }
1139 if (compute_ov) {
1140 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1141 }
1142 tcg_gen_br(l2);
1143 gen_set_label(l1);
1144 if (sign) {
1145 tcg_gen_sari_i64(ret, arg1, 63);
1146 } else {
1147 tcg_gen_movi_i64(ret, 0);
1148 }
1149 if (compute_ov) {
1150 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1151 }
1152 gen_set_label(l2);
1153 if (unlikely(Rc(ctx->opcode) != 0))
1154 gen_set_Rc0(ctx, ret);
d9bce9d9 1155}
74637406
AJ		 1156#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1157GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1158{ \
2ef1b120
AJ		 1159 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 sign, compute_ov); \
74637406
AJ		 1162}
1163/* divwu divwu. divwuo divwuo. */
1164GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1165GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1166/* divw divw. divwo divwo. */
1167GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1168GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1169#endif
74637406
AJ		 1170
1171/* mulhw mulhw. */
1172GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1173{
a7812ae4 1174 TCGv_i64 t0, t1;
74637406 1175
a7812ae4
PB		 1176 t0 = tcg_temp_new_i64();
1177 t1 = tcg_temp_new_i64();
74637406
AJ		 1178#if defined(TARGET_PPC64)
1179 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1183#else
1184 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1185 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1186 tcg_gen_mul_i64(t0, t0, t1);
1187 tcg_gen_shri_i64(t0, t0, 32);
1188 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1189#endif
a7812ae4
PB		 1190 tcg_temp_free_i64(t0);
1191 tcg_temp_free_i64(t1);
74637406
AJ		 1192 if (unlikely(Rc(ctx->opcode) != 0))
1193 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1194}
74637406
AJ		 1195/* mulhwu mulhwu. */
1196GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1197{
a7812ae4 1198 TCGv_i64 t0, t1;
74637406 1199
a7812ae4
PB		 1200 t0 = tcg_temp_new_i64();
1201 t1 = tcg_temp_new_i64();
d9bce9d9 1202#if defined(TARGET_PPC64)
74637406
AJ		 1203 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1207#else
1208 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1209 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1210 tcg_gen_mul_i64(t0, t0, t1);
1211 tcg_gen_shri_i64(t0, t0, 32);
1212 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1213#endif
a7812ae4
PB		 1214 tcg_temp_free_i64(t0);
1215 tcg_temp_free_i64(t1);
74637406
AJ		 1216 if (unlikely(Rc(ctx->opcode) != 0))
1217 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1218}
74637406
AJ		 1219/* mullw mullw. */
1220GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1221{
74637406
AJ		 1222 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1223 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1224 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1227}
74637406
AJ		 1228/* mullwo mullwo. */
1229GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1230{
74637406 1231 int l1;
a7812ae4 1232 TCGv_i64 t0, t1;
74637406 1233
a7812ae4
PB		 1234 t0 = tcg_temp_new_i64();
1235 t1 = tcg_temp_new_i64();
74637406
AJ		 1236 l1 = gen_new_label();
1237 /* Start with XER OV disabled, the most likely case */
1238 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1239#if defined(TARGET_PPC64)
1240 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1241 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1242#else
1243 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1244 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1245#endif
74637406
AJ		 1246 tcg_gen_mul_i64(t0, t0, t1);
1247#if defined(TARGET_PPC64)
1248 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1249 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1250#else
1251 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1252 tcg_gen_ext32s_i64(t1, t0);
1253 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1254#endif
1255 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1256 gen_set_label(l1);
a7812ae4
PB		 1257 tcg_temp_free_i64(t0);
1258 tcg_temp_free_i64(t1);
74637406
AJ		 1259 if (unlikely(Rc(ctx->opcode) != 0))
1260 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1261}
74637406
AJ		 1262/* mulli */
1263GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1264{
74637406
AJ		 1265 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1266 SIMM(ctx->opcode));
d9bce9d9
JM		 1267}
1268#if defined(TARGET_PPC64)
74637406
AJ		 1269#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1270GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1271{ \
a7812ae4 1272 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1274 if (unlikely(Rc(ctx->opcode) != 0)) \
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1276}
74637406
AJ		 1277/* mulhd mulhd. */
1278GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1279/* mulhdu mulhdu. */
1280GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1281/* mulld mulld. */
1282GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1283{
74637406
AJ		 1284 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1285 cpu_gpr[rB(ctx->opcode)]);
1286 if (unlikely(Rc(ctx->opcode) != 0))
1287 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1288}
74637406
AJ		 1289/* mulldo mulldo. */
1290GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1291#endif
74637406
AJ		 1292
1293/* neg neg. nego nego. */
ec6469a3 1294static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1295{
ec6469a3
AJ		 1296 int l1 = gen_new_label();
1297 int l2 = gen_new_label();
a7812ae4 1298 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1299#if defined(TARGET_PPC64)
74637406 1300 if (ctx->sf_mode) {
741a7444 1301 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1303 } else
1304#endif
1305 {
1306 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1307 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1308 }
74637406
AJ		 1309 tcg_gen_neg_tl(ret, arg1);
1310 if (ov_check) {
1311 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1312 }
1313 tcg_gen_br(l2);
1314 gen_set_label(l1);
ec6469a3 1315 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1316 if (ov_check) {
1317 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1318 }
1319 gen_set_label(l2);
ec6469a3 1320 tcg_temp_free(t0);
74637406
AJ		 1321 if (unlikely(Rc(ctx->opcode) != 0))
1322 gen_set_Rc0(ctx, ret);
1323}
1324GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1325{
ec6469a3 1326 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1327}
74637406 1328GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1329{
ec6469a3 1330 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1331}
74637406
AJ		 1332
1333/* Common subf function */
1334static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1335 int add_ca, int compute_ca, int compute_ov)
79aceca5 1336{
74637406 1337 TCGv t0, t1;
76a66253 1338
74637406 1339 if ((!compute_ca && !compute_ov) ||
a7812ae4 1340 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1341 t0 = ret;
e864cabd 1342 } else {
a7812ae4 1343 t0 = tcg_temp_local_new();
d9bce9d9 1344 }
76a66253 1345
74637406 1346 if (add_ca) {
a7812ae4 1347 t1 = tcg_temp_local_new();
74637406
AJ		 1348 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1349 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1350 }
79aceca5 1351
74637406
AJ		 1352 if (compute_ca && compute_ov) {
1353 /* Start with XER CA and OV disabled, the most likely case */
1354 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1355 } else if (compute_ca) {
1356 /* Start with XER CA disabled, the most likely case */
1357 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1358 } else if (compute_ov) {
1359 /* Start with XER OV disabled, the most likely case */
1360 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1361 }
1362
1363 if (add_ca) {
1364 tcg_gen_not_tl(t0, arg1);
1365 tcg_gen_add_tl(t0, t0, arg2);
1366 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1367 tcg_gen_add_tl(t0, t0, t1);
1368 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1369 tcg_temp_free(t1);
79aceca5 1370 } else {
74637406
AJ		 1371 tcg_gen_sub_tl(t0, arg2, arg1);
1372 if (compute_ca) {
1373 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1374 }
1375 }
1376 if (compute_ov) {
1377 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1378 }
1379
1380 if (unlikely(Rc(ctx->opcode) != 0))
1381 gen_set_Rc0(ctx, t0);
1382
a7812ae4 1383 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1384 tcg_gen_mov_tl(ret, t0);
1385 tcg_temp_free(t0);
79aceca5 1386 }
79aceca5 1387}
74637406
AJ		 1388/* Sub functions with Two operands functions */
1389#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1390GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1391{ \
1392 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1393 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1394 add_ca, compute_ca, compute_ov); \
1395}
1396/* Sub functions with one operand and one immediate */
1397#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1398 add_ca, compute_ca, compute_ov) \
1399GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1400{ \
1401 TCGv t0 = tcg_const_local_tl(const_val); \
1402 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1403 cpu_gpr[rA(ctx->opcode)], t0, \
1404 add_ca, compute_ca, compute_ov); \
1405 tcg_temp_free(t0); \
1406}
1407/* subf subf. subfo subfo. */
1408GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1409GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1410/* subfc subfc. subfco subfco. */
1411GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1412GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1413/* subfe subfe. subfeo subfo. */
1414GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1415GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1416/* subfme subfme. subfmeo subfmeo. */
1417GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1418GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1419/* subfze subfze. subfzeo subfzeo.*/
1420GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1421GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1422/* subfic */
1423GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1424{
74637406
AJ		 1425 /* Start with XER CA and OV disabled, the most likely case */
1426 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1427 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1428 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1429 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1430 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1431 tcg_temp_free(t1);
1432 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1433 tcg_temp_free(t0);
79aceca5
FB		 1434}
1435
79aceca5 1436/*** Integer logical ***/
26d67362
AJ		 1437#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1438GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1439{ \
26d67362
AJ		 1440 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1441 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1442 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1443 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1444}
79aceca5 1445
26d67362 1446#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1447GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1448{ \
26d67362 1449 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1450 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1451 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1452}
1453
1454/* and & and. */
26d67362 1455GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1456/* andc & andc. */
26d67362 1457GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1458/* andi. */
c7697e1f 1459GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1460{
26d67362
AJ		 1461 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1463}
1464/* andis. */
c7697e1f 1465GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1466{
26d67362
AJ		 1467 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1469}
79aceca5 1470/* cntlzw */
26d67362
AJ		 1471GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1472{
a7812ae4 1473 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1474 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1475 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1476}
79aceca5 1477/* eqv & eqv. */
26d67362 1478GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1479/* extsb & extsb. */
26d67362 1480GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1481/* extsh & extsh. */
26d67362 1482GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1483/* nand & nand. */
26d67362 1484GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1485/* nor & nor. */
26d67362 1486GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1487/* or & or. */
9a64fbe4
FB		 1488GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1489{
76a66253
JM		 1490 int rs, ra, rb;
1491
1492 rs = rS(ctx->opcode);
1493 ra = rA(ctx->opcode);
1494 rb = rB(ctx->opcode);
1495 /* Optimisation for mr. ri case */
1496 if (rs != ra || rs != rb) {
26d67362
AJ		 1497 if (rs != rb)
1498 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1499 else
1500 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1501 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1502 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1503 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1504 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1505#if defined(TARGET_PPC64)
1506 } else {
26d67362
AJ		 1507 int prio = 0;
1508
c80f84e3
JM		 1509 switch (rs) {
1510 case 1:
1511 /* Set process priority to low */
26d67362 1512 prio = 2;
c80f84e3
JM		 1513 break;
1514 case 6:
1515 /* Set process priority to medium-low */
26d67362 1516 prio = 3;
c80f84e3
JM		 1517 break;
1518 case 2:
1519 /* Set process priority to normal */
26d67362 1520 prio = 4;
c80f84e3 1521 break;
be147d08
JM		 1522#if !defined(CONFIG_USER_ONLY)
1523 case 31:
76db3ba4 1524 if (ctx->mem_idx > 0) {
be147d08 1525 /* Set process priority to very low */
26d67362 1526 prio = 1;
be147d08
JM		 1527 }
1528 break;
1529 case 5:
76db3ba4 1530 if (ctx->mem_idx > 0) {
be147d08 1531 /* Set process priority to medium-hight */
26d67362 1532 prio = 5;
be147d08
JM		 1533 }
1534 break;
1535 case 3:
76db3ba4 1536 if (ctx->mem_idx > 0) {
be147d08 1537 /* Set process priority to high */
26d67362 1538 prio = 6;
be147d08
JM		 1539 }
1540 break;
be147d08 1541 case 7:
76db3ba4 1542 if (ctx->mem_idx > 1) {
be147d08 1543 /* Set process priority to very high */
26d67362 1544 prio = 7;
be147d08
JM		 1545 }
1546 break;
be147d08 1547#endif
c80f84e3
JM		 1548 default:
1549 /* nop */
1550 break;
1551 }
26d67362 1552 if (prio) {
a7812ae4 1553 TCGv t0 = tcg_temp_new();
54cdcae6 1554 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1555 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1556 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1557 gen_store_spr(SPR_PPR, t0);
ea363694 1558 tcg_temp_free(t0);
26d67362 1559 }
c80f84e3 1560#endif
9a64fbe4 1561 }
9a64fbe4 1562}
79aceca5 1563/* orc & orc. */
26d67362 1564GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1565/* xor & xor. */
9a64fbe4
FB		 1566GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1567{
9a64fbe4 1568 /* Optimisation for "set to zero" case */
26d67362 1569 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1570 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1571 else
1572 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1573 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1575}
79aceca5
FB		 1576/* ori */
1577GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1578{
76a66253 1579 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1580
9a64fbe4
FB		 1581 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1582 /* NOP */
76a66253 1583 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1584 return;
76a66253 1585 }
26d67362 1586 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1587}
1588/* oris */
1589GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1590{
76a66253 1591 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1592
9a64fbe4
FB		 1593 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1594 /* NOP */
1595 return;
76a66253 1596 }
26d67362 1597 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1598}
1599/* xori */
1600GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1601{
76a66253 1602 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1603
1604 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1605 /* NOP */
1606 return;
1607 }
26d67362 1608 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1609}
79aceca5
FB		 1610/* xoris */
1611GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1612{
76a66253 1613 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1614
1615 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1616 /* NOP */
1617 return;
1618 }
26d67362 1619 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1620}
d9bce9d9 1621/* popcntb : PowerPC 2.03 specification */
05332d70 1622GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1623{
d9bce9d9
JM		 1624#if defined(TARGET_PPC64)
1625 if (ctx->sf_mode)
a7812ae4 1626 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1627 else
1628#endif
a7812ae4 1629 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1630}
1631
1632#if defined(TARGET_PPC64)
1633/* extsw & extsw. */
26d67362 1634GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1635/* cntlzd */
26d67362
AJ		 1636GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1637{
a7812ae4 1638 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1639 if (unlikely(Rc(ctx->opcode) != 0))
1640 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1641}
d9bce9d9
JM		 1642#endif
1643
79aceca5
FB		 1644/*** Integer rotate ***/
1645/* rlwimi & rlwimi. */
1646GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1647{
76a66253 1648 uint32_t mb, me, sh;
79aceca5
FB		 1649
1650 mb = MB(ctx->opcode);
1651 me = ME(ctx->opcode);
76a66253 1652 sh = SH(ctx->opcode);
d03ef511
AJ		 1653 if (likely(sh == 0 && mb == 0 && me == 31)) {
1654 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1655 } else {
d03ef511 1656 target_ulong mask;
a7812ae4
PB		 1657 TCGv t1;
1658 TCGv t0 = tcg_temp_new();
54843a58 1659#if defined(TARGET_PPC64)
a7812ae4
PB		 1660 TCGv_i32 t2 = tcg_temp_new_i32();
1661 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1662 tcg_gen_rotli_i32(t2, t2, sh);
1663 tcg_gen_extu_i32_i64(t0, t2);
1664 tcg_temp_free_i32(t2);
54843a58
AJ		 1665#else
1666 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1667#endif
76a66253 1668#if defined(TARGET_PPC64)
d03ef511
AJ		 1669 mb += 32;
1670 me += 32;
76a66253 1671#endif
d03ef511 1672 mask = MASK(mb, me);
a7812ae4 1673 t1 = tcg_temp_new();
d03ef511
AJ		 1674 tcg_gen_andi_tl(t0, t0, mask);
1675 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1676 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1677 tcg_temp_free(t0);
1678 tcg_temp_free(t1);
1679 }
76a66253 1680 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1681 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1682}
1683/* rlwinm & rlwinm. */
1684GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1685{
1686 uint32_t mb, me, sh;
3b46e624 1687
79aceca5
FB		 1688 sh = SH(ctx->opcode);
1689 mb = MB(ctx->opcode);
1690 me = ME(ctx->opcode);
d03ef511
AJ		 1691
1692 if (likely(mb == 0 && me == (31 - sh))) {
1693 if (likely(sh == 0)) {
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1695 } else {
a7812ae4 1696 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1697 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1698 tcg_gen_shli_tl(t0, t0, sh);
1699 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1700 tcg_temp_free(t0);
79aceca5 1701 }
d03ef511 1702 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1703 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1704 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1705 tcg_gen_shri_tl(t0, t0, mb);
1706 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1707 tcg_temp_free(t0);
1708 } else {
a7812ae4 1709 TCGv t0 = tcg_temp_new();
54843a58 1710#if defined(TARGET_PPC64)
a7812ae4 1711 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1712 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1713 tcg_gen_rotli_i32(t1, t1, sh);
1714 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1715 tcg_temp_free_i32(t1);
54843a58
AJ		 1716#else
1717 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1718#endif
76a66253 1719#if defined(TARGET_PPC64)
d03ef511
AJ		 1720 mb += 32;
1721 me += 32;
76a66253 1722#endif
d03ef511
AJ		 1723 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1724 tcg_temp_free(t0);
1725 }
76a66253 1726 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1727 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1728}
1729/* rlwnm & rlwnm. */
1730GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1731{
1732 uint32_t mb, me;
54843a58
AJ		 1733 TCGv t0;
1734#if defined(TARGET_PPC64)
a7812ae4 1735 TCGv_i32 t1, t2;
54843a58 1736#endif
79aceca5
FB		 1737
1738 mb = MB(ctx->opcode);
1739 me = ME(ctx->opcode);
a7812ae4 1740 t0 = tcg_temp_new();
d03ef511 1741 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1742#if defined(TARGET_PPC64)
a7812ae4
PB		 1743 t1 = tcg_temp_new_i32();
1744 t2 = tcg_temp_new_i32();
54843a58
AJ		 1745 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1746 tcg_gen_trunc_i64_i32(t2, t0);
1747 tcg_gen_rotl_i32(t1, t1, t2);
1748 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1749 tcg_temp_free_i32(t1);
1750 tcg_temp_free_i32(t2);
54843a58
AJ		 1751#else
1752 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1753#endif
76a66253
JM		 1754 if (unlikely(mb != 0 || me != 31)) {
1755#if defined(TARGET_PPC64)
1756 mb += 32;
1757 me += 32;
1758#endif
54843a58 1759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1760 } else {
54843a58 1761 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1762 }
54843a58 1763 tcg_temp_free(t0);
76a66253 1764 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1765 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1766}
1767
d9bce9d9
JM		 1768#if defined(TARGET_PPC64)
1769#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1770GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1771{ \
1772 gen_##name(ctx, 0); \
1773} \
c7697e1f
JM		 1774GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1775 PPC_64B) \
d9bce9d9
JM		 1776{ \
1777 gen_##name(ctx, 1); \
1778}
1779#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1780GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1781{ \
1782 gen_##name(ctx, 0, 0); \
1783} \
c7697e1f
JM		 1784GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1785 PPC_64B) \
d9bce9d9
JM		 1786{ \
1787 gen_##name(ctx, 0, 1); \
1788} \
c7697e1f
JM		 1789GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1790 PPC_64B) \
d9bce9d9
JM		 1791{ \
1792 gen_##name(ctx, 1, 0); \
1793} \
c7697e1f
JM		 1794GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1795 PPC_64B) \
d9bce9d9
JM		 1796{ \
1797 gen_##name(ctx, 1, 1); \
1798}
51789c41 1799
b068d6a7
JM		 1800static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1801 uint32_t me, uint32_t sh)
51789c41 1802{
d03ef511
AJ		 1803 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1804 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1805 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1806 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1807 } else {
a7812ae4 1808 TCGv t0 = tcg_temp_new();
54843a58 1809 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1810 if (likely(mb == 0 && me == 63)) {
54843a58 1811 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1812 } else {
1813 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1814 }
d03ef511 1815 tcg_temp_free(t0);
51789c41 1816 }
51789c41 1817 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1819}
d9bce9d9 1820/* rldicl - rldicl. */
b068d6a7 1821static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1822{
51789c41 1823 uint32_t sh, mb;
d9bce9d9 1824
9d53c753
JM		 1825 sh = SH(ctx->opcode) | (shn << 5);
1826 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1827 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1828}
51789c41 1829GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1830/* rldicr - rldicr. */
b068d6a7 1831static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1832{
51789c41 1833 uint32_t sh, me;
d9bce9d9 1834
9d53c753
JM		 1835 sh = SH(ctx->opcode) | (shn << 5);
1836 me = MB(ctx->opcode) | (men << 5);
51789c41 1837 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1838}
51789c41 1839GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1840/* rldic - rldic. */
b068d6a7 1841static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1842{
51789c41 1843 uint32_t sh, mb;
d9bce9d9 1844
9d53c753
JM		 1845 sh = SH(ctx->opcode) | (shn << 5);
1846 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1847 gen_rldinm(ctx, mb, 63 - sh, sh);
1848}
1849GEN_PPC64_R4(rldic, 0x1E, 0x04);
1850
b068d6a7
JM		 1851static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1852 uint32_t me)
51789c41 1853{
54843a58 1854 TCGv t0;
d03ef511
AJ		 1855
1856 mb = MB(ctx->opcode);
1857 me = ME(ctx->opcode);
a7812ae4 1858 t0 = tcg_temp_new();
d03ef511 1859 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1860 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1861 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1862 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1863 } else {
1864 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1865 }
1866 tcg_temp_free(t0);
51789c41 1867 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1869}
51789c41 1870
d9bce9d9 1871/* rldcl - rldcl. */
b068d6a7 1872static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1873{
51789c41 1874 uint32_t mb;
d9bce9d9 1875
9d53c753 1876 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1877 gen_rldnm(ctx, mb, 63);
d9bce9d9 1878}
36081602 1879GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1880/* rldcr - rldcr. */
b068d6a7 1881static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1882{
51789c41 1883 uint32_t me;
d9bce9d9 1884
9d53c753 1885 me = MB(ctx->opcode) | (men << 5);
51789c41 1886 gen_rldnm(ctx, 0, me);
d9bce9d9 1887}
36081602 1888GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1889/* rldimi - rldimi. */
b068d6a7 1890static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1891{
271a916e 1892 uint32_t sh, mb, me;
d9bce9d9 1893
9d53c753
JM		 1894 sh = SH(ctx->opcode) | (shn << 5);
1895 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1896 me = 63 - sh;
d03ef511
AJ		 1897 if (unlikely(sh == 0 && mb == 0)) {
1898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1899 } else {
1900 TCGv t0, t1;
1901 target_ulong mask;
1902
a7812ae4 1903 t0 = tcg_temp_new();
54843a58 1904 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1905 t1 = tcg_temp_new();
d03ef511
AJ		 1906 mask = MASK(mb, me);
1907 tcg_gen_andi_tl(t0, t0, mask);
1908 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1909 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1910 tcg_temp_free(t0);
1911 tcg_temp_free(t1);
51789c41 1912 }
51789c41 1913 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1915}
36081602 1916GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1917#endif
1918
79aceca5
FB		 1919/*** Integer shift ***/
1920/* slw & slw. */
26d67362
AJ		 1921GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1922{
fea0c503 1923 TCGv t0;
26d67362
AJ		 1924 int l1, l2;
1925 l1 = gen_new_label();
1926 l2 = gen_new_label();
1927
a7812ae4 1928 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1929 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1930 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1931 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1932 tcg_gen_br(l2);
1933 gen_set_label(l1);
fea0c503 1934 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1935 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1936 gen_set_label(l2);
fea0c503 1937 tcg_temp_free(t0);
26d67362
AJ		 1938 if (unlikely(Rc(ctx->opcode) != 0))
1939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1940}
79aceca5 1941/* sraw & sraw. */
26d67362
AJ		 1942GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1943{
a7812ae4
PB		 1944 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1945 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1946 if (unlikely(Rc(ctx->opcode) != 0))
1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1948}
79aceca5
FB		 1949/* srawi & srawi. */
1950GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1951{
26d67362
AJ		 1952 int sh = SH(ctx->opcode);
1953 if (sh != 0) {
1954 int l1, l2;
fea0c503 1955 TCGv t0;
26d67362
AJ		 1956 l1 = gen_new_label();
1957 l2 = gen_new_label();
a7812ae4 1958 t0 = tcg_temp_local_new();
fea0c503
AJ		 1959 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1960 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1961 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1962 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1963 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1964 tcg_gen_br(l2);
1965 gen_set_label(l1);
269f3e95 1966 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1967 gen_set_label(l2);
fea0c503
AJ		 1968 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1969 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1970 tcg_temp_free(t0);
26d67362
AJ		 1971 } else {
1972 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1973 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1974 }
76a66253 1975 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1977}
1978/* srw & srw. */
26d67362
AJ		 1979GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1980{
fea0c503 1981 TCGv t0, t1;
26d67362
AJ		 1982 int l1, l2;
1983 l1 = gen_new_label();
1984 l2 = gen_new_label();
d9bce9d9 1985
a7812ae4 1986 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1987 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1988 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1989 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1990 tcg_gen_br(l2);
1991 gen_set_label(l1);
a7812ae4 1992 t1 = tcg_temp_new();
fea0c503
AJ		 1993 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1994 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1995 tcg_temp_free(t1);
26d67362 1996 gen_set_label(l2);
fea0c503 1997 tcg_temp_free(t0);
26d67362
AJ		 1998 if (unlikely(Rc(ctx->opcode) != 0))
1999 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2000}
d9bce9d9
JM		 2001#if defined(TARGET_PPC64)
2002/* sld & sld. */
26d67362
AJ		 2003GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2004{
fea0c503 2005 TCGv t0;
26d67362
AJ		 2006 int l1, l2;
2007 l1 = gen_new_label();
2008 l2 = gen_new_label();
2009
a7812ae4 2010 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2011 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2012 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2013 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2014 tcg_gen_br(l2);
2015 gen_set_label(l1);
fea0c503 2016 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2017 gen_set_label(l2);
fea0c503 2018 tcg_temp_free(t0);
26d67362
AJ		 2019 if (unlikely(Rc(ctx->opcode) != 0))
2020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2021}
d9bce9d9 2022/* srad & srad. */
26d67362
AJ		 2023GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2024{
a7812ae4
PB		 2025 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2026 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029}
d9bce9d9 2030/* sradi & sradi. */
b068d6a7 2031static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2032{
26d67362 2033 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2034 if (sh != 0) {
26d67362 2035 int l1, l2;
fea0c503 2036 TCGv t0;
26d67362
AJ		 2037 l1 = gen_new_label();
2038 l2 = gen_new_label();
a7812ae4 2039 t0 = tcg_temp_local_new();
26d67362 2040 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2041 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2042 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2043 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2044 tcg_gen_br(l2);
2045 gen_set_label(l1);
269f3e95 2046 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2047 gen_set_label(l2);
a9730017 2048 tcg_temp_free(t0);
26d67362
AJ		 2049 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2050 } else {
2051 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2052 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2053 }
d9bce9d9 2054 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2056}
c7697e1f 2057GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2058{
2059 gen_sradi(ctx, 0);
2060}
c7697e1f 2061GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2062{
2063 gen_sradi(ctx, 1);
2064}
2065/* srd & srd. */
26d67362
AJ		 2066GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2067{
fea0c503 2068 TCGv t0;
26d67362
AJ		 2069 int l1, l2;
2070 l1 = gen_new_label();
2071 l2 = gen_new_label();
2072
a7812ae4 2073 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2074 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2075 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2076 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2077 tcg_gen_br(l2);
2078 gen_set_label(l1);
fea0c503 2079 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2080 gen_set_label(l2);
fea0c503 2081 tcg_temp_free(t0);
26d67362
AJ		 2082 if (unlikely(Rc(ctx->opcode) != 0))
2083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2084}
d9bce9d9 2085#endif
79aceca5
FB		 2086
2087/*** Floating-Point arithmetic ***/
7c58044c 2088#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2089GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2090{ \
76a66253 2091 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2092 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2093 return; \
2094 } \
eb44b959
AJ		 2095 /* NIP cannot be restored if the memory exception comes from an helper */ \
2096 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2097 gen_reset_fpstatus(); \
af12906f
AJ		 2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2100 if (isfloat) { \
af12906f 2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2102 } \
af12906f
AJ		 2103 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2104 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2105}
2106
7c58044c
JM		 2107#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2108_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2109_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2110
7c58044c
JM		 2111#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2112GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2113{ \
76a66253 2114 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2115 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2116 return; \
2117 } \
eb44b959
AJ		 2118 /* NIP cannot be restored if the memory exception comes from an helper */ \
2119 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2120 gen_reset_fpstatus(); \
af12906f
AJ		 2121 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2122 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2123 if (isfloat) { \
af12906f 2124 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2125 } \
af12906f
AJ		 2126 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2127 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2128}
7c58044c
JM		 2129#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2130_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2131_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2132
7c58044c
JM		 2133#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2134GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2135{ \
76a66253 2136 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2137 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2138 return; \
2139 } \
eb44b959
AJ		 2140 /* NIP cannot be restored if the memory exception comes from an helper */ \
2141 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2142 gen_reset_fpstatus(); \
af12906f
AJ		 2143 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2144 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2145 if (isfloat) { \
af12906f 2146 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2147 } \
af12906f
AJ		 2148 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2149 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2150}
7c58044c
JM		 2151#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2152_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2153_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2154
7c58044c 2155#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2156GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2157{ \
76a66253 2158 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2159 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2160 return; \
2161 } \
eb44b959
AJ		 2162 /* NIP cannot be restored if the memory exception comes from an helper */ \
2163 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2164 gen_reset_fpstatus(); \
af12906f
AJ		 2165 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2167 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2168}
2169
7c58044c 2170#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2171GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2172{ \
76a66253 2173 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2174 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2175 return; \
2176 } \
eb44b959
AJ		 2177 /* NIP cannot be restored if the memory exception comes from an helper */ \
2178 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2179 gen_reset_fpstatus(); \
af12906f
AJ		 2180 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2181 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2182 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2183}
2184
9a64fbe4 2185/* fadd - fadds */
7c58044c 2186GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2187/* fdiv - fdivs */
7c58044c 2188GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2189/* fmul - fmuls */
7c58044c 2190GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2191
d7e4b87e 2192/* fre */
7c58044c 2193GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2194
a750fc0b 2195/* fres */
7c58044c 2196GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2197
a750fc0b 2198/* frsqrte */
7c58044c
JM		 2199GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2200
2201/* frsqrtes */
af12906f 2202GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2203{
af12906f 2204 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2205 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2206 return;
2207 }
eb44b959
AJ		 2208 /* NIP cannot be restored if the memory exception comes from an helper */
2209 gen_update_nip(ctx, ctx->nip - 4);
af12906f
AJ		 2210 gen_reset_fpstatus();
2211 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2212 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2214}
79aceca5 2215
a750fc0b 2216/* fsel */
7c58044c 2217_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2218/* fsub - fsubs */
7c58044c 2219GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2220/* Optional: */
2221/* fsqrt */
a750fc0b 2222GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2223{
76a66253 2224 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2225 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2226 return;
2227 }
eb44b959
AJ		 2228 /* NIP cannot be restored if the memory exception comes from an helper */
2229 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2230 gen_reset_fpstatus();
af12906f
AJ		 2231 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2233}
79aceca5 2234
a750fc0b 2235GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2236{
76a66253 2237 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2238 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2239 return;
2240 }
eb44b959
AJ		 2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2243 gen_reset_fpstatus();
af12906f
AJ		 2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2245 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2247}
2248
2249/*** Floating-Point multiply-and-add ***/
4ecc3190 2250/* fmadd - fmadds */
7c58044c 2251GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2252/* fmsub - fmsubs */
7c58044c 2253GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2254/* fnmadd - fnmadds */
7c58044c 2255GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2256/* fnmsub - fnmsubs */
7c58044c 2257GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2258
2259/*** Floating-Point round & convert ***/
2260/* fctiw */
7c58044c 2261GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2262/* fctiwz */
7c58044c 2263GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2264/* frsp */
7c58044c 2265GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2266#if defined(TARGET_PPC64)
2267/* fcfid */
7c58044c 2268GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2269/* fctid */
7c58044c 2270GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2271/* fctidz */
7c58044c 2272GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2273#endif
79aceca5 2274
d7e4b87e 2275/* frin */
7c58044c 2276GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2277/* friz */
7c58044c 2278GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2279/* frip */
7c58044c 2280GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2281/* frim */
7c58044c 2282GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2283
79aceca5
FB		 2284/*** Floating-Point compare ***/
2285/* fcmpo */
76a66253 2286GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2287{
330c483b 2288 TCGv_i32 crf;
76a66253 2289 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2290 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2291 return;
2292 }
eb44b959
AJ		 2293 /* NIP cannot be restored if the memory exception comes from an helper */
2294 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2295 gen_reset_fpstatus();
9a819377
AJ		 2296 crf = tcg_const_i32(crfD(ctx->opcode));
2297 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2298 tcg_temp_free_i32(crf);
af12906f 2299 gen_helper_float_check_status();
79aceca5
FB		 2300}
2301
2302/* fcmpu */
76a66253 2303GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2304{
330c483b 2305 TCGv_i32 crf;
76a66253 2306 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2307 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2308 return;
2309 }
eb44b959
AJ		 2310 /* NIP cannot be restored if the memory exception comes from an helper */
2311 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2312 gen_reset_fpstatus();
9a819377
AJ		 2313 crf = tcg_const_i32(crfD(ctx->opcode));
2314 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2315 tcg_temp_free_i32(crf);
af12906f 2316 gen_helper_float_check_status();
79aceca5
FB		 2317}
2318
9a64fbe4
FB		 2319/*** Floating-point move ***/
2320/* fabs */
7c58044c
JM		 2321/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2322GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2323
2324/* fmr - fmr. */
7c58044c 2325/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2326GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2327{
76a66253 2328 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2329 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2330 return;
2331 }
af12906f
AJ		 2332 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2333 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2334}
2335
2336/* fnabs */
7c58044c
JM		 2337/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2338GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2339/* fneg */
7c58044c
JM		 2340/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2341GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2342
79aceca5
FB		 2343/*** Floating-Point status & ctrl register ***/
2344/* mcrfs */
2345GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2346{
7c58044c
JM		 2347 int bfa;
2348
76a66253 2349 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2350 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2351 return;
2352 }
7c58044c 2353 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2354 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2355 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2356 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2357}
2358
2359/* mffs */
2360GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2361{
76a66253 2362 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2363 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2364 return;
2365 }
7c58044c 2366 gen_reset_fpstatus();
af12906f
AJ		 2367 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2368 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2369}
2370
2371/* mtfsb0 */
2372GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2373{
fb0eaffc 2374 uint8_t crb;
3b46e624 2375
76a66253 2376 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2377 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2378 return;
2379 }
6e35d524 2380 crb = 31 - crbD(ctx->opcode);
7c58044c 2381 gen_reset_fpstatus();
6e35d524 2382 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2383 TCGv_i32 t0;
2384 /* NIP cannot be restored if the memory exception comes from an helper */
2385 gen_update_nip(ctx, ctx->nip - 4);
2386 t0 = tcg_const_i32(crb);
6e35d524
AJ		 2387 gen_helper_fpscr_clrbit(t0);
2388 tcg_temp_free_i32(t0);
2389 }
7c58044c 2390 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2391 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2392 }
79aceca5
FB		 2393}
2394
2395/* mtfsb1 */
2396GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2397{
fb0eaffc 2398 uint8_t crb;
3b46e624 2399
76a66253 2400 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2401 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2402 return;
2403 }
6e35d524 2404 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2405 gen_reset_fpstatus();
2406 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2407 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2408 TCGv_i32 t0;
2409 /* NIP cannot be restored if the memory exception comes from an helper */
2410 gen_update_nip(ctx, ctx->nip - 4);
2411 t0 = tcg_const_i32(crb);
af12906f 2412 gen_helper_fpscr_setbit(t0);
0f2f39c2 2413 tcg_temp_free_i32(t0);
af12906f 2414 }
7c58044c 2415 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2416 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2417 }
2418 /* We can raise a differed exception */
af12906f 2419 gen_helper_float_check_status();
79aceca5
FB		 2420}
2421
2422/* mtfsf */
4911012d 2423GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT)
79aceca5 2424{
0f2f39c2 2425 TCGv_i32 t0;
4911012d 2426 int L = ctx->opcode & 0x02000000;
af12906f 2427
76a66253 2428 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2429 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2430 return;
2431 }
eb44b959
AJ		 2432 /* NIP cannot be restored if the memory exception comes from an helper */
2433 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2434 gen_reset_fpstatus();
4911012d
BS		 2435 if (L)
2436 t0 = tcg_const_i32(0xff);
2437 else
2438 t0 = tcg_const_i32(FM(ctx->opcode));
af12906f 2439 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2440 tcg_temp_free_i32(t0);
7c58044c 2441 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2442 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2443 }
2444 /* We can raise a differed exception */
af12906f 2445 gen_helper_float_check_status();
79aceca5
FB		 2446}
2447
2448/* mtfsfi */
2449GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2450{
7c58044c 2451 int bf, sh;
0f2f39c2
AJ		 2452 TCGv_i64 t0;
2453 TCGv_i32 t1;
7c58044c 2454
76a66253 2455 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2456 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2457 return;
2458 }
7c58044c
JM		 2459 bf = crbD(ctx->opcode) >> 2;
2460 sh = 7 - bf;
eb44b959
AJ		 2461 /* NIP cannot be restored if the memory exception comes from an helper */
2462 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2463 gen_reset_fpstatus();
0f2f39c2 2464 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2465 t1 = tcg_const_i32(1 << sh);
2466 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2467 tcg_temp_free_i64(t0);
2468 tcg_temp_free_i32(t1);
7c58044c 2469 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2470 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2471 }
2472 /* We can raise a differed exception */
af12906f 2473 gen_helper_float_check_status();
79aceca5
FB		 2474}
2475
76a66253
JM		 2476/*** Addressing modes ***/
2477/* Register indirect with immediate index : EA = (rA|0) + SIMM */
76db3ba4 2478static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
76a66253
JM		 2479{
2480 target_long simm = SIMM(ctx->opcode);
2481
be147d08 2482 simm &= ~maskl;
76db3ba4
AJ		 2483 if (rA(ctx->opcode) == 0) {
2484#if defined(TARGET_PPC64)
2485 if (!ctx->sf_mode) {
2486 tcg_gen_movi_tl(EA, (uint32_t)simm);
2487 } else
2488#endif
e2be8d8d 2489 tcg_gen_movi_tl(EA, simm);
76db3ba4 2490 } else if (likely(simm != 0)) {
e2be8d8d 2491 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
76db3ba4
AJ		 2492#if defined(TARGET_PPC64)
2493 if (!ctx->sf_mode) {
2494 tcg_gen_ext32u_tl(EA, EA);
2495 }
2496#endif
2497 } else {
2498#if defined(TARGET_PPC64)
2499 if (!ctx->sf_mode) {
2500 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2501 } else
2502#endif
e2be8d8d 2503 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2504 }
76a66253
JM		 2505}
2506
76db3ba4 2507static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
76a66253 2508{
76db3ba4
AJ		 2509 if (rA(ctx->opcode) == 0) {
2510#if defined(TARGET_PPC64)
2511 if (!ctx->sf_mode) {
2512 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2513 } else
2514#endif
e2be8d8d 2515 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
76db3ba4 2516 } else {
e2be8d8d 2517 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76db3ba4
AJ		 2518#if defined(TARGET_PPC64)
2519 if (!ctx->sf_mode) {
2520 tcg_gen_ext32u_tl(EA, EA);
2521 }
2522#endif
2523 }
76a66253
JM		 2524}
2525
76db3ba4 2526static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
76a66253 2527{
76db3ba4 2528 if (rA(ctx->opcode) == 0) {
e2be8d8d 2529 tcg_gen_movi_tl(EA, 0);
76db3ba4
AJ		 2530 } else {
2531#if defined(TARGET_PPC64)
2532 if (!ctx->sf_mode) {
2533 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2534 } else
2535#endif
2536 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2537 }
2538}
2539
2540static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2541{
2542 tcg_gen_addi_tl(ret, arg1, val);
2543#if defined(TARGET_PPC64)
2544 if (!ctx->sf_mode) {
2545 tcg_gen_ext32u_tl(ret, ret);
2546 }
2547#endif
76a66253
JM		 2548}
2549
cf360a32
AJ		 2550static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2551{
2552 int l1 = gen_new_label();
2553 TCGv t0 = tcg_temp_new();
2554 TCGv_i32 t1, t2;
2555 /* NIP cannot be restored if the memory exception comes from an helper */
2556 gen_update_nip(ctx, ctx->nip - 4);
2557 tcg_gen_andi_tl(t0, EA, mask);
2558 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2559 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2560 t2 = tcg_const_i32(0);
2561 gen_helper_raise_exception_err(t1, t2);
2562 tcg_temp_free_i32(t1);
2563 tcg_temp_free_i32(t2);
2564 gen_set_label(l1);
2565 tcg_temp_free(t0);
2566}
2567
7863667f 2568/*** Integer load ***/
76db3ba4
AJ		 2569static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2570{
2571 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2572}
2573
2574static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2575{
2576 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2577}
2578
2579static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2580{
2581 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2582 if (unlikely(ctx->le_mode)) {
fa3966a3 2583 tcg_gen_bswap16_tl(arg1, arg1);
76db3ba4 2584 }
b61f2753
AJ		 2585}
2586
76db3ba4 2587static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2588{
76db3ba4 2589 if (unlikely(ctx->le_mode)) {
76db3ba4 2590 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
fa3966a3 2591 tcg_gen_bswap16_tl(arg1, arg1);
76db3ba4 2592 tcg_gen_ext16s_tl(arg1, arg1);
76db3ba4
AJ		 2593 } else {
2594 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2595 }
b61f2753
AJ		 2596}
2597
76db3ba4 2598static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2599{
76db3ba4
AJ		 2600 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2601 if (unlikely(ctx->le_mode)) {
fa3966a3 2602 tcg_gen_bswap32_tl(arg1, arg1);
76db3ba4 2603 }
b61f2753
AJ		 2604}
2605
76db3ba4
AJ		 2606#if defined(TARGET_PPC64)
2607static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2608{
a457e7ee 2609 if (unlikely(ctx->le_mode)) {
76db3ba4 2610 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
fa3966a3
AJ		 2611 tcg_gen_bswap32_tl(arg1, arg1);
2612 tcg_gen_ext32s_tl(arg1, arg1);
b61f2753 2613 } else
76db3ba4 2614 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753 2615}
76db3ba4 2616#endif
b61f2753 2617
76db3ba4 2618static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2619{
76db3ba4
AJ		 2620 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2621 if (unlikely(ctx->le_mode)) {
66896cb8 2622 tcg_gen_bswap64_i64(arg1, arg1);
76db3ba4 2623 }
b61f2753
AJ		 2624}
2625
76db3ba4 2626static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2627{
76db3ba4 2628 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2629}
2630
76db3ba4 2631static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2632{
76db3ba4 2633 if (unlikely(ctx->le_mode)) {
76db3ba4
AJ		 2634 TCGv t0 = tcg_temp_new();
2635 tcg_gen_ext16u_tl(t0, arg1);
fa3966a3 2636 tcg_gen_bswap16_tl(t0, t0);
76db3ba4
AJ		 2637 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2638 tcg_temp_free(t0);
76db3ba4
AJ		 2639 } else {
2640 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2641 }
b61f2753
AJ		 2642}
2643
76db3ba4 2644static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2645{
76db3ba4 2646 if (unlikely(ctx->le_mode)) {
fa3966a3
AJ		 2647 TCGv t0 = tcg_temp_new();
2648 tcg_gen_ext32u_tl(t0, arg1);
2649 tcg_gen_bswap32_tl(t0, t0);
76db3ba4
AJ		 2650 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2651 tcg_temp_free(t0);
76db3ba4
AJ		 2652 } else {
2653 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2654 }
b61f2753
AJ		 2655}
2656
76db3ba4 2657static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2658{
76db3ba4 2659 if (unlikely(ctx->le_mode)) {
a7812ae4 2660 TCGv_i64 t0 = tcg_temp_new_i64();
66896cb8 2661 tcg_gen_bswap64_i64(t0, arg1);
76db3ba4 2662 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2663 tcg_temp_free_i64(t0);
b61f2753 2664 } else
76db3ba4 2665 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2666}
2667
0c8aacd4
AJ		 2668#define GEN_LD(name, ldop, opc, type) \
2669GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2670{ \
76db3ba4
AJ		 2671 TCGv EA; \
2672 gen_set_access_type(ctx, ACCESS_INT); \
2673 EA = tcg_temp_new(); \
2674 gen_addr_imm_index(ctx, EA, 0); \
2675 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2676 tcg_temp_free(EA); \
79aceca5
FB		 2677}
2678
0c8aacd4
AJ		 2679#define GEN_LDU(name, ldop, opc, type) \
2680GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2681{ \
b61f2753 2682 TCGv EA; \
76a66253
JM		 2683 if (unlikely(rA(ctx->opcode) == 0 || \
2684 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2685 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2686 return; \
9a64fbe4 2687 } \
76db3ba4 2688 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2689 EA = tcg_temp_new(); \
9d53c753 2690 if (type == PPC_64B) \
76db3ba4 2691 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2692 else \
76db3ba4
AJ		 2693 gen_addr_imm_index(ctx, EA, 0); \
2694 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2695 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2696 tcg_temp_free(EA); \
79aceca5
FB		 2697}
2698
0c8aacd4
AJ		 2699#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2700GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2701{ \
b61f2753 2702 TCGv EA; \
76a66253
JM		 2703 if (unlikely(rA(ctx->opcode) == 0 || \
2704 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2705 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2706 return; \
9a64fbe4 2707 } \
76db3ba4 2708 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2709 EA = tcg_temp_new(); \
76db3ba4
AJ		 2710 gen_addr_reg_index(ctx, EA); \
2711 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2712 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2713 tcg_temp_free(EA); \
79aceca5
FB		 2714}
2715
0c8aacd4
AJ		 2716#define GEN_LDX(name, ldop, opc2, opc3, type) \
2717GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2718{ \
76db3ba4
AJ		 2719 TCGv EA; \
2720 gen_set_access_type(ctx, ACCESS_INT); \
2721 EA = tcg_temp_new(); \
2722 gen_addr_reg_index(ctx, EA); \
2723 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2724 tcg_temp_free(EA); \
79aceca5
FB		 2725}
2726
0c8aacd4
AJ		 2727#define GEN_LDS(name, ldop, op, type) \
2728GEN_LD(name, ldop, op | 0x20, type); \
2729GEN_LDU(name, ldop, op | 0x21, type); \
2730GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2731GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2732
2733/* lbz lbzu lbzux lbzx */
0c8aacd4 2734GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2735/* lha lhau lhaux lhax */
0c8aacd4 2736GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2737/* lhz lhzu lhzux lhzx */
0c8aacd4 2738GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2739/* lwz lwzu lwzux lwzx */
0c8aacd4 2740GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2741#if defined(TARGET_PPC64)
d9bce9d9 2742/* lwaux */
0c8aacd4 2743GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2744/* lwax */
0c8aacd4 2745GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2746/* ldux */
0c8aacd4 2747GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2748/* ldx */
0c8aacd4 2749GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2750GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2751{
b61f2753 2752 TCGv EA;
d9bce9d9
JM		 2753 if (Rc(ctx->opcode)) {
2754 if (unlikely(rA(ctx->opcode) == 0 ||
2755 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2756 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2757 return;
2758 }
2759 }
76db3ba4 2760 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2761 EA = tcg_temp_new();
76db3ba4 2762 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2763 if (ctx->opcode & 0x02) {
2764 /* lwa (lwau is undefined) */
76db3ba4 2765 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2766 } else {
2767 /* ld - ldu */
76db3ba4 2768 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2769 }
d9bce9d9 2770 if (Rc(ctx->opcode))
b61f2753
AJ		 2771 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2772 tcg_temp_free(EA);
d9bce9d9 2773}
be147d08
JM		 2774/* lq */
2775GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2776{
2777#if defined(CONFIG_USER_ONLY)
e06fcd75 2778 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2779#else
2780 int ra, rd;
b61f2753 2781 TCGv EA;
be147d08
JM		 2782
2783 /* Restore CPU state */
76db3ba4 2784 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2786 return;
2787 }
2788 ra = rA(ctx->opcode);
2789 rd = rD(ctx->opcode);
2790 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2791 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2792 return;
2793 }
76db3ba4 2794 if (unlikely(ctx->le_mode)) {
be147d08 2795 /* Little-endian mode is not handled */
e06fcd75 2796 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2797 return;
2798 }
76db3ba4 2799 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2800 EA = tcg_temp_new();
76db3ba4
AJ		 2801 gen_addr_imm_index(ctx, EA, 0x0F);
2802 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2803 gen_addr_add(ctx, EA, EA, 8);
2804 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
b61f2753 2805 tcg_temp_free(EA);
be147d08
JM		 2806#endif
2807}
d9bce9d9 2808#endif
79aceca5
FB		 2809
2810/*** Integer store ***/
0c8aacd4
AJ		 2811#define GEN_ST(name, stop, opc, type) \
2812GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2813{ \
76db3ba4
AJ		 2814 TCGv EA; \
2815 gen_set_access_type(ctx, ACCESS_INT); \
2816 EA = tcg_temp_new(); \
2817 gen_addr_imm_index(ctx, EA, 0); \
2818 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2819 tcg_temp_free(EA); \
79aceca5
FB		 2820}
2821
0c8aacd4
AJ		 2822#define GEN_STU(name, stop, opc, type) \
2823GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2824{ \
b61f2753 2825 TCGv EA; \
76a66253 2826 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2827 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2828 return; \
9a64fbe4 2829 } \
76db3ba4 2830 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2831 EA = tcg_temp_new(); \
9d53c753 2832 if (type == PPC_64B) \
76db3ba4 2833 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2834 else \
76db3ba4
AJ		 2835 gen_addr_imm_index(ctx, EA, 0); \
2836 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2837 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2838 tcg_temp_free(EA); \
79aceca5
FB		 2839}
2840
0c8aacd4
AJ		 2841#define GEN_STUX(name, stop, opc2, opc3, type) \
2842GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2843{ \
b61f2753 2844 TCGv EA; \
76a66253 2845 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2846 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2847 return; \
9a64fbe4 2848 } \
76db3ba4 2849 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2850 EA = tcg_temp_new(); \
76db3ba4
AJ		 2851 gen_addr_reg_index(ctx, EA); \
2852 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2853 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2854 tcg_temp_free(EA); \
79aceca5
FB		 2855}
2856
0c8aacd4
AJ		 2857#define GEN_STX(name, stop, opc2, opc3, type) \
2858GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2859{ \
76db3ba4
AJ		 2860 TCGv EA; \
2861 gen_set_access_type(ctx, ACCESS_INT); \
2862 EA = tcg_temp_new(); \
2863 gen_addr_reg_index(ctx, EA); \
2864 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2865 tcg_temp_free(EA); \
79aceca5
FB		 2866}
2867
0c8aacd4
AJ		 2868#define GEN_STS(name, stop, op, type) \
2869GEN_ST(name, stop, op | 0x20, type); \
2870GEN_STU(name, stop, op | 0x21, type); \
2871GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2872GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2873
2874/* stb stbu stbux stbx */
0c8aacd4 2875GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2876/* sth sthu sthux sthx */
0c8aacd4 2877GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2878/* stw stwu stwux stwx */
0c8aacd4 2879GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2880#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2881GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2882GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2883GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2884{
be147d08 2885 int rs;
b61f2753 2886 TCGv EA;
be147d08
JM		 2887
2888 rs = rS(ctx->opcode);
2889 if ((ctx->opcode & 0x3) == 0x2) {
2890#if defined(CONFIG_USER_ONLY)
e06fcd75 2891 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2892#else
2893 /* stq */
76db3ba4 2894 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2895 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2896 return;
2897 }
2898 if (unlikely(rs & 1)) {
e06fcd75 2899 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2900 return;
2901 }
76db3ba4 2902 if (unlikely(ctx->le_mode)) {
be147d08 2903 /* Little-endian mode is not handled */
e06fcd75 2904 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2905 return;
2906 }
76db3ba4 2907 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2908 EA = tcg_temp_new();
76db3ba4
AJ		 2909 gen_addr_imm_index(ctx, EA, 0x03);
2910 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2911 gen_addr_add(ctx, EA, EA, 8);
2912 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
b61f2753 2913 tcg_temp_free(EA);
be147d08
JM		 2914#endif
2915 } else {
2916 /* std / stdu */
2917 if (Rc(ctx->opcode)) {
2918 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2919 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2920 return;
2921 }
2922 }
76db3ba4 2923 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2924 EA = tcg_temp_new();
76db3ba4
AJ		 2925 gen_addr_imm_index(ctx, EA, 0x03);
2926 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 2927 if (Rc(ctx->opcode))
b61f2753
AJ		 2928 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2929 tcg_temp_free(EA);
d9bce9d9 2930 }
d9bce9d9
JM		 2931}
2932#endif
79aceca5
FB		 2933/*** Integer load and store with byte reverse ***/
2934/* lhbrx */
76db3ba4 2935static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2936{
76db3ba4
AJ		 2937 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2938 if (likely(!ctx->le_mode)) {
fa3966a3 2939 tcg_gen_bswap16_tl(arg1, arg1);
76db3ba4 2940 }
b61f2753 2941}
0c8aacd4 2942GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 2943
79aceca5 2944/* lwbrx */
76db3ba4 2945static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2946{
76db3ba4
AJ		 2947 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2948 if (likely(!ctx->le_mode)) {
fa3966a3 2949 tcg_gen_bswap32_tl(arg1, arg1);
76db3ba4 2950 }
b61f2753 2951}
0c8aacd4 2952GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 2953
79aceca5 2954/* sthbrx */
76db3ba4 2955static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2956{
76db3ba4 2957 if (likely(!ctx->le_mode)) {
76db3ba4
AJ		 2958 TCGv t0 = tcg_temp_new();
2959 tcg_gen_ext16u_tl(t0, arg1);
fa3966a3 2960 tcg_gen_bswap16_tl(t0, t0);
76db3ba4
AJ		 2961 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2962 tcg_temp_free(t0);
76db3ba4
AJ		 2963 } else {
2964 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2965 }
b61f2753 2966}
0c8aacd4 2967GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 2968
79aceca5 2969/* stwbrx */
76db3ba4 2970static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2971{
76db3ba4 2972 if (likely(!ctx->le_mode)) {
fa3966a3
AJ		 2973 TCGv t0 = tcg_temp_new();
2974 tcg_gen_ext32u_tl(t0, arg1);
2975 tcg_gen_bswap32_tl(t0, t0);
76db3ba4
AJ		 2976 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2977 tcg_temp_free(t0);
76db3ba4
AJ		 2978 } else {
2979 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2980 }
b61f2753 2981}
0c8aacd4 2982GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2983
2984/*** Integer load and store multiple ***/
2985/* lmw */
2986GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2987{
76db3ba4
AJ		 2988 TCGv t0;
2989 TCGv_i32 t1;
2990 gen_set_access_type(ctx, ACCESS_INT);
76a66253 2991 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2992 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 2993 t0 = tcg_temp_new();
2994 t1 = tcg_const_i32(rD(ctx->opcode));
2995 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 2996 gen_helper_lmw(t0, t1);
2997 tcg_temp_free(t0);
2998 tcg_temp_free_i32(t1);
79aceca5
FB		 2999}
3000
3001/* stmw */
3002GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3003{
76db3ba4
AJ		 3004 TCGv t0;
3005 TCGv_i32 t1;
3006 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3007 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3008 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3009 t0 = tcg_temp_new();
3010 t1 = tcg_const_i32(rS(ctx->opcode));
3011 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3012 gen_helper_stmw(t0, t1);
3013 tcg_temp_free(t0);
3014 tcg_temp_free_i32(t1);
79aceca5
FB		 3015}
3016
3017/*** Integer load and store strings ***/
3018/* lswi */
3fc6c082 3019/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3020 * rA is in the range of registers to be loaded.
3021 * In an other hand, IBM says this is valid, but rA won't be loaded.
3022 * For now, I'll follow the spec...
3023 */
05332d70 3024GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3025{
dfbc799d
AJ		 3026 TCGv t0;
3027 TCGv_i32 t1, t2;
79aceca5
FB		 3028 int nb = NB(ctx->opcode);
3029 int start = rD(ctx->opcode);
9a64fbe4 3030 int ra = rA(ctx->opcode);
79aceca5
FB		 3031 int nr;
3032
3033 if (nb == 0)
3034 nb = 32;
3035 nr = nb / 4;
76a66253
JM		 3036 if (unlikely(((start + nr) > 32 &&
3037 start <= ra && (start + nr - 32) > ra) ||
3038 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3039 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3040 return;
297d8e62 3041 }
76db3ba4 3042 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3043 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3044 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3045 t0 = tcg_temp_new();
76db3ba4 3046 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3047 t1 = tcg_const_i32(nb);
3048 t2 = tcg_const_i32(start);
3049 gen_helper_lsw(t0, t1, t2);
3050 tcg_temp_free(t0);
3051 tcg_temp_free_i32(t1);
3052 tcg_temp_free_i32(t2);
79aceca5
FB		 3053}
3054
3055/* lswx */
05332d70 3056GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3057{
76db3ba4
AJ		 3058 TCGv t0;
3059 TCGv_i32 t1, t2, t3;
3060 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3061 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3062 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3063 t0 = tcg_temp_new();
3064 gen_addr_reg_index(ctx, t0);
3065 t1 = tcg_const_i32(rD(ctx->opcode));
3066 t2 = tcg_const_i32(rA(ctx->opcode));
3067 t3 = tcg_const_i32(rB(ctx->opcode));
dfbc799d
AJ		 3068 gen_helper_lswx(t0, t1, t2, t3);
3069 tcg_temp_free(t0);
3070 tcg_temp_free_i32(t1);
3071 tcg_temp_free_i32(t2);
3072 tcg_temp_free_i32(t3);
79aceca5
FB		 3073}
3074
3075/* stswi */
05332d70 3076GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3077{
76db3ba4
AJ		 3078 TCGv t0;
3079 TCGv_i32 t1, t2;
4b3686fa 3080 int nb = NB(ctx->opcode);
76db3ba4 3081 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3082 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3083 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3084 t0 = tcg_temp_new();
3085 gen_addr_register(ctx, t0);
4b3686fa
FB		 3086 if (nb == 0)
3087 nb = 32;
dfbc799d 3088 t1 = tcg_const_i32(nb);
76db3ba4 3089 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3090 gen_helper_stsw(t0, t1, t2);
3091 tcg_temp_free(t0);
3092 tcg_temp_free_i32(t1);
3093 tcg_temp_free_i32(t2);
79aceca5
FB		 3094}
3095
3096/* stswx */
05332d70 3097GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3098{
76db3ba4
AJ		 3099 TCGv t0;
3100 TCGv_i32 t1, t2;
3101 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3102 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3103 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3104 t0 = tcg_temp_new();
3105 gen_addr_reg_index(ctx, t0);
3106 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3107 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3108 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3109 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3110 gen_helper_stsw(t0, t1, t2);
3111 tcg_temp_free(t0);
3112 tcg_temp_free_i32(t1);
3113 tcg_temp_free_i32(t2);
79aceca5
FB		 3114}
3115
3116/*** Memory synchronisation ***/
3117/* eieio */
0db1b20e 3118GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3119{
79aceca5
FB		 3120}
3121
3122/* isync */
0db1b20e 3123GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3124{
e06fcd75 3125 gen_stop_exception(ctx);
79aceca5
FB		 3126}
3127
111bfab3 3128/* lwarx */
76a66253 3129GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3130{
76db3ba4
AJ		 3131 TCGv t0;
3132 gen_set_access_type(ctx, ACCESS_RES);
3133 t0 = tcg_temp_local_new();
3134 gen_addr_reg_index(ctx, t0);
cf360a32 3135 gen_check_align(ctx, t0, 0x03);
76db3ba4 3136 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3137 tcg_gen_mov_tl(cpu_reserve, t0);
3138 tcg_temp_free(t0);
79aceca5
FB		 3139}
3140
3141/* stwcx. */
c7697e1f 3142GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3143{
76db3ba4
AJ		 3144 int l1;
3145 TCGv t0;
3146 gen_set_access_type(ctx, ACCESS_RES);
3147 t0 = tcg_temp_local_new();
3148 gen_addr_reg_index(ctx, t0);
cf360a32 3149 gen_check_align(ctx, t0, 0x03);
cf360a32
AJ		 3150 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3151 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3152 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3153 l1 = gen_new_label();
cf360a32
AJ		 3154 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3155 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3156 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3157 gen_set_label(l1);
3158 tcg_gen_movi_tl(cpu_reserve, -1);
3159 tcg_temp_free(t0);
79aceca5
FB		 3160}
3161
426613db 3162#if defined(TARGET_PPC64)
426613db 3163/* ldarx */
a750fc0b 3164GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3165{
76db3ba4
AJ		 3166 TCGv t0;
3167 gen_set_access_type(ctx, ACCESS_RES);
3168 t0 = tcg_temp_local_new();
3169 gen_addr_reg_index(ctx, t0);
cf360a32 3170 gen_check_align(ctx, t0, 0x07);
76db3ba4 3171 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3172 tcg_gen_mov_tl(cpu_reserve, t0);
3173 tcg_temp_free(t0);
426613db
JM		 3174}
3175
3176/* stdcx. */
c7697e1f 3177GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3178{
76db3ba4
AJ		 3179 int l1;
3180 TCGv t0;
3181 gen_set_access_type(ctx, ACCESS_RES);
3182 t0 = tcg_temp_local_new();
3183 gen_addr_reg_index(ctx, t0);
cf360a32 3184 gen_check_align(ctx, t0, 0x07);
cf360a32
AJ		 3185 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3186 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3187 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3188 l1 = gen_new_label();
cf360a32
AJ		 3189 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3190 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3191 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3192 gen_set_label(l1);
3193 tcg_gen_movi_tl(cpu_reserve, -1);
3194 tcg_temp_free(t0);
426613db
JM		 3195}
3196#endif /* defined(TARGET_PPC64) */
3197
79aceca5 3198/* sync */
a902d886 3199GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3200{
79aceca5
FB		 3201}
3202
0db1b20e
JM		 3203/* wait */
3204GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3205{
931ff272
AJ		 3206 TCGv_i32 t0 = tcg_temp_new_i32();
3207 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3208 tcg_temp_free_i32(t0);
0db1b20e 3209 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3210 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3211}
3212
79aceca5 3213/*** Floating-point load ***/
a0d7d5a7
AJ		 3214#define GEN_LDF(name, ldop, opc, type) \
3215GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3216{ \
a0d7d5a7 3217 TCGv EA; \
76a66253 3218 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3219 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3220 return; \
3221 } \
76db3ba4 3222 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3223 EA = tcg_temp_new(); \
76db3ba4
AJ		 3224 gen_addr_imm_index(ctx, EA, 0); \
3225 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3226 tcg_temp_free(EA); \
79aceca5
FB		 3227}
3228
a0d7d5a7
AJ		 3229#define GEN_LDUF(name, ldop, opc, type) \
3230GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3231{ \
a0d7d5a7 3232 TCGv EA; \
76a66253 3233 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3234 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3235 return; \
3236 } \
76a66253 3237 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3238 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3239 return; \
9a64fbe4 3240 } \
76db3ba4 3241 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3242 EA = tcg_temp_new(); \
76db3ba4
AJ		 3243 gen_addr_imm_index(ctx, EA, 0); \
3244 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3245 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3246 tcg_temp_free(EA); \
79aceca5
FB		 3247}
3248
a0d7d5a7
AJ		 3249#define GEN_LDUXF(name, ldop, opc, type) \
3250GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3251{ \
a0d7d5a7 3252 TCGv EA; \
76a66253 3253 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3254 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3255 return; \
3256 } \
76a66253 3257 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3258 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3259 return; \
9a64fbe4 3260 } \
76db3ba4 3261 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3262 EA = tcg_temp_new(); \
76db3ba4
AJ		 3263 gen_addr_reg_index(ctx, EA); \
3264 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3265 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3266 tcg_temp_free(EA); \
79aceca5
FB		 3267}
3268
a0d7d5a7
AJ		 3269#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3270GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3271{ \
a0d7d5a7 3272 TCGv EA; \
76a66253 3273 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3274 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3275 return; \
3276 } \
76db3ba4 3277 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3278 EA = tcg_temp_new(); \
76db3ba4
AJ		 3279 gen_addr_reg_index(ctx, EA); \
3280 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3281 tcg_temp_free(EA); \
79aceca5
FB		 3282}
3283
a0d7d5a7
AJ		 3284#define GEN_LDFS(name, ldop, op, type) \
3285GEN_LDF(name, ldop, op | 0x20, type); \
3286GEN_LDUF(name, ldop, op | 0x21, type); \
3287GEN_LDUXF(name, ldop, op | 0x01, type); \
3288GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3289
76db3ba4 3290static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3291{
3292 TCGv t0 = tcg_temp_new();
3293 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3294 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3295 tcg_gen_trunc_tl_i32(t1, t0);
3296 tcg_temp_free(t0);
3297 gen_helper_float32_to_float64(arg1, t1);
3298 tcg_temp_free_i32(t1);
3299}
79aceca5 3300
a0d7d5a7
AJ		 3301 /* lfd lfdu lfdux lfdx */
3302GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3303 /* lfs lfsu lfsux lfsx */
3304GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3305
3306/*** Floating-point store ***/
a0d7d5a7
AJ		 3307#define GEN_STF(name, stop, opc, type) \
3308GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3309{ \
a0d7d5a7 3310 TCGv EA; \
76a66253 3311 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3312 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3313 return; \
3314 } \
76db3ba4 3315 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3316 EA = tcg_temp_new(); \
76db3ba4
AJ		 3317 gen_addr_imm_index(ctx, EA, 0); \
3318 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3319 tcg_temp_free(EA); \
79aceca5
FB		 3320}
3321
a0d7d5a7
AJ		 3322#define GEN_STUF(name, stop, opc, type) \
3323GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3324{ \
a0d7d5a7 3325 TCGv EA; \
76a66253 3326 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3327 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3328 return; \
3329 } \
76a66253 3330 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3331 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3332 return; \
9a64fbe4 3333 } \
76db3ba4 3334 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3335 EA = tcg_temp_new(); \
76db3ba4
AJ		 3336 gen_addr_imm_index(ctx, EA, 0); \
3337 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3338 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3339 tcg_temp_free(EA); \
79aceca5
FB		 3340}
3341
a0d7d5a7
AJ		 3342#define GEN_STUXF(name, stop, opc, type) \
3343GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3344{ \
a0d7d5a7 3345 TCGv EA; \
76a66253 3346 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3347 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3348 return; \
3349 } \
76a66253 3350 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3351 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3352 return; \
9a64fbe4 3353 } \
76db3ba4 3354 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3355 EA = tcg_temp_new(); \
76db3ba4
AJ		 3356 gen_addr_reg_index(ctx, EA); \
3357 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3358 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3359 tcg_temp_free(EA); \
79aceca5
FB		 3360}
3361
a0d7d5a7
AJ		 3362#define GEN_STXF(name, stop, opc2, opc3, type) \
3363GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3364{ \
a0d7d5a7 3365 TCGv EA; \
76a66253 3366 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3367 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3368 return; \
3369 } \
76db3ba4 3370 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3371 EA = tcg_temp_new(); \
76db3ba4
AJ		 3372 gen_addr_reg_index(ctx, EA); \
3373 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3374 tcg_temp_free(EA); \
79aceca5
FB		 3375}
3376
a0d7d5a7
AJ		 3377#define GEN_STFS(name, stop, op, type) \
3378GEN_STF(name, stop, op | 0x20, type); \
3379GEN_STUF(name, stop, op | 0x21, type); \
3380GEN_STUXF(name, stop, op | 0x01, type); \
3381GEN_STXF(name, stop, 0x17, op | 0x00, type)
3382
76db3ba4 3383static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3384{
3385 TCGv_i32 t0 = tcg_temp_new_i32();
3386 TCGv t1 = tcg_temp_new();
3387 gen_helper_float64_to_float32(t0, arg1);
3388 tcg_gen_extu_i32_tl(t1, t0);
3389 tcg_temp_free_i32(t0);
76db3ba4 3390 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3391 tcg_temp_free(t1);
3392}
79aceca5
FB		 3393
3394/* stfd stfdu stfdux stfdx */
a0d7d5a7 3395GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3396/* stfs stfsu stfsux stfsx */
a0d7d5a7 3397GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3398
3399/* Optional: */
76db3ba4 3400static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3401{
3402 TCGv t0 = tcg_temp_new();
3403 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3404 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3405 tcg_temp_free(t0);
3406}
79aceca5 3407/* stfiwx */
a0d7d5a7 3408GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3409
3410/*** Branch ***/
b068d6a7
JM		 3411static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3412 target_ulong dest)
c1942362
FB		 3413{
3414 TranslationBlock *tb;
3415 tb = ctx->tb;
a2ffb812
AJ		 3416#if defined(TARGET_PPC64)
3417 if (!ctx->sf_mode)
3418 dest = (uint32_t) dest;
3419#endif
57fec1fe 3420 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3421 likely(!ctx->singlestep_enabled)) {
57fec1fe 3422 tcg_gen_goto_tb(n);
a2ffb812 3423 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3424 tcg_gen_exit_tb((long)tb + n);
c1942362 3425 } else {
a2ffb812 3426 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3427 if (unlikely(ctx->singlestep_enabled)) {
3428 if ((ctx->singlestep_enabled &
bdc4e053 3429 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3430 ctx->exception == POWERPC_EXCP_BRANCH) {
3431 target_ulong tmp = ctx->nip;
3432 ctx->nip = dest;
e06fcd75 3433 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3434 ctx->nip = tmp;
3435 }
3436 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3437 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3438 }
3439 }
57fec1fe 3440 tcg_gen_exit_tb(0);
c1942362 3441 }
c53be334
FB		 3442}
3443
b068d6a7 3444static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3445{
3446#if defined(TARGET_PPC64)
a2ffb812
AJ		 3447 if (ctx->sf_mode == 0)
3448 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3449 else
3450#endif
a2ffb812 3451 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3452}
3453
79aceca5
FB		 3454/* b ba bl bla */
3455GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3456{
76a66253 3457 target_ulong li, target;
38a64f9d 3458
8cbcb4fa 3459 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3460 /* sign extend LI */
76a66253 3461#if defined(TARGET_PPC64)
d9bce9d9
JM		 3462 if (ctx->sf_mode)
3463 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3464 else
76a66253 3465#endif
d9bce9d9 3466 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3467 if (likely(AA(ctx->opcode) == 0))
046d6672 3468 target = ctx->nip + li - 4;
79aceca5 3469 else
9a64fbe4 3470 target = li;
e1833e1f
JM		 3471 if (LK(ctx->opcode))
3472 gen_setlr(ctx, ctx->nip);
c1942362 3473 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3474}
3475
e98a6e40
FB		 3476#define BCOND_IM 0
3477#define BCOND_LR 1
3478#define BCOND_CTR 2
3479
b068d6a7 3480static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3481{
d9bce9d9 3482 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3483 int l1 = gen_new_label();
3484 TCGv target;
e98a6e40 3485
8cbcb4fa 3486 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3487 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3488 target = tcg_temp_local_new();
a2ffb812
AJ		 3489 if (type == BCOND_CTR)
3490 tcg_gen_mov_tl(target, cpu_ctr);
3491 else
3492 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3493 }
e1833e1f
JM		 3494 if (LK(ctx->opcode))
3495 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3496 l1 = gen_new_label();
3497 if ((bo & 0x4) == 0) {
3498 /* Decrement and test CTR */
a7812ae4 3499 TCGv temp = tcg_temp_new();
a2ffb812 3500 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3501 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3502 return;
3503 }
3504 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3505#if defined(TARGET_PPC64)
a2ffb812
AJ		 3506 if (!ctx->sf_mode)
3507 tcg_gen_ext32u_tl(temp, cpu_ctr);
3508 else
d9bce9d9 3509#endif
a2ffb812
AJ		 3510 tcg_gen_mov_tl(temp, cpu_ctr);
3511 if (bo & 0x2) {
3512 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3513 } else {
3514 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3515 }
a7812ae4 3516 tcg_temp_free(temp);
a2ffb812
AJ		 3517 }
3518 if ((bo & 0x10) == 0) {
3519 /* Test CR */
3520 uint32_t bi = BI(ctx->opcode);
3521 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3522 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3523
d9bce9d9 3524 if (bo & 0x8) {
a2ffb812
AJ		 3525 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3526 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3527 } else {
a2ffb812
AJ		 3528 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3529 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3530 }
a7812ae4 3531 tcg_temp_free_i32(temp);
d9bce9d9 3532 }
e98a6e40 3533 if (type == BCOND_IM) {
a2ffb812
AJ		 3534 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3535 if (likely(AA(ctx->opcode) == 0)) {
3536 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3537 } else {
3538 gen_goto_tb(ctx, 0, li);
3539 }
c53be334 3540 gen_set_label(l1);
c1942362 3541 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3542 } else {
d9bce9d9 3543#if defined(TARGET_PPC64)
a2ffb812
AJ		 3544 if (!(ctx->sf_mode))
3545 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3546 else
3547#endif
3548 tcg_gen_andi_tl(cpu_nip, target, ~3);
3549 tcg_gen_exit_tb(0);
3550 gen_set_label(l1);
3551#if defined(TARGET_PPC64)
3552 if (!(ctx->sf_mode))
3553 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3554 else
3555#endif
a2ffb812 3556 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3557 tcg_gen_exit_tb(0);
08e46e54 3558 }
e98a6e40
FB		 3559}
3560
3561GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3562{
e98a6e40
FB		 3563 gen_bcond(ctx, BCOND_IM);
3564}
3565
3566GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3567{
e98a6e40
FB		 3568 gen_bcond(ctx, BCOND_CTR);
3569}
3570
3571GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3572{
e98a6e40
FB		 3573 gen_bcond(ctx, BCOND_LR);
3574}
79aceca5
FB		 3575
3576/*** Condition register logical ***/
e1571908
AJ		 3577#define GEN_CRLOGIC(name, tcg_op, opc) \
3578GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3579{ \
fc0d441e
JM		 3580 uint8_t bitmask; \
3581 int sh; \
a7812ae4 3582 TCGv_i32 t0, t1; \
fc0d441e 3583 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3584 t0 = tcg_temp_new_i32(); \
fc0d441e 3585 if (sh > 0) \
fea0c503 3586 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3587 else if (sh < 0) \
fea0c503 3588 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3589 else \
fea0c503 3590 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3591 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3592 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3593 if (sh > 0) \
fea0c503 3594 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3595 else if (sh < 0) \
fea0c503 3596 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3597 else \
fea0c503
AJ		 3598 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3599 tcg_op(t0, t0, t1); \
fc0d441e 3600 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3601 tcg_gen_andi_i32(t0, t0, bitmask); \
3602 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3603 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3604 tcg_temp_free_i32(t0); \
3605 tcg_temp_free_i32(t1); \
79aceca5
FB		 3606}
3607
3608/* crand */
e1571908 3609GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3610/* crandc */
e1571908 3611GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3612/* creqv */
e1571908 3613GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3614/* crnand */
e1571908 3615GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3616/* crnor */
e1571908 3617GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3618/* cror */
e1571908 3619GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3620/* crorc */
e1571908 3621GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3622/* crxor */
e1571908 3623GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3624/* mcrf */
3625GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3626{
47e4661c 3627 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3628}
3629
3630/*** System linkage ***/
76db3ba4 3631/* rfi (mem_idx only) */
76a66253 3632GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3633{
9a64fbe4 3634#if defined(CONFIG_USER_ONLY)
e06fcd75 3635 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 3636#else
3637 /* Restore CPU state */
76db3ba4 3638 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3639 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 3640 return;
9a64fbe4 3641 }
d72a19f7 3642 gen_helper_rfi();
e06fcd75 3643 gen_sync_exception(ctx);
9a64fbe4 3644#endif
79aceca5
FB		 3645}
3646
426613db 3647#if defined(TARGET_PPC64)
a750fc0b 3648GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3649{
3650#if defined(CONFIG_USER_ONLY)
e06fcd75 3651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3652#else
3653 /* Restore CPU state */
76db3ba4 3654 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3656 return;
3657 }
d72a19f7 3658 gen_helper_rfid();
e06fcd75 3659 gen_sync_exception(ctx);
426613db
JM		 3660#endif
3661}
426613db 3662
5b8105fa 3663GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3664{
3665#if defined(CONFIG_USER_ONLY)
e06fcd75 3666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3667#else
3668 /* Restore CPU state */
76db3ba4 3669 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 3670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3671 return;
3672 }
d72a19f7 3673 gen_helper_hrfid();
e06fcd75 3674 gen_sync_exception(ctx);
be147d08
JM		 3675#endif
3676}
3677#endif
3678
79aceca5 3679/* sc */
417bf010
JM		 3680#if defined(CONFIG_USER_ONLY)
3681#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3682#else
3683#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3684#endif
e1833e1f 3685GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3686{
e1833e1f
JM		 3687 uint32_t lev;
3688
3689 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3690 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3691}
3692
3693/*** Trap ***/
3694/* tw */
76a66253 3695GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3696{
cab3bee2 3697 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3698 /* Update the nip since this might generate a trap exception */
d9bce9d9 3699 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3700 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3701 tcg_temp_free_i32(t0);
79aceca5
FB		 3702}
3703
3704/* twi */
3705GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3706{
cab3bee2
AJ		 3707 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3708 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3709 /* Update the nip since this might generate a trap exception */
3710 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3711 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3712 tcg_temp_free(t0);
3713 tcg_temp_free_i32(t1);
79aceca5
FB		 3714}
3715
d9bce9d9
JM		 3716#if defined(TARGET_PPC64)
3717/* td */
3718GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3719{
cab3bee2 3720 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3721 /* Update the nip since this might generate a trap exception */
3722 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3723 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3724 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3725}
3726
3727/* tdi */
3728GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3729{
cab3bee2
AJ		 3730 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3731 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3732 /* Update the nip since this might generate a trap exception */
3733 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3734 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3735 tcg_temp_free(t0);
3736 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3737}
3738#endif
3739
79aceca5 3740/*** Processor control ***/
79aceca5
FB		 3741/* mcrxr */
3742GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3743{
3d7b417e
AJ		 3744 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3745 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3746 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3747}
3748
0cfe11ea 3749/* mfcr mfocrf */
76a66253 3750GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3751{
76a66253 3752 uint32_t crm, crn;
3b46e624 3753
76a66253
JM		 3754 if (likely(ctx->opcode & 0x00100000)) {
3755 crm = CRM(ctx->opcode);
8dd640e4 3756 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 3757 crn = ctz32 (crm);
e1571908 3758 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 3759 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3760 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 3761 }
d9bce9d9 3762 } else {
651721b2
AJ		 3763 TCGv_i32 t0 = tcg_temp_new_i32();
3764 tcg_gen_mov_i32(t0, cpu_crf[0]);
3765 tcg_gen_shli_i32(t0, t0, 4);
3766 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3767 tcg_gen_shli_i32(t0, t0, 4);
3768 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3769 tcg_gen_shli_i32(t0, t0, 4);
3770 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3771 tcg_gen_shli_i32(t0, t0, 4);
3772 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3773 tcg_gen_shli_i32(t0, t0, 4);
3774 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3775 tcg_gen_shli_i32(t0, t0, 4);
3776 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3777 tcg_gen_shli_i32(t0, t0, 4);
3778 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3779 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3780 tcg_temp_free_i32(t0);
d9bce9d9 3781 }
79aceca5
FB		 3782}
3783
3784/* mfmsr */
3785GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3786{
9a64fbe4 3787#if defined(CONFIG_USER_ONLY)
e06fcd75 3788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3789#else
76db3ba4 3790 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3792 return;
9a64fbe4 3793 }
6527f6ea 3794 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3795#endif
79aceca5
FB		 3796}
3797
a11b8151 3798#if 1
6f2d8978 3799#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3800#else
3801static void spr_noaccess (void *opaque, int sprn)
3802{
3803 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3804 printf("ERROR: try to access SPR %d !\n", sprn);
3805}
3806#define SPR_NOACCESS (&spr_noaccess)
3807#endif
3808
79aceca5 3809/* mfspr */
b068d6a7 3810static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3811{
45d827d2 3812 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3813 uint32_t sprn = SPR(ctx->opcode);
3814
3fc6c082 3815#if !defined(CONFIG_USER_ONLY)
76db3ba4 3816 if (ctx->mem_idx == 2)
be147d08 3817 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 3818 else if (ctx->mem_idx)
3fc6c082
FB		 3819 read_cb = ctx->spr_cb[sprn].oea_read;
3820 else
9a64fbe4 3821#endif
3fc6c082 3822 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3823 if (likely(read_cb != NULL)) {
3824 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3825 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3826 } else {
3827 /* Privilege exception */
9fceefa7
JM		 3828 /* This is a hack to avoid warnings when running Linux:
3829 * this OS breaks the PowerPC virtualisation model,
3830 * allowing userland application to read the PVR
3831 */
3832 if (sprn != SPR_PVR) {
93fcfe39 3833 qemu_log("Trying to read privileged spr %d %03x at "
077fc206 3834 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3835 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3836 sprn, sprn, ctx->nip);
f24e5695 3837 }
e06fcd75 3838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3839 }
3fc6c082
FB		 3840 } else {
3841 /* Not defined */
93fcfe39 3842 qemu_log("Trying to read invalid spr %d %03x at "
077fc206 3843 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3844 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3845 sprn, sprn, ctx->nip);
e06fcd75 3846 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3847 }
79aceca5
FB		 3848}
3849
3fc6c082 3850GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3851{
3fc6c082 3852 gen_op_mfspr(ctx);
76a66253 3853}
3fc6c082
FB		 3854
3855/* mftb */
a750fc0b 3856GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3857{
3858 gen_op_mfspr(ctx);
79aceca5
FB		 3859}
3860
0cfe11ea 3861/* mtcrf mtocrf*/
8dd4983c 3862GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3863{
76a66253 3864 uint32_t crm, crn;
3b46e624 3865
76a66253 3866 crm = CRM(ctx->opcode);
8dd640e4 3867 if (likely((ctx->opcode & 0x00100000))) {
3868 if (crm && ((crm & (crm - 1)) == 0)) {
3869 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 3870 crn = ctz32 (crm);
8dd640e4 3871 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 3872 tcg_gen_shri_i32(temp, temp, crn * 4);
3873 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 3874 tcg_temp_free_i32(temp);
3875 }
76a66253 3876 } else {
651721b2
AJ		 3877 TCGv_i32 temp = tcg_temp_new_i32();
3878 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3879 for (crn = 0 ; crn < 8 ; crn++) {
3880 if (crm & (1 << crn)) {
3881 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3882 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3883 }
3884 }
a7812ae4 3885 tcg_temp_free_i32(temp);
76a66253 3886 }
79aceca5
FB		 3887}
3888
3889/* mtmsr */
426613db 3890#if defined(TARGET_PPC64)
be147d08 3891GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3892{
3893#if defined(CONFIG_USER_ONLY)
e06fcd75 3894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 3895#else
76db3ba4 3896 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3897 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 3898 return;
3899 }
be147d08
JM		 3900 if (ctx->opcode & 0x00010000) {
3901 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3902 TCGv t0 = tcg_temp_new();
3903 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3904 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3905 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3906 tcg_temp_free(t0);
be147d08 3907 } else {
056b05f8
JM		 3908 /* XXX: we need to update nip before the store
3909 * if we enter power saving mode, we will exit the loop
3910 * directly from ppc_store_msr
3911 */
be147d08 3912 gen_update_nip(ctx, ctx->nip);
6527f6ea 3913 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3914 /* Must stop the translation as machine state (may have) changed */
3915 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3916 gen_stop_exception(ctx);
be147d08 3917 }
426613db
JM		 3918#endif
3919}
3920#endif
3921
79aceca5
FB		 3922GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3923{
9a64fbe4 3924#if defined(CONFIG_USER_ONLY)
e06fcd75 3925 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3926#else
76db3ba4 3927 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3929 return;
9a64fbe4 3930 }
be147d08
JM		 3931 if (ctx->opcode & 0x00010000) {
3932 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 3933 TCGv t0 = tcg_temp_new();
3934 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3935 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3936 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3937 tcg_temp_free(t0);
be147d08 3938 } else {
056b05f8
JM		 3939 /* XXX: we need to update nip before the store
3940 * if we enter power saving mode, we will exit the loop
3941 * directly from ppc_store_msr
3942 */
be147d08 3943 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3944#if defined(TARGET_PPC64)
6527f6ea
AJ		 3945 if (!ctx->sf_mode) {
3946 TCGv t0 = tcg_temp_new();
3947 TCGv t1 = tcg_temp_new();
3948 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3949 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3950 tcg_gen_or_tl(t0, t0, t1);
3951 tcg_temp_free(t1);
3952 gen_helper_store_msr(t0);
3953 tcg_temp_free(t0);
3954 } else
d9bce9d9 3955#endif
6527f6ea 3956 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 3957 /* Must stop the translation as machine state (may have) changed */
6527f6ea 3958 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 3959 gen_stop_exception(ctx);
be147d08 3960 }
9a64fbe4 3961#endif
79aceca5
FB		 3962}
3963
3964/* mtspr */
3965GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3966{
45d827d2 3967 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 3968 uint32_t sprn = SPR(ctx->opcode);
3969
3fc6c082 3970#if !defined(CONFIG_USER_ONLY)
76db3ba4 3971 if (ctx->mem_idx == 2)
be147d08 3972 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 3973 else if (ctx->mem_idx)
3fc6c082
FB		 3974 write_cb = ctx->spr_cb[sprn].oea_write;
3975 else
9a64fbe4 3976#endif
3fc6c082 3977 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3978 if (likely(write_cb != NULL)) {
3979 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 3980 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 3981 } else {
3982 /* Privilege exception */
93fcfe39 3983 qemu_log("Trying to write privileged spr %d %03x at "
077fc206 3984 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3985 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3986 sprn, sprn, ctx->nip);
e06fcd75 3987 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 3988 }
3fc6c082
FB		 3989 } else {
3990 /* Not defined */
93fcfe39 3991 qemu_log("Trying to write invalid spr %d %03x at "
077fc206 3992 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3993 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3994 sprn, sprn, ctx->nip);
e06fcd75 3995 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3996 }
79aceca5
FB		 3997}
3998
3999/*** Cache management ***/
79aceca5 4000/* dcbf */
0db1b20e 4001GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4002{
dac454af 4003 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4004 TCGv t0;
4005 gen_set_access_type(ctx, ACCESS_CACHE);
4006 t0 = tcg_temp_new();
4007 gen_addr_reg_index(ctx, t0);
4008 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4009 tcg_temp_free(t0);
79aceca5
FB		 4010}
4011
4012/* dcbi (Supervisor only) */
9a64fbe4 4013GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4014{
a541f297 4015#if defined(CONFIG_USER_ONLY)
e06fcd75 4016 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4017#else
b61f2753 4018 TCGv EA, val;
76db3ba4 4019 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4020 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4021 return;
9a64fbe4 4022 }
a7812ae4 4023 EA = tcg_temp_new();
76db3ba4
AJ		 4024 gen_set_access_type(ctx, ACCESS_CACHE);
4025 gen_addr_reg_index(ctx, EA);
a7812ae4 4026 val = tcg_temp_new();
76a66253 4027 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4028 gen_qemu_ld8u(ctx, val, EA);
4029 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4030 tcg_temp_free(val);
4031 tcg_temp_free(EA);
a541f297 4032#endif
79aceca5
FB		 4033}
4034
4035/* dcdst */
9a64fbe4 4036GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4037{
76a66253 4038 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4039 TCGv t0;
4040 gen_set_access_type(ctx, ACCESS_CACHE);
4041 t0 = tcg_temp_new();
4042 gen_addr_reg_index(ctx, t0);
4043 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4044 tcg_temp_free(t0);
79aceca5
FB		 4045}
4046
4047/* dcbt */
0db1b20e 4048GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4049{
0db1b20e 4050 /* interpreted as no-op */
76a66253
JM		 4051 /* XXX: specification say this is treated as a load by the MMU
4052 * but does not generate any exception
4053 */
79aceca5
FB		 4054}
4055
4056/* dcbtst */
0db1b20e 4057GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4058{
0db1b20e 4059 /* interpreted as no-op */
76a66253
JM		 4060 /* XXX: specification say this is treated as a load by the MMU
4061 * but does not generate any exception
4062 */
79aceca5
FB		 4063}
4064
4065/* dcbz */
d63001d1 4066GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4067{
76db3ba4
AJ		 4068 TCGv t0;
4069 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4070 /* NIP cannot be restored if the memory exception comes from an helper */
4071 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4072 t0 = tcg_temp_new();
4073 gen_addr_reg_index(ctx, t0);
799a8c8d
AJ		 4074 gen_helper_dcbz(t0);
4075 tcg_temp_free(t0);
d63001d1
JM		 4076}
4077
c7697e1f 4078GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4079{
76db3ba4
AJ		 4080 TCGv t0;
4081 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4082 /* NIP cannot be restored if the memory exception comes from an helper */
4083 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4084 t0 = tcg_temp_new();
4085 gen_addr_reg_index(ctx, t0);
d63001d1 4086 if (ctx->opcode & 0x00200000)
799a8c8d 4087 gen_helper_dcbz(t0);
d63001d1 4088 else
799a8c8d
AJ		 4089 gen_helper_dcbz_970(t0);
4090 tcg_temp_free(t0);
79aceca5
FB		 4091}
4092
ae1c1a3d
AJ		 4093/* dst / dstt */
4094GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4095{
4096 if (rA(ctx->opcode) == 0) {
4097 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4098 } else {
4099 /* interpreted as no-op */
4100 }
4101}
4102
4103/* dstst /dststt */
4104GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4105{
4106 if (rA(ctx->opcode) == 0) {
4107 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4108 } else {
4109 /* interpreted as no-op */
4110 }
4111
4112}
4113
4114/* dss / dssall */
4115GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4116{
4117 /* interpreted as no-op */
4118}
4119
79aceca5 4120/* icbi */
1b413d55 4121GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4122{
76db3ba4
AJ		 4123 TCGv t0;
4124 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4125 /* NIP cannot be restored if the memory exception comes from an helper */
4126 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4127 t0 = tcg_temp_new();
4128 gen_addr_reg_index(ctx, t0);
37d269df
AJ		 4129 gen_helper_icbi(t0);
4130 tcg_temp_free(t0);
79aceca5
FB		 4131}
4132
4133/* Optional: */
4134/* dcba */
a750fc0b 4135GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4136{
0db1b20e
JM		 4137 /* interpreted as no-op */
4138 /* XXX: specification say this is treated as a store by the MMU
4139 * but does not generate any exception
4140 */
79aceca5
FB		 4141}
4142
4143/*** Segment register manipulation ***/
4144/* Supervisor only: */
4145/* mfsr */
4146GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4147{
9a64fbe4 4148#if defined(CONFIG_USER_ONLY)
e06fcd75 4149 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4150#else
74d37793 4151 TCGv t0;
76db3ba4 4152 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4154 return;
9a64fbe4 4155 }
74d37793
AJ		 4156 t0 = tcg_const_tl(SR(ctx->opcode));
4157 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4158 tcg_temp_free(t0);
9a64fbe4 4159#endif
79aceca5
FB		 4160}
4161
4162/* mfsrin */
9a64fbe4 4163GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4164{
9a64fbe4 4165#if defined(CONFIG_USER_ONLY)
e06fcd75 4166 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4167#else
74d37793 4168 TCGv t0;
76db3ba4 4169 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4171 return;
9a64fbe4 4172 }
74d37793
AJ		 4173 t0 = tcg_temp_new();
4174 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4175 tcg_gen_andi_tl(t0, t0, 0xF);
4176 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4177 tcg_temp_free(t0);
9a64fbe4 4178#endif
79aceca5
FB		 4179}
4180
4181/* mtsr */
e63c59cb 4182GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4183{
9a64fbe4 4184#if defined(CONFIG_USER_ONLY)
e06fcd75 4185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4186#else
74d37793 4187 TCGv t0;
76db3ba4 4188 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4190 return;
9a64fbe4 4191 }
74d37793
AJ		 4192 t0 = tcg_const_tl(SR(ctx->opcode));
4193 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4194 tcg_temp_free(t0);
9a64fbe4 4195#endif
79aceca5
FB		 4196}
4197
4198/* mtsrin */
9a64fbe4 4199GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4200{
9a64fbe4 4201#if defined(CONFIG_USER_ONLY)
e06fcd75 4202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4203#else
74d37793 4204 TCGv t0;
76db3ba4 4205 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4207 return;
9a64fbe4 4208 }
74d37793
AJ		 4209 t0 = tcg_temp_new();
4210 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4211 tcg_gen_andi_tl(t0, t0, 0xF);
4212 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4213 tcg_temp_free(t0);
9a64fbe4 4214#endif
79aceca5
FB		 4215}
4216
12de9a39
JM		 4217#if defined(TARGET_PPC64)
4218/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4219/* mfsr */
c7697e1f 4220GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4221{
4222#if defined(CONFIG_USER_ONLY)
e06fcd75 4223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4224#else
74d37793 4225 TCGv t0;
76db3ba4 4226 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4228 return;
4229 }
74d37793 4230 t0 = tcg_const_tl(SR(ctx->opcode));
f6b868fc 4231 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
74d37793 4232 tcg_temp_free(t0);
12de9a39
JM		 4233#endif
4234}
4235
4236/* mfsrin */
c7697e1f
JM		 4237GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4238 PPC_SEGMENT_64B)
12de9a39
JM		 4239{
4240#if defined(CONFIG_USER_ONLY)
e06fcd75 4241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4242#else
74d37793 4243 TCGv t0;
76db3ba4 4244 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4246 return;
4247 }
74d37793
AJ		 4248 t0 = tcg_temp_new();
4249 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4250 tcg_gen_andi_tl(t0, t0, 0xF);
f6b868fc 4251 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
74d37793 4252 tcg_temp_free(t0);
12de9a39
JM		 4253#endif
4254}
4255
4256/* mtsr */
c7697e1f 4257GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4258{
4259#if defined(CONFIG_USER_ONLY)
e06fcd75 4260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4261#else
74d37793 4262 TCGv t0;
76db3ba4 4263 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4265 return;
4266 }
74d37793 4267 t0 = tcg_const_tl(SR(ctx->opcode));
f6b868fc 4268 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4269 tcg_temp_free(t0);
12de9a39
JM		 4270#endif
4271}
4272
4273/* mtsrin */
c7697e1f
JM		 4274GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4275 PPC_SEGMENT_64B)
12de9a39
JM		 4276{
4277#if defined(CONFIG_USER_ONLY)
e06fcd75 4278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4279#else
74d37793 4280 TCGv t0;
76db3ba4 4281 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4283 return;
4284 }
74d37793
AJ		 4285 t0 = tcg_temp_new();
4286 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4287 tcg_gen_andi_tl(t0, t0, 0xF);
f6b868fc 4288 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4289 tcg_temp_free(t0);
12de9a39
JM		 4290#endif
4291}
f6b868fc
BS		 4292
4293/* slbmte */
4294GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B)
4295{
4296#if defined(CONFIG_USER_ONLY)
4297 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4298#else
4299 if (unlikely(!ctx->mem_idx)) {
4300 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4301 return;
4302 }
4303 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4304#endif
4305}
4306
12de9a39
JM		 4307#endif /* defined(TARGET_PPC64) */
4308
79aceca5 4309/*** Lookaside buffer management ***/
76db3ba4 4310/* Optional & mem_idx only: */
79aceca5 4311/* tlbia */
3fc6c082 4312GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4313{
9a64fbe4 4314#if defined(CONFIG_USER_ONLY)
e06fcd75 4315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4316#else
76db3ba4 4317 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4319 return;
9a64fbe4 4320 }
74d37793 4321 gen_helper_tlbia();
9a64fbe4 4322#endif
79aceca5
FB		 4323}
4324
bf14b1ce
BS		 4325/* tlbiel */
4326GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE)
4327{
4328#if defined(CONFIG_USER_ONLY)
4329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4330#else
4331 if (unlikely(!ctx->mem_idx)) {
4332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4333 return;
4334 }
4335 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4336#endif
4337}
4338
79aceca5 4339/* tlbie */
76a66253 4340GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4341{
9a64fbe4 4342#if defined(CONFIG_USER_ONLY)
e06fcd75 4343 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4344#else
76db3ba4 4345 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4346 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4347 return;
9a64fbe4 4348 }
d9bce9d9 4349#if defined(TARGET_PPC64)
74d37793
AJ		 4350 if (!ctx->sf_mode) {
4351 TCGv t0 = tcg_temp_new();
4352 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4353 gen_helper_tlbie(t0);
4354 tcg_temp_free(t0);
4355 } else
d9bce9d9 4356#endif
74d37793 4357 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4358#endif
79aceca5
FB		 4359}
4360
4361/* tlbsync */
76a66253 4362GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4363{
9a64fbe4 4364#if defined(CONFIG_USER_ONLY)
e06fcd75 4365 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4366#else
76db3ba4 4367 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4368 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4369 return;
9a64fbe4
FB		 4370 }
4371 /* This has no effect: it should ensure that all previous
4372 * tlbie have completed
4373 */
e06fcd75 4374 gen_stop_exception(ctx);
9a64fbe4 4375#endif
79aceca5
FB		 4376}
4377
426613db
JM		 4378#if defined(TARGET_PPC64)
4379/* slbia */
4380GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4381{
4382#if defined(CONFIG_USER_ONLY)
e06fcd75 4383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4384#else
76db3ba4 4385 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4387 return;
4388 }
74d37793 4389 gen_helper_slbia();
426613db
JM		 4390#endif
4391}
4392
4393/* slbie */
4394GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4395{
4396#if defined(CONFIG_USER_ONLY)
e06fcd75 4397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4398#else
76db3ba4 4399 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4401 return;
4402 }
74d37793 4403 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4404#endif
4405}
4406#endif
4407
79aceca5
FB		 4408/*** External control ***/
4409/* Optional: */
111bfab3 4410/* eciwx */
79aceca5
FB		 4411GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4412{
76db3ba4 4413 TCGv t0;
fa407c03 4414 /* Should check EAR[E] ! */
76db3ba4
AJ		 4415 gen_set_access_type(ctx, ACCESS_EXT);
4416 t0 = tcg_temp_new();
4417 gen_addr_reg_index(ctx, t0);
fa407c03 4418 gen_check_align(ctx, t0, 0x03);
76db3ba4 4419 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4420 tcg_temp_free(t0);
76a66253
JM		 4421}
4422
4423/* ecowx */
4424GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4425{
76db3ba4 4426 TCGv t0;
fa407c03 4427 /* Should check EAR[E] ! */
76db3ba4
AJ		 4428 gen_set_access_type(ctx, ACCESS_EXT);
4429 t0 = tcg_temp_new();
4430 gen_addr_reg_index(ctx, t0);
fa407c03 4431 gen_check_align(ctx, t0, 0x03);
76db3ba4 4432 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4433 tcg_temp_free(t0);
76a66253
JM		 4434}
4435
4436/* PowerPC 601 specific instructions */
4437/* abs - abs. */
4438GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4439{
22e0e173
AJ		 4440 int l1 = gen_new_label();
4441 int l2 = gen_new_label();
4442 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4443 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4444 tcg_gen_br(l2);
4445 gen_set_label(l1);
4446 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4447 gen_set_label(l2);
76a66253 4448 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4449 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4450}
4451
4452/* abso - abso. */
4453GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4454{
22e0e173
AJ		 4455 int l1 = gen_new_label();
4456 int l2 = gen_new_label();
4457 int l3 = gen_new_label();
4458 /* Start with XER OV disabled, the most likely case */
4459 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4460 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4461 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4462 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4463 tcg_gen_br(l2);
4464 gen_set_label(l1);
4465 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4466 tcg_gen_br(l3);
4467 gen_set_label(l2);
4468 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4469 gen_set_label(l3);
76a66253 4470 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4471 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4472}
4473
4474/* clcs */
a750fc0b 4475GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4476{
22e0e173
AJ		 4477 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4478 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4479 tcg_temp_free_i32(t0);
c7697e1f 4480 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4481}
4482
4483/* div - div. */
4484GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4485{
22e0e173 4486 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4487 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4489}
4490
4491/* divo - divo. */
4492GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4493{
22e0e173 4494 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4495 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4496 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4497}
4498
4499/* divs - divs. */
4500GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4501{
22e0e173 4502 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4503 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4504 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4505}
4506
4507/* divso - divso. */
4508GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4509{
22e0e173 4510 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4511 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4512 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4513}
4514
4515/* doz - doz. */
4516GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4517{
22e0e173
AJ		 4518 int l1 = gen_new_label();
4519 int l2 = gen_new_label();
4520 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4521 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4522 tcg_gen_br(l2);
4523 gen_set_label(l1);
4524 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4525 gen_set_label(l2);
76a66253 4526 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4527 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4528}
4529
4530/* dozo - dozo. */
4531GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4532{
22e0e173
AJ		 4533 int l1 = gen_new_label();
4534 int l2 = gen_new_label();
4535 TCGv t0 = tcg_temp_new();
4536 TCGv t1 = tcg_temp_new();
4537 TCGv t2 = tcg_temp_new();
4538 /* Start with XER OV disabled, the most likely case */
4539 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4540 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4541 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4542 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4543 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4544 tcg_gen_andc_tl(t1, t1, t2);
4545 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4546 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4547 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4548 tcg_gen_br(l2);
4549 gen_set_label(l1);
4550 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4551 gen_set_label(l2);
4552 tcg_temp_free(t0);
4553 tcg_temp_free(t1);
4554 tcg_temp_free(t2);
76a66253 4555 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4556 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4557}
4558
4559/* dozi */
4560GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4561{
22e0e173
AJ		 4562 target_long simm = SIMM(ctx->opcode);
4563 int l1 = gen_new_label();
4564 int l2 = gen_new_label();
4565 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4566 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4567 tcg_gen_br(l2);
4568 gen_set_label(l1);
4569 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4570 gen_set_label(l2);
4571 if (unlikely(Rc(ctx->opcode) != 0))
4572 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4573}
4574
76a66253
JM		 4575/* lscbx - lscbx. */
4576GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4577{
bdb4b689
AJ		 4578 TCGv t0 = tcg_temp_new();
4579 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4580 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4581 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4582
76db3ba4 4583 gen_addr_reg_index(ctx, t0);
76a66253 4584 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4585 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4586 gen_helper_lscbx(t0, t0, t1, t2, t3);
4587 tcg_temp_free_i32(t1);
4588 tcg_temp_free_i32(t2);
4589 tcg_temp_free_i32(t3);
3d7b417e 4590 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4591 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4592 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4593 gen_set_Rc0(ctx, t0);
4594 tcg_temp_free(t0);
76a66253
JM		 4595}
4596
4597/* maskg - maskg. */
4598GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4599{
22e0e173
AJ		 4600 int l1 = gen_new_label();
4601 TCGv t0 = tcg_temp_new();
4602 TCGv t1 = tcg_temp_new();
4603 TCGv t2 = tcg_temp_new();
4604 TCGv t3 = tcg_temp_new();
4605 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4606 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4607 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4608 tcg_gen_addi_tl(t2, t0, 1);
4609 tcg_gen_shr_tl(t2, t3, t2);
4610 tcg_gen_shr_tl(t3, t3, t1);
4611 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4612 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4613 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4614 gen_set_label(l1);
4615 tcg_temp_free(t0);
4616 tcg_temp_free(t1);
4617 tcg_temp_free(t2);
4618 tcg_temp_free(t3);
76a66253 4619 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4620 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4621}
4622
4623/* maskir - maskir. */
4624GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4625{
22e0e173
AJ		 4626 TCGv t0 = tcg_temp_new();
4627 TCGv t1 = tcg_temp_new();
4628 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4629 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4630 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4631 tcg_temp_free(t0);
4632 tcg_temp_free(t1);
76a66253 4633 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4634 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4635}
4636
4637/* mul - mul. */
4638GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4639{
22e0e173
AJ		 4640 TCGv_i64 t0 = tcg_temp_new_i64();
4641 TCGv_i64 t1 = tcg_temp_new_i64();
4642 TCGv t2 = tcg_temp_new();
4643 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4644 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4645 tcg_gen_mul_i64(t0, t0, t1);
4646 tcg_gen_trunc_i64_tl(t2, t0);
4647 gen_store_spr(SPR_MQ, t2);
4648 tcg_gen_shri_i64(t1, t0, 32);
4649 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4650 tcg_temp_free_i64(t0);
4651 tcg_temp_free_i64(t1);
4652 tcg_temp_free(t2);
76a66253 4653 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4654 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4655}
4656
4657/* mulo - mulo. */
4658GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4659{
22e0e173
AJ		 4660 int l1 = gen_new_label();
4661 TCGv_i64 t0 = tcg_temp_new_i64();
4662 TCGv_i64 t1 = tcg_temp_new_i64();
4663 TCGv t2 = tcg_temp_new();
4664 /* Start with XER OV disabled, the most likely case */
4665 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4666 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4667 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4668 tcg_gen_mul_i64(t0, t0, t1);
4669 tcg_gen_trunc_i64_tl(t2, t0);
4670 gen_store_spr(SPR_MQ, t2);
4671 tcg_gen_shri_i64(t1, t0, 32);
4672 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4673 tcg_gen_ext32s_i64(t1, t0);
4674 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4675 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4676 gen_set_label(l1);
4677 tcg_temp_free_i64(t0);
4678 tcg_temp_free_i64(t1);
4679 tcg_temp_free(t2);
76a66253 4680 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4681 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4682}
4683
4684/* nabs - nabs. */
4685GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4686{
22e0e173
AJ		 4687 int l1 = gen_new_label();
4688 int l2 = gen_new_label();
4689 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4690 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4691 tcg_gen_br(l2);
4692 gen_set_label(l1);
4693 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4694 gen_set_label(l2);
76a66253 4695 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4696 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4697}
4698
4699/* nabso - nabso. */
4700GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4701{
22e0e173
AJ		 4702 int l1 = gen_new_label();
4703 int l2 = gen_new_label();
4704 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4705 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4706 tcg_gen_br(l2);
4707 gen_set_label(l1);
4708 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4709 gen_set_label(l2);
4710 /* nabs never overflows */
4711 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4712 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4713 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4714}
4715
4716/* rlmi - rlmi. */
4717GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4718{
7487953d
AJ		 4719 uint32_t mb = MB(ctx->opcode);
4720 uint32_t me = ME(ctx->opcode);
4721 TCGv t0 = tcg_temp_new();
4722 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4723 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4724 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4725 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4726 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4727 tcg_temp_free(t0);
76a66253 4728 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4729 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4730}
4731
4732/* rrib - rrib. */
4733GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4734{
7487953d
AJ		 4735 TCGv t0 = tcg_temp_new();
4736 TCGv t1 = tcg_temp_new();
4737 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4738 tcg_gen_movi_tl(t1, 0x80000000);
4739 tcg_gen_shr_tl(t1, t1, t0);
4740 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4741 tcg_gen_and_tl(t0, t0, t1);
4742 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4743 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4744 tcg_temp_free(t0);
4745 tcg_temp_free(t1);
76a66253 4746 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4747 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4748}
4749
4750/* sle - sle. */
4751GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4752{
7487953d
AJ		 4753 TCGv t0 = tcg_temp_new();
4754 TCGv t1 = tcg_temp_new();
4755 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4756 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4757 tcg_gen_subfi_tl(t1, 32, t1);
4758 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4759 tcg_gen_or_tl(t1, t0, t1);
4760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4761 gen_store_spr(SPR_MQ, t1);
4762 tcg_temp_free(t0);
4763 tcg_temp_free(t1);
76a66253 4764 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4765 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4766}
4767
4768/* sleq - sleq. */
4769GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4770{
7487953d
AJ		 4771 TCGv t0 = tcg_temp_new();
4772 TCGv t1 = tcg_temp_new();
4773 TCGv t2 = tcg_temp_new();
4774 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4775 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4776 tcg_gen_shl_tl(t2, t2, t0);
4777 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4778 gen_load_spr(t1, SPR_MQ);
4779 gen_store_spr(SPR_MQ, t0);
4780 tcg_gen_and_tl(t0, t0, t2);
4781 tcg_gen_andc_tl(t1, t1, t2);
4782 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4783 tcg_temp_free(t0);
4784 tcg_temp_free(t1);
4785 tcg_temp_free(t2);
76a66253 4786 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4787 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4788}
4789
4790/* sliq - sliq. */
4791GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4792{
7487953d
AJ		 4793 int sh = SH(ctx->opcode);
4794 TCGv t0 = tcg_temp_new();
4795 TCGv t1 = tcg_temp_new();
4796 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4797 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4798 tcg_gen_or_tl(t1, t0, t1);
4799 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4800 gen_store_spr(SPR_MQ, t1);
4801 tcg_temp_free(t0);
4802 tcg_temp_free(t1);
76a66253 4803 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4804 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4805}
4806
4807/* slliq - slliq. */
4808GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4809{
7487953d
AJ		 4810 int sh = SH(ctx->opcode);
4811 TCGv t0 = tcg_temp_new();
4812 TCGv t1 = tcg_temp_new();
4813 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4814 gen_load_spr(t1, SPR_MQ);
4815 gen_store_spr(SPR_MQ, t0);
4816 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4817 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4818 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4819 tcg_temp_free(t0);
4820 tcg_temp_free(t1);
76a66253 4821 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4822 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4823}
4824
4825/* sllq - sllq. */
4826GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4827{
7487953d
AJ		 4828 int l1 = gen_new_label();
4829 int l2 = gen_new_label();
4830 TCGv t0 = tcg_temp_local_new();
4831 TCGv t1 = tcg_temp_local_new();
4832 TCGv t2 = tcg_temp_local_new();
4833 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4834 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4835 tcg_gen_shl_tl(t1, t1, t2);
4836 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4837 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4838 gen_load_spr(t0, SPR_MQ);
4839 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4840 tcg_gen_br(l2);
4841 gen_set_label(l1);
4842 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4843 gen_load_spr(t2, SPR_MQ);
4844 tcg_gen_andc_tl(t1, t2, t1);
4845 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4846 gen_set_label(l2);
4847 tcg_temp_free(t0);
4848 tcg_temp_free(t1);
4849 tcg_temp_free(t2);
76a66253 4850 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4851 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4852}
4853
4854/* slq - slq. */
4855GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4856{
7487953d
AJ		 4857 int l1 = gen_new_label();
4858 TCGv t0 = tcg_temp_new();
4859 TCGv t1 = tcg_temp_new();
4860 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4861 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4862 tcg_gen_subfi_tl(t1, 32, t1);
4863 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4864 tcg_gen_or_tl(t1, t0, t1);
4865 gen_store_spr(SPR_MQ, t1);
4866 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4867 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4868 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4869 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4870 gen_set_label(l1);
4871 tcg_temp_free(t0);
4872 tcg_temp_free(t1);
76a66253 4873 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4874 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4875}
4876
d9bce9d9 4877/* sraiq - sraiq. */
76a66253
JM		 4878GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4879{
7487953d
AJ		 4880 int sh = SH(ctx->opcode);
4881 int l1 = gen_new_label();
4882 TCGv t0 = tcg_temp_new();
4883 TCGv t1 = tcg_temp_new();
4884 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4885 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4886 tcg_gen_or_tl(t0, t0, t1);
4887 gen_store_spr(SPR_MQ, t0);
4888 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4889 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4890 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4891 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4892 gen_set_label(l1);
4893 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4894 tcg_temp_free(t0);
4895 tcg_temp_free(t1);
76a66253 4896 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4897 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4898}
4899
4900/* sraq - sraq. */
4901GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4902{
7487953d
AJ		 4903 int l1 = gen_new_label();
4904 int l2 = gen_new_label();
4905 TCGv t0 = tcg_temp_new();
4906 TCGv t1 = tcg_temp_local_new();
4907 TCGv t2 = tcg_temp_local_new();
4908 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4909 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4910 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4911 tcg_gen_subfi_tl(t2, 32, t2);
4912 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4913 tcg_gen_or_tl(t0, t0, t2);
4914 gen_store_spr(SPR_MQ, t0);
4915 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4916 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4917 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4918 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4919 gen_set_label(l1);
4920 tcg_temp_free(t0);
4921 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4922 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4923 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4924 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4925 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4926 gen_set_label(l2);
4927 tcg_temp_free(t1);
4928 tcg_temp_free(t2);
76a66253 4929 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4931}
4932
4933/* sre - sre. */
4934GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4935{
7487953d
AJ		 4936 TCGv t0 = tcg_temp_new();
4937 TCGv t1 = tcg_temp_new();
4938 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4939 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4940 tcg_gen_subfi_tl(t1, 32, t1);
4941 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4942 tcg_gen_or_tl(t1, t0, t1);
4943 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4944 gen_store_spr(SPR_MQ, t1);
4945 tcg_temp_free(t0);
4946 tcg_temp_free(t1);
76a66253 4947 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4948 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4949}
4950
4951/* srea - srea. */
4952GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4953{
7487953d
AJ		 4954 TCGv t0 = tcg_temp_new();
4955 TCGv t1 = tcg_temp_new();
4956 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4957 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4958 gen_store_spr(SPR_MQ, t0);
4959 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4960 tcg_temp_free(t0);
4961 tcg_temp_free(t1);
76a66253 4962 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4963 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4964}
4965
4966/* sreq */
4967GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4968{
7487953d
AJ		 4969 TCGv t0 = tcg_temp_new();
4970 TCGv t1 = tcg_temp_new();
4971 TCGv t2 = tcg_temp_new();
4972 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4973 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4974 tcg_gen_shr_tl(t1, t1, t0);
4975 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4976 gen_load_spr(t2, SPR_MQ);
4977 gen_store_spr(SPR_MQ, t0);
4978 tcg_gen_and_tl(t0, t0, t1);
4979 tcg_gen_andc_tl(t2, t2, t1);
4980 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4981 tcg_temp_free(t0);
4982 tcg_temp_free(t1);
4983 tcg_temp_free(t2);
76a66253 4984 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4986}
4987
4988/* sriq */
4989GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4990{
7487953d
AJ		 4991 int sh = SH(ctx->opcode);
4992 TCGv t0 = tcg_temp_new();
4993 TCGv t1 = tcg_temp_new();
4994 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4995 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4996 tcg_gen_or_tl(t1, t0, t1);
4997 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4998 gen_store_spr(SPR_MQ, t1);
4999 tcg_temp_free(t0);
5000 tcg_temp_free(t1);
76a66253 5001 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5002 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5003}
5004
5005/* srliq */
5006GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5007{
7487953d
AJ		 5008 int sh = SH(ctx->opcode);
5009 TCGv t0 = tcg_temp_new();
5010 TCGv t1 = tcg_temp_new();
5011 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5012 gen_load_spr(t1, SPR_MQ);
5013 gen_store_spr(SPR_MQ, t0);
5014 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5015 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5016 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5017 tcg_temp_free(t0);
5018 tcg_temp_free(t1);
76a66253 5019 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5021}
5022
5023/* srlq */
5024GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5025{
7487953d
AJ		 5026 int l1 = gen_new_label();
5027 int l2 = gen_new_label();
5028 TCGv t0 = tcg_temp_local_new();
5029 TCGv t1 = tcg_temp_local_new();
5030 TCGv t2 = tcg_temp_local_new();
5031 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5032 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5033 tcg_gen_shr_tl(t2, t1, t2);
5034 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5035 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5036 gen_load_spr(t0, SPR_MQ);
5037 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5038 tcg_gen_br(l2);
5039 gen_set_label(l1);
5040 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5041 tcg_gen_and_tl(t0, t0, t2);
5042 gen_load_spr(t1, SPR_MQ);
5043 tcg_gen_andc_tl(t1, t1, t2);
5044 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5045 gen_set_label(l2);
5046 tcg_temp_free(t0);
5047 tcg_temp_free(t1);
5048 tcg_temp_free(t2);
76a66253 5049 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5050 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5051}
5052
5053/* srq */
5054GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5055{
7487953d
AJ		 5056 int l1 = gen_new_label();
5057 TCGv t0 = tcg_temp_new();
5058 TCGv t1 = tcg_temp_new();
5059 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5060 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5061 tcg_gen_subfi_tl(t1, 32, t1);
5062 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5063 tcg_gen_or_tl(t1, t0, t1);
5064 gen_store_spr(SPR_MQ, t1);
5065 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5066 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5067 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5068 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5069 gen_set_label(l1);
5070 tcg_temp_free(t0);
5071 tcg_temp_free(t1);
76a66253 5072 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5073 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5074}
5075
5076/* PowerPC 602 specific instructions */
5077/* dsa */
5078GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5079{
5080 /* XXX: TODO */
e06fcd75 5081 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5082}
5083
5084/* esa */
5085GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5086{
5087 /* XXX: TODO */
e06fcd75 5088 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5089}
5090
5091/* mfrom */
5092GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5093{
5094#if defined(CONFIG_USER_ONLY)
e06fcd75 5095 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5096#else
76db3ba4 5097 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5098 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5099 return;
5100 }
cf02a65c 5101 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5102#endif
5103}
5104
5105/* 602 - 603 - G2 TLB management */
5106/* tlbld */
c7697e1f 5107GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5108{
5109#if defined(CONFIG_USER_ONLY)
e06fcd75 5110 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5111#else
76db3ba4 5112 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5113 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5114 return;
5115 }
74d37793 5116 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5117#endif
5118}
5119
5120/* tlbli */
c7697e1f 5121GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5122{
5123#if defined(CONFIG_USER_ONLY)
e06fcd75 5124 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5125#else
76db3ba4 5126 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5128 return;
5129 }
74d37793 5130 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5131#endif
5132}
5133
7dbe11ac
JM		 5134/* 74xx TLB management */
5135/* tlbld */
c7697e1f 5136GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5137{
5138#if defined(CONFIG_USER_ONLY)
e06fcd75 5139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5140#else
76db3ba4 5141 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5143 return;
5144 }
74d37793 5145 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5146#endif
5147}
5148
5149/* tlbli */
c7697e1f 5150GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5151{
5152#if defined(CONFIG_USER_ONLY)
e06fcd75 5153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5154#else
76db3ba4 5155 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5156 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5157 return;
5158 }
74d37793 5159 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5160#endif
5161}
5162
76a66253
JM		 5163/* POWER instructions not in PowerPC 601 */
5164/* clf */
5165GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5166{
5167 /* Cache line flush: implemented as no-op */
5168}
5169
5170/* cli */
5171GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5172{
7f75ffd3 5173 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5174#if defined(CONFIG_USER_ONLY)
e06fcd75 5175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5176#else
76db3ba4 5177 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5178 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5179 return;
5180 }
5181#endif
5182}
5183
5184/* dclst */
5185GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5186{
5187 /* Data cache line store: treated as no-op */
5188}
5189
5190GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5191{
5192#if defined(CONFIG_USER_ONLY)
e06fcd75 5193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5194#else
74d37793
AJ		 5195 int ra = rA(ctx->opcode);
5196 int rd = rD(ctx->opcode);
5197 TCGv t0;
76db3ba4 5198 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5200 return;
5201 }
74d37793 5202 t0 = tcg_temp_new();
76db3ba4 5203 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5204 tcg_gen_shri_tl(t0, t0, 28);
5205 tcg_gen_andi_tl(t0, t0, 0xF);
5206 gen_helper_load_sr(cpu_gpr[rd], t0);
5207 tcg_temp_free(t0);
76a66253 5208 if (ra != 0 && ra != rd)
74d37793 5209 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5210#endif
5211}
5212
5213GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5214{
5215#if defined(CONFIG_USER_ONLY)
e06fcd75 5216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5217#else
22e0e173 5218 TCGv t0;
76db3ba4 5219 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5221 return;
5222 }
22e0e173 5223 t0 = tcg_temp_new();
76db3ba4 5224 gen_addr_reg_index(ctx, t0);
22e0e173
AJ		 5225 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5226 tcg_temp_free(t0);
76a66253
JM		 5227#endif
5228}
5229
5230GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5231{
5232#if defined(CONFIG_USER_ONLY)
e06fcd75 5233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5234#else
76db3ba4 5235 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5237 return;
5238 }
d72a19f7 5239 gen_helper_rfsvc();
e06fcd75 5240 gen_sync_exception(ctx);
76a66253
JM		 5241#endif
5242}
5243
5244/* svc is not implemented for now */
5245
5246/* POWER2 specific instructions */
5247/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5248
5249/* lfq */
5250GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5251{
01a4afeb 5252 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5253 TCGv t0;
5254 gen_set_access_type(ctx, ACCESS_FLOAT);
5255 t0 = tcg_temp_new();
5256 gen_addr_imm_index(ctx, t0, 0);
5257 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5258 gen_addr_add(ctx, t0, t0, 8);
5259 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5260 tcg_temp_free(t0);
76a66253
JM		 5261}
5262
5263/* lfqu */
5264GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5265{
5266 int ra = rA(ctx->opcode);
01a4afeb 5267 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5268 TCGv t0, t1;
5269 gen_set_access_type(ctx, ACCESS_FLOAT);
5270 t0 = tcg_temp_new();
5271 t1 = tcg_temp_new();
5272 gen_addr_imm_index(ctx, t0, 0);
5273 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5274 gen_addr_add(ctx, t1, t0, 8);
5275 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5276 if (ra != 0)
01a4afeb
AJ		 5277 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5278 tcg_temp_free(t0);
5279 tcg_temp_free(t1);
76a66253
JM		 5280}
5281
5282/* lfqux */
5283GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5284{
5285 int ra = rA(ctx->opcode);
01a4afeb 5286 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5287 gen_set_access_type(ctx, ACCESS_FLOAT);
5288 TCGv t0, t1;
5289 t0 = tcg_temp_new();
5290 gen_addr_reg_index(ctx, t0);
5291 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5292 t1 = tcg_temp_new();
5293 gen_addr_add(ctx, t1, t0, 8);
5294 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5295 tcg_temp_free(t1);
76a66253 5296 if (ra != 0)
01a4afeb
AJ		 5297 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5298 tcg_temp_free(t0);
76a66253
JM		 5299}
5300
5301/* lfqx */
5302GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5303{
01a4afeb 5304 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5305 TCGv t0;
5306 gen_set_access_type(ctx, ACCESS_FLOAT);
5307 t0 = tcg_temp_new();
5308 gen_addr_reg_index(ctx, t0);
5309 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5310 gen_addr_add(ctx, t0, t0, 8);
5311 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5312 tcg_temp_free(t0);
76a66253
JM		 5313}
5314
5315/* stfq */
5316GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5317{
01a4afeb 5318 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5319 TCGv t0;
5320 gen_set_access_type(ctx, ACCESS_FLOAT);
5321 t0 = tcg_temp_new();
5322 gen_addr_imm_index(ctx, t0, 0);
5323 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5324 gen_addr_add(ctx, t0, t0, 8);
5325 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5326 tcg_temp_free(t0);
76a66253
JM		 5327}
5328
5329/* stfqu */
5330GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5331{
5332 int ra = rA(ctx->opcode);
01a4afeb 5333 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5334 TCGv t0, t1;
5335 gen_set_access_type(ctx, ACCESS_FLOAT);
5336 t0 = tcg_temp_new();
5337 gen_addr_imm_index(ctx, t0, 0);
5338 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5339 t1 = tcg_temp_new();
5340 gen_addr_add(ctx, t1, t0, 8);
5341 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5342 tcg_temp_free(t1);
76a66253 5343 if (ra != 0)
01a4afeb
AJ		 5344 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5345 tcg_temp_free(t0);
76a66253
JM		 5346}
5347
5348/* stfqux */
5349GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5350{
5351 int ra = rA(ctx->opcode);
01a4afeb 5352 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5353 TCGv t0, t1;
5354 gen_set_access_type(ctx, ACCESS_FLOAT);
5355 t0 = tcg_temp_new();
5356 gen_addr_reg_index(ctx, t0);
5357 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5358 t1 = tcg_temp_new();
5359 gen_addr_add(ctx, t1, t0, 8);
5360 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5361 tcg_temp_free(t1);
76a66253 5362 if (ra != 0)
01a4afeb
AJ		 5363 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5364 tcg_temp_free(t0);
76a66253
JM		 5365}
5366
5367/* stfqx */
5368GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5369{
01a4afeb 5370 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5371 TCGv t0;
5372 gen_set_access_type(ctx, ACCESS_FLOAT);
5373 t0 = tcg_temp_new();
5374 gen_addr_reg_index(ctx, t0);
5375 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5376 gen_addr_add(ctx, t0, t0, 8);
5377 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5378 tcg_temp_free(t0);
76a66253
JM		 5379}
5380
5381/* BookE specific instructions */
2662a059 5382/* XXX: not implemented on 440 ? */
05332d70 5383GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5384{
5385 /* XXX: TODO */
e06fcd75 5386 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5387}
5388
2662a059 5389/* XXX: not implemented on 440 ? */
05332d70 5390GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5391{
5392#if defined(CONFIG_USER_ONLY)
e06fcd75 5393 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5394#else
74d37793 5395 TCGv t0;
76db3ba4 5396 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5398 return;
5399 }
ec72e276 5400 t0 = tcg_temp_new();
76db3ba4 5401 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5402 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5403 tcg_temp_free(t0);
76a66253
JM		 5404#endif
5405}
5406
5407/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5408static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5409 int opc2, int opc3,
5410 int ra, int rb, int rt, int Rc)
76a66253 5411{
182608d4
AJ		 5412 TCGv t0, t1;
5413
a7812ae4
PB		 5414 t0 = tcg_temp_local_new();
5415 t1 = tcg_temp_local_new();
182608d4 5416
76a66253
JM		 5417 switch (opc3 & 0x0D) {
5418 case 0x05:
5419 /* macchw - macchw. - macchwo - macchwo. */
5420 /* macchws - macchws. - macchwso - macchwso. */
5421 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5422 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5423 /* mulchw - mulchw. */
182608d4
AJ		 5424 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5425 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5426 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5427 break;
5428 case 0x04:
5429 /* macchwu - macchwu. - macchwuo - macchwuo. */
5430 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5431 /* mulchwu - mulchwu. */
182608d4
AJ		 5432 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5433 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5434 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5435 break;
5436 case 0x01:
5437 /* machhw - machhw. - machhwo - machhwo. */
5438 /* machhws - machhws. - machhwso - machhwso. */
5439 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5440 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5441 /* mulhhw - mulhhw. */
182608d4
AJ		 5442 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5443 tcg_gen_ext16s_tl(t0, t0);
5444 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5445 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5446 break;
5447 case 0x00:
5448 /* machhwu - machhwu. - machhwuo - machhwuo. */
5449 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5450 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5451 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5452 tcg_gen_ext16u_tl(t0, t0);
5453 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5454 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5455 break;
5456 case 0x0D:
5457 /* maclhw - maclhw. - maclhwo - maclhwo. */
5458 /* maclhws - maclhws. - maclhwso - maclhwso. */
5459 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5460 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5461 /* mullhw - mullhw. */
182608d4
AJ		 5462 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5463 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5464 break;
5465 case 0x0C:
5466 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5467 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5468 /* mullhwu - mullhwu. */
182608d4
AJ		 5469 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5470 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5471 break;
5472 }
76a66253 5473 if (opc2 & 0x04) {
182608d4
AJ		 5474 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5475 tcg_gen_mul_tl(t1, t0, t1);
5476 if (opc2 & 0x02) {
5477 /* nmultiply-and-accumulate (0x0E) */
5478 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5479 } else {
5480 /* multiply-and-accumulate (0x0C) */
5481 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5482 }
5483
5484 if (opc3 & 0x12) {
5485 /* Check overflow and/or saturate */
5486 int l1 = gen_new_label();
5487
5488 if (opc3 & 0x10) {
5489 /* Start with XER OV disabled, the most likely case */
5490 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5491 }
5492 if (opc3 & 0x01) {
5493 /* Signed */
5494 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5495 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5496 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5497 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5498 if (opc3 & 0x02) {
182608d4
AJ		 5499 /* Saturate */
5500 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5501 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5502 }
5503 } else {
5504 /* Unsigned */
5505 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5506 if (opc3 & 0x02) {
182608d4
AJ		 5507 /* Saturate */
5508 tcg_gen_movi_tl(t0, UINT32_MAX);
5509 }
5510 }
5511 if (opc3 & 0x10) {
5512 /* Check overflow */
5513 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5514 }
5515 gen_set_label(l1);
5516 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5517 }
5518 } else {
5519 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5520 }
182608d4
AJ		 5521 tcg_temp_free(t0);
5522 tcg_temp_free(t1);
76a66253
JM		 5523 if (unlikely(Rc) != 0) {
5524 /* Update Rc0 */
182608d4 5525 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5526 }
5527}
5528
a750fc0b
JM		 5529#define GEN_MAC_HANDLER(name, opc2, opc3) \
5530GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5531{ \
5532 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5533 rD(ctx->opcode), Rc(ctx->opcode)); \
5534}
5535
5536/* macchw - macchw. */
a750fc0b 5537GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5538/* macchwo - macchwo. */
a750fc0b 5539GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5540/* macchws - macchws. */
a750fc0b 5541GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5542/* macchwso - macchwso. */
a750fc0b 5543GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5544/* macchwsu - macchwsu. */
a750fc0b 5545GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5546/* macchwsuo - macchwsuo. */
a750fc0b 5547GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5548/* macchwu - macchwu. */
a750fc0b 5549GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5550/* macchwuo - macchwuo. */
a750fc0b 5551GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5552/* machhw - machhw. */
a750fc0b 5553GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5554/* machhwo - machhwo. */
a750fc0b 5555GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5556/* machhws - machhws. */
a750fc0b 5557GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5558/* machhwso - machhwso. */
a750fc0b 5559GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5560/* machhwsu - machhwsu. */
a750fc0b 5561GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5562/* machhwsuo - machhwsuo. */
a750fc0b 5563GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5564/* machhwu - machhwu. */
a750fc0b 5565GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5566/* machhwuo - machhwuo. */
a750fc0b 5567GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5568/* maclhw - maclhw. */
a750fc0b 5569GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5570/* maclhwo - maclhwo. */
a750fc0b 5571GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5572/* maclhws - maclhws. */
a750fc0b 5573GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5574/* maclhwso - maclhwso. */
a750fc0b 5575GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5576/* maclhwu - maclhwu. */
a750fc0b 5577GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5578/* maclhwuo - maclhwuo. */
a750fc0b 5579GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5580/* maclhwsu - maclhwsu. */
a750fc0b 5581GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5582/* maclhwsuo - maclhwsuo. */
a750fc0b 5583GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5584/* nmacchw - nmacchw. */
a750fc0b 5585GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5586/* nmacchwo - nmacchwo. */
a750fc0b 5587GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5588/* nmacchws - nmacchws. */
a750fc0b 5589GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5590/* nmacchwso - nmacchwso. */
a750fc0b 5591GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5592/* nmachhw - nmachhw. */
a750fc0b 5593GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5594/* nmachhwo - nmachhwo. */
a750fc0b 5595GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5596/* nmachhws - nmachhws. */
a750fc0b 5597GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5598/* nmachhwso - nmachhwso. */
a750fc0b 5599GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5600/* nmaclhw - nmaclhw. */
a750fc0b 5601GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5602/* nmaclhwo - nmaclhwo. */
a750fc0b 5603GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5604/* nmaclhws - nmaclhws. */
a750fc0b 5605GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5606/* nmaclhwso - nmaclhwso. */
a750fc0b 5607GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5608
5609/* mulchw - mulchw. */
a750fc0b 5610GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5611/* mulchwu - mulchwu. */
a750fc0b 5612GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5613/* mulhhw - mulhhw. */
a750fc0b 5614GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5615/* mulhhwu - mulhhwu. */
a750fc0b 5616GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5617/* mullhw - mullhw. */
a750fc0b 5618GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5619/* mullhwu - mullhwu. */
a750fc0b 5620GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5621
5622/* mfdcr */
05332d70 5623GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5624{
5625#if defined(CONFIG_USER_ONLY)
e06fcd75 5626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5627#else
06dca6a7 5628 TCGv dcrn;
76db3ba4 5629 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5630 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5631 return;
5632 }
06dca6a7
AJ		 5633 /* NIP cannot be restored if the memory exception comes from an helper */
5634 gen_update_nip(ctx, ctx->nip - 4);
5635 dcrn = tcg_const_tl(SPR(ctx->opcode));
5636 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5637 tcg_temp_free(dcrn);
76a66253
JM		 5638#endif
5639}
5640
5641/* mtdcr */
05332d70 5642GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5643{
5644#if defined(CONFIG_USER_ONLY)
e06fcd75 5645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5646#else
06dca6a7 5647 TCGv dcrn;
76db3ba4 5648 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5650 return;
5651 }
06dca6a7
AJ		 5652 /* NIP cannot be restored if the memory exception comes from an helper */
5653 gen_update_nip(ctx, ctx->nip - 4);
5654 dcrn = tcg_const_tl(SPR(ctx->opcode));
5655 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5656 tcg_temp_free(dcrn);
a42bd6cc
JM		 5657#endif
5658}
5659
5660/* mfdcrx */
2662a059 5661/* XXX: not implemented on 440 ? */
05332d70 5662GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5663{
5664#if defined(CONFIG_USER_ONLY)
e06fcd75 5665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5666#else
76db3ba4 5667 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5668 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5669 return;
5670 }
06dca6a7
AJ		 5671 /* NIP cannot be restored if the memory exception comes from an helper */
5672 gen_update_nip(ctx, ctx->nip - 4);
5673 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5674 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5675#endif
5676}
5677
5678/* mtdcrx */
2662a059 5679/* XXX: not implemented on 440 ? */
05332d70 5680GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5681{
5682#if defined(CONFIG_USER_ONLY)
e06fcd75 5683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5684#else
76db3ba4 5685 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5687 return;
5688 }
06dca6a7
AJ		 5689 /* NIP cannot be restored if the memory exception comes from an helper */
5690 gen_update_nip(ctx, ctx->nip - 4);
5691 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5692 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5693#endif
5694}
5695
a750fc0b
JM		 5696/* mfdcrux (PPC 460) : user-mode access to DCR */
5697GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5698{
06dca6a7
AJ		 5699 /* NIP cannot be restored if the memory exception comes from an helper */
5700 gen_update_nip(ctx, ctx->nip - 4);
5701 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5702 /* Note: Rc update flag set leads to undefined state of Rc0 */
5703}
5704
5705/* mtdcrux (PPC 460) : user-mode access to DCR */
5706GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5707{
06dca6a7
AJ		 5708 /* NIP cannot be restored if the memory exception comes from an helper */
5709 gen_update_nip(ctx, ctx->nip - 4);
5710 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5711 /* Note: Rc update flag set leads to undefined state of Rc0 */
5712}
5713
76a66253
JM		 5714/* dccci */
5715GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5716{
5717#if defined(CONFIG_USER_ONLY)
e06fcd75 5718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5719#else
76db3ba4 5720 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5722 return;
5723 }
5724 /* interpreted as no-op */
5725#endif
5726}
5727
5728/* dcread */
5729GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5730{
5731#if defined(CONFIG_USER_ONLY)
e06fcd75 5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5733#else
b61f2753 5734 TCGv EA, val;
76db3ba4 5735 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5736 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5737 return;
5738 }
76db3ba4 5739 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5740 EA = tcg_temp_new();
76db3ba4 5741 gen_addr_reg_index(ctx, EA);
a7812ae4 5742 val = tcg_temp_new();
76db3ba4 5743 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5744 tcg_temp_free(val);
5745 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5746 tcg_temp_free(EA);
76a66253
JM		 5747#endif
5748}
5749
5750/* icbt */
c7697e1f 5751GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5752{
5753 /* interpreted as no-op */
5754 /* XXX: specification say this is treated as a load by the MMU
5755 * but does not generate any exception
5756 */
5757}
5758
5759/* iccci */
5760GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5761{
5762#if defined(CONFIG_USER_ONLY)
e06fcd75 5763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5764#else
76db3ba4 5765 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5767 return;
5768 }
5769 /* interpreted as no-op */
5770#endif
5771}
5772
5773/* icread */
5774GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5775{
5776#if defined(CONFIG_USER_ONLY)
e06fcd75 5777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5778#else
76db3ba4 5779 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5781 return;
5782 }
5783 /* interpreted as no-op */
5784#endif
5785}
5786
76db3ba4 5787/* rfci (mem_idx only) */
c7697e1f 5788GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5789{
5790#if defined(CONFIG_USER_ONLY)
e06fcd75 5791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5792#else
76db3ba4 5793 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5795 return;
5796 }
5797 /* Restore CPU state */
d72a19f7 5798 gen_helper_40x_rfci();
e06fcd75 5799 gen_sync_exception(ctx);
a42bd6cc
JM		 5800#endif
5801}
5802
5803GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5804{
5805#if defined(CONFIG_USER_ONLY)
e06fcd75 5806 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5807#else
76db3ba4 5808 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5810 return;
5811 }
5812 /* Restore CPU state */
d72a19f7 5813 gen_helper_rfci();
e06fcd75 5814 gen_sync_exception(ctx);
a42bd6cc
JM		 5815#endif
5816}
5817
5818/* BookE specific */
2662a059 5819/* XXX: not implemented on 440 ? */
05332d70 5820GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5821{
5822#if defined(CONFIG_USER_ONLY)
e06fcd75 5823 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5824#else
76db3ba4 5825 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5827 return;
5828 }
5829 /* Restore CPU state */
d72a19f7 5830 gen_helper_rfdi();
e06fcd75 5831 gen_sync_exception(ctx);
76a66253
JM		 5832#endif
5833}
5834
2662a059 5835/* XXX: not implemented on 440 ? */
a750fc0b 5836GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5837{
5838#if defined(CONFIG_USER_ONLY)
e06fcd75 5839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5840#else
76db3ba4 5841 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5842 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5843 return;
5844 }
5845 /* Restore CPU state */
d72a19f7 5846 gen_helper_rfmci();
e06fcd75 5847 gen_sync_exception(ctx);
a42bd6cc
JM		 5848#endif
5849}
5eb7995e 5850
d9bce9d9 5851/* TLB management - PowerPC 405 implementation */
76a66253 5852/* tlbre */
c7697e1f 5853GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5854{
5855#if defined(CONFIG_USER_ONLY)
e06fcd75 5856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5857#else
76db3ba4 5858 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5860 return;
5861 }
5862 switch (rB(ctx->opcode)) {
5863 case 0:
74d37793 5864 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5865 break;
5866 case 1:
74d37793 5867 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5868 break;
5869 default:
e06fcd75 5870 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5871 break;
9a64fbe4 5872 }
76a66253
JM		 5873#endif
5874}
5875
d9bce9d9 5876/* tlbsx - tlbsx. */
c7697e1f 5877GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5878{
5879#if defined(CONFIG_USER_ONLY)
e06fcd75 5880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5881#else
74d37793 5882 TCGv t0;
76db3ba4 5883 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5884 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5885 return;
5886 }
74d37793 5887 t0 = tcg_temp_new();
76db3ba4 5888 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5889 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5890 tcg_temp_free(t0);
5891 if (Rc(ctx->opcode)) {
5892 int l1 = gen_new_label();
5893 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5894 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5895 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5896 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5897 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5898 gen_set_label(l1);
5899 }
76a66253 5900#endif
79aceca5
FB		 5901}
5902
76a66253 5903/* tlbwe */
c7697e1f 5904GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5905{
76a66253 5906#if defined(CONFIG_USER_ONLY)
e06fcd75 5907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5908#else
76db3ba4 5909 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5910 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5911 return;
5912 }
5913 switch (rB(ctx->opcode)) {
5914 case 0:
74d37793 5915 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5916 break;
5917 case 1:
74d37793 5918 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5919 break;
5920 default:
e06fcd75 5921 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5922 break;
9a64fbe4 5923 }
76a66253
JM		 5924#endif
5925}
5926
a4bb6c3e 5927/* TLB management - PowerPC 440 implementation */
5eb7995e 5928/* tlbre */
c7697e1f 5929GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5930{
5931#if defined(CONFIG_USER_ONLY)
e06fcd75 5932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5933#else
76db3ba4 5934 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5936 return;
5937 }
5938 switch (rB(ctx->opcode)) {
5939 case 0:
5eb7995e 5940 case 1:
5eb7995e 5941 case 2:
74d37793
AJ		 5942 {
5943 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5944 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5945 tcg_temp_free_i32(t0);
5946 }
5eb7995e
JM		 5947 break;
5948 default:
e06fcd75 5949 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 5950 break;
5951 }
5952#endif
5953}
5954
5955/* tlbsx - tlbsx. */
c7697e1f 5956GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5957{
5958#if defined(CONFIG_USER_ONLY)
e06fcd75 5959 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5960#else
74d37793 5961 TCGv t0;
76db3ba4 5962 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5963 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5964 return;
5965 }
74d37793 5966 t0 = tcg_temp_new();
76db3ba4 5967 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5968 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5969 tcg_temp_free(t0);
5970 if (Rc(ctx->opcode)) {
5971 int l1 = gen_new_label();
5972 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5973 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5974 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5975 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5976 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5977 gen_set_label(l1);
5978 }
5eb7995e
JM		 5979#endif
5980}
5981
5982/* tlbwe */
c7697e1f 5983GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5984{
5985#if defined(CONFIG_USER_ONLY)
e06fcd75 5986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 5987#else
76db3ba4 5988 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 5990 return;
5991 }
5992 switch (rB(ctx->opcode)) {
5993 case 0:
5eb7995e 5994 case 1:
5eb7995e 5995 case 2:
74d37793
AJ		 5996 {
5997 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5998 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5999 tcg_temp_free_i32(t0);
6000 }
5eb7995e
JM		 6001 break;
6002 default:
e06fcd75 6003 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6004 break;
6005 }
6006#endif
6007}
6008
76a66253 6009/* wrtee */
05332d70 6010GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6011{
6012#if defined(CONFIG_USER_ONLY)
e06fcd75 6013 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6014#else
6527f6ea 6015 TCGv t0;
76db3ba4 6016 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6018 return;
6019 }
6527f6ea
AJ		 6020 t0 = tcg_temp_new();
6021 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6022 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6023 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6024 tcg_temp_free(t0);
dee96f6c
JM		 6025 /* Stop translation to have a chance to raise an exception
6026 * if we just set msr_ee to 1
6027 */
e06fcd75 6028 gen_stop_exception(ctx);
76a66253
JM		 6029#endif
6030}
6031
6032/* wrteei */
05332d70 6033GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6034{
6035#if defined(CONFIG_USER_ONLY)
e06fcd75 6036 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6037#else
76db3ba4 6038 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6039 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6040 return;
6041 }
6527f6ea
AJ		 6042 if (ctx->opcode & 0x00010000) {
6043 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6044 /* Stop translation to have a chance to raise an exception */
e06fcd75 6045 gen_stop_exception(ctx);
6527f6ea 6046 } else {
1b6e5f99 6047 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6048 }
76a66253
JM		 6049#endif
6050}
6051
08e46e54 6052/* PowerPC 440 specific instructions */
76a66253
JM		 6053/* dlmzb */
6054GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6055{
ef0d51af
AJ		 6056 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6057 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6058 cpu_gpr[rB(ctx->opcode)], t0);
6059 tcg_temp_free_i32(t0);
76a66253
JM		 6060}
6061
6062/* mbar replaces eieio on 440 */
26370046 6063GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
76a66253
JM		 6064{
6065 /* interpreted as no-op */
6066}
6067
6068/* msync replaces sync on 440 */
0db1b20e 6069GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6070{
6071 /* interpreted as no-op */
6072}
6073
6074/* icbt */
c7697e1f 6075GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6076{
6077 /* interpreted as no-op */
6078 /* XXX: specification say this is treated as a load by the MMU
6079 * but does not generate any exception
6080 */
79aceca5
FB		 6081}
6082
a9d9eb8f
JM		 6083/*** Altivec vector extension ***/
6084/* Altivec registers moves */
a9d9eb8f 6085
564e571a
AJ		 6086static always_inline TCGv_ptr gen_avr_ptr(int reg)
6087{
e4704b3b 6088 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6089 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6090 return r;
6091}
6092
a9d9eb8f 6093#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6094GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6095{ \
fe1e5c53 6096 TCGv EA; \
a9d9eb8f 6097 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6098 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6099 return; \
6100 } \
76db3ba4 6101 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6102 EA = tcg_temp_new(); \
76db3ba4 6103 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6104 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6105 if (ctx->le_mode) { \
6106 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6107 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6108 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6109 } else { \
76db3ba4 6110 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6111 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6112 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6113 } \
6114 tcg_temp_free(EA); \
a9d9eb8f
JM		 6115}
6116
6117#define GEN_VR_STX(name, opc2, opc3) \
6118GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6119{ \
fe1e5c53 6120 TCGv EA; \
a9d9eb8f 6121 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6122 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6123 return; \
6124 } \
76db3ba4 6125 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6126 EA = tcg_temp_new(); \
76db3ba4 6127 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6128 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6129 if (ctx->le_mode) { \
6130 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6131 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6132 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6133 } else { \
76db3ba4 6134 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6135 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6136 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6137 } \
6138 tcg_temp_free(EA); \
a9d9eb8f
JM		 6139}
6140
cbfb6ae9
AJ		 6141#define GEN_VR_LVE(name, opc2, opc3) \
6142 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6143 { \
6144 TCGv EA; \
6145 TCGv_ptr rs; \
6146 if (unlikely(!ctx->altivec_enabled)) { \
6147 gen_exception(ctx, POWERPC_EXCP_VPU); \
6148 return; \
6149 } \
6150 gen_set_access_type(ctx, ACCESS_INT); \
6151 EA = tcg_temp_new(); \
6152 gen_addr_reg_index(ctx, EA); \
6153 rs = gen_avr_ptr(rS(ctx->opcode)); \
6154 gen_helper_lve##name (rs, EA); \
6155 tcg_temp_free(EA); \
6156 tcg_temp_free_ptr(rs); \
6157 }
6158
6159#define GEN_VR_STVE(name, opc2, opc3) \
6160 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6161 { \
6162 TCGv EA; \
6163 TCGv_ptr rs; \
6164 if (unlikely(!ctx->altivec_enabled)) { \
6165 gen_exception(ctx, POWERPC_EXCP_VPU); \
6166 return; \
6167 } \
6168 gen_set_access_type(ctx, ACCESS_INT); \
6169 EA = tcg_temp_new(); \
6170 gen_addr_reg_index(ctx, EA); \
6171 rs = gen_avr_ptr(rS(ctx->opcode)); \
6172 gen_helper_stve##name (rs, EA); \
6173 tcg_temp_free(EA); \
6174 tcg_temp_free_ptr(rs); \
6175 }
6176
fe1e5c53 6177GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6178/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6179GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6180
cbfb6ae9
AJ		 6181GEN_VR_LVE(bx, 0x07, 0x00);
6182GEN_VR_LVE(hx, 0x07, 0x01);
6183GEN_VR_LVE(wx, 0x07, 0x02);
6184
fe1e5c53 6185GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6186/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6187GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6188
cbfb6ae9
AJ		 6189GEN_VR_STVE(bx, 0x07, 0x04);
6190GEN_VR_STVE(hx, 0x07, 0x05);
6191GEN_VR_STVE(wx, 0x07, 0x06);
6192
bf8d8ded
AJ		 6193GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6194{
6195 TCGv_ptr rd;
6196 TCGv EA;
6197 if (unlikely(!ctx->altivec_enabled)) {
6198 gen_exception(ctx, POWERPC_EXCP_VPU);
6199 return;
6200 }
6201 EA = tcg_temp_new();
6202 gen_addr_reg_index(ctx, EA);
6203 rd = gen_avr_ptr(rD(ctx->opcode));
6204 gen_helper_lvsl(rd, EA);
6205 tcg_temp_free(EA);
6206 tcg_temp_free_ptr(rd);
6207}
6208
6209GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6210{
6211 TCGv_ptr rd;
6212 TCGv EA;
6213 if (unlikely(!ctx->altivec_enabled)) {
6214 gen_exception(ctx, POWERPC_EXCP_VPU);
6215 return;
6216 }
6217 EA = tcg_temp_new();
6218 gen_addr_reg_index(ctx, EA);
6219 rd = gen_avr_ptr(rD(ctx->opcode));
6220 gen_helper_lvsr(rd, EA);
6221 tcg_temp_free(EA);
6222 tcg_temp_free_ptr(rd);
6223}
6224
785f451b
AJ		 6225GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6226{
6227 TCGv_i32 t;
6228 if (unlikely(!ctx->altivec_enabled)) {
6229 gen_exception(ctx, POWERPC_EXCP_VPU);
6230 return;
6231 }
6232 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6233 t = tcg_temp_new_i32();
6234 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6235 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6236 tcg_temp_free_i32(t);
785f451b
AJ		 6237}
6238
6239GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6240{
6e87b7c7 6241 TCGv_ptr p;
785f451b
AJ		 6242 if (unlikely(!ctx->altivec_enabled)) {
6243 gen_exception(ctx, POWERPC_EXCP_VPU);
6244 return;
6245 }
6e87b7c7
AJ		 6246 p = gen_avr_ptr(rD(ctx->opcode));
6247 gen_helper_mtvscr(p);
6248 tcg_temp_free_ptr(p);
785f451b
AJ		 6249}
6250
7a9b96cf
AJ		 6251/* Logical operations */
6252#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6253GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6254{ \
6255 if (unlikely(!ctx->altivec_enabled)) { \
6256 gen_exception(ctx, POWERPC_EXCP_VPU); \
6257 return; \
6258 } \
6259 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6260 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6261}
6262
6263GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6264GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6265GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6266GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6267GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6268
8e27dd6f
AJ		 6269#define GEN_VXFORM(name, opc2, opc3) \
6270GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6271{ \
6272 TCGv_ptr ra, rb, rd; \
6273 if (unlikely(!ctx->altivec_enabled)) { \
6274 gen_exception(ctx, POWERPC_EXCP_VPU); \
6275 return; \
6276 } \
6277 ra = gen_avr_ptr(rA(ctx->opcode)); \
6278 rb = gen_avr_ptr(rB(ctx->opcode)); \
6279 rd = gen_avr_ptr(rD(ctx->opcode)); \
6280 gen_helper_##name (rd, ra, rb); \
6281 tcg_temp_free_ptr(ra); \
6282 tcg_temp_free_ptr(rb); \
6283 tcg_temp_free_ptr(rd); \
6284}
6285
7872c51c
AJ		 6286GEN_VXFORM(vaddubm, 0, 0);
6287GEN_VXFORM(vadduhm, 0, 1);
6288GEN_VXFORM(vadduwm, 0, 2);
6289GEN_VXFORM(vsububm, 0, 16);
6290GEN_VXFORM(vsubuhm, 0, 17);
6291GEN_VXFORM(vsubuwm, 0, 18);
e4039339
AJ		 6292GEN_VXFORM(vmaxub, 1, 0);
6293GEN_VXFORM(vmaxuh, 1, 1);
6294GEN_VXFORM(vmaxuw, 1, 2);
6295GEN_VXFORM(vmaxsb, 1, 4);
6296GEN_VXFORM(vmaxsh, 1, 5);
6297GEN_VXFORM(vmaxsw, 1, 6);
6298GEN_VXFORM(vminub, 1, 8);
6299GEN_VXFORM(vminuh, 1, 9);
6300GEN_VXFORM(vminuw, 1, 10);
6301GEN_VXFORM(vminsb, 1, 12);
6302GEN_VXFORM(vminsh, 1, 13);
6303GEN_VXFORM(vminsw, 1, 14);
fab3cbe9
AJ		 6304GEN_VXFORM(vavgub, 1, 16);
6305GEN_VXFORM(vavguh, 1, 17);
6306GEN_VXFORM(vavguw, 1, 18);
6307GEN_VXFORM(vavgsb, 1, 20);
6308GEN_VXFORM(vavgsh, 1, 21);
6309GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 6310GEN_VXFORM(vmrghb, 6, 0);
6311GEN_VXFORM(vmrghh, 6, 1);
6312GEN_VXFORM(vmrghw, 6, 2);
6313GEN_VXFORM(vmrglb, 6, 4);
6314GEN_VXFORM(vmrglh, 6, 5);
6315GEN_VXFORM(vmrglw, 6, 6);
2c277908
AJ		 6316GEN_VXFORM(vmuloub, 4, 0);
6317GEN_VXFORM(vmulouh, 4, 1);
6318GEN_VXFORM(vmulosb, 4, 4);
6319GEN_VXFORM(vmulosh, 4, 5);
6320GEN_VXFORM(vmuleub, 4, 8);
6321GEN_VXFORM(vmuleuh, 4, 9);
6322GEN_VXFORM(vmulesb, 4, 12);
6323GEN_VXFORM(vmulesh, 4, 13);
d79f0809
AJ		 6324GEN_VXFORM(vslb, 2, 4);
6325GEN_VXFORM(vslh, 2, 5);
6326GEN_VXFORM(vslw, 2, 6);
07ef34c3
AJ		 6327GEN_VXFORM(vsrb, 2, 8);
6328GEN_VXFORM(vsrh, 2, 9);
6329GEN_VXFORM(vsrw, 2, 10);
6330GEN_VXFORM(vsrab, 2, 12);
6331GEN_VXFORM(vsrah, 2, 13);
6332GEN_VXFORM(vsraw, 2, 14);
7b239bec
AJ		 6333GEN_VXFORM(vslo, 6, 16);
6334GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 6335GEN_VXFORM(vaddcuw, 0, 6);
6336GEN_VXFORM(vsubcuw, 0, 22);
5ab09f33
AJ		 6337GEN_VXFORM(vaddubs, 0, 8);
6338GEN_VXFORM(vadduhs, 0, 9);
6339GEN_VXFORM(vadduws, 0, 10);
6340GEN_VXFORM(vaddsbs, 0, 12);
6341GEN_VXFORM(vaddshs, 0, 13);
6342GEN_VXFORM(vaddsws, 0, 14);
6343GEN_VXFORM(vsububs, 0, 24);
6344GEN_VXFORM(vsubuhs, 0, 25);
6345GEN_VXFORM(vsubuws, 0, 26);
6346GEN_VXFORM(vsubsbs, 0, 28);
6347GEN_VXFORM(vsubshs, 0, 29);
6348GEN_VXFORM(vsubsws, 0, 30);
5e1d0985
AJ		 6349GEN_VXFORM(vrlb, 2, 0);
6350GEN_VXFORM(vrlh, 2, 1);
6351GEN_VXFORM(vrlw, 2, 2);
d9430add
AJ		 6352GEN_VXFORM(vsl, 2, 7);
6353GEN_VXFORM(vsr, 2, 11);
5335a145
AJ		 6354GEN_VXFORM(vpkuhum, 7, 0);
6355GEN_VXFORM(vpkuwum, 7, 1);
6356GEN_VXFORM(vpkuhus, 7, 2);
6357GEN_VXFORM(vpkuwus, 7, 3);
6358GEN_VXFORM(vpkshus, 7, 4);
6359GEN_VXFORM(vpkswus, 7, 5);
6360GEN_VXFORM(vpkshss, 7, 6);
6361GEN_VXFORM(vpkswss, 7, 7);
1dd9ffb9 6362GEN_VXFORM(vpkpx, 7, 12);
8142cddd
AJ		 6363GEN_VXFORM(vsum4ubs, 4, 24);
6364GEN_VXFORM(vsum4sbs, 4, 28);
6365GEN_VXFORM(vsum4shs, 4, 25);
6366GEN_VXFORM(vsum2sws, 4, 26);
6367GEN_VXFORM(vsumsws, 4, 30);
56fdd213
AJ		 6368GEN_VXFORM(vaddfp, 5, 0);
6369GEN_VXFORM(vsubfp, 5, 1);
1536ff64
AJ		 6370GEN_VXFORM(vmaxfp, 5, 16);
6371GEN_VXFORM(vminfp, 5, 17);
fab3cbe9 6372
0cbcd906
AJ		 6373#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6374 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6375 { \
6376 TCGv_ptr ra, rb, rd; \
6377 if (unlikely(!ctx->altivec_enabled)) { \
6378 gen_exception(ctx, POWERPC_EXCP_VPU); \
6379 return; \
6380 } \
6381 ra = gen_avr_ptr(rA(ctx->opcode)); \
6382 rb = gen_avr_ptr(rB(ctx->opcode)); \
6383 rd = gen_avr_ptr(rD(ctx->opcode)); \
6384 gen_helper_##opname (rd, ra, rb); \
6385 tcg_temp_free_ptr(ra); \
6386 tcg_temp_free_ptr(rb); \
6387 tcg_temp_free_ptr(rd); \
6388 }
6389
6390#define GEN_VXRFORM(name, opc2, opc3) \
6391 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6392 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6393
1add6e23
AJ		 6394GEN_VXRFORM(vcmpequb, 3, 0)
6395GEN_VXRFORM(vcmpequh, 3, 1)
6396GEN_VXRFORM(vcmpequw, 3, 2)
6397GEN_VXRFORM(vcmpgtsb, 3, 12)
6398GEN_VXRFORM(vcmpgtsh, 3, 13)
6399GEN_VXRFORM(vcmpgtsw, 3, 14)
6400GEN_VXRFORM(vcmpgtub, 3, 8)
6401GEN_VXRFORM(vcmpgtuh, 3, 9)
6402GEN_VXRFORM(vcmpgtuw, 3, 10)
819ca121
AJ		 6403GEN_VXRFORM(vcmpeqfp, 3, 3)
6404GEN_VXRFORM(vcmpgefp, 3, 7)
6405GEN_VXRFORM(vcmpgtfp, 3, 11)
6406GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 6407
c026766b
AJ		 6408#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6409 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6410 { \
6411 TCGv_ptr rd; \
6412 TCGv_i32 simm; \
6413 if (unlikely(!ctx->altivec_enabled)) { \
6414 gen_exception(ctx, POWERPC_EXCP_VPU); \
6415 return; \
6416 } \
6417 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6418 rd = gen_avr_ptr(rD(ctx->opcode)); \
6419 gen_helper_##name (rd, simm); \
6420 tcg_temp_free_i32(simm); \
6421 tcg_temp_free_ptr(rd); \
6422 }
6423
6424GEN_VXFORM_SIMM(vspltisb, 6, 12);
6425GEN_VXFORM_SIMM(vspltish, 6, 13);
6426GEN_VXFORM_SIMM(vspltisw, 6, 14);
6427
de5f2484
AJ		 6428#define GEN_VXFORM_NOA(name, opc2, opc3) \
6429 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6430 { \
6431 TCGv_ptr rb, rd; \
6432 if (unlikely(!ctx->altivec_enabled)) { \
6433 gen_exception(ctx, POWERPC_EXCP_VPU); \
6434 return; \
6435 } \
6436 rb = gen_avr_ptr(rB(ctx->opcode)); \
6437 rd = gen_avr_ptr(rD(ctx->opcode)); \
6438 gen_helper_##name (rd, rb); \
6439 tcg_temp_free_ptr(rb); \
6440 tcg_temp_free_ptr(rd); \
6441 }
6442
6cf1c6e5
AJ		 6443GEN_VXFORM_NOA(vupkhsb, 7, 8);
6444GEN_VXFORM_NOA(vupkhsh, 7, 9);
6445GEN_VXFORM_NOA(vupklsb, 7, 10);
6446GEN_VXFORM_NOA(vupklsh, 7, 11);
79f85c3a
AJ		 6447GEN_VXFORM_NOA(vupkhpx, 7, 13);
6448GEN_VXFORM_NOA(vupklpx, 7, 15);
bdfbac35 6449GEN_VXFORM_NOA(vrefp, 5, 4);
071fc3b1 6450GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
b580763f 6451GEN_VXFORM_NOA(vlogefp, 5, 7);
f6b19645
AJ		 6452GEN_VXFORM_NOA(vrfim, 5, 8);
6453GEN_VXFORM_NOA(vrfin, 5, 9);
6454GEN_VXFORM_NOA(vrfip, 5, 10);
6455GEN_VXFORM_NOA(vrfiz, 5, 11);
79f85c3a 6456
21d21583
AJ		 6457#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6458 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6459 { \
6460 TCGv_ptr rd; \
6461 TCGv_i32 simm; \
6462 if (unlikely(!ctx->altivec_enabled)) { \
6463 gen_exception(ctx, POWERPC_EXCP_VPU); \
6464 return; \
6465 } \
6466 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6467 rd = gen_avr_ptr(rD(ctx->opcode)); \
6468 gen_helper_##name (rd, simm); \
6469 tcg_temp_free_i32(simm); \
6470 tcg_temp_free_ptr(rd); \
6471 }
6472
27a4edb3
AJ		 6473#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6474 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6475 { \
6476 TCGv_ptr rb, rd; \
6477 TCGv_i32 uimm; \
6478 if (unlikely(!ctx->altivec_enabled)) { \
6479 gen_exception(ctx, POWERPC_EXCP_VPU); \
6480 return; \
6481 } \
6482 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6483 rb = gen_avr_ptr(rB(ctx->opcode)); \
6484 rd = gen_avr_ptr(rD(ctx->opcode)); \
6485 gen_helper_##name (rd, rb, uimm); \
6486 tcg_temp_free_i32(uimm); \
6487 tcg_temp_free_ptr(rb); \
6488 tcg_temp_free_ptr(rd); \
6489 }
6490
e4e6bee7
AJ		 6491GEN_VXFORM_UIMM(vspltb, 6, 8);
6492GEN_VXFORM_UIMM(vsplth, 6, 9);
6493GEN_VXFORM_UIMM(vspltw, 6, 10);
e140632e
AJ		 6494GEN_VXFORM_UIMM(vcfux, 5, 12);
6495GEN_VXFORM_UIMM(vcfsx, 5, 13);
875b31db
AJ		 6496GEN_VXFORM_UIMM(vctuxs, 5, 14);
6497GEN_VXFORM_UIMM(vctsxs, 5, 15);
e4e6bee7 6498
cd633b10
AJ		 6499GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6500{
6501 TCGv_ptr ra, rb, rd;
fce5ecb7 6502 TCGv_i32 sh;
cd633b10
AJ		 6503 if (unlikely(!ctx->altivec_enabled)) {
6504 gen_exception(ctx, POWERPC_EXCP_VPU);
6505 return;
6506 }
6507 ra = gen_avr_ptr(rA(ctx->opcode));
6508 rb = gen_avr_ptr(rB(ctx->opcode));
6509 rd = gen_avr_ptr(rD(ctx->opcode));
6510 sh = tcg_const_i32(VSH(ctx->opcode));
6511 gen_helper_vsldoi (rd, ra, rb, sh);
6512 tcg_temp_free_ptr(ra);
6513 tcg_temp_free_ptr(rb);
6514 tcg_temp_free_ptr(rd);
fce5ecb7 6515 tcg_temp_free_i32(sh);
cd633b10
AJ		 6516}
6517
707cec33
AJ		 6518#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6519 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6520 { \
6521 TCGv_ptr ra, rb, rc, rd; \
6522 if (unlikely(!ctx->altivec_enabled)) { \
6523 gen_exception(ctx, POWERPC_EXCP_VPU); \
6524 return; \
6525 } \
6526 ra = gen_avr_ptr(rA(ctx->opcode)); \
6527 rb = gen_avr_ptr(rB(ctx->opcode)); \
6528 rc = gen_avr_ptr(rC(ctx->opcode)); \
6529 rd = gen_avr_ptr(rD(ctx->opcode)); \
6530 if (Rc(ctx->opcode)) { \
6531 gen_helper_##name1 (rd, ra, rb, rc); \
6532 } else { \
6533 gen_helper_##name0 (rd, ra, rb, rc); \
6534 } \
6535 tcg_temp_free_ptr(ra); \
6536 tcg_temp_free_ptr(rb); \
6537 tcg_temp_free_ptr(rc); \
6538 tcg_temp_free_ptr(rd); \
6539 }
6540
b161ae27
AJ		 6541GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6542
bcd2ee23
AJ		 6543GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6544{
6545 TCGv_ptr ra, rb, rc, rd;
6546 if (unlikely(!ctx->altivec_enabled)) {
6547 gen_exception(ctx, POWERPC_EXCP_VPU);
6548 return;
6549 }
6550 ra = gen_avr_ptr(rA(ctx->opcode));
6551 rb = gen_avr_ptr(rB(ctx->opcode));
6552 rc = gen_avr_ptr(rC(ctx->opcode));
6553 rd = gen_avr_ptr(rD(ctx->opcode));
6554 gen_helper_vmladduhm(rd, ra, rb, rc);
6555 tcg_temp_free_ptr(ra);
6556 tcg_temp_free_ptr(rb);
6557 tcg_temp_free_ptr(rc);
6558 tcg_temp_free_ptr(rd);
6559}
6560
b04ae981 6561GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 6562GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 6563GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 6564GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 6565GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 6566
0487d6a8 6567/*** SPE extension ***/
0487d6a8 6568/* Register moves */
3cd7d1dd 6569
a7812ae4 6570static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6571#if defined(TARGET_PPC64)
6572 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6573#else
36aa55dc 6574 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6575#endif
f78fb44e 6576}
3cd7d1dd 6577
a7812ae4 6578static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6579#if defined(TARGET_PPC64)
6580 tcg_gen_mov_i64(cpu_gpr[reg], t);
6581#else
a7812ae4 6582 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6583 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6584 tcg_gen_shri_i64(tmp, t, 32);
6585 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6586 tcg_temp_free_i64(tmp);
3cd7d1dd 6587#endif
f78fb44e 6588}
3cd7d1dd 6589
0487d6a8
JM		 6590#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6591GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6592{ \
6593 if (Rc(ctx->opcode)) \
6594 gen_##name1(ctx); \
6595 else \
6596 gen_##name0(ctx); \
6597}
6598
6599/* Handler for undefined SPE opcodes */
b068d6a7 6600static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6601{
e06fcd75 6602 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 6603}
6604
57951c27
AJ		 6605/* SPE logic */
6606#if defined(TARGET_PPC64)
6607#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6608static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6609{ \
6610 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6611 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6612 return; \
6613 } \
57951c27
AJ		 6614 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6615 cpu_gpr[rB(ctx->opcode)]); \
6616}
6617#else
6618#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6619static always_inline void gen_##name (DisasContext *ctx) \
6620{ \
6621 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6622 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6623 return; \
6624 } \
6625 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6626 cpu_gpr[rB(ctx->opcode)]); \
6627 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6628 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6629}
57951c27
AJ		 6630#endif
6631
6632GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6633GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6634GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6635GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6636GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6637GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6638GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6639GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6640
57951c27
AJ		 6641/* SPE logic immediate */
6642#if defined(TARGET_PPC64)
6643#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6644static always_inline void gen_##name (DisasContext *ctx) \
6645{ \
6646 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6647 gen_exception(ctx, POWERPC_EXCP_APU); \
3d3a6a0a
AJ		 6648 return; \
6649 } \
a7812ae4
PB		 6650 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6651 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6652 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6653 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6654 tcg_opi(t0, t0, rB(ctx->opcode)); \
6655 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6656 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6657 tcg_temp_free_i64(t2); \
57951c27
AJ		 6658 tcg_opi(t1, t1, rB(ctx->opcode)); \
6659 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6660 tcg_temp_free_i32(t0); \
6661 tcg_temp_free_i32(t1); \
3d3a6a0a 6662}
57951c27
AJ		 6663#else
6664#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6665static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6666{ \
6667 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6668 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6669 return; \
6670 } \
57951c27
AJ		 6671 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6672 rB(ctx->opcode)); \
6673 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6674 rB(ctx->opcode)); \
0487d6a8 6675}
57951c27
AJ		 6676#endif
6677GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6678GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6679GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6680GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6681
57951c27
AJ		 6682/* SPE arithmetic */
6683#if defined(TARGET_PPC64)
6684#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6685static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6686{ \
6687 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6688 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6689 return; \
6690 } \
a7812ae4
PB		 6691 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6692 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6693 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6694 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6695 tcg_op(t0, t0); \
6696 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6697 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6698 tcg_temp_free_i64(t2); \
57951c27
AJ		 6699 tcg_op(t1, t1); \
6700 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6701 tcg_temp_free_i32(t0); \
6702 tcg_temp_free_i32(t1); \
0487d6a8 6703}
57951c27 6704#else
a7812ae4 6705#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6706static always_inline void gen_##name (DisasContext *ctx) \
6707{ \
6708 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6709 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6710 return; \
6711 } \
6712 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6713 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6714}
6715#endif
0487d6a8 6716
a7812ae4 6717static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6718{
6719 int l1 = gen_new_label();
6720 int l2 = gen_new_label();
0487d6a8 6721
57951c27
AJ		 6722 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6723 tcg_gen_neg_i32(ret, arg1);
6724 tcg_gen_br(l2);
6725 gen_set_label(l1);
a7812ae4 6726 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6727 gen_set_label(l2);
6728}
6729GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6730GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6731GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6732GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6733static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6734{
57951c27
AJ		 6735 tcg_gen_addi_i32(ret, arg1, 0x8000);
6736 tcg_gen_ext16u_i32(ret, ret);
6737}
6738GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6739GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6740GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6741
57951c27
AJ		 6742#if defined(TARGET_PPC64)
6743#define GEN_SPEOP_ARITH2(name, tcg_op) \
6744static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6745{ \
6746 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6747 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6748 return; \
6749 } \
a7812ae4
PB		 6750 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6751 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6752 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
501e23c4 6753 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6754 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6755 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6756 tcg_op(t0, t0, t2); \
6757 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6758 tcg_gen_trunc_i64_i32(t1, t3); \
6759 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6760 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6761 tcg_temp_free_i64(t3); \
57951c27 6762 tcg_op(t1, t1, t2); \
a7812ae4 6763 tcg_temp_free_i32(t2); \
57951c27 6764 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6765 tcg_temp_free_i32(t0); \
6766 tcg_temp_free_i32(t1); \
0487d6a8 6767}
57951c27
AJ		 6768#else
6769#define GEN_SPEOP_ARITH2(name, tcg_op) \
6770static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6771{ \
6772 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6773 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6774 return; \
6775 } \
57951c27
AJ		 6776 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6777 cpu_gpr[rB(ctx->opcode)]); \
6778 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6779 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6780}
57951c27 6781#endif
0487d6a8 6782
a7812ae4 6783static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6784{
a7812ae4 6785 TCGv_i32 t0;
57951c27 6786 int l1, l2;
0487d6a8 6787
57951c27
AJ		 6788 l1 = gen_new_label();
6789 l2 = gen_new_label();
a7812ae4 6790 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6791 /* No error here: 6 bits are used */
6792 tcg_gen_andi_i32(t0, arg2, 0x3F);
6793 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6794 tcg_gen_shr_i32(ret, arg1, t0);
6795 tcg_gen_br(l2);
6796 gen_set_label(l1);
6797 tcg_gen_movi_i32(ret, 0);
6798 tcg_gen_br(l2);
a7812ae4 6799 tcg_temp_free_i32(t0);
57951c27
AJ		 6800}
6801GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6802static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6803{
a7812ae4 6804 TCGv_i32 t0;
57951c27
AJ		 6805 int l1, l2;
6806
6807 l1 = gen_new_label();
6808 l2 = gen_new_label();
a7812ae4 6809 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6810 /* No error here: 6 bits are used */
6811 tcg_gen_andi_i32(t0, arg2, 0x3F);
6812 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6813 tcg_gen_sar_i32(ret, arg1, t0);
6814 tcg_gen_br(l2);
6815 gen_set_label(l1);
6816 tcg_gen_movi_i32(ret, 0);
6817 tcg_gen_br(l2);
a7812ae4 6818 tcg_temp_free_i32(t0);
57951c27
AJ		 6819}
6820GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6821static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6822{
a7812ae4 6823 TCGv_i32 t0;
57951c27
AJ		 6824 int l1, l2;
6825
6826 l1 = gen_new_label();
6827 l2 = gen_new_label();
a7812ae4 6828 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6829 /* No error here: 6 bits are used */
6830 tcg_gen_andi_i32(t0, arg2, 0x3F);
6831 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6832 tcg_gen_shl_i32(ret, arg1, t0);
6833 tcg_gen_br(l2);
6834 gen_set_label(l1);
6835 tcg_gen_movi_i32(ret, 0);
6836 tcg_gen_br(l2);
a7812ae4 6837 tcg_temp_free_i32(t0);
57951c27
AJ		 6838}
6839GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6840static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6841{
a7812ae4 6842 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6843 tcg_gen_andi_i32(t0, arg2, 0x1F);
6844 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6845 tcg_temp_free_i32(t0);
57951c27
AJ		 6846}
6847GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6848static always_inline void gen_evmergehi (DisasContext *ctx)
6849{
6850 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6851 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6852 return;
6853 }
6854#if defined(TARGET_PPC64)
a7812ae4
PB		 6855 TCGv t0 = tcg_temp_new();
6856 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6857 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6858 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6859 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6860 tcg_temp_free(t0);
6861 tcg_temp_free(t1);
6862#else
6863 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6864 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6865#endif
6866}
6867GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6868static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6869{
57951c27
AJ		 6870 tcg_gen_sub_i32(ret, arg2, arg1);
6871}
6872GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6873
57951c27
AJ		 6874/* SPE arithmetic immediate */
6875#if defined(TARGET_PPC64)
6876#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6877static always_inline void gen_##name (DisasContext *ctx) \
6878{ \
6879 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6880 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6881 return; \
6882 } \
a7812ae4
PB		 6883 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6884 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6885 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6886 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6887 tcg_op(t0, t0, rA(ctx->opcode)); \
6888 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6889 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 6890 tcg_temp_free_i64(t2); \
57951c27
AJ		 6891 tcg_op(t1, t1, rA(ctx->opcode)); \
6892 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6893 tcg_temp_free_i32(t0); \
6894 tcg_temp_free_i32(t1); \
57951c27
AJ		 6895}
6896#else
6897#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6898static always_inline void gen_##name (DisasContext *ctx) \
6899{ \
6900 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6901 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6902 return; \
6903 } \
6904 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6905 rA(ctx->opcode)); \
6906 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6907 rA(ctx->opcode)); \
6908}
6909#endif
6910GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6911GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6912
6913/* SPE comparison */
6914#if defined(TARGET_PPC64)
6915#define GEN_SPEOP_COMP(name, tcg_cond) \
6916static always_inline void gen_##name (DisasContext *ctx) \
6917{ \
6918 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6919 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6920 return; \
6921 } \
6922 int l1 = gen_new_label(); \
6923 int l2 = gen_new_label(); \
6924 int l3 = gen_new_label(); \
6925 int l4 = gen_new_label(); \
a7812ae4
PB		 6926 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6927 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6928 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6929 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6930 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6931 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6932 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6933 tcg_gen_br(l2); \
6934 gen_set_label(l1); \
6935 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6936 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6937 gen_set_label(l2); \
6938 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6939 tcg_gen_trunc_i64_i32(t0, t2); \
6940 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6941 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6942 tcg_temp_free_i64(t2); \
57951c27
AJ		 6943 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6944 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6945 ~(CRF_CH | CRF_CH_AND_CL)); \
6946 tcg_gen_br(l4); \
6947 gen_set_label(l3); \
6948 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6949 CRF_CH | CRF_CH_OR_CL); \
6950 gen_set_label(l4); \
a7812ae4
PB		 6951 tcg_temp_free_i32(t0); \
6952 tcg_temp_free_i32(t1); \
57951c27
AJ		 6953}
6954#else
6955#define GEN_SPEOP_COMP(name, tcg_cond) \
6956static always_inline void gen_##name (DisasContext *ctx) \
6957{ \
6958 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6959 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6960 return; \
6961 } \
6962 int l1 = gen_new_label(); \
6963 int l2 = gen_new_label(); \
6964 int l3 = gen_new_label(); \
6965 int l4 = gen_new_label(); \
6966 \
6967 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6968 cpu_gpr[rB(ctx->opcode)], l1); \
6969 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6970 tcg_gen_br(l2); \
6971 gen_set_label(l1); \
6972 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6973 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6974 gen_set_label(l2); \
6975 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6976 cpu_gprh[rB(ctx->opcode)], l3); \
6977 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6978 ~(CRF_CH | CRF_CH_AND_CL)); \
6979 tcg_gen_br(l4); \
6980 gen_set_label(l3); \
6981 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6982 CRF_CH | CRF_CH_OR_CL); \
6983 gen_set_label(l4); \
6984}
6985#endif
6986GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6987GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6988GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6989GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6990GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6991
6992/* SPE misc */
6993static always_inline void gen_brinc (DisasContext *ctx)
6994{
6995 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6996 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6997 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6998}
57951c27
AJ		 6999static always_inline void gen_evmergelo (DisasContext *ctx)
7000{
7001 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7002 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7003 return;
7004 }
7005#if defined(TARGET_PPC64)
a7812ae4
PB		 7006 TCGv t0 = tcg_temp_new();
7007 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7008 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7009 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7010 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7011 tcg_temp_free(t0);
7012 tcg_temp_free(t1);
7013#else
7014 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7015 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7016#endif
7017}
7018static always_inline void gen_evmergehilo (DisasContext *ctx)
7019{
7020 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7021 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7022 return;
7023 }
7024#if defined(TARGET_PPC64)
a7812ae4
PB		 7025 TCGv t0 = tcg_temp_new();
7026 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7027 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7028 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7029 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7030 tcg_temp_free(t0);
7031 tcg_temp_free(t1);
7032#else
7033 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7034 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7035#endif
7036}
7037static always_inline void gen_evmergelohi (DisasContext *ctx)
7038{
7039 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7040 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7041 return;
7042 }
7043#if defined(TARGET_PPC64)
a7812ae4
PB		 7044 TCGv t0 = tcg_temp_new();
7045 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7046 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7047 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7048 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7049 tcg_temp_free(t0);
7050 tcg_temp_free(t1);
7051#else
7052 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7053 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7054#endif
7055}
7056static always_inline void gen_evsplati (DisasContext *ctx)
7057{
38d14952 7058 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 7059
57951c27 7060#if defined(TARGET_PPC64)
38d14952 7061 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7062#else
7063 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7064 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7065#endif
7066}
b068d6a7 7067static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 7068{
38d14952 7069 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 7070
57951c27 7071#if defined(TARGET_PPC64)
38d14952 7072 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7073#else
7074 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7075 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7076#endif
0487d6a8
JM		 7077}
7078
57951c27
AJ		 7079static always_inline void gen_evsel (DisasContext *ctx)
7080{
7081 int l1 = gen_new_label();
7082 int l2 = gen_new_label();
7083 int l3 = gen_new_label();
7084 int l4 = gen_new_label();
a7812ae4 7085 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 7086#if defined(TARGET_PPC64)
a7812ae4
PB		 7087 TCGv t1 = tcg_temp_local_new();
7088 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 7089#endif
7090 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7091 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7092#if defined(TARGET_PPC64)
7093 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7094#else
7095 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7096#endif
7097 tcg_gen_br(l2);
7098 gen_set_label(l1);
7099#if defined(TARGET_PPC64)
7100 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7101#else
7102 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7103#endif
7104 gen_set_label(l2);
7105 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7106 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7107#if defined(TARGET_PPC64)
7108 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7109#else
7110 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7111#endif
7112 tcg_gen_br(l4);
7113 gen_set_label(l3);
7114#if defined(TARGET_PPC64)
7115 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7116#else
7117 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7118#endif
7119 gen_set_label(l4);
a7812ae4 7120 tcg_temp_free_i32(t0);
57951c27
AJ		 7121#if defined(TARGET_PPC64)
7122 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7123 tcg_temp_free(t1);
7124 tcg_temp_free(t2);
7125#endif
7126}
7127GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7128{
7129 gen_evsel(ctx);
7130}
7131GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7132{
7133 gen_evsel(ctx);
7134}
7135GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7136{
7137 gen_evsel(ctx);
7138}
7139GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7140{
7141 gen_evsel(ctx);
7142}
0487d6a8
JM		 7143
7144GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7145GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7146GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7147GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7148GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7149GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7150GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7151GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7152GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7153GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7154GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7155GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7156GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7157GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7158GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7159GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7160GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7161GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7162GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7163GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7164GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7165GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7166GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7167GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7168GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7169
6a6ae23f 7170/* SPE load and stores */
76db3ba4 7171static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 7172{
7173 target_ulong uimm = rB(ctx->opcode);
7174
76db3ba4 7175 if (rA(ctx->opcode) == 0) {
6a6ae23f 7176 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 7177 } else {
6a6ae23f 7178 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
76db3ba4
AJ		 7179#if defined(TARGET_PPC64)
7180 if (!ctx->sf_mode) {
7181 tcg_gen_ext32u_tl(EA, EA);
7182 }
7183#endif
7184 }
0487d6a8 7185}
6a6ae23f
AJ		 7186
7187static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7188{
7189#if defined(TARGET_PPC64)
76db3ba4 7190 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7191#else
7192 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 7193 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 7194 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7195 tcg_gen_shri_i64(t0, t0, 32);
7196 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7197 tcg_temp_free_i64(t0);
7198#endif
0487d6a8 7199}
6a6ae23f
AJ		 7200
7201static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7202{
0487d6a8 7203#if defined(TARGET_PPC64)
6a6ae23f 7204 TCGv t0 = tcg_temp_new();
76db3ba4 7205 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 7206 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 7207 gen_addr_add(ctx, addr, addr, 4);
7208 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 7209 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7210 tcg_temp_free(t0);
7211#else
76db3ba4
AJ		 7212 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7213 gen_addr_add(ctx, addr, addr, 4);
7214 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 7215#endif
0487d6a8 7216}
6a6ae23f
AJ		 7217
7218static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7219{
7220 TCGv t0 = tcg_temp_new();
7221#if defined(TARGET_PPC64)
76db3ba4 7222 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7223 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7224 gen_addr_add(ctx, addr, addr, 2);
7225 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7226 tcg_gen_shli_tl(t0, t0, 32);
7227 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7228 gen_addr_add(ctx, addr, addr, 2);
7229 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7230 tcg_gen_shli_tl(t0, t0, 16);
7231 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7232 gen_addr_add(ctx, addr, addr, 2);
7233 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7234 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7235#else
76db3ba4 7236 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7237 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7238 gen_addr_add(ctx, addr, addr, 2);
7239 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7240 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7241 gen_addr_add(ctx, addr, addr, 2);
7242 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7243 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7244 gen_addr_add(ctx, addr, addr, 2);
7245 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7246 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7247#endif
6a6ae23f 7248 tcg_temp_free(t0);
0487d6a8
JM		 7249}
7250
6a6ae23f
AJ		 7251static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7252{
7253 TCGv t0 = tcg_temp_new();
76db3ba4 7254 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7255#if defined(TARGET_PPC64)
7256 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7257 tcg_gen_shli_tl(t0, t0, 16);
7258 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7259#else
7260 tcg_gen_shli_tl(t0, t0, 16);
7261 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7262 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7263#endif
7264 tcg_temp_free(t0);
0487d6a8
JM		 7265}
7266
6a6ae23f
AJ		 7267static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7268{
7269 TCGv t0 = tcg_temp_new();
76db3ba4 7270 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7271#if defined(TARGET_PPC64)
7272 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7273 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7274#else
7275 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7276 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7277#endif
7278 tcg_temp_free(t0);
0487d6a8
JM		 7279}
7280
6a6ae23f
AJ		 7281static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7282{
7283 TCGv t0 = tcg_temp_new();
76db3ba4 7284 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7285#if defined(TARGET_PPC64)
7286 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7287 tcg_gen_ext32u_tl(t0, t0);
7288 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7289#else
7290 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7291 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7292#endif
7293 tcg_temp_free(t0);
7294}
7295
7296static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7297{
7298 TCGv t0 = tcg_temp_new();
7299#if defined(TARGET_PPC64)
76db3ba4 7300 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7301 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7302 gen_addr_add(ctx, addr, addr, 2);
7303 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7304 tcg_gen_shli_tl(t0, t0, 16);
7305 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7306#else
76db3ba4 7307 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7308 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7309 gen_addr_add(ctx, addr, addr, 2);
7310 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7311 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7312#endif
7313 tcg_temp_free(t0);
7314}
7315
7316static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7317{
7318#if defined(TARGET_PPC64)
7319 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 7320 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7321 gen_addr_add(ctx, addr, addr, 2);
7322 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7323 tcg_gen_shli_tl(t0, t0, 32);
7324 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7325 tcg_temp_free(t0);
7326#else
76db3ba4
AJ		 7327 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7328 gen_addr_add(ctx, addr, addr, 2);
7329 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7330#endif
7331}
7332
7333static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7334{
7335#if defined(TARGET_PPC64)
7336 TCGv t0 = tcg_temp_new();
76db3ba4 7337 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 7338 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7339 gen_addr_add(ctx, addr, addr, 2);
7340 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7341 tcg_gen_shli_tl(t0, t0, 32);
7342 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7343 tcg_temp_free(t0);
7344#else
76db3ba4
AJ		 7345 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7346 gen_addr_add(ctx, addr, addr, 2);
7347 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7348#endif
7349}
7350
7351static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7352{
7353 TCGv t0 = tcg_temp_new();
76db3ba4 7354 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 7355#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7356 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7357 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7358#else
7359 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7360 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7361#endif
7362 tcg_temp_free(t0);
7363}
7364
7365static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7366{
7367 TCGv t0 = tcg_temp_new();
7368#if defined(TARGET_PPC64)
76db3ba4 7369 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7370 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7371 tcg_gen_shli_tl(t0, t0, 32);
7372 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7373 gen_addr_add(ctx, addr, addr, 2);
7374 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7375 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7376 tcg_gen_shli_tl(t0, t0, 16);
7377 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7378#else
76db3ba4 7379 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7380 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7381 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7382 gen_addr_add(ctx, addr, addr, 2);
7383 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7384 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7385 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 7386#endif
6a6ae23f
AJ		 7387 tcg_temp_free(t0);
7388}
7389
7390static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7391{
7392#if defined(TARGET_PPC64)
76db3ba4 7393 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 7394#else
6a6ae23f
AJ		 7395 TCGv_i64 t0 = tcg_temp_new_i64();
7396 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 7397 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 7398 tcg_temp_free_i64(t0);
7399#endif
7400}
7401
7402static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7403{
0487d6a8 7404#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7405 TCGv t0 = tcg_temp_new();
7406 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7407 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7408 tcg_temp_free(t0);
7409#else
76db3ba4 7410 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7411#endif
76db3ba4
AJ		 7412 gen_addr_add(ctx, addr, addr, 4);
7413 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7414}
7415
7416static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7417{
7418 TCGv t0 = tcg_temp_new();
7419#if defined(TARGET_PPC64)
7420 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7421#else
7422 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7423#endif
76db3ba4
AJ		 7424 gen_qemu_st16(ctx, t0, addr);
7425 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 7426#if defined(TARGET_PPC64)
7427 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7428 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7429#else
76db3ba4 7430 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7431#endif
76db3ba4 7432 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7433 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7434 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7435 tcg_temp_free(t0);
76db3ba4
AJ		 7436 gen_addr_add(ctx, addr, addr, 2);
7437 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7438}
7439
7440static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7441{
7442 TCGv t0 = tcg_temp_new();
7443#if defined(TARGET_PPC64)
7444 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7445#else
7446 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7447#endif
76db3ba4
AJ		 7448 gen_qemu_st16(ctx, t0, addr);
7449 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7450 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7451 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7452 tcg_temp_free(t0);
7453}
7454
7455static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7456{
7457#if defined(TARGET_PPC64)
7458 TCGv t0 = tcg_temp_new();
7459 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7460 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7461 tcg_temp_free(t0);
7462#else
76db3ba4 7463 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7464#endif
76db3ba4
AJ		 7465 gen_addr_add(ctx, addr, addr, 2);
7466 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7467}
7468
7469static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7470{
7471#if defined(TARGET_PPC64)
7472 TCGv t0 = tcg_temp_new();
7473 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7474 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7475 tcg_temp_free(t0);
7476#else
76db3ba4 7477 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7478#endif
7479}
7480
7481static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7482{
76db3ba4 7483 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7484}
7485
7486#define GEN_SPEOP_LDST(name, opc2, sh) \
76db3ba4 7487GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6a6ae23f
AJ		 7488{ \
7489 TCGv t0; \
7490 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7491 gen_exception(ctx, POWERPC_EXCP_APU); \
6a6ae23f
AJ		 7492 return; \
7493 } \
76db3ba4 7494 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 7495 t0 = tcg_temp_new(); \
7496 if (Rc(ctx->opcode)) { \
76db3ba4 7497 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 7498 } else { \
76db3ba4 7499 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 7500 } \
7501 gen_op_##name(ctx, t0); \
7502 tcg_temp_free(t0); \
7503}
7504
7505GEN_SPEOP_LDST(evldd, 0x00, 3);
7506GEN_SPEOP_LDST(evldw, 0x01, 3);
7507GEN_SPEOP_LDST(evldh, 0x02, 3);
7508GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7509GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7510GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7511GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7512GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7513GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7514GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7515GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7516
7517GEN_SPEOP_LDST(evstdd, 0x10, 3);
7518GEN_SPEOP_LDST(evstdw, 0x11, 3);
7519GEN_SPEOP_LDST(evstdh, 0x12, 3);
7520GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7521GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7522GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7523GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7524
7525/* Multiply and add - TODO */
7526#if 0
7527GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7528GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7529GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7530GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7531GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7532GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7533GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7534GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7535GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7536GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7537GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7538GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7539
7540GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7541GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7542GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7543GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7544GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7545GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7546GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7547GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7548GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7549GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7550GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7551GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7552GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7553GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7554
7555GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7556GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7557GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7558GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7559GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7560GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7561
7562GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7563GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7564GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7565GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7566GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7567GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7568GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7569GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7570GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7571GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7572GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7573GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7574
7575GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7576GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7577GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7578GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7579GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7580
7581GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7582GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7583GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7584GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7585GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7586GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7587GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7588GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7589GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7590GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7591GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7592GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7593
7594GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7595GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7596GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7597GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7598GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7599#endif
7600
7601/*** SPE floating-point extension ***/
1c97856d
AJ		 7602#if defined(TARGET_PPC64)
7603#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7604static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7605{ \
1c97856d
AJ		 7606 TCGv_i32 t0; \
7607 TCGv t1; \
7608 t0 = tcg_temp_new_i32(); \
7609 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7610 gen_helper_##name(t0, t0); \
7611 t1 = tcg_temp_new(); \
7612 tcg_gen_extu_i32_tl(t1, t0); \
7613 tcg_temp_free_i32(t0); \
7614 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7615 0xFFFFFFFF00000000ULL); \
7616 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7617 tcg_temp_free(t1); \
0487d6a8 7618}
1c97856d
AJ		 7619#define GEN_SPEFPUOP_CONV_32_64(name) \
7620static always_inline void gen_##name (DisasContext *ctx) \
7621{ \
7622 TCGv_i32 t0; \
7623 TCGv t1; \
7624 t0 = tcg_temp_new_i32(); \
7625 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7626 t1 = tcg_temp_new(); \
7627 tcg_gen_extu_i32_tl(t1, t0); \
7628 tcg_temp_free_i32(t0); \
7629 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7630 0xFFFFFFFF00000000ULL); \
7631 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7632 tcg_temp_free(t1); \
7633}
7634#define GEN_SPEFPUOP_CONV_64_32(name) \
7635static always_inline void gen_##name (DisasContext *ctx) \
7636{ \
7637 TCGv_i32 t0 = tcg_temp_new_i32(); \
7638 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7639 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7640 tcg_temp_free_i32(t0); \
7641}
7642#define GEN_SPEFPUOP_CONV_64_64(name) \
7643static always_inline void gen_##name (DisasContext *ctx) \
7644{ \
7645 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7646}
7647#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7648static always_inline void gen_##name (DisasContext *ctx) \
7649{ \
1c97856d
AJ		 7650 TCGv_i32 t0, t1; \
7651 TCGv_i64 t2; \
57951c27 7652 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7653 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7654 return; \
7655 } \
1c97856d
AJ		 7656 t0 = tcg_temp_new_i32(); \
7657 t1 = tcg_temp_new_i32(); \
7658 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7659 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7660 gen_helper_##name(t0, t0, t1); \
7661 tcg_temp_free_i32(t1); \
7662 t2 = tcg_temp_new(); \
7663 tcg_gen_extu_i32_tl(t2, t0); \
7664 tcg_temp_free_i32(t0); \
7665 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7666 0xFFFFFFFF00000000ULL); \
7667 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7668 tcg_temp_free(t2); \
57951c27 7669}
1c97856d 7670#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7671static always_inline void gen_##name (DisasContext *ctx) \
7672{ \
7673 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7674 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7675 return; \
7676 } \
1c97856d
AJ		 7677 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7678 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7679}
1c97856d 7680#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7681static always_inline void gen_##name (DisasContext *ctx) \
7682{ \
1c97856d 7683 TCGv_i32 t0, t1; \
57951c27 7684 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7685 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7686 return; \
7687 } \
1c97856d
AJ		 7688 t0 = tcg_temp_new_i32(); \
7689 t1 = tcg_temp_new_i32(); \
7690 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7691 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7692 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7693 tcg_temp_free_i32(t0); \
7694 tcg_temp_free_i32(t1); \
7695}
7696#define GEN_SPEFPUOP_COMP_64(name) \
7697static always_inline void gen_##name (DisasContext *ctx) \
7698{ \
7699 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7700 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7701 return; \
7702 } \
7703 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7704 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7705}
7706#else
7707#define GEN_SPEFPUOP_CONV_32_32(name) \
7708static always_inline void gen_##name (DisasContext *ctx) \
7709{ \
7710 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7711}
1c97856d
AJ		 7712#define GEN_SPEFPUOP_CONV_32_64(name) \
7713static always_inline void gen_##name (DisasContext *ctx) \
7714{ \
7715 TCGv_i64 t0 = tcg_temp_new_i64(); \
7716 gen_load_gpr64(t0, rB(ctx->opcode)); \
7717 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7718 tcg_temp_free_i64(t0); \
7719}
7720#define GEN_SPEFPUOP_CONV_64_32(name) \
7721static always_inline void gen_##name (DisasContext *ctx) \
7722{ \
7723 TCGv_i64 t0 = tcg_temp_new_i64(); \
7724 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7725 gen_store_gpr64(rD(ctx->opcode), t0); \
7726 tcg_temp_free_i64(t0); \
7727}
7728#define GEN_SPEFPUOP_CONV_64_64(name) \
7729static always_inline void gen_##name (DisasContext *ctx) \
7730{ \
7731 TCGv_i64 t0 = tcg_temp_new_i64(); \
7732 gen_load_gpr64(t0, rB(ctx->opcode)); \
7733 gen_helper_##name(t0, t0); \
7734 gen_store_gpr64(rD(ctx->opcode), t0); \
7735 tcg_temp_free_i64(t0); \
7736}
7737#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7738static always_inline void gen_##name (DisasContext *ctx) \
7739{ \
7740 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7741 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7742 return; \
7743 } \
7744 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7745 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7746}
7747#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7748static always_inline void gen_##name (DisasContext *ctx) \
7749{ \
7750 TCGv_i64 t0, t1; \
7751 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7752 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7753 return; \
7754 } \
7755 t0 = tcg_temp_new_i64(); \
7756 t1 = tcg_temp_new_i64(); \
7757 gen_load_gpr64(t0, rA(ctx->opcode)); \
7758 gen_load_gpr64(t1, rB(ctx->opcode)); \
7759 gen_helper_##name(t0, t0, t1); \
7760 gen_store_gpr64(rD(ctx->opcode), t0); \
7761 tcg_temp_free_i64(t0); \
7762 tcg_temp_free_i64(t1); \
7763}
7764#define GEN_SPEFPUOP_COMP_32(name) \
7765static always_inline void gen_##name (DisasContext *ctx) \
7766{ \
7767 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7768 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7769 return; \
7770 } \
7771 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7772 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7773}
7774#define GEN_SPEFPUOP_COMP_64(name) \
7775static always_inline void gen_##name (DisasContext *ctx) \
7776{ \
7777 TCGv_i64 t0, t1; \
7778 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7779 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7780 return; \
7781 } \
7782 t0 = tcg_temp_new_i64(); \
7783 t1 = tcg_temp_new_i64(); \
7784 gen_load_gpr64(t0, rA(ctx->opcode)); \
7785 gen_load_gpr64(t1, rB(ctx->opcode)); \
7786 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7787 tcg_temp_free_i64(t0); \
7788 tcg_temp_free_i64(t1); \
7789}
7790#endif
57951c27 7791
0487d6a8
JM		 7792/* Single precision floating-point vectors operations */
7793/* Arithmetic */
1c97856d
AJ		 7794GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7795GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7796GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7797GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7798static always_inline void gen_evfsabs (DisasContext *ctx)
7799{
7800 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7801 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7802 return;
7803 }
7804#if defined(TARGET_PPC64)
7805 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7806#else
7807 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7808 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7809#endif
7810}
7811static always_inline void gen_evfsnabs (DisasContext *ctx)
7812{
7813 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7814 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7815 return;
7816 }
7817#if defined(TARGET_PPC64)
7818 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7819#else
7820 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7821 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7822#endif
7823}
7824static always_inline void gen_evfsneg (DisasContext *ctx)
7825{
7826 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7827 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7828 return;
7829 }
7830#if defined(TARGET_PPC64)
7831 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7832#else
7833 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7834 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7835#endif
7836}
7837
0487d6a8 7838/* Conversion */
1c97856d
AJ		 7839GEN_SPEFPUOP_CONV_64_64(evfscfui);
7840GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7841GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7842GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7843GEN_SPEFPUOP_CONV_64_64(evfsctui);
7844GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7845GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7846GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7847GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7848GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7849
0487d6a8 7850/* Comparison */
1c97856d
AJ		 7851GEN_SPEFPUOP_COMP_64(evfscmpgt);
7852GEN_SPEFPUOP_COMP_64(evfscmplt);
7853GEN_SPEFPUOP_COMP_64(evfscmpeq);
7854GEN_SPEFPUOP_COMP_64(evfststgt);
7855GEN_SPEFPUOP_COMP_64(evfststlt);
7856GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7857
7858/* Opcodes definitions */
40569b7e
AJ		 7859GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7860GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7861GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7862GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7863GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7864GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7865GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7866GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7867GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7868GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7869GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7870GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7871GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7872GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 7873
7874/* Single precision floating-point operations */
7875/* Arithmetic */
1c97856d
AJ		 7876GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7877GEN_SPEFPUOP_ARITH2_32_32(efssub);
7878GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7879GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7880static always_inline void gen_efsabs (DisasContext *ctx)
7881{
7882 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7883 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7884 return;
7885 }
7886 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7887}
7888static always_inline void gen_efsnabs (DisasContext *ctx)
7889{
7890 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7891 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7892 return;
7893 }
7894 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7895}
7896static always_inline void gen_efsneg (DisasContext *ctx)
7897{
7898 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7899 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7900 return;
7901 }
7902 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7903}
7904
0487d6a8 7905/* Conversion */
1c97856d
AJ		 7906GEN_SPEFPUOP_CONV_32_32(efscfui);
7907GEN_SPEFPUOP_CONV_32_32(efscfsi);
7908GEN_SPEFPUOP_CONV_32_32(efscfuf);
7909GEN_SPEFPUOP_CONV_32_32(efscfsf);
7910GEN_SPEFPUOP_CONV_32_32(efsctui);
7911GEN_SPEFPUOP_CONV_32_32(efsctsi);
7912GEN_SPEFPUOP_CONV_32_32(efsctuf);
7913GEN_SPEFPUOP_CONV_32_32(efsctsf);
7914GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7915GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7916GEN_SPEFPUOP_CONV_32_64(efscfd);
7917
0487d6a8 7918/* Comparison */
1c97856d
AJ		 7919GEN_SPEFPUOP_COMP_32(efscmpgt);
7920GEN_SPEFPUOP_COMP_32(efscmplt);
7921GEN_SPEFPUOP_COMP_32(efscmpeq);
7922GEN_SPEFPUOP_COMP_32(efststgt);
7923GEN_SPEFPUOP_COMP_32(efststlt);
7924GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7925
7926/* Opcodes definitions */
40569b7e
AJ		 7927GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7928GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7929GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7930GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7931GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7932GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7933GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7934GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7935GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7936GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7937GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7938GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7939GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7940GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 7941
7942/* Double precision floating-point operations */
7943/* Arithmetic */
1c97856d
AJ		 7944GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7945GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7946GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7947GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7948static always_inline void gen_efdabs (DisasContext *ctx)
7949{
7950 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7951 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7952 return;
7953 }
7954#if defined(TARGET_PPC64)
7955 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7956#else
7957 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7958#endif
7959}
7960static always_inline void gen_efdnabs (DisasContext *ctx)
7961{
7962 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7963 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7964 return;
7965 }
7966#if defined(TARGET_PPC64)
7967 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7968#else
7969 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7970#endif
7971}
7972static always_inline void gen_efdneg (DisasContext *ctx)
7973{
7974 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7975 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7976 return;
7977 }
7978#if defined(TARGET_PPC64)
7979 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7980#else
7981 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7982#endif
7983}
7984
0487d6a8 7985/* Conversion */
1c97856d
AJ		 7986GEN_SPEFPUOP_CONV_64_32(efdcfui);
7987GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7988GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7989GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7990GEN_SPEFPUOP_CONV_32_64(efdctui);
7991GEN_SPEFPUOP_CONV_32_64(efdctsi);
7992GEN_SPEFPUOP_CONV_32_64(efdctuf);
7993GEN_SPEFPUOP_CONV_32_64(efdctsf);
7994GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7995GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7996GEN_SPEFPUOP_CONV_64_32(efdcfs);
7997GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7998GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7999GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8000GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 8001
0487d6a8 8002/* Comparison */
1c97856d
AJ		 8003GEN_SPEFPUOP_COMP_64(efdcmpgt);
8004GEN_SPEFPUOP_COMP_64(efdcmplt);
8005GEN_SPEFPUOP_COMP_64(efdcmpeq);
8006GEN_SPEFPUOP_COMP_64(efdtstgt);
8007GEN_SPEFPUOP_COMP_64(efdtstlt);
8008GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 8009
8010/* Opcodes definitions */
40569b7e
AJ		 8011GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8012GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8013GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8014GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8015GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8016GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8017GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8018GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8019GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8020GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8021GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8022GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8023GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8024GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8025GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8026GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
0487d6a8 8027
79aceca5
FB		 8028/* End opcode list */
8029GEN_OPCODE_MARK(end);
8030
3fc6c082 8031#include "translate_init.c"
0411a972 8032#include "helper_regs.h"
79aceca5 8033
9a64fbe4 8034/*****************************************************************************/
3fc6c082 8035/* Misc PowerPC helpers */
36081602
JM		 8036void cpu_dump_state (CPUState *env, FILE *f,
8037 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8038 int flags)
79aceca5 8039{
3fc6c082
FB		 8040#define RGPL 4
8041#define RFPL 4
3fc6c082 8042
79aceca5
FB		 8043 int i;
8044
077fc206 8045 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 8046 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 8047 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8048 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 8049#if !defined(NO_TIMER_DUMP)
077fc206 8050 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 8051#if !defined(CONFIG_USER_ONLY)
8052 "DECR %08x"
8053#endif
8054 "\n",
077fc206 8055 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 8056#if !defined(CONFIG_USER_ONLY)
8057 , cpu_ppc_load_decr(env)
8058#endif
8059 );
077fc206 8060#endif
76a66253 8061 for (i = 0; i < 32; i++) {
3fc6c082
FB		 8062 if ((i & (RGPL - 1)) == 0)
8063 cpu_fprintf(f, "GPR%02d", i);
6b542af7 8064 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 8065 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 8066 cpu_fprintf(f, "\n");
76a66253 8067 }
3fc6c082 8068 cpu_fprintf(f, "CR ");
76a66253 8069 for (i = 0; i < 8; i++)
7fe48483
FB		 8070 cpu_fprintf(f, "%01x", env->crf[i]);
8071 cpu_fprintf(f, " [");
76a66253
JM		 8072 for (i = 0; i < 8; i++) {
8073 char a = '-';
8074 if (env->crf[i] & 0x08)
8075 a = 'L';
8076 else if (env->crf[i] & 0x04)
8077 a = 'G';
8078 else if (env->crf[i] & 0x02)
8079 a = 'E';
7fe48483 8080 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 8081 }
6b542af7 8082 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 8083 for (i = 0; i < 32; i++) {
8084 if ((i & (RFPL - 1)) == 0)
8085 cpu_fprintf(f, "FPR%02d", i);
26a76461 8086 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 8087 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 8088 cpu_fprintf(f, "\n");
79aceca5 8089 }
7889270a 8090 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
f2e63a42 8091#if !defined(CONFIG_USER_ONLY)
6b542af7 8092 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 8093 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 8094#endif
79aceca5 8095
3fc6c082
FB		 8096#undef RGPL
8097#undef RFPL
79aceca5
FB		 8098}
8099
76a66253
JM		 8100void cpu_dump_statistics (CPUState *env, FILE*f,
8101 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8102 int flags)
8103{
8104#if defined(DO_PPC_STATISTICS)
8105 opc_handler_t **t1, **t2, **t3, *handler;
8106 int op1, op2, op3;
8107
8108 t1 = env->opcodes;
8109 for (op1 = 0; op1 < 64; op1++) {
8110 handler = t1[op1];
8111 if (is_indirect_opcode(handler)) {
8112 t2 = ind_table(handler);
8113 for (op2 = 0; op2 < 32; op2++) {
8114 handler = t2[op2];
8115 if (is_indirect_opcode(handler)) {
8116 t3 = ind_table(handler);
8117 for (op3 = 0; op3 < 32; op3++) {
8118 handler = t3[op3];
8119 if (handler->count == 0)
8120 continue;
8121 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8122 "%016llx %lld\n",
8123 op1, op2, op3, op1, (op3 << 5) | op2,
8124 handler->oname,
8125 handler->count, handler->count);
8126 }
8127 } else {
8128 if (handler->count == 0)
8129 continue;
8130 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8131 "%016llx %lld\n",
8132 op1, op2, op1, op2, handler->oname,
8133 handler->count, handler->count);
8134 }
8135 }
8136 } else {
8137 if (handler->count == 0)
8138 continue;
8139 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8140 op1, op1, handler->oname,
8141 handler->count, handler->count);
8142 }
8143 }
8144#endif
8145}
8146
9a64fbe4 8147/*****************************************************************************/
2cfc5f17
TS		 8148static always_inline void gen_intermediate_code_internal (CPUState *env,
8149 TranslationBlock *tb,
8150 int search_pc)
79aceca5 8151{
9fddaa0c 8152 DisasContext ctx, *ctxp = &ctx;
79aceca5 8153 opc_handler_t **table, *handler;
0fa85d43 8154 target_ulong pc_start;
79aceca5 8155 uint16_t *gen_opc_end;
a1d1bb31 8156 CPUBreakpoint *bp;
79aceca5 8157 int j, lj = -1;
2e70f6ef
PB		 8158 int num_insns;
8159 int max_insns;
79aceca5
FB		 8160
8161 pc_start = tb->pc;
79aceca5 8162 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
046d6672 8163 ctx.nip = pc_start;
79aceca5 8164 ctx.tb = tb;
e1833e1f 8165 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 8166 ctx.spr_cb = env->spr_cb;
76db3ba4
AJ		 8167 ctx.mem_idx = env->mmu_idx;
8168 ctx.access_type = -1;
8169 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 8170#if defined(TARGET_PPC64)
8171 ctx.sf_mode = msr_sf;
9a64fbe4 8172#endif
3cc62370 8173 ctx.fpu_enabled = msr_fp;
a9d9eb8f 8174 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 8175 ctx.spe_enabled = msr_spe;
8176 else
8177 ctx.spe_enabled = 0;
a9d9eb8f
JM		 8178 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8179 ctx.altivec_enabled = msr_vr;
8180 else
8181 ctx.altivec_enabled = 0;
d26bfc9a 8182 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 8183 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 8184 else
8cbcb4fa 8185 ctx.singlestep_enabled = 0;
d26bfc9a 8186 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 8187 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8188 if (unlikely(env->singlestep_enabled))
8189 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 8190#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 8191 /* Single step trace mode */
8192 msr_se = 1;
8193#endif
2e70f6ef
PB		 8194 num_insns = 0;
8195 max_insns = tb->cflags & CF_COUNT_MASK;
8196 if (max_insns == 0)
8197 max_insns = CF_COUNT_MASK;
8198
8199 gen_icount_start();
9a64fbe4 8200 /* Set env in case of segfault during code fetch */
e1833e1f 8201 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 8202 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8203 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 8204 if (bp->pc == ctx.nip) {
e06fcd75 8205 gen_debug_exception(ctxp);
ea4e754f
FB		 8206 break;
8207 }
8208 }
8209 }
76a66253 8210 if (unlikely(search_pc)) {
79aceca5
FB		 8211 j = gen_opc_ptr - gen_opc_buf;
8212 if (lj < j) {
8213 lj++;
8214 while (lj < j)
8215 gen_opc_instr_start[lj++] = 0;
046d6672 8216 gen_opc_pc[lj] = ctx.nip;
79aceca5 8217 gen_opc_instr_start[lj] = 1;
2e70f6ef 8218 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 8219 }
8220 }
d12d51d5
AL		 8221 LOG_DISAS("----------------\n");
8222 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8223 ctx.nip, ctx.mem_idx, (int)msr_ir);
2e70f6ef
PB		 8224 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8225 gen_io_start();
76db3ba4 8226 if (unlikely(ctx.le_mode)) {
056401ea
JM		 8227 ctx.opcode = bswap32(ldl_code(ctx.nip));
8228 } else {
8229 ctx.opcode = ldl_code(ctx.nip);
111bfab3 8230 }
d12d51d5 8231 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 8232 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 8233 opc3(ctx.opcode), little_endian ? "little" : "big");
046d6672 8234 ctx.nip += 4;
3fc6c082 8235 table = env->opcodes;
2e70f6ef 8236 num_insns++;
79aceca5
FB		 8237 handler = table[opc1(ctx.opcode)];
8238 if (is_indirect_opcode(handler)) {
8239 table = ind_table(handler);
8240 handler = table[opc2(ctx.opcode)];
8241 if (is_indirect_opcode(handler)) {
8242 table = ind_table(handler);
8243 handler = table[opc3(ctx.opcode)];
8244 }
8245 }
8246 /* Is opcode *REALLY* valid ? */
76a66253 8247 if (unlikely(handler->handler == &gen_invalid)) {
93fcfe39
AL		 8248 if (qemu_log_enabled()) {
8249 qemu_log("invalid/unsupported opcode: "
8250 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8251 opc1(ctx.opcode), opc2(ctx.opcode),
8252 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 8253 } else {
8254 printf("invalid/unsupported opcode: "
6b542af7 8255 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 8256 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8257 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 8258 }
76a66253
JM		 8259 } else {
8260 if (unlikely((ctx.opcode & handler->inval) != 0)) {
93fcfe39
AL		 8261 if (qemu_log_enabled()) {
8262 qemu_log("invalid bits: %08x for opcode: "
8263 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8264 ctx.opcode & handler->inval, opc1(ctx.opcode),
8265 opc2(ctx.opcode), opc3(ctx.opcode),
8266 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 8267 } else {
8268 printf("invalid bits: %08x for opcode: "
6b542af7 8269 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 8270 ctx.opcode & handler->inval, opc1(ctx.opcode),
8271 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8272 ctx.opcode, ctx.nip - 4);
76a66253 8273 }
e06fcd75 8274 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 8275 break;
79aceca5 8276 }
79aceca5 8277 }
4b3686fa 8278 (*(handler->handler))(&ctx);
76a66253
JM		 8279#if defined(DO_PPC_STATISTICS)
8280 handler->count++;
8281#endif
9a64fbe4 8282 /* Check trace mode exceptions */
8cbcb4fa
AJ		 8283 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8284 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8285 ctx.exception != POWERPC_SYSCALL &&
8286 ctx.exception != POWERPC_EXCP_TRAP &&
8287 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 8288 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 8289 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 8290 (env->singlestep_enabled) ||
8291 num_insns >= max_insns)) {
d26bfc9a
JM		 8292 /* if we reach a page boundary or are single stepping, stop
8293 * generation
8294 */
8dd4983c 8295 break;
76a66253 8296 }
3fc6c082
FB		 8297#if defined (DO_SINGLE_STEP)
8298 break;
8299#endif
8300 }
2e70f6ef
PB		 8301 if (tb->cflags & CF_LAST_IO)
8302 gen_io_end();
e1833e1f 8303 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 8304 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 8305 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa 8306 if (unlikely(env->singlestep_enabled)) {
e06fcd75 8307 gen_debug_exception(ctxp);
8cbcb4fa 8308 }
76a66253 8309 /* Generate the return instruction */
57fec1fe 8310 tcg_gen_exit_tb(0);
9a64fbe4 8311 }
2e70f6ef 8312 gen_icount_end(tb, num_insns);
79aceca5 8313 *gen_opc_ptr = INDEX_op_end;
76a66253 8314 if (unlikely(search_pc)) {
9a64fbe4
FB		 8315 j = gen_opc_ptr - gen_opc_buf;
8316 lj++;
8317 while (lj <= j)
8318 gen_opc_instr_start[lj++] = 0;
9a64fbe4 8319 } else {
046d6672 8320 tb->size = ctx.nip - pc_start;
2e70f6ef 8321 tb->icount = num_insns;
9a64fbe4 8322 }
d9bce9d9 8323#if defined(DEBUG_DISAS)
93fcfe39
AL		 8324 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8325 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8fec2b8c 8326 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 8327 int flags;
237c0af0 8328 flags = env->bfd_mach;
76db3ba4 8329 flags |= ctx.le_mode << 16;
93fcfe39
AL		 8330 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8331 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8332 qemu_log("\n");
9fddaa0c 8333 }
79aceca5 8334#endif
79aceca5
FB		 8335}
8336
2cfc5f17 8337void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 8338{
2cfc5f17 8339 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 8340}
8341
2cfc5f17 8342void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 8343{
2cfc5f17 8344 gen_intermediate_code_internal(env, tb, 1);
79aceca5 8345}
d2856f1a
AJ		 8346
8347void gen_pc_load(CPUState *env, TranslationBlock *tb,
8348 unsigned long searched_pc, int pc_pos, void *puc)
8349{
d2856f1a 8350 env->nip = gen_opc_pc[pc_pos];
d2856f1a 8351}
Qemu copy for testing