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CRIS: Plug a few temp leaks.
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
f10dc08e 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
79aceca5 32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
79aceca5 38//#define DO_SINGLE_STEP
9fddaa0c 39//#define PPC_DEBUG_DISAS
76a66253 40//#define DO_PPC_STATISTICS
7c58044c 41//#define OPTIMIZE_FPRF_UPDATE
79aceca5 42
a750fc0b
JM		 43/*****************************************************************************/
44/* Code translation helpers */
c53be334 45
f78fb44e
AJ		 46/* global register indexes */
47static TCGv cpu_env;
1d542695 48static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 49#if !defined(TARGET_PPC64)
1d542695 50 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 51#endif
a5e26afa 52 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
f78fb44e
AJ		 55static TCGv cpu_gpr[32];
56#if !defined(TARGET_PPC64)
57static TCGv cpu_gprh[32];
58#endif
a5e26afa 59static TCGv cpu_fpr[32];
1d542695 60static TCGv cpu_avrh[32], cpu_avrl[32];
47e4661c 61static TCGv cpu_crf[8];
bd568f18 62static TCGv cpu_nip;
cfdcd37a
AJ		 63static TCGv cpu_ctr;
64static TCGv cpu_lr;
3d7b417e 65static TCGv cpu_xer;
e1571908 66static TCGv cpu_fpscr;
f78fb44e
AJ		 67
68/* dyngen register indexes */
69static TCGv cpu_T[3];
70#if defined(TARGET_PPC64)
71#define cpu_T64 cpu_T
72#else
73static TCGv cpu_T64[3];
74#endif
a5e26afa 75static TCGv cpu_FT[3];
1d542695 76static TCGv cpu_AVRh[3], cpu_AVRl[3];
2e70f6ef
PB		 77
78#include "gen-icount.h"
79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
b2437bf2 84 static int done_init = 0;
f78fb44e 85
2e70f6ef
PB		 86 if (done_init)
87 return;
f78fb44e 88
2e70f6ef 89 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
1c73fe5b
AJ		 90#if TARGET_LONG_BITS > HOST_LONG_BITS
91 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
92 TCG_AREG0, offsetof(CPUState, t0), "T0");
93 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
94 TCG_AREG0, offsetof(CPUState, t1), "T1");
95 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
96 TCG_AREG0, offsetof(CPUState, t2), "T2");
97#else
98 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
99 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
100 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
101#endif
f78fb44e
AJ		 102#if !defined(TARGET_PPC64)
103 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 104 TCG_AREG0, offsetof(CPUState, t0_64),
f78fb44e
AJ		 105 "T0_64");
106 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 107 TCG_AREG0, offsetof(CPUState, t1_64),
f78fb44e
AJ		 108 "T1_64");
109 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 110 TCG_AREG0, offsetof(CPUState, t2_64),
f78fb44e
AJ		 111 "T2_64");
112#endif
a5e26afa
AJ		 113
114 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
115 offsetof(CPUState, ft0), "FT0");
116 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
117 offsetof(CPUState, ft1), "FT1");
118 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
119 offsetof(CPUState, ft2), "FT2");
120
1d542695
AJ		 121 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
122 offsetof(CPUState, avr0.u64[0]), "AVR0H");
123 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124 offsetof(CPUState, avr0.u64[1]), "AVR0L");
125 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126 offsetof(CPUState, avr1.u64[0]), "AVR1H");
127 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128 offsetof(CPUState, avr1.u64[1]), "AVR1L");
129 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
130 offsetof(CPUState, avr2.u64[0]), "AVR2H");
131 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
132 offsetof(CPUState, avr2.u64[1]), "AVR2L");
133
f78fb44e 134 p = cpu_reg_names;
47e4661c
AJ		 135
136 for (i = 0; i < 8; i++) {
137 sprintf(p, "crf%d", i);
138 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
139 offsetof(CPUState, crf[i]), p);
140 p += 5;
141 }
142
f78fb44e
AJ		 143 for (i = 0; i < 32; i++) {
144 sprintf(p, "r%d", i);
145 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
146 offsetof(CPUState, gpr[i]), p);
147 p += (i < 10) ? 3 : 4;
148#if !defined(TARGET_PPC64)
149 sprintf(p, "r%dH", i);
150 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
151 offsetof(CPUState, gprh[i]), p);
152 p += (i < 10) ? 4 : 5;
153#endif
1d542695 154
a5e26afa
AJ		 155 sprintf(p, "fp%d", i);
156 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
157 offsetof(CPUState, fpr[i]), p);
ec1ac72d 158 p += (i < 10) ? 4 : 5;
a5e26afa 159
1d542695
AJ		 160 sprintf(p, "avr%dH", i);
161 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
162 offsetof(CPUState, avr[i].u64[0]), p);
163 p += (i < 10) ? 6 : 7;
ec1ac72d 164
1d542695
AJ		 165 sprintf(p, "avr%dL", i);
166 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
167 offsetof(CPUState, avr[i].u64[1]), p);
168 p += (i < 10) ? 6 : 7;
f78fb44e 169 }
f10dc08e 170
bd568f18
AJ		 171 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
172 offsetof(CPUState, nip), "nip");
173
cfdcd37a
AJ		 174 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
175 offsetof(CPUState, ctr), "ctr");
176
177 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
178 offsetof(CPUState, lr), "lr");
179
3d7b417e
AJ		 180 cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
181 offsetof(CPUState, xer), "xer");
182
e1571908
AJ		 183 cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
184 offsetof(CPUState, fpscr), "fpscr");
185
f10dc08e
AJ		 186 /* register helpers */
187#undef DEF_HELPER
188#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
189#include "helper.h"
190
2e70f6ef
PB		 191 done_init = 1;
192}
193
7c58044c
JM		 194#if defined(OPTIMIZE_FPRF_UPDATE)
195static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
196static uint16_t **gen_fprf_ptr;
197#endif
79aceca5 198
79aceca5
FB		 199/* internal defines */
200typedef struct DisasContext {
201 struct TranslationBlock *tb;
0fa85d43 202 target_ulong nip;
79aceca5 203 uint32_t opcode;
9a64fbe4 204 uint32_t exception;
3cc62370
FB		 205 /* Routine used to access memory */
206 int mem_idx;
207 /* Translation flags */
9a64fbe4 208#if !defined(CONFIG_USER_ONLY)
79aceca5 209 int supervisor;
d9bce9d9
JM		 210#endif
211#if defined(TARGET_PPC64)
212 int sf_mode;
9a64fbe4 213#endif
3cc62370 214 int fpu_enabled;
a9d9eb8f 215 int altivec_enabled;
0487d6a8 216 int spe_enabled;
3fc6c082 217 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 218 int singlestep_enabled;
d63001d1 219 int dcache_line_size;
79aceca5
FB		 220} DisasContext;
221
3fc6c082 222struct opc_handler_t {
79aceca5
FB		 223 /* invalid bits */
224 uint32_t inval;
9a64fbe4 225 /* instruction type */
0487d6a8 226 uint64_t type;
79aceca5
FB		 227 /* handler */
228 void (*handler)(DisasContext *ctx);
a750fc0b 229#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 230 const char *oname;
a750fc0b
JM		 231#endif
232#if defined(DO_PPC_STATISTICS)
76a66253
JM		 233 uint64_t count;
234#endif
3fc6c082 235};
79aceca5 236
7c58044c
JM		 237static always_inline void gen_reset_fpstatus (void)
238{
239#ifdef CONFIG_SOFTFLOAT
240 gen_op_reset_fpstatus();
241#endif
242}
243
244static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
245{
246 if (set_fprf != 0) {
247 /* This case might be optimized later */
248#if defined(OPTIMIZE_FPRF_UPDATE)
249 *gen_fprf_ptr++ = gen_opc_ptr;
250#endif
251 gen_op_compute_fprf(1);
252 if (unlikely(set_rc))
47e4661c 253 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 254 gen_op_float_check_status();
255 } else if (unlikely(set_rc)) {
256 /* We always need to compute fpcc */
257 gen_op_compute_fprf(0);
47e4661c 258 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 259 if (set_fprf)
260 gen_op_float_check_status();
261 }
262}
263
264static always_inline void gen_optimize_fprf (void)
265{
266#if defined(OPTIMIZE_FPRF_UPDATE)
267 uint16_t **ptr;
268
269 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
270 *ptr = INDEX_op_nop1;
271 gen_fprf_ptr = gen_fprf_buf;
272#endif
273}
274
b068d6a7 275static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 276{
277#if defined(TARGET_PPC64)
278 if (ctx->sf_mode)
bd568f18 279 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 280 else
281#endif
bd568f18 282 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 283}
284
e1833e1f 285#define GEN_EXCP(ctx, excp, error) \
79aceca5 286do { \
e1833e1f 287 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 288 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 289 } \
290 gen_op_raise_exception_err((excp), (error)); \
291 ctx->exception = (excp); \
79aceca5
FB		 292} while (0)
293
e1833e1f
JM		 294#define GEN_EXCP_INVAL(ctx) \
295GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
296 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 297
e1833e1f
JM		 298#define GEN_EXCP_PRIVOPC(ctx) \
299GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
300 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 301
e1833e1f
JM		 302#define GEN_EXCP_PRIVREG(ctx) \
303GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
304 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
305
306#define GEN_EXCP_NO_FP(ctx) \
307GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
308
309#define GEN_EXCP_NO_AP(ctx) \
310GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 311
a9d9eb8f
JM		 312#define GEN_EXCP_NO_VR(ctx) \
313GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
314
f24e5695 315/* Stop translation */
b068d6a7 316static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 317{
d9bce9d9 318 gen_update_nip(ctx, ctx->nip);
e1833e1f 319 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 320}
321
f24e5695 322/* No need to update nip here, as execution flow will change */
b068d6a7 323static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 324{
e1833e1f 325 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 326}
327
79aceca5
FB		 328#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329static void gen_##name (DisasContext *ctx); \
330GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
331static void gen_##name (DisasContext *ctx)
332
c7697e1f
JM		 333#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
334static void gen_##name (DisasContext *ctx); \
335GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
336static void gen_##name (DisasContext *ctx)
337
79aceca5
FB		 338typedef struct opcode_t {
339 unsigned char opc1, opc2, opc3;
1235fc06 340#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 341 unsigned char pad[5];
342#else
343 unsigned char pad[1];
344#endif
79aceca5 345 opc_handler_t handler;
b55266b5 346 const char *oname;
79aceca5
FB		 347} opcode_t;
348
a750fc0b 349/*****************************************************************************/
79aceca5
FB		 350/*** Instruction decoding ***/
351#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 352static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 353{ \
354 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
355}
356
357#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 358static always_inline int32_t name (uint32_t opcode) \
79aceca5 359{ \
18fba28c 360 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 361}
362
363/* Opcode part 1 */
364EXTRACT_HELPER(opc1, 26, 6);
365/* Opcode part 2 */
366EXTRACT_HELPER(opc2, 1, 5);
367/* Opcode part 3 */
368EXTRACT_HELPER(opc3, 6, 5);
369/* Update Cr0 flags */
370EXTRACT_HELPER(Rc, 0, 1);
371/* Destination */
372EXTRACT_HELPER(rD, 21, 5);
373/* Source */
374EXTRACT_HELPER(rS, 21, 5);
375/* First operand */
376EXTRACT_HELPER(rA, 16, 5);
377/* Second operand */
378EXTRACT_HELPER(rB, 11, 5);
379/* Third operand */
380EXTRACT_HELPER(rC, 6, 5);
381/*** Get CRn ***/
382EXTRACT_HELPER(crfD, 23, 3);
383EXTRACT_HELPER(crfS, 18, 3);
384EXTRACT_HELPER(crbD, 21, 5);
385EXTRACT_HELPER(crbA, 16, 5);
386EXTRACT_HELPER(crbB, 11, 5);
387/* SPR / TBL */
3fc6c082 388EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 389static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 390{
391 uint32_t sprn = _SPR(opcode);
392
393 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
394}
79aceca5
FB		 395/*** Get constants ***/
396EXTRACT_HELPER(IMM, 12, 8);
397/* 16 bits signed immediate value */
398EXTRACT_SHELPER(SIMM, 0, 16);
399/* 16 bits unsigned immediate value */
400EXTRACT_HELPER(UIMM, 0, 16);
401/* Bit count */
402EXTRACT_HELPER(NB, 11, 5);
403/* Shift count */
404EXTRACT_HELPER(SH, 11, 5);
405/* Mask start */
406EXTRACT_HELPER(MB, 6, 5);
407/* Mask end */
408EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 409/* Trap operand */
410EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 411
412EXTRACT_HELPER(CRM, 12, 8);
413EXTRACT_HELPER(FM, 17, 8);
414EXTRACT_HELPER(SR, 16, 4);
e4bb997e 415EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 416
79aceca5
FB		 417/*** Jump target decoding ***/
418/* Displacement */
419EXTRACT_SHELPER(d, 0, 16);
420/* Immediate address */
b068d6a7 421static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 422{
423 return (opcode >> 0) & 0x03FFFFFC;
424}
425
b068d6a7 426static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 427{
428 return (opcode >> 0) & 0xFFFC;
429}
430
431EXTRACT_HELPER(BO, 21, 5);
432EXTRACT_HELPER(BI, 16, 5);
433/* Absolute/relative address */
434EXTRACT_HELPER(AA, 1, 1);
435/* Link */
436EXTRACT_HELPER(LK, 0, 1);
437
438/* Create a mask between <start> and <end> bits */
b068d6a7 439static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 440{
76a66253 441 target_ulong ret;
79aceca5 442
76a66253
JM		 443#if defined(TARGET_PPC64)
444 if (likely(start == 0)) {
6f2d8978 445 ret = UINT64_MAX << (63 - end);
76a66253 446 } else if (likely(end == 63)) {
6f2d8978 447 ret = UINT64_MAX >> start;
76a66253
JM		 448 }
449#else
450 if (likely(start == 0)) {
6f2d8978 451 ret = UINT32_MAX << (31 - end);
76a66253 452 } else if (likely(end == 31)) {
6f2d8978 453 ret = UINT32_MAX >> start;
76a66253
JM		 454 }
455#endif
456 else {
457 ret = (((target_ulong)(-1ULL)) >> (start)) ^
458 (((target_ulong)(-1ULL) >> (end)) >> 1);
459 if (unlikely(start > end))
460 return ~ret;
461 }
79aceca5
FB		 462
463 return ret;
464}
465
a750fc0b
JM		 466/*****************************************************************************/
467/* PowerPC Instructions types definitions */
468enum {
1b413d55 469 PPC_NONE = 0x0000000000000000ULL,
12de9a39 470 /* PowerPC base instructions set */
1b413d55
JM		 471 PPC_INSNS_BASE = 0x0000000000000001ULL,
472 /* integer operations instructions */
a750fc0b 473#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 474 /* flow control instructions */
a750fc0b 475#define PPC_FLOW PPC_INSNS_BASE
1b413d55 476 /* virtual memory instructions */
a750fc0b 477#define PPC_MEM PPC_INSNS_BASE
1b413d55 478 /* ld/st with reservation instructions */
a750fc0b 479#define PPC_RES PPC_INSNS_BASE
1b413d55 480 /* spr/msr access instructions */
a750fc0b 481#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 482 /* Deprecated instruction sets */
483 /* Original POWER instruction set */
f610349f 484 PPC_POWER = 0x0000000000000002ULL,
1b413d55 485 /* POWER2 instruction set extension */
f610349f 486 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 487 /* Power RTC support */
f610349f 488 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 489 /* Power-to-PowerPC bridge (601) */
f610349f 490 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 491 /* 64 bits PowerPC instruction set */
f610349f 492 PPC_64B = 0x0000000000000020ULL,
1b413d55 493 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 494 PPC_64BX = 0x0000000000000040ULL,
1b413d55 495 /* 64 bits hypervisor extensions */
f610349f 496 PPC_64H = 0x0000000000000080ULL,
1b413d55 497 /* New wait instruction (PowerPC 2.0x) */
f610349f 498 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 499 /* Time base mftb instruction */
f610349f 500 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 501
502 /* Fixed-point unit extensions */
503 /* PowerPC 602 specific */
f610349f 504 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 505 /* isel instruction */
506 PPC_ISEL = 0x0000000000000800ULL,
507 /* popcntb instruction */
508 PPC_POPCNTB = 0x0000000000001000ULL,
509 /* string load / store */
510 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 511
512 /* Floating-point unit extensions */
513 /* Optional floating point instructions */
514 PPC_FLOAT = 0x0000000000010000ULL,
515 /* New floating-point extensions (PowerPC 2.0x) */
516 PPC_FLOAT_EXT = 0x0000000000020000ULL,
517 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
518 PPC_FLOAT_FRES = 0x0000000000080000ULL,
519 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
520 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
521 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
522 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
523
524 /* Vector/SIMD extensions */
525 /* Altivec support */
526 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 527 /* PowerPC 2.03 SPE extension */
05332d70 528 PPC_SPE = 0x0000000002000000ULL,
1b413d55 529 /* PowerPC 2.03 SPE floating-point extension */
05332d70 530 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 531
12de9a39 532 /* Optional memory control instructions */
1b413d55
JM		 533 PPC_MEM_TLBIA = 0x0000000010000000ULL,
534 PPC_MEM_TLBIE = 0x0000000020000000ULL,
535 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
536 /* sync instruction */
537 PPC_MEM_SYNC = 0x0000000080000000ULL,
538 /* eieio instruction */
539 PPC_MEM_EIEIO = 0x0000000100000000ULL,
540
541 /* Cache control instructions */
c8623f2e 542 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 543 /* icbi instruction */
05332d70 544 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 545 /* dcbz instruction with fixed cache line size */
05332d70 546 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 547 /* dcbz instruction with tunable cache line size */
05332d70 548 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 549 /* dcba instruction */
05332d70
JM		 550 PPC_CACHE_DCBA = 0x0000002000000000ULL,
551 /* Freescale cache locking instructions */
552 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 553
554 /* MMU related extensions */
555 /* external control instructions */
05332d70 556 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 557 /* segment register access instructions */
05332d70 558 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 559 /* PowerPC 6xx TLB management instructions */
05332d70 560 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 561 /* PowerPC 74xx TLB management instructions */
05332d70 562 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 563 /* PowerPC 40x TLB management instructions */
05332d70 564 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 565 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 566 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 567 /* SLB management */
05332d70 568 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 569
12de9a39 570 /* Embedded PowerPC dedicated instructions */
05332d70 571 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 572 /* PowerPC 40x exception model */
05332d70 573 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 574 /* PowerPC 405 Mac instructions */
05332d70 575 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 576 /* PowerPC 440 specific instructions */
05332d70 577 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 578 /* BookE (embedded) PowerPC specification */
05332d70
JM		 579 PPC_BOOKE = 0x0010000000000000ULL,
580 /* mfapidi instruction */
581 PPC_MFAPIDI = 0x0020000000000000ULL,
582 /* tlbiva instruction */
583 PPC_TLBIVA = 0x0040000000000000ULL,
584 /* tlbivax instruction */
585 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 586 /* PowerPC 4xx dedicated instructions */
05332d70 587 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 588 /* PowerPC 40x ibct instructions */
05332d70 589 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 590 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 591 PPC_RFMCI = 0x0400000000000000ULL,
592 /* rfdi instruction */
593 PPC_RFDI = 0x0800000000000000ULL,
594 /* DCR accesses */
595 PPC_DCR = 0x1000000000000000ULL,
596 /* DCR extended accesse */
597 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 598 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 599 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 600};
601
602/*****************************************************************************/
603/* PowerPC instructions table */
3fc6c082
FB		 604#if HOST_LONG_BITS == 64
605#define OPC_ALIGN 8
606#else
607#define OPC_ALIGN 4
608#endif
1b039c09 609#if defined(__APPLE__)
d9bce9d9 610#define OPCODES_SECTION \
3fc6c082 611 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 612#else
d9bce9d9 613#define OPCODES_SECTION \
3fc6c082 614 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 615#endif
616
76a66253 617#if defined(DO_PPC_STATISTICS)
79aceca5 618#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 619OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
18fba28c 623 .pad = { 0, }, \
79aceca5
FB		 624 .handler = { \
625 .inval = invl, \
9a64fbe4 626 .type = _typ, \
79aceca5 627 .handler = &gen_##name, \
76a66253 628 .oname = stringify(name), \
79aceca5 629 }, \
3fc6c082 630 .oname = stringify(name), \
79aceca5 631}
c7697e1f
JM		 632#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
633OPCODES_SECTION opcode_t opc_##name = { \
634 .opc1 = op1, \
635 .opc2 = op2, \
636 .opc3 = op3, \
637 .pad = { 0, }, \
638 .handler = { \
639 .inval = invl, \
640 .type = _typ, \
641 .handler = &gen_##name, \
642 .oname = onam, \
643 }, \
644 .oname = onam, \
645}
76a66253
JM		 646#else
647#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
648OPCODES_SECTION opcode_t opc_##name = { \
649 .opc1 = op1, \
650 .opc2 = op2, \
651 .opc3 = op3, \
652 .pad = { 0, }, \
653 .handler = { \
654 .inval = invl, \
655 .type = _typ, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = stringify(name), \
659}
c7697e1f
JM		 660#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
661OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = op1, \
663 .opc2 = op2, \
664 .opc3 = op3, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = invl, \
668 .type = _typ, \
669 .handler = &gen_##name, \
670 }, \
671 .oname = onam, \
672}
76a66253 673#endif
79aceca5
FB		 674
675#define GEN_OPCODE_MARK(name) \
18fba28c 676OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 677 .opc1 = 0xFF, \
678 .opc2 = 0xFF, \
679 .opc3 = 0xFF, \
18fba28c 680 .pad = { 0, }, \
79aceca5
FB		 681 .handler = { \
682 .inval = 0x00000000, \
9a64fbe4 683 .type = 0x00, \
79aceca5
FB		 684 .handler = NULL, \
685 }, \
3fc6c082 686 .oname = stringify(name), \
79aceca5
FB		 687}
688
689/* Start opcode list */
690GEN_OPCODE_MARK(start);
691
692/* Invalid instruction */
9a64fbe4
FB		 693GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
694{
e1833e1f 695 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 696}
697
79aceca5
FB		 698static opc_handler_t invalid_handler = {
699 .inval = 0xFFFFFFFF,
9a64fbe4 700 .type = PPC_NONE,
79aceca5
FB		 701 .handler = gen_invalid,
702};
703
e1571908
AJ		 704/*** Integer comparison ***/
705
706static always_inline void gen_op_cmp(TCGv t0, TCGv t1, int s, int crf)
707{
708 int l1, l2, l3;
709
710 tcg_gen_shri_i32(cpu_crf[crf], cpu_xer, XER_SO);
711 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
712
713 l1 = gen_new_label();
714 l2 = gen_new_label();
715 l3 = gen_new_label();
716 if (s) {
717 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
718 tcg_gen_brcond_tl(TCG_COND_GT, t0, t1, l2);
719 } else {
720 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
721 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l2);
722 }
723 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
724 tcg_gen_br(l3);
725 gen_set_label(l1);
726 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
727 tcg_gen_br(l3);
728 gen_set_label(l2);
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
730 gen_set_label(l3);
731}
732
733static always_inline void gen_op_cmpi(TCGv t0, target_ulong t1, int s, int crf)
734{
735 TCGv temp = tcg_const_local_tl(t1);
736 gen_op_cmp(t0, temp, s, crf);
737 tcg_temp_free(temp);
738}
739
740#if defined(TARGET_PPC64)
741static always_inline void gen_op_cmp32(TCGv t0, TCGv t1, int s, int crf)
742{
743 TCGv t0_32, t1_32;
744 t0_32 = tcg_temp_local_new(TCG_TYPE_TL);
745 t1_32 = tcg_temp_local_new(TCG_TYPE_TL);
746 if (s) {
747 tcg_gen_ext32s_tl(t0_32, t0);
748 tcg_gen_ext32s_tl(t1_32, t1);
749 } else {
750 tcg_gen_ext32u_tl(t0_32, t0);
751 tcg_gen_ext32u_tl(t1_32, t1);
752 }
753 gen_op_cmp(t0_32, t1_32, s, crf);
754 tcg_temp_free(t1_32);
755 tcg_temp_free(t0_32);
756}
757
758static always_inline void gen_op_cmpi32(TCGv t0, target_ulong t1, int s, int crf)
759{
760 TCGv temp = tcg_const_local_tl(t1);
761 gen_op_cmp32(t0, temp, s, crf);
762 tcg_temp_free(temp);
763}
764#endif
765
766static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
767{
768#if defined(TARGET_PPC64)
769 if (!(ctx->sf_mode))
770 gen_op_cmpi32(reg, 0, 1, 0);
771 else
772#endif
773 gen_op_cmpi(reg, 0, 1, 0);
774}
775
776/* cmp */
777GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
778{
779#if defined(TARGET_PPC64)
780 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
781 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
782 1, crfD(ctx->opcode));
783 else
784#endif
785 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787}
788
789/* cmpi */
790GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
791{
792#if defined(TARGET_PPC64)
793 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
794 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
795 1, crfD(ctx->opcode));
796 else
797#endif
798 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800}
801
802/* cmpl */
803GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
804{
805#if defined(TARGET_PPC64)
806 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
807 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
808 0, crfD(ctx->opcode));
809 else
810#endif
811 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813}
814
815/* cmpli */
816GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
817{
818#if defined(TARGET_PPC64)
819 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
820 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
821 0, crfD(ctx->opcode));
822 else
823#endif
824 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826}
827
828/* isel (PowerPC 2.03 specification) */
829GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
830{
831 int l1, l2;
832 uint32_t bi = rC(ctx->opcode);
833 uint32_t mask;
834 TCGv temp;
835
836 l1 = gen_new_label();
837 l2 = gen_new_label();
838
839 mask = 1 << (3 - (bi & 0x03));
840 temp = tcg_temp_new(TCG_TYPE_I32);
841 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
842 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
843 if (rA(ctx->opcode) == 0)
844 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
845 else
846 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
847 tcg_gen_br(l2);
848 gen_set_label(l1);
849 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
850 gen_set_label(l2);
851}
852
79aceca5 853/*** Integer arithmetic ***/
d9bce9d9
JM		 854#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
855GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 856{ \
f78fb44e
AJ		 857 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
858 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 859 gen_op_##name(); \
f78fb44e 860 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 861 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 862 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 863}
864
d9bce9d9
JM		 865#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
866GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 867{ \
f78fb44e
AJ		 868 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
869 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 870 gen_op_##name(); \
f78fb44e 871 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 872 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 873 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 874}
875
d9bce9d9
JM		 876#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
877GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 878{ \
f78fb44e 879 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 880 gen_op_##name(); \
f78fb44e 881 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 882 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 883 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5 884}
d9bce9d9
JM		 885#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
886GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 887{ \
f78fb44e 888 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 889 gen_op_##name(); \
f78fb44e 890 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 891 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 892 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 893}
894
895/* Two operands arithmetic functions */
d9bce9d9
JM		 896#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
897__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
898__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
899
900/* Two operands arithmetic functions with no overflow allowed */
901#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
902__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
903
904/* One operand arithmetic functions */
905#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
906__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
907__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
908
909#if defined(TARGET_PPC64)
910#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
911GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
912{ \
f78fb44e
AJ		 913 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
914 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 915 if (ctx->sf_mode) \
916 gen_op_##name##_64(); \
917 else \
918 gen_op_##name(); \
f78fb44e 919 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 920 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 921 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 922}
923
924#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
925GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
926{ \
f78fb44e
AJ		 927 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
928 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 929 if (ctx->sf_mode) \
930 gen_op_##name##_64(); \
931 else \
932 gen_op_##name(); \
f78fb44e 933 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 934 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 935 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 936}
937
938#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
939GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
940{ \
f78fb44e 941 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 942 if (ctx->sf_mode) \
943 gen_op_##name##_64(); \
944 else \
945 gen_op_##name(); \
f78fb44e 946 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 947 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 948 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 949}
950#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
951GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
952{ \
f78fb44e 953 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 954 if (ctx->sf_mode) \
955 gen_op_##name##_64(); \
956 else \
957 gen_op_##name(); \
f78fb44e 958 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 959 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 960 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 961}
962
963/* Two operands arithmetic functions */
964#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
965__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
966__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 967
968/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 969#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
970__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 971
972/* One operand arithmetic functions */
d9bce9d9
JM		 973#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
974__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
975__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
976#else
977#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
978#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
979#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
980#endif
79aceca5
FB		 981
982/* add add. addo addo. */
39dd32ee
AJ		 983static always_inline void gen_op_add (void)
984{
985 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
986}
b068d6a7 987static always_inline void gen_op_addo (void)
d9bce9d9 988{
e55fd934 989 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 990 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 991 gen_op_check_addo();
992}
993#if defined(TARGET_PPC64)
994#define gen_op_add_64 gen_op_add
b068d6a7 995static always_inline void gen_op_addo_64 (void)
d9bce9d9 996{
e55fd934 997 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 998 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 999 gen_op_check_addo_64();
1000}
1001#endif
1002GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 1003/* addc addc. addco addco. */
b068d6a7 1004static always_inline void gen_op_addc (void)
d9bce9d9 1005{
e55fd934 1006 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1007 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1008 gen_op_check_addc();
1009}
b068d6a7 1010static always_inline void gen_op_addco (void)
d9bce9d9 1011{
e55fd934 1012 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1013 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1014 gen_op_check_addc();
1015 gen_op_check_addo();
1016}
1017#if defined(TARGET_PPC64)
b068d6a7 1018static always_inline void gen_op_addc_64 (void)
d9bce9d9 1019{
e55fd934 1020 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1021 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1022 gen_op_check_addc_64();
1023}
b068d6a7 1024static always_inline void gen_op_addco_64 (void)
d9bce9d9 1025{
e55fd934 1026 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1027 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1028 gen_op_check_addc_64();
1029 gen_op_check_addo_64();
1030}
1031#endif
1032GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 1033/* adde adde. addeo addeo. */
b068d6a7 1034static always_inline void gen_op_addeo (void)
d9bce9d9 1035{
e55fd934 1036 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1037 gen_op_adde();
1038 gen_op_check_addo();
1039}
1040#if defined(TARGET_PPC64)
b068d6a7 1041static always_inline void gen_op_addeo_64 (void)
d9bce9d9 1042{
e55fd934 1043 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1044 gen_op_adde_64();
1045 gen_op_check_addo_64();
1046}
1047#endif
1048GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 1049/* addme addme. addmeo addmeo. */
b068d6a7 1050static always_inline void gen_op_addme (void)
d9bce9d9 1051{
e55fd934 1052 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1053 gen_op_add_me();
1054}
1055#if defined(TARGET_PPC64)
b068d6a7 1056static always_inline void gen_op_addme_64 (void)
d9bce9d9 1057{
e55fd934 1058 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1059 gen_op_add_me_64();
1060}
1061#endif
1062GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 1063/* addze addze. addzeo addzeo. */
b068d6a7 1064static always_inline void gen_op_addze (void)
d9bce9d9 1065{
e55fd934 1066 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1067 gen_op_add_ze();
1068 gen_op_check_addc();
1069}
b068d6a7 1070static always_inline void gen_op_addzeo (void)
d9bce9d9 1071{
e55fd934 1072 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1073 gen_op_add_ze();
1074 gen_op_check_addc();
1075 gen_op_check_addo();
1076}
1077#if defined(TARGET_PPC64)
b068d6a7 1078static always_inline void gen_op_addze_64 (void)
d9bce9d9 1079{
e55fd934 1080 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1081 gen_op_add_ze();
1082 gen_op_check_addc_64();
1083}
b068d6a7 1084static always_inline void gen_op_addzeo_64 (void)
d9bce9d9 1085{
e55fd934 1086 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1087 gen_op_add_ze();
1088 gen_op_check_addc_64();
1089 gen_op_check_addo_64();
1090}
1091#endif
1092GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 1093/* divw divw. divwo divwo. */
d9bce9d9 1094GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 1095/* divwu divwu. divwuo divwuo. */
d9bce9d9 1096GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 1097/* mulhw mulhw. */
d9bce9d9 1098GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 1099/* mulhwu mulhwu. */
d9bce9d9 1100GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 1101/* mullw mullw. mullwo mullwo. */
d9bce9d9 1102GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 1103/* neg neg. nego nego. */
d9bce9d9 1104GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 1105/* subf subf. subfo subfo. */
7c417963
AJ		 1106static always_inline void gen_op_subf (void)
1107{
1108 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1109}
b068d6a7 1110static always_inline void gen_op_subfo (void)
d9bce9d9 1111{
f0413473 1112 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 1113 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 1114 gen_op_check_addo();
d9bce9d9
JM		 1115}
1116#if defined(TARGET_PPC64)
1117#define gen_op_subf_64 gen_op_subf
b068d6a7 1118static always_inline void gen_op_subfo_64 (void)
d9bce9d9 1119{
f0413473 1120 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 1121 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 1122 gen_op_check_addo_64();
d9bce9d9
JM		 1123}
1124#endif
1125GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 1126/* subfc subfc. subfco subfco. */
b068d6a7 1127static always_inline void gen_op_subfc (void)
d9bce9d9 1128{
7c417963 1129 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1130 gen_op_check_subfc();
1131}
b068d6a7 1132static always_inline void gen_op_subfco (void)
d9bce9d9 1133{
f0413473 1134 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 1135 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 1136 gen_op_check_subfc();
c3e10c7b 1137 gen_op_check_addo();
d9bce9d9
JM		 1138}
1139#if defined(TARGET_PPC64)
b068d6a7 1140static always_inline void gen_op_subfc_64 (void)
d9bce9d9 1141{
7c417963 1142 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1143 gen_op_check_subfc_64();
1144}
b068d6a7 1145static always_inline void gen_op_subfco_64 (void)
d9bce9d9 1146{
f0413473 1147 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 1148 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 1149 gen_op_check_subfc_64();
c3e10c7b 1150 gen_op_check_addo_64();
d9bce9d9
JM		 1151}
1152#endif
1153GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 1154/* subfe subfe. subfeo subfeo. */
b068d6a7 1155static always_inline void gen_op_subfeo (void)
d9bce9d9 1156{
f0413473 1157 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
d9bce9d9 1158 gen_op_subfe();
c3e10c7b 1159 gen_op_check_addo();
d9bce9d9
JM		 1160}
1161#if defined(TARGET_PPC64)
1162#define gen_op_subfe_64 gen_op_subfe
b068d6a7 1163static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 1164{
f0413473 1165 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
d9bce9d9 1166 gen_op_subfe_64();
c3e10c7b 1167 gen_op_check_addo_64();
d9bce9d9
JM		 1168}
1169#endif
1170GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 1171/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 1172GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 1173/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 1174GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 1175/* addi */
1176GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1177{
76a66253 1178 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1179
1180 if (rA(ctx->opcode) == 0) {
76a66253 1181 /* li case */
02f4f6c2 1182 tcg_gen_movi_tl(cpu_T[0], simm);
79aceca5 1183 } else {
f78fb44e 1184 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1185 if (likely(simm != 0))
39dd32ee 1186 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
79aceca5 1187 }
f78fb44e 1188 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1189}
1190/* addic */
1191GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1192{
76a66253
JM		 1193 target_long simm = SIMM(ctx->opcode);
1194
f78fb44e 1195 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1196 if (likely(simm != 0)) {
e55fd934 1197 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1198 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1199#if defined(TARGET_PPC64)
1200 if (ctx->sf_mode)
1201 gen_op_check_addc_64();
1202 else
1203#endif
1204 gen_op_check_addc();
e864cabd 1205 } else {
3d7b417e 1206 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1207 }
f78fb44e 1208 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1209}
1210/* addic. */
c7697e1f 1211GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1212{
76a66253
JM		 1213 target_long simm = SIMM(ctx->opcode);
1214
f78fb44e 1215 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1216 if (likely(simm != 0)) {
e55fd934 1217 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1218 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1219#if defined(TARGET_PPC64)
1220 if (ctx->sf_mode)
1221 gen_op_check_addc_64();
1222 else
1223#endif
1224 gen_op_check_addc();
966439a6 1225 } else {
3d7b417e 1226 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1227 }
f78fb44e 1228 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
e1571908 1229 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1230}
1231/* addis */
1232GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1233{
76a66253 1234 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1235
1236 if (rA(ctx->opcode) == 0) {
76a66253 1237 /* lis case */
02f4f6c2 1238 tcg_gen_movi_tl(cpu_T[0], simm << 16);
79aceca5 1239 } else {
f78fb44e 1240 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1241 if (likely(simm != 0))
39dd32ee 1242 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16);
79aceca5 1243 }
f78fb44e 1244 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1245}
1246/* mulli */
1247GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1248{
f78fb44e 1249 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
79aceca5 1250 gen_op_mulli(SIMM(ctx->opcode));
f78fb44e 1251 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1252}
1253/* subfic */
1254GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1255{
f78fb44e 1256 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9
JM		 1257#if defined(TARGET_PPC64)
1258 if (ctx->sf_mode)
1259 gen_op_subfic_64(SIMM(ctx->opcode));
1260 else
1261#endif
1262 gen_op_subfic(SIMM(ctx->opcode));
f78fb44e 1263 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1264}
1265
d9bce9d9
JM		 1266#if defined(TARGET_PPC64)
1267/* mulhd mulhd. */
a750fc0b 1268GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1269/* mulhdu mulhdu. */
a750fc0b 1270GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1271/* mulld mulld. mulldo mulldo. */
a750fc0b 1272GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1273/* divd divd. divdo divdo. */
a750fc0b 1274GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1275/* divdu divdu. divduo divduo. */
a750fc0b 1276GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1277#endif
1278
79aceca5 1279/*** Integer logical ***/
26d67362
AJ		 1280#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1281GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1282{ \
26d67362
AJ		 1283 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1284 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1285 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1286 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1287}
79aceca5 1288
26d67362 1289#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1290GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1291{ \
26d67362 1292 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1293 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1294 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1295}
1296
1297/* and & and. */
26d67362 1298GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1299/* andc & andc. */
26d67362 1300GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1301/* andi. */
c7697e1f 1302GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1303{
26d67362
AJ		 1304 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1305 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1306}
1307/* andis. */
c7697e1f 1308GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1309{
26d67362
AJ		 1310 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1311 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1312}
79aceca5 1313/* cntlzw */
26d67362
AJ		 1314GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1315{
1316 tcg_gen_helper_1_1(helper_cntlzw, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1317 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1318 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1319}
79aceca5 1320/* eqv & eqv. */
26d67362 1321GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1322/* extsb & extsb. */
26d67362 1323GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1324/* extsh & extsh. */
26d67362 1325GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1326/* nand & nand. */
26d67362 1327GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1328/* nor & nor. */
26d67362 1329GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1330/* or & or. */
9a64fbe4
FB		 1331GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1332{
76a66253
JM		 1333 int rs, ra, rb;
1334
1335 rs = rS(ctx->opcode);
1336 ra = rA(ctx->opcode);
1337 rb = rB(ctx->opcode);
1338 /* Optimisation for mr. ri case */
1339 if (rs != ra || rs != rb) {
26d67362
AJ		 1340 if (rs != rb)
1341 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1342 else
1343 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1344 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1345 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1346 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1347 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1348#if defined(TARGET_PPC64)
1349 } else {
26d67362
AJ		 1350 int prio = 0;
1351
c80f84e3
JM		 1352 switch (rs) {
1353 case 1:
1354 /* Set process priority to low */
26d67362 1355 prio = 2;
c80f84e3
JM		 1356 break;
1357 case 6:
1358 /* Set process priority to medium-low */
26d67362 1359 prio = 3;
c80f84e3
JM		 1360 break;
1361 case 2:
1362 /* Set process priority to normal */
26d67362 1363 prio = 4;
c80f84e3 1364 break;
be147d08
JM		 1365#if !defined(CONFIG_USER_ONLY)
1366 case 31:
1367 if (ctx->supervisor > 0) {
1368 /* Set process priority to very low */
26d67362 1369 prio = 1;
be147d08
JM		 1370 }
1371 break;
1372 case 5:
1373 if (ctx->supervisor > 0) {
1374 /* Set process priority to medium-hight */
26d67362 1375 prio = 5;
be147d08
JM		 1376 }
1377 break;
1378 case 3:
1379 if (ctx->supervisor > 0) {
1380 /* Set process priority to high */
26d67362 1381 prio = 6;
be147d08
JM		 1382 }
1383 break;
be147d08
JM		 1384 case 7:
1385 if (ctx->supervisor > 1) {
1386 /* Set process priority to very high */
26d67362 1387 prio = 7;
be147d08
JM		 1388 }
1389 break;
be147d08 1390#endif
c80f84e3
JM		 1391 default:
1392 /* nop */
1393 break;
1394 }
26d67362
AJ		 1395 if (prio) {
1396 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
1397 tcg_gen_ld_tl(temp, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1398 tcg_gen_andi_tl(temp, temp, ~0x001C000000000000ULL);
1399 tcg_gen_ori_tl(temp, temp, ((uint64_t)prio) << 50);
1400 tcg_gen_st_tl(temp, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1401 tcg_temp_free(temp);
1402 }
c80f84e3 1403#endif
9a64fbe4 1404 }
9a64fbe4 1405}
79aceca5 1406/* orc & orc. */
26d67362 1407GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1408/* xor & xor. */
9a64fbe4
FB		 1409GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1410{
9a64fbe4 1411 /* Optimisation for "set to zero" case */
26d67362
AJ		 1412 if (rS(ctx->opcode) != rB(ctx->opcode))
1413 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1414 else
1415 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1416 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1417 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1418}
79aceca5
FB		 1419/* ori */
1420GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1421{
76a66253 1422 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1423
9a64fbe4
FB		 1424 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1425 /* NOP */
76a66253 1426 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1427 return;
76a66253 1428 }
26d67362 1429 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1430}
1431/* oris */
1432GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1433{
76a66253 1434 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1435
9a64fbe4
FB		 1436 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1437 /* NOP */
1438 return;
76a66253 1439 }
26d67362 1440 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1441}
1442/* xori */
1443GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1444{
76a66253 1445 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1446
1447 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1448 /* NOP */
1449 return;
1450 }
26d67362 1451 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1452}
79aceca5
FB		 1453/* xoris */
1454GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1455{
76a66253 1456 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1457
1458 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1459 /* NOP */
1460 return;
1461 }
26d67362 1462 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1463}
d9bce9d9 1464/* popcntb : PowerPC 2.03 specification */
05332d70 1465GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1466{
d9bce9d9
JM		 1467#if defined(TARGET_PPC64)
1468 if (ctx->sf_mode)
26d67362 1469 tcg_gen_helper_1_1(helper_popcntb_64, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1470 else
1471#endif
26d67362 1472 tcg_gen_helper_1_1(helper_popcntb, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1473}
1474
1475#if defined(TARGET_PPC64)
1476/* extsw & extsw. */
26d67362 1477GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1478/* cntlzd */
26d67362
AJ		 1479GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1480{
1481 tcg_gen_helper_1_1(helper_cntlzd, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1482 if (unlikely(Rc(ctx->opcode) != 0))
1483 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1484}
d9bce9d9
JM		 1485#endif
1486
79aceca5
FB		 1487/*** Integer rotate ***/
1488/* rlwimi & rlwimi. */
1489GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1490{
76a66253
JM		 1491 target_ulong mask;
1492 uint32_t mb, me, sh;
79aceca5
FB		 1493
1494 mb = MB(ctx->opcode);
1495 me = ME(ctx->opcode);
76a66253 1496 sh = SH(ctx->opcode);
76a66253
JM		 1497 if (likely(sh == 0)) {
1498 if (likely(mb == 0 && me == 31)) {
f78fb44e 1499 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1500 goto do_store;
1501 } else if (likely(mb == 31 && me == 0)) {
f78fb44e 1502 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1503 goto do_store;
1504 }
f78fb44e
AJ		 1505 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1506 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1507 goto do_mask;
1508 }
f78fb44e
AJ		 1509 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1510 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1511 gen_op_rotli32_T0(SH(ctx->opcode));
1512 do_mask:
1513#if defined(TARGET_PPC64)
1514 mb += 32;
1515 me += 32;
1516#endif
1517 mask = MASK(mb, me);
0df5bdbe
AJ		 1518 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1519 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
76a66253
JM		 1520 gen_op_or();
1521 do_store:
f78fb44e 1522 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1523 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1524 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1525}
1526/* rlwinm & rlwinm. */
1527GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1528{
1529 uint32_t mb, me, sh;
3b46e624 1530
79aceca5
FB		 1531 sh = SH(ctx->opcode);
1532 mb = MB(ctx->opcode);
1533 me = ME(ctx->opcode);
f78fb44e 1534 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1535 if (likely(sh == 0)) {
1536 goto do_mask;
1537 }
1538 if (likely(mb == 0)) {
1539 if (likely(me == 31)) {
1540 gen_op_rotli32_T0(sh);
1541 goto do_store;
1542 } else if (likely(me == (31 - sh))) {
1543 gen_op_sli_T0(sh);
1544 goto do_store;
79aceca5 1545 }
76a66253
JM		 1546 } else if (likely(me == 31)) {
1547 if (likely(sh == (32 - mb))) {
1548 gen_op_srli_T0(mb);
1549 goto do_store;
79aceca5
FB		 1550 }
1551 }
76a66253
JM		 1552 gen_op_rotli32_T0(sh);
1553 do_mask:
1554#if defined(TARGET_PPC64)
1555 mb += 32;
1556 me += 32;
1557#endif
0df5bdbe 1558 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
76a66253 1559 do_store:
f78fb44e 1560 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1561 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1562 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1563}
1564/* rlwnm & rlwnm. */
1565GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1566{
1567 uint32_t mb, me;
1568
1569 mb = MB(ctx->opcode);
1570 me = ME(ctx->opcode);
f78fb44e
AJ		 1571 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1572 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 1573 gen_op_rotl32_T0_T1();
1574 if (unlikely(mb != 0 || me != 31)) {
1575#if defined(TARGET_PPC64)
1576 mb += 32;
1577 me += 32;
1578#endif
0df5bdbe 1579 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
79aceca5 1580 }
f78fb44e 1581 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1582 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1583 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1584}
1585
d9bce9d9
JM		 1586#if defined(TARGET_PPC64)
1587#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1588GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1589{ \
1590 gen_##name(ctx, 0); \
1591} \
c7697e1f
JM		 1592GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1593 PPC_64B) \
d9bce9d9
JM		 1594{ \
1595 gen_##name(ctx, 1); \
1596}
1597#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1598GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1599{ \
1600 gen_##name(ctx, 0, 0); \
1601} \
c7697e1f
JM		 1602GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1603 PPC_64B) \
d9bce9d9
JM		 1604{ \
1605 gen_##name(ctx, 0, 1); \
1606} \
c7697e1f
JM		 1607GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1608 PPC_64B) \
d9bce9d9
JM		 1609{ \
1610 gen_##name(ctx, 1, 0); \
1611} \
c7697e1f
JM		 1612GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1613 PPC_64B) \
d9bce9d9
JM		 1614{ \
1615 gen_##name(ctx, 1, 1); \
1616}
51789c41 1617
b068d6a7
JM		 1618static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1619 uint32_t me, uint32_t sh)
51789c41 1620{
f78fb44e 1621 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41
JM		 1622 if (likely(sh == 0)) {
1623 goto do_mask;
1624 }
1625 if (likely(mb == 0)) {
1626 if (likely(me == 63)) {
40d0591e 1627 gen_op_rotli64_T0(sh);
51789c41
JM		 1628 goto do_store;
1629 } else if (likely(me == (63 - sh))) {
1630 gen_op_sli_T0(sh);
1631 goto do_store;
1632 }
1633 } else if (likely(me == 63)) {
1634 if (likely(sh == (64 - mb))) {
40d0591e 1635 gen_op_srli_T0_64(mb);
51789c41
JM		 1636 goto do_store;
1637 }
1638 }
1639 gen_op_rotli64_T0(sh);
1640 do_mask:
0df5bdbe 1641 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1642 do_store:
f78fb44e 1643 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41 1644 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1645 gen_set_Rc0(ctx, cpu_T[0]);
51789c41 1646}
d9bce9d9 1647/* rldicl - rldicl. */
b068d6a7 1648static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1649{
51789c41 1650 uint32_t sh, mb;
d9bce9d9 1651
9d53c753
JM		 1652 sh = SH(ctx->opcode) | (shn << 5);
1653 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1654 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1655}
51789c41 1656GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1657/* rldicr - rldicr. */
b068d6a7 1658static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1659{
51789c41 1660 uint32_t sh, me;
d9bce9d9 1661
9d53c753
JM		 1662 sh = SH(ctx->opcode) | (shn << 5);
1663 me = MB(ctx->opcode) | (men << 5);
51789c41 1664 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1665}
51789c41 1666GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1667/* rldic - rldic. */
b068d6a7 1668static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1669{
51789c41 1670 uint32_t sh, mb;
d9bce9d9 1671
9d53c753
JM		 1672 sh = SH(ctx->opcode) | (shn << 5);
1673 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1674 gen_rldinm(ctx, mb, 63 - sh, sh);
1675}
1676GEN_PPC64_R4(rldic, 0x1E, 0x04);
1677
b068d6a7
JM		 1678static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1679 uint32_t me)
51789c41 1680{
f78fb44e
AJ		 1681 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1682 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
51789c41
JM		 1683 gen_op_rotl64_T0_T1();
1684 if (unlikely(mb != 0 || me != 63)) {
0df5bdbe 1685 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1686 }
f78fb44e 1687 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41 1688 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1689 gen_set_Rc0(ctx, cpu_T[0]);
d9bce9d9 1690}
51789c41 1691
d9bce9d9 1692/* rldcl - rldcl. */
b068d6a7 1693static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1694{
51789c41 1695 uint32_t mb;
d9bce9d9 1696
9d53c753 1697 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1698 gen_rldnm(ctx, mb, 63);
d9bce9d9 1699}
36081602 1700GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1701/* rldcr - rldcr. */
b068d6a7 1702static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1703{
51789c41 1704 uint32_t me;
d9bce9d9 1705
9d53c753 1706 me = MB(ctx->opcode) | (men << 5);
51789c41 1707 gen_rldnm(ctx, 0, me);
d9bce9d9 1708}
36081602 1709GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1710/* rldimi - rldimi. */
b068d6a7 1711static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1712{
51789c41 1713 uint64_t mask;
271a916e 1714 uint32_t sh, mb, me;
d9bce9d9 1715
9d53c753
JM		 1716 sh = SH(ctx->opcode) | (shn << 5);
1717 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1718 me = 63 - sh;
51789c41
JM		 1719 if (likely(sh == 0)) {
1720 if (likely(mb == 0)) {
f78fb44e 1721 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41 1722 goto do_store;
51789c41 1723 }
f78fb44e
AJ		 1724 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1725 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
51789c41
JM		 1726 goto do_mask;
1727 }
f78fb44e
AJ		 1728 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1729 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
40d0591e 1730 gen_op_rotli64_T0(sh);
51789c41 1731 do_mask:
271a916e 1732 mask = MASK(mb, me);
0df5bdbe
AJ		 1733 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1734 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
51789c41
JM		 1735 gen_op_or();
1736 do_store:
f78fb44e 1737 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41 1738 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1739 gen_set_Rc0(ctx, cpu_T[0]);
d9bce9d9 1740}
36081602 1741GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1742#endif
1743
79aceca5
FB		 1744/*** Integer shift ***/
1745/* slw & slw. */
26d67362
AJ		 1746GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1747{
1748 TCGv temp;
1749 int l1, l2;
1750 l1 = gen_new_label();
1751 l2 = gen_new_label();
1752
1753 temp = tcg_temp_local_new(TCG_TYPE_TL);
1754 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
1755 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1756 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1757 tcg_gen_br(l2);
1758 gen_set_label(l1);
1759 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
1760 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1761 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1762 gen_set_label(l2);
1763 tcg_temp_free(temp);
1764 if (unlikely(Rc(ctx->opcode) != 0))
1765 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1766}
79aceca5 1767/* sraw & sraw. */
26d67362
AJ		 1768GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1769{
1770 tcg_gen_helper_1_2(helper_sraw, cpu_gpr[rA(ctx->opcode)],
1771 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1772 if (unlikely(Rc(ctx->opcode) != 0))
1773 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1774}
79aceca5
FB		 1775/* srawi & srawi. */
1776GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1777{
26d67362
AJ		 1778 int sh = SH(ctx->opcode);
1779 if (sh != 0) {
1780 int l1, l2;
1781 TCGv temp;
1782 l1 = gen_new_label();
1783 l2 = gen_new_label();
1784 temp = tcg_temp_local_new(TCG_TYPE_TL);
1785 tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
1786 tcg_gen_brcondi_tl(TCG_COND_GE, temp, 0, l1);
1787 tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1788 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1789 tcg_gen_ori_i32(cpu_xer, cpu_xer, 1 << XER_CA);
1790 tcg_gen_br(l2);
1791 gen_set_label(l1);
1792 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
1793 gen_set_label(l2);
1794 tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
1795 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], temp, sh);
1796 tcg_temp_free(temp);
1797 } else {
1798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1799 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1800 }
76a66253 1801 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1802 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1803}
1804/* srw & srw. */
26d67362
AJ		 1805GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1806{
1807 TCGv temp;
1808 int l1, l2;
1809 l1 = gen_new_label();
1810 l2 = gen_new_label();
d9bce9d9 1811
26d67362
AJ		 1812 temp = tcg_temp_local_new(TCG_TYPE_TL);
1813 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
1814 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1815 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1816 tcg_gen_br(l2);
1817 gen_set_label(l1);
1818 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
1819 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1820 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1821 gen_set_label(l2);
1822 tcg_temp_free(temp);
1823 if (unlikely(Rc(ctx->opcode) != 0))
1824 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1825}
d9bce9d9
JM		 1826#if defined(TARGET_PPC64)
1827/* sld & sld. */
26d67362
AJ		 1828GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1829{
1830 TCGv temp;
1831 int l1, l2;
1832 l1 = gen_new_label();
1833 l2 = gen_new_label();
1834
1835 temp = tcg_temp_local_new(TCG_TYPE_TL);
1836 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
1837 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1838 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1839 tcg_gen_br(l2);
1840 gen_set_label(l1);
1841 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
1842 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1843 gen_set_label(l2);
1844 tcg_temp_free(temp);
1845 if (unlikely(Rc(ctx->opcode) != 0))
1846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1847}
d9bce9d9 1848/* srad & srad. */
26d67362
AJ		 1849GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
1850{
1851 tcg_gen_helper_1_2(helper_srad, cpu_gpr[rA(ctx->opcode)],
1852 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1853 if (unlikely(Rc(ctx->opcode) != 0))
1854 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1855}
d9bce9d9 1856/* sradi & sradi. */
b068d6a7 1857static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 1858{
26d67362 1859 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 1860 if (sh != 0) {
26d67362
AJ		 1861 int l1, l2;
1862 TCGv temp;
1863 l1 = gen_new_label();
1864 l2 = gen_new_label();
1865 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1866 temp = tcg_temp_new(TCG_TYPE_TL);
1867 tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1868 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1869 tcg_gen_ori_i32(cpu_xer, cpu_xer, 1 << XER_CA);
1870 tcg_gen_br(l2);
1871 gen_set_label(l1);
1872 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
1873 gen_set_label(l2);
1874 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1875 } else {
1876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1877 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1878 }
d9bce9d9 1879 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1881}
c7697e1f 1882GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1883{
1884 gen_sradi(ctx, 0);
1885}
c7697e1f 1886GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1887{
1888 gen_sradi(ctx, 1);
1889}
1890/* srd & srd. */
26d67362
AJ		 1891GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
1892{
1893 TCGv temp;
1894 int l1, l2;
1895 l1 = gen_new_label();
1896 l2 = gen_new_label();
1897
1898 temp = tcg_temp_local_new(TCG_TYPE_TL);
1899 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
1900 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1901 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1902 tcg_gen_br(l2);
1903 gen_set_label(l1);
1904 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
1905 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
1906 gen_set_label(l2);
1907 tcg_temp_free(temp);
1908 if (unlikely(Rc(ctx->opcode) != 0))
1909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1910}
d9bce9d9 1911#endif
79aceca5
FB		 1912
1913/*** Floating-Point arithmetic ***/
7c58044c 1914#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1915GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1916{ \
76a66253 1917 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1918 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1919 return; \
1920 } \
a5e26afa
AJ		 1921 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1922 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
1923 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1924 gen_reset_fpstatus(); \
4ecc3190
FB		 1925 gen_op_f##op(); \
1926 if (isfloat) { \
1927 gen_op_frsp(); \
1928 } \
a5e26afa 1929 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1930 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1931}
1932
7c58044c
JM		 1933#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1934_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1935_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1936
7c58044c
JM		 1937#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1938GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1939{ \
76a66253 1940 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1941 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1942 return; \
1943 } \
a5e26afa
AJ		 1944 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1945 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1946 gen_reset_fpstatus(); \
4ecc3190
FB		 1947 gen_op_f##op(); \
1948 if (isfloat) { \
1949 gen_op_frsp(); \
1950 } \
a5e26afa 1951 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1952 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1953}
7c58044c
JM		 1954#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1955_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1956_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1957
7c58044c
JM		 1958#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1959GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1960{ \
76a66253 1961 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1962 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1963 return; \
1964 } \
a5e26afa
AJ		 1965 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1966 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
7c58044c 1967 gen_reset_fpstatus(); \
4ecc3190
FB		 1968 gen_op_f##op(); \
1969 if (isfloat) { \
1970 gen_op_frsp(); \
1971 } \
a5e26afa 1972 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1973 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1974}
7c58044c
JM		 1975#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1976_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1977_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1978
7c58044c 1979#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 1980GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 1981{ \
76a66253 1982 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1983 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1984 return; \
1985 } \
a5e26afa 1986 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1987 gen_reset_fpstatus(); \
9a64fbe4 1988 gen_op_f##name(); \
a5e26afa 1989 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1990 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1991}
1992
7c58044c 1993#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 1994GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 1995{ \
76a66253 1996 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1997 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1998 return; \
1999 } \
a5e26afa 2000 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2001 gen_reset_fpstatus(); \
9a64fbe4 2002 gen_op_f##name(); \
a5e26afa 2003 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2004 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2005}
2006
9a64fbe4 2007/* fadd - fadds */
7c58044c 2008GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2009/* fdiv - fdivs */
7c58044c 2010GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2011/* fmul - fmuls */
7c58044c 2012GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2013
d7e4b87e 2014/* fre */
7c58044c 2015GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2016
a750fc0b 2017/* fres */
7c58044c 2018GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2019
a750fc0b 2020/* frsqrte */
7c58044c
JM		 2021GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2022
2023/* frsqrtes */
2024static always_inline void gen_op_frsqrtes (void)
2025{
2026 gen_op_frsqrte();
2027 gen_op_frsp();
2028}
1b413d55 2029GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 2030
a750fc0b 2031/* fsel */
7c58044c 2032_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2033/* fsub - fsubs */
7c58044c 2034GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2035/* Optional: */
2036/* fsqrt */
a750fc0b 2037GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2038{
76a66253 2039 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2040 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2041 return;
2042 }
a5e26afa 2043 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2044 gen_reset_fpstatus();
c7d344af 2045 gen_op_fsqrt();
a5e26afa 2046 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2047 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 2048}
79aceca5 2049
a750fc0b 2050GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2051{
76a66253 2052 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2053 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2054 return;
2055 }
a5e26afa 2056 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2057 gen_reset_fpstatus();
4ecc3190
FB		 2058 gen_op_fsqrt();
2059 gen_op_frsp();
a5e26afa 2060 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2061 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2062}
2063
2064/*** Floating-Point multiply-and-add ***/
4ecc3190 2065/* fmadd - fmadds */
7c58044c 2066GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2067/* fmsub - fmsubs */
7c58044c 2068GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2069/* fnmadd - fnmadds */
7c58044c 2070GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2071/* fnmsub - fnmsubs */
7c58044c 2072GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2073
2074/*** Floating-Point round & convert ***/
2075/* fctiw */
7c58044c 2076GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2077/* fctiwz */
7c58044c 2078GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2079/* frsp */
7c58044c 2080GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2081#if defined(TARGET_PPC64)
2082/* fcfid */
7c58044c 2083GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2084/* fctid */
7c58044c 2085GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2086/* fctidz */
7c58044c 2087GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2088#endif
79aceca5 2089
d7e4b87e 2090/* frin */
7c58044c 2091GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2092/* friz */
7c58044c 2093GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2094/* frip */
7c58044c 2095GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2096/* frim */
7c58044c 2097GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2098
79aceca5
FB		 2099/*** Floating-Point compare ***/
2100/* fcmpo */
76a66253 2101GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2102{
76a66253 2103 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2104 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2105 return;
2106 }
a5e26afa
AJ		 2107 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2108 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2109 gen_reset_fpstatus();
e1571908 2110 tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2111 gen_op_float_check_status();
79aceca5
FB		 2112}
2113
2114/* fcmpu */
76a66253 2115GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2116{
76a66253 2117 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2118 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2119 return;
2120 }
a5e26afa
AJ		 2121 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2122 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2123 gen_reset_fpstatus();
e1571908 2124 tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2125 gen_op_float_check_status();
79aceca5
FB		 2126}
2127
9a64fbe4
FB		 2128/*** Floating-point move ***/
2129/* fabs */
7c58044c
JM		 2130/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2131GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2132
2133/* fmr - fmr. */
7c58044c 2134/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2135GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2136{
76a66253 2137 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2138 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2139 return;
2140 }
a5e26afa
AJ		 2141 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2142 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2143 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2144}
2145
2146/* fnabs */
7c58044c
JM		 2147/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2148GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2149/* fneg */
7c58044c
JM		 2150/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2151GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2152
79aceca5
FB		 2153/*** Floating-Point status & ctrl register ***/
2154/* mcrfs */
2155GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2156{
7c58044c
JM		 2157 int bfa;
2158
76a66253 2159 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2160 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2161 return;
2162 }
7c58044c
JM		 2163 gen_optimize_fprf();
2164 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2165 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2166 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
7c58044c 2167 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 2168}
2169
2170/* mffs */
2171GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2172{
76a66253 2173 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2174 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2175 return;
2176 }
7c58044c
JM		 2177 gen_optimize_fprf();
2178 gen_reset_fpstatus();
2179 gen_op_load_fpscr_FT0();
a5e26afa 2180 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2181 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2182}
2183
2184/* mtfsb0 */
2185GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2186{
fb0eaffc 2187 uint8_t crb;
3b46e624 2188
76a66253 2189 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2190 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2191 return;
2192 }
7c58044c
JM		 2193 crb = 32 - (crbD(ctx->opcode) >> 2);
2194 gen_optimize_fprf();
2195 gen_reset_fpstatus();
2196 if (likely(crb != 30 && crb != 29))
2197 gen_op_fpscr_resetbit(~(1 << crb));
2198 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2199 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2200 }
79aceca5
FB		 2201}
2202
2203/* mtfsb1 */
2204GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2205{
fb0eaffc 2206 uint8_t crb;
3b46e624 2207
76a66253 2208 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2209 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2210 return;
2211 }
7c58044c
JM		 2212 crb = 32 - (crbD(ctx->opcode) >> 2);
2213 gen_optimize_fprf();
2214 gen_reset_fpstatus();
2215 /* XXX: we pretend we can only do IEEE floating-point computations */
2216 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2217 gen_op_fpscr_setbit(crb);
2218 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2219 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2220 }
2221 /* We can raise a differed exception */
2222 gen_op_float_check_status();
79aceca5
FB		 2223}
2224
2225/* mtfsf */
2226GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2227{
76a66253 2228 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2229 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2230 return;
2231 }
7c58044c 2232 gen_optimize_fprf();
a5e26afa 2233 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2234 gen_reset_fpstatus();
28b6751f 2235 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c 2236 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2237 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2238 }
2239 /* We can raise a differed exception */
2240 gen_op_float_check_status();
79aceca5
FB		 2241}
2242
2243/* mtfsfi */
2244GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2245{
7c58044c
JM		 2246 int bf, sh;
2247
76a66253 2248 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2249 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2250 return;
2251 }
7c58044c
JM		 2252 bf = crbD(ctx->opcode) >> 2;
2253 sh = 7 - bf;
2254 gen_optimize_fprf();
489251fa 2255 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
7c58044c
JM		 2256 gen_reset_fpstatus();
2257 gen_op_store_fpscr(1 << sh);
2258 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2259 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2260 }
2261 /* We can raise a differed exception */
2262 gen_op_float_check_status();
79aceca5
FB		 2263}
2264
76a66253
JM		 2265/*** Addressing modes ***/
2266/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2267static always_inline void gen_addr_imm_index (TCGv EA,
2268 DisasContext *ctx,
b068d6a7 2269 target_long maskl)
76a66253
JM		 2270{
2271 target_long simm = SIMM(ctx->opcode);
2272
be147d08 2273 simm &= ~maskl;
e2be8d8d
AJ		 2274 if (rA(ctx->opcode) == 0)
2275 tcg_gen_movi_tl(EA, simm);
2276 else if (likely(simm != 0))
2277 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2278 else
2279 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2280}
2281
e2be8d8d
AJ		 2282static always_inline void gen_addr_reg_index (TCGv EA,
2283 DisasContext *ctx)
76a66253 2284{
e2be8d8d
AJ		 2285 if (rA(ctx->opcode) == 0)
2286 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2287 else
2288 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2289}
2290
e2be8d8d
AJ		 2291static always_inline void gen_addr_register (TCGv EA,
2292 DisasContext *ctx)
76a66253 2293{
e2be8d8d
AJ		 2294 if (rA(ctx->opcode) == 0)
2295 tcg_gen_movi_tl(EA, 0);
2296 else
2297 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2298}
2299
7863667f
JM		 2300#if defined(TARGET_PPC64)
2301#define _GEN_MEM_FUNCS(name, mode) \
2302 &gen_op_##name##_##mode, \
2303 &gen_op_##name##_le_##mode, \
2304 &gen_op_##name##_64_##mode, \
2305 &gen_op_##name##_le_64_##mode
2306#else
2307#define _GEN_MEM_FUNCS(name, mode) \
2308 &gen_op_##name##_##mode, \
2309 &gen_op_##name##_le_##mode
2310#endif
9a64fbe4 2311#if defined(CONFIG_USER_ONLY)
d9bce9d9 2312#if defined(TARGET_PPC64)
7863667f 2313#define NB_MEM_FUNCS 4
d9bce9d9 2314#else
7863667f 2315#define NB_MEM_FUNCS 2
d9bce9d9 2316#endif
7863667f
JM		 2317#define GEN_MEM_FUNCS(name) \
2318 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2319#else
d9bce9d9 2320#if defined(TARGET_PPC64)
7863667f 2321#define NB_MEM_FUNCS 12
2857068e 2322#else
7863667f 2323#define NB_MEM_FUNCS 6
2857068e 2324#endif
7863667f
JM		 2325#define GEN_MEM_FUNCS(name) \
2326 _GEN_MEM_FUNCS(name, user), \
2327 _GEN_MEM_FUNCS(name, kernel), \
2328 _GEN_MEM_FUNCS(name, hypv)
2329#endif
2330
2331/*** Integer load ***/
2332#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
d9bce9d9 2333#define OP_LD_TABLE(width) \
7863667f
JM		 2334static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2335 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2336};
2337#define OP_ST_TABLE(width) \
7863667f
JM		 2338static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2339 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2340};
9a64fbe4 2341
b61f2753
AJ		 2342
2343#if defined(TARGET_PPC64)
2344#define GEN_QEMU_LD_PPC64(width) \
2345static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2346{ \
2347 if (likely(flags & 2)) \
2348 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2349 else { \
2350 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2351 tcg_gen_ext32u_tl(addr, t1); \
2352 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2353 tcg_temp_free(addr); \
2354 } \
2355}
2356GEN_QEMU_LD_PPC64(8u)
2357GEN_QEMU_LD_PPC64(8s)
2358GEN_QEMU_LD_PPC64(16u)
2359GEN_QEMU_LD_PPC64(16s)
2360GEN_QEMU_LD_PPC64(32u)
2361GEN_QEMU_LD_PPC64(32s)
2362GEN_QEMU_LD_PPC64(64)
2363
2364#define GEN_QEMU_ST_PPC64(width) \
2365static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2366{ \
2367 if (likely(flags & 2)) \
2368 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2369 else { \
2370 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2371 tcg_gen_ext32u_tl(addr, t1); \
2372 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2373 tcg_temp_free(addr); \
2374 } \
2375}
2376GEN_QEMU_ST_PPC64(8)
2377GEN_QEMU_ST_PPC64(16)
2378GEN_QEMU_ST_PPC64(32)
2379GEN_QEMU_ST_PPC64(64)
2380
2381static always_inline void gen_qemu_ld8u(TCGv t0, TCGv t1, int flags)
2382{
2383 gen_qemu_ld8u_ppc64(t0, t1, flags);
2384}
2385
2386static always_inline void gen_qemu_ld8s(TCGv t0, TCGv t1, int flags)
2387{
2388 gen_qemu_ld8s_ppc64(t0, t1, flags);
2389}
2390
2391static always_inline void gen_qemu_ld16u(TCGv t0, TCGv t1, int flags)
2392{
2393 if (unlikely(flags & 1)) {
2394 TCGv t0_32;
2395 gen_qemu_ld16u_ppc64(t0, t1, flags);
2396 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2397 tcg_gen_trunc_tl_i32(t0_32, t0);
2398 tcg_gen_bswap16_i32(t0_32, t0_32);
2399 tcg_gen_extu_i32_tl(t0, t0_32);
2400 tcg_temp_free(t0_32);
2401 } else
2402 gen_qemu_ld16u_ppc64(t0, t1, flags);
2403}
2404
2405static always_inline void gen_qemu_ld16s(TCGv t0, TCGv t1, int flags)
2406{
2407 if (unlikely(flags & 1)) {
2408 TCGv t0_32;
2409 gen_qemu_ld16u_ppc64(t0, t1, flags);
2410 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2411 tcg_gen_trunc_tl_i32(t0_32, t0);
2412 tcg_gen_bswap16_i32(t0_32, t0_32);
2413 tcg_gen_extu_i32_tl(t0, t0_32);
2414 tcg_gen_ext16s_tl(t0, t0);
2415 tcg_temp_free(t0_32);
2416 } else
2417 gen_qemu_ld16s_ppc64(t0, t1, flags);
2418}
2419
2420static always_inline void gen_qemu_ld32u(TCGv t0, TCGv t1, int flags)
2421{
2422 if (unlikely(flags & 1)) {
2423 TCGv t0_32;
2424 gen_qemu_ld32u_ppc64(t0, t1, flags);
2425 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2426 tcg_gen_trunc_tl_i32(t0_32, t0);
2427 tcg_gen_bswap_i32(t0_32, t0_32);
2428 tcg_gen_extu_i32_tl(t0, t0_32);
2429 tcg_temp_free(t0_32);
2430 } else
2431 gen_qemu_ld32u_ppc64(t0, t1, flags);
2432}
2433
2434static always_inline void gen_qemu_ld32s(TCGv t0, TCGv t1, int flags)
2435{
2436 if (unlikely(flags & 1)) {
2437 TCGv t0_32;
2438 gen_qemu_ld32u_ppc64(t0, t1, flags);
2439 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2440 tcg_gen_trunc_tl_i32(t0_32, t0);
2441 tcg_gen_bswap_i32(t0_32, t0_32);
2442 tcg_gen_ext_i32_tl(t0, t0_32);
2443 tcg_temp_free(t0_32);
2444 } else
2445 gen_qemu_ld32s_ppc64(t0, t1, flags);
2446}
2447
2448static always_inline void gen_qemu_ld64(TCGv t0, TCGv t1, int flags)
2449{
2450 gen_qemu_ld64_ppc64(t0, t1, flags);
2451 if (unlikely(flags & 1))
2452 tcg_gen_bswap_i64(t0, t0);
2453}
2454
2455static always_inline void gen_qemu_st8(TCGv t0, TCGv t1, int flags)
2456{
2457 gen_qemu_st8_ppc64(t0, t1, flags);
2458}
2459
2460static always_inline void gen_qemu_st16(TCGv t0, TCGv t1, int flags)
2461{
2462 if (unlikely(flags & 1)) {
2463 TCGv temp1, temp2;
2464 temp1 = tcg_temp_new(TCG_TYPE_I32);
2465 tcg_gen_trunc_tl_i32(temp1, t0);
2466 tcg_gen_ext16u_i32(temp1, temp1);
2467 tcg_gen_bswap16_i32(temp1, temp1);
2468 temp2 = tcg_temp_new(TCG_TYPE_I64);
2469 tcg_gen_extu_i32_tl(temp2, temp1);
2470 tcg_temp_free(temp1);
2471 gen_qemu_st16_ppc64(temp2, t1, flags);
2472 tcg_temp_free(temp2);
2473 } else
2474 gen_qemu_st16_ppc64(t0, t1, flags);
2475}
2476
2477static always_inline void gen_qemu_st32(TCGv t0, TCGv t1, int flags)
2478{
2479 if (unlikely(flags & 1)) {
2480 TCGv temp1, temp2;
2481 temp1 = tcg_temp_new(TCG_TYPE_I32);
2482 tcg_gen_trunc_tl_i32(temp1, t0);
2483 tcg_gen_bswap_i32(temp1, temp1);
2484 temp2 = tcg_temp_new(TCG_TYPE_I64);
2485 tcg_gen_extu_i32_tl(temp2, temp1);
2486 tcg_temp_free(temp1);
2487 gen_qemu_st32_ppc64(temp2, t1, flags);
2488 tcg_temp_free(temp2);
2489 } else
2490 gen_qemu_st32_ppc64(t0, t1, flags);
2491}
2492
2493static always_inline void gen_qemu_st64(TCGv t0, TCGv t1, int flags)
2494{
2495 if (unlikely(flags & 1)) {
2496 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2497 tcg_gen_bswap_i64(temp, t0);
2498 gen_qemu_st64_ppc64(temp, t1, flags);
2499 tcg_temp_free(temp);
2500 } else
2501 gen_qemu_st64_ppc64(t0, t1, flags);
2502}
2503
2504
2505#else /* defined(TARGET_PPC64) */
2506#define GEN_QEMU_LD_PPC32(width) \
2507static always_inline void gen_qemu_ld##width##_ppc32(TCGv t0, TCGv t1, int flags)\
2508{ \
2509 tcg_gen_qemu_ld##width(t0, t1, flags >> 1); \
2510}
2511GEN_QEMU_LD_PPC32(8u)
2512GEN_QEMU_LD_PPC32(8s)
2513GEN_QEMU_LD_PPC32(16u)
2514GEN_QEMU_LD_PPC32(16s)
2515GEN_QEMU_LD_PPC32(32u)
2516GEN_QEMU_LD_PPC32(32s)
2517GEN_QEMU_LD_PPC32(64)
2518
2519#define GEN_QEMU_ST_PPC32(width) \
2520static always_inline void gen_qemu_st##width##_ppc32(TCGv t0, TCGv t1, int flags)\
2521{ \
2522 tcg_gen_qemu_st##width(t0, t1, flags >> 1); \
2523}
2524GEN_QEMU_ST_PPC32(8)
2525GEN_QEMU_ST_PPC32(16)
2526GEN_QEMU_ST_PPC32(32)
2527GEN_QEMU_ST_PPC32(64)
2528
2529static always_inline void gen_qemu_ld8u(TCGv t0, TCGv t1, int flags)
2530{
2531 gen_qemu_ld8u_ppc32(t0, t1, flags >> 1);
2532}
2533
2534static always_inline void gen_qemu_ld8s(TCGv t0, TCGv t1, int flags)
2535{
2536 gen_qemu_ld8s_ppc32(t0, t1, flags >> 1);
2537}
2538
2539static always_inline void gen_qemu_ld16u(TCGv t0, TCGv t1, int flags)
2540{
2541 gen_qemu_ld16u_ppc32(t0, t1, flags >> 1);
2542 if (unlikely(flags & 1))
2543 tcg_gen_bswap16_i32(t0, t0);
2544}
2545
2546static always_inline void gen_qemu_ld16s(TCGv t0, TCGv t1, int flags)
2547{
2548 if (unlikely(flags & 1)) {
2549 gen_qemu_ld16u_ppc32(t0, t1, flags);
2550 tcg_gen_bswap16_i32(t0, t0);
2551 tcg_gen_ext16s_i32(t0, t0);
2552 } else
2553 gen_qemu_ld16s_ppc32(t0, t1, flags);
2554}
2555
2556static always_inline void gen_qemu_ld32u(TCGv t0, TCGv t1, int flags)
2557{
2558 gen_qemu_ld32u_ppc32(t0, t1, flags);
2559 if (unlikely(flags & 1))
2560 tcg_gen_bswap_i32(t0, t0);
2561}
2562
2563static always_inline void gen_qemu_ld64(TCGv t0, TCGv t1, int flags)
2564{
2565 gen_qemu_ld64_ppc32(t0, t1, flags);
2566 if (unlikely(flags & 1))
2567 tcg_gen_bswap_i64(t0, t0);
2568}
2569
2570static always_inline void gen_qemu_st8(TCGv t0, TCGv t1, int flags)
2571{
2572 gen_qemu_st8_ppc32(t0, t1, flags >> 1);
2573}
2574
2575static always_inline void gen_qemu_st16(TCGv t0, TCGv t1, int flags)
2576{
2577 if (unlikely(flags & 1)) {
2578 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2579 tcg_gen_ext16u_i32(temp, t0);
2580 tcg_gen_bswap16_i32(temp, temp);
2581 gen_qemu_st16_ppc32(temp, t1, flags >> 1);
2582 tcg_temp_free(temp);
2583 } else
2584 gen_qemu_st16_ppc32(t0, t1, flags >> 1);
2585}
2586
2587static always_inline void gen_qemu_st32(TCGv t0, TCGv t1, int flags)
2588{
2589 if (unlikely(flags & 1)) {
2590 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2591 tcg_gen_bswap_i32(temp, t0);
2592 gen_qemu_st32_ppc32(temp, t1, flags >> 1);
2593 tcg_temp_free(temp);
2594 } else
2595 gen_qemu_st32_ppc32(t0, t1, flags >> 1);
2596}
2597
2598static always_inline void gen_qemu_st64(TCGv t0, TCGv t1, int flags)
2599{
2600 if (unlikely(flags & 1)) {
2601 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2602 tcg_gen_bswap_i64(temp, t0);
2603 gen_qemu_st64_ppc32(temp, t1, flags >> 1);
2604 tcg_temp_free(temp);
2605 } else
2606 gen_qemu_st64_ppc32(t0, t1, flags >> 1);
2607}
2608
2609#endif
2610
d9bce9d9
JM		 2611#define GEN_LD(width, opc, type) \
2612GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2613{ \
b61f2753
AJ		 2614 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2615 gen_addr_imm_index(EA, ctx, 0); \
2616 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2617 tcg_temp_free(EA); \
79aceca5
FB		 2618}
2619
d9bce9d9
JM		 2620#define GEN_LDU(width, opc, type) \
2621GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2622{ \
b61f2753 2623 TCGv EA; \
76a66253
JM		 2624 if (unlikely(rA(ctx->opcode) == 0 || \
2625 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2626 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2627 return; \
9a64fbe4 2628 } \
b61f2753 2629 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2630 if (type == PPC_64B) \
b61f2753 2631 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2632 else \
b61f2753
AJ		 2633 gen_addr_imm_index(EA, ctx, 0); \
2634 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2635 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2636 tcg_temp_free(EA); \
79aceca5
FB		 2637}
2638
d9bce9d9
JM		 2639#define GEN_LDUX(width, opc2, opc3, type) \
2640GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2641{ \
b61f2753 2642 TCGv EA; \
76a66253
JM		 2643 if (unlikely(rA(ctx->opcode) == 0 || \
2644 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2645 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2646 return; \
9a64fbe4 2647 } \
b61f2753
AJ		 2648 EA = tcg_temp_new(TCG_TYPE_TL); \
2649 gen_addr_reg_index(EA, ctx); \
2650 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2651 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2652 tcg_temp_free(EA); \
79aceca5
FB		 2653}
2654
d9bce9d9
JM		 2655#define GEN_LDX(width, opc2, opc3, type) \
2656GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2657{ \
b61f2753
AJ		 2658 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2659 gen_addr_reg_index(EA, ctx); \
2660 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2661 tcg_temp_free(EA); \
79aceca5
FB		 2662}
2663
d9bce9d9 2664#define GEN_LDS(width, op, type) \
d9bce9d9
JM		 2665GEN_LD(width, op | 0x20, type); \
2666GEN_LDU(width, op | 0x21, type); \
2667GEN_LDUX(width, 0x17, op | 0x01, type); \
2668GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2669
2670/* lbz lbzu lbzux lbzx */
b61f2753 2671GEN_LDS(8u, 0x02, PPC_INTEGER);
79aceca5 2672/* lha lhau lhaux lhax */
b61f2753 2673GEN_LDS(16s, 0x0A, PPC_INTEGER);
79aceca5 2674/* lhz lhzu lhzux lhzx */
b61f2753 2675GEN_LDS(16u, 0x08, PPC_INTEGER);
79aceca5 2676/* lwz lwzu lwzux lwzx */
b61f2753 2677GEN_LDS(32u, 0x00, PPC_INTEGER);
d9bce9d9 2678#if defined(TARGET_PPC64)
d9bce9d9 2679/* lwaux */
b61f2753 2680GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2681/* lwax */
b61f2753 2682GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2683/* ldux */
b61f2753 2684GEN_LDUX(64, 0x15, 0x01, PPC_64B);
d9bce9d9 2685/* ldx */
b61f2753 2686GEN_LDX(64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2687GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2688{
b61f2753 2689 TCGv EA;
d9bce9d9
JM		 2690 if (Rc(ctx->opcode)) {
2691 if (unlikely(rA(ctx->opcode) == 0 ||
2692 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2693 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2694 return;
2695 }
2696 }
b61f2753
AJ		 2697 EA = tcg_temp_new(TCG_TYPE_TL);
2698 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2699 if (ctx->opcode & 0x02) {
2700 /* lwa (lwau is undefined) */
b61f2753 2701 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2702 } else {
2703 /* ld - ldu */
b61f2753 2704 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2705 }
d9bce9d9 2706 if (Rc(ctx->opcode))
b61f2753
AJ		 2707 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2708 tcg_temp_free(EA);
d9bce9d9 2709}
be147d08
JM		 2710/* lq */
2711GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2712{
2713#if defined(CONFIG_USER_ONLY)
2714 GEN_EXCP_PRIVOPC(ctx);
2715#else
2716 int ra, rd;
b61f2753 2717 TCGv EA;
be147d08
JM		 2718
2719 /* Restore CPU state */
2720 if (unlikely(ctx->supervisor == 0)) {
2721 GEN_EXCP_PRIVOPC(ctx);
2722 return;
2723 }
2724 ra = rA(ctx->opcode);
2725 rd = rD(ctx->opcode);
2726 if (unlikely((rd & 1) || rd == ra)) {
2727 GEN_EXCP_INVAL(ctx);
2728 return;
2729 }
2730 if (unlikely(ctx->mem_idx & 1)) {
2731 /* Little-endian mode is not handled */
2732 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2733 return;
2734 }
b61f2753
AJ		 2735 EA = tcg_temp_new(TCG_TYPE_TL);
2736 gen_addr_imm_index(EA, ctx, 0x0F);
2737 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2738 tcg_gen_addi_tl(EA, EA, 8);
2739 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2740 tcg_temp_free(EA);
be147d08
JM		 2741#endif
2742}
d9bce9d9 2743#endif
79aceca5
FB		 2744
2745/*** Integer store ***/
d9bce9d9
JM		 2746#define GEN_ST(width, opc, type) \
2747GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2748{ \
b61f2753
AJ		 2749 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2750 gen_addr_imm_index(EA, ctx, 0); \
2751 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2752 tcg_temp_free(EA); \
79aceca5
FB		 2753}
2754
d9bce9d9
JM		 2755#define GEN_STU(width, opc, type) \
2756GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2757{ \
b61f2753 2758 TCGv EA; \
76a66253 2759 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2760 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2761 return; \
9a64fbe4 2762 } \
b61f2753 2763 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2764 if (type == PPC_64B) \
b61f2753 2765 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2766 else \
b61f2753
AJ		 2767 gen_addr_imm_index(EA, ctx, 0); \
2768 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
79aceca5
FB		 2771}
2772
d9bce9d9
JM		 2773#define GEN_STUX(width, opc2, opc3, type) \
2774GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2775{ \
b61f2753 2776 TCGv EA; \
76a66253 2777 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2778 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2779 return; \
9a64fbe4 2780 } \
b61f2753
AJ		 2781 EA = tcg_temp_new(TCG_TYPE_TL); \
2782 gen_addr_reg_index(EA, ctx); \
2783 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2784 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2785 tcg_temp_free(EA); \
79aceca5
FB		 2786}
2787
d9bce9d9
JM		 2788#define GEN_STX(width, opc2, opc3, type) \
2789GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2790{ \
b61f2753
AJ		 2791 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2792 gen_addr_reg_index(EA, ctx); \
2793 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2794 tcg_temp_free(EA); \
79aceca5
FB		 2795}
2796
d9bce9d9 2797#define GEN_STS(width, op, type) \
d9bce9d9
JM		 2798GEN_ST(width, op | 0x20, type); \
2799GEN_STU(width, op | 0x21, type); \
2800GEN_STUX(width, 0x17, op | 0x01, type); \
2801GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2802
2803/* stb stbu stbux stbx */
b61f2753 2804GEN_STS(8, 0x06, PPC_INTEGER);
79aceca5 2805/* sth sthu sthux sthx */
b61f2753 2806GEN_STS(16, 0x0C, PPC_INTEGER);
79aceca5 2807/* stw stwu stwux stwx */
b61f2753 2808GEN_STS(32, 0x04, PPC_INTEGER);
d9bce9d9 2809#if defined(TARGET_PPC64)
b61f2753
AJ		 2810GEN_STUX(64, 0x15, 0x05, PPC_64B);
2811GEN_STX(64, 0x15, 0x04, PPC_64B);
be147d08 2812GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2813{
be147d08 2814 int rs;
b61f2753 2815 TCGv EA;
be147d08
JM		 2816
2817 rs = rS(ctx->opcode);
2818 if ((ctx->opcode & 0x3) == 0x2) {
2819#if defined(CONFIG_USER_ONLY)
2820 GEN_EXCP_PRIVOPC(ctx);
2821#else
2822 /* stq */
2823 if (unlikely(ctx->supervisor == 0)) {
2824 GEN_EXCP_PRIVOPC(ctx);
2825 return;
2826 }
2827 if (unlikely(rs & 1)) {
e1833e1f 2828 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2829 return;
2830 }
be147d08
JM		 2831 if (unlikely(ctx->mem_idx & 1)) {
2832 /* Little-endian mode is not handled */
2833 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2834 return;
2835 }
b61f2753
AJ		 2836 EA = tcg_temp_new(TCG_TYPE_TL);
2837 gen_addr_imm_index(EA, ctx, 0x03);
2838 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
2839 tcg_gen_addi_tl(EA, EA, 8);
2840 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
2841 tcg_temp_free(EA);
be147d08
JM		 2842#endif
2843 } else {
2844 /* std / stdu */
2845 if (Rc(ctx->opcode)) {
2846 if (unlikely(rA(ctx->opcode) == 0)) {
2847 GEN_EXCP_INVAL(ctx);
2848 return;
2849 }
2850 }
b61f2753
AJ		 2851 EA = tcg_temp_new(TCG_TYPE_TL);
2852 gen_addr_imm_index(EA, ctx, 0x03);
2853 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 2854 if (Rc(ctx->opcode))
b61f2753
AJ		 2855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2856 tcg_temp_free(EA);
d9bce9d9 2857 }
d9bce9d9
JM		 2858}
2859#endif
79aceca5
FB		 2860/*** Integer load and store with byte reverse ***/
2861/* lhbrx */
b61f2753
AJ		 2862void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
2863{
2864 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2865 gen_qemu_ld16u(temp, t1, flags);
2866 tcg_gen_bswap16_i32(temp, temp);
2867 tcg_gen_extu_i32_tl(t0, temp);
2868 tcg_temp_free(temp);
2869}
2870GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
2871
79aceca5 2872/* lwbrx */
b61f2753
AJ		 2873void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
2874{
2875 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2876 gen_qemu_ld32u(temp, t1, flags);
2877 tcg_gen_bswap_i32(temp, temp);
2878 tcg_gen_extu_i32_tl(t0, temp);
2879 tcg_temp_free(temp);
2880}
2881GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
2882
79aceca5 2883/* sthbrx */
b61f2753
AJ		 2884void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
2885{
2886 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2887 tcg_gen_trunc_tl_i32(temp, t0);
2888 tcg_gen_ext16u_i32(temp, temp);
2889 tcg_gen_bswap16_i32(temp, temp);
2890 gen_qemu_st16(temp, t1, flags);
2891 tcg_temp_free(temp);
2892}
2893GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
2894
79aceca5 2895/* stwbrx */
b61f2753
AJ		 2896void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
2897{
2898 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2899 tcg_gen_trunc_tl_i32(temp, t0);
2900 tcg_gen_bswap_i32(temp, temp);
2901 gen_qemu_st32(temp, t1, flags);
2902 tcg_temp_free(temp);
2903}
2904GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2905
2906/*** Integer load and store multiple ***/
111bfab3 2907#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 2908static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2909 GEN_MEM_FUNCS(lmw),
d9bce9d9 2910};
7863667f
JM		 2911static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2912 GEN_MEM_FUNCS(stmw),
d9bce9d9 2913};
9a64fbe4 2914
79aceca5
FB		 2915/* lmw */
2916GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2917{
76a66253 2918 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2919 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2920 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2921 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2922}
2923
2924/* stmw */
2925GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2926{
76a66253 2927 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2928 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2929 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2930 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2931}
2932
2933/*** Integer load and store strings ***/
9a64fbe4
FB		 2934#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2935#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 2936/* string load & stores are by definition endian-safe */
2937#define gen_op_lswi_le_raw gen_op_lswi_raw
2938#define gen_op_lswi_le_user gen_op_lswi_user
2939#define gen_op_lswi_le_kernel gen_op_lswi_kernel
2940#define gen_op_lswi_le_hypv gen_op_lswi_hypv
2941#define gen_op_lswi_le_64_raw gen_op_lswi_raw
2942#define gen_op_lswi_le_64_user gen_op_lswi_user
2943#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2944#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 2945static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2946 GEN_MEM_FUNCS(lswi),
d9bce9d9 2947};
e7c24003
JM		 2948#define gen_op_lswx_le_raw gen_op_lswx_raw
2949#define gen_op_lswx_le_user gen_op_lswx_user
2950#define gen_op_lswx_le_kernel gen_op_lswx_kernel
2951#define gen_op_lswx_le_hypv gen_op_lswx_hypv
2952#define gen_op_lswx_le_64_raw gen_op_lswx_raw
2953#define gen_op_lswx_le_64_user gen_op_lswx_user
2954#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2955#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 2956static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2957 GEN_MEM_FUNCS(lswx),
d9bce9d9 2958};
e7c24003
JM		 2959#define gen_op_stsw_le_raw gen_op_stsw_raw
2960#define gen_op_stsw_le_user gen_op_stsw_user
2961#define gen_op_stsw_le_kernel gen_op_stsw_kernel
2962#define gen_op_stsw_le_hypv gen_op_stsw_hypv
2963#define gen_op_stsw_le_64_raw gen_op_stsw_raw
2964#define gen_op_stsw_le_64_user gen_op_stsw_user
2965#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2966#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 2967static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2968 GEN_MEM_FUNCS(stsw),
9a64fbe4 2969};
9a64fbe4 2970
79aceca5 2971/* lswi */
3fc6c082 2972/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2973 * rA is in the range of registers to be loaded.
2974 * In an other hand, IBM says this is valid, but rA won't be loaded.
2975 * For now, I'll follow the spec...
2976 */
05332d70 2977GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 2978{
2979 int nb = NB(ctx->opcode);
2980 int start = rD(ctx->opcode);
9a64fbe4 2981 int ra = rA(ctx->opcode);
79aceca5
FB		 2982 int nr;
2983
2984 if (nb == 0)
2985 nb = 32;
2986 nr = nb / 4;
76a66253
JM		 2987 if (unlikely(((start + nr) > 32 &&
2988 start <= ra && (start + nr - 32) > ra) ||
2989 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 2990 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2991 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2992 return;
297d8e62 2993 }
8dd4983c 2994 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2995 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2996 gen_addr_register(cpu_T[0], ctx);
86c581dc 2997 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 2998 op_ldsts(lswi, start);
79aceca5
FB		 2999}
3000
3001/* lswx */
05332d70 3002GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3003{
9a64fbe4
FB		 3004 int ra = rA(ctx->opcode);
3005 int rb = rB(ctx->opcode);
3006
76a66253 3007 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3008 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3009 gen_addr_reg_index(cpu_T[0], ctx);
9a64fbe4 3010 if (ra == 0) {
9a64fbe4 3011 ra = rb;
79aceca5 3012 }
3d7b417e 3013 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3014 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 3015}
3016
3017/* stswi */
05332d70 3018GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3019{
4b3686fa
FB		 3020 int nb = NB(ctx->opcode);
3021
76a66253 3022 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3023 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3024 gen_addr_register(cpu_T[0], ctx);
4b3686fa
FB		 3025 if (nb == 0)
3026 nb = 32;
86c581dc 3027 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3028 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3029}
3030
3031/* stswx */
05332d70 3032GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3033{
8dd4983c 3034 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3035 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3036 gen_addr_reg_index(cpu_T[0], ctx);
3d7b417e 3037 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3038 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3039}
3040
3041/*** Memory synchronisation ***/
3042/* eieio */
0db1b20e 3043GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3044{
79aceca5
FB		 3045}
3046
3047/* isync */
0db1b20e 3048GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3049{
e1833e1f 3050 GEN_STOP(ctx);
79aceca5
FB		 3051}
3052
111bfab3
FB		 3053#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3054#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 3055static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3056 GEN_MEM_FUNCS(lwarx),
111bfab3 3057};
7863667f
JM		 3058static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3059 GEN_MEM_FUNCS(stwcx),
985a19d6 3060};
9a64fbe4 3061
111bfab3 3062/* lwarx */
76a66253 3063GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3064{
30032c94
JM		 3065 /* NIP cannot be restored if the memory exception comes from an helper */
3066 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3067 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 3068 op_lwarx();
f78fb44e 3069 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 3070}
3071
3072/* stwcx. */
c7697e1f 3073GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3074{
30032c94
JM		 3075 /* NIP cannot be restored if the memory exception comes from an helper */
3076 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3077 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3078 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 3079 op_stwcx();
79aceca5
FB		 3080}
3081
426613db
JM		 3082#if defined(TARGET_PPC64)
3083#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3084#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 3085static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3086 GEN_MEM_FUNCS(ldarx),
426613db 3087};
7863667f
JM		 3088static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3089 GEN_MEM_FUNCS(stdcx),
426613db 3090};
426613db
JM		 3091
3092/* ldarx */
a750fc0b 3093GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3094{
30032c94
JM		 3095 /* NIP cannot be restored if the memory exception comes from an helper */
3096 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3097 gen_addr_reg_index(cpu_T[0], ctx);
426613db 3098 op_ldarx();
f78fb44e 3099 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 3100}
3101
3102/* stdcx. */
c7697e1f 3103GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3104{
30032c94
JM		 3105 /* NIP cannot be restored if the memory exception comes from an helper */
3106 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3107 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3108 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 3109 op_stdcx();
3110}
3111#endif /* defined(TARGET_PPC64) */
3112
79aceca5 3113/* sync */
a902d886 3114GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3115{
79aceca5
FB		 3116}
3117
0db1b20e
JM		 3118/* wait */
3119GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3120{
3121 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 3122 gen_op_wait();
3123 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3124}
3125
79aceca5 3126/*** Floating-point load ***/
477023a6
JM		 3127#define GEN_LDF(width, opc, type) \
3128GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3129{ \
76a66253 3130 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3131 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3132 return; \
3133 } \
e2be8d8d 3134 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3135 op_ldst(l##width); \
a5e26afa 3136 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3137}
3138
477023a6
JM		 3139#define GEN_LDUF(width, opc, type) \
3140GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3141{ \
76a66253 3142 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3143 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3144 return; \
3145 } \
76a66253 3146 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3147 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3148 return; \
9a64fbe4 3149 } \
e2be8d8d 3150 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3151 op_ldst(l##width); \
a5e26afa 3152 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3153 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3154}
3155
477023a6
JM		 3156#define GEN_LDUXF(width, opc, type) \
3157GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3158{ \
76a66253 3159 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3160 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3161 return; \
3162 } \
76a66253 3163 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3164 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3165 return; \
9a64fbe4 3166 } \
e2be8d8d 3167 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3168 op_ldst(l##width); \
a5e26afa 3169 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3170 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3171}
3172
477023a6
JM		 3173#define GEN_LDXF(width, opc2, opc3, type) \
3174GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3175{ \
76a66253 3176 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3177 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3178 return; \
3179 } \
e2be8d8d 3180 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3181 op_ldst(l##width); \
a5e26afa 3182 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3183}
3184
477023a6 3185#define GEN_LDFS(width, op, type) \
9a64fbe4 3186OP_LD_TABLE(width); \
477023a6
JM		 3187GEN_LDF(width, op | 0x20, type); \
3188GEN_LDUF(width, op | 0x21, type); \
3189GEN_LDUXF(width, op | 0x01, type); \
3190GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3191
3192/* lfd lfdu lfdux lfdx */
477023a6 3193GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 3194/* lfs lfsu lfsux lfsx */
477023a6 3195GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3196
3197/*** Floating-point store ***/
477023a6
JM		 3198#define GEN_STF(width, opc, type) \
3199GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3200{ \
76a66253 3201 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3202 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3203 return; \
3204 } \
e2be8d8d 3205 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3206 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3207 op_ldst(st##width); \
79aceca5
FB		 3208}
3209
477023a6
JM		 3210#define GEN_STUF(width, opc, type) \
3211GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3212{ \
76a66253 3213 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3214 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3215 return; \
3216 } \
76a66253 3217 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3218 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3219 return; \
9a64fbe4 3220 } \
e2be8d8d 3221 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3222 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3223 op_ldst(st##width); \
f78fb44e 3224 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3225}
3226
477023a6
JM		 3227#define GEN_STUXF(width, opc, type) \
3228GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3229{ \
76a66253 3230 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3231 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3232 return; \
3233 } \
76a66253 3234 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3235 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3236 return; \
9a64fbe4 3237 } \
e2be8d8d 3238 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3239 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3240 op_ldst(st##width); \
f78fb44e 3241 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3242}
3243
477023a6
JM		 3244#define GEN_STXF(width, opc2, opc3, type) \
3245GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3246{ \
76a66253 3247 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3248 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3249 return; \
3250 } \
e2be8d8d 3251 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3252 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3253 op_ldst(st##width); \
79aceca5
FB		 3254}
3255
477023a6 3256#define GEN_STFS(width, op, type) \
9a64fbe4 3257OP_ST_TABLE(width); \
477023a6
JM		 3258GEN_STF(width, op | 0x20, type); \
3259GEN_STUF(width, op | 0x21, type); \
3260GEN_STUXF(width, op | 0x01, type); \
3261GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3262
3263/* stfd stfdu stfdux stfdx */
477023a6 3264GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 3265/* stfs stfsu stfsux stfsx */
477023a6 3266GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3267
3268/* Optional: */
3269/* stfiwx */
5b8105fa
JM		 3270OP_ST_TABLE(fiw);
3271GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3272
3273/*** Branch ***/
b068d6a7
JM		 3274static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3275 target_ulong dest)
c1942362
FB		 3276{
3277 TranslationBlock *tb;
3278 tb = ctx->tb;
a2ffb812
AJ		 3279#if defined(TARGET_PPC64)
3280 if (!ctx->sf_mode)
3281 dest = (uint32_t) dest;
3282#endif
57fec1fe 3283 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3284 likely(!ctx->singlestep_enabled)) {
57fec1fe 3285 tcg_gen_goto_tb(n);
a2ffb812 3286 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3287 tcg_gen_exit_tb((long)tb + n);
c1942362 3288 } else {
a2ffb812 3289 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3290 if (unlikely(ctx->singlestep_enabled)) {
3291 if ((ctx->singlestep_enabled &
3292 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3293 ctx->exception == POWERPC_EXCP_BRANCH) {
3294 target_ulong tmp = ctx->nip;
3295 ctx->nip = dest;
3296 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3297 ctx->nip = tmp;
3298 }
3299 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3300 gen_update_nip(ctx, dest);
3301 gen_op_debug();
3302 }
3303 }
57fec1fe 3304 tcg_gen_exit_tb(0);
c1942362 3305 }
c53be334
FB		 3306}
3307
b068d6a7 3308static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3309{
3310#if defined(TARGET_PPC64)
a2ffb812
AJ		 3311 if (ctx->sf_mode == 0)
3312 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3313 else
3314#endif
a2ffb812 3315 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3316}
3317
79aceca5
FB		 3318/* b ba bl bla */
3319GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3320{
76a66253 3321 target_ulong li, target;
38a64f9d 3322
8cbcb4fa 3323 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3324 /* sign extend LI */
76a66253 3325#if defined(TARGET_PPC64)
d9bce9d9
JM		 3326 if (ctx->sf_mode)
3327 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3328 else
76a66253 3329#endif
d9bce9d9 3330 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3331 if (likely(AA(ctx->opcode) == 0))
046d6672 3332 target = ctx->nip + li - 4;
79aceca5 3333 else
9a64fbe4 3334 target = li;
e1833e1f
JM		 3335 if (LK(ctx->opcode))
3336 gen_setlr(ctx, ctx->nip);
c1942362 3337 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3338}
3339
e98a6e40
FB		 3340#define BCOND_IM 0
3341#define BCOND_LR 1
3342#define BCOND_CTR 2
3343
b068d6a7 3344static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3345{
d9bce9d9 3346 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3347 int l1 = gen_new_label();
3348 TCGv target;
e98a6e40 3349
8cbcb4fa 3350 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812
AJ		 3351 if (type == BCOND_LR || type == BCOND_CTR) {
3352 target = tcg_temp_local_new(TCG_TYPE_TL);
3353 if (type == BCOND_CTR)
3354 tcg_gen_mov_tl(target, cpu_ctr);
3355 else
3356 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3357 }
e1833e1f
JM		 3358 if (LK(ctx->opcode))
3359 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3360 l1 = gen_new_label();
3361 if ((bo & 0x4) == 0) {
3362 /* Decrement and test CTR */
3363 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3364 if (unlikely(type == BCOND_CTR)) {
3365 GEN_EXCP_INVAL(ctx);
3366 return;
3367 }
3368 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3369#if defined(TARGET_PPC64)
a2ffb812
AJ		 3370 if (!ctx->sf_mode)
3371 tcg_gen_ext32u_tl(temp, cpu_ctr);
3372 else
d9bce9d9 3373#endif
a2ffb812
AJ		 3374 tcg_gen_mov_tl(temp, cpu_ctr);
3375 if (bo & 0x2) {
3376 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3377 } else {
3378 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3379 }
a2ffb812
AJ		 3380 }
3381 if ((bo & 0x10) == 0) {
3382 /* Test CR */
3383 uint32_t bi = BI(ctx->opcode);
3384 uint32_t mask = 1 << (3 - (bi & 0x03));
3385 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3386
d9bce9d9 3387 if (bo & 0x8) {
a2ffb812
AJ		 3388 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3389 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3390 } else {
a2ffb812
AJ		 3391 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3392 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9
JM		 3393 }
3394 }
e98a6e40 3395 if (type == BCOND_IM) {
a2ffb812
AJ		 3396
3397 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3398 if (likely(AA(ctx->opcode) == 0)) {
3399 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3400 } else {
3401 gen_goto_tb(ctx, 0, li);
3402 }
c53be334 3403 gen_set_label(l1);
c1942362 3404 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3405 } else {
d9bce9d9 3406#if defined(TARGET_PPC64)
a2ffb812
AJ		 3407 if (!(ctx->sf_mode))
3408 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3409 else
3410#endif
3411 tcg_gen_andi_tl(cpu_nip, target, ~3);
3412 tcg_gen_exit_tb(0);
3413 gen_set_label(l1);
3414#if defined(TARGET_PPC64)
3415 if (!(ctx->sf_mode))
3416 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3417 else
3418#endif
a2ffb812 3419 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3420 tcg_gen_exit_tb(0);
08e46e54 3421 }
e98a6e40
FB		 3422}
3423
3424GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3425{
e98a6e40
FB		 3426 gen_bcond(ctx, BCOND_IM);
3427}
3428
3429GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3430{
e98a6e40
FB		 3431 gen_bcond(ctx, BCOND_CTR);
3432}
3433
3434GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3435{
e98a6e40
FB		 3436 gen_bcond(ctx, BCOND_LR);
3437}
79aceca5
FB		 3438
3439/*** Condition register logical ***/
e1571908
AJ		 3440#define GEN_CRLOGIC(name, tcg_op, opc) \
3441GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3442{ \
fc0d441e
JM		 3443 uint8_t bitmask; \
3444 int sh; \
e1571908 3445 TCGv temp1, temp2; \
fc0d441e 3446 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
e1571908 3447 temp1 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e 3448 if (sh > 0) \
e1571908 3449 tcg_gen_shri_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3450 else if (sh < 0) \
e1571908
AJ		 3451 tcg_gen_shli_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3452 else \
2e31f5d3 3453 tcg_gen_mov_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2]); \
e1571908 3454 temp2 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e
JM		 3455 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3456 if (sh > 0) \
e1571908 3457 tcg_gen_shri_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3458 else if (sh < 0) \
e1571908
AJ		 3459 tcg_gen_shli_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3460 else \
3461 tcg_gen_mov_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2]); \
3462 tcg_op(temp1, temp1, temp2); \
fc0d441e 3463 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
e1571908
AJ		 3464 tcg_gen_andi_i32(temp1, temp1, bitmask); \
3465 tcg_gen_andi_i32(temp2, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3466 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], temp1, temp2); \
3467 tcg_temp_free(temp1); \
3468 tcg_temp_free(temp2); \
79aceca5
FB		 3469}
3470
3471/* crand */
e1571908 3472GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3473/* crandc */
e1571908 3474GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3475/* creqv */
e1571908 3476GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3477/* crnand */
e1571908 3478GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3479/* crnor */
e1571908 3480GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3481/* cror */
e1571908 3482GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3483/* crorc */
e1571908 3484GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3485/* crxor */
e1571908 3486GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3487/* mcrf */
3488GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3489{
47e4661c 3490 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3491}
3492
3493/*** System linkage ***/
3494/* rfi (supervisor only) */
76a66253 3495GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3496{
9a64fbe4 3497#if defined(CONFIG_USER_ONLY)
e1833e1f 3498 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3499#else
3500 /* Restore CPU state */
76a66253 3501 if (unlikely(!ctx->supervisor)) {
e1833e1f 3502 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3503 return;
9a64fbe4 3504 }
a42bd6cc 3505 gen_op_rfi();
e1833e1f 3506 GEN_SYNC(ctx);
9a64fbe4 3507#endif
79aceca5
FB		 3508}
3509
426613db 3510#if defined(TARGET_PPC64)
a750fc0b 3511GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3512{
3513#if defined(CONFIG_USER_ONLY)
e1833e1f 3514 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3515#else
3516 /* Restore CPU state */
3517 if (unlikely(!ctx->supervisor)) {
e1833e1f 3518 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3519 return;
3520 }
a42bd6cc 3521 gen_op_rfid();
e1833e1f 3522 GEN_SYNC(ctx);
426613db
JM		 3523#endif
3524}
426613db 3525
5b8105fa 3526GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3527{
3528#if defined(CONFIG_USER_ONLY)
3529 GEN_EXCP_PRIVOPC(ctx);
3530#else
3531 /* Restore CPU state */
3532 if (unlikely(ctx->supervisor <= 1)) {
3533 GEN_EXCP_PRIVOPC(ctx);
3534 return;
3535 }
3536 gen_op_hrfid();
3537 GEN_SYNC(ctx);
3538#endif
3539}
3540#endif
3541
79aceca5 3542/* sc */
417bf010
JM		 3543#if defined(CONFIG_USER_ONLY)
3544#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3545#else
3546#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3547#endif
e1833e1f 3548GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3549{
e1833e1f
JM		 3550 uint32_t lev;
3551
3552 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3553 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3554}
3555
3556/*** Trap ***/
3557/* tw */
76a66253 3558GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3559{
f78fb44e
AJ		 3560 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3561 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
a0ae05aa 3562 /* Update the nip since this might generate a trap exception */
d9bce9d9 3563 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3564 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3565}
3566
3567/* twi */
3568GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3569{
f78fb44e 3570 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3571 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3572 /* Update the nip since this might generate a trap exception */
3573 gen_update_nip(ctx, ctx->nip);
76a66253 3574 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3575}
3576
d9bce9d9
JM		 3577#if defined(TARGET_PPC64)
3578/* td */
3579GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3580{
f78fb44e
AJ		 3581 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3582 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3583 /* Update the nip since this might generate a trap exception */
3584 gen_update_nip(ctx, ctx->nip);
3585 gen_op_td(TO(ctx->opcode));
3586}
3587
3588/* tdi */
3589GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3590{
f78fb44e 3591 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3592 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3593 /* Update the nip since this might generate a trap exception */
3594 gen_update_nip(ctx, ctx->nip);
3595 gen_op_td(TO(ctx->opcode));
3596}
3597#endif
3598
79aceca5 3599/*** Processor control ***/
79aceca5
FB		 3600/* mcrxr */
3601GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3602{
3d7b417e
AJ		 3603 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3604 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3605 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3606}
3607
3608/* mfcr */
76a66253 3609GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3610{
76a66253 3611 uint32_t crm, crn;
3b46e624 3612
76a66253
JM		 3613 if (likely(ctx->opcode & 0x00100000)) {
3614 crm = CRM(ctx->opcode);
3615 if (likely((crm ^ (crm - 1)) == 0)) {
3616 crn = ffs(crm);
e1571908 3617 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3618 }
d9bce9d9 3619 } else {
e1571908 3620 tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3621 }
79aceca5
FB		 3622}
3623
3624/* mfmsr */
3625GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3626{
9a64fbe4 3627#if defined(CONFIG_USER_ONLY)
e1833e1f 3628 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3629#else
76a66253 3630 if (unlikely(!ctx->supervisor)) {
e1833e1f 3631 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3632 return;
9a64fbe4 3633 }
6676f424 3634 gen_op_load_msr();
f78fb44e 3635 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3636#endif
79aceca5
FB		 3637}
3638
a11b8151 3639#if 1
6f2d8978 3640#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3641#else
3642static void spr_noaccess (void *opaque, int sprn)
3643{
3644 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3645 printf("ERROR: try to access SPR %d !\n", sprn);
3646}
3647#define SPR_NOACCESS (&spr_noaccess)
3648#endif
3649
79aceca5 3650/* mfspr */
b068d6a7 3651static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3652{
3fc6c082 3653 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3654 uint32_t sprn = SPR(ctx->opcode);
3655
3fc6c082 3656#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3657 if (ctx->supervisor == 2)
3658 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3659 else if (ctx->supervisor)
3fc6c082
FB		 3660 read_cb = ctx->spr_cb[sprn].oea_read;
3661 else
9a64fbe4 3662#endif
3fc6c082 3663 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3664 if (likely(read_cb != NULL)) {
3665 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3666 (*read_cb)(ctx, sprn);
f78fb44e 3667 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3668 } else {
3669 /* Privilege exception */
9fceefa7
JM		 3670 /* This is a hack to avoid warnings when running Linux:
3671 * this OS breaks the PowerPC virtualisation model,
3672 * allowing userland application to read the PVR
3673 */
3674 if (sprn != SPR_PVR) {
3675 if (loglevel != 0) {
6b542af7 3676 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3677 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3678 }
077fc206
JM		 3679 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3680 sprn, sprn, ctx->nip);
f24e5695 3681 }
e1833e1f 3682 GEN_EXCP_PRIVREG(ctx);
79aceca5 3683 }
3fc6c082
FB		 3684 } else {
3685 /* Not defined */
4a057712 3686 if (loglevel != 0) {
077fc206
JM		 3687 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3688 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3689 }
077fc206
JM		 3690 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3691 sprn, sprn, ctx->nip);
e1833e1f
JM		 3692 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3693 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3694 }
79aceca5
FB		 3695}
3696
3fc6c082 3697GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3698{
3fc6c082 3699 gen_op_mfspr(ctx);
76a66253 3700}
3fc6c082
FB		 3701
3702/* mftb */
a750fc0b 3703GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3704{
3705 gen_op_mfspr(ctx);
79aceca5
FB		 3706}
3707
3708/* mtcrf */
8dd4983c 3709GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3710{
76a66253 3711 uint32_t crm, crn;
3b46e624 3712
76a66253
JM		 3713 crm = CRM(ctx->opcode);
3714 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3715 crn = ffs(crm);
e1571908
AJ		 3716 tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3717 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
76a66253 3718 } else {
e1571908
AJ		 3719 TCGv temp = tcg_const_tl(crm);
3720 tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], temp);
3721 tcg_temp_free(temp);
76a66253 3722 }
79aceca5
FB		 3723}
3724
3725/* mtmsr */
426613db 3726#if defined(TARGET_PPC64)
be147d08 3727GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3728{
3729#if defined(CONFIG_USER_ONLY)
e1833e1f 3730 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3731#else
3732 if (unlikely(!ctx->supervisor)) {
e1833e1f 3733 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3734 return;
3735 }
f78fb44e 3736 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3737 if (ctx->opcode & 0x00010000) {
3738 /* Special form that does not need any synchronisation */
3739 gen_op_update_riee();
3740 } else {
056b05f8
JM		 3741 /* XXX: we need to update nip before the store
3742 * if we enter power saving mode, we will exit the loop
3743 * directly from ppc_store_msr
3744 */
be147d08 3745 gen_update_nip(ctx, ctx->nip);
6676f424 3746 gen_op_store_msr();
be147d08
JM		 3747 /* Must stop the translation as machine state (may have) changed */
3748 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3749 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3750 }
426613db
JM		 3751#endif
3752}
3753#endif
3754
79aceca5
FB		 3755GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3756{
9a64fbe4 3757#if defined(CONFIG_USER_ONLY)
e1833e1f 3758 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3759#else
76a66253 3760 if (unlikely(!ctx->supervisor)) {
e1833e1f 3761 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3762 return;
9a64fbe4 3763 }
f78fb44e 3764 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3765 if (ctx->opcode & 0x00010000) {
3766 /* Special form that does not need any synchronisation */
3767 gen_op_update_riee();
3768 } else {
056b05f8
JM		 3769 /* XXX: we need to update nip before the store
3770 * if we enter power saving mode, we will exit the loop
3771 * directly from ppc_store_msr
3772 */
be147d08 3773 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3774#if defined(TARGET_PPC64)
be147d08 3775 if (!ctx->sf_mode)
6676f424 3776 gen_op_store_msr_32();
be147d08 3777 else
d9bce9d9 3778#endif
6676f424 3779 gen_op_store_msr();
be147d08
JM		 3780 /* Must stop the translation as machine state (may have) changed */
3781 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3782 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3783 }
9a64fbe4 3784#endif
79aceca5
FB		 3785}
3786
3787/* mtspr */
3788GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3789{
3fc6c082 3790 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3791 uint32_t sprn = SPR(ctx->opcode);
3792
3fc6c082 3793#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3794 if (ctx->supervisor == 2)
3795 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3796 else if (ctx->supervisor)
3fc6c082
FB		 3797 write_cb = ctx->spr_cb[sprn].oea_write;
3798 else
9a64fbe4 3799#endif
3fc6c082 3800 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3801 if (likely(write_cb != NULL)) {
3802 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 3803 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 3804 (*write_cb)(ctx, sprn);
3805 } else {
3806 /* Privilege exception */
4a057712 3807 if (loglevel != 0) {
077fc206
JM		 3808 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3809 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3810 }
077fc206
JM		 3811 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3812 sprn, sprn, ctx->nip);
e1833e1f 3813 GEN_EXCP_PRIVREG(ctx);
76a66253 3814 }
3fc6c082
FB		 3815 } else {
3816 /* Not defined */
4a057712 3817 if (loglevel != 0) {
077fc206
JM		 3818 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3819 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3820 }
077fc206
JM		 3821 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3822 sprn, sprn, ctx->nip);
e1833e1f
JM		 3823 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3824 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3825 }
79aceca5
FB		 3826}
3827
3828/*** Cache management ***/
79aceca5 3829/* dcbf */
0db1b20e 3830GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3831{
dac454af 3832 /* XXX: specification says this is treated as a load by the MMU */
b61f2753
AJ		 3833 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3834 gen_addr_reg_index(temp, ctx);
3835 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3836 tcg_temp_free(temp);
79aceca5
FB		 3837}
3838
3839/* dcbi (Supervisor only) */
9a64fbe4 3840GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3841{
a541f297 3842#if defined(CONFIG_USER_ONLY)
e1833e1f 3843 GEN_EXCP_PRIVOPC(ctx);
a541f297 3844#else
b61f2753 3845 TCGv EA, val;
76a66253 3846 if (unlikely(!ctx->supervisor)) {
e1833e1f 3847 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3848 return;
9a64fbe4 3849 }
b61f2753
AJ		 3850 EA = tcg_temp_new(TCG_TYPE_TL);
3851 gen_addr_reg_index(EA, ctx);
ed69522c 3852 val = tcg_temp_new(TCG_TYPE_TL);
76a66253 3853 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 3854 gen_qemu_ld8u(val, EA, ctx->mem_idx);
3855 gen_qemu_st8(val, EA, ctx->mem_idx);
3856 tcg_temp_free(val);
3857 tcg_temp_free(EA);
a541f297 3858#endif
79aceca5
FB		 3859}
3860
3861/* dcdst */
9a64fbe4 3862GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3863{
76a66253 3864 /* XXX: specification say this is treated as a load by the MMU */
b61f2753
AJ		 3865 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3866 gen_addr_reg_index(temp, ctx);
3867 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3868 tcg_temp_free(temp);
79aceca5
FB		 3869}
3870
3871/* dcbt */
0db1b20e 3872GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3873{
0db1b20e 3874 /* interpreted as no-op */
76a66253
JM		 3875 /* XXX: specification say this is treated as a load by the MMU
3876 * but does not generate any exception
3877 */
79aceca5
FB		 3878}
3879
3880/* dcbtst */
0db1b20e 3881GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3882{
0db1b20e 3883 /* interpreted as no-op */
76a66253
JM		 3884 /* XXX: specification say this is treated as a load by the MMU
3885 * but does not generate any exception
3886 */
79aceca5
FB		 3887}
3888
3889/* dcbz */
d63001d1 3890#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 3891static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3892 /* 32 bytes cache line size */
d63001d1 3893 {
7863667f
JM		 3894#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3895#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3896#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3897#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3898#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3899#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3900#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3901#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3902 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 3903 },
7863667f 3904 /* 64 bytes cache line size */
d63001d1 3905 {
7863667f
JM		 3906#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3907#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3908#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3909#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3910#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3911#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3912#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3913#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3914 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 3915 },
7863667f 3916 /* 128 bytes cache line size */
d63001d1 3917 {
7863667f
JM		 3918#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3919#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3920#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3921#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3922#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3923#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3924#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3925#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3926 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 3927 },
7863667f 3928 /* tunable cache line size */
d63001d1 3929 {
7863667f
JM		 3930#define gen_op_dcbz_le_raw gen_op_dcbz_raw
3931#define gen_op_dcbz_le_user gen_op_dcbz_user
3932#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3933#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3934#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3935#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3936#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3937#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3938 GEN_MEM_FUNCS(dcbz),
d63001d1 3939 },
76a66253 3940};
9a64fbe4 3941
b068d6a7
JM		 3942static always_inline void handler_dcbz (DisasContext *ctx,
3943 int dcache_line_size)
d63001d1
JM		 3944{
3945 int n;
3946
3947 switch (dcache_line_size) {
3948 case 32:
3949 n = 0;
3950 break;
3951 case 64:
3952 n = 1;
3953 break;
3954 case 128:
3955 n = 2;
3956 break;
3957 default:
3958 n = 3;
3959 break;
3960 }
3961 op_dcbz(n);
3962}
3963
3964GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 3965{
e2be8d8d 3966 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 3967 handler_dcbz(ctx, ctx->dcache_line_size);
3968 gen_op_check_reservation();
3969}
3970
c7697e1f 3971GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 3972{
e2be8d8d 3973 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 3974 if (ctx->opcode & 0x00200000)
3975 handler_dcbz(ctx, ctx->dcache_line_size);
3976 else
3977 handler_dcbz(ctx, -1);
4b3686fa 3978 gen_op_check_reservation();
79aceca5
FB		 3979}
3980
3981/* icbi */
36f69651 3982#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 3983#define gen_op_icbi_le_raw gen_op_icbi_raw
3984#define gen_op_icbi_le_user gen_op_icbi_user
3985#define gen_op_icbi_le_kernel gen_op_icbi_kernel
3986#define gen_op_icbi_le_hypv gen_op_icbi_hypv
3987#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3988#define gen_op_icbi_le_64_user gen_op_icbi_64_user
3989#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3990#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3991static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3992 GEN_MEM_FUNCS(icbi),
36f69651 3993};
e1833e1f 3994
1b413d55 3995GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 3996{
30032c94
JM		 3997 /* NIP cannot be restored if the memory exception comes from an helper */
3998 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3999 gen_addr_reg_index(cpu_T[0], ctx);
36f69651 4000 op_icbi();
79aceca5
FB		 4001}
4002
4003/* Optional: */
4004/* dcba */
a750fc0b 4005GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4006{
0db1b20e
JM		 4007 /* interpreted as no-op */
4008 /* XXX: specification say this is treated as a store by the MMU
4009 * but does not generate any exception
4010 */
79aceca5
FB		 4011}
4012
4013/*** Segment register manipulation ***/
4014/* Supervisor only: */
4015/* mfsr */
4016GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4017{
9a64fbe4 4018#if defined(CONFIG_USER_ONLY)
e1833e1f 4019 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4020#else
76a66253 4021 if (unlikely(!ctx->supervisor)) {
e1833e1f 4022 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4023 return;
9a64fbe4 4024 }
86c581dc 4025 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4026 gen_op_load_sr();
f78fb44e 4027 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4028#endif
79aceca5
FB		 4029}
4030
4031/* mfsrin */
9a64fbe4 4032GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4033{
9a64fbe4 4034#if defined(CONFIG_USER_ONLY)
e1833e1f 4035 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4036#else
76a66253 4037 if (unlikely(!ctx->supervisor)) {
e1833e1f 4038 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4039 return;
9a64fbe4 4040 }
f78fb44e 4041 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4042 gen_op_srli_T1(28);
4043 gen_op_load_sr();
f78fb44e 4044 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4045#endif
79aceca5
FB		 4046}
4047
4048/* mtsr */
e63c59cb 4049GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4050{
9a64fbe4 4051#if defined(CONFIG_USER_ONLY)
e1833e1f 4052 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4053#else
76a66253 4054 if (unlikely(!ctx->supervisor)) {
e1833e1f 4055 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4056 return;
9a64fbe4 4057 }
f78fb44e 4058 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4059 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4060 gen_op_store_sr();
9a64fbe4 4061#endif
79aceca5
FB		 4062}
4063
4064/* mtsrin */
9a64fbe4 4065GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4066{
9a64fbe4 4067#if defined(CONFIG_USER_ONLY)
e1833e1f 4068 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4069#else
76a66253 4070 if (unlikely(!ctx->supervisor)) {
e1833e1f 4071 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4072 return;
9a64fbe4 4073 }
f78fb44e
AJ		 4074 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4075 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4076 gen_op_srli_T1(28);
4077 gen_op_store_sr();
9a64fbe4 4078#endif
79aceca5
FB		 4079}
4080
12de9a39
JM		 4081#if defined(TARGET_PPC64)
4082/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4083/* mfsr */
c7697e1f 4084GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4085{
4086#if defined(CONFIG_USER_ONLY)
4087 GEN_EXCP_PRIVREG(ctx);
4088#else
4089 if (unlikely(!ctx->supervisor)) {
4090 GEN_EXCP_PRIVREG(ctx);
4091 return;
4092 }
86c581dc 4093 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4094 gen_op_load_slb();
f78fb44e 4095 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4096#endif
4097}
4098
4099/* mfsrin */
c7697e1f
JM		 4100GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4101 PPC_SEGMENT_64B)
12de9a39
JM		 4102{
4103#if defined(CONFIG_USER_ONLY)
4104 GEN_EXCP_PRIVREG(ctx);
4105#else
4106 if (unlikely(!ctx->supervisor)) {
4107 GEN_EXCP_PRIVREG(ctx);
4108 return;
4109 }
f78fb44e 4110 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4111 gen_op_srli_T1(28);
4112 gen_op_load_slb();
f78fb44e 4113 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4114#endif
4115}
4116
4117/* mtsr */
c7697e1f 4118GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4119{
4120#if defined(CONFIG_USER_ONLY)
4121 GEN_EXCP_PRIVREG(ctx);
4122#else
4123 if (unlikely(!ctx->supervisor)) {
4124 GEN_EXCP_PRIVREG(ctx);
4125 return;
4126 }
f78fb44e 4127 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4128 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4129 gen_op_store_slb();
4130#endif
4131}
4132
4133/* mtsrin */
c7697e1f
JM		 4134GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4135 PPC_SEGMENT_64B)
12de9a39
JM		 4136{
4137#if defined(CONFIG_USER_ONLY)
4138 GEN_EXCP_PRIVREG(ctx);
4139#else
4140 if (unlikely(!ctx->supervisor)) {
4141 GEN_EXCP_PRIVREG(ctx);
4142 return;
4143 }
f78fb44e
AJ		 4144 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4145 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4146 gen_op_srli_T1(28);
4147 gen_op_store_slb();
4148#endif
4149}
4150#endif /* defined(TARGET_PPC64) */
4151
79aceca5
FB		 4152/*** Lookaside buffer management ***/
4153/* Optional & supervisor only: */
4154/* tlbia */
3fc6c082 4155GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4156{
9a64fbe4 4157#if defined(CONFIG_USER_ONLY)
e1833e1f 4158 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4159#else
76a66253 4160 if (unlikely(!ctx->supervisor)) {
e1833e1f 4161 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4162 return;
9a64fbe4
FB		 4163 }
4164 gen_op_tlbia();
4165#endif
79aceca5
FB		 4166}
4167
4168/* tlbie */
76a66253 4169GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4170{
9a64fbe4 4171#if defined(CONFIG_USER_ONLY)
e1833e1f 4172 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4173#else
76a66253 4174 if (unlikely(!ctx->supervisor)) {
e1833e1f 4175 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4176 return;
9a64fbe4 4177 }
f78fb44e 4178 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4179#if defined(TARGET_PPC64)
4180 if (ctx->sf_mode)
4181 gen_op_tlbie_64();
4182 else
4183#endif
4184 gen_op_tlbie();
9a64fbe4 4185#endif
79aceca5
FB		 4186}
4187
4188/* tlbsync */
76a66253 4189GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4190{
9a64fbe4 4191#if defined(CONFIG_USER_ONLY)
e1833e1f 4192 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4193#else
76a66253 4194 if (unlikely(!ctx->supervisor)) {
e1833e1f 4195 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4196 return;
9a64fbe4
FB		 4197 }
4198 /* This has no effect: it should ensure that all previous
4199 * tlbie have completed
4200 */
e1833e1f 4201 GEN_STOP(ctx);
9a64fbe4 4202#endif
79aceca5
FB		 4203}
4204
426613db
JM		 4205#if defined(TARGET_PPC64)
4206/* slbia */
4207GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4208{
4209#if defined(CONFIG_USER_ONLY)
e1833e1f 4210 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4211#else
4212 if (unlikely(!ctx->supervisor)) {
e1833e1f 4213 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4214 return;
4215 }
4216 gen_op_slbia();
426613db
JM		 4217#endif
4218}
4219
4220/* slbie */
4221GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4222{
4223#if defined(CONFIG_USER_ONLY)
e1833e1f 4224 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4225#else
4226 if (unlikely(!ctx->supervisor)) {
e1833e1f 4227 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4228 return;
4229 }
f78fb44e 4230 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4231 gen_op_slbie();
426613db
JM		 4232#endif
4233}
4234#endif
4235
79aceca5
FB		 4236/*** External control ***/
4237/* Optional: */
9a64fbe4
FB		 4238#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4239#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4240static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4241 GEN_MEM_FUNCS(eciwx),
111bfab3 4242};
7863667f
JM		 4243static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4244 GEN_MEM_FUNCS(ecowx),
111bfab3 4245};
9a64fbe4 4246
111bfab3 4247/* eciwx */
79aceca5
FB		 4248GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4249{
9a64fbe4 4250 /* Should check EAR[E] & alignment ! */
e2be8d8d 4251 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4252 op_eciwx();
f78fb44e 4253 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4254}
4255
4256/* ecowx */
4257GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4258{
4259 /* Should check EAR[E] & alignment ! */
e2be8d8d 4260 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4261 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4262 op_ecowx();
4263}
4264
4265/* PowerPC 601 specific instructions */
4266/* abs - abs. */
4267GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4268{
f78fb44e 4269 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4270 gen_op_POWER_abs();
f78fb44e 4271 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4272 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4273 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4274}
4275
4276/* abso - abso. */
4277GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4278{
f78fb44e 4279 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4280 gen_op_POWER_abso();
f78fb44e 4281 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4282 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4283 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4284}
4285
4286/* clcs */
a750fc0b 4287GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4288{
f78fb44e 4289 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4290 gen_op_POWER_clcs();
c7697e1f 4291 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4292 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4293}
4294
4295/* div - div. */
4296GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4297{
f78fb44e
AJ		 4298 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4299 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4300 gen_op_POWER_div();
f78fb44e 4301 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4302 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4303 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4304}
4305
4306/* divo - divo. */
4307GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4308{
f78fb44e
AJ		 4309 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4310 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4311 gen_op_POWER_divo();
f78fb44e 4312 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4313 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4314 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4315}
4316
4317/* divs - divs. */
4318GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4319{
f78fb44e
AJ		 4320 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4321 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4322 gen_op_POWER_divs();
f78fb44e 4323 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4324 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4325 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4326}
4327
4328/* divso - divso. */
4329GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4330{
f78fb44e
AJ		 4331 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4332 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4333 gen_op_POWER_divso();
f78fb44e 4334 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4335 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4336 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4337}
4338
4339/* doz - doz. */
4340GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4341{
f78fb44e
AJ		 4342 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4343 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4344 gen_op_POWER_doz();
f78fb44e 4345 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4346 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4347 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4348}
4349
4350/* dozo - dozo. */
4351GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4352{
f78fb44e
AJ		 4353 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4354 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4355 gen_op_POWER_dozo();
f78fb44e 4356 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4357 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4358 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4359}
4360
4361/* dozi */
4362GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4363{
f78fb44e 4364 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4365 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4366 gen_op_POWER_doz();
f78fb44e 4367 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4368}
4369
7863667f
JM		 4370/* As lscbx load from memory byte after byte, it's always endian safe.
4371 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4372 */
2857068e 4373#define op_POWER_lscbx(start, ra, rb) \
76a66253 4374(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 4375#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4376#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4377#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4378#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4379#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4380#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4381#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4382#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4383#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4384#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4385#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4386#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4387static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4388 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4389};
76a66253
JM		 4390
4391/* lscbx - lscbx. */
4392GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4393{
4394 int ra = rA(ctx->opcode);
4395 int rb = rB(ctx->opcode);
4396
e2be8d8d 4397 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4398 if (ra == 0) {
4399 ra = rb;
4400 }
4401 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4402 gen_update_nip(ctx, ctx->nip - 4);
3d7b417e
AJ		 4403 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4404 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4405 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
76a66253 4406 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3d7b417e
AJ		 4407 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4408 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253 4409 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4410 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4411}
4412
4413/* maskg - maskg. */
4414GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4415{
f78fb44e
AJ		 4416 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4417 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4418 gen_op_POWER_maskg();
f78fb44e 4419 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4420 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4421 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4422}
4423
4424/* maskir - maskir. */
4425GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4426{
f78fb44e
AJ		 4427 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4428 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4429 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4430 gen_op_POWER_maskir();
f78fb44e 4431 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4432 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4433 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4434}
4435
4436/* mul - mul. */
4437GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4438{
f78fb44e
AJ		 4439 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4440 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4441 gen_op_POWER_mul();
f78fb44e 4442 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4443 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4444 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4445}
4446
4447/* mulo - mulo. */
4448GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4449{
f78fb44e
AJ		 4450 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4451 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4452 gen_op_POWER_mulo();
f78fb44e 4453 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4454 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4455 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4456}
4457
4458/* nabs - nabs. */
4459GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4460{
f78fb44e 4461 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4462 gen_op_POWER_nabs();
f78fb44e 4463 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4464 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4465 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4466}
4467
4468/* nabso - nabso. */
4469GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4470{
f78fb44e 4471 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4472 gen_op_POWER_nabso();
f78fb44e 4473 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4474 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4475 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4476}
4477
4478/* rlmi - rlmi. */
4479GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4480{
4481 uint32_t mb, me;
4482
4483 mb = MB(ctx->opcode);
4484 me = ME(ctx->opcode);
f78fb44e
AJ		 4485 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4486 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4487 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4488 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4489 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4490 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4491 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4492}
4493
4494/* rrib - rrib. */
4495GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4496{
f78fb44e
AJ		 4497 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4498 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4499 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4500 gen_op_POWER_rrib();
f78fb44e 4501 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4502 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4503 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4504}
4505
4506/* sle - sle. */
4507GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4508{
f78fb44e
AJ		 4509 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4510 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4511 gen_op_POWER_sle();
f78fb44e 4512 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4513 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4514 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4515}
4516
4517/* sleq - sleq. */
4518GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4519{
f78fb44e
AJ		 4520 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4521 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4522 gen_op_POWER_sleq();
f78fb44e 4523 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4524 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4525 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4526}
4527
4528/* sliq - sliq. */
4529GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4530{
f78fb44e 4531 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4532 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4533 gen_op_POWER_sle();
f78fb44e 4534 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4535 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4536 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4537}
4538
4539/* slliq - slliq. */
4540GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4541{
f78fb44e 4542 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4543 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4544 gen_op_POWER_sleq();
f78fb44e 4545 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4546 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4547 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4548}
4549
4550/* sllq - sllq. */
4551GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4552{
f78fb44e
AJ		 4553 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4554 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4555 gen_op_POWER_sllq();
f78fb44e 4556 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4557 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4558 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4559}
4560
4561/* slq - slq. */
4562GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4563{
f78fb44e
AJ		 4564 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4565 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4566 gen_op_POWER_slq();
f78fb44e 4567 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4568 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4569 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4570}
4571
d9bce9d9 4572/* sraiq - sraiq. */
76a66253
JM		 4573GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4574{
f78fb44e 4575 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4576 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4577 gen_op_POWER_sraq();
f78fb44e 4578 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4579 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4580 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4581}
4582
4583/* sraq - sraq. */
4584GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4585{
f78fb44e
AJ		 4586 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4587 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4588 gen_op_POWER_sraq();
f78fb44e 4589 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4590 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4591 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4592}
4593
4594/* sre - sre. */
4595GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4596{
f78fb44e
AJ		 4597 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4598 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4599 gen_op_POWER_sre();
f78fb44e 4600 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4601 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4602 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4603}
4604
4605/* srea - srea. */
4606GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4607{
f78fb44e
AJ		 4608 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4609 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4610 gen_op_POWER_srea();
f78fb44e 4611 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4612 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4613 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4614}
4615
4616/* sreq */
4617GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4618{
f78fb44e
AJ		 4619 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4620 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4621 gen_op_POWER_sreq();
f78fb44e 4622 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4623 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4624 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4625}
4626
4627/* sriq */
4628GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4629{
f78fb44e 4630 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4631 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4632 gen_op_POWER_srq();
f78fb44e 4633 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4634 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4635 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4636}
4637
4638/* srliq */
4639GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4640{
f78fb44e
AJ		 4641 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4642 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4643 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4644 gen_op_POWER_srlq();
f78fb44e 4645 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4646 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4647 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4648}
4649
4650/* srlq */
4651GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4652{
f78fb44e
AJ		 4653 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4654 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4655 gen_op_POWER_srlq();
f78fb44e 4656 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4657 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4658 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4659}
4660
4661/* srq */
4662GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4663{
f78fb44e
AJ		 4664 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4665 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4666 gen_op_POWER_srq();
f78fb44e 4667 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4668 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4669 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4670}
4671
4672/* PowerPC 602 specific instructions */
4673/* dsa */
4674GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4675{
4676 /* XXX: TODO */
e1833e1f 4677 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4678}
4679
4680/* esa */
4681GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4682{
4683 /* XXX: TODO */
e1833e1f 4684 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4685}
4686
4687/* mfrom */
4688GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4689{
4690#if defined(CONFIG_USER_ONLY)
e1833e1f 4691 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4692#else
4693 if (unlikely(!ctx->supervisor)) {
e1833e1f 4694 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4695 return;
4696 }
f78fb44e 4697 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4698 gen_op_602_mfrom();
f78fb44e 4699 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4700#endif
4701}
4702
4703/* 602 - 603 - G2 TLB management */
4704/* tlbld */
c7697e1f 4705GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4706{
4707#if defined(CONFIG_USER_ONLY)
e1833e1f 4708 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4709#else
4710 if (unlikely(!ctx->supervisor)) {
e1833e1f 4711 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4712 return;
4713 }
f78fb44e 4714 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4715 gen_op_6xx_tlbld();
76a66253
JM		 4716#endif
4717}
4718
4719/* tlbli */
c7697e1f 4720GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4721{
4722#if defined(CONFIG_USER_ONLY)
e1833e1f 4723 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4724#else
4725 if (unlikely(!ctx->supervisor)) {
e1833e1f 4726 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4727 return;
4728 }
f78fb44e 4729 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4730 gen_op_6xx_tlbli();
76a66253
JM		 4731#endif
4732}
4733
7dbe11ac
JM		 4734/* 74xx TLB management */
4735/* tlbld */
c7697e1f 4736GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4737{
4738#if defined(CONFIG_USER_ONLY)
4739 GEN_EXCP_PRIVOPC(ctx);
4740#else
4741 if (unlikely(!ctx->supervisor)) {
4742 GEN_EXCP_PRIVOPC(ctx);
4743 return;
4744 }
f78fb44e 4745 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4746 gen_op_74xx_tlbld();
4747#endif
4748}
4749
4750/* tlbli */
c7697e1f 4751GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4752{
4753#if defined(CONFIG_USER_ONLY)
4754 GEN_EXCP_PRIVOPC(ctx);
4755#else
4756 if (unlikely(!ctx->supervisor)) {
4757 GEN_EXCP_PRIVOPC(ctx);
4758 return;
4759 }
f78fb44e 4760 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4761 gen_op_74xx_tlbli();
4762#endif
4763}
4764
76a66253
JM		 4765/* POWER instructions not in PowerPC 601 */
4766/* clf */
4767GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4768{
4769 /* Cache line flush: implemented as no-op */
4770}
4771
4772/* cli */
4773GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4774{
7f75ffd3 4775 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4776#if defined(CONFIG_USER_ONLY)
e1833e1f 4777 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4778#else
4779 if (unlikely(!ctx->supervisor)) {
e1833e1f 4780 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4781 return;
4782 }
4783#endif
4784}
4785
4786/* dclst */
4787GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4788{
4789 /* Data cache line store: treated as no-op */
4790}
4791
4792GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4793{
4794#if defined(CONFIG_USER_ONLY)
e1833e1f 4795 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4796#else
4797 if (unlikely(!ctx->supervisor)) {
e1833e1f 4798 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4799 return;
4800 }
4801 int ra = rA(ctx->opcode);
4802 int rd = rD(ctx->opcode);
4803
e2be8d8d 4804 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4805 gen_op_POWER_mfsri();
f78fb44e 4806 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4807 if (ra != 0 && ra != rd)
f78fb44e 4808 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4809#endif
4810}
4811
4812GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4813{
4814#if defined(CONFIG_USER_ONLY)
e1833e1f 4815 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4816#else
4817 if (unlikely(!ctx->supervisor)) {
e1833e1f 4818 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4819 return;
4820 }
e2be8d8d 4821 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4822 gen_op_POWER_rac();
f78fb44e 4823 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4824#endif
4825}
4826
4827GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4828{
4829#if defined(CONFIG_USER_ONLY)
e1833e1f 4830 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4831#else
4832 if (unlikely(!ctx->supervisor)) {
e1833e1f 4833 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4834 return;
4835 }
4836 gen_op_POWER_rfsvc();
e1833e1f 4837 GEN_SYNC(ctx);
76a66253
JM		 4838#endif
4839}
4840
4841/* svc is not implemented for now */
4842
4843/* POWER2 specific instructions */
4844/* Quad manipulation (load/store two floats at a time) */
7863667f 4845/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 4846#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4847#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 4848#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4849#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4850#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4851#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4852#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4853#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4854#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4855#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4856#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4857#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4858#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4859#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4860#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4861#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4862#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4863#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4864static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4865 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 4866};
7863667f
JM		 4867static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4868 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 4869};
76a66253
JM		 4870
4871/* lfq */
4872GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4873{
4874 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4875 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4876 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4877 op_POWER2_lfq();
a5e26afa
AJ		 4878 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4879 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4880}
4881
4882/* lfqu */
4883GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4884{
4885 int ra = rA(ctx->opcode);
4886
4887 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4888 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4889 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4890 op_POWER2_lfq();
a5e26afa
AJ		 4891 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4892 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4893 if (ra != 0)
f78fb44e 4894 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4895}
4896
4897/* lfqux */
4898GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4899{
4900 int ra = rA(ctx->opcode);
4901
4902 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4903 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4904 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4905 op_POWER2_lfq();
a5e26afa
AJ		 4906 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4907 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4908 if (ra != 0)
f78fb44e 4909 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4910}
4911
4912/* lfqx */
4913GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4914{
4915 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4916 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4917 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4918 op_POWER2_lfq();
a5e26afa
AJ		 4919 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4920 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4921}
4922
4923/* stfq */
4924GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4925{
4926 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4927 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4928 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4929 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4930 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4931 op_POWER2_stfq();
4932}
4933
4934/* stfqu */
4935GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4936{
4937 int ra = rA(ctx->opcode);
4938
4939 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4940 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4941 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4942 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4943 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4944 op_POWER2_stfq();
4945 if (ra != 0)
f78fb44e 4946 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4947}
4948
4949/* stfqux */
4950GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4951{
4952 int ra = rA(ctx->opcode);
4953
4954 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4955 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4956 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 4957 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4958 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4959 op_POWER2_stfq();
4960 if (ra != 0)
f78fb44e 4961 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4962}
4963
4964/* stfqx */
4965GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4966{
4967 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4968 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4969 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 4970 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4971 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4972 op_POWER2_stfq();
4973}
4974
4975/* BookE specific instructions */
2662a059 4976/* XXX: not implemented on 440 ? */
05332d70 4977GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 4978{
4979 /* XXX: TODO */
e1833e1f 4980 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4981}
4982
2662a059 4983/* XXX: not implemented on 440 ? */
05332d70 4984GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 4985{
4986#if defined(CONFIG_USER_ONLY)
e1833e1f 4987 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4988#else
4989 if (unlikely(!ctx->supervisor)) {
e1833e1f 4990 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4991 return;
4992 }
e2be8d8d 4993 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4994 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 4995#if defined(TARGET_PPC64)
4996 if (ctx->sf_mode)
4997 gen_op_tlbie_64();
4998 else
4999#endif
5000 gen_op_tlbie();
76a66253
JM		 5001#endif
5002}
5003
5004/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5005static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5006 int opc2, int opc3,
5007 int ra, int rb, int rt, int Rc)
76a66253 5008{
f78fb44e
AJ		 5009 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
5010 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 5011 switch (opc3 & 0x0D) {
5012 case 0x05:
5013 /* macchw - macchw. - macchwo - macchwo. */
5014 /* macchws - macchws. - macchwso - macchwso. */
5015 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5016 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5017 /* mulchw - mulchw. */
5018 gen_op_405_mulchw();
5019 break;
5020 case 0x04:
5021 /* macchwu - macchwu. - macchwuo - macchwuo. */
5022 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5023 /* mulchwu - mulchwu. */
5024 gen_op_405_mulchwu();
5025 break;
5026 case 0x01:
5027 /* machhw - machhw. - machhwo - machhwo. */
5028 /* machhws - machhws. - machhwso - machhwso. */
5029 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5030 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5031 /* mulhhw - mulhhw. */
5032 gen_op_405_mulhhw();
5033 break;
5034 case 0x00:
5035 /* machhwu - machhwu. - machhwuo - machhwuo. */
5036 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5037 /* mulhhwu - mulhhwu. */
5038 gen_op_405_mulhhwu();
5039 break;
5040 case 0x0D:
5041 /* maclhw - maclhw. - maclhwo - maclhwo. */
5042 /* maclhws - maclhws. - maclhwso - maclhwso. */
5043 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5044 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5045 /* mullhw - mullhw. */
5046 gen_op_405_mullhw();
5047 break;
5048 case 0x0C:
5049 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5050 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5051 /* mullhwu - mullhwu. */
5052 gen_op_405_mullhwu();
5053 break;
5054 }
5055 if (opc2 & 0x02) {
5056 /* nmultiply-and-accumulate (0x0E) */
5057 gen_op_neg();
5058 }
5059 if (opc2 & 0x04) {
5060 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
f78fb44e 5061 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
e55fd934 5062 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
76a66253
JM		 5063 gen_op_405_add_T0_T2();
5064 }
5065 if (opc3 & 0x10) {
5066 /* Check overflow */
5067 if (opc3 & 0x01)
c3e10c7b 5068 gen_op_check_addo();
76a66253
JM		 5069 else
5070 gen_op_405_check_ovu();
5071 }
5072 if (opc3 & 0x02) {
5073 /* Saturate */
5074 if (opc3 & 0x01)
5075 gen_op_405_check_sat();
5076 else
5077 gen_op_405_check_satu();
5078 }
f78fb44e 5079 tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
76a66253
JM		 5080 if (unlikely(Rc) != 0) {
5081 /* Update Rc0 */
e1571908 5082 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 5083 }
5084}
5085
a750fc0b
JM		 5086#define GEN_MAC_HANDLER(name, opc2, opc3) \
5087GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5088{ \
5089 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5090 rD(ctx->opcode), Rc(ctx->opcode)); \
5091}
5092
5093/* macchw - macchw. */
a750fc0b 5094GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5095/* macchwo - macchwo. */
a750fc0b 5096GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5097/* macchws - macchws. */
a750fc0b 5098GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5099/* macchwso - macchwso. */
a750fc0b 5100GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5101/* macchwsu - macchwsu. */
a750fc0b 5102GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5103/* macchwsuo - macchwsuo. */
a750fc0b 5104GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5105/* macchwu - macchwu. */
a750fc0b 5106GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5107/* macchwuo - macchwuo. */
a750fc0b 5108GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5109/* machhw - machhw. */
a750fc0b 5110GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5111/* machhwo - machhwo. */
a750fc0b 5112GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5113/* machhws - machhws. */
a750fc0b 5114GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5115/* machhwso - machhwso. */
a750fc0b 5116GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5117/* machhwsu - machhwsu. */
a750fc0b 5118GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5119/* machhwsuo - machhwsuo. */
a750fc0b 5120GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5121/* machhwu - machhwu. */
a750fc0b 5122GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5123/* machhwuo - machhwuo. */
a750fc0b 5124GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5125/* maclhw - maclhw. */
a750fc0b 5126GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5127/* maclhwo - maclhwo. */
a750fc0b 5128GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5129/* maclhws - maclhws. */
a750fc0b 5130GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5131/* maclhwso - maclhwso. */
a750fc0b 5132GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5133/* maclhwu - maclhwu. */
a750fc0b 5134GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5135/* maclhwuo - maclhwuo. */
a750fc0b 5136GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5137/* maclhwsu - maclhwsu. */
a750fc0b 5138GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5139/* maclhwsuo - maclhwsuo. */
a750fc0b 5140GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5141/* nmacchw - nmacchw. */
a750fc0b 5142GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5143/* nmacchwo - nmacchwo. */
a750fc0b 5144GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5145/* nmacchws - nmacchws. */
a750fc0b 5146GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5147/* nmacchwso - nmacchwso. */
a750fc0b 5148GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5149/* nmachhw - nmachhw. */
a750fc0b 5150GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5151/* nmachhwo - nmachhwo. */
a750fc0b 5152GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5153/* nmachhws - nmachhws. */
a750fc0b 5154GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5155/* nmachhwso - nmachhwso. */
a750fc0b 5156GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5157/* nmaclhw - nmaclhw. */
a750fc0b 5158GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5159/* nmaclhwo - nmaclhwo. */
a750fc0b 5160GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5161/* nmaclhws - nmaclhws. */
a750fc0b 5162GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5163/* nmaclhwso - nmaclhwso. */
a750fc0b 5164GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5165
5166/* mulchw - mulchw. */
a750fc0b 5167GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5168/* mulchwu - mulchwu. */
a750fc0b 5169GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5170/* mulhhw - mulhhw. */
a750fc0b 5171GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5172/* mulhhwu - mulhhwu. */
a750fc0b 5173GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5174/* mullhw - mullhw. */
a750fc0b 5175GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5176/* mullhwu - mullhwu. */
a750fc0b 5177GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5178
5179/* mfdcr */
05332d70 5180GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5181{
5182#if defined(CONFIG_USER_ONLY)
e1833e1f 5183 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5184#else
5185 uint32_t dcrn = SPR(ctx->opcode);
5186
5187 if (unlikely(!ctx->supervisor)) {
e1833e1f 5188 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5189 return;
5190 }
86c581dc 5191 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5192 gen_op_load_dcr();
f78fb44e 5193 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5194#endif
5195}
5196
5197/* mtdcr */
05332d70 5198GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5199{
5200#if defined(CONFIG_USER_ONLY)
e1833e1f 5201 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5202#else
5203 uint32_t dcrn = SPR(ctx->opcode);
5204
5205 if (unlikely(!ctx->supervisor)) {
e1833e1f 5206 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5207 return;
5208 }
86c581dc 5209 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5210 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5211 gen_op_store_dcr();
5212#endif
5213}
5214
5215/* mfdcrx */
2662a059 5216/* XXX: not implemented on 440 ? */
05332d70 5217GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5218{
5219#if defined(CONFIG_USER_ONLY)
e1833e1f 5220 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5221#else
5222 if (unlikely(!ctx->supervisor)) {
e1833e1f 5223 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5224 return;
5225 }
f78fb44e 5226 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5227 gen_op_load_dcr();
f78fb44e 5228 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5229 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5230#endif
5231}
5232
5233/* mtdcrx */
2662a059 5234/* XXX: not implemented on 440 ? */
05332d70 5235GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5236{
5237#if defined(CONFIG_USER_ONLY)
e1833e1f 5238 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5239#else
5240 if (unlikely(!ctx->supervisor)) {
e1833e1f 5241 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5242 return;
5243 }
f78fb44e
AJ		 5244 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5245 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5246 gen_op_store_dcr();
a750fc0b 5247 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5248#endif
5249}
5250
a750fc0b
JM		 5251/* mfdcrux (PPC 460) : user-mode access to DCR */
5252GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5253{
f78fb44e 5254 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5255 gen_op_load_dcr();
f78fb44e 5256 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5257 /* Note: Rc update flag set leads to undefined state of Rc0 */
5258}
5259
5260/* mtdcrux (PPC 460) : user-mode access to DCR */
5261GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5262{
f78fb44e
AJ		 5263 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5264 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5265 gen_op_store_dcr();
5266 /* Note: Rc update flag set leads to undefined state of Rc0 */
5267}
5268
76a66253
JM		 5269/* dccci */
5270GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5271{
5272#if defined(CONFIG_USER_ONLY)
e1833e1f 5273 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5274#else
5275 if (unlikely(!ctx->supervisor)) {
e1833e1f 5276 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5277 return;
5278 }
5279 /* interpreted as no-op */
5280#endif
5281}
5282
5283/* dcread */
5284GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5285{
5286#if defined(CONFIG_USER_ONLY)
e1833e1f 5287 GEN_EXCP_PRIVOPC(ctx);
76a66253 5288#else
b61f2753 5289 TCGv EA, val;
76a66253 5290 if (unlikely(!ctx->supervisor)) {
e1833e1f 5291 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5292 return;
5293 }
b61f2753
AJ		 5294 EA = tcg_temp_new(TCG_TYPE_TL);
5295 gen_addr_reg_index(EA, ctx);
5296 val = tcg_temp_new(TCG_TYPE_TL);
5297 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5298 tcg_temp_free(val);
5299 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5300 tcg_temp_free(EA);
76a66253
JM		 5301#endif
5302}
5303
5304/* icbt */
c7697e1f 5305GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5306{
5307 /* interpreted as no-op */
5308 /* XXX: specification say this is treated as a load by the MMU
5309 * but does not generate any exception
5310 */
5311}
5312
5313/* iccci */
5314GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5315{
5316#if defined(CONFIG_USER_ONLY)
e1833e1f 5317 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5318#else
5319 if (unlikely(!ctx->supervisor)) {
e1833e1f 5320 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5321 return;
5322 }
5323 /* interpreted as no-op */
5324#endif
5325}
5326
5327/* icread */
5328GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5329{
5330#if defined(CONFIG_USER_ONLY)
e1833e1f 5331 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5332#else
5333 if (unlikely(!ctx->supervisor)) {
e1833e1f 5334 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5335 return;
5336 }
5337 /* interpreted as no-op */
5338#endif
5339}
5340
5341/* rfci (supervisor only) */
c7697e1f 5342GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5343{
5344#if defined(CONFIG_USER_ONLY)
e1833e1f 5345 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5346#else
5347 if (unlikely(!ctx->supervisor)) {
e1833e1f 5348 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5349 return;
5350 }
5351 /* Restore CPU state */
5352 gen_op_40x_rfci();
e1833e1f 5353 GEN_SYNC(ctx);
a42bd6cc
JM		 5354#endif
5355}
5356
5357GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5358{
5359#if defined(CONFIG_USER_ONLY)
e1833e1f 5360 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5361#else
5362 if (unlikely(!ctx->supervisor)) {
e1833e1f 5363 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5364 return;
5365 }
5366 /* Restore CPU state */
5367 gen_op_rfci();
e1833e1f 5368 GEN_SYNC(ctx);
a42bd6cc
JM		 5369#endif
5370}
5371
5372/* BookE specific */
2662a059 5373/* XXX: not implemented on 440 ? */
05332d70 5374GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5375{
5376#if defined(CONFIG_USER_ONLY)
e1833e1f 5377 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5378#else
5379 if (unlikely(!ctx->supervisor)) {
e1833e1f 5380 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5381 return;
5382 }
5383 /* Restore CPU state */
a42bd6cc 5384 gen_op_rfdi();
e1833e1f 5385 GEN_SYNC(ctx);
76a66253
JM		 5386#endif
5387}
5388
2662a059 5389/* XXX: not implemented on 440 ? */
a750fc0b 5390GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5391{
5392#if defined(CONFIG_USER_ONLY)
e1833e1f 5393 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5394#else
5395 if (unlikely(!ctx->supervisor)) {
e1833e1f 5396 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5397 return;
5398 }
5399 /* Restore CPU state */
5400 gen_op_rfmci();
e1833e1f 5401 GEN_SYNC(ctx);
a42bd6cc
JM		 5402#endif
5403}
5eb7995e 5404
d9bce9d9 5405/* TLB management - PowerPC 405 implementation */
76a66253 5406/* tlbre */
c7697e1f 5407GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5408{
5409#if defined(CONFIG_USER_ONLY)
e1833e1f 5410 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5411#else
5412 if (unlikely(!ctx->supervisor)) {
e1833e1f 5413 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5414 return;
5415 }
5416 switch (rB(ctx->opcode)) {
5417 case 0:
f78fb44e 5418 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5419 gen_op_4xx_tlbre_hi();
f78fb44e 5420 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5421 break;
5422 case 1:
f78fb44e 5423 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5424 gen_op_4xx_tlbre_lo();
f78fb44e 5425 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5426 break;
5427 default:
e1833e1f 5428 GEN_EXCP_INVAL(ctx);
76a66253 5429 break;
9a64fbe4 5430 }
76a66253
JM		 5431#endif
5432}
5433
d9bce9d9 5434/* tlbsx - tlbsx. */
c7697e1f 5435GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5436{
5437#if defined(CONFIG_USER_ONLY)
e1833e1f 5438 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5439#else
5440 if (unlikely(!ctx->supervisor)) {
e1833e1f 5441 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5442 return;
5443 }
e2be8d8d 5444 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5445 gen_op_4xx_tlbsx();
76a66253 5446 if (Rc(ctx->opcode))
daf4f96e 5447 gen_op_4xx_tlbsx_check();
f78fb44e 5448 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5449#endif
79aceca5
FB		 5450}
5451
76a66253 5452/* tlbwe */
c7697e1f 5453GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5454{
76a66253 5455#if defined(CONFIG_USER_ONLY)
e1833e1f 5456 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5457#else
5458 if (unlikely(!ctx->supervisor)) {
e1833e1f 5459 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5460 return;
5461 }
5462 switch (rB(ctx->opcode)) {
5463 case 0:
f78fb44e
AJ		 5464 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5465 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5466 gen_op_4xx_tlbwe_hi();
5467 break;
5468 case 1:
f78fb44e
AJ		 5469 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5470 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5471 gen_op_4xx_tlbwe_lo();
5472 break;
5473 default:
e1833e1f 5474 GEN_EXCP_INVAL(ctx);
76a66253 5475 break;
9a64fbe4 5476 }
76a66253
JM		 5477#endif
5478}
5479
a4bb6c3e 5480/* TLB management - PowerPC 440 implementation */
5eb7995e 5481/* tlbre */
c7697e1f 5482GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5483{
5484#if defined(CONFIG_USER_ONLY)
e1833e1f 5485 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5486#else
5487 if (unlikely(!ctx->supervisor)) {
e1833e1f 5488 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5489 return;
5490 }
5491 switch (rB(ctx->opcode)) {
5492 case 0:
5eb7995e 5493 case 1:
5eb7995e 5494 case 2:
f78fb44e 5495 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5496 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5497 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5498 break;
5499 default:
e1833e1f 5500 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5501 break;
5502 }
5503#endif
5504}
5505
5506/* tlbsx - tlbsx. */
c7697e1f 5507GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5508{
5509#if defined(CONFIG_USER_ONLY)
e1833e1f 5510 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5511#else
5512 if (unlikely(!ctx->supervisor)) {
e1833e1f 5513 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5514 return;
5515 }
e2be8d8d 5516 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5517 gen_op_440_tlbsx();
5eb7995e 5518 if (Rc(ctx->opcode))
daf4f96e 5519 gen_op_4xx_tlbsx_check();
f78fb44e 5520 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5521#endif
5522}
5523
5524/* tlbwe */
c7697e1f 5525GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5526{
5527#if defined(CONFIG_USER_ONLY)
e1833e1f 5528 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5529#else
5530 if (unlikely(!ctx->supervisor)) {
e1833e1f 5531 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5532 return;
5533 }
5534 switch (rB(ctx->opcode)) {
5535 case 0:
5eb7995e 5536 case 1:
5eb7995e 5537 case 2:
f78fb44e
AJ		 5538 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5539 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5540 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5541 break;
5542 default:
e1833e1f 5543 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5544 break;
5545 }
5546#endif
5547}
5548
76a66253 5549/* wrtee */
05332d70 5550GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5551{
5552#if defined(CONFIG_USER_ONLY)
e1833e1f 5553 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5554#else
5555 if (unlikely(!ctx->supervisor)) {
e1833e1f 5556 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5557 return;
5558 }
f78fb44e 5559 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5560 gen_op_wrte();
dee96f6c
JM		 5561 /* Stop translation to have a chance to raise an exception
5562 * if we just set msr_ee to 1
5563 */
e1833e1f 5564 GEN_STOP(ctx);
76a66253
JM		 5565#endif
5566}
5567
5568/* wrteei */
05332d70 5569GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5570{
5571#if defined(CONFIG_USER_ONLY)
e1833e1f 5572 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5573#else
5574 if (unlikely(!ctx->supervisor)) {
e1833e1f 5575 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5576 return;
5577 }
86c581dc 5578 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5579 gen_op_wrte();
dee96f6c
JM		 5580 /* Stop translation to have a chance to raise an exception
5581 * if we just set msr_ee to 1
5582 */
e1833e1f 5583 GEN_STOP(ctx);
76a66253
JM		 5584#endif
5585}
5586
08e46e54 5587/* PowerPC 440 specific instructions */
76a66253
JM		 5588/* dlmzb */
5589GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5590{
f78fb44e
AJ		 5591 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5592 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5593 gen_op_440_dlmzb();
f78fb44e 5594 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5595 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5596 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5597 if (Rc(ctx->opcode)) {
5598 gen_op_440_dlmzb_update_Rc();
47e4661c 5599 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
76a66253
JM		 5600 }
5601}
5602
5603/* mbar replaces eieio on 440 */
5604GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5605{
5606 /* interpreted as no-op */
5607}
5608
5609/* msync replaces sync on 440 */
0db1b20e 5610GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5611{
5612 /* interpreted as no-op */
5613}
5614
5615/* icbt */
c7697e1f 5616GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5617{
5618 /* interpreted as no-op */
5619 /* XXX: specification say this is treated as a load by the MMU
5620 * but does not generate any exception
5621 */
79aceca5
FB		 5622}
5623
a9d9eb8f
JM		 5624/*** Altivec vector extension ***/
5625/* Altivec registers moves */
a9d9eb8f 5626
1d542695
AJ		 5627static always_inline void gen_load_avr(int t, int reg) {
5628 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5629 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5630}
5631
5632static always_inline void gen_store_avr(int reg, int t) {
5633 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5634 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5635}
a9d9eb8f
JM		 5636
5637#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5638#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5639static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5640 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5641};
5642#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5643static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5644 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5645};
a9d9eb8f
JM		 5646
5647#define GEN_VR_LDX(name, opc2, opc3) \
5648GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5649{ \
5650 if (unlikely(!ctx->altivec_enabled)) { \
5651 GEN_EXCP_NO_VR(ctx); \
5652 return; \
5653 } \
e2be8d8d 5654 gen_addr_reg_index(cpu_T[0], ctx); \
a9d9eb8f 5655 op_vr_ldst(vr_l##name); \
1d542695 5656 gen_store_avr(rD(ctx->opcode), 0); \
a9d9eb8f
JM		 5657}
5658
5659#define GEN_VR_STX(name, opc2, opc3) \
5660GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5661{ \
5662 if (unlikely(!ctx->altivec_enabled)) { \
5663 GEN_EXCP_NO_VR(ctx); \
5664 return; \
5665 } \
e2be8d8d 5666 gen_addr_reg_index(cpu_T[0], ctx); \
1d542695 5667 gen_load_avr(0, rS(ctx->opcode)); \
a9d9eb8f
JM		 5668 op_vr_ldst(vr_st##name); \
5669}
5670
5671OP_VR_LD_TABLE(vx);
5672GEN_VR_LDX(vx, 0x07, 0x03);
5673/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5674#define gen_op_vr_lvxl gen_op_vr_lvx
5675GEN_VR_LDX(vxl, 0x07, 0x0B);
5676
5677OP_VR_ST_TABLE(vx);
5678GEN_VR_STX(vx, 0x07, 0x07);
5679/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5680#define gen_op_vr_stvxl gen_op_vr_stvx
5681GEN_VR_STX(vxl, 0x07, 0x0F);
5682
0487d6a8 5683/*** SPE extension ***/
0487d6a8 5684/* Register moves */
3cd7d1dd 5685
f78fb44e
AJ		 5686static always_inline void gen_load_gpr64(TCGv t, int reg) {
5687#if defined(TARGET_PPC64)
5688 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5689#else
36aa55dc 5690 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5691#endif
f78fb44e 5692}
3cd7d1dd 5693
f78fb44e
AJ		 5694static always_inline void gen_store_gpr64(int reg, TCGv t) {
5695#if defined(TARGET_PPC64)
5696 tcg_gen_mov_i64(cpu_gpr[reg], t);
5697#else
5698 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
19f98ff6 5699 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
f78fb44e
AJ		 5700 tcg_gen_shri_i64(tmp, t, 32);
5701 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5702 tcg_temp_free(tmp);
3cd7d1dd 5703#endif
f78fb44e 5704}
3cd7d1dd 5705
0487d6a8
JM		 5706#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5707GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5708{ \
5709 if (Rc(ctx->opcode)) \
5710 gen_##name1(ctx); \
5711 else \
5712 gen_##name0(ctx); \
5713}
5714
5715/* Handler for undefined SPE opcodes */
b068d6a7 5716static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5717{
e1833e1f 5718 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5719}
5720
5721/* SPE load and stores */
f0aabd1a 5722static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
0487d6a8
JM		 5723{
5724 target_long simm = rB(ctx->opcode);
5725
f0aabd1a
AJ		 5726 if (rA(ctx->opcode) == 0)
5727 tcg_gen_movi_tl(EA, simm << sh);
5728 else if (likely(simm != 0))
5729 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5730 else
5731 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
0487d6a8
JM		 5732}
5733
5734#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5735#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5736static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5737 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5738};
5739#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5740static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5741 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5742};
0487d6a8
JM		 5743
5744#define GEN_SPE_LD(name, sh) \
b068d6a7 5745static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5746{ \
5747 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5748 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5749 return; \
5750 } \
f0aabd1a 5751 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
0487d6a8 5752 op_spe_ldst(spe_l##name); \
f78fb44e 5753 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5754}
5755
5756#define GEN_SPE_LDX(name) \
b068d6a7 5757static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 5758{ \
5759 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5760 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5761 return; \
5762 } \
e2be8d8d 5763 gen_addr_reg_index(cpu_T[0], ctx); \
0487d6a8 5764 op_spe_ldst(spe_l##name); \
f78fb44e 5765 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5766}
5767
5768#define GEN_SPEOP_LD(name, sh) \
5769OP_SPE_LD_TABLE(name); \
5770GEN_SPE_LD(name, sh); \
5771GEN_SPE_LDX(name)
5772
5773#define GEN_SPE_ST(name, sh) \
b068d6a7 5774static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 5775{ \
5776 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5777 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5778 return; \
5779 } \
f0aabd1a 5780 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
f78fb44e 5781 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5782 op_spe_ldst(spe_st##name); \
5783}
5784
5785#define GEN_SPE_STX(name) \
b068d6a7 5786static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 5787{ \
5788 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5789 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5790 return; \
5791 } \
e2be8d8d 5792 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 5793 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5794 op_spe_ldst(spe_st##name); \
5795}
5796
5797#define GEN_SPEOP_ST(name, sh) \
5798OP_SPE_ST_TABLE(name); \
5799GEN_SPE_ST(name, sh); \
5800GEN_SPE_STX(name)
5801
5802#define GEN_SPEOP_LDST(name, sh) \
5803GEN_SPEOP_LD(name, sh); \
5804GEN_SPEOP_ST(name, sh)
5805
5806/* SPE arithmetic and logic */
5807#define GEN_SPEOP_ARITH2(name) \
b068d6a7 5808static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5809{ \
5810 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5811 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5812 return; \
5813 } \
f78fb44e
AJ		 5814 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5815 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5816 gen_op_##name(); \
f78fb44e 5817 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5818}
5819
cf960816 5820#define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \
3d3a6a0a
AJ		 5821static always_inline void gen_##name (DisasContext *ctx) \
5822{ \
5823 if (unlikely(!ctx->spe_enabled)) { \
5824 GEN_EXCP_NO_AP(ctx); \
5825 return; \
5826 } \
5827 TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \
5828 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
5829 gen_load_gpr64(t0, rA(ctx->opcode)); \
5830 gen_load_gpr64(t1, rB(ctx->opcode)); \
cf960816 5831 tcg_op(t0, t0, t1); \
3d3a6a0a
AJ		 5832 gen_store_gpr64(rD(ctx->opcode), t0); \
5833 tcg_temp_free(t0); \
5834 tcg_temp_free(t1); \
5835}
5836
0487d6a8 5837#define GEN_SPEOP_ARITH1(name) \
b068d6a7 5838static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5839{ \
5840 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5841 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5842 return; \
5843 } \
f78fb44e 5844 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8 5845 gen_op_##name(); \
f78fb44e 5846 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5847}
5848
5849#define GEN_SPEOP_COMP(name) \
b068d6a7 5850static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5851{ \
5852 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5853 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5854 return; \
5855 } \
f78fb44e
AJ		 5856 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5857 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5858 gen_op_##name(); \
47e4661c 5859 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
0487d6a8
JM		 5860}
5861
5862/* Logical */
cf960816
AJ		 5863GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64);
5864GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64);
5865GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64);
5866GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64);
5867GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64);
5868GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64);
5869GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64);
5870GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64);
0487d6a8
JM		 5871GEN_SPEOP_ARITH2(evsrwu);
5872GEN_SPEOP_ARITH2(evsrws);
5873GEN_SPEOP_ARITH2(evslw);
5874GEN_SPEOP_ARITH2(evrlw);
5875GEN_SPEOP_ARITH2(evmergehi);
5876GEN_SPEOP_ARITH2(evmergelo);
5877GEN_SPEOP_ARITH2(evmergehilo);
5878GEN_SPEOP_ARITH2(evmergelohi);
5879
5880/* Arithmetic */
5881GEN_SPEOP_ARITH2(evaddw);
5882GEN_SPEOP_ARITH2(evsubfw);
5883GEN_SPEOP_ARITH1(evabs);
5884GEN_SPEOP_ARITH1(evneg);
5885GEN_SPEOP_ARITH1(evextsb);
5886GEN_SPEOP_ARITH1(evextsh);
5887GEN_SPEOP_ARITH1(evrndw);
5888GEN_SPEOP_ARITH1(evcntlzw);
5889GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 5890static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 5891{
5892 /* Note: brinc is usable even if SPE is disabled */
f78fb44e
AJ		 5893 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5894 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 5895 gen_op_brinc();
f78fb44e 5896 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
0487d6a8
JM		 5897}
5898
5899#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 5900static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5901{ \
5902 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5903 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5904 return; \
5905 } \
f78fb44e 5906 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8
JM		 5907 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5908 gen_op_##name(); \
f78fb44e 5909 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5910}
5911
5912#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 5913static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5914{ \
5915 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5916 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5917 return; \
5918 } \
f78fb44e 5919 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8
JM		 5920 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5921 gen_op_##name(); \
f78fb44e 5922 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5923}
5924
5925GEN_SPEOP_ARITH_IMM2(evaddw);
5926#define gen_evaddiw gen_evaddwi
5927GEN_SPEOP_ARITH_IMM2(evsubfw);
5928#define gen_evsubifw gen_evsubfwi
5929GEN_SPEOP_LOGIC_IMM2(evslw);
5930GEN_SPEOP_LOGIC_IMM2(evsrwu);
5931#define gen_evsrwis gen_evsrwsi
5932GEN_SPEOP_LOGIC_IMM2(evsrws);
5933#define gen_evsrwiu gen_evsrwui
5934GEN_SPEOP_LOGIC_IMM2(evrlw);
5935
b068d6a7 5936static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 5937{
5938 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5939
5940 gen_op_splatwi_T0_64(imm);
f78fb44e 5941 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5942}
5943
b068d6a7 5944static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 5945{
5946 uint32_t imm = rA(ctx->opcode) << 27;
5947
5948 gen_op_splatwi_T0_64(imm);
f78fb44e 5949 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5950}
5951
5952/* Comparison */
5953GEN_SPEOP_COMP(evcmpgtu);
5954GEN_SPEOP_COMP(evcmpgts);
5955GEN_SPEOP_COMP(evcmpltu);
5956GEN_SPEOP_COMP(evcmplts);
5957GEN_SPEOP_COMP(evcmpeq);
5958
5959GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5960GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5961GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5962GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5963GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5964GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5965GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5966GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5967GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5968GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5969GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5970GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5971GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5972GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5973GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5974GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5975GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5976GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5977GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5978GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5979GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5980GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5981GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5982GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5983GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5984
b068d6a7 5985static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 5986{
5987 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 5988 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 5989 return;
5990 }
47e4661c 5991 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
f78fb44e
AJ		 5992 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
5993 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
0487d6a8 5994 gen_op_evsel();
f78fb44e 5995 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5996}
5997
c7697e1f 5998GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5999{
6000 gen_evsel(ctx);
6001}
c7697e1f 6002GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6003{
6004 gen_evsel(ctx);
6005}
c7697e1f 6006GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6007{
6008 gen_evsel(ctx);
6009}
c7697e1f 6010GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6011{
6012 gen_evsel(ctx);
6013}
6014
6015/* Load and stores */
0487d6a8
JM		 6016GEN_SPEOP_LDST(dd, 3);
6017GEN_SPEOP_LDST(dw, 3);
6018GEN_SPEOP_LDST(dh, 3);
6019GEN_SPEOP_LDST(whe, 2);
6020GEN_SPEOP_LD(whou, 2);
6021GEN_SPEOP_LD(whos, 2);
6022GEN_SPEOP_ST(who, 2);
6023
0487d6a8 6024#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 6025static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 6026{ \
6027 gen_op_srli32_T1_64(); \
6028 gen_op_spe_stwwo_##suffix(); \
6029}
6030#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 6031static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 6032{ \
6033 gen_op_srli32_T1_64(); \
6034 gen_op_spe_stwwo_le_##suffix(); \
6035}
6036#if defined(TARGET_PPC64)
6037#define GEN_OP_SPE_STWWE(suffix) \
6038_GEN_OP_SPE_STWWE(suffix); \
6039_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 6040static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 6041{ \
6042 gen_op_srli32_T1_64(); \
6043 gen_op_spe_stwwo_64_##suffix(); \
6044} \
b068d6a7 6045static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 6046{ \
6047 gen_op_srli32_T1_64(); \
6048 gen_op_spe_stwwo_le_64_##suffix(); \
6049}
6050#else
6051#define GEN_OP_SPE_STWWE(suffix) \
6052_GEN_OP_SPE_STWWE(suffix); \
6053_GEN_OP_SPE_STWWE_LE(suffix)
6054#endif
6055#if defined(CONFIG_USER_ONLY)
6056GEN_OP_SPE_STWWE(raw);
6057#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 6058GEN_OP_SPE_STWWE(user);
7863667f
JM		 6059GEN_OP_SPE_STWWE(kernel);
6060GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 6061#endif /* defined(CONFIG_USER_ONLY) */
6062GEN_SPEOP_ST(wwe, 2);
6063GEN_SPEOP_ST(wwo, 2);
6064
6065#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 6066static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 6067{ \
6068 gen_op_##op##_##suffix(); \
6069 gen_op_splatw_T1_64(); \
6070}
6071
6072#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 6073static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 6074{ \
6075 gen_op_spe_lh_##suffix(); \
6076 gen_op_sli16_T1_64(); \
6077}
6078
6079#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 6080static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 6081{ \
6082 gen_op_spe_lh_##suffix(); \
6083 gen_op_extsh_T1_64(); \
6084}
6085
6086#if defined(CONFIG_USER_ONLY)
6087GEN_OP_SPE_LHE(raw);
6088GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6089GEN_OP_SPE_LHE(le_raw);
6090GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6091GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6092GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6093GEN_OP_SPE_LHX(raw);
6094GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6095GEN_OP_SPE_LHX(le_raw);
6096GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6097#if defined(TARGET_PPC64)
6098GEN_OP_SPE_LHE(64_raw);
6099GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6100GEN_OP_SPE_LHE(le_64_raw);
6101GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6102GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6103GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6104GEN_OP_SPE_LHX(64_raw);
6105GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6106GEN_OP_SPE_LHX(le_64_raw);
6107GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6108#endif
6109#else
0487d6a8 6110GEN_OP_SPE_LHE(user);
7863667f
JM		 6111GEN_OP_SPE_LHE(kernel);
6112GEN_OP_SPE_LHE(hypv);
0487d6a8 6113GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 6114GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6115GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 6116GEN_OP_SPE_LHE(le_user);
7863667f
JM		 6117GEN_OP_SPE_LHE(le_kernel);
6118GEN_OP_SPE_LHE(le_hypv);
0487d6a8 6119GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 6120GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6121GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 6122GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 6123GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6124GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 6125GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 6126GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6127GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 6128GEN_OP_SPE_LHX(user);
7863667f
JM		 6129GEN_OP_SPE_LHX(kernel);
6130GEN_OP_SPE_LHX(hypv);
0487d6a8 6131GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 6132GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6133GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 6134GEN_OP_SPE_LHX(le_user);
7863667f
JM		 6135GEN_OP_SPE_LHX(le_kernel);
6136GEN_OP_SPE_LHX(le_hypv);
0487d6a8 6137GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 6138GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6139GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 6140#if defined(TARGET_PPC64)
0487d6a8 6141GEN_OP_SPE_LHE(64_user);
7863667f
JM		 6142GEN_OP_SPE_LHE(64_kernel);
6143GEN_OP_SPE_LHE(64_hypv);
0487d6a8 6144GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 6145GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6146GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 6147GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 6148GEN_OP_SPE_LHE(le_64_kernel);
6149GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 6150GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 6151GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6152GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 6153GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 6154GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6155GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 6156GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 6157GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6158GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 6159GEN_OP_SPE_LHX(64_user);
7863667f
JM		 6160GEN_OP_SPE_LHX(64_kernel);
6161GEN_OP_SPE_LHX(64_hypv);
0487d6a8 6162GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 6163GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6164GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 6165GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 6166GEN_OP_SPE_LHX(le_64_kernel);
6167GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 6168GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 6169GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6170GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 6171#endif
6172#endif
6173GEN_SPEOP_LD(hhesplat, 1);
6174GEN_SPEOP_LD(hhousplat, 1);
6175GEN_SPEOP_LD(hhossplat, 1);
6176GEN_SPEOP_LD(wwsplat, 2);
6177GEN_SPEOP_LD(whsplat, 2);
6178
6179GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6180GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6181GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6182GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6183GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6184GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6185GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6186GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6187GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6188GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6189GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6190GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6191GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6192GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6193GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6194GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6195GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6196GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6197
6198/* Multiply and add - TODO */
6199#if 0
6200GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6201GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6202GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6203GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6204GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6205GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6206GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6207GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6208GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6209GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6210GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6211GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6212
6213GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6214GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6215GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6216GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6217GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6218GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6219GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6220GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6221GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6222GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6223GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6224GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6225GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6226GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6227
6228GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6229GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6230GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6231GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6232GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6233GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6234
6235GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6236GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6237GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6238GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6239GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6240GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6241GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6242GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6243GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6244GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6245GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6246GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6247
6248GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6249GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6250GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6251GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6252GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6253
6254GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6255GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6256GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6257GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6258GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6259GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6260GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6261GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6262GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6263GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6264GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6265GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6266
6267GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6268GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6269GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6270GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6271GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6272#endif
6273
6274/*** SPE floating-point extension ***/
6275#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 6276static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6277{ \
f78fb44e 6278 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8 6279 gen_op_##name(); \
f78fb44e 6280 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6281}
6282
6283/* Single precision floating-point vectors operations */
6284/* Arithmetic */
6285GEN_SPEOP_ARITH2(evfsadd);
6286GEN_SPEOP_ARITH2(evfssub);
6287GEN_SPEOP_ARITH2(evfsmul);
6288GEN_SPEOP_ARITH2(evfsdiv);
6289GEN_SPEOP_ARITH1(evfsabs);
6290GEN_SPEOP_ARITH1(evfsnabs);
6291GEN_SPEOP_ARITH1(evfsneg);
6292/* Conversion */
6293GEN_SPEFPUOP_CONV(evfscfui);
6294GEN_SPEFPUOP_CONV(evfscfsi);
6295GEN_SPEFPUOP_CONV(evfscfuf);
6296GEN_SPEFPUOP_CONV(evfscfsf);
6297GEN_SPEFPUOP_CONV(evfsctui);
6298GEN_SPEFPUOP_CONV(evfsctsi);
6299GEN_SPEFPUOP_CONV(evfsctuf);
6300GEN_SPEFPUOP_CONV(evfsctsf);
6301GEN_SPEFPUOP_CONV(evfsctuiz);
6302GEN_SPEFPUOP_CONV(evfsctsiz);
6303/* Comparison */
6304GEN_SPEOP_COMP(evfscmpgt);
6305GEN_SPEOP_COMP(evfscmplt);
6306GEN_SPEOP_COMP(evfscmpeq);
6307GEN_SPEOP_COMP(evfststgt);
6308GEN_SPEOP_COMP(evfststlt);
6309GEN_SPEOP_COMP(evfststeq);
6310
6311/* Opcodes definitions */
6312GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6313GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6314GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6315GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6316GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6317GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6318GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6319GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6320GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6321GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6322GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6323GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6324GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6325GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6326
6327/* Single precision floating-point operations */
6328/* Arithmetic */
6329GEN_SPEOP_ARITH2(efsadd);
6330GEN_SPEOP_ARITH2(efssub);
6331GEN_SPEOP_ARITH2(efsmul);
6332GEN_SPEOP_ARITH2(efsdiv);
6333GEN_SPEOP_ARITH1(efsabs);
6334GEN_SPEOP_ARITH1(efsnabs);
6335GEN_SPEOP_ARITH1(efsneg);
6336/* Conversion */
6337GEN_SPEFPUOP_CONV(efscfui);
6338GEN_SPEFPUOP_CONV(efscfsi);
6339GEN_SPEFPUOP_CONV(efscfuf);
6340GEN_SPEFPUOP_CONV(efscfsf);
6341GEN_SPEFPUOP_CONV(efsctui);
6342GEN_SPEFPUOP_CONV(efsctsi);
6343GEN_SPEFPUOP_CONV(efsctuf);
6344GEN_SPEFPUOP_CONV(efsctsf);
6345GEN_SPEFPUOP_CONV(efsctuiz);
6346GEN_SPEFPUOP_CONV(efsctsiz);
6347GEN_SPEFPUOP_CONV(efscfd);
6348/* Comparison */
6349GEN_SPEOP_COMP(efscmpgt);
6350GEN_SPEOP_COMP(efscmplt);
6351GEN_SPEOP_COMP(efscmpeq);
6352GEN_SPEOP_COMP(efststgt);
6353GEN_SPEOP_COMP(efststlt);
6354GEN_SPEOP_COMP(efststeq);
6355
6356/* Opcodes definitions */
05332d70 6357GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 6358GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6359GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6360GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6361GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6362GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6363GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6364GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6365GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6366GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 6367GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6368GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 6369GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6370GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6371
6372/* Double precision floating-point operations */
6373/* Arithmetic */
6374GEN_SPEOP_ARITH2(efdadd);
6375GEN_SPEOP_ARITH2(efdsub);
6376GEN_SPEOP_ARITH2(efdmul);
6377GEN_SPEOP_ARITH2(efddiv);
6378GEN_SPEOP_ARITH1(efdabs);
6379GEN_SPEOP_ARITH1(efdnabs);
6380GEN_SPEOP_ARITH1(efdneg);
6381/* Conversion */
6382
6383GEN_SPEFPUOP_CONV(efdcfui);
6384GEN_SPEFPUOP_CONV(efdcfsi);
6385GEN_SPEFPUOP_CONV(efdcfuf);
6386GEN_SPEFPUOP_CONV(efdcfsf);
6387GEN_SPEFPUOP_CONV(efdctui);
6388GEN_SPEFPUOP_CONV(efdctsi);
6389GEN_SPEFPUOP_CONV(efdctuf);
6390GEN_SPEFPUOP_CONV(efdctsf);
6391GEN_SPEFPUOP_CONV(efdctuiz);
6392GEN_SPEFPUOP_CONV(efdctsiz);
6393GEN_SPEFPUOP_CONV(efdcfs);
6394GEN_SPEFPUOP_CONV(efdcfuid);
6395GEN_SPEFPUOP_CONV(efdcfsid);
6396GEN_SPEFPUOP_CONV(efdctuidz);
6397GEN_SPEFPUOP_CONV(efdctsidz);
6398/* Comparison */
6399GEN_SPEOP_COMP(efdcmpgt);
6400GEN_SPEOP_COMP(efdcmplt);
6401GEN_SPEOP_COMP(efdcmpeq);
6402GEN_SPEOP_COMP(efdtstgt);
6403GEN_SPEOP_COMP(efdtstlt);
6404GEN_SPEOP_COMP(efdtsteq);
6405
6406/* Opcodes definitions */
6407GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6408GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6409GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6410GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6411GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6412GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6413GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6414GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6415GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6416GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6417GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6418GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6419GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6420GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6421GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6422GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6423
79aceca5
FB		 6424/* End opcode list */
6425GEN_OPCODE_MARK(end);
6426
3fc6c082 6427#include "translate_init.c"
0411a972 6428#include "helper_regs.h"
79aceca5 6429
9a64fbe4 6430/*****************************************************************************/
3fc6c082 6431/* Misc PowerPC helpers */
36081602
JM		 6432void cpu_dump_state (CPUState *env, FILE *f,
6433 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6434 int flags)
79aceca5 6435{
3fc6c082
FB		 6436#define RGPL 4
6437#define RFPL 4
3fc6c082 6438
79aceca5
FB		 6439 int i;
6440
077fc206 6441 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 6442 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 6443 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6444 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 6445#if !defined(NO_TIMER_DUMP)
077fc206 6446 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6447#if !defined(CONFIG_USER_ONLY)
6448 "DECR %08x"
6449#endif
6450 "\n",
077fc206 6451 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6452#if !defined(CONFIG_USER_ONLY)
6453 , cpu_ppc_load_decr(env)
6454#endif
6455 );
077fc206 6456#endif
76a66253 6457 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6458 if ((i & (RGPL - 1)) == 0)
6459 cpu_fprintf(f, "GPR%02d", i);
6b542af7 6460 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 6461 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6462 cpu_fprintf(f, "\n");
76a66253 6463 }
3fc6c082 6464 cpu_fprintf(f, "CR ");
76a66253 6465 for (i = 0; i < 8; i++)
7fe48483
FB		 6466 cpu_fprintf(f, "%01x", env->crf[i]);
6467 cpu_fprintf(f, " [");
76a66253
JM		 6468 for (i = 0; i < 8; i++) {
6469 char a = '-';
6470 if (env->crf[i] & 0x08)
6471 a = 'L';
6472 else if (env->crf[i] & 0x04)
6473 a = 'G';
6474 else if (env->crf[i] & 0x02)
6475 a = 'E';
7fe48483 6476 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6477 }
6b542af7 6478 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 6479 for (i = 0; i < 32; i++) {
6480 if ((i & (RFPL - 1)) == 0)
6481 cpu_fprintf(f, "FPR%02d", i);
26a76461 6482 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6483 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6484 cpu_fprintf(f, "\n");
79aceca5 6485 }
f2e63a42 6486#if !defined(CONFIG_USER_ONLY)
6b542af7 6487 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 6488 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6489#endif
79aceca5 6490
3fc6c082
FB		 6491#undef RGPL
6492#undef RFPL
79aceca5
FB		 6493}
6494
76a66253
JM		 6495void cpu_dump_statistics (CPUState *env, FILE*f,
6496 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6497 int flags)
6498{
6499#if defined(DO_PPC_STATISTICS)
6500 opc_handler_t **t1, **t2, **t3, *handler;
6501 int op1, op2, op3;
6502
6503 t1 = env->opcodes;
6504 for (op1 = 0; op1 < 64; op1++) {
6505 handler = t1[op1];
6506 if (is_indirect_opcode(handler)) {
6507 t2 = ind_table(handler);
6508 for (op2 = 0; op2 < 32; op2++) {
6509 handler = t2[op2];
6510 if (is_indirect_opcode(handler)) {
6511 t3 = ind_table(handler);
6512 for (op3 = 0; op3 < 32; op3++) {
6513 handler = t3[op3];
6514 if (handler->count == 0)
6515 continue;
6516 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6517 "%016llx %lld\n",
6518 op1, op2, op3, op1, (op3 << 5) | op2,
6519 handler->oname,
6520 handler->count, handler->count);
6521 }
6522 } else {
6523 if (handler->count == 0)
6524 continue;
6525 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6526 "%016llx %lld\n",
6527 op1, op2, op1, op2, handler->oname,
6528 handler->count, handler->count);
6529 }
6530 }
6531 } else {
6532 if (handler->count == 0)
6533 continue;
6534 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6535 op1, op1, handler->oname,
6536 handler->count, handler->count);
6537 }
6538 }
6539#endif
6540}
6541
9a64fbe4 6542/*****************************************************************************/
2cfc5f17
TS		 6543static always_inline void gen_intermediate_code_internal (CPUState *env,
6544 TranslationBlock *tb,
6545 int search_pc)
79aceca5 6546{
9fddaa0c 6547 DisasContext ctx, *ctxp = &ctx;
79aceca5 6548 opc_handler_t **table, *handler;
0fa85d43 6549 target_ulong pc_start;
79aceca5 6550 uint16_t *gen_opc_end;
056401ea 6551 int supervisor, little_endian;
79aceca5 6552 int j, lj = -1;
2e70f6ef
PB		 6553 int num_insns;
6554 int max_insns;
79aceca5
FB		 6555
6556 pc_start = tb->pc;
79aceca5 6557 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 6558#if defined(OPTIMIZE_FPRF_UPDATE)
6559 gen_fprf_ptr = gen_fprf_buf;
6560#endif
046d6672 6561 ctx.nip = pc_start;
79aceca5 6562 ctx.tb = tb;
e1833e1f 6563 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6564 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6565 supervisor = env->mmu_idx;
6566#if !defined(CONFIG_USER_ONLY)
2857068e 6567 ctx.supervisor = supervisor;
d9bce9d9 6568#endif
056401ea 6569 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6570#if defined(TARGET_PPC64)
6571 ctx.sf_mode = msr_sf;
056401ea 6572 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6573#else
056401ea 6574 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6575#endif
d63001d1 6576 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6577 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6578 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6579 ctx.spe_enabled = msr_spe;
6580 else
6581 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6582 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6583 ctx.altivec_enabled = msr_vr;
6584 else
6585 ctx.altivec_enabled = 0;
d26bfc9a 6586 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 6587 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 6588 else
8cbcb4fa 6589 ctx.singlestep_enabled = 0;
d26bfc9a 6590 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 6591 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6592 if (unlikely(env->singlestep_enabled))
6593 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 6594#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6595 /* Single step trace mode */
6596 msr_se = 1;
6597#endif
2e70f6ef
PB		 6598 num_insns = 0;
6599 max_insns = tb->cflags & CF_COUNT_MASK;
6600 if (max_insns == 0)
6601 max_insns = CF_COUNT_MASK;
6602
6603 gen_icount_start();
9a64fbe4 6604 /* Set env in case of segfault during code fetch */
e1833e1f 6605 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6606 if (unlikely(env->nb_breakpoints > 0)) {
6607 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6608 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6609 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6610 gen_op_debug();
6611 break;
6612 }
6613 }
6614 }
76a66253 6615 if (unlikely(search_pc)) {
79aceca5
FB		 6616 j = gen_opc_ptr - gen_opc_buf;
6617 if (lj < j) {
6618 lj++;
6619 while (lj < j)
6620 gen_opc_instr_start[lj++] = 0;
046d6672 6621 gen_opc_pc[lj] = ctx.nip;
79aceca5 6622 gen_opc_instr_start[lj] = 1;
2e70f6ef 6623 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 6624 }
6625 }
9fddaa0c
FB		 6626#if defined PPC_DEBUG_DISAS
6627 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6628 fprintf(logfile, "----------------\n");
1b9eb036 6629 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6630 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6631 }
6632#endif
2e70f6ef
PB		 6633 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6634 gen_io_start();
056401ea
JM		 6635 if (unlikely(little_endian)) {
6636 ctx.opcode = bswap32(ldl_code(ctx.nip));
6637 } else {
6638 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6639 }
9fddaa0c
FB		 6640#if defined PPC_DEBUG_DISAS
6641 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6642 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6643 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6644 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6645 }
6646#endif
046d6672 6647 ctx.nip += 4;
3fc6c082 6648 table = env->opcodes;
2e70f6ef 6649 num_insns++;
79aceca5
FB		 6650 handler = table[opc1(ctx.opcode)];
6651 if (is_indirect_opcode(handler)) {
6652 table = ind_table(handler);
6653 handler = table[opc2(ctx.opcode)];
6654 if (is_indirect_opcode(handler)) {
6655 table = ind_table(handler);
6656 handler = table[opc3(ctx.opcode)];
6657 }
6658 }
6659 /* Is opcode *REALLY* valid ? */
76a66253 6660 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6661 if (loglevel != 0) {
76a66253 6662 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 6663 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 6664 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6665 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6666 } else {
6667 printf("invalid/unsupported opcode: "
6b542af7 6668 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 6669 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6670 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6671 }
76a66253
JM		 6672 } else {
6673 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6674 if (loglevel != 0) {
79aceca5 6675 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 6676 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 6677 ctx.opcode & handler->inval, opc1(ctx.opcode),
6678 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6679 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6680 } else {
6681 printf("invalid bits: %08x for opcode: "
6b542af7 6682 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 6683 ctx.opcode & handler->inval, opc1(ctx.opcode),
6684 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6685 ctx.opcode, ctx.nip - 4);
76a66253 6686 }
e1833e1f 6687 GEN_EXCP_INVAL(ctxp);
4b3686fa 6688 break;
79aceca5 6689 }
79aceca5 6690 }
4b3686fa 6691 (*(handler->handler))(&ctx);
76a66253
JM		 6692#if defined(DO_PPC_STATISTICS)
6693 handler->count++;
6694#endif
9a64fbe4 6695 /* Check trace mode exceptions */
8cbcb4fa
AJ		 6696 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6697 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6698 ctx.exception != POWERPC_SYSCALL &&
6699 ctx.exception != POWERPC_EXCP_TRAP &&
6700 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 6701 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 6702 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 6703 (env->singlestep_enabled) ||
6704 num_insns >= max_insns)) {
d26bfc9a
JM		 6705 /* if we reach a page boundary or are single stepping, stop
6706 * generation
6707 */
8dd4983c 6708 break;
76a66253 6709 }
3fc6c082
FB		 6710#if defined (DO_SINGLE_STEP)
6711 break;
6712#endif
6713 }
2e70f6ef
PB		 6714 if (tb->cflags & CF_LAST_IO)
6715 gen_io_end();
e1833e1f 6716 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6717 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6718 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 6719 if (unlikely(env->singlestep_enabled)) {
6720 gen_update_nip(&ctx, ctx.nip);
6721 gen_op_debug();
6722 }
76a66253 6723 /* Generate the return instruction */
57fec1fe 6724 tcg_gen_exit_tb(0);
9a64fbe4 6725 }
2e70f6ef 6726 gen_icount_end(tb, num_insns);
79aceca5 6727 *gen_opc_ptr = INDEX_op_end;
76a66253 6728 if (unlikely(search_pc)) {
9a64fbe4
FB		 6729 j = gen_opc_ptr - gen_opc_buf;
6730 lj++;
6731 while (lj <= j)
6732 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6733 } else {
046d6672 6734 tb->size = ctx.nip - pc_start;
2e70f6ef 6735 tb->icount = num_insns;
9a64fbe4 6736 }
d9bce9d9 6737#if defined(DEBUG_DISAS)
9fddaa0c 6738 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6739 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6740 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6741 }
6742 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6743 int flags;
237c0af0 6744 flags = env->bfd_mach;
056401ea 6745 flags |= little_endian << 16;
0fa85d43 6746 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6747 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6748 fprintf(logfile, "\n");
9fddaa0c 6749 }
79aceca5 6750#endif
79aceca5
FB		 6751}
6752
2cfc5f17 6753void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 6754{
2cfc5f17 6755 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 6756}
6757
2cfc5f17 6758void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 6759{
2cfc5f17 6760 gen_intermediate_code_internal(env, tb, 1);
79aceca5 6761}
d2856f1a
AJ		 6762
6763void gen_pc_load(CPUState *env, TranslationBlock *tb,
6764 unsigned long searched_pc, int pc_pos, void *puc)
6765{
6766 int type, c;
6767 /* for PPC, we need to look at the micro operation to get the
6768 * access type */
6769 env->nip = gen_opc_pc[pc_pos];
6770 c = gen_opc_buf[pc_pos];
6771 switch(c) {
6772#if defined(CONFIG_USER_ONLY)
6773#define CASE3(op)\
6774 case INDEX_op_ ## op ## _raw
6775#else
6776#define CASE3(op)\
6777 case INDEX_op_ ## op ## _user:\
6778 case INDEX_op_ ## op ## _kernel:\
6779 case INDEX_op_ ## op ## _hypv
6780#endif
6781
6782 CASE3(stfd):
6783 CASE3(stfs):
6784 CASE3(lfd):
6785 CASE3(lfs):
6786 type = ACCESS_FLOAT;
6787 break;
6788 CASE3(lwarx):
6789 type = ACCESS_RES;
6790 break;
6791 CASE3(stwcx):
6792 type = ACCESS_RES;
6793 break;
6794 CASE3(eciwx):
6795 CASE3(ecowx):
6796 type = ACCESS_EXT;
6797 break;
6798 default:
6799 type = ACCESS_INT;
6800 break;
6801 }
6802 env->access_type = type;
6803}
Qemu copy for testing