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target-ppc: convert external load/store instructions to TCG
[qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a7812ae4
PB		 32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
8cbcb4fa
AJ		 36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
a750fc0b 40/* Include definitions for instructions classes and implementations flags */
79aceca5 41//#define DO_SINGLE_STEP
9fddaa0c 42//#define PPC_DEBUG_DISAS
76a66253 43//#define DO_PPC_STATISTICS
7c58044c 44//#define OPTIMIZE_FPRF_UPDATE
79aceca5 45
a750fc0b
JM		 46/*****************************************************************************/
47/* Code translation helpers */
c53be334 48
f78fb44e 49/* global register indexes */
a7812ae4 50static TCGv_ptr cpu_env;
1d542695 51static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 52#if !defined(TARGET_PPC64)
1d542695 53 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 54#endif
a5e26afa 55 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
f78fb44e
AJ		 58static TCGv cpu_gpr[32];
59#if !defined(TARGET_PPC64)
60static TCGv cpu_gprh[32];
61#endif
a7812ae4
PB		 62static TCGv_i64 cpu_fpr[32];
63static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64static TCGv_i32 cpu_crf[8];
bd568f18 65static TCGv cpu_nip;
cfdcd37a
AJ		 66static TCGv cpu_ctr;
67static TCGv cpu_lr;
3d7b417e 68static TCGv cpu_xer;
cf360a32 69static TCGv cpu_reserve;
a7812ae4 70static TCGv_i32 cpu_fpscr;
a7859e89 71static TCGv_i32 cpu_access_type;
f78fb44e
AJ		 72
73/* dyngen register indexes */
74static TCGv cpu_T[3];
2e70f6ef
PB		 75
76#include "gen-icount.h"
77
78void ppc_translate_init(void)
79{
f78fb44e
AJ		 80 int i;
81 char* p;
b2437bf2 82 static int done_init = 0;
f78fb44e 83
2e70f6ef
PB		 84 if (done_init)
85 return;
f78fb44e 86
a7812ae4 87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1c73fe5b 88#if TARGET_LONG_BITS > HOST_LONG_BITS
a7812ae4
PB		 89 cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");
90 cpu_T[1] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t1), "T1");
91 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
1c73fe5b 92#else
a7812ae4
PB		 93 cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");
94 cpu_T[1] = tcg_global_reg_new(TCG_AREG2, "T1");
4870167d
AJ		 95#ifdef HOST_I386
96 /* XXX: This is a temporary workaround for i386.
97 * On i386 qemu_st32 runs out of registers.
98 * The proper fix is to remove cpu_T.
99 */
a7812ae4 100 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
4870167d 101#else
a7812ae4 102 cpu_T[2] = tcg_global_reg_new(TCG_AREG3, "T2");
1c73fe5b 103#endif
a7812ae4
PB		 104#endif
105
f78fb44e 106 p = cpu_reg_names;
47e4661c
AJ		 107
108 for (i = 0; i < 8; i++) {
109 sprintf(p, "crf%d", i);
a7812ae4
PB		 110 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 112 p += 5;
113 }
114
f78fb44e
AJ		 115 for (i = 0; i < 32; i++) {
116 sprintf(p, "r%d", i);
a7812ae4 117 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 118 offsetof(CPUState, gpr[i]), p);
119 p += (i < 10) ? 3 : 4;
120#if !defined(TARGET_PPC64)
121 sprintf(p, "r%dH", i);
a7812ae4
PB		 122 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
123 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 124 p += (i < 10) ? 4 : 5;
125#endif
1d542695 126
a5e26afa 127 sprintf(p, "fp%d", i);
a7812ae4
PB		 128 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
129 offsetof(CPUState, fpr[i]), p);
ec1ac72d 130 p += (i < 10) ? 4 : 5;
a5e26afa 131
1d542695 132 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 133#ifdef WORDS_BIGENDIAN
134 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUState, avr[i].u64[0]), p);
136#else
a7812ae4 137 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 138 offsetof(CPUState, avr[i].u64[1]), p);
139#endif
1d542695 140 p += (i < 10) ? 6 : 7;
ec1ac72d 141
1d542695 142 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 143#ifdef WORDS_BIGENDIAN
144 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
145 offsetof(CPUState, avr[i].u64[1]), p);
146#else
a7812ae4 147 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 148 offsetof(CPUState, avr[i].u64[0]), p);
149#endif
1d542695 150 p += (i < 10) ? 6 : 7;
f78fb44e 151 }
f10dc08e 152
a7812ae4 153 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 154 offsetof(CPUState, nip), "nip");
155
a7812ae4 156 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 157 offsetof(CPUState, ctr), "ctr");
158
a7812ae4 159 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 160 offsetof(CPUState, lr), "lr");
161
a7812ae4 162 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 163 offsetof(CPUState, xer), "xer");
164
cf360a32
AJ		 165 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUState, reserve), "reserve");
167
a7812ae4
PB		 168 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
169 offsetof(CPUState, fpscr), "fpscr");
e1571908 170
a7859e89
AJ		 171 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
172 offsetof(CPUState, access_type), "access_type");
173
f10dc08e 174 /* register helpers */
a7812ae4 175#define GEN_HELPER 2
f10dc08e
AJ		 176#include "helper.h"
177
2e70f6ef
PB		 178 done_init = 1;
179}
180
7c58044c
JM		 181#if defined(OPTIMIZE_FPRF_UPDATE)
182static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
183static uint16_t **gen_fprf_ptr;
184#endif
79aceca5 185
79aceca5
FB		 186/* internal defines */
187typedef struct DisasContext {
188 struct TranslationBlock *tb;
0fa85d43 189 target_ulong nip;
79aceca5 190 uint32_t opcode;
9a64fbe4 191 uint32_t exception;
3cc62370
FB		 192 /* Routine used to access memory */
193 int mem_idx;
194 /* Translation flags */
9a64fbe4 195#if !defined(CONFIG_USER_ONLY)
79aceca5 196 int supervisor;
d9bce9d9
JM		 197#endif
198#if defined(TARGET_PPC64)
199 int sf_mode;
9a64fbe4 200#endif
3cc62370 201 int fpu_enabled;
a9d9eb8f 202 int altivec_enabled;
0487d6a8 203 int spe_enabled;
3fc6c082 204 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 205 int singlestep_enabled;
79aceca5
FB		 206} DisasContext;
207
3fc6c082 208struct opc_handler_t {
79aceca5
FB		 209 /* invalid bits */
210 uint32_t inval;
9a64fbe4 211 /* instruction type */
0487d6a8 212 uint64_t type;
79aceca5
FB		 213 /* handler */
214 void (*handler)(DisasContext *ctx);
a750fc0b 215#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 216 const char *oname;
a750fc0b
JM		 217#endif
218#if defined(DO_PPC_STATISTICS)
76a66253
JM		 219 uint64_t count;
220#endif
3fc6c082 221};
79aceca5 222
7c58044c
JM		 223static always_inline void gen_reset_fpstatus (void)
224{
225#ifdef CONFIG_SOFTFLOAT
226 gen_op_reset_fpstatus();
227#endif
228}
229
0f2f39c2 230static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 231{
0f2f39c2 232 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 233
7c58044c
JM		 234 if (set_fprf != 0) {
235 /* This case might be optimized later */
236#if defined(OPTIMIZE_FPRF_UPDATE)
237 *gen_fprf_ptr++ = gen_opc_ptr;
238#endif
0f2f39c2 239 tcg_gen_movi_i32(t0, 1);
af12906f 240 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 241 if (unlikely(set_rc)) {
0f2f39c2 242 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 243 }
af12906f 244 gen_helper_float_check_status();
7c58044c
JM		 245 } else if (unlikely(set_rc)) {
246 /* We always need to compute fpcc */
0f2f39c2 247 tcg_gen_movi_i32(t0, 0);
af12906f 248 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 249 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 250 if (set_fprf)
af12906f 251 gen_helper_float_check_status();
7c58044c 252 }
af12906f 253
0f2f39c2 254 tcg_temp_free_i32(t0);
7c58044c
JM		 255}
256
257static always_inline void gen_optimize_fprf (void)
258{
259#if defined(OPTIMIZE_FPRF_UPDATE)
260 uint16_t **ptr;
261
262 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
263 *ptr = INDEX_op_nop1;
264 gen_fprf_ptr = gen_fprf_buf;
265#endif
266}
267
a7859e89
AJ		 268static always_inline void gen_set_access_type(int access_type)
269{
270 tcg_gen_movi_i32(cpu_access_type, access_type);
271}
272
b068d6a7 273static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 274{
275#if defined(TARGET_PPC64)
276 if (ctx->sf_mode)
bd568f18 277 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 278 else
279#endif
bd568f18 280 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 281}
282
e1833e1f 283#define GEN_EXCP(ctx, excp, error) \
79aceca5 284do { \
64adab3f
AJ		 285 TCGv_i32 t0 = tcg_const_i32(excp); \
286 TCGv_i32 t1 = tcg_const_i32(error); \
e1833e1f 287 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 288 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c 289 } \
64adab3f
AJ		 290 gen_helper_raise_exception_err(t0, t1); \
291 tcg_temp_free_i32(t0); \
292 tcg_temp_free_i32(t1); \
9fddaa0c 293 ctx->exception = (excp); \
79aceca5
FB		 294} while (0)
295
e1833e1f
JM		 296#define GEN_EXCP_INVAL(ctx) \
297GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
298 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 299
e1833e1f
JM		 300#define GEN_EXCP_PRIVOPC(ctx) \
301GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
302 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 303
e1833e1f
JM		 304#define GEN_EXCP_PRIVREG(ctx) \
305GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
306 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
307
308#define GEN_EXCP_NO_FP(ctx) \
309GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
310
311#define GEN_EXCP_NO_AP(ctx) \
312GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 313
a9d9eb8f
JM		 314#define GEN_EXCP_NO_VR(ctx) \
315GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
316
f24e5695 317/* Stop translation */
b068d6a7 318static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 319{
d9bce9d9 320 gen_update_nip(ctx, ctx->nip);
e1833e1f 321 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 322}
323
f24e5695 324/* No need to update nip here, as execution flow will change */
b068d6a7 325static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 326{
e1833e1f 327 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 328}
329
79aceca5
FB		 330#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
331static void gen_##name (DisasContext *ctx); \
332GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
333static void gen_##name (DisasContext *ctx)
334
c7697e1f
JM		 335#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
336static void gen_##name (DisasContext *ctx); \
337GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
338static void gen_##name (DisasContext *ctx)
339
79aceca5
FB		 340typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
1235fc06 342#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 343 unsigned char pad[5];
344#else
345 unsigned char pad[1];
346#endif
79aceca5 347 opc_handler_t handler;
b55266b5 348 const char *oname;
79aceca5
FB		 349} opcode_t;
350
a750fc0b 351/*****************************************************************************/
79aceca5
FB		 352/*** Instruction decoding ***/
353#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 354static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 355{ \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357}
358
359#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 360static always_inline int32_t name (uint32_t opcode) \
79aceca5 361{ \
18fba28c 362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 363}
364
365/* Opcode part 1 */
366EXTRACT_HELPER(opc1, 26, 6);
367/* Opcode part 2 */
368EXTRACT_HELPER(opc2, 1, 5);
369/* Opcode part 3 */
370EXTRACT_HELPER(opc3, 6, 5);
371/* Update Cr0 flags */
372EXTRACT_HELPER(Rc, 0, 1);
373/* Destination */
374EXTRACT_HELPER(rD, 21, 5);
375/* Source */
376EXTRACT_HELPER(rS, 21, 5);
377/* First operand */
378EXTRACT_HELPER(rA, 16, 5);
379/* Second operand */
380EXTRACT_HELPER(rB, 11, 5);
381/* Third operand */
382EXTRACT_HELPER(rC, 6, 5);
383/*** Get CRn ***/
384EXTRACT_HELPER(crfD, 23, 3);
385EXTRACT_HELPER(crfS, 18, 3);
386EXTRACT_HELPER(crbD, 21, 5);
387EXTRACT_HELPER(crbA, 16, 5);
388EXTRACT_HELPER(crbB, 11, 5);
389/* SPR / TBL */
3fc6c082 390EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 391static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 392{
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396}
79aceca5
FB		 397/*** Get constants ***/
398EXTRACT_HELPER(IMM, 12, 8);
399/* 16 bits signed immediate value */
400EXTRACT_SHELPER(SIMM, 0, 16);
401/* 16 bits unsigned immediate value */
402EXTRACT_HELPER(UIMM, 0, 16);
403/* Bit count */
404EXTRACT_HELPER(NB, 11, 5);
405/* Shift count */
406EXTRACT_HELPER(SH, 11, 5);
407/* Mask start */
408EXTRACT_HELPER(MB, 6, 5);
409/* Mask end */
410EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 411/* Trap operand */
412EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 413
414EXTRACT_HELPER(CRM, 12, 8);
415EXTRACT_HELPER(FM, 17, 8);
416EXTRACT_HELPER(SR, 16, 4);
e4bb997e 417EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 418
79aceca5
FB		 419/*** Jump target decoding ***/
420/* Displacement */
421EXTRACT_SHELPER(d, 0, 16);
422/* Immediate address */
b068d6a7 423static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 424{
425 return (opcode >> 0) & 0x03FFFFFC;
426}
427
b068d6a7 428static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 429{
430 return (opcode >> 0) & 0xFFFC;
431}
432
433EXTRACT_HELPER(BO, 21, 5);
434EXTRACT_HELPER(BI, 16, 5);
435/* Absolute/relative address */
436EXTRACT_HELPER(AA, 1, 1);
437/* Link */
438EXTRACT_HELPER(LK, 0, 1);
439
440/* Create a mask between <start> and <end> bits */
b068d6a7 441static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 442{
76a66253 443 target_ulong ret;
79aceca5 444
76a66253
JM		 445#if defined(TARGET_PPC64)
446 if (likely(start == 0)) {
6f2d8978 447 ret = UINT64_MAX << (63 - end);
76a66253 448 } else if (likely(end == 63)) {
6f2d8978 449 ret = UINT64_MAX >> start;
76a66253
JM		 450 }
451#else
452 if (likely(start == 0)) {
6f2d8978 453 ret = UINT32_MAX << (31 - end);
76a66253 454 } else if (likely(end == 31)) {
6f2d8978 455 ret = UINT32_MAX >> start;
76a66253
JM		 456 }
457#endif
458 else {
459 ret = (((target_ulong)(-1ULL)) >> (start)) ^
460 (((target_ulong)(-1ULL) >> (end)) >> 1);
461 if (unlikely(start > end))
462 return ~ret;
463 }
79aceca5
FB		 464
465 return ret;
466}
467
a750fc0b
JM		 468/*****************************************************************************/
469/* PowerPC Instructions types definitions */
470enum {
1b413d55 471 PPC_NONE = 0x0000000000000000ULL,
12de9a39 472 /* PowerPC base instructions set */
1b413d55
JM		 473 PPC_INSNS_BASE = 0x0000000000000001ULL,
474 /* integer operations instructions */
a750fc0b 475#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 476 /* flow control instructions */
a750fc0b 477#define PPC_FLOW PPC_INSNS_BASE
1b413d55 478 /* virtual memory instructions */
a750fc0b 479#define PPC_MEM PPC_INSNS_BASE
1b413d55 480 /* ld/st with reservation instructions */
a750fc0b 481#define PPC_RES PPC_INSNS_BASE
1b413d55 482 /* spr/msr access instructions */
a750fc0b 483#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 484 /* Deprecated instruction sets */
485 /* Original POWER instruction set */
f610349f 486 PPC_POWER = 0x0000000000000002ULL,
1b413d55 487 /* POWER2 instruction set extension */
f610349f 488 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 489 /* Power RTC support */
f610349f 490 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 491 /* Power-to-PowerPC bridge (601) */
f610349f 492 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 493 /* 64 bits PowerPC instruction set */
f610349f 494 PPC_64B = 0x0000000000000020ULL,
1b413d55 495 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 496 PPC_64BX = 0x0000000000000040ULL,
1b413d55 497 /* 64 bits hypervisor extensions */
f610349f 498 PPC_64H = 0x0000000000000080ULL,
1b413d55 499 /* New wait instruction (PowerPC 2.0x) */
f610349f 500 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 501 /* Time base mftb instruction */
f610349f 502 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 503
504 /* Fixed-point unit extensions */
505 /* PowerPC 602 specific */
f610349f 506 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 507 /* isel instruction */
508 PPC_ISEL = 0x0000000000000800ULL,
509 /* popcntb instruction */
510 PPC_POPCNTB = 0x0000000000001000ULL,
511 /* string load / store */
512 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 513
514 /* Floating-point unit extensions */
515 /* Optional floating point instructions */
516 PPC_FLOAT = 0x0000000000010000ULL,
517 /* New floating-point extensions (PowerPC 2.0x) */
518 PPC_FLOAT_EXT = 0x0000000000020000ULL,
519 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
520 PPC_FLOAT_FRES = 0x0000000000080000ULL,
521 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
522 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
523 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
524 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
525
526 /* Vector/SIMD extensions */
527 /* Altivec support */
528 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 529 /* PowerPC 2.03 SPE extension */
05332d70 530 PPC_SPE = 0x0000000002000000ULL,
1b413d55 531 /* PowerPC 2.03 SPE floating-point extension */
05332d70 532 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 533
12de9a39 534 /* Optional memory control instructions */
1b413d55
JM		 535 PPC_MEM_TLBIA = 0x0000000010000000ULL,
536 PPC_MEM_TLBIE = 0x0000000020000000ULL,
537 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
538 /* sync instruction */
539 PPC_MEM_SYNC = 0x0000000080000000ULL,
540 /* eieio instruction */
541 PPC_MEM_EIEIO = 0x0000000100000000ULL,
542
543 /* Cache control instructions */
c8623f2e 544 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 545 /* icbi instruction */
05332d70 546 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 547 /* dcbz instruction with fixed cache line size */
05332d70 548 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 549 /* dcbz instruction with tunable cache line size */
05332d70 550 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 551 /* dcba instruction */
05332d70
JM		 552 PPC_CACHE_DCBA = 0x0000002000000000ULL,
553 /* Freescale cache locking instructions */
554 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 555
556 /* MMU related extensions */
557 /* external control instructions */
05332d70 558 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 559 /* segment register access instructions */
05332d70 560 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 561 /* PowerPC 6xx TLB management instructions */
05332d70 562 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 563 /* PowerPC 74xx TLB management instructions */
05332d70 564 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 565 /* PowerPC 40x TLB management instructions */
05332d70 566 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 567 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 568 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 569 /* SLB management */
05332d70 570 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 571
12de9a39 572 /* Embedded PowerPC dedicated instructions */
05332d70 573 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 574 /* PowerPC 40x exception model */
05332d70 575 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 576 /* PowerPC 405 Mac instructions */
05332d70 577 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 578 /* PowerPC 440 specific instructions */
05332d70 579 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 580 /* BookE (embedded) PowerPC specification */
05332d70
JM		 581 PPC_BOOKE = 0x0010000000000000ULL,
582 /* mfapidi instruction */
583 PPC_MFAPIDI = 0x0020000000000000ULL,
584 /* tlbiva instruction */
585 PPC_TLBIVA = 0x0040000000000000ULL,
586 /* tlbivax instruction */
587 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 588 /* PowerPC 4xx dedicated instructions */
05332d70 589 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 590 /* PowerPC 40x ibct instructions */
05332d70 591 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 592 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 593 PPC_RFMCI = 0x0400000000000000ULL,
594 /* rfdi instruction */
595 PPC_RFDI = 0x0800000000000000ULL,
596 /* DCR accesses */
597 PPC_DCR = 0x1000000000000000ULL,
598 /* DCR extended accesse */
599 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 600 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 601 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 602};
603
604/*****************************************************************************/
605/* PowerPC instructions table */
3fc6c082
FB		 606#if HOST_LONG_BITS == 64
607#define OPC_ALIGN 8
608#else
609#define OPC_ALIGN 4
610#endif
1b039c09 611#if defined(__APPLE__)
d9bce9d9 612#define OPCODES_SECTION \
3fc6c082 613 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 614#else
d9bce9d9 615#define OPCODES_SECTION \
3fc6c082 616 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 617#endif
618
76a66253 619#if defined(DO_PPC_STATISTICS)
79aceca5 620#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 621OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 622 .opc1 = op1, \
623 .opc2 = op2, \
624 .opc3 = op3, \
18fba28c 625 .pad = { 0, }, \
79aceca5
FB		 626 .handler = { \
627 .inval = invl, \
9a64fbe4 628 .type = _typ, \
79aceca5 629 .handler = &gen_##name, \
76a66253 630 .oname = stringify(name), \
79aceca5 631 }, \
3fc6c082 632 .oname = stringify(name), \
79aceca5 633}
c7697e1f
JM		 634#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
635OPCODES_SECTION opcode_t opc_##name = { \
636 .opc1 = op1, \
637 .opc2 = op2, \
638 .opc3 = op3, \
639 .pad = { 0, }, \
640 .handler = { \
641 .inval = invl, \
642 .type = _typ, \
643 .handler = &gen_##name, \
644 .oname = onam, \
645 }, \
646 .oname = onam, \
647}
76a66253
JM		 648#else
649#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
650OPCODES_SECTION opcode_t opc_##name = { \
651 .opc1 = op1, \
652 .opc2 = op2, \
653 .opc3 = op3, \
654 .pad = { 0, }, \
655 .handler = { \
656 .inval = invl, \
657 .type = _typ, \
658 .handler = &gen_##name, \
659 }, \
660 .oname = stringify(name), \
661}
c7697e1f
JM		 662#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
663OPCODES_SECTION opcode_t opc_##name = { \
664 .opc1 = op1, \
665 .opc2 = op2, \
666 .opc3 = op3, \
667 .pad = { 0, }, \
668 .handler = { \
669 .inval = invl, \
670 .type = _typ, \
671 .handler = &gen_##name, \
672 }, \
673 .oname = onam, \
674}
76a66253 675#endif
79aceca5
FB		 676
677#define GEN_OPCODE_MARK(name) \
18fba28c 678OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 679 .opc1 = 0xFF, \
680 .opc2 = 0xFF, \
681 .opc3 = 0xFF, \
18fba28c 682 .pad = { 0, }, \
79aceca5
FB		 683 .handler = { \
684 .inval = 0x00000000, \
9a64fbe4 685 .type = 0x00, \
79aceca5
FB		 686 .handler = NULL, \
687 }, \
3fc6c082 688 .oname = stringify(name), \
79aceca5
FB		 689}
690
691/* Start opcode list */
692GEN_OPCODE_MARK(start);
693
694/* Invalid instruction */
9a64fbe4
FB		 695GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
696{
e1833e1f 697 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 698}
699
79aceca5
FB		 700static opc_handler_t invalid_handler = {
701 .inval = 0xFFFFFFFF,
9a64fbe4 702 .type = PPC_NONE,
79aceca5
FB		 703 .handler = gen_invalid,
704};
705
e1571908
AJ		 706/*** Integer comparison ***/
707
ea363694 708static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 709{
710 int l1, l2, l3;
711
269f3e95
AJ		 712 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
713 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 714 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
715
716 l1 = gen_new_label();
717 l2 = gen_new_label();
718 l3 = gen_new_label();
719 if (s) {
ea363694
AJ		 720 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
721 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 722 } else {
ea363694
AJ		 723 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
724 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 725 }
726 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
727 tcg_gen_br(l3);
728 gen_set_label(l1);
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
730 tcg_gen_br(l3);
731 gen_set_label(l2);
732 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
733 gen_set_label(l3);
734}
735
ea363694 736static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 737{
ea363694
AJ		 738 TCGv t0 = tcg_const_local_tl(arg1);
739 gen_op_cmp(arg0, t0, s, crf);
740 tcg_temp_free(t0);
e1571908
AJ		 741}
742
743#if defined(TARGET_PPC64)
ea363694 744static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 745{
ea363694 746 TCGv t0, t1;
a7812ae4
PB		 747 t0 = tcg_temp_local_new();
748 t1 = tcg_temp_local_new();
e1571908 749 if (s) {
ea363694
AJ		 750 tcg_gen_ext32s_tl(t0, arg0);
751 tcg_gen_ext32s_tl(t1, arg1);
e1571908 752 } else {
ea363694
AJ		 753 tcg_gen_ext32u_tl(t0, arg0);
754 tcg_gen_ext32u_tl(t1, arg1);
e1571908 755 }
ea363694
AJ		 756 gen_op_cmp(t0, t1, s, crf);
757 tcg_temp_free(t1);
758 tcg_temp_free(t0);
e1571908
AJ		 759}
760
ea363694 761static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 762{
ea363694
AJ		 763 TCGv t0 = tcg_const_local_tl(arg1);
764 gen_op_cmp32(arg0, t0, s, crf);
765 tcg_temp_free(t0);
e1571908
AJ		 766}
767#endif
768
769static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
770{
771#if defined(TARGET_PPC64)
772 if (!(ctx->sf_mode))
773 gen_op_cmpi32(reg, 0, 1, 0);
774 else
775#endif
776 gen_op_cmpi(reg, 0, 1, 0);
777}
778
779/* cmp */
780GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
781{
782#if defined(TARGET_PPC64)
783 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
784 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
785 1, crfD(ctx->opcode));
786 else
787#endif
788 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
789 1, crfD(ctx->opcode));
790}
791
792/* cmpi */
793GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
794{
795#if defined(TARGET_PPC64)
796 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
797 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
798 1, crfD(ctx->opcode));
799 else
800#endif
801 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
802 1, crfD(ctx->opcode));
803}
804
805/* cmpl */
806GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
807{
808#if defined(TARGET_PPC64)
809 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
810 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
811 0, crfD(ctx->opcode));
812 else
813#endif
814 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
815 0, crfD(ctx->opcode));
816}
817
818/* cmpli */
819GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
820{
821#if defined(TARGET_PPC64)
822 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
823 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
824 0, crfD(ctx->opcode));
825 else
826#endif
827 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
828 0, crfD(ctx->opcode));
829}
830
831/* isel (PowerPC 2.03 specification) */
832GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
833{
834 int l1, l2;
835 uint32_t bi = rC(ctx->opcode);
836 uint32_t mask;
a7812ae4 837 TCGv_i32 t0;
e1571908
AJ		 838
839 l1 = gen_new_label();
840 l2 = gen_new_label();
841
842 mask = 1 << (3 - (bi & 0x03));
a7812ae4 843 t0 = tcg_temp_new_i32();
fea0c503
AJ		 844 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
845 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 846 if (rA(ctx->opcode) == 0)
847 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
848 else
849 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
850 tcg_gen_br(l2);
851 gen_set_label(l1);
852 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
853 gen_set_label(l2);
a7812ae4 854 tcg_temp_free_i32(t0);
e1571908
AJ		 855}
856
79aceca5 857/*** Integer arithmetic ***/
79aceca5 858
74637406
AJ		 859static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
860{
861 int l1;
862 TCGv t0;
79aceca5 863
74637406
AJ		 864 l1 = gen_new_label();
865 /* Start with XER OV disabled, the most likely case */
866 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 867 t0 = tcg_temp_local_new();
74637406
AJ		 868 tcg_gen_xor_tl(t0, arg0, arg1);
869#if defined(TARGET_PPC64)
870 if (!ctx->sf_mode)
871 tcg_gen_ext32s_tl(t0, t0);
872#endif
873 if (sub)
874 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
875 else
876 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
877 tcg_gen_xor_tl(t0, arg1, arg2);
878#if defined(TARGET_PPC64)
879 if (!ctx->sf_mode)
880 tcg_gen_ext32s_tl(t0, t0);
881#endif
882 if (sub)
883 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
884 else
885 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
886 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
887 gen_set_label(l1);
888 tcg_temp_free(t0);
79aceca5
FB		 889}
890
74637406
AJ		 891static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
892{
893 int l1 = gen_new_label();
d9bce9d9
JM		 894
895#if defined(TARGET_PPC64)
74637406
AJ		 896 if (!(ctx->sf_mode)) {
897 TCGv t0, t1;
a7812ae4
PB		 898 t0 = tcg_temp_new();
899 t1 = tcg_temp_new();
d9bce9d9 900
74637406
AJ		 901 tcg_gen_ext32u_tl(t0, arg1);
902 tcg_gen_ext32u_tl(t1, arg2);
903 if (sub) {
904 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 905 } else {
74637406
AJ		 906 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
907 }
a9730017
AJ		 908 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
909 gen_set_label(l1);
910 tcg_temp_free(t0);
911 tcg_temp_free(t1);
74637406
AJ		 912 } else
913#endif
a9730017
AJ		 914 {
915 if (sub) {
916 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
917 } else {
918 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
919 }
920 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
921 gen_set_label(l1);
74637406 922 }
d9bce9d9
JM		 923}
924
74637406
AJ		 925/* Common add function */
926static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
927 int add_ca, int compute_ca, int compute_ov)
928{
929 TCGv t0, t1;
d9bce9d9 930
74637406 931 if ((!compute_ca && !compute_ov) ||
a7812ae4 932 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 933 t0 = ret;
934 } else {
a7812ae4 935 t0 = tcg_temp_local_new();
74637406 936 }
79aceca5 937
74637406 938 if (add_ca) {
a7812ae4 939 t1 = tcg_temp_local_new();
74637406
AJ		 940 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
941 tcg_gen_shri_tl(t1, t1, XER_CA);
942 }
79aceca5 943
74637406
AJ		 944 if (compute_ca && compute_ov) {
945 /* Start with XER CA and OV disabled, the most likely case */
946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
947 } else if (compute_ca) {
948 /* Start with XER CA disabled, the most likely case */
949 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
950 } else if (compute_ov) {
951 /* Start with XER OV disabled, the most likely case */
952 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
953 }
79aceca5 954
74637406
AJ		 955 tcg_gen_add_tl(t0, arg1, arg2);
956
957 if (compute_ca) {
958 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
959 }
960 if (add_ca) {
961 tcg_gen_add_tl(t0, t0, t1);
962 gen_op_arith_compute_ca(ctx, t0, t1, 0);
963 tcg_temp_free(t1);
964 }
965 if (compute_ov) {
966 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
967 }
968
969 if (unlikely(Rc(ctx->opcode) != 0))
970 gen_set_Rc0(ctx, t0);
971
a7812ae4 972 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 973 tcg_gen_mov_tl(ret, t0);
974 tcg_temp_free(t0);
975 }
39dd32ee 976}
74637406
AJ		 977/* Add functions with two operands */
978#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
979GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
980{ \
981 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
982 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
983 add_ca, compute_ca, compute_ov); \
984}
985/* Add functions with one operand and one immediate */
986#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
987 add_ca, compute_ca, compute_ov) \
988GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
989{ \
990 TCGv t0 = tcg_const_local_tl(const_val); \
991 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
992 cpu_gpr[rA(ctx->opcode)], t0, \
993 add_ca, compute_ca, compute_ov); \
994 tcg_temp_free(t0); \
995}
996
997/* add add. addo addo. */
998GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
999GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1000/* addc addc. addco addco. */
1001GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1002GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1003/* adde adde. addeo addeo. */
1004GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1005GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1006/* addme addme. addmeo addmeo. */
1007GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1008GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1009/* addze addze. addzeo addzeo.*/
1010GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1011GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1012/* addi */
1013GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1014{
74637406
AJ		 1015 target_long simm = SIMM(ctx->opcode);
1016
1017 if (rA(ctx->opcode) == 0) {
1018 /* li case */
1019 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1020 } else {
1021 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1022 }
d9bce9d9 1023}
74637406
AJ		 1024/* addic addic.*/
1025static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1026 int compute_Rc0)
d9bce9d9 1027{
74637406
AJ		 1028 target_long simm = SIMM(ctx->opcode);
1029
1030 /* Start with XER CA and OV disabled, the most likely case */
1031 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1032
1033 if (likely(simm != 0)) {
a7812ae4 1034 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1035 tcg_gen_addi_tl(t0, arg1, simm);
1036 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1037 tcg_gen_mov_tl(ret, t0);
1038 tcg_temp_free(t0);
1039 } else {
1040 tcg_gen_mov_tl(ret, arg1);
1041 }
1042 if (compute_Rc0) {
1043 gen_set_Rc0(ctx, ret);
1044 }
d9bce9d9 1045}
74637406 1046GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1047{
74637406 1048 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1049}
74637406 1050GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1051{
74637406 1052 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1053}
74637406
AJ		 1054/* addis */
1055GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1056{
74637406
AJ		 1057 target_long simm = SIMM(ctx->opcode);
1058
1059 if (rA(ctx->opcode) == 0) {
1060 /* lis case */
1061 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1062 } else {
1063 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1064 }
d9bce9d9 1065}
74637406
AJ		 1066
1067static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1068 int sign, int compute_ov)
d9bce9d9 1069{
2ef1b120
AJ		 1070 int l1 = gen_new_label();
1071 int l2 = gen_new_label();
a7812ae4
PB		 1072 TCGv_i32 t0 = tcg_temp_local_new_i32();
1073 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1074
2ef1b120
AJ		 1075 tcg_gen_trunc_tl_i32(t0, arg1);
1076 tcg_gen_trunc_tl_i32(t1, arg2);
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1078 if (sign) {
2ef1b120
AJ		 1079 int l3 = gen_new_label();
1080 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1081 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1082 gen_set_label(l3);
2ef1b120 1083 tcg_gen_div_i32(t0, t0, t1);
74637406 1084 } else {
2ef1b120 1085 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1086 }
1087 if (compute_ov) {
1088 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1089 }
1090 tcg_gen_br(l2);
1091 gen_set_label(l1);
1092 if (sign) {
2ef1b120 1093 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1094 } else {
1095 tcg_gen_movi_i32(t0, 0);
1096 }
1097 if (compute_ov) {
1098 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1099 }
1100 gen_set_label(l2);
2ef1b120 1101 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1102 tcg_temp_free_i32(t0);
1103 tcg_temp_free_i32(t1);
74637406
AJ		 1104 if (unlikely(Rc(ctx->opcode) != 0))
1105 gen_set_Rc0(ctx, ret);
d9bce9d9 1106}
74637406
AJ		 1107/* Div functions */
1108#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1109GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1110{ \
1111 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1112 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1113 sign, compute_ov); \
1114}
1115/* divwu divwu. divwuo divwuo. */
1116GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1117GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1118/* divw divw. divwo divwo. */
1119GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1120GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1121#if defined(TARGET_PPC64)
2ef1b120
AJ		 1122static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1123 int sign, int compute_ov)
d9bce9d9 1124{
2ef1b120
AJ		 1125 int l1 = gen_new_label();
1126 int l2 = gen_new_label();
74637406
AJ		 1127
1128 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1129 if (sign) {
2ef1b120 1130 int l3 = gen_new_label();
74637406
AJ		 1131 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1132 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1133 gen_set_label(l3);
74637406
AJ		 1134 tcg_gen_div_i64(ret, arg1, arg2);
1135 } else {
1136 tcg_gen_divu_i64(ret, arg1, arg2);
1137 }
1138 if (compute_ov) {
1139 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1140 }
1141 tcg_gen_br(l2);
1142 gen_set_label(l1);
1143 if (sign) {
1144 tcg_gen_sari_i64(ret, arg1, 63);
1145 } else {
1146 tcg_gen_movi_i64(ret, 0);
1147 }
1148 if (compute_ov) {
1149 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1150 }
1151 gen_set_label(l2);
1152 if (unlikely(Rc(ctx->opcode) != 0))
1153 gen_set_Rc0(ctx, ret);
d9bce9d9 1154}
74637406
AJ		 1155#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1156GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1157{ \
2ef1b120
AJ		 1158 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1159 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1160 sign, compute_ov); \
74637406
AJ		 1161}
1162/* divwu divwu. divwuo divwuo. */
1163GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1164GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1165/* divw divw. divwo divwo. */
1166GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1167GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1168#endif
74637406
AJ		 1169
1170/* mulhw mulhw. */
1171GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1172{
a7812ae4 1173 TCGv_i64 t0, t1;
74637406 1174
a7812ae4
PB		 1175 t0 = tcg_temp_new_i64();
1176 t1 = tcg_temp_new_i64();
74637406
AJ		 1177#if defined(TARGET_PPC64)
1178 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1179 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1180 tcg_gen_mul_i64(t0, t0, t1);
1181 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1182#else
1183 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1184 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1185 tcg_gen_mul_i64(t0, t0, t1);
1186 tcg_gen_shri_i64(t0, t0, 32);
1187 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1188#endif
a7812ae4
PB		 1189 tcg_temp_free_i64(t0);
1190 tcg_temp_free_i64(t1);
74637406
AJ		 1191 if (unlikely(Rc(ctx->opcode) != 0))
1192 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1193}
74637406
AJ		 1194/* mulhwu mulhwu. */
1195GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1196{
a7812ae4 1197 TCGv_i64 t0, t1;
74637406 1198
a7812ae4
PB		 1199 t0 = tcg_temp_new_i64();
1200 t1 = tcg_temp_new_i64();
d9bce9d9 1201#if defined(TARGET_PPC64)
74637406
AJ		 1202 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1203 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1204 tcg_gen_mul_i64(t0, t0, t1);
1205 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1206#else
1207 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1208 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1209 tcg_gen_mul_i64(t0, t0, t1);
1210 tcg_gen_shri_i64(t0, t0, 32);
1211 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1212#endif
a7812ae4
PB		 1213 tcg_temp_free_i64(t0);
1214 tcg_temp_free_i64(t1);
74637406
AJ		 1215 if (unlikely(Rc(ctx->opcode) != 0))
1216 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1217}
74637406
AJ		 1218/* mullw mullw. */
1219GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1220{
74637406
AJ		 1221 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1222 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1223 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1224 if (unlikely(Rc(ctx->opcode) != 0))
1225 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1226}
74637406
AJ		 1227/* mullwo mullwo. */
1228GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1229{
74637406 1230 int l1;
a7812ae4 1231 TCGv_i64 t0, t1;
74637406 1232
a7812ae4
PB		 1233 t0 = tcg_temp_new_i64();
1234 t1 = tcg_temp_new_i64();
74637406
AJ		 1235 l1 = gen_new_label();
1236 /* Start with XER OV disabled, the most likely case */
1237 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1238#if defined(TARGET_PPC64)
1239 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1240 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1241#else
1242 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1243 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1244#endif
74637406
AJ		 1245 tcg_gen_mul_i64(t0, t0, t1);
1246#if defined(TARGET_PPC64)
1247 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1248 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1249#else
1250 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1251 tcg_gen_ext32s_i64(t1, t0);
1252 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1253#endif
1254 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1255 gen_set_label(l1);
a7812ae4
PB		 1256 tcg_temp_free_i64(t0);
1257 tcg_temp_free_i64(t1);
74637406
AJ		 1258 if (unlikely(Rc(ctx->opcode) != 0))
1259 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1260}
74637406
AJ		 1261/* mulli */
1262GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1263{
74637406
AJ		 1264 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1265 SIMM(ctx->opcode));
d9bce9d9
JM		 1266}
1267#if defined(TARGET_PPC64)
74637406
AJ		 1268#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1269GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1270{ \
a7812ae4 1271 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1272 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1273 if (unlikely(Rc(ctx->opcode) != 0)) \
1274 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1275}
74637406
AJ		 1276/* mulhd mulhd. */
1277GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1278/* mulhdu mulhdu. */
1279GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1280/* mulld mulld. */
1281GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1282{
74637406
AJ		 1283 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1284 cpu_gpr[rB(ctx->opcode)]);
1285 if (unlikely(Rc(ctx->opcode) != 0))
1286 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1287}
74637406
AJ		 1288/* mulldo mulldo. */
1289GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1290#endif
74637406
AJ		 1291
1292/* neg neg. nego nego. */
ec6469a3 1293static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1294{
ec6469a3
AJ		 1295 int l1 = gen_new_label();
1296 int l2 = gen_new_label();
a7812ae4 1297 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1298#if defined(TARGET_PPC64)
74637406 1299 if (ctx->sf_mode) {
741a7444 1300 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1301 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1302 } else
1303#endif
1304 {
1305 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1306 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1307 }
74637406
AJ		 1308 tcg_gen_neg_tl(ret, arg1);
1309 if (ov_check) {
1310 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1311 }
1312 tcg_gen_br(l2);
1313 gen_set_label(l1);
ec6469a3 1314 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1315 if (ov_check) {
1316 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1317 }
1318 gen_set_label(l2);
ec6469a3 1319 tcg_temp_free(t0);
74637406
AJ		 1320 if (unlikely(Rc(ctx->opcode) != 0))
1321 gen_set_Rc0(ctx, ret);
1322}
1323GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1324{
ec6469a3 1325 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1326}
74637406 1327GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1328{
ec6469a3 1329 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1330}
74637406
AJ		 1331
1332/* Common subf function */
1333static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1334 int add_ca, int compute_ca, int compute_ov)
79aceca5 1335{
74637406 1336 TCGv t0, t1;
76a66253 1337
74637406 1338 if ((!compute_ca && !compute_ov) ||
a7812ae4 1339 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1340 t0 = ret;
e864cabd 1341 } else {
a7812ae4 1342 t0 = tcg_temp_local_new();
d9bce9d9 1343 }
76a66253 1344
74637406 1345 if (add_ca) {
a7812ae4 1346 t1 = tcg_temp_local_new();
74637406
AJ		 1347 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1348 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1349 }
79aceca5 1350
74637406
AJ		 1351 if (compute_ca && compute_ov) {
1352 /* Start with XER CA and OV disabled, the most likely case */
1353 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1354 } else if (compute_ca) {
1355 /* Start with XER CA disabled, the most likely case */
1356 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1357 } else if (compute_ov) {
1358 /* Start with XER OV disabled, the most likely case */
1359 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1360 }
1361
1362 if (add_ca) {
1363 tcg_gen_not_tl(t0, arg1);
1364 tcg_gen_add_tl(t0, t0, arg2);
1365 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1366 tcg_gen_add_tl(t0, t0, t1);
1367 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1368 tcg_temp_free(t1);
79aceca5 1369 } else {
74637406
AJ		 1370 tcg_gen_sub_tl(t0, arg2, arg1);
1371 if (compute_ca) {
1372 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1373 }
1374 }
1375 if (compute_ov) {
1376 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1377 }
1378
1379 if (unlikely(Rc(ctx->opcode) != 0))
1380 gen_set_Rc0(ctx, t0);
1381
a7812ae4 1382 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1383 tcg_gen_mov_tl(ret, t0);
1384 tcg_temp_free(t0);
79aceca5 1385 }
79aceca5 1386}
74637406
AJ		 1387/* Sub functions with Two operands functions */
1388#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1389GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1390{ \
1391 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1392 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1393 add_ca, compute_ca, compute_ov); \
1394}
1395/* Sub functions with one operand and one immediate */
1396#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1397 add_ca, compute_ca, compute_ov) \
1398GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1399{ \
1400 TCGv t0 = tcg_const_local_tl(const_val); \
1401 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1402 cpu_gpr[rA(ctx->opcode)], t0, \
1403 add_ca, compute_ca, compute_ov); \
1404 tcg_temp_free(t0); \
1405}
1406/* subf subf. subfo subfo. */
1407GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1408GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1409/* subfc subfc. subfco subfco. */
1410GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1411GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1412/* subfe subfe. subfeo subfo. */
1413GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1414GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1415/* subfme subfme. subfmeo subfmeo. */
1416GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1417GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1418/* subfze subfze. subfzeo subfzeo.*/
1419GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1420GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1421/* subfic */
1422GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1423{
74637406
AJ		 1424 /* Start with XER CA and OV disabled, the most likely case */
1425 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1426 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1427 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1428 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1429 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1430 tcg_temp_free(t1);
1431 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1432 tcg_temp_free(t0);
79aceca5
FB		 1433}
1434
79aceca5 1435/*** Integer logical ***/
26d67362
AJ		 1436#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1437GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1438{ \
26d67362
AJ		 1439 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1440 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1441 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1442 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1443}
79aceca5 1444
26d67362 1445#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1446GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1447{ \
26d67362 1448 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1449 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1450 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1451}
1452
1453/* and & and. */
26d67362 1454GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1455/* andc & andc. */
26d67362 1456GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1457/* andi. */
c7697e1f 1458GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1459{
26d67362
AJ		 1460 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1462}
1463/* andis. */
c7697e1f 1464GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1465{
26d67362
AJ		 1466 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1467 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1468}
79aceca5 1469/* cntlzw */
26d67362
AJ		 1470GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1471{
a7812ae4 1472 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1473 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1474 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1475}
79aceca5 1476/* eqv & eqv. */
26d67362 1477GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1478/* extsb & extsb. */
26d67362 1479GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1480/* extsh & extsh. */
26d67362 1481GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1482/* nand & nand. */
26d67362 1483GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1484/* nor & nor. */
26d67362 1485GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1486/* or & or. */
9a64fbe4
FB		 1487GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1488{
76a66253
JM		 1489 int rs, ra, rb;
1490
1491 rs = rS(ctx->opcode);
1492 ra = rA(ctx->opcode);
1493 rb = rB(ctx->opcode);
1494 /* Optimisation for mr. ri case */
1495 if (rs != ra || rs != rb) {
26d67362
AJ		 1496 if (rs != rb)
1497 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1498 else
1499 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1500 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1501 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1502 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1503 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1504#if defined(TARGET_PPC64)
1505 } else {
26d67362
AJ		 1506 int prio = 0;
1507
c80f84e3
JM		 1508 switch (rs) {
1509 case 1:
1510 /* Set process priority to low */
26d67362 1511 prio = 2;
c80f84e3
JM		 1512 break;
1513 case 6:
1514 /* Set process priority to medium-low */
26d67362 1515 prio = 3;
c80f84e3
JM		 1516 break;
1517 case 2:
1518 /* Set process priority to normal */
26d67362 1519 prio = 4;
c80f84e3 1520 break;
be147d08
JM		 1521#if !defined(CONFIG_USER_ONLY)
1522 case 31:
1523 if (ctx->supervisor > 0) {
1524 /* Set process priority to very low */
26d67362 1525 prio = 1;
be147d08
JM		 1526 }
1527 break;
1528 case 5:
1529 if (ctx->supervisor > 0) {
1530 /* Set process priority to medium-hight */
26d67362 1531 prio = 5;
be147d08
JM		 1532 }
1533 break;
1534 case 3:
1535 if (ctx->supervisor > 0) {
1536 /* Set process priority to high */
26d67362 1537 prio = 6;
be147d08
JM		 1538 }
1539 break;
be147d08
JM		 1540 case 7:
1541 if (ctx->supervisor > 1) {
1542 /* Set process priority to very high */
26d67362 1543 prio = 7;
be147d08
JM		 1544 }
1545 break;
be147d08 1546#endif
c80f84e3
JM		 1547 default:
1548 /* nop */
1549 break;
1550 }
26d67362 1551 if (prio) {
a7812ae4 1552 TCGv t0 = tcg_temp_new();
ea363694
AJ		 1553 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1554 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1555 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1556 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1557 tcg_temp_free(t0);
26d67362 1558 }
c80f84e3 1559#endif
9a64fbe4 1560 }
9a64fbe4 1561}
79aceca5 1562/* orc & orc. */
26d67362 1563GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1564/* xor & xor. */
9a64fbe4
FB		 1565GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1566{
9a64fbe4 1567 /* Optimisation for "set to zero" case */
26d67362 1568 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1569 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1570 else
1571 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1572 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1573 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1574}
79aceca5
FB		 1575/* ori */
1576GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1577{
76a66253 1578 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1579
9a64fbe4
FB		 1580 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1581 /* NOP */
76a66253 1582 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1583 return;
76a66253 1584 }
26d67362 1585 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1586}
1587/* oris */
1588GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1589{
76a66253 1590 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1591
9a64fbe4
FB		 1592 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1593 /* NOP */
1594 return;
76a66253 1595 }
26d67362 1596 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1597}
1598/* xori */
1599GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1600{
76a66253 1601 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1602
1603 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1604 /* NOP */
1605 return;
1606 }
26d67362 1607 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1608}
79aceca5
FB		 1609/* xoris */
1610GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1611{
76a66253 1612 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1613
1614 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1615 /* NOP */
1616 return;
1617 }
26d67362 1618 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1619}
d9bce9d9 1620/* popcntb : PowerPC 2.03 specification */
05332d70 1621GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1622{
d9bce9d9
JM		 1623#if defined(TARGET_PPC64)
1624 if (ctx->sf_mode)
a7812ae4 1625 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1626 else
1627#endif
a7812ae4 1628 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1629}
1630
1631#if defined(TARGET_PPC64)
1632/* extsw & extsw. */
26d67362 1633GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1634/* cntlzd */
26d67362
AJ		 1635GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1636{
a7812ae4 1637 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1638 if (unlikely(Rc(ctx->opcode) != 0))
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640}
d9bce9d9
JM		 1641#endif
1642
79aceca5
FB		 1643/*** Integer rotate ***/
1644/* rlwimi & rlwimi. */
1645GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1646{
76a66253 1647 uint32_t mb, me, sh;
79aceca5
FB		 1648
1649 mb = MB(ctx->opcode);
1650 me = ME(ctx->opcode);
76a66253 1651 sh = SH(ctx->opcode);
d03ef511
AJ		 1652 if (likely(sh == 0 && mb == 0 && me == 31)) {
1653 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1654 } else {
d03ef511 1655 target_ulong mask;
a7812ae4
PB		 1656 TCGv t1;
1657 TCGv t0 = tcg_temp_new();
54843a58 1658#if defined(TARGET_PPC64)
a7812ae4
PB		 1659 TCGv_i32 t2 = tcg_temp_new_i32();
1660 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1661 tcg_gen_rotli_i32(t2, t2, sh);
1662 tcg_gen_extu_i32_i64(t0, t2);
1663 tcg_temp_free_i32(t2);
54843a58
AJ		 1664#else
1665 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1666#endif
76a66253 1667#if defined(TARGET_PPC64)
d03ef511
AJ		 1668 mb += 32;
1669 me += 32;
76a66253 1670#endif
d03ef511 1671 mask = MASK(mb, me);
a7812ae4 1672 t1 = tcg_temp_new();
d03ef511
AJ		 1673 tcg_gen_andi_tl(t0, t0, mask);
1674 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1675 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1676 tcg_temp_free(t0);
1677 tcg_temp_free(t1);
1678 }
76a66253 1679 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1680 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1681}
1682/* rlwinm & rlwinm. */
1683GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1684{
1685 uint32_t mb, me, sh;
3b46e624 1686
79aceca5
FB		 1687 sh = SH(ctx->opcode);
1688 mb = MB(ctx->opcode);
1689 me = ME(ctx->opcode);
d03ef511
AJ		 1690
1691 if (likely(mb == 0 && me == (31 - sh))) {
1692 if (likely(sh == 0)) {
1693 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1694 } else {
a7812ae4 1695 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1696 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1697 tcg_gen_shli_tl(t0, t0, sh);
1698 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1699 tcg_temp_free(t0);
79aceca5 1700 }
d03ef511 1701 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1702 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1703 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1704 tcg_gen_shri_tl(t0, t0, mb);
1705 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1706 tcg_temp_free(t0);
1707 } else {
a7812ae4 1708 TCGv t0 = tcg_temp_new();
54843a58 1709#if defined(TARGET_PPC64)
a7812ae4 1710 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1711 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1712 tcg_gen_rotli_i32(t1, t1, sh);
1713 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1714 tcg_temp_free_i32(t1);
54843a58
AJ		 1715#else
1716 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1717#endif
76a66253 1718#if defined(TARGET_PPC64)
d03ef511
AJ		 1719 mb += 32;
1720 me += 32;
76a66253 1721#endif
d03ef511
AJ		 1722 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1723 tcg_temp_free(t0);
1724 }
76a66253 1725 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1726 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1727}
1728/* rlwnm & rlwnm. */
1729GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1730{
1731 uint32_t mb, me;
54843a58
AJ		 1732 TCGv t0;
1733#if defined(TARGET_PPC64)
a7812ae4 1734 TCGv_i32 t1, t2;
54843a58 1735#endif
79aceca5
FB		 1736
1737 mb = MB(ctx->opcode);
1738 me = ME(ctx->opcode);
a7812ae4 1739 t0 = tcg_temp_new();
d03ef511 1740 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1741#if defined(TARGET_PPC64)
a7812ae4
PB		 1742 t1 = tcg_temp_new_i32();
1743 t2 = tcg_temp_new_i32();
54843a58
AJ		 1744 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1745 tcg_gen_trunc_i64_i32(t2, t0);
1746 tcg_gen_rotl_i32(t1, t1, t2);
1747 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1748 tcg_temp_free_i32(t1);
1749 tcg_temp_free_i32(t2);
54843a58
AJ		 1750#else
1751 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1752#endif
76a66253
JM		 1753 if (unlikely(mb != 0 || me != 31)) {
1754#if defined(TARGET_PPC64)
1755 mb += 32;
1756 me += 32;
1757#endif
54843a58 1758 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1759 } else {
54843a58 1760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1761 }
54843a58 1762 tcg_temp_free(t0);
76a66253 1763 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1765}
1766
d9bce9d9
JM		 1767#if defined(TARGET_PPC64)
1768#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1769GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1770{ \
1771 gen_##name(ctx, 0); \
1772} \
c7697e1f
JM		 1773GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1774 PPC_64B) \
d9bce9d9
JM		 1775{ \
1776 gen_##name(ctx, 1); \
1777}
1778#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1779GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1780{ \
1781 gen_##name(ctx, 0, 0); \
1782} \
c7697e1f
JM		 1783GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1784 PPC_64B) \
d9bce9d9
JM		 1785{ \
1786 gen_##name(ctx, 0, 1); \
1787} \
c7697e1f
JM		 1788GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1789 PPC_64B) \
d9bce9d9
JM		 1790{ \
1791 gen_##name(ctx, 1, 0); \
1792} \
c7697e1f
JM		 1793GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1794 PPC_64B) \
d9bce9d9
JM		 1795{ \
1796 gen_##name(ctx, 1, 1); \
1797}
51789c41 1798
b068d6a7
JM		 1799static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1800 uint32_t me, uint32_t sh)
51789c41 1801{
d03ef511
AJ		 1802 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1803 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1804 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1805 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1806 } else {
a7812ae4 1807 TCGv t0 = tcg_temp_new();
54843a58 1808 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1809 if (likely(mb == 0 && me == 63)) {
54843a58 1810 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1811 } else {
1812 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1813 }
d03ef511 1814 tcg_temp_free(t0);
51789c41 1815 }
51789c41 1816 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1817 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1818}
d9bce9d9 1819/* rldicl - rldicl. */
b068d6a7 1820static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1821{
51789c41 1822 uint32_t sh, mb;
d9bce9d9 1823
9d53c753
JM		 1824 sh = SH(ctx->opcode) | (shn << 5);
1825 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1826 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1827}
51789c41 1828GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1829/* rldicr - rldicr. */
b068d6a7 1830static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1831{
51789c41 1832 uint32_t sh, me;
d9bce9d9 1833
9d53c753
JM		 1834 sh = SH(ctx->opcode) | (shn << 5);
1835 me = MB(ctx->opcode) | (men << 5);
51789c41 1836 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1837}
51789c41 1838GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1839/* rldic - rldic. */
b068d6a7 1840static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1841{
51789c41 1842 uint32_t sh, mb;
d9bce9d9 1843
9d53c753
JM		 1844 sh = SH(ctx->opcode) | (shn << 5);
1845 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1846 gen_rldinm(ctx, mb, 63 - sh, sh);
1847}
1848GEN_PPC64_R4(rldic, 0x1E, 0x04);
1849
b068d6a7
JM		 1850static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1851 uint32_t me)
51789c41 1852{
54843a58 1853 TCGv t0;
d03ef511
AJ		 1854
1855 mb = MB(ctx->opcode);
1856 me = ME(ctx->opcode);
a7812ae4 1857 t0 = tcg_temp_new();
d03ef511 1858 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1859 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1860 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1861 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1862 } else {
1863 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1864 }
1865 tcg_temp_free(t0);
51789c41 1866 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1867 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1868}
51789c41 1869
d9bce9d9 1870/* rldcl - rldcl. */
b068d6a7 1871static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1872{
51789c41 1873 uint32_t mb;
d9bce9d9 1874
9d53c753 1875 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1876 gen_rldnm(ctx, mb, 63);
d9bce9d9 1877}
36081602 1878GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1879/* rldcr - rldcr. */
b068d6a7 1880static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1881{
51789c41 1882 uint32_t me;
d9bce9d9 1883
9d53c753 1884 me = MB(ctx->opcode) | (men << 5);
51789c41 1885 gen_rldnm(ctx, 0, me);
d9bce9d9 1886}
36081602 1887GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1888/* rldimi - rldimi. */
b068d6a7 1889static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1890{
271a916e 1891 uint32_t sh, mb, me;
d9bce9d9 1892
9d53c753
JM		 1893 sh = SH(ctx->opcode) | (shn << 5);
1894 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1895 me = 63 - sh;
d03ef511
AJ		 1896 if (unlikely(sh == 0 && mb == 0)) {
1897 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1898 } else {
1899 TCGv t0, t1;
1900 target_ulong mask;
1901
a7812ae4 1902 t0 = tcg_temp_new();
54843a58 1903 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1904 t1 = tcg_temp_new();
d03ef511
AJ		 1905 mask = MASK(mb, me);
1906 tcg_gen_andi_tl(t0, t0, mask);
1907 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1908 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1909 tcg_temp_free(t0);
1910 tcg_temp_free(t1);
51789c41 1911 }
51789c41 1912 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1914}
36081602 1915GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1916#endif
1917
79aceca5
FB		 1918/*** Integer shift ***/
1919/* slw & slw. */
26d67362
AJ		 1920GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1921{
fea0c503 1922 TCGv t0;
26d67362
AJ		 1923 int l1, l2;
1924 l1 = gen_new_label();
1925 l2 = gen_new_label();
1926
a7812ae4 1927 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1928 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1929 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1930 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1931 tcg_gen_br(l2);
1932 gen_set_label(l1);
fea0c503 1933 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1934 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1935 gen_set_label(l2);
fea0c503 1936 tcg_temp_free(t0);
26d67362
AJ		 1937 if (unlikely(Rc(ctx->opcode) != 0))
1938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1939}
79aceca5 1940/* sraw & sraw. */
26d67362
AJ		 1941GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1942{
a7812ae4
PB		 1943 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1944 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1945 if (unlikely(Rc(ctx->opcode) != 0))
1946 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1947}
79aceca5
FB		 1948/* srawi & srawi. */
1949GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1950{
26d67362
AJ		 1951 int sh = SH(ctx->opcode);
1952 if (sh != 0) {
1953 int l1, l2;
fea0c503 1954 TCGv t0;
26d67362
AJ		 1955 l1 = gen_new_label();
1956 l2 = gen_new_label();
a7812ae4 1957 t0 = tcg_temp_local_new();
fea0c503
AJ		 1958 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1959 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1960 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1961 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1962 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1963 tcg_gen_br(l2);
1964 gen_set_label(l1);
269f3e95 1965 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1966 gen_set_label(l2);
fea0c503
AJ		 1967 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1968 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1969 tcg_temp_free(t0);
26d67362
AJ		 1970 } else {
1971 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1972 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1973 }
76a66253 1974 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1975 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1976}
1977/* srw & srw. */
26d67362
AJ		 1978GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1979{
fea0c503 1980 TCGv t0, t1;
26d67362
AJ		 1981 int l1, l2;
1982 l1 = gen_new_label();
1983 l2 = gen_new_label();
d9bce9d9 1984
a7812ae4 1985 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1986 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1987 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1988 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1989 tcg_gen_br(l2);
1990 gen_set_label(l1);
a7812ae4 1991 t1 = tcg_temp_new();
fea0c503
AJ		 1992 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1993 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1994 tcg_temp_free(t1);
26d67362 1995 gen_set_label(l2);
fea0c503 1996 tcg_temp_free(t0);
26d67362
AJ		 1997 if (unlikely(Rc(ctx->opcode) != 0))
1998 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1999}
d9bce9d9
JM		 2000#if defined(TARGET_PPC64)
2001/* sld & sld. */
26d67362
AJ		 2002GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2003{
fea0c503 2004 TCGv t0;
26d67362
AJ		 2005 int l1, l2;
2006 l1 = gen_new_label();
2007 l2 = gen_new_label();
2008
a7812ae4 2009 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2010 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2011 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2012 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2013 tcg_gen_br(l2);
2014 gen_set_label(l1);
fea0c503 2015 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2016 gen_set_label(l2);
fea0c503 2017 tcg_temp_free(t0);
26d67362
AJ		 2018 if (unlikely(Rc(ctx->opcode) != 0))
2019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2020}
d9bce9d9 2021/* srad & srad. */
26d67362
AJ		 2022GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2023{
a7812ae4
PB		 2024 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2025 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2026 if (unlikely(Rc(ctx->opcode) != 0))
2027 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2028}
d9bce9d9 2029/* sradi & sradi. */
b068d6a7 2030static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2031{
26d67362 2032 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2033 if (sh != 0) {
26d67362 2034 int l1, l2;
fea0c503 2035 TCGv t0;
26d67362
AJ		 2036 l1 = gen_new_label();
2037 l2 = gen_new_label();
a7812ae4 2038 t0 = tcg_temp_local_new();
26d67362 2039 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2040 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2041 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2042 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2043 tcg_gen_br(l2);
2044 gen_set_label(l1);
269f3e95 2045 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2046 gen_set_label(l2);
a9730017 2047 tcg_temp_free(t0);
26d67362
AJ		 2048 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2049 } else {
2050 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2051 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2052 }
d9bce9d9 2053 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2054 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2055}
c7697e1f 2056GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2057{
2058 gen_sradi(ctx, 0);
2059}
c7697e1f 2060GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2061{
2062 gen_sradi(ctx, 1);
2063}
2064/* srd & srd. */
26d67362
AJ		 2065GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2066{
fea0c503 2067 TCGv t0;
26d67362
AJ		 2068 int l1, l2;
2069 l1 = gen_new_label();
2070 l2 = gen_new_label();
2071
a7812ae4 2072 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2073 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2074 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2075 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2076 tcg_gen_br(l2);
2077 gen_set_label(l1);
fea0c503 2078 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2079 gen_set_label(l2);
fea0c503 2080 tcg_temp_free(t0);
26d67362
AJ		 2081 if (unlikely(Rc(ctx->opcode) != 0))
2082 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2083}
d9bce9d9 2084#endif
79aceca5
FB		 2085
2086/*** Floating-Point arithmetic ***/
7c58044c 2087#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2088GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2089{ \
76a66253 2090 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2091 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2092 return; \
2093 } \
7c58044c 2094 gen_reset_fpstatus(); \
af12906f
AJ		 2095 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2096 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2097 if (isfloat) { \
af12906f 2098 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2099 } \
af12906f
AJ		 2100 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2101 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2102}
2103
7c58044c
JM		 2104#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2105_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2106_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2107
7c58044c
JM		 2108#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2109GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2110{ \
76a66253 2111 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2112 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2113 return; \
2114 } \
7c58044c 2115 gen_reset_fpstatus(); \
af12906f
AJ		 2116 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2117 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2118 if (isfloat) { \
af12906f 2119 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2120 } \
af12906f
AJ		 2121 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2122 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2123}
7c58044c
JM		 2124#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2125_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2126_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2127
7c58044c
JM		 2128#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2129GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2130{ \
76a66253 2131 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2132 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2133 return; \
2134 } \
7c58044c 2135 gen_reset_fpstatus(); \
af12906f
AJ		 2136 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2137 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2138 if (isfloat) { \
af12906f 2139 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2140 } \
af12906f
AJ		 2141 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2142 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2143}
7c58044c
JM		 2144#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2145_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2146_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2147
7c58044c 2148#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2149GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2150{ \
76a66253 2151 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2152 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2153 return; \
2154 } \
7c58044c 2155 gen_reset_fpstatus(); \
af12906f
AJ		 2156 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2157 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2158 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2159}
2160
7c58044c 2161#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2162GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2163{ \
76a66253 2164 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2165 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2166 return; \
2167 } \
7c58044c 2168 gen_reset_fpstatus(); \
af12906f
AJ		 2169 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2170 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2171 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2172}
2173
9a64fbe4 2174/* fadd - fadds */
7c58044c 2175GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2176/* fdiv - fdivs */
7c58044c 2177GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2178/* fmul - fmuls */
7c58044c 2179GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2180
d7e4b87e 2181/* fre */
7c58044c 2182GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2183
a750fc0b 2184/* fres */
7c58044c 2185GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2186
a750fc0b 2187/* frsqrte */
7c58044c
JM		 2188GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2189
2190/* frsqrtes */
af12906f 2191GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2192{
af12906f
AJ		 2193 if (unlikely(!ctx->fpu_enabled)) {
2194 GEN_EXCP_NO_FP(ctx);
2195 return;
2196 }
2197 gen_reset_fpstatus();
2198 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2199 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2200 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2201}
79aceca5 2202
a750fc0b 2203/* fsel */
7c58044c 2204_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2205/* fsub - fsubs */
7c58044c 2206GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2207/* Optional: */
2208/* fsqrt */
a750fc0b 2209GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2210{
76a66253 2211 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2212 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2213 return;
2214 }
7c58044c 2215 gen_reset_fpstatus();
af12906f
AJ		 2216 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2217 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2218}
79aceca5 2219
a750fc0b 2220GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2221{
76a66253 2222 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2223 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2224 return;
2225 }
7c58044c 2226 gen_reset_fpstatus();
af12906f
AJ		 2227 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2228 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2229 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2230}
2231
2232/*** Floating-Point multiply-and-add ***/
4ecc3190 2233/* fmadd - fmadds */
7c58044c 2234GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2235/* fmsub - fmsubs */
7c58044c 2236GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2237/* fnmadd - fnmadds */
7c58044c 2238GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2239/* fnmsub - fnmsubs */
7c58044c 2240GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2241
2242/*** Floating-Point round & convert ***/
2243/* fctiw */
7c58044c 2244GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2245/* fctiwz */
7c58044c 2246GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2247/* frsp */
7c58044c 2248GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2249#if defined(TARGET_PPC64)
2250/* fcfid */
7c58044c 2251GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2252/* fctid */
7c58044c 2253GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2254/* fctidz */
7c58044c 2255GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2256#endif
79aceca5 2257
d7e4b87e 2258/* frin */
7c58044c 2259GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2260/* friz */
7c58044c 2261GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2262/* frip */
7c58044c 2263GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2264/* frim */
7c58044c 2265GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2266
79aceca5
FB		 2267/*** Floating-Point compare ***/
2268/* fcmpo */
76a66253 2269GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2270{
76a66253 2271 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2272 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2273 return;
2274 }
7c58044c 2275 gen_reset_fpstatus();
af12906f
AJ		 2276 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2277 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2278 gen_helper_float_check_status();
79aceca5
FB		 2279}
2280
2281/* fcmpu */
76a66253 2282GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2283{
76a66253 2284 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2285 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2286 return;
2287 }
7c58044c 2288 gen_reset_fpstatus();
af12906f
AJ		 2289 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2290 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2291 gen_helper_float_check_status();
79aceca5
FB		 2292}
2293
9a64fbe4
FB		 2294/*** Floating-point move ***/
2295/* fabs */
7c58044c
JM		 2296/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2297GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2298
2299/* fmr - fmr. */
7c58044c 2300/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2301GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2302{
76a66253 2303 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2304 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2305 return;
2306 }
af12906f
AJ		 2307 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2308 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2309}
2310
2311/* fnabs */
7c58044c
JM		 2312/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2313GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2314/* fneg */
7c58044c
JM		 2315/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2316GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2317
79aceca5
FB		 2318/*** Floating-Point status & ctrl register ***/
2319/* mcrfs */
2320GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2321{
7c58044c
JM		 2322 int bfa;
2323
76a66253 2324 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2325 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2326 return;
2327 }
7c58044c
JM		 2328 gen_optimize_fprf();
2329 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2330 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2331 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2332 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2333}
2334
2335/* mffs */
2336GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2337{
76a66253 2338 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2339 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2340 return;
2341 }
7c58044c
JM		 2342 gen_optimize_fprf();
2343 gen_reset_fpstatus();
af12906f
AJ		 2344 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2345 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2346}
2347
2348/* mtfsb0 */
2349GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2350{
fb0eaffc 2351 uint8_t crb;
3b46e624 2352
76a66253 2353 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2354 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2355 return;
2356 }
7c58044c
JM		 2357 crb = 32 - (crbD(ctx->opcode) >> 2);
2358 gen_optimize_fprf();
2359 gen_reset_fpstatus();
2360 if (likely(crb != 30 && crb != 29))
af12906f 2361 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
7c58044c 2362 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2363 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2364 }
79aceca5
FB		 2365}
2366
2367/* mtfsb1 */
2368GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2369{
fb0eaffc 2370 uint8_t crb;
3b46e624 2371
76a66253 2372 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2373 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2374 return;
2375 }
7c58044c
JM		 2376 crb = 32 - (crbD(ctx->opcode) >> 2);
2377 gen_optimize_fprf();
2378 gen_reset_fpstatus();
2379 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2380 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
0f2f39c2 2381 TCGv_i32 t0 = tcg_const_i32(crb);
af12906f 2382 gen_helper_fpscr_setbit(t0);
0f2f39c2 2383 tcg_temp_free_i32(t0);
af12906f 2384 }
7c58044c 2385 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2386 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2387 }
2388 /* We can raise a differed exception */
af12906f 2389 gen_helper_float_check_status();
79aceca5
FB		 2390}
2391
2392/* mtfsf */
2393GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2394{
0f2f39c2 2395 TCGv_i32 t0;
af12906f 2396
76a66253 2397 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2398 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2399 return;
2400 }
7c58044c 2401 gen_optimize_fprf();
7c58044c 2402 gen_reset_fpstatus();
af12906f
AJ		 2403 t0 = tcg_const_i32(FM(ctx->opcode));
2404 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2405 tcg_temp_free_i32(t0);
7c58044c 2406 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2407 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2408 }
2409 /* We can raise a differed exception */
af12906f 2410 gen_helper_float_check_status();
79aceca5
FB		 2411}
2412
2413/* mtfsfi */
2414GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2415{
7c58044c 2416 int bf, sh;
0f2f39c2
AJ		 2417 TCGv_i64 t0;
2418 TCGv_i32 t1;
7c58044c 2419
76a66253 2420 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2421 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2422 return;
2423 }
7c58044c
JM		 2424 bf = crbD(ctx->opcode) >> 2;
2425 sh = 7 - bf;
2426 gen_optimize_fprf();
7c58044c 2427 gen_reset_fpstatus();
0f2f39c2 2428 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2429 t1 = tcg_const_i32(1 << sh);
2430 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2431 tcg_temp_free_i64(t0);
2432 tcg_temp_free_i32(t1);
7c58044c 2433 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2434 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2435 }
2436 /* We can raise a differed exception */
af12906f 2437 gen_helper_float_check_status();
79aceca5
FB		 2438}
2439
76a66253
JM		 2440/*** Addressing modes ***/
2441/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2442static always_inline void gen_addr_imm_index (TCGv EA,
2443 DisasContext *ctx,
b068d6a7 2444 target_long maskl)
76a66253
JM		 2445{
2446 target_long simm = SIMM(ctx->opcode);
2447
be147d08 2448 simm &= ~maskl;
e2be8d8d
AJ		 2449 if (rA(ctx->opcode) == 0)
2450 tcg_gen_movi_tl(EA, simm);
2451 else if (likely(simm != 0))
2452 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2453 else
2454 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2455}
2456
e2be8d8d
AJ		 2457static always_inline void gen_addr_reg_index (TCGv EA,
2458 DisasContext *ctx)
76a66253 2459{
e2be8d8d
AJ		 2460 if (rA(ctx->opcode) == 0)
2461 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2462 else
2463 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2464}
2465
e2be8d8d
AJ		 2466static always_inline void gen_addr_register (TCGv EA,
2467 DisasContext *ctx)
76a66253 2468{
e2be8d8d
AJ		 2469 if (rA(ctx->opcode) == 0)
2470 tcg_gen_movi_tl(EA, 0);
2471 else
2472 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2473}
2474
cf360a32
AJ		 2475static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2476{
2477 int l1 = gen_new_label();
2478 TCGv t0 = tcg_temp_new();
2479 TCGv_i32 t1, t2;
2480 /* NIP cannot be restored if the memory exception comes from an helper */
2481 gen_update_nip(ctx, ctx->nip - 4);
2482 tcg_gen_andi_tl(t0, EA, mask);
2483 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2484 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2485 t2 = tcg_const_i32(0);
2486 gen_helper_raise_exception_err(t1, t2);
2487 tcg_temp_free_i32(t1);
2488 tcg_temp_free_i32(t2);
2489 gen_set_label(l1);
2490 tcg_temp_free(t0);
2491}
2492
7863667f 2493/*** Integer load ***/
b61f2753
AJ		 2494#if defined(TARGET_PPC64)
2495#define GEN_QEMU_LD_PPC64(width) \
2496static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2497{ \
2498 if (likely(flags & 2)) \
2499 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2500 else { \
a7812ae4 2501 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2502 tcg_gen_ext32u_tl(addr, t1); \
2503 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2504 tcg_temp_free(addr); \
2505 } \
2506}
2507GEN_QEMU_LD_PPC64(8u)
2508GEN_QEMU_LD_PPC64(8s)
2509GEN_QEMU_LD_PPC64(16u)
2510GEN_QEMU_LD_PPC64(16s)
2511GEN_QEMU_LD_PPC64(32u)
2512GEN_QEMU_LD_PPC64(32s)
2513GEN_QEMU_LD_PPC64(64)
2514
2515#define GEN_QEMU_ST_PPC64(width) \
2516static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2517{ \
2518 if (likely(flags & 2)) \
2519 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2520 else { \
a7812ae4 2521 TCGv addr = tcg_temp_new(); \
b61f2753
AJ		 2522 tcg_gen_ext32u_tl(addr, t1); \
2523 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2524 tcg_temp_free(addr); \
2525 } \
2526}
2527GEN_QEMU_ST_PPC64(8)
2528GEN_QEMU_ST_PPC64(16)
2529GEN_QEMU_ST_PPC64(32)
2530GEN_QEMU_ST_PPC64(64)
2531
ea363694 2532static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2533{
ea363694 2534 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2535}
2536
ea363694 2537static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2538{
ea363694 2539 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2540}
2541
ea363694 2542static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2543{
2544 if (unlikely(flags & 1)) {
a7812ae4 2545 TCGv_i32 t0;
ea363694 2546 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2547 t0 = tcg_temp_new_i32();
ea363694
AJ		 2548 tcg_gen_trunc_tl_i32(t0, arg0);
2549 tcg_gen_bswap16_i32(t0, t0);
2550 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2551 tcg_temp_free_i32(t0);
b61f2753 2552 } else
ea363694 2553 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2554}
2555
ea363694 2556static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2557{
2558 if (unlikely(flags & 1)) {
a7812ae4 2559 TCGv_i32 t0;
ea363694 2560 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
a7812ae4 2561 t0 = tcg_temp_new_i32();
ea363694
AJ		 2562 tcg_gen_trunc_tl_i32(t0, arg0);
2563 tcg_gen_bswap16_i32(t0, t0);
2564 tcg_gen_extu_i32_tl(arg0, t0);
2565 tcg_gen_ext16s_tl(arg0, arg0);
a7812ae4 2566 tcg_temp_free_i32(t0);
b61f2753 2567 } else
ea363694 2568 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2569}
2570
ea363694 2571static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2572{
2573 if (unlikely(flags & 1)) {
a7812ae4 2574 TCGv_i32 t0;
ea363694 2575 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2576 t0 = tcg_temp_new_i32();
ea363694
AJ		 2577 tcg_gen_trunc_tl_i32(t0, arg0);
2578 tcg_gen_bswap_i32(t0, t0);
2579 tcg_gen_extu_i32_tl(arg0, t0);
a7812ae4 2580 tcg_temp_free_i32(t0);
b61f2753 2581 } else
ea363694 2582 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2583}
2584
ea363694 2585static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2586{
2587 if (unlikely(flags & 1)) {
a7812ae4 2588 TCGv_i32 t0;
ea363694 2589 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
a7812ae4 2590 t0 = tcg_temp_new_i32();
ea363694
AJ		 2591 tcg_gen_trunc_tl_i32(t0, arg0);
2592 tcg_gen_bswap_i32(t0, t0);
2593 tcg_gen_ext_i32_tl(arg0, t0);
a7812ae4 2594 tcg_temp_free_i32(t0);
b61f2753 2595 } else
ea363694 2596 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2597}
2598
ea363694 2599static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2600{
ea363694 2601 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2602 if (unlikely(flags & 1))
ea363694 2603 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2604}
2605
ea363694 2606static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2607{
ea363694 2608 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2609}
2610
ea363694 2611static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2612{
2613 if (unlikely(flags & 1)) {
a7812ae4
PB		 2614 TCGv_i32 t0;
2615 TCGv_i64 t1;
2616 t0 = tcg_temp_new_i32();
ea363694
AJ		 2617 tcg_gen_trunc_tl_i32(t0, arg0);
2618 tcg_gen_ext16u_i32(t0, t0);
2619 tcg_gen_bswap16_i32(t0, t0);
a7812ae4 2620 t1 = tcg_temp_new_i64();
ea363694 2621 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2622 tcg_temp_free_i32(t0);
ea363694 2623 gen_qemu_st16_ppc64(t1, arg1, flags);
a7812ae4 2624 tcg_temp_free_i64(t1);
b61f2753 2625 } else
ea363694 2626 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2627}
2628
ea363694 2629static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2630{
2631 if (unlikely(flags & 1)) {
a7812ae4
PB		 2632 TCGv_i32 t0;
2633 TCGv_i64 t1;
2634 t0 = tcg_temp_new_i32();
ea363694
AJ		 2635 tcg_gen_trunc_tl_i32(t0, arg0);
2636 tcg_gen_bswap_i32(t0, t0);
a7812ae4 2637 t1 = tcg_temp_new_i64();
ea363694 2638 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2639 tcg_temp_free_i32(t0);
ea363694 2640 gen_qemu_st32_ppc64(t1, arg1, flags);
a7812ae4 2641 tcg_temp_free_i64(t1);
b61f2753 2642 } else
ea363694 2643 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2644}
2645
ea363694 2646static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2647{
2648 if (unlikely(flags & 1)) {
a7812ae4 2649 TCGv_i64 t0 = tcg_temp_new_i64();
ea363694
AJ		 2650 tcg_gen_bswap_i64(t0, arg0);
2651 gen_qemu_st64_ppc64(t0, arg1, flags);
a7812ae4 2652 tcg_temp_free_i64(t0);
b61f2753 2653 } else
ea363694 2654 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2655}
2656
2657
2658#else /* defined(TARGET_PPC64) */
a0d7d5a7
AJ		 2659#define GEN_QEMU_LD_PPC32(width) \
2660static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2661{ \
2662 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2663}
2664GEN_QEMU_LD_PPC32(8u)
2665GEN_QEMU_LD_PPC32(8s)
2666GEN_QEMU_LD_PPC32(16u)
2667GEN_QEMU_LD_PPC32(16s)
2668GEN_QEMU_LD_PPC32(32u)
2669GEN_QEMU_LD_PPC32(32s)
a0d7d5a7
AJ		 2670static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2671{
2672 tcg_gen_qemu_ld64(arg0, arg1, flags >> 1);
2673}
b61f2753 2674
a0d7d5a7
AJ		 2675#define GEN_QEMU_ST_PPC32(width) \
2676static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2677{ \
2678 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2679}
2680GEN_QEMU_ST_PPC32(8)
2681GEN_QEMU_ST_PPC32(16)
2682GEN_QEMU_ST_PPC32(32)
a0d7d5a7
AJ		 2683static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2684{
2685 tcg_gen_qemu_st64(arg0, arg1, flags >> 1);
2686}
b61f2753 2687
ea363694 2688static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2689{
ea363694 2690 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2691}
2692
ea363694 2693static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2694{
ea363694 2695 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2696}
2697
ea363694 2698static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2699{
ea363694 2700 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2701 if (unlikely(flags & 1))
ea363694 2702 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2703}
2704
ea363694 2705static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2706{
2707 if (unlikely(flags & 1)) {
ea363694
AJ		 2708 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2709 tcg_gen_bswap16_i32(arg0, arg0);
2710 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2711 } else
ea363694 2712 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2713}
2714
ea363694 2715static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2716{
ea363694 2717 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2718 if (unlikely(flags & 1))
ea363694 2719 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2720}
2721
a0d7d5a7
AJ		 2722static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags)
2723{
2724 gen_qemu_ld64_ppc32(arg0, arg1, flags);
2725 if (unlikely(flags & 1))
2726 tcg_gen_bswap_i64(arg0, arg0);
2727}
2728
ea363694 2729static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2730{
e32ad5c2 2731 gen_qemu_st8_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2732}
2733
ea363694 2734static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2735{
2736 if (unlikely(flags & 1)) {
a7812ae4 2737 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2738 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2739 tcg_gen_bswap16_i32(temp, temp);
e32ad5c2 2740 gen_qemu_st16_ppc32(temp, arg1, flags);
a7812ae4 2741 tcg_temp_free_i32(temp);
b61f2753 2742 } else
e32ad5c2 2743 gen_qemu_st16_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2744}
2745
ea363694 2746static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2747{
2748 if (unlikely(flags & 1)) {
a7812ae4 2749 TCGv_i32 temp = tcg_temp_new_i32();
ea363694 2750 tcg_gen_bswap_i32(temp, arg0);
e32ad5c2 2751 gen_qemu_st32_ppc32(temp, arg1, flags);
a7812ae4 2752 tcg_temp_free_i32(temp);
b61f2753 2753 } else
e32ad5c2 2754 gen_qemu_st32_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2755}
2756
a0d7d5a7
AJ		 2757static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags)
2758{
2759 if (unlikely(flags & 1)) {
2760 TCGv_i64 temp = tcg_temp_new_i64();
2761 tcg_gen_bswap_i64(temp, arg0);
2762 gen_qemu_st64_ppc32(temp, arg1, flags);
2763 tcg_temp_free_i64(temp);
2764 } else
2765 gen_qemu_st64_ppc32(arg0, arg1, flags);
2766}
b61f2753
AJ		 2767#endif
2768
0c8aacd4
AJ		 2769#define GEN_LD(name, ldop, opc, type) \
2770GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2771{ \
0c8aacd4 2772 TCGv EA = tcg_temp_new(); \
a7859e89 2773 gen_set_access_type(ACCESS_INT); \
b61f2753 2774 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2775 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2776 tcg_temp_free(EA); \
79aceca5
FB		 2777}
2778
0c8aacd4
AJ		 2779#define GEN_LDU(name, ldop, opc, type) \
2780GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2781{ \
b61f2753 2782 TCGv EA; \
76a66253
JM		 2783 if (unlikely(rA(ctx->opcode) == 0 || \
2784 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2785 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2786 return; \
9a64fbe4 2787 } \
0c8aacd4 2788 EA = tcg_temp_new(); \
a7859e89 2789 gen_set_access_type(ACCESS_INT); \
9d53c753 2790 if (type == PPC_64B) \
b61f2753 2791 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2792 else \
b61f2753 2793 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2794 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2795 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2796 tcg_temp_free(EA); \
79aceca5
FB		 2797}
2798
0c8aacd4
AJ		 2799#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2800GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2801{ \
b61f2753 2802 TCGv EA; \
76a66253
JM		 2803 if (unlikely(rA(ctx->opcode) == 0 || \
2804 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2805 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2806 return; \
9a64fbe4 2807 } \
0c8aacd4 2808 EA = tcg_temp_new(); \
a7859e89 2809 gen_set_access_type(ACCESS_INT); \
b61f2753 2810 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2811 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2812 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2813 tcg_temp_free(EA); \
79aceca5
FB		 2814}
2815
0c8aacd4
AJ		 2816#define GEN_LDX(name, ldop, opc2, opc3, type) \
2817GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2818{ \
0c8aacd4 2819 TCGv EA = tcg_temp_new(); \
a7859e89 2820 gen_set_access_type(ACCESS_INT); \
b61f2753 2821 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2822 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2823 tcg_temp_free(EA); \
79aceca5
FB		 2824}
2825
0c8aacd4
AJ		 2826#define GEN_LDS(name, ldop, op, type) \
2827GEN_LD(name, ldop, op | 0x20, type); \
2828GEN_LDU(name, ldop, op | 0x21, type); \
2829GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2830GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2831
2832/* lbz lbzu lbzux lbzx */
0c8aacd4 2833GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2834/* lha lhau lhaux lhax */
0c8aacd4 2835GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2836/* lhz lhzu lhzux lhzx */
0c8aacd4 2837GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2838/* lwz lwzu lwzux lwzx */
0c8aacd4 2839GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2840#if defined(TARGET_PPC64)
d9bce9d9 2841/* lwaux */
0c8aacd4 2842GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2843/* lwax */
0c8aacd4 2844GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2845/* ldux */
0c8aacd4 2846GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2847/* ldx */
0c8aacd4 2848GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2849GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2850{
b61f2753 2851 TCGv EA;
d9bce9d9
JM		 2852 if (Rc(ctx->opcode)) {
2853 if (unlikely(rA(ctx->opcode) == 0 ||
2854 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2855 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2856 return;
2857 }
2858 }
a7812ae4 2859 EA = tcg_temp_new();
a7859e89 2860 gen_set_access_type(ACCESS_INT);
b61f2753 2861 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2862 if (ctx->opcode & 0x02) {
2863 /* lwa (lwau is undefined) */
b61f2753 2864 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2865 } else {
2866 /* ld - ldu */
b61f2753 2867 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2868 }
d9bce9d9 2869 if (Rc(ctx->opcode))
b61f2753
AJ		 2870 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2871 tcg_temp_free(EA);
d9bce9d9 2872}
be147d08
JM		 2873/* lq */
2874GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2875{
2876#if defined(CONFIG_USER_ONLY)
2877 GEN_EXCP_PRIVOPC(ctx);
2878#else
2879 int ra, rd;
b61f2753 2880 TCGv EA;
be147d08
JM		 2881
2882 /* Restore CPU state */
2883 if (unlikely(ctx->supervisor == 0)) {
2884 GEN_EXCP_PRIVOPC(ctx);
2885 return;
2886 }
2887 ra = rA(ctx->opcode);
2888 rd = rD(ctx->opcode);
2889 if (unlikely((rd & 1) || rd == ra)) {
2890 GEN_EXCP_INVAL(ctx);
2891 return;
2892 }
2893 if (unlikely(ctx->mem_idx & 1)) {
2894 /* Little-endian mode is not handled */
2895 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2896 return;
2897 }
a7812ae4 2898 EA = tcg_temp_new();
a7859e89 2899 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 2900 gen_addr_imm_index(EA, ctx, 0x0F);
2901 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2902 tcg_gen_addi_tl(EA, EA, 8);
2903 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2904 tcg_temp_free(EA);
be147d08
JM		 2905#endif
2906}
d9bce9d9 2907#endif
79aceca5
FB		 2908
2909/*** Integer store ***/
0c8aacd4
AJ		 2910#define GEN_ST(name, stop, opc, type) \
2911GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2912{ \
0c8aacd4 2913 TCGv EA = tcg_temp_new(); \
a7859e89 2914 gen_set_access_type(ACCESS_INT); \
b61f2753 2915 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2916 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2917 tcg_temp_free(EA); \
79aceca5
FB		 2918}
2919
0c8aacd4
AJ		 2920#define GEN_STU(name, stop, opc, type) \
2921GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2922{ \
b61f2753 2923 TCGv EA; \
76a66253 2924 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2925 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2926 return; \
9a64fbe4 2927 } \
0c8aacd4 2928 EA = tcg_temp_new(); \
a7859e89 2929 gen_set_access_type(ACCESS_INT); \
9d53c753 2930 if (type == PPC_64B) \
b61f2753 2931 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2932 else \
b61f2753 2933 gen_addr_imm_index(EA, ctx, 0); \
0c8aacd4 2934 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2935 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2936 tcg_temp_free(EA); \
79aceca5
FB		 2937}
2938
0c8aacd4
AJ		 2939#define GEN_STUX(name, stop, opc2, opc3, type) \
2940GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2941{ \
b61f2753 2942 TCGv EA; \
76a66253 2943 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2944 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2945 return; \
9a64fbe4 2946 } \
0c8aacd4 2947 EA = tcg_temp_new(); \
a7859e89 2948 gen_set_access_type(ACCESS_INT); \
b61f2753 2949 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2950 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753
AJ		 2951 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2952 tcg_temp_free(EA); \
79aceca5
FB		 2953}
2954
0c8aacd4
AJ		 2955#define GEN_STX(name, stop, opc2, opc3, type) \
2956GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2957{ \
0c8aacd4 2958 TCGv EA = tcg_temp_new(); \
a7859e89 2959 gen_set_access_type(ACCESS_INT); \
b61f2753 2960 gen_addr_reg_index(EA, ctx); \
0c8aacd4 2961 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
b61f2753 2962 tcg_temp_free(EA); \
79aceca5
FB		 2963}
2964
0c8aacd4
AJ		 2965#define GEN_STS(name, stop, op, type) \
2966GEN_ST(name, stop, op | 0x20, type); \
2967GEN_STU(name, stop, op | 0x21, type); \
2968GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2969GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2970
2971/* stb stbu stbux stbx */
0c8aacd4 2972GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2973/* sth sthu sthux sthx */
0c8aacd4 2974GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2975/* stw stwu stwux stwx */
0c8aacd4 2976GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2977#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2978GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2979GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2980GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2981{
be147d08 2982 int rs;
b61f2753 2983 TCGv EA;
be147d08
JM		 2984
2985 rs = rS(ctx->opcode);
2986 if ((ctx->opcode & 0x3) == 0x2) {
2987#if defined(CONFIG_USER_ONLY)
2988 GEN_EXCP_PRIVOPC(ctx);
2989#else
2990 /* stq */
2991 if (unlikely(ctx->supervisor == 0)) {
2992 GEN_EXCP_PRIVOPC(ctx);
2993 return;
2994 }
2995 if (unlikely(rs & 1)) {
e1833e1f 2996 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2997 return;
2998 }
be147d08
JM		 2999 if (unlikely(ctx->mem_idx & 1)) {
3000 /* Little-endian mode is not handled */
3001 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3002 return;
3003 }
a7812ae4 3004 EA = tcg_temp_new();
a7859e89 3005 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3006 gen_addr_imm_index(EA, ctx, 0x03);
3007 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3008 tcg_gen_addi_tl(EA, EA, 8);
3009 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3010 tcg_temp_free(EA);
be147d08
JM		 3011#endif
3012 } else {
3013 /* std / stdu */
3014 if (Rc(ctx->opcode)) {
3015 if (unlikely(rA(ctx->opcode) == 0)) {
3016 GEN_EXCP_INVAL(ctx);
3017 return;
3018 }
3019 }
a7812ae4 3020 EA = tcg_temp_new();
a7859e89 3021 gen_set_access_type(ACCESS_INT);
b61f2753
AJ		 3022 gen_addr_imm_index(EA, ctx, 0x03);
3023 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 3024 if (Rc(ctx->opcode))
b61f2753
AJ		 3025 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3026 tcg_temp_free(EA);
d9bce9d9 3027 }
d9bce9d9
JM		 3028}
3029#endif
79aceca5
FB		 3030/*** Integer load and store with byte reverse ***/
3031/* lhbrx */
b61f2753
AJ		 3032void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3033{
a7812ae4
PB		 3034 TCGv_i32 temp = tcg_temp_new_i32();
3035 gen_qemu_ld16u(t0, t1, flags);
3036 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3037 tcg_gen_bswap16_i32(temp, temp);
3038 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3039 tcg_temp_free_i32(temp);
b61f2753 3040}
0c8aacd4 3041GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3042
79aceca5 3043/* lwbrx */
b61f2753
AJ		 3044void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3045{
a7812ae4
PB		 3046 TCGv_i32 temp = tcg_temp_new_i32();
3047 gen_qemu_ld32u(t0, t1, flags);
3048 tcg_gen_trunc_tl_i32(temp, t0);
b61f2753
AJ		 3049 tcg_gen_bswap_i32(temp, temp);
3050 tcg_gen_extu_i32_tl(t0, temp);
a7812ae4 3051 tcg_temp_free_i32(temp);
b61f2753 3052}
0c8aacd4 3053GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3054
79aceca5 3055/* sthbrx */
b61f2753
AJ		 3056void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3057{
a7812ae4
PB		 3058 TCGv_i32 temp = tcg_temp_new_i32();
3059 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3060 tcg_gen_trunc_tl_i32(temp, t0);
3061 tcg_gen_ext16u_i32(temp, temp);
3062 tcg_gen_bswap16_i32(temp, temp);
a7812ae4
PB		 3063 tcg_gen_extu_i32_tl(t2, temp);
3064 tcg_temp_free_i32(temp);
3065 gen_qemu_st16(t2, t1, flags);
3066 tcg_temp_free(t2);
b61f2753 3067}
0c8aacd4 3068GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3069
79aceca5 3070/* stwbrx */
b61f2753
AJ		 3071void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3072{
a7812ae4
PB		 3073 TCGv_i32 temp = tcg_temp_new_i32();
3074 TCGv t2 = tcg_temp_new();
b61f2753
AJ		 3075 tcg_gen_trunc_tl_i32(temp, t0);
3076 tcg_gen_bswap_i32(temp, temp);
a7812ae4
PB		 3077 tcg_gen_extu_i32_tl(t2, temp);
3078 tcg_temp_free_i32(temp);
87006d13 3079 gen_qemu_st32(t2, t1, flags);
a7812ae4 3080 tcg_temp_free(t2);
b61f2753 3081}
0c8aacd4 3082GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3083
3084/*** Integer load and store multiple ***/
3085/* lmw */
3086GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3087{
ff4a62cd
AJ		 3088 TCGv t0 = tcg_temp_new();
3089 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
76a66253 3090 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3091 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3092 gen_addr_imm_index(t0, ctx, 0);
3093 gen_helper_lmw(t0, t1);
3094 tcg_temp_free(t0);
3095 tcg_temp_free_i32(t1);
79aceca5
FB		 3096}
3097
3098/* stmw */
3099GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3100{
ff4a62cd
AJ		 3101 TCGv t0 = tcg_temp_new();
3102 TCGv_i32 t1 = tcg_const_i32(rS(ctx->opcode));
76a66253 3103 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3104 gen_update_nip(ctx, ctx->nip - 4);
ff4a62cd
AJ		 3105 gen_addr_imm_index(t0, ctx, 0);
3106 gen_helper_stmw(t0, t1);
3107 tcg_temp_free(t0);
3108 tcg_temp_free_i32(t1);
79aceca5
FB		 3109}
3110
3111/*** Integer load and store strings ***/
3112/* lswi */
3fc6c082 3113/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3114 * rA is in the range of registers to be loaded.
3115 * In an other hand, IBM says this is valid, but rA won't be loaded.
3116 * For now, I'll follow the spec...
3117 */
05332d70 3118GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3119{
dfbc799d
AJ		 3120 TCGv t0;
3121 TCGv_i32 t1, t2;
79aceca5
FB		 3122 int nb = NB(ctx->opcode);
3123 int start = rD(ctx->opcode);
9a64fbe4 3124 int ra = rA(ctx->opcode);
79aceca5
FB		 3125 int nr;
3126
3127 if (nb == 0)
3128 nb = 32;
3129 nr = nb / 4;
76a66253
JM		 3130 if (unlikely(((start + nr) > 32 &&
3131 start <= ra && (start + nr - 32) > ra) ||
3132 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3133 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3134 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3135 return;
297d8e62 3136 }
8dd4983c 3137 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3138 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3139 t0 = tcg_temp_new();
3140 gen_addr_register(t0, ctx);
3141 t1 = tcg_const_i32(nb);
3142 t2 = tcg_const_i32(start);
3143 gen_helper_lsw(t0, t1, t2);
3144 tcg_temp_free(t0);
3145 tcg_temp_free_i32(t1);
3146 tcg_temp_free_i32(t2);
79aceca5
FB		 3147}
3148
3149/* lswx */
05332d70 3150GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3151{
dfbc799d
AJ		 3152 TCGv t0 = tcg_temp_new();
3153 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
3154 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
3155 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 3156 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3157 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3158 gen_addr_reg_index(t0, ctx);
3159 gen_helper_lswx(t0, t1, t2, t3);
3160 tcg_temp_free(t0);
3161 tcg_temp_free_i32(t1);
3162 tcg_temp_free_i32(t2);
3163 tcg_temp_free_i32(t3);
79aceca5
FB		 3164}
3165
3166/* stswi */
05332d70 3167GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3168{
4b3686fa 3169 int nb = NB(ctx->opcode);
dfbc799d
AJ		 3170 TCGv t0 = tcg_temp_new();
3171 TCGv_i32 t1;
3172 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
76a66253 3173 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3174 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3175 gen_addr_register(t0, ctx);
4b3686fa
FB		 3176 if (nb == 0)
3177 nb = 32;
dfbc799d
AJ		 3178 t1 = tcg_const_i32(nb);
3179 gen_helper_stsw(t0, t1, t2);
3180 tcg_temp_free(t0);
3181 tcg_temp_free_i32(t1);
3182 tcg_temp_free_i32(t2);
79aceca5
FB		 3183}
3184
3185/* stswx */
05332d70 3186GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3187{
dfbc799d
AJ		 3188 TCGv t0 = tcg_temp_new();
3189 TCGv_i32 t1 = tcg_temp_new_i32();
3190 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
8dd4983c 3191 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3192 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d
AJ		 3193 gen_addr_reg_index(t0, ctx);
3194 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3195 tcg_gen_andi_i32(t1, t1, 0x7F);
3196 gen_helper_stsw(t0, t1, t2);
3197 tcg_temp_free(t0);
3198 tcg_temp_free_i32(t1);
3199 tcg_temp_free_i32(t2);
79aceca5
FB		 3200}
3201
3202/*** Memory synchronisation ***/
3203/* eieio */
0db1b20e 3204GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3205{
79aceca5
FB		 3206}
3207
3208/* isync */
0db1b20e 3209GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3210{
e1833e1f 3211 GEN_STOP(ctx);
79aceca5
FB		 3212}
3213
111bfab3 3214/* lwarx */
76a66253 3215GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3216{
cf360a32 3217 TCGv t0 = tcg_temp_local_new();
a7859e89 3218 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3219 gen_addr_reg_index(t0, ctx);
3220 gen_check_align(ctx, t0, 0x03);
3221#if defined(TARGET_PPC64)
3222 if (!ctx->sf_mode)
3223 tcg_gen_ext32u_tl(t0, t0);
3224#endif
3225 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3226 tcg_gen_mov_tl(cpu_reserve, t0);
3227 tcg_temp_free(t0);
79aceca5
FB		 3228}
3229
3230/* stwcx. */
c7697e1f 3231GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3232{
cf360a32
AJ		 3233 int l1 = gen_new_label();
3234 TCGv t0 = tcg_temp_local_new();
a7859e89 3235 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3236 gen_addr_reg_index(t0, ctx);
3237 gen_check_align(ctx, t0, 0x03);
3238#if defined(TARGET_PPC64)
3239 if (!ctx->sf_mode)
3240 tcg_gen_ext32u_tl(t0, t0);
3241#endif
3242 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3243 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3244 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3245 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3246 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3247 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3248 gen_set_label(l1);
3249 tcg_gen_movi_tl(cpu_reserve, -1);
3250 tcg_temp_free(t0);
79aceca5
FB		 3251}
3252
426613db 3253#if defined(TARGET_PPC64)
426613db 3254/* ldarx */
a750fc0b 3255GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3256{
cf360a32 3257 TCGv t0 = tcg_temp_local_new();
a7859e89 3258 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3259 gen_addr_reg_index(t0, ctx);
3260 gen_check_align(ctx, t0, 0x07);
3261 if (!ctx->sf_mode)
3262 tcg_gen_ext32u_tl(t0, t0);
3263 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3264 tcg_gen_mov_tl(cpu_reserve, t0);
3265 tcg_temp_free(t0);
426613db
JM		 3266}
3267
3268/* stdcx. */
c7697e1f 3269GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3270{
cf360a32
AJ		 3271 int l1 = gen_new_label();
3272 TCGv t0 = tcg_temp_local_new();
a7859e89 3273 gen_set_access_type(ACCESS_RES);
cf360a32
AJ		 3274 gen_addr_reg_index(t0, ctx);
3275 gen_check_align(ctx, t0, 0x07);
3276 if (!ctx->sf_mode)
3277 tcg_gen_ext32u_tl(t0, t0);
3278 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3279 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3280 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3281 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3282 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3283 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3284 gen_set_label(l1);
3285 tcg_gen_movi_tl(cpu_reserve, -1);
3286 tcg_temp_free(t0);
426613db
JM		 3287}
3288#endif /* defined(TARGET_PPC64) */
3289
79aceca5 3290/* sync */
a902d886 3291GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3292{
79aceca5
FB		 3293}
3294
0db1b20e
JM		 3295/* wait */
3296GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3297{
931ff272
AJ		 3298 TCGv_i32 t0 = tcg_temp_new_i32();
3299 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3300 tcg_temp_free_i32(t0);
0db1b20e 3301 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08 3302 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3303}
3304
79aceca5 3305/*** Floating-point load ***/
a0d7d5a7
AJ		 3306#define GEN_LDF(name, ldop, opc, type) \
3307GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3308{ \
a0d7d5a7 3309 TCGv EA; \
76a66253 3310 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3311 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3312 return; \
3313 } \
a7859e89 3314 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3315 EA = tcg_temp_new(); \
3316 gen_addr_imm_index(EA, ctx, 0); \
3317 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3318 tcg_temp_free(EA); \
79aceca5
FB		 3319}
3320
a0d7d5a7
AJ		 3321#define GEN_LDUF(name, ldop, opc, type) \
3322GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3323{ \
a0d7d5a7 3324 TCGv EA; \
76a66253 3325 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3326 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3327 return; \
3328 } \
76a66253 3329 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3330 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3331 return; \
9a64fbe4 3332 } \
a7859e89 3333 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3334 EA = tcg_temp_new(); \
3335 gen_addr_imm_index(EA, ctx, 0); \
3336 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3337 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3338 tcg_temp_free(EA); \
79aceca5
FB		 3339}
3340
a0d7d5a7
AJ		 3341#define GEN_LDUXF(name, ldop, opc, type) \
3342GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3343{ \
a0d7d5a7 3344 TCGv EA; \
76a66253 3345 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3346 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3347 return; \
3348 } \
76a66253 3349 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3350 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3351 return; \
9a64fbe4 3352 } \
a7859e89 3353 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3354 EA = tcg_temp_new(); \
3355 gen_addr_reg_index(EA, ctx); \
3356 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3357 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3358 tcg_temp_free(EA); \
79aceca5
FB		 3359}
3360
a0d7d5a7
AJ		 3361#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3362GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3363{ \
a0d7d5a7 3364 TCGv EA; \
76a66253 3365 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3366 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3367 return; \
3368 } \
a7859e89 3369 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3370 EA = tcg_temp_new(); \
3371 gen_addr_reg_index(EA, ctx); \
3372 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3373 tcg_temp_free(EA); \
79aceca5
FB		 3374}
3375
a0d7d5a7
AJ		 3376#define GEN_LDFS(name, ldop, op, type) \
3377GEN_LDF(name, ldop, op | 0x20, type); \
3378GEN_LDUF(name, ldop, op | 0x21, type); \
3379GEN_LDUXF(name, ldop, op | 0x01, type); \
3380GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3381
3382static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3383{
3384 TCGv t0 = tcg_temp_new();
3385 TCGv_i32 t1 = tcg_temp_new_i32();
3386 gen_qemu_ld32u(t0, arg2, flags);
3387 tcg_gen_trunc_tl_i32(t1, t0);
3388 tcg_temp_free(t0);
3389 gen_helper_float32_to_float64(arg1, t1);
3390 tcg_temp_free_i32(t1);
3391}
79aceca5 3392
a0d7d5a7
AJ		 3393 /* lfd lfdu lfdux lfdx */
3394GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3395 /* lfs lfsu lfsux lfsx */
3396GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3397
3398/*** Floating-point store ***/
a0d7d5a7
AJ		 3399#define GEN_STF(name, stop, opc, type) \
3400GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3401{ \
a0d7d5a7 3402 TCGv EA; \
76a66253 3403 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3404 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3405 return; \
3406 } \
a7859e89 3407 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3408 EA = tcg_temp_new(); \
3409 gen_addr_imm_index(EA, ctx, 0); \
3410 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3411 tcg_temp_free(EA); \
79aceca5
FB		 3412}
3413
a0d7d5a7
AJ		 3414#define GEN_STUF(name, stop, opc, type) \
3415GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3416{ \
a0d7d5a7 3417 TCGv EA; \
76a66253 3418 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3419 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3420 return; \
3421 } \
76a66253 3422 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3423 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3424 return; \
9a64fbe4 3425 } \
a7859e89 3426 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3427 EA = tcg_temp_new(); \
3428 gen_addr_imm_index(EA, ctx, 0); \
3429 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3430 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3431 tcg_temp_free(EA); \
79aceca5
FB		 3432}
3433
a0d7d5a7
AJ		 3434#define GEN_STUXF(name, stop, opc, type) \
3435GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3436{ \
a0d7d5a7 3437 TCGv EA; \
76a66253 3438 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3439 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3440 return; \
3441 } \
76a66253 3442 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3443 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3444 return; \
9a64fbe4 3445 } \
a7859e89 3446 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3447 EA = tcg_temp_new(); \
3448 gen_addr_reg_index(EA, ctx); \
3449 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3450 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3451 tcg_temp_free(EA); \
79aceca5
FB		 3452}
3453
a0d7d5a7
AJ		 3454#define GEN_STXF(name, stop, opc2, opc3, type) \
3455GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3456{ \
a0d7d5a7 3457 TCGv EA; \
76a66253 3458 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3459 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3460 return; \
3461 } \
a7859e89 3462 gen_set_access_type(ACCESS_FLOAT); \
a0d7d5a7
AJ		 3463 EA = tcg_temp_new(); \
3464 gen_addr_reg_index(EA, ctx); \
3465 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3466 tcg_temp_free(EA); \
79aceca5
FB		 3467}
3468
a0d7d5a7
AJ		 3469#define GEN_STFS(name, stop, op, type) \
3470GEN_STF(name, stop, op | 0x20, type); \
3471GEN_STUF(name, stop, op | 0x21, type); \
3472GEN_STUXF(name, stop, op | 0x01, type); \
3473GEN_STXF(name, stop, 0x17, op | 0x00, type)
3474
3475static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3476{
3477 TCGv_i32 t0 = tcg_temp_new_i32();
3478 TCGv t1 = tcg_temp_new();
3479 gen_helper_float64_to_float32(t0, arg1);
3480 tcg_gen_extu_i32_tl(t1, t0);
3481 tcg_temp_free_i32(t0);
3482 gen_qemu_st32(t1, arg2, flags);
3483 tcg_temp_free(t1);
3484}
79aceca5
FB		 3485
3486/* stfd stfdu stfdux stfdx */
a0d7d5a7 3487GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3488/* stfs stfsu stfsux stfsx */
a0d7d5a7 3489GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3490
3491/* Optional: */
a0d7d5a7
AJ		 3492static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags)
3493{
3494 TCGv t0 = tcg_temp_new();
3495 tcg_gen_trunc_i64_tl(t0, arg1),
3496 gen_qemu_st32(t0, arg2, flags);
3497 tcg_temp_free(t0);
3498}
79aceca5 3499/* stfiwx */
a0d7d5a7 3500GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3501
3502/*** Branch ***/
b068d6a7
JM		 3503static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3504 target_ulong dest)
c1942362
FB		 3505{
3506 TranslationBlock *tb;
3507 tb = ctx->tb;
a2ffb812
AJ		 3508#if defined(TARGET_PPC64)
3509 if (!ctx->sf_mode)
3510 dest = (uint32_t) dest;
3511#endif
57fec1fe 3512 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3513 likely(!ctx->singlestep_enabled)) {
57fec1fe 3514 tcg_gen_goto_tb(n);
a2ffb812 3515 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3516 tcg_gen_exit_tb((long)tb + n);
c1942362 3517 } else {
a2ffb812 3518 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3519 if (unlikely(ctx->singlestep_enabled)) {
3520 if ((ctx->singlestep_enabled &
bdc4e053 3521 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3522 ctx->exception == POWERPC_EXCP_BRANCH) {
3523 target_ulong tmp = ctx->nip;
3524 ctx->nip = dest;
3525 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3526 ctx->nip = tmp;
3527 }
3528 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3529 gen_update_nip(ctx, dest);
64adab3f 3530 gen_helper_raise_debug();
8cbcb4fa
AJ		 3531 }
3532 }
57fec1fe 3533 tcg_gen_exit_tb(0);
c1942362 3534 }
c53be334
FB		 3535}
3536
b068d6a7 3537static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3538{
3539#if defined(TARGET_PPC64)
a2ffb812
AJ		 3540 if (ctx->sf_mode == 0)
3541 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3542 else
3543#endif
a2ffb812 3544 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3545}
3546
79aceca5
FB		 3547/* b ba bl bla */
3548GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3549{
76a66253 3550 target_ulong li, target;
38a64f9d 3551
8cbcb4fa 3552 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3553 /* sign extend LI */
76a66253 3554#if defined(TARGET_PPC64)
d9bce9d9
JM		 3555 if (ctx->sf_mode)
3556 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3557 else
76a66253 3558#endif
d9bce9d9 3559 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3560 if (likely(AA(ctx->opcode) == 0))
046d6672 3561 target = ctx->nip + li - 4;
79aceca5 3562 else
9a64fbe4 3563 target = li;
e1833e1f
JM		 3564 if (LK(ctx->opcode))
3565 gen_setlr(ctx, ctx->nip);
c1942362 3566 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3567}
3568
e98a6e40
FB		 3569#define BCOND_IM 0
3570#define BCOND_LR 1
3571#define BCOND_CTR 2
3572
b068d6a7 3573static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3574{
d9bce9d9 3575 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3576 int l1 = gen_new_label();
3577 TCGv target;
e98a6e40 3578
8cbcb4fa 3579 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3580 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3581 target = tcg_temp_local_new();
a2ffb812
AJ		 3582 if (type == BCOND_CTR)
3583 tcg_gen_mov_tl(target, cpu_ctr);
3584 else
3585 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3586 }
e1833e1f
JM		 3587 if (LK(ctx->opcode))
3588 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3589 l1 = gen_new_label();
3590 if ((bo & 0x4) == 0) {
3591 /* Decrement and test CTR */
a7812ae4 3592 TCGv temp = tcg_temp_new();
a2ffb812
AJ		 3593 if (unlikely(type == BCOND_CTR)) {
3594 GEN_EXCP_INVAL(ctx);
3595 return;
3596 }
3597 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3598#if defined(TARGET_PPC64)
a2ffb812
AJ		 3599 if (!ctx->sf_mode)
3600 tcg_gen_ext32u_tl(temp, cpu_ctr);
3601 else
d9bce9d9 3602#endif
a2ffb812
AJ		 3603 tcg_gen_mov_tl(temp, cpu_ctr);
3604 if (bo & 0x2) {
3605 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3606 } else {
3607 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3608 }
a7812ae4 3609 tcg_temp_free(temp);
a2ffb812
AJ		 3610 }
3611 if ((bo & 0x10) == 0) {
3612 /* Test CR */
3613 uint32_t bi = BI(ctx->opcode);
3614 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3615 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3616
d9bce9d9 3617 if (bo & 0x8) {
a2ffb812
AJ		 3618 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3619 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3620 } else {
a2ffb812
AJ		 3621 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3622 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3623 }
a7812ae4 3624 tcg_temp_free_i32(temp);
d9bce9d9 3625 }
e98a6e40 3626 if (type == BCOND_IM) {
a2ffb812
AJ		 3627 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3628 if (likely(AA(ctx->opcode) == 0)) {
3629 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3630 } else {
3631 gen_goto_tb(ctx, 0, li);
3632 }
c53be334 3633 gen_set_label(l1);
c1942362 3634 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3635 } else {
d9bce9d9 3636#if defined(TARGET_PPC64)
a2ffb812
AJ		 3637 if (!(ctx->sf_mode))
3638 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3639 else
3640#endif
3641 tcg_gen_andi_tl(cpu_nip, target, ~3);
3642 tcg_gen_exit_tb(0);
3643 gen_set_label(l1);
3644#if defined(TARGET_PPC64)
3645 if (!(ctx->sf_mode))
3646 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3647 else
3648#endif
a2ffb812 3649 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3650 tcg_gen_exit_tb(0);
08e46e54 3651 }
e98a6e40
FB		 3652}
3653
3654GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3655{
e98a6e40
FB		 3656 gen_bcond(ctx, BCOND_IM);
3657}
3658
3659GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3660{
e98a6e40
FB		 3661 gen_bcond(ctx, BCOND_CTR);
3662}
3663
3664GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3665{
e98a6e40
FB		 3666 gen_bcond(ctx, BCOND_LR);
3667}
79aceca5
FB		 3668
3669/*** Condition register logical ***/
e1571908
AJ		 3670#define GEN_CRLOGIC(name, tcg_op, opc) \
3671GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3672{ \
fc0d441e
JM		 3673 uint8_t bitmask; \
3674 int sh; \
a7812ae4 3675 TCGv_i32 t0, t1; \
fc0d441e 3676 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3677 t0 = tcg_temp_new_i32(); \
fc0d441e 3678 if (sh > 0) \
fea0c503 3679 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3680 else if (sh < 0) \
fea0c503 3681 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3682 else \
fea0c503 3683 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3684 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3685 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3686 if (sh > 0) \
fea0c503 3687 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3688 else if (sh < 0) \
fea0c503 3689 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3690 else \
fea0c503
AJ		 3691 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3692 tcg_op(t0, t0, t1); \
fc0d441e 3693 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3694 tcg_gen_andi_i32(t0, t0, bitmask); \
3695 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3696 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3697 tcg_temp_free_i32(t0); \
3698 tcg_temp_free_i32(t1); \
79aceca5
FB		 3699}
3700
3701/* crand */
e1571908 3702GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3703/* crandc */
e1571908 3704GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3705/* creqv */
e1571908 3706GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3707/* crnand */
e1571908 3708GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3709/* crnor */
e1571908 3710GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3711/* cror */
e1571908 3712GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3713/* crorc */
e1571908 3714GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3715/* crxor */
e1571908 3716GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3717/* mcrf */
3718GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3719{
47e4661c 3720 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3721}
3722
3723/*** System linkage ***/
3724/* rfi (supervisor only) */
76a66253 3725GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3726{
9a64fbe4 3727#if defined(CONFIG_USER_ONLY)
e1833e1f 3728 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3729#else
3730 /* Restore CPU state */
76a66253 3731 if (unlikely(!ctx->supervisor)) {
e1833e1f 3732 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3733 return;
9a64fbe4 3734 }
a42bd6cc 3735 gen_op_rfi();
e1833e1f 3736 GEN_SYNC(ctx);
9a64fbe4 3737#endif
79aceca5
FB		 3738}
3739
426613db 3740#if defined(TARGET_PPC64)
a750fc0b 3741GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3742{
3743#if defined(CONFIG_USER_ONLY)
e1833e1f 3744 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3745#else
3746 /* Restore CPU state */
3747 if (unlikely(!ctx->supervisor)) {
e1833e1f 3748 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3749 return;
3750 }
a42bd6cc 3751 gen_op_rfid();
e1833e1f 3752 GEN_SYNC(ctx);
426613db
JM		 3753#endif
3754}
426613db 3755
5b8105fa 3756GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3757{
3758#if defined(CONFIG_USER_ONLY)
3759 GEN_EXCP_PRIVOPC(ctx);
3760#else
3761 /* Restore CPU state */
3762 if (unlikely(ctx->supervisor <= 1)) {
3763 GEN_EXCP_PRIVOPC(ctx);
3764 return;
3765 }
3766 gen_op_hrfid();
3767 GEN_SYNC(ctx);
3768#endif
3769}
3770#endif
3771
79aceca5 3772/* sc */
417bf010
JM		 3773#if defined(CONFIG_USER_ONLY)
3774#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3775#else
3776#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3777#endif
e1833e1f 3778GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3779{
e1833e1f
JM		 3780 uint32_t lev;
3781
3782 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3783 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3784}
3785
3786/*** Trap ***/
3787/* tw */
76a66253 3788GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3789{
cab3bee2 3790 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3791 /* Update the nip since this might generate a trap exception */
d9bce9d9 3792 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3793 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3794 tcg_temp_free_i32(t0);
79aceca5
FB		 3795}
3796
3797/* twi */
3798GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3799{
cab3bee2
AJ		 3800 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3801 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3802 /* Update the nip since this might generate a trap exception */
3803 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3804 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3805 tcg_temp_free(t0);
3806 tcg_temp_free_i32(t1);
79aceca5
FB		 3807}
3808
d9bce9d9
JM		 3809#if defined(TARGET_PPC64)
3810/* td */
3811GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3812{
cab3bee2 3813 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3814 /* Update the nip since this might generate a trap exception */
3815 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3816 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3817 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3818}
3819
3820/* tdi */
3821GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3822{
cab3bee2
AJ		 3823 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3824 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3825 /* Update the nip since this might generate a trap exception */
3826 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3827 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3828 tcg_temp_free(t0);
3829 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3830}
3831#endif
3832
79aceca5 3833/*** Processor control ***/
79aceca5
FB		 3834/* mcrxr */
3835GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3836{
3d7b417e
AJ		 3837 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3838 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3839 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3840}
3841
3842/* mfcr */
76a66253 3843GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3844{
76a66253 3845 uint32_t crm, crn;
3b46e624 3846
76a66253
JM		 3847 if (likely(ctx->opcode & 0x00100000)) {
3848 crm = CRM(ctx->opcode);
3849 if (likely((crm ^ (crm - 1)) == 0)) {
3850 crn = ffs(crm);
e1571908 3851 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3852 }
d9bce9d9 3853 } else {
a7812ae4 3854 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3855 }
79aceca5
FB		 3856}
3857
3858/* mfmsr */
3859GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3860{
9a64fbe4 3861#if defined(CONFIG_USER_ONLY)
e1833e1f 3862 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3863#else
76a66253 3864 if (unlikely(!ctx->supervisor)) {
e1833e1f 3865 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3866 return;
9a64fbe4 3867 }
6676f424 3868 gen_op_load_msr();
f78fb44e 3869 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3870#endif
79aceca5
FB		 3871}
3872
a11b8151 3873#if 1
6f2d8978 3874#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3875#else
3876static void spr_noaccess (void *opaque, int sprn)
3877{
3878 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3879 printf("ERROR: try to access SPR %d !\n", sprn);
3880}
3881#define SPR_NOACCESS (&spr_noaccess)
3882#endif
3883
79aceca5 3884/* mfspr */
b068d6a7 3885static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3886{
3fc6c082 3887 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3888 uint32_t sprn = SPR(ctx->opcode);
3889
3fc6c082 3890#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3891 if (ctx->supervisor == 2)
3892 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3893 else if (ctx->supervisor)
3fc6c082
FB		 3894 read_cb = ctx->spr_cb[sprn].oea_read;
3895 else
9a64fbe4 3896#endif
3fc6c082 3897 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3898 if (likely(read_cb != NULL)) {
3899 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3900 (*read_cb)(ctx, sprn);
f78fb44e 3901 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3902 } else {
3903 /* Privilege exception */
9fceefa7
JM		 3904 /* This is a hack to avoid warnings when running Linux:
3905 * this OS breaks the PowerPC virtualisation model,
3906 * allowing userland application to read the PVR
3907 */
3908 if (sprn != SPR_PVR) {
3909 if (loglevel != 0) {
6b542af7 3910 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3911 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3912 }
077fc206
JM		 3913 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3914 sprn, sprn, ctx->nip);
f24e5695 3915 }
e1833e1f 3916 GEN_EXCP_PRIVREG(ctx);
79aceca5 3917 }
3fc6c082
FB		 3918 } else {
3919 /* Not defined */
4a057712 3920 if (loglevel != 0) {
077fc206
JM		 3921 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3922 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3923 }
077fc206
JM		 3924 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3925 sprn, sprn, ctx->nip);
e1833e1f
JM		 3926 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3927 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3928 }
79aceca5
FB		 3929}
3930
3fc6c082 3931GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3932{
3fc6c082 3933 gen_op_mfspr(ctx);
76a66253 3934}
3fc6c082
FB		 3935
3936/* mftb */
a750fc0b 3937GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3938{
3939 gen_op_mfspr(ctx);
79aceca5
FB		 3940}
3941
3942/* mtcrf */
8dd4983c 3943GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3944{
76a66253 3945 uint32_t crm, crn;
3b46e624 3946
76a66253
JM		 3947 crm = CRM(ctx->opcode);
3948 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
a7812ae4 3949 TCGv_i32 temp = tcg_temp_new_i32();
76a66253 3950 crn = ffs(crm);
a7812ae4
PB		 3951 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3952 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
e1571908 3953 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
a7812ae4 3954 tcg_temp_free_i32(temp);
76a66253 3955 } else {
a7812ae4
PB		 3956 TCGv_i32 temp = tcg_const_i32(crm);
3957 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3958 tcg_temp_free_i32(temp);
76a66253 3959 }
79aceca5
FB		 3960}
3961
3962/* mtmsr */
426613db 3963#if defined(TARGET_PPC64)
be147d08 3964GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3965{
3966#if defined(CONFIG_USER_ONLY)
e1833e1f 3967 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3968#else
3969 if (unlikely(!ctx->supervisor)) {
e1833e1f 3970 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3971 return;
3972 }
f78fb44e 3973 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3974 if (ctx->opcode & 0x00010000) {
3975 /* Special form that does not need any synchronisation */
3976 gen_op_update_riee();
3977 } else {
056b05f8
JM		 3978 /* XXX: we need to update nip before the store
3979 * if we enter power saving mode, we will exit the loop
3980 * directly from ppc_store_msr
3981 */
be147d08 3982 gen_update_nip(ctx, ctx->nip);
6676f424 3983 gen_op_store_msr();
be147d08
JM		 3984 /* Must stop the translation as machine state (may have) changed */
3985 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3986 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3987 }
426613db
JM		 3988#endif
3989}
3990#endif
3991
79aceca5
FB		 3992GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3993{
9a64fbe4 3994#if defined(CONFIG_USER_ONLY)
e1833e1f 3995 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3996#else
76a66253 3997 if (unlikely(!ctx->supervisor)) {
e1833e1f 3998 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3999 return;
9a64fbe4 4000 }
f78fb44e 4001 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4002 if (ctx->opcode & 0x00010000) {
4003 /* Special form that does not need any synchronisation */
4004 gen_op_update_riee();
4005 } else {
056b05f8
JM		 4006 /* XXX: we need to update nip before the store
4007 * if we enter power saving mode, we will exit the loop
4008 * directly from ppc_store_msr
4009 */
be147d08 4010 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4011#if defined(TARGET_PPC64)
be147d08 4012 if (!ctx->sf_mode)
6676f424 4013 gen_op_store_msr_32();
be147d08 4014 else
d9bce9d9 4015#endif
6676f424 4016 gen_op_store_msr();
be147d08
JM		 4017 /* Must stop the translation as machine state (may have) changed */
4018 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 4019 ctx->exception = POWERPC_EXCP_STOP;
be147d08 4020 }
9a64fbe4 4021#endif
79aceca5
FB		 4022}
4023
4024/* mtspr */
4025GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4026{
3fc6c082 4027 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 4028 uint32_t sprn = SPR(ctx->opcode);
4029
3fc6c082 4030#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 4031 if (ctx->supervisor == 2)
4032 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 4033 else if (ctx->supervisor)
3fc6c082
FB		 4034 write_cb = ctx->spr_cb[sprn].oea_write;
4035 else
9a64fbe4 4036#endif
3fc6c082 4037 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4038 if (likely(write_cb != NULL)) {
4039 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 4040 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 4041 (*write_cb)(ctx, sprn);
4042 } else {
4043 /* Privilege exception */
4a057712 4044 if (loglevel != 0) {
077fc206
JM		 4045 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4046 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4047 }
077fc206
JM		 4048 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4049 sprn, sprn, ctx->nip);
e1833e1f 4050 GEN_EXCP_PRIVREG(ctx);
76a66253 4051 }
3fc6c082
FB		 4052 } else {
4053 /* Not defined */
4a057712 4054 if (loglevel != 0) {
077fc206
JM		 4055 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4056 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4057 }
077fc206
JM		 4058 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4059 sprn, sprn, ctx->nip);
e1833e1f
JM		 4060 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4061 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 4062 }
79aceca5
FB		 4063}
4064
4065/*** Cache management ***/
79aceca5 4066/* dcbf */
0db1b20e 4067GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4068{
dac454af 4069 /* XXX: specification says this is treated as a load by the MMU */
a7812ae4 4070 TCGv t0 = tcg_temp_new();
a7859e89 4071 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4072 gen_addr_reg_index(t0, ctx);
4073 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4074 tcg_temp_free(t0);
79aceca5
FB		 4075}
4076
4077/* dcbi (Supervisor only) */
9a64fbe4 4078GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4079{
a541f297 4080#if defined(CONFIG_USER_ONLY)
e1833e1f 4081 GEN_EXCP_PRIVOPC(ctx);
a541f297 4082#else
b61f2753 4083 TCGv EA, val;
76a66253 4084 if (unlikely(!ctx->supervisor)) {
e1833e1f 4085 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4086 return;
9a64fbe4 4087 }
a7812ae4 4088 EA = tcg_temp_new();
a7859e89 4089 gen_set_access_type(ACCESS_CACHE);
b61f2753 4090 gen_addr_reg_index(EA, ctx);
a7812ae4 4091 val = tcg_temp_new();
76a66253 4092 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 4093 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4094 gen_qemu_st8(val, EA, ctx->mem_idx);
4095 tcg_temp_free(val);
4096 tcg_temp_free(EA);
a541f297 4097#endif
79aceca5
FB		 4098}
4099
4100/* dcdst */
9a64fbe4 4101GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4102{
76a66253 4103 /* XXX: specification say this is treated as a load by the MMU */
a7812ae4 4104 TCGv t0 = tcg_temp_new();
a7859e89 4105 gen_set_access_type(ACCESS_CACHE);
fea0c503
AJ		 4106 gen_addr_reg_index(t0, ctx);
4107 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4108 tcg_temp_free(t0);
79aceca5
FB		 4109}
4110
4111/* dcbt */
0db1b20e 4112GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4113{
0db1b20e 4114 /* interpreted as no-op */
76a66253
JM		 4115 /* XXX: specification say this is treated as a load by the MMU
4116 * but does not generate any exception
4117 */
79aceca5
FB		 4118}
4119
4120/* dcbtst */
0db1b20e 4121GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4122{
0db1b20e 4123 /* interpreted as no-op */
76a66253
JM		 4124 /* XXX: specification say this is treated as a load by the MMU
4125 * but does not generate any exception
4126 */
79aceca5
FB		 4127}
4128
4129/* dcbz */
d63001d1 4130GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4131{
799a8c8d
AJ		 4132 TCGv t0 = tcg_temp_new();
4133 gen_addr_reg_index(t0, ctx);
4134 /* NIP cannot be restored if the memory exception comes from an helper */
4135 gen_update_nip(ctx, ctx->nip - 4);
4136 gen_helper_dcbz(t0);
4137 tcg_temp_free(t0);
d63001d1
JM		 4138}
4139
c7697e1f 4140GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4141{
799a8c8d
AJ		 4142 TCGv t0 = tcg_temp_new();
4143 gen_addr_reg_index(t0, ctx);
4144 /* NIP cannot be restored if the memory exception comes from an helper */
4145 gen_update_nip(ctx, ctx->nip - 4);
d63001d1 4146 if (ctx->opcode & 0x00200000)
799a8c8d 4147 gen_helper_dcbz(t0);
d63001d1 4148 else
799a8c8d
AJ		 4149 gen_helper_dcbz_970(t0);
4150 tcg_temp_free(t0);
79aceca5
FB		 4151}
4152
4153/* icbi */
1b413d55 4154GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4155{
37d269df 4156 TCGv t0 = tcg_temp_new();
30032c94
JM		 4157 /* NIP cannot be restored if the memory exception comes from an helper */
4158 gen_update_nip(ctx, ctx->nip - 4);
37d269df
AJ		 4159 gen_addr_reg_index(t0, ctx);
4160 gen_helper_icbi(t0);
4161 tcg_temp_free(t0);
79aceca5
FB		 4162}
4163
4164/* Optional: */
4165/* dcba */
a750fc0b 4166GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4167{
0db1b20e
JM		 4168 /* interpreted as no-op */
4169 /* XXX: specification say this is treated as a store by the MMU
4170 * but does not generate any exception
4171 */
79aceca5
FB		 4172}
4173
4174/*** Segment register manipulation ***/
4175/* Supervisor only: */
4176/* mfsr */
4177GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4178{
9a64fbe4 4179#if defined(CONFIG_USER_ONLY)
e1833e1f 4180 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4181#else
76a66253 4182 if (unlikely(!ctx->supervisor)) {
e1833e1f 4183 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4184 return;
9a64fbe4 4185 }
86c581dc 4186 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4187 gen_op_load_sr();
f78fb44e 4188 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4189#endif
79aceca5
FB		 4190}
4191
4192/* mfsrin */
9a64fbe4 4193GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4194{
9a64fbe4 4195#if defined(CONFIG_USER_ONLY)
e1833e1f 4196 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4197#else
76a66253 4198 if (unlikely(!ctx->supervisor)) {
e1833e1f 4199 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4200 return;
9a64fbe4 4201 }
f78fb44e 4202 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4203 gen_op_srli_T1(28);
4204 gen_op_load_sr();
f78fb44e 4205 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4206#endif
79aceca5
FB		 4207}
4208
4209/* mtsr */
e63c59cb 4210GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4211{
9a64fbe4 4212#if defined(CONFIG_USER_ONLY)
e1833e1f 4213 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4214#else
76a66253 4215 if (unlikely(!ctx->supervisor)) {
e1833e1f 4216 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4217 return;
9a64fbe4 4218 }
f78fb44e 4219 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4220 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4221 gen_op_store_sr();
9a64fbe4 4222#endif
79aceca5
FB		 4223}
4224
4225/* mtsrin */
9a64fbe4 4226GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4227{
9a64fbe4 4228#if defined(CONFIG_USER_ONLY)
e1833e1f 4229 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4230#else
76a66253 4231 if (unlikely(!ctx->supervisor)) {
e1833e1f 4232 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4233 return;
9a64fbe4 4234 }
f78fb44e
AJ		 4235 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4236 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4237 gen_op_srli_T1(28);
4238 gen_op_store_sr();
9a64fbe4 4239#endif
79aceca5
FB		 4240}
4241
12de9a39
JM		 4242#if defined(TARGET_PPC64)
4243/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4244/* mfsr */
c7697e1f 4245GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4246{
4247#if defined(CONFIG_USER_ONLY)
4248 GEN_EXCP_PRIVREG(ctx);
4249#else
4250 if (unlikely(!ctx->supervisor)) {
4251 GEN_EXCP_PRIVREG(ctx);
4252 return;
4253 }
86c581dc 4254 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4255 gen_op_load_slb();
f78fb44e 4256 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4257#endif
4258}
4259
4260/* mfsrin */
c7697e1f
JM		 4261GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4262 PPC_SEGMENT_64B)
12de9a39
JM		 4263{
4264#if defined(CONFIG_USER_ONLY)
4265 GEN_EXCP_PRIVREG(ctx);
4266#else
4267 if (unlikely(!ctx->supervisor)) {
4268 GEN_EXCP_PRIVREG(ctx);
4269 return;
4270 }
f78fb44e 4271 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4272 gen_op_srli_T1(28);
4273 gen_op_load_slb();
f78fb44e 4274 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4275#endif
4276}
4277
4278/* mtsr */
c7697e1f 4279GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4280{
4281#if defined(CONFIG_USER_ONLY)
4282 GEN_EXCP_PRIVREG(ctx);
4283#else
4284 if (unlikely(!ctx->supervisor)) {
4285 GEN_EXCP_PRIVREG(ctx);
4286 return;
4287 }
f78fb44e 4288 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4289 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4290 gen_op_store_slb();
4291#endif
4292}
4293
4294/* mtsrin */
c7697e1f
JM		 4295GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4296 PPC_SEGMENT_64B)
12de9a39
JM		 4297{
4298#if defined(CONFIG_USER_ONLY)
4299 GEN_EXCP_PRIVREG(ctx);
4300#else
4301 if (unlikely(!ctx->supervisor)) {
4302 GEN_EXCP_PRIVREG(ctx);
4303 return;
4304 }
f78fb44e
AJ		 4305 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4306 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4307 gen_op_srli_T1(28);
4308 gen_op_store_slb();
4309#endif
4310}
4311#endif /* defined(TARGET_PPC64) */
4312
79aceca5
FB		 4313/*** Lookaside buffer management ***/
4314/* Optional & supervisor only: */
4315/* tlbia */
3fc6c082 4316GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4317{
9a64fbe4 4318#if defined(CONFIG_USER_ONLY)
e1833e1f 4319 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4320#else
76a66253 4321 if (unlikely(!ctx->supervisor)) {
e1833e1f 4322 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4323 return;
9a64fbe4
FB		 4324 }
4325 gen_op_tlbia();
4326#endif
79aceca5
FB		 4327}
4328
4329/* tlbie */
76a66253 4330GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4331{
9a64fbe4 4332#if defined(CONFIG_USER_ONLY)
e1833e1f 4333 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4334#else
76a66253 4335 if (unlikely(!ctx->supervisor)) {
e1833e1f 4336 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4337 return;
9a64fbe4 4338 }
f78fb44e 4339 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4340#if defined(TARGET_PPC64)
4341 if (ctx->sf_mode)
4342 gen_op_tlbie_64();
4343 else
4344#endif
4345 gen_op_tlbie();
9a64fbe4 4346#endif
79aceca5
FB		 4347}
4348
4349/* tlbsync */
76a66253 4350GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4351{
9a64fbe4 4352#if defined(CONFIG_USER_ONLY)
e1833e1f 4353 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4354#else
76a66253 4355 if (unlikely(!ctx->supervisor)) {
e1833e1f 4356 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4357 return;
9a64fbe4
FB		 4358 }
4359 /* This has no effect: it should ensure that all previous
4360 * tlbie have completed
4361 */
e1833e1f 4362 GEN_STOP(ctx);
9a64fbe4 4363#endif
79aceca5
FB		 4364}
4365
426613db
JM		 4366#if defined(TARGET_PPC64)
4367/* slbia */
4368GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4369{
4370#if defined(CONFIG_USER_ONLY)
e1833e1f 4371 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4372#else
4373 if (unlikely(!ctx->supervisor)) {
e1833e1f 4374 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4375 return;
4376 }
4377 gen_op_slbia();
426613db
JM		 4378#endif
4379}
4380
4381/* slbie */
4382GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4383{
4384#if defined(CONFIG_USER_ONLY)
e1833e1f 4385 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4386#else
4387 if (unlikely(!ctx->supervisor)) {
e1833e1f 4388 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4389 return;
4390 }
f78fb44e 4391 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4392 gen_op_slbie();
426613db
JM		 4393#endif
4394}
4395#endif
4396
79aceca5
FB		 4397/*** External control ***/
4398/* Optional: */
111bfab3 4399/* eciwx */
79aceca5
FB		 4400GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4401{
fa407c03
AJ		 4402 /* Should check EAR[E] ! */
4403 TCGv t0 = tcg_temp_new();
a7859e89 4404 gen_set_access_type(ACCESS_RES);
fa407c03
AJ		 4405 gen_addr_reg_index(t0, ctx);
4406 gen_check_align(ctx, t0, 0x03);
4407 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
4408 tcg_temp_free(t0);
76a66253
JM		 4409}
4410
4411/* ecowx */
4412GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4413{
fa407c03
AJ		 4414 /* Should check EAR[E] ! */
4415 TCGv t0 = tcg_temp_new();
4416 gen_set_access_type(ACCESS_RES);
4417 gen_addr_reg_index(t0, ctx);
4418 gen_check_align(ctx, t0, 0x03);
4419 gen_qemu_st32(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
4420 tcg_temp_free(t0);
76a66253
JM		 4421}
4422
4423/* PowerPC 601 specific instructions */
4424/* abs - abs. */
4425GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4426{
f78fb44e 4427 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4428 gen_op_POWER_abs();
f78fb44e 4429 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4430 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4431 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4432}
4433
4434/* abso - abso. */
4435GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4436{
f78fb44e 4437 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4438 gen_op_POWER_abso();
f78fb44e 4439 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4440 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4441 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4442}
4443
4444/* clcs */
a750fc0b 4445GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4446{
f78fb44e 4447 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4448 gen_op_POWER_clcs();
c7697e1f 4449 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4450 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4451}
4452
4453/* div - div. */
4454GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4455{
f78fb44e
AJ		 4456 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4457 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4458 gen_op_POWER_div();
f78fb44e 4459 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4460 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4461 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4462}
4463
4464/* divo - divo. */
4465GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4466{
f78fb44e
AJ		 4467 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4468 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4469 gen_op_POWER_divo();
f78fb44e 4470 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4471 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4472 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4473}
4474
4475/* divs - divs. */
4476GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4477{
f78fb44e
AJ		 4478 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4479 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4480 gen_op_POWER_divs();
f78fb44e 4481 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4482 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4483 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4484}
4485
4486/* divso - divso. */
4487GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4488{
f78fb44e
AJ		 4489 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4490 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4491 gen_op_POWER_divso();
f78fb44e 4492 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4493 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4494 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4495}
4496
4497/* doz - doz. */
4498GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4499{
f78fb44e
AJ		 4500 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4501 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4502 gen_op_POWER_doz();
f78fb44e 4503 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4504 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4505 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4506}
4507
4508/* dozo - dozo. */
4509GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4510{
f78fb44e
AJ		 4511 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4512 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4513 gen_op_POWER_dozo();
f78fb44e 4514 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4515 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4516 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4517}
4518
4519/* dozi */
4520GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4521{
f78fb44e 4522 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4523 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4524 gen_op_POWER_doz();
f78fb44e 4525 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4526}
4527
76a66253
JM		 4528/* lscbx - lscbx. */
4529GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4530{
bdb4b689
AJ		 4531 TCGv t0 = tcg_temp_new();
4532 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4533 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4534 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4535
bdb4b689 4536 gen_addr_reg_index(t0, ctx);
76a66253 4537 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4538 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4539 gen_helper_lscbx(t0, t0, t1, t2, t3);
4540 tcg_temp_free_i32(t1);
4541 tcg_temp_free_i32(t2);
4542 tcg_temp_free_i32(t3);
3d7b417e 4543 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4544 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4545 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4546 gen_set_Rc0(ctx, t0);
4547 tcg_temp_free(t0);
76a66253
JM		 4548}
4549
4550/* maskg - maskg. */
4551GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4552{
f78fb44e
AJ		 4553 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4554 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4555 gen_op_POWER_maskg();
f78fb44e 4556 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4557 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4558 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4559}
4560
4561/* maskir - maskir. */
4562GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4563{
f78fb44e
AJ		 4564 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4565 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4566 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4567 gen_op_POWER_maskir();
f78fb44e 4568 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4569 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4570 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4571}
4572
4573/* mul - mul. */
4574GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4575{
f78fb44e
AJ		 4576 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4577 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4578 gen_op_POWER_mul();
f78fb44e 4579 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4580 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4581 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4582}
4583
4584/* mulo - mulo. */
4585GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4586{
f78fb44e
AJ		 4587 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4588 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4589 gen_op_POWER_mulo();
f78fb44e 4590 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4591 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4592 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4593}
4594
4595/* nabs - nabs. */
4596GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4597{
f78fb44e 4598 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4599 gen_op_POWER_nabs();
f78fb44e 4600 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4601 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4602 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4603}
4604
4605/* nabso - nabso. */
4606GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4607{
f78fb44e 4608 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4609 gen_op_POWER_nabso();
f78fb44e 4610 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4611 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4612 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4613}
4614
4615/* rlmi - rlmi. */
4616GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4617{
4618 uint32_t mb, me;
4619
4620 mb = MB(ctx->opcode);
4621 me = ME(ctx->opcode);
f78fb44e
AJ		 4622 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4623 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4624 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4625 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4626 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4627 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4628 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4629}
4630
4631/* rrib - rrib. */
4632GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4633{
f78fb44e
AJ		 4634 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4635 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4636 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4637 gen_op_POWER_rrib();
f78fb44e 4638 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4639 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4640 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4641}
4642
4643/* sle - sle. */
4644GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4645{
f78fb44e
AJ		 4646 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4647 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4648 gen_op_POWER_sle();
f78fb44e 4649 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4650 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4651 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4652}
4653
4654/* sleq - sleq. */
4655GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4656{
f78fb44e
AJ		 4657 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4658 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4659 gen_op_POWER_sleq();
f78fb44e 4660 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4661 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4662 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4663}
4664
4665/* sliq - sliq. */
4666GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4667{
f78fb44e 4668 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4669 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4670 gen_op_POWER_sle();
f78fb44e 4671 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4672 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4673 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4674}
4675
4676/* slliq - slliq. */
4677GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4678{
f78fb44e 4679 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4680 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4681 gen_op_POWER_sleq();
f78fb44e 4682 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4683 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4684 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4685}
4686
4687/* sllq - sllq. */
4688GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4689{
f78fb44e
AJ		 4690 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4691 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4692 gen_op_POWER_sllq();
f78fb44e 4693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4694 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4695 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4696}
4697
4698/* slq - slq. */
4699GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4700{
f78fb44e
AJ		 4701 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4702 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4703 gen_op_POWER_slq();
f78fb44e 4704 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4705 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4706 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4707}
4708
d9bce9d9 4709/* sraiq - sraiq. */
76a66253
JM		 4710GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4711{
f78fb44e 4712 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4713 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4714 gen_op_POWER_sraq();
f78fb44e 4715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4716 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4717 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4718}
4719
4720/* sraq - sraq. */
4721GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4722{
f78fb44e
AJ		 4723 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4724 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4725 gen_op_POWER_sraq();
f78fb44e 4726 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4727 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4728 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4729}
4730
4731/* sre - sre. */
4732GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4733{
f78fb44e
AJ		 4734 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4735 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4736 gen_op_POWER_sre();
f78fb44e 4737 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4738 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4739 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4740}
4741
4742/* srea - srea. */
4743GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4744{
f78fb44e
AJ		 4745 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4746 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4747 gen_op_POWER_srea();
f78fb44e 4748 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4749 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4750 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4751}
4752
4753/* sreq */
4754GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4755{
f78fb44e
AJ		 4756 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4757 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4758 gen_op_POWER_sreq();
f78fb44e 4759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4760 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4761 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4762}
4763
4764/* sriq */
4765GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4766{
f78fb44e 4767 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4768 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4769 gen_op_POWER_srq();
f78fb44e 4770 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4771 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4772 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4773}
4774
4775/* srliq */
4776GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4777{
f78fb44e
AJ		 4778 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4779 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4780 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4781 gen_op_POWER_srlq();
f78fb44e 4782 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4783 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4784 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4785}
4786
4787/* srlq */
4788GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4789{
f78fb44e
AJ		 4790 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4791 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4792 gen_op_POWER_srlq();
f78fb44e 4793 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4794 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4795 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4796}
4797
4798/* srq */
4799GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4800{
f78fb44e
AJ		 4801 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4802 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4803 gen_op_POWER_srq();
f78fb44e 4804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4805 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4806 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4807}
4808
4809/* PowerPC 602 specific instructions */
4810/* dsa */
4811GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4812{
4813 /* XXX: TODO */
e1833e1f 4814 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4815}
4816
4817/* esa */
4818GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4819{
4820 /* XXX: TODO */
e1833e1f 4821 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4822}
4823
4824/* mfrom */
4825GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4826{
4827#if defined(CONFIG_USER_ONLY)
e1833e1f 4828 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4829#else
4830 if (unlikely(!ctx->supervisor)) {
e1833e1f 4831 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4832 return;
4833 }
cf02a65c 4834 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4835#endif
4836}
4837
4838/* 602 - 603 - G2 TLB management */
4839/* tlbld */
c7697e1f 4840GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4841{
4842#if defined(CONFIG_USER_ONLY)
e1833e1f 4843 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4844#else
4845 if (unlikely(!ctx->supervisor)) {
e1833e1f 4846 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4847 return;
4848 }
0f3955e2 4849 gen_helper_load_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4850#endif
4851}
4852
4853/* tlbli */
c7697e1f 4854GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4855{
4856#if defined(CONFIG_USER_ONLY)
e1833e1f 4857 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4858#else
4859 if (unlikely(!ctx->supervisor)) {
e1833e1f 4860 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4861 return;
4862 }
0f3955e2 4863 gen_helper_load_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4864#endif
4865}
4866
7dbe11ac
JM		 4867/* 74xx TLB management */
4868/* tlbld */
c7697e1f 4869GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4870{
4871#if defined(CONFIG_USER_ONLY)
4872 GEN_EXCP_PRIVOPC(ctx);
4873#else
4874 if (unlikely(!ctx->supervisor)) {
4875 GEN_EXCP_PRIVOPC(ctx);
4876 return;
4877 }
0f3955e2 4878 gen_helper_load_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4879#endif
4880}
4881
4882/* tlbli */
c7697e1f 4883GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4884{
4885#if defined(CONFIG_USER_ONLY)
4886 GEN_EXCP_PRIVOPC(ctx);
4887#else
4888 if (unlikely(!ctx->supervisor)) {
4889 GEN_EXCP_PRIVOPC(ctx);
4890 return;
4891 }
0f3955e2 4892 gen_helper_load_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4893#endif
4894}
4895
76a66253
JM		 4896/* POWER instructions not in PowerPC 601 */
4897/* clf */
4898GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4899{
4900 /* Cache line flush: implemented as no-op */
4901}
4902
4903/* cli */
4904GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4905{
7f75ffd3 4906 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4907#if defined(CONFIG_USER_ONLY)
e1833e1f 4908 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4909#else
4910 if (unlikely(!ctx->supervisor)) {
e1833e1f 4911 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4912 return;
4913 }
4914#endif
4915}
4916
4917/* dclst */
4918GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4919{
4920 /* Data cache line store: treated as no-op */
4921}
4922
4923GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4924{
4925#if defined(CONFIG_USER_ONLY)
e1833e1f 4926 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4927#else
4928 if (unlikely(!ctx->supervisor)) {
e1833e1f 4929 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4930 return;
4931 }
4932 int ra = rA(ctx->opcode);
4933 int rd = rD(ctx->opcode);
4934
e2be8d8d 4935 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4936 gen_op_POWER_mfsri();
f78fb44e 4937 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4938 if (ra != 0 && ra != rd)
f78fb44e 4939 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4940#endif
4941}
4942
4943GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4944{
4945#if defined(CONFIG_USER_ONLY)
e1833e1f 4946 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4947#else
4948 if (unlikely(!ctx->supervisor)) {
e1833e1f 4949 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4950 return;
4951 }
e2be8d8d 4952 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4953 gen_op_POWER_rac();
f78fb44e 4954 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4955#endif
4956}
4957
4958GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4959{
4960#if defined(CONFIG_USER_ONLY)
e1833e1f 4961 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4962#else
4963 if (unlikely(!ctx->supervisor)) {
e1833e1f 4964 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4965 return;
4966 }
4967 gen_op_POWER_rfsvc();
e1833e1f 4968 GEN_SYNC(ctx);
76a66253
JM		 4969#endif
4970}
4971
4972/* svc is not implemented for now */
4973
4974/* POWER2 specific instructions */
4975/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 4976
4977/* lfq */
4978GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4979{
01a4afeb
AJ		 4980 int rd = rD(ctx->opcode);
4981 TCGv t0 = tcg_temp_new();
4982 gen_addr_imm_index(t0, ctx, 0);
4983 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
4984 tcg_gen_addi_tl(t0, t0, 8);
4985 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
4986 tcg_temp_free(t0);
76a66253
JM		 4987}
4988
4989/* lfqu */
4990GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4991{
4992 int ra = rA(ctx->opcode);
01a4afeb
AJ		 4993 int rd = rD(ctx->opcode);
4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 gen_addr_imm_index(t0, ctx, 0);
4997 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
4998 tcg_gen_addi_tl(t1, t0, 8);
4999 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5000 if (ra != 0)
01a4afeb
AJ		 5001 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5002 tcg_temp_free(t0);
5003 tcg_temp_free(t1);
76a66253
JM		 5004}
5005
5006/* lfqux */
5007GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5008{
5009 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5010 int rd = rD(ctx->opcode);
5011 TCGv t0 = tcg_temp_new();
5012 TCGv t1 = tcg_temp_new();
5013 gen_addr_reg_index(t0, ctx);
5014 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5015 tcg_gen_addi_tl(t1, t0, 8);
5016 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5017 if (ra != 0)
01a4afeb
AJ		 5018 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5019 tcg_temp_free(t0);
5020 tcg_temp_free(t1);
76a66253
JM		 5021}
5022
5023/* lfqx */
5024GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5025{
01a4afeb
AJ		 5026 int rd = rD(ctx->opcode);
5027 TCGv t0 = tcg_temp_new();
5028 gen_addr_reg_index(t0, ctx);
5029 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5030 tcg_gen_addi_tl(t0, t0, 8);
5031 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5032 tcg_temp_free(t0);
76a66253
JM		 5033}
5034
5035/* stfq */
5036GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5037{
01a4afeb
AJ		 5038 int rd = rD(ctx->opcode);
5039 TCGv t0 = tcg_temp_new();
5040 gen_addr_imm_index(t0, ctx, 0);
5041 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5042 tcg_gen_addi_tl(t0, t0, 8);
5043 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5044 tcg_temp_free(t0);
76a66253
JM		 5045}
5046
5047/* stfqu */
5048GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5049{
5050 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5051 int rd = rD(ctx->opcode);
5052 TCGv t0 = tcg_temp_new();
5053 TCGv t1 = tcg_temp_new();
5054 gen_addr_imm_index(t0, ctx, 0);
5055 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5056 tcg_gen_addi_tl(t1, t0, 8);
5057 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5058 if (ra != 0)
01a4afeb
AJ		 5059 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5060 tcg_temp_free(t0);
5061 tcg_temp_free(t1);
76a66253
JM		 5062}
5063
5064/* stfqux */
5065GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5066{
5067 int ra = rA(ctx->opcode);
01a4afeb
AJ		 5068 int rd = rD(ctx->opcode);
5069 TCGv t0 = tcg_temp_new();
5070 TCGv t1 = tcg_temp_new();
5071 gen_addr_reg_index(t0, ctx);
5072 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5073 tcg_gen_addi_tl(t1, t0, 8);
5074 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
76a66253 5075 if (ra != 0)
01a4afeb
AJ		 5076 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5077 tcg_temp_free(t0);
5078 tcg_temp_free(t1);
76a66253
JM		 5079}
5080
5081/* stfqx */
5082GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5083{
01a4afeb
AJ		 5084 int rd = rD(ctx->opcode);
5085 TCGv t0 = tcg_temp_new();
5086 gen_addr_reg_index(t0, ctx);
5087 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5088 tcg_gen_addi_tl(t0, t0, 8);
5089 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5090 tcg_temp_free(t0);
76a66253
JM		 5091}
5092
5093/* BookE specific instructions */
2662a059 5094/* XXX: not implemented on 440 ? */
05332d70 5095GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5096{
5097 /* XXX: TODO */
e1833e1f 5098 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5099}
5100
2662a059 5101/* XXX: not implemented on 440 ? */
05332d70 5102GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5103{
5104#if defined(CONFIG_USER_ONLY)
e1833e1f 5105 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5106#else
5107 if (unlikely(!ctx->supervisor)) {
e1833e1f 5108 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5109 return;
5110 }
e2be8d8d 5111 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5112 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5113#if defined(TARGET_PPC64)
5114 if (ctx->sf_mode)
5115 gen_op_tlbie_64();
5116 else
5117#endif
5118 gen_op_tlbie();
76a66253
JM		 5119#endif
5120}
5121
5122/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5123static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5124 int opc2, int opc3,
5125 int ra, int rb, int rt, int Rc)
76a66253 5126{
182608d4
AJ		 5127 TCGv t0, t1;
5128
a7812ae4
PB		 5129 t0 = tcg_temp_local_new();
5130 t1 = tcg_temp_local_new();
182608d4 5131
76a66253
JM		 5132 switch (opc3 & 0x0D) {
5133 case 0x05:
5134 /* macchw - macchw. - macchwo - macchwo. */
5135 /* macchws - macchws. - macchwso - macchwso. */
5136 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5137 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5138 /* mulchw - mulchw. */
182608d4
AJ		 5139 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5140 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5141 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5142 break;
5143 case 0x04:
5144 /* macchwu - macchwu. - macchwuo - macchwuo. */
5145 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5146 /* mulchwu - mulchwu. */
182608d4
AJ		 5147 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5148 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5149 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5150 break;
5151 case 0x01:
5152 /* machhw - machhw. - machhwo - machhwo. */
5153 /* machhws - machhws. - machhwso - machhwso. */
5154 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5155 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5156 /* mulhhw - mulhhw. */
182608d4
AJ		 5157 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5158 tcg_gen_ext16s_tl(t0, t0);
5159 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5160 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5161 break;
5162 case 0x00:
5163 /* machhwu - machhwu. - machhwuo - machhwuo. */
5164 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5165 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5166 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5167 tcg_gen_ext16u_tl(t0, t0);
5168 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5169 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5170 break;
5171 case 0x0D:
5172 /* maclhw - maclhw. - maclhwo - maclhwo. */
5173 /* maclhws - maclhws. - maclhwso - maclhwso. */
5174 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5175 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5176 /* mullhw - mullhw. */
182608d4
AJ		 5177 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5178 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5179 break;
5180 case 0x0C:
5181 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5182 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5183 /* mullhwu - mullhwu. */
182608d4
AJ		 5184 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5185 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5186 break;
5187 }
76a66253 5188 if (opc2 & 0x04) {
182608d4
AJ		 5189 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5190 tcg_gen_mul_tl(t1, t0, t1);
5191 if (opc2 & 0x02) {
5192 /* nmultiply-and-accumulate (0x0E) */
5193 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5194 } else {
5195 /* multiply-and-accumulate (0x0C) */
5196 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5197 }
5198
5199 if (opc3 & 0x12) {
5200 /* Check overflow and/or saturate */
5201 int l1 = gen_new_label();
5202
5203 if (opc3 & 0x10) {
5204 /* Start with XER OV disabled, the most likely case */
5205 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5206 }
5207 if (opc3 & 0x01) {
5208 /* Signed */
5209 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5210 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5211 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5212 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5213 if (opc3 & 0x02) {
182608d4
AJ		 5214 /* Saturate */
5215 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5216 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5217 }
5218 } else {
5219 /* Unsigned */
5220 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5221 if (opc3 & 0x02) {
182608d4
AJ		 5222 /* Saturate */
5223 tcg_gen_movi_tl(t0, UINT32_MAX);
5224 }
5225 }
5226 if (opc3 & 0x10) {
5227 /* Check overflow */
5228 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5229 }
5230 gen_set_label(l1);
5231 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5232 }
5233 } else {
5234 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5235 }
182608d4
AJ		 5236 tcg_temp_free(t0);
5237 tcg_temp_free(t1);
76a66253
JM		 5238 if (unlikely(Rc) != 0) {
5239 /* Update Rc0 */
182608d4 5240 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5241 }
5242}
5243
a750fc0b
JM		 5244#define GEN_MAC_HANDLER(name, opc2, opc3) \
5245GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5246{ \
5247 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5248 rD(ctx->opcode), Rc(ctx->opcode)); \
5249}
5250
5251/* macchw - macchw. */
a750fc0b 5252GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5253/* macchwo - macchwo. */
a750fc0b 5254GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5255/* macchws - macchws. */
a750fc0b 5256GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5257/* macchwso - macchwso. */
a750fc0b 5258GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5259/* macchwsu - macchwsu. */
a750fc0b 5260GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5261/* macchwsuo - macchwsuo. */
a750fc0b 5262GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5263/* macchwu - macchwu. */
a750fc0b 5264GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5265/* macchwuo - macchwuo. */
a750fc0b 5266GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5267/* machhw - machhw. */
a750fc0b 5268GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5269/* machhwo - machhwo. */
a750fc0b 5270GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5271/* machhws - machhws. */
a750fc0b 5272GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5273/* machhwso - machhwso. */
a750fc0b 5274GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5275/* machhwsu - machhwsu. */
a750fc0b 5276GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5277/* machhwsuo - machhwsuo. */
a750fc0b 5278GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5279/* machhwu - machhwu. */
a750fc0b 5280GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5281/* machhwuo - machhwuo. */
a750fc0b 5282GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5283/* maclhw - maclhw. */
a750fc0b 5284GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5285/* maclhwo - maclhwo. */
a750fc0b 5286GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5287/* maclhws - maclhws. */
a750fc0b 5288GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5289/* maclhwso - maclhwso. */
a750fc0b 5290GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5291/* maclhwu - maclhwu. */
a750fc0b 5292GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5293/* maclhwuo - maclhwuo. */
a750fc0b 5294GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5295/* maclhwsu - maclhwsu. */
a750fc0b 5296GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5297/* maclhwsuo - maclhwsuo. */
a750fc0b 5298GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5299/* nmacchw - nmacchw. */
a750fc0b 5300GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5301/* nmacchwo - nmacchwo. */
a750fc0b 5302GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5303/* nmacchws - nmacchws. */
a750fc0b 5304GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5305/* nmacchwso - nmacchwso. */
a750fc0b 5306GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5307/* nmachhw - nmachhw. */
a750fc0b 5308GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5309/* nmachhwo - nmachhwo. */
a750fc0b 5310GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5311/* nmachhws - nmachhws. */
a750fc0b 5312GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5313/* nmachhwso - nmachhwso. */
a750fc0b 5314GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5315/* nmaclhw - nmaclhw. */
a750fc0b 5316GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5317/* nmaclhwo - nmaclhwo. */
a750fc0b 5318GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5319/* nmaclhws - nmaclhws. */
a750fc0b 5320GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5321/* nmaclhwso - nmaclhwso. */
a750fc0b 5322GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5323
5324/* mulchw - mulchw. */
a750fc0b 5325GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5326/* mulchwu - mulchwu. */
a750fc0b 5327GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5328/* mulhhw - mulhhw. */
a750fc0b 5329GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5330/* mulhhwu - mulhhwu. */
a750fc0b 5331GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5332/* mullhw - mullhw. */
a750fc0b 5333GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5334/* mullhwu - mullhwu. */
a750fc0b 5335GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5336
5337/* mfdcr */
05332d70 5338GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5339{
5340#if defined(CONFIG_USER_ONLY)
e1833e1f 5341 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5342#else
5343 uint32_t dcrn = SPR(ctx->opcode);
5344
5345 if (unlikely(!ctx->supervisor)) {
e1833e1f 5346 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5347 return;
5348 }
86c581dc 5349 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5350 gen_op_load_dcr();
f78fb44e 5351 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5352#endif
5353}
5354
5355/* mtdcr */
05332d70 5356GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5357{
5358#if defined(CONFIG_USER_ONLY)
e1833e1f 5359 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5360#else
5361 uint32_t dcrn = SPR(ctx->opcode);
5362
5363 if (unlikely(!ctx->supervisor)) {
e1833e1f 5364 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5365 return;
5366 }
86c581dc 5367 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5368 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5369 gen_op_store_dcr();
5370#endif
5371}
5372
5373/* mfdcrx */
2662a059 5374/* XXX: not implemented on 440 ? */
05332d70 5375GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5376{
5377#if defined(CONFIG_USER_ONLY)
e1833e1f 5378 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5379#else
5380 if (unlikely(!ctx->supervisor)) {
e1833e1f 5381 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5382 return;
5383 }
f78fb44e 5384 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5385 gen_op_load_dcr();
f78fb44e 5386 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5387 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5388#endif
5389}
5390
5391/* mtdcrx */
2662a059 5392/* XXX: not implemented on 440 ? */
05332d70 5393GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5394{
5395#if defined(CONFIG_USER_ONLY)
e1833e1f 5396 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5397#else
5398 if (unlikely(!ctx->supervisor)) {
e1833e1f 5399 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5400 return;
5401 }
f78fb44e
AJ		 5402 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5403 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5404 gen_op_store_dcr();
a750fc0b 5405 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5406#endif
5407}
5408
a750fc0b
JM		 5409/* mfdcrux (PPC 460) : user-mode access to DCR */
5410GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5411{
f78fb44e 5412 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5413 gen_op_load_dcr();
f78fb44e 5414 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5415 /* Note: Rc update flag set leads to undefined state of Rc0 */
5416}
5417
5418/* mtdcrux (PPC 460) : user-mode access to DCR */
5419GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5420{
f78fb44e
AJ		 5421 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5422 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5423 gen_op_store_dcr();
5424 /* Note: Rc update flag set leads to undefined state of Rc0 */
5425}
5426
76a66253
JM		 5427/* dccci */
5428GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5429{
5430#if defined(CONFIG_USER_ONLY)
e1833e1f 5431 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5432#else
5433 if (unlikely(!ctx->supervisor)) {
e1833e1f 5434 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5435 return;
5436 }
5437 /* interpreted as no-op */
5438#endif
5439}
5440
5441/* dcread */
5442GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5443{
5444#if defined(CONFIG_USER_ONLY)
e1833e1f 5445 GEN_EXCP_PRIVOPC(ctx);
76a66253 5446#else
b61f2753 5447 TCGv EA, val;
76a66253 5448 if (unlikely(!ctx->supervisor)) {
e1833e1f 5449 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5450 return;
5451 }
a7812ae4 5452 EA = tcg_temp_new();
a7859e89 5453 gen_set_access_type(ACCESS_CACHE);
b61f2753 5454 gen_addr_reg_index(EA, ctx);
a7812ae4 5455 val = tcg_temp_new();
b61f2753
AJ		 5456 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5457 tcg_temp_free(val);
5458 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5459 tcg_temp_free(EA);
76a66253
JM		 5460#endif
5461}
5462
5463/* icbt */
c7697e1f 5464GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5465{
5466 /* interpreted as no-op */
5467 /* XXX: specification say this is treated as a load by the MMU
5468 * but does not generate any exception
5469 */
5470}
5471
5472/* iccci */
5473GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5474{
5475#if defined(CONFIG_USER_ONLY)
e1833e1f 5476 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5477#else
5478 if (unlikely(!ctx->supervisor)) {
e1833e1f 5479 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5480 return;
5481 }
5482 /* interpreted as no-op */
5483#endif
5484}
5485
5486/* icread */
5487GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5488{
5489#if defined(CONFIG_USER_ONLY)
e1833e1f 5490 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5491#else
5492 if (unlikely(!ctx->supervisor)) {
e1833e1f 5493 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5494 return;
5495 }
5496 /* interpreted as no-op */
5497#endif
5498}
5499
5500/* rfci (supervisor only) */
c7697e1f 5501GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5502{
5503#if defined(CONFIG_USER_ONLY)
e1833e1f 5504 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5505#else
5506 if (unlikely(!ctx->supervisor)) {
e1833e1f 5507 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5508 return;
5509 }
5510 /* Restore CPU state */
5511 gen_op_40x_rfci();
e1833e1f 5512 GEN_SYNC(ctx);
a42bd6cc
JM		 5513#endif
5514}
5515
5516GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5517{
5518#if defined(CONFIG_USER_ONLY)
e1833e1f 5519 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5520#else
5521 if (unlikely(!ctx->supervisor)) {
e1833e1f 5522 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5523 return;
5524 }
5525 /* Restore CPU state */
5526 gen_op_rfci();
e1833e1f 5527 GEN_SYNC(ctx);
a42bd6cc
JM		 5528#endif
5529}
5530
5531/* BookE specific */
2662a059 5532/* XXX: not implemented on 440 ? */
05332d70 5533GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5534{
5535#if defined(CONFIG_USER_ONLY)
e1833e1f 5536 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5537#else
5538 if (unlikely(!ctx->supervisor)) {
e1833e1f 5539 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5540 return;
5541 }
5542 /* Restore CPU state */
a42bd6cc 5543 gen_op_rfdi();
e1833e1f 5544 GEN_SYNC(ctx);
76a66253
JM		 5545#endif
5546}
5547
2662a059 5548/* XXX: not implemented on 440 ? */
a750fc0b 5549GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5550{
5551#if defined(CONFIG_USER_ONLY)
e1833e1f 5552 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5553#else
5554 if (unlikely(!ctx->supervisor)) {
e1833e1f 5555 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5556 return;
5557 }
5558 /* Restore CPU state */
5559 gen_op_rfmci();
e1833e1f 5560 GEN_SYNC(ctx);
a42bd6cc
JM		 5561#endif
5562}
5eb7995e 5563
d9bce9d9 5564/* TLB management - PowerPC 405 implementation */
76a66253 5565/* tlbre */
c7697e1f 5566GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5567{
5568#if defined(CONFIG_USER_ONLY)
e1833e1f 5569 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5570#else
5571 if (unlikely(!ctx->supervisor)) {
e1833e1f 5572 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5573 return;
5574 }
5575 switch (rB(ctx->opcode)) {
5576 case 0:
f78fb44e 5577 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5578 gen_op_4xx_tlbre_hi();
f78fb44e 5579 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5580 break;
5581 case 1:
f78fb44e 5582 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5583 gen_op_4xx_tlbre_lo();
f78fb44e 5584 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5585 break;
5586 default:
e1833e1f 5587 GEN_EXCP_INVAL(ctx);
76a66253 5588 break;
9a64fbe4 5589 }
76a66253
JM		 5590#endif
5591}
5592
d9bce9d9 5593/* tlbsx - tlbsx. */
c7697e1f 5594GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5595{
5596#if defined(CONFIG_USER_ONLY)
e1833e1f 5597 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5598#else
5599 if (unlikely(!ctx->supervisor)) {
e1833e1f 5600 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5601 return;
5602 }
e2be8d8d 5603 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5604 gen_op_4xx_tlbsx();
76a66253 5605 if (Rc(ctx->opcode))
daf4f96e 5606 gen_op_4xx_tlbsx_check();
f78fb44e 5607 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5608#endif
79aceca5
FB		 5609}
5610
76a66253 5611/* tlbwe */
c7697e1f 5612GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5613{
76a66253 5614#if defined(CONFIG_USER_ONLY)
e1833e1f 5615 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5616#else
5617 if (unlikely(!ctx->supervisor)) {
e1833e1f 5618 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5619 return;
5620 }
5621 switch (rB(ctx->opcode)) {
5622 case 0:
f78fb44e
AJ		 5623 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5624 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5625 gen_op_4xx_tlbwe_hi();
5626 break;
5627 case 1:
f78fb44e
AJ		 5628 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5629 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5630 gen_op_4xx_tlbwe_lo();
5631 break;
5632 default:
e1833e1f 5633 GEN_EXCP_INVAL(ctx);
76a66253 5634 break;
9a64fbe4 5635 }
76a66253
JM		 5636#endif
5637}
5638
a4bb6c3e 5639/* TLB management - PowerPC 440 implementation */
5eb7995e 5640/* tlbre */
c7697e1f 5641GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5642{
5643#if defined(CONFIG_USER_ONLY)
e1833e1f 5644 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5645#else
5646 if (unlikely(!ctx->supervisor)) {
e1833e1f 5647 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5648 return;
5649 }
5650 switch (rB(ctx->opcode)) {
5651 case 0:
5eb7995e 5652 case 1:
5eb7995e 5653 case 2:
f78fb44e 5654 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5655 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5656 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5657 break;
5658 default:
e1833e1f 5659 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5660 break;
5661 }
5662#endif
5663}
5664
5665/* tlbsx - tlbsx. */
c7697e1f 5666GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5667{
5668#if defined(CONFIG_USER_ONLY)
e1833e1f 5669 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5670#else
5671 if (unlikely(!ctx->supervisor)) {
e1833e1f 5672 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5673 return;
5674 }
e2be8d8d 5675 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5676 gen_op_440_tlbsx();
5eb7995e 5677 if (Rc(ctx->opcode))
daf4f96e 5678 gen_op_4xx_tlbsx_check();
f78fb44e 5679 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5680#endif
5681}
5682
5683/* tlbwe */
c7697e1f 5684GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5685{
5686#if defined(CONFIG_USER_ONLY)
e1833e1f 5687 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5688#else
5689 if (unlikely(!ctx->supervisor)) {
e1833e1f 5690 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5691 return;
5692 }
5693 switch (rB(ctx->opcode)) {
5694 case 0:
5eb7995e 5695 case 1:
5eb7995e 5696 case 2:
f78fb44e
AJ		 5697 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5698 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5699 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5700 break;
5701 default:
e1833e1f 5702 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5703 break;
5704 }
5705#endif
5706}
5707
76a66253 5708/* wrtee */
05332d70 5709GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5710{
5711#if defined(CONFIG_USER_ONLY)
e1833e1f 5712 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5713#else
5714 if (unlikely(!ctx->supervisor)) {
e1833e1f 5715 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5716 return;
5717 }
f78fb44e 5718 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5719 gen_op_wrte();
dee96f6c
JM		 5720 /* Stop translation to have a chance to raise an exception
5721 * if we just set msr_ee to 1
5722 */
e1833e1f 5723 GEN_STOP(ctx);
76a66253
JM		 5724#endif
5725}
5726
5727/* wrteei */
05332d70 5728GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5729{
5730#if defined(CONFIG_USER_ONLY)
e1833e1f 5731 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5732#else
5733 if (unlikely(!ctx->supervisor)) {
e1833e1f 5734 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5735 return;
5736 }
86c581dc 5737 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5738 gen_op_wrte();
dee96f6c
JM		 5739 /* Stop translation to have a chance to raise an exception
5740 * if we just set msr_ee to 1
5741 */
e1833e1f 5742 GEN_STOP(ctx);
76a66253
JM		 5743#endif
5744}
5745
08e46e54 5746/* PowerPC 440 specific instructions */
76a66253
JM		 5747/* dlmzb */
5748GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5749{
f78fb44e
AJ		 5750 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5751 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5752 gen_op_440_dlmzb();
f78fb44e 5753 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5754 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5755 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5756 if (Rc(ctx->opcode)) {
5757 gen_op_440_dlmzb_update_Rc();
a7812ae4
PB		 5758 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_T[0]);
5759 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 0xf);
76a66253
JM		 5760 }
5761}
5762
5763/* mbar replaces eieio on 440 */
5764GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5765{
5766 /* interpreted as no-op */
5767}
5768
5769/* msync replaces sync on 440 */
0db1b20e 5770GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5771{
5772 /* interpreted as no-op */
5773}
5774
5775/* icbt */
c7697e1f 5776GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5777{
5778 /* interpreted as no-op */
5779 /* XXX: specification say this is treated as a load by the MMU
5780 * but does not generate any exception
5781 */
79aceca5
FB		 5782}
5783
a9d9eb8f
JM		 5784/*** Altivec vector extension ***/
5785/* Altivec registers moves */
a9d9eb8f 5786
a9d9eb8f 5787#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 5788GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 5789{ \
fe1e5c53 5790 TCGv EA; \
a9d9eb8f
JM		 5791 if (unlikely(!ctx->altivec_enabled)) { \
5792 GEN_EXCP_NO_VR(ctx); \
5793 return; \
5794 } \
fe1e5c53
AJ		 5795 EA = tcg_temp_new(); \
5796 gen_addr_reg_index(EA, ctx); \
5797 tcg_gen_andi_tl(EA, EA, ~0xf); \
5798 if (ctx->mem_idx & 1) { \
5799 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5800 tcg_gen_addi_tl(EA, EA, 8); \
5801 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5802 } else { \
5803 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5804 tcg_gen_addi_tl(EA, EA, 8); \
5805 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5806 } \
5807 tcg_temp_free(EA); \
a9d9eb8f
JM		 5808}
5809
5810#define GEN_VR_STX(name, opc2, opc3) \
5811GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5812{ \
fe1e5c53 5813 TCGv EA; \
a9d9eb8f
JM		 5814 if (unlikely(!ctx->altivec_enabled)) { \
5815 GEN_EXCP_NO_VR(ctx); \
5816 return; \
5817 } \
fe1e5c53
AJ		 5818 EA = tcg_temp_new(); \
5819 gen_addr_reg_index(EA, ctx); \
5820 tcg_gen_andi_tl(EA, EA, ~0xf); \
5821 if (ctx->mem_idx & 1) { \
5822 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5823 tcg_gen_addi_tl(EA, EA, 8); \
5824 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5825 } else { \
5826 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5827 tcg_gen_addi_tl(EA, EA, 8); \
5828 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5829 } \
5830 tcg_temp_free(EA); \
a9d9eb8f
JM		 5831}
5832
fe1e5c53 5833GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 5834/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 5835GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 5836
fe1e5c53 5837GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 5838/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 5839GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 5840
0487d6a8 5841/*** SPE extension ***/
0487d6a8 5842/* Register moves */
3cd7d1dd 5843
a7812ae4 5844static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 5845#if defined(TARGET_PPC64)
5846 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5847#else
36aa55dc 5848 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5849#endif
f78fb44e 5850}
3cd7d1dd 5851
a7812ae4 5852static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 5853#if defined(TARGET_PPC64)
5854 tcg_gen_mov_i64(cpu_gpr[reg], t);
5855#else
a7812ae4 5856 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 5857 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 5858 tcg_gen_shri_i64(tmp, t, 32);
5859 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 5860 tcg_temp_free_i64(tmp);
3cd7d1dd 5861#endif
f78fb44e 5862}
3cd7d1dd 5863
0487d6a8
JM		 5864#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5865GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5866{ \
5867 if (Rc(ctx->opcode)) \
5868 gen_##name1(ctx); \
5869 else \
5870 gen_##name0(ctx); \
5871}
5872
5873/* Handler for undefined SPE opcodes */
b068d6a7 5874static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5875{
e1833e1f 5876 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5877}
5878
57951c27
AJ		 5879/* SPE logic */
5880#if defined(TARGET_PPC64)
5881#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 5882static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5883{ \
5884 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5885 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5886 return; \
5887 } \
57951c27
AJ		 5888 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5889 cpu_gpr[rB(ctx->opcode)]); \
5890}
5891#else
5892#define GEN_SPEOP_LOGIC2(name, tcg_op) \
5893static always_inline void gen_##name (DisasContext *ctx) \
5894{ \
5895 if (unlikely(!ctx->spe_enabled)) { \
5896 GEN_EXCP_NO_AP(ctx); \
5897 return; \
5898 } \
5899 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5900 cpu_gpr[rB(ctx->opcode)]); \
5901 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
5902 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 5903}
57951c27
AJ		 5904#endif
5905
5906GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
5907GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
5908GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
5909GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
5910GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
5911GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
5912GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
5913GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 5914
57951c27
AJ		 5915/* SPE logic immediate */
5916#if defined(TARGET_PPC64)
5917#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 5918static always_inline void gen_##name (DisasContext *ctx) \
5919{ \
5920 if (unlikely(!ctx->spe_enabled)) { \
5921 GEN_EXCP_NO_AP(ctx); \
5922 return; \
5923 } \
a7812ae4
PB		 5924 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
5925 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
5926 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 5927 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
5928 tcg_opi(t0, t0, rB(ctx->opcode)); \
5929 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
5930 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 5931 tcg_temp_free_i64(t2); \
57951c27
AJ		 5932 tcg_opi(t1, t1, rB(ctx->opcode)); \
5933 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 5934 tcg_temp_free_i32(t0); \
5935 tcg_temp_free_i32(t1); \
3d3a6a0a 5936}
57951c27
AJ		 5937#else
5938#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 5939static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5940{ \
5941 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5942 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5943 return; \
5944 } \
57951c27
AJ		 5945 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
5946 rB(ctx->opcode)); \
5947 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
5948 rB(ctx->opcode)); \
0487d6a8 5949}
57951c27
AJ		 5950#endif
5951GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
5952GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
5953GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
5954GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 5955
57951c27
AJ		 5956/* SPE arithmetic */
5957#if defined(TARGET_PPC64)
5958#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 5959static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5960{ \
5961 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5962 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5963 return; \
5964 } \
a7812ae4
PB		 5965 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
5966 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
5967 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 5968 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
5969 tcg_op(t0, t0); \
5970 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
5971 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 5972 tcg_temp_free_i64(t2); \
57951c27
AJ		 5973 tcg_op(t1, t1); \
5974 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 5975 tcg_temp_free_i32(t0); \
5976 tcg_temp_free_i32(t1); \
0487d6a8 5977}
57951c27 5978#else
a7812ae4 5979#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 5980static always_inline void gen_##name (DisasContext *ctx) \
5981{ \
5982 if (unlikely(!ctx->spe_enabled)) { \
5983 GEN_EXCP_NO_AP(ctx); \
5984 return; \
5985 } \
5986 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
5987 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
5988}
5989#endif
0487d6a8 5990
a7812ae4 5991static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 5992{
5993 int l1 = gen_new_label();
5994 int l2 = gen_new_label();
0487d6a8 5995
57951c27
AJ		 5996 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
5997 tcg_gen_neg_i32(ret, arg1);
5998 tcg_gen_br(l2);
5999 gen_set_label(l1);
a7812ae4 6000 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6001 gen_set_label(l2);
6002}
6003GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6004GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6005GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6006GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6007static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6008{
57951c27
AJ		 6009 tcg_gen_addi_i32(ret, arg1, 0x8000);
6010 tcg_gen_ext16u_i32(ret, ret);
6011}
6012GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6013GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6014GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6015
57951c27
AJ		 6016#if defined(TARGET_PPC64)
6017#define GEN_SPEOP_ARITH2(name, tcg_op) \
6018static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6019{ \
6020 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6021 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6022 return; \
6023 } \
a7812ae4
PB		 6024 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6025 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6026 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6027 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
57951c27
AJ		 6028 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6029 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6030 tcg_op(t0, t0, t2); \
6031 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6032 tcg_gen_trunc_i64_i32(t1, t3); \
6033 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6034 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6035 tcg_temp_free_i64(t3); \
57951c27 6036 tcg_op(t1, t1, t2); \
a7812ae4 6037 tcg_temp_free_i32(t2); \
57951c27 6038 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6039 tcg_temp_free_i32(t0); \
6040 tcg_temp_free_i32(t1); \
0487d6a8 6041}
57951c27
AJ		 6042#else
6043#define GEN_SPEOP_ARITH2(name, tcg_op) \
6044static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6045{ \
6046 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6047 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6048 return; \
6049 } \
57951c27
AJ		 6050 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6051 cpu_gpr[rB(ctx->opcode)]); \
6052 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6053 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6054}
57951c27 6055#endif
0487d6a8 6056
a7812ae4 6057static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6058{
a7812ae4 6059 TCGv_i32 t0;
57951c27 6060 int l1, l2;
0487d6a8 6061
57951c27
AJ		 6062 l1 = gen_new_label();
6063 l2 = gen_new_label();
a7812ae4 6064 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6065 /* No error here: 6 bits are used */
6066 tcg_gen_andi_i32(t0, arg2, 0x3F);
6067 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6068 tcg_gen_shr_i32(ret, arg1, t0);
6069 tcg_gen_br(l2);
6070 gen_set_label(l1);
6071 tcg_gen_movi_i32(ret, 0);
6072 tcg_gen_br(l2);
a7812ae4 6073 tcg_temp_free_i32(t0);
57951c27
AJ		 6074}
6075GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6076static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6077{
a7812ae4 6078 TCGv_i32 t0;
57951c27
AJ		 6079 int l1, l2;
6080
6081 l1 = gen_new_label();
6082 l2 = gen_new_label();
a7812ae4 6083 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6084 /* No error here: 6 bits are used */
6085 tcg_gen_andi_i32(t0, arg2, 0x3F);
6086 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6087 tcg_gen_sar_i32(ret, arg1, t0);
6088 tcg_gen_br(l2);
6089 gen_set_label(l1);
6090 tcg_gen_movi_i32(ret, 0);
6091 tcg_gen_br(l2);
a7812ae4 6092 tcg_temp_free_i32(t0);
57951c27
AJ		 6093}
6094GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6095static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6096{
a7812ae4 6097 TCGv_i32 t0;
57951c27
AJ		 6098 int l1, l2;
6099
6100 l1 = gen_new_label();
6101 l2 = gen_new_label();
a7812ae4 6102 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6103 /* No error here: 6 bits are used */
6104 tcg_gen_andi_i32(t0, arg2, 0x3F);
6105 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6106 tcg_gen_shl_i32(ret, arg1, t0);
6107 tcg_gen_br(l2);
6108 gen_set_label(l1);
6109 tcg_gen_movi_i32(ret, 0);
6110 tcg_gen_br(l2);
a7812ae4 6111 tcg_temp_free_i32(t0);
57951c27
AJ		 6112}
6113GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6114static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6115{
a7812ae4 6116 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6117 tcg_gen_andi_i32(t0, arg2, 0x1F);
6118 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6119 tcg_temp_free_i32(t0);
57951c27
AJ		 6120}
6121GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6122static always_inline void gen_evmergehi (DisasContext *ctx)
6123{
6124 if (unlikely(!ctx->spe_enabled)) {
6125 GEN_EXCP_NO_AP(ctx);
6126 return;
6127 }
6128#if defined(TARGET_PPC64)
a7812ae4
PB		 6129 TCGv t0 = tcg_temp_new();
6130 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6131 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6132 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6133 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6134 tcg_temp_free(t0);
6135 tcg_temp_free(t1);
6136#else
6137 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6138 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6139#endif
6140}
6141GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6142static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6143{
57951c27
AJ		 6144 tcg_gen_sub_i32(ret, arg2, arg1);
6145}
6146GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6147
57951c27
AJ		 6148/* SPE arithmetic immediate */
6149#if defined(TARGET_PPC64)
6150#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6151static always_inline void gen_##name (DisasContext *ctx) \
6152{ \
6153 if (unlikely(!ctx->spe_enabled)) { \
6154 GEN_EXCP_NO_AP(ctx); \
6155 return; \
6156 } \
a7812ae4
PB		 6157 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6158 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6159 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6160 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6161 tcg_op(t0, t0, rA(ctx->opcode)); \
6162 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6163 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6164 tcg_temp_free_i64(t2); \
57951c27
AJ		 6165 tcg_op(t1, t1, rA(ctx->opcode)); \
6166 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6167 tcg_temp_free_i32(t0); \
6168 tcg_temp_free_i32(t1); \
57951c27
AJ		 6169}
6170#else
6171#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6172static always_inline void gen_##name (DisasContext *ctx) \
6173{ \
6174 if (unlikely(!ctx->spe_enabled)) { \
6175 GEN_EXCP_NO_AP(ctx); \
6176 return; \
6177 } \
6178 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6179 rA(ctx->opcode)); \
6180 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6181 rA(ctx->opcode)); \
6182}
6183#endif
6184GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6185GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6186
6187/* SPE comparison */
6188#if defined(TARGET_PPC64)
6189#define GEN_SPEOP_COMP(name, tcg_cond) \
6190static always_inline void gen_##name (DisasContext *ctx) \
6191{ \
6192 if (unlikely(!ctx->spe_enabled)) { \
6193 GEN_EXCP_NO_AP(ctx); \
6194 return; \
6195 } \
6196 int l1 = gen_new_label(); \
6197 int l2 = gen_new_label(); \
6198 int l3 = gen_new_label(); \
6199 int l4 = gen_new_label(); \
a7812ae4
PB		 6200 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6201 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6202 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6203 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6204 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6205 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 6206 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 6207 tcg_gen_br(l2); \
6208 gen_set_label(l1); \
6209 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6210 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6211 gen_set_label(l2); \
6212 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6213 tcg_gen_trunc_i64_i32(t0, t2); \
6214 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6215 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6216 tcg_temp_free_i64(t2); \
57951c27
AJ		 6217 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6218 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6219 ~(CRF_CH | CRF_CH_AND_CL)); \
6220 tcg_gen_br(l4); \
6221 gen_set_label(l3); \
6222 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6223 CRF_CH | CRF_CH_OR_CL); \
6224 gen_set_label(l4); \
a7812ae4
PB		 6225 tcg_temp_free_i32(t0); \
6226 tcg_temp_free_i32(t1); \
57951c27
AJ		 6227}
6228#else
6229#define GEN_SPEOP_COMP(name, tcg_cond) \
6230static always_inline void gen_##name (DisasContext *ctx) \
6231{ \
6232 if (unlikely(!ctx->spe_enabled)) { \
6233 GEN_EXCP_NO_AP(ctx); \
6234 return; \
6235 } \
6236 int l1 = gen_new_label(); \
6237 int l2 = gen_new_label(); \
6238 int l3 = gen_new_label(); \
6239 int l4 = gen_new_label(); \
6240 \
6241 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6242 cpu_gpr[rB(ctx->opcode)], l1); \
6243 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6244 tcg_gen_br(l2); \
6245 gen_set_label(l1); \
6246 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6247 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6248 gen_set_label(l2); \
6249 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6250 cpu_gprh[rB(ctx->opcode)], l3); \
6251 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6252 ~(CRF_CH | CRF_CH_AND_CL)); \
6253 tcg_gen_br(l4); \
6254 gen_set_label(l3); \
6255 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6256 CRF_CH | CRF_CH_OR_CL); \
6257 gen_set_label(l4); \
6258}
6259#endif
6260GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6261GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6262GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6263GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6264GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6265
6266/* SPE misc */
6267static always_inline void gen_brinc (DisasContext *ctx)
6268{
6269 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 6270 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6271 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6272}
57951c27
AJ		 6273static always_inline void gen_evmergelo (DisasContext *ctx)
6274{
6275 if (unlikely(!ctx->spe_enabled)) {
6276 GEN_EXCP_NO_AP(ctx);
6277 return;
6278 }
6279#if defined(TARGET_PPC64)
a7812ae4
PB		 6280 TCGv t0 = tcg_temp_new();
6281 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6282 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6283 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6284 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6285 tcg_temp_free(t0);
6286 tcg_temp_free(t1);
6287#else
6288 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6289 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6290#endif
6291}
6292static always_inline void gen_evmergehilo (DisasContext *ctx)
6293{
6294 if (unlikely(!ctx->spe_enabled)) {
6295 GEN_EXCP_NO_AP(ctx);
6296 return;
6297 }
6298#if defined(TARGET_PPC64)
a7812ae4
PB		 6299 TCGv t0 = tcg_temp_new();
6300 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6301 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6302 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6303 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6304 tcg_temp_free(t0);
6305 tcg_temp_free(t1);
6306#else
6307 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6308 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6309#endif
6310}
6311static always_inline void gen_evmergelohi (DisasContext *ctx)
6312{
6313 if (unlikely(!ctx->spe_enabled)) {
6314 GEN_EXCP_NO_AP(ctx);
6315 return;
6316 }
6317#if defined(TARGET_PPC64)
a7812ae4
PB		 6318 TCGv t0 = tcg_temp_new();
6319 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6320 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6321 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6322 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6323 tcg_temp_free(t0);
6324 tcg_temp_free(t1);
6325#else
6326 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6327 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6328#endif
6329}
6330static always_inline void gen_evsplati (DisasContext *ctx)
6331{
38d14952 6332 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 6333
57951c27 6334#if defined(TARGET_PPC64)
38d14952 6335 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6336#else
6337 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6338 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6339#endif
6340}
b068d6a7 6341static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 6342{
38d14952 6343 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 6344
57951c27 6345#if defined(TARGET_PPC64)
38d14952 6346 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 6347#else
6348 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6349 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6350#endif
0487d6a8
JM		 6351}
6352
57951c27
AJ		 6353static always_inline void gen_evsel (DisasContext *ctx)
6354{
6355 int l1 = gen_new_label();
6356 int l2 = gen_new_label();
6357 int l3 = gen_new_label();
6358 int l4 = gen_new_label();
a7812ae4 6359 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 6360#if defined(TARGET_PPC64)
a7812ae4
PB		 6361 TCGv t1 = tcg_temp_local_new();
6362 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 6363#endif
6364 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6365 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6366#if defined(TARGET_PPC64)
6367 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6368#else
6369 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6370#endif
6371 tcg_gen_br(l2);
6372 gen_set_label(l1);
6373#if defined(TARGET_PPC64)
6374 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6375#else
6376 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6377#endif
6378 gen_set_label(l2);
6379 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6380 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6381#if defined(TARGET_PPC64)
6382 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6383#else
6384 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6385#endif
6386 tcg_gen_br(l4);
6387 gen_set_label(l3);
6388#if defined(TARGET_PPC64)
6389 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6390#else
6391 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6392#endif
6393 gen_set_label(l4);
a7812ae4 6394 tcg_temp_free_i32(t0);
57951c27
AJ		 6395#if defined(TARGET_PPC64)
6396 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6397 tcg_temp_free(t1);
6398 tcg_temp_free(t2);
6399#endif
6400}
6401GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6402{
6403 gen_evsel(ctx);
6404}
6405GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6406{
6407 gen_evsel(ctx);
6408}
6409GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6410{
6411 gen_evsel(ctx);
6412}
6413GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6414{
6415 gen_evsel(ctx);
6416}
0487d6a8
JM		 6417
6418GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6419GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6420GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6421GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6422GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6423GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6424GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6425GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6426GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6427GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6428GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6429GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6430GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6431GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6432GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6433GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6434GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6435GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6436GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6437GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6438GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6439GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6440GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6441GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6442GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6443
6a6ae23f
AJ		 6444/* SPE load and stores */
6445static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
6446{
6447 target_ulong uimm = rB(ctx->opcode);
6448
6449 if (rA(ctx->opcode) == 0)
6450 tcg_gen_movi_tl(EA, uimm << sh);
6451 else
6452 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
0487d6a8 6453}
6a6ae23f
AJ		 6454
6455static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6456{
6457#if defined(TARGET_PPC64)
6458 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6459#else
6460 TCGv_i64 t0 = tcg_temp_new_i64();
6461 gen_qemu_ld64(t0, addr, ctx->mem_idx);
6462 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6463 tcg_gen_shri_i64(t0, t0, 32);
6464 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6465 tcg_temp_free_i64(t0);
6466#endif
0487d6a8 6467}
6a6ae23f
AJ		 6468
6469static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6470{
0487d6a8 6471#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6472 TCGv t0 = tcg_temp_new();
6473 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6474 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6475 tcg_gen_addi_tl(addr, addr, 4);
6476 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6477 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6478 tcg_temp_free(t0);
6479#else
6480 gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6481 tcg_gen_addi_tl(addr, addr, 4);
6482 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6483#endif
0487d6a8 6484}
6a6ae23f
AJ		 6485
6486static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6487{
6488 TCGv t0 = tcg_temp_new();
6489#if defined(TARGET_PPC64)
6490 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6491 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6492 tcg_gen_addi_tl(addr, addr, 2);
6493 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6494 tcg_gen_shli_tl(t0, t0, 32);
6495 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6496 tcg_gen_addi_tl(addr, addr, 2);
6497 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6498 tcg_gen_shli_tl(t0, t0, 16);
6499 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6500 tcg_gen_addi_tl(addr, addr, 2);
6501 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6502 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6503#else
6a6ae23f
AJ		 6504 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6505 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6506 tcg_gen_addi_tl(addr, addr, 2);
6507 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6508 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6509 tcg_gen_addi_tl(addr, addr, 2);
6510 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6511 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6512 tcg_gen_addi_tl(addr, addr, 2);
6513 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6514 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 6515#endif
6a6ae23f 6516 tcg_temp_free(t0);
0487d6a8
JM		 6517}
6518
6a6ae23f
AJ		 6519static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6520{
6521 TCGv t0 = tcg_temp_new();
6522 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6523#if defined(TARGET_PPC64)
6524 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6525 tcg_gen_shli_tl(t0, t0, 16);
6526 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6527#else
6528 tcg_gen_shli_tl(t0, t0, 16);
6529 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6530 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6531#endif
6532 tcg_temp_free(t0);
0487d6a8
JM		 6533}
6534
6a6ae23f
AJ		 6535static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6536{
6537 TCGv t0 = tcg_temp_new();
6538 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6539#if defined(TARGET_PPC64)
6540 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6541 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6542#else
6543 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6544 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6545#endif
6546 tcg_temp_free(t0);
0487d6a8
JM		 6547}
6548
6a6ae23f
AJ		 6549static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6550{
6551 TCGv t0 = tcg_temp_new();
6552 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6553#if defined(TARGET_PPC64)
6554 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6555 tcg_gen_ext32u_tl(t0, t0);
6556 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6557#else
6558 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6559 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6560#endif
6561 tcg_temp_free(t0);
6562}
6563
6564static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6565{
6566 TCGv t0 = tcg_temp_new();
6567#if defined(TARGET_PPC64)
6568 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6569 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6570 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6571 tcg_gen_shli_tl(t0, t0, 16);
6572 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6573#else
6574 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6575 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6576 tcg_gen_addi_tl(addr, addr, 2);
6577 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6578 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6579#endif
6580 tcg_temp_free(t0);
6581}
6582
6583static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6584{
6585#if defined(TARGET_PPC64)
6586 TCGv t0 = tcg_temp_new();
6587 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6588 tcg_gen_addi_tl(addr, addr, 2);
6589 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6590 tcg_gen_shli_tl(t0, t0, 32);
6591 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6592 tcg_temp_free(t0);
6593#else
6594 gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6595 tcg_gen_addi_tl(addr, addr, 2);
6596 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6597#endif
6598}
6599
6600static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6601{
6602#if defined(TARGET_PPC64)
6603 TCGv t0 = tcg_temp_new();
6604 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6605 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6606 tcg_gen_addi_tl(addr, addr, 2);
6607 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6608 tcg_gen_shli_tl(t0, t0, 32);
6609 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6610 tcg_temp_free(t0);
6611#else
6612 gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6613 tcg_gen_addi_tl(addr, addr, 2);
6614 gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6615#endif
6616}
6617
6618static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6619{
6620 TCGv t0 = tcg_temp_new();
6621 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
0487d6a8 6622#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6623 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6624 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6625#else
6626 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6627 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6628#endif
6629 tcg_temp_free(t0);
6630}
6631
6632static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6633{
6634 TCGv t0 = tcg_temp_new();
6635#if defined(TARGET_PPC64)
6636 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6637 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6638 tcg_gen_shli_tl(t0, t0, 32);
6639 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6640 tcg_gen_addi_tl(addr, addr, 2);
6641 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6642 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6643 tcg_gen_shli_tl(t0, t0, 16);
6644 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6645#else
6646 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6647 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6648 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6649 tcg_gen_addi_tl(addr, addr, 2);
6650 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6651 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6652 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 6653#endif
6a6ae23f
AJ		 6654 tcg_temp_free(t0);
6655}
6656
6657static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6658{
6659#if defined(TARGET_PPC64)
6660 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
0487d6a8 6661#else
6a6ae23f
AJ		 6662 TCGv_i64 t0 = tcg_temp_new_i64();
6663 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6664 gen_qemu_st64(t0, addr, ctx->mem_idx);
6665 tcg_temp_free_i64(t0);
6666#endif
6667}
6668
6669static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6670{
0487d6a8 6671#if defined(TARGET_PPC64)
6a6ae23f
AJ		 6672 TCGv t0 = tcg_temp_new();
6673 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6674 gen_qemu_st32(t0, addr, ctx->mem_idx);
6675 tcg_temp_free(t0);
6676#else
6677 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6678#endif
6679 tcg_gen_addi_tl(addr, addr, 4);
6680 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6681}
6682
6683static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6684{
6685 TCGv t0 = tcg_temp_new();
6686#if defined(TARGET_PPC64)
6687 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6688#else
6689 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6690#endif
6691 gen_qemu_st16(t0, addr, ctx->mem_idx);
6692 tcg_gen_addi_tl(addr, addr, 2);
6693#if defined(TARGET_PPC64)
6694 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6695 gen_qemu_st16(t0, addr, ctx->mem_idx);
6696#else
6697 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6698#endif
6699 tcg_gen_addi_tl(addr, addr, 2);
6700 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6701 gen_qemu_st16(t0, addr, ctx->mem_idx);
6702 tcg_temp_free(t0);
6703 tcg_gen_addi_tl(addr, addr, 2);
6704 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6705}
6706
6707static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6708{
6709 TCGv t0 = tcg_temp_new();
6710#if defined(TARGET_PPC64)
6711 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6712#else
6713 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6714#endif
6715 gen_qemu_st16(t0, addr, ctx->mem_idx);
6716 tcg_gen_addi_tl(addr, addr, 2);
6717 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6718 gen_qemu_st16(t0, addr, ctx->mem_idx);
6719 tcg_temp_free(t0);
6720}
6721
6722static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6723{
6724#if defined(TARGET_PPC64)
6725 TCGv t0 = tcg_temp_new();
6726 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6727 gen_qemu_st16(t0, addr, ctx->mem_idx);
6728 tcg_temp_free(t0);
6729#else
6730 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6731#endif
6732 tcg_gen_addi_tl(addr, addr, 2);
6733 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6734}
6735
6736static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6737{
6738#if defined(TARGET_PPC64)
6739 TCGv t0 = tcg_temp_new();
6740 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6741 gen_qemu_st32(t0, addr, ctx->mem_idx);
6742 tcg_temp_free(t0);
6743#else
6744 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6745#endif
6746}
6747
6748static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6749{
6750 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6751}
6752
6753#define GEN_SPEOP_LDST(name, opc2, sh) \
6754GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6755{ \
6756 TCGv t0; \
6757 if (unlikely(!ctx->spe_enabled)) { \
6758 GEN_EXCP_NO_AP(ctx); \
6759 return; \
6760 } \
6761 t0 = tcg_temp_new(); \
6762 if (Rc(ctx->opcode)) { \
6763 gen_addr_spe_imm_index(t0, ctx, sh); \
6764 } else { \
6765 gen_addr_reg_index(t0, ctx); \
6766 } \
6767 gen_op_##name(ctx, t0); \
6768 tcg_temp_free(t0); \
6769}
6770
6771GEN_SPEOP_LDST(evldd, 0x00, 3);
6772GEN_SPEOP_LDST(evldw, 0x01, 3);
6773GEN_SPEOP_LDST(evldh, 0x02, 3);
6774GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
6775GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
6776GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
6777GEN_SPEOP_LDST(evlwhe, 0x08, 2);
6778GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
6779GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
6780GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
6781GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
6782
6783GEN_SPEOP_LDST(evstdd, 0x10, 3);
6784GEN_SPEOP_LDST(evstdw, 0x11, 3);
6785GEN_SPEOP_LDST(evstdh, 0x12, 3);
6786GEN_SPEOP_LDST(evstwhe, 0x18, 2);
6787GEN_SPEOP_LDST(evstwho, 0x1A, 2);
6788GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
6789GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 6790
6791/* Multiply and add - TODO */
6792#if 0
6793GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6794GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6795GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6796GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6797GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6798GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6799GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6800GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6801GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6802GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6803GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6804GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6805
6806GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6807GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6808GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6809GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6810GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6811GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6812GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6813GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6814GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6815GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6816GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6817GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6818GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6819GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6820
6821GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6822GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6823GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6824GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6825GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6826GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6827
6828GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6829GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6830GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6831GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6832GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6833GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6834GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6835GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6836GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6837GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6838GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6839GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6840
6841GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6842GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6843GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6844GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6845GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6846
6847GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6848GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6849GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6850GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6851GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6852GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6853GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6854GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6855GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6856GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6857GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6858GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6859
6860GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6861GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6862GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6863GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6864GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6865#endif
6866
6867/*** SPE floating-point extension ***/
1c97856d
AJ		 6868#if defined(TARGET_PPC64)
6869#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 6870static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6871{ \
1c97856d
AJ		 6872 TCGv_i32 t0; \
6873 TCGv t1; \
6874 t0 = tcg_temp_new_i32(); \
6875 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6876 gen_helper_##name(t0, t0); \
6877 t1 = tcg_temp_new(); \
6878 tcg_gen_extu_i32_tl(t1, t0); \
6879 tcg_temp_free_i32(t0); \
6880 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6881 0xFFFFFFFF00000000ULL); \
6882 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6883 tcg_temp_free(t1); \
0487d6a8 6884}
1c97856d
AJ		 6885#define GEN_SPEFPUOP_CONV_32_64(name) \
6886static always_inline void gen_##name (DisasContext *ctx) \
6887{ \
6888 TCGv_i32 t0; \
6889 TCGv t1; \
6890 t0 = tcg_temp_new_i32(); \
6891 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
6892 t1 = tcg_temp_new(); \
6893 tcg_gen_extu_i32_tl(t1, t0); \
6894 tcg_temp_free_i32(t0); \
6895 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6896 0xFFFFFFFF00000000ULL); \
6897 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6898 tcg_temp_free(t1); \
6899}
6900#define GEN_SPEFPUOP_CONV_64_32(name) \
6901static always_inline void gen_##name (DisasContext *ctx) \
6902{ \
6903 TCGv_i32 t0 = tcg_temp_new_i32(); \
6904 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6905 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
6906 tcg_temp_free_i32(t0); \
6907}
6908#define GEN_SPEFPUOP_CONV_64_64(name) \
6909static always_inline void gen_##name (DisasContext *ctx) \
6910{ \
6911 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6912}
6913#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 6914static always_inline void gen_##name (DisasContext *ctx) \
6915{ \
1c97856d
AJ		 6916 TCGv_i32 t0, t1; \
6917 TCGv_i64 t2; \
57951c27
AJ		 6918 if (unlikely(!ctx->spe_enabled)) { \
6919 GEN_EXCP_NO_AP(ctx); \
6920 return; \
6921 } \
1c97856d
AJ		 6922 t0 = tcg_temp_new_i32(); \
6923 t1 = tcg_temp_new_i32(); \
6924 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6925 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6926 gen_helper_##name(t0, t0, t1); \
6927 tcg_temp_free_i32(t1); \
6928 t2 = tcg_temp_new(); \
6929 tcg_gen_extu_i32_tl(t2, t0); \
6930 tcg_temp_free_i32(t0); \
6931 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6932 0xFFFFFFFF00000000ULL); \
6933 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
6934 tcg_temp_free(t2); \
57951c27 6935}
1c97856d 6936#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 6937static always_inline void gen_##name (DisasContext *ctx) \
6938{ \
6939 if (unlikely(!ctx->spe_enabled)) { \
6940 GEN_EXCP_NO_AP(ctx); \
6941 return; \
6942 } \
1c97856d
AJ		 6943 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6944 cpu_gpr[rB(ctx->opcode)]); \
57951c27 6945}
1c97856d 6946#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 6947static always_inline void gen_##name (DisasContext *ctx) \
6948{ \
1c97856d 6949 TCGv_i32 t0, t1; \
57951c27
AJ		 6950 if (unlikely(!ctx->spe_enabled)) { \
6951 GEN_EXCP_NO_AP(ctx); \
6952 return; \
6953 } \
1c97856d
AJ		 6954 t0 = tcg_temp_new_i32(); \
6955 t1 = tcg_temp_new_i32(); \
6956 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6957 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6958 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
6959 tcg_temp_free_i32(t0); \
6960 tcg_temp_free_i32(t1); \
6961}
6962#define GEN_SPEFPUOP_COMP_64(name) \
6963static always_inline void gen_##name (DisasContext *ctx) \
6964{ \
6965 if (unlikely(!ctx->spe_enabled)) { \
6966 GEN_EXCP_NO_AP(ctx); \
6967 return; \
6968 } \
6969 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
6970 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6971}
6972#else
6973#define GEN_SPEFPUOP_CONV_32_32(name) \
6974static always_inline void gen_##name (DisasContext *ctx) \
6975{ \
6976 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 6977}
1c97856d
AJ		 6978#define GEN_SPEFPUOP_CONV_32_64(name) \
6979static always_inline void gen_##name (DisasContext *ctx) \
6980{ \
6981 TCGv_i64 t0 = tcg_temp_new_i64(); \
6982 gen_load_gpr64(t0, rB(ctx->opcode)); \
6983 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
6984 tcg_temp_free_i64(t0); \
6985}
6986#define GEN_SPEFPUOP_CONV_64_32(name) \
6987static always_inline void gen_##name (DisasContext *ctx) \
6988{ \
6989 TCGv_i64 t0 = tcg_temp_new_i64(); \
6990 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
6991 gen_store_gpr64(rD(ctx->opcode), t0); \
6992 tcg_temp_free_i64(t0); \
6993}
6994#define GEN_SPEFPUOP_CONV_64_64(name) \
6995static always_inline void gen_##name (DisasContext *ctx) \
6996{ \
6997 TCGv_i64 t0 = tcg_temp_new_i64(); \
6998 gen_load_gpr64(t0, rB(ctx->opcode)); \
6999 gen_helper_##name(t0, t0); \
7000 gen_store_gpr64(rD(ctx->opcode), t0); \
7001 tcg_temp_free_i64(t0); \
7002}
7003#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7004static always_inline void gen_##name (DisasContext *ctx) \
7005{ \
7006 if (unlikely(!ctx->spe_enabled)) { \
7007 GEN_EXCP_NO_AP(ctx); \
7008 return; \
7009 } \
7010 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7011 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7012}
7013#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7014static always_inline void gen_##name (DisasContext *ctx) \
7015{ \
7016 TCGv_i64 t0, t1; \
7017 if (unlikely(!ctx->spe_enabled)) { \
7018 GEN_EXCP_NO_AP(ctx); \
7019 return; \
7020 } \
7021 t0 = tcg_temp_new_i64(); \
7022 t1 = tcg_temp_new_i64(); \
7023 gen_load_gpr64(t0, rA(ctx->opcode)); \
7024 gen_load_gpr64(t1, rB(ctx->opcode)); \
7025 gen_helper_##name(t0, t0, t1); \
7026 gen_store_gpr64(rD(ctx->opcode), t0); \
7027 tcg_temp_free_i64(t0); \
7028 tcg_temp_free_i64(t1); \
7029}
7030#define GEN_SPEFPUOP_COMP_32(name) \
7031static always_inline void gen_##name (DisasContext *ctx) \
7032{ \
7033 if (unlikely(!ctx->spe_enabled)) { \
7034 GEN_EXCP_NO_AP(ctx); \
7035 return; \
7036 } \
7037 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7038 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7039}
7040#define GEN_SPEFPUOP_COMP_64(name) \
7041static always_inline void gen_##name (DisasContext *ctx) \
7042{ \
7043 TCGv_i64 t0, t1; \
7044 if (unlikely(!ctx->spe_enabled)) { \
7045 GEN_EXCP_NO_AP(ctx); \
7046 return; \
7047 } \
7048 t0 = tcg_temp_new_i64(); \
7049 t1 = tcg_temp_new_i64(); \
7050 gen_load_gpr64(t0, rA(ctx->opcode)); \
7051 gen_load_gpr64(t1, rB(ctx->opcode)); \
7052 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7053 tcg_temp_free_i64(t0); \
7054 tcg_temp_free_i64(t1); \
7055}
7056#endif
57951c27 7057
0487d6a8
JM		 7058/* Single precision floating-point vectors operations */
7059/* Arithmetic */
1c97856d
AJ		 7060GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7061GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7062GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7063GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7064static always_inline void gen_evfsabs (DisasContext *ctx)
7065{
7066 if (unlikely(!ctx->spe_enabled)) {
7067 GEN_EXCP_NO_AP(ctx);
7068 return;
7069 }
7070#if defined(TARGET_PPC64)
7071 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7072#else
7073 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7074 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7075#endif
7076}
7077static always_inline void gen_evfsnabs (DisasContext *ctx)
7078{
7079 if (unlikely(!ctx->spe_enabled)) {
7080 GEN_EXCP_NO_AP(ctx);
7081 return;
7082 }
7083#if defined(TARGET_PPC64)
7084 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7085#else
7086 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7087 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7088#endif
7089}
7090static always_inline void gen_evfsneg (DisasContext *ctx)
7091{
7092 if (unlikely(!ctx->spe_enabled)) {
7093 GEN_EXCP_NO_AP(ctx);
7094 return;
7095 }
7096#if defined(TARGET_PPC64)
7097 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7098#else
7099 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7100 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7101#endif
7102}
7103
0487d6a8 7104/* Conversion */
1c97856d
AJ		 7105GEN_SPEFPUOP_CONV_64_64(evfscfui);
7106GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7107GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7108GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7109GEN_SPEFPUOP_CONV_64_64(evfsctui);
7110GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7111GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7112GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7113GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7114GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7115
0487d6a8 7116/* Comparison */
1c97856d
AJ		 7117GEN_SPEFPUOP_COMP_64(evfscmpgt);
7118GEN_SPEFPUOP_COMP_64(evfscmplt);
7119GEN_SPEFPUOP_COMP_64(evfscmpeq);
7120GEN_SPEFPUOP_COMP_64(evfststgt);
7121GEN_SPEFPUOP_COMP_64(evfststlt);
7122GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7123
7124/* Opcodes definitions */
7125GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7126GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7127GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7128GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7129GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7130GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7131GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7132GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7133GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7134GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7135GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7136GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7137GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7138GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7139
7140/* Single precision floating-point operations */
7141/* Arithmetic */
1c97856d
AJ		 7142GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7143GEN_SPEFPUOP_ARITH2_32_32(efssub);
7144GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7145GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7146static always_inline void gen_efsabs (DisasContext *ctx)
7147{
7148 if (unlikely(!ctx->spe_enabled)) {
7149 GEN_EXCP_NO_AP(ctx);
7150 return;
7151 }
7152 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7153}
7154static always_inline void gen_efsnabs (DisasContext *ctx)
7155{
7156 if (unlikely(!ctx->spe_enabled)) {
7157 GEN_EXCP_NO_AP(ctx);
7158 return;
7159 }
7160 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7161}
7162static always_inline void gen_efsneg (DisasContext *ctx)
7163{
7164 if (unlikely(!ctx->spe_enabled)) {
7165 GEN_EXCP_NO_AP(ctx);
7166 return;
7167 }
7168 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7169}
7170
0487d6a8 7171/* Conversion */
1c97856d
AJ		 7172GEN_SPEFPUOP_CONV_32_32(efscfui);
7173GEN_SPEFPUOP_CONV_32_32(efscfsi);
7174GEN_SPEFPUOP_CONV_32_32(efscfuf);
7175GEN_SPEFPUOP_CONV_32_32(efscfsf);
7176GEN_SPEFPUOP_CONV_32_32(efsctui);
7177GEN_SPEFPUOP_CONV_32_32(efsctsi);
7178GEN_SPEFPUOP_CONV_32_32(efsctuf);
7179GEN_SPEFPUOP_CONV_32_32(efsctsf);
7180GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7181GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7182GEN_SPEFPUOP_CONV_32_64(efscfd);
7183
0487d6a8 7184/* Comparison */
1c97856d
AJ		 7185GEN_SPEFPUOP_COMP_32(efscmpgt);
7186GEN_SPEFPUOP_COMP_32(efscmplt);
7187GEN_SPEFPUOP_COMP_32(efscmpeq);
7188GEN_SPEFPUOP_COMP_32(efststgt);
7189GEN_SPEFPUOP_COMP_32(efststlt);
7190GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 7191
7192/* Opcodes definitions */
05332d70 7193GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 7194GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7195GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7196GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7197GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7198GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7199GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7200GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7201GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7202GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 7203GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7204GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 7205GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7206GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7207
7208/* Double precision floating-point operations */
7209/* Arithmetic */
1c97856d
AJ		 7210GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7211GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7212GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7213GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7214static always_inline void gen_efdabs (DisasContext *ctx)
7215{
7216 if (unlikely(!ctx->spe_enabled)) {
7217 GEN_EXCP_NO_AP(ctx);
7218 return;
7219 }
7220#if defined(TARGET_PPC64)
7221 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7222#else
7223 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7224#endif
7225}
7226static always_inline void gen_efdnabs (DisasContext *ctx)
7227{
7228 if (unlikely(!ctx->spe_enabled)) {
7229 GEN_EXCP_NO_AP(ctx);
7230 return;
7231 }
7232#if defined(TARGET_PPC64)
7233 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7234#else
7235 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7236#endif
7237}
7238static always_inline void gen_efdneg (DisasContext *ctx)
7239{
7240 if (unlikely(!ctx->spe_enabled)) {
7241 GEN_EXCP_NO_AP(ctx);
7242 return;
7243 }
7244#if defined(TARGET_PPC64)
7245 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7246#else
7247 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7248#endif
7249}
7250
0487d6a8 7251/* Conversion */
1c97856d
AJ		 7252GEN_SPEFPUOP_CONV_64_32(efdcfui);
7253GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7254GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7255GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7256GEN_SPEFPUOP_CONV_32_64(efdctui);
7257GEN_SPEFPUOP_CONV_32_64(efdctsi);
7258GEN_SPEFPUOP_CONV_32_64(efdctuf);
7259GEN_SPEFPUOP_CONV_32_64(efdctsf);
7260GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7261GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7262GEN_SPEFPUOP_CONV_64_32(efdcfs);
7263GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7264GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7265GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7266GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 7267
0487d6a8 7268/* Comparison */
1c97856d
AJ		 7269GEN_SPEFPUOP_COMP_64(efdcmpgt);
7270GEN_SPEFPUOP_COMP_64(efdcmplt);
7271GEN_SPEFPUOP_COMP_64(efdcmpeq);
7272GEN_SPEFPUOP_COMP_64(efdtstgt);
7273GEN_SPEFPUOP_COMP_64(efdtstlt);
7274GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 7275
7276/* Opcodes definitions */
7277GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7278GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7279GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7280GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7281GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7282GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7283GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7284GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7285GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7286GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7287GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7288GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7289GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7290GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7291GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7292GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 7293
79aceca5
FB		 7294/* End opcode list */
7295GEN_OPCODE_MARK(end);
7296
3fc6c082 7297#include "translate_init.c"
0411a972 7298#include "helper_regs.h"
79aceca5 7299
9a64fbe4 7300/*****************************************************************************/
3fc6c082 7301/* Misc PowerPC helpers */
36081602
JM		 7302void cpu_dump_state (CPUState *env, FILE *f,
7303 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7304 int flags)
79aceca5 7305{
3fc6c082
FB		 7306#define RGPL 4
7307#define RFPL 4
3fc6c082 7308
79aceca5
FB		 7309 int i;
7310
077fc206 7311 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 7312 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 7313 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7314 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 7315#if !defined(NO_TIMER_DUMP)
077fc206 7316 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 7317#if !defined(CONFIG_USER_ONLY)
7318 "DECR %08x"
7319#endif
7320 "\n",
077fc206 7321 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 7322#if !defined(CONFIG_USER_ONLY)
7323 , cpu_ppc_load_decr(env)
7324#endif
7325 );
077fc206 7326#endif
76a66253 7327 for (i = 0; i < 32; i++) {
3fc6c082
FB		 7328 if ((i & (RGPL - 1)) == 0)
7329 cpu_fprintf(f, "GPR%02d", i);
6b542af7 7330 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 7331 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 7332 cpu_fprintf(f, "\n");
76a66253 7333 }
3fc6c082 7334 cpu_fprintf(f, "CR ");
76a66253 7335 for (i = 0; i < 8; i++)
7fe48483
FB		 7336 cpu_fprintf(f, "%01x", env->crf[i]);
7337 cpu_fprintf(f, " [");
76a66253
JM		 7338 for (i = 0; i < 8; i++) {
7339 char a = '-';
7340 if (env->crf[i] & 0x08)
7341 a = 'L';
7342 else if (env->crf[i] & 0x04)
7343 a = 'G';
7344 else if (env->crf[i] & 0x02)
7345 a = 'E';
7fe48483 7346 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 7347 }
6b542af7 7348 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 7349 for (i = 0; i < 32; i++) {
7350 if ((i & (RFPL - 1)) == 0)
7351 cpu_fprintf(f, "FPR%02d", i);
26a76461 7352 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 7353 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 7354 cpu_fprintf(f, "\n");
79aceca5 7355 }
f2e63a42 7356#if !defined(CONFIG_USER_ONLY)
6b542af7 7357 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 7358 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 7359#endif
79aceca5 7360
3fc6c082
FB		 7361#undef RGPL
7362#undef RFPL
79aceca5
FB		 7363}
7364
76a66253
JM		 7365void cpu_dump_statistics (CPUState *env, FILE*f,
7366 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7367 int flags)
7368{
7369#if defined(DO_PPC_STATISTICS)
7370 opc_handler_t **t1, **t2, **t3, *handler;
7371 int op1, op2, op3;
7372
7373 t1 = env->opcodes;
7374 for (op1 = 0; op1 < 64; op1++) {
7375 handler = t1[op1];
7376 if (is_indirect_opcode(handler)) {
7377 t2 = ind_table(handler);
7378 for (op2 = 0; op2 < 32; op2++) {
7379 handler = t2[op2];
7380 if (is_indirect_opcode(handler)) {
7381 t3 = ind_table(handler);
7382 for (op3 = 0; op3 < 32; op3++) {
7383 handler = t3[op3];
7384 if (handler->count == 0)
7385 continue;
7386 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7387 "%016llx %lld\n",
7388 op1, op2, op3, op1, (op3 << 5) | op2,
7389 handler->oname,
7390 handler->count, handler->count);
7391 }
7392 } else {
7393 if (handler->count == 0)
7394 continue;
7395 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7396 "%016llx %lld\n",
7397 op1, op2, op1, op2, handler->oname,
7398 handler->count, handler->count);
7399 }
7400 }
7401 } else {
7402 if (handler->count == 0)
7403 continue;
7404 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7405 op1, op1, handler->oname,
7406 handler->count, handler->count);
7407 }
7408 }
7409#endif
7410}
7411
9a64fbe4 7412/*****************************************************************************/
2cfc5f17
TS		 7413static always_inline void gen_intermediate_code_internal (CPUState *env,
7414 TranslationBlock *tb,
7415 int search_pc)
79aceca5 7416{
9fddaa0c 7417 DisasContext ctx, *ctxp = &ctx;
79aceca5 7418 opc_handler_t **table, *handler;
0fa85d43 7419 target_ulong pc_start;
79aceca5 7420 uint16_t *gen_opc_end;
056401ea 7421 int supervisor, little_endian;
a1d1bb31 7422 CPUBreakpoint *bp;
79aceca5 7423 int j, lj = -1;
2e70f6ef
PB		 7424 int num_insns;
7425 int max_insns;
79aceca5
FB		 7426
7427 pc_start = tb->pc;
79aceca5 7428 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 7429#if defined(OPTIMIZE_FPRF_UPDATE)
7430 gen_fprf_ptr = gen_fprf_buf;
7431#endif
046d6672 7432 ctx.nip = pc_start;
79aceca5 7433 ctx.tb = tb;
e1833e1f 7434 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 7435 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 7436 supervisor = env->mmu_idx;
7437#if !defined(CONFIG_USER_ONLY)
2857068e 7438 ctx.supervisor = supervisor;
d9bce9d9 7439#endif
056401ea 7440 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 7441#if defined(TARGET_PPC64)
7442 ctx.sf_mode = msr_sf;
056401ea 7443 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 7444#else
056401ea 7445 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 7446#endif
3cc62370 7447 ctx.fpu_enabled = msr_fp;
a9d9eb8f 7448 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 7449 ctx.spe_enabled = msr_spe;
7450 else
7451 ctx.spe_enabled = 0;
a9d9eb8f
JM		 7452 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7453 ctx.altivec_enabled = msr_vr;
7454 else
7455 ctx.altivec_enabled = 0;
d26bfc9a 7456 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 7457 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 7458 else
8cbcb4fa 7459 ctx.singlestep_enabled = 0;
d26bfc9a 7460 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 7461 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7462 if (unlikely(env->singlestep_enabled))
7463 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 7464#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 7465 /* Single step trace mode */
7466 msr_se = 1;
7467#endif
2e70f6ef
PB		 7468 num_insns = 0;
7469 max_insns = tb->cflags & CF_COUNT_MASK;
7470 if (max_insns == 0)
7471 max_insns = CF_COUNT_MASK;
7472
7473 gen_icount_start();
9a64fbe4 7474 /* Set env in case of segfault during code fetch */
e1833e1f 7475 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 7476 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7477 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 7478 if (bp->pc == ctx.nip) {
5fafdf24 7479 gen_update_nip(&ctx, ctx.nip);
64adab3f 7480 gen_helper_raise_debug();
ea4e754f
FB		 7481 break;
7482 }
7483 }
7484 }
76a66253 7485 if (unlikely(search_pc)) {
79aceca5
FB		 7486 j = gen_opc_ptr - gen_opc_buf;
7487 if (lj < j) {
7488 lj++;
7489 while (lj < j)
7490 gen_opc_instr_start[lj++] = 0;
046d6672 7491 gen_opc_pc[lj] = ctx.nip;
79aceca5 7492 gen_opc_instr_start[lj] = 1;
2e70f6ef 7493 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 7494 }
7495 }
9fddaa0c
FB		 7496#if defined PPC_DEBUG_DISAS
7497 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 7498 fprintf(logfile, "----------------\n");
1b9eb036 7499 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 7500 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 7501 }
7502#endif
2e70f6ef
PB		 7503 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7504 gen_io_start();
056401ea
JM		 7505 if (unlikely(little_endian)) {
7506 ctx.opcode = bswap32(ldl_code(ctx.nip));
7507 } else {
7508 ctx.opcode = ldl_code(ctx.nip);
111bfab3 7509 }
9fddaa0c
FB		 7510#if defined PPC_DEBUG_DISAS
7511 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 7512 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 7513 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 7514 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 7515 }
7516#endif
046d6672 7517 ctx.nip += 4;
3fc6c082 7518 table = env->opcodes;
2e70f6ef 7519 num_insns++;
79aceca5
FB		 7520 handler = table[opc1(ctx.opcode)];
7521 if (is_indirect_opcode(handler)) {
7522 table = ind_table(handler);
7523 handler = table[opc2(ctx.opcode)];
7524 if (is_indirect_opcode(handler)) {
7525 table = ind_table(handler);
7526 handler = table[opc3(ctx.opcode)];
7527 }
7528 }
7529 /* Is opcode *REALLY* valid ? */
76a66253 7530 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7531 if (loglevel != 0) {
76a66253 7532 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 7533 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 7534 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7535 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7536 } else {
7537 printf("invalid/unsupported opcode: "
6b542af7 7538 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 7539 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7540 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7541 }
76a66253
JM		 7542 } else {
7543 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7544 if (loglevel != 0) {
79aceca5 7545 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 7546 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 7547 ctx.opcode & handler->inval, opc1(ctx.opcode),
7548 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7549 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7550 } else {
7551 printf("invalid bits: %08x for opcode: "
6b542af7 7552 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 7553 ctx.opcode & handler->inval, opc1(ctx.opcode),
7554 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7555 ctx.opcode, ctx.nip - 4);
76a66253 7556 }
e1833e1f 7557 GEN_EXCP_INVAL(ctxp);
4b3686fa 7558 break;
79aceca5 7559 }
79aceca5 7560 }
4b3686fa 7561 (*(handler->handler))(&ctx);
76a66253
JM		 7562#if defined(DO_PPC_STATISTICS)
7563 handler->count++;
7564#endif
9a64fbe4 7565 /* Check trace mode exceptions */
8cbcb4fa
AJ		 7566 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7567 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7568 ctx.exception != POWERPC_SYSCALL &&
7569 ctx.exception != POWERPC_EXCP_TRAP &&
7570 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 7571 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 7572 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 7573 (env->singlestep_enabled) ||
7574 num_insns >= max_insns)) {
d26bfc9a
JM		 7575 /* if we reach a page boundary or are single stepping, stop
7576 * generation
7577 */
8dd4983c 7578 break;
76a66253 7579 }
3fc6c082
FB		 7580#if defined (DO_SINGLE_STEP)
7581 break;
7582#endif
7583 }
2e70f6ef
PB		 7584 if (tb->cflags & CF_LAST_IO)
7585 gen_io_end();
e1833e1f 7586 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7587 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7588 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 7589 if (unlikely(env->singlestep_enabled)) {
7590 gen_update_nip(&ctx, ctx.nip);
64adab3f 7591 gen_helper_raise_debug();
8cbcb4fa 7592 }
76a66253 7593 /* Generate the return instruction */
57fec1fe 7594 tcg_gen_exit_tb(0);
9a64fbe4 7595 }
2e70f6ef 7596 gen_icount_end(tb, num_insns);
79aceca5 7597 *gen_opc_ptr = INDEX_op_end;
76a66253 7598 if (unlikely(search_pc)) {
9a64fbe4
FB		 7599 j = gen_opc_ptr - gen_opc_buf;
7600 lj++;
7601 while (lj <= j)
7602 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7603 } else {
046d6672 7604 tb->size = ctx.nip - pc_start;
2e70f6ef 7605 tb->icount = num_insns;
9a64fbe4 7606 }
d9bce9d9 7607#if defined(DEBUG_DISAS)
9fddaa0c 7608 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7609 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7610 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7611 }
7612 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7613 int flags;
237c0af0 7614 flags = env->bfd_mach;
056401ea 7615 flags |= little_endian << 16;
0fa85d43 7616 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7617 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7618 fprintf(logfile, "\n");
9fddaa0c 7619 }
79aceca5 7620#endif
79aceca5
FB		 7621}
7622
2cfc5f17 7623void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 7624{
2cfc5f17 7625 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 7626}
7627
2cfc5f17 7628void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7629{
2cfc5f17 7630 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7631}
d2856f1a
AJ		 7632
7633void gen_pc_load(CPUState *env, TranslationBlock *tb,
7634 unsigned long searched_pc, int pc_pos, void *puc)
7635{
d2856f1a 7636 env->nip = gen_opc_pc[pc_pos];
d2856f1a 7637}
Qemu copy for testing