]> git.proxmox.com Git - qemu.git/blame - target-ppc/translate_init.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'spice/spice.v52' into staging
[qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
f7aa5583 5 * Copyright 2011 Freescale Semiconductor, Inc.
3fc6c082
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0 26#include "dis-asm.h"
4e47ea67 27#include "gdbstub.h"
a1e98583
DG		 28#include <kvm.h>
29#include "kvm_ppc.h"
237c0af0 30
3fc6c082
FB		 31//#define PPC_DUMP_CPU
32//#define PPC_DEBUG_SPR
80d11f44
JM		 33//#define PPC_DUMP_SPR_ACCESSES
34#if defined(CONFIG_USER_ONLY)
35#define TODO_USER_ONLY 1
36#endif
3fc6c082 37
e9df014c
JM		 38/* For user-mode emulation, we don't emulate any IRQ controller */
39#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 40#define PPC_IRQ_INIT_FN(name) \
41static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42{ \
e9df014c
JM		 43}
44#else
a750fc0b 45#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 46void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47#endif
a750fc0b 48
4e290a0b 49PPC_IRQ_INIT_FN(40x);
e9df014c 50PPC_IRQ_INIT_FN(6xx);
d0dfae6e 51PPC_IRQ_INIT_FN(970);
9d52e907 52PPC_IRQ_INIT_FN(POWER7);
9fdc60bf 53PPC_IRQ_INIT_FN(e500);
e9df014c 54
3fc6c082
FB		 55/* Generic callbacks:
56 * do nothing but store/retrieve spr value
57 */
45d827d2 58static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 59{
45d827d2
AJ		 60 gen_load_spr(cpu_gpr[gprn], sprn);
61#ifdef PPC_DUMP_SPR_ACCESSES
62 {
1ff7854e 63 TCGv_i32 t0 = tcg_const_i32(sprn);
45d827d2
AJ		 64 gen_helper_load_dump_spr(t0);
65 tcg_temp_free_i32(t0);
66 }
67#endif
a496775f
JM		 68}
69
45d827d2 70static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 71{
45d827d2
AJ		 72 gen_store_spr(sprn, cpu_gpr[gprn]);
73#ifdef PPC_DUMP_SPR_ACCESSES
74 {
1ff7854e 75 TCGv_i32 t0 = tcg_const_i32(sprn);
45d827d2
AJ		 76 gen_helper_store_dump_spr(t0);
77 tcg_temp_free_i32(t0);
78 }
04f20795 79#endif
45d827d2 80}
a496775f
JM		 81
82#if !defined(CONFIG_USER_ONLY)
45d827d2 83static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 84{
45d827d2
AJ		 85 TCGv t0 = tcg_temp_new();
86 TCGv t1 = tcg_temp_new();
87 gen_load_spr(t0, sprn);
88 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
89 tcg_gen_and_tl(t0, t0, t1);
90 gen_store_spr(sprn, t0);
91 tcg_temp_free(t0);
92 tcg_temp_free(t1);
a496775f
JM		 93}
94#endif
95
76a66253 96/* SPR common to all PowerPC */
3fc6c082 97/* XER */
45d827d2 98static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 99{
45d827d2 100 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
3fc6c082
FB		 101}
102
45d827d2 103static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 104{
45d827d2 105 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
3fc6c082
FB		 106}
107
108/* LR */
45d827d2 109static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 110{
45d827d2 111 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 112}
113
45d827d2 114static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 115{
45d827d2 116 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 117}
118
697ab892
DG		 119/* CFAR */
120#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
121static void spr_read_cfar (void *opaque, int gprn, int sprn)
122{
123 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
124}
125
126static void spr_write_cfar (void *opaque, int sprn, int gprn)
127{
128 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
129}
130#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
131
3fc6c082 132/* CTR */
45d827d2 133static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 134{
45d827d2 135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 136}
137
45d827d2 138static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 139{
45d827d2 140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 141}
142
143/* User read access to SPR */
144/* USPRx */
145/* UMMCRx */
146/* UPMCx */
147/* USIA */
148/* UDECR */
45d827d2 149static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 150{
45d827d2 151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 152}
153
76a66253 154/* SPR common to all non-embedded PowerPC */
3fc6c082 155/* DECR */
76a66253 156#if !defined(CONFIG_USER_ONLY)
45d827d2 157static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 158{
630ecca0
TG		 159 if (use_icount) {
160 gen_io_start();
161 }
45d827d2 162 gen_helper_load_decr(cpu_gpr[gprn]);
630ecca0
TG		 163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
3fc6c082
FB		 167}
168
45d827d2 169static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 170{
630ecca0
TG		 171 if (use_icount) {
172 gen_io_start();
173 }
45d827d2 174 gen_helper_store_decr(cpu_gpr[gprn]);
630ecca0
TG		 175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
3fc6c082 179}
76a66253 180#endif
3fc6c082 181
76a66253 182/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 183/* Time base */
45d827d2 184static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 185{
630ecca0
TG		 186 if (use_icount) {
187 gen_io_start();
188 }
45d827d2 189 gen_helper_load_tbl(cpu_gpr[gprn]);
630ecca0
TG		 190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
3fc6c082
FB		 194}
195
45d827d2 196static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 197{
630ecca0
TG		 198 if (use_icount) {
199 gen_io_start();
200 }
45d827d2 201 gen_helper_load_tbu(cpu_gpr[gprn]);
630ecca0
TG		 202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
3fc6c082
FB		 206}
207
a062e36c 208__attribute__ (( unused ))
45d827d2 209static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 210{
45d827d2 211 gen_helper_load_atbl(cpu_gpr[gprn]);
a062e36c
JM		 212}
213
214__attribute__ (( unused ))
45d827d2 215static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 216{
45d827d2 217 gen_helper_load_atbu(cpu_gpr[gprn]);
a062e36c
JM		 218}
219
76a66253 220#if !defined(CONFIG_USER_ONLY)
45d827d2 221static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 222{
630ecca0
TG		 223 if (use_icount) {
224 gen_io_start();
225 }
45d827d2 226 gen_helper_store_tbl(cpu_gpr[gprn]);
630ecca0
TG		 227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
3fc6c082
FB		 231}
232
45d827d2 233static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 234{
630ecca0
TG		 235 if (use_icount) {
236 gen_io_start();
237 }
45d827d2 238 gen_helper_store_tbu(cpu_gpr[gprn]);
630ecca0
TG		 239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
3fc6c082 243}
a062e36c
JM		 244
245__attribute__ (( unused ))
45d827d2 246static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 247{
45d827d2 248 gen_helper_store_atbl(cpu_gpr[gprn]);
a062e36c
JM		 249}
250
251__attribute__ (( unused ))
45d827d2 252static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 253{
45d827d2 254 gen_helper_store_atbu(cpu_gpr[gprn]);
a062e36c 255}
3a7f009a
DG		 256
257#if defined(TARGET_PPC64)
258__attribute__ (( unused ))
259static void spr_read_purr (void *opaque, int gprn, int sprn)
260{
261 gen_helper_load_purr(cpu_gpr[gprn]);
262}
263#endif
76a66253 264#endif
3fc6c082 265
76a66253 266#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 267/* IBAT0U...IBAT0U */
268/* IBAT0L...IBAT7L */
45d827d2 269static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 270{
1328c2bf 271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 272}
273
45d827d2 274static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 275{
1328c2bf 276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 277}
278
45d827d2 279static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 280{
45d827d2
AJ		 281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
3fc6c082
FB		 284}
285
45d827d2 286static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 287{
8daf1781 288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
45d827d2
AJ		 289 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
3fc6c082
FB		 291}
292
45d827d2 293static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 294{
45d827d2
AJ		 295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
3fc6c082
FB		 298}
299
45d827d2 300static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 301{
8daf1781 302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
45d827d2
AJ		 303 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
3fc6c082
FB		 305}
306
307/* DBAT0U...DBAT7U */
308/* DBAT0L...DBAT7L */
45d827d2 309static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 310{
1328c2bf 311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 312}
313
45d827d2 314static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 315{
1328c2bf 316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 317}
318
45d827d2 319static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 320{
45d827d2
AJ		 321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
3fc6c082
FB		 324}
325
45d827d2 326static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 327{
45d827d2
AJ		 328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
3fc6c082
FB		 331}
332
45d827d2 333static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 334{
45d827d2
AJ		 335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
3fc6c082
FB		 338}
339
45d827d2 340static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 341{
45d827d2
AJ		 342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
3fc6c082
FB		 345}
346
347/* SDR1 */
45d827d2 348static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 349{
45d827d2 350 gen_helper_store_sdr1(cpu_gpr[gprn]);
3fc6c082
FB		 351}
352
76a66253
JM		 353/* 64 bits PowerPC specific SPRs */
354/* ASR */
578bb252 355#if defined(TARGET_PPC64)
2adab7d6
BS		 356static void spr_read_hior (void *opaque, int gprn, int sprn)
357{
1328c2bf 358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 359}
360
361static void spr_write_hior (void *opaque, int sprn, int gprn)
362{
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
1328c2bf 365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 366 tcg_temp_free(t0);
367}
368
45d827d2 369static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 370{
1328c2bf 371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
76a66253
JM		 372}
373
45d827d2 374static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 375{
45d827d2 376 gen_helper_store_asr(cpu_gpr[gprn]);
76a66253
JM		 377}
378#endif
a750fc0b 379#endif
76a66253
JM		 380
381/* PowerPC 601 specific registers */
382/* RTC */
45d827d2 383static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 384{
45d827d2 385 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
76a66253
JM		 386}
387
45d827d2 388static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 389{
45d827d2 390 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 391}
392
393#if !defined(CONFIG_USER_ONLY)
45d827d2 394static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 395{
45d827d2 396 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 397}
398
45d827d2 399static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 400{
45d827d2 401 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
76a66253 402}
056401ea 403
45d827d2 404static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 405{
406 DisasContext *ctx = opaque;
407
45d827d2 408 gen_helper_store_hid0_601(cpu_gpr[gprn]);
056401ea 409 /* Must stop the translation as endianness may have changed */
e06fcd75 410 gen_stop_exception(ctx);
056401ea 411}
76a66253
JM		 412#endif
413
414/* Unified bats */
415#if !defined(CONFIG_USER_ONLY)
45d827d2 416static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 417{
1328c2bf 418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 419}
420
45d827d2 421static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 422{
45d827d2
AJ		 423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
76a66253
JM		 426}
427
45d827d2 428static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 429{
45d827d2
AJ		 430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
76a66253
JM		 433}
434#endif
435
436/* PowerPC 40x specific registers */
437#if !defined(CONFIG_USER_ONLY)
45d827d2 438static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 439{
45d827d2 440 gen_helper_load_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 441}
442
45d827d2 443static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 444{
45d827d2 445 gen_helper_store_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 446}
447
45d827d2 448static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 449{
450 DisasContext *ctx = opaque;
451
45d827d2 452 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
8ecc7913 453 /* We must stop translation as we may have rebooted */
e06fcd75 454 gen_stop_exception(ctx);
8ecc7913
JM		 455}
456
45d827d2 457static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 458{
45d827d2 459 gen_helper_store_40x_sler(cpu_gpr[gprn]);
c294fc58
JM		 460}
461
45d827d2 462static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 463{
45d827d2 464 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
76a66253
JM		 465}
466
45d827d2 467static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 468{
45d827d2 469 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
76a66253
JM		 470}
471#endif
472
473/* PowerPC 403 specific registers */
474/* PBL1 / PBU1 / PBL2 / PBU2 */
475#if !defined(CONFIG_USER_ONLY)
45d827d2 476static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 477{
1328c2bf 478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 479}
480
45d827d2 481static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 482{
45d827d2
AJ		 483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
76a66253
JM		 486}
487
45d827d2 488static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 489{
45d827d2
AJ		 490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
3fc6c082 494}
76a66253 495#endif
3fc6c082 496
d34defbc
AJ		 497/* SPE specific registers */
498static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499{
500 TCGv_i32 t0 = tcg_temp_new_i32();
1328c2bf 501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504}
505
506static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507{
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1328c2bf 510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 511 tcg_temp_free_i32(t0);
512}
513
6f5d427d
JM		 514#if !defined(CONFIG_USER_ONLY)
515/* Callback used to write the exception vector base */
45d827d2 516static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 517{
45d827d2 518 TCGv t0 = tcg_temp_new();
1328c2bf 519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
45d827d2 520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
45d827d2 522 gen_store_spr(sprn, t0);
69bd5820 523 tcg_temp_free(t0);
6f5d427d
JM		 524}
525
45d827d2 526static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 527{
528 DisasContext *ctx = opaque;
e9205258 529 int sprn_offs;
6f5d427d
JM		 530
531 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
e9205258 532 sprn_offs = sprn - SPR_BOOKE_IVOR0;
6f5d427d 533 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
e9205258
AG		 534 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
535 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
536 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
6f5d427d
JM		 537 } else {
538 printf("Trying to write an unknown exception vector %d %03x\n",
539 sprn, sprn);
e06fcd75 540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
e9205258 541 return;
6f5d427d 542 }
e9205258
AG		 543
544 TCGv t0 = tcg_temp_new();
1328c2bf 545 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
e9205258 546 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 547 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
e9205258
AG		 548 gen_store_spr(sprn, t0);
549 tcg_temp_free(t0);
6f5d427d
JM		 550}
551#endif
552
cf8358c8
AJ		 553static inline void vscr_init (CPUPPCState *env, uint32_t val)
554{
555 env->vscr = val;
556 /* Altivec always uses round-to-nearest */
557 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
558 set_flush_to_zero(vscr_nj, &env->vec_status);
559}
560
76a66253
JM		 561#if defined(CONFIG_USER_ONLY)
562#define spr_register(env, num, name, uea_read, uea_write, \
563 oea_read, oea_write, initial_value) \
564do { \
565 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
566} while (0)
567static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 568 const char *name,
45d827d2
AJ		 569 void (*uea_read)(void *opaque, int gprn, int sprn),
570 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 571 target_ulong initial_value)
572#else
3fc6c082 573static inline void spr_register (CPUPPCState *env, int num,
b55266b5 574 const char *name,
45d827d2
AJ		 575 void (*uea_read)(void *opaque, int gprn, int sprn),
576 void (*uea_write)(void *opaque, int sprn, int gprn),
577 void (*oea_read)(void *opaque, int gprn, int sprn),
578 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 579 target_ulong initial_value)
76a66253 580#endif
3fc6c082 581{
c227f099 582 ppc_spr_t *spr;
3fc6c082
FB		 583
584 spr = &env->spr_cb[num];
585 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 586#if !defined(CONFIG_USER_ONLY)
587 spr->oea_read != NULL || spr->oea_write != NULL ||
588#endif
589 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 590 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
591 exit(1);
592 }
593#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 594 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
595 name, initial_value);
3fc6c082
FB		 596#endif
597 spr->name = name;
598 spr->uea_read = uea_read;
599 spr->uea_write = uea_write;
76a66253 600#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 601 spr->oea_read = oea_read;
602 spr->oea_write = oea_write;
76a66253 603#endif
3fc6c082
FB		 604 env->spr[num] = initial_value;
605}
606
607/* Generic PowerPC SPRs */
608static void gen_spr_generic (CPUPPCState *env)
609{
610 /* Integer processing */
611 spr_register(env, SPR_XER, "XER",
612 &spr_read_xer, &spr_write_xer,
613 &spr_read_xer, &spr_write_xer,
614 0x00000000);
615 /* Branch contol */
616 spr_register(env, SPR_LR, "LR",
617 &spr_read_lr, &spr_write_lr,
618 &spr_read_lr, &spr_write_lr,
619 0x00000000);
620 spr_register(env, SPR_CTR, "CTR",
621 &spr_read_ctr, &spr_write_ctr,
622 &spr_read_ctr, &spr_write_ctr,
623 0x00000000);
624 /* Interrupt processing */
625 spr_register(env, SPR_SRR0, "SRR0",
626 SPR_NOACCESS, SPR_NOACCESS,
627 &spr_read_generic, &spr_write_generic,
628 0x00000000);
629 spr_register(env, SPR_SRR1, "SRR1",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_generic, &spr_write_generic,
632 0x00000000);
633 /* Processor control */
634 spr_register(env, SPR_SPRG0, "SPRG0",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_generic, &spr_write_generic,
637 0x00000000);
638 spr_register(env, SPR_SPRG1, "SPRG1",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_generic, &spr_write_generic,
641 0x00000000);
642 spr_register(env, SPR_SPRG2, "SPRG2",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_generic, &spr_write_generic,
645 0x00000000);
646 spr_register(env, SPR_SPRG3, "SPRG3",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650}
651
652/* SPR common to all non-embedded PowerPC, including 601 */
653static void gen_spr_ne_601 (CPUPPCState *env)
654{
655 /* Exception processing */
656 spr_register(env, SPR_DSISR, "DSISR",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_generic, &spr_write_generic,
659 0x00000000);
660 spr_register(env, SPR_DAR, "DAR",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_generic, &spr_write_generic,
663 0x00000000);
664 /* Timer */
665 spr_register(env, SPR_DECR, "DECR",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_decr, &spr_write_decr,
668 0x00000000);
669 /* Memory management */
670 spr_register(env, SPR_SDR1, "SDR1",
671 SPR_NOACCESS, SPR_NOACCESS,
bb593904 672 &spr_read_generic, &spr_write_sdr1,
3fc6c082
FB		 673 0x00000000);
674}
675
676/* BATs 0-3 */
677static void gen_low_BATs (CPUPPCState *env)
678{
f2e63a42 679#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 680 spr_register(env, SPR_IBAT0U, "IBAT0U",
681 SPR_NOACCESS, SPR_NOACCESS,
682 &spr_read_ibat, &spr_write_ibatu,
683 0x00000000);
684 spr_register(env, SPR_IBAT0L, "IBAT0L",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_ibat, &spr_write_ibatl,
687 0x00000000);
688 spr_register(env, SPR_IBAT1U, "IBAT1U",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_ibat, &spr_write_ibatu,
691 0x00000000);
692 spr_register(env, SPR_IBAT1L, "IBAT1L",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_ibat, &spr_write_ibatl,
695 0x00000000);
696 spr_register(env, SPR_IBAT2U, "IBAT2U",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_ibat, &spr_write_ibatu,
699 0x00000000);
700 spr_register(env, SPR_IBAT2L, "IBAT2L",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_ibat, &spr_write_ibatl,
703 0x00000000);
704 spr_register(env, SPR_IBAT3U, "IBAT3U",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_ibat, &spr_write_ibatu,
707 0x00000000);
708 spr_register(env, SPR_IBAT3L, "IBAT3L",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_ibat, &spr_write_ibatl,
711 0x00000000);
712 spr_register(env, SPR_DBAT0U, "DBAT0U",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_dbat, &spr_write_dbatu,
715 0x00000000);
716 spr_register(env, SPR_DBAT0L, "DBAT0L",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_dbat, &spr_write_dbatl,
719 0x00000000);
720 spr_register(env, SPR_DBAT1U, "DBAT1U",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_dbat, &spr_write_dbatu,
723 0x00000000);
724 spr_register(env, SPR_DBAT1L, "DBAT1L",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_dbat, &spr_write_dbatl,
727 0x00000000);
728 spr_register(env, SPR_DBAT2U, "DBAT2U",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_dbat, &spr_write_dbatu,
731 0x00000000);
732 spr_register(env, SPR_DBAT2L, "DBAT2L",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_dbat, &spr_write_dbatl,
735 0x00000000);
736 spr_register(env, SPR_DBAT3U, "DBAT3U",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_dbat, &spr_write_dbatu,
739 0x00000000);
740 spr_register(env, SPR_DBAT3L, "DBAT3L",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_dbat, &spr_write_dbatl,
743 0x00000000);
a750fc0b 744 env->nb_BATs += 4;
f2e63a42 745#endif
3fc6c082
FB		 746}
747
748/* BATs 4-7 */
749static void gen_high_BATs (CPUPPCState *env)
750{
f2e63a42 751#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 752 spr_register(env, SPR_IBAT4U, "IBAT4U",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_ibat_h, &spr_write_ibatu_h,
755 0x00000000);
756 spr_register(env, SPR_IBAT4L, "IBAT4L",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_ibat_h, &spr_write_ibatl_h,
759 0x00000000);
760 spr_register(env, SPR_IBAT5U, "IBAT5U",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_ibat_h, &spr_write_ibatu_h,
763 0x00000000);
764 spr_register(env, SPR_IBAT5L, "IBAT5L",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_ibat_h, &spr_write_ibatl_h,
767 0x00000000);
768 spr_register(env, SPR_IBAT6U, "IBAT6U",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_ibat_h, &spr_write_ibatu_h,
771 0x00000000);
772 spr_register(env, SPR_IBAT6L, "IBAT6L",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_ibat_h, &spr_write_ibatl_h,
775 0x00000000);
776 spr_register(env, SPR_IBAT7U, "IBAT7U",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_ibat_h, &spr_write_ibatu_h,
779 0x00000000);
780 spr_register(env, SPR_IBAT7L, "IBAT7L",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_ibat_h, &spr_write_ibatl_h,
783 0x00000000);
784 spr_register(env, SPR_DBAT4U, "DBAT4U",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_dbat_h, &spr_write_dbatu_h,
787 0x00000000);
788 spr_register(env, SPR_DBAT4L, "DBAT4L",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_dbat_h, &spr_write_dbatl_h,
791 0x00000000);
792 spr_register(env, SPR_DBAT5U, "DBAT5U",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_dbat_h, &spr_write_dbatu_h,
795 0x00000000);
796 spr_register(env, SPR_DBAT5L, "DBAT5L",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_dbat_h, &spr_write_dbatl_h,
799 0x00000000);
800 spr_register(env, SPR_DBAT6U, "DBAT6U",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_dbat_h, &spr_write_dbatu_h,
803 0x00000000);
804 spr_register(env, SPR_DBAT6L, "DBAT6L",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_dbat_h, &spr_write_dbatl_h,
807 0x00000000);
808 spr_register(env, SPR_DBAT7U, "DBAT7U",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_dbat_h, &spr_write_dbatu_h,
811 0x00000000);
812 spr_register(env, SPR_DBAT7L, "DBAT7L",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_dbat_h, &spr_write_dbatl_h,
815 0x00000000);
a750fc0b 816 env->nb_BATs += 4;
f2e63a42 817#endif
3fc6c082
FB		 818}
819
820/* Generic PowerPC time base */
821static void gen_tbl (CPUPPCState *env)
822{
823 spr_register(env, SPR_VTBL, "TBL",
824 &spr_read_tbl, SPR_NOACCESS,
825 &spr_read_tbl, SPR_NOACCESS,
826 0x00000000);
827 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 828 &spr_read_tbl, SPR_NOACCESS,
829 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 830 0x00000000);
831 spr_register(env, SPR_VTBU, "TBU",
832 &spr_read_tbu, SPR_NOACCESS,
833 &spr_read_tbu, SPR_NOACCESS,
834 0x00000000);
835 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 836 &spr_read_tbu, SPR_NOACCESS,
837 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 838 0x00000000);
839}
840
76a66253
JM		 841/* Softare table search registers */
842static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
843{
f2e63a42 844#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 845 env->nb_tlb = nb_tlbs;
846 env->nb_ways = nb_ways;
847 env->id_tlbs = 1;
1c53accc 848 env->tlb_type = TLB_6XX;
76a66253
JM		 849 spr_register(env, SPR_DMISS, "DMISS",
850 SPR_NOACCESS, SPR_NOACCESS,
851 &spr_read_generic, SPR_NOACCESS,
852 0x00000000);
853 spr_register(env, SPR_DCMP, "DCMP",
854 SPR_NOACCESS, SPR_NOACCESS,
855 &spr_read_generic, SPR_NOACCESS,
856 0x00000000);
857 spr_register(env, SPR_HASH1, "HASH1",
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_generic, SPR_NOACCESS,
860 0x00000000);
861 spr_register(env, SPR_HASH2, "HASH2",
862 SPR_NOACCESS, SPR_NOACCESS,
863 &spr_read_generic, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_IMISS, "IMISS",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, SPR_NOACCESS,
868 0x00000000);
869 spr_register(env, SPR_ICMP, "ICMP",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic, SPR_NOACCESS,
872 0x00000000);
873 spr_register(env, SPR_RPA, "RPA",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, &spr_write_generic,
876 0x00000000);
f2e63a42 877#endif
76a66253
JM		 878}
879
880/* SPR common to MPC755 and G2 */
881static void gen_spr_G2_755 (CPUPPCState *env)
882{
883 /* SGPRs */
884 spr_register(env, SPR_SPRG4, "SPRG4",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_generic,
887 0x00000000);
888 spr_register(env, SPR_SPRG5, "SPRG5",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, &spr_write_generic,
891 0x00000000);
892 spr_register(env, SPR_SPRG6, "SPRG6",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_generic,
895 0x00000000);
896 spr_register(env, SPR_SPRG7, "SPRG7",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, &spr_write_generic,
899 0x00000000);
76a66253
JM		 900}
901
3fc6c082
FB		 902/* SPR common to all 7xx PowerPC implementations */
903static void gen_spr_7xx (CPUPPCState *env)
904{
905 /* Breakpoints */
906 /* XXX : not implemented */
907 spr_register(env, SPR_DABR, "DABR",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 /* XXX : not implemented */
912 spr_register(env, SPR_IABR, "IABR",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916 /* Cache management */
917 /* XXX : not implemented */
918 spr_register(env, SPR_ICTC, "ICTC",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 /* Performance monitors */
923 /* XXX : not implemented */
924 spr_register(env, SPR_MMCR0, "MMCR0",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* XXX : not implemented */
929 spr_register(env, SPR_MMCR1, "MMCR1",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933 /* XXX : not implemented */
934 spr_register(env, SPR_PMC1, "PMC1",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938 /* XXX : not implemented */
939 spr_register(env, SPR_PMC2, "PMC2",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* XXX : not implemented */
944 spr_register(env, SPR_PMC3, "PMC3",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948 /* XXX : not implemented */
949 spr_register(env, SPR_PMC4, "PMC4",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953 /* XXX : not implemented */
a750fc0b 954 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, SPR_NOACCESS,
957 0x00000000);
578bb252 958 /* XXX : not implemented */
3fc6c082
FB		 959 spr_register(env, SPR_UMMCR0, "UMMCR0",
960 &spr_read_ureg, SPR_NOACCESS,
961 &spr_read_ureg, SPR_NOACCESS,
962 0x00000000);
578bb252 963 /* XXX : not implemented */
3fc6c082
FB		 964 spr_register(env, SPR_UMMCR1, "UMMCR1",
965 &spr_read_ureg, SPR_NOACCESS,
966 &spr_read_ureg, SPR_NOACCESS,
967 0x00000000);
578bb252 968 /* XXX : not implemented */
3fc6c082
FB		 969 spr_register(env, SPR_UPMC1, "UPMC1",
970 &spr_read_ureg, SPR_NOACCESS,
971 &spr_read_ureg, SPR_NOACCESS,
972 0x00000000);
578bb252 973 /* XXX : not implemented */
3fc6c082
FB		 974 spr_register(env, SPR_UPMC2, "UPMC2",
975 &spr_read_ureg, SPR_NOACCESS,
976 &spr_read_ureg, SPR_NOACCESS,
977 0x00000000);
578bb252 978 /* XXX : not implemented */
3fc6c082
FB		 979 spr_register(env, SPR_UPMC3, "UPMC3",
980 &spr_read_ureg, SPR_NOACCESS,
981 &spr_read_ureg, SPR_NOACCESS,
982 0x00000000);
578bb252 983 /* XXX : not implemented */
3fc6c082
FB		 984 spr_register(env, SPR_UPMC4, "UPMC4",
985 &spr_read_ureg, SPR_NOACCESS,
986 &spr_read_ureg, SPR_NOACCESS,
987 0x00000000);
578bb252 988 /* XXX : not implemented */
a750fc0b 989 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
a750fc0b 993 /* External access control */
3fc6c082 994 /* XXX : not implemented */
a750fc0b 995 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
a750fc0b
JM		 999}
1000
1001static void gen_spr_thrm (CPUPPCState *env)
1002{
1003 /* Thermal management */
3fc6c082 1004 /* XXX : not implemented */
a750fc0b 1005 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009 /* XXX : not implemented */
a750fc0b 1010 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
3fc6c082 1014 /* XXX : not implemented */
a750fc0b 1015 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019}
1020
1021/* SPR specific to PowerPC 604 implementation */
1022static void gen_spr_604 (CPUPPCState *env)
1023{
1024 /* Processor identification */
1025 spr_register(env, SPR_PIR, "PIR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_pir,
1028 0x00000000);
1029 /* Breakpoints */
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_IABR, "IABR",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_DABR, "DABR",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 /* Performance counters */
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_MMCR0, "MMCR0",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* XXX : not implemented */
3fc6c082
FB		 1047 spr_register(env, SPR_PMC1, "PMC1",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_PMC2, "PMC2",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* XXX : not implemented */
a750fc0b 1057 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, SPR_NOACCESS,
1060 0x00000000);
1061 /* XXX : not implemented */
1062 spr_register(env, SPR_SDA, "SDA",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, SPR_NOACCESS,
1065 0x00000000);
1066 /* External access control */
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_EAR, "EAR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072}
1073
76a66253
JM		 1074/* SPR specific to PowerPC 603 implementation */
1075static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1076{
76a66253
JM		 1077 /* External access control */
1078 /* XXX : not implemented */
1079 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1080 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
3fc6c082
FB		 1083}
1084
76a66253
JM		 1085/* SPR specific to PowerPC G2 implementation */
1086static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1087{
76a66253
JM		 1088 /* Memory base address */
1089 /* MBAR */
578bb252 1090 /* XXX : not implemented */
76a66253
JM		 1091 spr_register(env, SPR_MBAR, "MBAR",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_generic, &spr_write_generic,
1094 0x00000000);
76a66253 1095 /* Exception processing */
363be49c 1096 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1097 SPR_NOACCESS, SPR_NOACCESS,
1098 &spr_read_generic, &spr_write_generic,
1099 0x00000000);
363be49c 1100 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 /* Breakpoints */
1105 /* XXX : not implemented */
1106 spr_register(env, SPR_DABR, "DABR",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_generic, &spr_write_generic,
1109 0x00000000);
1110 /* XXX : not implemented */
1111 spr_register(env, SPR_DABR2, "DABR2",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* XXX : not implemented */
1116 spr_register(env, SPR_IABR, "IABR",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
1120 /* XXX : not implemented */
1121 spr_register(env, SPR_IABR2, "IABR2",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_IBCR, "IBCR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 /* XXX : not implemented */
1131 spr_register(env, SPR_DBCR, "DBCR",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, &spr_write_generic,
1134 0x00000000);
1135}
1136
1137/* SPR specific to PowerPC 602 implementation */
1138static void gen_spr_602 (CPUPPCState *env)
1139{
1140 /* ESA registers */
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_SER, "SER",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, &spr_write_generic,
1145 0x00000000);
1146 /* XXX : not implemented */
1147 spr_register(env, SPR_SEBR, "SEBR",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 /* XXX : not implemented */
a750fc0b 1152 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 /* Floating point status */
1157 /* XXX : not implemented */
1158 spr_register(env, SPR_SP, "SP",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_generic,
1161 0x00000000);
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_LT, "LT",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 /* Watchdog timer */
1168 /* XXX : not implemented */
1169 spr_register(env, SPR_TCR, "TCR",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* Interrupt base */
1174 spr_register(env, SPR_IBR, "IBR",
1175 SPR_NOACCESS, SPR_NOACCESS,
1176 &spr_read_generic, &spr_write_generic,
1177 0x00000000);
a750fc0b
JM		 1178 /* XXX : not implemented */
1179 spr_register(env, SPR_IABR, "IABR",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
76a66253
JM		 1183}
1184
1185/* SPR specific to PowerPC 601 implementation */
1186static void gen_spr_601 (CPUPPCState *env)
1187{
1188 /* Multiplication/division register */
1189 /* MQ */
1190 spr_register(env, SPR_MQ, "MQ",
1191 &spr_read_generic, &spr_write_generic,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* RTC registers */
1195 spr_register(env, SPR_601_RTCU, "RTCU",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 SPR_NOACCESS, &spr_write_601_rtcu,
1198 0x00000000);
1199 spr_register(env, SPR_601_VRTCU, "RTCU",
1200 &spr_read_601_rtcu, SPR_NOACCESS,
1201 &spr_read_601_rtcu, SPR_NOACCESS,
1202 0x00000000);
1203 spr_register(env, SPR_601_RTCL, "RTCL",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 SPR_NOACCESS, &spr_write_601_rtcl,
1206 0x00000000);
1207 spr_register(env, SPR_601_VRTCL, "RTCL",
1208 &spr_read_601_rtcl, SPR_NOACCESS,
1209 &spr_read_601_rtcl, SPR_NOACCESS,
1210 0x00000000);
1211 /* Timer */
1212#if 0 /* ? */
1213 spr_register(env, SPR_601_UDECR, "UDECR",
1214 &spr_read_decr, SPR_NOACCESS,
1215 &spr_read_decr, SPR_NOACCESS,
1216 0x00000000);
1217#endif
1218 /* External access control */
1219 /* XXX : not implemented */
1220 spr_register(env, SPR_EAR, "EAR",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* Memory management */
f2e63a42 1225#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1226 spr_register(env, SPR_IBAT0U, "IBAT0U",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_601_ubat, &spr_write_601_ubatu,
1229 0x00000000);
1230 spr_register(env, SPR_IBAT0L, "IBAT0L",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_601_ubat, &spr_write_601_ubatl,
1233 0x00000000);
1234 spr_register(env, SPR_IBAT1U, "IBAT1U",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_601_ubat, &spr_write_601_ubatu,
1237 0x00000000);
1238 spr_register(env, SPR_IBAT1L, "IBAT1L",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_601_ubat, &spr_write_601_ubatl,
1241 0x00000000);
1242 spr_register(env, SPR_IBAT2U, "IBAT2U",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_601_ubat, &spr_write_601_ubatu,
1245 0x00000000);
1246 spr_register(env, SPR_IBAT2L, "IBAT2L",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_601_ubat, &spr_write_601_ubatl,
1249 0x00000000);
1250 spr_register(env, SPR_IBAT3U, "IBAT3U",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_601_ubat, &spr_write_601_ubatu,
1253 0x00000000);
1254 spr_register(env, SPR_IBAT3L, "IBAT3L",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_601_ubat, &spr_write_601_ubatl,
1257 0x00000000);
a750fc0b 1258 env->nb_BATs = 4;
f2e63a42 1259#endif
a750fc0b
JM		 1260}
1261
1262static void gen_spr_74xx (CPUPPCState *env)
1263{
1264 /* Processor identification */
1265 spr_register(env, SPR_PIR, "PIR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_pir,
1268 0x00000000);
1269 /* XXX : not implemented */
1270 spr_register(env, SPR_MMCR2, "MMCR2",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
578bb252 1274 /* XXX : not implemented */
a750fc0b
JM		 1275 spr_register(env, SPR_UMMCR2, "UMMCR2",
1276 &spr_read_ureg, SPR_NOACCESS,
1277 &spr_read_ureg, SPR_NOACCESS,
1278 0x00000000);
1279 /* XXX: not implemented */
1280 spr_register(env, SPR_BAMR, "BAMR",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1283 0x00000000);
578bb252 1284 /* XXX : not implemented */
a750fc0b
JM		 1285 spr_register(env, SPR_MSSCR0, "MSSCR0",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289 /* Hardware implementation registers */
1290 /* XXX : not implemented */
1291 spr_register(env, SPR_HID0, "HID0",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 /* XXX : not implemented */
1296 spr_register(env, SPR_HID1, "HID1",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1299 0x00000000);
1300 /* Altivec */
1301 spr_register(env, SPR_VRSAVE, "VRSAVE",
1302 &spr_read_generic, &spr_write_generic,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
bd928eba
JM		 1305 /* XXX : not implemented */
1306 spr_register(env, SPR_L2CR, "L2CR",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
cf8358c8
AJ		 1310 /* Not strictly an SPR */
1311 vscr_init(env, 0x00010000);
a750fc0b
JM		 1312}
1313
a750fc0b
JM		 1314static void gen_l3_ctrl (CPUPPCState *env)
1315{
1316 /* L3CR */
1317 /* XXX : not implemented */
1318 spr_register(env, SPR_L3CR, "L3CR",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1321 0x00000000);
1322 /* L3ITCR0 */
578bb252 1323 /* XXX : not implemented */
a750fc0b
JM		 1324 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
a750fc0b 1328 /* L3PM */
578bb252 1329 /* XXX : not implemented */
a750fc0b
JM		 1330 spr_register(env, SPR_L3PM, "L3PM",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334}
a750fc0b 1335
578bb252 1336static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1337{
f2e63a42 1338#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1339 env->nb_tlb = nb_tlbs;
1340 env->nb_ways = nb_ways;
1341 env->id_tlbs = 1;
1c53accc 1342 env->tlb_type = TLB_6XX;
578bb252 1343 /* XXX : not implemented */
a750fc0b
JM		 1344 spr_register(env, SPR_PTEHI, "PTEHI",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
578bb252 1348 /* XXX : not implemented */
a750fc0b
JM		 1349 spr_register(env, SPR_PTELO, "PTELO",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
578bb252 1353 /* XXX : not implemented */
a750fc0b
JM		 1354 spr_register(env, SPR_TLBMISS, "TLBMISS",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
f2e63a42 1358#endif
76a66253
JM		 1359}
1360
01662f3e
AG		 1361#if !defined(CONFIG_USER_ONLY)
1362static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1363{
1364 TCGv t0 = tcg_temp_new();
1365
1366 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1367 gen_store_spr(sprn, t0);
1368 tcg_temp_free(t0);
1369}
1370
1371static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1372{
1ff7854e 1373 TCGv_i32 t0 = tcg_const_i32(sprn);
01662f3e 1374 gen_helper_booke206_tlbflush(t0);
1ff7854e 1375 tcg_temp_free_i32(t0);
01662f3e
AG		 1376}
1377
1378static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1379{
1ff7854e 1380 TCGv_i32 t0 = tcg_const_i32(sprn);
01662f3e 1381 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1ff7854e 1382 tcg_temp_free_i32(t0);
01662f3e
AG		 1383}
1384#endif
1385
80d11f44 1386static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1387{
80d11f44
JM		 1388 spr_register(env, SPR_USPRG4, "USPRG4",
1389 &spr_read_ureg, SPR_NOACCESS,
1390 &spr_read_ureg, SPR_NOACCESS,
1391 0x00000000);
1392 spr_register(env, SPR_USPRG5, "USPRG5",
1393 &spr_read_ureg, SPR_NOACCESS,
1394 &spr_read_ureg, SPR_NOACCESS,
1395 0x00000000);
1396 spr_register(env, SPR_USPRG6, "USPRG6",
1397 &spr_read_ureg, SPR_NOACCESS,
1398 &spr_read_ureg, SPR_NOACCESS,
1399 0x00000000);
1400 spr_register(env, SPR_USPRG7, "USPRG7",
1401 &spr_read_ureg, SPR_NOACCESS,
1402 &spr_read_ureg, SPR_NOACCESS,
76a66253 1403 0x00000000);
80d11f44
JM		 1404}
1405
1406/* PowerPC BookE SPR */
1407static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1408{
b55266b5 1409 const char *ivor_names[64] = {
80d11f44
JM		 1410 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1411 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1412 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1413 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1414 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1415 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1416 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1417 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1418 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1419 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1420 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1421 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1422 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1423 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1424 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1425 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1426 };
1427#define SPR_BOOKE_IVORxx (-1)
1428 int ivor_sprn[64] = {
1429 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1430 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1431 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1432 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1433 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1434 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1435 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1436 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1437 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
e9205258
AG		 1438 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1439 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
80d11f44
JM		 1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1443 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1444 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1445 };
1446 int i;
1447
76a66253 1448 /* Interrupt processing */
363be49c 1449 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
363be49c
JM		 1453 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_generic, &spr_write_generic,
1456 0x00000000);
76a66253
JM		 1457 /* Debug */
1458 /* XXX : not implemented */
1459 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463 /* XXX : not implemented */
1464 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
1468 /* XXX : not implemented */
76a66253
JM		 1469 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
1473 /* XXX : not implemented */
1474 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 /* XXX : not implemented */
76a66253
JM		 1479 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 /* XXX : not implemented */
1484 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1495 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1496 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1497 0x00000000);
1498 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502 spr_register(env, SPR_BOOKE_ESR, "ESR",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1505 0x00000000);
363be49c
JM		 1506 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1507 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1508 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1509 0x00000000);
1510 /* Exception vectors */
80d11f44
JM		 1511 for (i = 0; i < 64; i++) {
1512 if (ivor_mask & (1ULL << i)) {
1513 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1514 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1515 exit(1);
1516 }
1517 spr_register(env, ivor_sprn[i], ivor_names[i],
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_excp_vector,
1520 0x00000000);
1521 }
1522 }
76a66253
JM		 1523 spr_register(env, SPR_BOOKE_PID, "PID",
1524 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1525 &spr_read_generic, &spr_write_booke_pid,
76a66253
JM		 1526 0x00000000);
1527 spr_register(env, SPR_BOOKE_TCR, "TCR",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_booke_tcr,
1530 0x00000000);
1531 spr_register(env, SPR_BOOKE_TSR, "TSR",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_booke_tsr,
1534 0x00000000);
1535 /* Timer */
1536 spr_register(env, SPR_DECR, "DECR",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_decr, &spr_write_decr,
1539 0x00000000);
1540 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1541 SPR_NOACCESS, SPR_NOACCESS,
1542 SPR_NOACCESS, &spr_write_generic,
1543 0x00000000);
1544 /* SPRGs */
1545 spr_register(env, SPR_USPRG0, "USPRG0",
1546 &spr_read_generic, &spr_write_generic,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 spr_register(env, SPR_SPRG4, "SPRG4",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
76a66253
JM		 1553 spr_register(env, SPR_SPRG5, "SPRG5",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
76a66253
JM		 1557 spr_register(env, SPR_SPRG6, "SPRG6",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
76a66253
JM		 1561 spr_register(env, SPR_SPRG7, "SPRG7",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
76a66253
JM		 1565}
1566
01662f3e
AG		 1567static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1568 uint32_t maxsize, uint32_t flags,
1569 uint32_t nentries)
1570{
1571 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1572 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1573 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1574 flags | nentries;
1575}
1576
1577/* BookE 2.06 storage control registers */
1578static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1579 uint32_t *tlbncfg)
363be49c 1580{
f2e63a42 1581#if !defined(CONFIG_USER_ONLY)
b55266b5 1582 const char *mas_names[8] = {
80d11f44
JM		 1583 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1584 };
1585 int mas_sprn[8] = {
1586 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1587 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1588 };
1589 int i;
1590
363be49c 1591 /* TLB assist registers */
578bb252 1592 /* XXX : not implemented */
80d11f44
JM		 1593 for (i = 0; i < 8; i++) {
1594 if (mas_mask & (1 << i)) {
1595 spr_register(env, mas_sprn[i], mas_names[i],
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_generic,
1598 0x00000000);
1599 }
1600 }
363be49c 1601 if (env->nb_pids > 1) {
578bb252 1602 /* XXX : not implemented */
363be49c
JM		 1603 spr_register(env, SPR_BOOKE_PID1, "PID1",
1604 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1605 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1606 0x00000000);
1607 }
1608 if (env->nb_pids > 2) {
578bb252 1609 /* XXX : not implemented */
363be49c
JM		 1610 spr_register(env, SPR_BOOKE_PID2, "PID2",
1611 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1612 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1613 0x00000000);
1614 }
578bb252 1615 /* XXX : not implemented */
65f9ee8d 1616 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, SPR_NOACCESS,
1619 0x00000000); /* TOFIX */
363be49c
JM		 1620 switch (env->nb_ways) {
1621 case 4:
1622 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, SPR_NOACCESS,
01662f3e 1625 tlbncfg[3]);
363be49c
JM		 1626 /* Fallthru */
1627 case 3:
1628 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, SPR_NOACCESS,
01662f3e 1631 tlbncfg[2]);
363be49c
JM		 1632 /* Fallthru */
1633 case 2:
1634 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, SPR_NOACCESS,
01662f3e 1637 tlbncfg[1]);
363be49c
JM		 1638 /* Fallthru */
1639 case 1:
1640 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
01662f3e 1643 tlbncfg[0]);
363be49c
JM		 1644 /* Fallthru */
1645 case 0:
1646 default:
1647 break;
1648 }
f2e63a42 1649#endif
01662f3e
AG		 1650
1651 gen_spr_usprgh(env);
363be49c
JM		 1652}
1653
76a66253
JM		 1654/* SPR specific to PowerPC 440 implementation */
1655static void gen_spr_440 (CPUPPCState *env)
1656{
1657 /* Cache control */
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_440_DNV0, "DNV0",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 /* XXX : not implemented */
1664 spr_register(env, SPR_440_DNV1, "DNV1",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_generic,
1667 0x00000000);
1668 /* XXX : not implemented */
1669 spr_register(env, SPR_440_DNV2, "DNV2",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673 /* XXX : not implemented */
1674 spr_register(env, SPR_440_DNV3, "DNV3",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, &spr_write_generic,
1677 0x00000000);
1678 /* XXX : not implemented */
2662a059 1679 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1682 0x00000000);
1683 /* XXX : not implemented */
2662a059 1684 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 /* XXX : not implemented */
2662a059 1689 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
2662a059 1694 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_440_DVLIM, "DVLIM",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0x00000000);
1703 /* XXX : not implemented */
1704 spr_register(env, SPR_440_INV0, "INV0",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 /* XXX : not implemented */
1709 spr_register(env, SPR_440_INV1, "INV1",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_generic,
1712 0x00000000);
1713 /* XXX : not implemented */
1714 spr_register(env, SPR_440_INV2, "INV2",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 /* XXX : not implemented */
1719 spr_register(env, SPR_440_INV3, "INV3",
1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, &spr_write_generic,
1722 0x00000000);
1723 /* XXX : not implemented */
2662a059 1724 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_generic,
1727 0x00000000);
1728 /* XXX : not implemented */
2662a059 1729 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 /* XXX : not implemented */
2662a059 1734 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_generic,
1737 0x00000000);
1738 /* XXX : not implemented */
2662a059 1739 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_440_IVLIM, "IVLIM",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 /* Cache debug */
1749 /* XXX : not implemented */
2662a059 1750 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, SPR_NOACCESS,
1753 0x00000000);
1754 /* XXX : not implemented */
2662a059 1755 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, SPR_NOACCESS,
1758 0x00000000);
1759 /* XXX : not implemented */
2662a059 1760 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, SPR_NOACCESS,
1763 0x00000000);
1764 /* XXX : not implemented */
2662a059 1765 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, SPR_NOACCESS,
1768 0x00000000);
1769 /* XXX : not implemented */
2662a059 1770 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, SPR_NOACCESS,
1773 0x00000000);
1774 /* XXX : not implemented */
1775 spr_register(env, SPR_440_DBDR, "DBDR",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779 /* Processor control */
1780 spr_register(env, SPR_4xx_CCR0, "CCR0",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
1784 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, SPR_NOACCESS,
1787 0x00000000);
1788 /* Storage control */
1789 spr_register(env, SPR_440_MMUCR, "MMUCR",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_generic,
1792 0x00000000);
1793}
1794
1795/* SPR shared between PowerPC 40x implementations */
1796static void gen_spr_40x (CPUPPCState *env)
1797{
1798 /* Cache */
5cbdb3a3 1799 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1800 spr_register(env, SPR_40x_DCCR, "DCCR",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
5cbdb3a3 1804 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1805 spr_register(env, SPR_40x_ICCR, "ICCR",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
5cbdb3a3 1809 /* not emulated, as QEMU do not emulate caches */
2662a059 1810 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, SPR_NOACCESS,
1813 0x00000000);
76a66253
JM		 1814 /* Exception */
1815 spr_register(env, SPR_40x_DEAR, "DEAR",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819 spr_register(env, SPR_40x_ESR, "ESR",
1820 SPR_NOACCESS, SPR_NOACCESS,
1821 &spr_read_generic, &spr_write_generic,
1822 0x00000000);
1823 spr_register(env, SPR_40x_EVPR, "EVPR",
1824 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1825 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1826 0x00000000);
1827 spr_register(env, SPR_40x_SRR2, "SRR2",
1828 &spr_read_generic, &spr_write_generic,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 spr_register(env, SPR_40x_SRR3, "SRR3",
1832 &spr_read_generic, &spr_write_generic,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835 /* Timers */
1836 spr_register(env, SPR_40x_PIT, "PIT",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_40x_pit, &spr_write_40x_pit,
1839 0x00000000);
1840 spr_register(env, SPR_40x_TCR, "TCR",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_booke_tcr,
1843 0x00000000);
1844 spr_register(env, SPR_40x_TSR, "TSR",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_booke_tsr,
1847 0x00000000);
2662a059
JM		 1848}
1849
1850/* SPR specific to PowerPC 405 implementation */
1851static void gen_spr_405 (CPUPPCState *env)
1852{
1853 /* MMU */
1854 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, &spr_write_generic,
1857 0x00000000);
2662a059 1858 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1861 0x00700000);
1862 /* Debug interface */
76a66253
JM		 1863 /* XXX : not implemented */
1864 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1865 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1866 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1867 0x00000000);
1868 /* XXX : not implemented */
2662a059
JM		 1869 spr_register(env, SPR_405_DBCR1, "DBCR1",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873 /* XXX : not implemented */
76a66253
JM		 1874 spr_register(env, SPR_40x_DBSR, "DBSR",
1875 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1876 &spr_read_generic, &spr_write_clear,
1877 /* Last reset was system reset */
76a66253
JM		 1878 0x00000300);
1879 /* XXX : not implemented */
2662a059 1880 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1881 SPR_NOACCESS, SPR_NOACCESS,
1882 &spr_read_generic, &spr_write_generic,
1883 0x00000000);
2662a059 1884 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1885 SPR_NOACCESS, SPR_NOACCESS,
1886 &spr_read_generic, &spr_write_generic,
1887 0x00000000);
2662a059
JM		 1888 /* XXX : not implemented */
1889 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, &spr_write_generic,
2662a059 1892 0x00000000);
76a66253 1893 /* XXX : not implemented */
2662a059 1894 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 /* XXX : not implemented */
2662a059 1899 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_generic,
1902 0x00000000);
2662a059 1903 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
1908 spr_register(env, SPR_405_IAC3, "IAC3",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_405_IAC4, "IAC4",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 /* Storage control */
035feb88 1918 /* XXX: TODO: not implemented */
76a66253
JM		 1919 spr_register(env, SPR_405_SLER, "SLER",
1920 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1921 &spr_read_generic, &spr_write_40x_sler,
76a66253 1922 0x00000000);
2662a059
JM		 1923 spr_register(env, SPR_40x_ZPR, "ZPR",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
76a66253
JM		 1927 /* XXX : not implemented */
1928 spr_register(env, SPR_405_SU0R, "SU0R",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* SPRG */
1933 spr_register(env, SPR_USPRG0, "USPRG0",
1934 &spr_read_ureg, SPR_NOACCESS,
1935 &spr_read_ureg, SPR_NOACCESS,
1936 0x00000000);
1937 spr_register(env, SPR_SPRG4, "SPRG4",
1938 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1939 &spr_read_generic, &spr_write_generic,
76a66253 1940 0x00000000);
76a66253
JM		 1941 spr_register(env, SPR_SPRG5, "SPRG5",
1942 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1943 spr_read_generic, &spr_write_generic,
76a66253 1944 0x00000000);
76a66253
JM		 1945 spr_register(env, SPR_SPRG6, "SPRG6",
1946 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1947 spr_read_generic, &spr_write_generic,
76a66253 1948 0x00000000);
76a66253
JM		 1949 spr_register(env, SPR_SPRG7, "SPRG7",
1950 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1951 spr_read_generic, &spr_write_generic,
76a66253 1952 0x00000000);
80d11f44 1953 gen_spr_usprgh(env);
76a66253
JM		 1954}
1955
1956/* SPR shared between PowerPC 401 & 403 implementations */
1957static void gen_spr_401_403 (CPUPPCState *env)
1958{
1959 /* Time base */
1960 spr_register(env, SPR_403_VTBL, "TBL",
1961 &spr_read_tbl, SPR_NOACCESS,
1962 &spr_read_tbl, SPR_NOACCESS,
1963 0x00000000);
1964 spr_register(env, SPR_403_TBL, "TBL",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 SPR_NOACCESS, &spr_write_tbl,
1967 0x00000000);
1968 spr_register(env, SPR_403_VTBU, "TBU",
1969 &spr_read_tbu, SPR_NOACCESS,
1970 &spr_read_tbu, SPR_NOACCESS,
1971 0x00000000);
1972 spr_register(env, SPR_403_TBU, "TBU",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 SPR_NOACCESS, &spr_write_tbu,
1975 0x00000000);
1976 /* Debug */
5cbdb3a3 1977 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1978 spr_register(env, SPR_403_CDBCR, "CDBCR",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982}
1983
2662a059
JM		 1984/* SPR specific to PowerPC 401 implementation */
1985static void gen_spr_401 (CPUPPCState *env)
1986{
1987 /* Debug interface */
1988 /* XXX : not implemented */
1989 spr_register(env, SPR_40x_DBCR0, "DBCR",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_40x_dbcr0,
1992 0x00000000);
1993 /* XXX : not implemented */
1994 spr_register(env, SPR_40x_DBSR, "DBSR",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_clear,
1997 /* Last reset was system reset */
1998 0x00000300);
1999 /* XXX : not implemented */
2000 spr_register(env, SPR_40x_DAC1, "DAC",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004 /* XXX : not implemented */
2005 spr_register(env, SPR_40x_IAC1, "IAC",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 /* Storage control */
035feb88 2010 /* XXX: TODO: not implemented */
2662a059
JM		 2011 spr_register(env, SPR_405_SLER, "SLER",
2012 SPR_NOACCESS, SPR_NOACCESS,
2013 &spr_read_generic, &spr_write_40x_sler,
2014 0x00000000);
5cbdb3a3 2015 /* not emulated, as QEMU never does speculative access */
035feb88
JM		 2016 spr_register(env, SPR_40x_SGR, "SGR",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, &spr_write_generic,
2019 0xFFFFFFFF);
5cbdb3a3 2020 /* not emulated, as QEMU do not emulate caches */
035feb88
JM		 2021 spr_register(env, SPR_40x_DCWR, "DCWR",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_generic,
2024 0x00000000);
2662a059
JM		 2025}
2026
a750fc0b
JM		 2027static void gen_spr_401x2 (CPUPPCState *env)
2028{
2029 gen_spr_401(env);
2030 spr_register(env, SPR_40x_PID, "PID",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 spr_register(env, SPR_40x_ZPR, "ZPR",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038}
2039
76a66253
JM		 2040/* SPR specific to PowerPC 403 implementation */
2041static void gen_spr_403 (CPUPPCState *env)
2042{
2662a059
JM		 2043 /* Debug interface */
2044 /* XXX : not implemented */
2045 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_40x_dbcr0,
2048 0x00000000);
2049 /* XXX : not implemented */
2050 spr_register(env, SPR_40x_DBSR, "DBSR",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_clear,
2053 /* Last reset was system reset */
2054 0x00000300);
2055 /* XXX : not implemented */
2056 spr_register(env, SPR_40x_DAC1, "DAC1",
2057 SPR_NOACCESS, SPR_NOACCESS,
2058 &spr_read_generic, &spr_write_generic,
2059 0x00000000);
578bb252 2060 /* XXX : not implemented */
2662a059
JM		 2061 spr_register(env, SPR_40x_DAC2, "DAC2",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 &spr_read_generic, &spr_write_generic,
2064 0x00000000);
2065 /* XXX : not implemented */
2066 spr_register(env, SPR_40x_IAC1, "IAC1",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_generic, &spr_write_generic,
2069 0x00000000);
578bb252 2070 /* XXX : not implemented */
2662a059
JM		 2071 spr_register(env, SPR_40x_IAC2, "IAC2",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, &spr_write_generic,
2074 0x00000000);
a750fc0b
JM		 2075}
2076
2077static void gen_spr_403_real (CPUPPCState *env)
2078{
76a66253
JM		 2079 spr_register(env, SPR_403_PBL1, "PBL1",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_403_pbr, &spr_write_403_pbr,
2082 0x00000000);
2083 spr_register(env, SPR_403_PBU1, "PBU1",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_403_pbr, &spr_write_403_pbr,
2086 0x00000000);
2087 spr_register(env, SPR_403_PBL2, "PBL2",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_403_pbr, &spr_write_403_pbr,
2090 0x00000000);
2091 spr_register(env, SPR_403_PBU2, "PBU2",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_403_pbr, &spr_write_403_pbr,
2094 0x00000000);
a750fc0b
JM		 2095}
2096
2097static void gen_spr_403_mmu (CPUPPCState *env)
2098{
2099 /* MMU */
2100 spr_register(env, SPR_40x_PID, "PID",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
2662a059 2104 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_generic, &spr_write_generic,
2107 0x00000000);
2108}
2109
2110/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2111static void gen_spr_compress (CPUPPCState *env)
2112{
578bb252 2113 /* XXX : not implemented */
76a66253
JM		 2114 spr_register(env, SPR_401_SKR, "SKR",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118}
a750fc0b
JM		 2119
2120#if defined (TARGET_PPC64)
a750fc0b
JM		 2121/* SPR specific to PowerPC 620 */
2122static void gen_spr_620 (CPUPPCState *env)
2123{
082c6681
JM		 2124 /* Processor identification */
2125 spr_register(env, SPR_PIR, "PIR",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_pir,
2128 0x00000000);
2129 spr_register(env, SPR_ASR, "ASR",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_asr, &spr_write_asr,
2132 0x00000000);
2133 /* Breakpoints */
2134 /* XXX : not implemented */
2135 spr_register(env, SPR_IABR, "IABR",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, &spr_write_generic,
2138 0x00000000);
2139 /* XXX : not implemented */
2140 spr_register(env, SPR_DABR, "DABR",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
2144 /* XXX : not implemented */
2145 spr_register(env, SPR_SIAR, "SIAR",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, SPR_NOACCESS,
2148 0x00000000);
2149 /* XXX : not implemented */
2150 spr_register(env, SPR_SDA, "SDA",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, SPR_NOACCESS,
2153 0x00000000);
2154 /* XXX : not implemented */
2155 spr_register(env, SPR_620_PMC1R, "PMC1",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, SPR_NOACCESS,
2158 0x00000000);
2159 spr_register(env, SPR_620_PMC1W, "PMC1",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 SPR_NOACCESS, &spr_write_generic,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_620_PMC2R, "PMC2",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, SPR_NOACCESS,
2167 0x00000000);
2168 spr_register(env, SPR_620_PMC2W, "PMC2",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 SPR_NOACCESS, &spr_write_generic,
2171 0x00000000);
2172 /* XXX : not implemented */
2173 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, SPR_NOACCESS,
2176 0x00000000);
2177 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 SPR_NOACCESS, &spr_write_generic,
2180 0x00000000);
2181 /* External access control */
2182 /* XXX : not implemented */
2183 spr_register(env, SPR_EAR, "EAR",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187#if 0 // XXX: check this
578bb252 2188 /* XXX : not implemented */
a750fc0b
JM		 2189 spr_register(env, SPR_620_PMR0, "PMR0",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
578bb252 2193 /* XXX : not implemented */
a750fc0b
JM		 2194 spr_register(env, SPR_620_PMR1, "PMR1",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 0x00000000);
578bb252 2198 /* XXX : not implemented */
a750fc0b
JM		 2199 spr_register(env, SPR_620_PMR2, "PMR2",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_generic,
2202 0x00000000);
578bb252 2203 /* XXX : not implemented */
a750fc0b
JM		 2204 spr_register(env, SPR_620_PMR3, "PMR3",
2205 SPR_NOACCESS, SPR_NOACCESS,
2206 &spr_read_generic, &spr_write_generic,
2207 0x00000000);
578bb252 2208 /* XXX : not implemented */
a750fc0b
JM		 2209 spr_register(env, SPR_620_PMR4, "PMR4",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_generic,
2212 0x00000000);
578bb252 2213 /* XXX : not implemented */
a750fc0b
JM		 2214 spr_register(env, SPR_620_PMR5, "PMR5",
2215 SPR_NOACCESS, SPR_NOACCESS,
2216 &spr_read_generic, &spr_write_generic,
2217 0x00000000);
578bb252 2218 /* XXX : not implemented */
a750fc0b
JM		 2219 spr_register(env, SPR_620_PMR6, "PMR6",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
578bb252 2223 /* XXX : not implemented */
a750fc0b
JM		 2224 spr_register(env, SPR_620_PMR7, "PMR7",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0x00000000);
578bb252 2228 /* XXX : not implemented */
a750fc0b
JM		 2229 spr_register(env, SPR_620_PMR8, "PMR8",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
578bb252 2233 /* XXX : not implemented */
a750fc0b
JM		 2234 spr_register(env, SPR_620_PMR9, "PMR9",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
578bb252 2238 /* XXX : not implemented */
a750fc0b
JM		 2239 spr_register(env, SPR_620_PMRA, "PMR10",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
578bb252 2243 /* XXX : not implemented */
a750fc0b
JM		 2244 spr_register(env, SPR_620_PMRB, "PMR11",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_generic,
2247 0x00000000);
578bb252 2248 /* XXX : not implemented */
a750fc0b
JM		 2249 spr_register(env, SPR_620_PMRC, "PMR12",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
578bb252 2253 /* XXX : not implemented */
a750fc0b
JM		 2254 spr_register(env, SPR_620_PMRD, "PMR13",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
578bb252 2258 /* XXX : not implemented */
a750fc0b
JM		 2259 spr_register(env, SPR_620_PMRE, "PMR14",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
578bb252 2263 /* XXX : not implemented */
a750fc0b
JM		 2264 spr_register(env, SPR_620_PMRF, "PMR15",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
082c6681 2268#endif
578bb252 2269 /* XXX : not implemented */
082c6681 2270 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
578bb252 2274 /* XXX : not implemented */
082c6681
JM		 2275 spr_register(env, SPR_620_L2CR, "L2CR",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284}
a750fc0b 2285#endif /* defined (TARGET_PPC64) */
76a66253 2286
80d11f44 2287static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2288{
80d11f44
JM		 2289 /* Exception processing */
2290 spr_register(env, SPR_DSISR, "DSISR",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 spr_register(env, SPR_DAR, "DAR",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_generic,
2297 0x00000000);
2298 /* Timer */
2299 spr_register(env, SPR_DECR, "DECR",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_decr, &spr_write_decr,
2302 0x00000000);
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_MPC_EIE, "EIE",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 /* XXX : not implemented */
2309 spr_register(env, SPR_MPC_EID, "EID",
2310 SPR_NOACCESS, SPR_NOACCESS,
2311 &spr_read_generic, &spr_write_generic,
2312 0x00000000);
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_MPC_NRI, "NRI",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_MPC_CMPA, "CMPA",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* XXX : not implemented */
2324 spr_register(env, SPR_MPC_CMPB, "CMPB",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_MPC_CMPC, "CMPC",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_MPC_CMPD, "CMPD",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_MPC_ECR, "ECR",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_MPC_DER, "DER",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_MPC_CMPE, "CMPE",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_MPC_CMPF, "CMPF",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_MPC_CMPG, "CMPG",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_MPC_CMPH, "CMPH",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_MPC_BAR, "BAR",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_MPC_DPDR, "DPDR",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_MPC_IMMR, "IMMR",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403}
2404
2405static void gen_spr_5xx (CPUPPCState *env)
2406{
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512}
2513
2514static void gen_spr_8xx (CPUPPCState *env)
2515{
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 /* XXX : not implemented */
2537 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2538 SPR_NOACCESS, SPR_NOACCESS,
2539 &spr_read_generic, &spr_write_generic,
2540 0x00000000);
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 /* XXX : not implemented */
2547 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2548 SPR_NOACCESS, SPR_NOACCESS,
2549 &spr_read_generic, &spr_write_generic,
2550 0x00000000);
2551 /* XXX : not implemented */
2552 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2553 SPR_NOACCESS, SPR_NOACCESS,
2554 &spr_read_generic, &spr_write_generic,
2555 0x00000000);
2556 /* XXX : not implemented */
2557 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2558 SPR_NOACCESS, SPR_NOACCESS,
2559 &spr_read_generic, &spr_write_generic,
2560 0x00000000);
2561 /* XXX : not implemented */
2562 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2565 0x00000000);
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2570 0x00000000);
2571 /* XXX : not implemented */
2572 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2573 SPR_NOACCESS, SPR_NOACCESS,
2574 &spr_read_generic, &spr_write_generic,
2575 0x00000000);
2576 /* XXX : not implemented */
2577 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2578 SPR_NOACCESS, SPR_NOACCESS,
2579 &spr_read_generic, &spr_write_generic,
2580 0x00000000);
2581 /* XXX : not implemented */
2582 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2583 SPR_NOACCESS, SPR_NOACCESS,
2584 &spr_read_generic, &spr_write_generic,
2585 0x00000000);
2586 /* XXX : not implemented */
2587 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2588 SPR_NOACCESS, SPR_NOACCESS,
2589 &spr_read_generic, &spr_write_generic,
2590 0x00000000);
2591 /* XXX : not implemented */
2592 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2593 SPR_NOACCESS, SPR_NOACCESS,
2594 &spr_read_generic, &spr_write_generic,
2595 0x00000000);
2596 /* XXX : not implemented */
2597 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2598 SPR_NOACCESS, SPR_NOACCESS,
2599 &spr_read_generic, &spr_write_generic,
2600 0x00000000);
2601 /* XXX : not implemented */
2602 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2603 SPR_NOACCESS, SPR_NOACCESS,
2604 &spr_read_generic, &spr_write_generic,
2605 0x00000000);
2606 /* XXX : not implemented */
2607 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2608 SPR_NOACCESS, SPR_NOACCESS,
2609 &spr_read_generic, &spr_write_generic,
2610 0x00000000);
2611 /* XXX : not implemented */
2612 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2613 SPR_NOACCESS, SPR_NOACCESS,
2614 &spr_read_generic, &spr_write_generic,
2615 0x00000000);
2616 /* XXX : not implemented */
2617 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2618 SPR_NOACCESS, SPR_NOACCESS,
2619 &spr_read_generic, &spr_write_generic,
2620 0x00000000);
2621 /* XXX : not implemented */
2622 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2623 SPR_NOACCESS, SPR_NOACCESS,
2624 &spr_read_generic, &spr_write_generic,
2625 0x00000000);
2626 /* XXX : not implemented */
2627 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2628 SPR_NOACCESS, SPR_NOACCESS,
2629 &spr_read_generic, &spr_write_generic,
2630 0x00000000);
2631 /* XXX : not implemented */
2632 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2633 SPR_NOACCESS, SPR_NOACCESS,
2634 &spr_read_generic, &spr_write_generic,
2635 0x00000000);
2636 /* XXX : not implemented */
2637 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2638 SPR_NOACCESS, SPR_NOACCESS,
2639 &spr_read_generic, &spr_write_generic,
2640 0x00000000);
2641}
2642
2643// XXX: TODO
2644/*
2645 * AMR => SPR 29 (Power 2.04)
2646 * CTRL => SPR 136 (Power 2.04)
2647 * CTRL => SPR 152 (Power 2.04)
2648 * SCOMC => SPR 276 (64 bits ?)
2649 * SCOMD => SPR 277 (64 bits ?)
2650 * TBU40 => SPR 286 (Power 2.04 hypv)
2651 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2652 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2653 * HDSISR => SPR 306 (Power 2.04 hypv)
2654 * HDAR => SPR 307 (Power 2.04 hypv)
2655 * PURR => SPR 309 (Power 2.04 hypv)
2656 * HDEC => SPR 310 (Power 2.04 hypv)
2657 * HIOR => SPR 311 (hypv)
2658 * RMOR => SPR 312 (970)
2659 * HRMOR => SPR 313 (Power 2.04 hypv)
2660 * HSRR0 => SPR 314 (Power 2.04 hypv)
2661 * HSRR1 => SPR 315 (Power 2.04 hypv)
2662 * LPCR => SPR 316 (970)
2663 * LPIDR => SPR 317 (970)
80d11f44
JM		 2664 * EPR => SPR 702 (Power 2.04 emb)
2665 * perf => 768-783 (Power 2.04)
2666 * perf => 784-799 (Power 2.04)
2667 * PPR => SPR 896 (Power 2.04)
2668 * EPLC => SPR 947 (Power 2.04 emb)
2669 * EPSC => SPR 948 (Power 2.04 emb)
2670 * DABRX => 1015 (Power 2.04 hypv)
2671 * FPECR => SPR 1022 (?)
2672 * ... and more (thermal management, performance counters, ...)
2673 */
2674
2675/*****************************************************************************/
2676/* Exception vectors models */
2677static void init_excp_4xx_real (CPUPPCState *env)
2678{
2679#if !defined(CONFIG_USER_ONLY)
2680 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2681 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2682 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2683 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2684 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2685 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2686 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2687 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2688 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2689 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2690 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2691 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2692 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2693 /* Hardware reset vector */
2694 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2695#endif
2696}
2697
80d11f44
JM		 2698static void init_excp_4xx_softmmu (CPUPPCState *env)
2699{
2700#if !defined(CONFIG_USER_ONLY)
2701 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2702 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2703 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2704 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2705 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2706 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2707 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2708 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2709 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2710 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2711 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2712 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2713 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2714 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2715 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2716 env->ivor_mask = 0x0000FFF0UL;
2717 env->ivpr_mask = 0xFFFF0000UL;
2718 /* Hardware reset vector */
2719 env->hreset_vector = 0xFFFFFFFCUL;
2720#endif
2721}
2722
2723static void init_excp_MPC5xx (CPUPPCState *env)
2724{
2725#if !defined(CONFIG_USER_ONLY)
2726 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2727 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2728 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2729 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2730 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2731 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2732 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2733 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2734 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2735 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2736 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2737 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2738 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2739 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2740 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2741 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2742 env->ivor_mask = 0x0000FFF0UL;
2743 env->ivpr_mask = 0xFFFF0000UL;
2744 /* Hardware reset vector */
2745 env->hreset_vector = 0xFFFFFFFCUL;
2746#endif
2747}
2748
2749static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2750{
2751#if !defined(CONFIG_USER_ONLY)
2752 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2753 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2754 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2755 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2756 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2757 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2758 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2759 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2760 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2761 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2762 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2763 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2764 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2765 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2766 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2767 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2768 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2769 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2770 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2771 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2772 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2773 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2774 env->ivor_mask = 0x0000FFF0UL;
2775 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2776 /* Hardware reset vector */
80d11f44 2777 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2778#endif
2779}
2780
80d11f44 2781static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2782{
2783#if !defined(CONFIG_USER_ONLY)
2784 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2785 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2786 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2787 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2788 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2789 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2790 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2791 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2792 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2793 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2794 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2795 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2796 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2797 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2798 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2799 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2800 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2801 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2802 /* Hardware reset vector */
2803 env->hreset_vector = 0xFFFFFFFCUL;
2804#endif
2805}
2806
2807static void init_excp_e200 (CPUPPCState *env)
2808{
2809#if !defined(CONFIG_USER_ONLY)
2810 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2811 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2829 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
fc1c67bc 2830 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2831 env->ivor_mask = 0x0000FFF7UL;
2832 env->ivpr_mask = 0xFFFF0000UL;
2833 /* Hardware reset vector */
2834 env->hreset_vector = 0xFFFFFFFCUL;
2835#endif
2836}
2837
2838static void init_excp_BookE (CPUPPCState *env)
2839{
2840#if !defined(CONFIG_USER_ONLY)
2841 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
fc1c67bc 2857 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2858 env->ivor_mask = 0x0000FFE0UL;
2859 env->ivpr_mask = 0xFFFF0000UL;
2860 /* Hardware reset vector */
2861 env->hreset_vector = 0xFFFFFFFCUL;
2862#endif
2863}
2864
2865static void init_excp_601 (CPUPPCState *env)
2866{
2867#if !defined(CONFIG_USER_ONLY)
2868 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2869 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2870 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2871 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2872 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2873 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2874 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2875 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2876 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2877 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2878 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2879 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
fc1c67bc 2880 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2881 /* Hardware reset vector */
80d11f44 2882 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2883#endif
2884}
2885
80d11f44 2886static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2887{
2888#if !defined(CONFIG_USER_ONLY)
082c6681 2889 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2890 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2891 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2892 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2893 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2894 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2895 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2896 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2897 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2898 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2899 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2900 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2901 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2902 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2903 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2904 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2905 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2906 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2907 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
fc1c67bc 2908 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2909 /* Hardware reset vector */
2910 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2911#endif
2912}
2913
80d11f44 2914static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2915{
2916#if !defined(CONFIG_USER_ONLY)
2917 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2918 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2919 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2920 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2921 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2922 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2923 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2924 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2925 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2926 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2927 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2928 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2929 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2930 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2931 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2932 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2933 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2934 /* Hardware reset vector */
2935 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2936#endif
2937}
2938
2939static void init_excp_604 (CPUPPCState *env)
2940{
2941#if !defined(CONFIG_USER_ONLY)
2942 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2943 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2944 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2945 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2951 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2952 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2953 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2954 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2955 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2d3eb7bf 2956 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2957 /* Hardware reset vector */
2d3eb7bf 2958 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2959#endif
2960}
2961
578bb252 2962#if defined(TARGET_PPC64)
e1833e1f
JM		 2963static void init_excp_620 (CPUPPCState *env)
2964{
2965#if !defined(CONFIG_USER_ONLY)
2966 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2967 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2968 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2969 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2970 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2971 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2972 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2973 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2974 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2975 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2976 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2977 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2978 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2979 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2980 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2981 /* Hardware reset vector */
faadf50e 2982 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2983#endif
2984}
578bb252 2985#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2986
2987static void init_excp_7x0 (CPUPPCState *env)
2988{
2989#if !defined(CONFIG_USER_ONLY)
2990 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2991 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2992 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2993 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2994 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2995 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2996 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2997 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2998 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2999 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3000 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3001 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3002 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 3003 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 3004 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3005 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3006 /* Hardware reset vector */
3007 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3008#endif
3009}
3010
bd928eba 3011static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 3012{
3013#if !defined(CONFIG_USER_ONLY)
3014 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3015 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3016 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3017 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3018 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3019 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3020 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3021 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3022 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3023 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3024 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3025 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3026 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3027 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 3028 env->hreset_excp_prefix = 0x00000000UL;
bd928eba
JM		 3029 /* Hardware reset vector */
3030 env->hreset_vector = 0xFFFFFFFCUL;
3031#endif
3032}
3033
3034static void init_excp_750cx (CPUPPCState *env)
3035{
3036#if !defined(CONFIG_USER_ONLY)
3037 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3038 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3039 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3040 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3046 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3047 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3048 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3049 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 3050 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3051 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3052 /* Hardware reset vector */
3053 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3054#endif
3055}
3056
7a3a6927
JM		 3057/* XXX: Check if this is correct */
3058static void init_excp_7x5 (CPUPPCState *env)
3059{
3060#if !defined(CONFIG_USER_ONLY)
3061 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3062 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3063 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3064 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3065 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3066 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3067 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3068 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3069 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3070 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3071 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 3072 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 3073 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3074 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3075 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 3076 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3077 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 3078 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3079 env->hreset_excp_prefix = 0x00000000UL;
7a3a6927
JM		 3080 /* Hardware reset vector */
3081 env->hreset_vector = 0xFFFFFFFCUL;
3082#endif
3083}
3084
e1833e1f
JM		 3085static void init_excp_7400 (CPUPPCState *env)
3086{
3087#if !defined(CONFIG_USER_ONLY)
3088 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3089 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3090 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3091 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3092 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3093 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3094 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3095 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3096 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3097 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3098 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3099 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3100 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3102 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3103 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3104 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3105 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3106 /* Hardware reset vector */
3107 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3108#endif
3109}
3110
e1833e1f
JM		 3111static void init_excp_7450 (CPUPPCState *env)
3112{
3113#if !defined(CONFIG_USER_ONLY)
3114 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3115 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3116 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3117 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3118 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3119 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3120 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3121 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3122 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3123 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3124 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3125 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3126 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3127 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3128 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3129 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3130 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3131 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3132 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
fc1c67bc 3133 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3134 /* Hardware reset vector */
3135 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3136#endif
3137}
e1833e1f
JM		 3138
3139#if defined (TARGET_PPC64)
3140static void init_excp_970 (CPUPPCState *env)
3141{
3142#if !defined(CONFIG_USER_ONLY)
3143 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3144 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3145 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3146 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3147 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3148 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3149 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3150 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3151 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3152 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3153 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3154 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3155 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3156 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3157 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3158 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3159 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3160 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3161 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3162 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
fc1c67bc 3163 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3164 /* Hardware reset vector */
3165 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3166#endif
3167}
9d52e907
DG		 3168
3169static void init_excp_POWER7 (CPUPPCState *env)
3170{
3171#if !defined(CONFIG_USER_ONLY)
3172 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3173 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3174 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3175 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3176 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3177 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3178 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3179 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3180 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3181 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3182 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3183 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3184 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3185 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3186 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3187 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3188 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3189 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3190 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3191 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3192 env->hreset_excp_prefix = 0;
3193 /* Hardware reset vector */
3194 env->hreset_vector = 0x0000000000000100ULL;
3195#endif
3196}
e1833e1f
JM		 3197#endif
3198
2f462816
JM		 3199/*****************************************************************************/
3200/* Power management enable checks */
3201static int check_pow_none (CPUPPCState *env)
3202{
3203 return 0;
3204}
3205
3206static int check_pow_nocheck (CPUPPCState *env)
3207{
3208 return 1;
3209}
3210
3211static int check_pow_hid0 (CPUPPCState *env)
3212{
3213 if (env->spr[SPR_HID0] & 0x00E00000)
3214 return 1;
3215
3216 return 0;
3217}
3218
4e777442
JM		 3219static int check_pow_hid0_74xx (CPUPPCState *env)
3220{
3221 if (env->spr[SPR_HID0] & 0x00600000)
3222 return 1;
3223
3224 return 0;
3225}
3226
a750fc0b
JM		 3227/*****************************************************************************/
3228/* PowerPC implementations definitions */
76a66253 3229
a750fc0b 3230/* PowerPC 401 */
082c6681
JM		 3231#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3232 PPC_WRTEE | PPC_DCR | \
3233 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3234 PPC_CACHE_DCBZ | \
a750fc0b 3235 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3236 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3237#define POWERPC_INSNS2_401 (PPC_NONE)
a750fc0b 3238#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3239#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3240#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3241#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3242#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3243#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3244 POWERPC_FLAG_BUS_CLK)
2f462816 3245#define check_pow_401 check_pow_nocheck
76a66253 3246
a750fc0b
JM		 3247static void init_proc_401 (CPUPPCState *env)
3248{
3249 gen_spr_40x(env);
3250 gen_spr_401_403(env);
3251 gen_spr_401(env);
e1833e1f 3252 init_excp_4xx_real(env);
d63001d1
JM		 3253 env->dcache_line_size = 32;
3254 env->icache_line_size = 32;
4e290a0b
JM		 3255 /* Allocate hardware IRQ controller */
3256 ppc40x_irq_init(env);
ddd1055b
FC		 3257
3258 SET_FIT_PERIOD(12, 16, 20, 24);
3259 SET_WDT_PERIOD(16, 20, 24, 28);
a750fc0b 3260}
76a66253 3261
a750fc0b 3262/* PowerPC 401x2 */
082c6681
JM		 3263#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3264 PPC_DCR | PPC_WRTEE | \
3265 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3266 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3267 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3268 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3269 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3270#define POWERPC_INSNS2_401x2 (PPC_NONE)
a750fc0b
JM		 3271#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3272#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3273#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3274#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3275#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3276#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3277 POWERPC_FLAG_BUS_CLK)
2f462816 3278#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3279
3280static void init_proc_401x2 (CPUPPCState *env)
3281{
3282 gen_spr_40x(env);
3283 gen_spr_401_403(env);
3284 gen_spr_401x2(env);
3285 gen_spr_compress(env);
a750fc0b 3286 /* Memory management */
f2e63a42 3287#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3288 env->nb_tlb = 64;
3289 env->nb_ways = 1;
3290 env->id_tlbs = 0;
1c53accc 3291 env->tlb_type = TLB_EMB;
f2e63a42 3292#endif
e1833e1f 3293 init_excp_4xx_softmmu(env);
d63001d1
JM		 3294 env->dcache_line_size = 32;
3295 env->icache_line_size = 32;
4e290a0b
JM		 3296 /* Allocate hardware IRQ controller */
3297 ppc40x_irq_init(env);
ddd1055b
FC		 3298
3299 SET_FIT_PERIOD(12, 16, 20, 24);
3300 SET_WDT_PERIOD(16, 20, 24, 28);
76a66253
JM		 3301}
3302
a750fc0b 3303/* PowerPC 401x3 */
082c6681
JM		 3304#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3305 PPC_DCR | PPC_WRTEE | \
3306 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3307 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3308 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3309 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3310 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3311#define POWERPC_INSNS2_401x3 (PPC_NONE)
a750fc0b
JM		 3312#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3313#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3314#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3315#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3316#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3317#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3318 POWERPC_FLAG_BUS_CLK)
2f462816 3319#define check_pow_401x3 check_pow_nocheck
a750fc0b 3320
578bb252 3321__attribute__ (( unused ))
e1833e1f 3322static void init_proc_401x3 (CPUPPCState *env)
76a66253 3323{
4e290a0b
JM		 3324 gen_spr_40x(env);
3325 gen_spr_401_403(env);
3326 gen_spr_401(env);
3327 gen_spr_401x2(env);
3328 gen_spr_compress(env);
e1833e1f 3329 init_excp_4xx_softmmu(env);
d63001d1
JM		 3330 env->dcache_line_size = 32;
3331 env->icache_line_size = 32;
4e290a0b
JM		 3332 /* Allocate hardware IRQ controller */
3333 ppc40x_irq_init(env);
ddd1055b
FC		 3334
3335 SET_FIT_PERIOD(12, 16, 20, 24);
3336 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082 3337}
a750fc0b
JM		 3338
3339/* IOP480 */
082c6681
JM		 3340#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3341 PPC_DCR | PPC_WRTEE | \
3342 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3343 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3344 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3345 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3346 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3347#define POWERPC_INSNS2_IOP480 (PPC_NONE)
a750fc0b
JM		 3348#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3349#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3350#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3351#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3352#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3353#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3354 POWERPC_FLAG_BUS_CLK)
2f462816 3355#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3356
3357static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3358{
a750fc0b
JM		 3359 gen_spr_40x(env);
3360 gen_spr_401_403(env);
3361 gen_spr_401x2(env);
3362 gen_spr_compress(env);
a750fc0b 3363 /* Memory management */
f2e63a42 3364#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3365 env->nb_tlb = 64;
3366 env->nb_ways = 1;
3367 env->id_tlbs = 0;
1c53accc 3368 env->tlb_type = TLB_EMB;
f2e63a42 3369#endif
e1833e1f 3370 init_excp_4xx_softmmu(env);
d63001d1
JM		 3371 env->dcache_line_size = 32;
3372 env->icache_line_size = 32;
4e290a0b
JM		 3373 /* Allocate hardware IRQ controller */
3374 ppc40x_irq_init(env);
ddd1055b
FC		 3375
3376 SET_FIT_PERIOD(8, 12, 16, 20);
3377 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3378}
3379
a750fc0b 3380/* PowerPC 403 */
082c6681
JM		 3381#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3382 PPC_DCR | PPC_WRTEE | \
3383 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3384 PPC_CACHE_DCBZ | \
a750fc0b 3385 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3386 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3387#define POWERPC_INSNS2_403 (PPC_NONE)
a750fc0b 3388#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3389#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3390#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3391#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3392#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3393#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3394 POWERPC_FLAG_BUS_CLK)
2f462816 3395#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3396
3397static void init_proc_403 (CPUPPCState *env)
3fc6c082 3398{
a750fc0b
JM		 3399 gen_spr_40x(env);
3400 gen_spr_401_403(env);
3401 gen_spr_403(env);
3402 gen_spr_403_real(env);
e1833e1f 3403 init_excp_4xx_real(env);
d63001d1
JM		 3404 env->dcache_line_size = 32;
3405 env->icache_line_size = 32;
4e290a0b
JM		 3406 /* Allocate hardware IRQ controller */
3407 ppc40x_irq_init(env);
ddd1055b
FC		 3408
3409 SET_FIT_PERIOD(8, 12, 16, 20);
3410 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3411}
3412
a750fc0b 3413/* PowerPC 403 GCX */
082c6681
JM		 3414#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3415 PPC_DCR | PPC_WRTEE | \
3416 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3417 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3418 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3419 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3420 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3421#define POWERPC_INSNS2_403GCX (PPC_NONE)
a750fc0b
JM		 3422#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3423#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3424#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3425#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3426#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3427#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3428 POWERPC_FLAG_BUS_CLK)
2f462816 3429#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3430
3431static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3432{
a750fc0b
JM		 3433 gen_spr_40x(env);
3434 gen_spr_401_403(env);
3435 gen_spr_403(env);
3436 gen_spr_403_real(env);
3437 gen_spr_403_mmu(env);
3438 /* Bus access control */
5cbdb3a3 3439 /* not emulated, as QEMU never does speculative access */
a750fc0b
JM		 3440 spr_register(env, SPR_40x_SGR, "SGR",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0xFFFFFFFF);
5cbdb3a3 3444 /* not emulated, as QEMU do not emulate caches */
a750fc0b
JM		 3445 spr_register(env, SPR_40x_DCWR, "DCWR",
3446 SPR_NOACCESS, SPR_NOACCESS,
3447 &spr_read_generic, &spr_write_generic,
3448 0x00000000);
3449 /* Memory management */
f2e63a42 3450#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3451 env->nb_tlb = 64;
3452 env->nb_ways = 1;
3453 env->id_tlbs = 0;
1c53accc 3454 env->tlb_type = TLB_EMB;
f2e63a42 3455#endif
80d11f44
JM		 3456 init_excp_4xx_softmmu(env);
3457 env->dcache_line_size = 32;
3458 env->icache_line_size = 32;
3459 /* Allocate hardware IRQ controller */
3460 ppc40x_irq_init(env);
ddd1055b
FC		 3461
3462 SET_FIT_PERIOD(8, 12, 16, 20);
3463 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3464}
3465
3466/* PowerPC 405 */
082c6681
JM		 3467#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3468 PPC_DCR | PPC_WRTEE | \
3469 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3470 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3471 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3472 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3473 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
a5858d7a 3474#define POWERPC_INSNS2_405 (PPC_NONE)
80d11f44
JM		 3475#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3476#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3477#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3478#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3479#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3480#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3481 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3482#define check_pow_405 check_pow_nocheck
3483
3484static void init_proc_405 (CPUPPCState *env)
3485{
3486 /* Time base */
3487 gen_tbl(env);
3488 gen_spr_40x(env);
3489 gen_spr_405(env);
3490 /* Bus access control */
5cbdb3a3 3491 /* not emulated, as QEMU never does speculative access */
80d11f44
JM		 3492 spr_register(env, SPR_40x_SGR, "SGR",
3493 SPR_NOACCESS, SPR_NOACCESS,
3494 &spr_read_generic, &spr_write_generic,
3495 0xFFFFFFFF);
5cbdb3a3 3496 /* not emulated, as QEMU do not emulate caches */
80d11f44
JM		 3497 spr_register(env, SPR_40x_DCWR, "DCWR",
3498 SPR_NOACCESS, SPR_NOACCESS,
3499 &spr_read_generic, &spr_write_generic,
3500 0x00000000);
3501 /* Memory management */
3502#if !defined(CONFIG_USER_ONLY)
3503 env->nb_tlb = 64;
3504 env->nb_ways = 1;
3505 env->id_tlbs = 0;
1c53accc 3506 env->tlb_type = TLB_EMB;
80d11f44
JM		 3507#endif
3508 init_excp_4xx_softmmu(env);
3509 env->dcache_line_size = 32;
3510 env->icache_line_size = 32;
3511 /* Allocate hardware IRQ controller */
3512 ppc40x_irq_init(env);
ddd1055b
FC		 3513
3514 SET_FIT_PERIOD(8, 12, 16, 20);
3515 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3516}
3517
3518/* PowerPC 440 EP */
082c6681 3519#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
c0a7e81a
AG		 3520 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3521 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3522 PPC_FLOAT_STFIWX | \
082c6681
JM		 3523 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3524 PPC_CACHE | PPC_CACHE_ICBI | \
3525 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3526 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3527 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3528 PPC_440_SPEC)
a5858d7a 3529#define POWERPC_INSNS2_440EP (PPC_NONE)
c0a7e81a 3530#define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
80d11f44
JM		 3531#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3532#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3533#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3534#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3535#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3536 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3537#define check_pow_440EP check_pow_nocheck
3538
80d11f44
JM		 3539static void init_proc_440EP (CPUPPCState *env)
3540{
3541 /* Time base */
3542 gen_tbl(env);
3543 gen_spr_BookE(env, 0x000000000000FFFFULL);
3544 gen_spr_440(env);
3545 gen_spr_usprgh(env);
3546 /* Processor identification */
3547 spr_register(env, SPR_BOOKE_PIR, "PIR",
3548 SPR_NOACCESS, SPR_NOACCESS,
3549 &spr_read_generic, &spr_write_pir,
3550 0x00000000);
3551 /* XXX : not implemented */
3552 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3553 SPR_NOACCESS, SPR_NOACCESS,
3554 &spr_read_generic, &spr_write_generic,
3555 0x00000000);
3556 /* XXX : not implemented */
3557 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3558 SPR_NOACCESS, SPR_NOACCESS,
3559 &spr_read_generic, &spr_write_generic,
3560 0x00000000);
3561 /* XXX : not implemented */
3562 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
3566 /* XXX : not implemented */
3567 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
3571 /* XXX : not implemented */
3572 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3573 SPR_NOACCESS, SPR_NOACCESS,
3574 &spr_read_generic, &spr_write_generic,
3575 0x00000000);
3576 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3581 SPR_NOACCESS, SPR_NOACCESS,
3582 &spr_read_generic, &spr_write_generic,
3583 0x00000000);
3584 /* XXX : not implemented */
3585 spr_register(env, SPR_440_CCR1, "CCR1",
3586 SPR_NOACCESS, SPR_NOACCESS,
3587 &spr_read_generic, &spr_write_generic,
3588 0x00000000);
3589 /* Memory management */
3590#if !defined(CONFIG_USER_ONLY)
3591 env->nb_tlb = 64;
3592 env->nb_ways = 1;
3593 env->id_tlbs = 0;
1c53accc 3594 env->tlb_type = TLB_EMB;
80d11f44
JM		 3595#endif
3596 init_excp_BookE(env);
3597 env->dcache_line_size = 32;
3598 env->icache_line_size = 32;
c0a7e81a 3599 ppc40x_irq_init(env);
ddd1055b
FC		 3600
3601 SET_FIT_PERIOD(12, 16, 20, 24);
3602 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3603}
3604
3605/* PowerPC 440 GP */
082c6681
JM		 3606#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3607 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3608 PPC_CACHE | PPC_CACHE_ICBI | \
3609 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3610 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
082c6681
JM		 3611 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3612 PPC_440_SPEC)
a5858d7a 3613#define POWERPC_INSNS2_440GP (PPC_NONE)
80d11f44
JM		 3614#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3615#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3616#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3617#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3618#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3619#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3620 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3621#define check_pow_440GP check_pow_nocheck
3622
3623__attribute__ (( unused ))
3624static void init_proc_440GP (CPUPPCState *env)
3625{
3626 /* Time base */
3627 gen_tbl(env);
3628 gen_spr_BookE(env, 0x000000000000FFFFULL);
3629 gen_spr_440(env);
3630 gen_spr_usprgh(env);
3631 /* Processor identification */
3632 spr_register(env, SPR_BOOKE_PIR, "PIR",
3633 SPR_NOACCESS, SPR_NOACCESS,
3634 &spr_read_generic, &spr_write_pir,
3635 0x00000000);
3636 /* XXX : not implemented */
3637 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3638 SPR_NOACCESS, SPR_NOACCESS,
3639 &spr_read_generic, &spr_write_generic,
3640 0x00000000);
3641 /* XXX : not implemented */
3642 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_generic,
3645 0x00000000);
3646 /* XXX : not implemented */
3647 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* Memory management */
3657#if !defined(CONFIG_USER_ONLY)
3658 env->nb_tlb = 64;
3659 env->nb_ways = 1;
3660 env->id_tlbs = 0;
1c53accc 3661 env->tlb_type = TLB_EMB;
80d11f44
JM		 3662#endif
3663 init_excp_BookE(env);
3664 env->dcache_line_size = 32;
3665 env->icache_line_size = 32;
3666 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3667
3668 SET_FIT_PERIOD(12, 16, 20, 24);
3669 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3670}
3671
3672/* PowerPC 440x4 */
082c6681
JM		 3673#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3674 PPC_DCR | PPC_WRTEE | \
3675 PPC_CACHE | PPC_CACHE_ICBI | \
3676 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3677 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44
JM		 3678 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3679 PPC_440_SPEC)
a5858d7a 3680#define POWERPC_INSNS2_440x4 (PPC_NONE)
80d11f44
JM		 3681#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3682#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3683#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3684#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3685#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3686#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3687 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3688#define check_pow_440x4 check_pow_nocheck
3689
3690__attribute__ (( unused ))
3691static void init_proc_440x4 (CPUPPCState *env)
3692{
3693 /* Time base */
3694 gen_tbl(env);
3695 gen_spr_BookE(env, 0x000000000000FFFFULL);
3696 gen_spr_440(env);
3697 gen_spr_usprgh(env);
3698 /* Processor identification */
3699 spr_register(env, SPR_BOOKE_PIR, "PIR",
3700 SPR_NOACCESS, SPR_NOACCESS,
3701 &spr_read_generic, &spr_write_pir,
3702 0x00000000);
3703 /* XXX : not implemented */
3704 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3705 SPR_NOACCESS, SPR_NOACCESS,
3706 &spr_read_generic, &spr_write_generic,
3707 0x00000000);
3708 /* XXX : not implemented */
3709 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3710 SPR_NOACCESS, SPR_NOACCESS,
3711 &spr_read_generic, &spr_write_generic,
3712 0x00000000);
3713 /* XXX : not implemented */
3714 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3715 SPR_NOACCESS, SPR_NOACCESS,
3716 &spr_read_generic, &spr_write_generic,
3717 0x00000000);
3718 /* XXX : not implemented */
3719 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723 /* Memory management */
3724#if !defined(CONFIG_USER_ONLY)
3725 env->nb_tlb = 64;
3726 env->nb_ways = 1;
3727 env->id_tlbs = 0;
1c53accc 3728 env->tlb_type = TLB_EMB;
80d11f44
JM		 3729#endif
3730 init_excp_BookE(env);
d63001d1
JM		 3731 env->dcache_line_size = 32;
3732 env->icache_line_size = 32;
80d11f44 3733 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3734
3735 SET_FIT_PERIOD(12, 16, 20, 24);
3736 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3737}
3738
80d11f44 3739/* PowerPC 440x5 */
082c6681
JM		 3740#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3741 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3742 PPC_CACHE | PPC_CACHE_ICBI | \
3743 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3744 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3745 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3746 PPC_440_SPEC)
a5858d7a 3747#define POWERPC_INSNS2_440x5 (PPC_NONE)
80d11f44
JM		 3748#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3749#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3750#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3751#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3752#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3753#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3754 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3755#define check_pow_440x5 check_pow_nocheck
a750fc0b 3756
80d11f44 3757static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3758{
a750fc0b
JM		 3759 /* Time base */
3760 gen_tbl(env);
80d11f44
JM		 3761 gen_spr_BookE(env, 0x000000000000FFFFULL);
3762 gen_spr_440(env);
3763 gen_spr_usprgh(env);
3764 /* Processor identification */
3765 spr_register(env, SPR_BOOKE_PIR, "PIR",
3766 SPR_NOACCESS, SPR_NOACCESS,
3767 &spr_read_generic, &spr_write_pir,
3768 0x00000000);
3769 /* XXX : not implemented */
3770 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3771 SPR_NOACCESS, SPR_NOACCESS,
3772 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3773 0x00000000);
3774 /* XXX : not implemented */
3775 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3776 SPR_NOACCESS, SPR_NOACCESS,
3777 &spr_read_generic, &spr_write_generic,
3778 0x00000000);
3779 /* XXX : not implemented */
3780 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3781 SPR_NOACCESS, SPR_NOACCESS,
3782 &spr_read_generic, &spr_write_generic,
3783 0x00000000);
3784 /* XXX : not implemented */
3785 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3786 SPR_NOACCESS, SPR_NOACCESS,
3787 &spr_read_generic, &spr_write_generic,
3788 0x00000000);
3789 /* XXX : not implemented */
3790 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3791 SPR_NOACCESS, SPR_NOACCESS,
3792 &spr_read_generic, &spr_write_generic,
3793 0x00000000);
3794 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3795 SPR_NOACCESS, SPR_NOACCESS,
3796 &spr_read_generic, &spr_write_generic,
3797 0x00000000);
3798 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3799 SPR_NOACCESS, SPR_NOACCESS,
3800 &spr_read_generic, &spr_write_generic,
3801 0x00000000);
3802 /* XXX : not implemented */
3803 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3804 SPR_NOACCESS, SPR_NOACCESS,
3805 &spr_read_generic, &spr_write_generic,
3806 0x00000000);
3807 /* Memory management */
f2e63a42 3808#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3809 env->nb_tlb = 64;
3810 env->nb_ways = 1;
3811 env->id_tlbs = 0;
1c53accc 3812 env->tlb_type = TLB_EMB;
f2e63a42 3813#endif
80d11f44 3814 init_excp_BookE(env);
d63001d1
JM		 3815 env->dcache_line_size = 32;
3816 env->icache_line_size = 32;
95070372 3817 ppc40x_irq_init(env);
ddd1055b
FC		 3818
3819 SET_FIT_PERIOD(12, 16, 20, 24);
3820 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3821}
3822
80d11f44 3823/* PowerPC 460 (guessed) */
082c6681 3824#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3825 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
f4078236 3826 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
082c6681
JM		 3827 PPC_CACHE | PPC_CACHE_ICBI | \
3828 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3829 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3830 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3831 PPC_440_SPEC)
a5858d7a 3832#define POWERPC_INSNS2_460 (PPC_NONE)
80d11f44
JM		 3833#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3834#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3835#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3836#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3837#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3838#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3839 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3840#define check_pow_460 check_pow_nocheck
a750fc0b 3841
80d11f44
JM		 3842__attribute__ (( unused ))
3843static void init_proc_460 (CPUPPCState *env)
3fc6c082 3844{
a750fc0b
JM		 3845 /* Time base */
3846 gen_tbl(env);
80d11f44 3847 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3848 gen_spr_440(env);
80d11f44
JM		 3849 gen_spr_usprgh(env);
3850 /* Processor identification */
3851 spr_register(env, SPR_BOOKE_PIR, "PIR",
3852 SPR_NOACCESS, SPR_NOACCESS,
3853 &spr_read_generic, &spr_write_pir,
3854 0x00000000);
3855 /* XXX : not implemented */
3856 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3857 SPR_NOACCESS, SPR_NOACCESS,
3858 &spr_read_generic, &spr_write_generic,
3859 0x00000000);
3860 /* XXX : not implemented */
3861 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3862 SPR_NOACCESS, SPR_NOACCESS,
3863 &spr_read_generic, &spr_write_generic,
3864 0x00000000);
3865 /* XXX : not implemented */
3866 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3867 SPR_NOACCESS, SPR_NOACCESS,
3868 &spr_read_generic, &spr_write_generic,
3869 0x00000000);
3870 /* XXX : not implemented */
3871 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3872 SPR_NOACCESS, SPR_NOACCESS,
3873 &spr_read_generic, &spr_write_generic,
3874 0x00000000);
578bb252 3875 /* XXX : not implemented */
a750fc0b
JM		 3876 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_generic,
3879 0x00000000);
3880 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3885 SPR_NOACCESS, SPR_NOACCESS,
3886 &spr_read_generic, &spr_write_generic,
3887 0x00000000);
578bb252 3888 /* XXX : not implemented */
a750fc0b
JM		 3889 spr_register(env, SPR_440_CCR1, "CCR1",
3890 SPR_NOACCESS, SPR_NOACCESS,
3891 &spr_read_generic, &spr_write_generic,
3892 0x00000000);
80d11f44
JM		 3893 /* XXX : not implemented */
3894 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3895 &spr_read_generic, &spr_write_generic,
3896 &spr_read_generic, &spr_write_generic,
3897 0x00000000);
a750fc0b 3898 /* Memory management */
f2e63a42 3899#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3900 env->nb_tlb = 64;
3901 env->nb_ways = 1;
3902 env->id_tlbs = 0;
1c53accc 3903 env->tlb_type = TLB_EMB;
f2e63a42 3904#endif
e1833e1f 3905 init_excp_BookE(env);
d63001d1
JM		 3906 env->dcache_line_size = 32;
3907 env->icache_line_size = 32;
a750fc0b 3908 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3909
3910 SET_FIT_PERIOD(12, 16, 20, 24);
3911 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3912}
3913
80d11f44 3914/* PowerPC 460F (guessed) */
082c6681
JM		 3915#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3916 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3917 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
f4078236 3918 PPC_FLOAT_STFIWX | PPC_MFTB | \
082c6681
JM		 3919 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3920 PPC_WRTEE | PPC_MFAPIDI | \
3921 PPC_CACHE | PPC_CACHE_ICBI | \
3922 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3923 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3924 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3925 PPC_440_SPEC)
a5858d7a 3926#define POWERPC_INSNS2_460F (PPC_NONE)
80d11f44
JM		 3927#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3928#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3929#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3930#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3931#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3932#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3933 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3934#define check_pow_460F check_pow_nocheck
a750fc0b 3935
80d11f44
JM		 3936__attribute__ (( unused ))
3937static void init_proc_460F (CPUPPCState *env)
3fc6c082 3938{
a750fc0b
JM		 3939 /* Time base */
3940 gen_tbl(env);
80d11f44 3941 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3942 gen_spr_440(env);
80d11f44
JM		 3943 gen_spr_usprgh(env);
3944 /* Processor identification */
3945 spr_register(env, SPR_BOOKE_PIR, "PIR",
3946 SPR_NOACCESS, SPR_NOACCESS,
3947 &spr_read_generic, &spr_write_pir,
3948 0x00000000);
3949 /* XXX : not implemented */
3950 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3951 SPR_NOACCESS, SPR_NOACCESS,
3952 &spr_read_generic, &spr_write_generic,
3953 0x00000000);
3954 /* XXX : not implemented */
3955 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3956 SPR_NOACCESS, SPR_NOACCESS,
3957 &spr_read_generic, &spr_write_generic,
3958 0x00000000);
3959 /* XXX : not implemented */
3960 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3961 SPR_NOACCESS, SPR_NOACCESS,
3962 &spr_read_generic, &spr_write_generic,
3963 0x00000000);
3964 /* XXX : not implemented */
3965 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3966 SPR_NOACCESS, SPR_NOACCESS,
3967 &spr_read_generic, &spr_write_generic,
3968 0x00000000);
3969 /* XXX : not implemented */
3970 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_generic,
3973 0x00000000);
3974 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_generic,
3977 0x00000000);
3978 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3979 SPR_NOACCESS, SPR_NOACCESS,
3980 &spr_read_generic, &spr_write_generic,
3981 0x00000000);
3982 /* XXX : not implemented */
3983 spr_register(env, SPR_440_CCR1, "CCR1",
3984 SPR_NOACCESS, SPR_NOACCESS,
3985 &spr_read_generic, &spr_write_generic,
3986 0x00000000);
3987 /* XXX : not implemented */
3988 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3989 &spr_read_generic, &spr_write_generic,
3990 &spr_read_generic, &spr_write_generic,
3991 0x00000000);
a750fc0b 3992 /* Memory management */
f2e63a42 3993#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3994 env->nb_tlb = 64;
3995 env->nb_ways = 1;
3996 env->id_tlbs = 0;
1c53accc 3997 env->tlb_type = TLB_EMB;
f2e63a42 3998#endif
e1833e1f 3999 init_excp_BookE(env);
d63001d1
JM		 4000 env->dcache_line_size = 32;
4001 env->icache_line_size = 32;
a750fc0b 4002 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 4003
4004 SET_FIT_PERIOD(12, 16, 20, 24);
4005 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 4006}
4007
80d11f44
JM		 4008/* Freescale 5xx cores (aka RCPU) */
4009#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4010 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4011 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4012 PPC_MFTB)
a5858d7a 4013#define POWERPC_INSNS2_MPC5xx (PPC_NONE)
80d11f44
JM		 4014#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4015#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4016#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4017#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4018#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 4019#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4020 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4021#define check_pow_MPC5xx check_pow_none
4022
4023__attribute__ (( unused ))
4024static void init_proc_MPC5xx (CPUPPCState *env)
4025{
4026 /* Time base */
4027 gen_tbl(env);
4028 gen_spr_5xx_8xx(env);
4029 gen_spr_5xx(env);
4030 init_excp_MPC5xx(env);
4031 env->dcache_line_size = 32;
4032 env->icache_line_size = 32;
4033 /* XXX: TODO: allocate internal IRQ controller */
4034}
4035
4036/* Freescale 8xx cores (aka PowerQUICC) */
4037#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4038 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4039 PPC_CACHE_ICBI | PPC_MFTB)
a5858d7a 4040#define POWERPC_INSNS2_MPC8xx (PPC_NONE)
80d11f44
JM		 4041#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4042#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4043#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4044#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4045#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 4046#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4047 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4048#define check_pow_MPC8xx check_pow_none
4049
4050__attribute__ (( unused ))
4051static void init_proc_MPC8xx (CPUPPCState *env)
4052{
4053 /* Time base */
4054 gen_tbl(env);
4055 gen_spr_5xx_8xx(env);
4056 gen_spr_8xx(env);
4057 init_excp_MPC8xx(env);
4058 env->dcache_line_size = 32;
4059 env->icache_line_size = 32;
4060 /* XXX: TODO: allocate internal IRQ controller */
4061}
4062
4063/* Freescale 82xx cores (aka PowerQUICC-II) */
4064/* PowerPC G2 */
082c6681
JM		 4065#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4066 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4067 PPC_FLOAT_STFIWX | \
4068 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4069 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4070 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4071 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4072#define POWERPC_INSNS2_G2 (PPC_NONE)
80d11f44
JM		 4073#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4074#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4075//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4076#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4077#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4078#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4079 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4080#define check_pow_G2 check_pow_hid0
a750fc0b 4081
80d11f44 4082static void init_proc_G2 (CPUPPCState *env)
3fc6c082 4083{
80d11f44
JM		 4084 gen_spr_ne_601(env);
4085 gen_spr_G2_755(env);
4086 gen_spr_G2(env);
a750fc0b
JM		 4087 /* Time base */
4088 gen_tbl(env);
bd928eba
JM		 4089 /* External access control */
4090 /* XXX : not implemented */
4091 spr_register(env, SPR_EAR, "EAR",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
80d11f44
JM		 4095 /* Hardware implementation register */
4096 /* XXX : not implemented */
4097 spr_register(env, SPR_HID0, "HID0",
4098 SPR_NOACCESS, SPR_NOACCESS,
4099 &spr_read_generic, &spr_write_generic,
4100 0x00000000);
4101 /* XXX : not implemented */
4102 spr_register(env, SPR_HID1, "HID1",
4103 SPR_NOACCESS, SPR_NOACCESS,
4104 &spr_read_generic, &spr_write_generic,
4105 0x00000000);
4106 /* XXX : not implemented */
4107 spr_register(env, SPR_HID2, "HID2",
4108 SPR_NOACCESS, SPR_NOACCESS,
4109 &spr_read_generic, &spr_write_generic,
4110 0x00000000);
a750fc0b 4111 /* Memory management */
80d11f44
JM		 4112 gen_low_BATs(env);
4113 gen_high_BATs(env);
4114 gen_6xx_7xx_soft_tlb(env, 64, 2);
4115 init_excp_G2(env);
d63001d1
JM		 4116 env->dcache_line_size = 32;
4117 env->icache_line_size = 32;
80d11f44
JM		 4118 /* Allocate hardware IRQ controller */
4119 ppc6xx_irq_init(env);
3fc6c082 4120}
a750fc0b 4121
80d11f44 4122/* PowerPC G2LE */
082c6681
JM		 4123#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4124 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4125 PPC_FLOAT_STFIWX | \
4126 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4127 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4128 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4129 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4130#define POWERPC_INSNS2_G2LE (PPC_NONE)
80d11f44
JM		 4131#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4132#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4133#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4134#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4135#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4136#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4137 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4138#define check_pow_G2LE check_pow_hid0
a750fc0b 4139
80d11f44 4140static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 4141{
80d11f44
JM		 4142 gen_spr_ne_601(env);
4143 gen_spr_G2_755(env);
4144 gen_spr_G2(env);
a750fc0b
JM		 4145 /* Time base */
4146 gen_tbl(env);
bd928eba
JM		 4147 /* External access control */
4148 /* XXX : not implemented */
4149 spr_register(env, SPR_EAR, "EAR",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
4152 0x00000000);
80d11f44 4153 /* Hardware implementation register */
578bb252 4154 /* XXX : not implemented */
80d11f44 4155 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 4156 SPR_NOACCESS, SPR_NOACCESS,
4157 &spr_read_generic, &spr_write_generic,
4158 0x00000000);
80d11f44
JM		 4159 /* XXX : not implemented */
4160 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 4161 SPR_NOACCESS, SPR_NOACCESS,
4162 &spr_read_generic, &spr_write_generic,
4163 0x00000000);
578bb252 4164 /* XXX : not implemented */
80d11f44 4165 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 4166 SPR_NOACCESS, SPR_NOACCESS,
4167 &spr_read_generic, &spr_write_generic,
4168 0x00000000);
4169 /* Memory management */
80d11f44
JM		 4170 gen_low_BATs(env);
4171 gen_high_BATs(env);
4172 gen_6xx_7xx_soft_tlb(env, 64, 2);
4173 init_excp_G2(env);
d63001d1
JM		 4174 env->dcache_line_size = 32;
4175 env->icache_line_size = 32;
80d11f44
JM		 4176 /* Allocate hardware IRQ controller */
4177 ppc6xx_irq_init(env);
3fc6c082
FB		 4178}
4179
80d11f44
JM		 4180/* e200 core */
4181/* XXX: unimplemented instructions:
4182 * dcblc
4183 * dcbtlst
4184 * dcbtstls
4185 * icblc
4186 * icbtls
4187 * tlbivax
4188 * all SPE multiply-accumulate instructions
4189 */
082c6681 4190#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
40569b7e 4191 PPC_SPE | PPC_SPE_SINGLE | \
082c6681
JM		 4192 PPC_WRTEE | PPC_RFDI | \
4193 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4194 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 4195 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 4196 PPC_BOOKE)
a5858d7a 4197#define POWERPC_INSNS2_e200 (PPC_NONE)
80d11f44 4198#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
01662f3e 4199#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
80d11f44
JM		 4200#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4201#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4202#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4203#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4204 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4205 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4206#define check_pow_e200 check_pow_hid0
4207
578bb252 4208__attribute__ (( unused ))
80d11f44 4209static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4210{
e1833e1f
JM		 4211 /* Time base */
4212 gen_tbl(env);
80d11f44 4213 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4214 /* XXX : not implemented */
80d11f44 4215 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4216 &spr_read_spefscr, &spr_write_spefscr,
4217 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4218 0x00000000);
80d11f44 4219 /* Memory management */
01662f3e 4220 gen_spr_BookE206(env, 0x0000005D, NULL);
80d11f44
JM		 4221 /* XXX : not implemented */
4222 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4223 SPR_NOACCESS, SPR_NOACCESS,
4224 &spr_read_generic, &spr_write_generic,
4225 0x00000000);
80d11f44
JM		 4226 /* XXX : not implemented */
4227 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4228 SPR_NOACCESS, SPR_NOACCESS,
4229 &spr_read_generic, &spr_write_generic,
4230 0x00000000);
578bb252 4231 /* XXX : not implemented */
80d11f44 4232 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4233 SPR_NOACCESS, SPR_NOACCESS,
4234 &spr_read_generic, &spr_write_generic,
4235 0x00000000);
578bb252 4236 /* XXX : not implemented */
80d11f44
JM		 4237 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4238 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4239 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4240 0x00000000);
4241 /* XXX : not implemented */
4242 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4243 SPR_NOACCESS, SPR_NOACCESS,
4244 &spr_read_generic, &spr_write_generic,
4245 0x00000000);
4246 /* XXX : not implemented */
4247 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4248 SPR_NOACCESS, SPR_NOACCESS,
4249 &spr_read_generic, &spr_write_generic,
4250 0x00000000);
4251 /* XXX : not implemented */
4252 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4253 SPR_NOACCESS, SPR_NOACCESS,
4254 &spr_read_generic, &spr_write_generic,
4255 0x00000000);
4256 /* XXX : not implemented */
4257 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4258 SPR_NOACCESS, SPR_NOACCESS,
4259 &spr_read_generic, &spr_write_generic,
4260 0x00000000);
4261 /* XXX : not implemented */
4262 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4263 SPR_NOACCESS, SPR_NOACCESS,
4264 &spr_read_generic, &spr_write_generic,
4265 0x00000000);
4266 /* XXX : not implemented */
4267 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4268 SPR_NOACCESS, SPR_NOACCESS,
4269 &spr_read_generic, &spr_write_generic,
4270 0x00000000);
4271 /* XXX : not implemented */
4272 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4273 SPR_NOACCESS, SPR_NOACCESS,
4274 &spr_read_generic, &spr_write_generic,
4275 0x00000000);
4276 /* XXX : not implemented */
4277 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4278 SPR_NOACCESS, SPR_NOACCESS,
4279 &spr_read_generic, &spr_write_generic,
4280 0x00000000);
4281 /* XXX : not implemented */
4282 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4283 SPR_NOACCESS, SPR_NOACCESS,
4284 &spr_read_generic, &spr_write_generic,
4285 0x00000000);
4286 /* XXX : not implemented */
4287 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
01662f3e
AG		 4291 /* XXX : not implemented */
4292 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4293 SPR_NOACCESS, SPR_NOACCESS,
4294 &spr_read_generic, &spr_write_generic,
4295 0x00000000); /* TOFIX */
80d11f44
JM		 4296 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4297 SPR_NOACCESS, SPR_NOACCESS,
4298 &spr_read_generic, &spr_write_generic,
4299 0x00000000);
4300 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4301 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4302 &spr_read_generic, &spr_write_generic,
4303 0x00000000);
f2e63a42 4304#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4305 env->nb_tlb = 64;
4306 env->nb_ways = 1;
4307 env->id_tlbs = 0;
1c53accc 4308 env->tlb_type = TLB_EMB;
f2e63a42 4309#endif
80d11f44 4310 init_excp_e200(env);
d63001d1
JM		 4311 env->dcache_line_size = 32;
4312 env->icache_line_size = 32;
e1833e1f 4313 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4314}
a750fc0b 4315
80d11f44 4316/* e300 core */
082c6681
JM		 4317#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4318 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4319 PPC_FLOAT_STFIWX | \
4320 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4321 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4322 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4323 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4324#define POWERPC_INSNS2_e300 (PPC_NONE)
80d11f44
JM		 4325#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4326#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4327#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4328#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4329#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4330#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4331 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4332#define check_pow_e300 check_pow_hid0
a750fc0b 4333
578bb252 4334__attribute__ (( unused ))
80d11f44 4335static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4336{
80d11f44
JM		 4337 gen_spr_ne_601(env);
4338 gen_spr_603(env);
a750fc0b
JM		 4339 /* Time base */
4340 gen_tbl(env);
80d11f44
JM		 4341 /* hardware implementation registers */
4342 /* XXX : not implemented */
4343 spr_register(env, SPR_HID0, "HID0",
4344 SPR_NOACCESS, SPR_NOACCESS,
4345 &spr_read_generic, &spr_write_generic,
4346 0x00000000);
4347 /* XXX : not implemented */
4348 spr_register(env, SPR_HID1, "HID1",
4349 SPR_NOACCESS, SPR_NOACCESS,
4350 &spr_read_generic, &spr_write_generic,
4351 0x00000000);
8daf1781
TM		 4352 /* XXX : not implemented */
4353 spr_register(env, SPR_HID2, "HID2",
4354 SPR_NOACCESS, SPR_NOACCESS,
4355 &spr_read_generic, &spr_write_generic,
4356 0x00000000);
80d11f44
JM		 4357 /* Memory management */
4358 gen_low_BATs(env);
8daf1781 4359 gen_high_BATs(env);
80d11f44
JM		 4360 gen_6xx_7xx_soft_tlb(env, 64, 2);
4361 init_excp_603(env);
4362 env->dcache_line_size = 32;
4363 env->icache_line_size = 32;
4364 /* Allocate hardware IRQ controller */
4365 ppc6xx_irq_init(env);
4366}
4367
bd5ea513
AJ		 4368/* e500v1 core */
4369#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4370 PPC_SPE | PPC_SPE_SINGLE | \
4371 PPC_WRTEE | PPC_RFDI | \
4372 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4373 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
53319166 4374 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
01662f3e 4375#define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
bd5ea513 4376#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
01662f3e 4377#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4378#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4379#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4380#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4381#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4382 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4383 POWERPC_FLAG_BUS_CLK)
4384#define check_pow_e500v1 check_pow_hid0
01662f3e 4385#define init_proc_e500v1 init_proc_e500v1
bd5ea513
AJ		 4386
4387/* e500v2 core */
4388#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4389 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4390 PPC_WRTEE | PPC_RFDI | \
4391 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4392 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
53319166 4393 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
01662f3e 4394#define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
bd5ea513 4395#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
01662f3e 4396#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4397#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4398#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4399#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4400#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4401 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4402 POWERPC_FLAG_BUS_CLK)
4403#define check_pow_e500v2 check_pow_hid0
01662f3e 4404#define init_proc_e500v2 init_proc_e500v2
80d11f44 4405
f7aa5583
VS		 4406/* e500mc core */
4407#define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
4408 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4409 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4410 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4411 PPC_FLOAT | PPC_FLOAT_FRES | \
4412 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4413 PPC_FLOAT_STFIWX | PPC_WAIT | \
53319166 4414 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
8917f4dc 4415#define POWERPC_INSNS2_e500mc (PPC2_BOOKE206 | PPC2_PRCNTL)
f7aa5583
VS		 4416#define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4417#define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4418#define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4419#define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4420/* Fixme: figure out the correct flag for e500mc */
4421#define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4422#define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4423 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4424#define check_pow_e500mc check_pow_none
4425#define init_proc_e500mc init_proc_e500mc
4426
4427enum fsl_e500_version {
4428 fsl_e500v1,
4429 fsl_e500v2,
4430 fsl_e500mc,
4431};
4432
01662f3e 4433static void init_proc_e500 (CPUPPCState *env, int version)
80d11f44 4434{
01662f3e 4435 uint32_t tlbncfg[2];
2c9732db 4436 uint64_t ivor_mask = 0x0000000F0000FFFFULL;
a496e8ee
AG		 4437 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4438 | 0x0020; /* 32 kb */
01662f3e
AG		 4439#if !defined(CONFIG_USER_ONLY)
4440 int i;
4441#endif
4442
80d11f44
JM		 4443 /* Time base */
4444 gen_tbl(env);
01662f3e
AG		 4445 /*
4446 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4447 * complain when accessing them.
4448 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4449 */
2c9732db
AG		 4450 if (version == fsl_e500mc) {
4451 ivor_mask = 0x000003FE0000FFFFULL;
4452 }
4453 gen_spr_BookE(env, ivor_mask);
80d11f44
JM		 4454 /* Processor identification */
4455 spr_register(env, SPR_BOOKE_PIR, "PIR",
4456 SPR_NOACCESS, SPR_NOACCESS,
4457 &spr_read_generic, &spr_write_pir,
4458 0x00000000);
4459 /* XXX : not implemented */
4460 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4461 &spr_read_spefscr, &spr_write_spefscr,
4462 &spr_read_spefscr, &spr_write_spefscr,
80d11f44
JM		 4463 0x00000000);
4464 /* Memory management */
a5cabbda
MI		 4465#if defined(CONFIG_USER_ONLY)
4466 env->dcache_line_size = 32;
4467 env->icache_line_size = 32;
4468#else /* !defined(CONFIG_USER_ONLY) */
80d11f44 4469 env->nb_pids = 3;
01662f3e
AG		 4470 env->nb_ways = 2;
4471 env->id_tlbs = 0;
4472 switch (version) {
f7aa5583 4473 case fsl_e500v1:
01662f3e
AG		 4474 /* e500v1 */
4475 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4476 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
f7aa5583
VS		 4477 env->dcache_line_size = 32;
4478 env->icache_line_size = 32;
01662f3e 4479 break;
f7aa5583 4480 case fsl_e500v2:
01662f3e
AG		 4481 /* e500v2 */
4482 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4483 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
f7aa5583
VS		 4484 env->dcache_line_size = 32;
4485 env->icache_line_size = 32;
4486 break;
4487 case fsl_e500mc:
4488 /* e500mc */
4489 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4490 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4491 env->dcache_line_size = 64;
4492 env->icache_line_size = 64;
a496e8ee 4493 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
01662f3e
AG		 4494 break;
4495 default:
4496 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4497 }
80d11f44 4498#endif
01662f3e 4499 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
80d11f44
JM		 4500 /* XXX : not implemented */
4501 spr_register(env, SPR_HID0, "HID0",
4502 SPR_NOACCESS, SPR_NOACCESS,
4503 &spr_read_generic, &spr_write_generic,
4504 0x00000000);
4505 /* XXX : not implemented */
4506 spr_register(env, SPR_HID1, "HID1",
4507 SPR_NOACCESS, SPR_NOACCESS,
4508 &spr_read_generic, &spr_write_generic,
4509 0x00000000);
4510 /* XXX : not implemented */
4511 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4512 SPR_NOACCESS, SPR_NOACCESS,
4513 &spr_read_generic, &spr_write_generic,
4514 0x00000000);
4515 /* XXX : not implemented */
4516 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4517 SPR_NOACCESS, SPR_NOACCESS,
4518 &spr_read_generic, &spr_write_generic,
4519 0x00000000);
4520 /* XXX : not implemented */
4521 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4522 SPR_NOACCESS, SPR_NOACCESS,
4523 &spr_read_generic, &spr_write_generic,
4524 0x00000000);
578bb252 4525 /* XXX : not implemented */
a750fc0b
JM		 4526 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4527 SPR_NOACCESS, SPR_NOACCESS,
4528 &spr_read_generic, &spr_write_generic,
4529 0x00000000);
80d11f44
JM		 4530 /* XXX : not implemented */
4531 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4532 SPR_NOACCESS, SPR_NOACCESS,
4533 &spr_read_generic, &spr_write_generic,
4534 0x00000000);
80d11f44
JM		 4535 /* XXX : not implemented */
4536 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4537 SPR_NOACCESS, SPR_NOACCESS,
4538 &spr_read_generic, &spr_write_generic,
4539 0x00000000);
578bb252 4540 /* XXX : not implemented */
80d11f44 4541 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4542 SPR_NOACCESS, SPR_NOACCESS,
4543 &spr_read_generic, &spr_write_generic,
a496e8ee 4544 l1cfg0);
578bb252 4545 /* XXX : not implemented */
80d11f44
JM		 4546 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4547 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 4548 &spr_read_generic, &spr_write_e500_l1csr0,
80d11f44
JM		 4549 0x00000000);
4550 /* XXX : not implemented */
4551 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4552 SPR_NOACCESS, SPR_NOACCESS,
4553 &spr_read_generic, &spr_write_generic,
4554 0x00000000);
80d11f44
JM		 4555 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4556 SPR_NOACCESS, SPR_NOACCESS,
4557 &spr_read_generic, &spr_write_generic,
4558 0x00000000);
4559 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4560 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4561 &spr_read_generic, &spr_write_generic,
4562 0x00000000);
01662f3e
AG		 4563 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4564 SPR_NOACCESS, SPR_NOACCESS,
4565 &spr_read_generic, &spr_write_booke206_mmucsr0,
4566 0x00000000);
4567
f2e63a42 4568#if !defined(CONFIG_USER_ONLY)
01662f3e 4569 env->nb_tlb = 0;
1c53accc 4570 env->tlb_type = TLB_MAS;
01662f3e
AG		 4571 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4572 env->nb_tlb += booke206_tlb_size(env, i);
4573 }
f2e63a42 4574#endif
01662f3e 4575
80d11f44 4576 init_excp_e200(env);
9fdc60bf
AJ		 4577 /* Allocate hardware IRQ controller */
4578 ppce500_irq_init(env);
3fc6c082 4579}
a750fc0b 4580
01662f3e
AG		 4581static void init_proc_e500v1(CPUPPCState *env)
4582{
f7aa5583 4583 init_proc_e500(env, fsl_e500v1);
01662f3e
AG		 4584}
4585
4586static void init_proc_e500v2(CPUPPCState *env)
4587{
f7aa5583
VS		 4588 init_proc_e500(env, fsl_e500v2);
4589}
4590
4591static void init_proc_e500mc(CPUPPCState *env)
4592{
4593 init_proc_e500(env, fsl_e500mc);
01662f3e
AG		 4594}
4595
a750fc0b 4596/* Non-embedded PowerPC */
a750fc0b
JM		 4597
4598/* POWER : same as 601, without mfmsr, mfsr */
4599#if defined(TODO)
4600#define POWERPC_INSNS_POWER (XXX_TODO)
4601/* POWER RSC (from RAD6000) */
4602#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4603#endif /* TODO */
4604
4605/* PowerPC 601 */
082c6681
JM		 4606#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4607 PPC_FLOAT | \
4608 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4609 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4610 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4611#define POWERPC_INSNS2_601 (PPC_NONE)
25ba3a68 4612#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4613#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4614//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4615//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4616#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4617#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4618#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4619#define check_pow_601 check_pow_none
a750fc0b
JM		 4620
4621static void init_proc_601 (CPUPPCState *env)
3fc6c082 4622{
a750fc0b
JM		 4623 gen_spr_ne_601(env);
4624 gen_spr_601(env);
4625 /* Hardware implementation registers */
4626 /* XXX : not implemented */
4627 spr_register(env, SPR_HID0, "HID0",
4628 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4629 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4630 0x80010080);
a750fc0b
JM		 4631 /* XXX : not implemented */
4632 spr_register(env, SPR_HID1, "HID1",
4633 SPR_NOACCESS, SPR_NOACCESS,
4634 &spr_read_generic, &spr_write_generic,
4635 0x00000000);
4636 /* XXX : not implemented */
4637 spr_register(env, SPR_601_HID2, "HID2",
4638 SPR_NOACCESS, SPR_NOACCESS,
4639 &spr_read_generic, &spr_write_generic,
4640 0x00000000);
4641 /* XXX : not implemented */
4642 spr_register(env, SPR_601_HID5, "HID5",
4643 SPR_NOACCESS, SPR_NOACCESS,
4644 &spr_read_generic, &spr_write_generic,
4645 0x00000000);
a750fc0b 4646 /* Memory management */
e1833e1f 4647 init_excp_601(env);
082c6681
JM		 4648 /* XXX: beware that dcache line size is 64
4649 * but dcbz uses 32 bytes "sectors"
4650 * XXX: this breaks clcs instruction !
4651 */
4652 env->dcache_line_size = 32;
d63001d1 4653 env->icache_line_size = 64;
faadf50e
JM		 4654 /* Allocate hardware IRQ controller */
4655 ppc6xx_irq_init(env);
3fc6c082
FB		 4656}
4657
082c6681
JM		 4658/* PowerPC 601v */
4659#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4660 PPC_FLOAT | \
4661 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4662 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4663 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4664#define POWERPC_INSNS2_601v (PPC_NONE)
082c6681
JM		 4665#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4666#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4667#define POWERPC_MMU_601v (POWERPC_MMU_601)
4668#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4669#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4670#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4671#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4672#define check_pow_601v check_pow_none
4673
4674static void init_proc_601v (CPUPPCState *env)
4675{
4676 init_proc_601(env);
4677 /* XXX : not implemented */
4678 spr_register(env, SPR_601_HID15, "HID15",
4679 SPR_NOACCESS, SPR_NOACCESS,
4680 &spr_read_generic, &spr_write_generic,
4681 0x00000000);
4682}
4683
a750fc0b 4684/* PowerPC 602 */
082c6681
JM		 4685#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4686 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4687 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4688 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4689 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4690 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4691 PPC_SEGMENT | PPC_602_SPEC)
a5858d7a 4692#define POWERPC_INSNS2_602 (PPC_NONE)
082c6681
JM		 4693#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4694/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4695#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4696//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4697#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4698#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4699#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4700 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4701#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4702
4703static void init_proc_602 (CPUPPCState *env)
3fc6c082 4704{
a750fc0b
JM		 4705 gen_spr_ne_601(env);
4706 gen_spr_602(env);
4707 /* Time base */
4708 gen_tbl(env);
4709 /* hardware implementation registers */
4710 /* XXX : not implemented */
4711 spr_register(env, SPR_HID0, "HID0",
4712 SPR_NOACCESS, SPR_NOACCESS,
4713 &spr_read_generic, &spr_write_generic,
4714 0x00000000);
4715 /* XXX : not implemented */
4716 spr_register(env, SPR_HID1, "HID1",
4717 SPR_NOACCESS, SPR_NOACCESS,
4718 &spr_read_generic, &spr_write_generic,
4719 0x00000000);
4720 /* Memory management */
4721 gen_low_BATs(env);
4722 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4723 init_excp_602(env);
d63001d1
JM		 4724 env->dcache_line_size = 32;
4725 env->icache_line_size = 32;
a750fc0b
JM		 4726 /* Allocate hardware IRQ controller */
4727 ppc6xx_irq_init(env);
4728}
3fc6c082 4729
a750fc0b 4730/* PowerPC 603 */
082c6681
JM		 4731#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4732 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4733 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4734 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4735 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4736 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4737 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4738#define POWERPC_INSNS2_603 (PPC_NONE)
25ba3a68 4739#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4740#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4741//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4742#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4743#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4744#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4745 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4746#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4747
4748static void init_proc_603 (CPUPPCState *env)
4749{
4750 gen_spr_ne_601(env);
4751 gen_spr_603(env);
4752 /* Time base */
4753 gen_tbl(env);
4754 /* hardware implementation registers */
4755 /* XXX : not implemented */
4756 spr_register(env, SPR_HID0, "HID0",
4757 SPR_NOACCESS, SPR_NOACCESS,
4758 &spr_read_generic, &spr_write_generic,
4759 0x00000000);
4760 /* XXX : not implemented */
4761 spr_register(env, SPR_HID1, "HID1",
4762 SPR_NOACCESS, SPR_NOACCESS,
4763 &spr_read_generic, &spr_write_generic,
4764 0x00000000);
4765 /* Memory management */
4766 gen_low_BATs(env);
4767 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4768 init_excp_603(env);
d63001d1
JM		 4769 env->dcache_line_size = 32;
4770 env->icache_line_size = 32;
a750fc0b
JM		 4771 /* Allocate hardware IRQ controller */
4772 ppc6xx_irq_init(env);
3fc6c082
FB		 4773}
4774
a750fc0b 4775/* PowerPC 603e */
082c6681
JM		 4776#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4777 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4778 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4779 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4780 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4781 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4782 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4783#define POWERPC_INSNS2_603E (PPC_NONE)
a750fc0b
JM		 4784#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4785#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4786//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4787#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4788#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4789#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4790 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4791#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4792
4793static void init_proc_603E (CPUPPCState *env)
4794{
4795 gen_spr_ne_601(env);
4796 gen_spr_603(env);
4797 /* Time base */
4798 gen_tbl(env);
4799 /* hardware implementation registers */
4800 /* XXX : not implemented */
4801 spr_register(env, SPR_HID0, "HID0",
4802 SPR_NOACCESS, SPR_NOACCESS,
4803 &spr_read_generic, &spr_write_generic,
4804 0x00000000);
4805 /* XXX : not implemented */
4806 spr_register(env, SPR_HID1, "HID1",
4807 SPR_NOACCESS, SPR_NOACCESS,
4808 &spr_read_generic, &spr_write_generic,
4809 0x00000000);
4810 /* XXX : not implemented */
4811 spr_register(env, SPR_IABR, "IABR",
4812 SPR_NOACCESS, SPR_NOACCESS,
4813 &spr_read_generic, &spr_write_generic,
4814 0x00000000);
4815 /* Memory management */
4816 gen_low_BATs(env);
4817 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4818 init_excp_603(env);
d63001d1
JM		 4819 env->dcache_line_size = 32;
4820 env->icache_line_size = 32;
a750fc0b
JM		 4821 /* Allocate hardware IRQ controller */
4822 ppc6xx_irq_init(env);
4823}
4824
a750fc0b 4825/* PowerPC 604 */
082c6681
JM		 4826#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4827 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4828 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4829 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4830 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4831 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4832 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4833#define POWERPC_INSNS2_604 (PPC_NONE)
a750fc0b
JM		 4834#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4835#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4836//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4837#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4838#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4839#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4840 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4841#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4842
4843static void init_proc_604 (CPUPPCState *env)
4844{
4845 gen_spr_ne_601(env);
4846 gen_spr_604(env);
4847 /* Time base */
4848 gen_tbl(env);
4849 /* Hardware implementation registers */
4850 /* XXX : not implemented */
082c6681
JM		 4851 spr_register(env, SPR_HID0, "HID0",
4852 SPR_NOACCESS, SPR_NOACCESS,
4853 &spr_read_generic, &spr_write_generic,
4854 0x00000000);
4855 /* Memory management */
4856 gen_low_BATs(env);
4857 init_excp_604(env);
4858 env->dcache_line_size = 32;
4859 env->icache_line_size = 32;
4860 /* Allocate hardware IRQ controller */
4861 ppc6xx_irq_init(env);
4862}
4863
4864/* PowerPC 604E */
4865#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4866 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4867 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4868 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4869 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4870 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4871 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4872#define POWERPC_INSNS2_604E (PPC_NONE)
082c6681
JM		 4873#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4874#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4875#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4876#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4877#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4878#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4879 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4880#define check_pow_604E check_pow_nocheck
4881
4882static void init_proc_604E (CPUPPCState *env)
4883{
4884 gen_spr_ne_601(env);
4885 gen_spr_604(env);
4886 /* XXX : not implemented */
4887 spr_register(env, SPR_MMCR1, "MMCR1",
4888 SPR_NOACCESS, SPR_NOACCESS,
4889 &spr_read_generic, &spr_write_generic,
4890 0x00000000);
4891 /* XXX : not implemented */
4892 spr_register(env, SPR_PMC3, "PMC3",
4893 SPR_NOACCESS, SPR_NOACCESS,
4894 &spr_read_generic, &spr_write_generic,
4895 0x00000000);
4896 /* XXX : not implemented */
4897 spr_register(env, SPR_PMC4, "PMC4",
4898 SPR_NOACCESS, SPR_NOACCESS,
4899 &spr_read_generic, &spr_write_generic,
4900 0x00000000);
4901 /* Time base */
4902 gen_tbl(env);
4903 /* Hardware implementation registers */
4904 /* XXX : not implemented */
a750fc0b
JM		 4905 spr_register(env, SPR_HID0, "HID0",
4906 SPR_NOACCESS, SPR_NOACCESS,
4907 &spr_read_generic, &spr_write_generic,
4908 0x00000000);
4909 /* XXX : not implemented */
4910 spr_register(env, SPR_HID1, "HID1",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914 /* Memory management */
4915 gen_low_BATs(env);
e1833e1f 4916 init_excp_604(env);
d63001d1
JM		 4917 env->dcache_line_size = 32;
4918 env->icache_line_size = 32;
a750fc0b
JM		 4919 /* Allocate hardware IRQ controller */
4920 ppc6xx_irq_init(env);
4921}
4922
bd928eba
JM		 4923/* PowerPC 740 */
4924#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 4925 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4926 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4927 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4928 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4929 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4930 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4931#define POWERPC_INSNS2_740 (PPC_NONE)
bd928eba
JM		 4932#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4933#define POWERPC_MMU_740 (POWERPC_MMU_32B)
4934#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4935#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4936#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4937#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4938 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 4939#define check_pow_740 check_pow_hid0
a750fc0b 4940
bd928eba 4941static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 4942{
4943 gen_spr_ne_601(env);
4944 gen_spr_7xx(env);
4945 /* Time base */
4946 gen_tbl(env);
4947 /* Thermal management */
4948 gen_spr_thrm(env);
4949 /* Hardware implementation registers */
4950 /* XXX : not implemented */
4951 spr_register(env, SPR_HID0, "HID0",
4952 SPR_NOACCESS, SPR_NOACCESS,
4953 &spr_read_generic, &spr_write_generic,
4954 0x00000000);
4955 /* XXX : not implemented */
4956 spr_register(env, SPR_HID1, "HID1",
4957 SPR_NOACCESS, SPR_NOACCESS,
4958 &spr_read_generic, &spr_write_generic,
4959 0x00000000);
4960 /* Memory management */
4961 gen_low_BATs(env);
e1833e1f 4962 init_excp_7x0(env);
d63001d1
JM		 4963 env->dcache_line_size = 32;
4964 env->icache_line_size = 32;
a750fc0b
JM		 4965 /* Allocate hardware IRQ controller */
4966 ppc6xx_irq_init(env);
4967}
4968
bd928eba
JM		 4969/* PowerPC 750 */
4970#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4971 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4972 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4973 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4974 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4975 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4976 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4977#define POWERPC_INSNS2_750 (PPC_NONE)
bd928eba
JM		 4978#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4979#define POWERPC_MMU_750 (POWERPC_MMU_32B)
4980#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4981#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4982#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4983#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4984 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4985#define check_pow_750 check_pow_hid0
4986
4987static void init_proc_750 (CPUPPCState *env)
4988{
4989 gen_spr_ne_601(env);
4990 gen_spr_7xx(env);
4991 /* XXX : not implemented */
4992 spr_register(env, SPR_L2CR, "L2CR",
4993 SPR_NOACCESS, SPR_NOACCESS,
4994 &spr_read_generic, &spr_write_generic,
4995 0x00000000);
4996 /* Time base */
4997 gen_tbl(env);
4998 /* Thermal management */
4999 gen_spr_thrm(env);
5000 /* Hardware implementation registers */
5001 /* XXX : not implemented */
5002 spr_register(env, SPR_HID0, "HID0",
5003 SPR_NOACCESS, SPR_NOACCESS,
5004 &spr_read_generic, &spr_write_generic,
5005 0x00000000);
5006 /* XXX : not implemented */
5007 spr_register(env, SPR_HID1, "HID1",
5008 SPR_NOACCESS, SPR_NOACCESS,
5009 &spr_read_generic, &spr_write_generic,
5010 0x00000000);
5011 /* Memory management */
5012 gen_low_BATs(env);
5013 /* XXX: high BATs are also present but are known to be bugged on
5014 * die version 1.x
5015 */
5016 init_excp_7x0(env);
5017 env->dcache_line_size = 32;
5018 env->icache_line_size = 32;
5019 /* Allocate hardware IRQ controller */
5020 ppc6xx_irq_init(env);
5021}
5022
5023/* PowerPC 750 CL */
5024/* XXX: not implemented:
5025 * cache lock instructions:
5026 * dcbz_l
5027 * floating point paired instructions
5028 * psq_lux
5029 * psq_lx
5030 * psq_stux
5031 * psq_stx
5032 * ps_abs
5033 * ps_add
5034 * ps_cmpo0
5035 * ps_cmpo1
5036 * ps_cmpu0
5037 * ps_cmpu1
5038 * ps_div
5039 * ps_madd
5040 * ps_madds0
5041 * ps_madds1
5042 * ps_merge00
5043 * ps_merge01
5044 * ps_merge10
5045 * ps_merge11
5046 * ps_mr
5047 * ps_msub
5048 * ps_mul
5049 * ps_muls0
5050 * ps_muls1
5051 * ps_nabs
5052 * ps_neg
5053 * ps_nmadd
5054 * ps_nmsub
5055 * ps_res
5056 * ps_rsqrte
5057 * ps_sel
5058 * ps_sub
5059 * ps_sum0
5060 * ps_sum1
5061 */
5062#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5063 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5064 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5065 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5066 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5067 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5068 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5069#define POWERPC_INSNS2_750cl (PPC_NONE)
bd928eba
JM		 5070#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5071#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5072#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5073#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5074#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5075#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5076 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5077#define check_pow_750cl check_pow_hid0
5078
5079static void init_proc_750cl (CPUPPCState *env)
5080{
5081 gen_spr_ne_601(env);
5082 gen_spr_7xx(env);
5083 /* XXX : not implemented */
5084 spr_register(env, SPR_L2CR, "L2CR",
5085 SPR_NOACCESS, SPR_NOACCESS,
5086 &spr_read_generic, &spr_write_generic,
5087 0x00000000);
5088 /* Time base */
5089 gen_tbl(env);
5090 /* Thermal management */
5091 /* Those registers are fake on 750CL */
5092 spr_register(env, SPR_THRM1, "THRM1",
5093 SPR_NOACCESS, SPR_NOACCESS,
5094 &spr_read_generic, &spr_write_generic,
5095 0x00000000);
5096 spr_register(env, SPR_THRM2, "THRM2",
5097 SPR_NOACCESS, SPR_NOACCESS,
5098 &spr_read_generic, &spr_write_generic,
5099 0x00000000);
5100 spr_register(env, SPR_THRM3, "THRM3",
5101 SPR_NOACCESS, SPR_NOACCESS,
5102 &spr_read_generic, &spr_write_generic,
5103 0x00000000);
5104 /* XXX: not implemented */
5105 spr_register(env, SPR_750_TDCL, "TDCL",
5106 SPR_NOACCESS, SPR_NOACCESS,
5107 &spr_read_generic, &spr_write_generic,
5108 0x00000000);
5109 spr_register(env, SPR_750_TDCH, "TDCH",
5110 SPR_NOACCESS, SPR_NOACCESS,
5111 &spr_read_generic, &spr_write_generic,
5112 0x00000000);
5113 /* DMA */
5114 /* XXX : not implemented */
5115 spr_register(env, SPR_750_WPAR, "WPAR",
5116 SPR_NOACCESS, SPR_NOACCESS,
5117 &spr_read_generic, &spr_write_generic,
5118 0x00000000);
5119 spr_register(env, SPR_750_DMAL, "DMAL",
5120 SPR_NOACCESS, SPR_NOACCESS,
5121 &spr_read_generic, &spr_write_generic,
5122 0x00000000);
5123 spr_register(env, SPR_750_DMAU, "DMAU",
5124 SPR_NOACCESS, SPR_NOACCESS,
5125 &spr_read_generic, &spr_write_generic,
5126 0x00000000);
5127 /* Hardware implementation registers */
5128 /* XXX : not implemented */
5129 spr_register(env, SPR_HID0, "HID0",
5130 SPR_NOACCESS, SPR_NOACCESS,
5131 &spr_read_generic, &spr_write_generic,
5132 0x00000000);
5133 /* XXX : not implemented */
5134 spr_register(env, SPR_HID1, "HID1",
5135 SPR_NOACCESS, SPR_NOACCESS,
5136 &spr_read_generic, &spr_write_generic,
5137 0x00000000);
5138 /* XXX : not implemented */
5139 spr_register(env, SPR_750CL_HID2, "HID2",
5140 SPR_NOACCESS, SPR_NOACCESS,
5141 &spr_read_generic, &spr_write_generic,
5142 0x00000000);
5143 /* XXX : not implemented */
5144 spr_register(env, SPR_750CL_HID4, "HID4",
5145 SPR_NOACCESS, SPR_NOACCESS,
5146 &spr_read_generic, &spr_write_generic,
5147 0x00000000);
5148 /* Quantization registers */
5149 /* XXX : not implemented */
5150 spr_register(env, SPR_750_GQR0, "GQR0",
5151 SPR_NOACCESS, SPR_NOACCESS,
5152 &spr_read_generic, &spr_write_generic,
5153 0x00000000);
5154 /* XXX : not implemented */
5155 spr_register(env, SPR_750_GQR1, "GQR1",
5156 SPR_NOACCESS, SPR_NOACCESS,
5157 &spr_read_generic, &spr_write_generic,
5158 0x00000000);
5159 /* XXX : not implemented */
5160 spr_register(env, SPR_750_GQR2, "GQR2",
5161 SPR_NOACCESS, SPR_NOACCESS,
5162 &spr_read_generic, &spr_write_generic,
5163 0x00000000);
5164 /* XXX : not implemented */
5165 spr_register(env, SPR_750_GQR3, "GQR3",
5166 SPR_NOACCESS, SPR_NOACCESS,
5167 &spr_read_generic, &spr_write_generic,
5168 0x00000000);
5169 /* XXX : not implemented */
5170 spr_register(env, SPR_750_GQR4, "GQR4",
5171 SPR_NOACCESS, SPR_NOACCESS,
5172 &spr_read_generic, &spr_write_generic,
5173 0x00000000);
5174 /* XXX : not implemented */
5175 spr_register(env, SPR_750_GQR5, "GQR5",
5176 SPR_NOACCESS, SPR_NOACCESS,
5177 &spr_read_generic, &spr_write_generic,
5178 0x00000000);
5179 /* XXX : not implemented */
5180 spr_register(env, SPR_750_GQR6, "GQR6",
5181 SPR_NOACCESS, SPR_NOACCESS,
5182 &spr_read_generic, &spr_write_generic,
5183 0x00000000);
5184 /* XXX : not implemented */
5185 spr_register(env, SPR_750_GQR7, "GQR7",
5186 SPR_NOACCESS, SPR_NOACCESS,
5187 &spr_read_generic, &spr_write_generic,
5188 0x00000000);
5189 /* Memory management */
5190 gen_low_BATs(env);
5191 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5192 gen_high_BATs(env);
5193 init_excp_750cl(env);
5194 env->dcache_line_size = 32;
5195 env->icache_line_size = 32;
5196 /* Allocate hardware IRQ controller */
5197 ppc6xx_irq_init(env);
5198}
5199
4e777442 5200/* PowerPC 750CX */
bd928eba
JM		 5201#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5202 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5203 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5204 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5205 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5206 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5207 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5208#define POWERPC_INSNS2_750cx (PPC_NONE)
bd928eba
JM		 5209#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5210#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5211#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5212#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5213#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5214#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5215 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5216#define check_pow_750cx check_pow_hid0
5217
5218static void init_proc_750cx (CPUPPCState *env)
5219{
5220 gen_spr_ne_601(env);
5221 gen_spr_7xx(env);
5222 /* XXX : not implemented */
5223 spr_register(env, SPR_L2CR, "L2CR",
5224 SPR_NOACCESS, SPR_NOACCESS,
5225 &spr_read_generic, &spr_write_generic,
5226 0x00000000);
5227 /* Time base */
5228 gen_tbl(env);
5229 /* Thermal management */
5230 gen_spr_thrm(env);
5231 /* This register is not implemented but is present for compatibility */
5232 spr_register(env, SPR_SDA, "SDA",
5233 SPR_NOACCESS, SPR_NOACCESS,
5234 &spr_read_generic, &spr_write_generic,
5235 0x00000000);
5236 /* Hardware implementation registers */
5237 /* XXX : not implemented */
5238 spr_register(env, SPR_HID0, "HID0",
5239 SPR_NOACCESS, SPR_NOACCESS,
5240 &spr_read_generic, &spr_write_generic,
5241 0x00000000);
5242 /* XXX : not implemented */
5243 spr_register(env, SPR_HID1, "HID1",
5244 SPR_NOACCESS, SPR_NOACCESS,
5245 &spr_read_generic, &spr_write_generic,
5246 0x00000000);
5247 /* Memory management */
5248 gen_low_BATs(env);
4e777442
JM		 5249 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5250 gen_high_BATs(env);
bd928eba
JM		 5251 init_excp_750cx(env);
5252 env->dcache_line_size = 32;
5253 env->icache_line_size = 32;
5254 /* Allocate hardware IRQ controller */
5255 ppc6xx_irq_init(env);
5256}
5257
5258/* PowerPC 750FX */
082c6681
JM		 5259#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5260 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 5261 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5262 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5263 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5264 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5265 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5266#define POWERPC_INSNS2_750fx (PPC_NONE)
25ba3a68 5267#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 5268#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5269#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5270#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 5271#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 5272#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5273 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 5274#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 5275
5276static void init_proc_750fx (CPUPPCState *env)
5277{
5278 gen_spr_ne_601(env);
5279 gen_spr_7xx(env);
bd928eba
JM		 5280 /* XXX : not implemented */
5281 spr_register(env, SPR_L2CR, "L2CR",
5282 SPR_NOACCESS, SPR_NOACCESS,
5283 &spr_read_generic, &spr_write_generic,
5284 0x00000000);
a750fc0b
JM		 5285 /* Time base */
5286 gen_tbl(env);
5287 /* Thermal management */
5288 gen_spr_thrm(env);
bd928eba
JM		 5289 /* XXX : not implemented */
5290 spr_register(env, SPR_750_THRM4, "THRM4",
5291 SPR_NOACCESS, SPR_NOACCESS,
5292 &spr_read_generic, &spr_write_generic,
5293 0x00000000);
a750fc0b
JM		 5294 /* Hardware implementation registers */
5295 /* XXX : not implemented */
5296 spr_register(env, SPR_HID0, "HID0",
5297 SPR_NOACCESS, SPR_NOACCESS,
5298 &spr_read_generic, &spr_write_generic,
5299 0x00000000);
5300 /* XXX : not implemented */
5301 spr_register(env, SPR_HID1, "HID1",
5302 SPR_NOACCESS, SPR_NOACCESS,
5303 &spr_read_generic, &spr_write_generic,
5304 0x00000000);
5305 /* XXX : not implemented */
bd928eba 5306 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5307 SPR_NOACCESS, SPR_NOACCESS,
5308 &spr_read_generic, &spr_write_generic,
5309 0x00000000);
5310 /* Memory management */
5311 gen_low_BATs(env);
5312 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5313 gen_high_BATs(env);
bd928eba 5314 init_excp_7x0(env);
d63001d1
JM		 5315 env->dcache_line_size = 32;
5316 env->icache_line_size = 32;
a750fc0b
JM		 5317 /* Allocate hardware IRQ controller */
5318 ppc6xx_irq_init(env);
5319}
5320
bd928eba
JM		 5321/* PowerPC 750GX */
5322#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 5323 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba
JM		 5324 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5325 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5326 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5327 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5328 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5329#define POWERPC_INSNS2_750gx (PPC_NONE)
bd928eba
JM		 5330#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5331#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5332#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5333#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5334#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5335#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5336 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5337#define check_pow_750gx check_pow_hid0
5338
5339static void init_proc_750gx (CPUPPCState *env)
5340{
5341 gen_spr_ne_601(env);
5342 gen_spr_7xx(env);
5343 /* XXX : not implemented (XXX: different from 750fx) */
5344 spr_register(env, SPR_L2CR, "L2CR",
5345 SPR_NOACCESS, SPR_NOACCESS,
5346 &spr_read_generic, &spr_write_generic,
5347 0x00000000);
5348 /* Time base */
5349 gen_tbl(env);
5350 /* Thermal management */
5351 gen_spr_thrm(env);
5352 /* XXX : not implemented */
5353 spr_register(env, SPR_750_THRM4, "THRM4",
5354 SPR_NOACCESS, SPR_NOACCESS,
5355 &spr_read_generic, &spr_write_generic,
5356 0x00000000);
5357 /* Hardware implementation registers */
5358 /* XXX : not implemented (XXX: different from 750fx) */
5359 spr_register(env, SPR_HID0, "HID0",
5360 SPR_NOACCESS, SPR_NOACCESS,
5361 &spr_read_generic, &spr_write_generic,
5362 0x00000000);
5363 /* XXX : not implemented */
5364 spr_register(env, SPR_HID1, "HID1",
5365 SPR_NOACCESS, SPR_NOACCESS,
5366 &spr_read_generic, &spr_write_generic,
5367 0x00000000);
5368 /* XXX : not implemented (XXX: different from 750fx) */
5369 spr_register(env, SPR_750FX_HID2, "HID2",
5370 SPR_NOACCESS, SPR_NOACCESS,
5371 &spr_read_generic, &spr_write_generic,
5372 0x00000000);
5373 /* Memory management */
5374 gen_low_BATs(env);
5375 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5376 gen_high_BATs(env);
5377 init_excp_7x0(env);
5378 env->dcache_line_size = 32;
5379 env->icache_line_size = 32;
5380 /* Allocate hardware IRQ controller */
5381 ppc6xx_irq_init(env);
5382}
5383
5384/* PowerPC 745 */
5385#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5386 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5387 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5388 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5389 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5390 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5391 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5392#define POWERPC_INSNS2_745 (PPC_NONE)
bd928eba
JM		 5393#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5394#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5395#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5396#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5397#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5398#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5399 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5400#define check_pow_745 check_pow_hid0
5401
5402static void init_proc_745 (CPUPPCState *env)
5403{
5404 gen_spr_ne_601(env);
5405 gen_spr_7xx(env);
5406 gen_spr_G2_755(env);
5407 /* Time base */
5408 gen_tbl(env);
5409 /* Thermal management */
5410 gen_spr_thrm(env);
5411 /* Hardware implementation registers */
5412 /* XXX : not implemented */
5413 spr_register(env, SPR_HID0, "HID0",
5414 SPR_NOACCESS, SPR_NOACCESS,
5415 &spr_read_generic, &spr_write_generic,
5416 0x00000000);
5417 /* XXX : not implemented */
5418 spr_register(env, SPR_HID1, "HID1",
5419 SPR_NOACCESS, SPR_NOACCESS,
5420 &spr_read_generic, &spr_write_generic,
5421 0x00000000);
5422 /* XXX : not implemented */
5423 spr_register(env, SPR_HID2, "HID2",
5424 SPR_NOACCESS, SPR_NOACCESS,
5425 &spr_read_generic, &spr_write_generic,
5426 0x00000000);
5427 /* Memory management */
5428 gen_low_BATs(env);
5429 gen_high_BATs(env);
5430 gen_6xx_7xx_soft_tlb(env, 64, 2);
5431 init_excp_7x5(env);
5432 env->dcache_line_size = 32;
5433 env->icache_line_size = 32;
5434 /* Allocate hardware IRQ controller */
5435 ppc6xx_irq_init(env);
5436}
5437
5438/* PowerPC 755 */
5439#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5440 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5441 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5442 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5443 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5444 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5445 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5446#define POWERPC_INSNS2_755 (PPC_NONE)
bd928eba
JM		 5447#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5448#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5449#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5450#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5451#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5452#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5453 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5454#define check_pow_755 check_pow_hid0
a750fc0b 5455
bd928eba 5456static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5457{
5458 gen_spr_ne_601(env);
bd928eba 5459 gen_spr_7xx(env);
a750fc0b
JM		 5460 gen_spr_G2_755(env);
5461 /* Time base */
5462 gen_tbl(env);
5463 /* L2 cache control */
5464 /* XXX : not implemented */
bd928eba 5465 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5466 SPR_NOACCESS, SPR_NOACCESS,
5467 &spr_read_generic, &spr_write_generic,
5468 0x00000000);
5469 /* XXX : not implemented */
5470 spr_register(env, SPR_L2PMCR, "L2PMCR",
5471 SPR_NOACCESS, SPR_NOACCESS,
5472 &spr_read_generic, &spr_write_generic,
5473 0x00000000);
bd928eba
JM		 5474 /* Thermal management */
5475 gen_spr_thrm(env);
a750fc0b
JM		 5476 /* Hardware implementation registers */
5477 /* XXX : not implemented */
5478 spr_register(env, SPR_HID0, "HID0",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 &spr_read_generic, &spr_write_generic,
5481 0x00000000);
5482 /* XXX : not implemented */
5483 spr_register(env, SPR_HID1, "HID1",
5484 SPR_NOACCESS, SPR_NOACCESS,
5485 &spr_read_generic, &spr_write_generic,
5486 0x00000000);
5487 /* XXX : not implemented */
5488 spr_register(env, SPR_HID2, "HID2",
5489 SPR_NOACCESS, SPR_NOACCESS,
5490 &spr_read_generic, &spr_write_generic,
5491 0x00000000);
5492 /* Memory management */
5493 gen_low_BATs(env);
5494 gen_high_BATs(env);
5495 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5496 init_excp_7x5(env);
d63001d1
JM		 5497 env->dcache_line_size = 32;
5498 env->icache_line_size = 32;
a750fc0b
JM		 5499 /* Allocate hardware IRQ controller */
5500 ppc6xx_irq_init(env);
5501}
5502
5503/* PowerPC 7400 (aka G4) */
082c6681
JM		 5504#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5505 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5506 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5507 PPC_FLOAT_STFIWX | \
5508 PPC_CACHE | PPC_CACHE_ICBI | \
5509 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5510 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5511 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5512 PPC_MEM_TLBIA | \
5513 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5514 PPC_ALTIVEC)
a5858d7a 5515#define POWERPC_INSNS2_7400 (PPC_NONE)
a750fc0b
JM		 5516#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5517#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5518#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5519#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5520#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5521#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5522 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5523 POWERPC_FLAG_BUS_CLK)
488243b0 5524#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 5525
5526static void init_proc_7400 (CPUPPCState *env)
5527{
5528 gen_spr_ne_601(env);
5529 gen_spr_7xx(env);
5530 /* Time base */
5531 gen_tbl(env);
5532 /* 74xx specific SPR */
5533 gen_spr_74xx(env);
4e777442
JM		 5534 /* XXX : not implemented */
5535 spr_register(env, SPR_UBAMR, "UBAMR",
5536 &spr_read_ureg, SPR_NOACCESS,
5537 &spr_read_ureg, SPR_NOACCESS,
5538 0x00000000);
5539 /* XXX: this seems not implemented on all revisions. */
5540 /* XXX : not implemented */
5541 spr_register(env, SPR_MSSCR1, "MSSCR1",
5542 SPR_NOACCESS, SPR_NOACCESS,
5543 &spr_read_generic, &spr_write_generic,
5544 0x00000000);
a750fc0b
JM		 5545 /* Thermal management */
5546 gen_spr_thrm(env);
5547 /* Memory management */
5548 gen_low_BATs(env);
e1833e1f 5549 init_excp_7400(env);
d63001d1
JM		 5550 env->dcache_line_size = 32;
5551 env->icache_line_size = 32;
a750fc0b
JM		 5552 /* Allocate hardware IRQ controller */
5553 ppc6xx_irq_init(env);
5554}
5555
5556/* PowerPC 7410 (aka G4) */
082c6681
JM		 5557#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5558 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5559 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5560 PPC_FLOAT_STFIWX | \
5561 PPC_CACHE | PPC_CACHE_ICBI | \
5562 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5563 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5564 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5565 PPC_MEM_TLBIA | \
5566 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5567 PPC_ALTIVEC)
a5858d7a 5568#define POWERPC_INSNS2_7410 (PPC_NONE)
a750fc0b
JM		 5569#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5570#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5571#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5572#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5573#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5574#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5575 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5576 POWERPC_FLAG_BUS_CLK)
488243b0 5577#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 5578
5579static void init_proc_7410 (CPUPPCState *env)
5580{
5581 gen_spr_ne_601(env);
5582 gen_spr_7xx(env);
5583 /* Time base */
5584 gen_tbl(env);
5585 /* 74xx specific SPR */
5586 gen_spr_74xx(env);
4e777442
JM		 5587 /* XXX : not implemented */
5588 spr_register(env, SPR_UBAMR, "UBAMR",
5589 &spr_read_ureg, SPR_NOACCESS,
5590 &spr_read_ureg, SPR_NOACCESS,
5591 0x00000000);
a750fc0b
JM		 5592 /* Thermal management */
5593 gen_spr_thrm(env);
5594 /* L2PMCR */
5595 /* XXX : not implemented */
5596 spr_register(env, SPR_L2PMCR, "L2PMCR",
5597 SPR_NOACCESS, SPR_NOACCESS,
5598 &spr_read_generic, &spr_write_generic,
5599 0x00000000);
5600 /* LDSTDB */
5601 /* XXX : not implemented */
5602 spr_register(env, SPR_LDSTDB, "LDSTDB",
5603 SPR_NOACCESS, SPR_NOACCESS,
5604 &spr_read_generic, &spr_write_generic,
5605 0x00000000);
5606 /* Memory management */
5607 gen_low_BATs(env);
e1833e1f 5608 init_excp_7400(env);
d63001d1
JM		 5609 env->dcache_line_size = 32;
5610 env->icache_line_size = 32;
a750fc0b
JM		 5611 /* Allocate hardware IRQ controller */
5612 ppc6xx_irq_init(env);
5613}
5614
5615/* PowerPC 7440 (aka G4) */
082c6681
JM		 5616#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5617 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5618 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5619 PPC_FLOAT_STFIWX | \
5620 PPC_CACHE | PPC_CACHE_ICBI | \
5621 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5622 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5623 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5624 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5625 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5626 PPC_ALTIVEC)
a5858d7a 5627#define POWERPC_INSNS2_7440 (PPC_NONE)
a750fc0b
JM		 5628#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5629#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5630#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5631#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 5632#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 5633#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5634 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5635 POWERPC_FLAG_BUS_CLK)
4e777442 5636#define check_pow_7440 check_pow_hid0_74xx
a750fc0b 5637
578bb252 5638__attribute__ (( unused ))
a750fc0b
JM		 5639static void init_proc_7440 (CPUPPCState *env)
5640{
5641 gen_spr_ne_601(env);
5642 gen_spr_7xx(env);
5643 /* Time base */
5644 gen_tbl(env);
5645 /* 74xx specific SPR */
5646 gen_spr_74xx(env);
4e777442
JM		 5647 /* XXX : not implemented */
5648 spr_register(env, SPR_UBAMR, "UBAMR",
5649 &spr_read_ureg, SPR_NOACCESS,
5650 &spr_read_ureg, SPR_NOACCESS,
5651 0x00000000);
a750fc0b
JM		 5652 /* LDSTCR */
5653 /* XXX : not implemented */
5654 spr_register(env, SPR_LDSTCR, "LDSTCR",
5655 SPR_NOACCESS, SPR_NOACCESS,
5656 &spr_read_generic, &spr_write_generic,
5657 0x00000000);
5658 /* ICTRL */
5659 /* XXX : not implemented */
5660 spr_register(env, SPR_ICTRL, "ICTRL",
5661 SPR_NOACCESS, SPR_NOACCESS,
5662 &spr_read_generic, &spr_write_generic,
5663 0x00000000);
5664 /* MSSSR0 */
578bb252 5665 /* XXX : not implemented */
a750fc0b
JM		 5666 spr_register(env, SPR_MSSSR0, "MSSSR0",
5667 SPR_NOACCESS, SPR_NOACCESS,
5668 &spr_read_generic, &spr_write_generic,
5669 0x00000000);
5670 /* PMC */
5671 /* XXX : not implemented */
5672 spr_register(env, SPR_PMC5, "PMC5",
5673 SPR_NOACCESS, SPR_NOACCESS,
5674 &spr_read_generic, &spr_write_generic,
5675 0x00000000);
578bb252 5676 /* XXX : not implemented */
a750fc0b
JM		 5677 spr_register(env, SPR_UPMC5, "UPMC5",
5678 &spr_read_ureg, SPR_NOACCESS,
5679 &spr_read_ureg, SPR_NOACCESS,
5680 0x00000000);
578bb252 5681 /* XXX : not implemented */
a750fc0b
JM		 5682 spr_register(env, SPR_PMC6, "PMC6",
5683 SPR_NOACCESS, SPR_NOACCESS,
5684 &spr_read_generic, &spr_write_generic,
5685 0x00000000);
578bb252 5686 /* XXX : not implemented */
a750fc0b
JM		 5687 spr_register(env, SPR_UPMC6, "UPMC6",
5688 &spr_read_ureg, SPR_NOACCESS,
5689 &spr_read_ureg, SPR_NOACCESS,
5690 0x00000000);
5691 /* Memory management */
5692 gen_low_BATs(env);
578bb252 5693 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5694 init_excp_7450(env);
d63001d1
JM		 5695 env->dcache_line_size = 32;
5696 env->icache_line_size = 32;
a750fc0b
JM		 5697 /* Allocate hardware IRQ controller */
5698 ppc6xx_irq_init(env);
5699}
a750fc0b
JM		 5700
5701/* PowerPC 7450 (aka G4) */
082c6681
JM		 5702#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5703 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5704 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5705 PPC_FLOAT_STFIWX | \
5706 PPC_CACHE | PPC_CACHE_ICBI | \
5707 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5708 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5709 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5710 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5711 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5712 PPC_ALTIVEC)
a5858d7a 5713#define POWERPC_INSNS2_7450 (PPC_NONE)
a750fc0b
JM		 5714#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5715#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5716#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5717#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 5718#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 5719#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5720 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5721 POWERPC_FLAG_BUS_CLK)
4e777442 5722#define check_pow_7450 check_pow_hid0_74xx
a750fc0b 5723
578bb252 5724__attribute__ (( unused ))
a750fc0b
JM		 5725static void init_proc_7450 (CPUPPCState *env)
5726{
5727 gen_spr_ne_601(env);
5728 gen_spr_7xx(env);
5729 /* Time base */
5730 gen_tbl(env);
5731 /* 74xx specific SPR */
5732 gen_spr_74xx(env);
5733 /* Level 3 cache control */
5734 gen_l3_ctrl(env);
4e777442
JM		 5735 /* L3ITCR1 */
5736 /* XXX : not implemented */
5737 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5738 SPR_NOACCESS, SPR_NOACCESS,
5739 &spr_read_generic, &spr_write_generic,
5740 0x00000000);
5741 /* L3ITCR2 */
5742 /* XXX : not implemented */
5743 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5744 SPR_NOACCESS, SPR_NOACCESS,
5745 &spr_read_generic, &spr_write_generic,
5746 0x00000000);
5747 /* L3ITCR3 */
5748 /* XXX : not implemented */
5749 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5750 SPR_NOACCESS, SPR_NOACCESS,
5751 &spr_read_generic, &spr_write_generic,
5752 0x00000000);
5753 /* L3OHCR */
5754 /* XXX : not implemented */
5755 spr_register(env, SPR_L3OHCR, "L3OHCR",
5756 SPR_NOACCESS, SPR_NOACCESS,
5757 &spr_read_generic, &spr_write_generic,
5758 0x00000000);
5759 /* XXX : not implemented */
5760 spr_register(env, SPR_UBAMR, "UBAMR",
5761 &spr_read_ureg, SPR_NOACCESS,
5762 &spr_read_ureg, SPR_NOACCESS,
5763 0x00000000);
a750fc0b
JM		 5764 /* LDSTCR */
5765 /* XXX : not implemented */
5766 spr_register(env, SPR_LDSTCR, "LDSTCR",
5767 SPR_NOACCESS, SPR_NOACCESS,
5768 &spr_read_generic, &spr_write_generic,
5769 0x00000000);
5770 /* ICTRL */
5771 /* XXX : not implemented */
5772 spr_register(env, SPR_ICTRL, "ICTRL",
5773 SPR_NOACCESS, SPR_NOACCESS,
5774 &spr_read_generic, &spr_write_generic,
5775 0x00000000);
5776 /* MSSSR0 */
578bb252 5777 /* XXX : not implemented */
a750fc0b
JM		 5778 spr_register(env, SPR_MSSSR0, "MSSSR0",
5779 SPR_NOACCESS, SPR_NOACCESS,
5780 &spr_read_generic, &spr_write_generic,
5781 0x00000000);
5782 /* PMC */
5783 /* XXX : not implemented */
5784 spr_register(env, SPR_PMC5, "PMC5",
5785 SPR_NOACCESS, SPR_NOACCESS,
5786 &spr_read_generic, &spr_write_generic,
5787 0x00000000);
578bb252 5788 /* XXX : not implemented */
a750fc0b
JM		 5789 spr_register(env, SPR_UPMC5, "UPMC5",
5790 &spr_read_ureg, SPR_NOACCESS,
5791 &spr_read_ureg, SPR_NOACCESS,
5792 0x00000000);
578bb252 5793 /* XXX : not implemented */
a750fc0b
JM		 5794 spr_register(env, SPR_PMC6, "PMC6",
5795 SPR_NOACCESS, SPR_NOACCESS,
5796 &spr_read_generic, &spr_write_generic,
5797 0x00000000);
578bb252 5798 /* XXX : not implemented */
a750fc0b
JM		 5799 spr_register(env, SPR_UPMC6, "UPMC6",
5800 &spr_read_ureg, SPR_NOACCESS,
5801 &spr_read_ureg, SPR_NOACCESS,
5802 0x00000000);
5803 /* Memory management */
5804 gen_low_BATs(env);
578bb252 5805 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5806 init_excp_7450(env);
d63001d1
JM		 5807 env->dcache_line_size = 32;
5808 env->icache_line_size = 32;
a750fc0b
JM		 5809 /* Allocate hardware IRQ controller */
5810 ppc6xx_irq_init(env);
5811}
a750fc0b
JM		 5812
5813/* PowerPC 7445 (aka G4) */
082c6681
JM		 5814#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5815 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5816 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5817 PPC_FLOAT_STFIWX | \
5818 PPC_CACHE | PPC_CACHE_ICBI | \
5819 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5820 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5821 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5822 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5823 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5824 PPC_ALTIVEC)
a5858d7a 5825#define POWERPC_INSNS2_7445 (PPC_NONE)
a750fc0b
JM		 5826#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5827#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5828#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5829#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 5830#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 5831#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5832 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5833 POWERPC_FLAG_BUS_CLK)
4e777442 5834#define check_pow_7445 check_pow_hid0_74xx
a750fc0b 5835
578bb252 5836__attribute__ (( unused ))
a750fc0b
JM		 5837static void init_proc_7445 (CPUPPCState *env)
5838{
5839 gen_spr_ne_601(env);
5840 gen_spr_7xx(env);
5841 /* Time base */
5842 gen_tbl(env);
5843 /* 74xx specific SPR */
5844 gen_spr_74xx(env);
5845 /* LDSTCR */
5846 /* XXX : not implemented */
5847 spr_register(env, SPR_LDSTCR, "LDSTCR",
5848 SPR_NOACCESS, SPR_NOACCESS,
5849 &spr_read_generic, &spr_write_generic,
5850 0x00000000);
5851 /* ICTRL */
5852 /* XXX : not implemented */
5853 spr_register(env, SPR_ICTRL, "ICTRL",
5854 SPR_NOACCESS, SPR_NOACCESS,
5855 &spr_read_generic, &spr_write_generic,
5856 0x00000000);
5857 /* MSSSR0 */
578bb252 5858 /* XXX : not implemented */
a750fc0b
JM		 5859 spr_register(env, SPR_MSSSR0, "MSSSR0",
5860 SPR_NOACCESS, SPR_NOACCESS,
5861 &spr_read_generic, &spr_write_generic,
5862 0x00000000);
5863 /* PMC */
5864 /* XXX : not implemented */
5865 spr_register(env, SPR_PMC5, "PMC5",
5866 SPR_NOACCESS, SPR_NOACCESS,
5867 &spr_read_generic, &spr_write_generic,
5868 0x00000000);
578bb252 5869 /* XXX : not implemented */
a750fc0b
JM		 5870 spr_register(env, SPR_UPMC5, "UPMC5",
5871 &spr_read_ureg, SPR_NOACCESS,
5872 &spr_read_ureg, SPR_NOACCESS,
5873 0x00000000);
578bb252 5874 /* XXX : not implemented */
a750fc0b
JM		 5875 spr_register(env, SPR_PMC6, "PMC6",
5876 SPR_NOACCESS, SPR_NOACCESS,
5877 &spr_read_generic, &spr_write_generic,
5878 0x00000000);
578bb252 5879 /* XXX : not implemented */
a750fc0b
JM		 5880 spr_register(env, SPR_UPMC6, "UPMC6",
5881 &spr_read_ureg, SPR_NOACCESS,
5882 &spr_read_ureg, SPR_NOACCESS,
5883 0x00000000);
5884 /* SPRGs */
5885 spr_register(env, SPR_SPRG4, "SPRG4",
5886 SPR_NOACCESS, SPR_NOACCESS,
5887 &spr_read_generic, &spr_write_generic,
5888 0x00000000);
5889 spr_register(env, SPR_USPRG4, "USPRG4",
5890 &spr_read_ureg, SPR_NOACCESS,
5891 &spr_read_ureg, SPR_NOACCESS,
5892 0x00000000);
5893 spr_register(env, SPR_SPRG5, "SPRG5",
5894 SPR_NOACCESS, SPR_NOACCESS,
5895 &spr_read_generic, &spr_write_generic,
5896 0x00000000);
5897 spr_register(env, SPR_USPRG5, "USPRG5",
5898 &spr_read_ureg, SPR_NOACCESS,
5899 &spr_read_ureg, SPR_NOACCESS,
5900 0x00000000);
5901 spr_register(env, SPR_SPRG6, "SPRG6",
5902 SPR_NOACCESS, SPR_NOACCESS,
5903 &spr_read_generic, &spr_write_generic,
5904 0x00000000);
5905 spr_register(env, SPR_USPRG6, "USPRG6",
5906 &spr_read_ureg, SPR_NOACCESS,
5907 &spr_read_ureg, SPR_NOACCESS,
5908 0x00000000);
5909 spr_register(env, SPR_SPRG7, "SPRG7",
5910 SPR_NOACCESS, SPR_NOACCESS,
5911 &spr_read_generic, &spr_write_generic,
5912 0x00000000);
5913 spr_register(env, SPR_USPRG7, "USPRG7",
5914 &spr_read_ureg, SPR_NOACCESS,
5915 &spr_read_ureg, SPR_NOACCESS,
5916 0x00000000);
5917 /* Memory management */
5918 gen_low_BATs(env);
5919 gen_high_BATs(env);
578bb252 5920 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5921 init_excp_7450(env);
d63001d1
JM		 5922 env->dcache_line_size = 32;
5923 env->icache_line_size = 32;
a750fc0b
JM		 5924 /* Allocate hardware IRQ controller */
5925 ppc6xx_irq_init(env);
5926}
a750fc0b
JM		 5927
5928/* PowerPC 7455 (aka G4) */
082c6681
JM		 5929#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5930 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5931 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5932 PPC_FLOAT_STFIWX | \
5933 PPC_CACHE | PPC_CACHE_ICBI | \
5934 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5935 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5936 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5937 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5938 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5939 PPC_ALTIVEC)
a5858d7a 5940#define POWERPC_INSNS2_7455 (PPC_NONE)
a750fc0b
JM		 5941#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5942#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5943#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5944#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 5945#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 5946#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5947 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5948 POWERPC_FLAG_BUS_CLK)
4e777442 5949#define check_pow_7455 check_pow_hid0_74xx
a750fc0b 5950
578bb252 5951__attribute__ (( unused ))
a750fc0b
JM		 5952static void init_proc_7455 (CPUPPCState *env)
5953{
5954 gen_spr_ne_601(env);
5955 gen_spr_7xx(env);
5956 /* Time base */
5957 gen_tbl(env);
5958 /* 74xx specific SPR */
5959 gen_spr_74xx(env);
5960 /* Level 3 cache control */
5961 gen_l3_ctrl(env);
5962 /* LDSTCR */
5963 /* XXX : not implemented */
5964 spr_register(env, SPR_LDSTCR, "LDSTCR",
5965 SPR_NOACCESS, SPR_NOACCESS,
5966 &spr_read_generic, &spr_write_generic,
5967 0x00000000);
5968 /* ICTRL */
5969 /* XXX : not implemented */
5970 spr_register(env, SPR_ICTRL, "ICTRL",
5971 SPR_NOACCESS, SPR_NOACCESS,
5972 &spr_read_generic, &spr_write_generic,
5973 0x00000000);
5974 /* MSSSR0 */
578bb252 5975 /* XXX : not implemented */
a750fc0b
JM		 5976 spr_register(env, SPR_MSSSR0, "MSSSR0",
5977 SPR_NOACCESS, SPR_NOACCESS,
5978 &spr_read_generic, &spr_write_generic,
5979 0x00000000);
5980 /* PMC */
5981 /* XXX : not implemented */
5982 spr_register(env, SPR_PMC5, "PMC5",
5983 SPR_NOACCESS, SPR_NOACCESS,
5984 &spr_read_generic, &spr_write_generic,
5985 0x00000000);
578bb252 5986 /* XXX : not implemented */
a750fc0b
JM		 5987 spr_register(env, SPR_UPMC5, "UPMC5",
5988 &spr_read_ureg, SPR_NOACCESS,
5989 &spr_read_ureg, SPR_NOACCESS,
5990 0x00000000);
578bb252 5991 /* XXX : not implemented */
a750fc0b
JM		 5992 spr_register(env, SPR_PMC6, "PMC6",
5993 SPR_NOACCESS, SPR_NOACCESS,
5994 &spr_read_generic, &spr_write_generic,
5995 0x00000000);
578bb252 5996 /* XXX : not implemented */
a750fc0b
JM		 5997 spr_register(env, SPR_UPMC6, "UPMC6",
5998 &spr_read_ureg, SPR_NOACCESS,
5999 &spr_read_ureg, SPR_NOACCESS,
6000 0x00000000);
6001 /* SPRGs */
6002 spr_register(env, SPR_SPRG4, "SPRG4",
6003 SPR_NOACCESS, SPR_NOACCESS,
6004 &spr_read_generic, &spr_write_generic,
6005 0x00000000);
6006 spr_register(env, SPR_USPRG4, "USPRG4",
6007 &spr_read_ureg, SPR_NOACCESS,
6008 &spr_read_ureg, SPR_NOACCESS,
6009 0x00000000);
6010 spr_register(env, SPR_SPRG5, "SPRG5",
6011 SPR_NOACCESS, SPR_NOACCESS,
6012 &spr_read_generic, &spr_write_generic,
6013 0x00000000);
6014 spr_register(env, SPR_USPRG5, "USPRG5",
6015 &spr_read_ureg, SPR_NOACCESS,
6016 &spr_read_ureg, SPR_NOACCESS,
6017 0x00000000);
6018 spr_register(env, SPR_SPRG6, "SPRG6",
6019 SPR_NOACCESS, SPR_NOACCESS,
6020 &spr_read_generic, &spr_write_generic,
6021 0x00000000);
6022 spr_register(env, SPR_USPRG6, "USPRG6",
6023 &spr_read_ureg, SPR_NOACCESS,
6024 &spr_read_ureg, SPR_NOACCESS,
6025 0x00000000);
6026 spr_register(env, SPR_SPRG7, "SPRG7",
6027 SPR_NOACCESS, SPR_NOACCESS,
6028 &spr_read_generic, &spr_write_generic,
6029 0x00000000);
6030 spr_register(env, SPR_USPRG7, "USPRG7",
6031 &spr_read_ureg, SPR_NOACCESS,
6032 &spr_read_ureg, SPR_NOACCESS,
6033 0x00000000);
6034 /* Memory management */
6035 gen_low_BATs(env);
6036 gen_high_BATs(env);
578bb252 6037 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6038 init_excp_7450(env);
d63001d1
JM		 6039 env->dcache_line_size = 32;
6040 env->icache_line_size = 32;
a750fc0b
JM		 6041 /* Allocate hardware IRQ controller */
6042 ppc6xx_irq_init(env);
6043}
a750fc0b 6044
4e777442
JM		 6045/* PowerPC 7457 (aka G4) */
6046#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6047 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6048 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6049 PPC_FLOAT_STFIWX | \
6050 PPC_CACHE | PPC_CACHE_ICBI | \
6051 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6052 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6053 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6054 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6055 PPC_SEGMENT | PPC_EXTERN | \
6056 PPC_ALTIVEC)
a5858d7a 6057#define POWERPC_INSNS2_7457 (PPC_NONE)
4e777442
JM		 6058#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6059#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6060#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6061#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6062#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6063#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6064 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6065 POWERPC_FLAG_BUS_CLK)
6066#define check_pow_7457 check_pow_hid0_74xx
6067
6068__attribute__ (( unused ))
6069static void init_proc_7457 (CPUPPCState *env)
6070{
6071 gen_spr_ne_601(env);
6072 gen_spr_7xx(env);
6073 /* Time base */
6074 gen_tbl(env);
6075 /* 74xx specific SPR */
6076 gen_spr_74xx(env);
6077 /* Level 3 cache control */
6078 gen_l3_ctrl(env);
6079 /* L3ITCR1 */
6080 /* XXX : not implemented */
6081 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6082 SPR_NOACCESS, SPR_NOACCESS,
6083 &spr_read_generic, &spr_write_generic,
6084 0x00000000);
6085 /* L3ITCR2 */
6086 /* XXX : not implemented */
6087 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6088 SPR_NOACCESS, SPR_NOACCESS,
6089 &spr_read_generic, &spr_write_generic,
6090 0x00000000);
6091 /* L3ITCR3 */
6092 /* XXX : not implemented */
6093 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6094 SPR_NOACCESS, SPR_NOACCESS,
6095 &spr_read_generic, &spr_write_generic,
6096 0x00000000);
6097 /* L3OHCR */
6098 /* XXX : not implemented */
6099 spr_register(env, SPR_L3OHCR, "L3OHCR",
6100 SPR_NOACCESS, SPR_NOACCESS,
6101 &spr_read_generic, &spr_write_generic,
6102 0x00000000);
6103 /* LDSTCR */
6104 /* XXX : not implemented */
6105 spr_register(env, SPR_LDSTCR, "LDSTCR",
6106 SPR_NOACCESS, SPR_NOACCESS,
6107 &spr_read_generic, &spr_write_generic,
6108 0x00000000);
6109 /* ICTRL */
6110 /* XXX : not implemented */
6111 spr_register(env, SPR_ICTRL, "ICTRL",
6112 SPR_NOACCESS, SPR_NOACCESS,
6113 &spr_read_generic, &spr_write_generic,
6114 0x00000000);
6115 /* MSSSR0 */
6116 /* XXX : not implemented */
6117 spr_register(env, SPR_MSSSR0, "MSSSR0",
6118 SPR_NOACCESS, SPR_NOACCESS,
6119 &spr_read_generic, &spr_write_generic,
6120 0x00000000);
6121 /* PMC */
6122 /* XXX : not implemented */
6123 spr_register(env, SPR_PMC5, "PMC5",
6124 SPR_NOACCESS, SPR_NOACCESS,
6125 &spr_read_generic, &spr_write_generic,
6126 0x00000000);
6127 /* XXX : not implemented */
6128 spr_register(env, SPR_UPMC5, "UPMC5",
6129 &spr_read_ureg, SPR_NOACCESS,
6130 &spr_read_ureg, SPR_NOACCESS,
6131 0x00000000);
6132 /* XXX : not implemented */
6133 spr_register(env, SPR_PMC6, "PMC6",
6134 SPR_NOACCESS, SPR_NOACCESS,
6135 &spr_read_generic, &spr_write_generic,
6136 0x00000000);
6137 /* XXX : not implemented */
6138 spr_register(env, SPR_UPMC6, "UPMC6",
6139 &spr_read_ureg, SPR_NOACCESS,
6140 &spr_read_ureg, SPR_NOACCESS,
6141 0x00000000);
6142 /* SPRGs */
6143 spr_register(env, SPR_SPRG4, "SPRG4",
6144 SPR_NOACCESS, SPR_NOACCESS,
6145 &spr_read_generic, &spr_write_generic,
6146 0x00000000);
6147 spr_register(env, SPR_USPRG4, "USPRG4",
6148 &spr_read_ureg, SPR_NOACCESS,
6149 &spr_read_ureg, SPR_NOACCESS,
6150 0x00000000);
6151 spr_register(env, SPR_SPRG5, "SPRG5",
6152 SPR_NOACCESS, SPR_NOACCESS,
6153 &spr_read_generic, &spr_write_generic,
6154 0x00000000);
6155 spr_register(env, SPR_USPRG5, "USPRG5",
6156 &spr_read_ureg, SPR_NOACCESS,
6157 &spr_read_ureg, SPR_NOACCESS,
6158 0x00000000);
6159 spr_register(env, SPR_SPRG6, "SPRG6",
6160 SPR_NOACCESS, SPR_NOACCESS,
6161 &spr_read_generic, &spr_write_generic,
6162 0x00000000);
6163 spr_register(env, SPR_USPRG6, "USPRG6",
6164 &spr_read_ureg, SPR_NOACCESS,
6165 &spr_read_ureg, SPR_NOACCESS,
6166 0x00000000);
6167 spr_register(env, SPR_SPRG7, "SPRG7",
6168 SPR_NOACCESS, SPR_NOACCESS,
6169 &spr_read_generic, &spr_write_generic,
6170 0x00000000);
6171 spr_register(env, SPR_USPRG7, "USPRG7",
6172 &spr_read_ureg, SPR_NOACCESS,
6173 &spr_read_ureg, SPR_NOACCESS,
6174 0x00000000);
6175 /* Memory management */
6176 gen_low_BATs(env);
6177 gen_high_BATs(env);
6178 gen_74xx_soft_tlb(env, 128, 2);
6179 init_excp_7450(env);
6180 env->dcache_line_size = 32;
6181 env->icache_line_size = 32;
6182 /* Allocate hardware IRQ controller */
6183 ppc6xx_irq_init(env);
6184}
6185
a750fc0b
JM		 6186#if defined (TARGET_PPC64)
6187/* PowerPC 970 */
082c6681
JM		 6188#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6189 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6190 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6191 PPC_FLOAT_STFIWX | \
6192 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6193 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6194 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6195 PPC_64B | PPC_ALTIVEC | \
12de9a39 6196 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6197#define POWERPC_INSNS2_970 (PPC_NONE)
a750fc0b 6198#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 6199#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 6200//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6201#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 6202#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 6203#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6204 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6205 POWERPC_FLAG_BUS_CLK)
a750fc0b 6206
417bf010
JM		 6207#if defined(CONFIG_USER_ONLY)
6208#define POWERPC970_HID5_INIT 0x00000080
6209#else
6210#define POWERPC970_HID5_INIT 0x00000000
6211#endif
6212
2f462816
JM		 6213static int check_pow_970 (CPUPPCState *env)
6214{
6215 if (env->spr[SPR_HID0] & 0x00600000)
6216 return 1;
6217
6218 return 0;
6219}
6220
a750fc0b
JM		 6221static void init_proc_970 (CPUPPCState *env)
6222{
6223 gen_spr_ne_601(env);
6224 gen_spr_7xx(env);
6225 /* Time base */
6226 gen_tbl(env);
6227 /* Hardware implementation registers */
6228 /* XXX : not implemented */
6229 spr_register(env, SPR_HID0, "HID0",
6230 SPR_NOACCESS, SPR_NOACCESS,
06403421 6231 &spr_read_generic, &spr_write_clear,
d63001d1 6232 0x60000000);
a750fc0b
JM		 6233 /* XXX : not implemented */
6234 spr_register(env, SPR_HID1, "HID1",
6235 SPR_NOACCESS, SPR_NOACCESS,
6236 &spr_read_generic, &spr_write_generic,
6237 0x00000000);
6238 /* XXX : not implemented */
bd928eba 6239 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6240 SPR_NOACCESS, SPR_NOACCESS,
6241 &spr_read_generic, &spr_write_generic,
6242 0x00000000);
e57448f1
JM		 6243 /* XXX : not implemented */
6244 spr_register(env, SPR_970_HID5, "HID5",
6245 SPR_NOACCESS, SPR_NOACCESS,
6246 &spr_read_generic, &spr_write_generic,
417bf010 6247 POWERPC970_HID5_INIT);
bd928eba
JM		 6248 /* XXX : not implemented */
6249 spr_register(env, SPR_L2CR, "L2CR",
6250 SPR_NOACCESS, SPR_NOACCESS,
6251 &spr_read_generic, &spr_write_generic,
6252 0x00000000);
a750fc0b
JM		 6253 /* Memory management */
6254 /* XXX: not correct */
6255 gen_low_BATs(env);
12de9a39
JM		 6256 /* XXX : not implemented */
6257 spr_register(env, SPR_MMUCFG, "MMUCFG",
6258 SPR_NOACCESS, SPR_NOACCESS,
6259 &spr_read_generic, SPR_NOACCESS,
6260 0x00000000); /* TOFIX */
6261 /* XXX : not implemented */
6262 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6263 SPR_NOACCESS, SPR_NOACCESS,
6264 &spr_read_generic, &spr_write_generic,
6265 0x00000000); /* TOFIX */
6266 spr_register(env, SPR_HIOR, "SPR_HIOR",
6267 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6268 &spr_read_hior, &spr_write_hior,
6269 0x00000000);
f2e63a42 6270#if !defined(CONFIG_USER_ONLY)
12de9a39 6271 env->slb_nr = 32;
f2e63a42 6272#endif
e1833e1f 6273 init_excp_970(env);
d63001d1
JM		 6274 env->dcache_line_size = 128;
6275 env->icache_line_size = 128;
a750fc0b
JM		 6276 /* Allocate hardware IRQ controller */
6277 ppc970_irq_init(env);
cf8358c8
AJ		 6278 /* Can't find information on what this should be on reset. This
6279 * value is the one used by 74xx processors. */
6280 vscr_init(env, 0x00010000);
a750fc0b 6281}
a750fc0b
JM		 6282
6283/* PowerPC 970FX (aka G5) */
082c6681
JM		 6284#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6285 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6286 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6287 PPC_FLOAT_STFIWX | \
6288 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6289 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6290 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6291 PPC_64B | PPC_ALTIVEC | \
12de9a39 6292 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6293#define POWERPC_INSNS2_970FX (PPC_NONE)
a750fc0b 6294#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 6295#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 6296#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6297#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 6298#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 6299#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6300 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6301 POWERPC_FLAG_BUS_CLK)
a750fc0b 6302
2f462816
JM		 6303static int check_pow_970FX (CPUPPCState *env)
6304{
6305 if (env->spr[SPR_HID0] & 0x00600000)
6306 return 1;
6307
6308 return 0;
6309}
6310
a750fc0b
JM		 6311static void init_proc_970FX (CPUPPCState *env)
6312{
6313 gen_spr_ne_601(env);
6314 gen_spr_7xx(env);
6315 /* Time base */
6316 gen_tbl(env);
6317 /* Hardware implementation registers */
6318 /* XXX : not implemented */
6319 spr_register(env, SPR_HID0, "HID0",
6320 SPR_NOACCESS, SPR_NOACCESS,
06403421 6321 &spr_read_generic, &spr_write_clear,
d63001d1 6322 0x60000000);
a750fc0b
JM		 6323 /* XXX : not implemented */
6324 spr_register(env, SPR_HID1, "HID1",
6325 SPR_NOACCESS, SPR_NOACCESS,
6326 &spr_read_generic, &spr_write_generic,
6327 0x00000000);
6328 /* XXX : not implemented */
bd928eba 6329 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6330 SPR_NOACCESS, SPR_NOACCESS,
6331 &spr_read_generic, &spr_write_generic,
6332 0x00000000);
d63001d1
JM		 6333 /* XXX : not implemented */
6334 spr_register(env, SPR_970_HID5, "HID5",
6335 SPR_NOACCESS, SPR_NOACCESS,
6336 &spr_read_generic, &spr_write_generic,
417bf010 6337 POWERPC970_HID5_INIT);
bd928eba
JM		 6338 /* XXX : not implemented */
6339 spr_register(env, SPR_L2CR, "L2CR",
6340 SPR_NOACCESS, SPR_NOACCESS,
6341 &spr_read_generic, &spr_write_generic,
6342 0x00000000);
a750fc0b
JM		 6343 /* Memory management */
6344 /* XXX: not correct */
6345 gen_low_BATs(env);
12de9a39
JM		 6346 /* XXX : not implemented */
6347 spr_register(env, SPR_MMUCFG, "MMUCFG",
6348 SPR_NOACCESS, SPR_NOACCESS,
6349 &spr_read_generic, SPR_NOACCESS,
6350 0x00000000); /* TOFIX */
6351 /* XXX : not implemented */
6352 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6353 SPR_NOACCESS, SPR_NOACCESS,
6354 &spr_read_generic, &spr_write_generic,
6355 0x00000000); /* TOFIX */
6356 spr_register(env, SPR_HIOR, "SPR_HIOR",
6357 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6358 &spr_read_hior, &spr_write_hior,
6359 0x00000000);
4e98d8cf
BS		 6360 spr_register(env, SPR_CTRL, "SPR_CTRL",
6361 SPR_NOACCESS, SPR_NOACCESS,
6362 &spr_read_generic, &spr_write_generic,
6363 0x00000000);
6364 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6365 SPR_NOACCESS, SPR_NOACCESS,
6366 &spr_read_generic, &spr_write_generic,
6367 0x00000000);
6368 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6369 &spr_read_generic, &spr_write_generic,
6370 &spr_read_generic, &spr_write_generic,
6371 0x00000000);
f2e63a42 6372#if !defined(CONFIG_USER_ONLY)
8eee0af9 6373 env->slb_nr = 64;
f2e63a42 6374#endif
e1833e1f 6375 init_excp_970(env);
d63001d1
JM		 6376 env->dcache_line_size = 128;
6377 env->icache_line_size = 128;
a750fc0b
JM		 6378 /* Allocate hardware IRQ controller */
6379 ppc970_irq_init(env);
cf8358c8
AJ		 6380 /* Can't find information on what this should be on reset. This
6381 * value is the one used by 74xx processors. */
6382 vscr_init(env, 0x00010000);
a750fc0b 6383}
a750fc0b
JM		 6384
6385/* PowerPC 970 GX */
082c6681
JM		 6386#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6387 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6388 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6389 PPC_FLOAT_STFIWX | \
6390 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6391 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6392 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6393 PPC_64B | PPC_ALTIVEC | \
12de9a39 6394 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6395#define POWERPC_INSNS2_970GX (PPC_NONE)
a750fc0b 6396#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6397#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6398#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6399#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6400#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6401#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6402 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6403 POWERPC_FLAG_BUS_CLK)
a750fc0b 6404
2f462816
JM		 6405static int check_pow_970GX (CPUPPCState *env)
6406{
6407 if (env->spr[SPR_HID0] & 0x00600000)
6408 return 1;
6409
6410 return 0;
6411}
6412
a750fc0b
JM		 6413static void init_proc_970GX (CPUPPCState *env)
6414{
6415 gen_spr_ne_601(env);
6416 gen_spr_7xx(env);
6417 /* Time base */
6418 gen_tbl(env);
6419 /* Hardware implementation registers */
6420 /* XXX : not implemented */
6421 spr_register(env, SPR_HID0, "HID0",
6422 SPR_NOACCESS, SPR_NOACCESS,
06403421 6423 &spr_read_generic, &spr_write_clear,
d63001d1 6424 0x60000000);
a750fc0b
JM		 6425 /* XXX : not implemented */
6426 spr_register(env, SPR_HID1, "HID1",
6427 SPR_NOACCESS, SPR_NOACCESS,
6428 &spr_read_generic, &spr_write_generic,
6429 0x00000000);
6430 /* XXX : not implemented */
bd928eba 6431 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6432 SPR_NOACCESS, SPR_NOACCESS,
6433 &spr_read_generic, &spr_write_generic,
6434 0x00000000);
d63001d1
JM		 6435 /* XXX : not implemented */
6436 spr_register(env, SPR_970_HID5, "HID5",
6437 SPR_NOACCESS, SPR_NOACCESS,
6438 &spr_read_generic, &spr_write_generic,
417bf010 6439 POWERPC970_HID5_INIT);
bd928eba
JM		 6440 /* XXX : not implemented */
6441 spr_register(env, SPR_L2CR, "L2CR",
6442 SPR_NOACCESS, SPR_NOACCESS,
6443 &spr_read_generic, &spr_write_generic,
6444 0x00000000);
a750fc0b
JM		 6445 /* Memory management */
6446 /* XXX: not correct */
6447 gen_low_BATs(env);
12de9a39
JM		 6448 /* XXX : not implemented */
6449 spr_register(env, SPR_MMUCFG, "MMUCFG",
6450 SPR_NOACCESS, SPR_NOACCESS,
6451 &spr_read_generic, SPR_NOACCESS,
6452 0x00000000); /* TOFIX */
6453 /* XXX : not implemented */
6454 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6455 SPR_NOACCESS, SPR_NOACCESS,
6456 &spr_read_generic, &spr_write_generic,
6457 0x00000000); /* TOFIX */
6458 spr_register(env, SPR_HIOR, "SPR_HIOR",
6459 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6460 &spr_read_hior, &spr_write_hior,
6461 0x00000000);
f2e63a42 6462#if !defined(CONFIG_USER_ONLY)
12de9a39 6463 env->slb_nr = 32;
f2e63a42 6464#endif
e1833e1f 6465 init_excp_970(env);
d63001d1
JM		 6466 env->dcache_line_size = 128;
6467 env->icache_line_size = 128;
a750fc0b
JM		 6468 /* Allocate hardware IRQ controller */
6469 ppc970_irq_init(env);
cf8358c8
AJ		 6470 /* Can't find information on what this should be on reset. This
6471 * value is the one used by 74xx processors. */
6472 vscr_init(env, 0x00010000);
a750fc0b 6473}
a750fc0b 6474
2f462816 6475/* PowerPC 970 MP */
082c6681
JM		 6476#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6477 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6478 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6479 PPC_FLOAT_STFIWX | \
6480 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6481 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6482 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 6483 PPC_64B | PPC_ALTIVEC | \
6484 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6485#define POWERPC_INSNS2_970MP (PPC_NONE)
2f462816
JM		 6486#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6487#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6488#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6489#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6490#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6491#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6492 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6493 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6494
6495static int check_pow_970MP (CPUPPCState *env)
6496{
6497 if (env->spr[SPR_HID0] & 0x01C00000)
6498 return 1;
6499
6500 return 0;
6501}
6502
6503static void init_proc_970MP (CPUPPCState *env)
6504{
6505 gen_spr_ne_601(env);
6506 gen_spr_7xx(env);
6507 /* Time base */
6508 gen_tbl(env);
6509 /* Hardware implementation registers */
6510 /* XXX : not implemented */
6511 spr_register(env, SPR_HID0, "HID0",
6512 SPR_NOACCESS, SPR_NOACCESS,
6513 &spr_read_generic, &spr_write_clear,
6514 0x60000000);
6515 /* XXX : not implemented */
6516 spr_register(env, SPR_HID1, "HID1",
6517 SPR_NOACCESS, SPR_NOACCESS,
6518 &spr_read_generic, &spr_write_generic,
6519 0x00000000);
6520 /* XXX : not implemented */
bd928eba 6521 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6522 SPR_NOACCESS, SPR_NOACCESS,
6523 &spr_read_generic, &spr_write_generic,
6524 0x00000000);
6525 /* XXX : not implemented */
6526 spr_register(env, SPR_970_HID5, "HID5",
6527 SPR_NOACCESS, SPR_NOACCESS,
6528 &spr_read_generic, &spr_write_generic,
6529 POWERPC970_HID5_INIT);
bd928eba
JM		 6530 /* XXX : not implemented */
6531 spr_register(env, SPR_L2CR, "L2CR",
6532 SPR_NOACCESS, SPR_NOACCESS,
6533 &spr_read_generic, &spr_write_generic,
6534 0x00000000);
2f462816
JM		 6535 /* Memory management */
6536 /* XXX: not correct */
6537 gen_low_BATs(env);
6538 /* XXX : not implemented */
6539 spr_register(env, SPR_MMUCFG, "MMUCFG",
6540 SPR_NOACCESS, SPR_NOACCESS,
6541 &spr_read_generic, SPR_NOACCESS,
6542 0x00000000); /* TOFIX */
6543 /* XXX : not implemented */
6544 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6545 SPR_NOACCESS, SPR_NOACCESS,
6546 &spr_read_generic, &spr_write_generic,
6547 0x00000000); /* TOFIX */
6548 spr_register(env, SPR_HIOR, "SPR_HIOR",
6549 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6550 &spr_read_hior, &spr_write_hior,
6551 0x00000000);
2f462816
JM		 6552#if !defined(CONFIG_USER_ONLY)
6553 env->slb_nr = 32;
6554#endif
6555 init_excp_970(env);
6556 env->dcache_line_size = 128;
6557 env->icache_line_size = 128;
6558 /* Allocate hardware IRQ controller */
6559 ppc970_irq_init(env);
cf8358c8
AJ		 6560 /* Can't find information on what this should be on reset. This
6561 * value is the one used by 74xx processors. */
6562 vscr_init(env, 0x00010000);
2f462816
JM		 6563}
6564
9d52e907
DG		 6565#if defined(TARGET_PPC64)
6566/* POWER7 */
6567#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6568 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6569 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6570 PPC_FLOAT_STFIWX | \
6571 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6572 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6573 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6574 PPC_64B | PPC_ALTIVEC | \
6575 PPC_SEGMENT_64B | PPC_SLBI | \
6576 PPC_POPCNTB | PPC_POPCNTWD)
cd6e9320 6577#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
9d52e907
DG		 6578#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6579#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6580#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6581#define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6582#define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6583#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6584 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
697ab892 6585 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
9d52e907
DG		 6586#define check_pow_POWER7 check_pow_nocheck
6587
6588static void init_proc_POWER7 (CPUPPCState *env)
6589{
6590 gen_spr_ne_601(env);
6591 gen_spr_7xx(env);
6592 /* Time base */
6593 gen_tbl(env);
2e06214f
NW		 6594 /* Processor identification */
6595 spr_register(env, SPR_PIR, "PIR",
6596 SPR_NOACCESS, SPR_NOACCESS,
6597 &spr_read_generic, &spr_write_pir,
6598 0x00000000);
9d52e907
DG		 6599#if !defined(CONFIG_USER_ONLY)
6600 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6601 spr_register(env, SPR_PURR, "PURR",
6602 &spr_read_purr, SPR_NOACCESS,
6603 &spr_read_purr, SPR_NOACCESS,
6604 0x00000000);
6605 spr_register(env, SPR_SPURR, "SPURR",
6606 &spr_read_purr, SPR_NOACCESS,
6607 &spr_read_purr, SPR_NOACCESS,
6608 0x00000000);
697ab892
DG		 6609 spr_register(env, SPR_CFAR, "SPR_CFAR",
6610 SPR_NOACCESS, SPR_NOACCESS,
6611 &spr_read_cfar, &spr_write_cfar,
6612 0x00000000);
6613 spr_register(env, SPR_DSCR, "SPR_DSCR",
6614 SPR_NOACCESS, SPR_NOACCESS,
6615 &spr_read_generic, &spr_write_generic,
6616 0x00000000);
9d52e907
DG		 6617#endif /* !CONFIG_USER_ONLY */
6618 /* Memory management */
6619 /* XXX : not implemented */
6620 spr_register(env, SPR_MMUCFG, "MMUCFG",
6621 SPR_NOACCESS, SPR_NOACCESS,
6622 &spr_read_generic, SPR_NOACCESS,
6623 0x00000000); /* TOFIX */
6624 /* XXX : not implemented */
6625 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6626 SPR_NOACCESS, SPR_NOACCESS,
6627 &spr_read_generic, &spr_write_generic,
6628 0x80800000);
6629 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6630 SPR_NOACCESS, SPR_NOACCESS,
6631 &spr_read_generic, &spr_write_generic,
6632 0x80800000);
6633 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6634 &spr_read_generic, &spr_write_generic,
6635 &spr_read_generic, &spr_write_generic,
6636 0x00000000);
6637#if !defined(CONFIG_USER_ONLY)
6638 env->slb_nr = 32;
6639#endif
6640 init_excp_POWER7(env);
6641 env->dcache_line_size = 128;
6642 env->icache_line_size = 128;
6643 /* Allocate hardware IRQ controller */
6644 ppcPOWER7_irq_init(env);
6645 /* Can't find information on what this should be on reset. This
6646 * value is the one used by 74xx processors. */
6647 vscr_init(env, 0x00010000);
6648}
6649#endif /* TARGET_PPC64 */
6650
a750fc0b 6651/* PowerPC 620 */
082c6681
JM		 6652#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6653 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6654 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6655 PPC_FLOAT_STFIWX | \
6656 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6657 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6658 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6659 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6660 PPC_64B | PPC_SLBI)
a5858d7a 6661#define POWERPC_INSNS2_620 (PPC_NONE)
add78955
JM		 6662#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6663//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 6664#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 6665#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 6666#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 6667#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 6668 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 6669#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 6670
578bb252 6671__attribute__ (( unused ))
a750fc0b
JM		 6672static void init_proc_620 (CPUPPCState *env)
6673{
6674 gen_spr_ne_601(env);
6675 gen_spr_620(env);
6676 /* Time base */
6677 gen_tbl(env);
6678 /* Hardware implementation registers */
6679 /* XXX : not implemented */
6680 spr_register(env, SPR_HID0, "HID0",
6681 SPR_NOACCESS, SPR_NOACCESS,
6682 &spr_read_generic, &spr_write_generic,
6683 0x00000000);
6684 /* Memory management */
6685 gen_low_BATs(env);
e1833e1f 6686 init_excp_620(env);
d63001d1
JM		 6687 env->dcache_line_size = 64;
6688 env->icache_line_size = 64;
faadf50e
JM		 6689 /* Allocate hardware IRQ controller */
6690 ppc6xx_irq_init(env);
a750fc0b 6691}
a750fc0b
JM		 6692#endif /* defined (TARGET_PPC64) */
6693
6694/* Default 32 bits PowerPC target will be 604 */
6695#define CPU_POWERPC_PPC32 CPU_POWERPC_604
6696#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
a5858d7a 6697#define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
a750fc0b
JM		 6698#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6699#define POWERPC_MMU_PPC32 POWERPC_MMU_604
6700#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6701#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 6702#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 6703#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 6704#define check_pow_PPC32 check_pow_604
6705#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 6706
6707/* Default 64 bits PowerPC target will be 970 FX */
6708#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6709#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
a5858d7a 6710#define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
a750fc0b
JM		 6711#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6712#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6713#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6714#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 6715#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 6716#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 6717#define check_pow_PPC64 check_pow_970FX
6718#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 6719
6720/* Default PowerPC target will be PowerPC 32 */
6721#if defined (TARGET_PPC64) && 0 // XXX: TODO
a5858d7a
AG		 6722#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6723#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6bbc5ed1 6724#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC64
a5858d7a
AG		 6725#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6726#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6727#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6728#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6729#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6730#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6731#define check_pow_DEFAULT check_pow_PPC64
6732#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 6733#else
a5858d7a
AG		 6734#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6735#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6bbc5ed1 6736#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC32
a5858d7a
AG		 6737#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6738#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6739#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6740#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6741#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6742#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6743#define check_pow_DEFAULT check_pow_PPC32
6744#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 6745#endif
6746
6747/*****************************************************************************/
6748/* PVR definitions for most known PowerPC */
6749enum {
6750 /* PowerPC 401 family */
6751 /* Generic PowerPC 401 */
80d11f44 6752#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 6753 /* PowerPC 401 cores */
80d11f44
JM		 6754 CPU_POWERPC_401A1 = 0x00210000,
6755 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 6756#if 0
80d11f44 6757 CPU_POWERPC_401B3 = xxx,
a750fc0b 6758#endif
80d11f44
JM		 6759 CPU_POWERPC_401C2 = 0x00230000,
6760 CPU_POWERPC_401D2 = 0x00240000,
6761 CPU_POWERPC_401E2 = 0x00250000,
6762 CPU_POWERPC_401F2 = 0x00260000,
6763 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 6764 /* PowerPC 401 microcontrolers */
6765#if 0
80d11f44 6766 CPU_POWERPC_401GF = xxx,
a750fc0b 6767#endif
80d11f44 6768#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 6769 /* IBM Processor for Network Resources */
80d11f44 6770 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 6771#if 0
80d11f44 6772 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 6773#endif
6774 /* PowerPC 403 family */
6775 /* Generic PowerPC 403 */
80d11f44 6776#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 6777 /* PowerPC 403 microcontrollers */
80d11f44
JM		 6778 CPU_POWERPC_403GA = 0x00200011,
6779 CPU_POWERPC_403GB = 0x00200100,
6780 CPU_POWERPC_403GC = 0x00200200,
6781 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 6782#if 0
80d11f44 6783 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 6784#endif
6785 /* PowerPC 405 family */
6786 /* Generic PowerPC 405 */
80d11f44 6787#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 6788 /* PowerPC 405 cores */
6789#if 0
80d11f44 6790 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 6791#endif
6792#if 0
80d11f44 6793 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 6794#endif
6795#if 0
80d11f44 6796 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 6797#endif
6798#if 0
80d11f44 6799 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 6800#endif
6801#if 0
80d11f44 6802 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 6803#endif
6804#if 0
80d11f44 6805 CPU_POWERPC_405C4 = xxx,
a750fc0b 6806#endif
80d11f44 6807 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 6808#if 0
80d11f44 6809 CPU_POWERPC_405D3 = xxx,
a750fc0b 6810#endif
80d11f44 6811 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 6812#if 0
80d11f44 6813 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 6814#endif
6815#if 0
80d11f44 6816 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 6817#endif
6818#if 0
80d11f44 6819 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 6820#endif
6821#if 0
80d11f44 6822 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 6823#endif
6824#if 0
80d11f44 6825 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 6826#endif
6827 /* PowerPC 405 microcontrolers */
6828 /* XXX: missing 0x200108a0 */
80d11f44
JM		 6829#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6830 CPU_POWERPC_405CRa = 0x40110041,
6831 CPU_POWERPC_405CRb = 0x401100C5,
6832 CPU_POWERPC_405CRc = 0x40110145,
6833 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 6834#if 0
80d11f44 6835 CPU_POWERPC_405EXr = xxx,
a750fc0b 6836#endif
80d11f44 6837 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 6838#if 0
80d11f44
JM		 6839 CPU_POWERPC_405FX = xxx,
6840#endif
6841#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6842 CPU_POWERPC_405GPa = 0x40110000,
6843 CPU_POWERPC_405GPb = 0x40110040,
6844 CPU_POWERPC_405GPc = 0x40110082,
6845 CPU_POWERPC_405GPd = 0x401100C4,
6846#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6847 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 6848#if 0
80d11f44 6849 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 6850#endif
6851#if 0
80d11f44 6852 CPU_POWERPC_405L = xxx,
a750fc0b 6853#endif
80d11f44 6854 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 6855#if 0
80d11f44 6856 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 6857#endif
6858#if 0
80d11f44 6859 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 6860#endif
6861#if 0
80d11f44 6862 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 6863#endif
6864 /* IBM network processors */
80d11f44
JM		 6865 CPU_POWERPC_NPE405H = 0x414100C0,
6866 CPU_POWERPC_NPE405H2 = 0x41410140,
6867 CPU_POWERPC_NPE405L = 0x416100C0,
6868 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 6869#if 0
80d11f44 6870 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 6871#endif
6872#if 0
80d11f44 6873 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 6874#endif
6875#if 0
80d11f44 6876 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 6877#endif
6878 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6879#if 0
80d11f44 6880 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 6881#endif
6882#if 0
80d11f44 6883 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 6884#endif
6885#if 0
80d11f44 6886 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 6887#endif
80d11f44 6888 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 6889#if 0
80d11f44 6890 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 6891#endif
6892#if 0
80d11f44 6893 CPU_POWERPC_STB045 = xxx,
a750fc0b 6894#endif
80d11f44
JM		 6895 CPU_POWERPC_STB04 = 0x41810000,
6896 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 6897#if 0
80d11f44 6898 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 6899#endif
6900 /* Xilinx cores */
80d11f44
JM		 6901 CPU_POWERPC_X2VP4 = 0x20010820,
6902#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6903 CPU_POWERPC_X2VP20 = 0x20010860,
6904#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 6905#if 0
80d11f44 6906 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 6907#endif
6908#if 0
80d11f44 6909 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 6910#endif
6911#if 0
80d11f44 6912 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 6913#endif
6914#if 0
80d11f44 6915 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 6916#endif
6917 /* PowerPC 440 family */
6918 /* Generic PowerPC 440 */
80d11f44 6919#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 6920 /* PowerPC 440 cores */
6921#if 0
80d11f44 6922 CPU_POWERPC_440A4 = xxx,
a750fc0b 6923#endif
95070372 6924 CPU_POWERPC_440_XILINX = 0x7ff21910,
a750fc0b 6925#if 0
80d11f44 6926 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 6927#endif
6928#if 0
80d11f44 6929 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 6930#endif
6931#if 0
80d11f44 6932 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 6933#endif
6934#if 0
80d11f44 6935 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 6936#endif
6937#if 0
80d11f44 6938 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 6939#endif
6940#if 0
80d11f44 6941 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 6942#endif
6943 /* PowerPC 440 microcontrolers */
80d11f44
JM		 6944#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6945 CPU_POWERPC_440EPa = 0x42221850,
6946 CPU_POWERPC_440EPb = 0x422218D3,
6947#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6948 CPU_POWERPC_440GPb = 0x40120440,
6949 CPU_POWERPC_440GPc = 0x40120481,
6950#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6951#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6952 CPU_POWERPC_440GRX = 0x200008D0,
6953#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6954#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6955 CPU_POWERPC_440GXa = 0x51B21850,
6956 CPU_POWERPC_440GXb = 0x51B21851,
6957 CPU_POWERPC_440GXc = 0x51B21892,
6958 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 6959#if 0
80d11f44 6960 CPU_POWERPC_440S = xxx,
a750fc0b 6961#endif
80d11f44
JM		 6962 CPU_POWERPC_440SP = 0x53221850,
6963 CPU_POWERPC_440SP2 = 0x53221891,
6964 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 6965 /* PowerPC 460 family */
6966#if 0
6967 /* Generic PowerPC 464 */
80d11f44 6968#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 6969#endif
6970 /* PowerPC 464 microcontrolers */
6971#if 0
80d11f44 6972 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 6973#endif
6974#if 0
80d11f44 6975 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 6976#endif
6977 /* Freescale embedded PowerPC cores */
c3e36823 6978 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 6979 CPU_POWERPC_MPC5xx = 0x00020020,
6980#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6981#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6982#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6983#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6984#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6985#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6986#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6987#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6988#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6989#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6990#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6991#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6992#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 6993 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 6994 CPU_POWERPC_MPC8xx = 0x00500000,
6995#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6996#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6997#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6998#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6999#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
7000#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
7001#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
7002#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
7003#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
7004#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
7005#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
7006#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
7007#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
7008#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
7009#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 7010 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 7011 CPU_POWERPC_G2 = 0x00810011,
7012 CPU_POWERPC_G2H4 = 0x80811010,
7013 CPU_POWERPC_G2gp = 0x80821010,
7014 CPU_POWERPC_G2ls = 0x90810010,
7015 CPU_POWERPC_MPC603 = 0x00810100,
7016 CPU_POWERPC_G2_HIP3 = 0x00810101,
7017 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 7018 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 7019 CPU_POWERPC_G2LE = 0x80820010,
7020 CPU_POWERPC_G2LEgp = 0x80822010,
7021 CPU_POWERPC_G2LEls = 0xA0822010,
7022 CPU_POWERPC_G2LEgp1 = 0x80822011,
7023 CPU_POWERPC_G2LEgp3 = 0x80822013,
7024 /* MPC52xx microcontrollers */
c3e36823 7025 /* XXX: MPC 5121 ? */
80d11f44
JM		 7026#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
7027#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
7028#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7029#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7030#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7031#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
7032#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7033#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7034 /* MPC82xx microcontrollers */
7035#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
7036#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
7037#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
7038#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
7039#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
7040#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
7041#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
7042#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
7043#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7044#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7045#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7046#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7047#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7048#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7049#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7050#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7051#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7052#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7053#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7054#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7055#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7056#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7057#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7058#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7059#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7060#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7061#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7062#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7063#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 7064 /* e200 family */
80d11f44
JM		 7065 /* e200 cores */
7066#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 7067#if 0
80d11f44 7068 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 7069#endif
7070#if 0
80d11f44 7071 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 7072#endif
7073#if 0 /* ? */
80d11f44
JM		 7074 CPU_POWERPC_e200z3 = 0x81120000,
7075#endif
7076 CPU_POWERPC_e200z5 = 0x81000000,
7077 CPU_POWERPC_e200z6 = 0x81120000,
7078 /* MPC55xx microcontrollers */
7079#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7080#if 0
7081#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7082#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7083#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7084#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7085#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7086#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7087#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7088#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7089#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7090#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7091#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7092#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7093#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7094#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7095#endif
7096#if 0
7097#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7098#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7099#endif
7100#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7101#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7102#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7103#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7104#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7105#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 7106 /* e300 family */
80d11f44
JM		 7107 /* e300 cores */
7108#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7109 CPU_POWERPC_e300c1 = 0x00830010,
7110 CPU_POWERPC_e300c2 = 0x00840010,
7111 CPU_POWERPC_e300c3 = 0x00850010,
7112 CPU_POWERPC_e300c4 = 0x00860010,
7113 /* MPC83xx microcontrollers */
74d77cae
TM		 7114#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7115#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7116#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7117#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7118#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7119#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
a750fc0b 7120 /* e500 family */
80d11f44
JM		 7121 /* e500 cores */
7122#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
bd5ea513 7123#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
80d11f44 7124#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 7125 CPU_POWERPC_e500v1_v10 = 0x80200010,
7126 CPU_POWERPC_e500v1_v20 = 0x80200020,
80d11f44
JM		 7127 CPU_POWERPC_e500v2_v10 = 0x80210010,
7128 CPU_POWERPC_e500v2_v11 = 0x80210011,
7129 CPU_POWERPC_e500v2_v20 = 0x80210020,
7130 CPU_POWERPC_e500v2_v21 = 0x80210021,
7131 CPU_POWERPC_e500v2_v22 = 0x80210022,
7132 CPU_POWERPC_e500v2_v30 = 0x80210030,
f7aa5583 7133 CPU_POWERPC_e500mc = 0x80230020,
80d11f44
JM		 7134 /* MPC85xx microcontrollers */
7135#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7136#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7137#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7138#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7139#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7140#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7141#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
bd5ea513
AJ		 7142#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7143#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7144#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
80d11f44 7145#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
bd5ea513
AJ		 7146#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7147#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
80d11f44 7148#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
bd5ea513
AJ		 7149#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7150#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
80d11f44
JM		 7151#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7152#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7153#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7154#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7155#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7156#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7157#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7158#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7159#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7160#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7161#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7162#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7163#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7164#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7165#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7166#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7167#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7168#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7169#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7170#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7171#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7172#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7173#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7174#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7175#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7176#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7177#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7178#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7179#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7180#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7181#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7182#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7183#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7184#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7185#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7186#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7187#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7188#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7189#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7190#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7191#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7192#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7193#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7194#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7195#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7196#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7197#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7198#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7199#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7200#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7201#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7202#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7203#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7204#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 7205 /* e600 family */
80d11f44
JM		 7206 /* e600 cores */
7207 CPU_POWERPC_e600 = 0x80040010,
7208 /* MPC86xx microcontrollers */
7209#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7210#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7211#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 7212 /* PowerPC 6xx cores */
80d11f44
JM		 7213#define CPU_POWERPC_601 CPU_POWERPC_601_v2
7214 CPU_POWERPC_601_v0 = 0x00010001,
7215 CPU_POWERPC_601_v1 = 0x00010001,
bd928eba 7216#define CPU_POWERPC_601v CPU_POWERPC_601_v2
80d11f44
JM		 7217 CPU_POWERPC_601_v2 = 0x00010002,
7218 CPU_POWERPC_602 = 0x00050100,
7219 CPU_POWERPC_603 = 0x00030100,
7220#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7221 CPU_POWERPC_603E_v11 = 0x00060101,
7222 CPU_POWERPC_603E_v12 = 0x00060102,
7223 CPU_POWERPC_603E_v13 = 0x00060103,
7224 CPU_POWERPC_603E_v14 = 0x00060104,
7225 CPU_POWERPC_603E_v22 = 0x00060202,
7226 CPU_POWERPC_603E_v3 = 0x00060300,
7227 CPU_POWERPC_603E_v4 = 0x00060400,
7228 CPU_POWERPC_603E_v41 = 0x00060401,
7229 CPU_POWERPC_603E7t = 0x00071201,
7230 CPU_POWERPC_603E7v = 0x00070100,
7231 CPU_POWERPC_603E7v1 = 0x00070101,
7232 CPU_POWERPC_603E7v2 = 0x00070201,
7233 CPU_POWERPC_603E7 = 0x00070200,
7234 CPU_POWERPC_603P = 0x00070000,
7235#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 7236 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 7237 CPU_POWERPC_604 = 0x00040103,
7238#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 7239 /* XXX: missing 0x00091203 */
7240 /* XXX: missing 0x00092110 */
7241 /* XXX: missing 0x00092120 */
80d11f44
JM		 7242 CPU_POWERPC_604E_v10 = 0x00090100,
7243 CPU_POWERPC_604E_v22 = 0x00090202,
7244 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 7245 /* XXX: missing 0x000a0100 */
7246 /* XXX: missing 0x00093102 */
80d11f44 7247 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 7248#if 0
80d11f44 7249 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 7250#endif
7251 /* PowerPC 740/750 cores (aka G3) */
7252 /* XXX: missing 0x00084202 */
80d11f44 7253#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
bd928eba 7254 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 7255 CPU_POWERPC_7x0_v20 = 0x00080200,
7256 CPU_POWERPC_7x0_v21 = 0x00080201,
7257 CPU_POWERPC_7x0_v22 = 0x00080202,
7258 CPU_POWERPC_7x0_v30 = 0x00080300,
7259 CPU_POWERPC_7x0_v31 = 0x00080301,
7260 CPU_POWERPC_740E = 0x00080100,
bd928eba 7261 CPU_POWERPC_750E = 0x00080200,
80d11f44 7262 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 7263 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 7264#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7265 CPU_POWERPC_750CL_v10 = 0x00087200,
7266 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
80d11f44 7267#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
bd928eba
JM		 7268 CPU_POWERPC_750CX_v10 = 0x00082100,
7269 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 7270 CPU_POWERPC_750CX_v21 = 0x00082201,
7271 CPU_POWERPC_750CX_v22 = 0x00082202,
7272#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7273 CPU_POWERPC_750CXE_v21 = 0x00082211,
7274 CPU_POWERPC_750CXE_v22 = 0x00082212,
7275 CPU_POWERPC_750CXE_v23 = 0x00082213,
7276 CPU_POWERPC_750CXE_v24 = 0x00082214,
7277 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 7278 CPU_POWERPC_750CXE_v30 = 0x00082310,
7279 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 7280 CPU_POWERPC_750CXE_v31b = 0x00083311,
7281 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 7282 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 7283#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7284 CPU_POWERPC_750FX_v10 = 0x70000100,
7285 CPU_POWERPC_750FX_v20 = 0x70000200,
7286 CPU_POWERPC_750FX_v21 = 0x70000201,
7287 CPU_POWERPC_750FX_v22 = 0x70000202,
7288 CPU_POWERPC_750FX_v23 = 0x70000203,
7289 CPU_POWERPC_750GL = 0x70020102,
7290#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7291 CPU_POWERPC_750GX_v10 = 0x70020100,
7292 CPU_POWERPC_750GX_v11 = 0x70020101,
7293 CPU_POWERPC_750GX_v12 = 0x70020102,
7294#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
bd928eba
JM		 7295 CPU_POWERPC_750L_v20 = 0x00088200,
7296 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 7297 CPU_POWERPC_750L_v22 = 0x00088202,
7298 CPU_POWERPC_750L_v30 = 0x00088300,
7299 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 7300 /* PowerPC 745/755 cores */
80d11f44
JM		 7301#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7302 CPU_POWERPC_7x5_v10 = 0x00083100,
7303 CPU_POWERPC_7x5_v11 = 0x00083101,
7304 CPU_POWERPC_7x5_v20 = 0x00083200,
7305 CPU_POWERPC_7x5_v21 = 0x00083201,
7306 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7307 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7308 CPU_POWERPC_7x5_v24 = 0x00083204,
7309 CPU_POWERPC_7x5_v25 = 0x00083205,
7310 CPU_POWERPC_7x5_v26 = 0x00083206,
7311 CPU_POWERPC_7x5_v27 = 0x00083207,
7312 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 7313#if 0
80d11f44 7314 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 7315#endif
7316 /* PowerPC 74xx cores (aka G4) */
7317 /* XXX: missing 0x000C1101 */
80d11f44
JM		 7318#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7319 CPU_POWERPC_7400_v10 = 0x000C0100,
7320 CPU_POWERPC_7400_v11 = 0x000C0101,
7321 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 7322 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 7323 CPU_POWERPC_7400_v22 = 0x000C0202,
7324 CPU_POWERPC_7400_v26 = 0x000C0206,
7325 CPU_POWERPC_7400_v27 = 0x000C0207,
7326 CPU_POWERPC_7400_v28 = 0x000C0208,
7327 CPU_POWERPC_7400_v29 = 0x000C0209,
7328#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7329 CPU_POWERPC_7410_v10 = 0x800C1100,
7330 CPU_POWERPC_7410_v11 = 0x800C1101,
7331 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7332 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7333 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7334#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7335 CPU_POWERPC_7448_v10 = 0x80040100,
7336 CPU_POWERPC_7448_v11 = 0x80040101,
7337 CPU_POWERPC_7448_v20 = 0x80040200,
7338 CPU_POWERPC_7448_v21 = 0x80040201,
7339#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7340 CPU_POWERPC_7450_v10 = 0x80000100,
7341 CPU_POWERPC_7450_v11 = 0x80000101,
7342 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 7343 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 7344 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 7345#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7346 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7347 /* XXX: this entry might be a bug in some documentation */
7348 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44
JM		 7349#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7350 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 7351 /* XXX: missing 0x80010200 */
80d11f44
JM		 7352 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7353 CPU_POWERPC_74x5_v32 = 0x80010302,
7354 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7355 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7356#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 7357 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 7358 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 7359 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 7360#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7361 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7362 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7363 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 7364 /* 64 bits PowerPC */
00af685f 7365#if defined(TARGET_PPC64)
80d11f44
JM		 7366 CPU_POWERPC_620 = 0x00140000,
7367 CPU_POWERPC_630 = 0x00400000,
7368 CPU_POWERPC_631 = 0x00410104,
7369 CPU_POWERPC_POWER4 = 0x00350000,
7370 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 7371 /* XXX: missing 0x003A0201 */
80d11f44
JM		 7372 CPU_POWERPC_POWER5 = 0x003A0203,
7373#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7374 CPU_POWERPC_POWER5P = 0x003B0000,
7375#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7376 CPU_POWERPC_POWER6 = 0x003E0000,
7377 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7378 CPU_POWERPC_POWER6A = 0x0F000002,
9d52e907
DG		 7379#define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7380 CPU_POWERPC_POWER7_v20 = 0x003F0200,
37e305ce
DG		 7381 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7382 CPU_POWERPC_POWER7_v23 = 0x003F0203,
80d11f44
JM		 7383 CPU_POWERPC_970 = 0x00390202,
7384#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7385 CPU_POWERPC_970FX_v10 = 0x00391100,
7386 CPU_POWERPC_970FX_v20 = 0x003C0200,
7387 CPU_POWERPC_970FX_v21 = 0x003C0201,
7388 CPU_POWERPC_970FX_v30 = 0x003C0300,
7389 CPU_POWERPC_970FX_v31 = 0x003C0301,
7390 CPU_POWERPC_970GX = 0x00450000,
7391#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7392 CPU_POWERPC_970MP_v10 = 0x00440100,
7393 CPU_POWERPC_970MP_v11 = 0x00440101,
7394#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7395 CPU_POWERPC_CELL_v10 = 0x00700100,
7396 CPU_POWERPC_CELL_v20 = 0x00700400,
7397 CPU_POWERPC_CELL_v30 = 0x00700500,
7398 CPU_POWERPC_CELL_v31 = 0x00700501,
7399#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7400 CPU_POWERPC_RS64 = 0x00330000,
7401 CPU_POWERPC_RS64II = 0x00340000,
7402 CPU_POWERPC_RS64III = 0x00360000,
7403 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 7404#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 7405 /* Original POWER */
7406 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7407 * POWER2 (RIOS2) & RSC2 (P2SC) here
7408 */
7409#if 0
80d11f44 7410 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 7411#endif
7412#if 0
80d11f44 7413 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 7414#endif
7415 /* PA Semi core */
80d11f44 7416 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 7417};
7418
7419/* System version register (used on MPC 8xxx) */
7420enum {
80d11f44
JM		 7421 POWERPC_SVR_NONE = 0x00000000,
7422#define POWERPC_SVR_52xx POWERPC_SVR_5200
7423#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7424 POWERPC_SVR_5200_v10 = 0x80110010,
7425 POWERPC_SVR_5200_v11 = 0x80110011,
7426 POWERPC_SVR_5200_v12 = 0x80110012,
7427#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7428 POWERPC_SVR_5200B_v20 = 0x80110020,
7429 POWERPC_SVR_5200B_v21 = 0x80110021,
7430#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 7431#if 0
80d11f44 7432 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 7433#endif
7434#if 0
80d11f44 7435 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 7436#endif
7437#if 0
80d11f44 7438 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 7439#endif
7440#if 0
80d11f44 7441 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 7442#endif
7443#if 0
80d11f44 7444 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 7445#endif
7446#if 0
80d11f44 7447 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 7448#endif
7449#if 0
80d11f44 7450 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 7451#endif
7452#if 0
80d11f44 7453 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 7454#endif
7455#if 0
80d11f44 7456 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7457#endif
7458#if 0
80d11f44 7459 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7460#endif
7461#if 0
80d11f44 7462 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7463#endif
7464#if 0
80d11f44 7465 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7466#endif
7467#if 0
80d11f44 7468 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7469#endif
7470#if 0
80d11f44 7471 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7472#endif
7473#if 0
80d11f44 7474 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7475#endif
7476#if 0
80d11f44 7477 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7478#endif
7479#if 0
80d11f44 7480 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7481#endif
7482#if 0
80d11f44
JM		 7483 POWERPC_SVR_8323E = xxx,
7484#endif
492d7bf5 7485 POWERPC_SVR_8343 = 0x80570010,
80d11f44 7486 POWERPC_SVR_8343A = 0x80570030,
492d7bf5 7487 POWERPC_SVR_8343E = 0x80560010,
80d11f44 7488 POWERPC_SVR_8343EA = 0x80560030,
492d7bf5
TM		 7489#define POWERPC_SVR_8347 POWERPC_SVR_8347T
7490 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7491 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
80d11f44
JM		 7492#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7493 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7494 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
492d7bf5
TM		 7495#define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7496 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7497 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
80d11f44
JM		 7498#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7499 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7500 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7501 POWERPC_SVR_8349 = 0x80510010,
7502 POWERPC_SVR_8349A = 0x80510030,
7503 POWERPC_SVR_8349E = 0x80500010,
7504 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7505#if 0
80d11f44 7506 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7507#endif
7508#if 0
80d11f44
JM		 7509 POWERPC_SVR_8360E = xxx,
7510#endif
7511#define POWERPC_SVR_E500 0x40000000
7512 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7513 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7514 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7515 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7516 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7517 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7518#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7519 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7520 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7521#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7522 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7523 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7524#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7525 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7526 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7527 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7528#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7529 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7530 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7531#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7532 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7533 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7534#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7535 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7536 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7537 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7538 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7539#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7540 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7541 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7542 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7543 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7544#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7545 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7546 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7547#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7548 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7549 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7550#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7551 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7552 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7553#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7554 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7555 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7556#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7557 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7558 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7559#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7560 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7561 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7562 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7563 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7564#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7565 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7566 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7567 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7568 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7569#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7570 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7571 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7572#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7573 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7574 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7575#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7576 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7577 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7578 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7579 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7580 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7581 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7582 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7583 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7584 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7585#if 0
80d11f44 7586 POWERPC_SVR_8610 = xxx,
c3e36823 7587#endif
80d11f44
JM		 7588 POWERPC_SVR_8641 = 0x80900021,
7589 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7590};
7591
3fc6c082 7592/*****************************************************************************/
a750fc0b 7593/* PowerPC CPU definitions */
80d11f44 7594#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b 7595 { \
a5858d7a
AG		 7596 .name = _name, \
7597 .pvr = _pvr, \
7598 .svr = _svr, \
7599 .insns_flags = glue(POWERPC_INSNS_,_type), \
7600 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7601 .msr_mask = glue(POWERPC_MSRM_,_type), \
7602 .mmu_model = glue(POWERPC_MMU_,_type), \
7603 .excp_model = glue(POWERPC_EXCP_,_type), \
7604 .bus_model = glue(POWERPC_INPUT_,_type), \
7605 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7606 .flags = glue(POWERPC_FLAG_,_type), \
7607 .init_proc = &glue(init_proc_,_type), \
7608 .check_pow = &glue(check_pow_,_type), \
a750fc0b 7609 }
80d11f44
JM		 7610#define POWERPC_DEF(_name, _pvr, _type) \
7611POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7612
c227f099 7613static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 7614 /* Embedded PowerPC */
7615 /* PowerPC 401 family */
2662a059 7616 /* Generic PowerPC 401 */
80d11f44 7617 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 7618 /* PowerPC 401 cores */
2662a059 7619 /* PowerPC 401A1 */
80d11f44 7620 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 7621 /* PowerPC 401B2 */
80d11f44 7622 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 7623#if defined (TODO)
a750fc0b 7624 /* PowerPC 401B3 */
80d11f44 7625 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 7626#endif
7627 /* PowerPC 401C2 */
80d11f44 7628 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 7629 /* PowerPC 401D2 */
80d11f44 7630 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 7631 /* PowerPC 401E2 */
80d11f44 7632 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 7633 /* PowerPC 401F2 */
80d11f44 7634 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 7635 /* PowerPC 401G2 */
7636 /* XXX: to be checked */
80d11f44 7637 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 7638 /* PowerPC 401 microcontrolers */
2662a059 7639#if defined (TODO)
a750fc0b 7640 /* PowerPC 401GF */
80d11f44 7641 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 7642#endif
a750fc0b 7643 /* IOP480 (401 microcontroler) */
80d11f44 7644 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 7645 /* IBM Processor for Network Resources */
80d11f44 7646 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 7647#if defined (TODO)
80d11f44 7648 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 7649#endif
a750fc0b
JM		 7650 /* PowerPC 403 family */
7651 /* Generic PowerPC 403 */
80d11f44 7652 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 7653 /* PowerPC 403 microcontrolers */
7654 /* PowerPC 403 GA */
80d11f44 7655 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 7656 /* PowerPC 403 GB */
80d11f44 7657 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 7658 /* PowerPC 403 GC */
80d11f44 7659 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 7660 /* PowerPC 403 GCX */
80d11f44 7661 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 7662#if defined (TODO)
a750fc0b 7663 /* PowerPC 403 GP */
80d11f44 7664 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 7665#endif
a750fc0b
JM		 7666 /* PowerPC 405 family */
7667 /* Generic PowerPC 405 */
80d11f44 7668 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 7669 /* PowerPC 405 cores */
2662a059 7670#if defined (TODO)
a750fc0b 7671 /* PowerPC 405 A3 */
80d11f44 7672 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 7673#endif
3a607854 7674#if defined (TODO)
a750fc0b 7675 /* PowerPC 405 A4 */
80d11f44 7676 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 7677#endif
3a607854 7678#if defined (TODO)
a750fc0b 7679 /* PowerPC 405 B3 */
80d11f44 7680 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 7681#endif
7682#if defined (TODO)
a750fc0b 7683 /* PowerPC 405 B4 */
80d11f44 7684 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 7685#endif
7686#if defined (TODO)
7687 /* PowerPC 405 C3 */
80d11f44 7688 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 7689#endif
7690#if defined (TODO)
7691 /* PowerPC 405 C4 */
80d11f44 7692 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 7693#endif
7694 /* PowerPC 405 D2 */
80d11f44 7695 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 7696#if defined (TODO)
7697 /* PowerPC 405 D3 */
80d11f44 7698 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 7699#endif
7700 /* PowerPC 405 D4 */
80d11f44 7701 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 7702#if defined (TODO)
7703 /* PowerPC 405 D5 */
80d11f44 7704 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 7705#endif
7706#if defined (TODO)
7707 /* PowerPC 405 E4 */
80d11f44 7708 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 7709#endif
7710#if defined (TODO)
7711 /* PowerPC 405 F4 */
80d11f44 7712 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 7713#endif
7714#if defined (TODO)
7715 /* PowerPC 405 F5 */
80d11f44 7716 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 7717#endif
7718#if defined (TODO)
7719 /* PowerPC 405 F6 */
80d11f44 7720 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 7721#endif
7722 /* PowerPC 405 microcontrolers */
7723 /* PowerPC 405 CR */
80d11f44 7724 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 7725 /* PowerPC 405 CRa */
80d11f44 7726 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 7727 /* PowerPC 405 CRb */
80d11f44 7728 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 7729 /* PowerPC 405 CRc */
80d11f44 7730 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 7731 /* PowerPC 405 EP */
80d11f44 7732 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 7733#if defined(TODO)
7734 /* PowerPC 405 EXr */
80d11f44 7735 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 7736#endif
7737 /* PowerPC 405 EZ */
80d11f44 7738 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 7739#if defined(TODO)
7740 /* PowerPC 405 FX */
80d11f44 7741 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 7742#endif
7743 /* PowerPC 405 GP */
80d11f44 7744 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 7745 /* PowerPC 405 GPa */
80d11f44 7746 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 7747 /* PowerPC 405 GPb */
80d11f44 7748 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 7749 /* PowerPC 405 GPc */
80d11f44 7750 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 7751 /* PowerPC 405 GPd */
80d11f44 7752 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 7753 /* PowerPC 405 GPe */
80d11f44 7754 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 7755 /* PowerPC 405 GPR */
80d11f44 7756 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 7757#if defined(TODO)
7758 /* PowerPC 405 H */
80d11f44 7759 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 7760#endif
7761#if defined(TODO)
7762 /* PowerPC 405 L */
80d11f44 7763 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 7764#endif
7765 /* PowerPC 405 LP */
80d11f44 7766 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 7767#if defined(TODO)
7768 /* PowerPC 405 PM */
80d11f44 7769 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 7770#endif
7771#if defined(TODO)
7772 /* PowerPC 405 PS */
80d11f44 7773 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 7774#endif
7775#if defined(TODO)
7776 /* PowerPC 405 S */
80d11f44 7777 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 7778#endif
7779 /* Npe405 H */
80d11f44 7780 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 7781 /* Npe405 H2 */
80d11f44 7782 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 7783 /* Npe405 L */
80d11f44 7784 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 7785 /* Npe4GS3 */
80d11f44 7786 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 7787#if defined (TODO)
80d11f44 7788 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 7789#endif
7790#if defined (TODO)
80d11f44 7791 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 7792#endif
7793#if defined (TODO)
7794 /* PowerPC LC77700 (Sanyo) */
80d11f44 7795 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 7796#endif
7797 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7798#if defined (TODO)
7799 /* STB010000 */
80d11f44 7800 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 7801#endif
7802#if defined (TODO)
7803 /* STB01010 */
80d11f44 7804 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 7805#endif
7806#if defined (TODO)
7807 /* STB0210 */
80d11f44 7808 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 7809#endif
7810 /* STB03xx */
80d11f44 7811 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 7812#if defined (TODO)
7813 /* STB043x */
80d11f44 7814 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 7815#endif
7816#if defined (TODO)
7817 /* STB045x */
80d11f44 7818 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 7819#endif
7820 /* STB04xx */
80d11f44 7821 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 7822 /* STB25xx */
80d11f44 7823 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 7824#if defined (TODO)
7825 /* STB130 */
80d11f44 7826 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 7827#endif
7828 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 7829 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7830 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7831 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7832 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 7833#if defined (TODO)
7834 /* Zarlink ZL10310 */
80d11f44 7835 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 7836#endif
7837#if defined (TODO)
7838 /* Zarlink ZL10311 */
80d11f44 7839 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 7840#endif
7841#if defined (TODO)
7842 /* Zarlink ZL10320 */
80d11f44 7843 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 7844#endif
7845#if defined (TODO)
7846 /* Zarlink ZL10321 */
80d11f44 7847 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 7848#endif
7849 /* PowerPC 440 family */
80d11f44 7850#if defined(TODO_USER_ONLY)
a750fc0b 7851 /* Generic PowerPC 440 */
80d11f44
JM		 7852 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7853#endif
a750fc0b
JM		 7854 /* PowerPC 440 cores */
7855#if defined (TODO)
7856 /* PowerPC 440 A4 */
80d11f44 7857 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b 7858#endif
95070372
EI		 7859 /* PowerPC 440 Xilinx 5 */
7860 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
a750fc0b
JM		 7861#if defined (TODO)
7862 /* PowerPC 440 A5 */
80d11f44 7863 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 7864#endif
7865#if defined (TODO)
7866 /* PowerPC 440 B4 */
80d11f44 7867 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 7868#endif
7869#if defined (TODO)
7870 /* PowerPC 440 G4 */
80d11f44 7871 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 7872#endif
7873#if defined (TODO)
7874 /* PowerPC 440 F5 */
80d11f44 7875 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 7876#endif
7877#if defined (TODO)
7878 /* PowerPC 440 G5 */
80d11f44 7879 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 7880#endif
7881#if defined (TODO)
7882 /* PowerPC 440H4 */
80d11f44 7883 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 7884#endif
7885#if defined (TODO)
7886 /* PowerPC 440H6 */
80d11f44 7887 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 7888#endif
7889 /* PowerPC 440 microcontrolers */
7890 /* PowerPC 440 EP */
80d11f44 7891 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
a750fc0b 7892 /* PowerPC 440 EPa */
80d11f44 7893 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
a750fc0b 7894 /* PowerPC 440 EPb */
80d11f44 7895 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
a750fc0b 7896 /* PowerPC 440 EPX */
80d11f44 7897 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
80d11f44 7898#if defined(TODO_USER_ONLY)
a750fc0b 7899 /* PowerPC 440 GP */
80d11f44
JM		 7900 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7901#endif
7902#if defined(TODO_USER_ONLY)
a750fc0b 7903 /* PowerPC 440 GPb */
80d11f44
JM		 7904 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7905#endif
7906#if defined(TODO_USER_ONLY)
a750fc0b 7907 /* PowerPC 440 GPc */
80d11f44
JM		 7908 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7909#endif
7910#if defined(TODO_USER_ONLY)
a750fc0b 7911 /* PowerPC 440 GR */
80d11f44
JM		 7912 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7913#endif
7914#if defined(TODO_USER_ONLY)
a750fc0b 7915 /* PowerPC 440 GRa */
80d11f44
JM		 7916 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7917#endif
7918#if defined(TODO_USER_ONLY)
a750fc0b 7919 /* PowerPC 440 GRX */
80d11f44
JM		 7920 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7921#endif
7922#if defined(TODO_USER_ONLY)
a750fc0b 7923 /* PowerPC 440 GX */
80d11f44
JM		 7924 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7925#endif
7926#if defined(TODO_USER_ONLY)
a750fc0b 7927 /* PowerPC 440 GXa */
80d11f44
JM		 7928 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7929#endif
7930#if defined(TODO_USER_ONLY)
a750fc0b 7931 /* PowerPC 440 GXb */
80d11f44
JM		 7932 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7933#endif
7934#if defined(TODO_USER_ONLY)
a750fc0b 7935 /* PowerPC 440 GXc */
80d11f44
JM		 7936 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7937#endif
7938#if defined(TODO_USER_ONLY)
a750fc0b 7939 /* PowerPC 440 GXf */
80d11f44
JM		 7940 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7941#endif
a750fc0b
JM		 7942#if defined(TODO)
7943 /* PowerPC 440 S */
80d11f44 7944 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 7945#endif
80d11f44 7946#if defined(TODO_USER_ONLY)
a750fc0b 7947 /* PowerPC 440 SP */
80d11f44
JM		 7948 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7949#endif
7950#if defined(TODO_USER_ONLY)
a750fc0b 7951 /* PowerPC 440 SP2 */
80d11f44
JM		 7952 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7953#endif
7954#if defined(TODO_USER_ONLY)
a750fc0b 7955 /* PowerPC 440 SPE */
80d11f44
JM		 7956 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7957#endif
a750fc0b
JM		 7958 /* PowerPC 460 family */
7959#if defined (TODO)
7960 /* Generic PowerPC 464 */
80d11f44 7961 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 7962#endif
7963 /* PowerPC 464 microcontrolers */
7964#if defined (TODO)
7965 /* PowerPC 464H90 */
80d11f44 7966 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 7967#endif
7968#if defined (TODO)
7969 /* PowerPC 464H90F */
80d11f44 7970 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 7971#endif
7972 /* Freescale embedded PowerPC cores */
80d11f44
JM		 7973 /* MPC5xx family (aka RCPU) */
7974#if defined(TODO_USER_ONLY)
7975 /* Generic MPC5xx core */
7976 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7977#endif
7978#if defined(TODO_USER_ONLY)
7979 /* Codename for MPC5xx core */
7980 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7981#endif
7982 /* MPC5xx microcontrollers */
7983#if defined(TODO_USER_ONLY)
7984 /* MGT560 */
7985 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7986#endif
7987#if defined(TODO_USER_ONLY)
7988 /* MPC509 */
7989 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7990#endif
7991#if defined(TODO_USER_ONLY)
7992 /* MPC533 */
7993 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7994#endif
7995#if defined(TODO_USER_ONLY)
7996 /* MPC534 */
7997 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7998#endif
7999#if defined(TODO_USER_ONLY)
8000 /* MPC555 */
8001 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
8002#endif
8003#if defined(TODO_USER_ONLY)
8004 /* MPC556 */
8005 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
8006#endif
8007#if defined(TODO_USER_ONLY)
8008 /* MPC560 */
8009 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
8010#endif
8011#if defined(TODO_USER_ONLY)
8012 /* MPC561 */
8013 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
8014#endif
8015#if defined(TODO_USER_ONLY)
8016 /* MPC562 */
8017 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
8018#endif
8019#if defined(TODO_USER_ONLY)
8020 /* MPC563 */
8021 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
8022#endif
8023#if defined(TODO_USER_ONLY)
8024 /* MPC564 */
8025 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
8026#endif
8027#if defined(TODO_USER_ONLY)
8028 /* MPC565 */
8029 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
8030#endif
8031#if defined(TODO_USER_ONLY)
8032 /* MPC566 */
8033 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
8034#endif
8035 /* MPC8xx family (aka PowerQUICC) */
8036#if defined(TODO_USER_ONLY)
8037 /* Generic MPC8xx core */
8038 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
8039#endif
8040#if defined(TODO_USER_ONLY)
8041 /* Codename for MPC8xx core */
8042 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8043#endif
8044 /* MPC8xx microcontrollers */
8045#if defined(TODO_USER_ONLY)
8046 /* MGT823 */
8047 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8048#endif
8049#if defined(TODO_USER_ONLY)
8050 /* MPC821 */
8051 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8052#endif
8053#if defined(TODO_USER_ONLY)
8054 /* MPC823 */
8055 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8056#endif
8057#if defined(TODO_USER_ONLY)
8058 /* MPC850 */
8059 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8060#endif
8061#if defined(TODO_USER_ONLY)
8062 /* MPC852T */
8063 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8064#endif
8065#if defined(TODO_USER_ONLY)
8066 /* MPC855T */
8067 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8068#endif
8069#if defined(TODO_USER_ONLY)
8070 /* MPC857 */
8071 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8072#endif
8073#if defined(TODO_USER_ONLY)
8074 /* MPC859 */
8075 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8076#endif
8077#if defined(TODO_USER_ONLY)
8078 /* MPC860 */
8079 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8080#endif
8081#if defined(TODO_USER_ONLY)
8082 /* MPC862 */
8083 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8084#endif
8085#if defined(TODO_USER_ONLY)
8086 /* MPC866 */
8087 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8088#endif
8089#if defined(TODO_USER_ONLY)
8090 /* MPC870 */
8091 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8092#endif
8093#if defined(TODO_USER_ONLY)
8094 /* MPC875 */
8095 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8096#endif
8097#if defined(TODO_USER_ONLY)
8098 /* MPC880 */
8099 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8100#endif
8101#if defined(TODO_USER_ONLY)
8102 /* MPC885 */
8103 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8104#endif
8105 /* MPC82xx family (aka PowerQUICC-II) */
8106 /* Generic MPC52xx core */
8107 POWERPC_DEF_SVR("MPC52xx",
8108 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8109 /* Generic MPC82xx core */
8110 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8111 /* Codename for MPC82xx */
8112 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8113 /* PowerPC G2 core */
8114 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8115 /* PowerPC G2 H4 core */
8116 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8117 /* PowerPC G2 GP core */
8118 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8119 /* PowerPC G2 LS core */
8120 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8121 /* PowerPC G2 HiP3 core */
8122 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8123 /* PowerPC G2 HiP4 core */
8124 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8125 /* PowerPC MPC603 core */
8126 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8127 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8128 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8129 /* PowerPC G2LE GP core */
8130 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8131 /* PowerPC G2LE LS core */
8132 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8133 /* PowerPC G2LE GP1 core */
8134 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8135 /* PowerPC G2LE GP3 core */
8136 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8137 /* PowerPC MPC603 microcontrollers */
8138 /* MPC8240 */
8139 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8140 /* PowerPC G2 microcontrollers */
082c6681 8141#if defined(TODO)
80d11f44
JM		 8142 /* MPC5121 */
8143 POWERPC_DEF_SVR("MPC5121",
8144 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8145#endif
8146 /* MPC5200 */
8147 POWERPC_DEF_SVR("MPC5200",
8148 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8149 /* MPC5200 v1.0 */
8150 POWERPC_DEF_SVR("MPC5200_v10",
8151 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8152 /* MPC5200 v1.1 */
8153 POWERPC_DEF_SVR("MPC5200_v11",
8154 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8155 /* MPC5200 v1.2 */
8156 POWERPC_DEF_SVR("MPC5200_v12",
8157 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8158 /* MPC5200B */
8159 POWERPC_DEF_SVR("MPC5200B",
8160 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8161 /* MPC5200B v2.0 */
8162 POWERPC_DEF_SVR("MPC5200B_v20",
8163 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8164 /* MPC5200B v2.1 */
8165 POWERPC_DEF_SVR("MPC5200B_v21",
8166 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8167 /* MPC8241 */
8168 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8169 /* MPC8245 */
8170 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8171 /* MPC8247 */
8172 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8173 /* MPC8248 */
8174 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8175 /* MPC8250 */
8176 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8177 /* MPC8250 HiP3 */
8178 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8179 /* MPC8250 HiP4 */
8180 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8181 /* MPC8255 */
8182 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8183 /* MPC8255 HiP3 */
8184 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8185 /* MPC8255 HiP4 */
8186 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8187 /* MPC8260 */
8188 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8189 /* MPC8260 HiP3 */
8190 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8191 /* MPC8260 HiP4 */
8192 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8193 /* MPC8264 */
8194 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8195 /* MPC8264 HiP3 */
8196 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8197 /* MPC8264 HiP4 */
8198 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8199 /* MPC8265 */
8200 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8201 /* MPC8265 HiP3 */
8202 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8203 /* MPC8265 HiP4 */
8204 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8205 /* MPC8266 */
8206 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8207 /* MPC8266 HiP3 */
8208 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8209 /* MPC8266 HiP4 */
8210 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8211 /* MPC8270 */
8212 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8213 /* MPC8271 */
8214 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8215 /* MPC8272 */
8216 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8217 /* MPC8275 */
8218 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8219 /* MPC8280 */
8220 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 8221 /* e200 family */
a750fc0b 8222 /* Generic PowerPC e200 core */
80d11f44
JM		 8223 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8224 /* Generic MPC55xx core */
8225#if defined (TODO)
8226 POWERPC_DEF_SVR("MPC55xx",
8227 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 8228#endif
8229#if defined (TODO)
80d11f44
JM		 8230 /* PowerPC e200z0 core */
8231 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 8232#endif
8233#if defined (TODO)
80d11f44
JM		 8234 /* PowerPC e200z1 core */
8235 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8236#endif
8237#if defined (TODO)
8238 /* PowerPC e200z3 core */
8239 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8240#endif
8241 /* PowerPC e200z5 core */
8242 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 8243 /* PowerPC e200z6 core */
80d11f44
JM		 8244 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8245 /* PowerPC e200 microcontrollers */
8246#if defined (TODO)
8247 /* MPC5514E */
8248 POWERPC_DEF_SVR("MPC5514E",
8249 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 8250#endif
a750fc0b 8251#if defined (TODO)
80d11f44
JM		 8252 /* MPC5514E v0 */
8253 POWERPC_DEF_SVR("MPC5514E_v0",
8254 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 8255#endif
8256#if defined (TODO)
80d11f44
JM		 8257 /* MPC5514E v1 */
8258 POWERPC_DEF_SVR("MPC5514E_v1",
8259 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 8260#endif
8261#if defined (TODO)
80d11f44
JM		 8262 /* MPC5514G */
8263 POWERPC_DEF_SVR("MPC5514G",
8264 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 8265#endif
8266#if defined (TODO)
80d11f44
JM		 8267 /* MPC5514G v0 */
8268 POWERPC_DEF_SVR("MPC5514G_v0",
8269 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 8270#endif
a750fc0b 8271#if defined (TODO)
80d11f44
JM		 8272 /* MPC5514G v1 */
8273 POWERPC_DEF_SVR("MPC5514G_v1",
8274 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 8275#endif
8276#if defined (TODO)
80d11f44
JM		 8277 /* MPC5515S */
8278 POWERPC_DEF_SVR("MPC5515S",
8279 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 8280#endif
8281#if defined (TODO)
80d11f44
JM		 8282 /* MPC5516E */
8283 POWERPC_DEF_SVR("MPC5516E",
8284 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 8285#endif
8286#if defined (TODO)
80d11f44
JM		 8287 /* MPC5516E v0 */
8288 POWERPC_DEF_SVR("MPC5516E_v0",
8289 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 8290#endif
8291#if defined (TODO)
80d11f44
JM		 8292 /* MPC5516E v1 */
8293 POWERPC_DEF_SVR("MPC5516E_v1",
8294 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 8295#endif
a750fc0b 8296#if defined (TODO)
80d11f44
JM		 8297 /* MPC5516G */
8298 POWERPC_DEF_SVR("MPC5516G",
8299 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 8300#endif
a750fc0b 8301#if defined (TODO)
80d11f44
JM		 8302 /* MPC5516G v0 */
8303 POWERPC_DEF_SVR("MPC5516G_v0",
8304 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 8305#endif
a750fc0b 8306#if defined (TODO)
80d11f44
JM		 8307 /* MPC5516G v1 */
8308 POWERPC_DEF_SVR("MPC5516G_v1",
8309 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 8310#endif
a750fc0b 8311#if defined (TODO)
80d11f44
JM		 8312 /* MPC5516S */
8313 POWERPC_DEF_SVR("MPC5516S",
8314 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 8315#endif
8316#if defined (TODO)
80d11f44
JM		 8317 /* MPC5533 */
8318 POWERPC_DEF_SVR("MPC5533",
8319 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 8320#endif
8321#if defined (TODO)
80d11f44
JM		 8322 /* MPC5534 */
8323 POWERPC_DEF_SVR("MPC5534",
8324 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 8325#endif
80d11f44
JM		 8326#if defined (TODO)
8327 /* MPC5553 */
8328 POWERPC_DEF_SVR("MPC5553",
8329 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8330#endif
8331#if defined (TODO)
8332 /* MPC5554 */
8333 POWERPC_DEF_SVR("MPC5554",
8334 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8335#endif
8336#if defined (TODO)
8337 /* MPC5561 */
8338 POWERPC_DEF_SVR("MPC5561",
8339 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8340#endif
8341#if defined (TODO)
8342 /* MPC5565 */
8343 POWERPC_DEF_SVR("MPC5565",
8344 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8345#endif
8346#if defined (TODO)
8347 /* MPC5566 */
8348 POWERPC_DEF_SVR("MPC5566",
8349 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8350#endif
8351#if defined (TODO)
8352 /* MPC5567 */
8353 POWERPC_DEF_SVR("MPC5567",
8354 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8355#endif
8356 /* e300 family */
8357 /* Generic PowerPC e300 core */
8358 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8359 /* PowerPC e300c1 core */
8360 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8361 /* PowerPC e300c2 core */
8362 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8363 /* PowerPC e300c3 core */
8364 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8365 /* PowerPC e300c4 core */
8366 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8367 /* PowerPC e300 microcontrollers */
8368#if defined (TODO)
8369 /* MPC8313 */
8370 POWERPC_DEF_SVR("MPC8313",
74d77cae 8371 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
80d11f44
JM		 8372#endif
8373#if defined (TODO)
8374 /* MPC8313E */
8375 POWERPC_DEF_SVR("MPC8313E",
74d77cae 8376 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
80d11f44
JM		 8377#endif
8378#if defined (TODO)
8379 /* MPC8314 */
8380 POWERPC_DEF_SVR("MPC8314",
74d77cae 8381 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
80d11f44
JM		 8382#endif
8383#if defined (TODO)
8384 /* MPC8314E */
8385 POWERPC_DEF_SVR("MPC8314E",
74d77cae 8386 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
80d11f44
JM		 8387#endif
8388#if defined (TODO)
8389 /* MPC8315 */
8390 POWERPC_DEF_SVR("MPC8315",
74d77cae 8391 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
80d11f44
JM		 8392#endif
8393#if defined (TODO)
8394 /* MPC8315E */
8395 POWERPC_DEF_SVR("MPC8315E",
74d77cae 8396 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
80d11f44
JM		 8397#endif
8398#if defined (TODO)
8399 /* MPC8321 */
8400 POWERPC_DEF_SVR("MPC8321",
74d77cae 8401 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
80d11f44
JM		 8402#endif
8403#if defined (TODO)
8404 /* MPC8321E */
8405 POWERPC_DEF_SVR("MPC8321E",
74d77cae 8406 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
80d11f44
JM		 8407#endif
8408#if defined (TODO)
8409 /* MPC8323 */
8410 POWERPC_DEF_SVR("MPC8323",
74d77cae 8411 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
80d11f44
JM		 8412#endif
8413#if defined (TODO)
8414 /* MPC8323E */
8415 POWERPC_DEF_SVR("MPC8323E",
74d77cae 8416 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
80d11f44 8417#endif
492d7bf5
TM		 8418 /* MPC8343 */
8419 POWERPC_DEF_SVR("MPC8343",
74d77cae 8420 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
80d11f44
JM		 8421 /* MPC8343A */
8422 POWERPC_DEF_SVR("MPC8343A",
74d77cae 8423 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
492d7bf5
TM		 8424 /* MPC8343E */
8425 POWERPC_DEF_SVR("MPC8343E",
74d77cae 8426 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
80d11f44
JM		 8427 /* MPC8343EA */
8428 POWERPC_DEF_SVR("MPC8343EA",
74d77cae 8429 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
492d7bf5
TM		 8430 /* MPC8347 */
8431 POWERPC_DEF_SVR("MPC8347",
74d77cae 8432 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
492d7bf5
TM		 8433 /* MPC8347T */
8434 POWERPC_DEF_SVR("MPC8347T",
74d77cae 8435 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
492d7bf5
TM		 8436 /* MPC8347P */
8437 POWERPC_DEF_SVR("MPC8347P",
74d77cae 8438 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
80d11f44
JM		 8439 /* MPC8347A */
8440 POWERPC_DEF_SVR("MPC8347A",
74d77cae 8441 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
80d11f44
JM		 8442 /* MPC8347AT */
8443 POWERPC_DEF_SVR("MPC8347AT",
74d77cae 8444 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
80d11f44
JM		 8445 /* MPC8347AP */
8446 POWERPC_DEF_SVR("MPC8347AP",
74d77cae 8447 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
492d7bf5
TM		 8448 /* MPC8347E */
8449 POWERPC_DEF_SVR("MPC8347E",
74d77cae 8450 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
492d7bf5
TM		 8451 /* MPC8347ET */
8452 POWERPC_DEF_SVR("MPC8347ET",
74d77cae 8453 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
492d7bf5
TM		 8454 /* MPC8343EP */
8455 POWERPC_DEF_SVR("MPC8347EP",
74d77cae 8456 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
80d11f44
JM		 8457 /* MPC8347EA */
8458 POWERPC_DEF_SVR("MPC8347EA",
74d77cae 8459 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
80d11f44
JM		 8460 /* MPC8347EAT */
8461 POWERPC_DEF_SVR("MPC8347EAT",
74d77cae 8462 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
80d11f44
JM		 8463 /* MPC8343EAP */
8464 POWERPC_DEF_SVR("MPC8347EAP",
74d77cae 8465 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
80d11f44
JM		 8466 /* MPC8349 */
8467 POWERPC_DEF_SVR("MPC8349",
74d77cae 8468 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
80d11f44
JM		 8469 /* MPC8349A */
8470 POWERPC_DEF_SVR("MPC8349A",
74d77cae 8471 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
80d11f44
JM		 8472 /* MPC8349E */
8473 POWERPC_DEF_SVR("MPC8349E",
74d77cae 8474 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
80d11f44
JM		 8475 /* MPC8349EA */
8476 POWERPC_DEF_SVR("MPC8349EA",
74d77cae 8477 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
80d11f44
JM		 8478#if defined (TODO)
8479 /* MPC8358E */
8480 POWERPC_DEF_SVR("MPC8358E",
74d77cae 8481 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
80d11f44
JM		 8482#endif
8483#if defined (TODO)
8484 /* MPC8360E */
8485 POWERPC_DEF_SVR("MPC8360E",
74d77cae 8486 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
80d11f44
JM		 8487#endif
8488 /* MPC8377 */
8489 POWERPC_DEF_SVR("MPC8377",
74d77cae 8490 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
80d11f44
JM		 8491 /* MPC8377E */
8492 POWERPC_DEF_SVR("MPC8377E",
74d77cae 8493 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
80d11f44
JM		 8494 /* MPC8378 */
8495 POWERPC_DEF_SVR("MPC8378",
74d77cae 8496 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
80d11f44
JM		 8497 /* MPC8378E */
8498 POWERPC_DEF_SVR("MPC8378E",
74d77cae 8499 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
80d11f44
JM		 8500 /* MPC8379 */
8501 POWERPC_DEF_SVR("MPC8379",
74d77cae 8502 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
80d11f44
JM		 8503 /* MPC8379E */
8504 POWERPC_DEF_SVR("MPC8379E",
74d77cae 8505 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
80d11f44
JM		 8506 /* e500 family */
8507 /* PowerPC e500 core */
bd5ea513
AJ		 8508 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8509 /* PowerPC e500v1 core */
8510 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
80d11f44 8511 /* PowerPC e500 v1.0 core */
bd5ea513 8512 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
80d11f44 8513 /* PowerPC e500 v2.0 core */
bd5ea513 8514 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
80d11f44 8515 /* PowerPC e500v2 core */
bd5ea513 8516 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
80d11f44 8517 /* PowerPC e500v2 v1.0 core */
bd5ea513 8518 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
80d11f44 8519 /* PowerPC e500v2 v2.0 core */
bd5ea513 8520 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
80d11f44 8521 /* PowerPC e500v2 v2.1 core */
bd5ea513 8522 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
80d11f44 8523 /* PowerPC e500v2 v2.2 core */
bd5ea513 8524 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
80d11f44 8525 /* PowerPC e500v2 v3.0 core */
bd5ea513 8526 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
f7aa5583 8527 POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
80d11f44
JM		 8528 /* PowerPC e500 microcontrollers */
8529 /* MPC8533 */
8530 POWERPC_DEF_SVR("MPC8533",
bd5ea513 8531 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
80d11f44
JM		 8532 /* MPC8533 v1.0 */
8533 POWERPC_DEF_SVR("MPC8533_v10",
bd5ea513 8534 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
80d11f44
JM		 8535 /* MPC8533 v1.1 */
8536 POWERPC_DEF_SVR("MPC8533_v11",
bd5ea513 8537 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
80d11f44
JM		 8538 /* MPC8533E */
8539 POWERPC_DEF_SVR("MPC8533E",
bd5ea513 8540 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
80d11f44
JM		 8541 /* MPC8533E v1.0 */
8542 POWERPC_DEF_SVR("MPC8533E_v10",
bd5ea513 8543 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
80d11f44 8544 POWERPC_DEF_SVR("MPC8533E_v11",
bd5ea513 8545 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
80d11f44
JM		 8546 /* MPC8540 */
8547 POWERPC_DEF_SVR("MPC8540",
bd5ea513 8548 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
80d11f44
JM		 8549 /* MPC8540 v1.0 */
8550 POWERPC_DEF_SVR("MPC8540_v10",
bd5ea513 8551 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
80d11f44
JM		 8552 /* MPC8540 v2.0 */
8553 POWERPC_DEF_SVR("MPC8540_v20",
bd5ea513 8554 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
80d11f44
JM		 8555 /* MPC8540 v2.1 */
8556 POWERPC_DEF_SVR("MPC8540_v21",
bd5ea513 8557 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
80d11f44
JM		 8558 /* MPC8541 */
8559 POWERPC_DEF_SVR("MPC8541",
bd5ea513 8560 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
80d11f44
JM		 8561 /* MPC8541 v1.0 */
8562 POWERPC_DEF_SVR("MPC8541_v10",
bd5ea513 8563 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
80d11f44
JM		 8564 /* MPC8541 v1.1 */
8565 POWERPC_DEF_SVR("MPC8541_v11",
bd5ea513 8566 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
80d11f44
JM		 8567 /* MPC8541E */
8568 POWERPC_DEF_SVR("MPC8541E",
bd5ea513 8569 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
80d11f44
JM		 8570 /* MPC8541E v1.0 */
8571 POWERPC_DEF_SVR("MPC8541E_v10",
bd5ea513 8572 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
80d11f44
JM		 8573 /* MPC8541E v1.1 */
8574 POWERPC_DEF_SVR("MPC8541E_v11",
bd5ea513 8575 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
80d11f44
JM		 8576 /* MPC8543 */
8577 POWERPC_DEF_SVR("MPC8543",
bd5ea513 8578 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
80d11f44
JM		 8579 /* MPC8543 v1.0 */
8580 POWERPC_DEF_SVR("MPC8543_v10",
bd5ea513 8581 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
80d11f44
JM		 8582 /* MPC8543 v1.1 */
8583 POWERPC_DEF_SVR("MPC8543_v11",
bd5ea513 8584 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
80d11f44
JM		 8585 /* MPC8543 v2.0 */
8586 POWERPC_DEF_SVR("MPC8543_v20",
bd5ea513 8587 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
80d11f44
JM		 8588 /* MPC8543 v2.1 */
8589 POWERPC_DEF_SVR("MPC8543_v21",
bd5ea513 8590 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
80d11f44
JM		 8591 /* MPC8543E */
8592 POWERPC_DEF_SVR("MPC8543E",
bd5ea513 8593 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
80d11f44
JM		 8594 /* MPC8543E v1.0 */
8595 POWERPC_DEF_SVR("MPC8543E_v10",
bd5ea513 8596 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
80d11f44
JM		 8597 /* MPC8543E v1.1 */
8598 POWERPC_DEF_SVR("MPC8543E_v11",
bd5ea513 8599 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
80d11f44
JM		 8600 /* MPC8543E v2.0 */
8601 POWERPC_DEF_SVR("MPC8543E_v20",
bd5ea513 8602 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
80d11f44
JM		 8603 /* MPC8543E v2.1 */
8604 POWERPC_DEF_SVR("MPC8543E_v21",
bd5ea513 8605 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
80d11f44
JM		 8606 /* MPC8544 */
8607 POWERPC_DEF_SVR("MPC8544",
bd5ea513 8608 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
80d11f44
JM		 8609 /* MPC8544 v1.0 */
8610 POWERPC_DEF_SVR("MPC8544_v10",
bd5ea513 8611 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
80d11f44
JM		 8612 /* MPC8544 v1.1 */
8613 POWERPC_DEF_SVR("MPC8544_v11",
bd5ea513 8614 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
80d11f44
JM		 8615 /* MPC8544E */
8616 POWERPC_DEF_SVR("MPC8544E",
bd5ea513 8617 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
80d11f44
JM		 8618 /* MPC8544E v1.0 */
8619 POWERPC_DEF_SVR("MPC8544E_v10",
bd5ea513 8620 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
80d11f44
JM		 8621 /* MPC8544E v1.1 */
8622 POWERPC_DEF_SVR("MPC8544E_v11",
bd5ea513 8623 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
80d11f44
JM		 8624 /* MPC8545 */
8625 POWERPC_DEF_SVR("MPC8545",
bd5ea513 8626 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
80d11f44
JM		 8627 /* MPC8545 v2.0 */
8628 POWERPC_DEF_SVR("MPC8545_v20",
bd5ea513 8629 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
80d11f44
JM		 8630 /* MPC8545 v2.1 */
8631 POWERPC_DEF_SVR("MPC8545_v21",
bd5ea513 8632 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
80d11f44
JM		 8633 /* MPC8545E */
8634 POWERPC_DEF_SVR("MPC8545E",
bd5ea513 8635 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
80d11f44
JM		 8636 /* MPC8545E v2.0 */
8637 POWERPC_DEF_SVR("MPC8545E_v20",
bd5ea513 8638 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
80d11f44
JM		 8639 /* MPC8545E v2.1 */
8640 POWERPC_DEF_SVR("MPC8545E_v21",
bd5ea513 8641 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
80d11f44
JM		 8642 /* MPC8547E */
8643 POWERPC_DEF_SVR("MPC8547E",
bd5ea513 8644 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
80d11f44
JM		 8645 /* MPC8547E v2.0 */
8646 POWERPC_DEF_SVR("MPC8547E_v20",
bd5ea513 8647 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
80d11f44
JM		 8648 /* MPC8547E v2.1 */
8649 POWERPC_DEF_SVR("MPC8547E_v21",
bd5ea513 8650 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
80d11f44
JM		 8651 /* MPC8548 */
8652 POWERPC_DEF_SVR("MPC8548",
bd5ea513 8653 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
80d11f44
JM		 8654 /* MPC8548 v1.0 */
8655 POWERPC_DEF_SVR("MPC8548_v10",
bd5ea513 8656 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
80d11f44
JM		 8657 /* MPC8548 v1.1 */
8658 POWERPC_DEF_SVR("MPC8548_v11",
bd5ea513 8659 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
80d11f44
JM		 8660 /* MPC8548 v2.0 */
8661 POWERPC_DEF_SVR("MPC8548_v20",
bd5ea513 8662 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
80d11f44
JM		 8663 /* MPC8548 v2.1 */
8664 POWERPC_DEF_SVR("MPC8548_v21",
bd5ea513 8665 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
80d11f44
JM		 8666 /* MPC8548E */
8667 POWERPC_DEF_SVR("MPC8548E",
bd5ea513 8668 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
80d11f44
JM		 8669 /* MPC8548E v1.0 */
8670 POWERPC_DEF_SVR("MPC8548E_v10",
bd5ea513 8671 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
80d11f44
JM		 8672 /* MPC8548E v1.1 */
8673 POWERPC_DEF_SVR("MPC8548E_v11",
bd5ea513 8674 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
80d11f44
JM		 8675 /* MPC8548E v2.0 */
8676 POWERPC_DEF_SVR("MPC8548E_v20",
bd5ea513 8677 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
80d11f44
JM		 8678 /* MPC8548E v2.1 */
8679 POWERPC_DEF_SVR("MPC8548E_v21",
bd5ea513 8680 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
80d11f44
JM		 8681 /* MPC8555 */
8682 POWERPC_DEF_SVR("MPC8555",
bd5ea513 8683 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
80d11f44
JM		 8684 /* MPC8555 v1.0 */
8685 POWERPC_DEF_SVR("MPC8555_v10",
bd5ea513 8686 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
80d11f44
JM		 8687 /* MPC8555 v1.1 */
8688 POWERPC_DEF_SVR("MPC8555_v11",
bd5ea513 8689 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
80d11f44
JM		 8690 /* MPC8555E */
8691 POWERPC_DEF_SVR("MPC8555E",
bd5ea513 8692 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
80d11f44
JM		 8693 /* MPC8555E v1.0 */
8694 POWERPC_DEF_SVR("MPC8555E_v10",
bd5ea513 8695 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
80d11f44
JM		 8696 /* MPC8555E v1.1 */
8697 POWERPC_DEF_SVR("MPC8555E_v11",
bd5ea513 8698 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
80d11f44
JM		 8699 /* MPC8560 */
8700 POWERPC_DEF_SVR("MPC8560",
bd5ea513 8701 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
80d11f44
JM		 8702 /* MPC8560 v1.0 */
8703 POWERPC_DEF_SVR("MPC8560_v10",
bd5ea513 8704 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
80d11f44
JM		 8705 /* MPC8560 v2.0 */
8706 POWERPC_DEF_SVR("MPC8560_v20",
bd5ea513 8707 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
80d11f44
JM		 8708 /* MPC8560 v2.1 */
8709 POWERPC_DEF_SVR("MPC8560_v21",
bd5ea513 8710 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
80d11f44
JM		 8711 /* MPC8567 */
8712 POWERPC_DEF_SVR("MPC8567",
bd5ea513 8713 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
80d11f44
JM		 8714 /* MPC8567E */
8715 POWERPC_DEF_SVR("MPC8567E",
bd5ea513 8716 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
80d11f44
JM		 8717 /* MPC8568 */
8718 POWERPC_DEF_SVR("MPC8568",
bd5ea513 8719 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
80d11f44
JM		 8720 /* MPC8568E */
8721 POWERPC_DEF_SVR("MPC8568E",
bd5ea513 8722 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
80d11f44
JM		 8723 /* MPC8572 */
8724 POWERPC_DEF_SVR("MPC8572",
bd5ea513 8725 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
80d11f44
JM		 8726 /* MPC8572E */
8727 POWERPC_DEF_SVR("MPC8572E",
bd5ea513 8728 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
80d11f44
JM		 8729 /* e600 family */
8730 /* PowerPC e600 core */
8731 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8732 /* PowerPC e600 microcontrollers */
8733#if defined (TODO)
8734 /* MPC8610 */
8735 POWERPC_DEF_SVR("MPC8610",
8736 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8737#endif
8738 /* MPC8641 */
8739 POWERPC_DEF_SVR("MPC8641",
8740 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8741 /* MPC8641D */
8742 POWERPC_DEF_SVR("MPC8641D",
8743 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 8744 /* 32 bits "classic" PowerPC */
8745 /* PowerPC 6xx family */
8746 /* PowerPC 601 */
bd928eba 8747 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
c3e36823 8748 /* PowerPC 601v0 */
082c6681 8749 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 8750 /* PowerPC 601v1 */
082c6681
JM		 8751 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8752 /* PowerPC 601v */
bd928eba 8753 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
a750fc0b 8754 /* PowerPC 601v2 */
082c6681 8755 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 8756 /* PowerPC 602 */
80d11f44 8757 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 8758 /* PowerPC 603 */
80d11f44 8759 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 8760 /* Code name for PowerPC 603 */
80d11f44 8761 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 8762 /* PowerPC 603e (aka PID6) */
80d11f44 8763 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 8764 /* Code name for PowerPC 603e */
80d11f44 8765 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 8766 /* PowerPC 603e v1.1 */
80d11f44 8767 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 8768 /* PowerPC 603e v1.2 */
80d11f44 8769 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 8770 /* PowerPC 603e v1.3 */
80d11f44 8771 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 8772 /* PowerPC 603e v1.4 */
80d11f44 8773 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 8774 /* PowerPC 603e v2.2 */
80d11f44 8775 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 8776 /* PowerPC 603e v3 */
80d11f44 8777 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 8778 /* PowerPC 603e v4 */
80d11f44 8779 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 8780 /* PowerPC 603e v4.1 */
80d11f44 8781 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 8782 /* PowerPC 603e (aka PID7) */
80d11f44 8783 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 8784 /* PowerPC 603e7t */
80d11f44 8785 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 8786 /* PowerPC 603e7v */
80d11f44 8787 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 8788 /* Code name for PowerPC 603ev */
80d11f44 8789 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 8790 /* PowerPC 603e7v1 */
80d11f44 8791 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 8792 /* PowerPC 603e7v2 */
80d11f44 8793 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 8794 /* PowerPC 603p (aka PID7v) */
8795 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8796 /* PowerPC 603r (aka PID7t) */
80d11f44 8797 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 8798 /* Code name for PowerPC 603r */
80d11f44 8799 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 8800 /* PowerPC 604 */
80d11f44 8801 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 8802 /* PowerPC 604e (aka PID9) */
8803 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8804 /* Code name for PowerPC 604e */
8805 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 8806 /* PowerPC 604e v1.0 */
082c6681 8807 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 8808 /* PowerPC 604e v2.2 */
082c6681 8809 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 8810 /* PowerPC 604e v2.4 */
082c6681
JM		 8811 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8812 /* PowerPC 604r (aka PIDA) */
8813 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8814 /* Code name for PowerPC 604r */
8815 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 8816#if defined(TODO)
8817 /* PowerPC 604ev */
082c6681 8818 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 8819#endif
8820 /* PowerPC 7xx family */
8821 /* Generic PowerPC 740 (G3) */
bd928eba 8822 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
082c6681 8823 /* Code name for PowerPC 740 */
bd928eba 8824 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
a750fc0b 8825 /* Generic PowerPC 750 (G3) */
bd928eba 8826 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
082c6681 8827 /* Code name for PowerPC 750 */
bd928eba 8828 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
a750fc0b 8829 /* PowerPC 740/750 is also known as G3 */
bd928eba
JM		 8830 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8831 /* PowerPC 740 v1.0 (G3) */
8832 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8833 /* PowerPC 750 v1.0 (G3) */
8834 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
a750fc0b 8835 /* PowerPC 740 v2.0 (G3) */
bd928eba 8836 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
a750fc0b 8837 /* PowerPC 750 v2.0 (G3) */
bd928eba 8838 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
a750fc0b 8839 /* PowerPC 740 v2.1 (G3) */
bd928eba 8840 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
a750fc0b 8841 /* PowerPC 750 v2.1 (G3) */
bd928eba 8842 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
a750fc0b 8843 /* PowerPC 740 v2.2 (G3) */
bd928eba 8844 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
a750fc0b 8845 /* PowerPC 750 v2.2 (G3) */
bd928eba 8846 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
a750fc0b 8847 /* PowerPC 740 v3.0 (G3) */
bd928eba 8848 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
a750fc0b 8849 /* PowerPC 750 v3.0 (G3) */
bd928eba 8850 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
a750fc0b 8851 /* PowerPC 740 v3.1 (G3) */
bd928eba 8852 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
a750fc0b 8853 /* PowerPC 750 v3.1 (G3) */
bd928eba 8854 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
a750fc0b 8855 /* PowerPC 740E (G3) */
bd928eba
JM		 8856 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8857 /* PowerPC 750E (G3) */
8858 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
a750fc0b 8859 /* PowerPC 740P (G3) */
bd928eba 8860 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
a750fc0b 8861 /* PowerPC 750P (G3) */
bd928eba 8862 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
a750fc0b 8863 /* Code name for PowerPC 740P/750P (G3) */
bd928eba 8864 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
a750fc0b 8865 /* PowerPC 750CL (G3 embedded) */
bd928eba
JM		 8866 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8867 /* PowerPC 750CL v1.0 */
8868 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8869 /* PowerPC 750CL v2.0 */
8870 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
a750fc0b 8871 /* PowerPC 750CX (G3 embedded) */
bd928eba
JM		 8872 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8873 /* PowerPC 750CX v1.0 (G3 embedded) */
8874 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8875 /* PowerPC 750CX v2.1 (G3 embedded) */
8876 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
a750fc0b 8877 /* PowerPC 750CX v2.1 (G3 embedded) */
bd928eba 8878 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
a750fc0b 8879 /* PowerPC 750CX v2.2 (G3 embedded) */
bd928eba 8880 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
a750fc0b 8881 /* PowerPC 750CXe (G3 embedded) */
bd928eba 8882 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
a750fc0b 8883 /* PowerPC 750CXe v2.1 (G3 embedded) */
bd928eba 8884 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
a750fc0b 8885 /* PowerPC 750CXe v2.2 (G3 embedded) */
bd928eba 8886 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
a750fc0b 8887 /* PowerPC 750CXe v2.3 (G3 embedded) */
bd928eba 8888 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
a750fc0b 8889 /* PowerPC 750CXe v2.4 (G3 embedded) */
bd928eba 8890 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
a750fc0b 8891 /* PowerPC 750CXe v2.4b (G3 embedded) */
bd928eba
JM		 8892 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8893 /* PowerPC 750CXe v3.0 (G3 embedded) */
8894 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
a750fc0b 8895 /* PowerPC 750CXe v3.1 (G3 embedded) */
bd928eba 8896 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
a750fc0b 8897 /* PowerPC 750CXe v3.1b (G3 embedded) */
bd928eba 8898 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
a750fc0b 8899 /* PowerPC 750CXr (G3 embedded) */
bd928eba 8900 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
a750fc0b 8901 /* PowerPC 750FL (G3 embedded) */
80d11f44 8902 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 8903 /* PowerPC 750FX (G3 embedded) */
80d11f44 8904 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 8905 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 8906 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 8907 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 8908 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 8909 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 8910 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 8911 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 8912 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 8913 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 8914 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 8915 /* PowerPC 750GL (G3 embedded) */
bd928eba 8916 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
a750fc0b 8917 /* PowerPC 750GX (G3 embedded) */
bd928eba 8918 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
a750fc0b 8919 /* PowerPC 750GX v1.0 (G3 embedded) */
bd928eba 8920 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
a750fc0b 8921 /* PowerPC 750GX v1.1 (G3 embedded) */
bd928eba 8922 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
a750fc0b 8923 /* PowerPC 750GX v1.2 (G3 embedded) */
bd928eba 8924 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
a750fc0b 8925 /* PowerPC 750L (G3 embedded) */
bd928eba 8926 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
a750fc0b 8927 /* Code name for PowerPC 750L (G3 embedded) */
bd928eba
JM		 8928 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8929 /* PowerPC 750L v2.0 (G3 embedded) */
8930 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8931 /* PowerPC 750L v2.1 (G3 embedded) */
8932 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
a750fc0b 8933 /* PowerPC 750L v2.2 (G3 embedded) */
bd928eba 8934 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
a750fc0b 8935 /* PowerPC 750L v3.0 (G3 embedded) */
bd928eba 8936 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
a750fc0b 8937 /* PowerPC 750L v3.2 (G3 embedded) */
bd928eba 8938 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
a750fc0b 8939 /* Generic PowerPC 745 */
bd928eba 8940 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
a750fc0b 8941 /* Generic PowerPC 755 */
bd928eba 8942 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
a750fc0b 8943 /* Code name for PowerPC 745/755 */
bd928eba 8944 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
a750fc0b 8945 /* PowerPC 745 v1.0 */
bd928eba 8946 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
a750fc0b 8947 /* PowerPC 755 v1.0 */
bd928eba 8948 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
a750fc0b 8949 /* PowerPC 745 v1.1 */
bd928eba 8950 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
a750fc0b 8951 /* PowerPC 755 v1.1 */
bd928eba 8952 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
a750fc0b 8953 /* PowerPC 745 v2.0 */
bd928eba 8954 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
a750fc0b 8955 /* PowerPC 755 v2.0 */
bd928eba 8956 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
a750fc0b 8957 /* PowerPC 745 v2.1 */
bd928eba 8958 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
a750fc0b 8959 /* PowerPC 755 v2.1 */
bd928eba 8960 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
a750fc0b 8961 /* PowerPC 745 v2.2 */
bd928eba 8962 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
a750fc0b 8963 /* PowerPC 755 v2.2 */
bd928eba 8964 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
a750fc0b 8965 /* PowerPC 745 v2.3 */
bd928eba 8966 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
a750fc0b 8967 /* PowerPC 755 v2.3 */
bd928eba 8968 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
a750fc0b 8969 /* PowerPC 745 v2.4 */
bd928eba 8970 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
a750fc0b 8971 /* PowerPC 755 v2.4 */
bd928eba 8972 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
a750fc0b 8973 /* PowerPC 745 v2.5 */
bd928eba 8974 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
a750fc0b 8975 /* PowerPC 755 v2.5 */
bd928eba 8976 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
a750fc0b 8977 /* PowerPC 745 v2.6 */
bd928eba 8978 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
a750fc0b 8979 /* PowerPC 755 v2.6 */
bd928eba 8980 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
a750fc0b 8981 /* PowerPC 745 v2.7 */
bd928eba 8982 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
a750fc0b 8983 /* PowerPC 755 v2.7 */
bd928eba 8984 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
a750fc0b 8985 /* PowerPC 745 v2.8 */
bd928eba 8986 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
a750fc0b 8987 /* PowerPC 755 v2.8 */
bd928eba 8988 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
a750fc0b
JM		 8989#if defined (TODO)
8990 /* PowerPC 745P (G3) */
bd928eba 8991 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
a750fc0b 8992 /* PowerPC 755P (G3) */
bd928eba 8993 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
a750fc0b
JM		 8994#endif
8995 /* PowerPC 74xx family */
8996 /* PowerPC 7400 (G4) */
80d11f44 8997 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 8998 /* Code name for PowerPC 7400 */
80d11f44 8999 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 9000 /* PowerPC 74xx is also well known as G4 */
80d11f44 9001 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 9002 /* PowerPC 7400 v1.0 (G4) */
80d11f44 9003 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 9004 /* PowerPC 7400 v1.1 (G4) */
80d11f44 9005 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 9006 /* PowerPC 7400 v2.0 (G4) */
80d11f44 9007 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
4e777442
JM		 9008 /* PowerPC 7400 v2.1 (G4) */
9009 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
a750fc0b 9010 /* PowerPC 7400 v2.2 (G4) */
80d11f44 9011 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 9012 /* PowerPC 7400 v2.6 (G4) */
80d11f44 9013 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 9014 /* PowerPC 7400 v2.7 (G4) */
80d11f44 9015 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 9016 /* PowerPC 7400 v2.8 (G4) */
80d11f44 9017 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 9018 /* PowerPC 7400 v2.9 (G4) */
80d11f44 9019 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 9020 /* PowerPC 7410 (G4) */
80d11f44 9021 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 9022 /* Code name for PowerPC 7410 */
80d11f44 9023 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 9024 /* PowerPC 7410 v1.0 (G4) */
80d11f44 9025 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 9026 /* PowerPC 7410 v1.1 (G4) */
80d11f44 9027 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 9028 /* PowerPC 7410 v1.2 (G4) */
80d11f44 9029 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 9030 /* PowerPC 7410 v1.3 (G4) */
80d11f44 9031 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 9032 /* PowerPC 7410 v1.4 (G4) */
80d11f44 9033 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 9034 /* PowerPC 7448 (G4) */
80d11f44 9035 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 9036 /* PowerPC 7448 v1.0 (G4) */
80d11f44 9037 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 9038 /* PowerPC 7448 v1.1 (G4) */
80d11f44 9039 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 9040 /* PowerPC 7448 v2.0 (G4) */
80d11f44 9041 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 9042 /* PowerPC 7448 v2.1 (G4) */
80d11f44 9043 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 9044 /* PowerPC 7450 (G4) */
80d11f44 9045 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 9046 /* Code name for PowerPC 7450 */
80d11f44 9047 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 9048 /* PowerPC 7450 v1.0 (G4) */
80d11f44 9049 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 9050 /* PowerPC 7450 v1.1 (G4) */
80d11f44 9051 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 9052 /* PowerPC 7450 v1.2 (G4) */
80d11f44 9053 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 9054 /* PowerPC 7450 v2.0 (G4) */
80d11f44 9055 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 9056 /* PowerPC 7450 v2.1 (G4) */
80d11f44 9057 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 9058 /* PowerPC 7441 (G4) */
80d11f44 9059 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 9060 /* PowerPC 7451 (G4) */
80d11f44 9061 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
4e777442
JM		 9062 /* PowerPC 7441 v2.1 (G4) */
9063 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9064 /* PowerPC 7441 v2.3 (G4) */
9065 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9066 /* PowerPC 7451 v2.3 (G4) */
9067 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9068 /* PowerPC 7441 v2.10 (G4) */
9069 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9070 /* PowerPC 7451 v2.10 (G4) */
9071 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
a750fc0b 9072 /* PowerPC 7445 (G4) */
80d11f44 9073 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 9074 /* PowerPC 7455 (G4) */
80d11f44 9075 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 9076 /* Code name for PowerPC 7445/7455 */
80d11f44 9077 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 9078 /* PowerPC 7445 v1.0 (G4) */
80d11f44 9079 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 9080 /* PowerPC 7455 v1.0 (G4) */
80d11f44 9081 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 9082 /* PowerPC 7445 v2.1 (G4) */
80d11f44 9083 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 9084 /* PowerPC 7455 v2.1 (G4) */
80d11f44 9085 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 9086 /* PowerPC 7445 v3.2 (G4) */
80d11f44 9087 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 9088 /* PowerPC 7455 v3.2 (G4) */
80d11f44 9089 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 9090 /* PowerPC 7445 v3.3 (G4) */
80d11f44 9091 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 9092 /* PowerPC 7455 v3.3 (G4) */
80d11f44 9093 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 9094 /* PowerPC 7445 v3.4 (G4) */
80d11f44 9095 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 9096 /* PowerPC 7455 v3.4 (G4) */
80d11f44 9097 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 9098 /* PowerPC 7447 (G4) */
80d11f44 9099 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 9100 /* PowerPC 7457 (G4) */
80d11f44 9101 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 9102 /* Code name for PowerPC 7447/7457 */
80d11f44 9103 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 9104 /* PowerPC 7447 v1.0 (G4) */
80d11f44 9105 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 9106 /* PowerPC 7457 v1.0 (G4) */
80d11f44 9107 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 9108 /* PowerPC 7447 v1.1 (G4) */
80d11f44 9109 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 9110 /* PowerPC 7457 v1.1 (G4) */
80d11f44 9111 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 9112 /* PowerPC 7457 v1.2 (G4) */
80d11f44 9113 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 9114 /* PowerPC 7447A (G4) */
9115 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9116 /* PowerPC 7457A (G4) */
9117 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9118 /* PowerPC 7447A v1.0 (G4) */
9119 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9120 /* PowerPC 7457A v1.0 (G4) */
9121 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9122 /* Code name for PowerPC 7447A/7457A */
9123 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9124 /* PowerPC 7447A v1.1 (G4) */
9125 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9126 /* PowerPC 7457A v1.1 (G4) */
9127 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9128 /* PowerPC 7447A v1.2 (G4) */
9129 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9130 /* PowerPC 7457A v1.2 (G4) */
9131 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 9132 /* 64 bits PowerPC */
9133#if defined (TARGET_PPC64)
a750fc0b 9134 /* PowerPC 620 */
80d11f44 9135 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 9136 /* Code name for PowerPC 620 */
9137 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 9138#if defined (TODO)
a750fc0b 9139 /* PowerPC 630 (POWER3) */
80d11f44
JM		 9140 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9141 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 9142 /* Code names for POWER3 */
9143 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9144 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 9145#endif
3a607854 9146#if defined (TODO)
a750fc0b 9147 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 9148 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9149 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 9150#endif
9151#if defined (TODO)
a750fc0b 9152 /* POWER4 */
80d11f44 9153 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 9154#endif
3a607854 9155#if defined (TODO)
a750fc0b 9156 /* POWER4p */
80d11f44 9157 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 9158#endif
2662a059 9159#if defined (TODO)
a750fc0b 9160 /* POWER5 */
80d11f44 9161 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 9162 /* POWER5GR */
80d11f44 9163 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 9164#endif
3a607854 9165#if defined (TODO)
a750fc0b 9166 /* POWER5+ */
80d11f44 9167 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 9168 /* POWER5GS */
80d11f44 9169 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 9170#endif
2662a059 9171#if defined (TODO)
a750fc0b 9172 /* POWER6 */
80d11f44 9173 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 9174 /* POWER6 running in POWER5 mode */
80d11f44 9175 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 9176 /* POWER6A */
80d11f44 9177 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 9178#endif
9d52e907
DG		 9179 /* POWER7 */
9180 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9181 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
37e305ce
DG		 9182 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
9183 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
a750fc0b 9184 /* PowerPC 970 */
80d11f44 9185 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 9186 /* PowerPC 970FX (G5) */
80d11f44 9187 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 9188 /* PowerPC 970FX v1.0 (G5) */
80d11f44 9189 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 9190 /* PowerPC 970FX v2.0 (G5) */
80d11f44 9191 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 9192 /* PowerPC 970FX v2.1 (G5) */
80d11f44 9193 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 9194 /* PowerPC 970FX v3.0 (G5) */
80d11f44 9195 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 9196 /* PowerPC 970FX v3.1 (G5) */
80d11f44 9197 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 9198 /* PowerPC 970GX (G5) */
80d11f44 9199 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 9200 /* PowerPC 970MP */
80d11f44 9201 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 9202 /* PowerPC 970MP v1.0 */
80d11f44 9203 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 9204 /* PowerPC 970MP v1.1 */
80d11f44 9205 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 9206#if defined (TODO)
a750fc0b 9207 /* PowerPC Cell */
80d11f44 9208 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 9209#endif
9210#if defined (TODO)
a750fc0b 9211 /* PowerPC Cell v1.0 */
80d11f44 9212 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 9213#endif
9214#if defined (TODO)
a750fc0b 9215 /* PowerPC Cell v2.0 */
80d11f44 9216 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 9217#endif
9218#if defined (TODO)
a750fc0b 9219 /* PowerPC Cell v3.0 */
80d11f44 9220 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 9221#endif
3a607854 9222#if defined (TODO)
a750fc0b 9223 /* PowerPC Cell v3.1 */
80d11f44 9224 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 9225#endif
9226#if defined (TODO)
a750fc0b 9227 /* PowerPC Cell v3.2 */
80d11f44 9228 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 9229#endif
9230#if defined (TODO)
a750fc0b
JM		 9231 /* RS64 (Apache/A35) */
9232 /* This one seems to support the whole POWER2 instruction set
9233 * and the PowerPC 64 one.
9234 */
9235 /* What about A10 & A30 ? */
80d11f44
JM		 9236 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9237 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9238 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 9239#endif
9240#if defined (TODO)
a750fc0b 9241 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 9242 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9243 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9244 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 9245#endif
9246#if defined (TODO)
a750fc0b 9247 /* RS64-III (Pulsar) */
80d11f44
JM		 9248 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9249 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 9250#endif
9251#if defined (TODO)
a750fc0b 9252 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 9253 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9254 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9255 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9256 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 9257#endif
a750fc0b
JM		 9258#endif /* defined (TARGET_PPC64) */
9259 /* POWER */
3fc6c082 9260#if defined (TODO)
a750fc0b 9261 /* Original POWER */
80d11f44
JM		 9262 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9263 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9264 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9265 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9266 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 9267#endif
9268#if defined (TODO)
a750fc0b 9269 /* POWER2 */
80d11f44
JM		 9270 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9271 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9272 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 9273#endif
9274 /* PA semi cores */
9275#if defined (TODO)
9276 /* PA PA6T */
80d11f44 9277 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 9278#endif
9279 /* Generic PowerPCs */
9280#if defined (TARGET_PPC64)
80d11f44 9281 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 9282#endif
80d11f44
JM		 9283 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9284 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 9285 /* Fallback */
80d11f44 9286 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 9287};
9288
9289/*****************************************************************************/
60b14d95 9290/* Generic CPU instantiation routine */
c227f099 9291static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9292{
9293#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 9294 int i;
9295
a750fc0b 9296 env->irq_inputs = NULL;
e1833e1f
JM		 9297 /* Set all exception vectors to an invalid address */
9298 for (i = 0; i < POWERPC_EXCP_NB; i++)
9299 env->excp_vectors[i] = (target_ulong)(-1ULL);
fc1c67bc 9300 env->hreset_excp_prefix = 0x00000000;
e1833e1f
JM		 9301 env->ivor_mask = 0x00000000;
9302 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 9303 /* Default MMU definitions */
9304 env->nb_BATs = 0;
9305 env->nb_tlb = 0;
9306 env->nb_ways = 0;
1c53accc 9307 env->tlb_type = TLB_NONE;
f2e63a42 9308#endif
a750fc0b
JM		 9309 /* Register SPR common to all PowerPC implementations */
9310 gen_spr_generic(env);
9311 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 9312 /* Linux permits userspace to read PVR */
9313#if defined(CONFIG_LINUX_USER)
9314 &spr_read_generic,
9315#else
9316 SPR_NOACCESS,
9317#endif
9318 SPR_NOACCESS,
a750fc0b
JM		 9319 &spr_read_generic, SPR_NOACCESS,
9320 def->pvr);
80d11f44
JM		 9321 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9322 if (def->svr != POWERPC_SVR_NONE) {
9323 if (def->svr & POWERPC_SVR_E500) {
9324 spr_register(env, SPR_E500_SVR, "SVR",
9325 SPR_NOACCESS, SPR_NOACCESS,
9326 &spr_read_generic, SPR_NOACCESS,
9327 def->svr & ~POWERPC_SVR_E500);
9328 } else {
9329 spr_register(env, SPR_SVR, "SVR",
9330 SPR_NOACCESS, SPR_NOACCESS,
9331 &spr_read_generic, SPR_NOACCESS,
9332 def->svr);
9333 }
9334 }
a750fc0b
JM		 9335 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9336 (*def->init_proc)(env);
fc1c67bc
BS		 9337#if !defined(CONFIG_USER_ONLY)
9338 env->excp_prefix = env->hreset_excp_prefix;
9339#endif
25ba3a68
JM		 9340 /* MSR bits & flags consistency checks */
9341 if (env->msr_mask & (1 << 25)) {
9342 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9343 case POWERPC_FLAG_SPE:
9344 case POWERPC_FLAG_VRE:
9345 break;
9346 default:
9347 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9348 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9349 exit(1);
9350 }
9351 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9352 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9353 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9354 exit(1);
9355 }
9356 if (env->msr_mask & (1 << 17)) {
9357 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9358 case POWERPC_FLAG_TGPR:
9359 case POWERPC_FLAG_CE:
9360 break;
9361 default:
9362 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9363 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9364 exit(1);
9365 }
9366 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9367 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9368 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9369 exit(1);
9370 }
9371 if (env->msr_mask & (1 << 10)) {
9372 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9373 POWERPC_FLAG_UBLE)) {
9374 case POWERPC_FLAG_SE:
9375 case POWERPC_FLAG_DWE:
9376 case POWERPC_FLAG_UBLE:
9377 break;
9378 default:
9379 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9380 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9381 "POWERPC_FLAG_UBLE\n");
9382 exit(1);
9383 }
9384 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9385 POWERPC_FLAG_UBLE)) {
9386 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9387 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9388 "POWERPC_FLAG_UBLE\n");
9389 exit(1);
9390 }
9391 if (env->msr_mask & (1 << 9)) {
9392 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9393 case POWERPC_FLAG_BE:
9394 case POWERPC_FLAG_DE:
9395 break;
9396 default:
9397 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9398 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9399 exit(1);
9400 }
9401 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9402 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9403 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9404 exit(1);
9405 }
9406 if (env->msr_mask & (1 << 2)) {
9407 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9408 case POWERPC_FLAG_PX:
9409 case POWERPC_FLAG_PMM:
9410 break;
9411 default:
9412 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9413 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9414 exit(1);
9415 }
9416 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9417 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9418 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9419 exit(1);
9420 }
4018bae9
JM		 9421 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9422 fprintf(stderr, "PowerPC flags inconsistency\n"
9423 "Should define the time-base and decrementer clock source\n");
9424 exit(1);
9425 }
a750fc0b 9426 /* Allocate TLBs buffer when needed */
f2e63a42 9427#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9428 if (env->nb_tlb != 0) {
9429 int nb_tlb = env->nb_tlb;
9430 if (env->id_tlbs != 0)
9431 nb_tlb *= 2;
1c53accc
AG		 9432 switch (env->tlb_type) {
9433 case TLB_6XX:
7267c094 9434 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
1c53accc
AG		 9435 break;
9436 case TLB_EMB:
7267c094 9437 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
1c53accc
AG		 9438 break;
9439 case TLB_MAS:
7267c094 9440 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
1c53accc
AG		 9441 break;
9442 }
a750fc0b
JM		 9443 /* Pre-compute some useful values */
9444 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9445 }
a750fc0b
JM		 9446 if (env->irq_inputs == NULL) {
9447 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5cbdb3a3 9448 " Attempt QEMU to crash very soon !\n");
a750fc0b
JM		 9449 }
9450#endif
2f462816
JM		 9451 if (env->check_pow == NULL) {
9452 fprintf(stderr, "WARNING: no power management check handler "
9453 "registered.\n"
5cbdb3a3 9454 " Attempt QEMU to crash very soon !\n");
2f462816 9455 }
a750fc0b
JM		 9456}
9457
9458#if defined(PPC_DUMP_CPU)
9459static void dump_ppc_sprs (CPUPPCState *env)
9460{
9461 ppc_spr_t *spr;
9462#if !defined(CONFIG_USER_ONLY)
9463 uint32_t sr, sw;
9464#endif
9465 uint32_t ur, uw;
9466 int i, j, n;
9467
9468 printf("Special purpose registers:\n");
9469 for (i = 0; i < 32; i++) {
9470 for (j = 0; j < 32; j++) {
9471 n = (i << 5) | j;
9472 spr = &env->spr_cb[n];
9473 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9474 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9475#if !defined(CONFIG_USER_ONLY)
9476 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9477 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9478 if (sw || sr || uw || ur) {
9479 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9480 (i << 5) | j, (i << 5) | j, spr->name,
9481 sw ? 'w' : '-', sr ? 'r' : '-',
9482 uw ? 'w' : '-', ur ? 'r' : '-');
9483 }
9484#else
9485 if (uw || ur) {
9486 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9487 (i << 5) | j, (i << 5) | j, spr->name,
9488 uw ? 'w' : '-', ur ? 'r' : '-');
9489 }
9490#endif
9491 }
9492 }
9493 fflush(stdout);
9494 fflush(stderr);
9495}
9496#endif
9497
9498/*****************************************************************************/
9499#include <stdlib.h>
9500#include <string.h>
9501
a750fc0b
JM		 9502/* Opcode types */
9503enum {
9504 PPC_DIRECT = 0, /* Opcode routine */
9505 PPC_INDIRECT = 1, /* Indirect opcode table */
9506};
9507
9508static inline int is_indirect_opcode (void *handler)
9509{
5724753e 9510 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
a750fc0b
JM		 9511}
9512
c227f099 9513static inline opc_handler_t **ind_table(void *handler)
a750fc0b 9514{
5724753e 9515 return (opc_handler_t **)((uintptr_t)handler & ~3);
a750fc0b
JM		 9516}
9517
9518/* Instruction table creation */
9519/* Opcodes tables creation */
c227f099 9520static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 9521{
9522 int i;
9523
9524 for (i = 0; i < len; i++)
9525 table[i] = &invalid_handler;
9526}
9527
c227f099 9528static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 9529{
c227f099 9530 opc_handler_t **tmp;
a750fc0b 9531
c227f099 9532 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b 9533 fill_new_table(tmp, 0x20);
5724753e 9534 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
a750fc0b
JM		 9535
9536 return 0;
9537}
9538
c227f099
AL		 9539static int insert_in_table (opc_handler_t **table, unsigned char idx,
9540 opc_handler_t *handler)
a750fc0b
JM		 9541{
9542 if (table[idx] != &invalid_handler)
9543 return -1;
9544 table[idx] = handler;
9545
9546 return 0;
9547}
9548
c227f099
AL		 9549static int register_direct_insn (opc_handler_t **ppc_opcodes,
9550 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 9551{
9552 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9553 printf("*** ERROR: opcode %02x already assigned in main "
9554 "opcode table\n", idx);
4c1b1bfe
JM		 9555#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9556 printf(" Registered handler '%s' - new handler '%s'\n",
9557 ppc_opcodes[idx]->oname, handler->oname);
9558#endif
a750fc0b
JM		 9559 return -1;
9560 }
9561
9562 return 0;
9563}
9564
c227f099 9565static int register_ind_in_table (opc_handler_t **table,
a750fc0b 9566 unsigned char idx1, unsigned char idx2,
c227f099 9567 opc_handler_t *handler)
a750fc0b
JM		 9568{
9569 if (table[idx1] == &invalid_handler) {
9570 if (create_new_table(table, idx1) < 0) {
9571 printf("*** ERROR: unable to create indirect table "
9572 "idx=%02x\n", idx1);
9573 return -1;
9574 }
9575 } else {
9576 if (!is_indirect_opcode(table[idx1])) {
9577 printf("*** ERROR: idx %02x already assigned to a direct "
9578 "opcode\n", idx1);
4c1b1bfe
JM		 9579#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9580 printf(" Registered handler '%s' - new handler '%s'\n",
9581 ind_table(table[idx1])[idx2]->oname, handler->oname);
9582#endif
a750fc0b
JM		 9583 return -1;
9584 }
3a607854 9585 }
a750fc0b
JM		 9586 if (handler != NULL &&
9587 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9588 printf("*** ERROR: opcode %02x already assigned in "
9589 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9590#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9591 printf(" Registered handler '%s' - new handler '%s'\n",
9592 ind_table(table[idx1])[idx2]->oname, handler->oname);
9593#endif
a750fc0b 9594 return -1;
3a607854 9595 }
a750fc0b
JM		 9596
9597 return 0;
9598}
9599
c227f099 9600static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9601 unsigned char idx1, unsigned char idx2,
c227f099 9602 opc_handler_t *handler)
a750fc0b
JM		 9603{
9604 int ret;
9605
9606 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9607
9608 return ret;
9609}
9610
c227f099 9611static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9612 unsigned char idx1, unsigned char idx2,
c227f099 9613 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 9614{
9615 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9616 printf("*** ERROR: unable to join indirect table idx "
9617 "[%02x-%02x]\n", idx1, idx2);
9618 return -1;
9619 }
9620 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9621 handler) < 0) {
9622 printf("*** ERROR: unable to insert opcode "
9623 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9624 return -1;
9625 }
9626
9627 return 0;
9628}
9629
c227f099 9630static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 9631{
9632 if (insn->opc2 != 0xFF) {
9633 if (insn->opc3 != 0xFF) {
9634 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9635 insn->opc3, &insn->handler) < 0)
9636 return -1;
9637 } else {
9638 if (register_ind_insn(ppc_opcodes, insn->opc1,
9639 insn->opc2, &insn->handler) < 0)
9640 return -1;
9641 }
9642 } else {
9643 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9644 return -1;
9645 }
9646
9647 return 0;
9648}
9649
c227f099 9650static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 9651{
9652 int i, count, tmp;
9653
9654 for (i = 0, count = 0; i < len; i++) {
9655 /* Consistency fixup */
9656 if (table[i] == NULL)
9657 table[i] = &invalid_handler;
9658 if (table[i] != &invalid_handler) {
9659 if (is_indirect_opcode(table[i])) {
c227f099 9660 tmp = test_opcode_table(ind_table(table[i]), 0x20);
a750fc0b
JM		 9661 if (tmp == 0) {
9662 free(table[i]);
9663 table[i] = &invalid_handler;
9664 } else {
9665 count++;
9666 }
9667 } else {
9668 count++;
9669 }
9670 }
9671 }
9672
9673 return count;
9674}
9675
c227f099 9676static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 9677{
c227f099 9678 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
a750fc0b
JM		 9679 printf("*** WARNING: no opcode defined !\n");
9680}
9681
9682/*****************************************************************************/
c227f099 9683static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b 9684{
c227f099 9685 opcode_t *opc;
a750fc0b
JM		 9686
9687 fill_new_table(env->opcodes, 0x40);
5c55ff99 9688 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
a5858d7a
AG		 9689 if (((opc->handler.type & def->insns_flags) != 0) ||
9690 ((opc->handler.type2 & def->insns_flags2) != 0)) {
a750fc0b
JM		 9691 if (register_insn(env->opcodes, opc) < 0) {
9692 printf("*** ERROR initializing PowerPC instruction "
9693 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9694 opc->opc3);
9695 return -1;
9696 }
9697 }
9698 }
c227f099 9699 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 9700 fflush(stdout);
9701 fflush(stderr);
9702
9703 return 0;
9704}
9705
9706#if defined(PPC_DUMP_CPU)
25ba3a68 9707static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 9708{
c227f099 9709 opc_handler_t **table, *handler;
b55266b5 9710 const char *p, *q;
a750fc0b
JM		 9711 uint8_t opc1, opc2, opc3;
9712
9713 printf("Instructions set:\n");
9714 /* opc1 is 6 bits long */
9715 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9716 table = env->opcodes;
9717 handler = table[opc1];
9718 if (is_indirect_opcode(handler)) {
9719 /* opc2 is 5 bits long */
9720 for (opc2 = 0; opc2 < 0x20; opc2++) {
9721 table = env->opcodes;
9722 handler = env->opcodes[opc1];
9723 table = ind_table(handler);
9724 handler = table[opc2];
9725 if (is_indirect_opcode(handler)) {
9726 table = ind_table(handler);
9727 /* opc3 is 5 bits long */
9728 for (opc3 = 0; opc3 < 0x20; opc3++) {
9729 handler = table[opc3];
9730 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9731 /* Special hack to properly dump SPE insns */
9732 p = strchr(handler->oname, '_');
9733 if (p == NULL) {
9734 printf("INSN: %02x %02x %02x (%02d %04d) : "
9735 "%s\n",
9736 opc1, opc2, opc3, opc1,
9737 (opc3 << 5) | opc2,
9738 handler->oname);
9739 } else {
9740 q = "speundef";
9741 if ((p - handler->oname) != strlen(q) ||
9742 memcmp(handler->oname, q, strlen(q)) != 0) {
9743 /* First instruction */
9744 printf("INSN: %02x %02x %02x (%02d %04d) : "
9745 "%.*s\n",
9746 opc1, opc2 << 1, opc3, opc1,
9747 (opc3 << 6) | (opc2 << 1),
9748 (int)(p - handler->oname),
9749 handler->oname);
9750 }
9751 if (strcmp(p + 1, q) != 0) {
9752 /* Second instruction */
9753 printf("INSN: %02x %02x %02x (%02d %04d) : "
9754 "%s\n",
9755 opc1, (opc2 << 1) | 1, opc3, opc1,
9756 (opc3 << 6) | (opc2 << 1) | 1,
9757 p + 1);
9758 }
9759 }
a750fc0b
JM		 9760 }
9761 }
9762 } else {
9763 if (handler->handler != &gen_invalid) {
9764 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9765 opc1, opc2, opc1, opc2, handler->oname);
9766 }
9767 }
9768 }
9769 } else {
9770 if (handler->handler != &gen_invalid) {
9771 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9772 opc1, opc1, handler->oname);
9773 }
9774 }
9775 }
9776}
3a607854 9777#endif
a750fc0b 9778
1328c2bf 9779static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 9780{
9781 if (n < 32) {
9782 stfq_p(mem_buf, env->fpr[n]);
9783 return 8;
9784 }
9785 if (n == 32) {
5a576fb3 9786 stl_p(mem_buf, env->fpscr);
24951522
AJ		 9787 return 4;
9788 }
9789 return 0;
9790}
9791
1328c2bf 9792static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 9793{
9794 if (n < 32) {
9795 env->fpr[n] = ldfq_p(mem_buf);
9796 return 8;
9797 }
9798 if (n == 32) {
9799 /* FPSCR not implemented */
9800 return 4;
9801 }
9802 return 0;
9803}
9804
1328c2bf 9805static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 9806{
9807 if (n < 32) {
e2542fe2 9808#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9809 stq_p(mem_buf, env->avr[n].u64[0]);
9810 stq_p(mem_buf+8, env->avr[n].u64[1]);
9811#else
9812 stq_p(mem_buf, env->avr[n].u64[1]);
9813 stq_p(mem_buf+8, env->avr[n].u64[0]);
9814#endif
9815 return 16;
9816 }
70976a79 9817 if (n == 32) {
b4f8d821
AJ		 9818 stl_p(mem_buf, env->vscr);
9819 return 4;
9820 }
70976a79 9821 if (n == 33) {
b4f8d821
AJ		 9822 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9823 return 4;
9824 }
9825 return 0;
9826}
9827
1328c2bf 9828static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 9829{
9830 if (n < 32) {
e2542fe2 9831#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9832 env->avr[n].u64[0] = ldq_p(mem_buf);
9833 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9834#else
9835 env->avr[n].u64[1] = ldq_p(mem_buf);
9836 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9837#endif
9838 return 16;
9839 }
70976a79 9840 if (n == 32) {
b4f8d821
AJ		 9841 env->vscr = ldl_p(mem_buf);
9842 return 4;
9843 }
70976a79 9844 if (n == 33) {
b4f8d821
AJ		 9845 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9846 return 4;
9847 }
9848 return 0;
9849}
9850
1328c2bf 9851static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 9852{
9853 if (n < 32) {
9854#if defined(TARGET_PPC64)
9855 stl_p(mem_buf, env->gpr[n] >> 32);
9856#else
9857 stl_p(mem_buf, env->gprh[n]);
9858#endif
9859 return 4;
9860 }
70976a79 9861 if (n == 32) {
688890f7
AJ		 9862 stq_p(mem_buf, env->spe_acc);
9863 return 8;
9864 }
70976a79 9865 if (n == 33) {
d34defbc 9866 stl_p(mem_buf, env->spe_fscr);
688890f7
AJ		 9867 return 4;
9868 }
9869 return 0;
9870}
9871
1328c2bf 9872static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 9873{
9874 if (n < 32) {
9875#if defined(TARGET_PPC64)
9876 target_ulong lo = (uint32_t)env->gpr[n];
9877 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9878 env->gpr[n] = lo | hi;
9879#else
9880 env->gprh[n] = ldl_p(mem_buf);
9881#endif
9882 return 4;
9883 }
70976a79 9884 if (n == 32) {
688890f7
AJ		 9885 env->spe_acc = ldq_p(mem_buf);
9886 return 8;
9887 }
70976a79 9888 if (n == 33) {
d34defbc 9889 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 9890 return 4;
9891 }
9892 return 0;
9893}
9894
12b1143b
DG		 9895static int ppc_fixup_cpu(CPUPPCState *env)
9896{
9897 /* TCG doesn't (yet) emulate some groups of instructions that
9898 * are implemented on some otherwise supported CPUs (e.g. VSX
9899 * and decimal floating point instructions on POWER7). We
9900 * remove unsupported instruction groups from the cpu state's
9901 * instruction masks and hope the guest can cope. For at
9902 * least the pseries machine, the unavailability of these
9903 * instructions can be advertised to the guest via the device
9904 * tree. */
9905 if ((env->insns_flags & ~PPC_TCG_INSNS)
9906 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9907 fprintf(stderr, "Warning: Disabling some instructions which are not "
9908 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9909 env->insns_flags & ~PPC_TCG_INSNS,
9910 env->insns_flags2 & ~PPC_TCG_INSNS2);
9911 }
9912 env->insns_flags &= PPC_TCG_INSNS;
9913 env->insns_flags2 &= PPC_TCG_INSNS2;
9914 return 0;
9915}
9916
c227f099 9917int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9918{
9919 env->msr_mask = def->msr_mask;
9920 env->mmu_model = def->mmu_model;
9921 env->excp_model = def->excp_model;
9922 env->bus_model = def->bus_model;
c29b735c 9923 env->insns_flags = def->insns_flags;
a5858d7a 9924 env->insns_flags2 = def->insns_flags2;
d26bfc9a 9925 env->flags = def->flags;
237c0af0 9926 env->bfd_mach = def->bfd_mach;
2f462816 9927 env->check_pow = def->check_pow;
12b1143b
DG		 9928
9929 if (kvm_enabled()) {
9930 if (kvmppc_fixup_cpu(env) != 0) {
9931 fprintf(stderr, "Unable to virtualize selected CPU with KVM\n");
9932 exit(1);
9933 }
9934 } else {
9935 if (ppc_fixup_cpu(env) != 0) {
9936 fprintf(stderr, "Unable to emulate selected CPU with TCG\n");
9937 exit(1);
9938 }
9939 }
9940
a750fc0b
JM		 9941 if (create_ppc_opcodes(env, def) < 0)
9942 return -1;
9943 init_ppc_proc(env, def);
24951522
AJ		 9944
9945 if (def->insns_flags & PPC_FLOAT) {
9946 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9947 33, "power-fpu.xml", 0);
9948 }
b4f8d821
AJ		 9949 if (def->insns_flags & PPC_ALTIVEC) {
9950 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9951 34, "power-altivec.xml", 0);
9952 }
40569b7e 9953 if (def->insns_flags & PPC_SPE) {
688890f7
AJ		 9954 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9955 34, "power-spe.xml", 0);
9956 }
9957
a750fc0b 9958#if defined(PPC_DUMP_CPU)
3a607854 9959 {
b55266b5 9960 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 9961 switch (env->mmu_model) {
9962 case POWERPC_MMU_32B:
9963 mmu_model = "PowerPC 32";
9964 break;
a750fc0b
JM		 9965 case POWERPC_MMU_SOFT_6xx:
9966 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9967 break;
9968 case POWERPC_MMU_SOFT_74xx:
9969 mmu_model = "PowerPC 74xx with software driven TLBs";
9970 break;
9971 case POWERPC_MMU_SOFT_4xx:
9972 mmu_model = "PowerPC 4xx with software driven TLBs";
9973 break;
9974 case POWERPC_MMU_SOFT_4xx_Z:
9975 mmu_model = "PowerPC 4xx with software driven TLBs "
9976 "and zones protections";
9977 break;
b4095fed
JM		 9978 case POWERPC_MMU_REAL:
9979 mmu_model = "PowerPC real mode only";
9980 break;
9981 case POWERPC_MMU_MPC8xx:
9982 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 9983 break;
9984 case POWERPC_MMU_BOOKE:
9985 mmu_model = "PowerPC BookE";
9986 break;
01662f3e
AG		 9987 case POWERPC_MMU_BOOKE206:
9988 mmu_model = "PowerPC BookE 2.06";
a750fc0b 9989 break;
b4095fed
JM		 9990 case POWERPC_MMU_601:
9991 mmu_model = "PowerPC 601";
9992 break;
00af685f
JM		 9993#if defined (TARGET_PPC64)
9994 case POWERPC_MMU_64B:
9995 mmu_model = "PowerPC 64";
9996 break;
add78955
JM		 9997 case POWERPC_MMU_620:
9998 mmu_model = "PowerPC 620";
9999 break;
00af685f 10000#endif
a750fc0b
JM		 10001 default:
10002 mmu_model = "Unknown or invalid";
10003 break;
10004 }
10005 switch (env->excp_model) {
10006 case POWERPC_EXCP_STD:
10007 excp_model = "PowerPC";
10008 break;
10009 case POWERPC_EXCP_40x:
10010 excp_model = "PowerPC 40x";
10011 break;
10012 case POWERPC_EXCP_601:
10013 excp_model = "PowerPC 601";
10014 break;
10015 case POWERPC_EXCP_602:
10016 excp_model = "PowerPC 602";
10017 break;
10018 case POWERPC_EXCP_603:
10019 excp_model = "PowerPC 603";
10020 break;
10021 case POWERPC_EXCP_603E:
10022 excp_model = "PowerPC 603e";
10023 break;
10024 case POWERPC_EXCP_604:
10025 excp_model = "PowerPC 604";
10026 break;
10027 case POWERPC_EXCP_7x0:
10028 excp_model = "PowerPC 740/750";
10029 break;
10030 case POWERPC_EXCP_7x5:
10031 excp_model = "PowerPC 745/755";
10032 break;
10033 case POWERPC_EXCP_74xx:
10034 excp_model = "PowerPC 74xx";
10035 break;
a750fc0b
JM		 10036 case POWERPC_EXCP_BOOKE:
10037 excp_model = "PowerPC BookE";
10038 break;
00af685f
JM		 10039#if defined (TARGET_PPC64)
10040 case POWERPC_EXCP_970:
10041 excp_model = "PowerPC 970";
10042 break;
10043#endif
a750fc0b
JM		 10044 default:
10045 excp_model = "Unknown or invalid";
10046 break;
10047 }
10048 switch (env->bus_model) {
10049 case PPC_FLAGS_INPUT_6xx:
10050 bus_model = "PowerPC 6xx";
10051 break;
10052 case PPC_FLAGS_INPUT_BookE:
10053 bus_model = "PowerPC BookE";
10054 break;
10055 case PPC_FLAGS_INPUT_405:
10056 bus_model = "PowerPC 405";
10057 break;
a750fc0b
JM		 10058 case PPC_FLAGS_INPUT_401:
10059 bus_model = "PowerPC 401/403";
10060 break;
b4095fed
JM		 10061 case PPC_FLAGS_INPUT_RCPU:
10062 bus_model = "RCPU / MPC8xx";
10063 break;
00af685f
JM		 10064#if defined (TARGET_PPC64)
10065 case PPC_FLAGS_INPUT_970:
10066 bus_model = "PowerPC 970";
10067 break;
10068#endif
a750fc0b
JM		 10069 default:
10070 bus_model = "Unknown or invalid";
10071 break;
10072 }
10073 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10074 " MMU model : %s\n",
10075 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 10076#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 10077 if (env->tlb != NULL) {
10078 printf(" %d %s TLB in %d ways\n",
10079 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10080 env->nb_ways);
10081 }
f2e63a42 10082#endif
a750fc0b
JM		 10083 printf(" Exceptions model : %s\n"
10084 " Bus model : %s\n",
10085 excp_model, bus_model);
25ba3a68
JM		 10086 printf(" MSR features :\n");
10087 if (env->flags & POWERPC_FLAG_SPE)
10088 printf(" signal processing engine enable"
10089 "\n");
10090 else if (env->flags & POWERPC_FLAG_VRE)
10091 printf(" vector processor enable\n");
10092 if (env->flags & POWERPC_FLAG_TGPR)
10093 printf(" temporary GPRs\n");
10094 else if (env->flags & POWERPC_FLAG_CE)
10095 printf(" critical input enable\n");
10096 if (env->flags & POWERPC_FLAG_SE)
10097 printf(" single-step trace mode\n");
10098 else if (env->flags & POWERPC_FLAG_DWE)
10099 printf(" debug wait enable\n");
10100 else if (env->flags & POWERPC_FLAG_UBLE)
10101 printf(" user BTB lock enable\n");
10102 if (env->flags & POWERPC_FLAG_BE)
10103 printf(" branch-step trace mode\n");
10104 else if (env->flags & POWERPC_FLAG_DE)
10105 printf(" debug interrupt enable\n");
10106 if (env->flags & POWERPC_FLAG_PX)
10107 printf(" inclusive protection\n");
10108 else if (env->flags & POWERPC_FLAG_PMM)
10109 printf(" performance monitor mark\n");
10110 if (env->flags == POWERPC_FLAG_NONE)
10111 printf(" none\n");
4018bae9
JM		 10112 printf(" Time-base/decrementer clock source: %s\n",
10113 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 10114 }
10115 dump_ppc_insns(env);
10116 dump_ppc_sprs(env);
10117 fflush(stdout);
3a607854 10118#endif
a750fc0b
JM		 10119
10120 return 0;
10121}
3fc6c082 10122
f0ad8c34
AG		 10123static bool ppc_cpu_usable(const ppc_def_t *def)
10124{
10125#if defined(TARGET_PPCEMB)
10126 /* When using the ppcemb target, we only support 440 style cores */
10127 if (def->mmu_model != POWERPC_MMU_BOOKE) {
10128 return false;
10129 }
10130#endif
10131
10132 return true;
10133}
10134
a1e98583 10135const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
3fc6c082 10136{
be40edcd
DG		 10137 int i;
10138
10139 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
f0ad8c34
AG		 10140 if (!ppc_cpu_usable(&ppc_defs[i])) {
10141 continue;
10142 }
10143
be40edcd
DG		 10144 /* If we have an exact match, we're done */
10145 if (pvr == ppc_defs[i].pvr) {
10146 return &ppc_defs[i];
3fc6c082
FB		 10147 }
10148 }
ee4e83ed 10149
be40edcd 10150 return NULL;
3fc6c082
FB		 10151}
10152
ee4e83ed 10153#include <ctype.h>
3fc6c082 10154
c227f099 10155const ppc_def_t *cpu_ppc_find_by_name (const char *name)
ee4e83ed 10156{
c227f099 10157 const ppc_def_t *ret;
b55266b5 10158 const char *p;
ee4e83ed
JM		 10159 int i, max, len;
10160
a1e98583
DG		 10161 if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
10162 return kvmppc_host_cpu_def();
10163 }
10164
ee4e83ed
JM		 10165 /* Check if the given name is a PVR */
10166 len = strlen(name);
10167 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10168 p = name + 2;
10169 goto check_pvr;
10170 } else if (len == 8) {
10171 p = name;
10172 check_pvr:
10173 for (i = 0; i < 8; i++) {
cd390083 10174 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 10175 break;
10176 }
10177 if (i == 8)
10178 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10179 }
10180 ret = NULL;
b1503cda 10181 max = ARRAY_SIZE(ppc_defs);
068abdc8 10182 for (i = 0; i < max; i++) {
f0ad8c34
AG		 10183 if (!ppc_cpu_usable(&ppc_defs[i])) {
10184 continue;
10185 }
10186
ee4e83ed
JM		 10187 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10188 ret = &ppc_defs[i];
10189 break;
3fc6c082
FB		 10190 }
10191 }
ee4e83ed
JM		 10192
10193 return ret;
3fc6c082
FB		 10194}
10195
9a78eead 10196void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
3fc6c082 10197{
068abdc8 10198 int i, max;
3fc6c082 10199
b1503cda 10200 max = ARRAY_SIZE(ppc_defs);
068abdc8 10201 for (i = 0; i < max; i++) {
f0ad8c34
AG		 10202 if (!ppc_cpu_usable(&ppc_defs[i])) {
10203 continue;
10204 }
10205
a750fc0b
JM		 10206 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10207 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 10208 }
10209}
1d0cb67d
AF		 10210
10211/* CPUClass::reset() */
10212static void ppc_cpu_reset(CPUState *s)
10213{
10214 PowerPCCPU *cpu = POWERPC_CPU(s);
10215 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10216 CPUPPCState *env = &cpu->env;
a1389542
AF		 10217 target_ulong msr;
10218
10219 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
10220 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
10221 log_cpu_state(env, 0);
10222 }
1d0cb67d
AF		 10223
10224 pcc->parent_reset(s);
10225
a1389542
AF		 10226 msr = (target_ulong)0;
10227 if (0) {
10228 /* XXX: find a suitable condition to enable the hypervisor mode */
10229 msr |= (target_ulong)MSR_HVB;
10230 }
10231 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10232 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10233 msr |= (target_ulong)1 << MSR_EP;
10234#if defined(DO_SINGLE_STEP) && 0
10235 /* Single step trace mode */
10236 msr |= (target_ulong)1 << MSR_SE;
10237 msr |= (target_ulong)1 << MSR_BE;
10238#endif
10239#if defined(CONFIG_USER_ONLY)
10240 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10241 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10242 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10243 msr |= (target_ulong)1 << MSR_PR;
10244#else
10245 env->excp_prefix = env->hreset_excp_prefix;
10246 env->nip = env->hreset_vector | env->excp_prefix;
10247 if (env->mmu_model != POWERPC_MMU_REAL) {
10248 ppc_tlb_invalidate_all(env);
10249 }
10250#endif
10251 env->msr = msr & env->msr_mask;
10252#if defined(TARGET_PPC64)
10253 if (env->mmu_model & POWERPC_MMU_64) {
10254 env->msr |= (1ULL << MSR_SF);
10255 }
10256#endif
10257 hreg_compute_hflags(env);
10258 env->reserve_addr = (target_ulong)-1ULL;
10259 /* Be sure no exception or interrupt is pending */
10260 env->pending_interrupts = 0;
10261 env->exception_index = POWERPC_EXCP_NONE;
10262 env->error_code = 0;
10263 /* Flush all TLBs */
10264 tlb_flush(env, 1);
1d0cb67d
AF		 10265}
10266
6cca7ad6
AF		 10267static void ppc_cpu_initfn(Object *obj)
10268{
10269 PowerPCCPU *cpu = POWERPC_CPU(obj);
10270 CPUPPCState *env = &cpu->env;
10271
10272 cpu_exec_init(env);
10273}
10274
1d0cb67d
AF		 10275static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10276{
10277 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10278 CPUClass *cc = CPU_CLASS(oc);
10279
10280 pcc->parent_reset = cc->reset;
10281 cc->reset = ppc_cpu_reset;
10282}
10283
10284static const TypeInfo ppc_cpu_type_info = {
10285 .name = TYPE_POWERPC_CPU,
10286 .parent = TYPE_CPU,
10287 .instance_size = sizeof(PowerPCCPU),
6cca7ad6 10288 .instance_init = ppc_cpu_initfn,
1d0cb67d
AF		 10289 .abstract = false,
10290 .class_size = sizeof(PowerPCCPUClass),
10291 .class_init = ppc_cpu_class_init,
10292};
10293
10294static void ppc_cpu_register_types(void)
10295{
10296 type_register_static(&ppc_cpu_type_info);
10297}
10298
10299type_init(ppc_cpu_register_types)
Qemu copy for testing