]> git.proxmox.com Git - qemu.git/blame - target-ppc/translate_init.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Real-mode only PowerPC 40x do not have any TLBs.
[qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0
JM		 26#include "dis-asm.h"
27
3fc6c082
FB		 28//#define PPC_DUMP_CPU
29//#define PPC_DEBUG_SPR
a496775f 30//#define PPC_DEBUG_IRQ
3fc6c082
FB		 31
32struct ppc_def_t {
33 const unsigned char *name;
34 uint32_t pvr;
35 uint32_t pvr_mask;
0487d6a8 36 uint64_t insns_flags;
3fc6c082 37 uint64_t msr_mask;
a750fc0b
JM		 38 uint8_t mmu_model;
39 uint8_t excp_model;
40 uint8_t bus_model;
41 uint8_t pad;
d26bfc9a 42 uint32_t flags;
237c0af0 43 int bfd_mach;
a750fc0b 44 void (*init_proc)(CPUPPCState *env);
3fc6c082
FB		 45};
46
e9df014c
JM		 47/* For user-mode emulation, we don't emulate any IRQ controller */
48#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 49#define PPC_IRQ_INIT_FN(name) \
50static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
51{ \
e9df014c
JM		 52}
53#else
a750fc0b 54#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 55void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
56#endif
a750fc0b 57
4e290a0b 58PPC_IRQ_INIT_FN(40x);
e9df014c 59PPC_IRQ_INIT_FN(6xx);
d0dfae6e 60PPC_IRQ_INIT_FN(970);
e9df014c 61
3fc6c082
FB		 62/* Generic callbacks:
63 * do nothing but store/retrieve spr value
64 */
04f20795 65#ifdef PPC_DUMP_SPR_ACCESSES
3fc6c082
FB		 66static void spr_read_generic (void *opaque, int sprn)
67{
04f20795 68 gen_op_load_dump_spr(sprn);
3fc6c082
FB		 69}
70
71static void spr_write_generic (void *opaque, int sprn)
72{
04f20795 73 gen_op_store_dump_spr(sprn);
3fc6c082 74}
04f20795
JM		 75#else
76static void spr_read_generic (void *opaque, int sprn)
a496775f 77{
04f20795 78 gen_op_load_spr(sprn);
a496775f
JM		 79}
80
04f20795 81static void spr_write_generic (void *opaque, int sprn)
a496775f 82{
04f20795 83 gen_op_store_spr(sprn);
a496775f 84}
04f20795 85#endif
a496775f
JM		 86
87#if !defined(CONFIG_USER_ONLY)
88static void spr_write_clear (void *opaque, int sprn)
89{
90 gen_op_mask_spr(sprn);
91}
92#endif
93
76a66253 94/* SPR common to all PowerPC */
3fc6c082
FB		 95/* XER */
96static void spr_read_xer (void *opaque, int sprn)
97{
98 gen_op_load_xer();
99}
100
101static void spr_write_xer (void *opaque, int sprn)
102{
103 gen_op_store_xer();
104}
105
106/* LR */
107static void spr_read_lr (void *opaque, int sprn)
108{
109 gen_op_load_lr();
110}
111
112static void spr_write_lr (void *opaque, int sprn)
113{
114 gen_op_store_lr();
115}
116
117/* CTR */
118static void spr_read_ctr (void *opaque, int sprn)
119{
120 gen_op_load_ctr();
121}
122
123static void spr_write_ctr (void *opaque, int sprn)
124{
125 gen_op_store_ctr();
126}
127
128/* User read access to SPR */
129/* USPRx */
130/* UMMCRx */
131/* UPMCx */
132/* USIA */
133/* UDECR */
134static void spr_read_ureg (void *opaque, int sprn)
135{
136 gen_op_load_spr(sprn + 0x10);
137}
138
76a66253 139/* SPR common to all non-embedded PowerPC */
3fc6c082 140/* DECR */
76a66253 141#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 142static void spr_read_decr (void *opaque, int sprn)
143{
144 gen_op_load_decr();
145}
146
147static void spr_write_decr (void *opaque, int sprn)
148{
149 gen_op_store_decr();
150}
76a66253 151#endif
3fc6c082 152
76a66253 153/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082
FB		 154/* Time base */
155static void spr_read_tbl (void *opaque, int sprn)
156{
157 gen_op_load_tbl();
158}
159
76a66253 160static void spr_read_tbu (void *opaque, int sprn)
3fc6c082 161{
76a66253 162 gen_op_load_tbu();
3fc6c082
FB		 163}
164
a062e36c
JM		 165__attribute__ (( unused ))
166static void spr_read_atbl (void *opaque, int sprn)
167{
168 gen_op_load_atbl();
169}
170
171__attribute__ (( unused ))
172static void spr_read_atbu (void *opaque, int sprn)
173{
174 gen_op_load_atbu();
175}
176
76a66253
JM		 177#if !defined(CONFIG_USER_ONLY)
178static void spr_write_tbl (void *opaque, int sprn)
3fc6c082 179{
76a66253 180 gen_op_store_tbl();
3fc6c082
FB		 181}
182
183static void spr_write_tbu (void *opaque, int sprn)
184{
185 gen_op_store_tbu();
186}
a062e36c
JM		 187
188__attribute__ (( unused ))
189static void spr_write_atbl (void *opaque, int sprn)
190{
191 gen_op_store_atbl();
192}
193
194__attribute__ (( unused ))
195static void spr_write_atbu (void *opaque, int sprn)
196{
197 gen_op_store_atbu();
198}
76a66253 199#endif
3fc6c082 200
76a66253 201#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 202/* IBAT0U...IBAT0U */
203/* IBAT0L...IBAT7L */
204static void spr_read_ibat (void *opaque, int sprn)
205{
206 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
207}
208
209static void spr_read_ibat_h (void *opaque, int sprn)
210{
211 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
212}
213
214static void spr_write_ibatu (void *opaque, int sprn)
215{
3fc6c082 216 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
3fc6c082
FB		 217}
218
219static void spr_write_ibatu_h (void *opaque, int sprn)
220{
3fc6c082 221 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
3fc6c082
FB		 222}
223
224static void spr_write_ibatl (void *opaque, int sprn)
225{
3fc6c082 226 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
3fc6c082
FB		 227}
228
229static void spr_write_ibatl_h (void *opaque, int sprn)
230{
3fc6c082 231 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
3fc6c082
FB		 232}
233
234/* DBAT0U...DBAT7U */
235/* DBAT0L...DBAT7L */
236static void spr_read_dbat (void *opaque, int sprn)
237{
238 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
239}
240
241static void spr_read_dbat_h (void *opaque, int sprn)
242{
243 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
244}
245
246static void spr_write_dbatu (void *opaque, int sprn)
247{
3fc6c082 248 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
3fc6c082
FB		 249}
250
251static void spr_write_dbatu_h (void *opaque, int sprn)
252{
3fc6c082 253 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
3fc6c082
FB		 254}
255
256static void spr_write_dbatl (void *opaque, int sprn)
257{
3fc6c082 258 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
3fc6c082
FB		 259}
260
261static void spr_write_dbatl_h (void *opaque, int sprn)
262{
3fc6c082 263 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
3fc6c082
FB		 264}
265
266/* SDR1 */
267static void spr_read_sdr1 (void *opaque, int sprn)
268{
269 gen_op_load_sdr1();
270}
271
272static void spr_write_sdr1 (void *opaque, int sprn)
273{
3fc6c082 274 gen_op_store_sdr1();
3fc6c082
FB		 275}
276
76a66253
JM		 277/* 64 bits PowerPC specific SPRs */
278/* ASR */
578bb252
JM		 279#if defined(TARGET_PPC64)
280__attribute__ (( unused ))
76a66253
JM		 281static void spr_read_asr (void *opaque, int sprn)
282{
283 gen_op_load_asr();
284}
285
578bb252 286__attribute__ (( unused ))
76a66253
JM		 287static void spr_write_asr (void *opaque, int sprn)
288{
76a66253 289 gen_op_store_asr();
76a66253
JM		 290}
291#endif
a750fc0b 292#endif
76a66253
JM		 293
294/* PowerPC 601 specific registers */
295/* RTC */
296static void spr_read_601_rtcl (void *opaque, int sprn)
297{
298 gen_op_load_601_rtcl();
299}
300
301static void spr_read_601_rtcu (void *opaque, int sprn)
302{
303 gen_op_load_601_rtcu();
304}
305
306#if !defined(CONFIG_USER_ONLY)
307static void spr_write_601_rtcu (void *opaque, int sprn)
308{
309 gen_op_store_601_rtcu();
310}
311
312static void spr_write_601_rtcl (void *opaque, int sprn)
313{
314 gen_op_store_601_rtcl();
315}
316#endif
317
318/* Unified bats */
319#if !defined(CONFIG_USER_ONLY)
320static void spr_read_601_ubat (void *opaque, int sprn)
321{
322 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
323}
324
325static void spr_write_601_ubatu (void *opaque, int sprn)
326{
76a66253 327 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
76a66253
JM		 328}
329
330static void spr_write_601_ubatl (void *opaque, int sprn)
331{
76a66253 332 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
76a66253
JM		 333}
334#endif
335
336/* PowerPC 40x specific registers */
337#if !defined(CONFIG_USER_ONLY)
338static void spr_read_40x_pit (void *opaque, int sprn)
339{
340 gen_op_load_40x_pit();
341}
342
343static void spr_write_40x_pit (void *opaque, int sprn)
344{
345 gen_op_store_40x_pit();
346}
347
8ecc7913
JM		 348static void spr_write_40x_dbcr0 (void *opaque, int sprn)
349{
350 DisasContext *ctx = opaque;
351
352 gen_op_store_40x_dbcr0();
353 /* We must stop translation as we may have rebooted */
e1833e1f 354 GEN_STOP(ctx);
8ecc7913
JM		 355}
356
c294fc58
JM		 357static void spr_write_40x_sler (void *opaque, int sprn)
358{
c294fc58 359 gen_op_store_40x_sler();
c294fc58
JM		 360}
361
76a66253
JM		 362static void spr_write_booke_tcr (void *opaque, int sprn)
363{
364 gen_op_store_booke_tcr();
365}
366
367static void spr_write_booke_tsr (void *opaque, int sprn)
368{
369 gen_op_store_booke_tsr();
370}
371#endif
372
373/* PowerPC 403 specific registers */
374/* PBL1 / PBU1 / PBL2 / PBU2 */
375#if !defined(CONFIG_USER_ONLY)
376static void spr_read_403_pbr (void *opaque, int sprn)
377{
378 gen_op_load_403_pb(sprn - SPR_403_PBL1);
379}
380
381static void spr_write_403_pbr (void *opaque, int sprn)
382{
76a66253 383 gen_op_store_403_pb(sprn - SPR_403_PBL1);
76a66253
JM		 384}
385
3fc6c082
FB		 386static void spr_write_pir (void *opaque, int sprn)
387{
388 gen_op_store_pir();
389}
76a66253 390#endif
3fc6c082 391
6f5d427d
JM		 392#if !defined(CONFIG_USER_ONLY)
393/* Callback used to write the exception vector base */
394static void spr_write_excp_prefix (void *opaque, int sprn)
395{
396 gen_op_store_excp_prefix();
397 gen_op_store_spr(sprn);
398}
399
400static void spr_write_excp_vector (void *opaque, int sprn)
401{
402 DisasContext *ctx = opaque;
403
404 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
405 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
406 gen_op_store_spr(sprn);
407 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
408 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
409 gen_op_store_spr(sprn);
410 } else {
411 printf("Trying to write an unknown exception vector %d %03x\n",
412 sprn, sprn);
413 GEN_EXCP_PRIVREG(ctx);
414 }
415}
416#endif
417
76a66253
JM		 418#if defined(CONFIG_USER_ONLY)
419#define spr_register(env, num, name, uea_read, uea_write, \
420 oea_read, oea_write, initial_value) \
421do { \
422 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
423} while (0)
424static inline void _spr_register (CPUPPCState *env, int num,
425 const unsigned char *name,
426 void (*uea_read)(void *opaque, int sprn),
427 void (*uea_write)(void *opaque, int sprn),
428 target_ulong initial_value)
429#else
3fc6c082
FB		 430static inline void spr_register (CPUPPCState *env, int num,
431 const unsigned char *name,
432 void (*uea_read)(void *opaque, int sprn),
433 void (*uea_write)(void *opaque, int sprn),
434 void (*oea_read)(void *opaque, int sprn),
435 void (*oea_write)(void *opaque, int sprn),
436 target_ulong initial_value)
76a66253 437#endif
3fc6c082
FB		 438{
439 ppc_spr_t *spr;
440
441 spr = &env->spr_cb[num];
442 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 443#if !defined(CONFIG_USER_ONLY)
444 spr->oea_read != NULL || spr->oea_write != NULL ||
445#endif
446 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 447 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
448 exit(1);
449 }
450#if defined(PPC_DEBUG_SPR)
1b9eb036 451 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 452 initial_value);
3fc6c082
FB		 453#endif
454 spr->name = name;
455 spr->uea_read = uea_read;
456 spr->uea_write = uea_write;
76a66253 457#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 458 spr->oea_read = oea_read;
459 spr->oea_write = oea_write;
76a66253 460#endif
3fc6c082
FB		 461 env->spr[num] = initial_value;
462}
463
464/* Generic PowerPC SPRs */
465static void gen_spr_generic (CPUPPCState *env)
466{
467 /* Integer processing */
468 spr_register(env, SPR_XER, "XER",
469 &spr_read_xer, &spr_write_xer,
470 &spr_read_xer, &spr_write_xer,
471 0x00000000);
472 /* Branch contol */
473 spr_register(env, SPR_LR, "LR",
474 &spr_read_lr, &spr_write_lr,
475 &spr_read_lr, &spr_write_lr,
476 0x00000000);
477 spr_register(env, SPR_CTR, "CTR",
478 &spr_read_ctr, &spr_write_ctr,
479 &spr_read_ctr, &spr_write_ctr,
480 0x00000000);
481 /* Interrupt processing */
482 spr_register(env, SPR_SRR0, "SRR0",
483 SPR_NOACCESS, SPR_NOACCESS,
484 &spr_read_generic, &spr_write_generic,
485 0x00000000);
486 spr_register(env, SPR_SRR1, "SRR1",
487 SPR_NOACCESS, SPR_NOACCESS,
488 &spr_read_generic, &spr_write_generic,
489 0x00000000);
490 /* Processor control */
491 spr_register(env, SPR_SPRG0, "SPRG0",
492 SPR_NOACCESS, SPR_NOACCESS,
493 &spr_read_generic, &spr_write_generic,
494 0x00000000);
495 spr_register(env, SPR_SPRG1, "SPRG1",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499 spr_register(env, SPR_SPRG2, "SPRG2",
500 SPR_NOACCESS, SPR_NOACCESS,
501 &spr_read_generic, &spr_write_generic,
502 0x00000000);
503 spr_register(env, SPR_SPRG3, "SPRG3",
504 SPR_NOACCESS, SPR_NOACCESS,
505 &spr_read_generic, &spr_write_generic,
506 0x00000000);
507}
508
509/* SPR common to all non-embedded PowerPC, including 601 */
510static void gen_spr_ne_601 (CPUPPCState *env)
511{
512 /* Exception processing */
513 spr_register(env, SPR_DSISR, "DSISR",
514 SPR_NOACCESS, SPR_NOACCESS,
515 &spr_read_generic, &spr_write_generic,
516 0x00000000);
517 spr_register(env, SPR_DAR, "DAR",
518 SPR_NOACCESS, SPR_NOACCESS,
519 &spr_read_generic, &spr_write_generic,
520 0x00000000);
521 /* Timer */
522 spr_register(env, SPR_DECR, "DECR",
523 SPR_NOACCESS, SPR_NOACCESS,
524 &spr_read_decr, &spr_write_decr,
525 0x00000000);
526 /* Memory management */
527 spr_register(env, SPR_SDR1, "SDR1",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_sdr1, &spr_write_sdr1,
530 0x00000000);
531}
532
533/* BATs 0-3 */
534static void gen_low_BATs (CPUPPCState *env)
535{
f2e63a42 536#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 537 spr_register(env, SPR_IBAT0U, "IBAT0U",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_ibat, &spr_write_ibatu,
540 0x00000000);
541 spr_register(env, SPR_IBAT0L, "IBAT0L",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_ibat, &spr_write_ibatl,
544 0x00000000);
545 spr_register(env, SPR_IBAT1U, "IBAT1U",
546 SPR_NOACCESS, SPR_NOACCESS,
547 &spr_read_ibat, &spr_write_ibatu,
548 0x00000000);
549 spr_register(env, SPR_IBAT1L, "IBAT1L",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_ibat, &spr_write_ibatl,
552 0x00000000);
553 spr_register(env, SPR_IBAT2U, "IBAT2U",
554 SPR_NOACCESS, SPR_NOACCESS,
555 &spr_read_ibat, &spr_write_ibatu,
556 0x00000000);
557 spr_register(env, SPR_IBAT2L, "IBAT2L",
558 SPR_NOACCESS, SPR_NOACCESS,
559 &spr_read_ibat, &spr_write_ibatl,
560 0x00000000);
561 spr_register(env, SPR_IBAT3U, "IBAT3U",
562 SPR_NOACCESS, SPR_NOACCESS,
563 &spr_read_ibat, &spr_write_ibatu,
564 0x00000000);
565 spr_register(env, SPR_IBAT3L, "IBAT3L",
566 SPR_NOACCESS, SPR_NOACCESS,
567 &spr_read_ibat, &spr_write_ibatl,
568 0x00000000);
569 spr_register(env, SPR_DBAT0U, "DBAT0U",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_dbat, &spr_write_dbatu,
572 0x00000000);
573 spr_register(env, SPR_DBAT0L, "DBAT0L",
574 SPR_NOACCESS, SPR_NOACCESS,
575 &spr_read_dbat, &spr_write_dbatl,
576 0x00000000);
577 spr_register(env, SPR_DBAT1U, "DBAT1U",
578 SPR_NOACCESS, SPR_NOACCESS,
579 &spr_read_dbat, &spr_write_dbatu,
580 0x00000000);
581 spr_register(env, SPR_DBAT1L, "DBAT1L",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_dbat, &spr_write_dbatl,
584 0x00000000);
585 spr_register(env, SPR_DBAT2U, "DBAT2U",
586 SPR_NOACCESS, SPR_NOACCESS,
587 &spr_read_dbat, &spr_write_dbatu,
588 0x00000000);
589 spr_register(env, SPR_DBAT2L, "DBAT2L",
590 SPR_NOACCESS, SPR_NOACCESS,
591 &spr_read_dbat, &spr_write_dbatl,
592 0x00000000);
593 spr_register(env, SPR_DBAT3U, "DBAT3U",
594 SPR_NOACCESS, SPR_NOACCESS,
595 &spr_read_dbat, &spr_write_dbatu,
596 0x00000000);
597 spr_register(env, SPR_DBAT3L, "DBAT3L",
598 SPR_NOACCESS, SPR_NOACCESS,
599 &spr_read_dbat, &spr_write_dbatl,
600 0x00000000);
a750fc0b 601 env->nb_BATs += 4;
f2e63a42 602#endif
3fc6c082
FB		 603}
604
605/* BATs 4-7 */
606static void gen_high_BATs (CPUPPCState *env)
607{
f2e63a42 608#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 609 spr_register(env, SPR_IBAT4U, "IBAT4U",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_ibat_h, &spr_write_ibatu_h,
612 0x00000000);
613 spr_register(env, SPR_IBAT4L, "IBAT4L",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_ibat_h, &spr_write_ibatl_h,
616 0x00000000);
617 spr_register(env, SPR_IBAT5U, "IBAT5U",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_ibat_h, &spr_write_ibatu_h,
620 0x00000000);
621 spr_register(env, SPR_IBAT5L, "IBAT5L",
622 SPR_NOACCESS, SPR_NOACCESS,
623 &spr_read_ibat_h, &spr_write_ibatl_h,
624 0x00000000);
625 spr_register(env, SPR_IBAT6U, "IBAT6U",
626 SPR_NOACCESS, SPR_NOACCESS,
627 &spr_read_ibat_h, &spr_write_ibatu_h,
628 0x00000000);
629 spr_register(env, SPR_IBAT6L, "IBAT6L",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_ibat_h, &spr_write_ibatl_h,
632 0x00000000);
633 spr_register(env, SPR_IBAT7U, "IBAT7U",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_ibat_h, &spr_write_ibatu_h,
636 0x00000000);
637 spr_register(env, SPR_IBAT7L, "IBAT7L",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_ibat_h, &spr_write_ibatl_h,
640 0x00000000);
641 spr_register(env, SPR_DBAT4U, "DBAT4U",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_dbat_h, &spr_write_dbatu_h,
644 0x00000000);
645 spr_register(env, SPR_DBAT4L, "DBAT4L",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_dbat_h, &spr_write_dbatl_h,
648 0x00000000);
649 spr_register(env, SPR_DBAT5U, "DBAT5U",
650 SPR_NOACCESS, SPR_NOACCESS,
651 &spr_read_dbat_h, &spr_write_dbatu_h,
652 0x00000000);
653 spr_register(env, SPR_DBAT5L, "DBAT5L",
654 SPR_NOACCESS, SPR_NOACCESS,
655 &spr_read_dbat_h, &spr_write_dbatl_h,
656 0x00000000);
657 spr_register(env, SPR_DBAT6U, "DBAT6U",
658 SPR_NOACCESS, SPR_NOACCESS,
659 &spr_read_dbat_h, &spr_write_dbatu_h,
660 0x00000000);
661 spr_register(env, SPR_DBAT6L, "DBAT6L",
662 SPR_NOACCESS, SPR_NOACCESS,
663 &spr_read_dbat_h, &spr_write_dbatl_h,
664 0x00000000);
665 spr_register(env, SPR_DBAT7U, "DBAT7U",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_dbat_h, &spr_write_dbatu_h,
668 0x00000000);
669 spr_register(env, SPR_DBAT7L, "DBAT7L",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_dbat_h, &spr_write_dbatl_h,
672 0x00000000);
a750fc0b 673 env->nb_BATs += 4;
f2e63a42 674#endif
3fc6c082
FB		 675}
676
677/* Generic PowerPC time base */
678static void gen_tbl (CPUPPCState *env)
679{
680 spr_register(env, SPR_VTBL, "TBL",
681 &spr_read_tbl, SPR_NOACCESS,
682 &spr_read_tbl, SPR_NOACCESS,
683 0x00000000);
684 spr_register(env, SPR_TBL, "TBL",
685 SPR_NOACCESS, SPR_NOACCESS,
686 SPR_NOACCESS, &spr_write_tbl,
687 0x00000000);
688 spr_register(env, SPR_VTBU, "TBU",
689 &spr_read_tbu, SPR_NOACCESS,
690 &spr_read_tbu, SPR_NOACCESS,
691 0x00000000);
692 spr_register(env, SPR_TBU, "TBU",
693 SPR_NOACCESS, SPR_NOACCESS,
694 SPR_NOACCESS, &spr_write_tbu,
695 0x00000000);
696}
697
76a66253
JM		 698/* Softare table search registers */
699static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
700{
f2e63a42 701#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 702 env->nb_tlb = nb_tlbs;
703 env->nb_ways = nb_ways;
704 env->id_tlbs = 1;
705 spr_register(env, SPR_DMISS, "DMISS",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, SPR_NOACCESS,
708 0x00000000);
709 spr_register(env, SPR_DCMP, "DCMP",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, SPR_NOACCESS,
712 0x00000000);
713 spr_register(env, SPR_HASH1, "HASH1",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_generic, SPR_NOACCESS,
716 0x00000000);
717 spr_register(env, SPR_HASH2, "HASH2",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_generic, SPR_NOACCESS,
720 0x00000000);
721 spr_register(env, SPR_IMISS, "IMISS",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_generic, SPR_NOACCESS,
724 0x00000000);
725 spr_register(env, SPR_ICMP, "ICMP",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, SPR_NOACCESS,
728 0x00000000);
729 spr_register(env, SPR_RPA, "RPA",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
f2e63a42 733#endif
76a66253
JM		 734}
735
736/* SPR common to MPC755 and G2 */
737static void gen_spr_G2_755 (CPUPPCState *env)
738{
739 /* SGPRs */
740 spr_register(env, SPR_SPRG4, "SPRG4",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 spr_register(env, SPR_SPRG5, "SPRG5",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_generic, &spr_write_generic,
747 0x00000000);
748 spr_register(env, SPR_SPRG6, "SPRG6",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
751 0x00000000);
752 spr_register(env, SPR_SPRG7, "SPRG7",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_generic, &spr_write_generic,
755 0x00000000);
756 /* External access control */
757 /* XXX : not implemented */
758 spr_register(env, SPR_EAR, "EAR",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_generic,
761 0x00000000);
762}
763
3fc6c082
FB		 764/* SPR common to all 7xx PowerPC implementations */
765static void gen_spr_7xx (CPUPPCState *env)
766{
767 /* Breakpoints */
768 /* XXX : not implemented */
769 spr_register(env, SPR_DABR, "DABR",
770 SPR_NOACCESS, SPR_NOACCESS,
771 &spr_read_generic, &spr_write_generic,
772 0x00000000);
773 /* XXX : not implemented */
774 spr_register(env, SPR_IABR, "IABR",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, &spr_write_generic,
777 0x00000000);
778 /* Cache management */
779 /* XXX : not implemented */
780 spr_register(env, SPR_ICTC, "ICTC",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_generic,
783 0x00000000);
76a66253
JM		 784 /* XXX : not implemented */
785 spr_register(env, SPR_L2CR, "L2CR",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_generic,
788 0x00000000);
3fc6c082
FB		 789 /* Performance monitors */
790 /* XXX : not implemented */
791 spr_register(env, SPR_MMCR0, "MMCR0",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_generic, &spr_write_generic,
794 0x00000000);
795 /* XXX : not implemented */
796 spr_register(env, SPR_MMCR1, "MMCR1",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_generic, &spr_write_generic,
799 0x00000000);
800 /* XXX : not implemented */
801 spr_register(env, SPR_PMC1, "PMC1",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_generic, &spr_write_generic,
804 0x00000000);
805 /* XXX : not implemented */
806 spr_register(env, SPR_PMC2, "PMC2",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
810 /* XXX : not implemented */
811 spr_register(env, SPR_PMC3, "PMC3",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_generic, &spr_write_generic,
814 0x00000000);
815 /* XXX : not implemented */
816 spr_register(env, SPR_PMC4, "PMC4",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_generic, &spr_write_generic,
819 0x00000000);
820 /* XXX : not implemented */
a750fc0b 821 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_generic, SPR_NOACCESS,
824 0x00000000);
578bb252 825 /* XXX : not implemented */
3fc6c082
FB		 826 spr_register(env, SPR_UMMCR0, "UMMCR0",
827 &spr_read_ureg, SPR_NOACCESS,
828 &spr_read_ureg, SPR_NOACCESS,
829 0x00000000);
578bb252 830 /* XXX : not implemented */
3fc6c082
FB		 831 spr_register(env, SPR_UMMCR1, "UMMCR1",
832 &spr_read_ureg, SPR_NOACCESS,
833 &spr_read_ureg, SPR_NOACCESS,
834 0x00000000);
578bb252 835 /* XXX : not implemented */
3fc6c082
FB		 836 spr_register(env, SPR_UPMC1, "UPMC1",
837 &spr_read_ureg, SPR_NOACCESS,
838 &spr_read_ureg, SPR_NOACCESS,
839 0x00000000);
578bb252 840 /* XXX : not implemented */
3fc6c082
FB		 841 spr_register(env, SPR_UPMC2, "UPMC2",
842 &spr_read_ureg, SPR_NOACCESS,
843 &spr_read_ureg, SPR_NOACCESS,
844 0x00000000);
578bb252 845 /* XXX : not implemented */
3fc6c082
FB		 846 spr_register(env, SPR_UPMC3, "UPMC3",
847 &spr_read_ureg, SPR_NOACCESS,
848 &spr_read_ureg, SPR_NOACCESS,
849 0x00000000);
578bb252 850 /* XXX : not implemented */
3fc6c082
FB		 851 spr_register(env, SPR_UPMC4, "UPMC4",
852 &spr_read_ureg, SPR_NOACCESS,
853 &spr_read_ureg, SPR_NOACCESS,
854 0x00000000);
578bb252 855 /* XXX : not implemented */
a750fc0b 856 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 857 &spr_read_ureg, SPR_NOACCESS,
858 &spr_read_ureg, SPR_NOACCESS,
859 0x00000000);
a750fc0b 860 /* External access control */
3fc6c082 861 /* XXX : not implemented */
a750fc0b 862 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_generic, &spr_write_generic,
865 0x00000000);
a750fc0b
JM		 866}
867
868static void gen_spr_thrm (CPUPPCState *env)
869{
870 /* Thermal management */
3fc6c082 871 /* XXX : not implemented */
a750fc0b 872 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876 /* XXX : not implemented */
a750fc0b 877 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, &spr_write_generic,
880 0x00000000);
3fc6c082 881 /* XXX : not implemented */
a750fc0b 882 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
885 0x00000000);
886}
887
888/* SPR specific to PowerPC 604 implementation */
889static void gen_spr_604 (CPUPPCState *env)
890{
891 /* Processor identification */
892 spr_register(env, SPR_PIR, "PIR",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_pir,
895 0x00000000);
896 /* Breakpoints */
897 /* XXX : not implemented */
898 spr_register(env, SPR_IABR, "IABR",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_generic, &spr_write_generic,
901 0x00000000);
902 /* XXX : not implemented */
903 spr_register(env, SPR_DABR, "DABR",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 /* Performance counters */
908 /* XXX : not implemented */
909 spr_register(env, SPR_MMCR0, "MMCR0",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 /* XXX : not implemented */
914 spr_register(env, SPR_MMCR1, "MMCR1",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 /* XXX : not implemented */
919 spr_register(env, SPR_PMC1, "PMC1",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 /* XXX : not implemented */
924 spr_register(env, SPR_PMC2, "PMC2",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* XXX : not implemented */
929 spr_register(env, SPR_PMC3, "PMC3",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933 /* XXX : not implemented */
934 spr_register(env, SPR_PMC4, "PMC4",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938 /* XXX : not implemented */
a750fc0b 939 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, SPR_NOACCESS,
942 0x00000000);
943 /* XXX : not implemented */
944 spr_register(env, SPR_SDA, "SDA",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, SPR_NOACCESS,
947 0x00000000);
948 /* External access control */
949 /* XXX : not implemented */
950 spr_register(env, SPR_EAR, "EAR",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954}
955
76a66253
JM		 956/* SPR specific to PowerPC 603 implementation */
957static void gen_spr_603 (CPUPPCState *env)
3fc6c082 958{
76a66253
JM		 959 /* External access control */
960 /* XXX : not implemented */
961 spr_register(env, SPR_EAR, "EAR",
3fc6c082 962 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
3fc6c082
FB		 965}
966
76a66253
JM		 967/* SPR specific to PowerPC G2 implementation */
968static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 969{
76a66253
JM		 970 /* Memory base address */
971 /* MBAR */
578bb252 972 /* XXX : not implemented */
76a66253
JM		 973 spr_register(env, SPR_MBAR, "MBAR",
974 SPR_NOACCESS, SPR_NOACCESS,
975 &spr_read_generic, &spr_write_generic,
976 0x00000000);
977 /* System version register */
978 /* SVR */
578bb252 979 /* XXX : TODO: initialize it to an appropriate value */
76a66253
JM		 980 spr_register(env, SPR_SVR, "SVR",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, SPR_NOACCESS,
983 0x00000000);
984 /* Exception processing */
363be49c 985 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_generic,
988 0x00000000);
363be49c 989 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, &spr_write_generic,
992 0x00000000);
993 /* Breakpoints */
994 /* XXX : not implemented */
995 spr_register(env, SPR_DABR, "DABR",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 /* XXX : not implemented */
1000 spr_register(env, SPR_DABR2, "DABR2",
1001 SPR_NOACCESS, SPR_NOACCESS,
1002 &spr_read_generic, &spr_write_generic,
1003 0x00000000);
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_IABR, "IABR",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_IABR2, "IABR2",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014 /* XXX : not implemented */
1015 spr_register(env, SPR_IBCR, "IBCR",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019 /* XXX : not implemented */
1020 spr_register(env, SPR_DBCR, "DBCR",
1021 SPR_NOACCESS, SPR_NOACCESS,
1022 &spr_read_generic, &spr_write_generic,
1023 0x00000000);
1024}
1025
1026/* SPR specific to PowerPC 602 implementation */
1027static void gen_spr_602 (CPUPPCState *env)
1028{
1029 /* ESA registers */
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_SER, "SER",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_SEBR, "SEBR",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 /* XXX : not implemented */
a750fc0b 1041 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* Floating point status */
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_SP, "SP",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_LT, "LT",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* Watchdog timer */
1057 /* XXX : not implemented */
1058 spr_register(env, SPR_TCR, "TCR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062 /* Interrupt base */
1063 spr_register(env, SPR_IBR, "IBR",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, &spr_write_generic,
1066 0x00000000);
a750fc0b
JM		 1067 /* XXX : not implemented */
1068 spr_register(env, SPR_IABR, "IABR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
76a66253
JM		 1072}
1073
1074/* SPR specific to PowerPC 601 implementation */
1075static void gen_spr_601 (CPUPPCState *env)
1076{
1077 /* Multiplication/division register */
1078 /* MQ */
1079 spr_register(env, SPR_MQ, "MQ",
1080 &spr_read_generic, &spr_write_generic,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 /* RTC registers */
1084 spr_register(env, SPR_601_RTCU, "RTCU",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 SPR_NOACCESS, &spr_write_601_rtcu,
1087 0x00000000);
1088 spr_register(env, SPR_601_VRTCU, "RTCU",
1089 &spr_read_601_rtcu, SPR_NOACCESS,
1090 &spr_read_601_rtcu, SPR_NOACCESS,
1091 0x00000000);
1092 spr_register(env, SPR_601_RTCL, "RTCL",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 SPR_NOACCESS, &spr_write_601_rtcl,
1095 0x00000000);
1096 spr_register(env, SPR_601_VRTCL, "RTCL",
1097 &spr_read_601_rtcl, SPR_NOACCESS,
1098 &spr_read_601_rtcl, SPR_NOACCESS,
1099 0x00000000);
1100 /* Timer */
1101#if 0 /* ? */
1102 spr_register(env, SPR_601_UDECR, "UDECR",
1103 &spr_read_decr, SPR_NOACCESS,
1104 &spr_read_decr, SPR_NOACCESS,
1105 0x00000000);
1106#endif
1107 /* External access control */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_EAR, "EAR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* Memory management */
f2e63a42 1114#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1115 spr_register(env, SPR_IBAT0U, "IBAT0U",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_601_ubat, &spr_write_601_ubatu,
1118 0x00000000);
1119 spr_register(env, SPR_IBAT0L, "IBAT0L",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_601_ubat, &spr_write_601_ubatl,
1122 0x00000000);
1123 spr_register(env, SPR_IBAT1U, "IBAT1U",
1124 SPR_NOACCESS, SPR_NOACCESS,
1125 &spr_read_601_ubat, &spr_write_601_ubatu,
1126 0x00000000);
1127 spr_register(env, SPR_IBAT1L, "IBAT1L",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_601_ubat, &spr_write_601_ubatl,
1130 0x00000000);
1131 spr_register(env, SPR_IBAT2U, "IBAT2U",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_601_ubat, &spr_write_601_ubatu,
1134 0x00000000);
1135 spr_register(env, SPR_IBAT2L, "IBAT2L",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_601_ubat, &spr_write_601_ubatl,
1138 0x00000000);
1139 spr_register(env, SPR_IBAT3U, "IBAT3U",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_601_ubat, &spr_write_601_ubatu,
1142 0x00000000);
1143 spr_register(env, SPR_IBAT3L, "IBAT3L",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_601_ubat, &spr_write_601_ubatl,
1146 0x00000000);
a750fc0b 1147 env->nb_BATs = 4;
f2e63a42 1148#endif
a750fc0b
JM		 1149}
1150
1151static void gen_spr_74xx (CPUPPCState *env)
1152{
1153 /* Processor identification */
1154 spr_register(env, SPR_PIR, "PIR",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_pir,
1157 0x00000000);
1158 /* XXX : not implemented */
1159 spr_register(env, SPR_MMCR2, "MMCR2",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, &spr_write_generic,
1162 0x00000000);
578bb252 1163 /* XXX : not implemented */
a750fc0b
JM		 1164 spr_register(env, SPR_UMMCR2, "UMMCR2",
1165 &spr_read_ureg, SPR_NOACCESS,
1166 &spr_read_ureg, SPR_NOACCESS,
1167 0x00000000);
1168 /* XXX: not implemented */
1169 spr_register(env, SPR_BAMR, "BAMR",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
578bb252 1173 /* XXX : not implemented */
a750fc0b
JM		 1174 spr_register(env, SPR_UBAMR, "UBAMR",
1175 &spr_read_ureg, SPR_NOACCESS,
1176 &spr_read_ureg, SPR_NOACCESS,
1177 0x00000000);
578bb252 1178 /* XXX : not implemented */
a750fc0b
JM		 1179 spr_register(env, SPR_MSSCR0, "MSSCR0",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 /* Hardware implementation registers */
1184 /* XXX : not implemented */
1185 spr_register(env, SPR_HID0, "HID0",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* XXX : not implemented */
1190 spr_register(env, SPR_HID1, "HID1",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* Altivec */
1195 spr_register(env, SPR_VRSAVE, "VRSAVE",
1196 &spr_read_generic, &spr_write_generic,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199}
1200
a750fc0b
JM		 1201static void gen_l3_ctrl (CPUPPCState *env)
1202{
1203 /* L3CR */
1204 /* XXX : not implemented */
1205 spr_register(env, SPR_L3CR, "L3CR",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 /* L3ITCR0 */
578bb252 1210 /* XXX : not implemented */
a750fc0b
JM		 1211 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* L3ITCR1 */
578bb252 1216 /* XXX : not implemented */
a750fc0b
JM		 1217 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 0x00000000);
1221 /* L3ITCR2 */
578bb252 1222 /* XXX : not implemented */
a750fc0b
JM		 1223 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 /* L3ITCR3 */
578bb252 1228 /* XXX : not implemented */
a750fc0b
JM		 1229 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_generic, &spr_write_generic,
1232 0x00000000);
1233 /* L3OHCR */
578bb252 1234 /* XXX : not implemented */
a750fc0b
JM		 1235 spr_register(env, SPR_L3OHCR, "L3OHCR",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239 /* L3PM */
578bb252 1240 /* XXX : not implemented */
a750fc0b
JM		 1241 spr_register(env, SPR_L3PM, "L3PM",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245}
a750fc0b 1246
578bb252 1247static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1248{
f2e63a42 1249#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1250 env->nb_tlb = nb_tlbs;
1251 env->nb_ways = nb_ways;
1252 env->id_tlbs = 1;
1253 /* XXX : not implemented */
a750fc0b
JM		 1254 spr_register(env, SPR_PTEHI, "PTEHI",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
578bb252 1258 /* XXX : not implemented */
a750fc0b
JM		 1259 spr_register(env, SPR_PTELO, "PTELO",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
578bb252 1263 /* XXX : not implemented */
a750fc0b
JM		 1264 spr_register(env, SPR_TLBMISS, "TLBMISS",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
f2e63a42 1268#endif
76a66253
JM		 1269}
1270
1271/* PowerPC BookE SPR */
1272static void gen_spr_BookE (CPUPPCState *env)
1273{
1274 /* Processor identification */
1275 spr_register(env, SPR_BOOKE_PIR, "PIR",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_generic, &spr_write_pir,
1278 0x00000000);
1279 /* Interrupt processing */
363be49c 1280 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1283 0x00000000);
363be49c
JM		 1284 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
2662a059 1288#if 0
363be49c
JM		 1289 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 &spr_read_generic, &spr_write_generic,
1296 0x00000000);
2662a059 1297#endif
76a66253
JM		 1298 /* Debug */
1299 /* XXX : not implemented */
1300 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* XXX : not implemented */
1310 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* XXX : not implemented */
1315 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* XXX : not implemented */
1320 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324 /* XXX : not implemented */
1325 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* XXX : not implemented */
1335 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339 /* XXX : not implemented */
1340 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
1344 /* XXX : not implemented */
1345 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1356 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1357 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1358 0x00000000);
1359 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363 spr_register(env, SPR_BOOKE_ESR, "ESR",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
363be49c
JM		 1367 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1368 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1369 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1370 0x00000000);
1371 /* Exception vectors */
76a66253
JM		 1372 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1373 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1374 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1375 0x00000000);
1376 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1377 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1378 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1379 0x00000000);
1380 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1381 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1382 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1383 0x00000000);
1384 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1385 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1386 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1387 0x00000000);
1388 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1389 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1390 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1391 0x00000000);
1392 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1393 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1394 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1395 0x00000000);
1396 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1397 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1398 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1399 0x00000000);
1400 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1401 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1402 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1403 0x00000000);
1404 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1405 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1406 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1407 0x00000000);
1408 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1409 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1410 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1411 0x00000000);
1412 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1413 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1414 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1415 0x00000000);
1416 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1417 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1418 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1419 0x00000000);
1420 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1421 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1422 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1423 0x00000000);
1424 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1425 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1426 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1427 0x00000000);
1428 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1429 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1430 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1431 0x00000000);
1432 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1433 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1434 &spr_read_generic, &spr_write_excp_vector,
76a66253 1435 0x00000000);
2662a059 1436#if 0
363be49c
JM		 1437 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1438 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1439 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1440 0x00000000);
1441 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1442 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1443 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1444 0x00000000);
1445 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1446 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1447 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1448 0x00000000);
1449 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1450 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1451 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1452 0x00000000);
1453 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1454 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1455 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1456 0x00000000);
1457 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1458 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1459 &spr_read_generic, &spr_write_excp_vector,
363be49c 1460 0x00000000);
2662a059 1461#endif
76a66253
JM		 1462 spr_register(env, SPR_BOOKE_PID, "PID",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_generic,
1465 0x00000000);
1466 spr_register(env, SPR_BOOKE_TCR, "TCR",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_booke_tcr,
1469 0x00000000);
1470 spr_register(env, SPR_BOOKE_TSR, "TSR",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_booke_tsr,
1473 0x00000000);
1474 /* Timer */
1475 spr_register(env, SPR_DECR, "DECR",
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_decr, &spr_write_decr,
1478 0x00000000);
1479 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 SPR_NOACCESS, &spr_write_generic,
1482 0x00000000);
1483 /* SPRGs */
1484 spr_register(env, SPR_USPRG0, "USPRG0",
1485 &spr_read_generic, &spr_write_generic,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 spr_register(env, SPR_SPRG4, "SPRG4",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 spr_register(env, SPR_USPRG4, "USPRG4",
1493 &spr_read_ureg, SPR_NOACCESS,
1494 &spr_read_ureg, SPR_NOACCESS,
1495 0x00000000);
1496 spr_register(env, SPR_SPRG5, "SPRG5",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_generic,
1499 0x00000000);
1500 spr_register(env, SPR_USPRG5, "USPRG5",
1501 &spr_read_ureg, SPR_NOACCESS,
1502 &spr_read_ureg, SPR_NOACCESS,
1503 0x00000000);
1504 spr_register(env, SPR_SPRG6, "SPRG6",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_generic, &spr_write_generic,
1507 0x00000000);
1508 spr_register(env, SPR_USPRG6, "USPRG6",
1509 &spr_read_ureg, SPR_NOACCESS,
1510 &spr_read_ureg, SPR_NOACCESS,
1511 0x00000000);
1512 spr_register(env, SPR_SPRG7, "SPRG7",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1515 0x00000000);
1516 spr_register(env, SPR_USPRG7, "USPRG7",
1517 &spr_read_ureg, SPR_NOACCESS,
1518 &spr_read_ureg, SPR_NOACCESS,
1519 0x00000000);
1520}
1521
363be49c
JM		 1522/* FSL storage control registers */
1523static void gen_spr_BookE_FSL (CPUPPCState *env)
1524{
f2e63a42 1525#if !defined(CONFIG_USER_ONLY)
363be49c 1526 /* TLB assist registers */
578bb252 1527 /* XXX : not implemented */
363be49c
JM		 1528 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
578bb252 1532 /* XXX : not implemented */
363be49c
JM		 1533 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
578bb252 1537 /* XXX : not implemented */
363be49c
JM		 1538 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
578bb252 1542 /* XXX : not implemented */
363be49c
JM		 1543 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
578bb252 1547 /* XXX : not implemented */
363be49c
JM		 1548 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
578bb252 1552 /* XXX : not implemented */
363be49c
JM		 1553 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
578bb252 1557 /* XXX : not implemented */
363be49c
JM		 1558 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 if (env->nb_pids > 1) {
578bb252 1563 /* XXX : not implemented */
363be49c
JM		 1564 spr_register(env, SPR_BOOKE_PID1, "PID1",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568 }
1569 if (env->nb_pids > 2) {
578bb252 1570 /* XXX : not implemented */
363be49c
JM		 1571 spr_register(env, SPR_BOOKE_PID2, "PID2",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 }
578bb252 1576 /* XXX : not implemented */
65f9ee8d 1577 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, SPR_NOACCESS,
1580 0x00000000); /* TOFIX */
578bb252 1581 /* XXX : not implemented */
65f9ee8d 1582 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000); /* TOFIX */
1586 switch (env->nb_ways) {
1587 case 4:
578bb252 1588 /* XXX : not implemented */
363be49c
JM		 1589 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, SPR_NOACCESS,
1592 0x00000000); /* TOFIX */
1593 /* Fallthru */
1594 case 3:
578bb252 1595 /* XXX : not implemented */
363be49c
JM		 1596 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, SPR_NOACCESS,
1599 0x00000000); /* TOFIX */
1600 /* Fallthru */
1601 case 2:
578bb252 1602 /* XXX : not implemented */
363be49c
JM		 1603 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, SPR_NOACCESS,
1606 0x00000000); /* TOFIX */
1607 /* Fallthru */
1608 case 1:
578bb252 1609 /* XXX : not implemented */
363be49c
JM		 1610 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, SPR_NOACCESS,
1613 0x00000000); /* TOFIX */
1614 /* Fallthru */
1615 case 0:
1616 default:
1617 break;
1618 }
f2e63a42 1619#endif
363be49c
JM		 1620}
1621
76a66253
JM		 1622/* SPR specific to PowerPC 440 implementation */
1623static void gen_spr_440 (CPUPPCState *env)
1624{
1625 /* Cache control */
1626 /* XXX : not implemented */
1627 spr_register(env, SPR_440_DNV0, "DNV0",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, &spr_write_generic,
1630 0x00000000);
1631 /* XXX : not implemented */
1632 spr_register(env, SPR_440_DNV1, "DNV1",
1633 SPR_NOACCESS, SPR_NOACCESS,
1634 &spr_read_generic, &spr_write_generic,
1635 0x00000000);
1636 /* XXX : not implemented */
1637 spr_register(env, SPR_440_DNV2, "DNV2",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, &spr_write_generic,
1640 0x00000000);
1641 /* XXX : not implemented */
1642 spr_register(env, SPR_440_DNV3, "DNV3",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, &spr_write_generic,
1645 0x00000000);
1646 /* XXX : not implemented */
2662a059 1647 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651 /* XXX : not implemented */
2662a059 1652 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656 /* XXX : not implemented */
2662a059 1657 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00000000);
1661 /* XXX : not implemented */
2662a059 1662 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic,
1665 0x00000000);
1666 /* XXX : not implemented */
1667 spr_register(env, SPR_440_DVLIM, "DVLIM",
1668 SPR_NOACCESS, SPR_NOACCESS,
1669 &spr_read_generic, &spr_write_generic,
1670 0x00000000);
1671 /* XXX : not implemented */
1672 spr_register(env, SPR_440_INV0, "INV0",
1673 SPR_NOACCESS, SPR_NOACCESS,
1674 &spr_read_generic, &spr_write_generic,
1675 0x00000000);
1676 /* XXX : not implemented */
1677 spr_register(env, SPR_440_INV1, "INV1",
1678 SPR_NOACCESS, SPR_NOACCESS,
1679 &spr_read_generic, &spr_write_generic,
1680 0x00000000);
1681 /* XXX : not implemented */
1682 spr_register(env, SPR_440_INV2, "INV2",
1683 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_generic,
1685 0x00000000);
1686 /* XXX : not implemented */
1687 spr_register(env, SPR_440_INV3, "INV3",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_generic,
1690 0x00000000);
1691 /* XXX : not implemented */
2662a059 1692 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_generic,
1695 0x00000000);
1696 /* XXX : not implemented */
2662a059 1697 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, &spr_write_generic,
1700 0x00000000);
1701 /* XXX : not implemented */
2662a059 1702 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, &spr_write_generic,
1705 0x00000000);
1706 /* XXX : not implemented */
2662a059 1707 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1708 SPR_NOACCESS, SPR_NOACCESS,
1709 &spr_read_generic, &spr_write_generic,
1710 0x00000000);
1711 /* XXX : not implemented */
1712 spr_register(env, SPR_440_IVLIM, "IVLIM",
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_generic, &spr_write_generic,
1715 0x00000000);
1716 /* Cache debug */
1717 /* XXX : not implemented */
2662a059 1718 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, SPR_NOACCESS,
1721 0x00000000);
1722 /* XXX : not implemented */
2662a059 1723 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, SPR_NOACCESS,
1726 0x00000000);
1727 /* XXX : not implemented */
2662a059 1728 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, SPR_NOACCESS,
1731 0x00000000);
1732 /* XXX : not implemented */
2662a059 1733 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, SPR_NOACCESS,
1736 0x00000000);
1737 /* XXX : not implemented */
2662a059 1738 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, SPR_NOACCESS,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_DBDR, "DBDR",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* Processor control */
1748 spr_register(env, SPR_4xx_CCR0, "CCR0",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, SPR_NOACCESS,
1755 0x00000000);
1756 /* Storage control */
1757 spr_register(env, SPR_440_MMUCR, "MMUCR",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761}
1762
1763/* SPR shared between PowerPC 40x implementations */
1764static void gen_spr_40x (CPUPPCState *env)
1765{
1766 /* Cache */
035feb88 1767 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1768 spr_register(env, SPR_40x_DCCR, "DCCR",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
035feb88 1772 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1773 spr_register(env, SPR_40x_ICCR, "ICCR",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
578bb252 1777 /* not emulated, as Qemu do not emulate caches */
2662a059 1778 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, SPR_NOACCESS,
1781 0x00000000);
76a66253
JM		 1782 /* Exception */
1783 spr_register(env, SPR_40x_DEAR, "DEAR",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 spr_register(env, SPR_40x_ESR, "ESR",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 spr_register(env, SPR_40x_EVPR, "EVPR",
1792 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1793 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1794 0x00000000);
1795 spr_register(env, SPR_40x_SRR2, "SRR2",
1796 &spr_read_generic, &spr_write_generic,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 spr_register(env, SPR_40x_SRR3, "SRR3",
1800 &spr_read_generic, &spr_write_generic,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* Timers */
1804 spr_register(env, SPR_40x_PIT, "PIT",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_40x_pit, &spr_write_40x_pit,
1807 0x00000000);
1808 spr_register(env, SPR_40x_TCR, "TCR",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_booke_tcr,
1811 0x00000000);
1812 spr_register(env, SPR_40x_TSR, "TSR",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_booke_tsr,
1815 0x00000000);
2662a059
JM		 1816}
1817
1818/* SPR specific to PowerPC 405 implementation */
1819static void gen_spr_405 (CPUPPCState *env)
1820{
1821 /* MMU */
1822 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_generic,
1825 0x00000000);
2662a059 1826 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1829 0x00700000);
1830 /* Debug interface */
76a66253
JM		 1831 /* XXX : not implemented */
1832 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1833 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1834 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1835 0x00000000);
1836 /* XXX : not implemented */
2662a059
JM		 1837 spr_register(env, SPR_405_DBCR1, "DBCR1",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* XXX : not implemented */
76a66253
JM		 1842 spr_register(env, SPR_40x_DBSR, "DBSR",
1843 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1844 &spr_read_generic, &spr_write_clear,
1845 /* Last reset was system reset */
76a66253
JM		 1846 0x00000300);
1847 /* XXX : not implemented */
2662a059 1848 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_generic,
1851 0x00000000);
2662a059 1852 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_generic,
1855 0x00000000);
2662a059
JM		 1856 /* XXX : not implemented */
1857 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
2662a059 1860 0x00000000);
76a66253 1861 /* XXX : not implemented */
2662a059 1862 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 /* XXX : not implemented */
2662a059 1867 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1868 SPR_NOACCESS, SPR_NOACCESS,
1869 &spr_read_generic, &spr_write_generic,
1870 0x00000000);
2662a059 1871 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_405_IAC3, "IAC3",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_405_IAC4, "IAC4",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* Storage control */
035feb88 1886 /* XXX: TODO: not implemented */
76a66253
JM		 1887 spr_register(env, SPR_405_SLER, "SLER",
1888 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1889 &spr_read_generic, &spr_write_40x_sler,
76a66253 1890 0x00000000);
2662a059
JM		 1891 spr_register(env, SPR_40x_ZPR, "ZPR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
76a66253
JM		 1895 /* XXX : not implemented */
1896 spr_register(env, SPR_405_SU0R, "SU0R",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900 /* SPRG */
1901 spr_register(env, SPR_USPRG0, "USPRG0",
1902 &spr_read_ureg, SPR_NOACCESS,
1903 &spr_read_ureg, SPR_NOACCESS,
1904 0x00000000);
1905 spr_register(env, SPR_SPRG4, "SPRG4",
1906 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1907 &spr_read_generic, &spr_write_generic,
76a66253
JM		 1908 0x00000000);
1909 spr_register(env, SPR_USPRG4, "USPRG4",
1910 &spr_read_ureg, SPR_NOACCESS,
1911 &spr_read_ureg, SPR_NOACCESS,
1912 0x00000000);
1913 spr_register(env, SPR_SPRG5, "SPRG5",
1914 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1915 spr_read_generic, &spr_write_generic,
76a66253
JM		 1916 0x00000000);
1917 spr_register(env, SPR_USPRG5, "USPRG5",
1918 &spr_read_ureg, SPR_NOACCESS,
1919 &spr_read_ureg, SPR_NOACCESS,
1920 0x00000000);
1921 spr_register(env, SPR_SPRG6, "SPRG6",
1922 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1923 spr_read_generic, &spr_write_generic,
76a66253
JM		 1924 0x00000000);
1925 spr_register(env, SPR_USPRG6, "USPRG6",
1926 &spr_read_ureg, SPR_NOACCESS,
1927 &spr_read_ureg, SPR_NOACCESS,
1928 0x00000000);
1929 spr_register(env, SPR_SPRG7, "SPRG7",
1930 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1931 spr_read_generic, &spr_write_generic,
76a66253
JM		 1932 0x00000000);
1933 spr_register(env, SPR_USPRG7, "USPRG7",
1934 &spr_read_ureg, SPR_NOACCESS,
1935 &spr_read_ureg, SPR_NOACCESS,
1936 0x00000000);
76a66253
JM		 1937}
1938
1939/* SPR shared between PowerPC 401 & 403 implementations */
1940static void gen_spr_401_403 (CPUPPCState *env)
1941{
1942 /* Time base */
1943 spr_register(env, SPR_403_VTBL, "TBL",
1944 &spr_read_tbl, SPR_NOACCESS,
1945 &spr_read_tbl, SPR_NOACCESS,
1946 0x00000000);
1947 spr_register(env, SPR_403_TBL, "TBL",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 SPR_NOACCESS, &spr_write_tbl,
1950 0x00000000);
1951 spr_register(env, SPR_403_VTBU, "TBU",
1952 &spr_read_tbu, SPR_NOACCESS,
1953 &spr_read_tbu, SPR_NOACCESS,
1954 0x00000000);
1955 spr_register(env, SPR_403_TBU, "TBU",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 SPR_NOACCESS, &spr_write_tbu,
1958 0x00000000);
1959 /* Debug */
578bb252 1960 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1961 spr_register(env, SPR_403_CDBCR, "CDBCR",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 &spr_read_generic, &spr_write_generic,
1964 0x00000000);
1965}
1966
2662a059
JM		 1967/* SPR specific to PowerPC 401 implementation */
1968static void gen_spr_401 (CPUPPCState *env)
1969{
1970 /* Debug interface */
1971 /* XXX : not implemented */
1972 spr_register(env, SPR_40x_DBCR0, "DBCR",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_40x_dbcr0,
1975 0x00000000);
1976 /* XXX : not implemented */
1977 spr_register(env, SPR_40x_DBSR, "DBSR",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_clear,
1980 /* Last reset was system reset */
1981 0x00000300);
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_40x_DAC1, "DAC",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_40x_IAC1, "IAC",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 /* Storage control */
035feb88 1993 /* XXX: TODO: not implemented */
2662a059
JM		 1994 spr_register(env, SPR_405_SLER, "SLER",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_40x_sler,
1997 0x00000000);
035feb88
JM		 1998 /* not emulated, as Qemu never does speculative access */
1999 spr_register(env, SPR_40x_SGR, "SGR",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0xFFFFFFFF);
2003 /* not emulated, as Qemu do not emulate caches */
2004 spr_register(env, SPR_40x_DCWR, "DCWR",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2662a059
JM		 2008}
2009
a750fc0b
JM		 2010static void gen_spr_401x2 (CPUPPCState *env)
2011{
2012 gen_spr_401(env);
2013 spr_register(env, SPR_40x_PID, "PID",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0x00000000);
2017 spr_register(env, SPR_40x_ZPR, "ZPR",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021}
2022
76a66253
JM		 2023/* SPR specific to PowerPC 403 implementation */
2024static void gen_spr_403 (CPUPPCState *env)
2025{
2662a059
JM		 2026 /* Debug interface */
2027 /* XXX : not implemented */
2028 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_40x_dbcr0,
2031 0x00000000);
2032 /* XXX : not implemented */
2033 spr_register(env, SPR_40x_DBSR, "DBSR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_clear,
2036 /* Last reset was system reset */
2037 0x00000300);
2038 /* XXX : not implemented */
2039 spr_register(env, SPR_40x_DAC1, "DAC1",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
578bb252 2043 /* XXX : not implemented */
2662a059
JM		 2044 spr_register(env, SPR_40x_DAC2, "DAC2",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_generic,
2047 0x00000000);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_40x_IAC1, "IAC1",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_generic,
2052 0x00000000);
578bb252 2053 /* XXX : not implemented */
2662a059
JM		 2054 spr_register(env, SPR_40x_IAC2, "IAC2",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_generic, &spr_write_generic,
2057 0x00000000);
a750fc0b
JM		 2058}
2059
2060static void gen_spr_403_real (CPUPPCState *env)
2061{
76a66253
JM		 2062 spr_register(env, SPR_403_PBL1, "PBL1",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_403_pbr, &spr_write_403_pbr,
2065 0x00000000);
2066 spr_register(env, SPR_403_PBU1, "PBU1",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_403_pbr, &spr_write_403_pbr,
2069 0x00000000);
2070 spr_register(env, SPR_403_PBL2, "PBL2",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_403_pbr, &spr_write_403_pbr,
2073 0x00000000);
2074 spr_register(env, SPR_403_PBU2, "PBU2",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_403_pbr, &spr_write_403_pbr,
2077 0x00000000);
a750fc0b
JM		 2078}
2079
2080static void gen_spr_403_mmu (CPUPPCState *env)
2081{
2082 /* MMU */
2083 spr_register(env, SPR_40x_PID, "PID",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2662a059 2087 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic,
2090 0x00000000);
2091}
2092
2093/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2094static void gen_spr_compress (CPUPPCState *env)
2095{
578bb252 2096 /* XXX : not implemented */
76a66253
JM		 2097 spr_register(env, SPR_401_SKR, "SKR",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2101}
a750fc0b
JM		 2102
2103#if defined (TARGET_PPC64)
a750fc0b
JM		 2104/* SPR specific to PowerPC 620 */
2105static void gen_spr_620 (CPUPPCState *env)
2106{
578bb252 2107 /* XXX : not implemented */
a750fc0b
JM		 2108 spr_register(env, SPR_620_PMR0, "PMR0",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_generic,
2111 0x00000000);
578bb252 2112 /* XXX : not implemented */
a750fc0b
JM		 2113 spr_register(env, SPR_620_PMR1, "PMR1",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_generic,
2116 0x00000000);
578bb252 2117 /* XXX : not implemented */
a750fc0b
JM		 2118 spr_register(env, SPR_620_PMR2, "PMR2",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
578bb252 2122 /* XXX : not implemented */
a750fc0b
JM		 2123 spr_register(env, SPR_620_PMR3, "PMR3",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
578bb252 2127 /* XXX : not implemented */
a750fc0b
JM		 2128 spr_register(env, SPR_620_PMR4, "PMR4",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
578bb252 2132 /* XXX : not implemented */
a750fc0b
JM		 2133 spr_register(env, SPR_620_PMR5, "PMR5",
2134 SPR_NOACCESS, SPR_NOACCESS,
2135 &spr_read_generic, &spr_write_generic,
2136 0x00000000);
578bb252 2137 /* XXX : not implemented */
a750fc0b
JM		 2138 spr_register(env, SPR_620_PMR6, "PMR6",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
578bb252 2142 /* XXX : not implemented */
a750fc0b
JM		 2143 spr_register(env, SPR_620_PMR7, "PMR7",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_generic,
2146 0x00000000);
578bb252 2147 /* XXX : not implemented */
a750fc0b
JM		 2148 spr_register(env, SPR_620_PMR8, "PMR8",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_generic,
2151 0x00000000);
578bb252 2152 /* XXX : not implemented */
a750fc0b
JM		 2153 spr_register(env, SPR_620_PMR9, "PMR9",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, &spr_write_generic,
2156 0x00000000);
578bb252 2157 /* XXX : not implemented */
a750fc0b
JM		 2158 spr_register(env, SPR_620_PMRA, "PMR10",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
578bb252 2162 /* XXX : not implemented */
a750fc0b
JM		 2163 spr_register(env, SPR_620_PMRB, "PMR11",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_generic,
2166 0x00000000);
578bb252 2167 /* XXX : not implemented */
a750fc0b
JM		 2168 spr_register(env, SPR_620_PMRC, "PMR12",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_generic, &spr_write_generic,
2171 0x00000000);
578bb252 2172 /* XXX : not implemented */
a750fc0b
JM		 2173 spr_register(env, SPR_620_PMRD, "PMR13",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0x00000000);
578bb252 2177 /* XXX : not implemented */
a750fc0b
JM		 2178 spr_register(env, SPR_620_PMRE, "PMR14",
2179 SPR_NOACCESS, SPR_NOACCESS,
2180 &spr_read_generic, &spr_write_generic,
2181 0x00000000);
578bb252 2182 /* XXX : not implemented */
a750fc0b
JM		 2183 spr_register(env, SPR_620_PMRF, "PMR15",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
578bb252 2187 /* XXX : not implemented */
a750fc0b
JM		 2188 spr_register(env, SPR_620_HID8, "HID8",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
578bb252 2192 /* XXX : not implemented */
a750fc0b
JM		 2193 spr_register(env, SPR_620_HID9, "HID9",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197}
a750fc0b 2198#endif /* defined (TARGET_PPC64) */
76a66253 2199
2662a059 2200// XXX: TODO
76a66253 2201/*
2662a059
JM		 2202 * AMR => SPR 29 (Power 2.04)
2203 * CTRL => SPR 136 (Power 2.04)
2204 * CTRL => SPR 152 (Power 2.04)
2662a059
JM		 2205 * SCOMC => SPR 276 (64 bits ?)
2206 * SCOMD => SPR 277 (64 bits ?)
2662a059
JM		 2207 * TBU40 => SPR 286 (Power 2.04 hypv)
2208 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2209 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2210 * HDSISR => SPR 306 (Power 2.04 hypv)
2211 * HDAR => SPR 307 (Power 2.04 hypv)
2212 * PURR => SPR 309 (Power 2.04 hypv)
2213 * HDEC => SPR 310 (Power 2.04 hypv)
2214 * HIOR => SPR 311 (hypv)
2215 * RMOR => SPR 312 (970)
2216 * HRMOR => SPR 313 (Power 2.04 hypv)
2217 * HSRR0 => SPR 314 (Power 2.04 hypv)
2218 * HSRR1 => SPR 315 (Power 2.04 hypv)
2219 * LPCR => SPR 316 (970)
2220 * LPIDR => SPR 317 (970)
2221 * SPEFSCR => SPR 512 (Power 2.04 emb)
2662a059
JM		 2222 * EPR => SPR 702 (Power 2.04 emb)
2223 * perf => 768-783 (Power 2.04)
2224 * perf => 784-799 (Power 2.04)
2225 * PPR => SPR 896 (Power 2.04)
2226 * EPLC => SPR 947 (Power 2.04 emb)
2227 * EPSC => SPR 948 (Power 2.04 emb)
2228 * DABRX => 1015 (Power 2.04 hypv)
2229 * FPECR => SPR 1022 (?)
76a66253
JM		 2230 * ... and more (thermal management, performance counters, ...)
2231 */
2232
e1833e1f
JM		 2233/*****************************************************************************/
2234/* Exception vectors models */
2235static void init_excp_4xx_real (CPUPPCState *env)
2236{
2237#if !defined(CONFIG_USER_ONLY)
2238 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2239 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2240 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2241 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2242 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2243 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2244 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2245 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2246 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2247 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
6f5d427d
JM		 2248 env->excp_prefix = 0x00000000;
2249 env->ivor_mask = 0x0000FFF0;
2250 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2251 /* Hardware reset vector */
2252 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2253#endif
2254}
2255
2256static void init_excp_4xx_softmmu (CPUPPCState *env)
2257{
2258#if !defined(CONFIG_USER_ONLY)
2259 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2260 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2261 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2262 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2263 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2264 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2265 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2266 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2267 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2268 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2269 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2270 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2271 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2272 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
6f5d427d
JM		 2273 env->excp_prefix = 0x00000000;
2274 env->ivor_mask = 0x0000FFF0;
2275 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2276 /* Hardware reset vector */
2277 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2278#endif
2279}
2280
2281static void init_excp_BookE (CPUPPCState *env)
2282{
2283#if !defined(CONFIG_USER_ONLY)
2284 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2285 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2286 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2287 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2288 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2289 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2290 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2291 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2292 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2293 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2294 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2295 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2296 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2297 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2298 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2299 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2300 env->excp_prefix = 0x00000000;
2301 env->ivor_mask = 0x0000FFE0;
2302 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2303 /* Hardware reset vector */
2304 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2305#endif
2306}
2307
2308static void init_excp_601 (CPUPPCState *env)
2309{
2310#if !defined(CONFIG_USER_ONLY)
2311 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2312 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2313 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2314 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2315 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2316 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2317 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2318 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2319 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2320 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2321 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2322 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2323 env->excp_prefix = 0xFFF00000;
1c27f8fb 2324 /* Hardware reset vector */
4e80effc 2325 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2326#endif
2327}
2328
2329static void init_excp_602 (CPUPPCState *env)
2330{
2331#if !defined(CONFIG_USER_ONLY)
2332 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2333 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2334 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2335 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2336 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2337 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2338 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2339 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2340 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2341 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2342 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2343 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2344 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2345 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2346 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2347 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2348 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2349 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2350 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2351 env->excp_prefix = 0xFFF00000;
1c27f8fb
JM		 2352 /* Hardware reset vector */
2353 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2354#endif
2355}
2356
2357static void init_excp_603 (CPUPPCState *env)
2358{
2359#if !defined(CONFIG_USER_ONLY)
2360 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2361 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2362 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2363 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2364 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2365 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2366 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2367 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2368 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2369 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2370 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2371 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2372 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2373 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2374 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2375 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2376 /* Hardware reset vector */
2377 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2378#endif
2379}
2380
2381static void init_excp_G2 (CPUPPCState *env)
2382{
2383#if !defined(CONFIG_USER_ONLY)
2384 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2385 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2386 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2387 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2388 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2389 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2390 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2391 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2392 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2393 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2394 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2395 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2396 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2397 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2398 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2399 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2400 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2401 /* Hardware reset vector */
2402 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2403#endif
2404}
2405
2406static void init_excp_604 (CPUPPCState *env)
2407{
2408#if !defined(CONFIG_USER_ONLY)
2409 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2410 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2411 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2412 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2413 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2414 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2415 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2416 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2417 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2418 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2419 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2420 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2421 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2422 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2423 /* Hardware reset vector */
2424 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2425#endif
2426}
2427
578bb252 2428#if defined(TARGET_PPC64)
e1833e1f
JM		 2429static void init_excp_620 (CPUPPCState *env)
2430{
2431#if !defined(CONFIG_USER_ONLY)
2432 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2433 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2434 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2435 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2436 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2437 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2438 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2439 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2440 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2441 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2442 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2443 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2444 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2445 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2446 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2447 /* Hardware reset vector */
2448 env->hreset_vector = 0x0000000000000100ULL; /* ? */
e1833e1f
JM		 2449#endif
2450}
578bb252 2451#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2452
2453static void init_excp_7x0 (CPUPPCState *env)
2454{
2455#if !defined(CONFIG_USER_ONLY)
2456 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2457 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2458 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2459 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2460 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2461 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2462 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2463 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2464 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2465 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2466 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2467 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2468 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2469 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2470 /* Hardware reset vector */
2471 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2472#endif
2473}
2474
2475static void init_excp_750FX (CPUPPCState *env)
2476{
2477#if !defined(CONFIG_USER_ONLY)
2478 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2479 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2480 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2481 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2482 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2483 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2484 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2485 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2486 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2487 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2488 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2489 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2490 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2491 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2492 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2493 /* Hardware reset vector */
2494 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2495#endif
2496}
2497
7a3a6927
JM		 2498/* XXX: Check if this is correct */
2499static void init_excp_7x5 (CPUPPCState *env)
2500{
2501#if !defined(CONFIG_USER_ONLY)
2502 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2503 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2504 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2505 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2506 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2507 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2508 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2509 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2510 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2511 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2512 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2513 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2514 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2515 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2516 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2517 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2518 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2519 /* Hardware reset vector */
2520 env->hreset_vector = 0xFFFFFFFCUL;
2521#endif
2522}
2523
e1833e1f
JM		 2524static void init_excp_7400 (CPUPPCState *env)
2525{
2526#if !defined(CONFIG_USER_ONLY)
2527 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2528 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2529 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2530 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2531 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2532 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2533 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2534 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2535 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2536 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2537 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2538 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2539 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2540 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2541 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2542 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2543 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2544 /* Hardware reset vector */
2545 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2546#endif
2547}
2548
e1833e1f
JM		 2549static void init_excp_7450 (CPUPPCState *env)
2550{
2551#if !defined(CONFIG_USER_ONLY)
2552 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2553 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2554 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2555 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2556 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2557 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2558 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2559 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2560 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2561 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2562 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2563 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2564 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2565 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2566 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2567 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2568 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2569 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2570 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1c27f8fb
JM		 2571 /* Hardware reset vector */
2572 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2573#endif
2574}
e1833e1f
JM		 2575
2576#if defined (TARGET_PPC64)
2577static void init_excp_970 (CPUPPCState *env)
2578{
2579#if !defined(CONFIG_USER_ONLY)
2580 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2581 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2582 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2583 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2584 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2585 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2586 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2587 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2588 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2589 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2590 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2591#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2592 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2593#endif
2594 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2595 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2596 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2597 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2598 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2599 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2600 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2601 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
1c27f8fb
JM		 2602 /* Hardware reset vector */
2603 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2604#endif
2605}
2606#endif
2607
a750fc0b
JM		 2608/*****************************************************************************/
2609/* PowerPC implementations definitions */
76a66253 2610
a750fc0b 2611/* PowerPC 40x instruction set */
d63001d1 2612#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
76a66253 2613
a750fc0b
JM		 2614/* PowerPC 401 */
2615#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2616 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2617 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2618#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2619#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2620#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2621#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 2622#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
d26bfc9a 2623#define POWERPC_FLAG_401 (POWERPC_FLAG_NONE)
76a66253 2624
a750fc0b
JM		 2625static void init_proc_401 (CPUPPCState *env)
2626{
2627 gen_spr_40x(env);
2628 gen_spr_401_403(env);
2629 gen_spr_401(env);
e1833e1f 2630 init_excp_4xx_real(env);
d63001d1
JM		 2631 env->dcache_line_size = 32;
2632 env->icache_line_size = 32;
4e290a0b
JM		 2633 /* Allocate hardware IRQ controller */
2634 ppc40x_irq_init(env);
a750fc0b 2635}
76a66253 2636
a750fc0b
JM		 2637/* PowerPC 401x2 */
2638#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2639 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2640 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2641 PPC_CACHE_DCBA | PPC_MFTB | \
2642 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2643#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2644#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2645#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2646#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 2647#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
d26bfc9a 2648#define POWERPC_FLAG_401x2 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2649
2650static void init_proc_401x2 (CPUPPCState *env)
2651{
2652 gen_spr_40x(env);
2653 gen_spr_401_403(env);
2654 gen_spr_401x2(env);
2655 gen_spr_compress(env);
a750fc0b 2656 /* Memory management */
f2e63a42 2657#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2658 env->nb_tlb = 64;
2659 env->nb_ways = 1;
2660 env->id_tlbs = 0;
f2e63a42 2661#endif
e1833e1f 2662 init_excp_4xx_softmmu(env);
d63001d1
JM		 2663 env->dcache_line_size = 32;
2664 env->icache_line_size = 32;
4e290a0b
JM		 2665 /* Allocate hardware IRQ controller */
2666 ppc40x_irq_init(env);
76a66253
JM		 2667}
2668
a750fc0b 2669/* PowerPC 401x3 */
a750fc0b
JM		 2670#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2671 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2672 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2673 PPC_CACHE_DCBA | PPC_MFTB | \
2674 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2675#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2676#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2677#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2678#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 2679#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
d26bfc9a 2680#define POWERPC_FLAG_401x3 (POWERPC_FLAG_NONE)
a750fc0b 2681
578bb252 2682__attribute__ (( unused ))
e1833e1f 2683static void init_proc_401x3 (CPUPPCState *env)
76a66253 2684{
4e290a0b
JM		 2685 gen_spr_40x(env);
2686 gen_spr_401_403(env);
2687 gen_spr_401(env);
2688 gen_spr_401x2(env);
2689 gen_spr_compress(env);
e1833e1f 2690 init_excp_4xx_softmmu(env);
d63001d1
JM		 2691 env->dcache_line_size = 32;
2692 env->icache_line_size = 32;
4e290a0b
JM		 2693 /* Allocate hardware IRQ controller */
2694 ppc40x_irq_init(env);
3fc6c082 2695}
a750fc0b
JM		 2696
2697/* IOP480 */
2698#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2699 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2700 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2701 PPC_CACHE_DCBA | \
2702 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2703#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2704#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2705#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2706#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 2707#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
d26bfc9a 2708#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2709
2710static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 2711{
a750fc0b
JM		 2712 gen_spr_40x(env);
2713 gen_spr_401_403(env);
2714 gen_spr_401x2(env);
2715 gen_spr_compress(env);
a750fc0b 2716 /* Memory management */
f2e63a42 2717#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2718 env->nb_tlb = 64;
2719 env->nb_ways = 1;
2720 env->id_tlbs = 0;
f2e63a42 2721#endif
e1833e1f 2722 init_excp_4xx_softmmu(env);
d63001d1
JM		 2723 env->dcache_line_size = 32;
2724 env->icache_line_size = 32;
4e290a0b
JM		 2725 /* Allocate hardware IRQ controller */
2726 ppc40x_irq_init(env);
3fc6c082
FB		 2727}
2728
a750fc0b
JM		 2729/* PowerPC 403 */
2730#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2731 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
a750fc0b
JM		 2732 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2733#define POWERPC_MSRM_403 (0x000000000007D00DULL)
2734#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2735#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2736#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 2737#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
d26bfc9a 2738#define POWERPC_FLAG_403 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2739
2740static void init_proc_403 (CPUPPCState *env)
3fc6c082 2741{
a750fc0b
JM		 2742 gen_spr_40x(env);
2743 gen_spr_401_403(env);
2744 gen_spr_403(env);
2745 gen_spr_403_real(env);
e1833e1f 2746 init_excp_4xx_real(env);
d63001d1
JM		 2747 env->dcache_line_size = 32;
2748 env->icache_line_size = 32;
4e290a0b
JM		 2749 /* Allocate hardware IRQ controller */
2750 ppc40x_irq_init(env);
d63001d1
JM		 2751#if !defined(CONFIG_USER_ONLY)
2752 /* Hardware reset vector */
2753 env->hreset_vector = 0xFFFFFFFCUL;
2754#endif
3fc6c082
FB		 2755}
2756
a750fc0b
JM		 2757/* PowerPC 403 GCX */
2758#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2759 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2760 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2761 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2762#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2763#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2764#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2765#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 2766#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
d26bfc9a 2767#define POWERPC_FLAG_403GCX (POWERPC_FLAG_NONE)
a750fc0b
JM		 2768
2769static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 2770{
a750fc0b
JM		 2771 gen_spr_40x(env);
2772 gen_spr_401_403(env);
2773 gen_spr_403(env);
2774 gen_spr_403_real(env);
2775 gen_spr_403_mmu(env);
2776 /* Bus access control */
035feb88 2777 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 2778 spr_register(env, SPR_40x_SGR, "SGR",
2779 SPR_NOACCESS, SPR_NOACCESS,
2780 &spr_read_generic, &spr_write_generic,
2781 0xFFFFFFFF);
035feb88 2782 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 2783 spr_register(env, SPR_40x_DCWR, "DCWR",
2784 SPR_NOACCESS, SPR_NOACCESS,
2785 &spr_read_generic, &spr_write_generic,
2786 0x00000000);
2787 /* Memory management */
f2e63a42 2788#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2789 env->nb_tlb = 64;
2790 env->nb_ways = 1;
2791 env->id_tlbs = 0;
f2e63a42 2792#endif
e1833e1f 2793 init_excp_4xx_softmmu(env);
d63001d1
JM		 2794 env->dcache_line_size = 32;
2795 env->icache_line_size = 32;
4e290a0b
JM		 2796 /* Allocate hardware IRQ controller */
2797 ppc40x_irq_init(env);
3fc6c082
FB		 2798}
2799
a750fc0b
JM		 2800/* PowerPC 405 */
2801#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2802 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2803 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2804 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2805 PPC_405_MAC)
2806#define POWERPC_MSRM_405 (0x000000000006E630ULL)
2807#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2808#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2809#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
237c0af0 2810#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
d26bfc9a 2811#define POWERPC_FLAG_405 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2812
2813static void init_proc_405 (CPUPPCState *env)
3fc6c082 2814{
a750fc0b
JM		 2815 /* Time base */
2816 gen_tbl(env);
2817 gen_spr_40x(env);
2818 gen_spr_405(env);
2819 /* Bus access control */
035feb88 2820 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 2821 spr_register(env, SPR_40x_SGR, "SGR",
2822 SPR_NOACCESS, SPR_NOACCESS,
2823 &spr_read_generic, &spr_write_generic,
2824 0xFFFFFFFF);
035feb88 2825 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 2826 spr_register(env, SPR_40x_DCWR, "DCWR",
2827 SPR_NOACCESS, SPR_NOACCESS,
2828 &spr_read_generic, &spr_write_generic,
2829 0x00000000);
2830 /* Memory management */
f2e63a42 2831#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2832 env->nb_tlb = 64;
2833 env->nb_ways = 1;
2834 env->id_tlbs = 0;
f2e63a42 2835#endif
e1833e1f 2836 init_excp_4xx_softmmu(env);
d63001d1
JM		 2837 env->dcache_line_size = 32;
2838 env->icache_line_size = 32;
a750fc0b 2839 /* Allocate hardware IRQ controller */
4e290a0b 2840 ppc40x_irq_init(env);
3fc6c082
FB		 2841}
2842
a750fc0b
JM		 2843/* PowerPC 440 EP */
2844#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2845 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2846 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2847 PPC_440_SPEC | PPC_RFMCI)
2848#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2849#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2850#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2851#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
237c0af0 2852#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
d26bfc9a 2853#define POWERPC_FLAG_440EP (POWERPC_FLAG_NONE)
a750fc0b
JM		 2854
2855static void init_proc_440EP (CPUPPCState *env)
3fc6c082 2856{
a750fc0b
JM		 2857 /* Time base */
2858 gen_tbl(env);
2859 gen_spr_BookE(env);
2860 gen_spr_440(env);
578bb252 2861 /* XXX : not implemented */
a750fc0b
JM		 2862 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2863 SPR_NOACCESS, SPR_NOACCESS,
2864 &spr_read_generic, &spr_write_generic,
2865 0x00000000);
2866 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2867 SPR_NOACCESS, SPR_NOACCESS,
2868 &spr_read_generic, &spr_write_generic,
2869 0x00000000);
2870 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2871 SPR_NOACCESS, SPR_NOACCESS,
2872 &spr_read_generic, &spr_write_generic,
2873 0x00000000);
578bb252 2874 /* XXX : not implemented */
a750fc0b
JM		 2875 spr_register(env, SPR_440_CCR1, "CCR1",
2876 SPR_NOACCESS, SPR_NOACCESS,
2877 &spr_read_generic, &spr_write_generic,
2878 0x00000000);
2879 /* Memory management */
f2e63a42 2880#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2881 env->nb_tlb = 64;
2882 env->nb_ways = 1;
2883 env->id_tlbs = 0;
f2e63a42 2884#endif
e1833e1f 2885 init_excp_BookE(env);
d63001d1
JM		 2886 env->dcache_line_size = 32;
2887 env->icache_line_size = 32;
a750fc0b 2888 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2889}
2890
a750fc0b
JM		 2891/* PowerPC 440 GP */
2892#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2893 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2894 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2895 PPC_405_MAC | PPC_440_SPEC)
2896#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2897#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2898#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2899#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
237c0af0 2900#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
d26bfc9a 2901#define POWERPC_FLAG_440GP (POWERPC_FLAG_NONE)
a750fc0b
JM		 2902
2903static void init_proc_440GP (CPUPPCState *env)
3fc6c082 2904{
a750fc0b
JM		 2905 /* Time base */
2906 gen_tbl(env);
2907 gen_spr_BookE(env);
2908 gen_spr_440(env);
2909 /* Memory management */
f2e63a42 2910#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2911 env->nb_tlb = 64;
2912 env->nb_ways = 1;
2913 env->id_tlbs = 0;
f2e63a42 2914#endif
e1833e1f 2915 init_excp_BookE(env);
d63001d1
JM		 2916 env->dcache_line_size = 32;
2917 env->icache_line_size = 32;
a750fc0b 2918 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2919}
2920
a750fc0b 2921/* PowerPC 440x4 */
a750fc0b
JM		 2922#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2923 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2924 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2925 PPC_440_SPEC)
2926#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2927#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2928#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2929#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
237c0af0 2930#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
d26bfc9a 2931#define POWERPC_FLAG_440x4 (POWERPC_FLAG_NONE)
a750fc0b 2932
578bb252 2933__attribute__ (( unused ))
a750fc0b 2934static void init_proc_440x4 (CPUPPCState *env)
3fc6c082 2935{
a750fc0b
JM		 2936 /* Time base */
2937 gen_tbl(env);
2938 gen_spr_BookE(env);
2939 gen_spr_440(env);
2940 /* Memory management */
f2e63a42 2941#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2942 env->nb_tlb = 64;
2943 env->nb_ways = 1;
2944 env->id_tlbs = 0;
f2e63a42 2945#endif
e1833e1f 2946 init_excp_BookE(env);
d63001d1
JM		 2947 env->dcache_line_size = 32;
2948 env->icache_line_size = 32;
a750fc0b 2949 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 2950}
a750fc0b
JM		 2951
2952/* PowerPC 440x5 */
2953#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2954 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2955 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2956 PPC_440_SPEC | PPC_RFMCI)
2957#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2958#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2959#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2960#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
237c0af0 2961#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
d26bfc9a 2962#define POWERPC_FLAG_440x5 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2963
2964static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 2965{
a750fc0b
JM		 2966 /* Time base */
2967 gen_tbl(env);
2968 gen_spr_BookE(env);
2969 gen_spr_440(env);
578bb252 2970 /* XXX : not implemented */
a750fc0b
JM		 2971 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2972 SPR_NOACCESS, SPR_NOACCESS,
2973 &spr_read_generic, &spr_write_generic,
2974 0x00000000);
2975 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2976 SPR_NOACCESS, SPR_NOACCESS,
2977 &spr_read_generic, &spr_write_generic,
2978 0x00000000);
2979 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2980 SPR_NOACCESS, SPR_NOACCESS,
2981 &spr_read_generic, &spr_write_generic,
2982 0x00000000);
578bb252 2983 /* XXX : not implemented */
a750fc0b
JM		 2984 spr_register(env, SPR_440_CCR1, "CCR1",
2985 SPR_NOACCESS, SPR_NOACCESS,
2986 &spr_read_generic, &spr_write_generic,
2987 0x00000000);
2988 /* Memory management */
f2e63a42 2989#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2990 env->nb_tlb = 64;
2991 env->nb_ways = 1;
2992 env->id_tlbs = 0;
f2e63a42 2993#endif
e1833e1f 2994 init_excp_BookE(env);
d63001d1
JM		 2995 env->dcache_line_size = 32;
2996 env->icache_line_size = 32;
a750fc0b 2997 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2998}
2999
a750fc0b 3000/* PowerPC 460 (guessed) */
578bb252 3001#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
a750fc0b
JM		 3002 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3003 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3004 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3005#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3006#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3007#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3008#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
237c0af0 3009#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
d26bfc9a 3010#define POWERPC_FLAG_460 (POWERPC_FLAG_NONE)
a750fc0b 3011
578bb252 3012__attribute__ (( unused ))
a750fc0b 3013static void init_proc_460 (CPUPPCState *env)
3fc6c082 3014{
e1833e1f
JM		 3015 /* Time base */
3016 gen_tbl(env);
3017 gen_spr_BookE(env);
3018 gen_spr_440(env);
578bb252 3019 /* XXX : not implemented */
e1833e1f
JM		 3020 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3021 SPR_NOACCESS, SPR_NOACCESS,
3022 &spr_read_generic, &spr_write_generic,
3023 0x00000000);
3024 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3025 SPR_NOACCESS, SPR_NOACCESS,
3026 &spr_read_generic, &spr_write_generic,
3027 0x00000000);
3028 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3029 SPR_NOACCESS, SPR_NOACCESS,
3030 &spr_read_generic, &spr_write_generic,
3031 0x00000000);
578bb252 3032 /* XXX : not implemented */
e1833e1f
JM		 3033 spr_register(env, SPR_440_CCR1, "CCR1",
3034 SPR_NOACCESS, SPR_NOACCESS,
3035 &spr_read_generic, &spr_write_generic,
3036 0x00000000);
578bb252 3037 /* XXX : not implemented */
e1833e1f
JM		 3038 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3039 &spr_read_generic, &spr_write_generic,
3040 &spr_read_generic, &spr_write_generic,
3041 0x00000000);
3042 /* Memory management */
f2e63a42 3043#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 3044 env->nb_tlb = 64;
3045 env->nb_ways = 1;
3046 env->id_tlbs = 0;
f2e63a42 3047#endif
e1833e1f 3048 init_excp_BookE(env);
d63001d1
JM		 3049 env->dcache_line_size = 32;
3050 env->icache_line_size = 32;
e1833e1f 3051 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3052}
a750fc0b
JM		 3053
3054/* PowerPC 460F (guessed) */
a750fc0b
JM		 3055#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
3056 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3057 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3058 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3059 PPC_FLOAT_STFIWX | \
3060 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3061 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3062#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3063#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3064#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3065#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
237c0af0 3066#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
d26bfc9a 3067#define POWERPC_FLAG_460F (POWERPC_FLAG_NONE)
a750fc0b 3068
578bb252 3069__attribute__ (( unused ))
e1833e1f 3070static void init_proc_460F (CPUPPCState *env)
3fc6c082 3071{
a750fc0b
JM		 3072 /* Time base */
3073 gen_tbl(env);
3074 gen_spr_BookE(env);
3075 gen_spr_440(env);
578bb252 3076 /* XXX : not implemented */
a750fc0b
JM		 3077 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3078 SPR_NOACCESS, SPR_NOACCESS,
3079 &spr_read_generic, &spr_write_generic,
3080 0x00000000);
3081 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3082 SPR_NOACCESS, SPR_NOACCESS,
3083 &spr_read_generic, &spr_write_generic,
3084 0x00000000);
3085 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3086 SPR_NOACCESS, SPR_NOACCESS,
3087 &spr_read_generic, &spr_write_generic,
3088 0x00000000);
578bb252 3089 /* XXX : not implemented */
a750fc0b
JM		 3090 spr_register(env, SPR_440_CCR1, "CCR1",
3091 SPR_NOACCESS, SPR_NOACCESS,
3092 &spr_read_generic, &spr_write_generic,
3093 0x00000000);
578bb252 3094 /* XXX : not implemented */
a750fc0b
JM		 3095 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3096 &spr_read_generic, &spr_write_generic,
3097 &spr_read_generic, &spr_write_generic,
3098 0x00000000);
3099 /* Memory management */
f2e63a42 3100#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3101 env->nb_tlb = 64;
3102 env->nb_ways = 1;
3103 env->id_tlbs = 0;
f2e63a42 3104#endif
e1833e1f 3105 init_excp_BookE(env);
d63001d1
JM		 3106 env->dcache_line_size = 32;
3107 env->icache_line_size = 32;
a750fc0b 3108 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3109}
a750fc0b
JM		 3110
3111/* Generic BookE PowerPC */
a750fc0b
JM		 3112#define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3113 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3114 PPC_CACHE_DCBA | \
3115 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3116 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3117 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
3118 PPC_BOOKE)
3119#define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3120#define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3121#define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3122#define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
237c0af0 3123#define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
d26bfc9a 3124#define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
a750fc0b 3125
578bb252 3126__attribute__ (( unused ))
a750fc0b 3127static void init_proc_BookE (CPUPPCState *env)
3fc6c082 3128{
e1833e1f 3129 init_excp_BookE(env);
d63001d1
JM		 3130 env->dcache_line_size = 32;
3131 env->icache_line_size = 32;
3fc6c082 3132}
a750fc0b
JM		 3133
3134/* e200 core */
a750fc0b
JM		 3135
3136/* e300 core */
a750fc0b
JM		 3137
3138/* e500 core */
a750fc0b
JM		 3139#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3140 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3141 PPC_CACHE_DCBA | \
3142 PPC_BOOKE | PPC_E500_VECTOR)
3143#define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3144#define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3145#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
237c0af0 3146#define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
d26bfc9a 3147#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
a750fc0b 3148
578bb252 3149__attribute__ (( unused ))
a750fc0b 3150static void init_proc_e500 (CPUPPCState *env)
3fc6c082 3151{
a750fc0b
JM		 3152 /* Time base */
3153 gen_tbl(env);
3154 gen_spr_BookE(env);
3155 /* Memory management */
3156 gen_spr_BookE_FSL(env);
f2e63a42 3157#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3158 env->nb_tlb = 64;
3159 env->nb_ways = 1;
3160 env->id_tlbs = 0;
f2e63a42 3161#endif
e1833e1f 3162 init_excp_BookE(env);
d63001d1
JM		 3163 env->dcache_line_size = 32;
3164 env->icache_line_size = 32;
a750fc0b 3165 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3166}
a750fc0b
JM		 3167
3168/* e600 core */
a750fc0b
JM		 3169
3170/* Non-embedded PowerPC */
3171/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3172#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
12de9a39 3173 PPC_MEM_EIEIO | PPC_MEM_TLBIE)
a750fc0b
JM		 3174/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3175#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3176 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3177 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
12de9a39
JM		 3178 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3179 PPC_SEGMENT)
a750fc0b
JM		 3180
3181/* POWER : same as 601, without mfmsr, mfsr */
3182#if defined(TODO)
3183#define POWERPC_INSNS_POWER (XXX_TODO)
3184/* POWER RSC (from RAD6000) */
3185#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3186#endif /* TODO */
3187
3188/* PowerPC 601 */
d63001d1 3189#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
12de9a39 3190 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
a750fc0b
JM		 3191#define POWERPC_MSRM_601 (0x000000000000FE70ULL)
3192//#define POWERPC_MMU_601 (POWERPC_MMU_601)
3193//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3194#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 3195#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
d26bfc9a 3196#define POWERPC_FLAG_601 (POWERPC_FLAG_NONE)
a750fc0b
JM		 3197
3198static void init_proc_601 (CPUPPCState *env)
3fc6c082 3199{
a750fc0b
JM		 3200 gen_spr_ne_601(env);
3201 gen_spr_601(env);
3202 /* Hardware implementation registers */
3203 /* XXX : not implemented */
3204 spr_register(env, SPR_HID0, "HID0",
3205 SPR_NOACCESS, SPR_NOACCESS,
3206 &spr_read_generic, &spr_write_generic,
3207 0x00000000);
3208 /* XXX : not implemented */
3209 spr_register(env, SPR_HID1, "HID1",
3210 SPR_NOACCESS, SPR_NOACCESS,
3211 &spr_read_generic, &spr_write_generic,
3212 0x00000000);
3213 /* XXX : not implemented */
3214 spr_register(env, SPR_601_HID2, "HID2",
3215 SPR_NOACCESS, SPR_NOACCESS,
3216 &spr_read_generic, &spr_write_generic,
3217 0x00000000);
3218 /* XXX : not implemented */
3219 spr_register(env, SPR_601_HID5, "HID5",
3220 SPR_NOACCESS, SPR_NOACCESS,
3221 &spr_read_generic, &spr_write_generic,
3222 0x00000000);
3223 /* XXX : not implemented */
3224 spr_register(env, SPR_601_HID15, "HID15",
3225 SPR_NOACCESS, SPR_NOACCESS,
3226 &spr_read_generic, &spr_write_generic,
3227 0x00000000);
3228 /* Memory management */
f2e63a42 3229#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3230 env->nb_tlb = 64;
3231 env->nb_ways = 2;
3232 env->id_tlbs = 0;
f2e63a42 3233#endif
e1833e1f 3234 init_excp_601(env);
d63001d1
JM		 3235 env->dcache_line_size = 64;
3236 env->icache_line_size = 64;
a750fc0b 3237 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3238}
3239
a750fc0b
JM		 3240/* PowerPC 602 */
3241#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3242 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3243 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
d63001d1 3244 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
12de9a39 3245 PPC_SEGMENT | PPC_602_SPEC)
a750fc0b
JM		 3246#define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3247#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3248//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3249#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 3250#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
d26bfc9a 3251#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3252
3253static void init_proc_602 (CPUPPCState *env)
3fc6c082 3254{
a750fc0b
JM		 3255 gen_spr_ne_601(env);
3256 gen_spr_602(env);
3257 /* Time base */
3258 gen_tbl(env);
3259 /* hardware implementation registers */
3260 /* XXX : not implemented */
3261 spr_register(env, SPR_HID0, "HID0",
3262 SPR_NOACCESS, SPR_NOACCESS,
3263 &spr_read_generic, &spr_write_generic,
3264 0x00000000);
3265 /* XXX : not implemented */
3266 spr_register(env, SPR_HID1, "HID1",
3267 SPR_NOACCESS, SPR_NOACCESS,
3268 &spr_read_generic, &spr_write_generic,
3269 0x00000000);
3270 /* Memory management */
3271 gen_low_BATs(env);
3272 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3273 init_excp_602(env);
d63001d1
JM		 3274 env->dcache_line_size = 32;
3275 env->icache_line_size = 32;
a750fc0b
JM		 3276 /* Allocate hardware IRQ controller */
3277 ppc6xx_irq_init(env);
3278}
3fc6c082 3279
a750fc0b
JM		 3280/* PowerPC 603 */
3281#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3282#define POWERPC_MSRM_603 (0x000000000001FF73ULL)
3283#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3284//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3285#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 3286#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
d26bfc9a 3287#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3288
3289static void init_proc_603 (CPUPPCState *env)
3290{
3291 gen_spr_ne_601(env);
3292 gen_spr_603(env);
3293 /* Time base */
3294 gen_tbl(env);
3295 /* hardware implementation registers */
3296 /* XXX : not implemented */
3297 spr_register(env, SPR_HID0, "HID0",
3298 SPR_NOACCESS, SPR_NOACCESS,
3299 &spr_read_generic, &spr_write_generic,
3300 0x00000000);
3301 /* XXX : not implemented */
3302 spr_register(env, SPR_HID1, "HID1",
3303 SPR_NOACCESS, SPR_NOACCESS,
3304 &spr_read_generic, &spr_write_generic,
3305 0x00000000);
3306 /* Memory management */
3307 gen_low_BATs(env);
3308 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3309 init_excp_603(env);
d63001d1
JM		 3310 env->dcache_line_size = 32;
3311 env->icache_line_size = 32;
a750fc0b
JM		 3312 /* Allocate hardware IRQ controller */
3313 ppc6xx_irq_init(env);
3fc6c082
FB		 3314}
3315
a750fc0b
JM		 3316/* PowerPC 603e */
3317#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3318#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3319#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3320//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3321#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 3322#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
d26bfc9a 3323#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3324
3325static void init_proc_603E (CPUPPCState *env)
3326{
3327 gen_spr_ne_601(env);
3328 gen_spr_603(env);
3329 /* Time base */
3330 gen_tbl(env);
3331 /* hardware implementation registers */
3332 /* XXX : not implemented */
3333 spr_register(env, SPR_HID0, "HID0",
3334 SPR_NOACCESS, SPR_NOACCESS,
3335 &spr_read_generic, &spr_write_generic,
3336 0x00000000);
3337 /* XXX : not implemented */
3338 spr_register(env, SPR_HID1, "HID1",
3339 SPR_NOACCESS, SPR_NOACCESS,
3340 &spr_read_generic, &spr_write_generic,
3341 0x00000000);
3342 /* XXX : not implemented */
3343 spr_register(env, SPR_IABR, "IABR",
3344 SPR_NOACCESS, SPR_NOACCESS,
3345 &spr_read_generic, &spr_write_generic,
3346 0x00000000);
3347 /* Memory management */
3348 gen_low_BATs(env);
3349 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3350 init_excp_603(env);
d63001d1
JM		 3351 env->dcache_line_size = 32;
3352 env->icache_line_size = 32;
a750fc0b
JM		 3353 /* Allocate hardware IRQ controller */
3354 ppc6xx_irq_init(env);
3355}
3356
3357/* PowerPC G2 */
3358#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3359#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3360#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3361//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3362#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
237c0af0 3363#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
d26bfc9a 3364#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3365
3366static void init_proc_G2 (CPUPPCState *env)
3367{
3368 gen_spr_ne_601(env);
3369 gen_spr_G2_755(env);
3370 gen_spr_G2(env);
3371 /* Time base */
3372 gen_tbl(env);
3373 /* Hardware implementation register */
3374 /* XXX : not implemented */
3375 spr_register(env, SPR_HID0, "HID0",
3376 SPR_NOACCESS, SPR_NOACCESS,
3377 &spr_read_generic, &spr_write_generic,
3378 0x00000000);
3379 /* XXX : not implemented */
3380 spr_register(env, SPR_HID1, "HID1",
3381 SPR_NOACCESS, SPR_NOACCESS,
3382 &spr_read_generic, &spr_write_generic,
3383 0x00000000);
3384 /* XXX : not implemented */
3385 spr_register(env, SPR_HID2, "HID2",
3386 SPR_NOACCESS, SPR_NOACCESS,
3387 &spr_read_generic, &spr_write_generic,
3388 0x00000000);
3389 /* Memory management */
3390 gen_low_BATs(env);
3391 gen_high_BATs(env);
3392 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3393 init_excp_G2(env);
d63001d1
JM		 3394 env->dcache_line_size = 32;
3395 env->icache_line_size = 32;
a750fc0b
JM		 3396 /* Allocate hardware IRQ controller */
3397 ppc6xx_irq_init(env);
3398}
3399
3400/* PowerPC G2LE */
3401#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3402#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3403#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3404#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3405#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
237c0af0 3406#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
d26bfc9a 3407#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3408
3409static void init_proc_G2LE (CPUPPCState *env)
3410{
3411 gen_spr_ne_601(env);
3412 gen_spr_G2_755(env);
3413 gen_spr_G2(env);
3414 /* Time base */
3415 gen_tbl(env);
3416 /* Hardware implementation register */
3417 /* XXX : not implemented */
3418 spr_register(env, SPR_HID0, "HID0",
3419 SPR_NOACCESS, SPR_NOACCESS,
3420 &spr_read_generic, &spr_write_generic,
3421 0x00000000);
3422 /* XXX : not implemented */
3423 spr_register(env, SPR_HID1, "HID1",
3424 SPR_NOACCESS, SPR_NOACCESS,
3425 &spr_read_generic, &spr_write_generic,
3426 0x00000000);
3427 /* XXX : not implemented */
3428 spr_register(env, SPR_HID2, "HID2",
3429 SPR_NOACCESS, SPR_NOACCESS,
3430 &spr_read_generic, &spr_write_generic,
3431 0x00000000);
3432 /* Memory management */
3433 gen_low_BATs(env);
3434 gen_high_BATs(env);
3435 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3436 init_excp_G2(env);
d63001d1
JM		 3437 env->dcache_line_size = 32;
3438 env->icache_line_size = 32;
a750fc0b
JM		 3439 /* Allocate hardware IRQ controller */
3440 ppc6xx_irq_init(env);
3441}
3442
3443/* PowerPC 604 */
3444#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3445#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3446#define POWERPC_MMU_604 (POWERPC_MMU_32B)
3447//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3448#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 3449#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
d26bfc9a 3450#define POWERPC_FLAG_604 (POWERPC_FLAG_NONE)
a750fc0b
JM		 3451
3452static void init_proc_604 (CPUPPCState *env)
3453{
3454 gen_spr_ne_601(env);
3455 gen_spr_604(env);
3456 /* Time base */
3457 gen_tbl(env);
3458 /* Hardware implementation registers */
3459 /* XXX : not implemented */
3460 spr_register(env, SPR_HID0, "HID0",
3461 SPR_NOACCESS, SPR_NOACCESS,
3462 &spr_read_generic, &spr_write_generic,
3463 0x00000000);
3464 /* XXX : not implemented */
3465 spr_register(env, SPR_HID1, "HID1",
3466 SPR_NOACCESS, SPR_NOACCESS,
3467 &spr_read_generic, &spr_write_generic,
3468 0x00000000);
3469 /* Memory management */
3470 gen_low_BATs(env);
e1833e1f 3471 init_excp_604(env);
d63001d1
JM		 3472 env->dcache_line_size = 32;
3473 env->icache_line_size = 32;
a750fc0b
JM		 3474 /* Allocate hardware IRQ controller */
3475 ppc6xx_irq_init(env);
3476}
3477
3478/* PowerPC 740/750 (aka G3) */
3479#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3480#define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
3481#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3482//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3483#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
237c0af0 3484#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
d26bfc9a 3485#define POWERPC_FLAG_7x0 (POWERPC_FLAG_NONE)
a750fc0b
JM		 3486
3487static void init_proc_7x0 (CPUPPCState *env)
3488{
3489 gen_spr_ne_601(env);
3490 gen_spr_7xx(env);
3491 /* Time base */
3492 gen_tbl(env);
3493 /* Thermal management */
3494 gen_spr_thrm(env);
3495 /* Hardware implementation registers */
3496 /* XXX : not implemented */
3497 spr_register(env, SPR_HID0, "HID0",
3498 SPR_NOACCESS, SPR_NOACCESS,
3499 &spr_read_generic, &spr_write_generic,
3500 0x00000000);
3501 /* XXX : not implemented */
3502 spr_register(env, SPR_HID1, "HID1",
3503 SPR_NOACCESS, SPR_NOACCESS,
3504 &spr_read_generic, &spr_write_generic,
3505 0x00000000);
3506 /* Memory management */
3507 gen_low_BATs(env);
e1833e1f 3508 init_excp_7x0(env);
d63001d1
JM		 3509 env->dcache_line_size = 32;
3510 env->icache_line_size = 32;
a750fc0b
JM		 3511 /* Allocate hardware IRQ controller */
3512 ppc6xx_irq_init(env);
3513}
3514
3515/* PowerPC 750FX/GX */
3516#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3517#define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
3518#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3519#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3520#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 3521#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
d26bfc9a 3522#define POWERPC_FLAG_750fx (POWERPC_FLAG_NONE)
a750fc0b
JM		 3523
3524static void init_proc_750fx (CPUPPCState *env)
3525{
3526 gen_spr_ne_601(env);
3527 gen_spr_7xx(env);
3528 /* Time base */
3529 gen_tbl(env);
3530 /* Thermal management */
3531 gen_spr_thrm(env);
3532 /* Hardware implementation registers */
3533 /* XXX : not implemented */
3534 spr_register(env, SPR_HID0, "HID0",
3535 SPR_NOACCESS, SPR_NOACCESS,
3536 &spr_read_generic, &spr_write_generic,
3537 0x00000000);
3538 /* XXX : not implemented */
3539 spr_register(env, SPR_HID1, "HID1",
3540 SPR_NOACCESS, SPR_NOACCESS,
3541 &spr_read_generic, &spr_write_generic,
3542 0x00000000);
3543 /* XXX : not implemented */
3544 spr_register(env, SPR_750_HID2, "HID2",
3545 SPR_NOACCESS, SPR_NOACCESS,
3546 &spr_read_generic, &spr_write_generic,
3547 0x00000000);
3548 /* Memory management */
3549 gen_low_BATs(env);
3550 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3551 gen_high_BATs(env);
e1833e1f 3552 init_excp_750FX(env);
d63001d1
JM		 3553 env->dcache_line_size = 32;
3554 env->icache_line_size = 32;
a750fc0b
JM		 3555 /* Allocate hardware IRQ controller */
3556 ppc6xx_irq_init(env);
3557}
3558
3559/* PowerPC 745/755 */
3560#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3561#define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
3562#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3563//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3564#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
237c0af0 3565#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
d26bfc9a 3566#define POWERPC_FLAG_7x5 (POWERPC_FLAG_NONE)
a750fc0b
JM		 3567
3568static void init_proc_7x5 (CPUPPCState *env)
3569{
3570 gen_spr_ne_601(env);
3571 gen_spr_G2_755(env);
3572 /* Time base */
3573 gen_tbl(env);
3574 /* L2 cache control */
3575 /* XXX : not implemented */
3576 spr_register(env, SPR_ICTC, "ICTC",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 /* XXX : not implemented */
3581 spr_register(env, SPR_L2PMCR, "L2PMCR",
3582 SPR_NOACCESS, SPR_NOACCESS,
3583 &spr_read_generic, &spr_write_generic,
3584 0x00000000);
3585 /* Hardware implementation registers */
3586 /* XXX : not implemented */
3587 spr_register(env, SPR_HID0, "HID0",
3588 SPR_NOACCESS, SPR_NOACCESS,
3589 &spr_read_generic, &spr_write_generic,
3590 0x00000000);
3591 /* XXX : not implemented */
3592 spr_register(env, SPR_HID1, "HID1",
3593 SPR_NOACCESS, SPR_NOACCESS,
3594 &spr_read_generic, &spr_write_generic,
3595 0x00000000);
3596 /* XXX : not implemented */
3597 spr_register(env, SPR_HID2, "HID2",
3598 SPR_NOACCESS, SPR_NOACCESS,
3599 &spr_read_generic, &spr_write_generic,
3600 0x00000000);
3601 /* Memory management */
3602 gen_low_BATs(env);
3603 gen_high_BATs(env);
3604 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 3605 init_excp_7x5(env);
d63001d1
JM		 3606 env->dcache_line_size = 32;
3607 env->icache_line_size = 32;
a750fc0b
JM		 3608 /* Allocate hardware IRQ controller */
3609 ppc6xx_irq_init(env);
d63001d1
JM		 3610#if !defined(CONFIG_USER_ONLY)
3611 /* Hardware reset vector */
3612 env->hreset_vector = 0xFFFFFFFCUL;
3613#endif
a750fc0b
JM		 3614}
3615
3616/* PowerPC 7400 (aka G4) */
3617#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3618 PPC_EXTERN | PPC_MEM_TLBIA | \
3619 PPC_ALTIVEC)
3620#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3621#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3622#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3623#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 3624#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
d26bfc9a 3625#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE)
a750fc0b
JM		 3626
3627static void init_proc_7400 (CPUPPCState *env)
3628{
3629 gen_spr_ne_601(env);
3630 gen_spr_7xx(env);
3631 /* Time base */
3632 gen_tbl(env);
3633 /* 74xx specific SPR */
3634 gen_spr_74xx(env);
3635 /* Thermal management */
3636 gen_spr_thrm(env);
3637 /* Memory management */
3638 gen_low_BATs(env);
e1833e1f 3639 init_excp_7400(env);
d63001d1
JM		 3640 env->dcache_line_size = 32;
3641 env->icache_line_size = 32;
a750fc0b
JM		 3642 /* Allocate hardware IRQ controller */
3643 ppc6xx_irq_init(env);
3644}
3645
3646/* PowerPC 7410 (aka G4) */
3647#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3648 PPC_EXTERN | PPC_MEM_TLBIA | \
3649 PPC_ALTIVEC)
3650#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3651#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3652#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3653#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 3654#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
d26bfc9a 3655#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE)
a750fc0b
JM		 3656
3657static void init_proc_7410 (CPUPPCState *env)
3658{
3659 gen_spr_ne_601(env);
3660 gen_spr_7xx(env);
3661 /* Time base */
3662 gen_tbl(env);
3663 /* 74xx specific SPR */
3664 gen_spr_74xx(env);
3665 /* Thermal management */
3666 gen_spr_thrm(env);
3667 /* L2PMCR */
3668 /* XXX : not implemented */
3669 spr_register(env, SPR_L2PMCR, "L2PMCR",
3670 SPR_NOACCESS, SPR_NOACCESS,
3671 &spr_read_generic, &spr_write_generic,
3672 0x00000000);
3673 /* LDSTDB */
3674 /* XXX : not implemented */
3675 spr_register(env, SPR_LDSTDB, "LDSTDB",
3676 SPR_NOACCESS, SPR_NOACCESS,
3677 &spr_read_generic, &spr_write_generic,
3678 0x00000000);
3679 /* Memory management */
3680 gen_low_BATs(env);
e1833e1f 3681 init_excp_7400(env);
d63001d1
JM		 3682 env->dcache_line_size = 32;
3683 env->icache_line_size = 32;
a750fc0b
JM		 3684 /* Allocate hardware IRQ controller */
3685 ppc6xx_irq_init(env);
3686}
3687
3688/* PowerPC 7440 (aka G4) */
a750fc0b
JM		 3689#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3690 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3691 PPC_ALTIVEC)
3692#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3693#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3694#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3695#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 3696#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
d26bfc9a 3697#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE)
a750fc0b 3698
578bb252 3699__attribute__ (( unused ))
a750fc0b
JM		 3700static void init_proc_7440 (CPUPPCState *env)
3701{
3702 gen_spr_ne_601(env);
3703 gen_spr_7xx(env);
3704 /* Time base */
3705 gen_tbl(env);
3706 /* 74xx specific SPR */
3707 gen_spr_74xx(env);
3708 /* LDSTCR */
3709 /* XXX : not implemented */
3710 spr_register(env, SPR_LDSTCR, "LDSTCR",
3711 SPR_NOACCESS, SPR_NOACCESS,
3712 &spr_read_generic, &spr_write_generic,
3713 0x00000000);
3714 /* ICTRL */
3715 /* XXX : not implemented */
3716 spr_register(env, SPR_ICTRL, "ICTRL",
3717 SPR_NOACCESS, SPR_NOACCESS,
3718 &spr_read_generic, &spr_write_generic,
3719 0x00000000);
3720 /* MSSSR0 */
578bb252 3721 /* XXX : not implemented */
a750fc0b
JM		 3722 spr_register(env, SPR_MSSSR0, "MSSSR0",
3723 SPR_NOACCESS, SPR_NOACCESS,
3724 &spr_read_generic, &spr_write_generic,
3725 0x00000000);
3726 /* PMC */
3727 /* XXX : not implemented */
3728 spr_register(env, SPR_PMC5, "PMC5",
3729 SPR_NOACCESS, SPR_NOACCESS,
3730 &spr_read_generic, &spr_write_generic,
3731 0x00000000);
578bb252 3732 /* XXX : not implemented */
a750fc0b
JM		 3733 spr_register(env, SPR_UPMC5, "UPMC5",
3734 &spr_read_ureg, SPR_NOACCESS,
3735 &spr_read_ureg, SPR_NOACCESS,
3736 0x00000000);
578bb252 3737 /* XXX : not implemented */
a750fc0b
JM		 3738 spr_register(env, SPR_PMC6, "PMC6",
3739 SPR_NOACCESS, SPR_NOACCESS,
3740 &spr_read_generic, &spr_write_generic,
3741 0x00000000);
578bb252 3742 /* XXX : not implemented */
a750fc0b
JM		 3743 spr_register(env, SPR_UPMC6, "UPMC6",
3744 &spr_read_ureg, SPR_NOACCESS,
3745 &spr_read_ureg, SPR_NOACCESS,
3746 0x00000000);
3747 /* Memory management */
3748 gen_low_BATs(env);
578bb252 3749 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 3750 init_excp_7450(env);
d63001d1
JM		 3751 env->dcache_line_size = 32;
3752 env->icache_line_size = 32;
a750fc0b
JM		 3753 /* Allocate hardware IRQ controller */
3754 ppc6xx_irq_init(env);
3755}
a750fc0b
JM		 3756
3757/* PowerPC 7450 (aka G4) */
a750fc0b
JM		 3758#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3759 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3760 PPC_ALTIVEC)
3761#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3762#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3763#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3764#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 3765#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
d26bfc9a 3766#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE)
a750fc0b 3767
578bb252 3768__attribute__ (( unused ))
a750fc0b
JM		 3769static void init_proc_7450 (CPUPPCState *env)
3770{
3771 gen_spr_ne_601(env);
3772 gen_spr_7xx(env);
3773 /* Time base */
3774 gen_tbl(env);
3775 /* 74xx specific SPR */
3776 gen_spr_74xx(env);
3777 /* Level 3 cache control */
3778 gen_l3_ctrl(env);
3779 /* LDSTCR */
3780 /* XXX : not implemented */
3781 spr_register(env, SPR_LDSTCR, "LDSTCR",
3782 SPR_NOACCESS, SPR_NOACCESS,
3783 &spr_read_generic, &spr_write_generic,
3784 0x00000000);
3785 /* ICTRL */
3786 /* XXX : not implemented */
3787 spr_register(env, SPR_ICTRL, "ICTRL",
3788 SPR_NOACCESS, SPR_NOACCESS,
3789 &spr_read_generic, &spr_write_generic,
3790 0x00000000);
3791 /* MSSSR0 */
578bb252 3792 /* XXX : not implemented */
a750fc0b
JM		 3793 spr_register(env, SPR_MSSSR0, "MSSSR0",
3794 SPR_NOACCESS, SPR_NOACCESS,
3795 &spr_read_generic, &spr_write_generic,
3796 0x00000000);
3797 /* PMC */
3798 /* XXX : not implemented */
3799 spr_register(env, SPR_PMC5, "PMC5",
3800 SPR_NOACCESS, SPR_NOACCESS,
3801 &spr_read_generic, &spr_write_generic,
3802 0x00000000);
578bb252 3803 /* XXX : not implemented */
a750fc0b
JM		 3804 spr_register(env, SPR_UPMC5, "UPMC5",
3805 &spr_read_ureg, SPR_NOACCESS,
3806 &spr_read_ureg, SPR_NOACCESS,
3807 0x00000000);
578bb252 3808 /* XXX : not implemented */
a750fc0b
JM		 3809 spr_register(env, SPR_PMC6, "PMC6",
3810 SPR_NOACCESS, SPR_NOACCESS,
3811 &spr_read_generic, &spr_write_generic,
3812 0x00000000);
578bb252 3813 /* XXX : not implemented */
a750fc0b
JM		 3814 spr_register(env, SPR_UPMC6, "UPMC6",
3815 &spr_read_ureg, SPR_NOACCESS,
3816 &spr_read_ureg, SPR_NOACCESS,
3817 0x00000000);
3818 /* Memory management */
3819 gen_low_BATs(env);
578bb252 3820 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3821 init_excp_7450(env);
d63001d1
JM		 3822 env->dcache_line_size = 32;
3823 env->icache_line_size = 32;
a750fc0b
JM		 3824 /* Allocate hardware IRQ controller */
3825 ppc6xx_irq_init(env);
3826}
a750fc0b
JM		 3827
3828/* PowerPC 7445 (aka G4) */
a750fc0b
JM		 3829#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3830 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3831 PPC_ALTIVEC)
3832#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3833#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3834#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3835#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 3836#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
d26bfc9a 3837#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE)
a750fc0b 3838
578bb252 3839__attribute__ (( unused ))
a750fc0b
JM		 3840static void init_proc_7445 (CPUPPCState *env)
3841{
3842 gen_spr_ne_601(env);
3843 gen_spr_7xx(env);
3844 /* Time base */
3845 gen_tbl(env);
3846 /* 74xx specific SPR */
3847 gen_spr_74xx(env);
3848 /* LDSTCR */
3849 /* XXX : not implemented */
3850 spr_register(env, SPR_LDSTCR, "LDSTCR",
3851 SPR_NOACCESS, SPR_NOACCESS,
3852 &spr_read_generic, &spr_write_generic,
3853 0x00000000);
3854 /* ICTRL */
3855 /* XXX : not implemented */
3856 spr_register(env, SPR_ICTRL, "ICTRL",
3857 SPR_NOACCESS, SPR_NOACCESS,
3858 &spr_read_generic, &spr_write_generic,
3859 0x00000000);
3860 /* MSSSR0 */
578bb252 3861 /* XXX : not implemented */
a750fc0b
JM		 3862 spr_register(env, SPR_MSSSR0, "MSSSR0",
3863 SPR_NOACCESS, SPR_NOACCESS,
3864 &spr_read_generic, &spr_write_generic,
3865 0x00000000);
3866 /* PMC */
3867 /* XXX : not implemented */
3868 spr_register(env, SPR_PMC5, "PMC5",
3869 SPR_NOACCESS, SPR_NOACCESS,
3870 &spr_read_generic, &spr_write_generic,
3871 0x00000000);
578bb252 3872 /* XXX : not implemented */
a750fc0b
JM		 3873 spr_register(env, SPR_UPMC5, "UPMC5",
3874 &spr_read_ureg, SPR_NOACCESS,
3875 &spr_read_ureg, SPR_NOACCESS,
3876 0x00000000);
578bb252 3877 /* XXX : not implemented */
a750fc0b
JM		 3878 spr_register(env, SPR_PMC6, "PMC6",
3879 SPR_NOACCESS, SPR_NOACCESS,
3880 &spr_read_generic, &spr_write_generic,
3881 0x00000000);
578bb252 3882 /* XXX : not implemented */
a750fc0b
JM		 3883 spr_register(env, SPR_UPMC6, "UPMC6",
3884 &spr_read_ureg, SPR_NOACCESS,
3885 &spr_read_ureg, SPR_NOACCESS,
3886 0x00000000);
3887 /* SPRGs */
3888 spr_register(env, SPR_SPRG4, "SPRG4",
3889 SPR_NOACCESS, SPR_NOACCESS,
3890 &spr_read_generic, &spr_write_generic,
3891 0x00000000);
3892 spr_register(env, SPR_USPRG4, "USPRG4",
3893 &spr_read_ureg, SPR_NOACCESS,
3894 &spr_read_ureg, SPR_NOACCESS,
3895 0x00000000);
3896 spr_register(env, SPR_SPRG5, "SPRG5",
3897 SPR_NOACCESS, SPR_NOACCESS,
3898 &spr_read_generic, &spr_write_generic,
3899 0x00000000);
3900 spr_register(env, SPR_USPRG5, "USPRG5",
3901 &spr_read_ureg, SPR_NOACCESS,
3902 &spr_read_ureg, SPR_NOACCESS,
3903 0x00000000);
3904 spr_register(env, SPR_SPRG6, "SPRG6",
3905 SPR_NOACCESS, SPR_NOACCESS,
3906 &spr_read_generic, &spr_write_generic,
3907 0x00000000);
3908 spr_register(env, SPR_USPRG6, "USPRG6",
3909 &spr_read_ureg, SPR_NOACCESS,
3910 &spr_read_ureg, SPR_NOACCESS,
3911 0x00000000);
3912 spr_register(env, SPR_SPRG7, "SPRG7",
3913 SPR_NOACCESS, SPR_NOACCESS,
3914 &spr_read_generic, &spr_write_generic,
3915 0x00000000);
3916 spr_register(env, SPR_USPRG7, "USPRG7",
3917 &spr_read_ureg, SPR_NOACCESS,
3918 &spr_read_ureg, SPR_NOACCESS,
3919 0x00000000);
3920 /* Memory management */
3921 gen_low_BATs(env);
3922 gen_high_BATs(env);
578bb252 3923 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3924 init_excp_7450(env);
d63001d1
JM		 3925 env->dcache_line_size = 32;
3926 env->icache_line_size = 32;
a750fc0b
JM		 3927 /* Allocate hardware IRQ controller */
3928 ppc6xx_irq_init(env);
3929}
a750fc0b
JM		 3930
3931/* PowerPC 7455 (aka G4) */
a750fc0b
JM		 3932#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3933 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3934 PPC_ALTIVEC)
3935#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3936#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3937#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3938#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 3939#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
d26bfc9a 3940#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE)
a750fc0b 3941
578bb252 3942__attribute__ (( unused ))
a750fc0b
JM		 3943static void init_proc_7455 (CPUPPCState *env)
3944{
3945 gen_spr_ne_601(env);
3946 gen_spr_7xx(env);
3947 /* Time base */
3948 gen_tbl(env);
3949 /* 74xx specific SPR */
3950 gen_spr_74xx(env);
3951 /* Level 3 cache control */
3952 gen_l3_ctrl(env);
3953 /* LDSTCR */
3954 /* XXX : not implemented */
3955 spr_register(env, SPR_LDSTCR, "LDSTCR",
3956 SPR_NOACCESS, SPR_NOACCESS,
3957 &spr_read_generic, &spr_write_generic,
3958 0x00000000);
3959 /* ICTRL */
3960 /* XXX : not implemented */
3961 spr_register(env, SPR_ICTRL, "ICTRL",
3962 SPR_NOACCESS, SPR_NOACCESS,
3963 &spr_read_generic, &spr_write_generic,
3964 0x00000000);
3965 /* MSSSR0 */
578bb252 3966 /* XXX : not implemented */
a750fc0b
JM		 3967 spr_register(env, SPR_MSSSR0, "MSSSR0",
3968 SPR_NOACCESS, SPR_NOACCESS,
3969 &spr_read_generic, &spr_write_generic,
3970 0x00000000);
3971 /* PMC */
3972 /* XXX : not implemented */
3973 spr_register(env, SPR_PMC5, "PMC5",
3974 SPR_NOACCESS, SPR_NOACCESS,
3975 &spr_read_generic, &spr_write_generic,
3976 0x00000000);
578bb252 3977 /* XXX : not implemented */
a750fc0b
JM		 3978 spr_register(env, SPR_UPMC5, "UPMC5",
3979 &spr_read_ureg, SPR_NOACCESS,
3980 &spr_read_ureg, SPR_NOACCESS,
3981 0x00000000);
578bb252 3982 /* XXX : not implemented */
a750fc0b
JM		 3983 spr_register(env, SPR_PMC6, "PMC6",
3984 SPR_NOACCESS, SPR_NOACCESS,
3985 &spr_read_generic, &spr_write_generic,
3986 0x00000000);
578bb252 3987 /* XXX : not implemented */
a750fc0b
JM		 3988 spr_register(env, SPR_UPMC6, "UPMC6",
3989 &spr_read_ureg, SPR_NOACCESS,
3990 &spr_read_ureg, SPR_NOACCESS,
3991 0x00000000);
3992 /* SPRGs */
3993 spr_register(env, SPR_SPRG4, "SPRG4",
3994 SPR_NOACCESS, SPR_NOACCESS,
3995 &spr_read_generic, &spr_write_generic,
3996 0x00000000);
3997 spr_register(env, SPR_USPRG4, "USPRG4",
3998 &spr_read_ureg, SPR_NOACCESS,
3999 &spr_read_ureg, SPR_NOACCESS,
4000 0x00000000);
4001 spr_register(env, SPR_SPRG5, "SPRG5",
4002 SPR_NOACCESS, SPR_NOACCESS,
4003 &spr_read_generic, &spr_write_generic,
4004 0x00000000);
4005 spr_register(env, SPR_USPRG5, "USPRG5",
4006 &spr_read_ureg, SPR_NOACCESS,
4007 &spr_read_ureg, SPR_NOACCESS,
4008 0x00000000);
4009 spr_register(env, SPR_SPRG6, "SPRG6",
4010 SPR_NOACCESS, SPR_NOACCESS,
4011 &spr_read_generic, &spr_write_generic,
4012 0x00000000);
4013 spr_register(env, SPR_USPRG6, "USPRG6",
4014 &spr_read_ureg, SPR_NOACCESS,
4015 &spr_read_ureg, SPR_NOACCESS,
4016 0x00000000);
4017 spr_register(env, SPR_SPRG7, "SPRG7",
4018 SPR_NOACCESS, SPR_NOACCESS,
4019 &spr_read_generic, &spr_write_generic,
4020 0x00000000);
4021 spr_register(env, SPR_USPRG7, "USPRG7",
4022 &spr_read_ureg, SPR_NOACCESS,
4023 &spr_read_ureg, SPR_NOACCESS,
4024 0x00000000);
4025 /* Memory management */
4026 gen_low_BATs(env);
4027 gen_high_BATs(env);
578bb252 4028 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 4029 init_excp_7450(env);
d63001d1
JM		 4030 env->dcache_line_size = 32;
4031 env->icache_line_size = 32;
a750fc0b
JM		 4032 /* Allocate hardware IRQ controller */
4033 ppc6xx_irq_init(env);
4034}
a750fc0b
JM		 4035
4036#if defined (TARGET_PPC64)
d63001d1 4037#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
12de9a39
JM		 4038 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4039 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4040 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
a750fc0b 4041/* PowerPC 970 */
d63001d1 4042#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4043 PPC_64B | PPC_ALTIVEC | \
12de9a39 4044 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4045#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 4046#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 4047//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4048#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 4049#define POWERPC_BFDM_970 (bfd_mach_ppc64)
d26bfc9a 4050#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE)
a750fc0b 4051
417bf010
JM		 4052#if defined(CONFIG_USER_ONLY)
4053#define POWERPC970_HID5_INIT 0x00000080
4054#else
4055#define POWERPC970_HID5_INIT 0x00000000
4056#endif
4057
a750fc0b
JM		 4058static void init_proc_970 (CPUPPCState *env)
4059{
4060 gen_spr_ne_601(env);
4061 gen_spr_7xx(env);
4062 /* Time base */
4063 gen_tbl(env);
4064 /* Hardware implementation registers */
4065 /* XXX : not implemented */
4066 spr_register(env, SPR_HID0, "HID0",
4067 SPR_NOACCESS, SPR_NOACCESS,
06403421 4068 &spr_read_generic, &spr_write_clear,
d63001d1 4069 0x60000000);
a750fc0b
JM		 4070 /* XXX : not implemented */
4071 spr_register(env, SPR_HID1, "HID1",
4072 SPR_NOACCESS, SPR_NOACCESS,
4073 &spr_read_generic, &spr_write_generic,
4074 0x00000000);
4075 /* XXX : not implemented */
4076 spr_register(env, SPR_750_HID2, "HID2",
4077 SPR_NOACCESS, SPR_NOACCESS,
4078 &spr_read_generic, &spr_write_generic,
4079 0x00000000);
e57448f1
JM		 4080 /* XXX : not implemented */
4081 spr_register(env, SPR_970_HID5, "HID5",
4082 SPR_NOACCESS, SPR_NOACCESS,
4083 &spr_read_generic, &spr_write_generic,
417bf010 4084 POWERPC970_HID5_INIT);
a750fc0b
JM		 4085 /* Memory management */
4086 /* XXX: not correct */
4087 gen_low_BATs(env);
12de9a39
JM		 4088 /* XXX : not implemented */
4089 spr_register(env, SPR_MMUCFG, "MMUCFG",
4090 SPR_NOACCESS, SPR_NOACCESS,
4091 &spr_read_generic, SPR_NOACCESS,
4092 0x00000000); /* TOFIX */
4093 /* XXX : not implemented */
4094 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4095 SPR_NOACCESS, SPR_NOACCESS,
4096 &spr_read_generic, &spr_write_generic,
4097 0x00000000); /* TOFIX */
4098 spr_register(env, SPR_HIOR, "SPR_HIOR",
4099 SPR_NOACCESS, SPR_NOACCESS,
4100 &spr_read_generic, &spr_write_generic,
4101 0xFFF00000); /* XXX: This is a hack */
4102#if !defined(CONFIG_USER_ONLY)
4103 env->excp_prefix = 0xFFF00000;
a750fc0b 4104#endif
f2e63a42 4105#if !defined(CONFIG_USER_ONLY)
12de9a39 4106 env->slb_nr = 32;
f2e63a42 4107#endif
e1833e1f 4108 init_excp_970(env);
d63001d1
JM		 4109 env->dcache_line_size = 128;
4110 env->icache_line_size = 128;
a750fc0b
JM		 4111 /* Allocate hardware IRQ controller */
4112 ppc970_irq_init(env);
4113}
a750fc0b
JM		 4114
4115/* PowerPC 970FX (aka G5) */
d63001d1 4116#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4117 PPC_64B | PPC_ALTIVEC | \
12de9a39 4118 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4119#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 4120#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 4121#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4122#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 4123#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
d26bfc9a 4124#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE)
a750fc0b
JM		 4125
4126static void init_proc_970FX (CPUPPCState *env)
4127{
4128 gen_spr_ne_601(env);
4129 gen_spr_7xx(env);
4130 /* Time base */
4131 gen_tbl(env);
4132 /* Hardware implementation registers */
4133 /* XXX : not implemented */
4134 spr_register(env, SPR_HID0, "HID0",
4135 SPR_NOACCESS, SPR_NOACCESS,
06403421 4136 &spr_read_generic, &spr_write_clear,
d63001d1 4137 0x60000000);
a750fc0b
JM		 4138 /* XXX : not implemented */
4139 spr_register(env, SPR_HID1, "HID1",
4140 SPR_NOACCESS, SPR_NOACCESS,
4141 &spr_read_generic, &spr_write_generic,
4142 0x00000000);
4143 /* XXX : not implemented */
4144 spr_register(env, SPR_750_HID2, "HID2",
4145 SPR_NOACCESS, SPR_NOACCESS,
4146 &spr_read_generic, &spr_write_generic,
4147 0x00000000);
d63001d1
JM		 4148 /* XXX : not implemented */
4149 spr_register(env, SPR_970_HID5, "HID5",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
417bf010 4152 POWERPC970_HID5_INIT);
a750fc0b
JM		 4153 /* Memory management */
4154 /* XXX: not correct */
4155 gen_low_BATs(env);
12de9a39
JM		 4156 /* XXX : not implemented */
4157 spr_register(env, SPR_MMUCFG, "MMUCFG",
4158 SPR_NOACCESS, SPR_NOACCESS,
4159 &spr_read_generic, SPR_NOACCESS,
4160 0x00000000); /* TOFIX */
4161 /* XXX : not implemented */
4162 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4163 SPR_NOACCESS, SPR_NOACCESS,
4164 &spr_read_generic, &spr_write_generic,
4165 0x00000000); /* TOFIX */
4166 spr_register(env, SPR_HIOR, "SPR_HIOR",
4167 SPR_NOACCESS, SPR_NOACCESS,
4168 &spr_read_generic, &spr_write_generic,
4169 0xFFF00000); /* XXX: This is a hack */
4170#if !defined(CONFIG_USER_ONLY)
4171 env->excp_prefix = 0xFFF00000;
a750fc0b 4172#endif
f2e63a42 4173#if !defined(CONFIG_USER_ONLY)
12de9a39 4174 env->slb_nr = 32;
f2e63a42 4175#endif
e1833e1f 4176 init_excp_970(env);
d63001d1
JM		 4177 env->dcache_line_size = 128;
4178 env->icache_line_size = 128;
a750fc0b
JM		 4179 /* Allocate hardware IRQ controller */
4180 ppc970_irq_init(env);
4181}
a750fc0b
JM		 4182
4183/* PowerPC 970 GX */
d63001d1 4184#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4185 PPC_64B | PPC_ALTIVEC | \
12de9a39 4186 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4187#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 4188#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 4189#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4190#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 4191#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
d26bfc9a 4192#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE)
a750fc0b
JM		 4193
4194static void init_proc_970GX (CPUPPCState *env)
4195{
4196 gen_spr_ne_601(env);
4197 gen_spr_7xx(env);
4198 /* Time base */
4199 gen_tbl(env);
4200 /* Hardware implementation registers */
4201 /* XXX : not implemented */
4202 spr_register(env, SPR_HID0, "HID0",
4203 SPR_NOACCESS, SPR_NOACCESS,
06403421 4204 &spr_read_generic, &spr_write_clear,
d63001d1 4205 0x60000000);
a750fc0b
JM		 4206 /* XXX : not implemented */
4207 spr_register(env, SPR_HID1, "HID1",
4208 SPR_NOACCESS, SPR_NOACCESS,
4209 &spr_read_generic, &spr_write_generic,
4210 0x00000000);
4211 /* XXX : not implemented */
4212 spr_register(env, SPR_750_HID2, "HID2",
4213 SPR_NOACCESS, SPR_NOACCESS,
4214 &spr_read_generic, &spr_write_generic,
4215 0x00000000);
d63001d1
JM		 4216 /* XXX : not implemented */
4217 spr_register(env, SPR_970_HID5, "HID5",
4218 SPR_NOACCESS, SPR_NOACCESS,
4219 &spr_read_generic, &spr_write_generic,
417bf010 4220 POWERPC970_HID5_INIT);
a750fc0b
JM		 4221 /* Memory management */
4222 /* XXX: not correct */
4223 gen_low_BATs(env);
12de9a39
JM		 4224 /* XXX : not implemented */
4225 spr_register(env, SPR_MMUCFG, "MMUCFG",
4226 SPR_NOACCESS, SPR_NOACCESS,
4227 &spr_read_generic, SPR_NOACCESS,
4228 0x00000000); /* TOFIX */
4229 /* XXX : not implemented */
4230 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4231 SPR_NOACCESS, SPR_NOACCESS,
4232 &spr_read_generic, &spr_write_generic,
4233 0x00000000); /* TOFIX */
4234 spr_register(env, SPR_HIOR, "SPR_HIOR",
4235 SPR_NOACCESS, SPR_NOACCESS,
4236 &spr_read_generic, &spr_write_generic,
4237 0xFFF00000); /* XXX: This is a hack */
4238#if !defined(CONFIG_USER_ONLY)
4239 env->excp_prefix = 0xFFF00000;
a750fc0b 4240#endif
f2e63a42 4241#if !defined(CONFIG_USER_ONLY)
12de9a39 4242 env->slb_nr = 32;
f2e63a42 4243#endif
e1833e1f 4244 init_excp_970(env);
d63001d1
JM		 4245 env->dcache_line_size = 128;
4246 env->icache_line_size = 128;
a750fc0b
JM		 4247 /* Allocate hardware IRQ controller */
4248 ppc970_irq_init(env);
4249}
a750fc0b
JM		 4250
4251/* PowerPC 620 */
a750fc0b
JM		 4252#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4253 PPC_64B | PPC_SLBI)
4254#define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4255#define POWERPC_MMU_620 (POWERPC_MMU_64B)
4256#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4257#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
237c0af0 4258#define POWERPC_BFDM_620 (bfd_mach_ppc64)
d26bfc9a 4259#define POWERPC_FLAG_620 (POWERPC_FLAG_NONE)
a750fc0b 4260
578bb252 4261__attribute__ (( unused ))
a750fc0b
JM		 4262static void init_proc_620 (CPUPPCState *env)
4263{
4264 gen_spr_ne_601(env);
4265 gen_spr_620(env);
4266 /* Time base */
4267 gen_tbl(env);
4268 /* Hardware implementation registers */
4269 /* XXX : not implemented */
4270 spr_register(env, SPR_HID0, "HID0",
4271 SPR_NOACCESS, SPR_NOACCESS,
4272 &spr_read_generic, &spr_write_generic,
4273 0x00000000);
4274 /* Memory management */
4275 gen_low_BATs(env);
4276 gen_high_BATs(env);
e1833e1f 4277 init_excp_620(env);
d63001d1
JM		 4278 env->dcache_line_size = 64;
4279 env->icache_line_size = 64;
a750fc0b
JM		 4280 /* XXX: TODO: initialize internal interrupt controller */
4281}
a750fc0b
JM		 4282#endif /* defined (TARGET_PPC64) */
4283
4284/* Default 32 bits PowerPC target will be 604 */
4285#define CPU_POWERPC_PPC32 CPU_POWERPC_604
4286#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4287#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4288#define POWERPC_MMU_PPC32 POWERPC_MMU_604
4289#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4290#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4291#define init_proc_PPC32 init_proc_604
237c0af0 4292#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 4293#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
a750fc0b
JM		 4294
4295/* Default 64 bits PowerPC target will be 970 FX */
4296#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4297#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4298#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4299#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4300#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4301#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4302#define init_proc_PPC64 init_proc_970FX
237c0af0 4303#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 4304#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
a750fc0b
JM		 4305
4306/* Default PowerPC target will be PowerPC 32 */
4307#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 4308#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4309#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4310#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4311#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4312#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4313#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4314#define init_proc_DEFAULT init_proc_PPC64
237c0af0 4315#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 4316#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
a750fc0b 4317#else
d12f4c38
JM		 4318#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4319#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4320#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4321#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4322#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4323#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4324#define init_proc_DEFAULT init_proc_PPC32
237c0af0 4325#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 4326#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
a750fc0b
JM		 4327#endif
4328
4329/*****************************************************************************/
4330/* PVR definitions for most known PowerPC */
4331enum {
4332 /* PowerPC 401 family */
4333 /* Generic PowerPC 401 */
4334#define CPU_POWERPC_401 CPU_POWERPC_401G2
4335 /* PowerPC 401 cores */
4336 CPU_POWERPC_401A1 = 0x00210000,
4337 CPU_POWERPC_401B2 = 0x00220000,
4338#if 0
4339 CPU_POWERPC_401B3 = xxx,
4340#endif
4341 CPU_POWERPC_401C2 = 0x00230000,
4342 CPU_POWERPC_401D2 = 0x00240000,
4343 CPU_POWERPC_401E2 = 0x00250000,
4344 CPU_POWERPC_401F2 = 0x00260000,
4345 CPU_POWERPC_401G2 = 0x00270000,
4346 /* PowerPC 401 microcontrolers */
4347#if 0
4348 CPU_POWERPC_401GF = xxx,
4349#endif
4350#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4351 /* IBM Processor for Network Resources */
4352 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4353#if 0
4354 CPU_POWERPC_XIPCHIP = xxx,
4355#endif
4356 /* PowerPC 403 family */
4357 /* Generic PowerPC 403 */
4358#define CPU_POWERPC_403 CPU_POWERPC_403GC
4359 /* PowerPC 403 microcontrollers */
4360 CPU_POWERPC_403GA = 0x00200011,
4361 CPU_POWERPC_403GB = 0x00200100,
4362 CPU_POWERPC_403GC = 0x00200200,
4363 CPU_POWERPC_403GCX = 0x00201400,
4364#if 0
4365 CPU_POWERPC_403GP = xxx,
4366#endif
4367 /* PowerPC 405 family */
4368 /* Generic PowerPC 405 */
4369#define CPU_POWERPC_405 CPU_POWERPC_405D4
4370 /* PowerPC 405 cores */
4371#if 0
4372 CPU_POWERPC_405A3 = xxx,
4373#endif
4374#if 0
4375 CPU_POWERPC_405A4 = xxx,
4376#endif
4377#if 0
4378 CPU_POWERPC_405B3 = xxx,
4379#endif
4380#if 0
4381 CPU_POWERPC_405B4 = xxx,
4382#endif
4383#if 0
4384 CPU_POWERPC_405C3 = xxx,
4385#endif
4386#if 0
4387 CPU_POWERPC_405C4 = xxx,
4388#endif
4389 CPU_POWERPC_405D2 = 0x20010000,
4390#if 0
4391 CPU_POWERPC_405D3 = xxx,
4392#endif
4393 CPU_POWERPC_405D4 = 0x41810000,
4394#if 0
4395 CPU_POWERPC_405D5 = xxx,
4396#endif
4397#if 0
4398 CPU_POWERPC_405E4 = xxx,
4399#endif
4400#if 0
4401 CPU_POWERPC_405F4 = xxx,
4402#endif
4403#if 0
4404 CPU_POWERPC_405F5 = xxx,
4405#endif
4406#if 0
4407 CPU_POWERPC_405F6 = xxx,
4408#endif
4409 /* PowerPC 405 microcontrolers */
4410 /* XXX: missing 0x200108a0 */
4411#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4412 CPU_POWERPC_405CRa = 0x40110041,
4413 CPU_POWERPC_405CRb = 0x401100C5,
4414 CPU_POWERPC_405CRc = 0x40110145,
4415 CPU_POWERPC_405EP = 0x51210950,
4416#if 0
4417 CPU_POWERPC_405EXr = xxx,
4418#endif
4419 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4420#if 0
4421 CPU_POWERPC_405FX = xxx,
4422#endif
4423#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4424 CPU_POWERPC_405GPa = 0x40110000,
4425 CPU_POWERPC_405GPb = 0x40110040,
4426 CPU_POWERPC_405GPc = 0x40110082,
4427 CPU_POWERPC_405GPd = 0x401100C4,
4428#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4429 CPU_POWERPC_405GPR = 0x50910951,
4430#if 0
4431 CPU_POWERPC_405H = xxx,
4432#endif
4433#if 0
4434 CPU_POWERPC_405L = xxx,
4435#endif
4436 CPU_POWERPC_405LP = 0x41F10000,
4437#if 0
4438 CPU_POWERPC_405PM = xxx,
4439#endif
4440#if 0
4441 CPU_POWERPC_405PS = xxx,
4442#endif
4443#if 0
4444 CPU_POWERPC_405S = xxx,
4445#endif
4446 /* IBM network processors */
4447 CPU_POWERPC_NPE405H = 0x414100C0,
4448 CPU_POWERPC_NPE405H2 = 0x41410140,
4449 CPU_POWERPC_NPE405L = 0x416100C0,
4450 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4451#if 0
4452 CPU_POWERPC_NPCxx1 = xxx,
4453#endif
4454#if 0
4455 CPU_POWERPC_NPR161 = xxx,
4456#endif
4457#if 0
4458 CPU_POWERPC_LC77700 = xxx,
4459#endif
4460 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4461#if 0
4462 CPU_POWERPC_STB01000 = xxx,
4463#endif
4464#if 0
4465 CPU_POWERPC_STB01010 = xxx,
4466#endif
4467#if 0
4468 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4469#endif
4470 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4471#if 0
4472 CPU_POWERPC_STB043 = xxx,
4473#endif
4474#if 0
4475 CPU_POWERPC_STB045 = xxx,
4476#endif
4477 CPU_POWERPC_STB04 = 0x41810000,
4478 CPU_POWERPC_STB25 = 0x51510950,
4479#if 0
4480 CPU_POWERPC_STB130 = xxx,
4481#endif
4482 /* Xilinx cores */
4483 CPU_POWERPC_X2VP4 = 0x20010820,
4484#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4485 CPU_POWERPC_X2VP20 = 0x20010860,
4486#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4487#if 0
4488 CPU_POWERPC_ZL10310 = xxx,
4489#endif
4490#if 0
4491 CPU_POWERPC_ZL10311 = xxx,
4492#endif
4493#if 0
4494 CPU_POWERPC_ZL10320 = xxx,
4495#endif
4496#if 0
4497 CPU_POWERPC_ZL10321 = xxx,
4498#endif
4499 /* PowerPC 440 family */
4500 /* Generic PowerPC 440 */
4501#define CPU_POWERPC_440 CPU_POWERPC_440GXf
4502 /* PowerPC 440 cores */
4503#if 0
4504 CPU_POWERPC_440A4 = xxx,
4505#endif
4506#if 0
4507 CPU_POWERPC_440A5 = xxx,
4508#endif
4509#if 0
4510 CPU_POWERPC_440B4 = xxx,
4511#endif
4512#if 0
4513 CPU_POWERPC_440F5 = xxx,
4514#endif
4515#if 0
4516 CPU_POWERPC_440G5 = xxx,
4517#endif
4518#if 0
4519 CPU_POWERPC_440H4 = xxx,
4520#endif
4521#if 0
4522 CPU_POWERPC_440H6 = xxx,
4523#endif
4524 /* PowerPC 440 microcontrolers */
4525#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4526 CPU_POWERPC_440EPa = 0x42221850,
4527 CPU_POWERPC_440EPb = 0x422218D3,
4528#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4529 CPU_POWERPC_440GPb = 0x40120440,
4530 CPU_POWERPC_440GPc = 0x40120481,
4531#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4532#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4533 CPU_POWERPC_440GRX = 0x200008D0,
4534#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4535#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4536 CPU_POWERPC_440GXa = 0x51B21850,
4537 CPU_POWERPC_440GXb = 0x51B21851,
4538 CPU_POWERPC_440GXc = 0x51B21892,
4539 CPU_POWERPC_440GXf = 0x51B21894,
4540#if 0
4541 CPU_POWERPC_440S = xxx,
4542#endif
4543 CPU_POWERPC_440SP = 0x53221850,
4544 CPU_POWERPC_440SP2 = 0x53221891,
4545 CPU_POWERPC_440SPE = 0x53421890,
4546 /* PowerPC 460 family */
4547#if 0
4548 /* Generic PowerPC 464 */
4549#define CPU_POWERPC_464 CPU_POWERPC_464H90
4550#endif
4551 /* PowerPC 464 microcontrolers */
4552#if 0
4553 CPU_POWERPC_464H90 = xxx,
4554#endif
4555#if 0
4556 CPU_POWERPC_464H90FP = xxx,
4557#endif
4558 /* Freescale embedded PowerPC cores */
4559 /* e200 family */
4560#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4561#if 0
4562 CPU_POWERPC_e200z0 = xxx,
4563#endif
4564#if 0
4565 CPU_POWERPC_e200z3 = xxx,
4566#endif
4567 CPU_POWERPC_e200z5 = 0x81000000,
4568 CPU_POWERPC_e200z6 = 0x81120000,
4569 /* e300 family */
4570#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4571 CPU_POWERPC_e300c1 = 0x00830000,
4572 CPU_POWERPC_e300c2 = 0x00840000,
4573 CPU_POWERPC_e300c3 = 0x00850000,
4574 /* e500 family */
4575#define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4576 CPU_POWERPC_e500_v11 = 0x80200010,
4577 CPU_POWERPC_e500_v12 = 0x80200020,
4578 CPU_POWERPC_e500_v21 = 0x80210010,
4579 CPU_POWERPC_e500_v22 = 0x80210020,
4580#if 0
4581 CPU_POWERPC_e500mc = xxx,
4582#endif
4583 /* e600 family */
4584 CPU_POWERPC_e600 = 0x80040010,
4585 /* PowerPC MPC 5xx cores */
4586 CPU_POWERPC_5xx = 0x00020020,
4587 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4588 CPU_POWERPC_8xx = 0x00500000,
4589 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4590 CPU_POWERPC_82xx_HIP3 = 0x00810101,
4591 CPU_POWERPC_82xx_HIP4 = 0x80811014,
4592 CPU_POWERPC_827x = 0x80822013,
4593 /* PowerPC 6xx cores */
4594 CPU_POWERPC_601 = 0x00010001,
4595 CPU_POWERPC_601a = 0x00010002,
4596 CPU_POWERPC_602 = 0x00050100,
4597 CPU_POWERPC_603 = 0x00030100,
4598#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4599 CPU_POWERPC_603E_v11 = 0x00060101,
4600 CPU_POWERPC_603E_v12 = 0x00060102,
4601 CPU_POWERPC_603E_v13 = 0x00060103,
4602 CPU_POWERPC_603E_v14 = 0x00060104,
4603 CPU_POWERPC_603E_v22 = 0x00060202,
4604 CPU_POWERPC_603E_v3 = 0x00060300,
4605 CPU_POWERPC_603E_v4 = 0x00060400,
4606 CPU_POWERPC_603E_v41 = 0x00060401,
4607 CPU_POWERPC_603E7t = 0x00071201,
4608 CPU_POWERPC_603E7v = 0x00070100,
4609 CPU_POWERPC_603E7v1 = 0x00070101,
4610 CPU_POWERPC_603E7v2 = 0x00070201,
4611 CPU_POWERPC_603E7 = 0x00070200,
4612 CPU_POWERPC_603P = 0x00070000,
4613#define CPU_POWERPC_603R CPU_POWERPC_603E7t
4614 CPU_POWERPC_G2 = 0x00810011,
4615#if 0 // Linux pretends the MSB is zero...
4616 CPU_POWERPC_G2H4 = 0x80811010,
4617 CPU_POWERPC_G2gp = 0x80821010,
4618 CPU_POWERPC_G2ls = 0x90810010,
4619 CPU_POWERPC_G2LE = 0x80820010,
4620 CPU_POWERPC_G2LEgp = 0x80822010,
4621 CPU_POWERPC_G2LEls = 0xA0822010,
4622#else
4623 CPU_POWERPC_G2H4 = 0x00811010,
4624 CPU_POWERPC_G2gp = 0x00821010,
4625 CPU_POWERPC_G2ls = 0x10810010,
4626 CPU_POWERPC_G2LE = 0x00820010,
4627 CPU_POWERPC_G2LEgp = 0x00822010,
4628 CPU_POWERPC_G2LEls = 0x20822010,
4629#endif
4630 CPU_POWERPC_604 = 0x00040103,
4631#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4632 CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
4633 CPU_POWERPC_604E_v22 = 0x00090202,
4634 CPU_POWERPC_604E_v24 = 0x00090204,
4635 CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
4636#if 0
4637 CPU_POWERPC_604EV = xxx,
4638#endif
4639 /* PowerPC 740/750 cores (aka G3) */
4640 /* XXX: missing 0x00084202 */
4641#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4642 CPU_POWERPC_7x0_v20 = 0x00080200,
4643 CPU_POWERPC_7x0_v21 = 0x00080201,
4644 CPU_POWERPC_7x0_v22 = 0x00080202,
4645 CPU_POWERPC_7x0_v30 = 0x00080300,
4646 CPU_POWERPC_7x0_v31 = 0x00080301,
4647 CPU_POWERPC_740E = 0x00080100,
4648 CPU_POWERPC_7x0P = 0x10080000,
4649 /* XXX: missing 0x00087010 (CL ?) */
4650 CPU_POWERPC_750CL = 0x00087200,
4651#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4652 CPU_POWERPC_750CX_v21 = 0x00082201,
4653 CPU_POWERPC_750CX_v22 = 0x00082202,
4654#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4655 CPU_POWERPC_750CXE_v21 = 0x00082211,
4656 CPU_POWERPC_750CXE_v22 = 0x00082212,
4657 CPU_POWERPC_750CXE_v23 = 0x00082213,
4658 CPU_POWERPC_750CXE_v24 = 0x00082214,
4659 CPU_POWERPC_750CXE_v24b = 0x00083214,
4660 CPU_POWERPC_750CXE_v31 = 0x00083211,
4661 CPU_POWERPC_750CXE_v31b = 0x00083311,
4662 CPU_POWERPC_750CXR = 0x00083410,
4663 CPU_POWERPC_750E = 0x00080200,
4664 CPU_POWERPC_750FL = 0x700A0203,
4665#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4666 CPU_POWERPC_750FX_v10 = 0x70000100,
4667 CPU_POWERPC_750FX_v20 = 0x70000200,
4668 CPU_POWERPC_750FX_v21 = 0x70000201,
4669 CPU_POWERPC_750FX_v22 = 0x70000202,
4670 CPU_POWERPC_750FX_v23 = 0x70000203,
4671 CPU_POWERPC_750GL = 0x70020102,
4672#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4673 CPU_POWERPC_750GX_v10 = 0x70020100,
4674 CPU_POWERPC_750GX_v11 = 0x70020101,
4675 CPU_POWERPC_750GX_v12 = 0x70020102,
4676#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4677 CPU_POWERPC_750L_v22 = 0x00088202,
4678 CPU_POWERPC_750L_v30 = 0x00088300,
4679 CPU_POWERPC_750L_v32 = 0x00088302,
4680 /* PowerPC 745/755 cores */
4681#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4682 CPU_POWERPC_7x5_v10 = 0x00083100,
4683 CPU_POWERPC_7x5_v11 = 0x00083101,
4684 CPU_POWERPC_7x5_v20 = 0x00083200,
4685 CPU_POWERPC_7x5_v21 = 0x00083201,
4686 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
4687 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
4688 CPU_POWERPC_7x5_v24 = 0x00083204,
4689 CPU_POWERPC_7x5_v25 = 0x00083205,
4690 CPU_POWERPC_7x5_v26 = 0x00083206,
4691 CPU_POWERPC_7x5_v27 = 0x00083207,
4692 CPU_POWERPC_7x5_v28 = 0x00083208,
4693#if 0
4694 CPU_POWERPC_7x5P = xxx,
4695#endif
4696 /* PowerPC 74xx cores (aka G4) */
4697 /* XXX: missing 0x000C1101 */
4698#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4699 CPU_POWERPC_7400_v10 = 0x000C0100,
4700 CPU_POWERPC_7400_v11 = 0x000C0101,
4701 CPU_POWERPC_7400_v20 = 0x000C0200,
4702 CPU_POWERPC_7400_v22 = 0x000C0202,
4703 CPU_POWERPC_7400_v26 = 0x000C0206,
4704 CPU_POWERPC_7400_v27 = 0x000C0207,
4705 CPU_POWERPC_7400_v28 = 0x000C0208,
4706 CPU_POWERPC_7400_v29 = 0x000C0209,
4707#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4708 CPU_POWERPC_7410_v10 = 0x800C1100,
4709 CPU_POWERPC_7410_v11 = 0x800C1101,
4710 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
4711 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
4712 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
4713#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4714 CPU_POWERPC_7448_v10 = 0x80040100,
4715 CPU_POWERPC_7448_v11 = 0x80040101,
4716 CPU_POWERPC_7448_v20 = 0x80040200,
4717 CPU_POWERPC_7448_v21 = 0x80040201,
4718#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4719 CPU_POWERPC_7450_v10 = 0x80000100,
4720 CPU_POWERPC_7450_v11 = 0x80000101,
4721 CPU_POWERPC_7450_v12 = 0x80000102,
4722 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
4723 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4724 CPU_POWERPC_74x1 = 0x80000203,
4725 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
4726 /* XXX: missing 0x80010200 */
4727#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4728 CPU_POWERPC_74x5_v10 = 0x80010100,
4729 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
4730 CPU_POWERPC_74x5_v32 = 0x80010302,
4731 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
4732 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
4733#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4734 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
4735 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
4736 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
4737 /* 64 bits PowerPC */
00af685f 4738#if defined(TARGET_PPC64)
a750fc0b
JM		 4739 CPU_POWERPC_620 = 0x00140000,
4740 CPU_POWERPC_630 = 0x00400000,
4741 CPU_POWERPC_631 = 0x00410104,
4742 CPU_POWERPC_POWER4 = 0x00350000,
4743 CPU_POWERPC_POWER4P = 0x00380000,
4744 CPU_POWERPC_POWER5 = 0x003A0203,
4745#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4746 CPU_POWERPC_POWER5P = 0x003B0000,
4747#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4748 CPU_POWERPC_POWER6 = 0x003E0000,
4749 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
4750 CPU_POWERPC_POWER6A = 0x0F000002,
4751 CPU_POWERPC_970 = 0x00390202,
4752#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4753 CPU_POWERPC_970FX_v10 = 0x00391100,
4754 CPU_POWERPC_970FX_v20 = 0x003C0200,
4755 CPU_POWERPC_970FX_v21 = 0x003C0201,
4756 CPU_POWERPC_970FX_v30 = 0x003C0300,
4757 CPU_POWERPC_970FX_v31 = 0x003C0301,
4758 CPU_POWERPC_970GX = 0x00450000,
4759#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4760 CPU_POWERPC_970MP_v10 = 0x00440100,
4761 CPU_POWERPC_970MP_v11 = 0x00440101,
4762#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4763 CPU_POWERPC_CELL_v10 = 0x00700100,
4764 CPU_POWERPC_CELL_v20 = 0x00700400,
4765 CPU_POWERPC_CELL_v30 = 0x00700500,
4766 CPU_POWERPC_CELL_v31 = 0x00700501,
4767#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4768 CPU_POWERPC_RS64 = 0x00330000,
4769 CPU_POWERPC_RS64II = 0x00340000,
4770 CPU_POWERPC_RS64III = 0x00360000,
4771 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 4772#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 4773 /* Original POWER */
4774 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4775 * POWER2 (RIOS2) & RSC2 (P2SC) here
4776 */
4777#if 0
4778 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4779#endif
4780#if 0
4781 CPU_POWER2 = xxx, /* 0x40000 ? */
4782#endif
4783 /* PA Semi core */
4784 CPU_POWERPC_PA6T = 0x00900000,
4785};
4786
4787/* System version register (used on MPC 8xxx) */
4788enum {
4789 PPC_SVR_8540 = 0x80300000,
4790 PPC_SVR_8541E = 0x807A0010,
4791 PPC_SVR_8543v10 = 0x80320010,
4792 PPC_SVR_8543v11 = 0x80320011,
4793 PPC_SVR_8543v20 = 0x80320020,
4794 PPC_SVR_8543Ev10 = 0x803A0010,
4795 PPC_SVR_8543Ev11 = 0x803A0011,
4796 PPC_SVR_8543Ev20 = 0x803A0020,
4797 PPC_SVR_8545 = 0x80310220,
4798 PPC_SVR_8545E = 0x80390220,
4799 PPC_SVR_8547E = 0x80390120,
4800 PPC_SCR_8548v10 = 0x80310010,
4801 PPC_SCR_8548v11 = 0x80310011,
4802 PPC_SCR_8548v20 = 0x80310020,
4803 PPC_SVR_8548Ev10 = 0x80390010,
4804 PPC_SVR_8548Ev11 = 0x80390011,
4805 PPC_SVR_8548Ev20 = 0x80390020,
4806 PPC_SVR_8555E = 0x80790010,
4807 PPC_SVR_8560v10 = 0x80700010,
4808 PPC_SVR_8560v20 = 0x80700020,
4809};
4810
3fc6c082 4811/*****************************************************************************/
a750fc0b
JM		 4812/* PowerPC CPU definitions */
4813#define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4814 { \
4815 .name = _name, \
4816 .pvr = _pvr, \
4817 .pvr_mask = _pvr_mask, \
4818 .insns_flags = glue(POWERPC_INSNS_,_type), \
4819 .msr_mask = glue(POWERPC_MSRM_,_type), \
4820 .mmu_model = glue(POWERPC_MMU_,_type), \
4821 .excp_model = glue(POWERPC_EXCP_,_type), \
4822 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 4823 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 4824 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b
JM		 4825 .init_proc = &glue(init_proc_,_type), \
4826 }
4827
3a607854 4828static ppc_def_t ppc_defs[] = {
a750fc0b
JM		 4829 /* Embedded PowerPC */
4830 /* PowerPC 401 family */
2662a059 4831 /* Generic PowerPC 401 */
a750fc0b
JM		 4832 POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
4833 /* PowerPC 401 cores */
2662a059 4834 /* PowerPC 401A1 */
a750fc0b
JM		 4835 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
4836 /* PowerPC 401B2 */
4837 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
2662a059 4838#if defined (TODO)
a750fc0b
JM		 4839 /* PowerPC 401B3 */
4840 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
4841#endif
4842 /* PowerPC 401C2 */
4843 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
4844 /* PowerPC 401D2 */
4845 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
4846 /* PowerPC 401E2 */
4847 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
4848 /* PowerPC 401F2 */
4849 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
4850 /* PowerPC 401G2 */
4851 /* XXX: to be checked */
4852 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
4853 /* PowerPC 401 microcontrolers */
2662a059 4854#if defined (TODO)
a750fc0b
JM		 4855 /* PowerPC 401GF */
4856 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
3fc6c082 4857#endif
a750fc0b
JM		 4858 /* IOP480 (401 microcontroler) */
4859 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
4860 /* IBM Processor for Network Resources */
4861 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
3fc6c082 4862#if defined (TODO)
a750fc0b 4863 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
3fc6c082 4864#endif
a750fc0b
JM		 4865 /* PowerPC 403 family */
4866 /* Generic PowerPC 403 */
4867 POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
4868 /* PowerPC 403 microcontrolers */
4869 /* PowerPC 403 GA */
4870 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
4871 /* PowerPC 403 GB */
4872 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
4873 /* PowerPC 403 GC */
4874 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
4875 /* PowerPC 403 GCX */
4876 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
3fc6c082 4877#if defined (TODO)
a750fc0b
JM		 4878 /* PowerPC 403 GP */
4879 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
3fc6c082 4880#endif
a750fc0b
JM		 4881 /* PowerPC 405 family */
4882 /* Generic PowerPC 405 */
4883 POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
4884 /* PowerPC 405 cores */
2662a059 4885#if defined (TODO)
a750fc0b
JM		 4886 /* PowerPC 405 A3 */
4887 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
3a607854 4888#endif
3a607854 4889#if defined (TODO)
a750fc0b
JM		 4890 /* PowerPC 405 A4 */
4891 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
3a607854 4892#endif
3a607854 4893#if defined (TODO)
a750fc0b
JM		 4894 /* PowerPC 405 B3 */
4895 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
3fc6c082
FB		 4896#endif
4897#if defined (TODO)
a750fc0b
JM		 4898 /* PowerPC 405 B4 */
4899 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
4900#endif
4901#if defined (TODO)
4902 /* PowerPC 405 C3 */
4903 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
4904#endif
4905#if defined (TODO)
4906 /* PowerPC 405 C4 */
4907 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
4908#endif
4909 /* PowerPC 405 D2 */
4910 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
4911#if defined (TODO)
4912 /* PowerPC 405 D3 */
4913 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
4914#endif
4915 /* PowerPC 405 D4 */
4916 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
4917#if defined (TODO)
4918 /* PowerPC 405 D5 */
4919 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
4920#endif
4921#if defined (TODO)
4922 /* PowerPC 405 E4 */
4923 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
4924#endif
4925#if defined (TODO)
4926 /* PowerPC 405 F4 */
4927 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
4928#endif
4929#if defined (TODO)
4930 /* PowerPC 405 F5 */
4931 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
4932#endif
4933#if defined (TODO)
4934 /* PowerPC 405 F6 */
4935 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
4936#endif
4937 /* PowerPC 405 microcontrolers */
4938 /* PowerPC 405 CR */
4939 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
4940 /* PowerPC 405 CRa */
4941 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
4942 /* PowerPC 405 CRb */
4943 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
4944 /* PowerPC 405 CRc */
4945 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
4946 /* PowerPC 405 EP */
4947 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
4948#if defined(TODO)
4949 /* PowerPC 405 EXr */
4950 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
4951#endif
4952 /* PowerPC 405 EZ */
4953 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
4954#if defined(TODO)
4955 /* PowerPC 405 FX */
4956 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
4957#endif
4958 /* PowerPC 405 GP */
4959 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
4960 /* PowerPC 405 GPa */
4961 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
4962 /* PowerPC 405 GPb */
4963 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
4964 /* PowerPC 405 GPc */
4965 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
4966 /* PowerPC 405 GPd */
4967 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
4968 /* PowerPC 405 GPe */
4969 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
4970 /* PowerPC 405 GPR */
4971 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
4972#if defined(TODO)
4973 /* PowerPC 405 H */
4974 POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
4975#endif
4976#if defined(TODO)
4977 /* PowerPC 405 L */
4978 POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
4979#endif
4980 /* PowerPC 405 LP */
4981 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
4982#if defined(TODO)
4983 /* PowerPC 405 PM */
4984 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
4985#endif
4986#if defined(TODO)
4987 /* PowerPC 405 PS */
4988 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
4989#endif
4990#if defined(TODO)
4991 /* PowerPC 405 S */
4992 POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
4993#endif
4994 /* Npe405 H */
4995 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
4996 /* Npe405 H2 */
4997 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
4998 /* Npe405 L */
4999 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
5000 /* Npe4GS3 */
5001 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
5002#if defined (TODO)
5003 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
5004#endif
5005#if defined (TODO)
5006 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
5007#endif
5008#if defined (TODO)
5009 /* PowerPC LC77700 (Sanyo) */
5010 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
5011#endif
5012 /* PowerPC 401/403/405 based set-top-box microcontrolers */
5013#if defined (TODO)
5014 /* STB010000 */
5015 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
5016#endif
5017#if defined (TODO)
5018 /* STB01010 */
5019 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
5020#endif
5021#if defined (TODO)
5022 /* STB0210 */
5023 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
5024#endif
5025 /* STB03xx */
5026 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
5027#if defined (TODO)
5028 /* STB043x */
5029 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
5030#endif
5031#if defined (TODO)
5032 /* STB045x */
5033 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
5034#endif
5035 /* STB04xx */
5036 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
5037 /* STB25xx */
5038 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
5039#if defined (TODO)
5040 /* STB130 */
5041 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
5042#endif
5043 /* Xilinx PowerPC 405 cores */
5044 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
5045 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
5046 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
5047 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
5048#if defined (TODO)
5049 /* Zarlink ZL10310 */
5050 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
5051#endif
5052#if defined (TODO)
5053 /* Zarlink ZL10311 */
5054 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
5055#endif
5056#if defined (TODO)
5057 /* Zarlink ZL10320 */
5058 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
5059#endif
5060#if defined (TODO)
5061 /* Zarlink ZL10321 */
5062 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
5063#endif
5064 /* PowerPC 440 family */
5065 /* Generic PowerPC 440 */
5066 POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
5067 /* PowerPC 440 cores */
5068#if defined (TODO)
5069 /* PowerPC 440 A4 */
5070 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
5071#endif
5072#if defined (TODO)
5073 /* PowerPC 440 A5 */
5074 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
5075#endif
5076#if defined (TODO)
5077 /* PowerPC 440 B4 */
5078 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
5079#endif
5080#if defined (TODO)
5081 /* PowerPC 440 G4 */
5082 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
5083#endif
5084#if defined (TODO)
5085 /* PowerPC 440 F5 */
5086 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
5087#endif
5088#if defined (TODO)
5089 /* PowerPC 440 G5 */
5090 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
5091#endif
5092#if defined (TODO)
5093 /* PowerPC 440H4 */
5094 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
5095#endif
5096#if defined (TODO)
5097 /* PowerPC 440H6 */
5098 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
5099#endif
5100 /* PowerPC 440 microcontrolers */
5101 /* PowerPC 440 EP */
5102 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
5103 /* PowerPC 440 EPa */
5104 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
5105 /* PowerPC 440 EPb */
5106 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
5107 /* PowerPC 440 EPX */
5108 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
5109 /* PowerPC 440 GP */
5110 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
5111 /* PowerPC 440 GPb */
5112 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
5113 /* PowerPC 440 GPc */
5114 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
5115 /* PowerPC 440 GR */
5116 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
5117 /* PowerPC 440 GRa */
5118 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
5119 /* PowerPC 440 GRX */
5120 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
5121 /* PowerPC 440 GX */
5122 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
5123 /* PowerPC 440 GXa */
5124 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
5125 /* PowerPC 440 GXb */
5126 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
5127 /* PowerPC 440 GXc */
5128 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
5129 /* PowerPC 440 GXf */
5130 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
5131#if defined(TODO)
5132 /* PowerPC 440 S */
5133 POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
5134#endif
5135 /* PowerPC 440 SP */
5136 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
5137 /* PowerPC 440 SP2 */
5138 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
5139 /* PowerPC 440 SPE */
5140 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
5141 /* PowerPC 460 family */
5142#if defined (TODO)
5143 /* Generic PowerPC 464 */
5144 POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
5145#endif
5146 /* PowerPC 464 microcontrolers */
5147#if defined (TODO)
5148 /* PowerPC 464H90 */
5149 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
5150#endif
5151#if defined (TODO)
5152 /* PowerPC 464H90F */
5153 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
5154#endif
5155 /* Freescale embedded PowerPC cores */
5156 /* e200 family */
5157#if defined (TODO)
5158 /* Generic PowerPC e200 core */
5159 POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
5160#endif
5161#if defined (TODO)
5162 /* PowerPC e200z5 core */
5163 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
5164#endif
5165#if defined (TODO)
5166 /* PowerPC e200z6 core */
5167 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
5168#endif
5169 /* e300 family */
5170#if defined (TODO)
5171 /* Generic PowerPC e300 core */
5172 POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
5173#endif
5174#if defined (TODO)
5175 /* PowerPC e300c1 core */
5176 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
5177#endif
5178#if defined (TODO)
5179 /* PowerPC e300c2 core */
5180 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
5181#endif
5182#if defined (TODO)
5183 /* PowerPC e300c3 core */
5184 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
5185#endif
5186 /* e500 family */
5187#if defined (TODO)
5188 /* PowerPC e500 core */
5189 POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
5190#endif
5191#if defined (TODO)
5192 /* PowerPC e500 v1.1 core */
5193 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
5194#endif
5195#if defined (TODO)
5196 /* PowerPC e500 v1.2 core */
5197 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
5198#endif
5199#if defined (TODO)
5200 /* PowerPC e500 v2.1 core */
5201 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
5202#endif
5203#if defined (TODO)
5204 /* PowerPC e500 v2.2 core */
5205 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
5206#endif
5207 /* e600 family */
5208#if defined (TODO)
5209 /* PowerPC e600 core */
5210 POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
5211#endif
5212 /* PowerPC MPC 5xx cores */
5213#if defined (TODO)
5214 /* PowerPC MPC 5xx */
5215 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
5216#endif
5217 /* PowerPC MPC 8xx cores */
5218#if defined (TODO)
5219 /* PowerPC MPC 8xx */
5220 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
5221#endif
5222 /* PowerPC MPC 8xxx cores */
5223#if defined (TODO)
5224 /* PowerPC MPC 82xx HIP3 */
5225 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
5226#endif
5227#if defined (TODO)
5228 /* PowerPC MPC 82xx HIP4 */
5229 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
5230#endif
5231#if defined (TODO)
5232 /* PowerPC MPC 827x */
5233 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
5234#endif
5235
5236 /* 32 bits "classic" PowerPC */
5237 /* PowerPC 6xx family */
5238 /* PowerPC 601 */
5239 POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
5240 /* PowerPC 601v2 */
5241 POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
5242 /* PowerPC 602 */
5243 POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
5244 /* PowerPC 603 */
5245 POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5246 /* Code name for PowerPC 603 */
5247 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5248 /* PowerPC 603e */
5249 POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5250 /* Code name for PowerPC 603e */
5251 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5252 /* PowerPC 603e v1.1 */
5253 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
5254 /* PowerPC 603e v1.2 */
5255 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
5256 /* PowerPC 603e v1.3 */
5257 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
5258 /* PowerPC 603e v1.4 */
5259 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
5260 /* PowerPC 603e v2.2 */
5261 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
5262 /* PowerPC 603e v3 */
5263 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
5264 /* PowerPC 603e v4 */
5265 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
5266 /* PowerPC 603e v4.1 */
5267 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
5268 /* PowerPC 603e */
5269 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
5270 /* PowerPC 603e7t */
5271 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
5272 /* PowerPC 603e7v */
5273 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5274 /* Code name for PowerPC 603ev */
5275 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5276 /* PowerPC 603e7v1 */
5277 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
5278 /* PowerPC 603e7v2 */
5279 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
5280 /* PowerPC 603p */
5281 /* to be checked */
5282 POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
5283 /* PowerPC 603r */
5284 POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5285 /* Code name for PowerPC 603r */
5286 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5287 /* PowerPC G2 core */
5288 POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
5289 /* PowerPC G2 H4 */
5290 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
5291 /* PowerPC G2 GP */
5292 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
5293 /* PowerPC G2 LS */
5294 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
5295 /* PowerPC G2LE */
5296 /* Same as G2, with little-endian mode support */
5297 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
5298 /* PowerPC G2LE GP */
5299 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
5300 /* PowerPC G2LE LS */
5301 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
5302 /* PowerPC 604 */
5303 POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
5304 /* PowerPC 604e */
5305 POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
5306 /* PowerPC 604e v1.0 */
5307 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
5308 /* PowerPC 604e v2.2 */
5309 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
5310 /* PowerPC 604e v2.4 */
5311 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
5312 /* PowerPC 604r */
5313 POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
5314#if defined(TODO)
5315 /* PowerPC 604ev */
5316 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
5317#endif
5318 /* PowerPC 7xx family */
5319 /* Generic PowerPC 740 (G3) */
5320 POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5321 /* Generic PowerPC 750 (G3) */
5322 POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5323 /* Code name for generic PowerPC 740/750 (G3) */
5324 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5325 /* PowerPC 740/750 is also known as G3 */
5326 POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5327 /* PowerPC 740 v2.0 (G3) */
5328 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5329 /* PowerPC 750 v2.0 (G3) */
5330 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5331 /* PowerPC 740 v2.1 (G3) */
5332 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5333 /* PowerPC 750 v2.1 (G3) */
5334 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5335 /* PowerPC 740 v2.2 (G3) */
5336 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5337 /* PowerPC 750 v2.2 (G3) */
5338 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5339 /* PowerPC 740 v3.0 (G3) */
5340 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5341 /* PowerPC 750 v3.0 (G3) */
5342 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5343 /* PowerPC 740 v3.1 (G3) */
5344 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5345 /* PowerPC 750 v3.1 (G3) */
5346 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5347 /* PowerPC 740E (G3) */
5348 POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
5349 /* PowerPC 740P (G3) */
5350 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5351 /* PowerPC 750P (G3) */
5352 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5353 /* Code name for PowerPC 740P/750P (G3) */
5354 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5355 /* PowerPC 750CL (G3 embedded) */
5356 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
5357 /* PowerPC 750CX (G3 embedded) */
5358 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
5359 /* PowerPC 750CX v2.1 (G3 embedded) */
5360 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
5361 /* PowerPC 750CX v2.2 (G3 embedded) */
5362 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
5363 /* PowerPC 750CXe (G3 embedded) */
5364 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
5365 /* PowerPC 750CXe v2.1 (G3 embedded) */
5366 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
5367 /* PowerPC 750CXe v2.2 (G3 embedded) */
5368 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
5369 /* PowerPC 750CXe v2.3 (G3 embedded) */
5370 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
5371 /* PowerPC 750CXe v2.4 (G3 embedded) */
5372 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
5373 /* PowerPC 750CXe v2.4b (G3 embedded) */
5374 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
5375 /* PowerPC 750CXe v3.1 (G3 embedded) */
5376 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
5377 /* PowerPC 750CXe v3.1b (G3 embedded) */
5378 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
5379 /* PowerPC 750CXr (G3 embedded) */
5380 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
5381 /* PowerPC 750E (G3) */
5382 POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
5383 /* PowerPC 750FL (G3 embedded) */
d12f4c38 5384 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 750fx),
a750fc0b
JM		 5385 /* PowerPC 750FX (G3 embedded) */
5386 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
5387 /* PowerPC 750FX v1.0 (G3 embedded) */
5388 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
5389 /* PowerPC 750FX v2.0 (G3 embedded) */
5390 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
5391 /* PowerPC 750FX v2.1 (G3 embedded) */
5392 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
5393 /* PowerPC 750FX v2.2 (G3 embedded) */
5394 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
5395 /* PowerPC 750FX v2.3 (G3 embedded) */
5396 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
5397 /* PowerPC 750GL (G3 embedded) */
d12f4c38 5398 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 750fx),
a750fc0b
JM		 5399 /* PowerPC 750GX (G3 embedded) */
5400 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
5401 /* PowerPC 750GX v1.0 (G3 embedded) */
5402 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
5403 /* PowerPC 750GX v1.1 (G3 embedded) */
5404 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
5405 /* PowerPC 750GX v1.2 (G3 embedded) */
5406 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
5407 /* PowerPC 750L (G3 embedded) */
5408 POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5409 /* Code name for PowerPC 750L (G3 embedded) */
5410 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5411 /* PowerPC 750L v2.2 (G3 embedded) */
5412 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
5413 /* PowerPC 750L v3.0 (G3 embedded) */
5414 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
5415 /* PowerPC 750L v3.2 (G3 embedded) */
5416 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
5417 /* Generic PowerPC 745 */
5418 POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5419 /* Generic PowerPC 755 */
5420 POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5421 /* Code name for PowerPC 745/755 */
5422 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5423 /* PowerPC 745 v1.0 */
5424 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5425 /* PowerPC 755 v1.0 */
5426 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5427 /* PowerPC 745 v1.1 */
5428 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5429 /* PowerPC 755 v1.1 */
5430 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5431 /* PowerPC 745 v2.0 */
5432 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5433 /* PowerPC 755 v2.0 */
5434 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5435 /* PowerPC 745 v2.1 */
5436 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5437 /* PowerPC 755 v2.1 */
5438 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5439 /* PowerPC 745 v2.2 */
5440 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5441 /* PowerPC 755 v2.2 */
5442 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5443 /* PowerPC 745 v2.3 */
5444 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5445 /* PowerPC 755 v2.3 */
5446 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5447 /* PowerPC 745 v2.4 */
5448 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5449 /* PowerPC 755 v2.4 */
5450 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5451 /* PowerPC 745 v2.5 */
5452 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5453 /* PowerPC 755 v2.5 */
5454 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5455 /* PowerPC 745 v2.6 */
5456 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5457 /* PowerPC 755 v2.6 */
5458 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5459 /* PowerPC 745 v2.7 */
5460 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5461 /* PowerPC 755 v2.7 */
5462 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5463 /* PowerPC 745 v2.8 */
5464 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5465 /* PowerPC 755 v2.8 */
5466 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5467#if defined (TODO)
5468 /* PowerPC 745P (G3) */
5469 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5470 /* PowerPC 755P (G3) */
5471 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5472#endif
5473 /* PowerPC 74xx family */
5474 /* PowerPC 7400 (G4) */
5475 POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5476 /* Code name for PowerPC 7400 */
5477 POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5478 /* PowerPC 74xx is also well known as G4 */
5479 POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5480 /* PowerPC 7400 v1.0 (G4) */
5481 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
5482 /* PowerPC 7400 v1.1 (G4) */
5483 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
5484 /* PowerPC 7400 v2.0 (G4) */
5485 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
5486 /* PowerPC 7400 v2.2 (G4) */
5487 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
5488 /* PowerPC 7400 v2.6 (G4) */
5489 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
5490 /* PowerPC 7400 v2.7 (G4) */
5491 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
5492 /* PowerPC 7400 v2.8 (G4) */
5493 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
5494 /* PowerPC 7400 v2.9 (G4) */
5495 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
5496 /* PowerPC 7410 (G4) */
5497 POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5498 /* Code name for PowerPC 7410 */
5499 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5500 /* PowerPC 7410 v1.0 (G4) */
5501 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
5502 /* PowerPC 7410 v1.1 (G4) */
5503 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
5504 /* PowerPC 7410 v1.2 (G4) */
5505 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
5506 /* PowerPC 7410 v1.3 (G4) */
5507 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
5508 /* PowerPC 7410 v1.4 (G4) */
5509 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
5510 /* PowerPC 7448 (G4) */
5511 POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
5512 /* PowerPC 7448 v1.0 (G4) */
5513 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
5514 /* PowerPC 7448 v1.1 (G4) */
5515 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
5516 /* PowerPC 7448 v2.0 (G4) */
5517 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
5518 /* PowerPC 7448 v2.1 (G4) */
5519 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
5520#if defined (TODO)
5521 /* PowerPC 7450 (G4) */
5522 POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5523 /* Code name for PowerPC 7450 */
5524 POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5525#endif
5526#if defined (TODO)
5527 /* PowerPC 7450 v1.0 (G4) */
5528 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
5529#endif
5530#if defined (TODO)
5531 /* PowerPC 7450 v1.1 (G4) */
5532 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
5533#endif
5534#if defined (TODO)
5535 /* PowerPC 7450 v1.2 (G4) */
5536 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
5537#endif
5538#if defined (TODO)
5539 /* PowerPC 7450 v2.0 (G4) */
5540 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
5541#endif
5542#if defined (TODO)
5543 /* PowerPC 7450 v2.1 (G4) */
5544 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
5545#endif
5546#if defined (TODO)
5547 /* PowerPC 7441 (G4) */
5548 POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
5549 /* PowerPC 7451 (G4) */
5550 POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
5551#endif
3fc6c082 5552#if defined (TODO)
a750fc0b
JM		 5553 /* PowerPC 7441g (G4) */
5554 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
5555 /* PowerPC 7451g (G4) */
5556 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
2662a059
JM		 5557#endif
5558#if defined (TODO)
a750fc0b
JM		 5559 /* PowerPC 7445 (G4) */
5560 POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
5561 /* PowerPC 7455 (G4) */
5562 POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5563 /* Code name for PowerPC 7445/7455 */
5564 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
2662a059
JM		 5565#endif
5566#if defined (TODO)
a750fc0b
JM		 5567 /* PowerPC 7445 v1.0 (G4) */
5568 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
5569 /* PowerPC 7455 v1.0 (G4) */
5570 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
5571#endif
2662a059 5572#if defined (TODO)
a750fc0b
JM		 5573 /* PowerPC 7445 v2.1 (G4) */
5574 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
5575 /* PowerPC 7455 v2.1 (G4) */
5576 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
2662a059
JM		 5577#endif
5578#if defined (TODO)
a750fc0b
JM		 5579 /* PowerPC 7445 v3.2 (G4) */
5580 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
5581 /* PowerPC 7455 v3.2 (G4) */
5582 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
2662a059
JM		 5583#endif
5584#if defined (TODO)
a750fc0b
JM		 5585 /* PowerPC 7445 v3.3 (G4) */
5586 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
5587 /* PowerPC 7455 v3.3 (G4) */
5588 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
3fc6c082
FB		 5589#endif
5590#if defined (TODO)
a750fc0b
JM		 5591 /* PowerPC 7445 v3.4 (G4) */
5592 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
5593 /* PowerPC 7455 v3.4 (G4) */
5594 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
3a607854 5595#endif
04f20795 5596#if defined (TODO)
a750fc0b
JM		 5597 /* PowerPC 7447 (G4) */
5598 POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
5599 /* PowerPC 7457 (G4) */
5600 POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5601 /* Code name for PowerPC 7447/7457 */
5602 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
3fc6c082
FB		 5603#endif
5604#if defined (TODO)
a750fc0b
JM		 5605 /* PowerPC 7447 v1.0 (G4) */
5606 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
5607 /* PowerPC 7457 v1.0 (G4) */
5608 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5609 /* Code name for PowerPC 7447A/7457A */
5610 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
3a607854
JM		 5611#endif
5612#if defined (TODO)
a750fc0b
JM		 5613 /* PowerPC 7447 v1.1 (G4) */
5614 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
5615 /* PowerPC 7457 v1.1 (G4) */
5616 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
3a607854
JM		 5617#endif
5618#if defined (TODO)
a750fc0b
JM		 5619 /* PowerPC 7447 v1.2 (G4) */
5620 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
5621 /* PowerPC 7457 v1.2 (G4) */
5622 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
5623#endif
5624 /* 64 bits PowerPC */
5625#if defined (TARGET_PPC64)
3fc6c082 5626#if defined (TODO)
a750fc0b
JM		 5627 /* PowerPC 620 */
5628 POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
5629#endif
3fc6c082 5630#if defined (TODO)
a750fc0b
JM		 5631 /* PowerPC 630 (POWER3) */
5632 POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5633 POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5634#endif
3a607854 5635#if defined (TODO)
a750fc0b
JM		 5636 /* PowerPC 631 (Power 3+) */
5637 POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5638 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
3a607854
JM		 5639#endif
5640#if defined (TODO)
a750fc0b
JM		 5641 /* POWER4 */
5642 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
5643#endif
3a607854 5644#if defined (TODO)
a750fc0b
JM		 5645 /* POWER4p */
5646 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
5647#endif
2662a059 5648#if defined (TODO)
a750fc0b
JM		 5649 /* POWER5 */
5650 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
5651 /* POWER5GR */
5652 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
2662a059 5653#endif
3a607854 5654#if defined (TODO)
a750fc0b
JM		 5655 /* POWER5+ */
5656 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
5657 /* POWER5GS */
5658 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
5659#endif
2662a059 5660#if defined (TODO)
a750fc0b
JM		 5661 /* POWER6 */
5662 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
5663 /* POWER6 running in POWER5 mode */
5664 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
5665 /* POWER6A */
5666 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
2662a059 5667#endif
a750fc0b
JM		 5668 /* PowerPC 970 */
5669 POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
a750fc0b
JM		 5670 /* PowerPC 970FX (G5) */
5671 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5672 /* PowerPC 970FX v1.0 (G5) */
5673 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5674 /* PowerPC 970FX v2.0 (G5) */
5675 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5676 /* PowerPC 970FX v2.1 (G5) */
5677 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5678 /* PowerPC 970FX v3.0 (G5) */
5679 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5680 /* PowerPC 970FX v3.1 (G5) */
5681 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5682 /* PowerPC 970GX (G5) */
5683 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
a750fc0b
JM		 5684 /* PowerPC 970MP */
5685 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970),
a750fc0b
JM		 5686 /* PowerPC 970MP v1.0 */
5687 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970),
a750fc0b
JM		 5688 /* PowerPC 970MP v1.1 */
5689 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970),
3a607854 5690#if defined (TODO)
a750fc0b
JM		 5691 /* PowerPC Cell */
5692 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
2662a059
JM		 5693#endif
5694#if defined (TODO)
a750fc0b
JM		 5695 /* PowerPC Cell v1.0 */
5696 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
2662a059
JM		 5697#endif
5698#if defined (TODO)
a750fc0b
JM		 5699 /* PowerPC Cell v2.0 */
5700 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
2662a059
JM		 5701#endif
5702#if defined (TODO)
a750fc0b
JM		 5703 /* PowerPC Cell v3.0 */
5704 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
3a607854 5705#endif
3a607854 5706#if defined (TODO)
a750fc0b
JM		 5707 /* PowerPC Cell v3.1 */
5708 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
2662a059
JM		 5709#endif
5710#if defined (TODO)
a750fc0b
JM		 5711 /* PowerPC Cell v3.2 */
5712 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
2662a059
JM		 5713#endif
5714#if defined (TODO)
a750fc0b
JM		 5715 /* RS64 (Apache/A35) */
5716 /* This one seems to support the whole POWER2 instruction set
5717 * and the PowerPC 64 one.
5718 */
5719 /* What about A10 & A30 ? */
5720 POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5721 POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5722 POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
3a607854
JM		 5723#endif
5724#if defined (TODO)
a750fc0b
JM		 5725 /* RS64-II (NorthStar/A50) */
5726 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5727 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5728 POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
3a607854
JM		 5729#endif
5730#if defined (TODO)
a750fc0b
JM		 5731 /* RS64-III (Pulsar) */
5732 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5733 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
2662a059
JM		 5734#endif
5735#if defined (TODO)
a750fc0b
JM		 5736 /* RS64-IV (IceStar/IStar/SStar) */
5737 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5738 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5739 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5740 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
3a607854 5741#endif
a750fc0b
JM		 5742#endif /* defined (TARGET_PPC64) */
5743 /* POWER */
3fc6c082 5744#if defined (TODO)
a750fc0b
JM		 5745 /* Original POWER */
5746 POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5747 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5748 POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5749 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5750 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
76a66253
JM		 5751#endif
5752#if defined (TODO)
a750fc0b
JM		 5753 /* POWER2 */
5754 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5755 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5756 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5757#endif
5758 /* PA semi cores */
5759#if defined (TODO)
5760 /* PA PA6T */
5761 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
5762#endif
5763 /* Generic PowerPCs */
5764#if defined (TARGET_PPC64)
5765#if defined (TODO)
5766 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
5767#endif
5768#endif
5769 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
d12f4c38 5770 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
a750fc0b 5771 /* Fallback */
d12f4c38 5772 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
a750fc0b
JM		 5773};
5774
5775/*****************************************************************************/
5776/* Generic CPU instanciation routine */
5777static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5778{
5779#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 5780 int i;
5781
a750fc0b 5782 env->irq_inputs = NULL;
e1833e1f
JM		 5783 /* Set all exception vectors to an invalid address */
5784 for (i = 0; i < POWERPC_EXCP_NB; i++)
5785 env->excp_vectors[i] = (target_ulong)(-1ULL);
5786 env->excp_prefix = 0x00000000;
5787 env->ivor_mask = 0x00000000;
5788 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 5789 /* Default MMU definitions */
5790 env->nb_BATs = 0;
5791 env->nb_tlb = 0;
5792 env->nb_ways = 0;
f2e63a42 5793#endif
a750fc0b
JM		 5794 /* Register SPR common to all PowerPC implementations */
5795 gen_spr_generic(env);
5796 spr_register(env, SPR_PVR, "PVR",
5797 SPR_NOACCESS, SPR_NOACCESS,
5798 &spr_read_generic, SPR_NOACCESS,
5799 def->pvr);
5800 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5801 (*def->init_proc)(env);
5802 /* Allocate TLBs buffer when needed */
f2e63a42 5803#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 5804 if (env->nb_tlb != 0) {
5805 int nb_tlb = env->nb_tlb;
5806 if (env->id_tlbs != 0)
5807 nb_tlb *= 2;
5808 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
5809 /* Pre-compute some useful values */
5810 env->tlb_per_way = env->nb_tlb / env->nb_ways;
5811 }
a750fc0b
JM		 5812 if (env->irq_inputs == NULL) {
5813 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5814 " Attempt Qemu to crash very soon !\n");
5815 }
5816#endif
5817}
5818
5819#if defined(PPC_DUMP_CPU)
5820static void dump_ppc_sprs (CPUPPCState *env)
5821{
5822 ppc_spr_t *spr;
5823#if !defined(CONFIG_USER_ONLY)
5824 uint32_t sr, sw;
5825#endif
5826 uint32_t ur, uw;
5827 int i, j, n;
5828
5829 printf("Special purpose registers:\n");
5830 for (i = 0; i < 32; i++) {
5831 for (j = 0; j < 32; j++) {
5832 n = (i << 5) | j;
5833 spr = &env->spr_cb[n];
5834 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
5835 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
5836#if !defined(CONFIG_USER_ONLY)
5837 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
5838 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
5839 if (sw || sr || uw || ur) {
5840 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5841 (i << 5) | j, (i << 5) | j, spr->name,
5842 sw ? 'w' : '-', sr ? 'r' : '-',
5843 uw ? 'w' : '-', ur ? 'r' : '-');
5844 }
5845#else
5846 if (uw || ur) {
5847 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5848 (i << 5) | j, (i << 5) | j, spr->name,
5849 uw ? 'w' : '-', ur ? 'r' : '-');
5850 }
5851#endif
5852 }
5853 }
5854 fflush(stdout);
5855 fflush(stderr);
5856}
5857#endif
5858
5859/*****************************************************************************/
5860#include <stdlib.h>
5861#include <string.h>
5862
5863int fflush (FILE *stream);
5864
5865/* Opcode types */
5866enum {
5867 PPC_DIRECT = 0, /* Opcode routine */
5868 PPC_INDIRECT = 1, /* Indirect opcode table */
5869};
5870
5871static inline int is_indirect_opcode (void *handler)
5872{
5873 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
5874}
5875
5876static inline opc_handler_t **ind_table(void *handler)
5877{
5878 return (opc_handler_t **)((unsigned long)handler & ~3);
5879}
5880
5881/* Instruction table creation */
5882/* Opcodes tables creation */
5883static void fill_new_table (opc_handler_t **table, int len)
5884{
5885 int i;
5886
5887 for (i = 0; i < len; i++)
5888 table[i] = &invalid_handler;
5889}
5890
5891static int create_new_table (opc_handler_t **table, unsigned char idx)
5892{
5893 opc_handler_t **tmp;
5894
5895 tmp = malloc(0x20 * sizeof(opc_handler_t));
5896 if (tmp == NULL)
5897 return -1;
5898 fill_new_table(tmp, 0x20);
5899 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
5900
5901 return 0;
5902}
5903
5904static int insert_in_table (opc_handler_t **table, unsigned char idx,
5905 opc_handler_t *handler)
5906{
5907 if (table[idx] != &invalid_handler)
5908 return -1;
5909 table[idx] = handler;
5910
5911 return 0;
5912}
5913
5914static int register_direct_insn (opc_handler_t **ppc_opcodes,
5915 unsigned char idx, opc_handler_t *handler)
5916{
5917 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
5918 printf("*** ERROR: opcode %02x already assigned in main "
5919 "opcode table\n", idx);
5920 return -1;
5921 }
5922
5923 return 0;
5924}
5925
5926static int register_ind_in_table (opc_handler_t **table,
5927 unsigned char idx1, unsigned char idx2,
5928 opc_handler_t *handler)
5929{
5930 if (table[idx1] == &invalid_handler) {
5931 if (create_new_table(table, idx1) < 0) {
5932 printf("*** ERROR: unable to create indirect table "
5933 "idx=%02x\n", idx1);
5934 return -1;
5935 }
5936 } else {
5937 if (!is_indirect_opcode(table[idx1])) {
5938 printf("*** ERROR: idx %02x already assigned to a direct "
5939 "opcode\n", idx1);
5940 return -1;
5941 }
3a607854 5942 }
a750fc0b
JM		 5943 if (handler != NULL &&
5944 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
5945 printf("*** ERROR: opcode %02x already assigned in "
5946 "opcode table %02x\n", idx2, idx1);
5947 return -1;
3a607854 5948 }
a750fc0b
JM		 5949
5950 return 0;
5951}
5952
5953static int register_ind_insn (opc_handler_t **ppc_opcodes,
5954 unsigned char idx1, unsigned char idx2,
5955 opc_handler_t *handler)
5956{
5957 int ret;
5958
5959 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
5960
5961 return ret;
5962}
5963
5964static int register_dblind_insn (opc_handler_t **ppc_opcodes,
5965 unsigned char idx1, unsigned char idx2,
5966 unsigned char idx3, opc_handler_t *handler)
5967{
5968 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
5969 printf("*** ERROR: unable to join indirect table idx "
5970 "[%02x-%02x]\n", idx1, idx2);
5971 return -1;
5972 }
5973 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
5974 handler) < 0) {
5975 printf("*** ERROR: unable to insert opcode "
5976 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
5977 return -1;
5978 }
5979
5980 return 0;
5981}
5982
5983static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
5984{
5985 if (insn->opc2 != 0xFF) {
5986 if (insn->opc3 != 0xFF) {
5987 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
5988 insn->opc3, &insn->handler) < 0)
5989 return -1;
5990 } else {
5991 if (register_ind_insn(ppc_opcodes, insn->opc1,
5992 insn->opc2, &insn->handler) < 0)
5993 return -1;
5994 }
5995 } else {
5996 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
5997 return -1;
5998 }
5999
6000 return 0;
6001}
6002
6003static int test_opcode_table (opc_handler_t **table, int len)
6004{
6005 int i, count, tmp;
6006
6007 for (i = 0, count = 0; i < len; i++) {
6008 /* Consistency fixup */
6009 if (table[i] == NULL)
6010 table[i] = &invalid_handler;
6011 if (table[i] != &invalid_handler) {
6012 if (is_indirect_opcode(table[i])) {
6013 tmp = test_opcode_table(ind_table(table[i]), 0x20);
6014 if (tmp == 0) {
6015 free(table[i]);
6016 table[i] = &invalid_handler;
6017 } else {
6018 count++;
6019 }
6020 } else {
6021 count++;
6022 }
6023 }
6024 }
6025
6026 return count;
6027}
6028
6029static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
6030{
6031 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
6032 printf("*** WARNING: no opcode defined !\n");
6033}
6034
6035/*****************************************************************************/
6036static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
6037{
6038 opcode_t *opc, *start, *end;
6039
6040 fill_new_table(env->opcodes, 0x40);
6041 if (&opc_start < &opc_end) {
6042 start = &opc_start;
6043 end = &opc_end;
6044 } else {
6045 start = &opc_end;
6046 end = &opc_start;
6047 }
6048 for (opc = start + 1; opc != end; opc++) {
6049 if ((opc->handler.type & def->insns_flags) != 0) {
6050 if (register_insn(env->opcodes, opc) < 0) {
6051 printf("*** ERROR initializing PowerPC instruction "
6052 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
6053 opc->opc3);
6054 return -1;
6055 }
6056 }
6057 }
6058 fix_opcode_tables(env->opcodes);
6059 fflush(stdout);
6060 fflush(stderr);
6061
6062 return 0;
6063}
6064
6065#if defined(PPC_DUMP_CPU)
6066static int dump_ppc_insns (CPUPPCState *env)
6067{
6068 opc_handler_t **table, *handler;
6069 uint8_t opc1, opc2, opc3;
6070
6071 printf("Instructions set:\n");
6072 /* opc1 is 6 bits long */
6073 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
6074 table = env->opcodes;
6075 handler = table[opc1];
6076 if (is_indirect_opcode(handler)) {
6077 /* opc2 is 5 bits long */
6078 for (opc2 = 0; opc2 < 0x20; opc2++) {
6079 table = env->opcodes;
6080 handler = env->opcodes[opc1];
6081 table = ind_table(handler);
6082 handler = table[opc2];
6083 if (is_indirect_opcode(handler)) {
6084 table = ind_table(handler);
6085 /* opc3 is 5 bits long */
6086 for (opc3 = 0; opc3 < 0x20; opc3++) {
6087 handler = table[opc3];
6088 if (handler->handler != &gen_invalid) {
6089 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
6090 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
6091 handler->oname);
6092 }
6093 }
6094 } else {
6095 if (handler->handler != &gen_invalid) {
6096 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
6097 opc1, opc2, opc1, opc2, handler->oname);
6098 }
6099 }
6100 }
6101 } else {
6102 if (handler->handler != &gen_invalid) {
6103 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6104 opc1, opc1, handler->oname);
6105 }
6106 }
6107 }
6108}
3a607854 6109#endif
a750fc0b
JM		 6110
6111int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
6112{
6113 env->msr_mask = def->msr_mask;
6114 env->mmu_model = def->mmu_model;
6115 env->excp_model = def->excp_model;
6116 env->bus_model = def->bus_model;
d26bfc9a 6117 env->flags = def->flags;
237c0af0 6118 env->bfd_mach = def->bfd_mach;
a750fc0b
JM		 6119 if (create_ppc_opcodes(env, def) < 0)
6120 return -1;
6121 init_ppc_proc(env, def);
6122#if defined(PPC_DUMP_CPU)
3a607854 6123 {
a750fc0b
JM		 6124 const unsigned char *mmu_model, *excp_model, *bus_model;
6125 switch (env->mmu_model) {
6126 case POWERPC_MMU_32B:
6127 mmu_model = "PowerPC 32";
6128 break;
a750fc0b
JM		 6129 case POWERPC_MMU_601:
6130 mmu_model = "PowerPC 601";
6131 break;
6132 case POWERPC_MMU_SOFT_6xx:
6133 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
6134 break;
6135 case POWERPC_MMU_SOFT_74xx:
6136 mmu_model = "PowerPC 74xx with software driven TLBs";
6137 break;
6138 case POWERPC_MMU_SOFT_4xx:
6139 mmu_model = "PowerPC 4xx with software driven TLBs";
6140 break;
6141 case POWERPC_MMU_SOFT_4xx_Z:
6142 mmu_model = "PowerPC 4xx with software driven TLBs "
6143 "and zones protections";
6144 break;
6145 case POWERPC_MMU_REAL_4xx:
6146 mmu_model = "PowerPC 4xx real mode only";
6147 break;
6148 case POWERPC_MMU_BOOKE:
6149 mmu_model = "PowerPC BookE";
6150 break;
6151 case POWERPC_MMU_BOOKE_FSL:
6152 mmu_model = "PowerPC BookE FSL";
6153 break;
00af685f
JM		 6154#if defined (TARGET_PPC64)
6155 case POWERPC_MMU_64B:
6156 mmu_model = "PowerPC 64";
6157 break;
00af685f 6158#endif
a750fc0b
JM		 6159 default:
6160 mmu_model = "Unknown or invalid";
6161 break;
6162 }
6163 switch (env->excp_model) {
6164 case POWERPC_EXCP_STD:
6165 excp_model = "PowerPC";
6166 break;
6167 case POWERPC_EXCP_40x:
6168 excp_model = "PowerPC 40x";
6169 break;
6170 case POWERPC_EXCP_601:
6171 excp_model = "PowerPC 601";
6172 break;
6173 case POWERPC_EXCP_602:
6174 excp_model = "PowerPC 602";
6175 break;
6176 case POWERPC_EXCP_603:
6177 excp_model = "PowerPC 603";
6178 break;
6179 case POWERPC_EXCP_603E:
6180 excp_model = "PowerPC 603e";
6181 break;
6182 case POWERPC_EXCP_604:
6183 excp_model = "PowerPC 604";
6184 break;
6185 case POWERPC_EXCP_7x0:
6186 excp_model = "PowerPC 740/750";
6187 break;
6188 case POWERPC_EXCP_7x5:
6189 excp_model = "PowerPC 745/755";
6190 break;
6191 case POWERPC_EXCP_74xx:
6192 excp_model = "PowerPC 74xx";
6193 break;
a750fc0b
JM		 6194 case POWERPC_EXCP_BOOKE:
6195 excp_model = "PowerPC BookE";
6196 break;
00af685f
JM		 6197#if defined (TARGET_PPC64)
6198 case POWERPC_EXCP_970:
6199 excp_model = "PowerPC 970";
6200 break;
6201#endif
a750fc0b
JM		 6202 default:
6203 excp_model = "Unknown or invalid";
6204 break;
6205 }
6206 switch (env->bus_model) {
6207 case PPC_FLAGS_INPUT_6xx:
6208 bus_model = "PowerPC 6xx";
6209 break;
6210 case PPC_FLAGS_INPUT_BookE:
6211 bus_model = "PowerPC BookE";
6212 break;
6213 case PPC_FLAGS_INPUT_405:
6214 bus_model = "PowerPC 405";
6215 break;
a750fc0b
JM		 6216 case PPC_FLAGS_INPUT_401:
6217 bus_model = "PowerPC 401/403";
6218 break;
00af685f
JM		 6219#if defined (TARGET_PPC64)
6220 case PPC_FLAGS_INPUT_970:
6221 bus_model = "PowerPC 970";
6222 break;
6223#endif
a750fc0b
JM		 6224 default:
6225 bus_model = "Unknown or invalid";
6226 break;
6227 }
6228 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6229 " MMU model : %s\n",
6230 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 6231#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 6232 if (env->tlb != NULL) {
6233 printf(" %d %s TLB in %d ways\n",
6234 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6235 env->nb_ways);
6236 }
f2e63a42 6237#endif
a750fc0b
JM		 6238 printf(" Exceptions model : %s\n"
6239 " Bus model : %s\n",
6240 excp_model, bus_model);
6241 }
6242 dump_ppc_insns(env);
6243 dump_ppc_sprs(env);
6244 fflush(stdout);
3a607854 6245#endif
a750fc0b
JM		 6246
6247 return 0;
6248}
3fc6c082
FB		 6249
6250int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
6251{
068abdc8 6252 int i, max, ret;
3fc6c082
FB		 6253
6254 ret = -1;
6255 *def = NULL;
068abdc8
JM		 6256 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6257 for (i = 0; i < max; i++) {
3fc6c082
FB		 6258 if (strcasecmp(name, ppc_defs[i].name) == 0) {
6259 *def = &ppc_defs[i];
6260 ret = 0;
6261 break;
6262 }
6263 }
6264
6265 return ret;
6266}
6267
6268int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
6269{
068abdc8 6270 int i, max, ret;
3fc6c082
FB		 6271
6272 ret = -1;
6273 *def = NULL;
068abdc8
JM		 6274 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6275 for (i = 0; i < max; i++) {
3fc6c082
FB		 6276 if ((pvr & ppc_defs[i].pvr_mask) ==
6277 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
6278 *def = &ppc_defs[i];
6279 ret = 0;
6280 break;
6281 }
6282 }
6283
6284 return ret;
6285}
6286
6287void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
6288{
068abdc8 6289 int i, max;
3fc6c082 6290
068abdc8
JM		 6291 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6292 for (i = 0; i < max; i++) {
a750fc0b
JM		 6293 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
6294 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 6295 }
6296}
Qemu copy for testing