]> git.proxmox.com Git - qemu.git/blame - target-ppc/translate_init.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Change default werror semantics from "report" to "enospc"
[qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
3fc6c082
FB		 19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0 26#include "dis-asm.h"
ee4e83ed 27#include "host-utils.h"
4e47ea67 28#include "gdbstub.h"
237c0af0 29
3fc6c082
FB		 30//#define PPC_DUMP_CPU
31//#define PPC_DEBUG_SPR
80d11f44
JM		 32//#define PPC_DUMP_SPR_ACCESSES
33#if defined(CONFIG_USER_ONLY)
34#define TODO_USER_ONLY 1
35#endif
3fc6c082
FB		 36
37struct ppc_def_t {
b55266b5 38 const char *name;
3fc6c082 39 uint32_t pvr;
80d11f44 40 uint32_t svr;
0487d6a8 41 uint64_t insns_flags;
3fc6c082 42 uint64_t msr_mask;
7820dbf3
JM		 43 powerpc_mmu_t mmu_model;
44 powerpc_excp_t excp_model;
45 powerpc_input_t bus_model;
d26bfc9a 46 uint32_t flags;
237c0af0 47 int bfd_mach;
a750fc0b 48 void (*init_proc)(CPUPPCState *env);
4c1b1bfe 49 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 50};
51
e9df014c
JM		 52/* For user-mode emulation, we don't emulate any IRQ controller */
53#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 54#define PPC_IRQ_INIT_FN(name) \
55static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
56{ \
e9df014c
JM		 57}
58#else
a750fc0b 59#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 60void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
61#endif
a750fc0b 62
4e290a0b 63PPC_IRQ_INIT_FN(40x);
e9df014c 64PPC_IRQ_INIT_FN(6xx);
d0dfae6e 65PPC_IRQ_INIT_FN(970);
e9df014c 66
3fc6c082
FB		 67/* Generic callbacks:
68 * do nothing but store/retrieve spr value
69 */
45d827d2 70static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 71{
45d827d2
AJ		 72 gen_load_spr(cpu_gpr[gprn], sprn);
73#ifdef PPC_DUMP_SPR_ACCESSES
74 {
75 TCGv t0 = tcg_const_i32(sprn);
76 gen_helper_load_dump_spr(t0);
77 tcg_temp_free_i32(t0);
78 }
79#endif
a496775f
JM		 80}
81
45d827d2 82static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 83{
45d827d2
AJ		 84 gen_store_spr(sprn, cpu_gpr[gprn]);
85#ifdef PPC_DUMP_SPR_ACCESSES
86 {
87 TCGv t0 = tcg_const_i32(sprn);
88 gen_helper_store_dump_spr(t0);
89 tcg_temp_free_i32(t0);
90 }
04f20795 91#endif
45d827d2 92}
a496775f
JM		 93
94#if !defined(CONFIG_USER_ONLY)
45d827d2 95static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 96{
45d827d2
AJ		 97 TCGv t0 = tcg_temp_new();
98 TCGv t1 = tcg_temp_new();
99 gen_load_spr(t0, sprn);
100 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
101 tcg_gen_and_tl(t0, t0, t1);
102 gen_store_spr(sprn, t0);
103 tcg_temp_free(t0);
104 tcg_temp_free(t1);
a496775f
JM		 105}
106#endif
107
76a66253 108/* SPR common to all PowerPC */
3fc6c082 109/* XER */
45d827d2 110static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 111{
45d827d2 112 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
3fc6c082
FB		 113}
114
45d827d2 115static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 116{
45d827d2 117 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
3fc6c082
FB		 118}
119
120/* LR */
45d827d2 121static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 122{
45d827d2 123 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 124}
125
45d827d2 126static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 127{
45d827d2 128 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 129}
130
131/* CTR */
45d827d2 132static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 133{
45d827d2 134 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 135}
136
45d827d2 137static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 138{
45d827d2 139 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 140}
141
142/* User read access to SPR */
143/* USPRx */
144/* UMMCRx */
145/* UPMCx */
146/* USIA */
147/* UDECR */
45d827d2 148static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 149{
45d827d2 150 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 151}
152
76a66253 153/* SPR common to all non-embedded PowerPC */
3fc6c082 154/* DECR */
76a66253 155#if !defined(CONFIG_USER_ONLY)
45d827d2 156static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 157{
45d827d2 158 gen_helper_load_decr(cpu_gpr[gprn]);
3fc6c082
FB		 159}
160
45d827d2 161static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 162{
45d827d2 163 gen_helper_store_decr(cpu_gpr[gprn]);
3fc6c082 164}
76a66253 165#endif
3fc6c082 166
76a66253 167/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 168/* Time base */
45d827d2 169static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 170{
45d827d2 171 gen_helper_load_tbl(cpu_gpr[gprn]);
3fc6c082
FB		 172}
173
45d827d2 174static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 175{
45d827d2 176 gen_helper_load_tbu(cpu_gpr[gprn]);
3fc6c082
FB		 177}
178
a062e36c 179__attribute__ (( unused ))
45d827d2 180static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 181{
45d827d2 182 gen_helper_load_atbl(cpu_gpr[gprn]);
a062e36c
JM		 183}
184
185__attribute__ (( unused ))
45d827d2 186static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 187{
45d827d2 188 gen_helper_load_atbu(cpu_gpr[gprn]);
a062e36c
JM		 189}
190
76a66253 191#if !defined(CONFIG_USER_ONLY)
45d827d2 192static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 193{
45d827d2 194 gen_helper_store_tbl(cpu_gpr[gprn]);
3fc6c082
FB		 195}
196
45d827d2 197static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 198{
45d827d2 199 gen_helper_store_tbu(cpu_gpr[gprn]);
3fc6c082 200}
a062e36c
JM		 201
202__attribute__ (( unused ))
45d827d2 203static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 204{
45d827d2 205 gen_helper_store_atbl(cpu_gpr[gprn]);
a062e36c
JM		 206}
207
208__attribute__ (( unused ))
45d827d2 209static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 210{
45d827d2 211 gen_helper_store_atbu(cpu_gpr[gprn]);
a062e36c 212}
76a66253 213#endif
3fc6c082 214
76a66253 215#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 216/* IBAT0U...IBAT0U */
217/* IBAT0L...IBAT7L */
45d827d2 218static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 219{
45d827d2 220 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 221}
222
45d827d2 223static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 224{
45d827d2 225 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 226}
227
45d827d2 228static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 229{
45d827d2
AJ		 230 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
231 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
232 tcg_temp_free_i32(t0);
3fc6c082
FB		 233}
234
45d827d2 235static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 236{
45d827d2
AJ		 237 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2);
238 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
239 tcg_temp_free_i32(t0);
3fc6c082
FB		 240}
241
45d827d2 242static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 243{
45d827d2
AJ		 244 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
245 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
246 tcg_temp_free_i32(t0);
3fc6c082
FB		 247}
248
45d827d2 249static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 250{
45d827d2
AJ		 251 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2);
252 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
253 tcg_temp_free_i32(t0);
3fc6c082
FB		 254}
255
256/* DBAT0U...DBAT7U */
257/* DBAT0L...DBAT7L */
45d827d2 258static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 259{
45d827d2 260 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 261}
262
45d827d2 263static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 264{
45d827d2 265 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 266}
267
45d827d2 268static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 269{
45d827d2
AJ		 270 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
271 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
272 tcg_temp_free_i32(t0);
3fc6c082
FB		 273}
274
45d827d2 275static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 276{
45d827d2
AJ		 277 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
278 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
279 tcg_temp_free_i32(t0);
3fc6c082
FB		 280}
281
45d827d2 282static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 283{
45d827d2
AJ		 284 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
285 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
286 tcg_temp_free_i32(t0);
3fc6c082
FB		 287}
288
45d827d2 289static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 290{
45d827d2
AJ		 291 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
292 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
293 tcg_temp_free_i32(t0);
3fc6c082
FB		 294}
295
296/* SDR1 */
45d827d2 297static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
3fc6c082 298{
45d827d2 299 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
3fc6c082
FB		 300}
301
45d827d2 302static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 303{
45d827d2 304 gen_helper_store_sdr1(cpu_gpr[gprn]);
3fc6c082
FB		 305}
306
76a66253
JM		 307/* 64 bits PowerPC specific SPRs */
308/* ASR */
578bb252 309#if defined(TARGET_PPC64)
45d827d2 310static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 311{
45d827d2 312 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
76a66253
JM		 313}
314
45d827d2 315static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 316{
45d827d2 317 gen_helper_store_asr(cpu_gpr[gprn]);
76a66253
JM		 318}
319#endif
a750fc0b 320#endif
76a66253
JM		 321
322/* PowerPC 601 specific registers */
323/* RTC */
45d827d2 324static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 325{
45d827d2 326 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
76a66253
JM		 327}
328
45d827d2 329static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 330{
45d827d2 331 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 332}
333
334#if !defined(CONFIG_USER_ONLY)
45d827d2 335static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 336{
45d827d2 337 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 338}
339
45d827d2 340static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 341{
45d827d2 342 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
76a66253 343}
056401ea 344
45d827d2 345static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 346{
347 DisasContext *ctx = opaque;
348
45d827d2 349 gen_helper_store_hid0_601(cpu_gpr[gprn]);
056401ea 350 /* Must stop the translation as endianness may have changed */
e06fcd75 351 gen_stop_exception(ctx);
056401ea 352}
76a66253
JM		 353#endif
354
355/* Unified bats */
356#if !defined(CONFIG_USER_ONLY)
45d827d2 357static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 358{
45d827d2 359 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 360}
361
45d827d2 362static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 363{
45d827d2
AJ		 364 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
365 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
366 tcg_temp_free_i32(t0);
76a66253
JM		 367}
368
45d827d2 369static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 370{
45d827d2
AJ		 371 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
372 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
373 tcg_temp_free_i32(t0);
76a66253
JM		 374}
375#endif
376
377/* PowerPC 40x specific registers */
378#if !defined(CONFIG_USER_ONLY)
45d827d2 379static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 380{
45d827d2 381 gen_helper_load_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 382}
383
45d827d2 384static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 385{
45d827d2 386 gen_helper_store_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 387}
388
45d827d2 389static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 390{
391 DisasContext *ctx = opaque;
392
45d827d2 393 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
8ecc7913 394 /* We must stop translation as we may have rebooted */
e06fcd75 395 gen_stop_exception(ctx);
8ecc7913
JM		 396}
397
45d827d2 398static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 399{
45d827d2 400 gen_helper_store_40x_sler(cpu_gpr[gprn]);
c294fc58
JM		 401}
402
45d827d2 403static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 404{
45d827d2 405 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
76a66253
JM		 406}
407
45d827d2 408static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 409{
45d827d2 410 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
76a66253
JM		 411}
412#endif
413
414/* PowerPC 403 specific registers */
415/* PBL1 / PBU1 / PBL2 / PBU2 */
416#if !defined(CONFIG_USER_ONLY)
45d827d2 417static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 418{
45d827d2 419 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 420}
421
45d827d2 422static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 423{
45d827d2
AJ		 424 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
425 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
426 tcg_temp_free_i32(t0);
76a66253
JM		 427}
428
45d827d2 429static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 430{
45d827d2
AJ		 431 TCGv t0 = tcg_temp_new();
432 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
433 gen_store_spr(SPR_PIR, t0);
434 tcg_temp_free(t0);
3fc6c082 435}
76a66253 436#endif
3fc6c082 437
6f5d427d
JM		 438#if !defined(CONFIG_USER_ONLY)
439/* Callback used to write the exception vector base */
45d827d2 440static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 441{
45d827d2
AJ		 442 TCGv t0 = tcg_temp_new();
443 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
444 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
445 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
446 gen_store_spr(sprn, t0);
6f5d427d
JM		 447}
448
45d827d2 449static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 450{
451 DisasContext *ctx = opaque;
452
453 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
45d827d2
AJ		 454 TCGv t0 = tcg_temp_new();
455 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
456 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
457 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
458 gen_store_spr(sprn, t0);
459 tcg_temp_free(t0);
6f5d427d 460 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
45d827d2
AJ		 461 TCGv t0 = tcg_temp_new();
462 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
463 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
464 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
465 gen_store_spr(sprn, t0);
466 tcg_temp_free(t0);
6f5d427d
JM		 467 } else {
468 printf("Trying to write an unknown exception vector %d %03x\n",
469 sprn, sprn);
e06fcd75 470 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6f5d427d
JM		 471 }
472}
473#endif
474
cf8358c8
AJ		 475static inline void vscr_init (CPUPPCState *env, uint32_t val)
476{
477 env->vscr = val;
478 /* Altivec always uses round-to-nearest */
479 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
480 set_flush_to_zero(vscr_nj, &env->vec_status);
481}
482
76a66253
JM		 483#if defined(CONFIG_USER_ONLY)
484#define spr_register(env, num, name, uea_read, uea_write, \
485 oea_read, oea_write, initial_value) \
486do { \
487 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
488} while (0)
489static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 490 const char *name,
45d827d2
AJ		 491 void (*uea_read)(void *opaque, int gprn, int sprn),
492 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 493 target_ulong initial_value)
494#else
3fc6c082 495static inline void spr_register (CPUPPCState *env, int num,
b55266b5 496 const char *name,
45d827d2
AJ		 497 void (*uea_read)(void *opaque, int gprn, int sprn),
498 void (*uea_write)(void *opaque, int sprn, int gprn),
499 void (*oea_read)(void *opaque, int gprn, int sprn),
500 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 501 target_ulong initial_value)
76a66253 502#endif
3fc6c082
FB		 503{
504 ppc_spr_t *spr;
505
506 spr = &env->spr_cb[num];
507 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 508#if !defined(CONFIG_USER_ONLY)
509 spr->oea_read != NULL || spr->oea_write != NULL ||
510#endif
511 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 512 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
513 exit(1);
514 }
515#if defined(PPC_DEBUG_SPR)
1b9eb036 516 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 517 initial_value);
3fc6c082
FB		 518#endif
519 spr->name = name;
520 spr->uea_read = uea_read;
521 spr->uea_write = uea_write;
76a66253 522#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 523 spr->oea_read = oea_read;
524 spr->oea_write = oea_write;
76a66253 525#endif
3fc6c082
FB		 526 env->spr[num] = initial_value;
527}
528
529/* Generic PowerPC SPRs */
530static void gen_spr_generic (CPUPPCState *env)
531{
532 /* Integer processing */
533 spr_register(env, SPR_XER, "XER",
534 &spr_read_xer, &spr_write_xer,
535 &spr_read_xer, &spr_write_xer,
536 0x00000000);
537 /* Branch contol */
538 spr_register(env, SPR_LR, "LR",
539 &spr_read_lr, &spr_write_lr,
540 &spr_read_lr, &spr_write_lr,
541 0x00000000);
542 spr_register(env, SPR_CTR, "CTR",
543 &spr_read_ctr, &spr_write_ctr,
544 &spr_read_ctr, &spr_write_ctr,
545 0x00000000);
546 /* Interrupt processing */
547 spr_register(env, SPR_SRR0, "SRR0",
548 SPR_NOACCESS, SPR_NOACCESS,
549 &spr_read_generic, &spr_write_generic,
550 0x00000000);
551 spr_register(env, SPR_SRR1, "SRR1",
552 SPR_NOACCESS, SPR_NOACCESS,
553 &spr_read_generic, &spr_write_generic,
554 0x00000000);
555 /* Processor control */
556 spr_register(env, SPR_SPRG0, "SPRG0",
557 SPR_NOACCESS, SPR_NOACCESS,
558 &spr_read_generic, &spr_write_generic,
559 0x00000000);
560 spr_register(env, SPR_SPRG1, "SPRG1",
561 SPR_NOACCESS, SPR_NOACCESS,
562 &spr_read_generic, &spr_write_generic,
563 0x00000000);
564 spr_register(env, SPR_SPRG2, "SPRG2",
565 SPR_NOACCESS, SPR_NOACCESS,
566 &spr_read_generic, &spr_write_generic,
567 0x00000000);
568 spr_register(env, SPR_SPRG3, "SPRG3",
569 SPR_NOACCESS, SPR_NOACCESS,
570 &spr_read_generic, &spr_write_generic,
571 0x00000000);
572}
573
574/* SPR common to all non-embedded PowerPC, including 601 */
575static void gen_spr_ne_601 (CPUPPCState *env)
576{
577 /* Exception processing */
578 spr_register(env, SPR_DSISR, "DSISR",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_generic, &spr_write_generic,
581 0x00000000);
582 spr_register(env, SPR_DAR, "DAR",
583 SPR_NOACCESS, SPR_NOACCESS,
584 &spr_read_generic, &spr_write_generic,
585 0x00000000);
586 /* Timer */
587 spr_register(env, SPR_DECR, "DECR",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_decr, &spr_write_decr,
590 0x00000000);
591 /* Memory management */
592 spr_register(env, SPR_SDR1, "SDR1",
593 SPR_NOACCESS, SPR_NOACCESS,
594 &spr_read_sdr1, &spr_write_sdr1,
595 0x00000000);
596}
597
598/* BATs 0-3 */
599static void gen_low_BATs (CPUPPCState *env)
600{
f2e63a42 601#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 602 spr_register(env, SPR_IBAT0U, "IBAT0U",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_ibat, &spr_write_ibatu,
605 0x00000000);
606 spr_register(env, SPR_IBAT0L, "IBAT0L",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_ibat, &spr_write_ibatl,
609 0x00000000);
610 spr_register(env, SPR_IBAT1U, "IBAT1U",
611 SPR_NOACCESS, SPR_NOACCESS,
612 &spr_read_ibat, &spr_write_ibatu,
613 0x00000000);
614 spr_register(env, SPR_IBAT1L, "IBAT1L",
615 SPR_NOACCESS, SPR_NOACCESS,
616 &spr_read_ibat, &spr_write_ibatl,
617 0x00000000);
618 spr_register(env, SPR_IBAT2U, "IBAT2U",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_ibat, &spr_write_ibatu,
621 0x00000000);
622 spr_register(env, SPR_IBAT2L, "IBAT2L",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_ibat, &spr_write_ibatl,
625 0x00000000);
626 spr_register(env, SPR_IBAT3U, "IBAT3U",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_ibat, &spr_write_ibatu,
629 0x00000000);
630 spr_register(env, SPR_IBAT3L, "IBAT3L",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_ibat, &spr_write_ibatl,
633 0x00000000);
634 spr_register(env, SPR_DBAT0U, "DBAT0U",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_dbat, &spr_write_dbatu,
637 0x00000000);
638 spr_register(env, SPR_DBAT0L, "DBAT0L",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_dbat, &spr_write_dbatl,
641 0x00000000);
642 spr_register(env, SPR_DBAT1U, "DBAT1U",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_dbat, &spr_write_dbatu,
645 0x00000000);
646 spr_register(env, SPR_DBAT1L, "DBAT1L",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_dbat, &spr_write_dbatl,
649 0x00000000);
650 spr_register(env, SPR_DBAT2U, "DBAT2U",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_dbat, &spr_write_dbatu,
653 0x00000000);
654 spr_register(env, SPR_DBAT2L, "DBAT2L",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_dbat, &spr_write_dbatl,
657 0x00000000);
658 spr_register(env, SPR_DBAT3U, "DBAT3U",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_dbat, &spr_write_dbatu,
661 0x00000000);
662 spr_register(env, SPR_DBAT3L, "DBAT3L",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_dbat, &spr_write_dbatl,
665 0x00000000);
a750fc0b 666 env->nb_BATs += 4;
f2e63a42 667#endif
3fc6c082
FB		 668}
669
670/* BATs 4-7 */
671static void gen_high_BATs (CPUPPCState *env)
672{
f2e63a42 673#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 674 spr_register(env, SPR_IBAT4U, "IBAT4U",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_ibat_h, &spr_write_ibatu_h,
677 0x00000000);
678 spr_register(env, SPR_IBAT4L, "IBAT4L",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_ibat_h, &spr_write_ibatl_h,
681 0x00000000);
682 spr_register(env, SPR_IBAT5U, "IBAT5U",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_ibat_h, &spr_write_ibatu_h,
685 0x00000000);
686 spr_register(env, SPR_IBAT5L, "IBAT5L",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_ibat_h, &spr_write_ibatl_h,
689 0x00000000);
690 spr_register(env, SPR_IBAT6U, "IBAT6U",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_ibat_h, &spr_write_ibatu_h,
693 0x00000000);
694 spr_register(env, SPR_IBAT6L, "IBAT6L",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_ibat_h, &spr_write_ibatl_h,
697 0x00000000);
698 spr_register(env, SPR_IBAT7U, "IBAT7U",
699 SPR_NOACCESS, SPR_NOACCESS,
700 &spr_read_ibat_h, &spr_write_ibatu_h,
701 0x00000000);
702 spr_register(env, SPR_IBAT7L, "IBAT7L",
703 SPR_NOACCESS, SPR_NOACCESS,
704 &spr_read_ibat_h, &spr_write_ibatl_h,
705 0x00000000);
706 spr_register(env, SPR_DBAT4U, "DBAT4U",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_dbat_h, &spr_write_dbatu_h,
709 0x00000000);
710 spr_register(env, SPR_DBAT4L, "DBAT4L",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_dbat_h, &spr_write_dbatl_h,
713 0x00000000);
714 spr_register(env, SPR_DBAT5U, "DBAT5U",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_dbat_h, &spr_write_dbatu_h,
717 0x00000000);
718 spr_register(env, SPR_DBAT5L, "DBAT5L",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_dbat_h, &spr_write_dbatl_h,
721 0x00000000);
722 spr_register(env, SPR_DBAT6U, "DBAT6U",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_dbat_h, &spr_write_dbatu_h,
725 0x00000000);
726 spr_register(env, SPR_DBAT6L, "DBAT6L",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_dbat_h, &spr_write_dbatl_h,
729 0x00000000);
730 spr_register(env, SPR_DBAT7U, "DBAT7U",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_dbat_h, &spr_write_dbatu_h,
733 0x00000000);
734 spr_register(env, SPR_DBAT7L, "DBAT7L",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_dbat_h, &spr_write_dbatl_h,
737 0x00000000);
a750fc0b 738 env->nb_BATs += 4;
f2e63a42 739#endif
3fc6c082
FB		 740}
741
742/* Generic PowerPC time base */
743static void gen_tbl (CPUPPCState *env)
744{
745 spr_register(env, SPR_VTBL, "TBL",
746 &spr_read_tbl, SPR_NOACCESS,
747 &spr_read_tbl, SPR_NOACCESS,
748 0x00000000);
749 spr_register(env, SPR_TBL, "TBL",
750 SPR_NOACCESS, SPR_NOACCESS,
751 SPR_NOACCESS, &spr_write_tbl,
752 0x00000000);
753 spr_register(env, SPR_VTBU, "TBU",
754 &spr_read_tbu, SPR_NOACCESS,
755 &spr_read_tbu, SPR_NOACCESS,
756 0x00000000);
757 spr_register(env, SPR_TBU, "TBU",
758 SPR_NOACCESS, SPR_NOACCESS,
759 SPR_NOACCESS, &spr_write_tbu,
760 0x00000000);
761}
762
76a66253
JM		 763/* Softare table search registers */
764static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
765{
f2e63a42 766#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 767 env->nb_tlb = nb_tlbs;
768 env->nb_ways = nb_ways;
769 env->id_tlbs = 1;
770 spr_register(env, SPR_DMISS, "DMISS",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, SPR_NOACCESS,
773 0x00000000);
774 spr_register(env, SPR_DCMP, "DCMP",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, SPR_NOACCESS,
777 0x00000000);
778 spr_register(env, SPR_HASH1, "HASH1",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, SPR_NOACCESS,
781 0x00000000);
782 spr_register(env, SPR_HASH2, "HASH2",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_generic, SPR_NOACCESS,
785 0x00000000);
786 spr_register(env, SPR_IMISS, "IMISS",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, SPR_NOACCESS,
789 0x00000000);
790 spr_register(env, SPR_ICMP, "ICMP",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_generic, SPR_NOACCESS,
793 0x00000000);
794 spr_register(env, SPR_RPA, "RPA",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_generic, &spr_write_generic,
797 0x00000000);
f2e63a42 798#endif
76a66253
JM		 799}
800
801/* SPR common to MPC755 and G2 */
802static void gen_spr_G2_755 (CPUPPCState *env)
803{
804 /* SGPRs */
805 spr_register(env, SPR_SPRG4, "SPRG4",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_generic, &spr_write_generic,
808 0x00000000);
809 spr_register(env, SPR_SPRG5, "SPRG5",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_generic, &spr_write_generic,
812 0x00000000);
813 spr_register(env, SPR_SPRG6, "SPRG6",
814 SPR_NOACCESS, SPR_NOACCESS,
815 &spr_read_generic, &spr_write_generic,
816 0x00000000);
817 spr_register(env, SPR_SPRG7, "SPRG7",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_generic, &spr_write_generic,
820 0x00000000);
76a66253
JM		 821}
822
3fc6c082
FB		 823/* SPR common to all 7xx PowerPC implementations */
824static void gen_spr_7xx (CPUPPCState *env)
825{
826 /* Breakpoints */
827 /* XXX : not implemented */
828 spr_register(env, SPR_DABR, "DABR",
829 SPR_NOACCESS, SPR_NOACCESS,
830 &spr_read_generic, &spr_write_generic,
831 0x00000000);
832 /* XXX : not implemented */
833 spr_register(env, SPR_IABR, "IABR",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_generic, &spr_write_generic,
836 0x00000000);
837 /* Cache management */
838 /* XXX : not implemented */
839 spr_register(env, SPR_ICTC, "ICTC",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_generic, &spr_write_generic,
842 0x00000000);
843 /* Performance monitors */
844 /* XXX : not implemented */
845 spr_register(env, SPR_MMCR0, "MMCR0",
846 SPR_NOACCESS, SPR_NOACCESS,
847 &spr_read_generic, &spr_write_generic,
848 0x00000000);
849 /* XXX : not implemented */
850 spr_register(env, SPR_MMCR1, "MMCR1",
851 SPR_NOACCESS, SPR_NOACCESS,
852 &spr_read_generic, &spr_write_generic,
853 0x00000000);
854 /* XXX : not implemented */
855 spr_register(env, SPR_PMC1, "PMC1",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_generic, &spr_write_generic,
858 0x00000000);
859 /* XXX : not implemented */
860 spr_register(env, SPR_PMC2, "PMC2",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, &spr_write_generic,
863 0x00000000);
864 /* XXX : not implemented */
865 spr_register(env, SPR_PMC3, "PMC3",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, &spr_write_generic,
868 0x00000000);
869 /* XXX : not implemented */
870 spr_register(env, SPR_PMC4, "PMC4",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, &spr_write_generic,
873 0x00000000);
874 /* XXX : not implemented */
a750fc0b 875 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, SPR_NOACCESS,
878 0x00000000);
578bb252 879 /* XXX : not implemented */
3fc6c082
FB		 880 spr_register(env, SPR_UMMCR0, "UMMCR0",
881 &spr_read_ureg, SPR_NOACCESS,
882 &spr_read_ureg, SPR_NOACCESS,
883 0x00000000);
578bb252 884 /* XXX : not implemented */
3fc6c082
FB		 885 spr_register(env, SPR_UMMCR1, "UMMCR1",
886 &spr_read_ureg, SPR_NOACCESS,
887 &spr_read_ureg, SPR_NOACCESS,
888 0x00000000);
578bb252 889 /* XXX : not implemented */
3fc6c082
FB		 890 spr_register(env, SPR_UPMC1, "UPMC1",
891 &spr_read_ureg, SPR_NOACCESS,
892 &spr_read_ureg, SPR_NOACCESS,
893 0x00000000);
578bb252 894 /* XXX : not implemented */
3fc6c082
FB		 895 spr_register(env, SPR_UPMC2, "UPMC2",
896 &spr_read_ureg, SPR_NOACCESS,
897 &spr_read_ureg, SPR_NOACCESS,
898 0x00000000);
578bb252 899 /* XXX : not implemented */
3fc6c082
FB		 900 spr_register(env, SPR_UPMC3, "UPMC3",
901 &spr_read_ureg, SPR_NOACCESS,
902 &spr_read_ureg, SPR_NOACCESS,
903 0x00000000);
578bb252 904 /* XXX : not implemented */
3fc6c082
FB		 905 spr_register(env, SPR_UPMC4, "UPMC4",
906 &spr_read_ureg, SPR_NOACCESS,
907 &spr_read_ureg, SPR_NOACCESS,
908 0x00000000);
578bb252 909 /* XXX : not implemented */
a750fc0b 910 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 911 &spr_read_ureg, SPR_NOACCESS,
912 &spr_read_ureg, SPR_NOACCESS,
913 0x00000000);
a750fc0b 914 /* External access control */
3fc6c082 915 /* XXX : not implemented */
a750fc0b 916 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, &spr_write_generic,
919 0x00000000);
a750fc0b
JM		 920}
921
922static void gen_spr_thrm (CPUPPCState *env)
923{
924 /* Thermal management */
3fc6c082 925 /* XXX : not implemented */
a750fc0b 926 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
930 /* XXX : not implemented */
a750fc0b 931 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 932 SPR_NOACCESS, SPR_NOACCESS,
933 &spr_read_generic, &spr_write_generic,
934 0x00000000);
3fc6c082 935 /* XXX : not implemented */
a750fc0b 936 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_generic, &spr_write_generic,
939 0x00000000);
940}
941
942/* SPR specific to PowerPC 604 implementation */
943static void gen_spr_604 (CPUPPCState *env)
944{
945 /* Processor identification */
946 spr_register(env, SPR_PIR, "PIR",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_pir,
949 0x00000000);
950 /* Breakpoints */
951 /* XXX : not implemented */
952 spr_register(env, SPR_IABR, "IABR",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, &spr_write_generic,
955 0x00000000);
956 /* XXX : not implemented */
957 spr_register(env, SPR_DABR, "DABR",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, &spr_write_generic,
960 0x00000000);
961 /* Performance counters */
962 /* XXX : not implemented */
963 spr_register(env, SPR_MMCR0, "MMCR0",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, &spr_write_generic,
966 0x00000000);
967 /* XXX : not implemented */
3fc6c082
FB		 968 spr_register(env, SPR_PMC1, "PMC1",
969 SPR_NOACCESS, SPR_NOACCESS,
970 &spr_read_generic, &spr_write_generic,
971 0x00000000);
972 /* XXX : not implemented */
973 spr_register(env, SPR_PMC2, "PMC2",
974 SPR_NOACCESS, SPR_NOACCESS,
975 &spr_read_generic, &spr_write_generic,
976 0x00000000);
977 /* XXX : not implemented */
a750fc0b 978 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 979 SPR_NOACCESS, SPR_NOACCESS,
980 &spr_read_generic, SPR_NOACCESS,
981 0x00000000);
982 /* XXX : not implemented */
983 spr_register(env, SPR_SDA, "SDA",
984 SPR_NOACCESS, SPR_NOACCESS,
985 &spr_read_generic, SPR_NOACCESS,
986 0x00000000);
987 /* External access control */
988 /* XXX : not implemented */
989 spr_register(env, SPR_EAR, "EAR",
990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, &spr_write_generic,
992 0x00000000);
993}
994
76a66253
JM		 995/* SPR specific to PowerPC 603 implementation */
996static void gen_spr_603 (CPUPPCState *env)
3fc6c082 997{
76a66253
JM		 998 /* External access control */
999 /* XXX : not implemented */
1000 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1001 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1002 &spr_read_generic, &spr_write_generic,
1003 0x00000000);
3fc6c082
FB		 1004}
1005
76a66253
JM		 1006/* SPR specific to PowerPC G2 implementation */
1007static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1008{
76a66253
JM		 1009 /* Memory base address */
1010 /* MBAR */
578bb252 1011 /* XXX : not implemented */
76a66253
JM		 1012 spr_register(env, SPR_MBAR, "MBAR",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1015 0x00000000);
76a66253 1016 /* Exception processing */
363be49c 1017 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, &spr_write_generic,
1020 0x00000000);
363be49c 1021 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, &spr_write_generic,
1024 0x00000000);
1025 /* Breakpoints */
1026 /* XXX : not implemented */
1027 spr_register(env, SPR_DABR, "DABR",
1028 SPR_NOACCESS, SPR_NOACCESS,
1029 &spr_read_generic, &spr_write_generic,
1030 0x00000000);
1031 /* XXX : not implemented */
1032 spr_register(env, SPR_DABR2, "DABR2",
1033 SPR_NOACCESS, SPR_NOACCESS,
1034 &spr_read_generic, &spr_write_generic,
1035 0x00000000);
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_IABR, "IABR",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_generic,
1040 0x00000000);
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_IABR2, "IABR2",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_IBCR, "IBCR",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_DBCR, "DBCR",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056}
1057
1058/* SPR specific to PowerPC 602 implementation */
1059static void gen_spr_602 (CPUPPCState *env)
1060{
1061 /* ESA registers */
1062 /* XXX : not implemented */
1063 spr_register(env, SPR_SER, "SER",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, &spr_write_generic,
1066 0x00000000);
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_SEBR, "SEBR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 /* XXX : not implemented */
a750fc0b 1073 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1074 SPR_NOACCESS, SPR_NOACCESS,
1075 &spr_read_generic, &spr_write_generic,
1076 0x00000000);
1077 /* Floating point status */
1078 /* XXX : not implemented */
1079 spr_register(env, SPR_SP, "SP",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 /* XXX : not implemented */
1084 spr_register(env, SPR_LT, "LT",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_generic,
1087 0x00000000);
1088 /* Watchdog timer */
1089 /* XXX : not implemented */
1090 spr_register(env, SPR_TCR, "TCR",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_generic, &spr_write_generic,
1093 0x00000000);
1094 /* Interrupt base */
1095 spr_register(env, SPR_IBR, "IBR",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_generic,
1098 0x00000000);
a750fc0b
JM		 1099 /* XXX : not implemented */
1100 spr_register(env, SPR_IABR, "IABR",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
76a66253
JM		 1104}
1105
1106/* SPR specific to PowerPC 601 implementation */
1107static void gen_spr_601 (CPUPPCState *env)
1108{
1109 /* Multiplication/division register */
1110 /* MQ */
1111 spr_register(env, SPR_MQ, "MQ",
1112 &spr_read_generic, &spr_write_generic,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* RTC registers */
1116 spr_register(env, SPR_601_RTCU, "RTCU",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 SPR_NOACCESS, &spr_write_601_rtcu,
1119 0x00000000);
1120 spr_register(env, SPR_601_VRTCU, "RTCU",
1121 &spr_read_601_rtcu, SPR_NOACCESS,
1122 &spr_read_601_rtcu, SPR_NOACCESS,
1123 0x00000000);
1124 spr_register(env, SPR_601_RTCL, "RTCL",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 SPR_NOACCESS, &spr_write_601_rtcl,
1127 0x00000000);
1128 spr_register(env, SPR_601_VRTCL, "RTCL",
1129 &spr_read_601_rtcl, SPR_NOACCESS,
1130 &spr_read_601_rtcl, SPR_NOACCESS,
1131 0x00000000);
1132 /* Timer */
1133#if 0 /* ? */
1134 spr_register(env, SPR_601_UDECR, "UDECR",
1135 &spr_read_decr, SPR_NOACCESS,
1136 &spr_read_decr, SPR_NOACCESS,
1137 0x00000000);
1138#endif
1139 /* External access control */
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_EAR, "EAR",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* Memory management */
f2e63a42 1146#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1147 spr_register(env, SPR_IBAT0U, "IBAT0U",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_601_ubat, &spr_write_601_ubatu,
1150 0x00000000);
1151 spr_register(env, SPR_IBAT0L, "IBAT0L",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_601_ubat, &spr_write_601_ubatl,
1154 0x00000000);
1155 spr_register(env, SPR_IBAT1U, "IBAT1U",
1156 SPR_NOACCESS, SPR_NOACCESS,
1157 &spr_read_601_ubat, &spr_write_601_ubatu,
1158 0x00000000);
1159 spr_register(env, SPR_IBAT1L, "IBAT1L",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_601_ubat, &spr_write_601_ubatl,
1162 0x00000000);
1163 spr_register(env, SPR_IBAT2U, "IBAT2U",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_601_ubat, &spr_write_601_ubatu,
1166 0x00000000);
1167 spr_register(env, SPR_IBAT2L, "IBAT2L",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_601_ubat, &spr_write_601_ubatl,
1170 0x00000000);
1171 spr_register(env, SPR_IBAT3U, "IBAT3U",
1172 SPR_NOACCESS, SPR_NOACCESS,
1173 &spr_read_601_ubat, &spr_write_601_ubatu,
1174 0x00000000);
1175 spr_register(env, SPR_IBAT3L, "IBAT3L",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_601_ubat, &spr_write_601_ubatl,
1178 0x00000000);
a750fc0b 1179 env->nb_BATs = 4;
f2e63a42 1180#endif
a750fc0b
JM		 1181}
1182
1183static void gen_spr_74xx (CPUPPCState *env)
1184{
1185 /* Processor identification */
1186 spr_register(env, SPR_PIR, "PIR",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_pir,
1189 0x00000000);
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_MMCR2, "MMCR2",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
578bb252 1195 /* XXX : not implemented */
a750fc0b
JM		 1196 spr_register(env, SPR_UMMCR2, "UMMCR2",
1197 &spr_read_ureg, SPR_NOACCESS,
1198 &spr_read_ureg, SPR_NOACCESS,
1199 0x00000000);
1200 /* XXX: not implemented */
1201 spr_register(env, SPR_BAMR, "BAMR",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 &spr_read_generic, &spr_write_generic,
1204 0x00000000);
578bb252 1205 /* XXX : not implemented */
a750fc0b
JM		 1206 spr_register(env, SPR_MSSCR0, "MSSCR0",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* Hardware implementation registers */
1211 /* XXX : not implemented */
1212 spr_register(env, SPR_HID0, "HID0",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 /* XXX : not implemented */
1217 spr_register(env, SPR_HID1, "HID1",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 0x00000000);
1221 /* Altivec */
1222 spr_register(env, SPR_VRSAVE, "VRSAVE",
1223 &spr_read_generic, &spr_write_generic,
1224 &spr_read_generic, &spr_write_generic,
1225 0x00000000);
bd928eba
JM		 1226 /* XXX : not implemented */
1227 spr_register(env, SPR_L2CR, "L2CR",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
cf8358c8
AJ		 1231 /* Not strictly an SPR */
1232 vscr_init(env, 0x00010000);
a750fc0b
JM		 1233}
1234
a750fc0b
JM		 1235static void gen_l3_ctrl (CPUPPCState *env)
1236{
1237 /* L3CR */
1238 /* XXX : not implemented */
1239 spr_register(env, SPR_L3CR, "L3CR",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 &spr_read_generic, &spr_write_generic,
1242 0x00000000);
1243 /* L3ITCR0 */
578bb252 1244 /* XXX : not implemented */
a750fc0b
JM		 1245 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_generic, &spr_write_generic,
1248 0x00000000);
a750fc0b 1249 /* L3PM */
578bb252 1250 /* XXX : not implemented */
a750fc0b
JM		 1251 spr_register(env, SPR_L3PM, "L3PM",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1254 0x00000000);
1255}
a750fc0b 1256
578bb252 1257static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1258{
f2e63a42 1259#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1260 env->nb_tlb = nb_tlbs;
1261 env->nb_ways = nb_ways;
1262 env->id_tlbs = 1;
1263 /* XXX : not implemented */
a750fc0b
JM		 1264 spr_register(env, SPR_PTEHI, "PTEHI",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
578bb252 1268 /* XXX : not implemented */
a750fc0b
JM		 1269 spr_register(env, SPR_PTELO, "PTELO",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
578bb252 1273 /* XXX : not implemented */
a750fc0b
JM		 1274 spr_register(env, SPR_TLBMISS, "TLBMISS",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
f2e63a42 1278#endif
76a66253
JM		 1279}
1280
80d11f44 1281static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1282{
80d11f44
JM		 1283 spr_register(env, SPR_USPRG4, "USPRG4",
1284 &spr_read_ureg, SPR_NOACCESS,
1285 &spr_read_ureg, SPR_NOACCESS,
1286 0x00000000);
1287 spr_register(env, SPR_USPRG5, "USPRG5",
1288 &spr_read_ureg, SPR_NOACCESS,
1289 &spr_read_ureg, SPR_NOACCESS,
1290 0x00000000);
1291 spr_register(env, SPR_USPRG6, "USPRG6",
1292 &spr_read_ureg, SPR_NOACCESS,
1293 &spr_read_ureg, SPR_NOACCESS,
1294 0x00000000);
1295 spr_register(env, SPR_USPRG7, "USPRG7",
1296 &spr_read_ureg, SPR_NOACCESS,
1297 &spr_read_ureg, SPR_NOACCESS,
76a66253 1298 0x00000000);
80d11f44
JM		 1299}
1300
1301/* PowerPC BookE SPR */
1302static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1303{
b55266b5 1304 const char *ivor_names[64] = {
80d11f44
JM		 1305 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1306 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1307 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1308 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1309 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1310 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1311 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1312 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1313 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1314 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1315 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1316 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1317 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1318 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1319 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1320 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1321 };
1322#define SPR_BOOKE_IVORxx (-1)
1323 int ivor_sprn[64] = {
1324 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1325 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1326 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1327 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1328 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1329 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1330 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1331 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1332 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1333 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1334 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1335 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1336 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1337 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1338 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1339 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1340 };
1341 int i;
1342
76a66253 1343 /* Interrupt processing */
363be49c 1344 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
363be49c
JM		 1348 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
76a66253
JM		 1352 /* Debug */
1353 /* XXX : not implemented */
1354 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 /* XXX : not implemented */
1359 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363 /* XXX : not implemented */
76a66253
JM		 1364 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368 /* XXX : not implemented */
1369 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_generic,
1372 0x00000000);
1373 /* XXX : not implemented */
76a66253
JM		 1374 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
1378 /* XXX : not implemented */
1379 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383 /* XXX : not implemented */
1384 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388 /* XXX : not implemented */
1389 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1390 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1391 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1392 0x00000000);
1393 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_generic,
1396 0x00000000);
1397 spr_register(env, SPR_BOOKE_ESR, "ESR",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
363be49c
JM		 1401 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1402 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1403 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1404 0x00000000);
1405 /* Exception vectors */
80d11f44
JM		 1406 for (i = 0; i < 64; i++) {
1407 if (ivor_mask & (1ULL << i)) {
1408 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1409 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1410 exit(1);
1411 }
1412 spr_register(env, ivor_sprn[i], ivor_names[i],
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_excp_vector,
1415 0x00000000);
1416 }
1417 }
76a66253
JM		 1418 spr_register(env, SPR_BOOKE_PID, "PID",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_generic,
1421 0x00000000);
1422 spr_register(env, SPR_BOOKE_TCR, "TCR",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, &spr_write_booke_tcr,
1425 0x00000000);
1426 spr_register(env, SPR_BOOKE_TSR, "TSR",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_generic, &spr_write_booke_tsr,
1429 0x00000000);
1430 /* Timer */
1431 spr_register(env, SPR_DECR, "DECR",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_decr, &spr_write_decr,
1434 0x00000000);
1435 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1436 SPR_NOACCESS, SPR_NOACCESS,
1437 SPR_NOACCESS, &spr_write_generic,
1438 0x00000000);
1439 /* SPRGs */
1440 spr_register(env, SPR_USPRG0, "USPRG0",
1441 &spr_read_generic, &spr_write_generic,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
1444 spr_register(env, SPR_SPRG4, "SPRG4",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
76a66253
JM		 1448 spr_register(env, SPR_SPRG5, "SPRG5",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
76a66253
JM		 1452 spr_register(env, SPR_SPRG6, "SPRG6",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
76a66253
JM		 1456 spr_register(env, SPR_SPRG7, "SPRG7",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_generic,
1459 0x00000000);
76a66253
JM		 1460}
1461
363be49c 1462/* FSL storage control registers */
80d11f44 1463static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
363be49c 1464{
f2e63a42 1465#if !defined(CONFIG_USER_ONLY)
b55266b5 1466 const char *mas_names[8] = {
80d11f44
JM		 1467 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1468 };
1469 int mas_sprn[8] = {
1470 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1471 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1472 };
1473 int i;
1474
363be49c 1475 /* TLB assist registers */
578bb252 1476 /* XXX : not implemented */
80d11f44
JM		 1477 for (i = 0; i < 8; i++) {
1478 if (mas_mask & (1 << i)) {
1479 spr_register(env, mas_sprn[i], mas_names[i],
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 }
1484 }
363be49c 1485 if (env->nb_pids > 1) {
578bb252 1486 /* XXX : not implemented */
363be49c
JM		 1487 spr_register(env, SPR_BOOKE_PID1, "PID1",
1488 SPR_NOACCESS, SPR_NOACCESS,
1489 &spr_read_generic, &spr_write_generic,
1490 0x00000000);
1491 }
1492 if (env->nb_pids > 2) {
578bb252 1493 /* XXX : not implemented */
363be49c
JM		 1494 spr_register(env, SPR_BOOKE_PID2, "PID2",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 }
578bb252 1499 /* XXX : not implemented */
65f9ee8d 1500 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, SPR_NOACCESS,
1503 0x00000000); /* TOFIX */
578bb252 1504 /* XXX : not implemented */
65f9ee8d 1505 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000); /* TOFIX */
1509 switch (env->nb_ways) {
1510 case 4:
578bb252 1511 /* XXX : not implemented */
363be49c
JM		 1512 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, SPR_NOACCESS,
1515 0x00000000); /* TOFIX */
1516 /* Fallthru */
1517 case 3:
578bb252 1518 /* XXX : not implemented */
363be49c
JM		 1519 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, SPR_NOACCESS,
1522 0x00000000); /* TOFIX */
1523 /* Fallthru */
1524 case 2:
578bb252 1525 /* XXX : not implemented */
363be49c
JM		 1526 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, SPR_NOACCESS,
1529 0x00000000); /* TOFIX */
1530 /* Fallthru */
1531 case 1:
578bb252 1532 /* XXX : not implemented */
363be49c
JM		 1533 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, SPR_NOACCESS,
1536 0x00000000); /* TOFIX */
1537 /* Fallthru */
1538 case 0:
1539 default:
1540 break;
1541 }
f2e63a42 1542#endif
363be49c
JM		 1543}
1544
76a66253
JM		 1545/* SPR specific to PowerPC 440 implementation */
1546static void gen_spr_440 (CPUPPCState *env)
1547{
1548 /* Cache control */
1549 /* XXX : not implemented */
1550 spr_register(env, SPR_440_DNV0, "DNV0",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554 /* XXX : not implemented */
1555 spr_register(env, SPR_440_DNV1, "DNV1",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, &spr_write_generic,
1558 0x00000000);
1559 /* XXX : not implemented */
1560 spr_register(env, SPR_440_DNV2, "DNV2",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 /* XXX : not implemented */
1565 spr_register(env, SPR_440_DNV3, "DNV3",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 /* XXX : not implemented */
2662a059 1570 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574 /* XXX : not implemented */
2662a059 1575 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_generic,
1578 0x00000000);
1579 /* XXX : not implemented */
2662a059 1580 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00000000);
1584 /* XXX : not implemented */
2662a059 1585 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_generic,
1588 0x00000000);
1589 /* XXX : not implemented */
1590 spr_register(env, SPR_440_DVLIM, "DVLIM",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, &spr_write_generic,
1593 0x00000000);
1594 /* XXX : not implemented */
1595 spr_register(env, SPR_440_INV0, "INV0",
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_generic,
1598 0x00000000);
1599 /* XXX : not implemented */
1600 spr_register(env, SPR_440_INV1, "INV1",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_generic,
1603 0x00000000);
1604 /* XXX : not implemented */
1605 spr_register(env, SPR_440_INV2, "INV2",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, &spr_write_generic,
1608 0x00000000);
1609 /* XXX : not implemented */
1610 spr_register(env, SPR_440_INV3, "INV3",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_generic,
1613 0x00000000);
1614 /* XXX : not implemented */
2662a059 1615 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_generic,
1618 0x00000000);
1619 /* XXX : not implemented */
2662a059 1620 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, &spr_write_generic,
1623 0x00000000);
1624 /* XXX : not implemented */
2662a059 1625 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_generic,
1628 0x00000000);
1629 /* XXX : not implemented */
2662a059 1630 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 /* XXX : not implemented */
1635 spr_register(env, SPR_440_IVLIM, "IVLIM",
1636 SPR_NOACCESS, SPR_NOACCESS,
1637 &spr_read_generic, &spr_write_generic,
1638 0x00000000);
1639 /* Cache debug */
1640 /* XXX : not implemented */
2662a059 1641 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1642 SPR_NOACCESS, SPR_NOACCESS,
1643 &spr_read_generic, SPR_NOACCESS,
1644 0x00000000);
1645 /* XXX : not implemented */
2662a059 1646 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, SPR_NOACCESS,
1649 0x00000000);
1650 /* XXX : not implemented */
2662a059 1651 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, SPR_NOACCESS,
1654 0x00000000);
1655 /* XXX : not implemented */
2662a059 1656 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, SPR_NOACCESS,
1659 0x00000000);
1660 /* XXX : not implemented */
2662a059 1661 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1662 SPR_NOACCESS, SPR_NOACCESS,
1663 &spr_read_generic, SPR_NOACCESS,
1664 0x00000000);
1665 /* XXX : not implemented */
1666 spr_register(env, SPR_440_DBDR, "DBDR",
1667 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, &spr_write_generic,
1669 0x00000000);
1670 /* Processor control */
1671 spr_register(env, SPR_4xx_CCR0, "CCR0",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_generic,
1674 0x00000000);
1675 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, SPR_NOACCESS,
1678 0x00000000);
1679 /* Storage control */
1680 spr_register(env, SPR_440_MMUCR, "MMUCR",
1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, &spr_write_generic,
1683 0x00000000);
1684}
1685
1686/* SPR shared between PowerPC 40x implementations */
1687static void gen_spr_40x (CPUPPCState *env)
1688{
1689 /* Cache */
035feb88 1690 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1691 spr_register(env, SPR_40x_DCCR, "DCCR",
1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
035feb88 1695 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1696 spr_register(env, SPR_40x_ICCR, "ICCR",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
578bb252 1700 /* not emulated, as Qemu do not emulate caches */
2662a059 1701 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, SPR_NOACCESS,
1704 0x00000000);
76a66253
JM		 1705 /* Exception */
1706 spr_register(env, SPR_40x_DEAR, "DEAR",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 spr_register(env, SPR_40x_ESR, "ESR",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
1714 spr_register(env, SPR_40x_EVPR, "EVPR",
1715 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1716 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1717 0x00000000);
1718 spr_register(env, SPR_40x_SRR2, "SRR2",
1719 &spr_read_generic, &spr_write_generic,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 spr_register(env, SPR_40x_SRR3, "SRR3",
1723 &spr_read_generic, &spr_write_generic,
1724 &spr_read_generic, &spr_write_generic,
1725 0x00000000);
1726 /* Timers */
1727 spr_register(env, SPR_40x_PIT, "PIT",
1728 SPR_NOACCESS, SPR_NOACCESS,
1729 &spr_read_40x_pit, &spr_write_40x_pit,
1730 0x00000000);
1731 spr_register(env, SPR_40x_TCR, "TCR",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_booke_tcr,
1734 0x00000000);
1735 spr_register(env, SPR_40x_TSR, "TSR",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_generic, &spr_write_booke_tsr,
1738 0x00000000);
2662a059
JM		 1739}
1740
1741/* SPR specific to PowerPC 405 implementation */
1742static void gen_spr_405 (CPUPPCState *env)
1743{
1744 /* MMU */
1745 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
1748 0x00000000);
2662a059 1749 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1752 0x00700000);
1753 /* Debug interface */
76a66253
JM		 1754 /* XXX : not implemented */
1755 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1756 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1757 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1758 0x00000000);
1759 /* XXX : not implemented */
2662a059
JM		 1760 spr_register(env, SPR_405_DBCR1, "DBCR1",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, &spr_write_generic,
1763 0x00000000);
1764 /* XXX : not implemented */
76a66253
JM		 1765 spr_register(env, SPR_40x_DBSR, "DBSR",
1766 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1767 &spr_read_generic, &spr_write_clear,
1768 /* Last reset was system reset */
76a66253
JM		 1769 0x00000300);
1770 /* XXX : not implemented */
2662a059 1771 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1772 SPR_NOACCESS, SPR_NOACCESS,
1773 &spr_read_generic, &spr_write_generic,
1774 0x00000000);
2662a059 1775 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
2662a059
JM		 1779 /* XXX : not implemented */
1780 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
2662a059 1783 0x00000000);
76a66253 1784 /* XXX : not implemented */
2662a059 1785 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_generic,
1788 0x00000000);
1789 /* XXX : not implemented */
2662a059 1790 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
2662a059 1794 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, &spr_write_generic,
1797 0x00000000);
1798 /* XXX : not implemented */
1799 spr_register(env, SPR_405_IAC3, "IAC3",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* XXX : not implemented */
1804 spr_register(env, SPR_405_IAC4, "IAC4",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 /* Storage control */
035feb88 1809 /* XXX: TODO: not implemented */
76a66253
JM		 1810 spr_register(env, SPR_405_SLER, "SLER",
1811 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1812 &spr_read_generic, &spr_write_40x_sler,
76a66253 1813 0x00000000);
2662a059
JM		 1814 spr_register(env, SPR_40x_ZPR, "ZPR",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
76a66253
JM		 1818 /* XXX : not implemented */
1819 spr_register(env, SPR_405_SU0R, "SU0R",
1820 SPR_NOACCESS, SPR_NOACCESS,
1821 &spr_read_generic, &spr_write_generic,
1822 0x00000000);
1823 /* SPRG */
1824 spr_register(env, SPR_USPRG0, "USPRG0",
1825 &spr_read_ureg, SPR_NOACCESS,
1826 &spr_read_ureg, SPR_NOACCESS,
1827 0x00000000);
1828 spr_register(env, SPR_SPRG4, "SPRG4",
1829 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1830 &spr_read_generic, &spr_write_generic,
76a66253 1831 0x00000000);
76a66253
JM		 1832 spr_register(env, SPR_SPRG5, "SPRG5",
1833 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1834 spr_read_generic, &spr_write_generic,
76a66253 1835 0x00000000);
76a66253
JM		 1836 spr_register(env, SPR_SPRG6, "SPRG6",
1837 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1838 spr_read_generic, &spr_write_generic,
76a66253 1839 0x00000000);
76a66253
JM		 1840 spr_register(env, SPR_SPRG7, "SPRG7",
1841 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1842 spr_read_generic, &spr_write_generic,
76a66253 1843 0x00000000);
80d11f44 1844 gen_spr_usprgh(env);
76a66253
JM		 1845}
1846
1847/* SPR shared between PowerPC 401 & 403 implementations */
1848static void gen_spr_401_403 (CPUPPCState *env)
1849{
1850 /* Time base */
1851 spr_register(env, SPR_403_VTBL, "TBL",
1852 &spr_read_tbl, SPR_NOACCESS,
1853 &spr_read_tbl, SPR_NOACCESS,
1854 0x00000000);
1855 spr_register(env, SPR_403_TBL, "TBL",
1856 SPR_NOACCESS, SPR_NOACCESS,
1857 SPR_NOACCESS, &spr_write_tbl,
1858 0x00000000);
1859 spr_register(env, SPR_403_VTBU, "TBU",
1860 &spr_read_tbu, SPR_NOACCESS,
1861 &spr_read_tbu, SPR_NOACCESS,
1862 0x00000000);
1863 spr_register(env, SPR_403_TBU, "TBU",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 SPR_NOACCESS, &spr_write_tbu,
1866 0x00000000);
1867 /* Debug */
578bb252 1868 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1869 spr_register(env, SPR_403_CDBCR, "CDBCR",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873}
1874
2662a059
JM		 1875/* SPR specific to PowerPC 401 implementation */
1876static void gen_spr_401 (CPUPPCState *env)
1877{
1878 /* Debug interface */
1879 /* XXX : not implemented */
1880 spr_register(env, SPR_40x_DBCR0, "DBCR",
1881 SPR_NOACCESS, SPR_NOACCESS,
1882 &spr_read_generic, &spr_write_40x_dbcr0,
1883 0x00000000);
1884 /* XXX : not implemented */
1885 spr_register(env, SPR_40x_DBSR, "DBSR",
1886 SPR_NOACCESS, SPR_NOACCESS,
1887 &spr_read_generic, &spr_write_clear,
1888 /* Last reset was system reset */
1889 0x00000300);
1890 /* XXX : not implemented */
1891 spr_register(env, SPR_40x_DAC1, "DAC",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 /* XXX : not implemented */
1896 spr_register(env, SPR_40x_IAC1, "IAC",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900 /* Storage control */
035feb88 1901 /* XXX: TODO: not implemented */
2662a059
JM		 1902 spr_register(env, SPR_405_SLER, "SLER",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_40x_sler,
1905 0x00000000);
035feb88
JM		 1906 /* not emulated, as Qemu never does speculative access */
1907 spr_register(env, SPR_40x_SGR, "SGR",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0xFFFFFFFF);
1911 /* not emulated, as Qemu do not emulate caches */
1912 spr_register(env, SPR_40x_DCWR, "DCWR",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_generic,
1915 0x00000000);
2662a059
JM		 1916}
1917
a750fc0b
JM		 1918static void gen_spr_401x2 (CPUPPCState *env)
1919{
1920 gen_spr_401(env);
1921 spr_register(env, SPR_40x_PID, "PID",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925 spr_register(env, SPR_40x_ZPR, "ZPR",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929}
1930
76a66253
JM		 1931/* SPR specific to PowerPC 403 implementation */
1932static void gen_spr_403 (CPUPPCState *env)
1933{
2662a059
JM		 1934 /* Debug interface */
1935 /* XXX : not implemented */
1936 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1937 SPR_NOACCESS, SPR_NOACCESS,
1938 &spr_read_generic, &spr_write_40x_dbcr0,
1939 0x00000000);
1940 /* XXX : not implemented */
1941 spr_register(env, SPR_40x_DBSR, "DBSR",
1942 SPR_NOACCESS, SPR_NOACCESS,
1943 &spr_read_generic, &spr_write_clear,
1944 /* Last reset was system reset */
1945 0x00000300);
1946 /* XXX : not implemented */
1947 spr_register(env, SPR_40x_DAC1, "DAC1",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00000000);
578bb252 1951 /* XXX : not implemented */
2662a059
JM		 1952 spr_register(env, SPR_40x_DAC2, "DAC2",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
1956 /* XXX : not implemented */
1957 spr_register(env, SPR_40x_IAC1, "IAC1",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 &spr_read_generic, &spr_write_generic,
1960 0x00000000);
578bb252 1961 /* XXX : not implemented */
2662a059
JM		 1962 spr_register(env, SPR_40x_IAC2, "IAC2",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
a750fc0b
JM		 1966}
1967
1968static void gen_spr_403_real (CPUPPCState *env)
1969{
76a66253
JM		 1970 spr_register(env, SPR_403_PBL1, "PBL1",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_403_pbr, &spr_write_403_pbr,
1973 0x00000000);
1974 spr_register(env, SPR_403_PBU1, "PBU1",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_403_pbr, &spr_write_403_pbr,
1977 0x00000000);
1978 spr_register(env, SPR_403_PBL2, "PBL2",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_403_pbr, &spr_write_403_pbr,
1981 0x00000000);
1982 spr_register(env, SPR_403_PBU2, "PBU2",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_403_pbr, &spr_write_403_pbr,
1985 0x00000000);
a750fc0b
JM		 1986}
1987
1988static void gen_spr_403_mmu (CPUPPCState *env)
1989{
1990 /* MMU */
1991 spr_register(env, SPR_40x_PID, "PID",
1992 SPR_NOACCESS, SPR_NOACCESS,
1993 &spr_read_generic, &spr_write_generic,
1994 0x00000000);
2662a059 1995 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_generic,
1998 0x00000000);
1999}
2000
2001/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2002static void gen_spr_compress (CPUPPCState *env)
2003{
578bb252 2004 /* XXX : not implemented */
76a66253
JM		 2005 spr_register(env, SPR_401_SKR, "SKR",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009}
a750fc0b
JM		 2010
2011#if defined (TARGET_PPC64)
a750fc0b
JM		 2012/* SPR specific to PowerPC 620 */
2013static void gen_spr_620 (CPUPPCState *env)
2014{
082c6681
JM		 2015 /* Processor identification */
2016 spr_register(env, SPR_PIR, "PIR",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, &spr_write_pir,
2019 0x00000000);
2020 spr_register(env, SPR_ASR, "ASR",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_asr, &spr_write_asr,
2023 0x00000000);
2024 /* Breakpoints */
2025 /* XXX : not implemented */
2026 spr_register(env, SPR_IABR, "IABR",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
2030 /* XXX : not implemented */
2031 spr_register(env, SPR_DABR, "DABR",
2032 SPR_NOACCESS, SPR_NOACCESS,
2033 &spr_read_generic, &spr_write_generic,
2034 0x00000000);
2035 /* XXX : not implemented */
2036 spr_register(env, SPR_SIAR, "SIAR",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, SPR_NOACCESS,
2039 0x00000000);
2040 /* XXX : not implemented */
2041 spr_register(env, SPR_SDA, "SDA",
2042 SPR_NOACCESS, SPR_NOACCESS,
2043 &spr_read_generic, SPR_NOACCESS,
2044 0x00000000);
2045 /* XXX : not implemented */
2046 spr_register(env, SPR_620_PMC1R, "PMC1",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 &spr_read_generic, SPR_NOACCESS,
2049 0x00000000);
2050 spr_register(env, SPR_620_PMC1W, "PMC1",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 SPR_NOACCESS, &spr_write_generic,
2053 0x00000000);
2054 /* XXX : not implemented */
2055 spr_register(env, SPR_620_PMC2R, "PMC2",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, SPR_NOACCESS,
2058 0x00000000);
2059 spr_register(env, SPR_620_PMC2W, "PMC2",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 SPR_NOACCESS, &spr_write_generic,
2062 0x00000000);
2063 /* XXX : not implemented */
2064 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, SPR_NOACCESS,
2067 0x00000000);
2068 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 SPR_NOACCESS, &spr_write_generic,
2071 0x00000000);
2072 /* External access control */
2073 /* XXX : not implemented */
2074 spr_register(env, SPR_EAR, "EAR",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_generic,
2077 0x00000000);
2078#if 0 // XXX: check this
578bb252 2079 /* XXX : not implemented */
a750fc0b
JM		 2080 spr_register(env, SPR_620_PMR0, "PMR0",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
578bb252 2084 /* XXX : not implemented */
a750fc0b
JM		 2085 spr_register(env, SPR_620_PMR1, "PMR1",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
578bb252 2089 /* XXX : not implemented */
a750fc0b
JM		 2090 spr_register(env, SPR_620_PMR2, "PMR2",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_generic, &spr_write_generic,
2093 0x00000000);
578bb252 2094 /* XXX : not implemented */
a750fc0b
JM		 2095 spr_register(env, SPR_620_PMR3, "PMR3",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
578bb252 2099 /* XXX : not implemented */
a750fc0b
JM		 2100 spr_register(env, SPR_620_PMR4, "PMR4",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
578bb252 2104 /* XXX : not implemented */
a750fc0b
JM		 2105 spr_register(env, SPR_620_PMR5, "PMR5",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0x00000000);
578bb252 2109 /* XXX : not implemented */
a750fc0b
JM		 2110 spr_register(env, SPR_620_PMR6, "PMR6",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
578bb252 2114 /* XXX : not implemented */
a750fc0b
JM		 2115 spr_register(env, SPR_620_PMR7, "PMR7",
2116 SPR_NOACCESS, SPR_NOACCESS,
2117 &spr_read_generic, &spr_write_generic,
2118 0x00000000);
578bb252 2119 /* XXX : not implemented */
a750fc0b
JM		 2120 spr_register(env, SPR_620_PMR8, "PMR8",
2121 SPR_NOACCESS, SPR_NOACCESS,
2122 &spr_read_generic, &spr_write_generic,
2123 0x00000000);
578bb252 2124 /* XXX : not implemented */
a750fc0b
JM		 2125 spr_register(env, SPR_620_PMR9, "PMR9",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_generic,
2128 0x00000000);
578bb252 2129 /* XXX : not implemented */
a750fc0b
JM		 2130 spr_register(env, SPR_620_PMRA, "PMR10",
2131 SPR_NOACCESS, SPR_NOACCESS,
2132 &spr_read_generic, &spr_write_generic,
2133 0x00000000);
578bb252 2134 /* XXX : not implemented */
a750fc0b
JM		 2135 spr_register(env, SPR_620_PMRB, "PMR11",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, &spr_write_generic,
2138 0x00000000);
578bb252 2139 /* XXX : not implemented */
a750fc0b
JM		 2140 spr_register(env, SPR_620_PMRC, "PMR12",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
578bb252 2144 /* XXX : not implemented */
a750fc0b
JM		 2145 spr_register(env, SPR_620_PMRD, "PMR13",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
578bb252 2149 /* XXX : not implemented */
a750fc0b
JM		 2150 spr_register(env, SPR_620_PMRE, "PMR14",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_generic,
2153 0x00000000);
578bb252 2154 /* XXX : not implemented */
a750fc0b
JM		 2155 spr_register(env, SPR_620_PMRF, "PMR15",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_generic,
2158 0x00000000);
082c6681 2159#endif
578bb252 2160 /* XXX : not implemented */
082c6681 2161 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2162 SPR_NOACCESS, SPR_NOACCESS,
2163 &spr_read_generic, &spr_write_generic,
2164 0x00000000);
578bb252 2165 /* XXX : not implemented */
082c6681
JM		 2166 spr_register(env, SPR_620_L2CR, "L2CR",
2167 SPR_NOACCESS, SPR_NOACCESS,
2168 &spr_read_generic, &spr_write_generic,
2169 0x00000000);
2170 /* XXX : not implemented */
2171 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175}
a750fc0b 2176#endif /* defined (TARGET_PPC64) */
76a66253 2177
80d11f44 2178static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2179{
80d11f44
JM		 2180 /* Exception processing */
2181 spr_register(env, SPR_DSISR, "DSISR",
2182 SPR_NOACCESS, SPR_NOACCESS,
2183 &spr_read_generic, &spr_write_generic,
2184 0x00000000);
2185 spr_register(env, SPR_DAR, "DAR",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, &spr_write_generic,
2188 0x00000000);
2189 /* Timer */
2190 spr_register(env, SPR_DECR, "DECR",
2191 SPR_NOACCESS, SPR_NOACCESS,
2192 &spr_read_decr, &spr_write_decr,
2193 0x00000000);
2194 /* XXX : not implemented */
2195 spr_register(env, SPR_MPC_EIE, "EIE",
2196 SPR_NOACCESS, SPR_NOACCESS,
2197 &spr_read_generic, &spr_write_generic,
2198 0x00000000);
2199 /* XXX : not implemented */
2200 spr_register(env, SPR_MPC_EID, "EID",
2201 SPR_NOACCESS, SPR_NOACCESS,
2202 &spr_read_generic, &spr_write_generic,
2203 0x00000000);
2204 /* XXX : not implemented */
2205 spr_register(env, SPR_MPC_NRI, "NRI",
2206 SPR_NOACCESS, SPR_NOACCESS,
2207 &spr_read_generic, &spr_write_generic,
2208 0x00000000);
2209 /* XXX : not implemented */
2210 spr_register(env, SPR_MPC_CMPA, "CMPA",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_generic,
2213 0x00000000);
2214 /* XXX : not implemented */
2215 spr_register(env, SPR_MPC_CMPB, "CMPB",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0x00000000);
2219 /* XXX : not implemented */
2220 spr_register(env, SPR_MPC_CMPC, "CMPC",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 /* XXX : not implemented */
2225 spr_register(env, SPR_MPC_CMPD, "CMPD",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 0x00000000);
2229 /* XXX : not implemented */
2230 spr_register(env, SPR_MPC_ECR, "ECR",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_MPC_DER, "DER",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_MPC_CMPE, "CMPE",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_MPC_CMPF, "CMPF",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_MPC_CMPG, "CMPG",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_MPC_CMPH, "CMPH",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_MPC_BAR, "BAR",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_MPC_DPDR, "DPDR",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_MPC_IMMR, "IMMR",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294}
2295
2296static void gen_spr_5xx (CPUPPCState *env)
2297{
2298 /* XXX : not implemented */
2299 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0x00000000);
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 /* XXX : not implemented */
2309 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2310 SPR_NOACCESS, SPR_NOACCESS,
2311 &spr_read_generic, &spr_write_generic,
2312 0x00000000);
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* XXX : not implemented */
2324 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403}
2404
2405static void gen_spr_8xx (CPUPPCState *env)
2406{
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532}
2533
2534// XXX: TODO
2535/*
2536 * AMR => SPR 29 (Power 2.04)
2537 * CTRL => SPR 136 (Power 2.04)
2538 * CTRL => SPR 152 (Power 2.04)
2539 * SCOMC => SPR 276 (64 bits ?)
2540 * SCOMD => SPR 277 (64 bits ?)
2541 * TBU40 => SPR 286 (Power 2.04 hypv)
2542 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2543 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2544 * HDSISR => SPR 306 (Power 2.04 hypv)
2545 * HDAR => SPR 307 (Power 2.04 hypv)
2546 * PURR => SPR 309 (Power 2.04 hypv)
2547 * HDEC => SPR 310 (Power 2.04 hypv)
2548 * HIOR => SPR 311 (hypv)
2549 * RMOR => SPR 312 (970)
2550 * HRMOR => SPR 313 (Power 2.04 hypv)
2551 * HSRR0 => SPR 314 (Power 2.04 hypv)
2552 * HSRR1 => SPR 315 (Power 2.04 hypv)
2553 * LPCR => SPR 316 (970)
2554 * LPIDR => SPR 317 (970)
2555 * SPEFSCR => SPR 512 (Power 2.04 emb)
2556 * EPR => SPR 702 (Power 2.04 emb)
2557 * perf => 768-783 (Power 2.04)
2558 * perf => 784-799 (Power 2.04)
2559 * PPR => SPR 896 (Power 2.04)
2560 * EPLC => SPR 947 (Power 2.04 emb)
2561 * EPSC => SPR 948 (Power 2.04 emb)
2562 * DABRX => 1015 (Power 2.04 hypv)
2563 * FPECR => SPR 1022 (?)
2564 * ... and more (thermal management, performance counters, ...)
2565 */
2566
2567/*****************************************************************************/
2568/* Exception vectors models */
2569static void init_excp_4xx_real (CPUPPCState *env)
2570{
2571#if !defined(CONFIG_USER_ONLY)
2572 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2573 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2574 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2575 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2576 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2577 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2578 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2579 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2580 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2581 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
faadf50e 2582 env->excp_prefix = 0x00000000UL;
80d11f44 2583 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2584 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2585 /* Hardware reset vector */
2586 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2587#endif
2588}
2589
80d11f44
JM		 2590static void init_excp_4xx_softmmu (CPUPPCState *env)
2591{
2592#if !defined(CONFIG_USER_ONLY)
2593 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2594 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2595 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2596 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2597 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2598 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2599 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2600 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2601 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2602 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2603 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2604 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2605 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2606 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2607 env->excp_prefix = 0x00000000UL;
2608 env->ivor_mask = 0x0000FFF0UL;
2609 env->ivpr_mask = 0xFFFF0000UL;
2610 /* Hardware reset vector */
2611 env->hreset_vector = 0xFFFFFFFCUL;
2612#endif
2613}
2614
2615static void init_excp_MPC5xx (CPUPPCState *env)
2616{
2617#if !defined(CONFIG_USER_ONLY)
2618 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2619 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2620 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2621 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2622 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2623 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2624 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2625 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2626 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2627 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2628 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2629 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2630 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2631 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2632 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2633 env->excp_prefix = 0x00000000UL;
2634 env->ivor_mask = 0x0000FFF0UL;
2635 env->ivpr_mask = 0xFFFF0000UL;
2636 /* Hardware reset vector */
2637 env->hreset_vector = 0xFFFFFFFCUL;
2638#endif
2639}
2640
2641static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2642{
2643#if !defined(CONFIG_USER_ONLY)
2644 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2645 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2646 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2647 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2648 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2649 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2650 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2651 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2652 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2653 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2654 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2655 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2656 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2657 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2658 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2659 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2660 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2661 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2662 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2663 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2664 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2665 env->excp_prefix = 0x00000000UL;
2666 env->ivor_mask = 0x0000FFF0UL;
2667 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2668 /* Hardware reset vector */
80d11f44 2669 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2670#endif
2671}
2672
80d11f44 2673static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2674{
2675#if !defined(CONFIG_USER_ONLY)
2676 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2677 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2678 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2679 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2680 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2681 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2682 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2683 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2684 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2685 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2686 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2687 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2688 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2689 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2690 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2691 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2692 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2693 env->excp_prefix = 0x00000000UL;
2694 /* Hardware reset vector */
2695 env->hreset_vector = 0xFFFFFFFCUL;
2696#endif
2697}
2698
2699static void init_excp_e200 (CPUPPCState *env)
2700{
2701#if !defined(CONFIG_USER_ONLY)
2702 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2703 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2704 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2705 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2706 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2707 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2708 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2709 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2710 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2711 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2712 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2713 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2714 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2715 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2716 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2717 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2718 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2719 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2720 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2721 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2722 env->excp_prefix = 0x00000000UL;
2723 env->ivor_mask = 0x0000FFF7UL;
2724 env->ivpr_mask = 0xFFFF0000UL;
2725 /* Hardware reset vector */
2726 env->hreset_vector = 0xFFFFFFFCUL;
2727#endif
2728}
2729
2730static void init_excp_BookE (CPUPPCState *env)
2731{
2732#if !defined(CONFIG_USER_ONLY)
2733 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2736 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2738 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2739 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2740 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2741 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2746 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2749 env->excp_prefix = 0x00000000UL;
2750 env->ivor_mask = 0x0000FFE0UL;
2751 env->ivpr_mask = 0xFFFF0000UL;
2752 /* Hardware reset vector */
2753 env->hreset_vector = 0xFFFFFFFCUL;
2754#endif
2755}
2756
2757static void init_excp_601 (CPUPPCState *env)
2758{
2759#if !defined(CONFIG_USER_ONLY)
2760 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2761 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2762 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2763 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2764 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2765 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2766 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2767 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2768 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2769 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2770 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2771 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
faadf50e 2772 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2773 /* Hardware reset vector */
80d11f44 2774 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2775#endif
2776}
2777
80d11f44 2778static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2779{
2780#if !defined(CONFIG_USER_ONLY)
082c6681 2781 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2782 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2783 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2784 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2785 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2786 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2787 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2788 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2789 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2790 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2791 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2792 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2793 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2794 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2795 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2796 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2797 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2798 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2799 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2800 env->excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2801 /* Hardware reset vector */
2802 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2803#endif
2804}
2805
80d11f44 2806static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2807{
2808#if !defined(CONFIG_USER_ONLY)
2809 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2810 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2811 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2812 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2813 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2814 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2815 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2816 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2817 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2818 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2819 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2820 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2821 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2822 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2823 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2824 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2825 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2826 /* Hardware reset vector */
2827 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2828#endif
2829}
2830
2831static void init_excp_604 (CPUPPCState *env)
2832{
2833#if !defined(CONFIG_USER_ONLY)
2834 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2835 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2836 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2837 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2838 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2839 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2840 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2841 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2842 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2843 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2844 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2845 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2846 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2847 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2848 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2849 /* Hardware reset vector */
2850 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2851#endif
2852}
2853
578bb252 2854#if defined(TARGET_PPC64)
e1833e1f
JM		 2855static void init_excp_620 (CPUPPCState *env)
2856{
2857#if !defined(CONFIG_USER_ONLY)
2858 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2859 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2860 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2861 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2862 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2863 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2864 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2865 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2866 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2867 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2868 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2869 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2870 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2871 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2872 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2873 /* Hardware reset vector */
faadf50e 2874 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2875#endif
2876}
578bb252 2877#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2878
2879static void init_excp_7x0 (CPUPPCState *env)
2880{
2881#if !defined(CONFIG_USER_ONLY)
2882 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2883 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2884 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2885 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2886 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2887 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2888 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2889 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2890 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2891 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2892 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2893 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2894 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 2895 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 2896 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2897 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2898 /* Hardware reset vector */
2899 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2900#endif
2901}
2902
bd928eba 2903static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 2904{
2905#if !defined(CONFIG_USER_ONLY)
2906 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2907 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2908 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2909 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2910 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2911 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2912 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2913 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2914 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2915 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2916 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2917 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2918 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2919 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba
JM		 2920 env->excp_prefix = 0x00000000UL;
2921 /* Hardware reset vector */
2922 env->hreset_vector = 0xFFFFFFFCUL;
2923#endif
2924}
2925
2926static void init_excp_750cx (CPUPPCState *env)
2927{
2928#if !defined(CONFIG_USER_ONLY)
2929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2940 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2941 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 2942 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2943 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2944 /* Hardware reset vector */
2945 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2946#endif
2947}
2948
7a3a6927
JM		 2949/* XXX: Check if this is correct */
2950static void init_excp_7x5 (CPUPPCState *env)
2951{
2952#if !defined(CONFIG_USER_ONLY)
2953 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2954 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2955 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2956 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2957 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2958 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2959 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2960 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2961 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2962 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2963 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 2964 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 2965 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2966 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2967 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 2968 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2969 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 2970 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2971 env->excp_prefix = 0x00000000UL;
7a3a6927
JM		 2972 /* Hardware reset vector */
2973 env->hreset_vector = 0xFFFFFFFCUL;
2974#endif
2975}
2976
e1833e1f
JM		 2977static void init_excp_7400 (CPUPPCState *env)
2978{
2979#if !defined(CONFIG_USER_ONLY)
2980 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2981 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2982 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2983 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2984 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2985 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2986 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2987 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2988 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2989 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2990 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2991 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2992 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2993 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2994 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2995 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2996 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2997 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2998 /* Hardware reset vector */
2999 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3000#endif
3001}
3002
e1833e1f
JM		 3003static void init_excp_7450 (CPUPPCState *env)
3004{
3005#if !defined(CONFIG_USER_ONLY)
3006 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3007 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3008 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3009 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3010 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3011 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3012 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3013 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3014 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3015 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3016 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3017 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3018 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3019 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3020 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3021 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3022 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3023 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3024 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
faadf50e 3025 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3026 /* Hardware reset vector */
3027 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3028#endif
3029}
e1833e1f
JM		 3030
3031#if defined (TARGET_PPC64)
3032static void init_excp_970 (CPUPPCState *env)
3033{
3034#if !defined(CONFIG_USER_ONLY)
3035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3038 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3040 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3046 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3047 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3048 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3049 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3050 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3051 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3052 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3053 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3054 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
faadf50e 3055 env->excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3056 /* Hardware reset vector */
3057 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3058#endif
3059}
3060#endif
3061
2f462816
JM		 3062/*****************************************************************************/
3063/* Power management enable checks */
3064static int check_pow_none (CPUPPCState *env)
3065{
3066 return 0;
3067}
3068
3069static int check_pow_nocheck (CPUPPCState *env)
3070{
3071 return 1;
3072}
3073
3074static int check_pow_hid0 (CPUPPCState *env)
3075{
3076 if (env->spr[SPR_HID0] & 0x00E00000)
3077 return 1;
3078
3079 return 0;
3080}
3081
4e777442
JM		 3082static int check_pow_hid0_74xx (CPUPPCState *env)
3083{
3084 if (env->spr[SPR_HID0] & 0x00600000)
3085 return 1;
3086
3087 return 0;
3088}
3089
a750fc0b
JM		 3090/*****************************************************************************/
3091/* PowerPC implementations definitions */
76a66253 3092
a750fc0b 3093/* PowerPC 401 */
082c6681
JM		 3094#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3095 PPC_WRTEE | PPC_DCR | \
3096 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3097 PPC_CACHE_DCBZ | \
a750fc0b 3098 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3099 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3100#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3101#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3102#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3103#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3104#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3105#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3106 POWERPC_FLAG_BUS_CLK)
2f462816 3107#define check_pow_401 check_pow_nocheck
76a66253 3108
a750fc0b
JM		 3109static void init_proc_401 (CPUPPCState *env)
3110{
3111 gen_spr_40x(env);
3112 gen_spr_401_403(env);
3113 gen_spr_401(env);
e1833e1f 3114 init_excp_4xx_real(env);
d63001d1
JM		 3115 env->dcache_line_size = 32;
3116 env->icache_line_size = 32;
4e290a0b
JM		 3117 /* Allocate hardware IRQ controller */
3118 ppc40x_irq_init(env);
a750fc0b 3119}
76a66253 3120
a750fc0b 3121/* PowerPC 401x2 */
082c6681
JM		 3122#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3123 PPC_DCR | PPC_WRTEE | \
3124 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3125 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3126 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3127 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3128 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3129#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3130#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3131#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3132#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3133#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3134#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3135 POWERPC_FLAG_BUS_CLK)
2f462816 3136#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3137
3138static void init_proc_401x2 (CPUPPCState *env)
3139{
3140 gen_spr_40x(env);
3141 gen_spr_401_403(env);
3142 gen_spr_401x2(env);
3143 gen_spr_compress(env);
a750fc0b 3144 /* Memory management */
f2e63a42 3145#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3146 env->nb_tlb = 64;
3147 env->nb_ways = 1;
3148 env->id_tlbs = 0;
f2e63a42 3149#endif
e1833e1f 3150 init_excp_4xx_softmmu(env);
d63001d1
JM		 3151 env->dcache_line_size = 32;
3152 env->icache_line_size = 32;
4e290a0b
JM		 3153 /* Allocate hardware IRQ controller */
3154 ppc40x_irq_init(env);
76a66253
JM		 3155}
3156
a750fc0b 3157/* PowerPC 401x3 */
082c6681
JM		 3158#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3159 PPC_DCR | PPC_WRTEE | \
3160 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3161 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3162 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3163 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3164 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3165#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3166#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3167#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3168#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3169#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3170#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3171 POWERPC_FLAG_BUS_CLK)
2f462816 3172#define check_pow_401x3 check_pow_nocheck
a750fc0b 3173
578bb252 3174__attribute__ (( unused ))
e1833e1f 3175static void init_proc_401x3 (CPUPPCState *env)
76a66253 3176{
4e290a0b
JM		 3177 gen_spr_40x(env);
3178 gen_spr_401_403(env);
3179 gen_spr_401(env);
3180 gen_spr_401x2(env);
3181 gen_spr_compress(env);
e1833e1f 3182 init_excp_4xx_softmmu(env);
d63001d1
JM		 3183 env->dcache_line_size = 32;
3184 env->icache_line_size = 32;
4e290a0b
JM		 3185 /* Allocate hardware IRQ controller */
3186 ppc40x_irq_init(env);
3fc6c082 3187}
a750fc0b
JM		 3188
3189/* IOP480 */
082c6681
JM		 3190#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3191 PPC_DCR | PPC_WRTEE | \
3192 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3193 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3194 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3195 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3196 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3197#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3198#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3199#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3200#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3201#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3202#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3203 POWERPC_FLAG_BUS_CLK)
2f462816 3204#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3205
3206static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3207{
a750fc0b
JM		 3208 gen_spr_40x(env);
3209 gen_spr_401_403(env);
3210 gen_spr_401x2(env);
3211 gen_spr_compress(env);
a750fc0b 3212 /* Memory management */
f2e63a42 3213#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3214 env->nb_tlb = 64;
3215 env->nb_ways = 1;
3216 env->id_tlbs = 0;
f2e63a42 3217#endif
e1833e1f 3218 init_excp_4xx_softmmu(env);
d63001d1
JM		 3219 env->dcache_line_size = 32;
3220 env->icache_line_size = 32;
4e290a0b
JM		 3221 /* Allocate hardware IRQ controller */
3222 ppc40x_irq_init(env);
3fc6c082
FB		 3223}
3224
a750fc0b 3225/* PowerPC 403 */
082c6681
JM		 3226#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3227 PPC_DCR | PPC_WRTEE | \
3228 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3229 PPC_CACHE_DCBZ | \
a750fc0b 3230 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3231 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3232#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3233#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3234#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3235#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3236#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3237#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3238 POWERPC_FLAG_BUS_CLK)
2f462816 3239#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3240
3241static void init_proc_403 (CPUPPCState *env)
3fc6c082 3242{
a750fc0b
JM		 3243 gen_spr_40x(env);
3244 gen_spr_401_403(env);
3245 gen_spr_403(env);
3246 gen_spr_403_real(env);
e1833e1f 3247 init_excp_4xx_real(env);
d63001d1
JM		 3248 env->dcache_line_size = 32;
3249 env->icache_line_size = 32;
4e290a0b
JM		 3250 /* Allocate hardware IRQ controller */
3251 ppc40x_irq_init(env);
3fc6c082
FB		 3252}
3253
a750fc0b 3254/* PowerPC 403 GCX */
082c6681
JM		 3255#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3256 PPC_DCR | PPC_WRTEE | \
3257 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3258 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3259 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3260 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3261 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3262#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3263#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3264#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3265#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3266#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3267#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3268 POWERPC_FLAG_BUS_CLK)
2f462816 3269#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3270
3271static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3272{
a750fc0b
JM		 3273 gen_spr_40x(env);
3274 gen_spr_401_403(env);
3275 gen_spr_403(env);
3276 gen_spr_403_real(env);
3277 gen_spr_403_mmu(env);
3278 /* Bus access control */
035feb88 3279 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3280 spr_register(env, SPR_40x_SGR, "SGR",
3281 SPR_NOACCESS, SPR_NOACCESS,
3282 &spr_read_generic, &spr_write_generic,
3283 0xFFFFFFFF);
035feb88 3284 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3285 spr_register(env, SPR_40x_DCWR, "DCWR",
3286 SPR_NOACCESS, SPR_NOACCESS,
3287 &spr_read_generic, &spr_write_generic,
3288 0x00000000);
3289 /* Memory management */
f2e63a42 3290#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3291 env->nb_tlb = 64;
3292 env->nb_ways = 1;
3293 env->id_tlbs = 0;
f2e63a42 3294#endif
80d11f44
JM		 3295 init_excp_4xx_softmmu(env);
3296 env->dcache_line_size = 32;
3297 env->icache_line_size = 32;
3298 /* Allocate hardware IRQ controller */
3299 ppc40x_irq_init(env);
3300}
3301
3302/* PowerPC 405 */
082c6681
JM		 3303#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3304 PPC_DCR | PPC_WRTEE | \
3305 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3306 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3307 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3308 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3309 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
80d11f44
JM		 3310#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3311#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3312#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3313#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3314#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3315#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3316 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3317#define check_pow_405 check_pow_nocheck
3318
3319static void init_proc_405 (CPUPPCState *env)
3320{
3321 /* Time base */
3322 gen_tbl(env);
3323 gen_spr_40x(env);
3324 gen_spr_405(env);
3325 /* Bus access control */
3326 /* not emulated, as Qemu never does speculative access */
3327 spr_register(env, SPR_40x_SGR, "SGR",
3328 SPR_NOACCESS, SPR_NOACCESS,
3329 &spr_read_generic, &spr_write_generic,
3330 0xFFFFFFFF);
3331 /* not emulated, as Qemu do not emulate caches */
3332 spr_register(env, SPR_40x_DCWR, "DCWR",
3333 SPR_NOACCESS, SPR_NOACCESS,
3334 &spr_read_generic, &spr_write_generic,
3335 0x00000000);
3336 /* Memory management */
3337#if !defined(CONFIG_USER_ONLY)
3338 env->nb_tlb = 64;
3339 env->nb_ways = 1;
3340 env->id_tlbs = 0;
3341#endif
3342 init_excp_4xx_softmmu(env);
3343 env->dcache_line_size = 32;
3344 env->icache_line_size = 32;
3345 /* Allocate hardware IRQ controller */
3346 ppc40x_irq_init(env);
3347}
3348
3349/* PowerPC 440 EP */
082c6681
JM		 3350#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3351 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3352 PPC_CACHE | PPC_CACHE_ICBI | \
3353 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3354 PPC_MEM_TLBSYNC | \
80d11f44 3355 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3356 PPC_440_SPEC)
80d11f44
JM		 3357#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3358#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3359#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3360#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3361#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3362#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3363 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3364#define check_pow_440EP check_pow_nocheck
3365
3366__attribute__ (( unused ))
3367static void init_proc_440EP (CPUPPCState *env)
3368{
3369 /* Time base */
3370 gen_tbl(env);
3371 gen_spr_BookE(env, 0x000000000000FFFFULL);
3372 gen_spr_440(env);
3373 gen_spr_usprgh(env);
3374 /* Processor identification */
3375 spr_register(env, SPR_BOOKE_PIR, "PIR",
3376 SPR_NOACCESS, SPR_NOACCESS,
3377 &spr_read_generic, &spr_write_pir,
3378 0x00000000);
3379 /* XXX : not implemented */
3380 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3381 SPR_NOACCESS, SPR_NOACCESS,
3382 &spr_read_generic, &spr_write_generic,
3383 0x00000000);
3384 /* XXX : not implemented */
3385 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3386 SPR_NOACCESS, SPR_NOACCESS,
3387 &spr_read_generic, &spr_write_generic,
3388 0x00000000);
3389 /* XXX : not implemented */
3390 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3391 SPR_NOACCESS, SPR_NOACCESS,
3392 &spr_read_generic, &spr_write_generic,
3393 0x00000000);
3394 /* XXX : not implemented */
3395 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3396 SPR_NOACCESS, SPR_NOACCESS,
3397 &spr_read_generic, &spr_write_generic,
3398 0x00000000);
3399 /* XXX : not implemented */
3400 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3401 SPR_NOACCESS, SPR_NOACCESS,
3402 &spr_read_generic, &spr_write_generic,
3403 0x00000000);
3404 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3405 SPR_NOACCESS, SPR_NOACCESS,
3406 &spr_read_generic, &spr_write_generic,
3407 0x00000000);
3408 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3409 SPR_NOACCESS, SPR_NOACCESS,
3410 &spr_read_generic, &spr_write_generic,
3411 0x00000000);
3412 /* XXX : not implemented */
3413 spr_register(env, SPR_440_CCR1, "CCR1",
3414 SPR_NOACCESS, SPR_NOACCESS,
3415 &spr_read_generic, &spr_write_generic,
3416 0x00000000);
3417 /* Memory management */
3418#if !defined(CONFIG_USER_ONLY)
3419 env->nb_tlb = 64;
3420 env->nb_ways = 1;
3421 env->id_tlbs = 0;
3422#endif
3423 init_excp_BookE(env);
3424 env->dcache_line_size = 32;
3425 env->icache_line_size = 32;
3426 /* XXX: TODO: allocate internal IRQ controller */
3427}
3428
3429/* PowerPC 440 GP */
082c6681
JM		 3430#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3431 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3432 PPC_CACHE | PPC_CACHE_ICBI | \
3433 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3434 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3435 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3436 PPC_440_SPEC)
80d11f44
JM		 3437#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3438#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3439#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3440#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3441#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3442#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3443 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3444#define check_pow_440GP check_pow_nocheck
3445
3446__attribute__ (( unused ))
3447static void init_proc_440GP (CPUPPCState *env)
3448{
3449 /* Time base */
3450 gen_tbl(env);
3451 gen_spr_BookE(env, 0x000000000000FFFFULL);
3452 gen_spr_440(env);
3453 gen_spr_usprgh(env);
3454 /* Processor identification */
3455 spr_register(env, SPR_BOOKE_PIR, "PIR",
3456 SPR_NOACCESS, SPR_NOACCESS,
3457 &spr_read_generic, &spr_write_pir,
3458 0x00000000);
3459 /* XXX : not implemented */
3460 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3461 SPR_NOACCESS, SPR_NOACCESS,
3462 &spr_read_generic, &spr_write_generic,
3463 0x00000000);
3464 /* XXX : not implemented */
3465 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3466 SPR_NOACCESS, SPR_NOACCESS,
3467 &spr_read_generic, &spr_write_generic,
3468 0x00000000);
3469 /* XXX : not implemented */
3470 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3471 SPR_NOACCESS, SPR_NOACCESS,
3472 &spr_read_generic, &spr_write_generic,
3473 0x00000000);
3474 /* XXX : not implemented */
3475 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3476 SPR_NOACCESS, SPR_NOACCESS,
3477 &spr_read_generic, &spr_write_generic,
3478 0x00000000);
3479 /* Memory management */
3480#if !defined(CONFIG_USER_ONLY)
3481 env->nb_tlb = 64;
3482 env->nb_ways = 1;
3483 env->id_tlbs = 0;
3484#endif
3485 init_excp_BookE(env);
3486 env->dcache_line_size = 32;
3487 env->icache_line_size = 32;
3488 /* XXX: TODO: allocate internal IRQ controller */
3489}
3490
3491/* PowerPC 440x4 */
082c6681
JM		 3492#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3493 PPC_DCR | PPC_WRTEE | \
3494 PPC_CACHE | PPC_CACHE_ICBI | \
3495 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3496 PPC_MEM_TLBSYNC | \
80d11f44
JM		 3497 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3498 PPC_440_SPEC)
3499#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3500#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3501#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3502#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3503#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3504#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3505 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3506#define check_pow_440x4 check_pow_nocheck
3507
3508__attribute__ (( unused ))
3509static void init_proc_440x4 (CPUPPCState *env)
3510{
3511 /* Time base */
3512 gen_tbl(env);
3513 gen_spr_BookE(env, 0x000000000000FFFFULL);
3514 gen_spr_440(env);
3515 gen_spr_usprgh(env);
3516 /* Processor identification */
3517 spr_register(env, SPR_BOOKE_PIR, "PIR",
3518 SPR_NOACCESS, SPR_NOACCESS,
3519 &spr_read_generic, &spr_write_pir,
3520 0x00000000);
3521 /* XXX : not implemented */
3522 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3523 SPR_NOACCESS, SPR_NOACCESS,
3524 &spr_read_generic, &spr_write_generic,
3525 0x00000000);
3526 /* XXX : not implemented */
3527 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3528 SPR_NOACCESS, SPR_NOACCESS,
3529 &spr_read_generic, &spr_write_generic,
3530 0x00000000);
3531 /* XXX : not implemented */
3532 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3533 SPR_NOACCESS, SPR_NOACCESS,
3534 &spr_read_generic, &spr_write_generic,
3535 0x00000000);
3536 /* XXX : not implemented */
3537 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3538 SPR_NOACCESS, SPR_NOACCESS,
3539 &spr_read_generic, &spr_write_generic,
3540 0x00000000);
3541 /* Memory management */
3542#if !defined(CONFIG_USER_ONLY)
3543 env->nb_tlb = 64;
3544 env->nb_ways = 1;
3545 env->id_tlbs = 0;
3546#endif
3547 init_excp_BookE(env);
d63001d1
JM		 3548 env->dcache_line_size = 32;
3549 env->icache_line_size = 32;
80d11f44 3550 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3551}
3552
80d11f44 3553/* PowerPC 440x5 */
082c6681
JM		 3554#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3555 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3556 PPC_CACHE | PPC_CACHE_ICBI | \
3557 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3558 PPC_MEM_TLBSYNC | \
80d11f44 3559 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3560 PPC_440_SPEC)
80d11f44
JM		 3561#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3562#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3563#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3564#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3565#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3566#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3567 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3568#define check_pow_440x5 check_pow_nocheck
a750fc0b 3569
80d11f44
JM		 3570__attribute__ (( unused ))
3571static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3572{
a750fc0b
JM		 3573 /* Time base */
3574 gen_tbl(env);
80d11f44
JM		 3575 gen_spr_BookE(env, 0x000000000000FFFFULL);
3576 gen_spr_440(env);
3577 gen_spr_usprgh(env);
3578 /* Processor identification */
3579 spr_register(env, SPR_BOOKE_PIR, "PIR",
3580 SPR_NOACCESS, SPR_NOACCESS,
3581 &spr_read_generic, &spr_write_pir,
3582 0x00000000);
3583 /* XXX : not implemented */
3584 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3585 SPR_NOACCESS, SPR_NOACCESS,
3586 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3587 0x00000000);
3588 /* XXX : not implemented */
3589 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3590 SPR_NOACCESS, SPR_NOACCESS,
3591 &spr_read_generic, &spr_write_generic,
3592 0x00000000);
3593 /* XXX : not implemented */
3594 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3595 SPR_NOACCESS, SPR_NOACCESS,
3596 &spr_read_generic, &spr_write_generic,
3597 0x00000000);
3598 /* XXX : not implemented */
3599 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3600 SPR_NOACCESS, SPR_NOACCESS,
3601 &spr_read_generic, &spr_write_generic,
3602 0x00000000);
3603 /* XXX : not implemented */
3604 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3605 SPR_NOACCESS, SPR_NOACCESS,
3606 &spr_read_generic, &spr_write_generic,
3607 0x00000000);
3608 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3609 SPR_NOACCESS, SPR_NOACCESS,
3610 &spr_read_generic, &spr_write_generic,
3611 0x00000000);
3612 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3613 SPR_NOACCESS, SPR_NOACCESS,
3614 &spr_read_generic, &spr_write_generic,
3615 0x00000000);
3616 /* XXX : not implemented */
3617 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3618 SPR_NOACCESS, SPR_NOACCESS,
3619 &spr_read_generic, &spr_write_generic,
3620 0x00000000);
3621 /* Memory management */
f2e63a42 3622#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3623 env->nb_tlb = 64;
3624 env->nb_ways = 1;
3625 env->id_tlbs = 0;
f2e63a42 3626#endif
80d11f44 3627 init_excp_BookE(env);
d63001d1
JM		 3628 env->dcache_line_size = 32;
3629 env->icache_line_size = 32;
80d11f44 3630 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3631}
3632
80d11f44 3633/* PowerPC 460 (guessed) */
082c6681 3634#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3635 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
082c6681
JM		 3636 PPC_WRTEE | PPC_MFAPIDI | \
3637 PPC_CACHE | PPC_CACHE_ICBI | \
3638 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3639 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3640 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3641 PPC_440_SPEC)
80d11f44
JM		 3642#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3643#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3644#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3645#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3646#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3647#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3648 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3649#define check_pow_460 check_pow_nocheck
a750fc0b 3650
80d11f44
JM		 3651__attribute__ (( unused ))
3652static void init_proc_460 (CPUPPCState *env)
3fc6c082 3653{
a750fc0b
JM		 3654 /* Time base */
3655 gen_tbl(env);
80d11f44 3656 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3657 gen_spr_440(env);
80d11f44
JM		 3658 gen_spr_usprgh(env);
3659 /* Processor identification */
3660 spr_register(env, SPR_BOOKE_PIR, "PIR",
3661 SPR_NOACCESS, SPR_NOACCESS,
3662 &spr_read_generic, &spr_write_pir,
3663 0x00000000);
3664 /* XXX : not implemented */
3665 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3666 SPR_NOACCESS, SPR_NOACCESS,
3667 &spr_read_generic, &spr_write_generic,
3668 0x00000000);
3669 /* XXX : not implemented */
3670 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3671 SPR_NOACCESS, SPR_NOACCESS,
3672 &spr_read_generic, &spr_write_generic,
3673 0x00000000);
3674 /* XXX : not implemented */
3675 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3676 SPR_NOACCESS, SPR_NOACCESS,
3677 &spr_read_generic, &spr_write_generic,
3678 0x00000000);
3679 /* XXX : not implemented */
3680 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3681 SPR_NOACCESS, SPR_NOACCESS,
3682 &spr_read_generic, &spr_write_generic,
3683 0x00000000);
578bb252 3684 /* XXX : not implemented */
a750fc0b
JM		 3685 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3686 SPR_NOACCESS, SPR_NOACCESS,
3687 &spr_read_generic, &spr_write_generic,
3688 0x00000000);
3689 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3690 SPR_NOACCESS, SPR_NOACCESS,
3691 &spr_read_generic, &spr_write_generic,
3692 0x00000000);
3693 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3694 SPR_NOACCESS, SPR_NOACCESS,
3695 &spr_read_generic, &spr_write_generic,
3696 0x00000000);
578bb252 3697 /* XXX : not implemented */
a750fc0b
JM		 3698 spr_register(env, SPR_440_CCR1, "CCR1",
3699 SPR_NOACCESS, SPR_NOACCESS,
3700 &spr_read_generic, &spr_write_generic,
3701 0x00000000);
80d11f44
JM		 3702 /* XXX : not implemented */
3703 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3704 &spr_read_generic, &spr_write_generic,
3705 &spr_read_generic, &spr_write_generic,
3706 0x00000000);
a750fc0b 3707 /* Memory management */
f2e63a42 3708#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3709 env->nb_tlb = 64;
3710 env->nb_ways = 1;
3711 env->id_tlbs = 0;
f2e63a42 3712#endif
e1833e1f 3713 init_excp_BookE(env);
d63001d1
JM		 3714 env->dcache_line_size = 32;
3715 env->icache_line_size = 32;
a750fc0b 3716 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3717}
3718
80d11f44 3719/* PowerPC 460F (guessed) */
082c6681
JM		 3720#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3721 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3722 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
80d11f44 3723 PPC_FLOAT_STFIWX | \
082c6681
JM		 3724 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3725 PPC_WRTEE | PPC_MFAPIDI | \
3726 PPC_CACHE | PPC_CACHE_ICBI | \
3727 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3728 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3729 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3730 PPC_440_SPEC)
80d11f44
JM		 3731#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3732#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3733#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3734#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3735#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3736#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3737 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3738#define check_pow_460F check_pow_nocheck
a750fc0b 3739
80d11f44
JM		 3740__attribute__ (( unused ))
3741static void init_proc_460F (CPUPPCState *env)
3fc6c082 3742{
a750fc0b
JM		 3743 /* Time base */
3744 gen_tbl(env);
80d11f44 3745 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3746 gen_spr_440(env);
80d11f44
JM		 3747 gen_spr_usprgh(env);
3748 /* Processor identification */
3749 spr_register(env, SPR_BOOKE_PIR, "PIR",
3750 SPR_NOACCESS, SPR_NOACCESS,
3751 &spr_read_generic, &spr_write_pir,
3752 0x00000000);
3753 /* XXX : not implemented */
3754 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3755 SPR_NOACCESS, SPR_NOACCESS,
3756 &spr_read_generic, &spr_write_generic,
3757 0x00000000);
3758 /* XXX : not implemented */
3759 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3760 SPR_NOACCESS, SPR_NOACCESS,
3761 &spr_read_generic, &spr_write_generic,
3762 0x00000000);
3763 /* XXX : not implemented */
3764 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3765 SPR_NOACCESS, SPR_NOACCESS,
3766 &spr_read_generic, &spr_write_generic,
3767 0x00000000);
3768 /* XXX : not implemented */
3769 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3770 SPR_NOACCESS, SPR_NOACCESS,
3771 &spr_read_generic, &spr_write_generic,
3772 0x00000000);
3773 /* XXX : not implemented */
3774 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3775 SPR_NOACCESS, SPR_NOACCESS,
3776 &spr_read_generic, &spr_write_generic,
3777 0x00000000);
3778 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3779 SPR_NOACCESS, SPR_NOACCESS,
3780 &spr_read_generic, &spr_write_generic,
3781 0x00000000);
3782 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3783 SPR_NOACCESS, SPR_NOACCESS,
3784 &spr_read_generic, &spr_write_generic,
3785 0x00000000);
3786 /* XXX : not implemented */
3787 spr_register(env, SPR_440_CCR1, "CCR1",
3788 SPR_NOACCESS, SPR_NOACCESS,
3789 &spr_read_generic, &spr_write_generic,
3790 0x00000000);
3791 /* XXX : not implemented */
3792 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3793 &spr_read_generic, &spr_write_generic,
3794 &spr_read_generic, &spr_write_generic,
3795 0x00000000);
a750fc0b 3796 /* Memory management */
f2e63a42 3797#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3798 env->nb_tlb = 64;
3799 env->nb_ways = 1;
3800 env->id_tlbs = 0;
f2e63a42 3801#endif
e1833e1f 3802 init_excp_BookE(env);
d63001d1
JM		 3803 env->dcache_line_size = 32;
3804 env->icache_line_size = 32;
a750fc0b 3805 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3806}
3807
80d11f44
JM		 3808/* Freescale 5xx cores (aka RCPU) */
3809#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3810 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3811 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3812 PPC_MFTB)
3813#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3814#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3815#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3816#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3817#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 3818#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3819 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3820#define check_pow_MPC5xx check_pow_none
3821
3822__attribute__ (( unused ))
3823static void init_proc_MPC5xx (CPUPPCState *env)
3824{
3825 /* Time base */
3826 gen_tbl(env);
3827 gen_spr_5xx_8xx(env);
3828 gen_spr_5xx(env);
3829 init_excp_MPC5xx(env);
3830 env->dcache_line_size = 32;
3831 env->icache_line_size = 32;
3832 /* XXX: TODO: allocate internal IRQ controller */
3833}
3834
3835/* Freescale 8xx cores (aka PowerQUICC) */
3836#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3837 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3838 PPC_CACHE_ICBI | PPC_MFTB)
3839#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3840#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3841#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3842#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3843#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 3844#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3845 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3846#define check_pow_MPC8xx check_pow_none
3847
3848__attribute__ (( unused ))
3849static void init_proc_MPC8xx (CPUPPCState *env)
3850{
3851 /* Time base */
3852 gen_tbl(env);
3853 gen_spr_5xx_8xx(env);
3854 gen_spr_8xx(env);
3855 init_excp_MPC8xx(env);
3856 env->dcache_line_size = 32;
3857 env->icache_line_size = 32;
3858 /* XXX: TODO: allocate internal IRQ controller */
3859}
3860
3861/* Freescale 82xx cores (aka PowerQUICC-II) */
3862/* PowerPC G2 */
082c6681
JM		 3863#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3864 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3865 PPC_FLOAT_STFIWX | \
3866 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3867 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3868 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3869 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3870#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3871#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3872//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3873#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3874#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3875#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3876 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3877#define check_pow_G2 check_pow_hid0
a750fc0b 3878
80d11f44 3879static void init_proc_G2 (CPUPPCState *env)
3fc6c082 3880{
80d11f44
JM		 3881 gen_spr_ne_601(env);
3882 gen_spr_G2_755(env);
3883 gen_spr_G2(env);
a750fc0b
JM		 3884 /* Time base */
3885 gen_tbl(env);
bd928eba
JM		 3886 /* External access control */
3887 /* XXX : not implemented */
3888 spr_register(env, SPR_EAR, "EAR",
3889 SPR_NOACCESS, SPR_NOACCESS,
3890 &spr_read_generic, &spr_write_generic,
3891 0x00000000);
80d11f44
JM		 3892 /* Hardware implementation register */
3893 /* XXX : not implemented */
3894 spr_register(env, SPR_HID0, "HID0",
3895 SPR_NOACCESS, SPR_NOACCESS,
3896 &spr_read_generic, &spr_write_generic,
3897 0x00000000);
3898 /* XXX : not implemented */
3899 spr_register(env, SPR_HID1, "HID1",
3900 SPR_NOACCESS, SPR_NOACCESS,
3901 &spr_read_generic, &spr_write_generic,
3902 0x00000000);
3903 /* XXX : not implemented */
3904 spr_register(env, SPR_HID2, "HID2",
3905 SPR_NOACCESS, SPR_NOACCESS,
3906 &spr_read_generic, &spr_write_generic,
3907 0x00000000);
a750fc0b 3908 /* Memory management */
80d11f44
JM		 3909 gen_low_BATs(env);
3910 gen_high_BATs(env);
3911 gen_6xx_7xx_soft_tlb(env, 64, 2);
3912 init_excp_G2(env);
d63001d1
JM		 3913 env->dcache_line_size = 32;
3914 env->icache_line_size = 32;
80d11f44
JM		 3915 /* Allocate hardware IRQ controller */
3916 ppc6xx_irq_init(env);
3fc6c082 3917}
a750fc0b 3918
80d11f44 3919/* PowerPC G2LE */
082c6681
JM		 3920#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3921 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3922 PPC_FLOAT_STFIWX | \
3923 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3924 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3925 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3926 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3927#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3928#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3929#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3930#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3931#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3932#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3933 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3934#define check_pow_G2LE check_pow_hid0
a750fc0b 3935
80d11f44 3936static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 3937{
80d11f44
JM		 3938 gen_spr_ne_601(env);
3939 gen_spr_G2_755(env);
3940 gen_spr_G2(env);
a750fc0b
JM		 3941 /* Time base */
3942 gen_tbl(env);
bd928eba
JM		 3943 /* External access control */
3944 /* XXX : not implemented */
3945 spr_register(env, SPR_EAR, "EAR",
3946 SPR_NOACCESS, SPR_NOACCESS,
3947 &spr_read_generic, &spr_write_generic,
3948 0x00000000);
80d11f44 3949 /* Hardware implementation register */
578bb252 3950 /* XXX : not implemented */
80d11f44 3951 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 3952 SPR_NOACCESS, SPR_NOACCESS,
3953 &spr_read_generic, &spr_write_generic,
3954 0x00000000);
80d11f44
JM		 3955 /* XXX : not implemented */
3956 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 3957 SPR_NOACCESS, SPR_NOACCESS,
3958 &spr_read_generic, &spr_write_generic,
3959 0x00000000);
578bb252 3960 /* XXX : not implemented */
80d11f44 3961 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 3962 SPR_NOACCESS, SPR_NOACCESS,
3963 &spr_read_generic, &spr_write_generic,
3964 0x00000000);
3965 /* Memory management */
80d11f44
JM		 3966 gen_low_BATs(env);
3967 gen_high_BATs(env);
3968 gen_6xx_7xx_soft_tlb(env, 64, 2);
3969 init_excp_G2(env);
d63001d1
JM		 3970 env->dcache_line_size = 32;
3971 env->icache_line_size = 32;
80d11f44
JM		 3972 /* Allocate hardware IRQ controller */
3973 ppc6xx_irq_init(env);
3fc6c082
FB		 3974}
3975
80d11f44
JM		 3976/* e200 core */
3977/* XXX: unimplemented instructions:
3978 * dcblc
3979 * dcbtlst
3980 * dcbtstls
3981 * icblc
3982 * icbtls
3983 * tlbivax
3984 * all SPE multiply-accumulate instructions
3985 */
082c6681 3986#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
40569b7e 3987 PPC_SPE | PPC_SPE_SINGLE | \
082c6681
JM		 3988 PPC_WRTEE | PPC_RFDI | \
3989 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
3990 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 3991 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 3992 PPC_BOOKE)
80d11f44
JM		 3993#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
3994#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
3995#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
3996#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
3997#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
3998#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 3999 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4000 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4001#define check_pow_e200 check_pow_hid0
4002
578bb252 4003__attribute__ (( unused ))
80d11f44 4004static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4005{
e1833e1f
JM		 4006 /* Time base */
4007 gen_tbl(env);
80d11f44 4008 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4009 /* XXX : not implemented */
80d11f44 4010 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
e1833e1f
JM		 4011 SPR_NOACCESS, SPR_NOACCESS,
4012 &spr_read_generic, &spr_write_generic,
4013 0x00000000);
80d11f44
JM		 4014 /* Memory management */
4015 gen_spr_BookE_FSL(env, 0x0000005D);
4016 /* XXX : not implemented */
4017 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4018 SPR_NOACCESS, SPR_NOACCESS,
4019 &spr_read_generic, &spr_write_generic,
4020 0x00000000);
80d11f44
JM		 4021 /* XXX : not implemented */
4022 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4023 SPR_NOACCESS, SPR_NOACCESS,
4024 &spr_read_generic, &spr_write_generic,
4025 0x00000000);
578bb252 4026 /* XXX : not implemented */
80d11f44 4027 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4028 SPR_NOACCESS, SPR_NOACCESS,
4029 &spr_read_generic, &spr_write_generic,
4030 0x00000000);
578bb252 4031 /* XXX : not implemented */
80d11f44
JM		 4032 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4033 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4034 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4035 0x00000000);
4036 /* XXX : not implemented */
4037 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4038 SPR_NOACCESS, SPR_NOACCESS,
4039 &spr_read_generic, &spr_write_generic,
4040 0x00000000);
4041 /* XXX : not implemented */
4042 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4043 SPR_NOACCESS, SPR_NOACCESS,
4044 &spr_read_generic, &spr_write_generic,
4045 0x00000000);
4046 /* XXX : not implemented */
4047 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4048 SPR_NOACCESS, SPR_NOACCESS,
4049 &spr_read_generic, &spr_write_generic,
4050 0x00000000);
4051 /* XXX : not implemented */
4052 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4053 SPR_NOACCESS, SPR_NOACCESS,
4054 &spr_read_generic, &spr_write_generic,
4055 0x00000000);
4056 /* XXX : not implemented */
4057 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4058 SPR_NOACCESS, SPR_NOACCESS,
4059 &spr_read_generic, &spr_write_generic,
4060 0x00000000);
4061 /* XXX : not implemented */
4062 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4063 SPR_NOACCESS, SPR_NOACCESS,
4064 &spr_read_generic, &spr_write_generic,
4065 0x00000000);
4066 /* XXX : not implemented */
4067 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4068 SPR_NOACCESS, SPR_NOACCESS,
4069 &spr_read_generic, &spr_write_generic,
4070 0x00000000);
4071 /* XXX : not implemented */
4072 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4073 SPR_NOACCESS, SPR_NOACCESS,
4074 &spr_read_generic, &spr_write_generic,
4075 0x00000000);
4076 /* XXX : not implemented */
4077 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4078 SPR_NOACCESS, SPR_NOACCESS,
4079 &spr_read_generic, &spr_write_generic,
4080 0x00000000);
4081 /* XXX : not implemented */
4082 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4083 SPR_NOACCESS, SPR_NOACCESS,
4084 &spr_read_generic, &spr_write_generic,
4085 0x00000000);
4086 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4087 SPR_NOACCESS, SPR_NOACCESS,
4088 &spr_read_generic, &spr_write_generic,
4089 0x00000000);
4090 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4091 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4092 &spr_read_generic, &spr_write_generic,
4093 0x00000000);
f2e63a42 4094#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4095 env->nb_tlb = 64;
4096 env->nb_ways = 1;
4097 env->id_tlbs = 0;
f2e63a42 4098#endif
80d11f44 4099 init_excp_e200(env);
d63001d1
JM		 4100 env->dcache_line_size = 32;
4101 env->icache_line_size = 32;
e1833e1f 4102 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4103}
a750fc0b 4104
80d11f44 4105/* e300 core */
082c6681
JM		 4106#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4107 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4108 PPC_FLOAT_STFIWX | \
4109 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4110 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4111 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4112 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 4113#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4114#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4115#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4116#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4117#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4118#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4119 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4120#define check_pow_e300 check_pow_hid0
a750fc0b 4121
578bb252 4122__attribute__ (( unused ))
80d11f44 4123static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4124{
80d11f44
JM		 4125 gen_spr_ne_601(env);
4126 gen_spr_603(env);
a750fc0b
JM		 4127 /* Time base */
4128 gen_tbl(env);
80d11f44
JM		 4129 /* hardware implementation registers */
4130 /* XXX : not implemented */
4131 spr_register(env, SPR_HID0, "HID0",
4132 SPR_NOACCESS, SPR_NOACCESS,
4133 &spr_read_generic, &spr_write_generic,
4134 0x00000000);
4135 /* XXX : not implemented */
4136 spr_register(env, SPR_HID1, "HID1",
4137 SPR_NOACCESS, SPR_NOACCESS,
4138 &spr_read_generic, &spr_write_generic,
4139 0x00000000);
4140 /* Memory management */
4141 gen_low_BATs(env);
4142 gen_6xx_7xx_soft_tlb(env, 64, 2);
4143 init_excp_603(env);
4144 env->dcache_line_size = 32;
4145 env->icache_line_size = 32;
4146 /* Allocate hardware IRQ controller */
4147 ppc6xx_irq_init(env);
4148}
4149
bd5ea513
AJ		 4150/* e500v1 core */
4151#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4152 PPC_SPE | PPC_SPE_SINGLE | \
4153 PPC_WRTEE | PPC_RFDI | \
4154 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4155 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4156 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4157 PPC_BOOKE)
4158#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4159#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE_FSL)
4160#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4161#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4162#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4163#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4164 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4165 POWERPC_FLAG_BUS_CLK)
4166#define check_pow_e500v1 check_pow_hid0
4167#define init_proc_e500v1 init_proc_e500
4168
4169/* e500v2 core */
4170#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4171 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4172 PPC_WRTEE | PPC_RFDI | \
4173 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4174 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4175 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4176 PPC_BOOKE)
4177#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4178#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE_FSL)
4179#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4180#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4181#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4182#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4183 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4184 POWERPC_FLAG_BUS_CLK)
4185#define check_pow_e500v2 check_pow_hid0
4186#define init_proc_e500v2 init_proc_e500
80d11f44
JM		 4187
4188__attribute__ (( unused ))
4189static void init_proc_e500 (CPUPPCState *env)
4190{
4191 /* Time base */
4192 gen_tbl(env);
4193 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4194 /* Processor identification */
4195 spr_register(env, SPR_BOOKE_PIR, "PIR",
4196 SPR_NOACCESS, SPR_NOACCESS,
4197 &spr_read_generic, &spr_write_pir,
4198 0x00000000);
4199 /* XXX : not implemented */
4200 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4201 SPR_NOACCESS, SPR_NOACCESS,
4202 &spr_read_generic, &spr_write_generic,
4203 0x00000000);
4204 /* Memory management */
4205#if !defined(CONFIG_USER_ONLY)
4206 env->nb_pids = 3;
4207#endif
4208 gen_spr_BookE_FSL(env, 0x0000005F);
4209 /* XXX : not implemented */
4210 spr_register(env, SPR_HID0, "HID0",
4211 SPR_NOACCESS, SPR_NOACCESS,
4212 &spr_read_generic, &spr_write_generic,
4213 0x00000000);
4214 /* XXX : not implemented */
4215 spr_register(env, SPR_HID1, "HID1",
4216 SPR_NOACCESS, SPR_NOACCESS,
4217 &spr_read_generic, &spr_write_generic,
4218 0x00000000);
4219 /* XXX : not implemented */
4220 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4221 SPR_NOACCESS, SPR_NOACCESS,
4222 &spr_read_generic, &spr_write_generic,
4223 0x00000000);
4224 /* XXX : not implemented */
4225 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4226 SPR_NOACCESS, SPR_NOACCESS,
4227 &spr_read_generic, &spr_write_generic,
4228 0x00000000);
4229 /* XXX : not implemented */
4230 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4231 SPR_NOACCESS, SPR_NOACCESS,
4232 &spr_read_generic, &spr_write_generic,
4233 0x00000000);
578bb252 4234 /* XXX : not implemented */
a750fc0b
JM		 4235 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4236 SPR_NOACCESS, SPR_NOACCESS,
4237 &spr_read_generic, &spr_write_generic,
4238 0x00000000);
80d11f44
JM		 4239 /* XXX : not implemented */
4240 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4241 SPR_NOACCESS, SPR_NOACCESS,
4242 &spr_read_generic, &spr_write_generic,
4243 0x00000000);
80d11f44
JM		 4244 /* XXX : not implemented */
4245 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4246 SPR_NOACCESS, SPR_NOACCESS,
4247 &spr_read_generic, &spr_write_generic,
4248 0x00000000);
578bb252 4249 /* XXX : not implemented */
80d11f44 4250 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4251 SPR_NOACCESS, SPR_NOACCESS,
4252 &spr_read_generic, &spr_write_generic,
4253 0x00000000);
578bb252 4254 /* XXX : not implemented */
80d11f44
JM		 4255 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4256 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b 4257 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4258 0x00000000);
4259 /* XXX : not implemented */
4260 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4261 SPR_NOACCESS, SPR_NOACCESS,
4262 &spr_read_generic, &spr_write_generic,
4263 0x00000000);
4264 /* XXX : not implemented */
4265 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4266 SPR_NOACCESS, SPR_NOACCESS,
4267 &spr_read_generic, &spr_write_generic,
4268 0x00000000);
4269 /* XXX : not implemented */
4270 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4271 SPR_NOACCESS, SPR_NOACCESS,
4272 &spr_read_generic, &spr_write_generic,
4273 0x00000000);
4274 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4275 SPR_NOACCESS, SPR_NOACCESS,
4276 &spr_read_generic, &spr_write_generic,
4277 0x00000000);
4278 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4279 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4280 &spr_read_generic, &spr_write_generic,
4281 0x00000000);
f2e63a42 4282#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4283 env->nb_tlb = 64;
4284 env->nb_ways = 1;
4285 env->id_tlbs = 0;
f2e63a42 4286#endif
80d11f44 4287 init_excp_e200(env);
d63001d1
JM		 4288 env->dcache_line_size = 32;
4289 env->icache_line_size = 32;
a750fc0b 4290 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4291}
a750fc0b 4292
a750fc0b 4293/* Non-embedded PowerPC */
a750fc0b
JM		 4294
4295/* POWER : same as 601, without mfmsr, mfsr */
4296#if defined(TODO)
4297#define POWERPC_INSNS_POWER (XXX_TODO)
4298/* POWER RSC (from RAD6000) */
4299#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4300#endif /* TODO */
4301
4302/* PowerPC 601 */
082c6681
JM		 4303#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4304 PPC_FLOAT | \
4305 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4306 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4307 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4308#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4309#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4310//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4311//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4312#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4313#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4314#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4315#define check_pow_601 check_pow_none
a750fc0b
JM		 4316
4317static void init_proc_601 (CPUPPCState *env)
3fc6c082 4318{
a750fc0b
JM		 4319 gen_spr_ne_601(env);
4320 gen_spr_601(env);
4321 /* Hardware implementation registers */
4322 /* XXX : not implemented */
4323 spr_register(env, SPR_HID0, "HID0",
4324 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4325 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4326 0x80010080);
a750fc0b
JM		 4327 /* XXX : not implemented */
4328 spr_register(env, SPR_HID1, "HID1",
4329 SPR_NOACCESS, SPR_NOACCESS,
4330 &spr_read_generic, &spr_write_generic,
4331 0x00000000);
4332 /* XXX : not implemented */
4333 spr_register(env, SPR_601_HID2, "HID2",
4334 SPR_NOACCESS, SPR_NOACCESS,
4335 &spr_read_generic, &spr_write_generic,
4336 0x00000000);
4337 /* XXX : not implemented */
4338 spr_register(env, SPR_601_HID5, "HID5",
4339 SPR_NOACCESS, SPR_NOACCESS,
4340 &spr_read_generic, &spr_write_generic,
4341 0x00000000);
a750fc0b 4342 /* Memory management */
e1833e1f 4343 init_excp_601(env);
082c6681
JM		 4344 /* XXX: beware that dcache line size is 64
4345 * but dcbz uses 32 bytes "sectors"
4346 * XXX: this breaks clcs instruction !
4347 */
4348 env->dcache_line_size = 32;
d63001d1 4349 env->icache_line_size = 64;
faadf50e
JM		 4350 /* Allocate hardware IRQ controller */
4351 ppc6xx_irq_init(env);
3fc6c082
FB		 4352}
4353
082c6681
JM		 4354/* PowerPC 601v */
4355#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4356 PPC_FLOAT | \
4357 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4358 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4359 PPC_SEGMENT | PPC_EXTERN)
4360#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4361#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4362#define POWERPC_MMU_601v (POWERPC_MMU_601)
4363#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4364#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4365#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4366#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4367#define check_pow_601v check_pow_none
4368
4369static void init_proc_601v (CPUPPCState *env)
4370{
4371 init_proc_601(env);
4372 /* XXX : not implemented */
4373 spr_register(env, SPR_601_HID15, "HID15",
4374 SPR_NOACCESS, SPR_NOACCESS,
4375 &spr_read_generic, &spr_write_generic,
4376 0x00000000);
4377}
4378
a750fc0b 4379/* PowerPC 602 */
082c6681
JM		 4380#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4381 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4382 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4383 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4384 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4385 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4386 PPC_SEGMENT | PPC_602_SPEC)
082c6681
JM		 4387#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4388/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4389#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4390//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4391#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4392#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4393#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4394 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4395#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4396
4397static void init_proc_602 (CPUPPCState *env)
3fc6c082 4398{
a750fc0b
JM		 4399 gen_spr_ne_601(env);
4400 gen_spr_602(env);
4401 /* Time base */
4402 gen_tbl(env);
4403 /* hardware implementation registers */
4404 /* XXX : not implemented */
4405 spr_register(env, SPR_HID0, "HID0",
4406 SPR_NOACCESS, SPR_NOACCESS,
4407 &spr_read_generic, &spr_write_generic,
4408 0x00000000);
4409 /* XXX : not implemented */
4410 spr_register(env, SPR_HID1, "HID1",
4411 SPR_NOACCESS, SPR_NOACCESS,
4412 &spr_read_generic, &spr_write_generic,
4413 0x00000000);
4414 /* Memory management */
4415 gen_low_BATs(env);
4416 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4417 init_excp_602(env);
d63001d1
JM		 4418 env->dcache_line_size = 32;
4419 env->icache_line_size = 32;
a750fc0b
JM		 4420 /* Allocate hardware IRQ controller */
4421 ppc6xx_irq_init(env);
4422}
3fc6c082 4423
a750fc0b 4424/* PowerPC 603 */
082c6681
JM		 4425#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4426 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4427 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4428 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4429 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4430 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4431 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4432#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4433#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4434//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4435#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4436#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4437#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4438 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4439#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4440
4441static void init_proc_603 (CPUPPCState *env)
4442{
4443 gen_spr_ne_601(env);
4444 gen_spr_603(env);
4445 /* Time base */
4446 gen_tbl(env);
4447 /* hardware implementation registers */
4448 /* XXX : not implemented */
4449 spr_register(env, SPR_HID0, "HID0",
4450 SPR_NOACCESS, SPR_NOACCESS,
4451 &spr_read_generic, &spr_write_generic,
4452 0x00000000);
4453 /* XXX : not implemented */
4454 spr_register(env, SPR_HID1, "HID1",
4455 SPR_NOACCESS, SPR_NOACCESS,
4456 &spr_read_generic, &spr_write_generic,
4457 0x00000000);
4458 /* Memory management */
4459 gen_low_BATs(env);
4460 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4461 init_excp_603(env);
d63001d1
JM		 4462 env->dcache_line_size = 32;
4463 env->icache_line_size = 32;
a750fc0b
JM		 4464 /* Allocate hardware IRQ controller */
4465 ppc6xx_irq_init(env);
3fc6c082
FB		 4466}
4467
a750fc0b 4468/* PowerPC 603e */
082c6681
JM		 4469#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4470 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4471 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4472 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4473 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4474 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4475 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4476#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4477#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4478//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4479#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4480#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4481#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4482 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4483#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4484
4485static void init_proc_603E (CPUPPCState *env)
4486{
4487 gen_spr_ne_601(env);
4488 gen_spr_603(env);
4489 /* Time base */
4490 gen_tbl(env);
4491 /* hardware implementation registers */
4492 /* XXX : not implemented */
4493 spr_register(env, SPR_HID0, "HID0",
4494 SPR_NOACCESS, SPR_NOACCESS,
4495 &spr_read_generic, &spr_write_generic,
4496 0x00000000);
4497 /* XXX : not implemented */
4498 spr_register(env, SPR_HID1, "HID1",
4499 SPR_NOACCESS, SPR_NOACCESS,
4500 &spr_read_generic, &spr_write_generic,
4501 0x00000000);
4502 /* XXX : not implemented */
4503 spr_register(env, SPR_IABR, "IABR",
4504 SPR_NOACCESS, SPR_NOACCESS,
4505 &spr_read_generic, &spr_write_generic,
4506 0x00000000);
4507 /* Memory management */
4508 gen_low_BATs(env);
4509 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4510 init_excp_603(env);
d63001d1
JM		 4511 env->dcache_line_size = 32;
4512 env->icache_line_size = 32;
a750fc0b
JM		 4513 /* Allocate hardware IRQ controller */
4514 ppc6xx_irq_init(env);
4515}
4516
a750fc0b 4517/* PowerPC 604 */
082c6681
JM		 4518#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4519 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4520 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4521 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4522 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4523 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4524 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4525#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4526#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4527//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4528#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4529#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4530#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4531 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4532#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4533
4534static void init_proc_604 (CPUPPCState *env)
4535{
4536 gen_spr_ne_601(env);
4537 gen_spr_604(env);
4538 /* Time base */
4539 gen_tbl(env);
4540 /* Hardware implementation registers */
4541 /* XXX : not implemented */
082c6681
JM		 4542 spr_register(env, SPR_HID0, "HID0",
4543 SPR_NOACCESS, SPR_NOACCESS,
4544 &spr_read_generic, &spr_write_generic,
4545 0x00000000);
4546 /* Memory management */
4547 gen_low_BATs(env);
4548 init_excp_604(env);
4549 env->dcache_line_size = 32;
4550 env->icache_line_size = 32;
4551 /* Allocate hardware IRQ controller */
4552 ppc6xx_irq_init(env);
4553}
4554
4555/* PowerPC 604E */
4556#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4557 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4558 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4559 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4560 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4561 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4562 PPC_SEGMENT | PPC_EXTERN)
4563#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4564#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4565#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4566#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4567#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4568#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4569 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4570#define check_pow_604E check_pow_nocheck
4571
4572static void init_proc_604E (CPUPPCState *env)
4573{
4574 gen_spr_ne_601(env);
4575 gen_spr_604(env);
4576 /* XXX : not implemented */
4577 spr_register(env, SPR_MMCR1, "MMCR1",
4578 SPR_NOACCESS, SPR_NOACCESS,
4579 &spr_read_generic, &spr_write_generic,
4580 0x00000000);
4581 /* XXX : not implemented */
4582 spr_register(env, SPR_PMC3, "PMC3",
4583 SPR_NOACCESS, SPR_NOACCESS,
4584 &spr_read_generic, &spr_write_generic,
4585 0x00000000);
4586 /* XXX : not implemented */
4587 spr_register(env, SPR_PMC4, "PMC4",
4588 SPR_NOACCESS, SPR_NOACCESS,
4589 &spr_read_generic, &spr_write_generic,
4590 0x00000000);
4591 /* Time base */
4592 gen_tbl(env);
4593 /* Hardware implementation registers */
4594 /* XXX : not implemented */
a750fc0b
JM		 4595 spr_register(env, SPR_HID0, "HID0",
4596 SPR_NOACCESS, SPR_NOACCESS,
4597 &spr_read_generic, &spr_write_generic,
4598 0x00000000);
4599 /* XXX : not implemented */
4600 spr_register(env, SPR_HID1, "HID1",
4601 SPR_NOACCESS, SPR_NOACCESS,
4602 &spr_read_generic, &spr_write_generic,
4603 0x00000000);
4604 /* Memory management */
4605 gen_low_BATs(env);
e1833e1f 4606 init_excp_604(env);
d63001d1
JM		 4607 env->dcache_line_size = 32;
4608 env->icache_line_size = 32;
a750fc0b
JM		 4609 /* Allocate hardware IRQ controller */
4610 ppc6xx_irq_init(env);
4611}
4612
bd928eba
JM		 4613/* PowerPC 740 */
4614#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 4615 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4616 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4617 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4618 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4619 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4620 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 4621#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4622#define POWERPC_MMU_740 (POWERPC_MMU_32B)
4623#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4624#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4625#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4626#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4627 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 4628#define check_pow_740 check_pow_hid0
a750fc0b 4629
bd928eba 4630static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 4631{
4632 gen_spr_ne_601(env);
4633 gen_spr_7xx(env);
4634 /* Time base */
4635 gen_tbl(env);
4636 /* Thermal management */
4637 gen_spr_thrm(env);
4638 /* Hardware implementation registers */
4639 /* XXX : not implemented */
4640 spr_register(env, SPR_HID0, "HID0",
4641 SPR_NOACCESS, SPR_NOACCESS,
4642 &spr_read_generic, &spr_write_generic,
4643 0x00000000);
4644 /* XXX : not implemented */
4645 spr_register(env, SPR_HID1, "HID1",
4646 SPR_NOACCESS, SPR_NOACCESS,
4647 &spr_read_generic, &spr_write_generic,
4648 0x00000000);
4649 /* Memory management */
4650 gen_low_BATs(env);
e1833e1f 4651 init_excp_7x0(env);
d63001d1
JM		 4652 env->dcache_line_size = 32;
4653 env->icache_line_size = 32;
a750fc0b
JM		 4654 /* Allocate hardware IRQ controller */
4655 ppc6xx_irq_init(env);
4656}
4657
bd928eba
JM		 4658/* PowerPC 750 */
4659#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4660 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4661 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4662 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4663 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4664 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4665 PPC_SEGMENT | PPC_EXTERN)
4666#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4667#define POWERPC_MMU_750 (POWERPC_MMU_32B)
4668#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4669#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4670#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4671#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4672 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4673#define check_pow_750 check_pow_hid0
4674
4675static void init_proc_750 (CPUPPCState *env)
4676{
4677 gen_spr_ne_601(env);
4678 gen_spr_7xx(env);
4679 /* XXX : not implemented */
4680 spr_register(env, SPR_L2CR, "L2CR",
4681 SPR_NOACCESS, SPR_NOACCESS,
4682 &spr_read_generic, &spr_write_generic,
4683 0x00000000);
4684 /* Time base */
4685 gen_tbl(env);
4686 /* Thermal management */
4687 gen_spr_thrm(env);
4688 /* Hardware implementation registers */
4689 /* XXX : not implemented */
4690 spr_register(env, SPR_HID0, "HID0",
4691 SPR_NOACCESS, SPR_NOACCESS,
4692 &spr_read_generic, &spr_write_generic,
4693 0x00000000);
4694 /* XXX : not implemented */
4695 spr_register(env, SPR_HID1, "HID1",
4696 SPR_NOACCESS, SPR_NOACCESS,
4697 &spr_read_generic, &spr_write_generic,
4698 0x00000000);
4699 /* Memory management */
4700 gen_low_BATs(env);
4701 /* XXX: high BATs are also present but are known to be bugged on
4702 * die version 1.x
4703 */
4704 init_excp_7x0(env);
4705 env->dcache_line_size = 32;
4706 env->icache_line_size = 32;
4707 /* Allocate hardware IRQ controller */
4708 ppc6xx_irq_init(env);
4709}
4710
4711/* PowerPC 750 CL */
4712/* XXX: not implemented:
4713 * cache lock instructions:
4714 * dcbz_l
4715 * floating point paired instructions
4716 * psq_lux
4717 * psq_lx
4718 * psq_stux
4719 * psq_stx
4720 * ps_abs
4721 * ps_add
4722 * ps_cmpo0
4723 * ps_cmpo1
4724 * ps_cmpu0
4725 * ps_cmpu1
4726 * ps_div
4727 * ps_madd
4728 * ps_madds0
4729 * ps_madds1
4730 * ps_merge00
4731 * ps_merge01
4732 * ps_merge10
4733 * ps_merge11
4734 * ps_mr
4735 * ps_msub
4736 * ps_mul
4737 * ps_muls0
4738 * ps_muls1
4739 * ps_nabs
4740 * ps_neg
4741 * ps_nmadd
4742 * ps_nmsub
4743 * ps_res
4744 * ps_rsqrte
4745 * ps_sel
4746 * ps_sub
4747 * ps_sum0
4748 * ps_sum1
4749 */
4750#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4751 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4752 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4753 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4754 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4755 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4756 PPC_SEGMENT | PPC_EXTERN)
4757#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4758#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4759#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4760#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4761#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4762#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4763 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4764#define check_pow_750cl check_pow_hid0
4765
4766static void init_proc_750cl (CPUPPCState *env)
4767{
4768 gen_spr_ne_601(env);
4769 gen_spr_7xx(env);
4770 /* XXX : not implemented */
4771 spr_register(env, SPR_L2CR, "L2CR",
4772 SPR_NOACCESS, SPR_NOACCESS,
4773 &spr_read_generic, &spr_write_generic,
4774 0x00000000);
4775 /* Time base */
4776 gen_tbl(env);
4777 /* Thermal management */
4778 /* Those registers are fake on 750CL */
4779 spr_register(env, SPR_THRM1, "THRM1",
4780 SPR_NOACCESS, SPR_NOACCESS,
4781 &spr_read_generic, &spr_write_generic,
4782 0x00000000);
4783 spr_register(env, SPR_THRM2, "THRM2",
4784 SPR_NOACCESS, SPR_NOACCESS,
4785 &spr_read_generic, &spr_write_generic,
4786 0x00000000);
4787 spr_register(env, SPR_THRM3, "THRM3",
4788 SPR_NOACCESS, SPR_NOACCESS,
4789 &spr_read_generic, &spr_write_generic,
4790 0x00000000);
4791 /* XXX: not implemented */
4792 spr_register(env, SPR_750_TDCL, "TDCL",
4793 SPR_NOACCESS, SPR_NOACCESS,
4794 &spr_read_generic, &spr_write_generic,
4795 0x00000000);
4796 spr_register(env, SPR_750_TDCH, "TDCH",
4797 SPR_NOACCESS, SPR_NOACCESS,
4798 &spr_read_generic, &spr_write_generic,
4799 0x00000000);
4800 /* DMA */
4801 /* XXX : not implemented */
4802 spr_register(env, SPR_750_WPAR, "WPAR",
4803 SPR_NOACCESS, SPR_NOACCESS,
4804 &spr_read_generic, &spr_write_generic,
4805 0x00000000);
4806 spr_register(env, SPR_750_DMAL, "DMAL",
4807 SPR_NOACCESS, SPR_NOACCESS,
4808 &spr_read_generic, &spr_write_generic,
4809 0x00000000);
4810 spr_register(env, SPR_750_DMAU, "DMAU",
4811 SPR_NOACCESS, SPR_NOACCESS,
4812 &spr_read_generic, &spr_write_generic,
4813 0x00000000);
4814 /* Hardware implementation registers */
4815 /* XXX : not implemented */
4816 spr_register(env, SPR_HID0, "HID0",
4817 SPR_NOACCESS, SPR_NOACCESS,
4818 &spr_read_generic, &spr_write_generic,
4819 0x00000000);
4820 /* XXX : not implemented */
4821 spr_register(env, SPR_HID1, "HID1",
4822 SPR_NOACCESS, SPR_NOACCESS,
4823 &spr_read_generic, &spr_write_generic,
4824 0x00000000);
4825 /* XXX : not implemented */
4826 spr_register(env, SPR_750CL_HID2, "HID2",
4827 SPR_NOACCESS, SPR_NOACCESS,
4828 &spr_read_generic, &spr_write_generic,
4829 0x00000000);
4830 /* XXX : not implemented */
4831 spr_register(env, SPR_750CL_HID4, "HID4",
4832 SPR_NOACCESS, SPR_NOACCESS,
4833 &spr_read_generic, &spr_write_generic,
4834 0x00000000);
4835 /* Quantization registers */
4836 /* XXX : not implemented */
4837 spr_register(env, SPR_750_GQR0, "GQR0",
4838 SPR_NOACCESS, SPR_NOACCESS,
4839 &spr_read_generic, &spr_write_generic,
4840 0x00000000);
4841 /* XXX : not implemented */
4842 spr_register(env, SPR_750_GQR1, "GQR1",
4843 SPR_NOACCESS, SPR_NOACCESS,
4844 &spr_read_generic, &spr_write_generic,
4845 0x00000000);
4846 /* XXX : not implemented */
4847 spr_register(env, SPR_750_GQR2, "GQR2",
4848 SPR_NOACCESS, SPR_NOACCESS,
4849 &spr_read_generic, &spr_write_generic,
4850 0x00000000);
4851 /* XXX : not implemented */
4852 spr_register(env, SPR_750_GQR3, "GQR3",
4853 SPR_NOACCESS, SPR_NOACCESS,
4854 &spr_read_generic, &spr_write_generic,
4855 0x00000000);
4856 /* XXX : not implemented */
4857 spr_register(env, SPR_750_GQR4, "GQR4",
4858 SPR_NOACCESS, SPR_NOACCESS,
4859 &spr_read_generic, &spr_write_generic,
4860 0x00000000);
4861 /* XXX : not implemented */
4862 spr_register(env, SPR_750_GQR5, "GQR5",
4863 SPR_NOACCESS, SPR_NOACCESS,
4864 &spr_read_generic, &spr_write_generic,
4865 0x00000000);
4866 /* XXX : not implemented */
4867 spr_register(env, SPR_750_GQR6, "GQR6",
4868 SPR_NOACCESS, SPR_NOACCESS,
4869 &spr_read_generic, &spr_write_generic,
4870 0x00000000);
4871 /* XXX : not implemented */
4872 spr_register(env, SPR_750_GQR7, "GQR7",
4873 SPR_NOACCESS, SPR_NOACCESS,
4874 &spr_read_generic, &spr_write_generic,
4875 0x00000000);
4876 /* Memory management */
4877 gen_low_BATs(env);
4878 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4879 gen_high_BATs(env);
4880 init_excp_750cl(env);
4881 env->dcache_line_size = 32;
4882 env->icache_line_size = 32;
4883 /* Allocate hardware IRQ controller */
4884 ppc6xx_irq_init(env);
4885}
4886
4e777442 4887/* PowerPC 750CX */
bd928eba
JM		 4888#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4889 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4890 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4891 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4892 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4893 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4894 PPC_SEGMENT | PPC_EXTERN)
4895#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
4896#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
4897#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
4898#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
4899#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
4900#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4901 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4902#define check_pow_750cx check_pow_hid0
4903
4904static void init_proc_750cx (CPUPPCState *env)
4905{
4906 gen_spr_ne_601(env);
4907 gen_spr_7xx(env);
4908 /* XXX : not implemented */
4909 spr_register(env, SPR_L2CR, "L2CR",
4910 SPR_NOACCESS, SPR_NOACCESS,
4911 &spr_read_generic, &spr_write_generic,
4912 0x00000000);
4913 /* Time base */
4914 gen_tbl(env);
4915 /* Thermal management */
4916 gen_spr_thrm(env);
4917 /* This register is not implemented but is present for compatibility */
4918 spr_register(env, SPR_SDA, "SDA",
4919 SPR_NOACCESS, SPR_NOACCESS,
4920 &spr_read_generic, &spr_write_generic,
4921 0x00000000);
4922 /* Hardware implementation registers */
4923 /* XXX : not implemented */
4924 spr_register(env, SPR_HID0, "HID0",
4925 SPR_NOACCESS, SPR_NOACCESS,
4926 &spr_read_generic, &spr_write_generic,
4927 0x00000000);
4928 /* XXX : not implemented */
4929 spr_register(env, SPR_HID1, "HID1",
4930 SPR_NOACCESS, SPR_NOACCESS,
4931 &spr_read_generic, &spr_write_generic,
4932 0x00000000);
4933 /* Memory management */
4934 gen_low_BATs(env);
4e777442
JM		 4935 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4936 gen_high_BATs(env);
bd928eba
JM		 4937 init_excp_750cx(env);
4938 env->dcache_line_size = 32;
4939 env->icache_line_size = 32;
4940 /* Allocate hardware IRQ controller */
4941 ppc6xx_irq_init(env);
4942}
4943
4944/* PowerPC 750FX */
082c6681
JM		 4945#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4946 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4947 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4948 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4949 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4950 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4951 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4952#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 4953#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4954#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4955#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 4956#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 4957#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4958 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4959#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 4960
4961static void init_proc_750fx (CPUPPCState *env)
4962{
4963 gen_spr_ne_601(env);
4964 gen_spr_7xx(env);
bd928eba
JM		 4965 /* XXX : not implemented */
4966 spr_register(env, SPR_L2CR, "L2CR",
4967 SPR_NOACCESS, SPR_NOACCESS,
4968 &spr_read_generic, &spr_write_generic,
4969 0x00000000);
a750fc0b
JM		 4970 /* Time base */
4971 gen_tbl(env);
4972 /* Thermal management */
4973 gen_spr_thrm(env);
bd928eba
JM		 4974 /* XXX : not implemented */
4975 spr_register(env, SPR_750_THRM4, "THRM4",
4976 SPR_NOACCESS, SPR_NOACCESS,
4977 &spr_read_generic, &spr_write_generic,
4978 0x00000000);
a750fc0b
JM		 4979 /* Hardware implementation registers */
4980 /* XXX : not implemented */
4981 spr_register(env, SPR_HID0, "HID0",
4982 SPR_NOACCESS, SPR_NOACCESS,
4983 &spr_read_generic, &spr_write_generic,
4984 0x00000000);
4985 /* XXX : not implemented */
4986 spr_register(env, SPR_HID1, "HID1",
4987 SPR_NOACCESS, SPR_NOACCESS,
4988 &spr_read_generic, &spr_write_generic,
4989 0x00000000);
4990 /* XXX : not implemented */
bd928eba 4991 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 4992 SPR_NOACCESS, SPR_NOACCESS,
4993 &spr_read_generic, &spr_write_generic,
4994 0x00000000);
4995 /* Memory management */
4996 gen_low_BATs(env);
4997 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4998 gen_high_BATs(env);
bd928eba 4999 init_excp_7x0(env);
d63001d1
JM		 5000 env->dcache_line_size = 32;
5001 env->icache_line_size = 32;
a750fc0b
JM		 5002 /* Allocate hardware IRQ controller */
5003 ppc6xx_irq_init(env);
5004}
5005
bd928eba
JM		 5006/* PowerPC 750GX */
5007#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 5008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba
JM		 5009 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5010 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5011 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5013 PPC_SEGMENT | PPC_EXTERN)
5014#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5015#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5016#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5017#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5018#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5019#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5020 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5021#define check_pow_750gx check_pow_hid0
5022
5023static void init_proc_750gx (CPUPPCState *env)
5024{
5025 gen_spr_ne_601(env);
5026 gen_spr_7xx(env);
5027 /* XXX : not implemented (XXX: different from 750fx) */
5028 spr_register(env, SPR_L2CR, "L2CR",
5029 SPR_NOACCESS, SPR_NOACCESS,
5030 &spr_read_generic, &spr_write_generic,
5031 0x00000000);
5032 /* Time base */
5033 gen_tbl(env);
5034 /* Thermal management */
5035 gen_spr_thrm(env);
5036 /* XXX : not implemented */
5037 spr_register(env, SPR_750_THRM4, "THRM4",
5038 SPR_NOACCESS, SPR_NOACCESS,
5039 &spr_read_generic, &spr_write_generic,
5040 0x00000000);
5041 /* Hardware implementation registers */
5042 /* XXX : not implemented (XXX: different from 750fx) */
5043 spr_register(env, SPR_HID0, "HID0",
5044 SPR_NOACCESS, SPR_NOACCESS,
5045 &spr_read_generic, &spr_write_generic,
5046 0x00000000);
5047 /* XXX : not implemented */
5048 spr_register(env, SPR_HID1, "HID1",
5049 SPR_NOACCESS, SPR_NOACCESS,
5050 &spr_read_generic, &spr_write_generic,
5051 0x00000000);
5052 /* XXX : not implemented (XXX: different from 750fx) */
5053 spr_register(env, SPR_750FX_HID2, "HID2",
5054 SPR_NOACCESS, SPR_NOACCESS,
5055 &spr_read_generic, &spr_write_generic,
5056 0x00000000);
5057 /* Memory management */
5058 gen_low_BATs(env);
5059 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5060 gen_high_BATs(env);
5061 init_excp_7x0(env);
5062 env->dcache_line_size = 32;
5063 env->icache_line_size = 32;
5064 /* Allocate hardware IRQ controller */
5065 ppc6xx_irq_init(env);
5066}
5067
5068/* PowerPC 745 */
5069#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5070 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5071 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5072 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5073 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5074 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5075 PPC_SEGMENT | PPC_EXTERN)
5076#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5077#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5078#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5079#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5080#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5081#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5082 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5083#define check_pow_745 check_pow_hid0
5084
5085static void init_proc_745 (CPUPPCState *env)
5086{
5087 gen_spr_ne_601(env);
5088 gen_spr_7xx(env);
5089 gen_spr_G2_755(env);
5090 /* Time base */
5091 gen_tbl(env);
5092 /* Thermal management */
5093 gen_spr_thrm(env);
5094 /* Hardware implementation registers */
5095 /* XXX : not implemented */
5096 spr_register(env, SPR_HID0, "HID0",
5097 SPR_NOACCESS, SPR_NOACCESS,
5098 &spr_read_generic, &spr_write_generic,
5099 0x00000000);
5100 /* XXX : not implemented */
5101 spr_register(env, SPR_HID1, "HID1",
5102 SPR_NOACCESS, SPR_NOACCESS,
5103 &spr_read_generic, &spr_write_generic,
5104 0x00000000);
5105 /* XXX : not implemented */
5106 spr_register(env, SPR_HID2, "HID2",
5107 SPR_NOACCESS, SPR_NOACCESS,
5108 &spr_read_generic, &spr_write_generic,
5109 0x00000000);
5110 /* Memory management */
5111 gen_low_BATs(env);
5112 gen_high_BATs(env);
5113 gen_6xx_7xx_soft_tlb(env, 64, 2);
5114 init_excp_7x5(env);
5115 env->dcache_line_size = 32;
5116 env->icache_line_size = 32;
5117 /* Allocate hardware IRQ controller */
5118 ppc6xx_irq_init(env);
5119}
5120
5121/* PowerPC 755 */
5122#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5123 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5124 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5125 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5126 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5127 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5128 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 5129#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5130#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5131#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5132#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5133#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5134#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5135 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5136#define check_pow_755 check_pow_hid0
a750fc0b 5137
bd928eba 5138static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5139{
5140 gen_spr_ne_601(env);
bd928eba 5141 gen_spr_7xx(env);
a750fc0b
JM		 5142 gen_spr_G2_755(env);
5143 /* Time base */
5144 gen_tbl(env);
5145 /* L2 cache control */
5146 /* XXX : not implemented */
bd928eba 5147 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5148 SPR_NOACCESS, SPR_NOACCESS,
5149 &spr_read_generic, &spr_write_generic,
5150 0x00000000);
5151 /* XXX : not implemented */
5152 spr_register(env, SPR_L2PMCR, "L2PMCR",
5153 SPR_NOACCESS, SPR_NOACCESS,
5154 &spr_read_generic, &spr_write_generic,
5155 0x00000000);
bd928eba
JM		 5156 /* Thermal management */
5157 gen_spr_thrm(env);
a750fc0b
JM		 5158 /* Hardware implementation registers */
5159 /* XXX : not implemented */
5160 spr_register(env, SPR_HID0, "HID0",
5161 SPR_NOACCESS, SPR_NOACCESS,
5162 &spr_read_generic, &spr_write_generic,
5163 0x00000000);
5164 /* XXX : not implemented */
5165 spr_register(env, SPR_HID1, "HID1",
5166 SPR_NOACCESS, SPR_NOACCESS,
5167 &spr_read_generic, &spr_write_generic,
5168 0x00000000);
5169 /* XXX : not implemented */
5170 spr_register(env, SPR_HID2, "HID2",
5171 SPR_NOACCESS, SPR_NOACCESS,
5172 &spr_read_generic, &spr_write_generic,
5173 0x00000000);
5174 /* Memory management */
5175 gen_low_BATs(env);
5176 gen_high_BATs(env);
5177 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5178 init_excp_7x5(env);
d63001d1
JM		 5179 env->dcache_line_size = 32;
5180 env->icache_line_size = 32;
a750fc0b
JM		 5181 /* Allocate hardware IRQ controller */
5182 ppc6xx_irq_init(env);
5183}
5184
5185/* PowerPC 7400 (aka G4) */
082c6681
JM		 5186#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5187 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5188 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5189 PPC_FLOAT_STFIWX | \
5190 PPC_CACHE | PPC_CACHE_ICBI | \
5191 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5192 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5193 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5194 PPC_MEM_TLBIA | \
5195 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5196 PPC_ALTIVEC)
5197#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5198#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5199#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5200#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5201#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5202#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5203 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5204 POWERPC_FLAG_BUS_CLK)
4e777442 5205#define check_pow_7400 check_pow_hid0_74xx
a750fc0b
JM		 5206
5207static void init_proc_7400 (CPUPPCState *env)
5208{
5209 gen_spr_ne_601(env);
5210 gen_spr_7xx(env);
5211 /* Time base */
5212 gen_tbl(env);
5213 /* 74xx specific SPR */
5214 gen_spr_74xx(env);
4e777442
JM		 5215 /* XXX : not implemented */
5216 spr_register(env, SPR_UBAMR, "UBAMR",
5217 &spr_read_ureg, SPR_NOACCESS,
5218 &spr_read_ureg, SPR_NOACCESS,
5219 0x00000000);
5220 /* XXX: this seems not implemented on all revisions. */
5221 /* XXX : not implemented */
5222 spr_register(env, SPR_MSSCR1, "MSSCR1",
5223 SPR_NOACCESS, SPR_NOACCESS,
5224 &spr_read_generic, &spr_write_generic,
5225 0x00000000);
a750fc0b
JM		 5226 /* Thermal management */
5227 gen_spr_thrm(env);
5228 /* Memory management */
5229 gen_low_BATs(env);
e1833e1f 5230 init_excp_7400(env);
d63001d1
JM		 5231 env->dcache_line_size = 32;
5232 env->icache_line_size = 32;
a750fc0b
JM		 5233 /* Allocate hardware IRQ controller */
5234 ppc6xx_irq_init(env);
5235}
5236
5237/* PowerPC 7410 (aka G4) */
082c6681
JM		 5238#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5239 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5240 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5241 PPC_FLOAT_STFIWX | \
5242 PPC_CACHE | PPC_CACHE_ICBI | \
5243 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5244 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5245 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5246 PPC_MEM_TLBIA | \
5247 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5248 PPC_ALTIVEC)
5249#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5250#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5251#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5252#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5253#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5254#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5255 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5256 POWERPC_FLAG_BUS_CLK)
4e777442 5257#define check_pow_7410 check_pow_hid0_74xx
a750fc0b
JM		 5258
5259static void init_proc_7410 (CPUPPCState *env)
5260{
5261 gen_spr_ne_601(env);
5262 gen_spr_7xx(env);
5263 /* Time base */
5264 gen_tbl(env);
5265 /* 74xx specific SPR */
5266 gen_spr_74xx(env);
4e777442
JM		 5267 /* XXX : not implemented */
5268 spr_register(env, SPR_UBAMR, "UBAMR",
5269 &spr_read_ureg, SPR_NOACCESS,
5270 &spr_read_ureg, SPR_NOACCESS,
5271 0x00000000);
a750fc0b
JM		 5272 /* Thermal management */
5273 gen_spr_thrm(env);
5274 /* L2PMCR */
5275 /* XXX : not implemented */
5276 spr_register(env, SPR_L2PMCR, "L2PMCR",
5277 SPR_NOACCESS, SPR_NOACCESS,
5278 &spr_read_generic, &spr_write_generic,
5279 0x00000000);
5280 /* LDSTDB */
5281 /* XXX : not implemented */
5282 spr_register(env, SPR_LDSTDB, "LDSTDB",
5283 SPR_NOACCESS, SPR_NOACCESS,
5284 &spr_read_generic, &spr_write_generic,
5285 0x00000000);
5286 /* Memory management */
5287 gen_low_BATs(env);
e1833e1f 5288 init_excp_7400(env);
d63001d1
JM		 5289 env->dcache_line_size = 32;
5290 env->icache_line_size = 32;
a750fc0b
JM		 5291 /* Allocate hardware IRQ controller */
5292 ppc6xx_irq_init(env);
5293}
5294
5295/* PowerPC 7440 (aka G4) */
082c6681
JM		 5296#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5297 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5298 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5299 PPC_FLOAT_STFIWX | \
5300 PPC_CACHE | PPC_CACHE_ICBI | \
5301 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5302 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5303 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5304 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5305 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5306 PPC_ALTIVEC)
5307#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5308#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5309#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5310#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 5311#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 5312#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5313 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5314 POWERPC_FLAG_BUS_CLK)
4e777442 5315#define check_pow_7440 check_pow_hid0_74xx
a750fc0b 5316
578bb252 5317__attribute__ (( unused ))
a750fc0b
JM		 5318static void init_proc_7440 (CPUPPCState *env)
5319{
5320 gen_spr_ne_601(env);
5321 gen_spr_7xx(env);
5322 /* Time base */
5323 gen_tbl(env);
5324 /* 74xx specific SPR */
5325 gen_spr_74xx(env);
4e777442
JM		 5326 /* XXX : not implemented */
5327 spr_register(env, SPR_UBAMR, "UBAMR",
5328 &spr_read_ureg, SPR_NOACCESS,
5329 &spr_read_ureg, SPR_NOACCESS,
5330 0x00000000);
a750fc0b
JM		 5331 /* LDSTCR */
5332 /* XXX : not implemented */
5333 spr_register(env, SPR_LDSTCR, "LDSTCR",
5334 SPR_NOACCESS, SPR_NOACCESS,
5335 &spr_read_generic, &spr_write_generic,
5336 0x00000000);
5337 /* ICTRL */
5338 /* XXX : not implemented */
5339 spr_register(env, SPR_ICTRL, "ICTRL",
5340 SPR_NOACCESS, SPR_NOACCESS,
5341 &spr_read_generic, &spr_write_generic,
5342 0x00000000);
5343 /* MSSSR0 */
578bb252 5344 /* XXX : not implemented */
a750fc0b
JM		 5345 spr_register(env, SPR_MSSSR0, "MSSSR0",
5346 SPR_NOACCESS, SPR_NOACCESS,
5347 &spr_read_generic, &spr_write_generic,
5348 0x00000000);
5349 /* PMC */
5350 /* XXX : not implemented */
5351 spr_register(env, SPR_PMC5, "PMC5",
5352 SPR_NOACCESS, SPR_NOACCESS,
5353 &spr_read_generic, &spr_write_generic,
5354 0x00000000);
578bb252 5355 /* XXX : not implemented */
a750fc0b
JM		 5356 spr_register(env, SPR_UPMC5, "UPMC5",
5357 &spr_read_ureg, SPR_NOACCESS,
5358 &spr_read_ureg, SPR_NOACCESS,
5359 0x00000000);
578bb252 5360 /* XXX : not implemented */
a750fc0b
JM		 5361 spr_register(env, SPR_PMC6, "PMC6",
5362 SPR_NOACCESS, SPR_NOACCESS,
5363 &spr_read_generic, &spr_write_generic,
5364 0x00000000);
578bb252 5365 /* XXX : not implemented */
a750fc0b
JM		 5366 spr_register(env, SPR_UPMC6, "UPMC6",
5367 &spr_read_ureg, SPR_NOACCESS,
5368 &spr_read_ureg, SPR_NOACCESS,
5369 0x00000000);
5370 /* Memory management */
5371 gen_low_BATs(env);
578bb252 5372 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5373 init_excp_7450(env);
d63001d1
JM		 5374 env->dcache_line_size = 32;
5375 env->icache_line_size = 32;
a750fc0b
JM		 5376 /* Allocate hardware IRQ controller */
5377 ppc6xx_irq_init(env);
5378}
a750fc0b
JM		 5379
5380/* PowerPC 7450 (aka G4) */
082c6681
JM		 5381#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5382 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5383 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5384 PPC_FLOAT_STFIWX | \
5385 PPC_CACHE | PPC_CACHE_ICBI | \
5386 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5387 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5388 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5389 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5390 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5391 PPC_ALTIVEC)
5392#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5393#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5394#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5395#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 5396#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 5397#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5398 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5399 POWERPC_FLAG_BUS_CLK)
4e777442 5400#define check_pow_7450 check_pow_hid0_74xx
a750fc0b 5401
578bb252 5402__attribute__ (( unused ))
a750fc0b
JM		 5403static void init_proc_7450 (CPUPPCState *env)
5404{
5405 gen_spr_ne_601(env);
5406 gen_spr_7xx(env);
5407 /* Time base */
5408 gen_tbl(env);
5409 /* 74xx specific SPR */
5410 gen_spr_74xx(env);
5411 /* Level 3 cache control */
5412 gen_l3_ctrl(env);
4e777442
JM		 5413 /* L3ITCR1 */
5414 /* XXX : not implemented */
5415 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5416 SPR_NOACCESS, SPR_NOACCESS,
5417 &spr_read_generic, &spr_write_generic,
5418 0x00000000);
5419 /* L3ITCR2 */
5420 /* XXX : not implemented */
5421 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5422 SPR_NOACCESS, SPR_NOACCESS,
5423 &spr_read_generic, &spr_write_generic,
5424 0x00000000);
5425 /* L3ITCR3 */
5426 /* XXX : not implemented */
5427 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5428 SPR_NOACCESS, SPR_NOACCESS,
5429 &spr_read_generic, &spr_write_generic,
5430 0x00000000);
5431 /* L3OHCR */
5432 /* XXX : not implemented */
5433 spr_register(env, SPR_L3OHCR, "L3OHCR",
5434 SPR_NOACCESS, SPR_NOACCESS,
5435 &spr_read_generic, &spr_write_generic,
5436 0x00000000);
5437 /* XXX : not implemented */
5438 spr_register(env, SPR_UBAMR, "UBAMR",
5439 &spr_read_ureg, SPR_NOACCESS,
5440 &spr_read_ureg, SPR_NOACCESS,
5441 0x00000000);
a750fc0b
JM		 5442 /* LDSTCR */
5443 /* XXX : not implemented */
5444 spr_register(env, SPR_LDSTCR, "LDSTCR",
5445 SPR_NOACCESS, SPR_NOACCESS,
5446 &spr_read_generic, &spr_write_generic,
5447 0x00000000);
5448 /* ICTRL */
5449 /* XXX : not implemented */
5450 spr_register(env, SPR_ICTRL, "ICTRL",
5451 SPR_NOACCESS, SPR_NOACCESS,
5452 &spr_read_generic, &spr_write_generic,
5453 0x00000000);
5454 /* MSSSR0 */
578bb252 5455 /* XXX : not implemented */
a750fc0b
JM		 5456 spr_register(env, SPR_MSSSR0, "MSSSR0",
5457 SPR_NOACCESS, SPR_NOACCESS,
5458 &spr_read_generic, &spr_write_generic,
5459 0x00000000);
5460 /* PMC */
5461 /* XXX : not implemented */
5462 spr_register(env, SPR_PMC5, "PMC5",
5463 SPR_NOACCESS, SPR_NOACCESS,
5464 &spr_read_generic, &spr_write_generic,
5465 0x00000000);
578bb252 5466 /* XXX : not implemented */
a750fc0b
JM		 5467 spr_register(env, SPR_UPMC5, "UPMC5",
5468 &spr_read_ureg, SPR_NOACCESS,
5469 &spr_read_ureg, SPR_NOACCESS,
5470 0x00000000);
578bb252 5471 /* XXX : not implemented */
a750fc0b
JM		 5472 spr_register(env, SPR_PMC6, "PMC6",
5473 SPR_NOACCESS, SPR_NOACCESS,
5474 &spr_read_generic, &spr_write_generic,
5475 0x00000000);
578bb252 5476 /* XXX : not implemented */
a750fc0b
JM		 5477 spr_register(env, SPR_UPMC6, "UPMC6",
5478 &spr_read_ureg, SPR_NOACCESS,
5479 &spr_read_ureg, SPR_NOACCESS,
5480 0x00000000);
5481 /* Memory management */
5482 gen_low_BATs(env);
578bb252 5483 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5484 init_excp_7450(env);
d63001d1
JM		 5485 env->dcache_line_size = 32;
5486 env->icache_line_size = 32;
a750fc0b
JM		 5487 /* Allocate hardware IRQ controller */
5488 ppc6xx_irq_init(env);
5489}
a750fc0b
JM		 5490
5491/* PowerPC 7445 (aka G4) */
082c6681
JM		 5492#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5493 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5494 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5495 PPC_FLOAT_STFIWX | \
5496 PPC_CACHE | PPC_CACHE_ICBI | \
5497 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5498 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5499 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5500 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5501 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5502 PPC_ALTIVEC)
5503#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5504#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5505#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5506#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 5507#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 5508#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5509 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5510 POWERPC_FLAG_BUS_CLK)
4e777442 5511#define check_pow_7445 check_pow_hid0_74xx
a750fc0b 5512
578bb252 5513__attribute__ (( unused ))
a750fc0b
JM		 5514static void init_proc_7445 (CPUPPCState *env)
5515{
5516 gen_spr_ne_601(env);
5517 gen_spr_7xx(env);
5518 /* Time base */
5519 gen_tbl(env);
5520 /* 74xx specific SPR */
5521 gen_spr_74xx(env);
5522 /* LDSTCR */
5523 /* XXX : not implemented */
5524 spr_register(env, SPR_LDSTCR, "LDSTCR",
5525 SPR_NOACCESS, SPR_NOACCESS,
5526 &spr_read_generic, &spr_write_generic,
5527 0x00000000);
5528 /* ICTRL */
5529 /* XXX : not implemented */
5530 spr_register(env, SPR_ICTRL, "ICTRL",
5531 SPR_NOACCESS, SPR_NOACCESS,
5532 &spr_read_generic, &spr_write_generic,
5533 0x00000000);
5534 /* MSSSR0 */
578bb252 5535 /* XXX : not implemented */
a750fc0b
JM		 5536 spr_register(env, SPR_MSSSR0, "MSSSR0",
5537 SPR_NOACCESS, SPR_NOACCESS,
5538 &spr_read_generic, &spr_write_generic,
5539 0x00000000);
5540 /* PMC */
5541 /* XXX : not implemented */
5542 spr_register(env, SPR_PMC5, "PMC5",
5543 SPR_NOACCESS, SPR_NOACCESS,
5544 &spr_read_generic, &spr_write_generic,
5545 0x00000000);
578bb252 5546 /* XXX : not implemented */
a750fc0b
JM		 5547 spr_register(env, SPR_UPMC5, "UPMC5",
5548 &spr_read_ureg, SPR_NOACCESS,
5549 &spr_read_ureg, SPR_NOACCESS,
5550 0x00000000);
578bb252 5551 /* XXX : not implemented */
a750fc0b
JM		 5552 spr_register(env, SPR_PMC6, "PMC6",
5553 SPR_NOACCESS, SPR_NOACCESS,
5554 &spr_read_generic, &spr_write_generic,
5555 0x00000000);
578bb252 5556 /* XXX : not implemented */
a750fc0b
JM		 5557 spr_register(env, SPR_UPMC6, "UPMC6",
5558 &spr_read_ureg, SPR_NOACCESS,
5559 &spr_read_ureg, SPR_NOACCESS,
5560 0x00000000);
5561 /* SPRGs */
5562 spr_register(env, SPR_SPRG4, "SPRG4",
5563 SPR_NOACCESS, SPR_NOACCESS,
5564 &spr_read_generic, &spr_write_generic,
5565 0x00000000);
5566 spr_register(env, SPR_USPRG4, "USPRG4",
5567 &spr_read_ureg, SPR_NOACCESS,
5568 &spr_read_ureg, SPR_NOACCESS,
5569 0x00000000);
5570 spr_register(env, SPR_SPRG5, "SPRG5",
5571 SPR_NOACCESS, SPR_NOACCESS,
5572 &spr_read_generic, &spr_write_generic,
5573 0x00000000);
5574 spr_register(env, SPR_USPRG5, "USPRG5",
5575 &spr_read_ureg, SPR_NOACCESS,
5576 &spr_read_ureg, SPR_NOACCESS,
5577 0x00000000);
5578 spr_register(env, SPR_SPRG6, "SPRG6",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_generic,
5581 0x00000000);
5582 spr_register(env, SPR_USPRG6, "USPRG6",
5583 &spr_read_ureg, SPR_NOACCESS,
5584 &spr_read_ureg, SPR_NOACCESS,
5585 0x00000000);
5586 spr_register(env, SPR_SPRG7, "SPRG7",
5587 SPR_NOACCESS, SPR_NOACCESS,
5588 &spr_read_generic, &spr_write_generic,
5589 0x00000000);
5590 spr_register(env, SPR_USPRG7, "USPRG7",
5591 &spr_read_ureg, SPR_NOACCESS,
5592 &spr_read_ureg, SPR_NOACCESS,
5593 0x00000000);
5594 /* Memory management */
5595 gen_low_BATs(env);
5596 gen_high_BATs(env);
578bb252 5597 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5598 init_excp_7450(env);
d63001d1
JM		 5599 env->dcache_line_size = 32;
5600 env->icache_line_size = 32;
a750fc0b
JM		 5601 /* Allocate hardware IRQ controller */
5602 ppc6xx_irq_init(env);
5603}
a750fc0b
JM		 5604
5605/* PowerPC 7455 (aka G4) */
082c6681
JM		 5606#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5607 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5608 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5609 PPC_FLOAT_STFIWX | \
5610 PPC_CACHE | PPC_CACHE_ICBI | \
5611 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5612 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5613 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5614 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5615 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5616 PPC_ALTIVEC)
5617#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5618#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5619#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5620#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 5621#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 5622#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5623 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5624 POWERPC_FLAG_BUS_CLK)
4e777442 5625#define check_pow_7455 check_pow_hid0_74xx
a750fc0b 5626
578bb252 5627__attribute__ (( unused ))
a750fc0b
JM		 5628static void init_proc_7455 (CPUPPCState *env)
5629{
5630 gen_spr_ne_601(env);
5631 gen_spr_7xx(env);
5632 /* Time base */
5633 gen_tbl(env);
5634 /* 74xx specific SPR */
5635 gen_spr_74xx(env);
5636 /* Level 3 cache control */
5637 gen_l3_ctrl(env);
5638 /* LDSTCR */
5639 /* XXX : not implemented */
5640 spr_register(env, SPR_LDSTCR, "LDSTCR",
5641 SPR_NOACCESS, SPR_NOACCESS,
5642 &spr_read_generic, &spr_write_generic,
5643 0x00000000);
5644 /* ICTRL */
5645 /* XXX : not implemented */
5646 spr_register(env, SPR_ICTRL, "ICTRL",
5647 SPR_NOACCESS, SPR_NOACCESS,
5648 &spr_read_generic, &spr_write_generic,
5649 0x00000000);
5650 /* MSSSR0 */
578bb252 5651 /* XXX : not implemented */
a750fc0b
JM		 5652 spr_register(env, SPR_MSSSR0, "MSSSR0",
5653 SPR_NOACCESS, SPR_NOACCESS,
5654 &spr_read_generic, &spr_write_generic,
5655 0x00000000);
5656 /* PMC */
5657 /* XXX : not implemented */
5658 spr_register(env, SPR_PMC5, "PMC5",
5659 SPR_NOACCESS, SPR_NOACCESS,
5660 &spr_read_generic, &spr_write_generic,
5661 0x00000000);
578bb252 5662 /* XXX : not implemented */
a750fc0b
JM		 5663 spr_register(env, SPR_UPMC5, "UPMC5",
5664 &spr_read_ureg, SPR_NOACCESS,
5665 &spr_read_ureg, SPR_NOACCESS,
5666 0x00000000);
578bb252 5667 /* XXX : not implemented */
a750fc0b
JM		 5668 spr_register(env, SPR_PMC6, "PMC6",
5669 SPR_NOACCESS, SPR_NOACCESS,
5670 &spr_read_generic, &spr_write_generic,
5671 0x00000000);
578bb252 5672 /* XXX : not implemented */
a750fc0b
JM		 5673 spr_register(env, SPR_UPMC6, "UPMC6",
5674 &spr_read_ureg, SPR_NOACCESS,
5675 &spr_read_ureg, SPR_NOACCESS,
5676 0x00000000);
5677 /* SPRGs */
5678 spr_register(env, SPR_SPRG4, "SPRG4",
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_generic, &spr_write_generic,
5681 0x00000000);
5682 spr_register(env, SPR_USPRG4, "USPRG4",
5683 &spr_read_ureg, SPR_NOACCESS,
5684 &spr_read_ureg, SPR_NOACCESS,
5685 0x00000000);
5686 spr_register(env, SPR_SPRG5, "SPRG5",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic,
5689 0x00000000);
5690 spr_register(env, SPR_USPRG5, "USPRG5",
5691 &spr_read_ureg, SPR_NOACCESS,
5692 &spr_read_ureg, SPR_NOACCESS,
5693 0x00000000);
5694 spr_register(env, SPR_SPRG6, "SPRG6",
5695 SPR_NOACCESS, SPR_NOACCESS,
5696 &spr_read_generic, &spr_write_generic,
5697 0x00000000);
5698 spr_register(env, SPR_USPRG6, "USPRG6",
5699 &spr_read_ureg, SPR_NOACCESS,
5700 &spr_read_ureg, SPR_NOACCESS,
5701 0x00000000);
5702 spr_register(env, SPR_SPRG7, "SPRG7",
5703 SPR_NOACCESS, SPR_NOACCESS,
5704 &spr_read_generic, &spr_write_generic,
5705 0x00000000);
5706 spr_register(env, SPR_USPRG7, "USPRG7",
5707 &spr_read_ureg, SPR_NOACCESS,
5708 &spr_read_ureg, SPR_NOACCESS,
5709 0x00000000);
5710 /* Memory management */
5711 gen_low_BATs(env);
5712 gen_high_BATs(env);
578bb252 5713 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5714 init_excp_7450(env);
d63001d1
JM		 5715 env->dcache_line_size = 32;
5716 env->icache_line_size = 32;
a750fc0b
JM		 5717 /* Allocate hardware IRQ controller */
5718 ppc6xx_irq_init(env);
5719}
a750fc0b 5720
4e777442
JM		 5721/* PowerPC 7457 (aka G4) */
5722#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5723 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5724 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5725 PPC_FLOAT_STFIWX | \
5726 PPC_CACHE | PPC_CACHE_ICBI | \
5727 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5728 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5729 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5730 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5731 PPC_SEGMENT | PPC_EXTERN | \
5732 PPC_ALTIVEC)
5733#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5734#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5735#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5736#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5737#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5738#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5739 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5740 POWERPC_FLAG_BUS_CLK)
5741#define check_pow_7457 check_pow_hid0_74xx
5742
5743__attribute__ (( unused ))
5744static void init_proc_7457 (CPUPPCState *env)
5745{
5746 gen_spr_ne_601(env);
5747 gen_spr_7xx(env);
5748 /* Time base */
5749 gen_tbl(env);
5750 /* 74xx specific SPR */
5751 gen_spr_74xx(env);
5752 /* Level 3 cache control */
5753 gen_l3_ctrl(env);
5754 /* L3ITCR1 */
5755 /* XXX : not implemented */
5756 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5757 SPR_NOACCESS, SPR_NOACCESS,
5758 &spr_read_generic, &spr_write_generic,
5759 0x00000000);
5760 /* L3ITCR2 */
5761 /* XXX : not implemented */
5762 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5763 SPR_NOACCESS, SPR_NOACCESS,
5764 &spr_read_generic, &spr_write_generic,
5765 0x00000000);
5766 /* L3ITCR3 */
5767 /* XXX : not implemented */
5768 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5769 SPR_NOACCESS, SPR_NOACCESS,
5770 &spr_read_generic, &spr_write_generic,
5771 0x00000000);
5772 /* L3OHCR */
5773 /* XXX : not implemented */
5774 spr_register(env, SPR_L3OHCR, "L3OHCR",
5775 SPR_NOACCESS, SPR_NOACCESS,
5776 &spr_read_generic, &spr_write_generic,
5777 0x00000000);
5778 /* LDSTCR */
5779 /* XXX : not implemented */
5780 spr_register(env, SPR_LDSTCR, "LDSTCR",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 0x00000000);
5784 /* ICTRL */
5785 /* XXX : not implemented */
5786 spr_register(env, SPR_ICTRL, "ICTRL",
5787 SPR_NOACCESS, SPR_NOACCESS,
5788 &spr_read_generic, &spr_write_generic,
5789 0x00000000);
5790 /* MSSSR0 */
5791 /* XXX : not implemented */
5792 spr_register(env, SPR_MSSSR0, "MSSSR0",
5793 SPR_NOACCESS, SPR_NOACCESS,
5794 &spr_read_generic, &spr_write_generic,
5795 0x00000000);
5796 /* PMC */
5797 /* XXX : not implemented */
5798 spr_register(env, SPR_PMC5, "PMC5",
5799 SPR_NOACCESS, SPR_NOACCESS,
5800 &spr_read_generic, &spr_write_generic,
5801 0x00000000);
5802 /* XXX : not implemented */
5803 spr_register(env, SPR_UPMC5, "UPMC5",
5804 &spr_read_ureg, SPR_NOACCESS,
5805 &spr_read_ureg, SPR_NOACCESS,
5806 0x00000000);
5807 /* XXX : not implemented */
5808 spr_register(env, SPR_PMC6, "PMC6",
5809 SPR_NOACCESS, SPR_NOACCESS,
5810 &spr_read_generic, &spr_write_generic,
5811 0x00000000);
5812 /* XXX : not implemented */
5813 spr_register(env, SPR_UPMC6, "UPMC6",
5814 &spr_read_ureg, SPR_NOACCESS,
5815 &spr_read_ureg, SPR_NOACCESS,
5816 0x00000000);
5817 /* SPRGs */
5818 spr_register(env, SPR_SPRG4, "SPRG4",
5819 SPR_NOACCESS, SPR_NOACCESS,
5820 &spr_read_generic, &spr_write_generic,
5821 0x00000000);
5822 spr_register(env, SPR_USPRG4, "USPRG4",
5823 &spr_read_ureg, SPR_NOACCESS,
5824 &spr_read_ureg, SPR_NOACCESS,
5825 0x00000000);
5826 spr_register(env, SPR_SPRG5, "SPRG5",
5827 SPR_NOACCESS, SPR_NOACCESS,
5828 &spr_read_generic, &spr_write_generic,
5829 0x00000000);
5830 spr_register(env, SPR_USPRG5, "USPRG5",
5831 &spr_read_ureg, SPR_NOACCESS,
5832 &spr_read_ureg, SPR_NOACCESS,
5833 0x00000000);
5834 spr_register(env, SPR_SPRG6, "SPRG6",
5835 SPR_NOACCESS, SPR_NOACCESS,
5836 &spr_read_generic, &spr_write_generic,
5837 0x00000000);
5838 spr_register(env, SPR_USPRG6, "USPRG6",
5839 &spr_read_ureg, SPR_NOACCESS,
5840 &spr_read_ureg, SPR_NOACCESS,
5841 0x00000000);
5842 spr_register(env, SPR_SPRG7, "SPRG7",
5843 SPR_NOACCESS, SPR_NOACCESS,
5844 &spr_read_generic, &spr_write_generic,
5845 0x00000000);
5846 spr_register(env, SPR_USPRG7, "USPRG7",
5847 &spr_read_ureg, SPR_NOACCESS,
5848 &spr_read_ureg, SPR_NOACCESS,
5849 0x00000000);
5850 /* Memory management */
5851 gen_low_BATs(env);
5852 gen_high_BATs(env);
5853 gen_74xx_soft_tlb(env, 128, 2);
5854 init_excp_7450(env);
5855 env->dcache_line_size = 32;
5856 env->icache_line_size = 32;
5857 /* Allocate hardware IRQ controller */
5858 ppc6xx_irq_init(env);
5859}
5860
a750fc0b
JM		 5861#if defined (TARGET_PPC64)
5862/* PowerPC 970 */
082c6681
JM		 5863#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5864 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5865 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5866 PPC_FLOAT_STFIWX | \
5867 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5868 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5869 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5870 PPC_64B | PPC_ALTIVEC | \
12de9a39 5871 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5872#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 5873#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 5874//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
5875#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 5876#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 5877#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5878 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5879 POWERPC_FLAG_BUS_CLK)
a750fc0b 5880
417bf010
JM		 5881#if defined(CONFIG_USER_ONLY)
5882#define POWERPC970_HID5_INIT 0x00000080
5883#else
5884#define POWERPC970_HID5_INIT 0x00000000
5885#endif
5886
2f462816
JM		 5887static int check_pow_970 (CPUPPCState *env)
5888{
5889 if (env->spr[SPR_HID0] & 0x00600000)
5890 return 1;
5891
5892 return 0;
5893}
5894
a750fc0b
JM		 5895static void init_proc_970 (CPUPPCState *env)
5896{
5897 gen_spr_ne_601(env);
5898 gen_spr_7xx(env);
5899 /* Time base */
5900 gen_tbl(env);
5901 /* Hardware implementation registers */
5902 /* XXX : not implemented */
5903 spr_register(env, SPR_HID0, "HID0",
5904 SPR_NOACCESS, SPR_NOACCESS,
06403421 5905 &spr_read_generic, &spr_write_clear,
d63001d1 5906 0x60000000);
a750fc0b
JM		 5907 /* XXX : not implemented */
5908 spr_register(env, SPR_HID1, "HID1",
5909 SPR_NOACCESS, SPR_NOACCESS,
5910 &spr_read_generic, &spr_write_generic,
5911 0x00000000);
5912 /* XXX : not implemented */
bd928eba 5913 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5914 SPR_NOACCESS, SPR_NOACCESS,
5915 &spr_read_generic, &spr_write_generic,
5916 0x00000000);
e57448f1
JM		 5917 /* XXX : not implemented */
5918 spr_register(env, SPR_970_HID5, "HID5",
5919 SPR_NOACCESS, SPR_NOACCESS,
5920 &spr_read_generic, &spr_write_generic,
417bf010 5921 POWERPC970_HID5_INIT);
bd928eba
JM		 5922 /* XXX : not implemented */
5923 spr_register(env, SPR_L2CR, "L2CR",
5924 SPR_NOACCESS, SPR_NOACCESS,
5925 &spr_read_generic, &spr_write_generic,
5926 0x00000000);
a750fc0b
JM		 5927 /* Memory management */
5928 /* XXX: not correct */
5929 gen_low_BATs(env);
12de9a39
JM		 5930 /* XXX : not implemented */
5931 spr_register(env, SPR_MMUCFG, "MMUCFG",
5932 SPR_NOACCESS, SPR_NOACCESS,
5933 &spr_read_generic, SPR_NOACCESS,
5934 0x00000000); /* TOFIX */
5935 /* XXX : not implemented */
5936 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5937 SPR_NOACCESS, SPR_NOACCESS,
5938 &spr_read_generic, &spr_write_generic,
5939 0x00000000); /* TOFIX */
5940 spr_register(env, SPR_HIOR, "SPR_HIOR",
5941 SPR_NOACCESS, SPR_NOACCESS,
5942 &spr_read_generic, &spr_write_generic,
5943 0xFFF00000); /* XXX: This is a hack */
f2e63a42 5944#if !defined(CONFIG_USER_ONLY)
12de9a39 5945 env->slb_nr = 32;
f2e63a42 5946#endif
e1833e1f 5947 init_excp_970(env);
d63001d1
JM		 5948 env->dcache_line_size = 128;
5949 env->icache_line_size = 128;
a750fc0b
JM		 5950 /* Allocate hardware IRQ controller */
5951 ppc970_irq_init(env);
cf8358c8
AJ		 5952 /* Can't find information on what this should be on reset. This
5953 * value is the one used by 74xx processors. */
5954 vscr_init(env, 0x00010000);
a750fc0b 5955}
a750fc0b
JM		 5956
5957/* PowerPC 970FX (aka G5) */
082c6681
JM		 5958#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5959 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5960 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5961 PPC_FLOAT_STFIWX | \
5962 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5963 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5964 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5965 PPC_64B | PPC_ALTIVEC | \
12de9a39 5966 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5967#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 5968#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 5969#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
5970#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 5971#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 5972#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5973 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5974 POWERPC_FLAG_BUS_CLK)
a750fc0b 5975
2f462816
JM		 5976static int check_pow_970FX (CPUPPCState *env)
5977{
5978 if (env->spr[SPR_HID0] & 0x00600000)
5979 return 1;
5980
5981 return 0;
5982}
5983
a750fc0b
JM		 5984static void init_proc_970FX (CPUPPCState *env)
5985{
5986 gen_spr_ne_601(env);
5987 gen_spr_7xx(env);
5988 /* Time base */
5989 gen_tbl(env);
5990 /* Hardware implementation registers */
5991 /* XXX : not implemented */
5992 spr_register(env, SPR_HID0, "HID0",
5993 SPR_NOACCESS, SPR_NOACCESS,
06403421 5994 &spr_read_generic, &spr_write_clear,
d63001d1 5995 0x60000000);
a750fc0b
JM		 5996 /* XXX : not implemented */
5997 spr_register(env, SPR_HID1, "HID1",
5998 SPR_NOACCESS, SPR_NOACCESS,
5999 &spr_read_generic, &spr_write_generic,
6000 0x00000000);
6001 /* XXX : not implemented */
bd928eba 6002 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6003 SPR_NOACCESS, SPR_NOACCESS,
6004 &spr_read_generic, &spr_write_generic,
6005 0x00000000);
d63001d1
JM		 6006 /* XXX : not implemented */
6007 spr_register(env, SPR_970_HID5, "HID5",
6008 SPR_NOACCESS, SPR_NOACCESS,
6009 &spr_read_generic, &spr_write_generic,
417bf010 6010 POWERPC970_HID5_INIT);
bd928eba
JM		 6011 /* XXX : not implemented */
6012 spr_register(env, SPR_L2CR, "L2CR",
6013 SPR_NOACCESS, SPR_NOACCESS,
6014 &spr_read_generic, &spr_write_generic,
6015 0x00000000);
a750fc0b
JM		 6016 /* Memory management */
6017 /* XXX: not correct */
6018 gen_low_BATs(env);
12de9a39
JM		 6019 /* XXX : not implemented */
6020 spr_register(env, SPR_MMUCFG, "MMUCFG",
6021 SPR_NOACCESS, SPR_NOACCESS,
6022 &spr_read_generic, SPR_NOACCESS,
6023 0x00000000); /* TOFIX */
6024 /* XXX : not implemented */
6025 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6026 SPR_NOACCESS, SPR_NOACCESS,
6027 &spr_read_generic, &spr_write_generic,
6028 0x00000000); /* TOFIX */
6029 spr_register(env, SPR_HIOR, "SPR_HIOR",
6030 SPR_NOACCESS, SPR_NOACCESS,
6031 &spr_read_generic, &spr_write_generic,
6032 0xFFF00000); /* XXX: This is a hack */
f2e63a42 6033#if !defined(CONFIG_USER_ONLY)
12de9a39 6034 env->slb_nr = 32;
f2e63a42 6035#endif
e1833e1f 6036 init_excp_970(env);
d63001d1
JM		 6037 env->dcache_line_size = 128;
6038 env->icache_line_size = 128;
a750fc0b
JM		 6039 /* Allocate hardware IRQ controller */
6040 ppc970_irq_init(env);
cf8358c8
AJ		 6041 /* Can't find information on what this should be on reset. This
6042 * value is the one used by 74xx processors. */
6043 vscr_init(env, 0x00010000);
a750fc0b 6044}
a750fc0b
JM		 6045
6046/* PowerPC 970 GX */
082c6681
JM		 6047#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6048 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6049 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6050 PPC_FLOAT_STFIWX | \
6051 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6052 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6053 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6054 PPC_64B | PPC_ALTIVEC | \
12de9a39 6055 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 6056#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6057#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6058#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6059#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6060#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6061#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6062 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6063 POWERPC_FLAG_BUS_CLK)
a750fc0b 6064
2f462816
JM		 6065static int check_pow_970GX (CPUPPCState *env)
6066{
6067 if (env->spr[SPR_HID0] & 0x00600000)
6068 return 1;
6069
6070 return 0;
6071}
6072
a750fc0b
JM		 6073static void init_proc_970GX (CPUPPCState *env)
6074{
6075 gen_spr_ne_601(env);
6076 gen_spr_7xx(env);
6077 /* Time base */
6078 gen_tbl(env);
6079 /* Hardware implementation registers */
6080 /* XXX : not implemented */
6081 spr_register(env, SPR_HID0, "HID0",
6082 SPR_NOACCESS, SPR_NOACCESS,
06403421 6083 &spr_read_generic, &spr_write_clear,
d63001d1 6084 0x60000000);
a750fc0b
JM		 6085 /* XXX : not implemented */
6086 spr_register(env, SPR_HID1, "HID1",
6087 SPR_NOACCESS, SPR_NOACCESS,
6088 &spr_read_generic, &spr_write_generic,
6089 0x00000000);
6090 /* XXX : not implemented */
bd928eba 6091 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6092 SPR_NOACCESS, SPR_NOACCESS,
6093 &spr_read_generic, &spr_write_generic,
6094 0x00000000);
d63001d1
JM		 6095 /* XXX : not implemented */
6096 spr_register(env, SPR_970_HID5, "HID5",
6097 SPR_NOACCESS, SPR_NOACCESS,
6098 &spr_read_generic, &spr_write_generic,
417bf010 6099 POWERPC970_HID5_INIT);
bd928eba
JM		 6100 /* XXX : not implemented */
6101 spr_register(env, SPR_L2CR, "L2CR",
6102 SPR_NOACCESS, SPR_NOACCESS,
6103 &spr_read_generic, &spr_write_generic,
6104 0x00000000);
a750fc0b
JM		 6105 /* Memory management */
6106 /* XXX: not correct */
6107 gen_low_BATs(env);
12de9a39
JM		 6108 /* XXX : not implemented */
6109 spr_register(env, SPR_MMUCFG, "MMUCFG",
6110 SPR_NOACCESS, SPR_NOACCESS,
6111 &spr_read_generic, SPR_NOACCESS,
6112 0x00000000); /* TOFIX */
6113 /* XXX : not implemented */
6114 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6115 SPR_NOACCESS, SPR_NOACCESS,
6116 &spr_read_generic, &spr_write_generic,
6117 0x00000000); /* TOFIX */
6118 spr_register(env, SPR_HIOR, "SPR_HIOR",
6119 SPR_NOACCESS, SPR_NOACCESS,
6120 &spr_read_generic, &spr_write_generic,
6121 0xFFF00000); /* XXX: This is a hack */
f2e63a42 6122#if !defined(CONFIG_USER_ONLY)
12de9a39 6123 env->slb_nr = 32;
f2e63a42 6124#endif
e1833e1f 6125 init_excp_970(env);
d63001d1
JM		 6126 env->dcache_line_size = 128;
6127 env->icache_line_size = 128;
a750fc0b
JM		 6128 /* Allocate hardware IRQ controller */
6129 ppc970_irq_init(env);
cf8358c8
AJ		 6130 /* Can't find information on what this should be on reset. This
6131 * value is the one used by 74xx processors. */
6132 vscr_init(env, 0x00010000);
a750fc0b 6133}
a750fc0b 6134
2f462816 6135/* PowerPC 970 MP */
082c6681
JM		 6136#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6137 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6138 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6139 PPC_FLOAT_STFIWX | \
6140 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6141 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6142 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 6143 PPC_64B | PPC_ALTIVEC | \
6144 PPC_SEGMENT_64B | PPC_SLBI)
6145#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6146#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6147#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6148#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6149#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6150#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6151 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6152 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6153
6154static int check_pow_970MP (CPUPPCState *env)
6155{
6156 if (env->spr[SPR_HID0] & 0x01C00000)
6157 return 1;
6158
6159 return 0;
6160}
6161
6162static void init_proc_970MP (CPUPPCState *env)
6163{
6164 gen_spr_ne_601(env);
6165 gen_spr_7xx(env);
6166 /* Time base */
6167 gen_tbl(env);
6168 /* Hardware implementation registers */
6169 /* XXX : not implemented */
6170 spr_register(env, SPR_HID0, "HID0",
6171 SPR_NOACCESS, SPR_NOACCESS,
6172 &spr_read_generic, &spr_write_clear,
6173 0x60000000);
6174 /* XXX : not implemented */
6175 spr_register(env, SPR_HID1, "HID1",
6176 SPR_NOACCESS, SPR_NOACCESS,
6177 &spr_read_generic, &spr_write_generic,
6178 0x00000000);
6179 /* XXX : not implemented */
bd928eba 6180 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6181 SPR_NOACCESS, SPR_NOACCESS,
6182 &spr_read_generic, &spr_write_generic,
6183 0x00000000);
6184 /* XXX : not implemented */
6185 spr_register(env, SPR_970_HID5, "HID5",
6186 SPR_NOACCESS, SPR_NOACCESS,
6187 &spr_read_generic, &spr_write_generic,
6188 POWERPC970_HID5_INIT);
bd928eba
JM		 6189 /* XXX : not implemented */
6190 spr_register(env, SPR_L2CR, "L2CR",
6191 SPR_NOACCESS, SPR_NOACCESS,
6192 &spr_read_generic, &spr_write_generic,
6193 0x00000000);
2f462816
JM		 6194 /* Memory management */
6195 /* XXX: not correct */
6196 gen_low_BATs(env);
6197 /* XXX : not implemented */
6198 spr_register(env, SPR_MMUCFG, "MMUCFG",
6199 SPR_NOACCESS, SPR_NOACCESS,
6200 &spr_read_generic, SPR_NOACCESS,
6201 0x00000000); /* TOFIX */
6202 /* XXX : not implemented */
6203 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6204 SPR_NOACCESS, SPR_NOACCESS,
6205 &spr_read_generic, &spr_write_generic,
6206 0x00000000); /* TOFIX */
6207 spr_register(env, SPR_HIOR, "SPR_HIOR",
6208 SPR_NOACCESS, SPR_NOACCESS,
6209 &spr_read_generic, &spr_write_generic,
6210 0xFFF00000); /* XXX: This is a hack */
2f462816
JM		 6211#if !defined(CONFIG_USER_ONLY)
6212 env->slb_nr = 32;
6213#endif
6214 init_excp_970(env);
6215 env->dcache_line_size = 128;
6216 env->icache_line_size = 128;
6217 /* Allocate hardware IRQ controller */
6218 ppc970_irq_init(env);
cf8358c8
AJ		 6219 /* Can't find information on what this should be on reset. This
6220 * value is the one used by 74xx processors. */
6221 vscr_init(env, 0x00010000);
2f462816
JM		 6222}
6223
a750fc0b 6224/* PowerPC 620 */
082c6681
JM		 6225#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6226 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6227 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6228 PPC_FLOAT_STFIWX | \
6229 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6230 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6231 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6232 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6233 PPC_64B | PPC_SLBI)
add78955
JM		 6234#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6235//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 6236#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 6237#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 6238#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 6239#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 6240 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 6241#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 6242
578bb252 6243__attribute__ (( unused ))
a750fc0b
JM		 6244static void init_proc_620 (CPUPPCState *env)
6245{
6246 gen_spr_ne_601(env);
6247 gen_spr_620(env);
6248 /* Time base */
6249 gen_tbl(env);
6250 /* Hardware implementation registers */
6251 /* XXX : not implemented */
6252 spr_register(env, SPR_HID0, "HID0",
6253 SPR_NOACCESS, SPR_NOACCESS,
6254 &spr_read_generic, &spr_write_generic,
6255 0x00000000);
6256 /* Memory management */
6257 gen_low_BATs(env);
e1833e1f 6258 init_excp_620(env);
d63001d1
JM		 6259 env->dcache_line_size = 64;
6260 env->icache_line_size = 64;
faadf50e
JM		 6261 /* Allocate hardware IRQ controller */
6262 ppc6xx_irq_init(env);
a750fc0b 6263}
a750fc0b
JM		 6264#endif /* defined (TARGET_PPC64) */
6265
6266/* Default 32 bits PowerPC target will be 604 */
6267#define CPU_POWERPC_PPC32 CPU_POWERPC_604
6268#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6269#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6270#define POWERPC_MMU_PPC32 POWERPC_MMU_604
6271#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6272#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 6273#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 6274#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 6275#define check_pow_PPC32 check_pow_604
6276#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 6277
6278/* Default 64 bits PowerPC target will be 970 FX */
6279#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6280#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6281#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6282#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6283#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6284#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 6285#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 6286#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 6287#define check_pow_PPC64 check_pow_970FX
6288#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 6289
6290/* Default PowerPC target will be PowerPC 32 */
6291#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 6292#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6293#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6294#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6295#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6296#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6297#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
237c0af0 6298#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 6299#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
2f462816
JM		 6300#define check_pow_DEFAULT check_pow_PPC64
6301#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 6302#else
d12f4c38
JM		 6303#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6304#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6305#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6306#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6307#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6308#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
237c0af0 6309#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 6310#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
2f462816
JM		 6311#define check_pow_DEFAULT check_pow_PPC32
6312#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 6313#endif
6314
6315/*****************************************************************************/
6316/* PVR definitions for most known PowerPC */
6317enum {
6318 /* PowerPC 401 family */
6319 /* Generic PowerPC 401 */
80d11f44 6320#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 6321 /* PowerPC 401 cores */
80d11f44
JM		 6322 CPU_POWERPC_401A1 = 0x00210000,
6323 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 6324#if 0
80d11f44 6325 CPU_POWERPC_401B3 = xxx,
a750fc0b 6326#endif
80d11f44
JM		 6327 CPU_POWERPC_401C2 = 0x00230000,
6328 CPU_POWERPC_401D2 = 0x00240000,
6329 CPU_POWERPC_401E2 = 0x00250000,
6330 CPU_POWERPC_401F2 = 0x00260000,
6331 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 6332 /* PowerPC 401 microcontrolers */
6333#if 0
80d11f44 6334 CPU_POWERPC_401GF = xxx,
a750fc0b 6335#endif
80d11f44 6336#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 6337 /* IBM Processor for Network Resources */
80d11f44 6338 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 6339#if 0
80d11f44 6340 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 6341#endif
6342 /* PowerPC 403 family */
6343 /* Generic PowerPC 403 */
80d11f44 6344#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 6345 /* PowerPC 403 microcontrollers */
80d11f44
JM		 6346 CPU_POWERPC_403GA = 0x00200011,
6347 CPU_POWERPC_403GB = 0x00200100,
6348 CPU_POWERPC_403GC = 0x00200200,
6349 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 6350#if 0
80d11f44 6351 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 6352#endif
6353 /* PowerPC 405 family */
6354 /* Generic PowerPC 405 */
80d11f44 6355#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 6356 /* PowerPC 405 cores */
6357#if 0
80d11f44 6358 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 6359#endif
6360#if 0
80d11f44 6361 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 6362#endif
6363#if 0
80d11f44 6364 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 6365#endif
6366#if 0
80d11f44 6367 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 6368#endif
6369#if 0
80d11f44 6370 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 6371#endif
6372#if 0
80d11f44 6373 CPU_POWERPC_405C4 = xxx,
a750fc0b 6374#endif
80d11f44 6375 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 6376#if 0
80d11f44 6377 CPU_POWERPC_405D3 = xxx,
a750fc0b 6378#endif
80d11f44 6379 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 6380#if 0
80d11f44 6381 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 6382#endif
6383#if 0
80d11f44 6384 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 6385#endif
6386#if 0
80d11f44 6387 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 6388#endif
6389#if 0
80d11f44 6390 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 6391#endif
6392#if 0
80d11f44 6393 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 6394#endif
6395 /* PowerPC 405 microcontrolers */
6396 /* XXX: missing 0x200108a0 */
80d11f44
JM		 6397#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6398 CPU_POWERPC_405CRa = 0x40110041,
6399 CPU_POWERPC_405CRb = 0x401100C5,
6400 CPU_POWERPC_405CRc = 0x40110145,
6401 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 6402#if 0
80d11f44 6403 CPU_POWERPC_405EXr = xxx,
a750fc0b 6404#endif
80d11f44 6405 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 6406#if 0
80d11f44
JM		 6407 CPU_POWERPC_405FX = xxx,
6408#endif
6409#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6410 CPU_POWERPC_405GPa = 0x40110000,
6411 CPU_POWERPC_405GPb = 0x40110040,
6412 CPU_POWERPC_405GPc = 0x40110082,
6413 CPU_POWERPC_405GPd = 0x401100C4,
6414#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6415 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 6416#if 0
80d11f44 6417 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 6418#endif
6419#if 0
80d11f44 6420 CPU_POWERPC_405L = xxx,
a750fc0b 6421#endif
80d11f44 6422 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 6423#if 0
80d11f44 6424 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 6425#endif
6426#if 0
80d11f44 6427 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 6428#endif
6429#if 0
80d11f44 6430 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 6431#endif
6432 /* IBM network processors */
80d11f44
JM		 6433 CPU_POWERPC_NPE405H = 0x414100C0,
6434 CPU_POWERPC_NPE405H2 = 0x41410140,
6435 CPU_POWERPC_NPE405L = 0x416100C0,
6436 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 6437#if 0
80d11f44 6438 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 6439#endif
6440#if 0
80d11f44 6441 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 6442#endif
6443#if 0
80d11f44 6444 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 6445#endif
6446 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6447#if 0
80d11f44 6448 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 6449#endif
6450#if 0
80d11f44 6451 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 6452#endif
6453#if 0
80d11f44 6454 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 6455#endif
80d11f44 6456 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 6457#if 0
80d11f44 6458 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 6459#endif
6460#if 0
80d11f44 6461 CPU_POWERPC_STB045 = xxx,
a750fc0b 6462#endif
80d11f44
JM		 6463 CPU_POWERPC_STB04 = 0x41810000,
6464 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 6465#if 0
80d11f44 6466 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 6467#endif
6468 /* Xilinx cores */
80d11f44
JM		 6469 CPU_POWERPC_X2VP4 = 0x20010820,
6470#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6471 CPU_POWERPC_X2VP20 = 0x20010860,
6472#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 6473#if 0
80d11f44 6474 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 6475#endif
6476#if 0
80d11f44 6477 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 6478#endif
6479#if 0
80d11f44 6480 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 6481#endif
6482#if 0
80d11f44 6483 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 6484#endif
6485 /* PowerPC 440 family */
6486 /* Generic PowerPC 440 */
80d11f44 6487#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 6488 /* PowerPC 440 cores */
6489#if 0
80d11f44 6490 CPU_POWERPC_440A4 = xxx,
a750fc0b
JM		 6491#endif
6492#if 0
80d11f44 6493 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 6494#endif
6495#if 0
80d11f44 6496 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 6497#endif
6498#if 0
80d11f44 6499 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 6500#endif
6501#if 0
80d11f44 6502 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 6503#endif
6504#if 0
80d11f44 6505 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 6506#endif
6507#if 0
80d11f44 6508 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 6509#endif
6510 /* PowerPC 440 microcontrolers */
80d11f44
JM		 6511#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6512 CPU_POWERPC_440EPa = 0x42221850,
6513 CPU_POWERPC_440EPb = 0x422218D3,
6514#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6515 CPU_POWERPC_440GPb = 0x40120440,
6516 CPU_POWERPC_440GPc = 0x40120481,
6517#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6518#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6519 CPU_POWERPC_440GRX = 0x200008D0,
6520#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6521#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6522 CPU_POWERPC_440GXa = 0x51B21850,
6523 CPU_POWERPC_440GXb = 0x51B21851,
6524 CPU_POWERPC_440GXc = 0x51B21892,
6525 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 6526#if 0
80d11f44 6527 CPU_POWERPC_440S = xxx,
a750fc0b 6528#endif
80d11f44
JM		 6529 CPU_POWERPC_440SP = 0x53221850,
6530 CPU_POWERPC_440SP2 = 0x53221891,
6531 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 6532 /* PowerPC 460 family */
6533#if 0
6534 /* Generic PowerPC 464 */
80d11f44 6535#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 6536#endif
6537 /* PowerPC 464 microcontrolers */
6538#if 0
80d11f44 6539 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 6540#endif
6541#if 0
80d11f44 6542 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 6543#endif
6544 /* Freescale embedded PowerPC cores */
c3e36823 6545 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 6546 CPU_POWERPC_MPC5xx = 0x00020020,
6547#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6548#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6549#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6550#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6551#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6552#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6553#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6554#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6555#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6556#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6557#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6558#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6559#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 6560 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 6561 CPU_POWERPC_MPC8xx = 0x00500000,
6562#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6563#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6564#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6565#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6566#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6567#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6568#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6569#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6570#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6571#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6572#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6573#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6574#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6575#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6576#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 6577 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 6578 CPU_POWERPC_G2 = 0x00810011,
6579 CPU_POWERPC_G2H4 = 0x80811010,
6580 CPU_POWERPC_G2gp = 0x80821010,
6581 CPU_POWERPC_G2ls = 0x90810010,
6582 CPU_POWERPC_MPC603 = 0x00810100,
6583 CPU_POWERPC_G2_HIP3 = 0x00810101,
6584 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 6585 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 6586 CPU_POWERPC_G2LE = 0x80820010,
6587 CPU_POWERPC_G2LEgp = 0x80822010,
6588 CPU_POWERPC_G2LEls = 0xA0822010,
6589 CPU_POWERPC_G2LEgp1 = 0x80822011,
6590 CPU_POWERPC_G2LEgp3 = 0x80822013,
6591 /* MPC52xx microcontrollers */
c3e36823 6592 /* XXX: MPC 5121 ? */
80d11f44
JM		 6593#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6594#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6595#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6596#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6597#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6598#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6599#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6600#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6601 /* MPC82xx microcontrollers */
6602#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6603#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6604#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6605#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6606#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6607#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6608#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6609#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6610#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6611#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6612#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6613#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6614#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6615#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6616#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6617#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6618#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6619#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6620#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6621#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6622#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6623#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6624#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6625#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6626#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6627#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6628#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6629#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6630#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 6631 /* e200 family */
80d11f44
JM		 6632 /* e200 cores */
6633#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 6634#if 0
80d11f44 6635 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 6636#endif
6637#if 0
80d11f44 6638 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 6639#endif
6640#if 0 /* ? */
80d11f44
JM		 6641 CPU_POWERPC_e200z3 = 0x81120000,
6642#endif
6643 CPU_POWERPC_e200z5 = 0x81000000,
6644 CPU_POWERPC_e200z6 = 0x81120000,
6645 /* MPC55xx microcontrollers */
6646#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6647#if 0
6648#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6649#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6650#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6651#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6652#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6653#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6654#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6655#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6656#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6657#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6658#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6659#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6660#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6661#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6662#endif
6663#if 0
6664#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6665#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6666#endif
6667#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6668#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6669#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6670#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6671#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6672#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 6673 /* e300 family */
80d11f44
JM		 6674 /* e300 cores */
6675#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
6676 CPU_POWERPC_e300c1 = 0x00830010,
6677 CPU_POWERPC_e300c2 = 0x00840010,
6678 CPU_POWERPC_e300c3 = 0x00850010,
6679 CPU_POWERPC_e300c4 = 0x00860010,
6680 /* MPC83xx microcontrollers */
6681#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
6682#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
6683#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
6684#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
6685#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
6686#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
6687#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
6688#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
6689#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
6690#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
6691#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
6692#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
6693#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
6694#define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
6695#define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
6696#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
6697#define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
6698#define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
6699#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
6700#define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
6701#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
6702#define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
6703#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
6704#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
6705#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
6706#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
6707#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
6708#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
6709#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
6710#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
a750fc0b 6711 /* e500 family */
80d11f44
JM		 6712 /* e500 cores */
6713#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
bd5ea513 6714#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
80d11f44 6715#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 6716 CPU_POWERPC_e500v1_v10 = 0x80200010,
6717 CPU_POWERPC_e500v1_v20 = 0x80200020,
80d11f44
JM		 6718 CPU_POWERPC_e500v2_v10 = 0x80210010,
6719 CPU_POWERPC_e500v2_v11 = 0x80210011,
6720 CPU_POWERPC_e500v2_v20 = 0x80210020,
6721 CPU_POWERPC_e500v2_v21 = 0x80210021,
6722 CPU_POWERPC_e500v2_v22 = 0x80210022,
6723 CPU_POWERPC_e500v2_v30 = 0x80210030,
6724 /* MPC85xx microcontrollers */
6725#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
6726#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
6727#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
6728#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
6729#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
6730#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
6731#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
bd5ea513
AJ		 6732#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
6733#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
6734#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
80d11f44 6735#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
bd5ea513
AJ		 6736#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
6737#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
80d11f44 6738#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
bd5ea513
AJ		 6739#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
6740#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
80d11f44
JM		 6741#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
6742#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
6743#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
6744#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
6745#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
6746#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
6747#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
6748#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
6749#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
6750#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
6751#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
6752#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
6753#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
6754#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
6755#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
6756#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
6757#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
6758#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
6759#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
6760#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
6761#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
6762#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
6763#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
6764#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
6765#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
6766#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
6767#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
6768#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
6769#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
6770#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
6771#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
6772#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
6773#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
6774#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
6775#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
6776#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
6777#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
6778#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
6779#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
6780#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
6781#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
6782#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
6783#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
6784#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
6785#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
6786#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
6787#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
6788#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
6789#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
6790#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
6791#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
6792#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
6793#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
6794#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 6795 /* e600 family */
80d11f44
JM		 6796 /* e600 cores */
6797 CPU_POWERPC_e600 = 0x80040010,
6798 /* MPC86xx microcontrollers */
6799#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
6800#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
6801#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 6802 /* PowerPC 6xx cores */
80d11f44
JM		 6803#define CPU_POWERPC_601 CPU_POWERPC_601_v2
6804 CPU_POWERPC_601_v0 = 0x00010001,
6805 CPU_POWERPC_601_v1 = 0x00010001,
bd928eba 6806#define CPU_POWERPC_601v CPU_POWERPC_601_v2
80d11f44
JM		 6807 CPU_POWERPC_601_v2 = 0x00010002,
6808 CPU_POWERPC_602 = 0x00050100,
6809 CPU_POWERPC_603 = 0x00030100,
6810#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
6811 CPU_POWERPC_603E_v11 = 0x00060101,
6812 CPU_POWERPC_603E_v12 = 0x00060102,
6813 CPU_POWERPC_603E_v13 = 0x00060103,
6814 CPU_POWERPC_603E_v14 = 0x00060104,
6815 CPU_POWERPC_603E_v22 = 0x00060202,
6816 CPU_POWERPC_603E_v3 = 0x00060300,
6817 CPU_POWERPC_603E_v4 = 0x00060400,
6818 CPU_POWERPC_603E_v41 = 0x00060401,
6819 CPU_POWERPC_603E7t = 0x00071201,
6820 CPU_POWERPC_603E7v = 0x00070100,
6821 CPU_POWERPC_603E7v1 = 0x00070101,
6822 CPU_POWERPC_603E7v2 = 0x00070201,
6823 CPU_POWERPC_603E7 = 0x00070200,
6824 CPU_POWERPC_603P = 0x00070000,
6825#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 6826 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 6827 CPU_POWERPC_604 = 0x00040103,
6828#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 6829 /* XXX: missing 0x00091203 */
6830 /* XXX: missing 0x00092110 */
6831 /* XXX: missing 0x00092120 */
80d11f44
JM		 6832 CPU_POWERPC_604E_v10 = 0x00090100,
6833 CPU_POWERPC_604E_v22 = 0x00090202,
6834 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 6835 /* XXX: missing 0x000a0100 */
6836 /* XXX: missing 0x00093102 */
80d11f44 6837 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 6838#if 0
80d11f44 6839 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 6840#endif
6841 /* PowerPC 740/750 cores (aka G3) */
6842 /* XXX: missing 0x00084202 */
80d11f44 6843#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
bd928eba 6844 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 6845 CPU_POWERPC_7x0_v20 = 0x00080200,
6846 CPU_POWERPC_7x0_v21 = 0x00080201,
6847 CPU_POWERPC_7x0_v22 = 0x00080202,
6848 CPU_POWERPC_7x0_v30 = 0x00080300,
6849 CPU_POWERPC_7x0_v31 = 0x00080301,
6850 CPU_POWERPC_740E = 0x00080100,
bd928eba 6851 CPU_POWERPC_750E = 0x00080200,
80d11f44 6852 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 6853 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 6854#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
6855 CPU_POWERPC_750CL_v10 = 0x00087200,
6856 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
80d11f44 6857#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
bd928eba
JM		 6858 CPU_POWERPC_750CX_v10 = 0x00082100,
6859 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 6860 CPU_POWERPC_750CX_v21 = 0x00082201,
6861 CPU_POWERPC_750CX_v22 = 0x00082202,
6862#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
6863 CPU_POWERPC_750CXE_v21 = 0x00082211,
6864 CPU_POWERPC_750CXE_v22 = 0x00082212,
6865 CPU_POWERPC_750CXE_v23 = 0x00082213,
6866 CPU_POWERPC_750CXE_v24 = 0x00082214,
6867 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 6868 CPU_POWERPC_750CXE_v30 = 0x00082310,
6869 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 6870 CPU_POWERPC_750CXE_v31b = 0x00083311,
6871 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 6872 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 6873#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6874 CPU_POWERPC_750FX_v10 = 0x70000100,
6875 CPU_POWERPC_750FX_v20 = 0x70000200,
6876 CPU_POWERPC_750FX_v21 = 0x70000201,
6877 CPU_POWERPC_750FX_v22 = 0x70000202,
6878 CPU_POWERPC_750FX_v23 = 0x70000203,
6879 CPU_POWERPC_750GL = 0x70020102,
6880#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
6881 CPU_POWERPC_750GX_v10 = 0x70020100,
6882 CPU_POWERPC_750GX_v11 = 0x70020101,
6883 CPU_POWERPC_750GX_v12 = 0x70020102,
6884#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
bd928eba
JM		 6885 CPU_POWERPC_750L_v20 = 0x00088200,
6886 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 6887 CPU_POWERPC_750L_v22 = 0x00088202,
6888 CPU_POWERPC_750L_v30 = 0x00088300,
6889 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 6890 /* PowerPC 745/755 cores */
80d11f44
JM		 6891#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
6892 CPU_POWERPC_7x5_v10 = 0x00083100,
6893 CPU_POWERPC_7x5_v11 = 0x00083101,
6894 CPU_POWERPC_7x5_v20 = 0x00083200,
6895 CPU_POWERPC_7x5_v21 = 0x00083201,
6896 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
6897 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
6898 CPU_POWERPC_7x5_v24 = 0x00083204,
6899 CPU_POWERPC_7x5_v25 = 0x00083205,
6900 CPU_POWERPC_7x5_v26 = 0x00083206,
6901 CPU_POWERPC_7x5_v27 = 0x00083207,
6902 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 6903#if 0
80d11f44 6904 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 6905#endif
6906 /* PowerPC 74xx cores (aka G4) */
6907 /* XXX: missing 0x000C1101 */
80d11f44
JM		 6908#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
6909 CPU_POWERPC_7400_v10 = 0x000C0100,
6910 CPU_POWERPC_7400_v11 = 0x000C0101,
6911 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 6912 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 6913 CPU_POWERPC_7400_v22 = 0x000C0202,
6914 CPU_POWERPC_7400_v26 = 0x000C0206,
6915 CPU_POWERPC_7400_v27 = 0x000C0207,
6916 CPU_POWERPC_7400_v28 = 0x000C0208,
6917 CPU_POWERPC_7400_v29 = 0x000C0209,
6918#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
6919 CPU_POWERPC_7410_v10 = 0x800C1100,
6920 CPU_POWERPC_7410_v11 = 0x800C1101,
6921 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
6922 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
6923 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
6924#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
6925 CPU_POWERPC_7448_v10 = 0x80040100,
6926 CPU_POWERPC_7448_v11 = 0x80040101,
6927 CPU_POWERPC_7448_v20 = 0x80040200,
6928 CPU_POWERPC_7448_v21 = 0x80040201,
6929#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
6930 CPU_POWERPC_7450_v10 = 0x80000100,
6931 CPU_POWERPC_7450_v11 = 0x80000101,
6932 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 6933 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 6934 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 6935#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
6936 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
6937 /* XXX: this entry might be a bug in some documentation */
6938 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44
JM		 6939#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
6940 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 6941 /* XXX: missing 0x80010200 */
80d11f44
JM		 6942 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
6943 CPU_POWERPC_74x5_v32 = 0x80010302,
6944 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
6945 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
6946#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 6947 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 6948 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 6949 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 6950#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
6951 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
6952 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
6953 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 6954 /* 64 bits PowerPC */
00af685f 6955#if defined(TARGET_PPC64)
80d11f44
JM		 6956 CPU_POWERPC_620 = 0x00140000,
6957 CPU_POWERPC_630 = 0x00400000,
6958 CPU_POWERPC_631 = 0x00410104,
6959 CPU_POWERPC_POWER4 = 0x00350000,
6960 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 6961 /* XXX: missing 0x003A0201 */
80d11f44
JM		 6962 CPU_POWERPC_POWER5 = 0x003A0203,
6963#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
6964 CPU_POWERPC_POWER5P = 0x003B0000,
6965#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
6966 CPU_POWERPC_POWER6 = 0x003E0000,
6967 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
6968 CPU_POWERPC_POWER6A = 0x0F000002,
6969 CPU_POWERPC_970 = 0x00390202,
6970#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
6971 CPU_POWERPC_970FX_v10 = 0x00391100,
6972 CPU_POWERPC_970FX_v20 = 0x003C0200,
6973 CPU_POWERPC_970FX_v21 = 0x003C0201,
6974 CPU_POWERPC_970FX_v30 = 0x003C0300,
6975 CPU_POWERPC_970FX_v31 = 0x003C0301,
6976 CPU_POWERPC_970GX = 0x00450000,
6977#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
6978 CPU_POWERPC_970MP_v10 = 0x00440100,
6979 CPU_POWERPC_970MP_v11 = 0x00440101,
6980#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
6981 CPU_POWERPC_CELL_v10 = 0x00700100,
6982 CPU_POWERPC_CELL_v20 = 0x00700400,
6983 CPU_POWERPC_CELL_v30 = 0x00700500,
6984 CPU_POWERPC_CELL_v31 = 0x00700501,
6985#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
6986 CPU_POWERPC_RS64 = 0x00330000,
6987 CPU_POWERPC_RS64II = 0x00340000,
6988 CPU_POWERPC_RS64III = 0x00360000,
6989 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 6990#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 6991 /* Original POWER */
6992 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
6993 * POWER2 (RIOS2) & RSC2 (P2SC) here
6994 */
6995#if 0
80d11f44 6996 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 6997#endif
6998#if 0
80d11f44 6999 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 7000#endif
7001 /* PA Semi core */
80d11f44 7002 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 7003};
7004
7005/* System version register (used on MPC 8xxx) */
7006enum {
80d11f44
JM		 7007 POWERPC_SVR_NONE = 0x00000000,
7008#define POWERPC_SVR_52xx POWERPC_SVR_5200
7009#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7010 POWERPC_SVR_5200_v10 = 0x80110010,
7011 POWERPC_SVR_5200_v11 = 0x80110011,
7012 POWERPC_SVR_5200_v12 = 0x80110012,
7013#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7014 POWERPC_SVR_5200B_v20 = 0x80110020,
7015 POWERPC_SVR_5200B_v21 = 0x80110021,
7016#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 7017#if 0
80d11f44 7018 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 7019#endif
7020#if 0
80d11f44 7021 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 7022#endif
7023#if 0
80d11f44 7024 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 7025#endif
7026#if 0
80d11f44 7027 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 7028#endif
7029#if 0
80d11f44 7030 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 7031#endif
7032#if 0
80d11f44 7033 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 7034#endif
7035#if 0
80d11f44 7036 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 7037#endif
7038#if 0
80d11f44 7039 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 7040#endif
7041#if 0
80d11f44 7042 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7043#endif
7044#if 0
80d11f44 7045 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7046#endif
7047#if 0
80d11f44 7048 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7049#endif
7050#if 0
80d11f44 7051 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7052#endif
7053#if 0
80d11f44 7054 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7055#endif
7056#if 0
80d11f44 7057 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7058#endif
7059#if 0
80d11f44 7060 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7061#endif
7062#if 0
80d11f44 7063 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7064#endif
7065#if 0
80d11f44 7066 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7067#endif
7068#if 0
80d11f44
JM		 7069 POWERPC_SVR_8323E = xxx,
7070#endif
7071 POWERPC_SVR_8343A = 0x80570030,
7072 POWERPC_SVR_8343EA = 0x80560030,
7073#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7074 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7075 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7076#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7077 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7078 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7079 POWERPC_SVR_8349 = 0x80510010,
7080 POWERPC_SVR_8349A = 0x80510030,
7081 POWERPC_SVR_8349E = 0x80500010,
7082 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7083#if 0
80d11f44 7084 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7085#endif
7086#if 0
80d11f44
JM		 7087 POWERPC_SVR_8360E = xxx,
7088#endif
7089#define POWERPC_SVR_E500 0x40000000
7090 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7091 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7092 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7093 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7094 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7095 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7096#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7097 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7098 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7099#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7100 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7101 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7102#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7103 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7104 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7105 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7106#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7107 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7108 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7109#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7110 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7111 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7112#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7113 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7114 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7115 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7116 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7117#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7118 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7119 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7120 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7121 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7122#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7123 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7124 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7125#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7126 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7127 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7128#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7129 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7130 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7131#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7132 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7133 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7134#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7135 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7136 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7137#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7138 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7139 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7140 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7141 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7142#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7143 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7144 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7145 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7146 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7147#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7148 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7149 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7150#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7151 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7152 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7153#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7154 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7155 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7156 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7157 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7158 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7159 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7160 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7161 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7162 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7163#if 0
80d11f44 7164 POWERPC_SVR_8610 = xxx,
c3e36823 7165#endif
80d11f44
JM		 7166 POWERPC_SVR_8641 = 0x80900021,
7167 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7168};
7169
3fc6c082 7170/*****************************************************************************/
a750fc0b 7171/* PowerPC CPU definitions */
80d11f44 7172#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b
JM		 7173 { \
7174 .name = _name, \
7175 .pvr = _pvr, \
80d11f44 7176 .svr = _svr, \
a750fc0b
JM		 7177 .insns_flags = glue(POWERPC_INSNS_,_type), \
7178 .msr_mask = glue(POWERPC_MSRM_,_type), \
7179 .mmu_model = glue(POWERPC_MMU_,_type), \
7180 .excp_model = glue(POWERPC_EXCP_,_type), \
7181 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 7182 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 7183 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b 7184 .init_proc = &glue(init_proc_,_type), \
2f462816 7185 .check_pow = &glue(check_pow_,_type), \
a750fc0b 7186 }
80d11f44
JM		 7187#define POWERPC_DEF(_name, _pvr, _type) \
7188POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7189
ee4e83ed 7190static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 7191 /* Embedded PowerPC */
7192 /* PowerPC 401 family */
2662a059 7193 /* Generic PowerPC 401 */
80d11f44 7194 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 7195 /* PowerPC 401 cores */
2662a059 7196 /* PowerPC 401A1 */
80d11f44 7197 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 7198 /* PowerPC 401B2 */
80d11f44 7199 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 7200#if defined (TODO)
a750fc0b 7201 /* PowerPC 401B3 */
80d11f44 7202 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 7203#endif
7204 /* PowerPC 401C2 */
80d11f44 7205 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 7206 /* PowerPC 401D2 */
80d11f44 7207 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 7208 /* PowerPC 401E2 */
80d11f44 7209 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 7210 /* PowerPC 401F2 */
80d11f44 7211 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 7212 /* PowerPC 401G2 */
7213 /* XXX: to be checked */
80d11f44 7214 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 7215 /* PowerPC 401 microcontrolers */
2662a059 7216#if defined (TODO)
a750fc0b 7217 /* PowerPC 401GF */
80d11f44 7218 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 7219#endif
a750fc0b 7220 /* IOP480 (401 microcontroler) */
80d11f44 7221 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 7222 /* IBM Processor for Network Resources */
80d11f44 7223 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 7224#if defined (TODO)
80d11f44 7225 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 7226#endif
a750fc0b
JM		 7227 /* PowerPC 403 family */
7228 /* Generic PowerPC 403 */
80d11f44 7229 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 7230 /* PowerPC 403 microcontrolers */
7231 /* PowerPC 403 GA */
80d11f44 7232 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 7233 /* PowerPC 403 GB */
80d11f44 7234 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 7235 /* PowerPC 403 GC */
80d11f44 7236 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 7237 /* PowerPC 403 GCX */
80d11f44 7238 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 7239#if defined (TODO)
a750fc0b 7240 /* PowerPC 403 GP */
80d11f44 7241 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 7242#endif
a750fc0b
JM		 7243 /* PowerPC 405 family */
7244 /* Generic PowerPC 405 */
80d11f44 7245 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 7246 /* PowerPC 405 cores */
2662a059 7247#if defined (TODO)
a750fc0b 7248 /* PowerPC 405 A3 */
80d11f44 7249 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 7250#endif
3a607854 7251#if defined (TODO)
a750fc0b 7252 /* PowerPC 405 A4 */
80d11f44 7253 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 7254#endif
3a607854 7255#if defined (TODO)
a750fc0b 7256 /* PowerPC 405 B3 */
80d11f44 7257 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 7258#endif
7259#if defined (TODO)
a750fc0b 7260 /* PowerPC 405 B4 */
80d11f44 7261 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 7262#endif
7263#if defined (TODO)
7264 /* PowerPC 405 C3 */
80d11f44 7265 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 7266#endif
7267#if defined (TODO)
7268 /* PowerPC 405 C4 */
80d11f44 7269 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 7270#endif
7271 /* PowerPC 405 D2 */
80d11f44 7272 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 7273#if defined (TODO)
7274 /* PowerPC 405 D3 */
80d11f44 7275 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 7276#endif
7277 /* PowerPC 405 D4 */
80d11f44 7278 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 7279#if defined (TODO)
7280 /* PowerPC 405 D5 */
80d11f44 7281 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 7282#endif
7283#if defined (TODO)
7284 /* PowerPC 405 E4 */
80d11f44 7285 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 7286#endif
7287#if defined (TODO)
7288 /* PowerPC 405 F4 */
80d11f44 7289 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 7290#endif
7291#if defined (TODO)
7292 /* PowerPC 405 F5 */
80d11f44 7293 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 7294#endif
7295#if defined (TODO)
7296 /* PowerPC 405 F6 */
80d11f44 7297 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 7298#endif
7299 /* PowerPC 405 microcontrolers */
7300 /* PowerPC 405 CR */
80d11f44 7301 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 7302 /* PowerPC 405 CRa */
80d11f44 7303 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 7304 /* PowerPC 405 CRb */
80d11f44 7305 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 7306 /* PowerPC 405 CRc */
80d11f44 7307 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 7308 /* PowerPC 405 EP */
80d11f44 7309 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 7310#if defined(TODO)
7311 /* PowerPC 405 EXr */
80d11f44 7312 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 7313#endif
7314 /* PowerPC 405 EZ */
80d11f44 7315 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 7316#if defined(TODO)
7317 /* PowerPC 405 FX */
80d11f44 7318 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 7319#endif
7320 /* PowerPC 405 GP */
80d11f44 7321 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 7322 /* PowerPC 405 GPa */
80d11f44 7323 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 7324 /* PowerPC 405 GPb */
80d11f44 7325 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 7326 /* PowerPC 405 GPc */
80d11f44 7327 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 7328 /* PowerPC 405 GPd */
80d11f44 7329 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 7330 /* PowerPC 405 GPe */
80d11f44 7331 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 7332 /* PowerPC 405 GPR */
80d11f44 7333 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 7334#if defined(TODO)
7335 /* PowerPC 405 H */
80d11f44 7336 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 7337#endif
7338#if defined(TODO)
7339 /* PowerPC 405 L */
80d11f44 7340 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 7341#endif
7342 /* PowerPC 405 LP */
80d11f44 7343 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 7344#if defined(TODO)
7345 /* PowerPC 405 PM */
80d11f44 7346 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 7347#endif
7348#if defined(TODO)
7349 /* PowerPC 405 PS */
80d11f44 7350 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 7351#endif
7352#if defined(TODO)
7353 /* PowerPC 405 S */
80d11f44 7354 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 7355#endif
7356 /* Npe405 H */
80d11f44 7357 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 7358 /* Npe405 H2 */
80d11f44 7359 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 7360 /* Npe405 L */
80d11f44 7361 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 7362 /* Npe4GS3 */
80d11f44 7363 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 7364#if defined (TODO)
80d11f44 7365 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 7366#endif
7367#if defined (TODO)
80d11f44 7368 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 7369#endif
7370#if defined (TODO)
7371 /* PowerPC LC77700 (Sanyo) */
80d11f44 7372 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 7373#endif
7374 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7375#if defined (TODO)
7376 /* STB010000 */
80d11f44 7377 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 7378#endif
7379#if defined (TODO)
7380 /* STB01010 */
80d11f44 7381 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 7382#endif
7383#if defined (TODO)
7384 /* STB0210 */
80d11f44 7385 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 7386#endif
7387 /* STB03xx */
80d11f44 7388 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 7389#if defined (TODO)
7390 /* STB043x */
80d11f44 7391 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 7392#endif
7393#if defined (TODO)
7394 /* STB045x */
80d11f44 7395 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 7396#endif
7397 /* STB04xx */
80d11f44 7398 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 7399 /* STB25xx */
80d11f44 7400 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 7401#if defined (TODO)
7402 /* STB130 */
80d11f44 7403 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 7404#endif
7405 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 7406 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7407 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7408 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7409 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 7410#if defined (TODO)
7411 /* Zarlink ZL10310 */
80d11f44 7412 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 7413#endif
7414#if defined (TODO)
7415 /* Zarlink ZL10311 */
80d11f44 7416 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 7417#endif
7418#if defined (TODO)
7419 /* Zarlink ZL10320 */
80d11f44 7420 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 7421#endif
7422#if defined (TODO)
7423 /* Zarlink ZL10321 */
80d11f44 7424 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 7425#endif
7426 /* PowerPC 440 family */
80d11f44 7427#if defined(TODO_USER_ONLY)
a750fc0b 7428 /* Generic PowerPC 440 */
80d11f44
JM		 7429 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7430#endif
a750fc0b
JM		 7431 /* PowerPC 440 cores */
7432#if defined (TODO)
7433 /* PowerPC 440 A4 */
80d11f44 7434 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b
JM		 7435#endif
7436#if defined (TODO)
7437 /* PowerPC 440 A5 */
80d11f44 7438 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 7439#endif
7440#if defined (TODO)
7441 /* PowerPC 440 B4 */
80d11f44 7442 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 7443#endif
7444#if defined (TODO)
7445 /* PowerPC 440 G4 */
80d11f44 7446 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 7447#endif
7448#if defined (TODO)
7449 /* PowerPC 440 F5 */
80d11f44 7450 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 7451#endif
7452#if defined (TODO)
7453 /* PowerPC 440 G5 */
80d11f44 7454 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 7455#endif
7456#if defined (TODO)
7457 /* PowerPC 440H4 */
80d11f44 7458 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 7459#endif
7460#if defined (TODO)
7461 /* PowerPC 440H6 */
80d11f44 7462 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 7463#endif
7464 /* PowerPC 440 microcontrolers */
80d11f44 7465#if defined(TODO_USER_ONLY)
a750fc0b 7466 /* PowerPC 440 EP */
80d11f44
JM		 7467 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7468#endif
7469#if defined(TODO_USER_ONLY)
a750fc0b 7470 /* PowerPC 440 EPa */
80d11f44
JM		 7471 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7472#endif
7473#if defined(TODO_USER_ONLY)
a750fc0b 7474 /* PowerPC 440 EPb */
80d11f44
JM		 7475 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7476#endif
7477#if defined(TODO_USER_ONLY)
a750fc0b 7478 /* PowerPC 440 EPX */
80d11f44
JM		 7479 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7480#endif
7481#if defined(TODO_USER_ONLY)
a750fc0b 7482 /* PowerPC 440 GP */
80d11f44
JM		 7483 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7484#endif
7485#if defined(TODO_USER_ONLY)
a750fc0b 7486 /* PowerPC 440 GPb */
80d11f44
JM		 7487 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7488#endif
7489#if defined(TODO_USER_ONLY)
a750fc0b 7490 /* PowerPC 440 GPc */
80d11f44
JM		 7491 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7492#endif
7493#if defined(TODO_USER_ONLY)
a750fc0b 7494 /* PowerPC 440 GR */
80d11f44
JM		 7495 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7496#endif
7497#if defined(TODO_USER_ONLY)
a750fc0b 7498 /* PowerPC 440 GRa */
80d11f44
JM		 7499 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7500#endif
7501#if defined(TODO_USER_ONLY)
a750fc0b 7502 /* PowerPC 440 GRX */
80d11f44
JM		 7503 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7504#endif
7505#if defined(TODO_USER_ONLY)
a750fc0b 7506 /* PowerPC 440 GX */
80d11f44
JM		 7507 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7508#endif
7509#if defined(TODO_USER_ONLY)
a750fc0b 7510 /* PowerPC 440 GXa */
80d11f44
JM		 7511 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7512#endif
7513#if defined(TODO_USER_ONLY)
a750fc0b 7514 /* PowerPC 440 GXb */
80d11f44
JM		 7515 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7516#endif
7517#if defined(TODO_USER_ONLY)
a750fc0b 7518 /* PowerPC 440 GXc */
80d11f44
JM		 7519 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7520#endif
7521#if defined(TODO_USER_ONLY)
a750fc0b 7522 /* PowerPC 440 GXf */
80d11f44
JM		 7523 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7524#endif
a750fc0b
JM		 7525#if defined(TODO)
7526 /* PowerPC 440 S */
80d11f44 7527 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 7528#endif
80d11f44 7529#if defined(TODO_USER_ONLY)
a750fc0b 7530 /* PowerPC 440 SP */
80d11f44
JM		 7531 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7532#endif
7533#if defined(TODO_USER_ONLY)
a750fc0b 7534 /* PowerPC 440 SP2 */
80d11f44
JM		 7535 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7536#endif
7537#if defined(TODO_USER_ONLY)
a750fc0b 7538 /* PowerPC 440 SPE */
80d11f44
JM		 7539 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7540#endif
a750fc0b
JM		 7541 /* PowerPC 460 family */
7542#if defined (TODO)
7543 /* Generic PowerPC 464 */
80d11f44 7544 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 7545#endif
7546 /* PowerPC 464 microcontrolers */
7547#if defined (TODO)
7548 /* PowerPC 464H90 */
80d11f44 7549 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 7550#endif
7551#if defined (TODO)
7552 /* PowerPC 464H90F */
80d11f44 7553 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 7554#endif
7555 /* Freescale embedded PowerPC cores */
80d11f44
JM		 7556 /* MPC5xx family (aka RCPU) */
7557#if defined(TODO_USER_ONLY)
7558 /* Generic MPC5xx core */
7559 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7560#endif
7561#if defined(TODO_USER_ONLY)
7562 /* Codename for MPC5xx core */
7563 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7564#endif
7565 /* MPC5xx microcontrollers */
7566#if defined(TODO_USER_ONLY)
7567 /* MGT560 */
7568 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7569#endif
7570#if defined(TODO_USER_ONLY)
7571 /* MPC509 */
7572 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7573#endif
7574#if defined(TODO_USER_ONLY)
7575 /* MPC533 */
7576 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7577#endif
7578#if defined(TODO_USER_ONLY)
7579 /* MPC534 */
7580 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7581#endif
7582#if defined(TODO_USER_ONLY)
7583 /* MPC555 */
7584 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7585#endif
7586#if defined(TODO_USER_ONLY)
7587 /* MPC556 */
7588 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7589#endif
7590#if defined(TODO_USER_ONLY)
7591 /* MPC560 */
7592 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7593#endif
7594#if defined(TODO_USER_ONLY)
7595 /* MPC561 */
7596 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7597#endif
7598#if defined(TODO_USER_ONLY)
7599 /* MPC562 */
7600 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7601#endif
7602#if defined(TODO_USER_ONLY)
7603 /* MPC563 */
7604 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7605#endif
7606#if defined(TODO_USER_ONLY)
7607 /* MPC564 */
7608 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7609#endif
7610#if defined(TODO_USER_ONLY)
7611 /* MPC565 */
7612 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7613#endif
7614#if defined(TODO_USER_ONLY)
7615 /* MPC566 */
7616 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7617#endif
7618 /* MPC8xx family (aka PowerQUICC) */
7619#if defined(TODO_USER_ONLY)
7620 /* Generic MPC8xx core */
7621 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7622#endif
7623#if defined(TODO_USER_ONLY)
7624 /* Codename for MPC8xx core */
7625 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7626#endif
7627 /* MPC8xx microcontrollers */
7628#if defined(TODO_USER_ONLY)
7629 /* MGT823 */
7630 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7631#endif
7632#if defined(TODO_USER_ONLY)
7633 /* MPC821 */
7634 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7635#endif
7636#if defined(TODO_USER_ONLY)
7637 /* MPC823 */
7638 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7639#endif
7640#if defined(TODO_USER_ONLY)
7641 /* MPC850 */
7642 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7643#endif
7644#if defined(TODO_USER_ONLY)
7645 /* MPC852T */
7646 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7647#endif
7648#if defined(TODO_USER_ONLY)
7649 /* MPC855T */
7650 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7651#endif
7652#if defined(TODO_USER_ONLY)
7653 /* MPC857 */
7654 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7655#endif
7656#if defined(TODO_USER_ONLY)
7657 /* MPC859 */
7658 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7659#endif
7660#if defined(TODO_USER_ONLY)
7661 /* MPC860 */
7662 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
7663#endif
7664#if defined(TODO_USER_ONLY)
7665 /* MPC862 */
7666 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
7667#endif
7668#if defined(TODO_USER_ONLY)
7669 /* MPC866 */
7670 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
7671#endif
7672#if defined(TODO_USER_ONLY)
7673 /* MPC870 */
7674 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
7675#endif
7676#if defined(TODO_USER_ONLY)
7677 /* MPC875 */
7678 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
7679#endif
7680#if defined(TODO_USER_ONLY)
7681 /* MPC880 */
7682 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
7683#endif
7684#if defined(TODO_USER_ONLY)
7685 /* MPC885 */
7686 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
7687#endif
7688 /* MPC82xx family (aka PowerQUICC-II) */
7689 /* Generic MPC52xx core */
7690 POWERPC_DEF_SVR("MPC52xx",
7691 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
7692 /* Generic MPC82xx core */
7693 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
7694 /* Codename for MPC82xx */
7695 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
7696 /* PowerPC G2 core */
7697 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
7698 /* PowerPC G2 H4 core */
7699 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
7700 /* PowerPC G2 GP core */
7701 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
7702 /* PowerPC G2 LS core */
7703 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
7704 /* PowerPC G2 HiP3 core */
7705 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
7706 /* PowerPC G2 HiP4 core */
7707 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
7708 /* PowerPC MPC603 core */
7709 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
7710 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
7711 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
7712 /* PowerPC G2LE GP core */
7713 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
7714 /* PowerPC G2LE LS core */
7715 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
7716 /* PowerPC G2LE GP1 core */
7717 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
7718 /* PowerPC G2LE GP3 core */
7719 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
7720 /* PowerPC MPC603 microcontrollers */
7721 /* MPC8240 */
7722 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
7723 /* PowerPC G2 microcontrollers */
082c6681 7724#if defined(TODO)
80d11f44
JM		 7725 /* MPC5121 */
7726 POWERPC_DEF_SVR("MPC5121",
7727 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
7728#endif
7729 /* MPC5200 */
7730 POWERPC_DEF_SVR("MPC5200",
7731 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
7732 /* MPC5200 v1.0 */
7733 POWERPC_DEF_SVR("MPC5200_v10",
7734 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
7735 /* MPC5200 v1.1 */
7736 POWERPC_DEF_SVR("MPC5200_v11",
7737 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
7738 /* MPC5200 v1.2 */
7739 POWERPC_DEF_SVR("MPC5200_v12",
7740 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
7741 /* MPC5200B */
7742 POWERPC_DEF_SVR("MPC5200B",
7743 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
7744 /* MPC5200B v2.0 */
7745 POWERPC_DEF_SVR("MPC5200B_v20",
7746 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7747 /* MPC5200B v2.1 */
7748 POWERPC_DEF_SVR("MPC5200B_v21",
7749 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7750 /* MPC8241 */
7751 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
7752 /* MPC8245 */
7753 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
7754 /* MPC8247 */
7755 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
7756 /* MPC8248 */
7757 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
7758 /* MPC8250 */
7759 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
7760 /* MPC8250 HiP3 */
7761 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
7762 /* MPC8250 HiP4 */
7763 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
7764 /* MPC8255 */
7765 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
7766 /* MPC8255 HiP3 */
7767 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
7768 /* MPC8255 HiP4 */
7769 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
7770 /* MPC8260 */
7771 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
7772 /* MPC8260 HiP3 */
7773 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
7774 /* MPC8260 HiP4 */
7775 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
7776 /* MPC8264 */
7777 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
7778 /* MPC8264 HiP3 */
7779 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
7780 /* MPC8264 HiP4 */
7781 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
7782 /* MPC8265 */
7783 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
7784 /* MPC8265 HiP3 */
7785 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
7786 /* MPC8265 HiP4 */
7787 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
7788 /* MPC8266 */
7789 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
7790 /* MPC8266 HiP3 */
7791 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
7792 /* MPC8266 HiP4 */
7793 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
7794 /* MPC8270 */
7795 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
7796 /* MPC8271 */
7797 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
7798 /* MPC8272 */
7799 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
7800 /* MPC8275 */
7801 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
7802 /* MPC8280 */
7803 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 7804 /* e200 family */
a750fc0b 7805 /* Generic PowerPC e200 core */
80d11f44
JM		 7806 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
7807 /* Generic MPC55xx core */
7808#if defined (TODO)
7809 POWERPC_DEF_SVR("MPC55xx",
7810 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 7811#endif
7812#if defined (TODO)
80d11f44
JM		 7813 /* PowerPC e200z0 core */
7814 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 7815#endif
7816#if defined (TODO)
80d11f44
JM		 7817 /* PowerPC e200z1 core */
7818 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
7819#endif
7820#if defined (TODO)
7821 /* PowerPC e200z3 core */
7822 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
7823#endif
7824 /* PowerPC e200z5 core */
7825 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 7826 /* PowerPC e200z6 core */
80d11f44
JM		 7827 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
7828 /* PowerPC e200 microcontrollers */
7829#if defined (TODO)
7830 /* MPC5514E */
7831 POWERPC_DEF_SVR("MPC5514E",
7832 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 7833#endif
a750fc0b 7834#if defined (TODO)
80d11f44
JM		 7835 /* MPC5514E v0 */
7836 POWERPC_DEF_SVR("MPC5514E_v0",
7837 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 7838#endif
7839#if defined (TODO)
80d11f44
JM		 7840 /* MPC5514E v1 */
7841 POWERPC_DEF_SVR("MPC5514E_v1",
7842 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 7843#endif
7844#if defined (TODO)
80d11f44
JM		 7845 /* MPC5514G */
7846 POWERPC_DEF_SVR("MPC5514G",
7847 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 7848#endif
7849#if defined (TODO)
80d11f44
JM		 7850 /* MPC5514G v0 */
7851 POWERPC_DEF_SVR("MPC5514G_v0",
7852 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 7853#endif
a750fc0b 7854#if defined (TODO)
80d11f44
JM		 7855 /* MPC5514G v1 */
7856 POWERPC_DEF_SVR("MPC5514G_v1",
7857 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 7858#endif
7859#if defined (TODO)
80d11f44
JM		 7860 /* MPC5515S */
7861 POWERPC_DEF_SVR("MPC5515S",
7862 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 7863#endif
7864#if defined (TODO)
80d11f44
JM		 7865 /* MPC5516E */
7866 POWERPC_DEF_SVR("MPC5516E",
7867 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 7868#endif
7869#if defined (TODO)
80d11f44
JM		 7870 /* MPC5516E v0 */
7871 POWERPC_DEF_SVR("MPC5516E_v0",
7872 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 7873#endif
7874#if defined (TODO)
80d11f44
JM		 7875 /* MPC5516E v1 */
7876 POWERPC_DEF_SVR("MPC5516E_v1",
7877 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 7878#endif
a750fc0b 7879#if defined (TODO)
80d11f44
JM		 7880 /* MPC5516G */
7881 POWERPC_DEF_SVR("MPC5516G",
7882 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 7883#endif
a750fc0b 7884#if defined (TODO)
80d11f44
JM		 7885 /* MPC5516G v0 */
7886 POWERPC_DEF_SVR("MPC5516G_v0",
7887 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 7888#endif
a750fc0b 7889#if defined (TODO)
80d11f44
JM		 7890 /* MPC5516G v1 */
7891 POWERPC_DEF_SVR("MPC5516G_v1",
7892 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 7893#endif
a750fc0b 7894#if defined (TODO)
80d11f44
JM		 7895 /* MPC5516S */
7896 POWERPC_DEF_SVR("MPC5516S",
7897 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 7898#endif
7899#if defined (TODO)
80d11f44
JM		 7900 /* MPC5533 */
7901 POWERPC_DEF_SVR("MPC5533",
7902 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 7903#endif
7904#if defined (TODO)
80d11f44
JM		 7905 /* MPC5534 */
7906 POWERPC_DEF_SVR("MPC5534",
7907 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 7908#endif
80d11f44
JM		 7909#if defined (TODO)
7910 /* MPC5553 */
7911 POWERPC_DEF_SVR("MPC5553",
7912 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
7913#endif
7914#if defined (TODO)
7915 /* MPC5554 */
7916 POWERPC_DEF_SVR("MPC5554",
7917 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
7918#endif
7919#if defined (TODO)
7920 /* MPC5561 */
7921 POWERPC_DEF_SVR("MPC5561",
7922 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
7923#endif
7924#if defined (TODO)
7925 /* MPC5565 */
7926 POWERPC_DEF_SVR("MPC5565",
7927 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
7928#endif
7929#if defined (TODO)
7930 /* MPC5566 */
7931 POWERPC_DEF_SVR("MPC5566",
7932 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
7933#endif
7934#if defined (TODO)
7935 /* MPC5567 */
7936 POWERPC_DEF_SVR("MPC5567",
7937 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
7938#endif
7939 /* e300 family */
7940 /* Generic PowerPC e300 core */
7941 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
7942 /* PowerPC e300c1 core */
7943 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
7944 /* PowerPC e300c2 core */
7945 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
7946 /* PowerPC e300c3 core */
7947 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
7948 /* PowerPC e300c4 core */
7949 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
7950 /* PowerPC e300 microcontrollers */
7951#if defined (TODO)
7952 /* MPC8313 */
7953 POWERPC_DEF_SVR("MPC8313",
7954 CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
7955#endif
7956#if defined (TODO)
7957 /* MPC8313E */
7958 POWERPC_DEF_SVR("MPC8313E",
7959 CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
7960#endif
7961#if defined (TODO)
7962 /* MPC8314 */
7963 POWERPC_DEF_SVR("MPC8314",
7964 CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
7965#endif
7966#if defined (TODO)
7967 /* MPC8314E */
7968 POWERPC_DEF_SVR("MPC8314E",
7969 CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
7970#endif
7971#if defined (TODO)
7972 /* MPC8315 */
7973 POWERPC_DEF_SVR("MPC8315",
7974 CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
7975#endif
7976#if defined (TODO)
7977 /* MPC8315E */
7978 POWERPC_DEF_SVR("MPC8315E",
7979 CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
7980#endif
7981#if defined (TODO)
7982 /* MPC8321 */
7983 POWERPC_DEF_SVR("MPC8321",
7984 CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
7985#endif
7986#if defined (TODO)
7987 /* MPC8321E */
7988 POWERPC_DEF_SVR("MPC8321E",
7989 CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
7990#endif
7991#if defined (TODO)
7992 /* MPC8323 */
7993 POWERPC_DEF_SVR("MPC8323",
7994 CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
7995#endif
7996#if defined (TODO)
7997 /* MPC8323E */
7998 POWERPC_DEF_SVR("MPC8323E",
7999 CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
8000#endif
8001 /* MPC8343A */
8002 POWERPC_DEF_SVR("MPC8343A",
8003 CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
8004 /* MPC8343EA */
8005 POWERPC_DEF_SVR("MPC8343EA",
8006 CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
8007 /* MPC8347A */
8008 POWERPC_DEF_SVR("MPC8347A",
8009 CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
8010 /* MPC8347AT */
8011 POWERPC_DEF_SVR("MPC8347AT",
8012 CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
8013 /* MPC8347AP */
8014 POWERPC_DEF_SVR("MPC8347AP",
8015 CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
8016 /* MPC8347EA */
8017 POWERPC_DEF_SVR("MPC8347EA",
8018 CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
8019 /* MPC8347EAT */
8020 POWERPC_DEF_SVR("MPC8347EAT",
8021 CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
8022 /* MPC8343EAP */
8023 POWERPC_DEF_SVR("MPC8347EAP",
8024 CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
8025 /* MPC8349 */
8026 POWERPC_DEF_SVR("MPC8349",
8027 CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
8028 /* MPC8349A */
8029 POWERPC_DEF_SVR("MPC8349A",
8030 CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
8031 /* MPC8349E */
8032 POWERPC_DEF_SVR("MPC8349E",
8033 CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
8034 /* MPC8349EA */
8035 POWERPC_DEF_SVR("MPC8349EA",
8036 CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
8037#if defined (TODO)
8038 /* MPC8358E */
8039 POWERPC_DEF_SVR("MPC8358E",
8040 CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
8041#endif
8042#if defined (TODO)
8043 /* MPC8360E */
8044 POWERPC_DEF_SVR("MPC8360E",
8045 CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
8046#endif
8047 /* MPC8377 */
8048 POWERPC_DEF_SVR("MPC8377",
8049 CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
8050 /* MPC8377E */
8051 POWERPC_DEF_SVR("MPC8377E",
8052 CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
8053 /* MPC8378 */
8054 POWERPC_DEF_SVR("MPC8378",
8055 CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
8056 /* MPC8378E */
8057 POWERPC_DEF_SVR("MPC8378E",
8058 CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
8059 /* MPC8379 */
8060 POWERPC_DEF_SVR("MPC8379",
8061 CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
8062 /* MPC8379E */
8063 POWERPC_DEF_SVR("MPC8379E",
8064 CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
8065 /* e500 family */
8066 /* PowerPC e500 core */
bd5ea513
AJ		 8067 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8068 /* PowerPC e500v1 core */
8069 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
80d11f44 8070 /* PowerPC e500 v1.0 core */
bd5ea513 8071 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
80d11f44 8072 /* PowerPC e500 v2.0 core */
bd5ea513 8073 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
80d11f44 8074 /* PowerPC e500v2 core */
bd5ea513 8075 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
80d11f44 8076 /* PowerPC e500v2 v1.0 core */
bd5ea513 8077 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
80d11f44 8078 /* PowerPC e500v2 v2.0 core */
bd5ea513 8079 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
80d11f44 8080 /* PowerPC e500v2 v2.1 core */
bd5ea513 8081 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
80d11f44 8082 /* PowerPC e500v2 v2.2 core */
bd5ea513 8083 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
80d11f44 8084 /* PowerPC e500v2 v3.0 core */
bd5ea513 8085 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
80d11f44
JM		 8086 /* PowerPC e500 microcontrollers */
8087 /* MPC8533 */
8088 POWERPC_DEF_SVR("MPC8533",
bd5ea513 8089 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
80d11f44
JM		 8090 /* MPC8533 v1.0 */
8091 POWERPC_DEF_SVR("MPC8533_v10",
bd5ea513 8092 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
80d11f44
JM		 8093 /* MPC8533 v1.1 */
8094 POWERPC_DEF_SVR("MPC8533_v11",
bd5ea513 8095 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
80d11f44
JM		 8096 /* MPC8533E */
8097 POWERPC_DEF_SVR("MPC8533E",
bd5ea513 8098 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
80d11f44
JM		 8099 /* MPC8533E v1.0 */
8100 POWERPC_DEF_SVR("MPC8533E_v10",
bd5ea513 8101 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
80d11f44 8102 POWERPC_DEF_SVR("MPC8533E_v11",
bd5ea513 8103 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
80d11f44
JM		 8104 /* MPC8540 */
8105 POWERPC_DEF_SVR("MPC8540",
bd5ea513 8106 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
80d11f44
JM		 8107 /* MPC8540 v1.0 */
8108 POWERPC_DEF_SVR("MPC8540_v10",
bd5ea513 8109 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
80d11f44
JM		 8110 /* MPC8540 v2.0 */
8111 POWERPC_DEF_SVR("MPC8540_v20",
bd5ea513 8112 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
80d11f44
JM		 8113 /* MPC8540 v2.1 */
8114 POWERPC_DEF_SVR("MPC8540_v21",
bd5ea513 8115 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
80d11f44
JM		 8116 /* MPC8541 */
8117 POWERPC_DEF_SVR("MPC8541",
bd5ea513 8118 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
80d11f44
JM		 8119 /* MPC8541 v1.0 */
8120 POWERPC_DEF_SVR("MPC8541_v10",
bd5ea513 8121 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
80d11f44
JM		 8122 /* MPC8541 v1.1 */
8123 POWERPC_DEF_SVR("MPC8541_v11",
bd5ea513 8124 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
80d11f44
JM		 8125 /* MPC8541E */
8126 POWERPC_DEF_SVR("MPC8541E",
bd5ea513 8127 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
80d11f44
JM		 8128 /* MPC8541E v1.0 */
8129 POWERPC_DEF_SVR("MPC8541E_v10",
bd5ea513 8130 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
80d11f44
JM		 8131 /* MPC8541E v1.1 */
8132 POWERPC_DEF_SVR("MPC8541E_v11",
bd5ea513 8133 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
80d11f44
JM		 8134 /* MPC8543 */
8135 POWERPC_DEF_SVR("MPC8543",
bd5ea513 8136 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
80d11f44
JM		 8137 /* MPC8543 v1.0 */
8138 POWERPC_DEF_SVR("MPC8543_v10",
bd5ea513 8139 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
80d11f44
JM		 8140 /* MPC8543 v1.1 */
8141 POWERPC_DEF_SVR("MPC8543_v11",
bd5ea513 8142 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
80d11f44
JM		 8143 /* MPC8543 v2.0 */
8144 POWERPC_DEF_SVR("MPC8543_v20",
bd5ea513 8145 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
80d11f44
JM		 8146 /* MPC8543 v2.1 */
8147 POWERPC_DEF_SVR("MPC8543_v21",
bd5ea513 8148 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
80d11f44
JM		 8149 /* MPC8543E */
8150 POWERPC_DEF_SVR("MPC8543E",
bd5ea513 8151 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
80d11f44
JM		 8152 /* MPC8543E v1.0 */
8153 POWERPC_DEF_SVR("MPC8543E_v10",
bd5ea513 8154 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
80d11f44
JM		 8155 /* MPC8543E v1.1 */
8156 POWERPC_DEF_SVR("MPC8543E_v11",
bd5ea513 8157 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
80d11f44
JM		 8158 /* MPC8543E v2.0 */
8159 POWERPC_DEF_SVR("MPC8543E_v20",
bd5ea513 8160 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
80d11f44
JM		 8161 /* MPC8543E v2.1 */
8162 POWERPC_DEF_SVR("MPC8543E_v21",
bd5ea513 8163 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
80d11f44
JM		 8164 /* MPC8544 */
8165 POWERPC_DEF_SVR("MPC8544",
bd5ea513 8166 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
80d11f44
JM		 8167 /* MPC8544 v1.0 */
8168 POWERPC_DEF_SVR("MPC8544_v10",
bd5ea513 8169 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
80d11f44
JM		 8170 /* MPC8544 v1.1 */
8171 POWERPC_DEF_SVR("MPC8544_v11",
bd5ea513 8172 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
80d11f44
JM		 8173 /* MPC8544E */
8174 POWERPC_DEF_SVR("MPC8544E",
bd5ea513 8175 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
80d11f44
JM		 8176 /* MPC8544E v1.0 */
8177 POWERPC_DEF_SVR("MPC8544E_v10",
bd5ea513 8178 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
80d11f44
JM		 8179 /* MPC8544E v1.1 */
8180 POWERPC_DEF_SVR("MPC8544E_v11",
bd5ea513 8181 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
80d11f44
JM		 8182 /* MPC8545 */
8183 POWERPC_DEF_SVR("MPC8545",
bd5ea513 8184 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
80d11f44
JM		 8185 /* MPC8545 v2.0 */
8186 POWERPC_DEF_SVR("MPC8545_v20",
bd5ea513 8187 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
80d11f44
JM		 8188 /* MPC8545 v2.1 */
8189 POWERPC_DEF_SVR("MPC8545_v21",
bd5ea513 8190 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
80d11f44
JM		 8191 /* MPC8545E */
8192 POWERPC_DEF_SVR("MPC8545E",
bd5ea513 8193 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
80d11f44
JM		 8194 /* MPC8545E v2.0 */
8195 POWERPC_DEF_SVR("MPC8545E_v20",
bd5ea513 8196 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
80d11f44
JM		 8197 /* MPC8545E v2.1 */
8198 POWERPC_DEF_SVR("MPC8545E_v21",
bd5ea513 8199 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
80d11f44
JM		 8200 /* MPC8547E */
8201 POWERPC_DEF_SVR("MPC8547E",
bd5ea513 8202 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
80d11f44
JM		 8203 /* MPC8547E v2.0 */
8204 POWERPC_DEF_SVR("MPC8547E_v20",
bd5ea513 8205 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
80d11f44
JM		 8206 /* MPC8547E v2.1 */
8207 POWERPC_DEF_SVR("MPC8547E_v21",
bd5ea513 8208 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
80d11f44
JM		 8209 /* MPC8548 */
8210 POWERPC_DEF_SVR("MPC8548",
bd5ea513 8211 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
80d11f44
JM		 8212 /* MPC8548 v1.0 */
8213 POWERPC_DEF_SVR("MPC8548_v10",
bd5ea513 8214 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
80d11f44
JM		 8215 /* MPC8548 v1.1 */
8216 POWERPC_DEF_SVR("MPC8548_v11",
bd5ea513 8217 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
80d11f44
JM		 8218 /* MPC8548 v2.0 */
8219 POWERPC_DEF_SVR("MPC8548_v20",
bd5ea513 8220 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
80d11f44
JM		 8221 /* MPC8548 v2.1 */
8222 POWERPC_DEF_SVR("MPC8548_v21",
bd5ea513 8223 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
80d11f44
JM		 8224 /* MPC8548E */
8225 POWERPC_DEF_SVR("MPC8548E",
bd5ea513 8226 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
80d11f44
JM		 8227 /* MPC8548E v1.0 */
8228 POWERPC_DEF_SVR("MPC8548E_v10",
bd5ea513 8229 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
80d11f44
JM		 8230 /* MPC8548E v1.1 */
8231 POWERPC_DEF_SVR("MPC8548E_v11",
bd5ea513 8232 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
80d11f44
JM		 8233 /* MPC8548E v2.0 */
8234 POWERPC_DEF_SVR("MPC8548E_v20",
bd5ea513 8235 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
80d11f44
JM		 8236 /* MPC8548E v2.1 */
8237 POWERPC_DEF_SVR("MPC8548E_v21",
bd5ea513 8238 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
80d11f44
JM		 8239 /* MPC8555 */
8240 POWERPC_DEF_SVR("MPC8555",
bd5ea513 8241 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
80d11f44
JM		 8242 /* MPC8555 v1.0 */
8243 POWERPC_DEF_SVR("MPC8555_v10",
bd5ea513 8244 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
80d11f44
JM		 8245 /* MPC8555 v1.1 */
8246 POWERPC_DEF_SVR("MPC8555_v11",
bd5ea513 8247 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
80d11f44
JM		 8248 /* MPC8555E */
8249 POWERPC_DEF_SVR("MPC8555E",
bd5ea513 8250 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
80d11f44
JM		 8251 /* MPC8555E v1.0 */
8252 POWERPC_DEF_SVR("MPC8555E_v10",
bd5ea513 8253 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
80d11f44
JM		 8254 /* MPC8555E v1.1 */
8255 POWERPC_DEF_SVR("MPC8555E_v11",
bd5ea513 8256 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
80d11f44
JM		 8257 /* MPC8560 */
8258 POWERPC_DEF_SVR("MPC8560",
bd5ea513 8259 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
80d11f44
JM		 8260 /* MPC8560 v1.0 */
8261 POWERPC_DEF_SVR("MPC8560_v10",
bd5ea513 8262 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
80d11f44
JM		 8263 /* MPC8560 v2.0 */
8264 POWERPC_DEF_SVR("MPC8560_v20",
bd5ea513 8265 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
80d11f44
JM		 8266 /* MPC8560 v2.1 */
8267 POWERPC_DEF_SVR("MPC8560_v21",
bd5ea513 8268 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
80d11f44
JM		 8269 /* MPC8567 */
8270 POWERPC_DEF_SVR("MPC8567",
bd5ea513 8271 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
80d11f44
JM		 8272 /* MPC8567E */
8273 POWERPC_DEF_SVR("MPC8567E",
bd5ea513 8274 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
80d11f44
JM		 8275 /* MPC8568 */
8276 POWERPC_DEF_SVR("MPC8568",
bd5ea513 8277 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
80d11f44
JM		 8278 /* MPC8568E */
8279 POWERPC_DEF_SVR("MPC8568E",
bd5ea513 8280 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
80d11f44
JM		 8281 /* MPC8572 */
8282 POWERPC_DEF_SVR("MPC8572",
bd5ea513 8283 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
80d11f44
JM		 8284 /* MPC8572E */
8285 POWERPC_DEF_SVR("MPC8572E",
bd5ea513 8286 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
80d11f44
JM		 8287 /* e600 family */
8288 /* PowerPC e600 core */
8289 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8290 /* PowerPC e600 microcontrollers */
8291#if defined (TODO)
8292 /* MPC8610 */
8293 POWERPC_DEF_SVR("MPC8610",
8294 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8295#endif
8296 /* MPC8641 */
8297 POWERPC_DEF_SVR("MPC8641",
8298 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8299 /* MPC8641D */
8300 POWERPC_DEF_SVR("MPC8641D",
8301 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 8302 /* 32 bits "classic" PowerPC */
8303 /* PowerPC 6xx family */
8304 /* PowerPC 601 */
bd928eba 8305 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
c3e36823 8306 /* PowerPC 601v0 */
082c6681 8307 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 8308 /* PowerPC 601v1 */
082c6681
JM		 8309 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8310 /* PowerPC 601v */
bd928eba 8311 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
a750fc0b 8312 /* PowerPC 601v2 */
082c6681 8313 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 8314 /* PowerPC 602 */
80d11f44 8315 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 8316 /* PowerPC 603 */
80d11f44 8317 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 8318 /* Code name for PowerPC 603 */
80d11f44 8319 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 8320 /* PowerPC 603e (aka PID6) */
80d11f44 8321 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 8322 /* Code name for PowerPC 603e */
80d11f44 8323 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 8324 /* PowerPC 603e v1.1 */
80d11f44 8325 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 8326 /* PowerPC 603e v1.2 */
80d11f44 8327 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 8328 /* PowerPC 603e v1.3 */
80d11f44 8329 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 8330 /* PowerPC 603e v1.4 */
80d11f44 8331 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 8332 /* PowerPC 603e v2.2 */
80d11f44 8333 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 8334 /* PowerPC 603e v3 */
80d11f44 8335 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 8336 /* PowerPC 603e v4 */
80d11f44 8337 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 8338 /* PowerPC 603e v4.1 */
80d11f44 8339 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 8340 /* PowerPC 603e (aka PID7) */
80d11f44 8341 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 8342 /* PowerPC 603e7t */
80d11f44 8343 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 8344 /* PowerPC 603e7v */
80d11f44 8345 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 8346 /* Code name for PowerPC 603ev */
80d11f44 8347 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 8348 /* PowerPC 603e7v1 */
80d11f44 8349 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 8350 /* PowerPC 603e7v2 */
80d11f44 8351 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 8352 /* PowerPC 603p (aka PID7v) */
8353 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8354 /* PowerPC 603r (aka PID7t) */
80d11f44 8355 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 8356 /* Code name for PowerPC 603r */
80d11f44 8357 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 8358 /* PowerPC 604 */
80d11f44 8359 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 8360 /* PowerPC 604e (aka PID9) */
8361 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8362 /* Code name for PowerPC 604e */
8363 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 8364 /* PowerPC 604e v1.0 */
082c6681 8365 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 8366 /* PowerPC 604e v2.2 */
082c6681 8367 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 8368 /* PowerPC 604e v2.4 */
082c6681
JM		 8369 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8370 /* PowerPC 604r (aka PIDA) */
8371 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8372 /* Code name for PowerPC 604r */
8373 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 8374#if defined(TODO)
8375 /* PowerPC 604ev */
082c6681 8376 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 8377#endif
8378 /* PowerPC 7xx family */
8379 /* Generic PowerPC 740 (G3) */
bd928eba 8380 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
082c6681 8381 /* Code name for PowerPC 740 */
bd928eba 8382 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
a750fc0b 8383 /* Generic PowerPC 750 (G3) */
bd928eba 8384 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
082c6681 8385 /* Code name for PowerPC 750 */
bd928eba 8386 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
a750fc0b 8387 /* PowerPC 740/750 is also known as G3 */
bd928eba
JM		 8388 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8389 /* PowerPC 740 v1.0 (G3) */
8390 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8391 /* PowerPC 750 v1.0 (G3) */
8392 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
a750fc0b 8393 /* PowerPC 740 v2.0 (G3) */
bd928eba 8394 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
a750fc0b 8395 /* PowerPC 750 v2.0 (G3) */
bd928eba 8396 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
a750fc0b 8397 /* PowerPC 740 v2.1 (G3) */
bd928eba 8398 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
a750fc0b 8399 /* PowerPC 750 v2.1 (G3) */
bd928eba 8400 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
a750fc0b 8401 /* PowerPC 740 v2.2 (G3) */
bd928eba 8402 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
a750fc0b 8403 /* PowerPC 750 v2.2 (G3) */
bd928eba 8404 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
a750fc0b 8405 /* PowerPC 740 v3.0 (G3) */
bd928eba 8406 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
a750fc0b 8407 /* PowerPC 750 v3.0 (G3) */
bd928eba 8408 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
a750fc0b 8409 /* PowerPC 740 v3.1 (G3) */
bd928eba 8410 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
a750fc0b 8411 /* PowerPC 750 v3.1 (G3) */
bd928eba 8412 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
a750fc0b 8413 /* PowerPC 740E (G3) */
bd928eba
JM		 8414 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8415 /* PowerPC 750E (G3) */
8416 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
a750fc0b 8417 /* PowerPC 740P (G3) */
bd928eba 8418 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
a750fc0b 8419 /* PowerPC 750P (G3) */
bd928eba 8420 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
a750fc0b 8421 /* Code name for PowerPC 740P/750P (G3) */
bd928eba 8422 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
a750fc0b 8423 /* PowerPC 750CL (G3 embedded) */
bd928eba
JM		 8424 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8425 /* PowerPC 750CL v1.0 */
8426 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8427 /* PowerPC 750CL v2.0 */
8428 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
a750fc0b 8429 /* PowerPC 750CX (G3 embedded) */
bd928eba
JM		 8430 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8431 /* PowerPC 750CX v1.0 (G3 embedded) */
8432 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8433 /* PowerPC 750CX v2.1 (G3 embedded) */
8434 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
a750fc0b 8435 /* PowerPC 750CX v2.1 (G3 embedded) */
bd928eba 8436 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
a750fc0b 8437 /* PowerPC 750CX v2.2 (G3 embedded) */
bd928eba 8438 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
a750fc0b 8439 /* PowerPC 750CXe (G3 embedded) */
bd928eba 8440 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
a750fc0b 8441 /* PowerPC 750CXe v2.1 (G3 embedded) */
bd928eba 8442 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
a750fc0b 8443 /* PowerPC 750CXe v2.2 (G3 embedded) */
bd928eba 8444 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
a750fc0b 8445 /* PowerPC 750CXe v2.3 (G3 embedded) */
bd928eba 8446 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
a750fc0b 8447 /* PowerPC 750CXe v2.4 (G3 embedded) */
bd928eba 8448 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
a750fc0b 8449 /* PowerPC 750CXe v2.4b (G3 embedded) */
bd928eba
JM		 8450 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8451 /* PowerPC 750CXe v3.0 (G3 embedded) */
8452 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
a750fc0b 8453 /* PowerPC 750CXe v3.1 (G3 embedded) */
bd928eba 8454 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
a750fc0b 8455 /* PowerPC 750CXe v3.1b (G3 embedded) */
bd928eba 8456 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
a750fc0b 8457 /* PowerPC 750CXr (G3 embedded) */
bd928eba 8458 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
a750fc0b 8459 /* PowerPC 750FL (G3 embedded) */
80d11f44 8460 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 8461 /* PowerPC 750FX (G3 embedded) */
80d11f44 8462 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 8463 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 8464 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 8465 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 8466 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 8467 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 8468 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 8469 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 8470 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 8471 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 8472 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 8473 /* PowerPC 750GL (G3 embedded) */
bd928eba 8474 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
a750fc0b 8475 /* PowerPC 750GX (G3 embedded) */
bd928eba 8476 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
a750fc0b 8477 /* PowerPC 750GX v1.0 (G3 embedded) */
bd928eba 8478 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
a750fc0b 8479 /* PowerPC 750GX v1.1 (G3 embedded) */
bd928eba 8480 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
a750fc0b 8481 /* PowerPC 750GX v1.2 (G3 embedded) */
bd928eba 8482 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
a750fc0b 8483 /* PowerPC 750L (G3 embedded) */
bd928eba 8484 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
a750fc0b 8485 /* Code name for PowerPC 750L (G3 embedded) */
bd928eba
JM		 8486 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8487 /* PowerPC 750L v2.0 (G3 embedded) */
8488 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8489 /* PowerPC 750L v2.1 (G3 embedded) */
8490 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
a750fc0b 8491 /* PowerPC 750L v2.2 (G3 embedded) */
bd928eba 8492 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
a750fc0b 8493 /* PowerPC 750L v3.0 (G3 embedded) */
bd928eba 8494 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
a750fc0b 8495 /* PowerPC 750L v3.2 (G3 embedded) */
bd928eba 8496 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
a750fc0b 8497 /* Generic PowerPC 745 */
bd928eba 8498 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
a750fc0b 8499 /* Generic PowerPC 755 */
bd928eba 8500 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
a750fc0b 8501 /* Code name for PowerPC 745/755 */
bd928eba 8502 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
a750fc0b 8503 /* PowerPC 745 v1.0 */
bd928eba 8504 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
a750fc0b 8505 /* PowerPC 755 v1.0 */
bd928eba 8506 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
a750fc0b 8507 /* PowerPC 745 v1.1 */
bd928eba 8508 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
a750fc0b 8509 /* PowerPC 755 v1.1 */
bd928eba 8510 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
a750fc0b 8511 /* PowerPC 745 v2.0 */
bd928eba 8512 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
a750fc0b 8513 /* PowerPC 755 v2.0 */
bd928eba 8514 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
a750fc0b 8515 /* PowerPC 745 v2.1 */
bd928eba 8516 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
a750fc0b 8517 /* PowerPC 755 v2.1 */
bd928eba 8518 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
a750fc0b 8519 /* PowerPC 745 v2.2 */
bd928eba 8520 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
a750fc0b 8521 /* PowerPC 755 v2.2 */
bd928eba 8522 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
a750fc0b 8523 /* PowerPC 745 v2.3 */
bd928eba 8524 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
a750fc0b 8525 /* PowerPC 755 v2.3 */
bd928eba 8526 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
a750fc0b 8527 /* PowerPC 745 v2.4 */
bd928eba 8528 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
a750fc0b 8529 /* PowerPC 755 v2.4 */
bd928eba 8530 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
a750fc0b 8531 /* PowerPC 745 v2.5 */
bd928eba 8532 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
a750fc0b 8533 /* PowerPC 755 v2.5 */
bd928eba 8534 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
a750fc0b 8535 /* PowerPC 745 v2.6 */
bd928eba 8536 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
a750fc0b 8537 /* PowerPC 755 v2.6 */
bd928eba 8538 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
a750fc0b 8539 /* PowerPC 745 v2.7 */
bd928eba 8540 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
a750fc0b 8541 /* PowerPC 755 v2.7 */
bd928eba 8542 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
a750fc0b 8543 /* PowerPC 745 v2.8 */
bd928eba 8544 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
a750fc0b 8545 /* PowerPC 755 v2.8 */
bd928eba 8546 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
a750fc0b
JM		 8547#if defined (TODO)
8548 /* PowerPC 745P (G3) */
bd928eba 8549 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
a750fc0b 8550 /* PowerPC 755P (G3) */
bd928eba 8551 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
a750fc0b
JM		 8552#endif
8553 /* PowerPC 74xx family */
8554 /* PowerPC 7400 (G4) */
80d11f44 8555 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 8556 /* Code name for PowerPC 7400 */
80d11f44 8557 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 8558 /* PowerPC 74xx is also well known as G4 */
80d11f44 8559 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 8560 /* PowerPC 7400 v1.0 (G4) */
80d11f44 8561 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 8562 /* PowerPC 7400 v1.1 (G4) */
80d11f44 8563 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 8564 /* PowerPC 7400 v2.0 (G4) */
80d11f44 8565 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
4e777442
JM		 8566 /* PowerPC 7400 v2.1 (G4) */
8567 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
a750fc0b 8568 /* PowerPC 7400 v2.2 (G4) */
80d11f44 8569 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 8570 /* PowerPC 7400 v2.6 (G4) */
80d11f44 8571 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 8572 /* PowerPC 7400 v2.7 (G4) */
80d11f44 8573 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 8574 /* PowerPC 7400 v2.8 (G4) */
80d11f44 8575 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 8576 /* PowerPC 7400 v2.9 (G4) */
80d11f44 8577 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 8578 /* PowerPC 7410 (G4) */
80d11f44 8579 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 8580 /* Code name for PowerPC 7410 */
80d11f44 8581 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 8582 /* PowerPC 7410 v1.0 (G4) */
80d11f44 8583 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 8584 /* PowerPC 7410 v1.1 (G4) */
80d11f44 8585 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 8586 /* PowerPC 7410 v1.2 (G4) */
80d11f44 8587 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 8588 /* PowerPC 7410 v1.3 (G4) */
80d11f44 8589 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 8590 /* PowerPC 7410 v1.4 (G4) */
80d11f44 8591 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 8592 /* PowerPC 7448 (G4) */
80d11f44 8593 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 8594 /* PowerPC 7448 v1.0 (G4) */
80d11f44 8595 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 8596 /* PowerPC 7448 v1.1 (G4) */
80d11f44 8597 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 8598 /* PowerPC 7448 v2.0 (G4) */
80d11f44 8599 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 8600 /* PowerPC 7448 v2.1 (G4) */
80d11f44 8601 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 8602 /* PowerPC 7450 (G4) */
80d11f44 8603 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 8604 /* Code name for PowerPC 7450 */
80d11f44 8605 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 8606 /* PowerPC 7450 v1.0 (G4) */
80d11f44 8607 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 8608 /* PowerPC 7450 v1.1 (G4) */
80d11f44 8609 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 8610 /* PowerPC 7450 v1.2 (G4) */
80d11f44 8611 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 8612 /* PowerPC 7450 v2.0 (G4) */
80d11f44 8613 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 8614 /* PowerPC 7450 v2.1 (G4) */
80d11f44 8615 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 8616 /* PowerPC 7441 (G4) */
80d11f44 8617 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 8618 /* PowerPC 7451 (G4) */
80d11f44 8619 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
4e777442
JM		 8620 /* PowerPC 7441 v2.1 (G4) */
8621 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
8622 /* PowerPC 7441 v2.3 (G4) */
8623 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
8624 /* PowerPC 7451 v2.3 (G4) */
8625 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
8626 /* PowerPC 7441 v2.10 (G4) */
8627 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
8628 /* PowerPC 7451 v2.10 (G4) */
8629 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
a750fc0b 8630 /* PowerPC 7445 (G4) */
80d11f44 8631 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 8632 /* PowerPC 7455 (G4) */
80d11f44 8633 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 8634 /* Code name for PowerPC 7445/7455 */
80d11f44 8635 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 8636 /* PowerPC 7445 v1.0 (G4) */
80d11f44 8637 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 8638 /* PowerPC 7455 v1.0 (G4) */
80d11f44 8639 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 8640 /* PowerPC 7445 v2.1 (G4) */
80d11f44 8641 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 8642 /* PowerPC 7455 v2.1 (G4) */
80d11f44 8643 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 8644 /* PowerPC 7445 v3.2 (G4) */
80d11f44 8645 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 8646 /* PowerPC 7455 v3.2 (G4) */
80d11f44 8647 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 8648 /* PowerPC 7445 v3.3 (G4) */
80d11f44 8649 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 8650 /* PowerPC 7455 v3.3 (G4) */
80d11f44 8651 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 8652 /* PowerPC 7445 v3.4 (G4) */
80d11f44 8653 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 8654 /* PowerPC 7455 v3.4 (G4) */
80d11f44 8655 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 8656 /* PowerPC 7447 (G4) */
80d11f44 8657 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 8658 /* PowerPC 7457 (G4) */
80d11f44 8659 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 8660 /* Code name for PowerPC 7447/7457 */
80d11f44 8661 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 8662 /* PowerPC 7447 v1.0 (G4) */
80d11f44 8663 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 8664 /* PowerPC 7457 v1.0 (G4) */
80d11f44 8665 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 8666 /* PowerPC 7447 v1.1 (G4) */
80d11f44 8667 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 8668 /* PowerPC 7457 v1.1 (G4) */
80d11f44 8669 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 8670 /* PowerPC 7457 v1.2 (G4) */
80d11f44 8671 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 8672 /* PowerPC 7447A (G4) */
8673 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
8674 /* PowerPC 7457A (G4) */
8675 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
8676 /* PowerPC 7447A v1.0 (G4) */
8677 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
8678 /* PowerPC 7457A v1.0 (G4) */
8679 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
8680 /* Code name for PowerPC 7447A/7457A */
8681 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
8682 /* PowerPC 7447A v1.1 (G4) */
8683 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
8684 /* PowerPC 7457A v1.1 (G4) */
8685 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
8686 /* PowerPC 7447A v1.2 (G4) */
8687 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
8688 /* PowerPC 7457A v1.2 (G4) */
8689 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 8690 /* 64 bits PowerPC */
8691#if defined (TARGET_PPC64)
a750fc0b 8692 /* PowerPC 620 */
80d11f44 8693 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 8694 /* Code name for PowerPC 620 */
8695 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 8696#if defined (TODO)
a750fc0b 8697 /* PowerPC 630 (POWER3) */
80d11f44
JM		 8698 POWERPC_DEF("630", CPU_POWERPC_630, 630),
8699 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 8700 /* Code names for POWER3 */
8701 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
8702 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 8703#endif
3a607854 8704#if defined (TODO)
a750fc0b 8705 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 8706 POWERPC_DEF("631", CPU_POWERPC_631, 631),
8707 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 8708#endif
8709#if defined (TODO)
a750fc0b 8710 /* POWER4 */
80d11f44 8711 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 8712#endif
3a607854 8713#if defined (TODO)
a750fc0b 8714 /* POWER4p */
80d11f44 8715 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 8716#endif
2662a059 8717#if defined (TODO)
a750fc0b 8718 /* POWER5 */
80d11f44 8719 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 8720 /* POWER5GR */
80d11f44 8721 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 8722#endif
3a607854 8723#if defined (TODO)
a750fc0b 8724 /* POWER5+ */
80d11f44 8725 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 8726 /* POWER5GS */
80d11f44 8727 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 8728#endif
2662a059 8729#if defined (TODO)
a750fc0b 8730 /* POWER6 */
80d11f44 8731 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 8732 /* POWER6 running in POWER5 mode */
80d11f44 8733 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 8734 /* POWER6A */
80d11f44 8735 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 8736#endif
a750fc0b 8737 /* PowerPC 970 */
80d11f44 8738 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 8739 /* PowerPC 970FX (G5) */
80d11f44 8740 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 8741 /* PowerPC 970FX v1.0 (G5) */
80d11f44 8742 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 8743 /* PowerPC 970FX v2.0 (G5) */
80d11f44 8744 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 8745 /* PowerPC 970FX v2.1 (G5) */
80d11f44 8746 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 8747 /* PowerPC 970FX v3.0 (G5) */
80d11f44 8748 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 8749 /* PowerPC 970FX v3.1 (G5) */
80d11f44 8750 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 8751 /* PowerPC 970GX (G5) */
80d11f44 8752 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 8753 /* PowerPC 970MP */
80d11f44 8754 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 8755 /* PowerPC 970MP v1.0 */
80d11f44 8756 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 8757 /* PowerPC 970MP v1.1 */
80d11f44 8758 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 8759#if defined (TODO)
a750fc0b 8760 /* PowerPC Cell */
80d11f44 8761 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 8762#endif
8763#if defined (TODO)
a750fc0b 8764 /* PowerPC Cell v1.0 */
80d11f44 8765 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 8766#endif
8767#if defined (TODO)
a750fc0b 8768 /* PowerPC Cell v2.0 */
80d11f44 8769 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 8770#endif
8771#if defined (TODO)
a750fc0b 8772 /* PowerPC Cell v3.0 */
80d11f44 8773 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 8774#endif
3a607854 8775#if defined (TODO)
a750fc0b 8776 /* PowerPC Cell v3.1 */
80d11f44 8777 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 8778#endif
8779#if defined (TODO)
a750fc0b 8780 /* PowerPC Cell v3.2 */
80d11f44 8781 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 8782#endif
8783#if defined (TODO)
a750fc0b
JM		 8784 /* RS64 (Apache/A35) */
8785 /* This one seems to support the whole POWER2 instruction set
8786 * and the PowerPC 64 one.
8787 */
8788 /* What about A10 & A30 ? */
80d11f44
JM		 8789 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
8790 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
8791 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 8792#endif
8793#if defined (TODO)
a750fc0b 8794 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 8795 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
8796 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
8797 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 8798#endif
8799#if defined (TODO)
a750fc0b 8800 /* RS64-III (Pulsar) */
80d11f44
JM		 8801 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
8802 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 8803#endif
8804#if defined (TODO)
a750fc0b 8805 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 8806 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
8807 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
8808 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
8809 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 8810#endif
a750fc0b
JM		 8811#endif /* defined (TARGET_PPC64) */
8812 /* POWER */
3fc6c082 8813#if defined (TODO)
a750fc0b 8814 /* Original POWER */
80d11f44
JM		 8815 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
8816 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
8817 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
8818 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
8819 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 8820#endif
8821#if defined (TODO)
a750fc0b 8822 /* POWER2 */
80d11f44
JM		 8823 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
8824 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
8825 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 8826#endif
8827 /* PA semi cores */
8828#if defined (TODO)
8829 /* PA PA6T */
80d11f44 8830 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 8831#endif
8832 /* Generic PowerPCs */
8833#if defined (TARGET_PPC64)
80d11f44 8834 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 8835#endif
80d11f44
JM		 8836 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
8837 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 8838 /* Fallback */
80d11f44 8839 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 8840};
8841
8842/*****************************************************************************/
8843/* Generic CPU instanciation routine */
aaed909a 8844static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8845{
8846#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 8847 int i;
8848
a750fc0b 8849 env->irq_inputs = NULL;
e1833e1f
JM		 8850 /* Set all exception vectors to an invalid address */
8851 for (i = 0; i < POWERPC_EXCP_NB; i++)
8852 env->excp_vectors[i] = (target_ulong)(-1ULL);
8853 env->excp_prefix = 0x00000000;
8854 env->ivor_mask = 0x00000000;
8855 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 8856 /* Default MMU definitions */
8857 env->nb_BATs = 0;
8858 env->nb_tlb = 0;
8859 env->nb_ways = 0;
f2e63a42 8860#endif
a750fc0b
JM		 8861 /* Register SPR common to all PowerPC implementations */
8862 gen_spr_generic(env);
8863 spr_register(env, SPR_PVR, "PVR",
8864 SPR_NOACCESS, SPR_NOACCESS,
8865 &spr_read_generic, SPR_NOACCESS,
8866 def->pvr);
80d11f44
JM		 8867 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8868 if (def->svr != POWERPC_SVR_NONE) {
8869 if (def->svr & POWERPC_SVR_E500) {
8870 spr_register(env, SPR_E500_SVR, "SVR",
8871 SPR_NOACCESS, SPR_NOACCESS,
8872 &spr_read_generic, SPR_NOACCESS,
8873 def->svr & ~POWERPC_SVR_E500);
8874 } else {
8875 spr_register(env, SPR_SVR, "SVR",
8876 SPR_NOACCESS, SPR_NOACCESS,
8877 &spr_read_generic, SPR_NOACCESS,
8878 def->svr);
8879 }
8880 }
a750fc0b
JM		 8881 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8882 (*def->init_proc)(env);
25ba3a68
JM		 8883 /* MSR bits & flags consistency checks */
8884 if (env->msr_mask & (1 << 25)) {
8885 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8886 case POWERPC_FLAG_SPE:
8887 case POWERPC_FLAG_VRE:
8888 break;
8889 default:
8890 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8891 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8892 exit(1);
8893 }
8894 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8895 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8896 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8897 exit(1);
8898 }
8899 if (env->msr_mask & (1 << 17)) {
8900 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8901 case POWERPC_FLAG_TGPR:
8902 case POWERPC_FLAG_CE:
8903 break;
8904 default:
8905 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8906 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8907 exit(1);
8908 }
8909 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8910 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8911 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8912 exit(1);
8913 }
8914 if (env->msr_mask & (1 << 10)) {
8915 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8916 POWERPC_FLAG_UBLE)) {
8917 case POWERPC_FLAG_SE:
8918 case POWERPC_FLAG_DWE:
8919 case POWERPC_FLAG_UBLE:
8920 break;
8921 default:
8922 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8923 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8924 "POWERPC_FLAG_UBLE\n");
8925 exit(1);
8926 }
8927 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8928 POWERPC_FLAG_UBLE)) {
8929 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8930 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8931 "POWERPC_FLAG_UBLE\n");
8932 exit(1);
8933 }
8934 if (env->msr_mask & (1 << 9)) {
8935 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8936 case POWERPC_FLAG_BE:
8937 case POWERPC_FLAG_DE:
8938 break;
8939 default:
8940 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8941 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8942 exit(1);
8943 }
8944 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8945 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8946 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8947 exit(1);
8948 }
8949 if (env->msr_mask & (1 << 2)) {
8950 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8951 case POWERPC_FLAG_PX:
8952 case POWERPC_FLAG_PMM:
8953 break;
8954 default:
8955 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8956 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8957 exit(1);
8958 }
8959 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8960 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8961 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8962 exit(1);
8963 }
4018bae9
JM		 8964 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8965 fprintf(stderr, "PowerPC flags inconsistency\n"
8966 "Should define the time-base and decrementer clock source\n");
8967 exit(1);
8968 }
a750fc0b 8969 /* Allocate TLBs buffer when needed */
f2e63a42 8970#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 8971 if (env->nb_tlb != 0) {
8972 int nb_tlb = env->nb_tlb;
8973 if (env->id_tlbs != 0)
8974 nb_tlb *= 2;
8975 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
8976 /* Pre-compute some useful values */
8977 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8978 }
a750fc0b
JM		 8979 if (env->irq_inputs == NULL) {
8980 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8981 " Attempt Qemu to crash very soon !\n");
8982 }
8983#endif
2f462816
JM		 8984 if (env->check_pow == NULL) {
8985 fprintf(stderr, "WARNING: no power management check handler "
8986 "registered.\n"
8987 " Attempt Qemu to crash very soon !\n");
8988 }
a750fc0b
JM		 8989}
8990
8991#if defined(PPC_DUMP_CPU)
8992static void dump_ppc_sprs (CPUPPCState *env)
8993{
8994 ppc_spr_t *spr;
8995#if !defined(CONFIG_USER_ONLY)
8996 uint32_t sr, sw;
8997#endif
8998 uint32_t ur, uw;
8999 int i, j, n;
9000
9001 printf("Special purpose registers:\n");
9002 for (i = 0; i < 32; i++) {
9003 for (j = 0; j < 32; j++) {
9004 n = (i << 5) | j;
9005 spr = &env->spr_cb[n];
9006 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9007 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9008#if !defined(CONFIG_USER_ONLY)
9009 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9010 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9011 if (sw || sr || uw || ur) {
9012 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9013 (i << 5) | j, (i << 5) | j, spr->name,
9014 sw ? 'w' : '-', sr ? 'r' : '-',
9015 uw ? 'w' : '-', ur ? 'r' : '-');
9016 }
9017#else
9018 if (uw || ur) {
9019 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9020 (i << 5) | j, (i << 5) | j, spr->name,
9021 uw ? 'w' : '-', ur ? 'r' : '-');
9022 }
9023#endif
9024 }
9025 }
9026 fflush(stdout);
9027 fflush(stderr);
9028}
9029#endif
9030
9031/*****************************************************************************/
9032#include <stdlib.h>
9033#include <string.h>
9034
a750fc0b
JM		 9035/* Opcode types */
9036enum {
9037 PPC_DIRECT = 0, /* Opcode routine */
9038 PPC_INDIRECT = 1, /* Indirect opcode table */
9039};
9040
9041static inline int is_indirect_opcode (void *handler)
9042{
9043 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9044}
9045
9046static inline opc_handler_t **ind_table(void *handler)
9047{
9048 return (opc_handler_t **)((unsigned long)handler & ~3);
9049}
9050
9051/* Instruction table creation */
9052/* Opcodes tables creation */
9053static void fill_new_table (opc_handler_t **table, int len)
9054{
9055 int i;
9056
9057 for (i = 0; i < len; i++)
9058 table[i] = &invalid_handler;
9059}
9060
9061static int create_new_table (opc_handler_t **table, unsigned char idx)
9062{
9063 opc_handler_t **tmp;
9064
9065 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b
JM		 9066 fill_new_table(tmp, 0x20);
9067 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9068
9069 return 0;
9070}
9071
9072static int insert_in_table (opc_handler_t **table, unsigned char idx,
9073 opc_handler_t *handler)
9074{
9075 if (table[idx] != &invalid_handler)
9076 return -1;
9077 table[idx] = handler;
9078
9079 return 0;
9080}
9081
9082static int register_direct_insn (opc_handler_t **ppc_opcodes,
9083 unsigned char idx, opc_handler_t *handler)
9084{
9085 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9086 printf("*** ERROR: opcode %02x already assigned in main "
9087 "opcode table\n", idx);
4c1b1bfe
JM		 9088#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9089 printf(" Registered handler '%s' - new handler '%s'\n",
9090 ppc_opcodes[idx]->oname, handler->oname);
9091#endif
a750fc0b
JM		 9092 return -1;
9093 }
9094
9095 return 0;
9096}
9097
9098static int register_ind_in_table (opc_handler_t **table,
9099 unsigned char idx1, unsigned char idx2,
9100 opc_handler_t *handler)
9101{
9102 if (table[idx1] == &invalid_handler) {
9103 if (create_new_table(table, idx1) < 0) {
9104 printf("*** ERROR: unable to create indirect table "
9105 "idx=%02x\n", idx1);
9106 return -1;
9107 }
9108 } else {
9109 if (!is_indirect_opcode(table[idx1])) {
9110 printf("*** ERROR: idx %02x already assigned to a direct "
9111 "opcode\n", idx1);
4c1b1bfe
JM		 9112#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9113 printf(" Registered handler '%s' - new handler '%s'\n",
9114 ind_table(table[idx1])[idx2]->oname, handler->oname);
9115#endif
a750fc0b
JM		 9116 return -1;
9117 }
3a607854 9118 }
a750fc0b
JM		 9119 if (handler != NULL &&
9120 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9121 printf("*** ERROR: opcode %02x already assigned in "
9122 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9123#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9124 printf(" Registered handler '%s' - new handler '%s'\n",
9125 ind_table(table[idx1])[idx2]->oname, handler->oname);
9126#endif
a750fc0b 9127 return -1;
3a607854 9128 }
a750fc0b
JM		 9129
9130 return 0;
9131}
9132
9133static int register_ind_insn (opc_handler_t **ppc_opcodes,
9134 unsigned char idx1, unsigned char idx2,
9135 opc_handler_t *handler)
9136{
9137 int ret;
9138
9139 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9140
9141 return ret;
9142}
9143
9144static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9145 unsigned char idx1, unsigned char idx2,
9146 unsigned char idx3, opc_handler_t *handler)
9147{
9148 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9149 printf("*** ERROR: unable to join indirect table idx "
9150 "[%02x-%02x]\n", idx1, idx2);
9151 return -1;
9152 }
9153 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9154 handler) < 0) {
9155 printf("*** ERROR: unable to insert opcode "
9156 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9157 return -1;
9158 }
9159
9160 return 0;
9161}
9162
9163static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9164{
9165 if (insn->opc2 != 0xFF) {
9166 if (insn->opc3 != 0xFF) {
9167 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9168 insn->opc3, &insn->handler) < 0)
9169 return -1;
9170 } else {
9171 if (register_ind_insn(ppc_opcodes, insn->opc1,
9172 insn->opc2, &insn->handler) < 0)
9173 return -1;
9174 }
9175 } else {
9176 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9177 return -1;
9178 }
9179
9180 return 0;
9181}
9182
9183static int test_opcode_table (opc_handler_t **table, int len)
9184{
9185 int i, count, tmp;
9186
9187 for (i = 0, count = 0; i < len; i++) {
9188 /* Consistency fixup */
9189 if (table[i] == NULL)
9190 table[i] = &invalid_handler;
9191 if (table[i] != &invalid_handler) {
9192 if (is_indirect_opcode(table[i])) {
9193 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9194 if (tmp == 0) {
9195 free(table[i]);
9196 table[i] = &invalid_handler;
9197 } else {
9198 count++;
9199 }
9200 } else {
9201 count++;
9202 }
9203 }
9204 }
9205
9206 return count;
9207}
9208
9209static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9210{
9211 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9212 printf("*** WARNING: no opcode defined !\n");
9213}
9214
9215/*****************************************************************************/
aaed909a 9216static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9217{
9218 opcode_t *opc, *start, *end;
9219
9220 fill_new_table(env->opcodes, 0x40);
9221 if (&opc_start < &opc_end) {
9222 start = &opc_start;
9223 end = &opc_end;
9224 } else {
9225 start = &opc_end;
9226 end = &opc_start;
9227 }
9228 for (opc = start + 1; opc != end; opc++) {
9229 if ((opc->handler.type & def->insns_flags) != 0) {
9230 if (register_insn(env->opcodes, opc) < 0) {
9231 printf("*** ERROR initializing PowerPC instruction "
9232 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9233 opc->opc3);
9234 return -1;
9235 }
9236 }
9237 }
9238 fix_opcode_tables(env->opcodes);
9239 fflush(stdout);
9240 fflush(stderr);
9241
9242 return 0;
9243}
9244
9245#if defined(PPC_DUMP_CPU)
25ba3a68 9246static void dump_ppc_insns (CPUPPCState *env)
a750fc0b
JM		 9247{
9248 opc_handler_t **table, *handler;
b55266b5 9249 const char *p, *q;
a750fc0b
JM		 9250 uint8_t opc1, opc2, opc3;
9251
9252 printf("Instructions set:\n");
9253 /* opc1 is 6 bits long */
9254 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9255 table = env->opcodes;
9256 handler = table[opc1];
9257 if (is_indirect_opcode(handler)) {
9258 /* opc2 is 5 bits long */
9259 for (opc2 = 0; opc2 < 0x20; opc2++) {
9260 table = env->opcodes;
9261 handler = env->opcodes[opc1];
9262 table = ind_table(handler);
9263 handler = table[opc2];
9264 if (is_indirect_opcode(handler)) {
9265 table = ind_table(handler);
9266 /* opc3 is 5 bits long */
9267 for (opc3 = 0; opc3 < 0x20; opc3++) {
9268 handler = table[opc3];
9269 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9270 /* Special hack to properly dump SPE insns */
9271 p = strchr(handler->oname, '_');
9272 if (p == NULL) {
9273 printf("INSN: %02x %02x %02x (%02d %04d) : "
9274 "%s\n",
9275 opc1, opc2, opc3, opc1,
9276 (opc3 << 5) | opc2,
9277 handler->oname);
9278 } else {
9279 q = "speundef";
9280 if ((p - handler->oname) != strlen(q) ||
9281 memcmp(handler->oname, q, strlen(q)) != 0) {
9282 /* First instruction */
9283 printf("INSN: %02x %02x %02x (%02d %04d) : "
9284 "%.*s\n",
9285 opc1, opc2 << 1, opc3, opc1,
9286 (opc3 << 6) | (opc2 << 1),
9287 (int)(p - handler->oname),
9288 handler->oname);
9289 }
9290 if (strcmp(p + 1, q) != 0) {
9291 /* Second instruction */
9292 printf("INSN: %02x %02x %02x (%02d %04d) : "
9293 "%s\n",
9294 opc1, (opc2 << 1) | 1, opc3, opc1,
9295 (opc3 << 6) | (opc2 << 1) | 1,
9296 p + 1);
9297 }
9298 }
a750fc0b
JM		 9299 }
9300 }
9301 } else {
9302 if (handler->handler != &gen_invalid) {
9303 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9304 opc1, opc2, opc1, opc2, handler->oname);
9305 }
9306 }
9307 }
9308 } else {
9309 if (handler->handler != &gen_invalid) {
9310 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9311 opc1, opc1, handler->oname);
9312 }
9313 }
9314 }
9315}
3a607854 9316#endif
a750fc0b 9317
24951522
AJ		 9318static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9319{
9320 if (n < 32) {
9321 stfq_p(mem_buf, env->fpr[n]);
9322 return 8;
9323 }
9324 if (n == 32) {
9325 /* FPSCR not implemented */
9326 memset(mem_buf, 0, 4);
9327 return 4;
9328 }
9329 return 0;
9330}
9331
9332static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9333{
9334 if (n < 32) {
9335 env->fpr[n] = ldfq_p(mem_buf);
9336 return 8;
9337 }
9338 if (n == 32) {
9339 /* FPSCR not implemented */
9340 return 4;
9341 }
9342 return 0;
9343}
9344
b4f8d821
AJ		 9345static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9346{
9347 if (n < 32) {
9348#ifdef WORDS_BIGENDIAN
9349 stq_p(mem_buf, env->avr[n].u64[0]);
9350 stq_p(mem_buf+8, env->avr[n].u64[1]);
9351#else
9352 stq_p(mem_buf, env->avr[n].u64[1]);
9353 stq_p(mem_buf+8, env->avr[n].u64[0]);
9354#endif
9355 return 16;
9356 }
9357 if (n == 33) {
9358 stl_p(mem_buf, env->vscr);
9359 return 4;
9360 }
9361 if (n == 34) {
9362 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9363 return 4;
9364 }
9365 return 0;
9366}
9367
9368static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9369{
9370 if (n < 32) {
9371#ifdef WORDS_BIGENDIAN
9372 env->avr[n].u64[0] = ldq_p(mem_buf);
9373 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9374#else
9375 env->avr[n].u64[1] = ldq_p(mem_buf);
9376 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9377#endif
9378 return 16;
9379 }
9380 if (n == 33) {
9381 env->vscr = ldl_p(mem_buf);
9382 return 4;
9383 }
9384 if (n == 34) {
9385 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9386 return 4;
9387 }
9388 return 0;
9389}
9390
688890f7
AJ		 9391static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9392{
9393 if (n < 32) {
9394#if defined(TARGET_PPC64)
9395 stl_p(mem_buf, env->gpr[n] >> 32);
9396#else
9397 stl_p(mem_buf, env->gprh[n]);
9398#endif
9399 return 4;
9400 }
9401 if (n == 33) {
9402 stq_p(mem_buf, env->spe_acc);
9403 return 8;
9404 }
9405 if (n == 34) {
9406 /* SPEFSCR not implemented */
9407 memset(mem_buf, 0, 4);
9408 return 4;
9409 }
9410 return 0;
9411}
9412
9413static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9414{
9415 if (n < 32) {
9416#if defined(TARGET_PPC64)
9417 target_ulong lo = (uint32_t)env->gpr[n];
9418 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9419 env->gpr[n] = lo | hi;
9420#else
9421 env->gprh[n] = ldl_p(mem_buf);
9422#endif
9423 return 4;
9424 }
9425 if (n == 33) {
9426 env->spe_acc = ldq_p(mem_buf);
9427 return 8;
9428 }
9429 if (n == 34) {
9430 /* SPEFSCR not implemented */
9431 return 4;
9432 }
9433 return 0;
9434}
9435
aaed909a 9436int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9437{
9438 env->msr_mask = def->msr_mask;
9439 env->mmu_model = def->mmu_model;
9440 env->excp_model = def->excp_model;
9441 env->bus_model = def->bus_model;
d26bfc9a 9442 env->flags = def->flags;
237c0af0 9443 env->bfd_mach = def->bfd_mach;
2f462816 9444 env->check_pow = def->check_pow;
a750fc0b
JM		 9445 if (create_ppc_opcodes(env, def) < 0)
9446 return -1;
9447 init_ppc_proc(env, def);
24951522
AJ		 9448
9449 if (def->insns_flags & PPC_FLOAT) {
9450 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9451 33, "power-fpu.xml", 0);
9452 }
b4f8d821
AJ		 9453 if (def->insns_flags & PPC_ALTIVEC) {
9454 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9455 34, "power-altivec.xml", 0);
9456 }
40569b7e 9457 if (def->insns_flags & PPC_SPE) {
688890f7
AJ		 9458 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9459 34, "power-spe.xml", 0);
9460 }
9461
a750fc0b 9462#if defined(PPC_DUMP_CPU)
3a607854 9463 {
b55266b5 9464 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 9465 switch (env->mmu_model) {
9466 case POWERPC_MMU_32B:
9467 mmu_model = "PowerPC 32";
9468 break;
a750fc0b
JM		 9469 case POWERPC_MMU_SOFT_6xx:
9470 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9471 break;
9472 case POWERPC_MMU_SOFT_74xx:
9473 mmu_model = "PowerPC 74xx with software driven TLBs";
9474 break;
9475 case POWERPC_MMU_SOFT_4xx:
9476 mmu_model = "PowerPC 4xx with software driven TLBs";
9477 break;
9478 case POWERPC_MMU_SOFT_4xx_Z:
9479 mmu_model = "PowerPC 4xx with software driven TLBs "
9480 "and zones protections";
9481 break;
b4095fed
JM		 9482 case POWERPC_MMU_REAL:
9483 mmu_model = "PowerPC real mode only";
9484 break;
9485 case POWERPC_MMU_MPC8xx:
9486 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 9487 break;
9488 case POWERPC_MMU_BOOKE:
9489 mmu_model = "PowerPC BookE";
9490 break;
9491 case POWERPC_MMU_BOOKE_FSL:
9492 mmu_model = "PowerPC BookE FSL";
9493 break;
b4095fed
JM		 9494 case POWERPC_MMU_601:
9495 mmu_model = "PowerPC 601";
9496 break;
00af685f
JM		 9497#if defined (TARGET_PPC64)
9498 case POWERPC_MMU_64B:
9499 mmu_model = "PowerPC 64";
9500 break;
add78955
JM		 9501 case POWERPC_MMU_620:
9502 mmu_model = "PowerPC 620";
9503 break;
00af685f 9504#endif
a750fc0b
JM		 9505 default:
9506 mmu_model = "Unknown or invalid";
9507 break;
9508 }
9509 switch (env->excp_model) {
9510 case POWERPC_EXCP_STD:
9511 excp_model = "PowerPC";
9512 break;
9513 case POWERPC_EXCP_40x:
9514 excp_model = "PowerPC 40x";
9515 break;
9516 case POWERPC_EXCP_601:
9517 excp_model = "PowerPC 601";
9518 break;
9519 case POWERPC_EXCP_602:
9520 excp_model = "PowerPC 602";
9521 break;
9522 case POWERPC_EXCP_603:
9523 excp_model = "PowerPC 603";
9524 break;
9525 case POWERPC_EXCP_603E:
9526 excp_model = "PowerPC 603e";
9527 break;
9528 case POWERPC_EXCP_604:
9529 excp_model = "PowerPC 604";
9530 break;
9531 case POWERPC_EXCP_7x0:
9532 excp_model = "PowerPC 740/750";
9533 break;
9534 case POWERPC_EXCP_7x5:
9535 excp_model = "PowerPC 745/755";
9536 break;
9537 case POWERPC_EXCP_74xx:
9538 excp_model = "PowerPC 74xx";
9539 break;
a750fc0b
JM		 9540 case POWERPC_EXCP_BOOKE:
9541 excp_model = "PowerPC BookE";
9542 break;
00af685f
JM		 9543#if defined (TARGET_PPC64)
9544 case POWERPC_EXCP_970:
9545 excp_model = "PowerPC 970";
9546 break;
9547#endif
a750fc0b
JM		 9548 default:
9549 excp_model = "Unknown or invalid";
9550 break;
9551 }
9552 switch (env->bus_model) {
9553 case PPC_FLAGS_INPUT_6xx:
9554 bus_model = "PowerPC 6xx";
9555 break;
9556 case PPC_FLAGS_INPUT_BookE:
9557 bus_model = "PowerPC BookE";
9558 break;
9559 case PPC_FLAGS_INPUT_405:
9560 bus_model = "PowerPC 405";
9561 break;
a750fc0b
JM		 9562 case PPC_FLAGS_INPUT_401:
9563 bus_model = "PowerPC 401/403";
9564 break;
b4095fed
JM		 9565 case PPC_FLAGS_INPUT_RCPU:
9566 bus_model = "RCPU / MPC8xx";
9567 break;
00af685f
JM		 9568#if defined (TARGET_PPC64)
9569 case PPC_FLAGS_INPUT_970:
9570 bus_model = "PowerPC 970";
9571 break;
9572#endif
a750fc0b
JM		 9573 default:
9574 bus_model = "Unknown or invalid";
9575 break;
9576 }
9577 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9578 " MMU model : %s\n",
9579 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 9580#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9581 if (env->tlb != NULL) {
9582 printf(" %d %s TLB in %d ways\n",
9583 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9584 env->nb_ways);
9585 }
f2e63a42 9586#endif
a750fc0b
JM		 9587 printf(" Exceptions model : %s\n"
9588 " Bus model : %s\n",
9589 excp_model, bus_model);
25ba3a68
JM		 9590 printf(" MSR features :\n");
9591 if (env->flags & POWERPC_FLAG_SPE)
9592 printf(" signal processing engine enable"
9593 "\n");
9594 else if (env->flags & POWERPC_FLAG_VRE)
9595 printf(" vector processor enable\n");
9596 if (env->flags & POWERPC_FLAG_TGPR)
9597 printf(" temporary GPRs\n");
9598 else if (env->flags & POWERPC_FLAG_CE)
9599 printf(" critical input enable\n");
9600 if (env->flags & POWERPC_FLAG_SE)
9601 printf(" single-step trace mode\n");
9602 else if (env->flags & POWERPC_FLAG_DWE)
9603 printf(" debug wait enable\n");
9604 else if (env->flags & POWERPC_FLAG_UBLE)
9605 printf(" user BTB lock enable\n");
9606 if (env->flags & POWERPC_FLAG_BE)
9607 printf(" branch-step trace mode\n");
9608 else if (env->flags & POWERPC_FLAG_DE)
9609 printf(" debug interrupt enable\n");
9610 if (env->flags & POWERPC_FLAG_PX)
9611 printf(" inclusive protection\n");
9612 else if (env->flags & POWERPC_FLAG_PMM)
9613 printf(" performance monitor mark\n");
9614 if (env->flags == POWERPC_FLAG_NONE)
9615 printf(" none\n");
4018bae9
JM		 9616 printf(" Time-base/decrementer clock source: %s\n",
9617 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 9618 }
9619 dump_ppc_insns(env);
9620 dump_ppc_sprs(env);
9621 fflush(stdout);
3a607854 9622#endif
a750fc0b
JM		 9623
9624 return 0;
9625}
3fc6c082 9626
ee4e83ed 9627static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 9628{
ee4e83ed
JM		 9629 const ppc_def_t *ret;
9630 uint32_t pvr_rev;
9631 int i, best, match, best_match, max;
3fc6c082 9632
ee4e83ed 9633 ret = NULL;
b1503cda 9634 max = ARRAY_SIZE(ppc_defs);
ee4e83ed
JM		 9635 best = -1;
9636 pvr_rev = pvr & 0xFFFF;
9637 /* We want all specified bits to match */
9638 best_match = 32 - ctz32(pvr_rev);
068abdc8 9639 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9640 /* We check that the 16 higher bits are the same to ensure the CPU
9641 * model will be the choosen one.
9642 */
9643 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9644 /* We want as much as possible of the low-level 16 bits
9645 * to be the same but we allow inexact matches.
9646 */
9647 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9648 /* We check '>=' instead of '>' because the PPC_defs table
9649 * is ordered by increasing revision.
4c1b1bfe 9650 * Then, we will match the higher revision compatible
ee4e83ed
JM		 9651 * with the requested PVR
9652 */
9653 if (match >= best_match) {
9654 best = i;
9655 best_match = match;
9656 }
3fc6c082
FB		 9657 }
9658 }
ee4e83ed
JM		 9659 if (best != -1)
9660 ret = &ppc_defs[best];
9661
9662 return ret;
3fc6c082
FB		 9663}
9664
ee4e83ed 9665#include <ctype.h>
3fc6c082 9666
b55266b5 9667const ppc_def_t *cpu_ppc_find_by_name (const char *name)
ee4e83ed
JM		 9668{
9669 const ppc_def_t *ret;
b55266b5 9670 const char *p;
ee4e83ed
JM		 9671 int i, max, len;
9672
9673 /* Check if the given name is a PVR */
9674 len = strlen(name);
9675 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9676 p = name + 2;
9677 goto check_pvr;
9678 } else if (len == 8) {
9679 p = name;
9680 check_pvr:
9681 for (i = 0; i < 8; i++) {
cd390083 9682 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 9683 break;
9684 }
9685 if (i == 8)
9686 return ppc_find_by_pvr(strtoul(name, NULL, 16));
9687 }
9688 ret = NULL;
b1503cda 9689 max = ARRAY_SIZE(ppc_defs);
068abdc8 9690 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9691 if (strcasecmp(name, ppc_defs[i].name) == 0) {
9692 ret = &ppc_defs[i];
9693 break;
3fc6c082
FB		 9694 }
9695 }
ee4e83ed
JM		 9696
9697 return ret;
3fc6c082
FB		 9698}
9699
9700void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
9701{
068abdc8 9702 int i, max;
3fc6c082 9703
b1503cda 9704 max = ARRAY_SIZE(ppc_defs);
068abdc8 9705 for (i = 0; i < max; i++) {
a750fc0b
JM		 9706 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9707 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 9708 }
9709}
Qemu copy for testing