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cpu: Replace do_interrupt() by CPUClass::do_interrupt method
[qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
31
9349b4f9 32#define CPUArchState struct CPUS390XState
10ec5117 33
022c62cb 34#include "exec/cpu-defs.h"
bcec36ea
AG		 35#define TARGET_PAGE_BITS 12
36
37#define TARGET_PHYS_ADDR_SPACE_BITS 64
38#define TARGET_VIRT_ADDR_SPACE_BITS 64
39
022c62cb 40#include "exec/cpu-all.h"
10ec5117 41
6b4c305c 42#include "fpu/softfloat.h"
10ec5117 43
bcec36ea 44#define NB_MMU_MODES 3
10ec5117 45
bcec36ea
AG		 46#define MMU_MODE0_SUFFIX _primary
47#define MMU_MODE1_SUFFIX _secondary
48#define MMU_MODE2_SUFFIX _home
49
50#define MMU_USER_IDX 1
51
52#define MAX_EXT_QUEUE 16
5d69c547
CH		 53#define MAX_IO_QUEUE 16
54#define MAX_MCHK_QUEUE 16
55
56#define PSW_MCHK_MASK 0x0004000000000000
57#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 58
59typedef struct PSW {
60 uint64_t mask;
61 uint64_t addr;
62} PSW;
63
64typedef struct ExtQueue {
65 uint32_t code;
66 uint32_t param;
67 uint32_t param64;
68} ExtQueue;
10ec5117 69
5d69c547
CH		 70typedef struct IOIntQueue {
71 uint16_t id;
72 uint16_t nr;
73 uint32_t parm;
74 uint32_t word;
75} IOIntQueue;
76
77typedef struct MchkQueue {
78 uint16_t type;
79} MchkQueue;
80
10ec5117 81typedef struct CPUS390XState {
1ac5889f
RH		 82 uint64_t regs[16]; /* GP registers */
83 CPU_DoubleU fregs[16]; /* FP registers */
84 uint32_t aregs[16]; /* access registers */
10ec5117 85
1ac5889f
RH		 86 uint32_t fpc; /* floating-point control register */
87 uint32_t cc_op;
10ec5117 88
10ec5117
AG		 89 float_status fpu_status; /* passed to softfloat lib */
90
1ac5889f
RH		 91 /* The low part of a 128-bit return, or remainder of a divide. */
92 uint64_t retxl;
93
bcec36ea 94 PSW psw;
10ec5117 95
bcec36ea
AG		 96 uint64_t cc_src;
97 uint64_t cc_dst;
98 uint64_t cc_vr;
10ec5117
AG		 99
100 uint64_t __excp_addr;
bcec36ea
AG		 101 uint64_t psa;
102
103 uint32_t int_pgm_code;
d5a103cd 104 uint32_t int_pgm_ilen;
bcec36ea
AG		 105
106 uint32_t int_svc_code;
d5a103cd 107 uint32_t int_svc_ilen;
bcec36ea
AG		 108
109 uint64_t cregs[16]; /* control registers */
110
bcec36ea 111 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 112 IOIntQueue io_queue[MAX_IO_QUEUE][8];
113 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 114
5d69c547 115 int pending_int;
4e836781 116 int ext_index;
5d69c547
CH		 117 int io_index[8];
118 int mchk_index;
119
120 uint64_t ckc;
121 uint64_t cputm;
122 uint32_t todpr;
4e836781
AG		 123
124 CPU_COMMON
125
bcec36ea
AG		 126 /* reset does memset(0) up to here */
127
bcec36ea
AG		 128 int cpu_num;
129 uint8_t *storage_keys;
130
131 uint64_t tod_offset;
132 uint64_t tod_basetime;
133 QEMUTimer *tod_timer;
134
135 QEMUTimer *cpu_timer;
10ec5117
AG		 136} CPUS390XState;
137
564b863d
AF		 138#include "cpu-qom.h"
139
10ec5117 140#if defined(CONFIG_USER_ONLY)
a4e3ad19 141static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
10ec5117 142{
bcec36ea 143 if (newsp) {
10ec5117 144 env->regs[15] = newsp;
bcec36ea 145 }
90b4f8ad 146 env->regs[2] = 0;
10ec5117
AG		 147}
148#endif
149
7b18aad5
CH		 150/* distinguish between 24 bit and 31 bit addressing */
151#define HIGH_ORDER_BIT 0x80000000
152
bcec36ea
AG		 153/* Interrupt Codes */
154/* Program Interrupts */
155#define PGM_OPERATION 0x0001
156#define PGM_PRIVILEGED 0x0002
157#define PGM_EXECUTE 0x0003
158#define PGM_PROTECTION 0x0004
159#define PGM_ADDRESSING 0x0005
160#define PGM_SPECIFICATION 0x0006
161#define PGM_DATA 0x0007
162#define PGM_FIXPT_OVERFLOW 0x0008
163#define PGM_FIXPT_DIVIDE 0x0009
164#define PGM_DEC_OVERFLOW 0x000a
165#define PGM_DEC_DIVIDE 0x000b
166#define PGM_HFP_EXP_OVERFLOW 0x000c
167#define PGM_HFP_EXP_UNDERFLOW 0x000d
168#define PGM_HFP_SIGNIFICANCE 0x000e
169#define PGM_HFP_DIVIDE 0x000f
170#define PGM_SEGMENT_TRANS 0x0010
171#define PGM_PAGE_TRANS 0x0011
172#define PGM_TRANS_SPEC 0x0012
173#define PGM_SPECIAL_OP 0x0013
174#define PGM_OPERAND 0x0015
175#define PGM_TRACE_TABLE 0x0016
176#define PGM_SPACE_SWITCH 0x001c
177#define PGM_HFP_SQRT 0x001d
178#define PGM_PC_TRANS_SPEC 0x001f
179#define PGM_AFX_TRANS 0x0020
180#define PGM_ASX_TRANS 0x0021
181#define PGM_LX_TRANS 0x0022
182#define PGM_EX_TRANS 0x0023
183#define PGM_PRIM_AUTH 0x0024
184#define PGM_SEC_AUTH 0x0025
185#define PGM_ALET_SPEC 0x0028
186#define PGM_ALEN_SPEC 0x0029
187#define PGM_ALE_SEQ 0x002a
188#define PGM_ASTE_VALID 0x002b
189#define PGM_ASTE_SEQ 0x002c
190#define PGM_EXT_AUTH 0x002d
191#define PGM_STACK_FULL 0x0030
192#define PGM_STACK_EMPTY 0x0031
193#define PGM_STACK_SPEC 0x0032
194#define PGM_STACK_TYPE 0x0033
195#define PGM_STACK_OP 0x0034
196#define PGM_ASCE_TYPE 0x0038
197#define PGM_REG_FIRST_TRANS 0x0039
198#define PGM_REG_SEC_TRANS 0x003a
199#define PGM_REG_THIRD_TRANS 0x003b
200#define PGM_MONITOR 0x0040
201#define PGM_PER 0x0080
202#define PGM_CRYPTO 0x0119
203
204/* External Interrupts */
205#define EXT_INTERRUPT_KEY 0x0040
206#define EXT_CLOCK_COMP 0x1004
207#define EXT_CPU_TIMER 0x1005
208#define EXT_MALFUNCTION 0x1200
209#define EXT_EMERGENCY 0x1201
210#define EXT_EXTERNAL_CALL 0x1202
211#define EXT_ETR 0x1406
212#define EXT_SERVICE 0x2401
213#define EXT_VIRTIO 0x2603
214
215/* PSW defines */
216#undef PSW_MASK_PER
217#undef PSW_MASK_DAT
218#undef PSW_MASK_IO
219#undef PSW_MASK_EXT
220#undef PSW_MASK_KEY
221#undef PSW_SHIFT_KEY
222#undef PSW_MASK_MCHECK
223#undef PSW_MASK_WAIT
224#undef PSW_MASK_PSTATE
225#undef PSW_MASK_ASC
226#undef PSW_MASK_CC
227#undef PSW_MASK_PM
228#undef PSW_MASK_64
229
230#define PSW_MASK_PER 0x4000000000000000ULL
231#define PSW_MASK_DAT 0x0400000000000000ULL
232#define PSW_MASK_IO 0x0200000000000000ULL
233#define PSW_MASK_EXT 0x0100000000000000ULL
234#define PSW_MASK_KEY 0x00F0000000000000ULL
235#define PSW_SHIFT_KEY 56
236#define PSW_MASK_MCHECK 0x0004000000000000ULL
237#define PSW_MASK_WAIT 0x0002000000000000ULL
238#define PSW_MASK_PSTATE 0x0001000000000000ULL
239#define PSW_MASK_ASC 0x0000C00000000000ULL
240#define PSW_MASK_CC 0x0000300000000000ULL
241#define PSW_MASK_PM 0x00000F0000000000ULL
242#define PSW_MASK_64 0x0000000100000000ULL
243#define PSW_MASK_32 0x0000000080000000ULL
244
245#undef PSW_ASC_PRIMARY
246#undef PSW_ASC_ACCREG
247#undef PSW_ASC_SECONDARY
248#undef PSW_ASC_HOME
249
250#define PSW_ASC_PRIMARY 0x0000000000000000ULL
251#define PSW_ASC_ACCREG 0x0000400000000000ULL
252#define PSW_ASC_SECONDARY 0x0000800000000000ULL
253#define PSW_ASC_HOME 0x0000C00000000000ULL
254
255/* tb flags */
256
257#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
258#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
259#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
260#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
261#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
262#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
263#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
264#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
265#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
266#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
267#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
268#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
269#define FLAG_MASK_32 0x00001000
270
a4e3ad19 271static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 272{
bcec36ea
AG		 273 if (env->psw.mask & PSW_MASK_PSTATE) {
274 return 1;
275 }
276
10c339a0
AG		 277 return 0;
278}
279
a4e3ad19 280static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 281 target_ulong *cs_base, int *flags)
282{
283 *pc = env->psw.addr;
284 *cs_base = 0;
285 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
286 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
287}
288
d5a103cd
RH		 289/* While the PoO talks about ILC (a number between 1-3) what is actually
290 stored in LowCore is shifted left one bit (an even between 2-6). As
291 this is the actual length of the insn and therefore more useful, that
292 is what we want to pass around and manipulate. To make sure that we
293 have applied this distinction universally, rename the "ILC" to "ILEN". */
294static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 295{
296 switch (opc >> 6) {
297 case 0:
d5a103cd 298 return 2;
bcec36ea
AG		 299 case 1:
300 case 2:
d5a103cd
RH		 301 return 4;
302 default:
303 return 6;
bcec36ea 304 }
bcec36ea
AG		 305}
306
d5a103cd
RH		 307#ifndef CONFIG_USER_ONLY
308/* In several cases of runtime exceptions, we havn't recorded the true
309 instruction length. Use these codes when raising exceptions in order
310 to re-compute the length by examining the insn in memory. */
311#define ILEN_LATER 0x20
312#define ILEN_LATER_INC 0x21
313#endif
bcec36ea 314
564b863d 315S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 316void s390x_translate_init(void);
10ec5117 317int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 318
319/* you can call this signal handler from your SIGBUS and SIGSEGV
320 signal handlers to inform the virtual CPU of exceptions. non zero
321 is returned if the signal was handled by the virtual CPU. */
322int cpu_s390x_signal_handler(int host_signum, void *pinfo,
323 void *puc);
324int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
97b348e7 325 int mmu_idx);
10ec5117
AG		 326#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
327
db1c8f53 328#include "ioinst.h"
52705890 329
10c339a0 330#ifndef CONFIG_USER_ONLY
38322ed6
CH		 331void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
332 int is_write);
333void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
334 int is_write);
7b18aad5
CH		 335static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
336{
337 hwaddr addr = 0;
338 uint8_t reg;
339
340 reg = ipb >> 28;
341 if (reg > 0) {
342 addr = env->regs[reg];
343 }
344 addr += (ipb >> 16) & 0xfff;
345
346 return addr;
347}
348
8f22e0df
AF		 349void s390x_tod_timer(void *opaque);
350void s390x_cpu_timer(void *opaque);
351
28e942f8 352int s390_virtio_hypercall(CPUS390XState *env);
bcec36ea 353
1f206266 354#ifdef CONFIG_KVM
1bc22652
AF		 355void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
356void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
357void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
bcec36ea 358 uint64_t parm64, int vm);
1f206266 359#else
1bc22652 360static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
1f206266
AG		 361{
362}
363
1bc22652 364static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
1f206266
AG		 365 uint64_t token)
366{
367}
368
1bc22652 369static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
1f206266
AG		 370 uint32_t parm, uint64_t parm64,
371 int vm)
372{
373}
374#endif
45fa769b 375S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
49e15878
AF		 376void s390_add_running_cpu(S390CPU *cpu);
377unsigned s390_del_running_cpu(S390CPU *cpu);
bcec36ea 378
000a1a38
CB		 379/* service interrupts are floating therefore we must not pass an cpustate */
380void s390_sclp_extint(uint32_t parm);
381
d1ff903c 382/* from s390-virtio-bus */
a8170e5e 383extern const hwaddr virtio_size;
d1ff903c 384
ef81522b 385#else
49e15878 386static inline void s390_add_running_cpu(S390CPU *cpu)
ef81522b
AG		 387{
388}
389
49e15878 390static inline unsigned s390_del_running_cpu(S390CPU *cpu)
ef81522b
AG		 391{
392 return 0;
393}
10c339a0 394#endif
bcec36ea
AG		 395void cpu_lock(void);
396void cpu_unlock(void);
10c339a0 397
7b18aad5
CH		 398typedef struct SubchDev SubchDev;
399
df1fe5bb
CH		 400#ifndef CONFIG_USER_ONLY
401SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
402 uint16_t schid);
403bool css_subch_visible(SubchDev *sch);
404void css_conditional_io_interrupt(SubchDev *sch);
405int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 406bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
df1fe5bb
CH		 407int css_do_msch(SubchDev *sch, SCHIB *schib);
408int css_do_xsch(SubchDev *sch);
409int css_do_csch(SubchDev *sch);
410int css_do_hsch(SubchDev *sch);
411int css_do_ssch(SubchDev *sch, ORB *orb);
412int css_do_tsch(SubchDev *sch, IRB *irb);
413int css_do_stcrw(CRW *crw);
50c8d9bf 414int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 415int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
416 int rfmt, void *buf);
417void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
418int css_enable_mcsse(void);
419int css_enable_mss(void);
420int css_do_rsch(SubchDev *sch);
421int css_do_rchp(uint8_t cssid, uint8_t chpid);
422bool css_present(uint8_t cssid);
423#else
7b18aad5
CH		 424static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
425 uint16_t schid)
426{
427 return NULL;
428}
429static inline bool css_subch_visible(SubchDev *sch)
430{
431 return false;
432}
433static inline void css_conditional_io_interrupt(SubchDev *sch)
434{
435}
436static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
437{
438 return -ENODEV;
439}
440static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
441{
442 return true;
443}
444static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
445{
446 return -ENODEV;
447}
448static inline int css_do_xsch(SubchDev *sch)
449{
450 return -ENODEV;
451}
452static inline int css_do_csch(SubchDev *sch)
453{
454 return -ENODEV;
455}
456static inline int css_do_hsch(SubchDev *sch)
457{
458 return -ENODEV;
459}
460static inline int css_do_ssch(SubchDev *sch, ORB *orb)
461{
462 return -ENODEV;
463}
464static inline int css_do_tsch(SubchDev *sch, IRB *irb)
465{
466 return -ENODEV;
467}
468static inline int css_do_stcrw(CRW *crw)
469{
470 return 1;
471}
50c8d9bf 472static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
7b18aad5
CH		 473{
474 return 0;
475}
476static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
477 int rfmt, uint8_t l_chpid, void *buf)
478{
479 return 0;
480}
481static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
482{
483}
484static inline int css_enable_mss(void)
485{
486 return -EINVAL;
487}
488static inline int css_enable_mcsse(void)
489{
490 return -EINVAL;
491}
492static inline int css_do_rsch(SubchDev *sch)
493{
494 return -ENODEV;
495}
496static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
497{
498 return -ENODEV;
499}
500static inline bool css_present(uint8_t cssid)
501{
502 return false;
503}
df1fe5bb 504#endif
7b18aad5 505
bcec36ea
AG		 506static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
507{
508 env->aregs[0] = newtls >> 32;
509 env->aregs[1] = newtls & 0xffffffffULL;
510}
10c339a0 511
564b863d 512#define cpu_init(model) (&cpu_s390x_init(model)->env)
10ec5117
AG		 513#define cpu_exec cpu_s390x_exec
514#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 515#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 516
904e5fd5
VM		 517void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
518#define cpu_list s390_cpu_list
519
022c62cb 520#include "exec/exec-all.h"
bcec36ea 521
bcec36ea
AG		 522#define EXCP_EXT 1 /* external interrupt */
523#define EXCP_SVC 2 /* supervisor call (syscall) */
524#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 525#define EXCP_IO 7 /* I/O interrupt */
526#define EXCP_MCHK 8 /* machine check */
bcec36ea 527
bcec36ea
AG		 528#define INTERRUPT_EXT (1 << 0)
529#define INTERRUPT_TOD (1 << 1)
530#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 531#define INTERRUPT_IO (1 << 3)
532#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 533
534/* Program Status Word. */
535#define S390_PSWM_REGNUM 0
536#define S390_PSWA_REGNUM 1
537/* General Purpose Registers. */
538#define S390_R0_REGNUM 2
539#define S390_R1_REGNUM 3
540#define S390_R2_REGNUM 4
541#define S390_R3_REGNUM 5
542#define S390_R4_REGNUM 6
543#define S390_R5_REGNUM 7
544#define S390_R6_REGNUM 8
545#define S390_R7_REGNUM 9
546#define S390_R8_REGNUM 10
547#define S390_R9_REGNUM 11
548#define S390_R10_REGNUM 12
549#define S390_R11_REGNUM 13
550#define S390_R12_REGNUM 14
551#define S390_R13_REGNUM 15
552#define S390_R14_REGNUM 16
553#define S390_R15_REGNUM 17
554/* Access Registers. */
555#define S390_A0_REGNUM 18
556#define S390_A1_REGNUM 19
557#define S390_A2_REGNUM 20
558#define S390_A3_REGNUM 21
559#define S390_A4_REGNUM 22
560#define S390_A5_REGNUM 23
561#define S390_A6_REGNUM 24
562#define S390_A7_REGNUM 25
563#define S390_A8_REGNUM 26
564#define S390_A9_REGNUM 27
565#define S390_A10_REGNUM 28
566#define S390_A11_REGNUM 29
567#define S390_A12_REGNUM 30
568#define S390_A13_REGNUM 31
569#define S390_A14_REGNUM 32
570#define S390_A15_REGNUM 33
571/* Floating Point Control Word. */
572#define S390_FPC_REGNUM 34
573/* Floating Point Registers. */
574#define S390_F0_REGNUM 35
575#define S390_F1_REGNUM 36
576#define S390_F2_REGNUM 37
577#define S390_F3_REGNUM 38
578#define S390_F4_REGNUM 39
579#define S390_F5_REGNUM 40
580#define S390_F6_REGNUM 41
581#define S390_F7_REGNUM 42
582#define S390_F8_REGNUM 43
583#define S390_F9_REGNUM 44
584#define S390_F10_REGNUM 45
585#define S390_F11_REGNUM 46
586#define S390_F12_REGNUM 47
587#define S390_F13_REGNUM 48
588#define S390_F14_REGNUM 49
589#define S390_F15_REGNUM 50
590/* Total. */
591#define S390_NUM_REGS 51
592
bcec36ea
AG		 593/* CC optimization */
594
595enum cc_op {
596 CC_OP_CONST0 = 0, /* CC is 0 */
597 CC_OP_CONST1, /* CC is 1 */
598 CC_OP_CONST2, /* CC is 2 */
599 CC_OP_CONST3, /* CC is 3 */
600
601 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
602 CC_OP_STATIC, /* CC value is env->cc_op */
603
604 CC_OP_NZ, /* env->cc_dst != 0 */
605 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
606 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
607 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
608 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
609 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
610 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
611
612 CC_OP_ADD_64, /* overflow on add (64bit) */
613 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 614 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 615 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
616 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 617 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 618 CC_OP_ABS_64, /* sign eval on abs (64bit) */
619 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
620
621 CC_OP_ADD_32, /* overflow on add (32bit) */
622 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 623 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 624 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
625 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 626 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 627 CC_OP_ABS_32, /* sign eval on abs (64bit) */
628 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
629
630 CC_OP_COMP_32, /* complement */
631 CC_OP_COMP_64, /* complement */
632
633 CC_OP_TM_32, /* test under mask (32bit) */
634 CC_OP_TM_64, /* test under mask (64bit) */
635
bcec36ea
AG		 636 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
637 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 638 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 639
640 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 641 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
642 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 643 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 644 CC_OP_MAX
645};
646
647static const char *cc_names[] = {
648 [CC_OP_CONST0] = "CC_OP_CONST0",
649 [CC_OP_CONST1] = "CC_OP_CONST1",
650 [CC_OP_CONST2] = "CC_OP_CONST2",
651 [CC_OP_CONST3] = "CC_OP_CONST3",
652 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
653 [CC_OP_STATIC] = "CC_OP_STATIC",
654 [CC_OP_NZ] = "CC_OP_NZ",
655 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
656 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
657 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
658 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
659 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
660 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
661 [CC_OP_ADD_64] = "CC_OP_ADD_64",
662 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 663 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 664 [CC_OP_SUB_64] = "CC_OP_SUB_64",
665 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 666 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 667 [CC_OP_ABS_64] = "CC_OP_ABS_64",
668 [CC_OP_NABS_64] = "CC_OP_NABS_64",
669 [CC_OP_ADD_32] = "CC_OP_ADD_32",
670 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 671 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 672 [CC_OP_SUB_32] = "CC_OP_SUB_32",
673 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 674 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 675 [CC_OP_ABS_32] = "CC_OP_ABS_32",
676 [CC_OP_NABS_32] = "CC_OP_NABS_32",
677 [CC_OP_COMP_32] = "CC_OP_COMP_32",
678 [CC_OP_COMP_64] = "CC_OP_COMP_64",
679 [CC_OP_TM_32] = "CC_OP_TM_32",
680 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 681 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
682 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 683 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 684 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 685 [CC_OP_SLA_32] = "CC_OP_SLA_32",
686 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 687 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 688};
689
690static inline const char *cc_name(int cc_op)
691{
692 return cc_names[cc_op];
693}
694
bcec36ea
AG		 695typedef struct LowCore
696{
697 /* prefix area: defined by architecture */
698 uint32_t ccw1[2]; /* 0x000 */
699 uint32_t ccw2[4]; /* 0x008 */
700 uint8_t pad1[0x80-0x18]; /* 0x018 */
701 uint32_t ext_params; /* 0x080 */
702 uint16_t cpu_addr; /* 0x084 */
703 uint16_t ext_int_code; /* 0x086 */
d5a103cd 704 uint16_t svc_ilen; /* 0x088 */
bcec36ea 705 uint16_t svc_code; /* 0x08a */
d5a103cd 706 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 707 uint16_t pgm_code; /* 0x08e */
708 uint32_t data_exc_code; /* 0x090 */
709 uint16_t mon_class_num; /* 0x094 */
710 uint16_t per_perc_atmid; /* 0x096 */
711 uint64_t per_address; /* 0x098 */
712 uint8_t exc_access_id; /* 0x0a0 */
713 uint8_t per_access_id; /* 0x0a1 */
714 uint8_t op_access_id; /* 0x0a2 */
715 uint8_t ar_access_id; /* 0x0a3 */
716 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
717 uint64_t trans_exc_code; /* 0x0a8 */
718 uint64_t monitor_code; /* 0x0b0 */
719 uint16_t subchannel_id; /* 0x0b8 */
720 uint16_t subchannel_nr; /* 0x0ba */
721 uint32_t io_int_parm; /* 0x0bc */
722 uint32_t io_int_word; /* 0x0c0 */
723 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
724 uint32_t stfl_fac_list; /* 0x0c8 */
725 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
726 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
727 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
728 uint32_t external_damage_code; /* 0x0f4 */
729 uint64_t failing_storage_address; /* 0x0f8 */
730 uint8_t pad6[0x120-0x100]; /* 0x100 */
731 PSW restart_old_psw; /* 0x120 */
732 PSW external_old_psw; /* 0x130 */
733 PSW svc_old_psw; /* 0x140 */
734 PSW program_old_psw; /* 0x150 */
735 PSW mcck_old_psw; /* 0x160 */
736 PSW io_old_psw; /* 0x170 */
737 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
738 PSW restart_psw; /* 0x1a0 */
739 PSW external_new_psw; /* 0x1b0 */
740 PSW svc_new_psw; /* 0x1c0 */
741 PSW program_new_psw; /* 0x1d0 */
742 PSW mcck_new_psw; /* 0x1e0 */
743 PSW io_new_psw; /* 0x1f0 */
744 PSW return_psw; /* 0x200 */
745 uint8_t irb[64]; /* 0x210 */
746 uint64_t sync_enter_timer; /* 0x250 */
747 uint64_t async_enter_timer; /* 0x258 */
748 uint64_t exit_timer; /* 0x260 */
749 uint64_t last_update_timer; /* 0x268 */
750 uint64_t user_timer; /* 0x270 */
751 uint64_t system_timer; /* 0x278 */
752 uint64_t last_update_clock; /* 0x280 */
753 uint64_t steal_clock; /* 0x288 */
754 PSW return_mcck_psw; /* 0x290 */
755 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
756 /* System info area */
757 uint64_t save_area[16]; /* 0xc00 */
758 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
759 uint64_t kernel_stack; /* 0xd40 */
760 uint64_t thread_info; /* 0xd48 */
761 uint64_t async_stack; /* 0xd50 */
762 uint64_t kernel_asce; /* 0xd58 */
763 uint64_t user_asce; /* 0xd60 */
764 uint64_t panic_stack; /* 0xd68 */
765 uint64_t user_exec_asce; /* 0xd70 */
766 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
767
768 /* SMP info area: defined by DJB */
769 uint64_t clock_comparator; /* 0xdc0 */
770 uint64_t ext_call_fast; /* 0xdc8 */
771 uint64_t percpu_offset; /* 0xdd0 */
772 uint64_t current_task; /* 0xdd8 */
773 uint32_t softirq_pending; /* 0xde0 */
774 uint32_t pad_0x0de4; /* 0xde4 */
775 uint64_t int_clock; /* 0xde8 */
776 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
777
778 /* 0xe00 is used as indicator for dump tools */
779 /* whether the kernel died with panic() or not */
780 uint32_t panic_magic; /* 0xe00 */
781
782 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
783
784 /* 64 bit extparam used for pfault, diag 250 etc */
785 uint64_t ext_params2; /* 0x11B8 */
786
787 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
788
789 /* System info area */
790
791 uint64_t floating_pt_save_area[16]; /* 0x1200 */
792 uint64_t gpregs_save_area[16]; /* 0x1280 */
793 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
794 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
795 uint32_t prefixreg_save_area; /* 0x1318 */
796 uint32_t fpt_creg_save_area; /* 0x131c */
797 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
798 uint32_t tod_progreg_save_area; /* 0x1324 */
799 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
800 uint32_t clock_comp_save_area[2]; /* 0x1330 */
801 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
802 uint32_t access_regs_save_area[16]; /* 0x1340 */
803 uint64_t cregs_save_area[16]; /* 0x1380 */
804
805 /* align to the top of the prefix area */
806
807 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 808} QEMU_PACKED LowCore;
bcec36ea
AG		 809
810/* STSI */
811#define STSI_LEVEL_MASK 0x00000000f0000000ULL
812#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
813#define STSI_LEVEL_1 0x0000000010000000ULL
814#define STSI_LEVEL_2 0x0000000020000000ULL
815#define STSI_LEVEL_3 0x0000000030000000ULL
816#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
817#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
818#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
819#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
820
821/* Basic Machine Configuration */
822struct sysib_111 {
823 uint32_t res1[8];
824 uint8_t manuf[16];
825 uint8_t type[4];
826 uint8_t res2[12];
827 uint8_t model[16];
828 uint8_t sequence[16];
829 uint8_t plant[4];
830 uint8_t res3[156];
831};
832
833/* Basic Machine CPU */
834struct sysib_121 {
835 uint32_t res1[80];
836 uint8_t sequence[16];
837 uint8_t plant[4];
838 uint8_t res2[2];
839 uint16_t cpu_addr;
840 uint8_t res3[152];
841};
842
843/* Basic Machine CPUs */
844struct sysib_122 {
845 uint8_t res1[32];
846 uint32_t capability;
847 uint16_t total_cpus;
848 uint16_t active_cpus;
849 uint16_t standby_cpus;
850 uint16_t reserved_cpus;
851 uint16_t adjustments[2026];
852};
853
854/* LPAR CPU */
855struct sysib_221 {
856 uint32_t res1[80];
857 uint8_t sequence[16];
858 uint8_t plant[4];
859 uint16_t cpu_id;
860 uint16_t cpu_addr;
861 uint8_t res3[152];
862};
863
864/* LPAR CPUs */
865struct sysib_222 {
866 uint32_t res1[32];
867 uint16_t lpar_num;
868 uint8_t res2;
869 uint8_t lcpuc;
870 uint16_t total_cpus;
871 uint16_t conf_cpus;
872 uint16_t standby_cpus;
873 uint16_t reserved_cpus;
874 uint8_t name[8];
875 uint32_t caf;
876 uint8_t res3[16];
877 uint16_t dedicated_cpus;
878 uint16_t shared_cpus;
879 uint8_t res4[180];
880};
881
882/* VM CPUs */
883struct sysib_322 {
884 uint8_t res1[31];
885 uint8_t count;
886 struct {
887 uint8_t res2[4];
888 uint16_t total_cpus;
889 uint16_t conf_cpus;
890 uint16_t standby_cpus;
891 uint16_t reserved_cpus;
892 uint8_t name[8];
893 uint32_t caf;
894 uint8_t cpi[16];
895 uint8_t res3[24];
896 } vm[8];
897 uint8_t res4[3552];
898};
899
900/* MMU defines */
901#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
902#define _ASCE_SUBSPACE 0x200 /* subspace group control */
903#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
904#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
905#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
906#define _ASCE_REAL_SPACE 0x20 /* real space control */
907#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
908#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
909#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
910#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
911#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
912#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
913
914#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
915#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
916#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
917#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
918#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
919#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
920#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
921
922#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
923#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
924#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
925
926#define _PAGE_RO 0x200 /* HW read-only bit */
927#define _PAGE_INVALID 0x400 /* HW invalid bit */
928
b9959138
AG		 929#define SK_C (0x1 << 1)
930#define SK_R (0x1 << 2)
931#define SK_F (0x1 << 3)
932#define SK_ACC_MASK (0xf << 4)
bcec36ea 933
bcec36ea
AG		 934#define SIGP_SENSE 0x01
935#define SIGP_EXTERNAL_CALL 0x02
936#define SIGP_EMERGENCY 0x03
937#define SIGP_START 0x04
938#define SIGP_STOP 0x05
939#define SIGP_RESTART 0x06
940#define SIGP_STOP_STORE_STATUS 0x09
941#define SIGP_INITIAL_CPU_RESET 0x0b
942#define SIGP_CPU_RESET 0x0c
943#define SIGP_SET_PREFIX 0x0d
944#define SIGP_STORE_STATUS_ADDR 0x0e
945#define SIGP_SET_ARCH 0x12
946
947/* cpu status bits */
948#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
949#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
950#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
951#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
952#define SIGP_STAT_STOPPED 0x00000040UL
953#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
954#define SIGP_STAT_CHECK_STOP 0x00000010UL
955#define SIGP_STAT_INOPERATIVE 0x00000004UL
956#define SIGP_STAT_INVALID_ORDER 0x00000002UL
957#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
958
a4e3ad19
AF		 959void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
960int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
bcec36ea 961 target_ulong *raddr, int *flags);
f6c98f92 962int sclp_service_call(uint32_t sccb, uint64_t code);
a4e3ad19 963uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 964 uint64_t vr);
965
966#define TARGET_HAS_ICE 1
967
968/* The value of the TOD clock for 1.1.1970. */
969#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
970
971/* Converts ns to s390's clock format */
972static inline uint64_t time2tod(uint64_t ns) {
973 return (ns << 9) / 125;
974}
975
f9466733 976static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 977 uint64_t param64)
978{
f9466733
AF		 979 CPUS390XState *env = &cpu->env;
980
bcec36ea
AG		 981 if (env->ext_index == MAX_EXT_QUEUE - 1) {
982 /* ugh - can't queue anymore. Let's drop. */
983 return;
984 }
985
986 env->ext_index++;
987 assert(env->ext_index < MAX_EXT_QUEUE);
988
989 env->ext_queue[env->ext_index].code = code;
990 env->ext_queue[env->ext_index].param = param;
991 env->ext_queue[env->ext_index].param64 = param64;
992
993 env->pending_int |= INTERRUPT_EXT;
c3affe56 994 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 995}
10c339a0 996
f9466733 997static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 998 uint16_t subchannel_number,
999 uint32_t io_int_parm, uint32_t io_int_word)
1000{
f9466733 1001 CPUS390XState *env = &cpu->env;
91b0a8f3 1002 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 1003
1004 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1005 /* ugh - can't queue anymore. Let's drop. */
1006 return;
1007 }
1008
1009 env->io_index[isc]++;
1010 assert(env->io_index[isc] < MAX_IO_QUEUE);
1011
1012 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1013 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1014 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1015 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1016
1017 env->pending_int |= INTERRUPT_IO;
c3affe56 1018 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1019}
1020
f9466733 1021static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 1022{
f9466733
AF		 1023 CPUS390XState *env = &cpu->env;
1024
5d69c547
CH		 1025 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1026 /* ugh - can't queue anymore. Let's drop. */
1027 return;
1028 }
1029
1030 env->mchk_index++;
1031 assert(env->mchk_index < MAX_MCHK_QUEUE);
1032
1033 env->mchk_queue[env->mchk_index].type = 1;
1034
1035 env->pending_int |= INTERRUPT_MCHK;
c3affe56 1036 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1037}
1038
3993c6bd 1039static inline bool cpu_has_work(CPUState *cpu)
f081c76c 1040{
259186a7
AF		 1041 S390CPU *s390_cpu = S390_CPU(cpu);
1042 CPUS390XState *env = &s390_cpu->env;
3993c6bd 1043
259186a7 1044 return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
f081c76c
BS		 1045 (env->psw.mask & PSW_MASK_EXT);
1046}
1047
a4e3ad19 1048static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
f081c76c
BS		 1049{
1050 env->psw.addr = tb->pc;
1051}
1052
e72ca652 1053/* fpu_helper.c */
e72ca652
BS		 1054uint32_t set_cc_nz_f32(float32 v);
1055uint32_t set_cc_nz_f64(float64 v);
587626f8 1056uint32_t set_cc_nz_f128(float128 v);
e72ca652 1057
aea1e885 1058/* misc_helper.c */
d5a103cd 1059void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 1060void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1061 uintptr_t retaddr);
a78b0504 1062
df1fe5bb
CH		 1063#include <sysemu/kvm.h>
1064
09b99878
CH		 1065#ifdef CONFIG_KVM
1066void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1067 uint16_t subchannel_nr, uint32_t io_int_parm,
1068 uint32_t io_int_word);
1069void kvm_s390_crw_mchk(S390CPU *cpu);
1070void kvm_s390_enable_css_support(S390CPU *cpu);
1071#else
df1fe5bb
CH		 1072static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1073 uint16_t subchannel_id,
1074 uint16_t subchannel_nr,
1075 uint32_t io_int_parm,
1076 uint32_t io_int_word)
1077{
1078}
1079static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1080{
1081}
09b99878
CH		 1082static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1083{
1084}
1085#endif
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CH		 1086
1087static inline void s390_io_interrupt(S390CPU *cpu,
1088 uint16_t subchannel_id,
1089 uint16_t subchannel_nr,
1090 uint32_t io_int_parm,
1091 uint32_t io_int_word)
1092{
1093 if (kvm_enabled()) {
1094 kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1095 io_int_word);
1096 } else {
f9466733 1097 cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
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CH		 1098 io_int_word);
1099 }
1100}
1101
1102static inline void s390_crw_mchk(S390CPU *cpu)
1103{
1104 if (kvm_enabled()) {
1105 kvm_s390_crw_mchk(cpu);
1106 } else {
f9466733 1107 cpu_inject_crw_mchk(cpu);
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CH		 1108 }
1109}
1110
10ec5117 1111#endif
Qemu copy for testing