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linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user
[qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
31
9349b4f9 32#define CPUArchState struct CPUS390XState
10ec5117 33
022c62cb 34#include "exec/cpu-defs.h"
bcec36ea
AG		 35#define TARGET_PAGE_BITS 12
36
5b23fd03 37#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG		 38#define TARGET_VIRT_ADDR_SPACE_BITS 64
39
022c62cb 40#include "exec/cpu-all.h"
10ec5117 41
6b4c305c 42#include "fpu/softfloat.h"
10ec5117 43
bcec36ea 44#define NB_MMU_MODES 3
10ec5117 45
bcec36ea
AG		 46#define MMU_MODE0_SUFFIX _primary
47#define MMU_MODE1_SUFFIX _secondary
48#define MMU_MODE2_SUFFIX _home
49
50#define MMU_USER_IDX 1
51
52#define MAX_EXT_QUEUE 16
5d69c547
CH		 53#define MAX_IO_QUEUE 16
54#define MAX_MCHK_QUEUE 16
55
56#define PSW_MCHK_MASK 0x0004000000000000
57#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 58
59typedef struct PSW {
60 uint64_t mask;
61 uint64_t addr;
62} PSW;
63
64typedef struct ExtQueue {
65 uint32_t code;
66 uint32_t param;
67 uint32_t param64;
68} ExtQueue;
10ec5117 69
5d69c547
CH		 70typedef struct IOIntQueue {
71 uint16_t id;
72 uint16_t nr;
73 uint32_t parm;
74 uint32_t word;
75} IOIntQueue;
76
77typedef struct MchkQueue {
78 uint16_t type;
79} MchkQueue;
80
420840e5
JH		 81/* Defined values for CPUS390XState.runtime_reg_dirty_mask */
82#define KVM_S390_RUNTIME_DIRTY_NONE 0
83#define KVM_S390_RUNTIME_DIRTY_PARTIAL 1
84#define KVM_S390_RUNTIME_DIRTY_FULL 2
85
10ec5117 86typedef struct CPUS390XState {
1ac5889f
RH		 87 uint64_t regs[16]; /* GP registers */
88 CPU_DoubleU fregs[16]; /* FP registers */
89 uint32_t aregs[16]; /* access registers */
10ec5117 90
1ac5889f
RH		 91 uint32_t fpc; /* floating-point control register */
92 uint32_t cc_op;
10ec5117 93
10ec5117
AG		 94 float_status fpu_status; /* passed to softfloat lib */
95
1ac5889f
RH		 96 /* The low part of a 128-bit return, or remainder of a divide. */
97 uint64_t retxl;
98
bcec36ea 99 PSW psw;
10ec5117 100
bcec36ea
AG		 101 uint64_t cc_src;
102 uint64_t cc_dst;
103 uint64_t cc_vr;
10ec5117
AG		 104
105 uint64_t __excp_addr;
bcec36ea
AG		 106 uint64_t psa;
107
108 uint32_t int_pgm_code;
d5a103cd 109 uint32_t int_pgm_ilen;
bcec36ea
AG		 110
111 uint32_t int_svc_code;
d5a103cd 112 uint32_t int_svc_ilen;
bcec36ea
AG		 113
114 uint64_t cregs[16]; /* control registers */
115
bcec36ea 116 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 117 IOIntQueue io_queue[MAX_IO_QUEUE][8];
118 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 119
5d69c547 120 int pending_int;
4e836781 121 int ext_index;
5d69c547
CH		 122 int io_index[8];
123 int mchk_index;
124
125 uint64_t ckc;
126 uint64_t cputm;
127 uint32_t todpr;
4e836781 128
420840e5
JH		 129 /* on S390 the runtime register set has two dirty states:
130 * a partial dirty state in which only the registers that
131 * are needed all the time are fetched. And a fully dirty
132 * state in which all runtime registers are fetched.
133 */
134 uint32_t runtime_reg_dirty_mask;
135
4e836781
AG		 136 CPU_COMMON
137
bcec36ea
AG		 138 /* reset does memset(0) up to here */
139
bcec36ea
AG		 140 int cpu_num;
141 uint8_t *storage_keys;
142
143 uint64_t tod_offset;
144 uint64_t tod_basetime;
145 QEMUTimer *tod_timer;
146
147 QEMUTimer *cpu_timer;
10ec5117
AG		 148} CPUS390XState;
149
564b863d
AF		 150#include "cpu-qom.h"
151
7b18aad5
CH		 152/* distinguish between 24 bit and 31 bit addressing */
153#define HIGH_ORDER_BIT 0x80000000
154
bcec36ea
AG		 155/* Interrupt Codes */
156/* Program Interrupts */
157#define PGM_OPERATION 0x0001
158#define PGM_PRIVILEGED 0x0002
159#define PGM_EXECUTE 0x0003
160#define PGM_PROTECTION 0x0004
161#define PGM_ADDRESSING 0x0005
162#define PGM_SPECIFICATION 0x0006
163#define PGM_DATA 0x0007
164#define PGM_FIXPT_OVERFLOW 0x0008
165#define PGM_FIXPT_DIVIDE 0x0009
166#define PGM_DEC_OVERFLOW 0x000a
167#define PGM_DEC_DIVIDE 0x000b
168#define PGM_HFP_EXP_OVERFLOW 0x000c
169#define PGM_HFP_EXP_UNDERFLOW 0x000d
170#define PGM_HFP_SIGNIFICANCE 0x000e
171#define PGM_HFP_DIVIDE 0x000f
172#define PGM_SEGMENT_TRANS 0x0010
173#define PGM_PAGE_TRANS 0x0011
174#define PGM_TRANS_SPEC 0x0012
175#define PGM_SPECIAL_OP 0x0013
176#define PGM_OPERAND 0x0015
177#define PGM_TRACE_TABLE 0x0016
178#define PGM_SPACE_SWITCH 0x001c
179#define PGM_HFP_SQRT 0x001d
180#define PGM_PC_TRANS_SPEC 0x001f
181#define PGM_AFX_TRANS 0x0020
182#define PGM_ASX_TRANS 0x0021
183#define PGM_LX_TRANS 0x0022
184#define PGM_EX_TRANS 0x0023
185#define PGM_PRIM_AUTH 0x0024
186#define PGM_SEC_AUTH 0x0025
187#define PGM_ALET_SPEC 0x0028
188#define PGM_ALEN_SPEC 0x0029
189#define PGM_ALE_SEQ 0x002a
190#define PGM_ASTE_VALID 0x002b
191#define PGM_ASTE_SEQ 0x002c
192#define PGM_EXT_AUTH 0x002d
193#define PGM_STACK_FULL 0x0030
194#define PGM_STACK_EMPTY 0x0031
195#define PGM_STACK_SPEC 0x0032
196#define PGM_STACK_TYPE 0x0033
197#define PGM_STACK_OP 0x0034
198#define PGM_ASCE_TYPE 0x0038
199#define PGM_REG_FIRST_TRANS 0x0039
200#define PGM_REG_SEC_TRANS 0x003a
201#define PGM_REG_THIRD_TRANS 0x003b
202#define PGM_MONITOR 0x0040
203#define PGM_PER 0x0080
204#define PGM_CRYPTO 0x0119
205
206/* External Interrupts */
207#define EXT_INTERRUPT_KEY 0x0040
208#define EXT_CLOCK_COMP 0x1004
209#define EXT_CPU_TIMER 0x1005
210#define EXT_MALFUNCTION 0x1200
211#define EXT_EMERGENCY 0x1201
212#define EXT_EXTERNAL_CALL 0x1202
213#define EXT_ETR 0x1406
214#define EXT_SERVICE 0x2401
215#define EXT_VIRTIO 0x2603
216
217/* PSW defines */
218#undef PSW_MASK_PER
219#undef PSW_MASK_DAT
220#undef PSW_MASK_IO
221#undef PSW_MASK_EXT
222#undef PSW_MASK_KEY
223#undef PSW_SHIFT_KEY
224#undef PSW_MASK_MCHECK
225#undef PSW_MASK_WAIT
226#undef PSW_MASK_PSTATE
227#undef PSW_MASK_ASC
228#undef PSW_MASK_CC
229#undef PSW_MASK_PM
230#undef PSW_MASK_64
231
232#define PSW_MASK_PER 0x4000000000000000ULL
233#define PSW_MASK_DAT 0x0400000000000000ULL
234#define PSW_MASK_IO 0x0200000000000000ULL
235#define PSW_MASK_EXT 0x0100000000000000ULL
236#define PSW_MASK_KEY 0x00F0000000000000ULL
237#define PSW_SHIFT_KEY 56
238#define PSW_MASK_MCHECK 0x0004000000000000ULL
239#define PSW_MASK_WAIT 0x0002000000000000ULL
240#define PSW_MASK_PSTATE 0x0001000000000000ULL
241#define PSW_MASK_ASC 0x0000C00000000000ULL
242#define PSW_MASK_CC 0x0000300000000000ULL
243#define PSW_MASK_PM 0x00000F0000000000ULL
244#define PSW_MASK_64 0x0000000100000000ULL
245#define PSW_MASK_32 0x0000000080000000ULL
246
247#undef PSW_ASC_PRIMARY
248#undef PSW_ASC_ACCREG
249#undef PSW_ASC_SECONDARY
250#undef PSW_ASC_HOME
251
252#define PSW_ASC_PRIMARY 0x0000000000000000ULL
253#define PSW_ASC_ACCREG 0x0000400000000000ULL
254#define PSW_ASC_SECONDARY 0x0000800000000000ULL
255#define PSW_ASC_HOME 0x0000C00000000000ULL
256
257/* tb flags */
258
259#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
260#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
261#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
262#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
263#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
264#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
265#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
266#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
267#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
268#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
269#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
270#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
271#define FLAG_MASK_32 0x00001000
272
a4e3ad19 273static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 274{
bcec36ea
AG		 275 if (env->psw.mask & PSW_MASK_PSTATE) {
276 return 1;
277 }
278
10c339a0
AG		 279 return 0;
280}
281
a4e3ad19 282static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 283 target_ulong *cs_base, int *flags)
284{
285 *pc = env->psw.addr;
286 *cs_base = 0;
287 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
288 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
289}
290
d5a103cd
RH		 291/* While the PoO talks about ILC (a number between 1-3) what is actually
292 stored in LowCore is shifted left one bit (an even between 2-6). As
293 this is the actual length of the insn and therefore more useful, that
294 is what we want to pass around and manipulate. To make sure that we
295 have applied this distinction universally, rename the "ILC" to "ILEN". */
296static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 297{
298 switch (opc >> 6) {
299 case 0:
d5a103cd 300 return 2;
bcec36ea
AG		 301 case 1:
302 case 2:
d5a103cd
RH		 303 return 4;
304 default:
305 return 6;
bcec36ea 306 }
bcec36ea
AG		 307}
308
d5a103cd
RH		 309#ifndef CONFIG_USER_ONLY
310/* In several cases of runtime exceptions, we havn't recorded the true
311 instruction length. Use these codes when raising exceptions in order
312 to re-compute the length by examining the insn in memory. */
313#define ILEN_LATER 0x20
314#define ILEN_LATER_INC 0x21
315#endif
bcec36ea 316
564b863d 317S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 318void s390x_translate_init(void);
10ec5117 319int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 320
321/* you can call this signal handler from your SIGBUS and SIGSEGV
322 signal handlers to inform the virtual CPU of exceptions. non zero
323 is returned if the signal was handled by the virtual CPU. */
324int cpu_s390x_signal_handler(int host_signum, void *pinfo,
325 void *puc);
326int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
97b348e7 327 int mmu_idx);
10ec5117
AG		 328#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
329
db1c8f53 330#include "ioinst.h"
52705890 331
10c339a0 332#ifndef CONFIG_USER_ONLY
38322ed6
CH		 333void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
334 int is_write);
335void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
336 int is_write);
7b18aad5
CH		 337static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
338{
339 hwaddr addr = 0;
340 uint8_t reg;
341
342 reg = ipb >> 28;
343 if (reg > 0) {
344 addr = env->regs[reg];
345 }
346 addr += (ipb >> 16) & 0xfff;
347
348 return addr;
349}
350
8f22e0df
AF		 351void s390x_tod_timer(void *opaque);
352void s390x_cpu_timer(void *opaque);
353
28e942f8 354int s390_virtio_hypercall(CPUS390XState *env);
bcec36ea 355
1f206266 356#ifdef CONFIG_KVM
1bc22652
AF		 357void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
358void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
359void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
bcec36ea 360 uint64_t parm64, int vm);
1f206266 361#else
1bc22652 362static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
1f206266
AG		 363{
364}
365
1bc22652 366static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
1f206266
AG		 367 uint64_t token)
368{
369}
370
1bc22652 371static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
1f206266
AG		 372 uint32_t parm, uint64_t parm64,
373 int vm)
374{
375}
376#endif
45fa769b 377S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
49e15878
AF		 378void s390_add_running_cpu(S390CPU *cpu);
379unsigned s390_del_running_cpu(S390CPU *cpu);
bcec36ea 380
000a1a38
CB		 381/* service interrupts are floating therefore we must not pass an cpustate */
382void s390_sclp_extint(uint32_t parm);
383
d1ff903c 384/* from s390-virtio-bus */
a8170e5e 385extern const hwaddr virtio_size;
d1ff903c 386
ef81522b 387#else
49e15878 388static inline void s390_add_running_cpu(S390CPU *cpu)
ef81522b
AG		 389{
390}
391
49e15878 392static inline unsigned s390_del_running_cpu(S390CPU *cpu)
ef81522b
AG		 393{
394 return 0;
395}
10c339a0 396#endif
bcec36ea
AG		 397void cpu_lock(void);
398void cpu_unlock(void);
10c339a0 399
7b18aad5
CH		 400typedef struct SubchDev SubchDev;
401
df1fe5bb
CH		 402#ifndef CONFIG_USER_ONLY
403SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
404 uint16_t schid);
405bool css_subch_visible(SubchDev *sch);
406void css_conditional_io_interrupt(SubchDev *sch);
407int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 408bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
df1fe5bb
CH		 409int css_do_msch(SubchDev *sch, SCHIB *schib);
410int css_do_xsch(SubchDev *sch);
411int css_do_csch(SubchDev *sch);
412int css_do_hsch(SubchDev *sch);
413int css_do_ssch(SubchDev *sch, ORB *orb);
414int css_do_tsch(SubchDev *sch, IRB *irb);
415int css_do_stcrw(CRW *crw);
50c8d9bf 416int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 417int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
418 int rfmt, void *buf);
419void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
420int css_enable_mcsse(void);
421int css_enable_mss(void);
422int css_do_rsch(SubchDev *sch);
423int css_do_rchp(uint8_t cssid, uint8_t chpid);
424bool css_present(uint8_t cssid);
425#else
7b18aad5
CH		 426static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
427 uint16_t schid)
428{
429 return NULL;
430}
431static inline bool css_subch_visible(SubchDev *sch)
432{
433 return false;
434}
435static inline void css_conditional_io_interrupt(SubchDev *sch)
436{
437}
438static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
439{
440 return -ENODEV;
441}
442static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
443{
444 return true;
445}
446static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
447{
448 return -ENODEV;
449}
450static inline int css_do_xsch(SubchDev *sch)
451{
452 return -ENODEV;
453}
454static inline int css_do_csch(SubchDev *sch)
455{
456 return -ENODEV;
457}
458static inline int css_do_hsch(SubchDev *sch)
459{
460 return -ENODEV;
461}
462static inline int css_do_ssch(SubchDev *sch, ORB *orb)
463{
464 return -ENODEV;
465}
466static inline int css_do_tsch(SubchDev *sch, IRB *irb)
467{
468 return -ENODEV;
469}
470static inline int css_do_stcrw(CRW *crw)
471{
472 return 1;
473}
50c8d9bf 474static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
7b18aad5
CH		 475{
476 return 0;
477}
478static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
479 int rfmt, uint8_t l_chpid, void *buf)
480{
481 return 0;
482}
483static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
484{
485}
486static inline int css_enable_mss(void)
487{
488 return -EINVAL;
489}
490static inline int css_enable_mcsse(void)
491{
492 return -EINVAL;
493}
494static inline int css_do_rsch(SubchDev *sch)
495{
496 return -ENODEV;
497}
498static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
499{
500 return -ENODEV;
501}
502static inline bool css_present(uint8_t cssid)
503{
504 return false;
505}
df1fe5bb 506#endif
7b18aad5 507
564b863d 508#define cpu_init(model) (&cpu_s390x_init(model)->env)
10ec5117
AG		 509#define cpu_exec cpu_s390x_exec
510#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 511#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 512
904e5fd5
VM		 513void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
514#define cpu_list s390_cpu_list
515
022c62cb 516#include "exec/exec-all.h"
bcec36ea 517
bcec36ea
AG		 518#define EXCP_EXT 1 /* external interrupt */
519#define EXCP_SVC 2 /* supervisor call (syscall) */
520#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 521#define EXCP_IO 7 /* I/O interrupt */
522#define EXCP_MCHK 8 /* machine check */
bcec36ea 523
bcec36ea
AG		 524#define INTERRUPT_EXT (1 << 0)
525#define INTERRUPT_TOD (1 << 1)
526#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 527#define INTERRUPT_IO (1 << 3)
528#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 529
530/* Program Status Word. */
531#define S390_PSWM_REGNUM 0
532#define S390_PSWA_REGNUM 1
533/* General Purpose Registers. */
534#define S390_R0_REGNUM 2
535#define S390_R1_REGNUM 3
536#define S390_R2_REGNUM 4
537#define S390_R3_REGNUM 5
538#define S390_R4_REGNUM 6
539#define S390_R5_REGNUM 7
540#define S390_R6_REGNUM 8
541#define S390_R7_REGNUM 9
542#define S390_R8_REGNUM 10
543#define S390_R9_REGNUM 11
544#define S390_R10_REGNUM 12
545#define S390_R11_REGNUM 13
546#define S390_R12_REGNUM 14
547#define S390_R13_REGNUM 15
548#define S390_R14_REGNUM 16
549#define S390_R15_REGNUM 17
550/* Access Registers. */
551#define S390_A0_REGNUM 18
552#define S390_A1_REGNUM 19
553#define S390_A2_REGNUM 20
554#define S390_A3_REGNUM 21
555#define S390_A4_REGNUM 22
556#define S390_A5_REGNUM 23
557#define S390_A6_REGNUM 24
558#define S390_A7_REGNUM 25
559#define S390_A8_REGNUM 26
560#define S390_A9_REGNUM 27
561#define S390_A10_REGNUM 28
562#define S390_A11_REGNUM 29
563#define S390_A12_REGNUM 30
564#define S390_A13_REGNUM 31
565#define S390_A14_REGNUM 32
566#define S390_A15_REGNUM 33
567/* Floating Point Control Word. */
568#define S390_FPC_REGNUM 34
569/* Floating Point Registers. */
570#define S390_F0_REGNUM 35
571#define S390_F1_REGNUM 36
572#define S390_F2_REGNUM 37
573#define S390_F3_REGNUM 38
574#define S390_F4_REGNUM 39
575#define S390_F5_REGNUM 40
576#define S390_F6_REGNUM 41
577#define S390_F7_REGNUM 42
578#define S390_F8_REGNUM 43
579#define S390_F9_REGNUM 44
580#define S390_F10_REGNUM 45
581#define S390_F11_REGNUM 46
582#define S390_F12_REGNUM 47
583#define S390_F13_REGNUM 48
584#define S390_F14_REGNUM 49
585#define S390_F15_REGNUM 50
586/* Total. */
587#define S390_NUM_REGS 51
588
bcec36ea
AG		 589/* CC optimization */
590
591enum cc_op {
592 CC_OP_CONST0 = 0, /* CC is 0 */
593 CC_OP_CONST1, /* CC is 1 */
594 CC_OP_CONST2, /* CC is 2 */
595 CC_OP_CONST3, /* CC is 3 */
596
597 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
598 CC_OP_STATIC, /* CC value is env->cc_op */
599
600 CC_OP_NZ, /* env->cc_dst != 0 */
601 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
602 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
603 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
604 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
605 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
606 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
607
608 CC_OP_ADD_64, /* overflow on add (64bit) */
609 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 610 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 611 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
612 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 613 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 614 CC_OP_ABS_64, /* sign eval on abs (64bit) */
615 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
616
617 CC_OP_ADD_32, /* overflow on add (32bit) */
618 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 619 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 620 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
621 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 622 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 623 CC_OP_ABS_32, /* sign eval on abs (64bit) */
624 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
625
626 CC_OP_COMP_32, /* complement */
627 CC_OP_COMP_64, /* complement */
628
629 CC_OP_TM_32, /* test under mask (32bit) */
630 CC_OP_TM_64, /* test under mask (64bit) */
631
bcec36ea
AG		 632 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
633 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 634 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 635
636 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 637 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
638 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 639 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 640 CC_OP_MAX
641};
642
643static const char *cc_names[] = {
644 [CC_OP_CONST0] = "CC_OP_CONST0",
645 [CC_OP_CONST1] = "CC_OP_CONST1",
646 [CC_OP_CONST2] = "CC_OP_CONST2",
647 [CC_OP_CONST3] = "CC_OP_CONST3",
648 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
649 [CC_OP_STATIC] = "CC_OP_STATIC",
650 [CC_OP_NZ] = "CC_OP_NZ",
651 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
652 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
653 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
654 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
655 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
656 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
657 [CC_OP_ADD_64] = "CC_OP_ADD_64",
658 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 659 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 660 [CC_OP_SUB_64] = "CC_OP_SUB_64",
661 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 662 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 663 [CC_OP_ABS_64] = "CC_OP_ABS_64",
664 [CC_OP_NABS_64] = "CC_OP_NABS_64",
665 [CC_OP_ADD_32] = "CC_OP_ADD_32",
666 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 667 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 668 [CC_OP_SUB_32] = "CC_OP_SUB_32",
669 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 670 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 671 [CC_OP_ABS_32] = "CC_OP_ABS_32",
672 [CC_OP_NABS_32] = "CC_OP_NABS_32",
673 [CC_OP_COMP_32] = "CC_OP_COMP_32",
674 [CC_OP_COMP_64] = "CC_OP_COMP_64",
675 [CC_OP_TM_32] = "CC_OP_TM_32",
676 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 677 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
678 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 679 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 680 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 681 [CC_OP_SLA_32] = "CC_OP_SLA_32",
682 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 683 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 684};
685
686static inline const char *cc_name(int cc_op)
687{
688 return cc_names[cc_op];
689}
690
bcec36ea
AG		 691typedef struct LowCore
692{
693 /* prefix area: defined by architecture */
694 uint32_t ccw1[2]; /* 0x000 */
695 uint32_t ccw2[4]; /* 0x008 */
696 uint8_t pad1[0x80-0x18]; /* 0x018 */
697 uint32_t ext_params; /* 0x080 */
698 uint16_t cpu_addr; /* 0x084 */
699 uint16_t ext_int_code; /* 0x086 */
d5a103cd 700 uint16_t svc_ilen; /* 0x088 */
bcec36ea 701 uint16_t svc_code; /* 0x08a */
d5a103cd 702 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 703 uint16_t pgm_code; /* 0x08e */
704 uint32_t data_exc_code; /* 0x090 */
705 uint16_t mon_class_num; /* 0x094 */
706 uint16_t per_perc_atmid; /* 0x096 */
707 uint64_t per_address; /* 0x098 */
708 uint8_t exc_access_id; /* 0x0a0 */
709 uint8_t per_access_id; /* 0x0a1 */
710 uint8_t op_access_id; /* 0x0a2 */
711 uint8_t ar_access_id; /* 0x0a3 */
712 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
713 uint64_t trans_exc_code; /* 0x0a8 */
714 uint64_t monitor_code; /* 0x0b0 */
715 uint16_t subchannel_id; /* 0x0b8 */
716 uint16_t subchannel_nr; /* 0x0ba */
717 uint32_t io_int_parm; /* 0x0bc */
718 uint32_t io_int_word; /* 0x0c0 */
719 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
720 uint32_t stfl_fac_list; /* 0x0c8 */
721 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
722 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
723 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
724 uint32_t external_damage_code; /* 0x0f4 */
725 uint64_t failing_storage_address; /* 0x0f8 */
726 uint8_t pad6[0x120-0x100]; /* 0x100 */
727 PSW restart_old_psw; /* 0x120 */
728 PSW external_old_psw; /* 0x130 */
729 PSW svc_old_psw; /* 0x140 */
730 PSW program_old_psw; /* 0x150 */
731 PSW mcck_old_psw; /* 0x160 */
732 PSW io_old_psw; /* 0x170 */
733 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
734 PSW restart_psw; /* 0x1a0 */
735 PSW external_new_psw; /* 0x1b0 */
736 PSW svc_new_psw; /* 0x1c0 */
737 PSW program_new_psw; /* 0x1d0 */
738 PSW mcck_new_psw; /* 0x1e0 */
739 PSW io_new_psw; /* 0x1f0 */
740 PSW return_psw; /* 0x200 */
741 uint8_t irb[64]; /* 0x210 */
742 uint64_t sync_enter_timer; /* 0x250 */
743 uint64_t async_enter_timer; /* 0x258 */
744 uint64_t exit_timer; /* 0x260 */
745 uint64_t last_update_timer; /* 0x268 */
746 uint64_t user_timer; /* 0x270 */
747 uint64_t system_timer; /* 0x278 */
748 uint64_t last_update_clock; /* 0x280 */
749 uint64_t steal_clock; /* 0x288 */
750 PSW return_mcck_psw; /* 0x290 */
751 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
752 /* System info area */
753 uint64_t save_area[16]; /* 0xc00 */
754 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
755 uint64_t kernel_stack; /* 0xd40 */
756 uint64_t thread_info; /* 0xd48 */
757 uint64_t async_stack; /* 0xd50 */
758 uint64_t kernel_asce; /* 0xd58 */
759 uint64_t user_asce; /* 0xd60 */
760 uint64_t panic_stack; /* 0xd68 */
761 uint64_t user_exec_asce; /* 0xd70 */
762 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
763
764 /* SMP info area: defined by DJB */
765 uint64_t clock_comparator; /* 0xdc0 */
766 uint64_t ext_call_fast; /* 0xdc8 */
767 uint64_t percpu_offset; /* 0xdd0 */
768 uint64_t current_task; /* 0xdd8 */
769 uint32_t softirq_pending; /* 0xde0 */
770 uint32_t pad_0x0de4; /* 0xde4 */
771 uint64_t int_clock; /* 0xde8 */
772 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
773
774 /* 0xe00 is used as indicator for dump tools */
775 /* whether the kernel died with panic() or not */
776 uint32_t panic_magic; /* 0xe00 */
777
778 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
779
780 /* 64 bit extparam used for pfault, diag 250 etc */
781 uint64_t ext_params2; /* 0x11B8 */
782
783 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
784
785 /* System info area */
786
787 uint64_t floating_pt_save_area[16]; /* 0x1200 */
788 uint64_t gpregs_save_area[16]; /* 0x1280 */
789 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
790 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
791 uint32_t prefixreg_save_area; /* 0x1318 */
792 uint32_t fpt_creg_save_area; /* 0x131c */
793 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
794 uint32_t tod_progreg_save_area; /* 0x1324 */
795 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
796 uint32_t clock_comp_save_area[2]; /* 0x1330 */
797 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
798 uint32_t access_regs_save_area[16]; /* 0x1340 */
799 uint64_t cregs_save_area[16]; /* 0x1380 */
800
801 /* align to the top of the prefix area */
802
803 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 804} QEMU_PACKED LowCore;
bcec36ea
AG		 805
806/* STSI */
807#define STSI_LEVEL_MASK 0x00000000f0000000ULL
808#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
809#define STSI_LEVEL_1 0x0000000010000000ULL
810#define STSI_LEVEL_2 0x0000000020000000ULL
811#define STSI_LEVEL_3 0x0000000030000000ULL
812#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
813#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
814#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
815#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
816
817/* Basic Machine Configuration */
818struct sysib_111 {
819 uint32_t res1[8];
820 uint8_t manuf[16];
821 uint8_t type[4];
822 uint8_t res2[12];
823 uint8_t model[16];
824 uint8_t sequence[16];
825 uint8_t plant[4];
826 uint8_t res3[156];
827};
828
829/* Basic Machine CPU */
830struct sysib_121 {
831 uint32_t res1[80];
832 uint8_t sequence[16];
833 uint8_t plant[4];
834 uint8_t res2[2];
835 uint16_t cpu_addr;
836 uint8_t res3[152];
837};
838
839/* Basic Machine CPUs */
840struct sysib_122 {
841 uint8_t res1[32];
842 uint32_t capability;
843 uint16_t total_cpus;
844 uint16_t active_cpus;
845 uint16_t standby_cpus;
846 uint16_t reserved_cpus;
847 uint16_t adjustments[2026];
848};
849
850/* LPAR CPU */
851struct sysib_221 {
852 uint32_t res1[80];
853 uint8_t sequence[16];
854 uint8_t plant[4];
855 uint16_t cpu_id;
856 uint16_t cpu_addr;
857 uint8_t res3[152];
858};
859
860/* LPAR CPUs */
861struct sysib_222 {
862 uint32_t res1[32];
863 uint16_t lpar_num;
864 uint8_t res2;
865 uint8_t lcpuc;
866 uint16_t total_cpus;
867 uint16_t conf_cpus;
868 uint16_t standby_cpus;
869 uint16_t reserved_cpus;
870 uint8_t name[8];
871 uint32_t caf;
872 uint8_t res3[16];
873 uint16_t dedicated_cpus;
874 uint16_t shared_cpus;
875 uint8_t res4[180];
876};
877
878/* VM CPUs */
879struct sysib_322 {
880 uint8_t res1[31];
881 uint8_t count;
882 struct {
883 uint8_t res2[4];
884 uint16_t total_cpus;
885 uint16_t conf_cpus;
886 uint16_t standby_cpus;
887 uint16_t reserved_cpus;
888 uint8_t name[8];
889 uint32_t caf;
890 uint8_t cpi[16];
891 uint8_t res3[24];
892 } vm[8];
893 uint8_t res4[3552];
894};
895
896/* MMU defines */
897#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
898#define _ASCE_SUBSPACE 0x200 /* subspace group control */
899#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
900#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
901#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
902#define _ASCE_REAL_SPACE 0x20 /* real space control */
903#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
904#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
905#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
906#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
907#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
908#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
909
910#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
911#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
912#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
913#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
914#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
915#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
916#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
917
918#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
919#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
920#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
921
922#define _PAGE_RO 0x200 /* HW read-only bit */
923#define _PAGE_INVALID 0x400 /* HW invalid bit */
924
b9959138
AG		 925#define SK_C (0x1 << 1)
926#define SK_R (0x1 << 2)
927#define SK_F (0x1 << 3)
928#define SK_ACC_MASK (0xf << 4)
bcec36ea 929
bcec36ea
AG		 930#define SIGP_SENSE 0x01
931#define SIGP_EXTERNAL_CALL 0x02
932#define SIGP_EMERGENCY 0x03
933#define SIGP_START 0x04
934#define SIGP_STOP 0x05
935#define SIGP_RESTART 0x06
936#define SIGP_STOP_STORE_STATUS 0x09
937#define SIGP_INITIAL_CPU_RESET 0x0b
938#define SIGP_CPU_RESET 0x0c
939#define SIGP_SET_PREFIX 0x0d
940#define SIGP_STORE_STATUS_ADDR 0x0e
941#define SIGP_SET_ARCH 0x12
942
943/* cpu status bits */
944#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
945#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
946#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
947#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
948#define SIGP_STAT_STOPPED 0x00000040UL
949#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
950#define SIGP_STAT_CHECK_STOP 0x00000010UL
951#define SIGP_STAT_INOPERATIVE 0x00000004UL
952#define SIGP_STAT_INVALID_ORDER 0x00000002UL
953#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
954
a4e3ad19
AF		 955void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
956int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
bcec36ea 957 target_ulong *raddr, int *flags);
f6c98f92 958int sclp_service_call(uint32_t sccb, uint64_t code);
a4e3ad19 959uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 960 uint64_t vr);
961
962#define TARGET_HAS_ICE 1
963
964/* The value of the TOD clock for 1.1.1970. */
965#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
966
967/* Converts ns to s390's clock format */
968static inline uint64_t time2tod(uint64_t ns) {
969 return (ns << 9) / 125;
970}
971
f9466733 972static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 973 uint64_t param64)
974{
f9466733
AF		 975 CPUS390XState *env = &cpu->env;
976
bcec36ea
AG		 977 if (env->ext_index == MAX_EXT_QUEUE - 1) {
978 /* ugh - can't queue anymore. Let's drop. */
979 return;
980 }
981
982 env->ext_index++;
983 assert(env->ext_index < MAX_EXT_QUEUE);
984
985 env->ext_queue[env->ext_index].code = code;
986 env->ext_queue[env->ext_index].param = param;
987 env->ext_queue[env->ext_index].param64 = param64;
988
989 env->pending_int |= INTERRUPT_EXT;
c3affe56 990 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 991}
10c339a0 992
f9466733 993static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 994 uint16_t subchannel_number,
995 uint32_t io_int_parm, uint32_t io_int_word)
996{
f9466733 997 CPUS390XState *env = &cpu->env;
91b0a8f3 998 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 999
1000 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1001 /* ugh - can't queue anymore. Let's drop. */
1002 return;
1003 }
1004
1005 env->io_index[isc]++;
1006 assert(env->io_index[isc] < MAX_IO_QUEUE);
1007
1008 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1009 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1010 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1011 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1012
1013 env->pending_int |= INTERRUPT_IO;
c3affe56 1014 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1015}
1016
f9466733 1017static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 1018{
f9466733
AF		 1019 CPUS390XState *env = &cpu->env;
1020
5d69c547
CH		 1021 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1022 /* ugh - can't queue anymore. Let's drop. */
1023 return;
1024 }
1025
1026 env->mchk_index++;
1027 assert(env->mchk_index < MAX_MCHK_QUEUE);
1028
1029 env->mchk_queue[env->mchk_index].type = 1;
1030
1031 env->pending_int |= INTERRUPT_MCHK;
c3affe56 1032 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1033}
1034
3993c6bd 1035static inline bool cpu_has_work(CPUState *cpu)
f081c76c 1036{
259186a7
AF		 1037 S390CPU *s390_cpu = S390_CPU(cpu);
1038 CPUS390XState *env = &s390_cpu->env;
3993c6bd 1039
259186a7 1040 return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
f081c76c
BS		 1041 (env->psw.mask & PSW_MASK_EXT);
1042}
1043
a4e3ad19 1044static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
f081c76c
BS		 1045{
1046 env->psw.addr = tb->pc;
1047}
1048
e72ca652 1049/* fpu_helper.c */
e72ca652
BS		 1050uint32_t set_cc_nz_f32(float32 v);
1051uint32_t set_cc_nz_f64(float64 v);
587626f8 1052uint32_t set_cc_nz_f128(float128 v);
e72ca652 1053
aea1e885 1054/* misc_helper.c */
d5a103cd 1055void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 1056void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1057 uintptr_t retaddr);
a78b0504 1058
df1fe5bb
CH		 1059#include <sysemu/kvm.h>
1060
09b99878
CH		 1061#ifdef CONFIG_KVM
1062void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1063 uint16_t subchannel_nr, uint32_t io_int_parm,
1064 uint32_t io_int_word);
1065void kvm_s390_crw_mchk(S390CPU *cpu);
1066void kvm_s390_enable_css_support(S390CPU *cpu);
420840e5 1067int kvm_s390_get_registers_partial(CPUState *cpu);
cc3ac9c4
CH		 1068int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1069 int vq, bool assign);
09b99878 1070#else
df1fe5bb
CH		 1071static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1072 uint16_t subchannel_id,
1073 uint16_t subchannel_nr,
1074 uint32_t io_int_parm,
1075 uint32_t io_int_word)
1076{
1077}
1078static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1079{
1080}
09b99878
CH		 1081static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1082{
1083}
420840e5
JH		 1084static inline int kvm_s390_get_registers_partial(CPUState *cpu)
1085{
1086 return -ENOSYS;
1087}
cc3ac9c4
CH		 1088static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1089 uint32_t sch, int vq,
b4436a0b
CH		 1090 bool assign)
1091{
1092 return -ENOSYS;
1093}
09b99878 1094#endif
df1fe5bb
CH		 1095
1096static inline void s390_io_interrupt(S390CPU *cpu,
1097 uint16_t subchannel_id,
1098 uint16_t subchannel_nr,
1099 uint32_t io_int_parm,
1100 uint32_t io_int_word)
1101{
1102 if (kvm_enabled()) {
1103 kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1104 io_int_word);
1105 } else {
f9466733 1106 cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
df1fe5bb
CH		 1107 io_int_word);
1108 }
1109}
1110
1111static inline void s390_crw_mchk(S390CPU *cpu)
1112{
1113 if (kvm_enabled()) {
1114 kvm_s390_crw_mchk(cpu);
1115 } else {
f9466733 1116 cpu_inject_crw_mchk(cpu);
df1fe5bb
CH		 1117 }
1118}
1119
cc3ac9c4
CH		 1120static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1121 uint32_t sch_id, int vq,
b4436a0b
CH		 1122 bool assign)
1123{
1124 if (kvm_enabled()) {
cc3ac9c4 1125 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH		 1126 } else {
1127 return -ENOSYS;
1128 }
1129}
1130
10ec5117 1131#endif
Qemu copy for testing