projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 10ec5117 AG |
1 | /* |
| 2 | * S/390 virtual CPU header | |
| 3 | * | |
| 4 | * Copyright (c) 2009 Ulrich Hecht | |
| 5 | * | |
| 6 | * This library is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU Lesser General Public | |
| 8 | * License as published by the Free Software Foundation; either | |
| 9 | * version 2 of the License, or (at your option) any later version. | |
| 10 | * | |
| 11 | * This library is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | * Lesser General Public License for more details. | |
| 15 | * | |
| ccb084d3 CB |
16 | * Contributions after 2012-10-29 are licensed under the terms of the |
| 17 | * GNU GPL, version 2 or (at your option) any later version. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU (Lesser) General Public | |
| 70539e18 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 10ec5117 AG |
21 | */ |
| 22 | #ifndef CPU_S390X_H | |
| 23 | #define CPU_S390X_H | |
| 45133b74 SW |
24 | |
| 25 | #include "config.h" | |
| 26 | #include "qemu-common.h" | |
| 10ec5117 AG |
27 | |
| 28 | #define TARGET_LONG_BITS 64 | |
| 29 | ||
| 30 | #define ELF_MACHINE EM_S390 | |
| 31 | ||
| 9349b4f9 | 32 | #define CPUArchState struct CPUS390XState |
| 10ec5117 | 33 | |
| 022c62cb | 34 | #include "exec/cpu-defs.h" |
| bcec36ea AG |
35 | #define TARGET_PAGE_BITS 12 |
| 36 | ||
| 37 | #define TARGET_PHYS_ADDR_SPACE_BITS 64 | |
| 38 | #define TARGET_VIRT_ADDR_SPACE_BITS 64 | |
| 39 | ||
| 022c62cb | 40 | #include "exec/cpu-all.h" |
| 10ec5117 | 41 | |
| 6b4c305c | 42 | #include "fpu/softfloat.h" |
| 10ec5117 | 43 | |
| bcec36ea | 44 | #define NB_MMU_MODES 3 |
| 10ec5117 | 45 | |
| bcec36ea AG |
46 | #define MMU_MODE0_SUFFIX _primary |
| 47 | #define MMU_MODE1_SUFFIX _secondary | |
| 48 | #define MMU_MODE2_SUFFIX _home | |
| 49 | ||
| 50 | #define MMU_USER_IDX 1 | |
| 51 | ||
| 52 | #define MAX_EXT_QUEUE 16 | |
| 53 | ||
| 54 | typedef struct PSW { | |
| 55 | uint64_t mask; | |
| 56 | uint64_t addr; | |
| 57 | } PSW; | |
| 58 | ||
| 59 | typedef struct ExtQueue { | |
| 60 | uint32_t code; | |
| 61 | uint32_t param; | |
| 62 | uint32_t param64; | |
| 63 | } ExtQueue; | |
| 10ec5117 AG |
64 | |
| 65 | typedef struct CPUS390XState { | |
| 1ac5889f RH |
66 | uint64_t regs[16]; /* GP registers */ |
| 67 | CPU_DoubleU fregs[16]; /* FP registers */ | |
| 68 | uint32_t aregs[16]; /* access registers */ | |
| 10ec5117 | 69 | |
| 1ac5889f RH |
70 | uint32_t fpc; /* floating-point control register */ |
| 71 | uint32_t cc_op; | |
| 10ec5117 | 72 | |
| 10ec5117 AG |
73 | float_status fpu_status; /* passed to softfloat lib */ |
| 74 | ||
| 1ac5889f RH |
75 | /* The low part of a 128-bit return, or remainder of a divide. */ |
| 76 | uint64_t retxl; | |
| 77 | ||
| bcec36ea | 78 | PSW psw; |
| 10ec5117 | 79 | |
| bcec36ea AG |
80 | uint64_t cc_src; |
| 81 | uint64_t cc_dst; | |
| 82 | uint64_t cc_vr; | |
| 10ec5117 AG |
83 | |
| 84 | uint64_t __excp_addr; | |
| bcec36ea AG |
85 | uint64_t psa; |
| 86 | ||
| 87 | uint32_t int_pgm_code; | |
| d5a103cd | 88 | uint32_t int_pgm_ilen; |
| bcec36ea AG |
89 | |
| 90 | uint32_t int_svc_code; | |
| d5a103cd | 91 | uint32_t int_svc_ilen; |
| bcec36ea AG |
92 | |
| 93 | uint64_t cregs[16]; /* control registers */ | |
| 94 | ||
| bcec36ea | 95 | ExtQueue ext_queue[MAX_EXT_QUEUE]; |
| 1ac5889f | 96 | int pending_int; |
| bcec36ea | 97 | |
| 4e836781 AG |
98 | int ext_index; |
| 99 | ||
| 100 | CPU_COMMON | |
| 101 | ||
| bcec36ea AG |
102 | /* reset does memset(0) up to here */ |
| 103 | ||
| bcec36ea AG |
104 | int cpu_num; |
| 105 | uint8_t *storage_keys; | |
| 106 | ||
| 107 | uint64_t tod_offset; | |
| 108 | uint64_t tod_basetime; | |
| 109 | QEMUTimer *tod_timer; | |
| 110 | ||
| 111 | QEMUTimer *cpu_timer; | |
| 10ec5117 AG |
112 | } CPUS390XState; |
| 113 | ||
| 564b863d AF |
114 | #include "cpu-qom.h" |
| 115 | ||
| 10ec5117 | 116 | #if defined(CONFIG_USER_ONLY) |
| a4e3ad19 | 117 | static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp) |
| 10ec5117 | 118 | { |
| bcec36ea | 119 | if (newsp) { |
| 10ec5117 | 120 | env->regs[15] = newsp; |
| bcec36ea | 121 | } |
| 90b4f8ad | 122 | env->regs[2] = 0; |
| 10ec5117 AG |
123 | } |
| 124 | #endif | |
| 125 | ||
| bcec36ea AG |
126 | /* Interrupt Codes */ |
| 127 | /* Program Interrupts */ | |
| 128 | #define PGM_OPERATION 0x0001 | |
| 129 | #define PGM_PRIVILEGED 0x0002 | |
| 130 | #define PGM_EXECUTE 0x0003 | |
| 131 | #define PGM_PROTECTION 0x0004 | |
| 132 | #define PGM_ADDRESSING 0x0005 | |
| 133 | #define PGM_SPECIFICATION 0x0006 | |
| 134 | #define PGM_DATA 0x0007 | |
| 135 | #define PGM_FIXPT_OVERFLOW 0x0008 | |
| 136 | #define PGM_FIXPT_DIVIDE 0x0009 | |
| 137 | #define PGM_DEC_OVERFLOW 0x000a | |
| 138 | #define PGM_DEC_DIVIDE 0x000b | |
| 139 | #define PGM_HFP_EXP_OVERFLOW 0x000c | |
| 140 | #define PGM_HFP_EXP_UNDERFLOW 0x000d | |
| 141 | #define PGM_HFP_SIGNIFICANCE 0x000e | |
| 142 | #define PGM_HFP_DIVIDE 0x000f | |
| 143 | #define PGM_SEGMENT_TRANS 0x0010 | |
| 144 | #define PGM_PAGE_TRANS 0x0011 | |
| 145 | #define PGM_TRANS_SPEC 0x0012 | |
| 146 | #define PGM_SPECIAL_OP 0x0013 | |
| 147 | #define PGM_OPERAND 0x0015 | |
| 148 | #define PGM_TRACE_TABLE 0x0016 | |
| 149 | #define PGM_SPACE_SWITCH 0x001c | |
| 150 | #define PGM_HFP_SQRT 0x001d | |
| 151 | #define PGM_PC_TRANS_SPEC 0x001f | |
| 152 | #define PGM_AFX_TRANS 0x0020 | |
| 153 | #define PGM_ASX_TRANS 0x0021 | |
| 154 | #define PGM_LX_TRANS 0x0022 | |
| 155 | #define PGM_EX_TRANS 0x0023 | |
| 156 | #define PGM_PRIM_AUTH 0x0024 | |
| 157 | #define PGM_SEC_AUTH 0x0025 | |
| 158 | #define PGM_ALET_SPEC 0x0028 | |
| 159 | #define PGM_ALEN_SPEC 0x0029 | |
| 160 | #define PGM_ALE_SEQ 0x002a | |
| 161 | #define PGM_ASTE_VALID 0x002b | |
| 162 | #define PGM_ASTE_SEQ 0x002c | |
| 163 | #define PGM_EXT_AUTH 0x002d | |
| 164 | #define PGM_STACK_FULL 0x0030 | |
| 165 | #define PGM_STACK_EMPTY 0x0031 | |
| 166 | #define PGM_STACK_SPEC 0x0032 | |
| 167 | #define PGM_STACK_TYPE 0x0033 | |
| 168 | #define PGM_STACK_OP 0x0034 | |
| 169 | #define PGM_ASCE_TYPE 0x0038 | |
| 170 | #define PGM_REG_FIRST_TRANS 0x0039 | |
| 171 | #define PGM_REG_SEC_TRANS 0x003a | |
| 172 | #define PGM_REG_THIRD_TRANS 0x003b | |
| 173 | #define PGM_MONITOR 0x0040 | |
| 174 | #define PGM_PER 0x0080 | |
| 175 | #define PGM_CRYPTO 0x0119 | |
| 176 | ||
| 177 | /* External Interrupts */ | |
| 178 | #define EXT_INTERRUPT_KEY 0x0040 | |
| 179 | #define EXT_CLOCK_COMP 0x1004 | |
| 180 | #define EXT_CPU_TIMER 0x1005 | |
| 181 | #define EXT_MALFUNCTION 0x1200 | |
| 182 | #define EXT_EMERGENCY 0x1201 | |
| 183 | #define EXT_EXTERNAL_CALL 0x1202 | |
| 184 | #define EXT_ETR 0x1406 | |
| 185 | #define EXT_SERVICE 0x2401 | |
| 186 | #define EXT_VIRTIO 0x2603 | |
| 187 | ||
| 188 | /* PSW defines */ | |
| 189 | #undef PSW_MASK_PER | |
| 190 | #undef PSW_MASK_DAT | |
| 191 | #undef PSW_MASK_IO | |
| 192 | #undef PSW_MASK_EXT | |
| 193 | #undef PSW_MASK_KEY | |
| 194 | #undef PSW_SHIFT_KEY | |
| 195 | #undef PSW_MASK_MCHECK | |
| 196 | #undef PSW_MASK_WAIT | |
| 197 | #undef PSW_MASK_PSTATE | |
| 198 | #undef PSW_MASK_ASC | |
| 199 | #undef PSW_MASK_CC | |
| 200 | #undef PSW_MASK_PM | |
| 201 | #undef PSW_MASK_64 | |
| 202 | ||
| 203 | #define PSW_MASK_PER 0x4000000000000000ULL | |
| 204 | #define PSW_MASK_DAT 0x0400000000000000ULL | |
| 205 | #define PSW_MASK_IO 0x0200000000000000ULL | |
| 206 | #define PSW_MASK_EXT 0x0100000000000000ULL | |
| 207 | #define PSW_MASK_KEY 0x00F0000000000000ULL | |
| 208 | #define PSW_SHIFT_KEY 56 | |
| 209 | #define PSW_MASK_MCHECK 0x0004000000000000ULL | |
| 210 | #define PSW_MASK_WAIT 0x0002000000000000ULL | |
| 211 | #define PSW_MASK_PSTATE 0x0001000000000000ULL | |
| 212 | #define PSW_MASK_ASC 0x0000C00000000000ULL | |
| 213 | #define PSW_MASK_CC 0x0000300000000000ULL | |
| 214 | #define PSW_MASK_PM 0x00000F0000000000ULL | |
| 215 | #define PSW_MASK_64 0x0000000100000000ULL | |
| 216 | #define PSW_MASK_32 0x0000000080000000ULL | |
| 217 | ||
| 218 | #undef PSW_ASC_PRIMARY | |
| 219 | #undef PSW_ASC_ACCREG | |
| 220 | #undef PSW_ASC_SECONDARY | |
| 221 | #undef PSW_ASC_HOME | |
| 222 | ||
| 223 | #define PSW_ASC_PRIMARY 0x0000000000000000ULL | |
| 224 | #define PSW_ASC_ACCREG 0x0000400000000000ULL | |
| 225 | #define PSW_ASC_SECONDARY 0x0000800000000000ULL | |
| 226 | #define PSW_ASC_HOME 0x0000C00000000000ULL | |
| 227 | ||
| 228 | /* tb flags */ | |
| 229 | ||
| 230 | #define FLAG_MASK_PER (PSW_MASK_PER >> 32) | |
| 231 | #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32) | |
| 232 | #define FLAG_MASK_IO (PSW_MASK_IO >> 32) | |
| 233 | #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32) | |
| 234 | #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32) | |
| 235 | #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32) | |
| 236 | #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32) | |
| 237 | #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32) | |
| 238 | #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32) | |
| 239 | #define FLAG_MASK_CC (PSW_MASK_CC >> 32) | |
| 240 | #define FLAG_MASK_PM (PSW_MASK_PM >> 32) | |
| 241 | #define FLAG_MASK_64 (PSW_MASK_64 >> 32) | |
| 242 | #define FLAG_MASK_32 0x00001000 | |
| 243 | ||
| a4e3ad19 | 244 | static inline int cpu_mmu_index (CPUS390XState *env) |
| 10c339a0 | 245 | { |
| bcec36ea AG |
246 | if (env->psw.mask & PSW_MASK_PSTATE) { |
| 247 | return 1; | |
| 248 | } | |
| 249 | ||
| 10c339a0 AG |
250 | return 0; |
| 251 | } | |
| 252 | ||
| a4e3ad19 | 253 | static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, |
| bcec36ea AG |
254 | target_ulong *cs_base, int *flags) |
| 255 | { | |
| 256 | *pc = env->psw.addr; | |
| 257 | *cs_base = 0; | |
| 258 | *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) | | |
| 259 | ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0); | |
| 260 | } | |
| 261 | ||
| d5a103cd RH |
262 | /* While the PoO talks about ILC (a number between 1-3) what is actually |
| 263 | stored in LowCore is shifted left one bit (an even between 2-6). As | |
| 264 | this is the actual length of the insn and therefore more useful, that | |
| 265 | is what we want to pass around and manipulate. To make sure that we | |
| 266 | have applied this distinction universally, rename the "ILC" to "ILEN". */ | |
| 267 | static inline int get_ilen(uint8_t opc) | |
| bcec36ea AG |
268 | { |
| 269 | switch (opc >> 6) { | |
| 270 | case 0: | |
| d5a103cd | 271 | return 2; |
| bcec36ea AG |
272 | case 1: |
| 273 | case 2: | |
| d5a103cd RH |
274 | return 4; |
| 275 | default: | |
| 276 | return 6; | |
| bcec36ea | 277 | } |
| bcec36ea AG |
278 | } |
| 279 | ||
| d5a103cd RH |
280 | #ifndef CONFIG_USER_ONLY |
| 281 | /* In several cases of runtime exceptions, we havn't recorded the true | |
| 282 | instruction length. Use these codes when raising exceptions in order | |
| 283 | to re-compute the length by examining the insn in memory. */ | |
| 284 | #define ILEN_LATER 0x20 | |
| 285 | #define ILEN_LATER_INC 0x21 | |
| 286 | #endif | |
| bcec36ea | 287 | |
| 564b863d | 288 | S390CPU *cpu_s390x_init(const char *cpu_model); |
| bcec36ea | 289 | void s390x_translate_init(void); |
| 10ec5117 AG |
290 | int cpu_s390x_exec(CPUS390XState *s); |
| 291 | void cpu_s390x_close(CPUS390XState *s); | |
| a4e3ad19 | 292 | void do_interrupt (CPUS390XState *env); |
| 10ec5117 AG |
293 | |
| 294 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
| 295 | signal handlers to inform the virtual CPU of exceptions. non zero | |
| 296 | is returned if the signal was handled by the virtual CPU. */ | |
| 297 | int cpu_s390x_signal_handler(int host_signum, void *pinfo, | |
| 298 | void *puc); | |
| 299 | int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw, | |
| 97b348e7 | 300 | int mmu_idx); |
| 10ec5117 AG |
301 | #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault |
| 302 | ||
| 52705890 | 303 | |
| 10c339a0 | 304 | #ifndef CONFIG_USER_ONLY |
| 8f22e0df AF |
305 | void s390x_tod_timer(void *opaque); |
| 306 | void s390x_cpu_timer(void *opaque); | |
| 307 | ||
| a4e3ad19 | 308 | int s390_virtio_hypercall(CPUS390XState *env, uint64_t mem, uint64_t hypercall); |
| bcec36ea | 309 | |
| 1f206266 | 310 | #ifdef CONFIG_KVM |
| 1bc22652 AF |
311 | void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code); |
| 312 | void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token); | |
| 313 | void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm, | |
| bcec36ea | 314 | uint64_t parm64, int vm); |
| 1f206266 | 315 | #else |
| 1bc22652 | 316 | static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code) |
| 1f206266 AG |
317 | { |
| 318 | } | |
| 319 | ||
| 1bc22652 | 320 | static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, |
| 1f206266 AG |
321 | uint64_t token) |
| 322 | { | |
| 323 | } | |
| 324 | ||
| 1bc22652 | 325 | static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type, |
| 1f206266 AG |
326 | uint32_t parm, uint64_t parm64, |
| 327 | int vm) | |
| 328 | { | |
| 329 | } | |
| 330 | #endif | |
| 45fa769b | 331 | S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); |
| a4e3ad19 AF |
332 | void s390_add_running_cpu(CPUS390XState *env); |
| 333 | unsigned s390_del_running_cpu(CPUS390XState *env); | |
| bcec36ea | 334 | |
| 000a1a38 CB |
335 | /* service interrupts are floating therefore we must not pass an cpustate */ |
| 336 | void s390_sclp_extint(uint32_t parm); | |
| 337 | ||
| d1ff903c | 338 | /* from s390-virtio-bus */ |
| a8170e5e | 339 | extern const hwaddr virtio_size; |
| d1ff903c | 340 | |
| ef81522b | 341 | #else |
| a4e3ad19 | 342 | static inline void s390_add_running_cpu(CPUS390XState *env) |
| ef81522b AG |
343 | { |
| 344 | } | |
| 345 | ||
| a4e3ad19 | 346 | static inline unsigned s390_del_running_cpu(CPUS390XState *env) |
| ef81522b AG |
347 | { |
| 348 | return 0; | |
| 349 | } | |
| 10c339a0 | 350 | #endif |
| bcec36ea AG |
351 | void cpu_lock(void); |
| 352 | void cpu_unlock(void); | |
| 10c339a0 | 353 | |
| bcec36ea AG |
354 | static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls) |
| 355 | { | |
| 356 | env->aregs[0] = newtls >> 32; | |
| 357 | env->aregs[1] = newtls & 0xffffffffULL; | |
| 358 | } | |
| 10c339a0 | 359 | |
| 564b863d | 360 | #define cpu_init(model) (&cpu_s390x_init(model)->env) |
| 10ec5117 AG |
361 | #define cpu_exec cpu_s390x_exec |
| 362 | #define cpu_gen_code cpu_s390x_gen_code | |
| bcec36ea | 363 | #define cpu_signal_handler cpu_s390x_signal_handler |
| 10ec5117 | 364 | |
| 022c62cb | 365 | #include "exec/exec-all.h" |
| bcec36ea | 366 | |
| bcec36ea AG |
367 | #define EXCP_EXT 1 /* external interrupt */ |
| 368 | #define EXCP_SVC 2 /* supervisor call (syscall) */ | |
| 369 | #define EXCP_PGM 3 /* program interruption */ | |
| 370 | ||
| bcec36ea AG |
371 | #define INTERRUPT_EXT (1 << 0) |
| 372 | #define INTERRUPT_TOD (1 << 1) | |
| 373 | #define INTERRUPT_CPUTIMER (1 << 2) | |
| 10c339a0 AG |
374 | |
| 375 | /* Program Status Word. */ | |
| 376 | #define S390_PSWM_REGNUM 0 | |
| 377 | #define S390_PSWA_REGNUM 1 | |
| 378 | /* General Purpose Registers. */ | |
| 379 | #define S390_R0_REGNUM 2 | |
| 380 | #define S390_R1_REGNUM 3 | |
| 381 | #define S390_R2_REGNUM 4 | |
| 382 | #define S390_R3_REGNUM 5 | |
| 383 | #define S390_R4_REGNUM 6 | |
| 384 | #define S390_R5_REGNUM 7 | |
| 385 | #define S390_R6_REGNUM 8 | |
| 386 | #define S390_R7_REGNUM 9 | |
| 387 | #define S390_R8_REGNUM 10 | |
| 388 | #define S390_R9_REGNUM 11 | |
| 389 | #define S390_R10_REGNUM 12 | |
| 390 | #define S390_R11_REGNUM 13 | |
| 391 | #define S390_R12_REGNUM 14 | |
| 392 | #define S390_R13_REGNUM 15 | |
| 393 | #define S390_R14_REGNUM 16 | |
| 394 | #define S390_R15_REGNUM 17 | |
| 395 | /* Access Registers. */ | |
| 396 | #define S390_A0_REGNUM 18 | |
| 397 | #define S390_A1_REGNUM 19 | |
| 398 | #define S390_A2_REGNUM 20 | |
| 399 | #define S390_A3_REGNUM 21 | |
| 400 | #define S390_A4_REGNUM 22 | |
| 401 | #define S390_A5_REGNUM 23 | |
| 402 | #define S390_A6_REGNUM 24 | |
| 403 | #define S390_A7_REGNUM 25 | |
| 404 | #define S390_A8_REGNUM 26 | |
| 405 | #define S390_A9_REGNUM 27 | |
| 406 | #define S390_A10_REGNUM 28 | |
| 407 | #define S390_A11_REGNUM 29 | |
| 408 | #define S390_A12_REGNUM 30 | |
| 409 | #define S390_A13_REGNUM 31 | |
| 410 | #define S390_A14_REGNUM 32 | |
| 411 | #define S390_A15_REGNUM 33 | |
| 412 | /* Floating Point Control Word. */ | |
| 413 | #define S390_FPC_REGNUM 34 | |
| 414 | /* Floating Point Registers. */ | |
| 415 | #define S390_F0_REGNUM 35 | |
| 416 | #define S390_F1_REGNUM 36 | |
| 417 | #define S390_F2_REGNUM 37 | |
| 418 | #define S390_F3_REGNUM 38 | |
| 419 | #define S390_F4_REGNUM 39 | |
| 420 | #define S390_F5_REGNUM 40 | |
| 421 | #define S390_F6_REGNUM 41 | |
| 422 | #define S390_F7_REGNUM 42 | |
| 423 | #define S390_F8_REGNUM 43 | |
| 424 | #define S390_F9_REGNUM 44 | |
| 425 | #define S390_F10_REGNUM 45 | |
| 426 | #define S390_F11_REGNUM 46 | |
| 427 | #define S390_F12_REGNUM 47 | |
| 428 | #define S390_F13_REGNUM 48 | |
| 429 | #define S390_F14_REGNUM 49 | |
| 430 | #define S390_F15_REGNUM 50 | |
| 431 | /* Total. */ | |
| 432 | #define S390_NUM_REGS 51 | |
| 433 | ||
| bcec36ea AG |
434 | /* CC optimization */ |
| 435 | ||
| 436 | enum cc_op { | |
| 437 | CC_OP_CONST0 = 0, /* CC is 0 */ | |
| 438 | CC_OP_CONST1, /* CC is 1 */ | |
| 439 | CC_OP_CONST2, /* CC is 2 */ | |
| 440 | CC_OP_CONST3, /* CC is 3 */ | |
| 441 | ||
| 442 | CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */ | |
| 443 | CC_OP_STATIC, /* CC value is env->cc_op */ | |
| 444 | ||
| 445 | CC_OP_NZ, /* env->cc_dst != 0 */ | |
| 446 | CC_OP_LTGT_32, /* signed less/greater than (32bit) */ | |
| 447 | CC_OP_LTGT_64, /* signed less/greater than (64bit) */ | |
| 448 | CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */ | |
| 449 | CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */ | |
| 450 | CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */ | |
| 451 | CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */ | |
| 452 | ||
| 453 | CC_OP_ADD_64, /* overflow on add (64bit) */ | |
| 454 | CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */ | |
| 4e4bb438 | 455 | CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */ |
| e7d81004 SW |
456 | CC_OP_SUB_64, /* overflow on subtraction (64bit) */ |
| 457 | CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */ | |
| 4e4bb438 | 458 | CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */ |
| bcec36ea AG |
459 | CC_OP_ABS_64, /* sign eval on abs (64bit) */ |
| 460 | CC_OP_NABS_64, /* sign eval on nabs (64bit) */ | |
| 461 | ||
| 462 | CC_OP_ADD_32, /* overflow on add (32bit) */ | |
| 463 | CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */ | |
| 4e4bb438 | 464 | CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */ |
| e7d81004 SW |
465 | CC_OP_SUB_32, /* overflow on subtraction (32bit) */ |
| 466 | CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */ | |
| 4e4bb438 | 467 | CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */ |
| bcec36ea AG |
468 | CC_OP_ABS_32, /* sign eval on abs (64bit) */ |
| 469 | CC_OP_NABS_32, /* sign eval on nabs (64bit) */ | |
| 470 | ||
| 471 | CC_OP_COMP_32, /* complement */ | |
| 472 | CC_OP_COMP_64, /* complement */ | |
| 473 | ||
| 474 | CC_OP_TM_32, /* test under mask (32bit) */ | |
| 475 | CC_OP_TM_64, /* test under mask (64bit) */ | |
| 476 | ||
| bcec36ea AG |
477 | CC_OP_NZ_F32, /* FP dst != 0 (32bit) */ |
| 478 | CC_OP_NZ_F64, /* FP dst != 0 (64bit) */ | |
| 587626f8 | 479 | CC_OP_NZ_F128, /* FP dst != 0 (128bit) */ |
| bcec36ea AG |
480 | |
| 481 | CC_OP_ICM, /* insert characters under mask */ | |
| cbe24bfa RH |
482 | CC_OP_SLA_32, /* Calculate shift left signed (32bit) */ |
| 483 | CC_OP_SLA_64, /* Calculate shift left signed (64bit) */ | |
| 102bf2c6 | 484 | CC_OP_FLOGR, /* find leftmost one */ |
| bcec36ea AG |
485 | CC_OP_MAX |
| 486 | }; | |
| 487 | ||
| 488 | static const char *cc_names[] = { | |
| 489 | [CC_OP_CONST0] = "CC_OP_CONST0", | |
| 490 | [CC_OP_CONST1] = "CC_OP_CONST1", | |
| 491 | [CC_OP_CONST2] = "CC_OP_CONST2", | |
| 492 | [CC_OP_CONST3] = "CC_OP_CONST3", | |
| 493 | [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC", | |
| 494 | [CC_OP_STATIC] = "CC_OP_STATIC", | |
| 495 | [CC_OP_NZ] = "CC_OP_NZ", | |
| 496 | [CC_OP_LTGT_32] = "CC_OP_LTGT_32", | |
| 497 | [CC_OP_LTGT_64] = "CC_OP_LTGT_64", | |
| 498 | [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32", | |
| 499 | [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64", | |
| 500 | [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32", | |
| 501 | [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64", | |
| 502 | [CC_OP_ADD_64] = "CC_OP_ADD_64", | |
| 503 | [CC_OP_ADDU_64] = "CC_OP_ADDU_64", | |
| 4e4bb438 | 504 | [CC_OP_ADDC_64] = "CC_OP_ADDC_64", |
| bcec36ea AG |
505 | [CC_OP_SUB_64] = "CC_OP_SUB_64", |
| 506 | [CC_OP_SUBU_64] = "CC_OP_SUBU_64", | |
| 4e4bb438 | 507 | [CC_OP_SUBB_64] = "CC_OP_SUBB_64", |
| bcec36ea AG |
508 | [CC_OP_ABS_64] = "CC_OP_ABS_64", |
| 509 | [CC_OP_NABS_64] = "CC_OP_NABS_64", | |
| 510 | [CC_OP_ADD_32] = "CC_OP_ADD_32", | |
| 511 | [CC_OP_ADDU_32] = "CC_OP_ADDU_32", | |
| 4e4bb438 | 512 | [CC_OP_ADDC_32] = "CC_OP_ADDC_32", |
| bcec36ea AG |
513 | [CC_OP_SUB_32] = "CC_OP_SUB_32", |
| 514 | [CC_OP_SUBU_32] = "CC_OP_SUBU_32", | |
| 4e4bb438 | 515 | [CC_OP_SUBB_32] = "CC_OP_SUBB_32", |
| bcec36ea AG |
516 | [CC_OP_ABS_32] = "CC_OP_ABS_32", |
| 517 | [CC_OP_NABS_32] = "CC_OP_NABS_32", | |
| 518 | [CC_OP_COMP_32] = "CC_OP_COMP_32", | |
| 519 | [CC_OP_COMP_64] = "CC_OP_COMP_64", | |
| 520 | [CC_OP_TM_32] = "CC_OP_TM_32", | |
| 521 | [CC_OP_TM_64] = "CC_OP_TM_64", | |
| bcec36ea AG |
522 | [CC_OP_NZ_F32] = "CC_OP_NZ_F32", |
| 523 | [CC_OP_NZ_F64] = "CC_OP_NZ_F64", | |
| 587626f8 | 524 | [CC_OP_NZ_F128] = "CC_OP_NZ_F128", |
| bcec36ea | 525 | [CC_OP_ICM] = "CC_OP_ICM", |
| cbe24bfa RH |
526 | [CC_OP_SLA_32] = "CC_OP_SLA_32", |
| 527 | [CC_OP_SLA_64] = "CC_OP_SLA_64", | |
| 102bf2c6 | 528 | [CC_OP_FLOGR] = "CC_OP_FLOGR", |
| bcec36ea AG |
529 | }; |
| 530 | ||
| 531 | static inline const char *cc_name(int cc_op) | |
| 532 | { | |
| 533 | return cc_names[cc_op]; | |
| 534 | } | |
| 535 | ||
| bcec36ea AG |
536 | typedef struct LowCore |
| 537 | { | |
| 538 | /* prefix area: defined by architecture */ | |
| 539 | uint32_t ccw1[2]; /* 0x000 */ | |
| 540 | uint32_t ccw2[4]; /* 0x008 */ | |
| 541 | uint8_t pad1[0x80-0x18]; /* 0x018 */ | |
| 542 | uint32_t ext_params; /* 0x080 */ | |
| 543 | uint16_t cpu_addr; /* 0x084 */ | |
| 544 | uint16_t ext_int_code; /* 0x086 */ | |
| d5a103cd | 545 | uint16_t svc_ilen; /* 0x088 */ |
| bcec36ea | 546 | uint16_t svc_code; /* 0x08a */ |
| d5a103cd | 547 | uint16_t pgm_ilen; /* 0x08c */ |
| bcec36ea AG |
548 | uint16_t pgm_code; /* 0x08e */ |
| 549 | uint32_t data_exc_code; /* 0x090 */ | |
| 550 | uint16_t mon_class_num; /* 0x094 */ | |
| 551 | uint16_t per_perc_atmid; /* 0x096 */ | |
| 552 | uint64_t per_address; /* 0x098 */ | |
| 553 | uint8_t exc_access_id; /* 0x0a0 */ | |
| 554 | uint8_t per_access_id; /* 0x0a1 */ | |
| 555 | uint8_t op_access_id; /* 0x0a2 */ | |
| 556 | uint8_t ar_access_id; /* 0x0a3 */ | |
| 557 | uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */ | |
| 558 | uint64_t trans_exc_code; /* 0x0a8 */ | |
| 559 | uint64_t monitor_code; /* 0x0b0 */ | |
| 560 | uint16_t subchannel_id; /* 0x0b8 */ | |
| 561 | uint16_t subchannel_nr; /* 0x0ba */ | |
| 562 | uint32_t io_int_parm; /* 0x0bc */ | |
| 563 | uint32_t io_int_word; /* 0x0c0 */ | |
| 564 | uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */ | |
| 565 | uint32_t stfl_fac_list; /* 0x0c8 */ | |
| 566 | uint8_t pad4[0xe8-0xcc]; /* 0x0cc */ | |
| 567 | uint32_t mcck_interruption_code[2]; /* 0x0e8 */ | |
| 568 | uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */ | |
| 569 | uint32_t external_damage_code; /* 0x0f4 */ | |
| 570 | uint64_t failing_storage_address; /* 0x0f8 */ | |
| 571 | uint8_t pad6[0x120-0x100]; /* 0x100 */ | |
| 572 | PSW restart_old_psw; /* 0x120 */ | |
| 573 | PSW external_old_psw; /* 0x130 */ | |
| 574 | PSW svc_old_psw; /* 0x140 */ | |
| 575 | PSW program_old_psw; /* 0x150 */ | |
| 576 | PSW mcck_old_psw; /* 0x160 */ | |
| 577 | PSW io_old_psw; /* 0x170 */ | |
| 578 | uint8_t pad7[0x1a0-0x180]; /* 0x180 */ | |
| 579 | PSW restart_psw; /* 0x1a0 */ | |
| 580 | PSW external_new_psw; /* 0x1b0 */ | |
| 581 | PSW svc_new_psw; /* 0x1c0 */ | |
| 582 | PSW program_new_psw; /* 0x1d0 */ | |
| 583 | PSW mcck_new_psw; /* 0x1e0 */ | |
| 584 | PSW io_new_psw; /* 0x1f0 */ | |
| 585 | PSW return_psw; /* 0x200 */ | |
| 586 | uint8_t irb[64]; /* 0x210 */ | |
| 587 | uint64_t sync_enter_timer; /* 0x250 */ | |
| 588 | uint64_t async_enter_timer; /* 0x258 */ | |
| 589 | uint64_t exit_timer; /* 0x260 */ | |
| 590 | uint64_t last_update_timer; /* 0x268 */ | |
| 591 | uint64_t user_timer; /* 0x270 */ | |
| 592 | uint64_t system_timer; /* 0x278 */ | |
| 593 | uint64_t last_update_clock; /* 0x280 */ | |
| 594 | uint64_t steal_clock; /* 0x288 */ | |
| 595 | PSW return_mcck_psw; /* 0x290 */ | |
| 596 | uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */ | |
| 597 | /* System info area */ | |
| 598 | uint64_t save_area[16]; /* 0xc00 */ | |
| 599 | uint8_t pad9[0xd40-0xc80]; /* 0xc80 */ | |
| 600 | uint64_t kernel_stack; /* 0xd40 */ | |
| 601 | uint64_t thread_info; /* 0xd48 */ | |
| 602 | uint64_t async_stack; /* 0xd50 */ | |
| 603 | uint64_t kernel_asce; /* 0xd58 */ | |
| 604 | uint64_t user_asce; /* 0xd60 */ | |
| 605 | uint64_t panic_stack; /* 0xd68 */ | |
| 606 | uint64_t user_exec_asce; /* 0xd70 */ | |
| 607 | uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */ | |
| 608 | ||
| 609 | /* SMP info area: defined by DJB */ | |
| 610 | uint64_t clock_comparator; /* 0xdc0 */ | |
| 611 | uint64_t ext_call_fast; /* 0xdc8 */ | |
| 612 | uint64_t percpu_offset; /* 0xdd0 */ | |
| 613 | uint64_t current_task; /* 0xdd8 */ | |
| 614 | uint32_t softirq_pending; /* 0xde0 */ | |
| 615 | uint32_t pad_0x0de4; /* 0xde4 */ | |
| 616 | uint64_t int_clock; /* 0xde8 */ | |
| 617 | uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */ | |
| 618 | ||
| 619 | /* 0xe00 is used as indicator for dump tools */ | |
| 620 | /* whether the kernel died with panic() or not */ | |
| 621 | uint32_t panic_magic; /* 0xe00 */ | |
| 622 | ||
| 623 | uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */ | |
| 624 | ||
| 625 | /* 64 bit extparam used for pfault, diag 250 etc */ | |
| 626 | uint64_t ext_params2; /* 0x11B8 */ | |
| 627 | ||
| 628 | uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */ | |
| 629 | ||
| 630 | /* System info area */ | |
| 631 | ||
| 632 | uint64_t floating_pt_save_area[16]; /* 0x1200 */ | |
| 633 | uint64_t gpregs_save_area[16]; /* 0x1280 */ | |
| 634 | uint32_t st_status_fixed_logout[4]; /* 0x1300 */ | |
| 635 | uint8_t pad15[0x1318-0x1310]; /* 0x1310 */ | |
| 636 | uint32_t prefixreg_save_area; /* 0x1318 */ | |
| 637 | uint32_t fpt_creg_save_area; /* 0x131c */ | |
| 638 | uint8_t pad16[0x1324-0x1320]; /* 0x1320 */ | |
| 639 | uint32_t tod_progreg_save_area; /* 0x1324 */ | |
| 640 | uint32_t cpu_timer_save_area[2]; /* 0x1328 */ | |
| 641 | uint32_t clock_comp_save_area[2]; /* 0x1330 */ | |
| 642 | uint8_t pad17[0x1340-0x1338]; /* 0x1338 */ | |
| 643 | uint32_t access_regs_save_area[16]; /* 0x1340 */ | |
| 644 | uint64_t cregs_save_area[16]; /* 0x1380 */ | |
| 645 | ||
| 646 | /* align to the top of the prefix area */ | |
| 647 | ||
| 648 | uint8_t pad18[0x2000-0x1400]; /* 0x1400 */ | |
| 541dc0d4 | 649 | } QEMU_PACKED LowCore; |
| bcec36ea AG |
650 | |
| 651 | /* STSI */ | |
| 652 | #define STSI_LEVEL_MASK 0x00000000f0000000ULL | |
| 653 | #define STSI_LEVEL_CURRENT 0x0000000000000000ULL | |
| 654 | #define STSI_LEVEL_1 0x0000000010000000ULL | |
| 655 | #define STSI_LEVEL_2 0x0000000020000000ULL | |
| 656 | #define STSI_LEVEL_3 0x0000000030000000ULL | |
| 657 | #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL | |
| 658 | #define STSI_R0_SEL1_MASK 0x00000000000000ffULL | |
| 659 | #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL | |
| 660 | #define STSI_R1_SEL2_MASK 0x000000000000ffffULL | |
| 661 | ||
| 662 | /* Basic Machine Configuration */ | |
| 663 | struct sysib_111 { | |
| 664 | uint32_t res1[8]; | |
| 665 | uint8_t manuf[16]; | |
| 666 | uint8_t type[4]; | |
| 667 | uint8_t res2[12]; | |
| 668 | uint8_t model[16]; | |
| 669 | uint8_t sequence[16]; | |
| 670 | uint8_t plant[4]; | |
| 671 | uint8_t res3[156]; | |
| 672 | }; | |
| 673 | ||
| 674 | /* Basic Machine CPU */ | |
| 675 | struct sysib_121 { | |
| 676 | uint32_t res1[80]; | |
| 677 | uint8_t sequence[16]; | |
| 678 | uint8_t plant[4]; | |
| 679 | uint8_t res2[2]; | |
| 680 | uint16_t cpu_addr; | |
| 681 | uint8_t res3[152]; | |
| 682 | }; | |
| 683 | ||
| 684 | /* Basic Machine CPUs */ | |
| 685 | struct sysib_122 { | |
| 686 | uint8_t res1[32]; | |
| 687 | uint32_t capability; | |
| 688 | uint16_t total_cpus; | |
| 689 | uint16_t active_cpus; | |
| 690 | uint16_t standby_cpus; | |
| 691 | uint16_t reserved_cpus; | |
| 692 | uint16_t adjustments[2026]; | |
| 693 | }; | |
| 694 | ||
| 695 | /* LPAR CPU */ | |
| 696 | struct sysib_221 { | |
| 697 | uint32_t res1[80]; | |
| 698 | uint8_t sequence[16]; | |
| 699 | uint8_t plant[4]; | |
| 700 | uint16_t cpu_id; | |
| 701 | uint16_t cpu_addr; | |
| 702 | uint8_t res3[152]; | |
| 703 | }; | |
| 704 | ||
| 705 | /* LPAR CPUs */ | |
| 706 | struct sysib_222 { | |
| 707 | uint32_t res1[32]; | |
| 708 | uint16_t lpar_num; | |
| 709 | uint8_t res2; | |
| 710 | uint8_t lcpuc; | |
| 711 | uint16_t total_cpus; | |
| 712 | uint16_t conf_cpus; | |
| 713 | uint16_t standby_cpus; | |
| 714 | uint16_t reserved_cpus; | |
| 715 | uint8_t name[8]; | |
| 716 | uint32_t caf; | |
| 717 | uint8_t res3[16]; | |
| 718 | uint16_t dedicated_cpus; | |
| 719 | uint16_t shared_cpus; | |
| 720 | uint8_t res4[180]; | |
| 721 | }; | |
| 722 | ||
| 723 | /* VM CPUs */ | |
| 724 | struct sysib_322 { | |
| 725 | uint8_t res1[31]; | |
| 726 | uint8_t count; | |
| 727 | struct { | |
| 728 | uint8_t res2[4]; | |
| 729 | uint16_t total_cpus; | |
| 730 | uint16_t conf_cpus; | |
| 731 | uint16_t standby_cpus; | |
| 732 | uint16_t reserved_cpus; | |
| 733 | uint8_t name[8]; | |
| 734 | uint32_t caf; | |
| 735 | uint8_t cpi[16]; | |
| 736 | uint8_t res3[24]; | |
| 737 | } vm[8]; | |
| 738 | uint8_t res4[3552]; | |
| 739 | }; | |
| 740 | ||
| 741 | /* MMU defines */ | |
| 742 | #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */ | |
| 743 | #define _ASCE_SUBSPACE 0x200 /* subspace group control */ | |
| 744 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
| 745 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
| 746 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
| 747 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
| 748 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
| 749 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
| 750 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
| 751 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
| 752 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
| 753 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
| 754 | ||
| 755 | #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */ | |
| 756 | #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ | |
| 757 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ | |
| 758 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
| 759 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
| 760 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
| 761 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
| 762 | ||
| 763 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */ | |
| 764 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ | |
| 765 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
| 766 | ||
| 767 | #define _PAGE_RO 0x200 /* HW read-only bit */ | |
| 768 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ | |
| 769 | ||
| b9959138 AG |
770 | #define SK_C (0x1 << 1) |
| 771 | #define SK_R (0x1 << 2) | |
| 772 | #define SK_F (0x1 << 3) | |
| 773 | #define SK_ACC_MASK (0xf << 4) | |
| bcec36ea AG |
774 | |
| 775 | ||
| 776 | /* EBCDIC handling */ | |
| 777 | static const uint8_t ebcdic2ascii[] = { | |
| 778 | 0x00, 0x01, 0x02, 0x03, 0x07, 0x09, 0x07, 0x7F, | |
| 779 | 0x07, 0x07, 0x07, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, | |
| 780 | 0x10, 0x11, 0x12, 0x13, 0x07, 0x0A, 0x08, 0x07, | |
| 781 | 0x18, 0x19, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, | |
| 782 | 0x07, 0x07, 0x1C, 0x07, 0x07, 0x0A, 0x17, 0x1B, | |
| 783 | 0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x06, 0x07, | |
| 784 | 0x07, 0x07, 0x16, 0x07, 0x07, 0x07, 0x07, 0x04, | |
| 785 | 0x07, 0x07, 0x07, 0x07, 0x14, 0x15, 0x07, 0x1A, | |
| 786 | 0x20, 0xFF, 0x83, 0x84, 0x85, 0xA0, 0x07, 0x86, | |
| 787 | 0x87, 0xA4, 0x5B, 0x2E, 0x3C, 0x28, 0x2B, 0x21, | |
| 788 | 0x26, 0x82, 0x88, 0x89, 0x8A, 0xA1, 0x8C, 0x07, | |
| 789 | 0x8D, 0xE1, 0x5D, 0x24, 0x2A, 0x29, 0x3B, 0x5E, | |
| 790 | 0x2D, 0x2F, 0x07, 0x8E, 0x07, 0x07, 0x07, 0x8F, | |
| 791 | 0x80, 0xA5, 0x07, 0x2C, 0x25, 0x5F, 0x3E, 0x3F, | |
| 792 | 0x07, 0x90, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, | |
| 793 | 0x70, 0x60, 0x3A, 0x23, 0x40, 0x27, 0x3D, 0x22, | |
| 794 | 0x07, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, | |
| 795 | 0x68, 0x69, 0xAE, 0xAF, 0x07, 0x07, 0x07, 0xF1, | |
| 796 | 0xF8, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, | |
| 797 | 0x71, 0x72, 0xA6, 0xA7, 0x91, 0x07, 0x92, 0x07, | |
| 798 | 0xE6, 0x7E, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, | |
| 799 | 0x79, 0x7A, 0xAD, 0xAB, 0x07, 0x07, 0x07, 0x07, | |
| 800 | 0x9B, 0x9C, 0x9D, 0xFA, 0x07, 0x07, 0x07, 0xAC, | |
| 801 | 0xAB, 0x07, 0xAA, 0x7C, 0x07, 0x07, 0x07, 0x07, | |
| 802 | 0x7B, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, | |
| 803 | 0x48, 0x49, 0x07, 0x93, 0x94, 0x95, 0xA2, 0x07, | |
| 804 | 0x7D, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, | |
| 805 | 0x51, 0x52, 0x07, 0x96, 0x81, 0x97, 0xA3, 0x98, | |
| 806 | 0x5C, 0xF6, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, | |
| 807 | 0x59, 0x5A, 0xFD, 0x07, 0x99, 0x07, 0x07, 0x07, | |
| 808 | 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, | |
| 809 | 0x38, 0x39, 0x07, 0x07, 0x9A, 0x07, 0x07, 0x07, | |
| 810 | }; | |
| 811 | ||
| 812 | static const uint8_t ascii2ebcdic [] = { | |
| 813 | 0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F, | |
| 814 | 0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, | |
| 815 | 0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26, | |
| 816 | 0x18, 0x19, 0x3F, 0x27, 0x22, 0x1D, 0x1E, 0x1F, | |
| 817 | 0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D, | |
| 818 | 0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61, | |
| 819 | 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, | |
| 820 | 0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F, | |
| 821 | 0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, | |
| 822 | 0xC8, 0xC9, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, | |
| 823 | 0xD7, 0xD8, 0xD9, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, | |
| 824 | 0xE7, 0xE8, 0xE9, 0xBA, 0xE0, 0xBB, 0xB0, 0x6D, | |
| 825 | 0x79, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, | |
| 826 | 0x88, 0x89, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, | |
| 827 | 0x97, 0x98, 0x99, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, | |
| 828 | 0xA7, 0xA8, 0xA9, 0xC0, 0x4F, 0xD0, 0xA1, 0x07, | |
| 829 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 830 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 831 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 832 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 833 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 834 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 835 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 836 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 837 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 838 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 839 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 840 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 841 | 0x3F, 0x59, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 842 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 843 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 844 | 0x90, 0x3F, 0x3F, 0x3F, 0x3F, 0xEA, 0x3F, 0xFF | |
| 845 | }; | |
| 846 | ||
| 847 | static inline void ebcdic_put(uint8_t *p, const char *ascii, int len) | |
| 848 | { | |
| 849 | int i; | |
| 850 | ||
| 851 | for (i = 0; i < len; i++) { | |
| 852 | p[i] = ascii2ebcdic[(int)ascii[i]]; | |
| 853 | } | |
| 854 | } | |
| 855 | ||
| 856 | #define SIGP_SENSE 0x01 | |
| 857 | #define SIGP_EXTERNAL_CALL 0x02 | |
| 858 | #define SIGP_EMERGENCY 0x03 | |
| 859 | #define SIGP_START 0x04 | |
| 860 | #define SIGP_STOP 0x05 | |
| 861 | #define SIGP_RESTART 0x06 | |
| 862 | #define SIGP_STOP_STORE_STATUS 0x09 | |
| 863 | #define SIGP_INITIAL_CPU_RESET 0x0b | |
| 864 | #define SIGP_CPU_RESET 0x0c | |
| 865 | #define SIGP_SET_PREFIX 0x0d | |
| 866 | #define SIGP_STORE_STATUS_ADDR 0x0e | |
| 867 | #define SIGP_SET_ARCH 0x12 | |
| 868 | ||
| 869 | /* cpu status bits */ | |
| 870 | #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL | |
| 871 | #define SIGP_STAT_INCORRECT_STATE 0x00000200UL | |
| 872 | #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL | |
| 873 | #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL | |
| 874 | #define SIGP_STAT_STOPPED 0x00000040UL | |
| 875 | #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL | |
| 876 | #define SIGP_STAT_CHECK_STOP 0x00000010UL | |
| 877 | #define SIGP_STAT_INOPERATIVE 0x00000004UL | |
| 878 | #define SIGP_STAT_INVALID_ORDER 0x00000002UL | |
| 879 | #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL | |
| 880 | ||
| a4e3ad19 AF |
881 | void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); |
| 882 | int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, | |
| bcec36ea | 883 | target_ulong *raddr, int *flags); |
| f6c98f92 | 884 | int sclp_service_call(uint32_t sccb, uint64_t code); |
| a4e3ad19 | 885 | uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, |
| bcec36ea AG |
886 | uint64_t vr); |
| 887 | ||
| 888 | #define TARGET_HAS_ICE 1 | |
| 889 | ||
| 890 | /* The value of the TOD clock for 1.1.1970. */ | |
| 891 | #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL | |
| 892 | ||
| 893 | /* Converts ns to s390's clock format */ | |
| 894 | static inline uint64_t time2tod(uint64_t ns) { | |
| 895 | return (ns << 9) / 125; | |
| 896 | } | |
| 897 | ||
| a4e3ad19 | 898 | static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t param, |
| bcec36ea AG |
899 | uint64_t param64) |
| 900 | { | |
| 901 | if (env->ext_index == MAX_EXT_QUEUE - 1) { | |
| 902 | /* ugh - can't queue anymore. Let's drop. */ | |
| 903 | return; | |
| 904 | } | |
| 905 | ||
| 906 | env->ext_index++; | |
| 907 | assert(env->ext_index < MAX_EXT_QUEUE); | |
| 908 | ||
| 909 | env->ext_queue[env->ext_index].code = code; | |
| 910 | env->ext_queue[env->ext_index].param = param; | |
| 911 | env->ext_queue[env->ext_index].param64 = param64; | |
| 912 | ||
| 913 | env->pending_int |= INTERRUPT_EXT; | |
| 914 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
| 915 | } | |
| 10c339a0 | 916 | |
| 3993c6bd | 917 | static inline bool cpu_has_work(CPUState *cpu) |
| f081c76c | 918 | { |
| 3993c6bd AF |
919 | CPUS390XState *env = &S390_CPU(cpu)->env; |
| 920 | ||
| f081c76c BS |
921 | return (env->interrupt_request & CPU_INTERRUPT_HARD) && |
| 922 | (env->psw.mask & PSW_MASK_EXT); | |
| 923 | } | |
| 924 | ||
| a4e3ad19 | 925 | static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb) |
| f081c76c BS |
926 | { |
| 927 | env->psw.addr = tb->pc; | |
| 928 | } | |
| 929 | ||
| e72ca652 | 930 | /* fpu_helper.c */ |
| e72ca652 BS |
931 | uint32_t set_cc_nz_f32(float32 v); |
| 932 | uint32_t set_cc_nz_f64(float64 v); | |
| 587626f8 | 933 | uint32_t set_cc_nz_f128(float128 v); |
| e72ca652 | 934 | |
| aea1e885 | 935 | /* misc_helper.c */ |
| d5a103cd | 936 | void program_interrupt(CPUS390XState *env, uint32_t code, int ilen); |
| b4e2bd35 RH |
937 | void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, |
| 938 | uintptr_t retaddr); | |
| a78b0504 | 939 | |
| 10ec5117 | 940 | #endif |