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10ec5117 AG |
1 | /* |
2 | * S/390 helpers | |
3 | * | |
4 | * Copyright (c) 2009 Ulrich Hecht | |
d5a43964 | 5 | * Copyright (c) 2011 Alexander Graf |
10ec5117 AG |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
70539e18 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
10ec5117 AG |
19 | */ |
20 | ||
10ec5117 | 21 | #include "cpu.h" |
022c62cb | 22 | #include "exec/gdbstub.h" |
1de7afc9 | 23 | #include "qemu/timer.h" |
ef81522b | 24 | #ifndef CONFIG_USER_ONLY |
9c17d615 | 25 | #include "sysemu/sysemu.h" |
ef81522b | 26 | #endif |
10ec5117 | 27 | |
d5a43964 AG |
28 | //#define DEBUG_S390 |
29 | //#define DEBUG_S390_PTE | |
30 | //#define DEBUG_S390_STDOUT | |
31 | ||
32 | #ifdef DEBUG_S390 | |
33 | #ifdef DEBUG_S390_STDOUT | |
34 | #define DPRINTF(fmt, ...) \ | |
35 | do { fprintf(stderr, fmt, ## __VA_ARGS__); \ | |
36 | qemu_log(fmt, ##__VA_ARGS__); } while (0) | |
37 | #else | |
38 | #define DPRINTF(fmt, ...) \ | |
39 | do { qemu_log(fmt, ## __VA_ARGS__); } while (0) | |
40 | #endif | |
41 | #else | |
42 | #define DPRINTF(fmt, ...) \ | |
43 | do { } while (0) | |
44 | #endif | |
45 | ||
46 | #ifdef DEBUG_S390_PTE | |
47 | #define PTE_DPRINTF DPRINTF | |
48 | #else | |
49 | #define PTE_DPRINTF(fmt, ...) \ | |
50 | do { } while (0) | |
51 | #endif | |
52 | ||
53 | #ifndef CONFIG_USER_ONLY | |
8f22e0df | 54 | void s390x_tod_timer(void *opaque) |
d5a43964 | 55 | { |
b8ba6799 AF |
56 | S390CPU *cpu = opaque; |
57 | CPUS390XState *env = &cpu->env; | |
d5a43964 AG |
58 | |
59 | env->pending_int |= INTERRUPT_TOD; | |
60 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
61 | } | |
62 | ||
8f22e0df | 63 | void s390x_cpu_timer(void *opaque) |
d5a43964 | 64 | { |
b8ba6799 AF |
65 | S390CPU *cpu = opaque; |
66 | CPUS390XState *env = &cpu->env; | |
d5a43964 AG |
67 | |
68 | env->pending_int |= INTERRUPT_CPUTIMER; | |
69 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
70 | } | |
71 | #endif | |
10c339a0 | 72 | |
564b863d | 73 | S390CPU *cpu_s390x_init(const char *cpu_model) |
10ec5117 | 74 | { |
29e4bcb2 | 75 | S390CPU *cpu; |
10ec5117 | 76 | CPUS390XState *env; |
71e47088 | 77 | static int inited; |
10ec5117 | 78 | |
29e4bcb2 AF |
79 | cpu = S390_CPU(object_new(TYPE_S390_CPU)); |
80 | env = &cpu->env; | |
8f22e0df | 81 | |
d5ab9713 | 82 | if (tcg_enabled() && !inited) { |
10ec5117 | 83 | inited = 1; |
d5a43964 | 84 | s390x_translate_init(); |
10ec5117 AG |
85 | } |
86 | ||
87 | env->cpu_model_str = cpu_model; | |
1f136632 AF |
88 | |
89 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); | |
90 | ||
564b863d | 91 | return cpu; |
10ec5117 AG |
92 | } |
93 | ||
d5a43964 AG |
94 | #if defined(CONFIG_USER_ONLY) |
95 | ||
71e47088 | 96 | void do_interrupt(CPUS390XState *env) |
d5a43964 AG |
97 | { |
98 | env->exception_index = -1; | |
99 | } | |
100 | ||
71e47088 BS |
101 | int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address, |
102 | int rw, int mmu_idx) | |
d5a43964 | 103 | { |
d5a103cd RH |
104 | env->exception_index = EXCP_PGM; |
105 | env->int_pgm_code = PGM_ADDRESSING; | |
106 | /* On real machines this value is dropped into LowMem. Since this | |
107 | is userland, simply put this someplace that cpu_loop can find it. */ | |
71e47088 | 108 | env->__excp_addr = address; |
d5a43964 AG |
109 | return 1; |
110 | } | |
111 | ||
b7e516ce | 112 | #else /* !CONFIG_USER_ONLY */ |
d5a43964 AG |
113 | |
114 | /* Ensure to exit the TB after this call! */ | |
71e47088 | 115 | static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, |
d5a103cd | 116 | uint32_t ilen) |
d5a43964 AG |
117 | { |
118 | env->exception_index = EXCP_PGM; | |
119 | env->int_pgm_code = code; | |
d5a103cd | 120 | env->int_pgm_ilen = ilen; |
d5a43964 AG |
121 | } |
122 | ||
a4e3ad19 | 123 | static int trans_bits(CPUS390XState *env, uint64_t mode) |
d5a43964 AG |
124 | { |
125 | int bits = 0; | |
126 | ||
127 | switch (mode) { | |
128 | case PSW_ASC_PRIMARY: | |
129 | bits = 1; | |
130 | break; | |
131 | case PSW_ASC_SECONDARY: | |
132 | bits = 2; | |
133 | break; | |
134 | case PSW_ASC_HOME: | |
135 | bits = 3; | |
136 | break; | |
137 | default: | |
138 | cpu_abort(env, "unknown asc mode\n"); | |
139 | break; | |
140 | } | |
141 | ||
142 | return bits; | |
143 | } | |
144 | ||
71e47088 BS |
145 | static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, |
146 | uint64_t mode) | |
d5a43964 | 147 | { |
d5a103cd | 148 | int ilen = ILEN_LATER_INC; |
d5a43964 AG |
149 | int bits = trans_bits(env, mode) | 4; |
150 | ||
71e47088 | 151 | DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits); |
d5a43964 AG |
152 | |
153 | stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits); | |
d5a103cd | 154 | trigger_pgm_exception(env, PGM_PROTECTION, ilen); |
d5a43964 AG |
155 | } |
156 | ||
71e47088 BS |
157 | static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, |
158 | uint32_t type, uint64_t asc, int rw) | |
d5a43964 | 159 | { |
d5a103cd | 160 | int ilen = ILEN_LATER; |
d5a43964 AG |
161 | int bits = trans_bits(env, asc); |
162 | ||
d5a103cd | 163 | /* Code accesses have an undefined ilc. */ |
d5a43964 | 164 | if (rw == 2) { |
d5a103cd | 165 | ilen = 2; |
d5a43964 AG |
166 | } |
167 | ||
71e47088 | 168 | DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits); |
d5a43964 AG |
169 | |
170 | stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits); | |
d5a103cd | 171 | trigger_pgm_exception(env, type, ilen); |
d5a43964 AG |
172 | } |
173 | ||
71e47088 BS |
174 | static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, |
175 | uint64_t asc, uint64_t asce, int level, | |
176 | target_ulong *raddr, int *flags, int rw) | |
c92114b1 | 177 | { |
d5a43964 AG |
178 | uint64_t offs = 0; |
179 | uint64_t origin; | |
180 | uint64_t new_asce; | |
181 | ||
71e47088 | 182 | PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce); |
d5a43964 AG |
183 | |
184 | if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) || | |
185 | ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) { | |
186 | /* XXX different regions have different faults */ | |
71e47088 | 187 | DPRINTF("%s: invalid region\n", __func__); |
d5a43964 AG |
188 | trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw); |
189 | return -1; | |
190 | } | |
191 | ||
192 | if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) { | |
193 | trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw); | |
194 | return -1; | |
195 | } | |
196 | ||
197 | if (asce & _ASCE_REAL_SPACE) { | |
198 | /* direct mapping */ | |
199 | ||
200 | *raddr = vaddr; | |
201 | return 0; | |
202 | } | |
203 | ||
204 | origin = asce & _ASCE_ORIGIN; | |
205 | ||
206 | switch (level) { | |
207 | case _ASCE_TYPE_REGION1 + 4: | |
208 | offs = (vaddr >> 50) & 0x3ff8; | |
209 | break; | |
210 | case _ASCE_TYPE_REGION1: | |
211 | offs = (vaddr >> 39) & 0x3ff8; | |
212 | break; | |
213 | case _ASCE_TYPE_REGION2: | |
214 | offs = (vaddr >> 28) & 0x3ff8; | |
215 | break; | |
216 | case _ASCE_TYPE_REGION3: | |
217 | offs = (vaddr >> 17) & 0x3ff8; | |
218 | break; | |
219 | case _ASCE_TYPE_SEGMENT: | |
220 | offs = (vaddr >> 9) & 0x07f8; | |
221 | origin = asce & _SEGMENT_ENTRY_ORIGIN; | |
222 | break; | |
223 | } | |
224 | ||
225 | /* XXX region protection flags */ | |
226 | /* *flags &= ~PAGE_WRITE */ | |
227 | ||
228 | new_asce = ldq_phys(origin + offs); | |
229 | PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n", | |
71e47088 | 230 | __func__, origin, offs, new_asce); |
d5a43964 AG |
231 | |
232 | if (level != _ASCE_TYPE_SEGMENT) { | |
233 | /* yet another region */ | |
234 | return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr, | |
235 | flags, rw); | |
236 | } | |
237 | ||
238 | /* PTE */ | |
239 | if (new_asce & _PAGE_INVALID) { | |
71e47088 | 240 | DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce); |
d5a43964 AG |
241 | trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw); |
242 | return -1; | |
243 | } | |
244 | ||
245 | if (new_asce & _PAGE_RO) { | |
246 | *flags &= ~PAGE_WRITE; | |
247 | } | |
248 | ||
249 | *raddr = new_asce & _ASCE_ORIGIN; | |
250 | ||
71e47088 | 251 | PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce); |
d5a43964 | 252 | |
c92114b1 AG |
253 | return 0; |
254 | } | |
255 | ||
71e47088 BS |
256 | static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, |
257 | uint64_t asc, target_ulong *raddr, int *flags, | |
258 | int rw) | |
d5a43964 AG |
259 | { |
260 | uint64_t asce = 0; | |
261 | int level, new_level; | |
262 | int r; | |
10c339a0 | 263 | |
d5a43964 AG |
264 | switch (asc) { |
265 | case PSW_ASC_PRIMARY: | |
71e47088 | 266 | PTE_DPRINTF("%s: asc=primary\n", __func__); |
d5a43964 AG |
267 | asce = env->cregs[1]; |
268 | break; | |
269 | case PSW_ASC_SECONDARY: | |
71e47088 | 270 | PTE_DPRINTF("%s: asc=secondary\n", __func__); |
d5a43964 AG |
271 | asce = env->cregs[7]; |
272 | break; | |
273 | case PSW_ASC_HOME: | |
71e47088 | 274 | PTE_DPRINTF("%s: asc=home\n", __func__); |
d5a43964 AG |
275 | asce = env->cregs[13]; |
276 | break; | |
277 | } | |
278 | ||
279 | switch (asce & _ASCE_TYPE_MASK) { | |
280 | case _ASCE_TYPE_REGION1: | |
281 | break; | |
282 | case _ASCE_TYPE_REGION2: | |
283 | if (vaddr & 0xffe0000000000000ULL) { | |
284 | DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 | |
71e47088 | 285 | " 0xffe0000000000000ULL\n", __func__, vaddr); |
d5a43964 AG |
286 | trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw); |
287 | return -1; | |
288 | } | |
289 | break; | |
290 | case _ASCE_TYPE_REGION3: | |
291 | if (vaddr & 0xfffffc0000000000ULL) { | |
292 | DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 | |
71e47088 | 293 | " 0xfffffc0000000000ULL\n", __func__, vaddr); |
d5a43964 AG |
294 | trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw); |
295 | return -1; | |
296 | } | |
297 | break; | |
298 | case _ASCE_TYPE_SEGMENT: | |
299 | if (vaddr & 0xffffffff80000000ULL) { | |
300 | DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 | |
71e47088 | 301 | " 0xffffffff80000000ULL\n", __func__, vaddr); |
d5a43964 AG |
302 | trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw); |
303 | return -1; | |
304 | } | |
305 | break; | |
306 | } | |
307 | ||
308 | /* fake level above current */ | |
309 | level = asce & _ASCE_TYPE_MASK; | |
310 | new_level = level + 4; | |
311 | asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK); | |
312 | ||
313 | r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw); | |
314 | ||
315 | if ((rw == 1) && !(*flags & PAGE_WRITE)) { | |
316 | trigger_prot_fault(env, vaddr, asc); | |
317 | return -1; | |
318 | } | |
319 | ||
320 | return r; | |
321 | } | |
322 | ||
a4e3ad19 | 323 | int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, |
d5a43964 AG |
324 | target_ulong *raddr, int *flags) |
325 | { | |
326 | int r = -1; | |
b9959138 | 327 | uint8_t *sk; |
d5a43964 AG |
328 | |
329 | *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
330 | vaddr &= TARGET_PAGE_MASK; | |
331 | ||
332 | if (!(env->psw.mask & PSW_MASK_DAT)) { | |
333 | *raddr = vaddr; | |
334 | r = 0; | |
335 | goto out; | |
336 | } | |
337 | ||
338 | switch (asc) { | |
339 | case PSW_ASC_PRIMARY: | |
340 | case PSW_ASC_HOME: | |
341 | r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw); | |
342 | break; | |
343 | case PSW_ASC_SECONDARY: | |
344 | /* | |
345 | * Instruction: Primary | |
346 | * Data: Secondary | |
347 | */ | |
348 | if (rw == 2) { | |
349 | r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags, | |
350 | rw); | |
351 | *flags &= ~(PAGE_READ | PAGE_WRITE); | |
352 | } else { | |
353 | r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags, | |
354 | rw); | |
355 | *flags &= ~(PAGE_EXEC); | |
356 | } | |
357 | break; | |
358 | case PSW_ASC_ACCREG: | |
359 | default: | |
360 | hw_error("guest switched to unknown asc mode\n"); | |
361 | break; | |
362 | } | |
363 | ||
71e47088 | 364 | out: |
d5a43964 AG |
365 | /* Convert real address -> absolute address */ |
366 | if (*raddr < 0x2000) { | |
367 | *raddr = *raddr + env->psa; | |
368 | } | |
369 | ||
b9959138 AG |
370 | if (*raddr <= ram_size) { |
371 | sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE]; | |
372 | if (*flags & PAGE_READ) { | |
373 | *sk |= SK_R; | |
374 | } | |
375 | ||
376 | if (*flags & PAGE_WRITE) { | |
377 | *sk |= SK_C; | |
378 | } | |
379 | } | |
380 | ||
d5a43964 AG |
381 | return r; |
382 | } | |
383 | ||
71e47088 BS |
384 | int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr, |
385 | int rw, int mmu_idx) | |
10c339a0 | 386 | { |
d5a43964 AG |
387 | uint64_t asc = env->psw.mask & PSW_MASK_ASC; |
388 | target_ulong vaddr, raddr; | |
10c339a0 AG |
389 | int prot; |
390 | ||
97b348e7 | 391 | DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n", |
07cc7d12 | 392 | __func__, orig_vaddr, rw, mmu_idx); |
d5a43964 | 393 | |
71e47088 BS |
394 | orig_vaddr &= TARGET_PAGE_MASK; |
395 | vaddr = orig_vaddr; | |
d5a43964 AG |
396 | |
397 | /* 31-Bit mode */ | |
398 | if (!(env->psw.mask & PSW_MASK_64)) { | |
399 | vaddr &= 0x7fffffff; | |
400 | } | |
401 | ||
402 | if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) { | |
403 | /* Translation ended in exception */ | |
404 | return 1; | |
405 | } | |
10c339a0 | 406 | |
d5a43964 AG |
407 | /* check out of RAM access */ |
408 | if (raddr > (ram_size + virtio_size)) { | |
a6f921b0 AF |
409 | DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, |
410 | (uint64_t)raddr, (uint64_t)ram_size); | |
d5a103cd | 411 | trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER); |
d5a43964 AG |
412 | return 1; |
413 | } | |
10c339a0 | 414 | |
71e47088 | 415 | DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, |
d5a43964 AG |
416 | (uint64_t)vaddr, (uint64_t)raddr, prot); |
417 | ||
71e47088 | 418 | tlb_set_page(env, orig_vaddr, raddr, prot, |
d4c430a8 | 419 | mmu_idx, TARGET_PAGE_SIZE); |
d5a43964 | 420 | |
d4c430a8 | 421 | return 0; |
10c339a0 | 422 | } |
d5a43964 | 423 | |
a8170e5e | 424 | hwaddr cpu_get_phys_page_debug(CPUS390XState *env, |
71e47088 | 425 | target_ulong vaddr) |
d5a43964 AG |
426 | { |
427 | target_ulong raddr; | |
428 | int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
429 | int old_exc = env->exception_index; | |
430 | uint64_t asc = env->psw.mask & PSW_MASK_ASC; | |
431 | ||
432 | /* 31-Bit mode */ | |
433 | if (!(env->psw.mask & PSW_MASK_64)) { | |
434 | vaddr &= 0x7fffffff; | |
435 | } | |
436 | ||
437 | mmu_translate(env, vaddr, 2, asc, &raddr, &prot); | |
438 | env->exception_index = old_exc; | |
439 | ||
440 | return raddr; | |
441 | } | |
442 | ||
a4e3ad19 | 443 | void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) |
d5a43964 AG |
444 | { |
445 | if (mask & PSW_MASK_WAIT) { | |
49e15878 | 446 | S390CPU *cpu = s390_env_get_cpu(env); |
d5a43964 | 447 | if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) { |
49e15878 | 448 | if (s390_del_running_cpu(cpu) == 0) { |
ef81522b AG |
449 | #ifndef CONFIG_USER_ONLY |
450 | qemu_system_shutdown_request(); | |
451 | #endif | |
452 | } | |
d5a43964 | 453 | } |
ef81522b AG |
454 | env->halted = 1; |
455 | env->exception_index = EXCP_HLT; | |
d5a43964 AG |
456 | } |
457 | ||
458 | env->psw.addr = addr; | |
459 | env->psw.mask = mask; | |
51855ecf | 460 | env->cc_op = (mask >> 44) & 3; |
d5a43964 AG |
461 | } |
462 | ||
a4e3ad19 | 463 | static uint64_t get_psw_mask(CPUS390XState *env) |
d5a43964 | 464 | { |
51855ecf | 465 | uint64_t r; |
d5a43964 AG |
466 | |
467 | env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr); | |
468 | ||
51855ecf RH |
469 | r = env->psw.mask; |
470 | r &= ~PSW_MASK_CC; | |
d5a43964 | 471 | assert(!(env->cc_op & ~3)); |
51855ecf | 472 | r |= (uint64_t)env->cc_op << 44; |
d5a43964 AG |
473 | |
474 | return r; | |
475 | } | |
476 | ||
4782a23b CH |
477 | static LowCore *cpu_map_lowcore(CPUS390XState *env) |
478 | { | |
479 | LowCore *lowcore; | |
480 | hwaddr len = sizeof(LowCore); | |
481 | ||
482 | lowcore = cpu_physical_memory_map(env->psa, &len, 1); | |
483 | ||
484 | if (len < sizeof(LowCore)) { | |
485 | cpu_abort(env, "Could not map lowcore\n"); | |
486 | } | |
487 | ||
488 | return lowcore; | |
489 | } | |
490 | ||
491 | static void cpu_unmap_lowcore(LowCore *lowcore) | |
492 | { | |
493 | cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore)); | |
494 | } | |
495 | ||
38322ed6 CH |
496 | void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len, |
497 | int is_write) | |
498 | { | |
499 | hwaddr start = addr; | |
500 | ||
501 | /* Mind the prefix area. */ | |
502 | if (addr < 8192) { | |
503 | /* Map the lowcore. */ | |
504 | start += env->psa; | |
505 | *len = MIN(*len, 8192 - addr); | |
506 | } else if ((addr >= env->psa) && (addr < env->psa + 8192)) { | |
507 | /* Map the 0 page. */ | |
508 | start -= env->psa; | |
509 | *len = MIN(*len, 8192 - start); | |
510 | } | |
511 | ||
512 | return cpu_physical_memory_map(start, len, is_write); | |
513 | } | |
514 | ||
515 | void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len, | |
516 | int is_write) | |
517 | { | |
518 | cpu_physical_memory_unmap(addr, len, is_write, len); | |
519 | } | |
520 | ||
a4e3ad19 | 521 | static void do_svc_interrupt(CPUS390XState *env) |
d5a43964 AG |
522 | { |
523 | uint64_t mask, addr; | |
524 | LowCore *lowcore; | |
d5a43964 | 525 | |
4782a23b | 526 | lowcore = cpu_map_lowcore(env); |
d5a43964 AG |
527 | |
528 | lowcore->svc_code = cpu_to_be16(env->int_svc_code); | |
d5a103cd | 529 | lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen); |
d5a43964 | 530 | lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env)); |
d5a103cd | 531 | lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen); |
d5a43964 AG |
532 | mask = be64_to_cpu(lowcore->svc_new_psw.mask); |
533 | addr = be64_to_cpu(lowcore->svc_new_psw.addr); | |
534 | ||
4782a23b | 535 | cpu_unmap_lowcore(lowcore); |
d5a43964 AG |
536 | |
537 | load_psw(env, mask, addr); | |
538 | } | |
539 | ||
a4e3ad19 | 540 | static void do_program_interrupt(CPUS390XState *env) |
d5a43964 AG |
541 | { |
542 | uint64_t mask, addr; | |
543 | LowCore *lowcore; | |
d5a103cd | 544 | int ilen = env->int_pgm_ilen; |
d5a43964 | 545 | |
d5a103cd RH |
546 | switch (ilen) { |
547 | case ILEN_LATER: | |
548 | ilen = get_ilen(cpu_ldub_code(env, env->psw.addr)); | |
d5a43964 | 549 | break; |
d5a103cd RH |
550 | case ILEN_LATER_INC: |
551 | ilen = get_ilen(cpu_ldub_code(env, env->psw.addr)); | |
552 | env->psw.addr += ilen; | |
d5a43964 | 553 | break; |
d5a103cd RH |
554 | default: |
555 | assert(ilen == 2 || ilen == 4 || ilen == 6); | |
d5a43964 AG |
556 | } |
557 | ||
d5a103cd RH |
558 | qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n", |
559 | __func__, env->int_pgm_code, ilen); | |
d5a43964 | 560 | |
4782a23b | 561 | lowcore = cpu_map_lowcore(env); |
d5a43964 | 562 | |
d5a103cd | 563 | lowcore->pgm_ilen = cpu_to_be16(ilen); |
d5a43964 AG |
564 | lowcore->pgm_code = cpu_to_be16(env->int_pgm_code); |
565 | lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env)); | |
566 | lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr); | |
567 | mask = be64_to_cpu(lowcore->program_new_psw.mask); | |
568 | addr = be64_to_cpu(lowcore->program_new_psw.addr); | |
569 | ||
4782a23b | 570 | cpu_unmap_lowcore(lowcore); |
d5a43964 | 571 | |
71e47088 | 572 | DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__, |
d5a103cd | 573 | env->int_pgm_code, ilen, env->psw.mask, |
d5a43964 AG |
574 | env->psw.addr); |
575 | ||
576 | load_psw(env, mask, addr); | |
577 | } | |
578 | ||
579 | #define VIRTIO_SUBCODE_64 0x0D00 | |
580 | ||
a4e3ad19 | 581 | static void do_ext_interrupt(CPUS390XState *env) |
d5a43964 AG |
582 | { |
583 | uint64_t mask, addr; | |
584 | LowCore *lowcore; | |
d5a43964 AG |
585 | ExtQueue *q; |
586 | ||
587 | if (!(env->psw.mask & PSW_MASK_EXT)) { | |
588 | cpu_abort(env, "Ext int w/o ext mask\n"); | |
589 | } | |
590 | ||
591 | if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) { | |
592 | cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index); | |
593 | } | |
594 | ||
595 | q = &env->ext_queue[env->ext_index]; | |
4782a23b | 596 | lowcore = cpu_map_lowcore(env); |
d5a43964 AG |
597 | |
598 | lowcore->ext_int_code = cpu_to_be16(q->code); | |
599 | lowcore->ext_params = cpu_to_be32(q->param); | |
600 | lowcore->ext_params2 = cpu_to_be64(q->param64); | |
601 | lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env)); | |
602 | lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr); | |
603 | lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64); | |
604 | mask = be64_to_cpu(lowcore->external_new_psw.mask); | |
605 | addr = be64_to_cpu(lowcore->external_new_psw.addr); | |
606 | ||
4782a23b | 607 | cpu_unmap_lowcore(lowcore); |
d5a43964 AG |
608 | |
609 | env->ext_index--; | |
610 | if (env->ext_index == -1) { | |
611 | env->pending_int &= ~INTERRUPT_EXT; | |
612 | } | |
613 | ||
71e47088 | 614 | DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, |
d5a43964 AG |
615 | env->psw.mask, env->psw.addr); |
616 | ||
617 | load_psw(env, mask, addr); | |
618 | } | |
3110e292 | 619 | |
5d69c547 CH |
620 | static void do_io_interrupt(CPUS390XState *env) |
621 | { | |
5d69c547 CH |
622 | LowCore *lowcore; |
623 | IOIntQueue *q; | |
624 | uint8_t isc; | |
625 | int disable = 1; | |
626 | int found = 0; | |
627 | ||
628 | if (!(env->psw.mask & PSW_MASK_IO)) { | |
629 | cpu_abort(env, "I/O int w/o I/O mask\n"); | |
630 | } | |
631 | ||
632 | for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) { | |
91b0a8f3 CH |
633 | uint64_t isc_bits; |
634 | ||
5d69c547 CH |
635 | if (env->io_index[isc] < 0) { |
636 | continue; | |
637 | } | |
638 | if (env->io_index[isc] > MAX_IO_QUEUE) { | |
639 | cpu_abort(env, "I/O queue overrun for isc %d: %d\n", | |
640 | isc, env->io_index[isc]); | |
641 | } | |
642 | ||
643 | q = &env->io_queue[env->io_index[isc]][isc]; | |
91b0a8f3 CH |
644 | isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word)); |
645 | if (!(env->cregs[6] & isc_bits)) { | |
5d69c547 CH |
646 | disable = 0; |
647 | continue; | |
648 | } | |
bd9a8d85 CH |
649 | if (!found) { |
650 | uint64_t mask, addr; | |
5d69c547 | 651 | |
bd9a8d85 CH |
652 | found = 1; |
653 | lowcore = cpu_map_lowcore(env); | |
5d69c547 | 654 | |
bd9a8d85 CH |
655 | lowcore->subchannel_id = cpu_to_be16(q->id); |
656 | lowcore->subchannel_nr = cpu_to_be16(q->nr); | |
657 | lowcore->io_int_parm = cpu_to_be32(q->parm); | |
658 | lowcore->io_int_word = cpu_to_be32(q->word); | |
659 | lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env)); | |
660 | lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr); | |
661 | mask = be64_to_cpu(lowcore->io_new_psw.mask); | |
662 | addr = be64_to_cpu(lowcore->io_new_psw.addr); | |
5d69c547 | 663 | |
bd9a8d85 CH |
664 | cpu_unmap_lowcore(lowcore); |
665 | ||
666 | env->io_index[isc]--; | |
667 | ||
668 | DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, | |
669 | env->psw.mask, env->psw.addr); | |
670 | load_psw(env, mask, addr); | |
671 | } | |
b22dd124 | 672 | if (env->io_index[isc] >= 0) { |
5d69c547 CH |
673 | disable = 0; |
674 | } | |
bd9a8d85 | 675 | continue; |
5d69c547 CH |
676 | } |
677 | ||
678 | if (disable) { | |
679 | env->pending_int &= ~INTERRUPT_IO; | |
680 | } | |
681 | ||
5d69c547 CH |
682 | } |
683 | ||
684 | static void do_mchk_interrupt(CPUS390XState *env) | |
685 | { | |
686 | uint64_t mask, addr; | |
687 | LowCore *lowcore; | |
688 | MchkQueue *q; | |
689 | int i; | |
690 | ||
691 | if (!(env->psw.mask & PSW_MASK_MCHECK)) { | |
692 | cpu_abort(env, "Machine check w/o mchk mask\n"); | |
693 | } | |
694 | ||
695 | if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) { | |
696 | cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index); | |
697 | } | |
698 | ||
699 | q = &env->mchk_queue[env->mchk_index]; | |
700 | ||
701 | if (q->type != 1) { | |
702 | /* Don't know how to handle this... */ | |
703 | cpu_abort(env, "Unknown machine check type %d\n", q->type); | |
704 | } | |
705 | if (!(env->cregs[14] & (1 << 28))) { | |
706 | /* CRW machine checks disabled */ | |
707 | return; | |
708 | } | |
709 | ||
710 | lowcore = cpu_map_lowcore(env); | |
711 | ||
712 | for (i = 0; i < 16; i++) { | |
713 | lowcore->floating_pt_save_area[i] = cpu_to_be64(env->fregs[i].ll); | |
714 | lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]); | |
715 | lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]); | |
716 | lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]); | |
717 | } | |
718 | lowcore->prefixreg_save_area = cpu_to_be32(env->psa); | |
719 | lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc); | |
720 | lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr); | |
721 | lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32); | |
722 | lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm); | |
723 | lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32); | |
724 | lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc); | |
725 | ||
726 | lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d); | |
727 | lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000); | |
728 | lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env)); | |
729 | lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr); | |
730 | mask = be64_to_cpu(lowcore->mcck_new_psw.mask); | |
731 | addr = be64_to_cpu(lowcore->mcck_new_psw.addr); | |
732 | ||
733 | cpu_unmap_lowcore(lowcore); | |
734 | ||
735 | env->mchk_index--; | |
736 | if (env->mchk_index == -1) { | |
737 | env->pending_int &= ~INTERRUPT_MCHK; | |
738 | } | |
739 | ||
740 | DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, | |
741 | env->psw.mask, env->psw.addr); | |
742 | ||
743 | load_psw(env, mask, addr); | |
744 | } | |
745 | ||
71e47088 | 746 | void do_interrupt(CPUS390XState *env) |
3110e292 | 747 | { |
f9466733 AF |
748 | S390CPU *cpu = s390_env_get_cpu(env); |
749 | ||
0d404541 RH |
750 | qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n", |
751 | __func__, env->exception_index, env->psw.addr); | |
d5a43964 | 752 | |
49e15878 | 753 | s390_add_running_cpu(cpu); |
5d69c547 CH |
754 | /* handle machine checks */ |
755 | if ((env->psw.mask & PSW_MASK_MCHECK) && | |
756 | (env->exception_index == -1)) { | |
757 | if (env->pending_int & INTERRUPT_MCHK) { | |
758 | env->exception_index = EXCP_MCHK; | |
759 | } | |
760 | } | |
d5a43964 AG |
761 | /* handle external interrupts */ |
762 | if ((env->psw.mask & PSW_MASK_EXT) && | |
763 | env->exception_index == -1) { | |
764 | if (env->pending_int & INTERRUPT_EXT) { | |
765 | /* code is already in env */ | |
766 | env->exception_index = EXCP_EXT; | |
767 | } else if (env->pending_int & INTERRUPT_TOD) { | |
f9466733 | 768 | cpu_inject_ext(cpu, 0x1004, 0, 0); |
d5a43964 AG |
769 | env->exception_index = EXCP_EXT; |
770 | env->pending_int &= ~INTERRUPT_EXT; | |
771 | env->pending_int &= ~INTERRUPT_TOD; | |
772 | } else if (env->pending_int & INTERRUPT_CPUTIMER) { | |
f9466733 | 773 | cpu_inject_ext(cpu, 0x1005, 0, 0); |
d5a43964 AG |
774 | env->exception_index = EXCP_EXT; |
775 | env->pending_int &= ~INTERRUPT_EXT; | |
776 | env->pending_int &= ~INTERRUPT_TOD; | |
777 | } | |
778 | } | |
5d69c547 CH |
779 | /* handle I/O interrupts */ |
780 | if ((env->psw.mask & PSW_MASK_IO) && | |
781 | (env->exception_index == -1)) { | |
782 | if (env->pending_int & INTERRUPT_IO) { | |
783 | env->exception_index = EXCP_IO; | |
784 | } | |
785 | } | |
d5a43964 AG |
786 | |
787 | switch (env->exception_index) { | |
788 | case EXCP_PGM: | |
789 | do_program_interrupt(env); | |
790 | break; | |
791 | case EXCP_SVC: | |
792 | do_svc_interrupt(env); | |
793 | break; | |
794 | case EXCP_EXT: | |
795 | do_ext_interrupt(env); | |
796 | break; | |
5d69c547 CH |
797 | case EXCP_IO: |
798 | do_io_interrupt(env); | |
799 | break; | |
800 | case EXCP_MCHK: | |
801 | do_mchk_interrupt(env); | |
802 | break; | |
d5a43964 AG |
803 | } |
804 | env->exception_index = -1; | |
805 | ||
806 | if (!env->pending_int) { | |
807 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
808 | } | |
3110e292 | 809 | } |
d5a43964 AG |
810 | |
811 | #endif /* CONFIG_USER_ONLY */ |