[qemu.git] / target-s390x / helper.c

/*
 *  S/390 helpers
 *
 *  Copyright (c) 2009 Ulrich Hecht
 *  Copyright (c) 2011 Alexander Graf
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "exec/gdbstub.h"
#include "qemu-timer.h"
#ifndef CONFIG_USER_ONLY
#include "sysemu.h"
#endif

//#define DEBUG_S390
//#define DEBUG_S390_PTE
//#define DEBUG_S390_STDOUT

#ifdef DEBUG_S390
#ifdef DEBUG_S390_STDOUT
#define DPRINTF(fmt, ...) \
    do { fprintf(stderr, fmt, ## __VA_ARGS__); \
         qemu_log(fmt, ##__VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) \
    do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
#endif
#else
#define DPRINTF(fmt, ...) \
    do { } while (0)
#endif

#ifdef DEBUG_S390_PTE
#define PTE_DPRINTF DPRINTF
#else
#define PTE_DPRINTF(fmt, ...) \
    do { } while (0)
#endif

#ifndef CONFIG_USER_ONLY
void s390x_tod_timer(void *opaque)
{
    S390CPU *cpu = opaque;
    CPUS390XState *env = &cpu->env;

    env->pending_int |= INTERRUPT_TOD;
    cpu_interrupt(env, CPU_INTERRUPT_HARD);
}

void s390x_cpu_timer(void *opaque)
{
    S390CPU *cpu = opaque;
    CPUS390XState *env = &cpu->env;

    env->pending_int |= INTERRUPT_CPUTIMER;
    cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
#endif

S390CPU *cpu_s390x_init(const char *cpu_model)
{
    S390CPU *cpu;
    CPUS390XState *env;
    static int inited;

    cpu = S390_CPU(object_new(TYPE_S390_CPU));
    env = &cpu->env;

    if (tcg_enabled() && !inited) {
        inited = 1;
        s390x_translate_init();
    }

    env->cpu_model_str = cpu_model;
    qemu_init_vcpu(env);
    return cpu;
}

#if defined(CONFIG_USER_ONLY)

void do_interrupt(CPUS390XState *env)
{
    env->exception_index = -1;
}

int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
                               int rw, int mmu_idx)
{
    /* fprintf(stderr, "%s: address 0x%lx rw %d mmu_idx %d\n",
       __func__, address, rw, mmu_idx); */
    env->exception_index = EXCP_ADDR;
    /* FIXME: find out how this works on a real machine */
    env->__excp_addr = address;
    return 1;
}

#else /* !CONFIG_USER_ONLY */

/* Ensure to exit the TB after this call! */
static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
                                  uint32_t ilc)
{
    env->exception_index = EXCP_PGM;
    env->int_pgm_code = code;
    env->int_pgm_ilc = ilc;
}

static int trans_bits(CPUS390XState *env, uint64_t mode)
{
    int bits = 0;

    switch (mode) {
    case PSW_ASC_PRIMARY:
        bits = 1;
        break;
    case PSW_ASC_SECONDARY:
        bits = 2;
        break;
    case PSW_ASC_HOME:
        bits = 3;
        break;
    default:
        cpu_abort(env, "unknown asc mode\n");
        break;
    }

    return bits;
}

static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
                               uint64_t mode)
{
    int ilc = ILC_LATER_INC_2;
    int bits = trans_bits(env, mode) | 4;

    DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);

    stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
    trigger_pgm_exception(env, PGM_PROTECTION, ilc);
}

static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
                               uint32_t type, uint64_t asc, int rw)
{
    int ilc = ILC_LATER;
    int bits = trans_bits(env, asc);

    if (rw == 2) {
        /* code has is undefined ilc */
        ilc = 2;
    }

    DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);

    stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
    trigger_pgm_exception(env, type, ilc);
}

static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
                              uint64_t asc, uint64_t asce, int level,
                              target_ulong *raddr, int *flags, int rw)
{
    uint64_t offs = 0;
    uint64_t origin;
    uint64_t new_asce;

    PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);

    if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
        ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
        /* XXX different regions have different faults */
        DPRINTF("%s: invalid region\n", __func__);
        trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
        return -1;
    }

    if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
        trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
        return -1;
    }

    if (asce & _ASCE_REAL_SPACE) {
        /* direct mapping */

        *raddr = vaddr;
        return 0;
    }

    origin = asce & _ASCE_ORIGIN;

    switch (level) {
    case _ASCE_TYPE_REGION1 + 4:
        offs = (vaddr >> 50) & 0x3ff8;
        break;
    case _ASCE_TYPE_REGION1:
        offs = (vaddr >> 39) & 0x3ff8;
        break;
    case _ASCE_TYPE_REGION2:
        offs = (vaddr >> 28) & 0x3ff8;
        break;
    case _ASCE_TYPE_REGION3:
        offs = (vaddr >> 17) & 0x3ff8;
        break;
    case _ASCE_TYPE_SEGMENT:
        offs = (vaddr >> 9) & 0x07f8;
        origin = asce & _SEGMENT_ENTRY_ORIGIN;
        break;
    }

    /* XXX region protection flags */
    /* *flags &= ~PAGE_WRITE */

    new_asce = ldq_phys(origin + offs);
    PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
                __func__, origin, offs, new_asce);

    if (level != _ASCE_TYPE_SEGMENT) {
        /* yet another region */
        return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
                                  flags, rw);
    }

    /* PTE */
    if (new_asce & _PAGE_INVALID) {
        DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
        trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
        return -1;
    }

    if (new_asce & _PAGE_RO) {
        *flags &= ~PAGE_WRITE;
    }

    *raddr = new_asce & _ASCE_ORIGIN;

    PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);

    return 0;
}

static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
                             uint64_t asc, target_ulong *raddr, int *flags,
                             int rw)
{
    uint64_t asce = 0;
    int level, new_level;
    int r;

    switch (asc) {
    case PSW_ASC_PRIMARY:
        PTE_DPRINTF("%s: asc=primary\n", __func__);
        asce = env->cregs[1];
        break;
    case PSW_ASC_SECONDARY:
        PTE_DPRINTF("%s: asc=secondary\n", __func__);
        asce = env->cregs[7];
        break;
    case PSW_ASC_HOME:
        PTE_DPRINTF("%s: asc=home\n", __func__);
        asce = env->cregs[13];
        break;
    }

    switch (asce & _ASCE_TYPE_MASK) {
    case _ASCE_TYPE_REGION1:
        break;
    case _ASCE_TYPE_REGION2:
        if (vaddr & 0xffe0000000000000ULL) {
            DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
                    " 0xffe0000000000000ULL\n", __func__, vaddr);
            trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
            return -1;
        }
        break;
    case _ASCE_TYPE_REGION3:
        if (vaddr & 0xfffffc0000000000ULL) {
            DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
                    " 0xfffffc0000000000ULL\n", __func__, vaddr);
            trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
            return -1;
        }
        break;
    case _ASCE_TYPE_SEGMENT:
        if (vaddr & 0xffffffff80000000ULL) {
            DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
                    " 0xffffffff80000000ULL\n", __func__, vaddr);
            trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
            return -1;
        }
        break;
    }

    /* fake level above current */
    level = asce & _ASCE_TYPE_MASK;
    new_level = level + 4;
    asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);

    r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);

    if ((rw == 1) && !(*flags & PAGE_WRITE)) {
        trigger_prot_fault(env, vaddr, asc);
        return -1;
    }

    return r;
}

int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
                  target_ulong *raddr, int *flags)
{
    int r = -1;
    uint8_t *sk;

    *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
    vaddr &= TARGET_PAGE_MASK;

    if (!(env->psw.mask & PSW_MASK_DAT)) {
        *raddr = vaddr;
        r = 0;
        goto out;
    }

    switch (asc) {
    case PSW_ASC_PRIMARY:
    case PSW_ASC_HOME:
        r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
        break;
    case PSW_ASC_SECONDARY:
        /*
         * Instruction: Primary
         * Data: Secondary
         */
        if (rw == 2) {
            r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
                                  rw);
            *flags &= ~(PAGE_READ | PAGE_WRITE);
        } else {
            r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
                                  rw);
            *flags &= ~(PAGE_EXEC);
        }
        break;
    case PSW_ASC_ACCREG:
    default:
        hw_error("guest switched to unknown asc mode\n");
        break;
    }

 out:
    /* Convert real address -> absolute address */
    if (*raddr < 0x2000) {
        *raddr = *raddr + env->psa;
    }

    if (*raddr <= ram_size) {
        sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
        if (*flags & PAGE_READ) {
            *sk |= SK_R;
        }

        if (*flags & PAGE_WRITE) {
            *sk |= SK_C;
        }
    }

    return r;
}

int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
                               int rw, int mmu_idx)
{
    uint64_t asc = env->psw.mask & PSW_MASK_ASC;
    target_ulong vaddr, raddr;
    int prot;

    DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
            __func__, _vaddr, rw, mmu_idx);

    orig_vaddr &= TARGET_PAGE_MASK;
    vaddr = orig_vaddr;

    /* 31-Bit mode */
    if (!(env->psw.mask & PSW_MASK_64)) {
        vaddr &= 0x7fffffff;
    }

    if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
        /* Translation ended in exception */
        return 1;
    }

    /* check out of RAM access */
    if (raddr > (ram_size + virtio_size)) {
        DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
                (uint64_t)aaddr, (uint64_t)ram_size);
        trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
        return 1;
    }

    DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
            (uint64_t)vaddr, (uint64_t)raddr, prot);

    tlb_set_page(env, orig_vaddr, raddr, prot,
                 mmu_idx, TARGET_PAGE_SIZE);

    return 0;
}

hwaddr cpu_get_phys_page_debug(CPUS390XState *env,
                                           target_ulong vaddr)
{
    target_ulong raddr;
    int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
    int old_exc = env->exception_index;
    uint64_t asc = env->psw.mask & PSW_MASK_ASC;

    /* 31-Bit mode */
    if (!(env->psw.mask & PSW_MASK_64)) {
        vaddr &= 0x7fffffff;
    }

    mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
    env->exception_index = old_exc;

    return raddr;
}

void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
{
    if (mask & PSW_MASK_WAIT) {
        if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
            if (s390_del_running_cpu(env) == 0) {
#ifndef CONFIG_USER_ONLY
                qemu_system_shutdown_request();
#endif
            }
        }
        env->halted = 1;
        env->exception_index = EXCP_HLT;
    }

    env->psw.addr = addr;
    env->psw.mask = mask;
    env->cc_op = (mask >> 13) & 3;
}

static uint64_t get_psw_mask(CPUS390XState *env)
{
    uint64_t r = env->psw.mask;

    env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);

    r &= ~(3ULL << 13);
    assert(!(env->cc_op & ~3));
    r |= env->cc_op << 13;

    return r;
}

static void do_svc_interrupt(CPUS390XState *env)
{
    uint64_t mask, addr;
    LowCore *lowcore;
    hwaddr len = TARGET_PAGE_SIZE;

    lowcore = cpu_physical_memory_map(env->psa, &len, 1);

    lowcore->svc_code = cpu_to_be16(env->int_svc_code);
    lowcore->svc_ilc = cpu_to_be16(env->int_svc_ilc);
    lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
    lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + (env->int_svc_ilc));
    mask = be64_to_cpu(lowcore->svc_new_psw.mask);
    addr = be64_to_cpu(lowcore->svc_new_psw.addr);

    cpu_physical_memory_unmap(lowcore, len, 1, len);

    load_psw(env, mask, addr);
}

static void do_program_interrupt(CPUS390XState *env)
{
    uint64_t mask, addr;
    LowCore *lowcore;
    hwaddr len = TARGET_PAGE_SIZE;
    int ilc = env->int_pgm_ilc;

    switch (ilc) {
    case ILC_LATER:
        ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
        break;
    case ILC_LATER_INC:
        ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
        env->psw.addr += ilc * 2;
        break;
    case ILC_LATER_INC_2:
        ilc = get_ilc(cpu_ldub_code(env, env->psw.addr)) * 2;
        env->psw.addr += ilc;
        break;
    }

    qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilc=%d\n",
                  __func__, env->int_pgm_code, ilc);

    lowcore = cpu_physical_memory_map(env->psa, &len, 1);

    lowcore->pgm_ilc = cpu_to_be16(ilc);
    lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
    lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
    lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
    mask = be64_to_cpu(lowcore->program_new_psw.mask);
    addr = be64_to_cpu(lowcore->program_new_psw.addr);

    cpu_physical_memory_unmap(lowcore, len, 1, len);

    DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
            env->int_pgm_code, ilc, env->psw.mask,
            env->psw.addr);

    load_psw(env, mask, addr);
}

#define VIRTIO_SUBCODE_64 0x0D00

static void do_ext_interrupt(CPUS390XState *env)
{
    uint64_t mask, addr;
    LowCore *lowcore;
    hwaddr len = TARGET_PAGE_SIZE;
    ExtQueue *q;

    if (!(env->psw.mask & PSW_MASK_EXT)) {
        cpu_abort(env, "Ext int w/o ext mask\n");
    }

    if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
        cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
    }

    q = &env->ext_queue[env->ext_index];
    lowcore = cpu_physical_memory_map(env->psa, &len, 1);

    lowcore->ext_int_code = cpu_to_be16(q->code);
    lowcore->ext_params = cpu_to_be32(q->param);
    lowcore->ext_params2 = cpu_to_be64(q->param64);
    lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
    lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
    lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
    mask = be64_to_cpu(lowcore->external_new_psw.mask);
    addr = be64_to_cpu(lowcore->external_new_psw.addr);

    cpu_physical_memory_unmap(lowcore, len, 1, len);

    env->ext_index--;
    if (env->ext_index == -1) {
        env->pending_int &= ~INTERRUPT_EXT;
    }

    DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
            env->psw.mask, env->psw.addr);

    load_psw(env, mask, addr);
}

void do_interrupt(CPUS390XState *env)
{
    qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
                  __func__, env->exception_index, env->psw.addr);

    s390_add_running_cpu(env);
    /* handle external interrupts */
    if ((env->psw.mask & PSW_MASK_EXT) &&
        env->exception_index == -1) {
        if (env->pending_int & INTERRUPT_EXT) {
            /* code is already in env */
            env->exception_index = EXCP_EXT;
        } else if (env->pending_int & INTERRUPT_TOD) {
            cpu_inject_ext(env, 0x1004, 0, 0);
            env->exception_index = EXCP_EXT;
            env->pending_int &= ~INTERRUPT_EXT;
            env->pending_int &= ~INTERRUPT_TOD;
        } else if (env->pending_int & INTERRUPT_CPUTIMER) {
            cpu_inject_ext(env, 0x1005, 0, 0);
            env->exception_index = EXCP_EXT;
            env->pending_int &= ~INTERRUPT_EXT;
            env->pending_int &= ~INTERRUPT_TOD;
        }
    }

    switch (env->exception_index) {
    case EXCP_PGM:
        do_program_interrupt(env);
        break;
    case EXCP_SVC:
        do_svc_interrupt(env);
        break;
    case EXCP_EXT:
        do_ext_interrupt(env);
        break;
    }
    env->exception_index = -1;

    if (!env->pending_int) {
        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
    }
}

#endif /* CONFIG_USER_ONLY */
Commit	Line	Data
10ec5117 AG	1	/*
	2	* S/390 helpers
	3	*
	4	* Copyright (c) 2009 Ulrich Hecht
d5a43964	5	* Copyright (c) 2011 Alexander Graf
10ec5117 AG	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
70539e18	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117 AG	19	*/
10ec5117 AG	20
10ec5117	21	#include "cpu.h"
022c62cb	22	#include "exec/gdbstub.h"
d5a43964	23	#include "qemu-timer.h"
ef81522b AG	24	#ifndef CONFIG_USER_ONLY
	25	#include "sysemu.h"
	26	#endif
10ec5117	27
d5a43964 AG	28	//#define DEBUG_S390
	29	//#define DEBUG_S390_PTE
	30	//#define DEBUG_S390_STDOUT
	31
	32	#ifdef DEBUG_S390
	33	#ifdef DEBUG_S390_STDOUT
	34	#define DPRINTF(fmt, ...) \
	35	do { fprintf(stderr, fmt, ## __VA_ARGS__); \
	36	qemu_log(fmt, ##__VA_ARGS__); } while (0)
	37	#else
	38	#define DPRINTF(fmt, ...) \
	39	do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
	40	#endif
	41	#else
	42	#define DPRINTF(fmt, ...) \
	43	do { } while (0)
	44	#endif
	45
	46	#ifdef DEBUG_S390_PTE
	47	#define PTE_DPRINTF DPRINTF
	48	#else
	49	#define PTE_DPRINTF(fmt, ...) \
	50	do { } while (0)
	51	#endif
	52
	53	#ifndef CONFIG_USER_ONLY
8f22e0df	54	void s390x_tod_timer(void *opaque)
d5a43964	55	{
b8ba6799 AF	56	S390CPU *cpu = opaque;
b8ba6799 AF	57	CPUS390XState *env = &cpu->env;
d5a43964 AG	58
	59	env->pending_int \|= INTERRUPT_TOD;
	60	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	61	}
	62
8f22e0df	63	void s390x_cpu_timer(void *opaque)
d5a43964	64	{
b8ba6799 AF	65	S390CPU *cpu = opaque;
b8ba6799 AF	66	CPUS390XState *env = &cpu->env;
d5a43964 AG	67
	68	env->pending_int \|= INTERRUPT_CPUTIMER;
	69	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	70	}
	71	#endif
10c339a0	72
564b863d	73	S390CPU cpu_s390x_init(const char cpu_model)
10ec5117	74	{
29e4bcb2	75	S390CPU *cpu;
10ec5117	76	CPUS390XState *env;
71e47088	77	static int inited;
10ec5117	78
29e4bcb2 AF	79	cpu = S390_CPU(object_new(TYPE_S390_CPU));
29e4bcb2 AF	80	env = &cpu->env;
8f22e0df	81
d5ab9713	82	if (tcg_enabled() && !inited) {
10ec5117	83	inited = 1;
d5a43964	84	s390x_translate_init();
10ec5117 AG	85	}
	86
	87	env->cpu_model_str = cpu_model;
10ec5117	88	qemu_init_vcpu(env);
564b863d	89	return cpu;
10ec5117 AG	90	}
10ec5117 AG	91
d5a43964 AG	92	#if defined(CONFIG_USER_ONLY)
d5a43964 AG	93
71e47088	94	void do_interrupt(CPUS390XState *env)
d5a43964 AG	95	{
	96	env->exception_index = -1;
	97	}
	98
71e47088 BS	99	int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
71e47088 BS	100	int rw, int mmu_idx)
d5a43964	101	{
71e47088 BS	102	/* fprintf(stderr, "%s: address 0x%lx rw %d mmu_idx %d\n",
71e47088 BS	103	__func__, address, rw, mmu_idx); */
d5a43964	104	env->exception_index = EXCP_ADDR;
71e47088 BS	105	/* FIXME: find out how this works on a real machine */
71e47088 BS	106	env->__excp_addr = address;
d5a43964 AG	107	return 1;
	108	}
	109
b7e516ce	110	#else /* !CONFIG_USER_ONLY */
d5a43964 AG	111
d5a43964 AG	112	/* Ensure to exit the TB after this call! */
71e47088 BS	113	static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
71e47088 BS	114	uint32_t ilc)
d5a43964 AG	115	{
	116	env->exception_index = EXCP_PGM;
	117	env->int_pgm_code = code;
	118	env->int_pgm_ilc = ilc;
	119	}
	120
a4e3ad19	121	static int trans_bits(CPUS390XState *env, uint64_t mode)
d5a43964 AG	122	{
	123	int bits = 0;
	124
	125	switch (mode) {
	126	case PSW_ASC_PRIMARY:
	127	bits = 1;
	128	break;
	129	case PSW_ASC_SECONDARY:
	130	bits = 2;
	131	break;
	132	case PSW_ASC_HOME:
	133	bits = 3;
	134	break;
	135	default:
	136	cpu_abort(env, "unknown asc mode\n");
	137	break;
	138	}
	139
	140	return bits;
	141	}
	142
71e47088 BS	143	static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
71e47088 BS	144	uint64_t mode)
d5a43964 AG	145	{
	146	int ilc = ILC_LATER_INC_2;
	147	int bits = trans_bits(env, mode) \| 4;
	148
71e47088	149	DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
d5a43964 AG	150
	151	stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr \| bits);
	152	trigger_pgm_exception(env, PGM_PROTECTION, ilc);
	153	}
	154
71e47088 BS	155	static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
71e47088 BS	156	uint32_t type, uint64_t asc, int rw)
d5a43964 AG	157	{
	158	int ilc = ILC_LATER;
	159	int bits = trans_bits(env, asc);
	160
	161	if (rw == 2) {
	162	/* code has is undefined ilc */
	163	ilc = 2;
	164	}
	165
71e47088	166	DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
d5a43964 AG	167
	168	stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr \| bits);
	169	trigger_pgm_exception(env, type, ilc);
	170	}
	171
71e47088 BS	172	static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
	173	uint64_t asc, uint64_t asce, int level,
	174	target_ulong raddr, int flags, int rw)
c92114b1	175	{
d5a43964 AG	176	uint64_t offs = 0;
	177	uint64_t origin;
	178	uint64_t new_asce;
	179
71e47088	180	PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
d5a43964 AG	181
	182	if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) \|\|
	183	((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
	184	/* XXX different regions have different faults */
71e47088	185	DPRINTF("%s: invalid region\n", __func__);
d5a43964 AG	186	trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
	187	return -1;
	188	}
	189
	190	if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
	191	trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
	192	return -1;
	193	}
	194
	195	if (asce & _ASCE_REAL_SPACE) {
	196	/* direct mapping */
	197
	198	*raddr = vaddr;
	199	return 0;
	200	}
	201
	202	origin = asce & _ASCE_ORIGIN;
	203
	204	switch (level) {
	205	case _ASCE_TYPE_REGION1 + 4:
	206	offs = (vaddr >> 50) & 0x3ff8;
	207	break;
	208	case _ASCE_TYPE_REGION1:
	209	offs = (vaddr >> 39) & 0x3ff8;
	210	break;
	211	case _ASCE_TYPE_REGION2:
	212	offs = (vaddr >> 28) & 0x3ff8;
	213	break;
	214	case _ASCE_TYPE_REGION3:
	215	offs = (vaddr >> 17) & 0x3ff8;
	216	break;
	217	case _ASCE_TYPE_SEGMENT:
	218	offs = (vaddr >> 9) & 0x07f8;
	219	origin = asce & _SEGMENT_ENTRY_ORIGIN;
	220	break;
	221	}
	222
	223	/* XXX region protection flags */
	224	/* flags &= ~PAGE_WRITE /
	225
	226	new_asce = ldq_phys(origin + offs);
	227	PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
71e47088	228	__func__, origin, offs, new_asce);
d5a43964 AG	229
	230	if (level != _ASCE_TYPE_SEGMENT) {
	231	/* yet another region */
	232	return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
	233	flags, rw);
	234	}
	235
	236	/* PTE */
	237	if (new_asce & _PAGE_INVALID) {
71e47088	238	DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
d5a43964 AG	239	trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
	240	return -1;
	241	}
	242
	243	if (new_asce & _PAGE_RO) {
	244	*flags &= ~PAGE_WRITE;
	245	}
	246
	247	*raddr = new_asce & _ASCE_ORIGIN;
	248
71e47088	249	PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
d5a43964	250
c92114b1 AG	251	return 0;
	252	}
	253
71e47088 BS	254	static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
	255	uint64_t asc, target_ulong raddr, int flags,
	256	int rw)
d5a43964 AG	257	{
	258	uint64_t asce = 0;
	259	int level, new_level;
	260	int r;
10c339a0	261
d5a43964 AG	262	switch (asc) {
d5a43964 AG	263	case PSW_ASC_PRIMARY:
71e47088	264	PTE_DPRINTF("%s: asc=primary\n", __func__);
d5a43964 AG	265	asce = env->cregs[1];
	266	break;
	267	case PSW_ASC_SECONDARY:
71e47088	268	PTE_DPRINTF("%s: asc=secondary\n", __func__);
d5a43964 AG	269	asce = env->cregs[7];
	270	break;
	271	case PSW_ASC_HOME:
71e47088	272	PTE_DPRINTF("%s: asc=home\n", __func__);
d5a43964 AG	273	asce = env->cregs[13];
	274	break;
	275	}
	276
	277	switch (asce & _ASCE_TYPE_MASK) {
	278	case _ASCE_TYPE_REGION1:
	279	break;
	280	case _ASCE_TYPE_REGION2:
	281	if (vaddr & 0xffe0000000000000ULL) {
	282	DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
71e47088	283	" 0xffe0000000000000ULL\n", __func__, vaddr);
d5a43964 AG	284	trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
	285	return -1;
	286	}
	287	break;
	288	case _ASCE_TYPE_REGION3:
	289	if (vaddr & 0xfffffc0000000000ULL) {
	290	DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
71e47088	291	" 0xfffffc0000000000ULL\n", __func__, vaddr);
d5a43964 AG	292	trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
	293	return -1;
	294	}
	295	break;
	296	case _ASCE_TYPE_SEGMENT:
	297	if (vaddr & 0xffffffff80000000ULL) {
	298	DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
71e47088	299	" 0xffffffff80000000ULL\n", __func__, vaddr);
d5a43964 AG	300	trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
	301	return -1;
	302	}
	303	break;
	304	}
	305
	306	/* fake level above current */
	307	level = asce & _ASCE_TYPE_MASK;
	308	new_level = level + 4;
	309	asce = (asce & ~_ASCE_TYPE_MASK) \| (new_level & _ASCE_TYPE_MASK);
	310
	311	r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
	312
	313	if ((rw == 1) && !(*flags & PAGE_WRITE)) {
	314	trigger_prot_fault(env, vaddr, asc);
	315	return -1;
	316	}
	317
	318	return r;
	319	}
	320
a4e3ad19	321	int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
d5a43964 AG	322	target_ulong raddr, int flags)
	323	{
	324	int r = -1;
b9959138	325	uint8_t *sk;
d5a43964 AG	326
	327	*flags = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
	328	vaddr &= TARGET_PAGE_MASK;
	329
	330	if (!(env->psw.mask & PSW_MASK_DAT)) {
	331	*raddr = vaddr;
	332	r = 0;
	333	goto out;
	334	}
	335
	336	switch (asc) {
	337	case PSW_ASC_PRIMARY:
	338	case PSW_ASC_HOME:
	339	r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
	340	break;
	341	case PSW_ASC_SECONDARY:
	342	/*
	343	* Instruction: Primary
	344	* Data: Secondary
	345	*/
	346	if (rw == 2) {
	347	r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
	348	rw);
	349	*flags &= ~(PAGE_READ \| PAGE_WRITE);
	350	} else {
	351	r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
	352	rw);
	353	*flags &= ~(PAGE_EXEC);
	354	}
	355	break;
	356	case PSW_ASC_ACCREG:
	357	default:
	358	hw_error("guest switched to unknown asc mode\n");
	359	break;
	360	}
	361
71e47088	362	out:
d5a43964 AG	363	/* Convert real address -> absolute address */
	364	if (*raddr < 0x2000) {
	365	raddr = raddr + env->psa;
	366	}
	367
b9959138 AG	368	if (*raddr <= ram_size) {
	369	sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
	370	if (*flags & PAGE_READ) {
	371	*sk \|= SK_R;
	372	}
	373
	374	if (*flags & PAGE_WRITE) {
	375	*sk \|= SK_C;
	376	}
	377	}
	378
d5a43964 AG	379	return r;
	380	}
	381
71e47088 BS	382	int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
71e47088 BS	383	int rw, int mmu_idx)
10c339a0	384	{
d5a43964 AG	385	uint64_t asc = env->psw.mask & PSW_MASK_ASC;
d5a43964 AG	386	target_ulong vaddr, raddr;
10c339a0 AG	387	int prot;
10c339a0 AG	388
97b348e7	389	DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
71e47088	390	__func__, _vaddr, rw, mmu_idx);
d5a43964	391
71e47088 BS	392	orig_vaddr &= TARGET_PAGE_MASK;
71e47088 BS	393	vaddr = orig_vaddr;
d5a43964 AG	394
	395	/* 31-Bit mode */
	396	if (!(env->psw.mask & PSW_MASK_64)) {
	397	vaddr &= 0x7fffffff;
	398	}
	399
	400	if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
	401	/* Translation ended in exception */
	402	return 1;
	403	}
10c339a0	404
d5a43964 AG	405	/* check out of RAM access */
d5a43964 AG	406	if (raddr > (ram_size + virtio_size)) {
71e47088	407	DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
d5a43964 AG	408	(uint64_t)aaddr, (uint64_t)ram_size);
	409	trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
	410	return 1;
	411	}
10c339a0	412
71e47088	413	DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
d5a43964 AG	414	(uint64_t)vaddr, (uint64_t)raddr, prot);
d5a43964 AG	415
71e47088	416	tlb_set_page(env, orig_vaddr, raddr, prot,
d4c430a8	417	mmu_idx, TARGET_PAGE_SIZE);
d5a43964	418
d4c430a8	419	return 0;
10c339a0	420	}
d5a43964	421
a8170e5e	422	hwaddr cpu_get_phys_page_debug(CPUS390XState *env,
71e47088	423	target_ulong vaddr)
d5a43964 AG	424	{
	425	target_ulong raddr;
	426	int prot = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
	427	int old_exc = env->exception_index;
	428	uint64_t asc = env->psw.mask & PSW_MASK_ASC;
	429
	430	/* 31-Bit mode */
	431	if (!(env->psw.mask & PSW_MASK_64)) {
	432	vaddr &= 0x7fffffff;
	433	}
	434
	435	mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
	436	env->exception_index = old_exc;
	437
	438	return raddr;
	439	}
	440
a4e3ad19	441	void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
d5a43964 AG	442	{
d5a43964 AG	443	if (mask & PSW_MASK_WAIT) {
d5a43964	444	if (!(mask & (PSW_MASK_IO \| PSW_MASK_EXT \| PSW_MASK_MCHECK))) {
ef81522b AG	445	if (s390_del_running_cpu(env) == 0) {
	446	#ifndef CONFIG_USER_ONLY
	447	qemu_system_shutdown_request();
	448	#endif
	449	}
d5a43964	450	}
ef81522b AG	451	env->halted = 1;
ef81522b AG	452	env->exception_index = EXCP_HLT;
d5a43964 AG	453	}
	454
	455	env->psw.addr = addr;
	456	env->psw.mask = mask;
	457	env->cc_op = (mask >> 13) & 3;
	458	}
	459
a4e3ad19	460	static uint64_t get_psw_mask(CPUS390XState *env)
d5a43964 AG	461	{
	462	uint64_t r = env->psw.mask;
	463
	464	env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
	465
	466	r &= ~(3ULL << 13);
	467	assert(!(env->cc_op & ~3));
	468	r \|= env->cc_op << 13;
	469
	470	return r;
	471	}
	472
a4e3ad19	473	static void do_svc_interrupt(CPUS390XState *env)
d5a43964 AG	474	{
	475	uint64_t mask, addr;
	476	LowCore *lowcore;
a8170e5e	477	hwaddr len = TARGET_PAGE_SIZE;
d5a43964 AG	478
	479	lowcore = cpu_physical_memory_map(env->psa, &len, 1);
	480
	481	lowcore->svc_code = cpu_to_be16(env->int_svc_code);
	482	lowcore->svc_ilc = cpu_to_be16(env->int_svc_ilc);
	483	lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
	484	lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + (env->int_svc_ilc));
	485	mask = be64_to_cpu(lowcore->svc_new_psw.mask);
	486	addr = be64_to_cpu(lowcore->svc_new_psw.addr);
	487
	488	cpu_physical_memory_unmap(lowcore, len, 1, len);
	489
	490	load_psw(env, mask, addr);
	491	}
	492
a4e3ad19	493	static void do_program_interrupt(CPUS390XState *env)
d5a43964 AG	494	{
	495	uint64_t mask, addr;
	496	LowCore *lowcore;
a8170e5e	497	hwaddr len = TARGET_PAGE_SIZE;
d5a43964 AG	498	int ilc = env->int_pgm_ilc;
	499
	500	switch (ilc) {
	501	case ILC_LATER:
19b0516f	502	ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
d5a43964 AG	503	break;
d5a43964 AG	504	case ILC_LATER_INC:
19b0516f	505	ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
d5a43964 AG	506	env->psw.addr += ilc * 2;
	507	break;
	508	case ILC_LATER_INC_2:
19b0516f	509	ilc = get_ilc(cpu_ldub_code(env, env->psw.addr)) * 2;
d5a43964 AG	510	env->psw.addr += ilc;
	511	break;
	512	}
	513
0d404541 RH	514	qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilc=%d\n",
0d404541 RH	515	__func__, env->int_pgm_code, ilc);
d5a43964 AG	516
	517	lowcore = cpu_physical_memory_map(env->psa, &len, 1);
	518
	519	lowcore->pgm_ilc = cpu_to_be16(ilc);
	520	lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
	521	lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
	522	lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
	523	mask = be64_to_cpu(lowcore->program_new_psw.mask);
	524	addr = be64_to_cpu(lowcore->program_new_psw.addr);
	525
	526	cpu_physical_memory_unmap(lowcore, len, 1, len);
	527
71e47088	528	DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
d5a43964 AG	529	env->int_pgm_code, ilc, env->psw.mask,
	530	env->psw.addr);
	531
	532	load_psw(env, mask, addr);
	533	}
	534
	535	#define VIRTIO_SUBCODE_64 0x0D00
	536
a4e3ad19	537	static void do_ext_interrupt(CPUS390XState *env)
d5a43964 AG	538	{
	539	uint64_t mask, addr;
	540	LowCore *lowcore;
a8170e5e	541	hwaddr len = TARGET_PAGE_SIZE;
d5a43964 AG	542	ExtQueue *q;
	543
	544	if (!(env->psw.mask & PSW_MASK_EXT)) {
	545	cpu_abort(env, "Ext int w/o ext mask\n");
	546	}
	547
	548	if (env->ext_index < 0 \|\| env->ext_index > MAX_EXT_QUEUE) {
	549	cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
	550	}
	551
	552	q = &env->ext_queue[env->ext_index];
	553	lowcore = cpu_physical_memory_map(env->psa, &len, 1);
	554
	555	lowcore->ext_int_code = cpu_to_be16(q->code);
	556	lowcore->ext_params = cpu_to_be32(q->param);
	557	lowcore->ext_params2 = cpu_to_be64(q->param64);
	558	lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
	559	lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
	560	lowcore->cpu_addr = cpu_to_be16(env->cpu_num \| VIRTIO_SUBCODE_64);
	561	mask = be64_to_cpu(lowcore->external_new_psw.mask);
	562	addr = be64_to_cpu(lowcore->external_new_psw.addr);
	563
	564	cpu_physical_memory_unmap(lowcore, len, 1, len);
	565
	566	env->ext_index--;
	567	if (env->ext_index == -1) {
	568	env->pending_int &= ~INTERRUPT_EXT;
	569	}
	570
71e47088	571	DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
d5a43964 AG	572	env->psw.mask, env->psw.addr);
	573
	574	load_psw(env, mask, addr);
	575	}
3110e292	576
71e47088	577	void do_interrupt(CPUS390XState *env)
3110e292	578	{
0d404541 RH	579	qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
0d404541 RH	580	__func__, env->exception_index, env->psw.addr);
d5a43964	581
ef81522b	582	s390_add_running_cpu(env);
d5a43964 AG	583	/* handle external interrupts */
	584	if ((env->psw.mask & PSW_MASK_EXT) &&
	585	env->exception_index == -1) {
	586	if (env->pending_int & INTERRUPT_EXT) {
	587	/* code is already in env */
	588	env->exception_index = EXCP_EXT;
	589	} else if (env->pending_int & INTERRUPT_TOD) {
	590	cpu_inject_ext(env, 0x1004, 0, 0);
	591	env->exception_index = EXCP_EXT;
	592	env->pending_int &= ~INTERRUPT_EXT;
	593	env->pending_int &= ~INTERRUPT_TOD;
	594	} else if (env->pending_int & INTERRUPT_CPUTIMER) {
	595	cpu_inject_ext(env, 0x1005, 0, 0);
	596	env->exception_index = EXCP_EXT;
	597	env->pending_int &= ~INTERRUPT_EXT;
	598	env->pending_int &= ~INTERRUPT_TOD;
	599	}
	600	}
	601
	602	switch (env->exception_index) {
	603	case EXCP_PGM:
	604	do_program_interrupt(env);
	605	break;
	606	case EXCP_SVC:
	607	do_svc_interrupt(env);
	608	break;
	609	case EXCP_EXT:
	610	do_ext_interrupt(env);
	611	break;
	612	}
	613	env->exception_index = -1;
	614
	615	if (!env->pending_int) {
	616	env->interrupt_request &= ~CPU_INTERRUPT_HARD;
	617	}
3110e292	618	}
d5a43964 AG	619
d5a43964 AG	620	#endif /* CONFIG_USER_ONLY */