[qemu.git] / target-s390x / helper.c

/*
 *  S/390 helpers
 *
 *  Copyright (c) 2009 Ulrich Hecht
 *  Copyright (c) 2011 Alexander Graf
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "gdbstub.h"
#include "qemu-timer.h"
#ifndef CONFIG_USER_ONLY
#include "sysemu.h"
#endif

//#define DEBUG_S390
//#define DEBUG_S390_PTE
//#define DEBUG_S390_STDOUT

#ifdef DEBUG_S390
#ifdef DEBUG_S390_STDOUT
#define DPRINTF(fmt, ...) \
    do { fprintf(stderr, fmt, ## __VA_ARGS__); \
         qemu_log(fmt, ##__VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) \
    do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
#endif
#else
#define DPRINTF(fmt, ...) \
    do { } while (0)
#endif

#ifdef DEBUG_S390_PTE
#define PTE_DPRINTF DPRINTF
#else
#define PTE_DPRINTF(fmt, ...) \
    do { } while (0)
#endif

#ifndef CONFIG_USER_ONLY
void s390x_tod_timer(void *opaque)
{
    S390CPU *cpu = opaque;
    CPUS390XState *env = &cpu->env;

    env->pending_int |= INTERRUPT_TOD;
    cpu_interrupt(env, CPU_INTERRUPT_HARD);
}

void s390x_cpu_timer(void *opaque)
{
    S390CPU *cpu = opaque;
    CPUS390XState *env = &cpu->env;

    env->pending_int |= INTERRUPT_CPUTIMER;
    cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
#endif

CPUS390XState *cpu_s390x_init(const char *cpu_model)
{
    S390CPU *cpu;
    CPUS390XState *env;
    static int inited = 0;

    cpu = S390_CPU(object_new(TYPE_S390_CPU));
    env = &cpu->env;

    if (tcg_enabled() && !inited) {
        inited = 1;
        s390x_translate_init();
    }

    env->cpu_model_str = cpu_model;
    qemu_init_vcpu(env);
    return env;
}

#if defined(CONFIG_USER_ONLY)

void do_interrupt (CPUS390XState *env)
{
    env->exception_index = -1;
}

int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
                                int mmu_idx)
{
    /* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
            __FUNCTION__, address, rw, mmu_idx); */
    env->exception_index = EXCP_ADDR;
    env->__excp_addr = address; /* FIXME: find out how this works on a real machine */
    return 1;
}

#endif /* CONFIG_USER_ONLY */

void cpu_state_reset(CPUS390XState *env)
{
    cpu_reset(ENV_GET_CPU(env));
}

#ifndef CONFIG_USER_ONLY

/* Ensure to exit the TB after this call! */
static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc)
{
    env->exception_index = EXCP_PGM;
    env->int_pgm_code = code;
    env->int_pgm_ilc = ilc;
}

static int trans_bits(CPUS390XState *env, uint64_t mode)
{
    int bits = 0;

    switch (mode) {
    case PSW_ASC_PRIMARY:
        bits = 1;
        break;
    case PSW_ASC_SECONDARY:
        bits = 2;
        break;
    case PSW_ASC_HOME:
        bits = 3;
        break;
    default:
        cpu_abort(env, "unknown asc mode\n");
        break;
    }

    return bits;
}

static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t mode)
{
    int ilc = ILC_LATER_INC_2;
    int bits = trans_bits(env, mode) | 4;

    DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);

    stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
    trigger_pgm_exception(env, PGM_PROTECTION, ilc);
}

static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type,
                               uint64_t asc, int rw)
{
    int ilc = ILC_LATER;
    int bits = trans_bits(env, asc);

    if (rw == 2) {
        /* code has is undefined ilc */
        ilc = 2;
    }

    DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);

    stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
    trigger_pgm_exception(env, type, ilc);
}

static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
                              uint64_t asce, int level, target_ulong *raddr,
                              int *flags, int rw)
{
    uint64_t offs = 0;
    uint64_t origin;
    uint64_t new_asce;

    PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __FUNCTION__, asce);

    if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
        ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
        /* XXX different regions have different faults */
        DPRINTF("%s: invalid region\n", __FUNCTION__);
        trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
        return -1;
    }

    if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
        trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
        return -1;
    }

    if (asce & _ASCE_REAL_SPACE) {
        /* direct mapping */

        *raddr = vaddr;
        return 0;
    }

    origin = asce & _ASCE_ORIGIN;

    switch (level) {
    case _ASCE_TYPE_REGION1 + 4:
        offs = (vaddr >> 50) & 0x3ff8;
        break;
    case _ASCE_TYPE_REGION1:
        offs = (vaddr >> 39) & 0x3ff8;
        break;
    case _ASCE_TYPE_REGION2:
        offs = (vaddr >> 28) & 0x3ff8;
        break;
    case _ASCE_TYPE_REGION3:
        offs = (vaddr >> 17) & 0x3ff8;
        break;
    case _ASCE_TYPE_SEGMENT:
        offs = (vaddr >> 9) & 0x07f8;
        origin = asce & _SEGMENT_ENTRY_ORIGIN;
        break;
    }

    /* XXX region protection flags */
    /* *flags &= ~PAGE_WRITE */

    new_asce = ldq_phys(origin + offs);
    PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
                __FUNCTION__, origin, offs, new_asce);

    if (level != _ASCE_TYPE_SEGMENT) {
        /* yet another region */
        return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
                                  flags, rw);
    }

    /* PTE */
    if (new_asce & _PAGE_INVALID) {
        DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __FUNCTION__, new_asce);
        trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
        return -1;
    }

    if (new_asce & _PAGE_RO) {
        *flags &= ~PAGE_WRITE;
    }

    *raddr = new_asce & _ASCE_ORIGIN;

    PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __FUNCTION__, new_asce);

    return 0;
}

static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
                             target_ulong *raddr, int *flags, int rw)
{
    uint64_t asce = 0;
    int level, new_level;
    int r;

    switch (asc) {
    case PSW_ASC_PRIMARY:
        PTE_DPRINTF("%s: asc=primary\n", __FUNCTION__);
        asce = env->cregs[1];
        break;
    case PSW_ASC_SECONDARY:
        PTE_DPRINTF("%s: asc=secondary\n", __FUNCTION__);
        asce = env->cregs[7];
        break;
    case PSW_ASC_HOME:
        PTE_DPRINTF("%s: asc=home\n", __FUNCTION__);
        asce = env->cregs[13];
        break;
    }

    switch (asce & _ASCE_TYPE_MASK) {
    case _ASCE_TYPE_REGION1:
        break;
    case _ASCE_TYPE_REGION2:
        if (vaddr & 0xffe0000000000000ULL) {
            DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
                        " 0xffe0000000000000ULL\n", __FUNCTION__,
                        vaddr);
            trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
            return -1;
        }
        break;
    case _ASCE_TYPE_REGION3:
        if (vaddr & 0xfffffc0000000000ULL) {
            DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
                        " 0xfffffc0000000000ULL\n", __FUNCTION__,
                        vaddr);
            trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
            return -1;
        }
        break;
    case _ASCE_TYPE_SEGMENT:
        if (vaddr & 0xffffffff80000000ULL) {
            DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
                        " 0xffffffff80000000ULL\n", __FUNCTION__,
                        vaddr);
            trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
            return -1;
        }
        break;
    }

    /* fake level above current */
    level = asce & _ASCE_TYPE_MASK;
    new_level = level + 4;
    asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);

    r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);

    if ((rw == 1) && !(*flags & PAGE_WRITE)) {
        trigger_prot_fault(env, vaddr, asc);
        return -1;
    }

    return r;
}

int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
                  target_ulong *raddr, int *flags)
{
    int r = -1;
    uint8_t *sk;

    *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
    vaddr &= TARGET_PAGE_MASK;

    if (!(env->psw.mask & PSW_MASK_DAT)) {
        *raddr = vaddr;
        r = 0;
        goto out;
    }

    switch (asc) {
    case PSW_ASC_PRIMARY:
    case PSW_ASC_HOME:
        r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
        break;
    case PSW_ASC_SECONDARY:
        /*
         * Instruction: Primary
         * Data: Secondary
         */
        if (rw == 2) {
            r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
                                  rw);
            *flags &= ~(PAGE_READ | PAGE_WRITE);
        } else {
            r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
                                  rw);
            *flags &= ~(PAGE_EXEC);
        }
        break;
    case PSW_ASC_ACCREG:
    default:
        hw_error("guest switched to unknown asc mode\n");
        break;
    }

out:
    /* Convert real address -> absolute address */
    if (*raddr < 0x2000) {
        *raddr = *raddr + env->psa;
    }

    if (*raddr <= ram_size) {
        sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
        if (*flags & PAGE_READ) {
            *sk |= SK_R;
        }

        if (*flags & PAGE_WRITE) {
            *sk |= SK_C;
        }
    }

    return r;
}

int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
                                int mmu_idx)
{
    uint64_t asc = env->psw.mask & PSW_MASK_ASC;
    target_ulong vaddr, raddr;
    int prot;

    DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
            __FUNCTION__, _vaddr, rw, mmu_idx);

    _vaddr &= TARGET_PAGE_MASK;
    vaddr = _vaddr;

    /* 31-Bit mode */
    if (!(env->psw.mask & PSW_MASK_64)) {
        vaddr &= 0x7fffffff;
    }

    if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
        /* Translation ended in exception */
        return 1;
    }

    /* check out of RAM access */
    if (raddr > (ram_size + virtio_size)) {
        DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __FUNCTION__,
                (uint64_t)aaddr, (uint64_t)ram_size);
        trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
        return 1;
    }

    DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __FUNCTION__,
            (uint64_t)vaddr, (uint64_t)raddr, prot);

    tlb_set_page(env, _vaddr, raddr, prot,
                 mmu_idx, TARGET_PAGE_SIZE);

    return 0;
}

target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env, target_ulong vaddr)
{
    target_ulong raddr;
    int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
    int old_exc = env->exception_index;
    uint64_t asc = env->psw.mask & PSW_MASK_ASC;

    /* 31-Bit mode */
    if (!(env->psw.mask & PSW_MASK_64)) {
        vaddr &= 0x7fffffff;
    }

    mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
    env->exception_index = old_exc;

    return raddr;
}

void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
{
    if (mask & PSW_MASK_WAIT) {
        if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
            if (s390_del_running_cpu(env) == 0) {
#ifndef CONFIG_USER_ONLY
                qemu_system_shutdown_request();
#endif
            }
        }
        env->halted = 1;
        env->exception_index = EXCP_HLT;
    }

    env->psw.addr = addr;
    env->psw.mask = mask;
    env->cc_op = (mask >> 13) & 3;
}

static uint64_t get_psw_mask(CPUS390XState *env)
{
    uint64_t r = env->psw.mask;

    env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);

    r &= ~(3ULL << 13);
    assert(!(env->cc_op & ~3));
    r |= env->cc_op << 13;

    return r;
}

static void do_svc_interrupt(CPUS390XState *env)
{
    uint64_t mask, addr;
    LowCore *lowcore;
    target_phys_addr_t len = TARGET_PAGE_SIZE;

    lowcore = cpu_physical_memory_map(env->psa, &len, 1);

    lowcore->svc_code = cpu_to_be16(env->int_svc_code);
    lowcore->svc_ilc = cpu_to_be16(env->int_svc_ilc);
    lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
    lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + (env->int_svc_ilc));
    mask = be64_to_cpu(lowcore->svc_new_psw.mask);
    addr = be64_to_cpu(lowcore->svc_new_psw.addr);

    cpu_physical_memory_unmap(lowcore, len, 1, len);

    load_psw(env, mask, addr);
}

static void do_program_interrupt(CPUS390XState *env)
{
    uint64_t mask, addr;
    LowCore *lowcore;
    target_phys_addr_t len = TARGET_PAGE_SIZE;
    int ilc = env->int_pgm_ilc;

    switch (ilc) {
    case ILC_LATER:
        ilc = get_ilc(ldub_code(env->psw.addr));
        break;
    case ILC_LATER_INC:
        ilc = get_ilc(ldub_code(env->psw.addr));
        env->psw.addr += ilc * 2;
        break;
    case ILC_LATER_INC_2:
        ilc = get_ilc(ldub_code(env->psw.addr)) * 2;
        env->psw.addr += ilc;
        break;
    }

    qemu_log("%s: code=0x%x ilc=%d\n", __FUNCTION__, env->int_pgm_code, ilc);

    lowcore = cpu_physical_memory_map(env->psa, &len, 1);

    lowcore->pgm_ilc = cpu_to_be16(ilc);
    lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
    lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
    lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
    mask = be64_to_cpu(lowcore->program_new_psw.mask);
    addr = be64_to_cpu(lowcore->program_new_psw.addr);

    cpu_physical_memory_unmap(lowcore, len, 1, len);

    DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
            env->int_pgm_code, ilc, env->psw.mask,
            env->psw.addr);

    load_psw(env, mask, addr);
}

#define VIRTIO_SUBCODE_64 0x0D00

static void do_ext_interrupt(CPUS390XState *env)
{
    uint64_t mask, addr;
    LowCore *lowcore;
    target_phys_addr_t len = TARGET_PAGE_SIZE;
    ExtQueue *q;

    if (!(env->psw.mask & PSW_MASK_EXT)) {
        cpu_abort(env, "Ext int w/o ext mask\n");
    }

    if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
        cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
    }

    q = &env->ext_queue[env->ext_index];
    lowcore = cpu_physical_memory_map(env->psa, &len, 1);

    lowcore->ext_int_code = cpu_to_be16(q->code);
    lowcore->ext_params = cpu_to_be32(q->param);
    lowcore->ext_params2 = cpu_to_be64(q->param64);
    lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
    lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
    lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
    mask = be64_to_cpu(lowcore->external_new_psw.mask);
    addr = be64_to_cpu(lowcore->external_new_psw.addr);

    cpu_physical_memory_unmap(lowcore, len, 1, len);

    env->ext_index--;
    if (env->ext_index == -1) {
        env->pending_int &= ~INTERRUPT_EXT;
    }

    DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
            env->psw.mask, env->psw.addr);

    load_psw(env, mask, addr);
}

void do_interrupt (CPUS390XState *env)
{
    qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index,
             env->psw.addr);

    s390_add_running_cpu(env);
    /* handle external interrupts */
    if ((env->psw.mask & PSW_MASK_EXT) &&
        env->exception_index == -1) {
        if (env->pending_int & INTERRUPT_EXT) {
            /* code is already in env */
            env->exception_index = EXCP_EXT;
        } else if (env->pending_int & INTERRUPT_TOD) {
            cpu_inject_ext(env, 0x1004, 0, 0);
            env->exception_index = EXCP_EXT;
            env->pending_int &= ~INTERRUPT_EXT;
            env->pending_int &= ~INTERRUPT_TOD;
        } else if (env->pending_int & INTERRUPT_CPUTIMER) {
            cpu_inject_ext(env, 0x1005, 0, 0);
            env->exception_index = EXCP_EXT;
            env->pending_int &= ~INTERRUPT_EXT;
            env->pending_int &= ~INTERRUPT_TOD;
        }
    }

    switch (env->exception_index) {
    case EXCP_PGM:
        do_program_interrupt(env);
        break;
    case EXCP_SVC:
        do_svc_interrupt(env);
        break;
    case EXCP_EXT:
        do_ext_interrupt(env);
        break;
    }
    env->exception_index = -1;

    if (!env->pending_int) {
        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
    }
}

#endif /* CONFIG_USER_ONLY */
Commit	Line	Data
10ec5117 AG	1	/*
	2	* S/390 helpers
	3	*
	4	* Copyright (c) 2009 Ulrich Hecht
d5a43964	5	* Copyright (c) 2011 Alexander Graf
10ec5117 AG	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
70539e18	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117 AG	19	*/
10ec5117 AG	20
10ec5117	21	#include "cpu.h"
10ec5117	22	#include "gdbstub.h"
d5a43964	23	#include "qemu-timer.h"
ef81522b AG	24	#ifndef CONFIG_USER_ONLY
	25	#include "sysemu.h"
	26	#endif
10ec5117	27
d5a43964 AG	28	//#define DEBUG_S390
	29	//#define DEBUG_S390_PTE
	30	//#define DEBUG_S390_STDOUT
	31
	32	#ifdef DEBUG_S390
	33	#ifdef DEBUG_S390_STDOUT
	34	#define DPRINTF(fmt, ...) \
	35	do { fprintf(stderr, fmt, ## __VA_ARGS__); \
	36	qemu_log(fmt, ##__VA_ARGS__); } while (0)
	37	#else
	38	#define DPRINTF(fmt, ...) \
	39	do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
	40	#endif
	41	#else
	42	#define DPRINTF(fmt, ...) \
	43	do { } while (0)
	44	#endif
	45
	46	#ifdef DEBUG_S390_PTE
	47	#define PTE_DPRINTF DPRINTF
	48	#else
	49	#define PTE_DPRINTF(fmt, ...) \
	50	do { } while (0)
	51	#endif
	52
	53	#ifndef CONFIG_USER_ONLY
8f22e0df	54	void s390x_tod_timer(void *opaque)
d5a43964	55	{
b8ba6799 AF	56	S390CPU *cpu = opaque;
b8ba6799 AF	57	CPUS390XState *env = &cpu->env;
d5a43964 AG	58
	59	env->pending_int \|= INTERRUPT_TOD;
	60	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	61	}
	62
8f22e0df	63	void s390x_cpu_timer(void *opaque)
d5a43964	64	{
b8ba6799 AF	65	S390CPU *cpu = opaque;
b8ba6799 AF	66	CPUS390XState *env = &cpu->env;
d5a43964 AG	67
	68	env->pending_int \|= INTERRUPT_CPUTIMER;
	69	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	70	}
	71	#endif
10c339a0	72
10ec5117 AG	73	CPUS390XState cpu_s390x_init(const char cpu_model)
10ec5117 AG	74	{
29e4bcb2	75	S390CPU *cpu;
10ec5117 AG	76	CPUS390XState *env;
	77	static int inited = 0;
	78
29e4bcb2 AF	79	cpu = S390_CPU(object_new(TYPE_S390_CPU));
29e4bcb2 AF	80	env = &cpu->env;
8f22e0df	81
d5ab9713	82	if (tcg_enabled() && !inited) {
10ec5117	83	inited = 1;
d5a43964	84	s390x_translate_init();
10ec5117 AG	85	}
	86
	87	env->cpu_model_str = cpu_model;
10ec5117 AG	88	qemu_init_vcpu(env);
	89	return env;
	90	}
	91
d5a43964 AG	92	#if defined(CONFIG_USER_ONLY)
d5a43964 AG	93
a4e3ad19	94	void do_interrupt (CPUS390XState *env)
d5a43964 AG	95	{
	96	env->exception_index = -1;
	97	}
	98
a4e3ad19	99	int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
97b348e7	100	int mmu_idx)
d5a43964	101	{
97b348e7 BS	102	/* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
97b348e7 BS	103	__FUNCTION__, address, rw, mmu_idx); */
d5a43964 AG	104	env->exception_index = EXCP_ADDR;
	105	env->__excp_addr = address; /* FIXME: find out how this works on a real machine */
	106	return 1;
	107	}
	108
	109	#endif /* CONFIG_USER_ONLY */
	110
1bba0dc9	111	void cpu_state_reset(CPUS390XState *env)
10ec5117	112	{
1ac1a749	113	cpu_reset(ENV_GET_CPU(env));
10ec5117	114	}
10c339a0	115
d5a43964 AG	116	#ifndef CONFIG_USER_ONLY
	117
	118	/* Ensure to exit the TB after this call! */
a4e3ad19	119	static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc)
d5a43964 AG	120	{
	121	env->exception_index = EXCP_PGM;
	122	env->int_pgm_code = code;
	123	env->int_pgm_ilc = ilc;
	124	}
	125
a4e3ad19	126	static int trans_bits(CPUS390XState *env, uint64_t mode)
d5a43964 AG	127	{
	128	int bits = 0;
	129
	130	switch (mode) {
	131	case PSW_ASC_PRIMARY:
	132	bits = 1;
	133	break;
	134	case PSW_ASC_SECONDARY:
	135	bits = 2;
	136	break;
	137	case PSW_ASC_HOME:
	138	bits = 3;
	139	break;
	140	default:
	141	cpu_abort(env, "unknown asc mode\n");
	142	break;
	143	}
	144
	145	return bits;
	146	}
	147
a4e3ad19	148	static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t mode)
d5a43964 AG	149	{
	150	int ilc = ILC_LATER_INC_2;
	151	int bits = trans_bits(env, mode) \| 4;
	152
	153	DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
	154
	155	stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr \| bits);
	156	trigger_pgm_exception(env, PGM_PROTECTION, ilc);
	157	}
	158
a4e3ad19	159	static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type,
d5a43964 AG	160	uint64_t asc, int rw)
	161	{
	162	int ilc = ILC_LATER;
	163	int bits = trans_bits(env, asc);
	164
	165	if (rw == 2) {
	166	/* code has is undefined ilc */
	167	ilc = 2;
	168	}
	169
	170	DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
	171
	172	stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr \| bits);
	173	trigger_pgm_exception(env, type, ilc);
	174	}
	175
a4e3ad19	176	static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
d5a43964 AG	177	uint64_t asce, int level, target_ulong *raddr,
d5a43964 AG	178	int *flags, int rw)
c92114b1	179	{
d5a43964 AG	180	uint64_t offs = 0;
	181	uint64_t origin;
	182	uint64_t new_asce;
	183
	184	PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __FUNCTION__, asce);
	185
	186	if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) \|\|
	187	((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
	188	/* XXX different regions have different faults */
	189	DPRINTF("%s: invalid region\n", __FUNCTION__);
	190	trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
	191	return -1;
	192	}
	193
	194	if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
	195	trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
	196	return -1;
	197	}
	198
	199	if (asce & _ASCE_REAL_SPACE) {
	200	/* direct mapping */
	201
	202	*raddr = vaddr;
	203	return 0;
	204	}
	205
	206	origin = asce & _ASCE_ORIGIN;
	207
	208	switch (level) {
	209	case _ASCE_TYPE_REGION1 + 4:
	210	offs = (vaddr >> 50) & 0x3ff8;
	211	break;
	212	case _ASCE_TYPE_REGION1:
	213	offs = (vaddr >> 39) & 0x3ff8;
	214	break;
	215	case _ASCE_TYPE_REGION2:
	216	offs = (vaddr >> 28) & 0x3ff8;
	217	break;
	218	case _ASCE_TYPE_REGION3:
	219	offs = (vaddr >> 17) & 0x3ff8;
	220	break;
	221	case _ASCE_TYPE_SEGMENT:
	222	offs = (vaddr >> 9) & 0x07f8;
	223	origin = asce & _SEGMENT_ENTRY_ORIGIN;
	224	break;
	225	}
	226
	227	/* XXX region protection flags */
	228	/* flags &= ~PAGE_WRITE /
	229
	230	new_asce = ldq_phys(origin + offs);
	231	PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
	232	__FUNCTION__, origin, offs, new_asce);
	233
	234	if (level != _ASCE_TYPE_SEGMENT) {
	235	/* yet another region */
	236	return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
	237	flags, rw);
	238	}
	239
	240	/* PTE */
	241	if (new_asce & _PAGE_INVALID) {
	242	DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __FUNCTION__, new_asce);
	243	trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
244	return -1;
245	}
246
247	if (new_asce & _PAGE_RO) {
248	*flags &= ~PAGE_WRITE;
249	}
250
251	*raddr = new_asce & _ASCE_ORIGIN;
252
253	PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __FUNCTION__, new_asce);
254
c92114b1 AG	255	return 0;
	256	}
	257
a4e3ad19	258	static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
d5a43964 AG	259	target_ulong raddr, int flags, int rw)
	260	{
	261	uint64_t asce = 0;
	262	int level, new_level;
	263	int r;
10c339a0	264
d5a43964 AG	265	switch (asc) {
	266	case PSW_ASC_PRIMARY:
	267	PTE_DPRINTF("%s: asc=primary\n", __FUNCTION__);
	268	asce = env->cregs[1];
	269	break;
	270	case PSW_ASC_SECONDARY:
	271	PTE_DPRINTF("%s: asc=secondary\n", __FUNCTION__);
	272	asce = env->cregs[7];
	273	break;
	274	case PSW_ASC_HOME:
	275	PTE_DPRINTF("%s: asc=home\n", __FUNCTION__);
	276	asce = env->cregs[13];
	277	break;
	278	}
	279
	280	switch (asce & _ASCE_TYPE_MASK) {
	281	case _ASCE_TYPE_REGION1:
	282	break;
	283	case _ASCE_TYPE_REGION2:
	284	if (vaddr & 0xffe0000000000000ULL) {
	285	DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
	286	" 0xffe0000000000000ULL\n", __FUNCTION__,
	287	vaddr);
	288	trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
	289	return -1;
	290	}
	291	break;
	292	case _ASCE_TYPE_REGION3:
	293	if (vaddr & 0xfffffc0000000000ULL) {
	294	DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
	295	" 0xfffffc0000000000ULL\n", __FUNCTION__,
	296	vaddr);
	297	trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
	298	return -1;
	299	}
	300	break;
	301	case _ASCE_TYPE_SEGMENT:
	302	if (vaddr & 0xffffffff80000000ULL) {
	303	DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
	304	" 0xffffffff80000000ULL\n", __FUNCTION__,
	305	vaddr);
	306	trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
	307	return -1;
	308	}
	309	break;
	310	}
	311
	312	/* fake level above current */
	313	level = asce & _ASCE_TYPE_MASK;
	314	new_level = level + 4;
	315	asce = (asce & ~_ASCE_TYPE_MASK) \| (new_level & _ASCE_TYPE_MASK);
	316
	317	r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
	318
	319	if ((rw == 1) && !(*flags & PAGE_WRITE)) {
	320	trigger_prot_fault(env, vaddr, asc);
	321	return -1;
	322	}
	323
	324	return r;
	325	}
	326
a4e3ad19	327	int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
d5a43964 AG	328	target_ulong raddr, int flags)
	329	{
	330	int r = -1;
b9959138	331	uint8_t *sk;
d5a43964 AG	332
	333	*flags = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
	334	vaddr &= TARGET_PAGE_MASK;
	335
	336	if (!(env->psw.mask & PSW_MASK_DAT)) {
	337	*raddr = vaddr;
	338	r = 0;
	339	goto out;
	340	}
	341
	342	switch (asc) {
	343	case PSW_ASC_PRIMARY:
	344	case PSW_ASC_HOME:
	345	r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
	346	break;
	347	case PSW_ASC_SECONDARY:
	348	/*
	349	* Instruction: Primary
	350	* Data: Secondary
	351	*/
	352	if (rw == 2) {
	353	r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
	354	rw);
	355	*flags &= ~(PAGE_READ \| PAGE_WRITE);
	356	} else {
	357	r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
	358	rw);
	359	*flags &= ~(PAGE_EXEC);
	360	}
	361	break;
	362	case PSW_ASC_ACCREG:
	363	default:
	364	hw_error("guest switched to unknown asc mode\n");
	365	break;
	366	}
	367
	368	out:
	369	/* Convert real address -> absolute address */
	370	if (*raddr < 0x2000) {
	371	raddr = raddr + env->psa;
	372	}
	373
b9959138 AG	374	if (*raddr <= ram_size) {
	375	sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
	376	if (*flags & PAGE_READ) {
	377	*sk \|= SK_R;
	378	}
	379
	380	if (*flags & PAGE_WRITE) {
	381	*sk \|= SK_C;
	382	}
	383	}
	384
d5a43964 AG	385	return r;
	386	}
	387
a4e3ad19	388	int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
97b348e7	389	int mmu_idx)
10c339a0	390	{
d5a43964 AG	391	uint64_t asc = env->psw.mask & PSW_MASK_ASC;
d5a43964 AG	392	target_ulong vaddr, raddr;
10c339a0 AG	393	int prot;
10c339a0 AG	394
97b348e7 BS	395	DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
97b348e7 BS	396	__FUNCTION__, _vaddr, rw, mmu_idx);
d5a43964 AG	397
	398	_vaddr &= TARGET_PAGE_MASK;
	399	vaddr = _vaddr;
	400
	401	/* 31-Bit mode */
	402	if (!(env->psw.mask & PSW_MASK_64)) {
	403	vaddr &= 0x7fffffff;
	404	}
	405
	406	if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
	407	/* Translation ended in exception */
	408	return 1;
	409	}
10c339a0	410
d5a43964 AG	411	/* check out of RAM access */
	412	if (raddr > (ram_size + virtio_size)) {
	413	DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __FUNCTION__,
	414	(uint64_t)aaddr, (uint64_t)ram_size);
	415	trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
	416	return 1;
	417	}
10c339a0	418
d5a43964 AG	419	DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __FUNCTION__,
	420	(uint64_t)vaddr, (uint64_t)raddr, prot);
	421
	422	tlb_set_page(env, _vaddr, raddr, prot,
d4c430a8	423	mmu_idx, TARGET_PAGE_SIZE);
d5a43964	424
d4c430a8	425	return 0;
10c339a0	426	}
d5a43964	427
a4e3ad19	428	target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env, target_ulong vaddr)
d5a43964 AG	429	{
	430	target_ulong raddr;
	431	int prot = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
	432	int old_exc = env->exception_index;
	433	uint64_t asc = env->psw.mask & PSW_MASK_ASC;
	434
	435	/* 31-Bit mode */
	436	if (!(env->psw.mask & PSW_MASK_64)) {
	437	vaddr &= 0x7fffffff;
	438	}
	439
	440	mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
	441	env->exception_index = old_exc;
	442
	443	return raddr;
	444	}
	445
a4e3ad19	446	void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
d5a43964 AG	447	{
d5a43964 AG	448	if (mask & PSW_MASK_WAIT) {
d5a43964	449	if (!(mask & (PSW_MASK_IO \| PSW_MASK_EXT \| PSW_MASK_MCHECK))) {
ef81522b AG	450	if (s390_del_running_cpu(env) == 0) {
	451	#ifndef CONFIG_USER_ONLY
	452	qemu_system_shutdown_request();
	453	#endif
	454	}
d5a43964	455	}
ef81522b AG	456	env->halted = 1;
ef81522b AG	457	env->exception_index = EXCP_HLT;
d5a43964 AG	458	}
	459
	460	env->psw.addr = addr;
	461	env->psw.mask = mask;
	462	env->cc_op = (mask >> 13) & 3;
	463	}
	464
a4e3ad19	465	static uint64_t get_psw_mask(CPUS390XState *env)
d5a43964 AG	466	{
	467	uint64_t r = env->psw.mask;
	468
	469	env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
	470
	471	r &= ~(3ULL << 13);
	472	assert(!(env->cc_op & ~3));
	473	r \|= env->cc_op << 13;
	474
	475	return r;
	476	}
	477
a4e3ad19	478	static void do_svc_interrupt(CPUS390XState *env)
d5a43964 AG	479	{
	480	uint64_t mask, addr;
	481	LowCore *lowcore;
	482	target_phys_addr_t len = TARGET_PAGE_SIZE;
	483
	484	lowcore = cpu_physical_memory_map(env->psa, &len, 1);
	485
	486	lowcore->svc_code = cpu_to_be16(env->int_svc_code);
	487	lowcore->svc_ilc = cpu_to_be16(env->int_svc_ilc);
	488	lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
	489	lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + (env->int_svc_ilc));
	490	mask = be64_to_cpu(lowcore->svc_new_psw.mask);
	491	addr = be64_to_cpu(lowcore->svc_new_psw.addr);
	492
	493	cpu_physical_memory_unmap(lowcore, len, 1, len);
	494
	495	load_psw(env, mask, addr);
	496	}
	497
a4e3ad19	498	static void do_program_interrupt(CPUS390XState *env)
d5a43964 AG	499	{
	500	uint64_t mask, addr;
	501	LowCore *lowcore;
	502	target_phys_addr_t len = TARGET_PAGE_SIZE;
	503	int ilc = env->int_pgm_ilc;
	504
	505	switch (ilc) {
	506	case ILC_LATER:
	507	ilc = get_ilc(ldub_code(env->psw.addr));
	508	break;
	509	case ILC_LATER_INC:
	510	ilc = get_ilc(ldub_code(env->psw.addr));
	511	env->psw.addr += ilc * 2;
	512	break;
	513	case ILC_LATER_INC_2:
	514	ilc = get_ilc(ldub_code(env->psw.addr)) * 2;
	515	env->psw.addr += ilc;
	516	break;
	517	}
	518
	519	qemu_log("%s: code=0x%x ilc=%d\n", __FUNCTION__, env->int_pgm_code, ilc);
	520
	521	lowcore = cpu_physical_memory_map(env->psa, &len, 1);
	522
	523	lowcore->pgm_ilc = cpu_to_be16(ilc);
	524	lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
	525	lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
	526	lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
	527	mask = be64_to_cpu(lowcore->program_new_psw.mask);
	528	addr = be64_to_cpu(lowcore->program_new_psw.addr);
	529
	530	cpu_physical_memory_unmap(lowcore, len, 1, len);
	531
	532	DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
	533	env->int_pgm_code, ilc, env->psw.mask,
	534	env->psw.addr);
	535
	536	load_psw(env, mask, addr);
	537	}
	538
	539	#define VIRTIO_SUBCODE_64 0x0D00
	540
a4e3ad19	541	static void do_ext_interrupt(CPUS390XState *env)
d5a43964 AG	542	{
	543	uint64_t mask, addr;
	544	LowCore *lowcore;
	545	target_phys_addr_t len = TARGET_PAGE_SIZE;
	546	ExtQueue *q;
	547
	548	if (!(env->psw.mask & PSW_MASK_EXT)) {
	549	cpu_abort(env, "Ext int w/o ext mask\n");
	550	}
	551
	552	if (env->ext_index < 0 \|\| env->ext_index > MAX_EXT_QUEUE) {
	553	cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
	554	}
	555
	556	q = &env->ext_queue[env->ext_index];
	557	lowcore = cpu_physical_memory_map(env->psa, &len, 1);
	558
	559	lowcore->ext_int_code = cpu_to_be16(q->code);
	560	lowcore->ext_params = cpu_to_be32(q->param);
	561	lowcore->ext_params2 = cpu_to_be64(q->param64);
	562	lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
	563	lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
	564	lowcore->cpu_addr = cpu_to_be16(env->cpu_num \| VIRTIO_SUBCODE_64);
	565	mask = be64_to_cpu(lowcore->external_new_psw.mask);
	566	addr = be64_to_cpu(lowcore->external_new_psw.addr);
	567
	568	cpu_physical_memory_unmap(lowcore, len, 1, len);
	569
	570	env->ext_index--;
	571	if (env->ext_index == -1) {
	572	env->pending_int &= ~INTERRUPT_EXT;
	573	}
	574
	575	DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
	576	env->psw.mask, env->psw.addr);
	577
	578	load_psw(env, mask, addr);
	579	}
3110e292	580
a4e3ad19	581	void do_interrupt (CPUS390XState *env)
3110e292	582	{
d5a43964 AG	583	qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index,
	584	env->psw.addr);
	585
ef81522b	586	s390_add_running_cpu(env);
d5a43964 AG	587	/* handle external interrupts */
	588	if ((env->psw.mask & PSW_MASK_EXT) &&
	589	env->exception_index == -1) {
	590	if (env->pending_int & INTERRUPT_EXT) {
	591	/* code is already in env */
	592	env->exception_index = EXCP_EXT;
	593	} else if (env->pending_int & INTERRUPT_TOD) {
	594	cpu_inject_ext(env, 0x1004, 0, 0);
	595	env->exception_index = EXCP_EXT;
	596	env->pending_int &= ~INTERRUPT_EXT;
	597	env->pending_int &= ~INTERRUPT_TOD;
	598	} else if (env->pending_int & INTERRUPT_CPUTIMER) {
	599	cpu_inject_ext(env, 0x1005, 0, 0);
	600	env->exception_index = EXCP_EXT;
	601	env->pending_int &= ~INTERRUPT_EXT;
	602	env->pending_int &= ~INTERRUPT_TOD;
	603	}
	604	}
	605
	606	switch (env->exception_index) {
	607	case EXCP_PGM:
	608	do_program_interrupt(env);
	609	break;
	610	case EXCP_SVC:
	611	do_svc_interrupt(env);
	612	break;
	613	case EXCP_EXT:
	614	do_ext_interrupt(env);
	615	break;
	616	}
	617	env->exception_index = -1;
	618
	619	if (!env->pending_int) {
	620	env->interrupt_request &= ~CPU_INTERRUPT_HARD;
	621	}
3110e292	622	}
d5a43964 AG	623
d5a43964 AG	624	#endif /* CONFIG_USER_ONLY */