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10ec5117 AG |
1 | /* |
2 | * S/390 translation | |
3 | * | |
4 | * Copyright (c) 2009 Ulrich Hecht | |
e023e832 | 5 | * Copyright (c) 2010 Alexander Graf |
10ec5117 AG |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
70539e18 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
10ec5117 | 19 | */ |
e023e832 AG |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | ||
26 | /* #define DEBUG_ILLEGAL_INSTRUCTIONS */ | |
27 | /* #define DEBUG_INLINE_BRANCHES */ | |
28 | #define S390X_DEBUG_DISAS | |
29 | /* #define S390X_DEBUG_DISAS_VERBOSE */ | |
30 | ||
31 | #ifdef S390X_DEBUG_DISAS_VERBOSE | |
32 | # define LOG_DISAS(...) qemu_log(__VA_ARGS__) | |
33 | #else | |
34 | # define LOG_DISAS(...) do { } while (0) | |
35 | #endif | |
10ec5117 AG |
36 | |
37 | #include "cpu.h" | |
38 | #include "exec-all.h" | |
39 | #include "disas.h" | |
40 | #include "tcg-op.h" | |
41 | #include "qemu-log.h" | |
42 | ||
e023e832 AG |
43 | /* global register indexes */ |
44 | static TCGv_ptr cpu_env; | |
45 | ||
46 | #include "gen-icount.h" | |
47 | #include "helpers.h" | |
48 | #define GEN_HELPER 1 | |
49 | #include "helpers.h" | |
50 | ||
51 | typedef struct DisasContext DisasContext; | |
52 | struct DisasContext { | |
53 | uint64_t pc; | |
54 | int is_jmp; | |
55 | enum cc_op cc_op; | |
56 | struct TranslationBlock *tb; | |
57 | }; | |
58 | ||
59 | #define DISAS_EXCP 4 | |
60 | ||
61 | static void gen_op_calc_cc(DisasContext *s); | |
62 | ||
63 | #ifdef DEBUG_INLINE_BRANCHES | |
64 | static uint64_t inline_branch_hit[CC_OP_MAX]; | |
65 | static uint64_t inline_branch_miss[CC_OP_MAX]; | |
66 | #endif | |
67 | ||
68 | static inline void debug_insn(uint64_t insn) | |
69 | { | |
70 | LOG_DISAS("insn: 0x%" PRIx64 "\n", insn); | |
71 | } | |
72 | ||
73 | static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc) | |
74 | { | |
75 | if (!(s->tb->flags & FLAG_MASK_64)) { | |
76 | if (s->tb->flags & FLAG_MASK_32) { | |
77 | return pc | 0x80000000; | |
78 | } | |
79 | } | |
80 | return pc; | |
81 | } | |
82 | ||
9a78eead | 83 | void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, |
10ec5117 AG |
84 | int flags) |
85 | { | |
86 | int i; | |
e023e832 | 87 | |
10ec5117 | 88 | for (i = 0; i < 16; i++) { |
e023e832 | 89 | cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]); |
10ec5117 AG |
90 | if ((i % 4) == 3) { |
91 | cpu_fprintf(f, "\n"); | |
92 | } else { | |
93 | cpu_fprintf(f, " "); | |
94 | } | |
95 | } | |
e023e832 | 96 | |
10ec5117 | 97 | for (i = 0; i < 16; i++) { |
bcec36ea | 98 | cpu_fprintf(f, "F%02d=%016" PRIx64, i, *(uint64_t *)&env->fregs[i]); |
10ec5117 AG |
99 | if ((i % 4) == 3) { |
100 | cpu_fprintf(f, "\n"); | |
101 | } else { | |
102 | cpu_fprintf(f, " "); | |
103 | } | |
104 | } | |
e023e832 AG |
105 | |
106 | cpu_fprintf(f, "\n"); | |
107 | ||
108 | #ifndef CONFIG_USER_ONLY | |
109 | for (i = 0; i < 16; i++) { | |
110 | cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]); | |
111 | if ((i % 4) == 3) { | |
112 | cpu_fprintf(f, "\n"); | |
113 | } else { | |
114 | cpu_fprintf(f, " "); | |
115 | } | |
116 | } | |
117 | #endif | |
118 | ||
119 | cpu_fprintf(f, "\n"); | |
120 | ||
121 | if (env->cc_op > 3) { | |
122 | cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n", | |
123 | env->psw.mask, env->psw.addr, cc_name(env->cc_op)); | |
124 | } else { | |
125 | cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n", | |
126 | env->psw.mask, env->psw.addr, env->cc_op); | |
127 | } | |
128 | ||
129 | #ifdef DEBUG_INLINE_BRANCHES | |
130 | for (i = 0; i < CC_OP_MAX; i++) { | |
131 | cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i), | |
132 | inline_branch_miss[i], inline_branch_hit[i]); | |
133 | } | |
134 | #endif | |
10ec5117 AG |
135 | } |
136 | ||
e023e832 AG |
137 | static TCGv_i64 psw_addr; |
138 | static TCGv_i64 psw_mask; | |
139 | ||
140 | static TCGv_i32 cc_op; | |
141 | static TCGv_i64 cc_src; | |
142 | static TCGv_i64 cc_dst; | |
143 | static TCGv_i64 cc_vr; | |
144 | ||
145 | static char cpu_reg_names[10*3 + 6*4]; | |
146 | static TCGv_i64 regs[16]; | |
147 | ||
148 | static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; | |
149 | ||
d5a43964 AG |
150 | void s390x_translate_init(void) |
151 | { | |
e023e832 AG |
152 | int i; |
153 | size_t cpu_reg_names_size = sizeof(cpu_reg_names); | |
154 | char *p; | |
155 | ||
156 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
157 | psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.addr), | |
158 | "psw_addr"); | |
159 | psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.mask), | |
160 | "psw_mask"); | |
161 | ||
162 | cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op), | |
163 | "cc_op"); | |
164 | cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_src), | |
165 | "cc_src"); | |
166 | cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_dst), | |
167 | "cc_dst"); | |
168 | cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_vr), | |
169 | "cc_vr"); | |
170 | ||
171 | p = cpu_reg_names; | |
172 | for (i = 0; i < 16; i++) { | |
173 | snprintf(p, cpu_reg_names_size, "r%d", i); | |
174 | regs[i] = tcg_global_mem_new(TCG_AREG0, | |
175 | offsetof(CPUState, regs[i]), p); | |
176 | p += (i < 10) ? 3 : 4; | |
177 | cpu_reg_names_size -= (i < 10) ? 3 : 4; | |
178 | } | |
d5a43964 AG |
179 | } |
180 | ||
e023e832 | 181 | static inline TCGv_i64 load_reg(int reg) |
10ec5117 | 182 | { |
e023e832 AG |
183 | TCGv_i64 r = tcg_temp_new_i64(); |
184 | tcg_gen_mov_i64(r, regs[reg]); | |
185 | return r; | |
10ec5117 AG |
186 | } |
187 | ||
e023e832 | 188 | static inline TCGv_i64 load_freg(int reg) |
10ec5117 | 189 | { |
e023e832 AG |
190 | TCGv_i64 r = tcg_temp_new_i64(); |
191 | tcg_gen_ld_i64(r, cpu_env, offsetof(CPUState, fregs[reg].d)); | |
192 | return r; | |
10ec5117 AG |
193 | } |
194 | ||
e023e832 | 195 | static inline TCGv_i32 load_freg32(int reg) |
10ec5117 | 196 | { |
e023e832 AG |
197 | TCGv_i32 r = tcg_temp_new_i32(); |
198 | tcg_gen_ld_i32(r, cpu_env, offsetof(CPUState, fregs[reg].l.upper)); | |
199 | return r; | |
200 | } | |
201 | ||
202 | static inline TCGv_i32 load_reg32(int reg) | |
203 | { | |
204 | TCGv_i32 r = tcg_temp_new_i32(); | |
205 | tcg_gen_trunc_i64_i32(r, regs[reg]); | |
206 | return r; | |
207 | } | |
208 | ||
209 | static inline TCGv_i64 load_reg32_i64(int reg) | |
210 | { | |
211 | TCGv_i64 r = tcg_temp_new_i64(); | |
212 | tcg_gen_ext32s_i64(r, regs[reg]); | |
213 | return r; | |
214 | } | |
215 | ||
216 | static inline void store_reg(int reg, TCGv_i64 v) | |
217 | { | |
218 | tcg_gen_mov_i64(regs[reg], v); | |
219 | } | |
220 | ||
221 | static inline void store_freg(int reg, TCGv_i64 v) | |
222 | { | |
223 | tcg_gen_st_i64(v, cpu_env, offsetof(CPUState, fregs[reg].d)); | |
224 | } | |
225 | ||
226 | static inline void store_reg32(int reg, TCGv_i32 v) | |
227 | { | |
228 | #if HOST_LONG_BITS == 32 | |
229 | tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v); | |
230 | #else | |
231 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
232 | tcg_gen_extu_i32_i64(tmp, v); | |
233 | /* 32 bit register writes keep the upper half */ | |
234 | tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32); | |
235 | tcg_temp_free_i64(tmp); | |
236 | #endif | |
237 | } | |
238 | ||
239 | static inline void store_reg32_i64(int reg, TCGv_i64 v) | |
240 | { | |
241 | /* 32 bit register writes keep the upper half */ | |
242 | #if HOST_LONG_BITS == 32 | |
243 | tcg_gen_mov_i32(TCGV_LOW(regs[reg]), TCGV_LOW(v)); | |
244 | #else | |
245 | tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32); | |
246 | #endif | |
247 | } | |
248 | ||
249 | static inline void store_reg16(int reg, TCGv_i32 v) | |
250 | { | |
251 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
252 | tcg_gen_extu_i32_i64(tmp, v); | |
253 | /* 16 bit register writes keep the upper bytes */ | |
254 | tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 16); | |
255 | tcg_temp_free_i64(tmp); | |
256 | } | |
257 | ||
258 | static inline void store_reg8(int reg, TCGv_i64 v) | |
259 | { | |
260 | /* 8 bit register writes keep the upper bytes */ | |
261 | tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 8); | |
262 | } | |
263 | ||
264 | static inline void store_freg32(int reg, TCGv_i32 v) | |
265 | { | |
266 | tcg_gen_st_i32(v, cpu_env, offsetof(CPUState, fregs[reg].l.upper)); | |
267 | } | |
268 | ||
269 | static inline void update_psw_addr(DisasContext *s) | |
270 | { | |
271 | /* psw.addr */ | |
272 | tcg_gen_movi_i64(psw_addr, s->pc); | |
273 | } | |
274 | ||
275 | static inline void potential_page_fault(DisasContext *s) | |
276 | { | |
277 | #ifndef CONFIG_USER_ONLY | |
278 | update_psw_addr(s); | |
279 | gen_op_calc_cc(s); | |
280 | #endif | |
281 | } | |
282 | ||
283 | static inline uint64_t ld_code2(uint64_t pc) | |
284 | { | |
285 | return (uint64_t)lduw_code(pc); | |
286 | } | |
287 | ||
288 | static inline uint64_t ld_code4(uint64_t pc) | |
289 | { | |
290 | return (uint64_t)ldl_code(pc); | |
291 | } | |
292 | ||
293 | static inline uint64_t ld_code6(uint64_t pc) | |
294 | { | |
295 | uint64_t opc; | |
296 | opc = (uint64_t)lduw_code(pc) << 32; | |
297 | opc |= (uint64_t)(uint32_t)ldl_code(pc+2); | |
298 | return opc; | |
299 | } | |
300 | ||
301 | static inline int get_mem_index(DisasContext *s) | |
302 | { | |
303 | switch (s->tb->flags & FLAG_MASK_ASC) { | |
304 | case PSW_ASC_PRIMARY >> 32: | |
305 | return 0; | |
306 | case PSW_ASC_SECONDARY >> 32: | |
307 | return 1; | |
308 | case PSW_ASC_HOME >> 32: | |
309 | return 2; | |
310 | default: | |
311 | tcg_abort(); | |
312 | break; | |
313 | } | |
314 | } | |
315 | ||
316 | static inline void gen_debug(DisasContext *s) | |
317 | { | |
318 | TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); | |
319 | update_psw_addr(s); | |
320 | gen_op_calc_cc(s); | |
321 | gen_helper_exception(tmp); | |
322 | tcg_temp_free_i32(tmp); | |
323 | s->is_jmp = DISAS_EXCP; | |
324 | } | |
325 | ||
326 | #ifdef CONFIG_USER_ONLY | |
327 | ||
328 | static void gen_illegal_opcode(DisasContext *s, int ilc) | |
329 | { | |
330 | TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC); | |
331 | update_psw_addr(s); | |
332 | gen_op_calc_cc(s); | |
333 | gen_helper_exception(tmp); | |
334 | tcg_temp_free_i32(tmp); | |
335 | s->is_jmp = DISAS_EXCP; | |
336 | } | |
337 | ||
338 | #else /* CONFIG_USER_ONLY */ | |
339 | ||
340 | static void debug_print_inst(DisasContext *s, int ilc) | |
341 | { | |
342 | #ifdef DEBUG_ILLEGAL_INSTRUCTIONS | |
343 | uint64_t inst = 0; | |
344 | ||
345 | switch (ilc & 3) { | |
346 | case 1: | |
347 | inst = ld_code2(s->pc); | |
348 | break; | |
349 | case 2: | |
350 | inst = ld_code4(s->pc); | |
351 | break; | |
352 | case 3: | |
353 | inst = ld_code6(s->pc); | |
354 | break; | |
355 | } | |
356 | ||
357 | fprintf(stderr, "Illegal instruction [%d at %016" PRIx64 "]: 0x%016" | |
358 | PRIx64 "\n", ilc, s->pc, inst); | |
359 | #endif | |
360 | } | |
361 | ||
362 | static void gen_program_exception(DisasContext *s, int ilc, int code) | |
363 | { | |
364 | TCGv_i32 tmp; | |
365 | ||
366 | debug_print_inst(s, ilc); | |
367 | ||
368 | /* remember what pgm exeption this was */ | |
369 | tmp = tcg_const_i32(code); | |
370 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_code)); | |
371 | tcg_temp_free_i32(tmp); | |
372 | ||
373 | tmp = tcg_const_i32(ilc); | |
374 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_ilc)); | |
375 | tcg_temp_free_i32(tmp); | |
376 | ||
377 | /* advance past instruction */ | |
378 | s->pc += (ilc * 2); | |
379 | update_psw_addr(s); | |
380 | ||
381 | /* save off cc */ | |
382 | gen_op_calc_cc(s); | |
383 | ||
384 | /* trigger exception */ | |
385 | tmp = tcg_const_i32(EXCP_PGM); | |
386 | gen_helper_exception(tmp); | |
387 | tcg_temp_free_i32(tmp); | |
388 | ||
389 | /* end TB here */ | |
390 | s->is_jmp = DISAS_EXCP; | |
391 | } | |
392 | ||
393 | ||
394 | static void gen_illegal_opcode(DisasContext *s, int ilc) | |
395 | { | |
396 | gen_program_exception(s, ilc, PGM_SPECIFICATION); | |
397 | } | |
398 | ||
399 | static void gen_privileged_exception(DisasContext *s, int ilc) | |
400 | { | |
401 | gen_program_exception(s, ilc, PGM_PRIVILEGED); | |
402 | } | |
403 | ||
404 | static void check_privileged(DisasContext *s, int ilc) | |
405 | { | |
406 | if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) { | |
407 | gen_privileged_exception(s, ilc); | |
408 | } | |
409 | } | |
410 | ||
411 | #endif /* CONFIG_USER_ONLY */ | |
412 | ||
413 | static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2) | |
414 | { | |
415 | TCGv_i64 tmp; | |
416 | ||
417 | /* 31-bitify the immediate part; register contents are dealt with below */ | |
418 | if (!(s->tb->flags & FLAG_MASK_64)) { | |
419 | d2 &= 0x7fffffffUL; | |
420 | } | |
421 | ||
422 | if (x2) { | |
423 | if (d2) { | |
424 | tmp = tcg_const_i64(d2); | |
425 | tcg_gen_add_i64(tmp, tmp, regs[x2]); | |
426 | } else { | |
427 | tmp = load_reg(x2); | |
428 | } | |
429 | if (b2) { | |
430 | tcg_gen_add_i64(tmp, tmp, regs[b2]); | |
431 | } | |
432 | } else if (b2) { | |
433 | if (d2) { | |
434 | tmp = tcg_const_i64(d2); | |
435 | tcg_gen_add_i64(tmp, tmp, regs[b2]); | |
436 | } else { | |
437 | tmp = load_reg(b2); | |
438 | } | |
439 | } else { | |
440 | tmp = tcg_const_i64(d2); | |
441 | } | |
442 | ||
443 | /* 31-bit mode mask if there are values loaded from registers */ | |
444 | if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) { | |
445 | tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL); | |
446 | } | |
447 | ||
448 | return tmp; | |
449 | } | |
450 | ||
451 | static void gen_op_movi_cc(DisasContext *s, uint32_t val) | |
452 | { | |
453 | s->cc_op = CC_OP_CONST0 + val; | |
454 | } | |
455 | ||
456 | static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst) | |
457 | { | |
458 | tcg_gen_discard_i64(cc_src); | |
459 | tcg_gen_mov_i64(cc_dst, dst); | |
460 | tcg_gen_discard_i64(cc_vr); | |
461 | s->cc_op = op; | |
462 | } | |
463 | ||
464 | static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst) | |
465 | { | |
466 | tcg_gen_discard_i64(cc_src); | |
467 | tcg_gen_extu_i32_i64(cc_dst, dst); | |
468 | tcg_gen_discard_i64(cc_vr); | |
469 | s->cc_op = op; | |
470 | } | |
471 | ||
472 | static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src, | |
473 | TCGv_i64 dst) | |
474 | { | |
475 | tcg_gen_mov_i64(cc_src, src); | |
476 | tcg_gen_mov_i64(cc_dst, dst); | |
477 | tcg_gen_discard_i64(cc_vr); | |
478 | s->cc_op = op; | |
479 | } | |
480 | ||
481 | static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src, | |
482 | TCGv_i32 dst) | |
483 | { | |
484 | tcg_gen_extu_i32_i64(cc_src, src); | |
485 | tcg_gen_extu_i32_i64(cc_dst, dst); | |
486 | tcg_gen_discard_i64(cc_vr); | |
487 | s->cc_op = op; | |
488 | } | |
489 | ||
490 | static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src, | |
491 | TCGv_i64 dst, TCGv_i64 vr) | |
492 | { | |
493 | tcg_gen_mov_i64(cc_src, src); | |
494 | tcg_gen_mov_i64(cc_dst, dst); | |
495 | tcg_gen_mov_i64(cc_vr, vr); | |
496 | s->cc_op = op; | |
497 | } | |
498 | ||
499 | static void gen_op_update3_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src, | |
500 | TCGv_i32 dst, TCGv_i32 vr) | |
501 | { | |
502 | tcg_gen_extu_i32_i64(cc_src, src); | |
503 | tcg_gen_extu_i32_i64(cc_dst, dst); | |
504 | tcg_gen_extu_i32_i64(cc_vr, vr); | |
505 | s->cc_op = op; | |
506 | } | |
507 | ||
508 | static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val) | |
509 | { | |
510 | gen_op_update1_cc_i32(s, CC_OP_NZ, val); | |
511 | } | |
512 | ||
513 | static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val) | |
514 | { | |
515 | gen_op_update1_cc_i64(s, CC_OP_NZ, val); | |
516 | } | |
517 | ||
518 | static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, | |
519 | enum cc_op cond) | |
520 | { | |
521 | gen_op_update2_cc_i32(s, cond, v1, v2); | |
522 | } | |
523 | ||
524 | static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, | |
525 | enum cc_op cond) | |
526 | { | |
527 | gen_op_update2_cc_i64(s, cond, v1, v2); | |
528 | } | |
529 | ||
530 | static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2) | |
531 | { | |
532 | cmp_32(s, v1, v2, CC_OP_LTGT_32); | |
533 | } | |
534 | ||
535 | static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2) | |
536 | { | |
537 | cmp_32(s, v1, v2, CC_OP_LTUGTU_32); | |
538 | } | |
539 | ||
540 | static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2) | |
541 | { | |
542 | /* XXX optimize for the constant? put it in s? */ | |
543 | TCGv_i32 tmp = tcg_const_i32(v2); | |
544 | cmp_32(s, v1, tmp, CC_OP_LTGT_32); | |
545 | tcg_temp_free_i32(tmp); | |
546 | } | |
547 | ||
548 | static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2) | |
549 | { | |
550 | TCGv_i32 tmp = tcg_const_i32(v2); | |
551 | cmp_32(s, v1, tmp, CC_OP_LTUGTU_32); | |
552 | tcg_temp_free_i32(tmp); | |
553 | } | |
554 | ||
555 | static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2) | |
556 | { | |
557 | cmp_64(s, v1, v2, CC_OP_LTGT_64); | |
558 | } | |
559 | ||
560 | static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2) | |
561 | { | |
562 | cmp_64(s, v1, v2, CC_OP_LTUGTU_64); | |
563 | } | |
564 | ||
565 | static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2) | |
566 | { | |
567 | TCGv_i64 tmp = tcg_const_i64(v2); | |
568 | cmp_s64(s, v1, tmp); | |
569 | tcg_temp_free_i64(tmp); | |
570 | } | |
571 | ||
572 | static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2) | |
573 | { | |
574 | TCGv_i64 tmp = tcg_const_i64(v2); | |
575 | cmp_u64(s, v1, tmp); | |
576 | tcg_temp_free_i64(tmp); | |
577 | } | |
578 | ||
579 | static inline void set_cc_s32(DisasContext *s, TCGv_i32 val) | |
580 | { | |
581 | gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val); | |
582 | } | |
583 | ||
584 | static inline void set_cc_s64(DisasContext *s, TCGv_i64 val) | |
585 | { | |
586 | gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val); | |
587 | } | |
588 | ||
589 | static void set_cc_add64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr) | |
590 | { | |
591 | gen_op_update3_cc_i64(s, CC_OP_ADD_64, v1, v2, vr); | |
592 | } | |
593 | ||
594 | static void set_cc_addu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, | |
595 | TCGv_i64 vr) | |
596 | { | |
597 | gen_op_update3_cc_i64(s, CC_OP_ADDU_64, v1, v2, vr); | |
598 | } | |
599 | ||
600 | static void set_cc_sub64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr) | |
601 | { | |
602 | gen_op_update3_cc_i64(s, CC_OP_SUB_64, v1, v2, vr); | |
603 | } | |
604 | ||
605 | static void set_cc_subu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, | |
606 | TCGv_i64 vr) | |
607 | { | |
608 | gen_op_update3_cc_i64(s, CC_OP_SUBU_64, v1, v2, vr); | |
609 | } | |
610 | ||
611 | static void set_cc_abs64(DisasContext *s, TCGv_i64 v1) | |
612 | { | |
613 | gen_op_update1_cc_i64(s, CC_OP_ABS_64, v1); | |
614 | } | |
615 | ||
616 | static void set_cc_nabs64(DisasContext *s, TCGv_i64 v1) | |
617 | { | |
618 | gen_op_update1_cc_i64(s, CC_OP_NABS_64, v1); | |
619 | } | |
620 | ||
621 | static void set_cc_add32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr) | |
622 | { | |
623 | gen_op_update3_cc_i32(s, CC_OP_ADD_32, v1, v2, vr); | |
624 | } | |
625 | ||
626 | static void set_cc_addu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, | |
627 | TCGv_i32 vr) | |
628 | { | |
629 | gen_op_update3_cc_i32(s, CC_OP_ADDU_32, v1, v2, vr); | |
630 | } | |
631 | ||
632 | static void set_cc_sub32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr) | |
633 | { | |
634 | gen_op_update3_cc_i32(s, CC_OP_SUB_32, v1, v2, vr); | |
635 | } | |
636 | ||
637 | static void set_cc_subu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, | |
638 | TCGv_i32 vr) | |
639 | { | |
640 | gen_op_update3_cc_i32(s, CC_OP_SUBU_32, v1, v2, vr); | |
641 | } | |
642 | ||
643 | static void set_cc_abs32(DisasContext *s, TCGv_i32 v1) | |
644 | { | |
645 | gen_op_update1_cc_i32(s, CC_OP_ABS_32, v1); | |
646 | } | |
647 | ||
648 | static void set_cc_nabs32(DisasContext *s, TCGv_i32 v1) | |
649 | { | |
650 | gen_op_update1_cc_i32(s, CC_OP_NABS_32, v1); | |
651 | } | |
652 | ||
653 | static void set_cc_comp32(DisasContext *s, TCGv_i32 v1) | |
654 | { | |
655 | gen_op_update1_cc_i32(s, CC_OP_COMP_32, v1); | |
656 | } | |
657 | ||
658 | static void set_cc_comp64(DisasContext *s, TCGv_i64 v1) | |
659 | { | |
660 | gen_op_update1_cc_i64(s, CC_OP_COMP_64, v1); | |
661 | } | |
662 | ||
663 | static void set_cc_icm(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2) | |
664 | { | |
665 | gen_op_update2_cc_i32(s, CC_OP_ICM, v1, v2); | |
666 | } | |
667 | ||
668 | static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2) | |
669 | { | |
670 | tcg_gen_extu_i32_i64(cc_src, v1); | |
671 | tcg_gen_mov_i64(cc_dst, v2); | |
672 | tcg_gen_discard_i64(cc_vr); | |
673 | s->cc_op = CC_OP_LTGT_F32; | |
674 | } | |
675 | ||
676 | static void set_cc_nz_f32(DisasContext *s, TCGv_i32 v1) | |
677 | { | |
678 | gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1); | |
679 | } | |
680 | ||
681 | static inline void set_cc_nz_f64(DisasContext *s, TCGv_i64 v1) | |
682 | { | |
683 | gen_op_update1_cc_i64(s, CC_OP_NZ_F64, v1); | |
684 | } | |
685 | ||
686 | /* CC value is in env->cc_op */ | |
687 | static inline void set_cc_static(DisasContext *s) | |
688 | { | |
689 | tcg_gen_discard_i64(cc_src); | |
690 | tcg_gen_discard_i64(cc_dst); | |
691 | tcg_gen_discard_i64(cc_vr); | |
692 | s->cc_op = CC_OP_STATIC; | |
693 | } | |
694 | ||
695 | static inline void gen_op_set_cc_op(DisasContext *s) | |
696 | { | |
697 | if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) { | |
698 | tcg_gen_movi_i32(cc_op, s->cc_op); | |
699 | } | |
700 | } | |
701 | ||
702 | static inline void gen_update_cc_op(DisasContext *s) | |
703 | { | |
704 | gen_op_set_cc_op(s); | |
705 | } | |
706 | ||
707 | /* calculates cc into cc_op */ | |
708 | static void gen_op_calc_cc(DisasContext *s) | |
709 | { | |
710 | TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op); | |
711 | TCGv_i64 dummy = tcg_const_i64(0); | |
712 | ||
713 | switch (s->cc_op) { | |
714 | case CC_OP_CONST0: | |
715 | case CC_OP_CONST1: | |
716 | case CC_OP_CONST2: | |
717 | case CC_OP_CONST3: | |
718 | /* s->cc_op is the cc value */ | |
719 | tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0); | |
720 | break; | |
721 | case CC_OP_STATIC: | |
722 | /* env->cc_op already is the cc value */ | |
723 | break; | |
724 | case CC_OP_NZ: | |
725 | case CC_OP_ABS_64: | |
726 | case CC_OP_NABS_64: | |
727 | case CC_OP_ABS_32: | |
728 | case CC_OP_NABS_32: | |
729 | case CC_OP_LTGT0_32: | |
730 | case CC_OP_LTGT0_64: | |
731 | case CC_OP_COMP_32: | |
732 | case CC_OP_COMP_64: | |
733 | case CC_OP_NZ_F32: | |
734 | case CC_OP_NZ_F64: | |
735 | /* 1 argument */ | |
736 | gen_helper_calc_cc(cc_op, local_cc_op, dummy, cc_dst, dummy); | |
737 | break; | |
738 | case CC_OP_ICM: | |
739 | case CC_OP_LTGT_32: | |
740 | case CC_OP_LTGT_64: | |
741 | case CC_OP_LTUGTU_32: | |
742 | case CC_OP_LTUGTU_64: | |
743 | case CC_OP_TM_32: | |
744 | case CC_OP_TM_64: | |
745 | case CC_OP_LTGT_F32: | |
746 | case CC_OP_LTGT_F64: | |
747 | case CC_OP_SLAG: | |
748 | /* 2 arguments */ | |
749 | gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, dummy); | |
750 | break; | |
751 | case CC_OP_ADD_64: | |
752 | case CC_OP_ADDU_64: | |
753 | case CC_OP_SUB_64: | |
754 | case CC_OP_SUBU_64: | |
755 | case CC_OP_ADD_32: | |
756 | case CC_OP_ADDU_32: | |
757 | case CC_OP_SUB_32: | |
758 | case CC_OP_SUBU_32: | |
759 | /* 3 arguments */ | |
760 | gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, cc_vr); | |
761 | break; | |
762 | case CC_OP_DYNAMIC: | |
763 | /* unknown operation - assume 3 arguments and cc_op in env */ | |
764 | gen_helper_calc_cc(cc_op, cc_op, cc_src, cc_dst, cc_vr); | |
765 | break; | |
766 | default: | |
767 | tcg_abort(); | |
768 | } | |
769 | ||
770 | tcg_temp_free_i32(local_cc_op); | |
771 | ||
772 | /* We now have cc in cc_op as constant */ | |
773 | set_cc_static(s); | |
774 | } | |
775 | ||
776 | static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2) | |
777 | { | |
778 | debug_insn(insn); | |
779 | ||
780 | *r1 = (insn >> 4) & 0xf; | |
781 | *r2 = insn & 0xf; | |
782 | } | |
783 | ||
784 | static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1, | |
785 | int *x2, int *b2, int *d2) | |
786 | { | |
787 | debug_insn(insn); | |
788 | ||
789 | *r1 = (insn >> 20) & 0xf; | |
790 | *x2 = (insn >> 16) & 0xf; | |
791 | *b2 = (insn >> 12) & 0xf; | |
792 | *d2 = insn & 0xfff; | |
793 | ||
794 | return get_address(s, *x2, *b2, *d2); | |
795 | } | |
796 | ||
797 | static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3, | |
798 | int *b2, int *d2) | |
799 | { | |
800 | debug_insn(insn); | |
801 | ||
802 | *r1 = (insn >> 20) & 0xf; | |
803 | /* aka m3 */ | |
804 | *r3 = (insn >> 16) & 0xf; | |
805 | *b2 = (insn >> 12) & 0xf; | |
806 | *d2 = insn & 0xfff; | |
807 | } | |
808 | ||
809 | static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2, | |
810 | int *b1, int *d1) | |
811 | { | |
812 | debug_insn(insn); | |
813 | ||
814 | *i2 = (insn >> 16) & 0xff; | |
815 | *b1 = (insn >> 12) & 0xf; | |
816 | *d1 = insn & 0xfff; | |
817 | ||
818 | return get_address(s, 0, *b1, *d1); | |
819 | } | |
820 | ||
821 | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc) | |
822 | { | |
823 | TranslationBlock *tb; | |
824 | ||
825 | gen_update_cc_op(s); | |
826 | ||
827 | tb = s->tb; | |
828 | /* NOTE: we handle the case where the TB spans two pages here */ | |
829 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) || | |
830 | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { | |
831 | /* jump to same page: we can use a direct jump */ | |
832 | tcg_gen_goto_tb(tb_num); | |
833 | tcg_gen_movi_i64(psw_addr, pc); | |
834 | tcg_gen_exit_tb((long)tb + tb_num); | |
835 | } else { | |
836 | /* jump to another page: currently not optimized */ | |
837 | tcg_gen_movi_i64(psw_addr, pc); | |
838 | tcg_gen_exit_tb(0); | |
839 | } | |
840 | } | |
841 | ||
842 | static inline void account_noninline_branch(DisasContext *s, int cc_op) | |
843 | { | |
844 | #ifdef DEBUG_INLINE_BRANCHES | |
845 | inline_branch_miss[cc_op]++; | |
846 | #endif | |
847 | } | |
848 | ||
849 | static inline void account_inline_branch(DisasContext *s) | |
850 | { | |
851 | #ifdef DEBUG_INLINE_BRANCHES | |
852 | inline_branch_hit[s->cc_op]++; | |
853 | #endif | |
854 | } | |
855 | ||
856 | static void gen_jcc(DisasContext *s, uint32_t mask, int skip) | |
857 | { | |
858 | TCGv_i32 tmp, tmp2, r; | |
859 | TCGv_i64 tmp64; | |
860 | int old_cc_op; | |
861 | ||
862 | switch (s->cc_op) { | |
863 | case CC_OP_LTGT0_32: | |
864 | tmp = tcg_temp_new_i32(); | |
865 | tcg_gen_trunc_i64_i32(tmp, cc_dst); | |
866 | switch (mask) { | |
867 | case 0x8 | 0x4: /* dst <= 0 */ | |
868 | tcg_gen_brcondi_i32(TCG_COND_GT, tmp, 0, skip); | |
869 | break; | |
870 | case 0x8 | 0x2: /* dst >= 0 */ | |
871 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, skip); | |
872 | break; | |
873 | case 0x8: /* dst == 0 */ | |
874 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip); | |
875 | break; | |
876 | case 0x7: /* dst != 0 */ | |
877 | case 0x6: /* dst != 0 */ | |
878 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip); | |
879 | break; | |
880 | case 0x4: /* dst < 0 */ | |
881 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, skip); | |
882 | break; | |
883 | case 0x2: /* dst > 0 */ | |
884 | tcg_gen_brcondi_i32(TCG_COND_LE, tmp, 0, skip); | |
885 | break; | |
886 | default: | |
887 | tcg_temp_free_i32(tmp); | |
888 | goto do_dynamic; | |
889 | } | |
890 | account_inline_branch(s); | |
891 | tcg_temp_free_i32(tmp); | |
892 | break; | |
893 | case CC_OP_LTGT0_64: | |
894 | switch (mask) { | |
895 | case 0x8 | 0x4: /* dst <= 0 */ | |
896 | tcg_gen_brcondi_i64(TCG_COND_GT, cc_dst, 0, skip); | |
897 | break; | |
898 | case 0x8 | 0x2: /* dst >= 0 */ | |
899 | tcg_gen_brcondi_i64(TCG_COND_LT, cc_dst, 0, skip); | |
900 | break; | |
901 | case 0x8: /* dst == 0 */ | |
902 | tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip); | |
903 | break; | |
904 | case 0x7: /* dst != 0 */ | |
905 | case 0x6: /* dst != 0 */ | |
906 | tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip); | |
907 | break; | |
908 | case 0x4: /* dst < 0 */ | |
909 | tcg_gen_brcondi_i64(TCG_COND_GE, cc_dst, 0, skip); | |
910 | break; | |
911 | case 0x2: /* dst > 0 */ | |
912 | tcg_gen_brcondi_i64(TCG_COND_LE, cc_dst, 0, skip); | |
913 | break; | |
914 | default: | |
915 | goto do_dynamic; | |
916 | } | |
917 | account_inline_branch(s); | |
918 | break; | |
919 | case CC_OP_LTGT_32: | |
920 | tmp = tcg_temp_new_i32(); | |
921 | tmp2 = tcg_temp_new_i32(); | |
922 | tcg_gen_trunc_i64_i32(tmp, cc_src); | |
923 | tcg_gen_trunc_i64_i32(tmp2, cc_dst); | |
924 | switch (mask) { | |
925 | case 0x8 | 0x4: /* src <= dst */ | |
926 | tcg_gen_brcond_i32(TCG_COND_GT, tmp, tmp2, skip); | |
927 | break; | |
928 | case 0x8 | 0x2: /* src >= dst */ | |
929 | tcg_gen_brcond_i32(TCG_COND_LT, tmp, tmp2, skip); | |
930 | break; | |
931 | case 0x8: /* src == dst */ | |
932 | tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip); | |
933 | break; | |
934 | case 0x7: /* src != dst */ | |
935 | case 0x6: /* src != dst */ | |
936 | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip); | |
937 | break; | |
938 | case 0x4: /* src < dst */ | |
939 | tcg_gen_brcond_i32(TCG_COND_GE, tmp, tmp2, skip); | |
940 | break; | |
941 | case 0x2: /* src > dst */ | |
942 | tcg_gen_brcond_i32(TCG_COND_LE, tmp, tmp2, skip); | |
943 | break; | |
944 | default: | |
945 | tcg_temp_free_i32(tmp); | |
946 | tcg_temp_free_i32(tmp2); | |
947 | goto do_dynamic; | |
948 | } | |
949 | account_inline_branch(s); | |
950 | tcg_temp_free_i32(tmp); | |
951 | tcg_temp_free_i32(tmp2); | |
952 | break; | |
953 | case CC_OP_LTGT_64: | |
954 | switch (mask) { | |
955 | case 0x8 | 0x4: /* src <= dst */ | |
956 | tcg_gen_brcond_i64(TCG_COND_GT, cc_src, cc_dst, skip); | |
957 | break; | |
958 | case 0x8 | 0x2: /* src >= dst */ | |
959 | tcg_gen_brcond_i64(TCG_COND_LT, cc_src, cc_dst, skip); | |
960 | break; | |
961 | case 0x8: /* src == dst */ | |
962 | tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip); | |
963 | break; | |
964 | case 0x7: /* src != dst */ | |
965 | case 0x6: /* src != dst */ | |
966 | tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip); | |
967 | break; | |
968 | case 0x4: /* src < dst */ | |
969 | tcg_gen_brcond_i64(TCG_COND_GE, cc_src, cc_dst, skip); | |
970 | break; | |
971 | case 0x2: /* src > dst */ | |
972 | tcg_gen_brcond_i64(TCG_COND_LE, cc_src, cc_dst, skip); | |
973 | break; | |
974 | default: | |
975 | goto do_dynamic; | |
976 | } | |
977 | account_inline_branch(s); | |
978 | break; | |
979 | case CC_OP_LTUGTU_32: | |
980 | tmp = tcg_temp_new_i32(); | |
981 | tmp2 = tcg_temp_new_i32(); | |
982 | tcg_gen_trunc_i64_i32(tmp, cc_src); | |
983 | tcg_gen_trunc_i64_i32(tmp2, cc_dst); | |
984 | switch (mask) { | |
985 | case 0x8 | 0x4: /* src <= dst */ | |
986 | tcg_gen_brcond_i32(TCG_COND_GTU, tmp, tmp2, skip); | |
987 | break; | |
988 | case 0x8 | 0x2: /* src >= dst */ | |
989 | tcg_gen_brcond_i32(TCG_COND_LTU, tmp, tmp2, skip); | |
990 | break; | |
991 | case 0x8: /* src == dst */ | |
992 | tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip); | |
993 | break; | |
994 | case 0x7: /* src != dst */ | |
995 | case 0x6: /* src != dst */ | |
996 | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip); | |
997 | break; | |
998 | case 0x4: /* src < dst */ | |
999 | tcg_gen_brcond_i32(TCG_COND_GEU, tmp, tmp2, skip); | |
1000 | break; | |
1001 | case 0x2: /* src > dst */ | |
1002 | tcg_gen_brcond_i32(TCG_COND_LEU, tmp, tmp2, skip); | |
1003 | break; | |
1004 | default: | |
1005 | tcg_temp_free_i32(tmp); | |
1006 | tcg_temp_free_i32(tmp2); | |
1007 | goto do_dynamic; | |
1008 | } | |
1009 | account_inline_branch(s); | |
1010 | tcg_temp_free_i32(tmp); | |
1011 | tcg_temp_free_i32(tmp2); | |
1012 | break; | |
1013 | case CC_OP_LTUGTU_64: | |
1014 | switch (mask) { | |
1015 | case 0x8 | 0x4: /* src <= dst */ | |
1016 | tcg_gen_brcond_i64(TCG_COND_GTU, cc_src, cc_dst, skip); | |
1017 | break; | |
1018 | case 0x8 | 0x2: /* src >= dst */ | |
1019 | tcg_gen_brcond_i64(TCG_COND_LTU, cc_src, cc_dst, skip); | |
1020 | break; | |
1021 | case 0x8: /* src == dst */ | |
1022 | tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip); | |
1023 | break; | |
1024 | case 0x7: /* src != dst */ | |
1025 | case 0x6: /* src != dst */ | |
1026 | tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip); | |
1027 | break; | |
1028 | case 0x4: /* src < dst */ | |
1029 | tcg_gen_brcond_i64(TCG_COND_GEU, cc_src, cc_dst, skip); | |
1030 | break; | |
1031 | case 0x2: /* src > dst */ | |
1032 | tcg_gen_brcond_i64(TCG_COND_LEU, cc_src, cc_dst, skip); | |
1033 | break; | |
1034 | default: | |
1035 | goto do_dynamic; | |
1036 | } | |
1037 | account_inline_branch(s); | |
1038 | break; | |
1039 | case CC_OP_NZ: | |
1040 | switch (mask) { | |
1041 | /* dst == 0 || dst != 0 */ | |
1042 | case 0x8 | 0x4: | |
1043 | case 0x8 | 0x4 | 0x2: | |
1044 | case 0x8 | 0x4 | 0x2 | 0x1: | |
1045 | case 0x8 | 0x4 | 0x1: | |
1046 | break; | |
1047 | /* dst == 0 */ | |
1048 | case 0x8: | |
1049 | case 0x8 | 0x2: | |
1050 | case 0x8 | 0x2 | 0x1: | |
1051 | case 0x8 | 0x1: | |
1052 | tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip); | |
1053 | break; | |
1054 | /* dst != 0 */ | |
1055 | case 0x4: | |
1056 | case 0x4 | 0x2: | |
1057 | case 0x4 | 0x2 | 0x1: | |
1058 | case 0x4 | 0x1: | |
1059 | tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip); | |
1060 | break; | |
1061 | default: | |
1062 | goto do_dynamic; | |
1063 | } | |
1064 | account_inline_branch(s); | |
1065 | break; | |
1066 | case CC_OP_TM_32: | |
1067 | tmp = tcg_temp_new_i32(); | |
1068 | tmp2 = tcg_temp_new_i32(); | |
1069 | ||
1070 | tcg_gen_trunc_i64_i32(tmp, cc_src); | |
1071 | tcg_gen_trunc_i64_i32(tmp2, cc_dst); | |
1072 | tcg_gen_and_i32(tmp, tmp, tmp2); | |
1073 | switch (mask) { | |
1074 | case 0x8: /* val & mask == 0 */ | |
1075 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip); | |
1076 | break; | |
1077 | case 0x4 | 0x2 | 0x1: /* val & mask != 0 */ | |
1078 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip); | |
1079 | break; | |
1080 | default: | |
2497a67f SW |
1081 | tcg_temp_free_i32(tmp); |
1082 | tcg_temp_free_i32(tmp2); | |
e023e832 AG |
1083 | goto do_dynamic; |
1084 | } | |
1085 | tcg_temp_free_i32(tmp); | |
2497a67f | 1086 | tcg_temp_free_i32(tmp2); |
e023e832 AG |
1087 | account_inline_branch(s); |
1088 | break; | |
1089 | case CC_OP_TM_64: | |
1090 | tmp64 = tcg_temp_new_i64(); | |
1091 | ||
1092 | tcg_gen_and_i64(tmp64, cc_src, cc_dst); | |
1093 | switch (mask) { | |
1094 | case 0x8: /* val & mask == 0 */ | |
1095 | tcg_gen_brcondi_i64(TCG_COND_NE, tmp64, 0, skip); | |
1096 | break; | |
1097 | case 0x4 | 0x2 | 0x1: /* val & mask != 0 */ | |
1098 | tcg_gen_brcondi_i64(TCG_COND_EQ, tmp64, 0, skip); | |
1099 | break; | |
1100 | default: | |
a825aefb | 1101 | tcg_temp_free_i64(tmp64); |
e023e832 AG |
1102 | goto do_dynamic; |
1103 | } | |
1104 | tcg_temp_free_i64(tmp64); | |
1105 | account_inline_branch(s); | |
1106 | break; | |
1107 | case CC_OP_ICM: | |
1108 | switch (mask) { | |
1109 | case 0x8: /* val == 0 */ | |
1110 | tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip); | |
1111 | break; | |
1112 | case 0x4 | 0x2 | 0x1: /* val != 0 */ | |
1113 | case 0x4 | 0x2: /* val != 0 */ | |
1114 | tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip); | |
1115 | break; | |
1116 | default: | |
1117 | goto do_dynamic; | |
1118 | } | |
1119 | account_inline_branch(s); | |
1120 | break; | |
1121 | case CC_OP_STATIC: | |
1122 | old_cc_op = s->cc_op; | |
1123 | goto do_dynamic_nocccalc; | |
1124 | case CC_OP_DYNAMIC: | |
1125 | default: | |
1126 | do_dynamic: | |
1127 | old_cc_op = s->cc_op; | |
1128 | /* calculate cc value */ | |
1129 | gen_op_calc_cc(s); | |
1130 | ||
1131 | do_dynamic_nocccalc: | |
1132 | /* jump based on cc */ | |
1133 | account_noninline_branch(s, old_cc_op); | |
1134 | ||
1135 | switch (mask) { | |
1136 | case 0x8 | 0x4 | 0x2 | 0x1: | |
1137 | /* always true */ | |
1138 | break; | |
1139 | case 0x8 | 0x4 | 0x2: /* cc != 3 */ | |
1140 | tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 3, skip); | |
1141 | break; | |
1142 | case 0x8 | 0x4 | 0x1: /* cc != 2 */ | |
1143 | tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 2, skip); | |
1144 | break; | |
1145 | case 0x8 | 0x2 | 0x1: /* cc != 1 */ | |
1146 | tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 1, skip); | |
1147 | break; | |
1148 | case 0x8 | 0x2: /* cc == 0 ||Â cc == 2 */ | |
1149 | tmp = tcg_temp_new_i32(); | |
1150 | tcg_gen_andi_i32(tmp, cc_op, 1); | |
1151 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip); | |
1152 | tcg_temp_free_i32(tmp); | |
1153 | break; | |
1154 | case 0x8 | 0x4: /* cc < 2 */ | |
1155 | tcg_gen_brcondi_i32(TCG_COND_GEU, cc_op, 2, skip); | |
1156 | break; | |
1157 | case 0x8: /* cc == 0 */ | |
1158 | tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 0, skip); | |
1159 | break; | |
1160 | case 0x4 | 0x2 | 0x1: /* cc != 0 */ | |
1161 | tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 0, skip); | |
1162 | break; | |
1163 | case 0x4 | 0x1: /* cc == 1 ||Â cc == 3 */ | |
1164 | tmp = tcg_temp_new_i32(); | |
1165 | tcg_gen_andi_i32(tmp, cc_op, 1); | |
1166 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip); | |
1167 | tcg_temp_free_i32(tmp); | |
1168 | break; | |
1169 | case 0x4: /* cc == 1 */ | |
1170 | tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 1, skip); | |
1171 | break; | |
1172 | case 0x2 | 0x1: /* cc > 1 */ | |
1173 | tcg_gen_brcondi_i32(TCG_COND_LEU, cc_op, 1, skip); | |
1174 | break; | |
1175 | case 0x2: /* cc == 2 */ | |
1176 | tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 2, skip); | |
1177 | break; | |
1178 | case 0x1: /* cc == 3 */ | |
1179 | tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 3, skip); | |
1180 | break; | |
1181 | default: /* cc is masked by something else */ | |
1182 | tmp = tcg_const_i32(3); | |
1183 | /* 3 - cc */ | |
1184 | tcg_gen_sub_i32(tmp, tmp, cc_op); | |
1185 | tmp2 = tcg_const_i32(1); | |
1186 | /* 1 << (3 - cc) */ | |
1187 | tcg_gen_shl_i32(tmp2, tmp2, tmp); | |
1188 | r = tcg_const_i32(mask); | |
1189 | /* mask & (1 << (3 - cc)) */ | |
1190 | tcg_gen_and_i32(r, r, tmp2); | |
1191 | tcg_temp_free_i32(tmp); | |
1192 | tcg_temp_free_i32(tmp2); | |
1193 | ||
1194 | tcg_gen_brcondi_i32(TCG_COND_EQ, r, 0, skip); | |
1195 | tcg_temp_free_i32(r); | |
1196 | break; | |
1197 | } | |
1198 | break; | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | static void gen_bcr(DisasContext *s, uint32_t mask, TCGv_i64 target, | |
1203 | uint64_t offset) | |
1204 | { | |
1205 | int skip; | |
1206 | ||
1207 | if (mask == 0xf) { | |
1208 | /* unconditional */ | |
1209 | tcg_gen_mov_i64(psw_addr, target); | |
1210 | tcg_gen_exit_tb(0); | |
1211 | } else if (mask == 0) { | |
1212 | /* ignore cc and never match */ | |
1213 | gen_goto_tb(s, 0, offset + 2); | |
1214 | } else { | |
1215 | TCGv_i64 new_addr = tcg_temp_local_new_i64(); | |
1216 | ||
1217 | tcg_gen_mov_i64(new_addr, target); | |
1218 | skip = gen_new_label(); | |
1219 | gen_jcc(s, mask, skip); | |
1220 | tcg_gen_mov_i64(psw_addr, new_addr); | |
1221 | tcg_temp_free_i64(new_addr); | |
1222 | tcg_gen_exit_tb(0); | |
1223 | gen_set_label(skip); | |
1224 | tcg_temp_free_i64(new_addr); | |
1225 | gen_goto_tb(s, 1, offset + 2); | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | static void gen_brc(uint32_t mask, DisasContext *s, int32_t offset) | |
1230 | { | |
1231 | int skip; | |
1232 | ||
1233 | if (mask == 0xf) { | |
1234 | /* unconditional */ | |
1235 | gen_goto_tb(s, 0, s->pc + offset); | |
1236 | } else if (mask == 0) { | |
1237 | /* ignore cc and never match */ | |
1238 | gen_goto_tb(s, 0, s->pc + 4); | |
1239 | } else { | |
1240 | skip = gen_new_label(); | |
1241 | gen_jcc(s, mask, skip); | |
1242 | gen_goto_tb(s, 0, s->pc + offset); | |
1243 | gen_set_label(skip); | |
1244 | gen_goto_tb(s, 1, s->pc + 4); | |
1245 | } | |
1246 | s->is_jmp = DISAS_TB_JUMP; | |
1247 | } | |
1248 | ||
1249 | static void gen_op_mvc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2) | |
1250 | { | |
1251 | TCGv_i64 tmp, tmp2; | |
1252 | int i; | |
1253 | int l_memset = gen_new_label(); | |
1254 | int l_out = gen_new_label(); | |
1255 | TCGv_i64 dest = tcg_temp_local_new_i64(); | |
1256 | TCGv_i64 src = tcg_temp_local_new_i64(); | |
1257 | TCGv_i32 vl; | |
1258 | ||
1259 | /* Find out if we should use the inline version of mvc */ | |
1260 | switch (l) { | |
1261 | case 0: | |
1262 | case 1: | |
1263 | case 2: | |
1264 | case 3: | |
1265 | case 4: | |
1266 | case 5: | |
1267 | case 6: | |
1268 | case 7: | |
1269 | case 11: | |
1270 | case 15: | |
1271 | /* use inline */ | |
1272 | break; | |
1273 | default: | |
1274 | /* Fall back to helper */ | |
1275 | vl = tcg_const_i32(l); | |
1276 | potential_page_fault(s); | |
1277 | gen_helper_mvc(vl, s1, s2); | |
1278 | tcg_temp_free_i32(vl); | |
1279 | return; | |
1280 | } | |
1281 | ||
1282 | tcg_gen_mov_i64(dest, s1); | |
1283 | tcg_gen_mov_i64(src, s2); | |
1284 | ||
1285 | if (!(s->tb->flags & FLAG_MASK_64)) { | |
1286 | /* XXX what if we overflow while moving? */ | |
1287 | tcg_gen_andi_i64(dest, dest, 0x7fffffffUL); | |
1288 | tcg_gen_andi_i64(src, src, 0x7fffffffUL); | |
1289 | } | |
1290 | ||
1291 | tmp = tcg_temp_new_i64(); | |
1292 | tcg_gen_addi_i64(tmp, src, 1); | |
1293 | tcg_gen_brcond_i64(TCG_COND_EQ, dest, tmp, l_memset); | |
1294 | tcg_temp_free_i64(tmp); | |
1295 | ||
1296 | switch (l) { | |
1297 | case 0: | |
1298 | tmp = tcg_temp_new_i64(); | |
1299 | ||
1300 | tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s)); | |
1301 | tcg_gen_qemu_st8(tmp, dest, get_mem_index(s)); | |
1302 | ||
1303 | tcg_temp_free_i64(tmp); | |
1304 | break; | |
1305 | case 1: | |
1306 | tmp = tcg_temp_new_i64(); | |
1307 | ||
1308 | tcg_gen_qemu_ld16u(tmp, src, get_mem_index(s)); | |
1309 | tcg_gen_qemu_st16(tmp, dest, get_mem_index(s)); | |
1310 | ||
1311 | tcg_temp_free_i64(tmp); | |
1312 | break; | |
1313 | case 3: | |
1314 | tmp = tcg_temp_new_i64(); | |
1315 | ||
1316 | tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s)); | |
1317 | tcg_gen_qemu_st32(tmp, dest, get_mem_index(s)); | |
1318 | ||
1319 | tcg_temp_free_i64(tmp); | |
1320 | break; | |
1321 | case 4: | |
1322 | tmp = tcg_temp_new_i64(); | |
1323 | tmp2 = tcg_temp_new_i64(); | |
1324 | ||
1325 | tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s)); | |
1326 | tcg_gen_addi_i64(src, src, 4); | |
1327 | tcg_gen_qemu_ld8u(tmp2, src, get_mem_index(s)); | |
1328 | tcg_gen_qemu_st32(tmp, dest, get_mem_index(s)); | |
1329 | tcg_gen_addi_i64(dest, dest, 4); | |
1330 | tcg_gen_qemu_st8(tmp2, dest, get_mem_index(s)); | |
1331 | ||
1332 | tcg_temp_free_i64(tmp); | |
1333 | tcg_temp_free_i64(tmp2); | |
1334 | break; | |
1335 | case 7: | |
1336 | tmp = tcg_temp_new_i64(); | |
1337 | ||
1338 | tcg_gen_qemu_ld64(tmp, src, get_mem_index(s)); | |
1339 | tcg_gen_qemu_st64(tmp, dest, get_mem_index(s)); | |
1340 | ||
1341 | tcg_temp_free_i64(tmp); | |
1342 | break; | |
1343 | default: | |
1344 | /* The inline version can become too big for too uneven numbers, only | |
1345 | use it on known good lengths */ | |
1346 | tmp = tcg_temp_new_i64(); | |
1347 | tmp2 = tcg_const_i64(8); | |
1348 | for (i = 0; (i + 7) <= l; i += 8) { | |
1349 | tcg_gen_qemu_ld64(tmp, src, get_mem_index(s)); | |
1350 | tcg_gen_qemu_st64(tmp, dest, get_mem_index(s)); | |
1351 | ||
1352 | tcg_gen_add_i64(src, src, tmp2); | |
1353 | tcg_gen_add_i64(dest, dest, tmp2); | |
1354 | } | |
1355 | ||
1356 | tcg_temp_free_i64(tmp2); | |
1357 | tmp2 = tcg_const_i64(1); | |
1358 | ||
1359 | for (; i <= l; i++) { | |
1360 | tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s)); | |
1361 | tcg_gen_qemu_st8(tmp, dest, get_mem_index(s)); | |
1362 | ||
1363 | tcg_gen_add_i64(src, src, tmp2); | |
1364 | tcg_gen_add_i64(dest, dest, tmp2); | |
1365 | } | |
1366 | ||
1367 | tcg_temp_free_i64(tmp2); | |
1368 | tcg_temp_free_i64(tmp); | |
1369 | break; | |
1370 | } | |
1371 | ||
1372 | tcg_gen_br(l_out); | |
1373 | ||
1374 | gen_set_label(l_memset); | |
1375 | /* memset case (dest == (src + 1)) */ | |
1376 | ||
1377 | tmp = tcg_temp_new_i64(); | |
1378 | tmp2 = tcg_temp_new_i64(); | |
1379 | /* fill tmp with the byte */ | |
1380 | tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s)); | |
1381 | tcg_gen_shli_i64(tmp2, tmp, 8); | |
1382 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
1383 | tcg_gen_shli_i64(tmp2, tmp, 16); | |
1384 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
1385 | tcg_gen_shli_i64(tmp2, tmp, 32); | |
1386 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
1387 | tcg_temp_free_i64(tmp2); | |
1388 | ||
1389 | tmp2 = tcg_const_i64(8); | |
1390 | ||
1391 | for (i = 0; (i + 7) <= l; i += 8) { | |
1392 | tcg_gen_qemu_st64(tmp, dest, get_mem_index(s)); | |
1393 | tcg_gen_addi_i64(dest, dest, 8); | |
1394 | } | |
1395 | ||
1396 | tcg_temp_free_i64(tmp2); | |
1397 | tmp2 = tcg_const_i64(1); | |
1398 | ||
1399 | for (; i <= l; i++) { | |
1400 | tcg_gen_qemu_st8(tmp, dest, get_mem_index(s)); | |
1401 | tcg_gen_addi_i64(dest, dest, 1); | |
1402 | } | |
1403 | ||
1404 | tcg_temp_free_i64(tmp2); | |
1405 | tcg_temp_free_i64(tmp); | |
1406 | ||
1407 | gen_set_label(l_out); | |
1408 | ||
1409 | tcg_temp_free(dest); | |
1410 | tcg_temp_free(src); | |
1411 | } | |
1412 | ||
1413 | static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2) | |
1414 | { | |
1415 | TCGv_i64 tmp; | |
1416 | TCGv_i64 tmp2; | |
1417 | TCGv_i32 vl; | |
1418 | ||
1419 | /* check for simple 32bit or 64bit match */ | |
1420 | switch (l) { | |
1421 | case 0: | |
1422 | tmp = tcg_temp_new_i64(); | |
1423 | tmp2 = tcg_temp_new_i64(); | |
1424 | ||
1425 | tcg_gen_qemu_ld8u(tmp, s1, get_mem_index(s)); | |
1426 | tcg_gen_qemu_ld8u(tmp2, s2, get_mem_index(s)); | |
1427 | cmp_u64(s, tmp, tmp2); | |
1428 | ||
1429 | tcg_temp_free_i64(tmp); | |
1430 | tcg_temp_free_i64(tmp2); | |
1431 | return; | |
1432 | case 1: | |
1433 | tmp = tcg_temp_new_i64(); | |
1434 | tmp2 = tcg_temp_new_i64(); | |
1435 | ||
1436 | tcg_gen_qemu_ld16u(tmp, s1, get_mem_index(s)); | |
1437 | tcg_gen_qemu_ld16u(tmp2, s2, get_mem_index(s)); | |
1438 | cmp_u64(s, tmp, tmp2); | |
1439 | ||
1440 | tcg_temp_free_i64(tmp); | |
1441 | tcg_temp_free_i64(tmp2); | |
1442 | return; | |
1443 | case 3: | |
1444 | tmp = tcg_temp_new_i64(); | |
1445 | tmp2 = tcg_temp_new_i64(); | |
1446 | ||
1447 | tcg_gen_qemu_ld32u(tmp, s1, get_mem_index(s)); | |
1448 | tcg_gen_qemu_ld32u(tmp2, s2, get_mem_index(s)); | |
1449 | cmp_u64(s, tmp, tmp2); | |
1450 | ||
1451 | tcg_temp_free_i64(tmp); | |
1452 | tcg_temp_free_i64(tmp2); | |
1453 | return; | |
1454 | case 7: | |
1455 | tmp = tcg_temp_new_i64(); | |
1456 | tmp2 = tcg_temp_new_i64(); | |
1457 | ||
1458 | tcg_gen_qemu_ld64(tmp, s1, get_mem_index(s)); | |
1459 | tcg_gen_qemu_ld64(tmp2, s2, get_mem_index(s)); | |
1460 | cmp_u64(s, tmp, tmp2); | |
1461 | ||
1462 | tcg_temp_free_i64(tmp); | |
1463 | tcg_temp_free_i64(tmp2); | |
1464 | return; | |
1465 | } | |
1466 | ||
1467 | potential_page_fault(s); | |
1468 | vl = tcg_const_i32(l); | |
1469 | gen_helper_clc(cc_op, vl, s1, s2); | |
1470 | tcg_temp_free_i32(vl); | |
1471 | set_cc_static(s); | |
1472 | } | |
1473 | ||
1474 | static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2) | |
1475 | { | |
1476 | TCGv_i64 addr, tmp, tmp2, tmp3, tmp4; | |
1477 | TCGv_i32 tmp32_1, tmp32_2, tmp32_3; | |
1478 | ||
1479 | LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n", | |
1480 | op, r1, x2, b2, d2); | |
1481 | addr = get_address(s, x2, b2, d2); | |
1482 | switch (op) { | |
1483 | case 0x2: /* LTG R1,D2(X2,B2) [RXY] */ | |
1484 | case 0x4: /* lg r1,d2(x2,b2) */ | |
1485 | tcg_gen_qemu_ld64(regs[r1], addr, get_mem_index(s)); | |
1486 | if (op == 0x2) { | |
1487 | set_cc_s64(s, regs[r1]); | |
1488 | } | |
1489 | break; | |
1490 | case 0x12: /* LT R1,D2(X2,B2) [RXY] */ | |
1491 | tmp2 = tcg_temp_new_i64(); | |
1492 | tmp32_1 = tcg_temp_new_i32(); | |
1493 | tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s)); | |
1494 | tcg_gen_trunc_i64_i32(tmp32_1, tmp2); | |
1495 | store_reg32(r1, tmp32_1); | |
1496 | set_cc_s32(s, tmp32_1); | |
1497 | tcg_temp_free_i64(tmp2); | |
1498 | tcg_temp_free_i32(tmp32_1); | |
1499 | break; | |
1500 | case 0xc: /* MSG R1,D2(X2,B2) [RXY] */ | |
1501 | case 0x1c: /* MSGF R1,D2(X2,B2) [RXY] */ | |
1502 | tmp2 = tcg_temp_new_i64(); | |
1503 | if (op == 0xc) { | |
1504 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1505 | } else { | |
1506 | tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s)); | |
1507 | } | |
1508 | tcg_gen_mul_i64(regs[r1], regs[r1], tmp2); | |
1509 | tcg_temp_free_i64(tmp2); | |
1510 | break; | |
1511 | case 0xd: /* DSG R1,D2(X2,B2) [RXY] */ | |
1512 | case 0x1d: /* DSGF R1,D2(X2,B2) [RXY] */ | |
1513 | tmp2 = tcg_temp_new_i64(); | |
1514 | if (op == 0x1d) { | |
1515 | tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s)); | |
1516 | } else { | |
1517 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1518 | } | |
1519 | tmp4 = load_reg(r1 + 1); | |
1520 | tmp3 = tcg_temp_new_i64(); | |
1521 | tcg_gen_div_i64(tmp3, tmp4, tmp2); | |
1522 | store_reg(r1 + 1, tmp3); | |
1523 | tcg_gen_rem_i64(tmp3, tmp4, tmp2); | |
1524 | store_reg(r1, tmp3); | |
1525 | tcg_temp_free_i64(tmp2); | |
1526 | tcg_temp_free_i64(tmp3); | |
1527 | tcg_temp_free_i64(tmp4); | |
1528 | break; | |
1529 | case 0x8: /* AG R1,D2(X2,B2) [RXY] */ | |
1530 | case 0xa: /* ALG R1,D2(X2,B2) [RXY] */ | |
1531 | case 0x18: /* AGF R1,D2(X2,B2) [RXY] */ | |
1532 | case 0x1a: /* ALGF R1,D2(X2,B2) [RXY] */ | |
1533 | if (op == 0x1a) { | |
1534 | tmp2 = tcg_temp_new_i64(); | |
1535 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1536 | } else if (op == 0x18) { | |
1537 | tmp2 = tcg_temp_new_i64(); | |
1538 | tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s)); | |
1539 | } else { | |
1540 | tmp2 = tcg_temp_new_i64(); | |
1541 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1542 | } | |
1543 | tmp4 = load_reg(r1); | |
1544 | tmp3 = tcg_temp_new_i64(); | |
1545 | tcg_gen_add_i64(tmp3, tmp4, tmp2); | |
1546 | store_reg(r1, tmp3); | |
1547 | switch (op) { | |
1548 | case 0x8: | |
1549 | case 0x18: | |
1550 | set_cc_add64(s, tmp4, tmp2, tmp3); | |
1551 | break; | |
1552 | case 0xa: | |
1553 | case 0x1a: | |
1554 | set_cc_addu64(s, tmp4, tmp2, tmp3); | |
1555 | break; | |
1556 | default: | |
1557 | tcg_abort(); | |
1558 | } | |
1559 | tcg_temp_free_i64(tmp2); | |
1560 | tcg_temp_free_i64(tmp3); | |
1561 | tcg_temp_free_i64(tmp4); | |
1562 | break; | |
1563 | case 0x9: /* SG R1,D2(X2,B2) [RXY] */ | |
1564 | case 0xb: /* SLG R1,D2(X2,B2) [RXY] */ | |
1565 | case 0x19: /* SGF R1,D2(X2,B2) [RXY] */ | |
1566 | case 0x1b: /* SLGF R1,D2(X2,B2) [RXY] */ | |
1567 | tmp2 = tcg_temp_new_i64(); | |
1568 | if (op == 0x19) { | |
1569 | tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s)); | |
1570 | } else if (op == 0x1b) { | |
1571 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1572 | } else { | |
1573 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1574 | } | |
1575 | tmp4 = load_reg(r1); | |
1576 | tmp3 = tcg_temp_new_i64(); | |
1577 | tcg_gen_sub_i64(tmp3, tmp4, tmp2); | |
1578 | store_reg(r1, tmp3); | |
1579 | switch (op) { | |
1580 | case 0x9: | |
1581 | case 0x19: | |
1582 | set_cc_sub64(s, tmp4, tmp2, tmp3); | |
1583 | break; | |
1584 | case 0xb: | |
1585 | case 0x1b: | |
1586 | set_cc_subu64(s, tmp4, tmp2, tmp3); | |
1587 | break; | |
1588 | default: | |
1589 | tcg_abort(); | |
1590 | } | |
1591 | tcg_temp_free_i64(tmp2); | |
1592 | tcg_temp_free_i64(tmp3); | |
1593 | tcg_temp_free_i64(tmp4); | |
1594 | break; | |
1595 | case 0xf: /* LRVG R1,D2(X2,B2) [RXE] */ | |
1596 | tmp2 = tcg_temp_new_i64(); | |
1597 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1598 | tcg_gen_bswap64_i64(tmp2, tmp2); | |
1599 | store_reg(r1, tmp2); | |
1600 | tcg_temp_free_i64(tmp2); | |
1601 | break; | |
1602 | case 0x14: /* LGF R1,D2(X2,B2) [RXY] */ | |
1603 | case 0x16: /* LLGF R1,D2(X2,B2) [RXY] */ | |
1604 | tmp2 = tcg_temp_new_i64(); | |
1605 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1606 | if (op == 0x14) { | |
1607 | tcg_gen_ext32s_i64(tmp2, tmp2); | |
1608 | } | |
1609 | store_reg(r1, tmp2); | |
1610 | tcg_temp_free_i64(tmp2); | |
1611 | break; | |
1612 | case 0x15: /* LGH R1,D2(X2,B2) [RXY] */ | |
1613 | tmp2 = tcg_temp_new_i64(); | |
1614 | tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s)); | |
1615 | store_reg(r1, tmp2); | |
1616 | tcg_temp_free_i64(tmp2); | |
1617 | break; | |
1618 | case 0x17: /* LLGT R1,D2(X2,B2) [RXY] */ | |
1619 | tmp2 = tcg_temp_new_i64(); | |
1620 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1621 | tcg_gen_andi_i64(tmp2, tmp2, 0x7fffffffULL); | |
1622 | store_reg(r1, tmp2); | |
1623 | tcg_temp_free_i64(tmp2); | |
1624 | break; | |
1625 | case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */ | |
1626 | tmp2 = tcg_temp_new_i64(); | |
1627 | tmp32_1 = tcg_temp_new_i32(); | |
1628 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1629 | tcg_gen_trunc_i64_i32(tmp32_1, tmp2); | |
1630 | tcg_temp_free_i64(tmp2); | |
1631 | tcg_gen_bswap32_i32(tmp32_1, tmp32_1); | |
1632 | store_reg32(r1, tmp32_1); | |
1633 | tcg_temp_free_i32(tmp32_1); | |
1634 | break; | |
1635 | case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */ | |
1636 | tmp2 = tcg_temp_new_i64(); | |
1637 | tmp32_1 = tcg_temp_new_i32(); | |
1638 | tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s)); | |
1639 | tcg_gen_trunc_i64_i32(tmp32_1, tmp2); | |
1640 | tcg_temp_free_i64(tmp2); | |
1641 | tcg_gen_bswap16_i32(tmp32_1, tmp32_1); | |
1642 | store_reg16(r1, tmp32_1); | |
1643 | tcg_temp_free_i32(tmp32_1); | |
1644 | break; | |
1645 | case 0x20: /* CG R1,D2(X2,B2) [RXY] */ | |
1646 | case 0x21: /* CLG R1,D2(X2,B2) */ | |
1647 | case 0x30: /* CGF R1,D2(X2,B2) [RXY] */ | |
1648 | case 0x31: /* CLGF R1,D2(X2,B2) [RXY] */ | |
1649 | tmp2 = tcg_temp_new_i64(); | |
1650 | switch (op) { | |
1651 | case 0x20: | |
1652 | case 0x21: | |
1653 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1654 | break; | |
1655 | case 0x30: | |
1656 | tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s)); | |
1657 | break; | |
1658 | case 0x31: | |
1659 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1660 | break; | |
1661 | default: | |
1662 | tcg_abort(); | |
1663 | } | |
1664 | switch (op) { | |
1665 | case 0x20: | |
1666 | case 0x30: | |
1667 | cmp_s64(s, regs[r1], tmp2); | |
1668 | break; | |
1669 | case 0x21: | |
1670 | case 0x31: | |
1671 | cmp_u64(s, regs[r1], tmp2); | |
1672 | break; | |
1673 | default: | |
1674 | tcg_abort(); | |
1675 | } | |
1676 | tcg_temp_free_i64(tmp2); | |
1677 | break; | |
1678 | case 0x24: /* stg r1, d2(x2,b2) */ | |
1679 | tcg_gen_qemu_st64(regs[r1], addr, get_mem_index(s)); | |
1680 | break; | |
1681 | case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */ | |
1682 | tmp32_1 = load_reg32(r1); | |
1683 | tmp2 = tcg_temp_new_i64(); | |
1684 | tcg_gen_bswap32_i32(tmp32_1, tmp32_1); | |
1685 | tcg_gen_extu_i32_i64(tmp2, tmp32_1); | |
1686 | tcg_temp_free_i32(tmp32_1); | |
1687 | tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s)); | |
1688 | tcg_temp_free_i64(tmp2); | |
1689 | break; | |
1690 | case 0x50: /* STY R1,D2(X2,B2) [RXY] */ | |
1691 | tmp32_1 = load_reg32(r1); | |
1692 | tmp2 = tcg_temp_new_i64(); | |
1693 | tcg_gen_extu_i32_i64(tmp2, tmp32_1); | |
1694 | tcg_temp_free_i32(tmp32_1); | |
1695 | tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s)); | |
1696 | tcg_temp_free_i64(tmp2); | |
1697 | break; | |
1698 | case 0x57: /* XY R1,D2(X2,B2) [RXY] */ | |
1699 | tmp32_1 = load_reg32(r1); | |
1700 | tmp32_2 = tcg_temp_new_i32(); | |
1701 | tmp2 = tcg_temp_new_i64(); | |
1702 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1703 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
1704 | tcg_temp_free_i64(tmp2); | |
1705 | tcg_gen_xor_i32(tmp32_2, tmp32_1, tmp32_2); | |
1706 | store_reg32(r1, tmp32_2); | |
1707 | set_cc_nz_u32(s, tmp32_2); | |
1708 | tcg_temp_free_i32(tmp32_1); | |
1709 | tcg_temp_free_i32(tmp32_2); | |
1710 | break; | |
1711 | case 0x58: /* LY R1,D2(X2,B2) [RXY] */ | |
1712 | tmp3 = tcg_temp_new_i64(); | |
1713 | tcg_gen_qemu_ld32u(tmp3, addr, get_mem_index(s)); | |
1714 | store_reg32_i64(r1, tmp3); | |
1715 | tcg_temp_free_i64(tmp3); | |
1716 | break; | |
1717 | case 0x5a: /* AY R1,D2(X2,B2) [RXY] */ | |
1718 | case 0x5b: /* SY R1,D2(X2,B2) [RXY] */ | |
1719 | tmp32_1 = load_reg32(r1); | |
1720 | tmp32_2 = tcg_temp_new_i32(); | |
1721 | tmp32_3 = tcg_temp_new_i32(); | |
1722 | tmp2 = tcg_temp_new_i64(); | |
1723 | tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s)); | |
1724 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
1725 | tcg_temp_free_i64(tmp2); | |
1726 | switch (op) { | |
1727 | case 0x5a: | |
1728 | tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2); | |
1729 | break; | |
1730 | case 0x5b: | |
1731 | tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2); | |
1732 | break; | |
1733 | default: | |
1734 | tcg_abort(); | |
1735 | } | |
1736 | store_reg32(r1, tmp32_3); | |
1737 | switch (op) { | |
1738 | case 0x5a: | |
1739 | set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3); | |
1740 | break; | |
1741 | case 0x5b: | |
1742 | set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3); | |
1743 | break; | |
1744 | default: | |
1745 | tcg_abort(); | |
1746 | } | |
1747 | tcg_temp_free_i32(tmp32_1); | |
1748 | tcg_temp_free_i32(tmp32_2); | |
1749 | tcg_temp_free_i32(tmp32_3); | |
1750 | break; | |
1751 | case 0x71: /* LAY R1,D2(X2,B2) [RXY] */ | |
1752 | store_reg(r1, addr); | |
1753 | break; | |
1754 | case 0x72: /* STCY R1,D2(X2,B2) [RXY] */ | |
1755 | tmp32_1 = load_reg32(r1); | |
1756 | tmp2 = tcg_temp_new_i64(); | |
1757 | tcg_gen_ext_i32_i64(tmp2, tmp32_1); | |
1758 | tcg_gen_qemu_st8(tmp2, addr, get_mem_index(s)); | |
1759 | tcg_temp_free_i32(tmp32_1); | |
1760 | tcg_temp_free_i64(tmp2); | |
1761 | break; | |
1762 | case 0x73: /* ICY R1,D2(X2,B2) [RXY] */ | |
1763 | tmp3 = tcg_temp_new_i64(); | |
1764 | tcg_gen_qemu_ld8u(tmp3, addr, get_mem_index(s)); | |
1765 | store_reg8(r1, tmp3); | |
1766 | tcg_temp_free_i64(tmp3); | |
1767 | break; | |
1768 | case 0x76: /* LB R1,D2(X2,B2) [RXY] */ | |
1769 | case 0x77: /* LGB R1,D2(X2,B2) [RXY] */ | |
1770 | tmp2 = tcg_temp_new_i64(); | |
1771 | tcg_gen_qemu_ld8s(tmp2, addr, get_mem_index(s)); | |
1772 | switch (op) { | |
1773 | case 0x76: | |
1774 | tcg_gen_ext8s_i64(tmp2, tmp2); | |
1775 | store_reg32_i64(r1, tmp2); | |
1776 | break; | |
1777 | case 0x77: | |
1778 | tcg_gen_ext8s_i64(tmp2, tmp2); | |
1779 | store_reg(r1, tmp2); | |
1780 | break; | |
1781 | default: | |
1782 | tcg_abort(); | |
1783 | } | |
1784 | tcg_temp_free_i64(tmp2); | |
1785 | break; | |
1786 | case 0x78: /* LHY R1,D2(X2,B2) [RXY] */ | |
1787 | tmp2 = tcg_temp_new_i64(); | |
1788 | tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s)); | |
1789 | store_reg32_i64(r1, tmp2); | |
1790 | tcg_temp_free_i64(tmp2); | |
1791 | break; | |
1792 | case 0x80: /* NG R1,D2(X2,B2) [RXY] */ | |
1793 | case 0x81: /* OG R1,D2(X2,B2) [RXY] */ | |
1794 | case 0x82: /* XG R1,D2(X2,B2) [RXY] */ | |
1795 | tmp3 = tcg_temp_new_i64(); | |
1796 | tcg_gen_qemu_ld64(tmp3, addr, get_mem_index(s)); | |
1797 | switch (op) { | |
1798 | case 0x80: | |
1799 | tcg_gen_and_i64(regs[r1], regs[r1], tmp3); | |
1800 | break; | |
1801 | case 0x81: | |
1802 | tcg_gen_or_i64(regs[r1], regs[r1], tmp3); | |
1803 | break; | |
1804 | case 0x82: | |
1805 | tcg_gen_xor_i64(regs[r1], regs[r1], tmp3); | |
1806 | break; | |
1807 | default: | |
1808 | tcg_abort(); | |
1809 | } | |
1810 | set_cc_nz_u64(s, regs[r1]); | |
1811 | tcg_temp_free_i64(tmp3); | |
1812 | break; | |
1813 | case 0x86: /* MLG R1,D2(X2,B2) [RXY] */ | |
1814 | tmp2 = tcg_temp_new_i64(); | |
1815 | tmp32_1 = tcg_const_i32(r1); | |
1816 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1817 | gen_helper_mlg(tmp32_1, tmp2); | |
1818 | tcg_temp_free_i64(tmp2); | |
1819 | tcg_temp_free_i32(tmp32_1); | |
1820 | break; | |
1821 | case 0x87: /* DLG R1,D2(X2,B2) [RXY] */ | |
1822 | tmp2 = tcg_temp_new_i64(); | |
1823 | tmp32_1 = tcg_const_i32(r1); | |
1824 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1825 | gen_helper_dlg(tmp32_1, tmp2); | |
1826 | tcg_temp_free_i64(tmp2); | |
1827 | tcg_temp_free_i32(tmp32_1); | |
1828 | break; | |
1829 | case 0x88: /* ALCG R1,D2(X2,B2) [RXY] */ | |
1830 | tmp2 = tcg_temp_new_i64(); | |
1831 | tmp3 = tcg_temp_new_i64(); | |
1832 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1833 | /* XXX possible optimization point */ | |
1834 | gen_op_calc_cc(s); | |
1835 | tcg_gen_extu_i32_i64(tmp3, cc_op); | |
1836 | tcg_gen_shri_i64(tmp3, tmp3, 1); | |
1837 | tcg_gen_andi_i64(tmp3, tmp3, 1); | |
1838 | tcg_gen_add_i64(tmp3, tmp2, tmp3); | |
1839 | tcg_gen_add_i64(tmp3, regs[r1], tmp3); | |
1840 | store_reg(r1, tmp3); | |
1841 | set_cc_addu64(s, regs[r1], tmp2, tmp3); | |
1842 | tcg_temp_free_i64(tmp2); | |
1843 | tcg_temp_free_i64(tmp3); | |
1844 | break; | |
1845 | case 0x89: /* SLBG R1,D2(X2,B2) [RXY] */ | |
1846 | tmp2 = tcg_temp_new_i64(); | |
1847 | tmp32_1 = tcg_const_i32(r1); | |
1848 | tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); | |
1849 | /* XXX possible optimization point */ | |
1850 | gen_op_calc_cc(s); | |
1851 | gen_helper_slbg(cc_op, cc_op, tmp32_1, regs[r1], tmp2); | |
1852 | set_cc_static(s); | |
1853 | tcg_temp_free_i64(tmp2); | |
1854 | tcg_temp_free_i32(tmp32_1); | |
1855 | break; | |
1856 | case 0x90: /* LLGC R1,D2(X2,B2) [RXY] */ | |
1857 | tcg_gen_qemu_ld8u(regs[r1], addr, get_mem_index(s)); | |
1858 | break; | |
1859 | case 0x91: /* LLGH R1,D2(X2,B2) [RXY] */ | |
1860 | tcg_gen_qemu_ld16u(regs[r1], addr, get_mem_index(s)); | |
1861 | break; | |
1862 | case 0x94: /* LLC R1,D2(X2,B2) [RXY] */ | |
1863 | tmp2 = tcg_temp_new_i64(); | |
1864 | tcg_gen_qemu_ld8u(tmp2, addr, get_mem_index(s)); | |
1865 | store_reg32_i64(r1, tmp2); | |
1866 | tcg_temp_free_i64(tmp2); | |
1867 | break; | |
1868 | case 0x95: /* LLH R1,D2(X2,B2) [RXY] */ | |
1869 | tmp2 = tcg_temp_new_i64(); | |
1870 | tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s)); | |
1871 | store_reg32_i64(r1, tmp2); | |
1872 | tcg_temp_free_i64(tmp2); | |
1873 | break; | |
1874 | case 0x96: /* ML R1,D2(X2,B2) [RXY] */ | |
1875 | tmp2 = tcg_temp_new_i64(); | |
1876 | tmp3 = load_reg((r1 + 1) & 15); | |
1877 | tcg_gen_ext32u_i64(tmp3, tmp3); | |
1878 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1879 | tcg_gen_mul_i64(tmp2, tmp2, tmp3); | |
1880 | store_reg32_i64((r1 + 1) & 15, tmp2); | |
1881 | tcg_gen_shri_i64(tmp2, tmp2, 32); | |
1882 | store_reg32_i64(r1, tmp2); | |
1883 | tcg_temp_free_i64(tmp2); | |
1884 | tcg_temp_free_i64(tmp3); | |
1885 | break; | |
1886 | case 0x97: /* DL R1,D2(X2,B2) [RXY] */ | |
1887 | /* reg(r1) = reg(r1, r1+1) % ld32(addr) */ | |
1888 | /* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */ | |
1889 | tmp = load_reg(r1); | |
1890 | tmp2 = tcg_temp_new_i64(); | |
1891 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1892 | tmp3 = load_reg((r1 + 1) & 15); | |
1893 | tcg_gen_ext32u_i64(tmp2, tmp2); | |
1894 | tcg_gen_ext32u_i64(tmp3, tmp3); | |
1895 | tcg_gen_shli_i64(tmp, tmp, 32); | |
1896 | tcg_gen_or_i64(tmp, tmp, tmp3); | |
1897 | ||
1898 | tcg_gen_rem_i64(tmp3, tmp, tmp2); | |
1899 | tcg_gen_div_i64(tmp, tmp, tmp2); | |
1900 | store_reg32_i64((r1 + 1) & 15, tmp); | |
1901 | store_reg32_i64(r1, tmp3); | |
1902 | tcg_temp_free_i64(tmp); | |
1903 | tcg_temp_free_i64(tmp2); | |
1904 | tcg_temp_free_i64(tmp3); | |
1905 | break; | |
1906 | case 0x98: /* ALC R1,D2(X2,B2) [RXY] */ | |
1907 | tmp2 = tcg_temp_new_i64(); | |
1908 | tmp32_1 = load_reg32(r1); | |
1909 | tmp32_2 = tcg_temp_new_i32(); | |
1910 | tmp32_3 = tcg_temp_new_i32(); | |
1911 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1912 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
1913 | /* XXX possible optimization point */ | |
1914 | gen_op_calc_cc(s); | |
1915 | gen_helper_addc_u32(tmp32_3, cc_op, tmp32_1, tmp32_2); | |
1916 | set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3); | |
1917 | store_reg32(r1, tmp32_3); | |
1918 | tcg_temp_free_i64(tmp2); | |
1919 | tcg_temp_free_i32(tmp32_1); | |
1920 | tcg_temp_free_i32(tmp32_2); | |
1921 | tcg_temp_free_i32(tmp32_3); | |
1922 | break; | |
1923 | case 0x99: /* SLB R1,D2(X2,B2) [RXY] */ | |
1924 | tmp2 = tcg_temp_new_i64(); | |
1925 | tmp32_1 = tcg_const_i32(r1); | |
1926 | tmp32_2 = tcg_temp_new_i32(); | |
1927 | tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); | |
1928 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
1929 | /* XXX possible optimization point */ | |
1930 | gen_op_calc_cc(s); | |
1931 | gen_helper_slb(cc_op, cc_op, tmp32_1, tmp32_2); | |
1932 | set_cc_static(s); | |
1933 | tcg_temp_free_i64(tmp2); | |
1934 | tcg_temp_free_i32(tmp32_1); | |
1935 | tcg_temp_free_i32(tmp32_2); | |
1936 | break; | |
1937 | default: | |
1938 | LOG_DISAS("illegal e3 operation 0x%x\n", op); | |
1939 | gen_illegal_opcode(s, 3); | |
1940 | break; | |
1941 | } | |
1942 | tcg_temp_free_i64(addr); | |
1943 | } | |
1944 | ||
1945 | #ifndef CONFIG_USER_ONLY | |
1946 | static void disas_e5(DisasContext* s, uint64_t insn) | |
1947 | { | |
1948 | TCGv_i64 tmp, tmp2; | |
1949 | int op = (insn >> 32) & 0xff; | |
1950 | ||
1951 | tmp = get_address(s, 0, (insn >> 28) & 0xf, (insn >> 16) & 0xfff); | |
1952 | tmp2 = get_address(s, 0, (insn >> 12) & 0xf, insn & 0xfff); | |
1953 | ||
1954 | LOG_DISAS("disas_e5: insn %" PRIx64 "\n", insn); | |
1955 | switch (op) { | |
1956 | case 0x01: /* TPROT D1(B1),D2(B2) [SSE] */ | |
1957 | /* Test Protection */ | |
1958 | potential_page_fault(s); | |
1959 | gen_helper_tprot(cc_op, tmp, tmp2); | |
1960 | set_cc_static(s); | |
1961 | break; | |
1962 | default: | |
1963 | LOG_DISAS("illegal e5 operation 0x%x\n", op); | |
1964 | gen_illegal_opcode(s, 3); | |
1965 | break; | |
1966 | } | |
1967 | ||
1968 | tcg_temp_free_i64(tmp); | |
1969 | tcg_temp_free_i64(tmp2); | |
1970 | } | |
1971 | #endif | |
1972 | ||
1973 | static void disas_eb(DisasContext *s, int op, int r1, int r3, int b2, int d2) | |
1974 | { | |
1975 | TCGv_i64 tmp, tmp2, tmp3, tmp4; | |
1976 | TCGv_i32 tmp32_1, tmp32_2; | |
1977 | int i, stm_len; | |
1978 | int ilc = 3; | |
1979 | ||
1980 | LOG_DISAS("disas_eb: op 0x%x r1 %d r3 %d b2 %d d2 0x%x\n", | |
1981 | op, r1, r3, b2, d2); | |
1982 | switch (op) { | |
1983 | case 0xc: /* SRLG R1,R3,D2(B2) [RSY] */ | |
1984 | case 0xd: /* SLLG R1,R3,D2(B2) [RSY] */ | |
1985 | case 0xa: /* SRAG R1,R3,D2(B2) [RSY] */ | |
1986 | case 0xb: /* SLAG R1,R3,D2(B2) [RSY] */ | |
1987 | case 0x1c: /* RLLG R1,R3,D2(B2) [RSY] */ | |
1988 | if (b2) { | |
1989 | tmp = get_address(s, 0, b2, d2); | |
1990 | tcg_gen_andi_i64(tmp, tmp, 0x3f); | |
1991 | } else { | |
1992 | tmp = tcg_const_i64(d2 & 0x3f); | |
1993 | } | |
1994 | switch (op) { | |
1995 | case 0xc: | |
1996 | tcg_gen_shr_i64(regs[r1], regs[r3], tmp); | |
1997 | break; | |
1998 | case 0xd: | |
1999 | tcg_gen_shl_i64(regs[r1], regs[r3], tmp); | |
2000 | break; | |
2001 | case 0xa: | |
2002 | tcg_gen_sar_i64(regs[r1], regs[r3], tmp); | |
2003 | break; | |
2004 | case 0xb: | |
2005 | tmp2 = tcg_temp_new_i64(); | |
2006 | tmp3 = tcg_temp_new_i64(); | |
2007 | gen_op_update2_cc_i64(s, CC_OP_SLAG, regs[r3], tmp); | |
2008 | tcg_gen_shl_i64(tmp2, regs[r3], tmp); | |
2009 | /* override sign bit with source sign */ | |
2010 | tcg_gen_andi_i64(tmp2, tmp2, ~0x8000000000000000ULL); | |
2011 | tcg_gen_andi_i64(tmp3, regs[r3], 0x8000000000000000ULL); | |
2012 | tcg_gen_or_i64(regs[r1], tmp2, tmp3); | |
2013 | tcg_temp_free_i64(tmp2); | |
2014 | tcg_temp_free_i64(tmp3); | |
2015 | break; | |
2016 | case 0x1c: | |
2017 | tcg_gen_rotl_i64(regs[r1], regs[r3], tmp); | |
2018 | break; | |
2019 | default: | |
2020 | tcg_abort(); | |
2021 | break; | |
2022 | } | |
2023 | if (op == 0xa) { | |
2024 | set_cc_s64(s, regs[r1]); | |
2025 | } | |
2026 | tcg_temp_free_i64(tmp); | |
2027 | break; | |
2028 | case 0x1d: /* RLL R1,R3,D2(B2) [RSY] */ | |
2029 | if (b2) { | |
2030 | tmp = get_address(s, 0, b2, d2); | |
2031 | tcg_gen_andi_i64(tmp, tmp, 0x3f); | |
2032 | } else { | |
2033 | tmp = tcg_const_i64(d2 & 0x3f); | |
2034 | } | |
2035 | tmp32_1 = tcg_temp_new_i32(); | |
2036 | tmp32_2 = load_reg32(r3); | |
2037 | tcg_gen_trunc_i64_i32(tmp32_1, tmp); | |
2038 | switch (op) { | |
2039 | case 0x1d: | |
2040 | tcg_gen_rotl_i32(tmp32_1, tmp32_2, tmp32_1); | |
2041 | break; | |
2042 | default: | |
2043 | tcg_abort(); | |
2044 | break; | |
2045 | } | |
2046 | store_reg32(r1, tmp32_1); | |
2047 | tcg_temp_free_i64(tmp); | |
2048 | tcg_temp_free_i32(tmp32_1); | |
2049 | tcg_temp_free_i32(tmp32_2); | |
2050 | break; | |
2051 | case 0x4: /* LMG R1,R3,D2(B2) [RSE] */ | |
2052 | case 0x24: /* STMG R1,R3,D2(B2) [RSE] */ | |
2053 | stm_len = 8; | |
2054 | goto do_mh; | |
2055 | case 0x26: /* STMH R1,R3,D2(B2) [RSE] */ | |
2056 | case 0x96: /* LMH R1,R3,D2(B2) [RSE] */ | |
2057 | stm_len = 4; | |
2058 | do_mh: | |
2059 | /* Apparently, unrolling lmg/stmg of any size gains performance - | |
2060 | even for very long ones... */ | |
2061 | tmp = get_address(s, 0, b2, d2); | |
2062 | tmp3 = tcg_const_i64(stm_len); | |
be82ee2a | 2063 | tmp4 = tcg_const_i64(op == 0x26 ? 32 : 4); |
e023e832 AG |
2064 | for (i = r1;; i = (i + 1) % 16) { |
2065 | switch (op) { | |
2066 | case 0x4: | |
2067 | tcg_gen_qemu_ld64(regs[i], tmp, get_mem_index(s)); | |
2068 | break; | |
2069 | case 0x96: | |
2070 | tmp2 = tcg_temp_new_i64(); | |
2071 | #if HOST_LONG_BITS == 32 | |
2072 | tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); | |
2073 | tcg_gen_trunc_i64_i32(TCGV_HIGH(regs[i]), tmp2); | |
2074 | #else | |
e023e832 | 2075 | tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); |
be82ee2a | 2076 | tcg_gen_shl_i64(tmp2, tmp2, tmp4); |
e023e832 AG |
2077 | tcg_gen_ext32u_i64(regs[i], regs[i]); |
2078 | tcg_gen_or_i64(regs[i], regs[i], tmp2); | |
2079 | #endif | |
2080 | tcg_temp_free_i64(tmp2); | |
2081 | break; | |
2082 | case 0x24: | |
2083 | tcg_gen_qemu_st64(regs[i], tmp, get_mem_index(s)); | |
2084 | break; | |
2085 | case 0x26: | |
2086 | tmp2 = tcg_temp_new_i64(); | |
2087 | tcg_gen_shr_i64(tmp2, regs[i], tmp4); | |
2088 | tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s)); | |
2089 | tcg_temp_free_i64(tmp2); | |
2090 | break; | |
2091 | default: | |
2092 | tcg_abort(); | |
2093 | } | |
2094 | if (i == r3) { | |
2095 | break; | |
2096 | } | |
2097 | tcg_gen_add_i64(tmp, tmp, tmp3); | |
2098 | } | |
2099 | tcg_temp_free_i64(tmp); | |
21de37a7 | 2100 | tcg_temp_free_i64(tmp3); |
e023e832 AG |
2101 | tcg_temp_free_i64(tmp4); |
2102 | break; | |
2103 | case 0x2c: /* STCMH R1,M3,D2(B2) [RSY] */ | |
2104 | tmp = get_address(s, 0, b2, d2); | |
2105 | tmp32_1 = tcg_const_i32(r1); | |
2106 | tmp32_2 = tcg_const_i32(r3); | |
2107 | potential_page_fault(s); | |
2108 | gen_helper_stcmh(tmp32_1, tmp, tmp32_2); | |
2109 | tcg_temp_free_i64(tmp); | |
2110 | tcg_temp_free_i32(tmp32_1); | |
2111 | tcg_temp_free_i32(tmp32_2); | |
2112 | break; | |
2113 | #ifndef CONFIG_USER_ONLY | |
2114 | case 0x2f: /* LCTLG R1,R3,D2(B2) [RSE] */ | |
2115 | /* Load Control */ | |
2116 | check_privileged(s, ilc); | |
2117 | tmp = get_address(s, 0, b2, d2); | |
2118 | tmp32_1 = tcg_const_i32(r1); | |
2119 | tmp32_2 = tcg_const_i32(r3); | |
2120 | potential_page_fault(s); | |
2121 | gen_helper_lctlg(tmp32_1, tmp, tmp32_2); | |
2122 | tcg_temp_free_i64(tmp); | |
2123 | tcg_temp_free_i32(tmp32_1); | |
2124 | tcg_temp_free_i32(tmp32_2); | |
2125 | break; | |
2126 | case 0x25: /* STCTG R1,R3,D2(B2) [RSE] */ | |
2127 | /* Store Control */ | |
2128 | check_privileged(s, ilc); | |
2129 | tmp = get_address(s, 0, b2, d2); | |
2130 | tmp32_1 = tcg_const_i32(r1); | |
2131 | tmp32_2 = tcg_const_i32(r3); | |
2132 | potential_page_fault(s); | |
2133 | gen_helper_stctg(tmp32_1, tmp, tmp32_2); | |
2134 | tcg_temp_free_i64(tmp); | |
2135 | tcg_temp_free_i32(tmp32_1); | |
2136 | tcg_temp_free_i32(tmp32_2); | |
2137 | break; | |
2138 | #endif | |
2139 | case 0x30: /* CSG R1,R3,D2(B2) [RSY] */ | |
2140 | tmp = get_address(s, 0, b2, d2); | |
2141 | tmp32_1 = tcg_const_i32(r1); | |
2142 | tmp32_2 = tcg_const_i32(r3); | |
2143 | potential_page_fault(s); | |
2144 | /* XXX rewrite in tcg */ | |
2145 | gen_helper_csg(cc_op, tmp32_1, tmp, tmp32_2); | |
2146 | set_cc_static(s); | |
2147 | tcg_temp_free_i64(tmp); | |
2148 | tcg_temp_free_i32(tmp32_1); | |
2149 | tcg_temp_free_i32(tmp32_2); | |
2150 | break; | |
2151 | case 0x3e: /* CDSG R1,R3,D2(B2) [RSY] */ | |
2152 | tmp = get_address(s, 0, b2, d2); | |
2153 | tmp32_1 = tcg_const_i32(r1); | |
2154 | tmp32_2 = tcg_const_i32(r3); | |
2155 | potential_page_fault(s); | |
2156 | /* XXX rewrite in tcg */ | |
2157 | gen_helper_cdsg(cc_op, tmp32_1, tmp, tmp32_2); | |
2158 | set_cc_static(s); | |
2159 | tcg_temp_free_i64(tmp); | |
2160 | tcg_temp_free_i32(tmp32_1); | |
2161 | tcg_temp_free_i32(tmp32_2); | |
2162 | break; | |
2163 | case 0x51: /* TMY D1(B1),I2 [SIY] */ | |
2164 | tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */ | |
2165 | tmp2 = tcg_const_i64((r1 << 4) | r3); | |
2166 | tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s)); | |
2167 | /* yes, this is a 32 bit operation with 64 bit tcg registers, because | |
2168 | that incurs less conversions */ | |
2169 | cmp_64(s, tmp, tmp2, CC_OP_TM_32); | |
2170 | tcg_temp_free_i64(tmp); | |
2171 | tcg_temp_free_i64(tmp2); | |
2172 | break; | |
2173 | case 0x52: /* MVIY D1(B1),I2 [SIY] */ | |
2174 | tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */ | |
2175 | tmp2 = tcg_const_i64((r1 << 4) | r3); | |
2176 | tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s)); | |
2177 | tcg_temp_free_i64(tmp); | |
2178 | tcg_temp_free_i64(tmp2); | |
2179 | break; | |
2180 | case 0x55: /* CLIY D1(B1),I2 [SIY] */ | |
2181 | tmp3 = get_address(s, 0, b2, d2); /* SIY -> this is the 1st operand */ | |
2182 | tmp = tcg_temp_new_i64(); | |
2183 | tmp32_1 = tcg_temp_new_i32(); | |
2184 | tcg_gen_qemu_ld8u(tmp, tmp3, get_mem_index(s)); | |
2185 | tcg_gen_trunc_i64_i32(tmp32_1, tmp); | |
2186 | cmp_u32c(s, tmp32_1, (r1 << 4) | r3); | |
2187 | tcg_temp_free_i64(tmp); | |
2188 | tcg_temp_free_i64(tmp3); | |
2189 | tcg_temp_free_i32(tmp32_1); | |
2190 | break; | |
2191 | case 0x80: /* ICMH R1,M3,D2(B2) [RSY] */ | |
2192 | tmp = get_address(s, 0, b2, d2); | |
2193 | tmp32_1 = tcg_const_i32(r1); | |
2194 | tmp32_2 = tcg_const_i32(r3); | |
2195 | potential_page_fault(s); | |
2196 | /* XXX split CC calculation out */ | |
2197 | gen_helper_icmh(cc_op, tmp32_1, tmp, tmp32_2); | |
2198 | set_cc_static(s); | |
2199 | tcg_temp_free_i64(tmp); | |
2200 | tcg_temp_free_i32(tmp32_1); | |
2201 | tcg_temp_free_i32(tmp32_2); | |
2202 | break; | |
2203 | default: | |
2204 | LOG_DISAS("illegal eb operation 0x%x\n", op); | |
2205 | gen_illegal_opcode(s, ilc); | |
2206 | break; | |
2207 | } | |
2208 | } | |
2209 | ||
2210 | static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2, | |
2211 | int r1b) | |
2212 | { | |
2213 | TCGv_i32 tmp_r1, tmp32; | |
2214 | TCGv_i64 addr, tmp; | |
2215 | addr = get_address(s, x2, b2, d2); | |
2216 | tmp_r1 = tcg_const_i32(r1); | |
2217 | switch (op) { | |
2218 | case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */ | |
2219 | potential_page_fault(s); | |
2220 | gen_helper_lxdb(tmp_r1, addr); | |
2221 | break; | |
2222 | case 0x9: /* CEB R1,D2(X2,B2) [RXE] */ | |
2223 | tmp = tcg_temp_new_i64(); | |
2224 | tmp32 = load_freg32(r1); | |
2225 | tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s)); | |
2226 | set_cc_cmp_f32_i64(s, tmp32, tmp); | |
2227 | tcg_temp_free_i64(tmp); | |
2228 | tcg_temp_free_i32(tmp32); | |
2229 | break; | |
2230 | case 0xa: /* AEB R1,D2(X2,B2) [RXE] */ | |
2231 | tmp = tcg_temp_new_i64(); | |
2232 | tmp32 = tcg_temp_new_i32(); | |
2233 | tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s)); | |
2234 | tcg_gen_trunc_i64_i32(tmp32, tmp); | |
2235 | gen_helper_aeb(tmp_r1, tmp32); | |
2236 | tcg_temp_free_i64(tmp); | |
2237 | tcg_temp_free_i32(tmp32); | |
2238 | ||
2239 | tmp32 = load_freg32(r1); | |
2240 | set_cc_nz_f32(s, tmp32); | |
2241 | tcg_temp_free_i32(tmp32); | |
2242 | break; | |
2243 | case 0xb: /* SEB R1,D2(X2,B2) [RXE] */ | |
2244 | tmp = tcg_temp_new_i64(); | |
2245 | tmp32 = tcg_temp_new_i32(); | |
2246 | tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s)); | |
2247 | tcg_gen_trunc_i64_i32(tmp32, tmp); | |
2248 | gen_helper_seb(tmp_r1, tmp32); | |
2249 | tcg_temp_free_i64(tmp); | |
2250 | tcg_temp_free_i32(tmp32); | |
2251 | ||
2252 | tmp32 = load_freg32(r1); | |
2253 | set_cc_nz_f32(s, tmp32); | |
2254 | tcg_temp_free_i32(tmp32); | |
2255 | break; | |
2256 | case 0xd: /* DEB R1,D2(X2,B2) [RXE] */ | |
2257 | tmp = tcg_temp_new_i64(); | |
2258 | tmp32 = tcg_temp_new_i32(); | |
2259 | tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s)); | |
2260 | tcg_gen_trunc_i64_i32(tmp32, tmp); | |
2261 | gen_helper_deb(tmp_r1, tmp32); | |
2262 | tcg_temp_free_i64(tmp); | |
2263 | tcg_temp_free_i32(tmp32); | |
2264 | break; | |
2265 | case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */ | |
2266 | potential_page_fault(s); | |
2267 | gen_helper_tceb(cc_op, tmp_r1, addr); | |
2268 | set_cc_static(s); | |
2269 | break; | |
2270 | case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */ | |
2271 | potential_page_fault(s); | |
2272 | gen_helper_tcdb(cc_op, tmp_r1, addr); | |
2273 | set_cc_static(s); | |
2274 | break; | |
2275 | case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */ | |
2276 | potential_page_fault(s); | |
2277 | gen_helper_tcxb(cc_op, tmp_r1, addr); | |
2278 | set_cc_static(s); | |
2279 | break; | |
2280 | case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */ | |
2281 | tmp = tcg_temp_new_i64(); | |
2282 | tmp32 = tcg_temp_new_i32(); | |
2283 | tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s)); | |
2284 | tcg_gen_trunc_i64_i32(tmp32, tmp); | |
2285 | gen_helper_meeb(tmp_r1, tmp32); | |
2286 | tcg_temp_free_i64(tmp); | |
2287 | tcg_temp_free_i32(tmp32); | |
2288 | break; | |
2289 | case 0x19: /* CDB R1,D2(X2,B2) [RXE] */ | |
2290 | potential_page_fault(s); | |
2291 | gen_helper_cdb(cc_op, tmp_r1, addr); | |
2292 | set_cc_static(s); | |
2293 | break; | |
2294 | case 0x1a: /* ADB R1,D2(X2,B2) [RXE] */ | |
2295 | potential_page_fault(s); | |
2296 | gen_helper_adb(cc_op, tmp_r1, addr); | |
2297 | set_cc_static(s); | |
2298 | break; | |
2299 | case 0x1b: /* SDB R1,D2(X2,B2) [RXE] */ | |
2300 | potential_page_fault(s); | |
2301 | gen_helper_sdb(cc_op, tmp_r1, addr); | |
2302 | set_cc_static(s); | |
2303 | break; | |
2304 | case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */ | |
2305 | potential_page_fault(s); | |
2306 | gen_helper_mdb(tmp_r1, addr); | |
2307 | break; | |
2308 | case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */ | |
2309 | potential_page_fault(s); | |
2310 | gen_helper_ddb(tmp_r1, addr); | |
2311 | break; | |
2312 | case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */ | |
2313 | /* for RXF insns, r1 is R3 and r1b is R1 */ | |
2314 | tmp32 = tcg_const_i32(r1b); | |
2315 | potential_page_fault(s); | |
2316 | gen_helper_madb(tmp32, addr, tmp_r1); | |
2317 | tcg_temp_free_i32(tmp32); | |
2318 | break; | |
2319 | default: | |
2320 | LOG_DISAS("illegal ed operation 0x%x\n", op); | |
2321 | gen_illegal_opcode(s, 3); | |
2322 | return; | |
2323 | } | |
2324 | tcg_temp_free_i32(tmp_r1); | |
2325 | tcg_temp_free_i64(addr); | |
2326 | } | |
2327 | ||
2328 | static void disas_a5(DisasContext *s, int op, int r1, int i2) | |
2329 | { | |
2330 | TCGv_i64 tmp, tmp2; | |
2331 | TCGv_i32 tmp32; | |
2332 | LOG_DISAS("disas_a5: op 0x%x r1 %d i2 0x%x\n", op, r1, i2); | |
2333 | switch (op) { | |
2334 | case 0x0: /* IIHH R1,I2 [RI] */ | |
2335 | tmp = tcg_const_i64(i2); | |
2336 | tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 48, 16); | |
87b0b705 | 2337 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2338 | break; |
2339 | case 0x1: /* IIHL R1,I2 [RI] */ | |
2340 | tmp = tcg_const_i64(i2); | |
2341 | tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 32, 16); | |
87b0b705 | 2342 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2343 | break; |
2344 | case 0x2: /* IILH R1,I2 [RI] */ | |
2345 | tmp = tcg_const_i64(i2); | |
2346 | tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 16, 16); | |
87b0b705 | 2347 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2348 | break; |
2349 | case 0x3: /* IILL R1,I2 [RI] */ | |
2350 | tmp = tcg_const_i64(i2); | |
2351 | tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 0, 16); | |
87b0b705 | 2352 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2353 | break; |
2354 | case 0x4: /* NIHH R1,I2 [RI] */ | |
2355 | case 0x8: /* OIHH R1,I2 [RI] */ | |
2356 | tmp = load_reg(r1); | |
2357 | tmp32 = tcg_temp_new_i32(); | |
2358 | switch (op) { | |
2359 | case 0x4: | |
2360 | tmp2 = tcg_const_i64((((uint64_t)i2) << 48) | |
2361 | | 0x0000ffffffffffffULL); | |
2362 | tcg_gen_and_i64(tmp, tmp, tmp2); | |
2363 | break; | |
2364 | case 0x8: | |
2365 | tmp2 = tcg_const_i64(((uint64_t)i2) << 48); | |
2366 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
2367 | break; | |
2368 | default: | |
2369 | tcg_abort(); | |
2370 | } | |
2371 | store_reg(r1, tmp); | |
2372 | tcg_gen_shri_i64(tmp2, tmp, 48); | |
2373 | tcg_gen_trunc_i64_i32(tmp32, tmp2); | |
2374 | set_cc_nz_u32(s, tmp32); | |
2375 | tcg_temp_free_i64(tmp2); | |
2376 | tcg_temp_free_i32(tmp32); | |
87b0b705 | 2377 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2378 | break; |
2379 | case 0x5: /* NIHL R1,I2 [RI] */ | |
2380 | case 0x9: /* OIHL R1,I2 [RI] */ | |
2381 | tmp = load_reg(r1); | |
2382 | tmp32 = tcg_temp_new_i32(); | |
2383 | switch (op) { | |
2384 | case 0x5: | |
2385 | tmp2 = tcg_const_i64((((uint64_t)i2) << 32) | |
2386 | | 0xffff0000ffffffffULL); | |
2387 | tcg_gen_and_i64(tmp, tmp, tmp2); | |
2388 | break; | |
2389 | case 0x9: | |
2390 | tmp2 = tcg_const_i64(((uint64_t)i2) << 32); | |
2391 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
2392 | break; | |
2393 | default: | |
2394 | tcg_abort(); | |
2395 | } | |
2396 | store_reg(r1, tmp); | |
2397 | tcg_gen_shri_i64(tmp2, tmp, 32); | |
2398 | tcg_gen_trunc_i64_i32(tmp32, tmp2); | |
2399 | tcg_gen_andi_i32(tmp32, tmp32, 0xffff); | |
2400 | set_cc_nz_u32(s, tmp32); | |
2401 | tcg_temp_free_i64(tmp2); | |
2402 | tcg_temp_free_i32(tmp32); | |
87b0b705 | 2403 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2404 | break; |
2405 | case 0x6: /* NILH R1,I2 [RI] */ | |
2406 | case 0xa: /* OILH R1,I2 [RI] */ | |
2407 | tmp = load_reg(r1); | |
2408 | tmp32 = tcg_temp_new_i32(); | |
2409 | switch (op) { | |
2410 | case 0x6: | |
2411 | tmp2 = tcg_const_i64((((uint64_t)i2) << 16) | |
2412 | | 0xffffffff0000ffffULL); | |
2413 | tcg_gen_and_i64(tmp, tmp, tmp2); | |
2414 | break; | |
2415 | case 0xa: | |
2416 | tmp2 = tcg_const_i64(((uint64_t)i2) << 16); | |
2417 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
2418 | break; | |
2419 | default: | |
2420 | tcg_abort(); | |
2421 | } | |
2422 | store_reg(r1, tmp); | |
2423 | tcg_gen_shri_i64(tmp, tmp, 16); | |
2424 | tcg_gen_trunc_i64_i32(tmp32, tmp); | |
2425 | tcg_gen_andi_i32(tmp32, tmp32, 0xffff); | |
2426 | set_cc_nz_u32(s, tmp32); | |
2427 | tcg_temp_free_i64(tmp2); | |
2428 | tcg_temp_free_i32(tmp32); | |
87b0b705 | 2429 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2430 | break; |
2431 | case 0x7: /* NILL R1,I2 [RI] */ | |
2432 | case 0xb: /* OILL R1,I2 [RI] */ | |
2433 | tmp = load_reg(r1); | |
2434 | tmp32 = tcg_temp_new_i32(); | |
2435 | switch (op) { | |
2436 | case 0x7: | |
2437 | tmp2 = tcg_const_i64(i2 | 0xffffffffffff0000ULL); | |
2438 | tcg_gen_and_i64(tmp, tmp, tmp2); | |
2439 | break; | |
2440 | case 0xb: | |
2441 | tmp2 = tcg_const_i64(i2); | |
2442 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
2443 | break; | |
2444 | default: | |
2445 | tcg_abort(); | |
2446 | } | |
2447 | store_reg(r1, tmp); | |
2448 | tcg_gen_trunc_i64_i32(tmp32, tmp); | |
2449 | tcg_gen_andi_i32(tmp32, tmp32, 0xffff); | |
2450 | set_cc_nz_u32(s, tmp32); /* signedness should not matter here */ | |
2451 | tcg_temp_free_i64(tmp2); | |
2452 | tcg_temp_free_i32(tmp32); | |
87b0b705 | 2453 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2454 | break; |
2455 | case 0xc: /* LLIHH R1,I2 [RI] */ | |
2456 | tmp = tcg_const_i64( ((uint64_t)i2) << 48 ); | |
2457 | store_reg(r1, tmp); | |
87b0b705 | 2458 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2459 | break; |
2460 | case 0xd: /* LLIHL R1,I2 [RI] */ | |
2461 | tmp = tcg_const_i64( ((uint64_t)i2) << 32 ); | |
2462 | store_reg(r1, tmp); | |
87b0b705 | 2463 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2464 | break; |
2465 | case 0xe: /* LLILH R1,I2 [RI] */ | |
2466 | tmp = tcg_const_i64( ((uint64_t)i2) << 16 ); | |
2467 | store_reg(r1, tmp); | |
87b0b705 | 2468 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2469 | break; |
2470 | case 0xf: /* LLILL R1,I2 [RI] */ | |
2471 | tmp = tcg_const_i64(i2); | |
2472 | store_reg(r1, tmp); | |
87b0b705 | 2473 | tcg_temp_free_i64(tmp); |
e023e832 AG |
2474 | break; |
2475 | default: | |
2476 | LOG_DISAS("illegal a5 operation 0x%x\n", op); | |
2477 | gen_illegal_opcode(s, 2); | |
2478 | return; | |
2479 | } | |
e023e832 AG |
2480 | } |
2481 | ||
2482 | static void disas_a7(DisasContext *s, int op, int r1, int i2) | |
2483 | { | |
2484 | TCGv_i64 tmp, tmp2; | |
2485 | TCGv_i32 tmp32_1, tmp32_2, tmp32_3; | |
2486 | int l1; | |
2487 | ||
2488 | LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op, r1, i2); | |
2489 | switch (op) { | |
2490 | case 0x0: /* TMLH or TMH R1,I2 [RI] */ | |
2491 | case 0x1: /* TMLL or TML R1,I2 [RI] */ | |
2492 | case 0x2: /* TMHH R1,I2 [RI] */ | |
2493 | case 0x3: /* TMHL R1,I2 [RI] */ | |
2494 | tmp = load_reg(r1); | |
2495 | tmp2 = tcg_const_i64((uint16_t)i2); | |
2496 | switch (op) { | |
2497 | case 0x0: | |
2498 | tcg_gen_shri_i64(tmp, tmp, 16); | |
2499 | break; | |
2500 | case 0x1: | |
2501 | break; | |
2502 | case 0x2: | |
2503 | tcg_gen_shri_i64(tmp, tmp, 48); | |
2504 | break; | |
2505 | case 0x3: | |
2506 | tcg_gen_shri_i64(tmp, tmp, 32); | |
2507 | break; | |
2508 | } | |
2509 | tcg_gen_andi_i64(tmp, tmp, 0xffff); | |
2510 | cmp_64(s, tmp, tmp2, CC_OP_TM_64); | |
2511 | tcg_temp_free_i64(tmp); | |
2512 | tcg_temp_free_i64(tmp2); | |
2513 | break; | |
2514 | case 0x4: /* brc m1, i2 */ | |
2515 | gen_brc(r1, s, i2 * 2LL); | |
2516 | return; | |
2517 | case 0x5: /* BRAS R1,I2 [RI] */ | |
2518 | tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 4)); | |
2519 | store_reg(r1, tmp); | |
2520 | tcg_temp_free_i64(tmp); | |
2521 | gen_goto_tb(s, 0, s->pc + i2 * 2LL); | |
2522 | s->is_jmp = DISAS_TB_JUMP; | |
2523 | break; | |
2524 | case 0x6: /* BRCT R1,I2 [RI] */ | |
2525 | tmp32_1 = load_reg32(r1); | |
2526 | tcg_gen_subi_i32(tmp32_1, tmp32_1, 1); | |
2527 | store_reg32(r1, tmp32_1); | |
2528 | gen_update_cc_op(s); | |
2529 | l1 = gen_new_label(); | |
2530 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp32_1, 0, l1); | |
2531 | gen_goto_tb(s, 0, s->pc + (i2 * 2LL)); | |
2532 | gen_set_label(l1); | |
2533 | gen_goto_tb(s, 1, s->pc + 4); | |
2534 | s->is_jmp = DISAS_TB_JUMP; | |
2535 | tcg_temp_free_i32(tmp32_1); | |
2536 | break; | |
2537 | case 0x7: /* BRCTG R1,I2 [RI] */ | |
2538 | tmp = load_reg(r1); | |
2539 | tcg_gen_subi_i64(tmp, tmp, 1); | |
2540 | store_reg(r1, tmp); | |
2541 | gen_update_cc_op(s); | |
2542 | l1 = gen_new_label(); | |
2543 | tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); | |
2544 | gen_goto_tb(s, 0, s->pc + (i2 * 2LL)); | |
2545 | gen_set_label(l1); | |
2546 | gen_goto_tb(s, 1, s->pc + 4); | |
2547 | s->is_jmp = DISAS_TB_JUMP; | |
2548 | tcg_temp_free_i64(tmp); | |
2549 | break; | |
2550 | case 0x8: /* lhi r1, i2 */ | |
2551 | tmp32_1 = tcg_const_i32(i2); | |
2552 | store_reg32(r1, tmp32_1); | |
2553 | tcg_temp_free_i32(tmp32_1); | |
2554 | break; | |
2555 | case 0x9: /* lghi r1, i2 */ | |
2556 | tmp = tcg_const_i64(i2); | |
2557 | store_reg(r1, tmp); | |
2558 | tcg_temp_free_i64(tmp); | |
2559 | break; | |
2560 | case 0xa: /* AHI R1,I2 [RI] */ | |
2561 | tmp32_1 = load_reg32(r1); | |
2562 | tmp32_2 = tcg_temp_new_i32(); | |
2563 | tmp32_3 = tcg_const_i32(i2); | |
2564 | ||
2565 | if (i2 < 0) { | |
2566 | tcg_gen_subi_i32(tmp32_2, tmp32_1, -i2); | |
2567 | } else { | |
2568 | tcg_gen_add_i32(tmp32_2, tmp32_1, tmp32_3); | |
2569 | } | |
2570 | ||
2571 | store_reg32(r1, tmp32_2); | |
2572 | set_cc_add32(s, tmp32_1, tmp32_3, tmp32_2); | |
2573 | tcg_temp_free_i32(tmp32_1); | |
2574 | tcg_temp_free_i32(tmp32_2); | |
2575 | tcg_temp_free_i32(tmp32_3); | |
2576 | break; | |
2577 | case 0xb: /* aghi r1, i2 */ | |
2578 | tmp = load_reg(r1); | |
2579 | tmp2 = tcg_const_i64(i2); | |
2580 | ||
2581 | if (i2 < 0) { | |
2582 | tcg_gen_subi_i64(regs[r1], tmp, -i2); | |
2583 | } else { | |
2584 | tcg_gen_add_i64(regs[r1], tmp, tmp2); | |
2585 | } | |
2586 | set_cc_add64(s, tmp, tmp2, regs[r1]); | |
2587 | tcg_temp_free_i64(tmp); | |
2588 | tcg_temp_free_i64(tmp2); | |
2589 | break; | |
2590 | case 0xc: /* MHI R1,I2 [RI] */ | |
2591 | tmp32_1 = load_reg32(r1); | |
2592 | tcg_gen_muli_i32(tmp32_1, tmp32_1, i2); | |
2593 | store_reg32(r1, tmp32_1); | |
2594 | tcg_temp_free_i32(tmp32_1); | |
2595 | break; | |
2596 | case 0xd: /* MGHI R1,I2 [RI] */ | |
2597 | tmp = load_reg(r1); | |
2598 | tcg_gen_muli_i64(tmp, tmp, i2); | |
2599 | store_reg(r1, tmp); | |
2600 | tcg_temp_free_i64(tmp); | |
2601 | break; | |
2602 | case 0xe: /* CHI R1,I2 [RI] */ | |
2603 | tmp32_1 = load_reg32(r1); | |
2604 | cmp_s32c(s, tmp32_1, i2); | |
2605 | tcg_temp_free_i32(tmp32_1); | |
2606 | break; | |
2607 | case 0xf: /* CGHI R1,I2 [RI] */ | |
2608 | tmp = load_reg(r1); | |
2609 | cmp_s64c(s, tmp, i2); | |
2610 | tcg_temp_free_i64(tmp); | |
2611 | break; | |
2612 | default: | |
2613 | LOG_DISAS("illegal a7 operation 0x%x\n", op); | |
2614 | gen_illegal_opcode(s, 2); | |
2615 | return; | |
2616 | } | |
2617 | } | |
2618 | ||
2619 | static void disas_b2(DisasContext *s, int op, uint32_t insn) | |
2620 | { | |
2621 | TCGv_i64 tmp, tmp2, tmp3; | |
2622 | TCGv_i32 tmp32_1, tmp32_2, tmp32_3; | |
2623 | int r1, r2; | |
2624 | int ilc = 2; | |
2625 | #ifndef CONFIG_USER_ONLY | |
2626 | int r3, d2, b2; | |
2627 | #endif | |
2628 | ||
2629 | r1 = (insn >> 4) & 0xf; | |
2630 | r2 = insn & 0xf; | |
2631 | ||
2632 | LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2); | |
2633 | ||
2634 | switch (op) { | |
2635 | case 0x22: /* IPM R1 [RRE] */ | |
2636 | tmp32_1 = tcg_const_i32(r1); | |
2637 | gen_op_calc_cc(s); | |
2638 | gen_helper_ipm(cc_op, tmp32_1); | |
2639 | tcg_temp_free_i32(tmp32_1); | |
2640 | break; | |
2641 | case 0x41: /* CKSM R1,R2 [RRE] */ | |
2642 | tmp32_1 = tcg_const_i32(r1); | |
2643 | tmp32_2 = tcg_const_i32(r2); | |
2644 | potential_page_fault(s); | |
2645 | gen_helper_cksm(tmp32_1, tmp32_2); | |
2646 | tcg_temp_free_i32(tmp32_1); | |
2647 | tcg_temp_free_i32(tmp32_2); | |
2648 | gen_op_movi_cc(s, 0); | |
2649 | break; | |
2650 | case 0x4e: /* SAR R1,R2 [RRE] */ | |
2651 | tmp32_1 = load_reg32(r2); | |
2652 | tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r1])); | |
2653 | tcg_temp_free_i32(tmp32_1); | |
2654 | break; | |
2655 | case 0x4f: /* EAR R1,R2 [RRE] */ | |
2656 | tmp32_1 = tcg_temp_new_i32(); | |
2657 | tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r2])); | |
2658 | store_reg32(r1, tmp32_1); | |
2659 | tcg_temp_free_i32(tmp32_1); | |
2660 | break; | |
2661 | case 0x52: /* MSR R1,R2 [RRE] */ | |
2662 | tmp32_1 = load_reg32(r1); | |
2663 | tmp32_2 = load_reg32(r2); | |
2664 | tcg_gen_mul_i32(tmp32_1, tmp32_1, tmp32_2); | |
2665 | store_reg32(r1, tmp32_1); | |
2666 | tcg_temp_free_i32(tmp32_1); | |
2667 | tcg_temp_free_i32(tmp32_2); | |
2668 | break; | |
2669 | case 0x54: /* MVPG R1,R2 [RRE] */ | |
2670 | tmp = load_reg(0); | |
2671 | tmp2 = load_reg(r1); | |
2672 | tmp3 = load_reg(r2); | |
2673 | potential_page_fault(s); | |
2674 | gen_helper_mvpg(tmp, tmp2, tmp3); | |
2675 | tcg_temp_free_i64(tmp); | |
2676 | tcg_temp_free_i64(tmp2); | |
2677 | tcg_temp_free_i64(tmp3); | |
2678 | /* XXX check CCO bit and set CC accordingly */ | |
2679 | gen_op_movi_cc(s, 0); | |
2680 | break; | |
2681 | case 0x55: /* MVST R1,R2 [RRE] */ | |
2682 | tmp32_1 = load_reg32(0); | |
2683 | tmp32_2 = tcg_const_i32(r1); | |
2684 | tmp32_3 = tcg_const_i32(r2); | |
2685 | potential_page_fault(s); | |
2686 | gen_helper_mvst(tmp32_1, tmp32_2, tmp32_3); | |
2687 | tcg_temp_free_i32(tmp32_1); | |
2688 | tcg_temp_free_i32(tmp32_2); | |
2689 | tcg_temp_free_i32(tmp32_3); | |
2690 | gen_op_movi_cc(s, 1); | |
2691 | break; | |
2692 | case 0x5d: /* CLST R1,R2 [RRE] */ | |
2693 | tmp32_1 = load_reg32(0); | |
2694 | tmp32_2 = tcg_const_i32(r1); | |
2695 | tmp32_3 = tcg_const_i32(r2); | |
2696 | potential_page_fault(s); | |
2697 | gen_helper_clst(cc_op, tmp32_1, tmp32_2, tmp32_3); | |
2698 | set_cc_static(s); | |
2699 | tcg_temp_free_i32(tmp32_1); | |
2700 | tcg_temp_free_i32(tmp32_2); | |
2701 | tcg_temp_free_i32(tmp32_3); | |
2702 | break; | |
2703 | case 0x5e: /* SRST R1,R2 [RRE] */ | |
2704 | tmp32_1 = load_reg32(0); | |
2705 | tmp32_2 = tcg_const_i32(r1); | |
2706 | tmp32_3 = tcg_const_i32(r2); | |
2707 | potential_page_fault(s); | |
2708 | gen_helper_srst(cc_op, tmp32_1, tmp32_2, tmp32_3); | |
2709 | set_cc_static(s); | |
2710 | tcg_temp_free_i32(tmp32_1); | |
2711 | tcg_temp_free_i32(tmp32_2); | |
2712 | tcg_temp_free_i32(tmp32_3); | |
2713 | break; | |
2714 | ||
2715 | #ifndef CONFIG_USER_ONLY | |
2716 | case 0x02: /* STIDP D2(B2) [S] */ | |
2717 | /* Store CPU ID */ | |
2718 | check_privileged(s, ilc); | |
2719 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2720 | tmp = get_address(s, 0, b2, d2); | |
2721 | potential_page_fault(s); | |
2722 | gen_helper_stidp(tmp); | |
2723 | tcg_temp_free_i64(tmp); | |
2724 | break; | |
2725 | case 0x04: /* SCK D2(B2) [S] */ | |
2726 | /* Set Clock */ | |
2727 | check_privileged(s, ilc); | |
2728 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2729 | tmp = get_address(s, 0, b2, d2); | |
2730 | potential_page_fault(s); | |
2731 | gen_helper_sck(cc_op, tmp); | |
2732 | set_cc_static(s); | |
2733 | tcg_temp_free_i64(tmp); | |
2734 | break; | |
2735 | case 0x05: /* STCK D2(B2) [S] */ | |
2736 | /* Store Clock */ | |
2737 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2738 | tmp = get_address(s, 0, b2, d2); | |
2739 | potential_page_fault(s); | |
2740 | gen_helper_stck(cc_op, tmp); | |
2741 | set_cc_static(s); | |
2742 | tcg_temp_free_i64(tmp); | |
2743 | break; | |
2744 | case 0x06: /* SCKC D2(B2) [S] */ | |
2745 | /* Set Clock Comparator */ | |
2746 | check_privileged(s, ilc); | |
2747 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2748 | tmp = get_address(s, 0, b2, d2); | |
2749 | potential_page_fault(s); | |
2750 | gen_helper_sckc(tmp); | |
2751 | tcg_temp_free_i64(tmp); | |
2752 | break; | |
2753 | case 0x07: /* STCKC D2(B2) [S] */ | |
2754 | /* Store Clock Comparator */ | |
2755 | check_privileged(s, ilc); | |
2756 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2757 | tmp = get_address(s, 0, b2, d2); | |
2758 | potential_page_fault(s); | |
2759 | gen_helper_stckc(tmp); | |
2760 | tcg_temp_free_i64(tmp); | |
2761 | break; | |
2762 | case 0x08: /* SPT D2(B2) [S] */ | |
2763 | /* Set CPU Timer */ | |
2764 | check_privileged(s, ilc); | |
2765 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2766 | tmp = get_address(s, 0, b2, d2); | |
2767 | potential_page_fault(s); | |
2768 | gen_helper_spt(tmp); | |
2769 | tcg_temp_free_i64(tmp); | |
2770 | break; | |
2771 | case 0x09: /* STPT D2(B2) [S] */ | |
2772 | /* Store CPU Timer */ | |
2773 | check_privileged(s, ilc); | |
2774 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2775 | tmp = get_address(s, 0, b2, d2); | |
2776 | potential_page_fault(s); | |
2777 | gen_helper_stpt(tmp); | |
2778 | tcg_temp_free_i64(tmp); | |
2779 | break; | |
2780 | case 0x0a: /* SPKA D2(B2) [S] */ | |
2781 | /* Set PSW Key from Address */ | |
2782 | check_privileged(s, ilc); | |
2783 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2784 | tmp = get_address(s, 0, b2, d2); | |
2785 | tmp2 = tcg_temp_new_i64(); | |
2786 | tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY); | |
2787 | tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4); | |
2788 | tcg_gen_or_i64(psw_mask, tmp2, tmp); | |
2789 | tcg_temp_free_i64(tmp2); | |
2790 | tcg_temp_free_i64(tmp); | |
2791 | break; | |
2792 | case 0x0d: /* PTLB [S] */ | |
2793 | /* Purge TLB */ | |
2794 | check_privileged(s, ilc); | |
2795 | gen_helper_ptlb(); | |
2796 | break; | |
2797 | case 0x10: /* SPX D2(B2) [S] */ | |
2798 | /* Set Prefix Register */ | |
2799 | check_privileged(s, ilc); | |
2800 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2801 | tmp = get_address(s, 0, b2, d2); | |
2802 | potential_page_fault(s); | |
2803 | gen_helper_spx(tmp); | |
2804 | tcg_temp_free_i64(tmp); | |
2805 | break; | |
2806 | case 0x11: /* STPX D2(B2) [S] */ | |
2807 | /* Store Prefix */ | |
2808 | check_privileged(s, ilc); | |
2809 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2810 | tmp = get_address(s, 0, b2, d2); | |
2811 | tmp2 = tcg_temp_new_i64(); | |
2812 | tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUState, psa)); | |
2813 | tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s)); | |
2814 | tcg_temp_free_i64(tmp); | |
2815 | tcg_temp_free_i64(tmp2); | |
2816 | break; | |
2817 | case 0x12: /* STAP D2(B2) [S] */ | |
2818 | /* Store CPU Address */ | |
2819 | check_privileged(s, ilc); | |
2820 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2821 | tmp = get_address(s, 0, b2, d2); | |
2822 | tmp2 = tcg_temp_new_i64(); | |
2823 | tmp32_1 = tcg_temp_new_i32(); | |
2824 | tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, cpu_num)); | |
2825 | tcg_gen_extu_i32_i64(tmp2, tmp32_1); | |
2826 | tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s)); | |
2827 | tcg_temp_free_i64(tmp); | |
2828 | tcg_temp_free_i64(tmp2); | |
2829 | tcg_temp_free_i32(tmp32_1); | |
2830 | break; | |
2831 | case 0x21: /* IPTE R1,R2 [RRE] */ | |
2832 | /* Invalidate PTE */ | |
2833 | check_privileged(s, ilc); | |
2834 | r1 = (insn >> 4) & 0xf; | |
2835 | r2 = insn & 0xf; | |
2836 | tmp = load_reg(r1); | |
2837 | tmp2 = load_reg(r2); | |
2838 | gen_helper_ipte(tmp, tmp2); | |
2839 | tcg_temp_free_i64(tmp); | |
2840 | tcg_temp_free_i64(tmp2); | |
2841 | break; | |
2842 | case 0x29: /* ISKE R1,R2 [RRE] */ | |
2843 | /* Insert Storage Key Extended */ | |
2844 | check_privileged(s, ilc); | |
2845 | r1 = (insn >> 4) & 0xf; | |
2846 | r2 = insn & 0xf; | |
2847 | tmp = load_reg(r2); | |
2848 | tmp2 = tcg_temp_new_i64(); | |
2849 | gen_helper_iske(tmp2, tmp); | |
2850 | store_reg(r1, tmp2); | |
2851 | tcg_temp_free_i64(tmp); | |
2852 | tcg_temp_free_i64(tmp2); | |
2853 | break; | |
2854 | case 0x2a: /* RRBE R1,R2 [RRE] */ | |
2855 | /* Set Storage Key Extended */ | |
2856 | check_privileged(s, ilc); | |
2857 | r1 = (insn >> 4) & 0xf; | |
2858 | r2 = insn & 0xf; | |
2859 | tmp32_1 = load_reg32(r1); | |
2860 | tmp = load_reg(r2); | |
2861 | gen_helper_rrbe(cc_op, tmp32_1, tmp); | |
2862 | set_cc_static(s); | |
2863 | tcg_temp_free_i32(tmp32_1); | |
2864 | tcg_temp_free_i64(tmp); | |
2865 | break; | |
2866 | case 0x2b: /* SSKE R1,R2 [RRE] */ | |
2867 | /* Set Storage Key Extended */ | |
2868 | check_privileged(s, ilc); | |
2869 | r1 = (insn >> 4) & 0xf; | |
2870 | r2 = insn & 0xf; | |
2871 | tmp32_1 = load_reg32(r1); | |
2872 | tmp = load_reg(r2); | |
2873 | gen_helper_sske(tmp32_1, tmp); | |
2874 | tcg_temp_free_i32(tmp32_1); | |
2875 | tcg_temp_free_i64(tmp); | |
2876 | break; | |
2877 | case 0x34: /* STCH ? */ | |
2878 | /* Store Subchannel */ | |
2879 | check_privileged(s, ilc); | |
2880 | gen_op_movi_cc(s, 3); | |
2881 | break; | |
2882 | case 0x46: /* STURA R1,R2 [RRE] */ | |
2883 | /* Store Using Real Address */ | |
2884 | check_privileged(s, ilc); | |
2885 | r1 = (insn >> 4) & 0xf; | |
2886 | r2 = insn & 0xf; | |
2887 | tmp32_1 = load_reg32(r1); | |
2888 | tmp = load_reg(r2); | |
2889 | potential_page_fault(s); | |
2890 | gen_helper_stura(tmp, tmp32_1); | |
2891 | tcg_temp_free_i32(tmp32_1); | |
2892 | tcg_temp_free_i64(tmp); | |
2893 | break; | |
2894 | case 0x50: /* CSP R1,R2 [RRE] */ | |
2895 | /* Compare And Swap And Purge */ | |
2896 | check_privileged(s, ilc); | |
2897 | r1 = (insn >> 4) & 0xf; | |
2898 | r2 = insn & 0xf; | |
2899 | tmp32_1 = tcg_const_i32(r1); | |
2900 | tmp32_2 = tcg_const_i32(r2); | |
2901 | gen_helper_csp(cc_op, tmp32_1, tmp32_2); | |
2902 | set_cc_static(s); | |
2903 | tcg_temp_free_i32(tmp32_1); | |
2904 | tcg_temp_free_i32(tmp32_2); | |
2905 | break; | |
2906 | case 0x5f: /* CHSC ? */ | |
2907 | /* Channel Subsystem Call */ | |
2908 | check_privileged(s, ilc); | |
2909 | gen_op_movi_cc(s, 3); | |
2910 | break; | |
2911 | case 0x78: /* STCKE D2(B2) [S] */ | |
2912 | /* Store Clock Extended */ | |
2913 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2914 | tmp = get_address(s, 0, b2, d2); | |
2915 | potential_page_fault(s); | |
2916 | gen_helper_stcke(cc_op, tmp); | |
2917 | set_cc_static(s); | |
2918 | tcg_temp_free_i64(tmp); | |
2919 | break; | |
2920 | case 0x79: /* SACF D2(B2) [S] */ | |
2921 | /* Store Clock Extended */ | |
2922 | check_privileged(s, ilc); | |
2923 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2924 | tmp = get_address(s, 0, b2, d2); | |
2925 | potential_page_fault(s); | |
2926 | gen_helper_sacf(tmp); | |
2927 | tcg_temp_free_i64(tmp); | |
2928 | /* addressing mode has changed, so end the block */ | |
2929 | s->pc += ilc * 2; | |
2930 | update_psw_addr(s); | |
2931 | s->is_jmp = DISAS_EXCP; | |
2932 | break; | |
2933 | case 0x7d: /* STSI D2,(B2) [S] */ | |
2934 | check_privileged(s, ilc); | |
2935 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2936 | tmp = get_address(s, 0, b2, d2); | |
2937 | tmp32_1 = load_reg32(0); | |
2938 | tmp32_2 = load_reg32(1); | |
2939 | potential_page_fault(s); | |
2940 | gen_helper_stsi(cc_op, tmp, tmp32_1, tmp32_2); | |
2941 | set_cc_static(s); | |
2942 | tcg_temp_free_i64(tmp); | |
2943 | tcg_temp_free_i32(tmp32_1); | |
2944 | tcg_temp_free_i32(tmp32_2); | |
2945 | break; | |
2946 | case 0x9d: /* LFPC D2(B2) [S] */ | |
2947 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2948 | tmp = get_address(s, 0, b2, d2); | |
2949 | tmp2 = tcg_temp_new_i64(); | |
2950 | tmp32_1 = tcg_temp_new_i32(); | |
2951 | tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); | |
2952 | tcg_gen_trunc_i64_i32(tmp32_1, tmp2); | |
2953 | tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc)); | |
2954 | tcg_temp_free_i64(tmp); | |
2955 | tcg_temp_free_i64(tmp2); | |
2956 | tcg_temp_free_i32(tmp32_1); | |
2957 | break; | |
2958 | case 0xb1: /* STFL D2(B2) [S] */ | |
2959 | /* Store Facility List (CPU features) at 200 */ | |
2960 | check_privileged(s, ilc); | |
2961 | tmp2 = tcg_const_i64(0xc0000000); | |
2962 | tmp = tcg_const_i64(200); | |
2963 | tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s)); | |
2964 | tcg_temp_free_i64(tmp2); | |
2965 | tcg_temp_free_i64(tmp); | |
2966 | break; | |
2967 | case 0xb2: /* LPSWE D2(B2) [S] */ | |
2968 | /* Load PSW Extended */ | |
2969 | check_privileged(s, ilc); | |
2970 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
2971 | tmp = get_address(s, 0, b2, d2); | |
2972 | tmp2 = tcg_temp_new_i64(); | |
2973 | tmp3 = tcg_temp_new_i64(); | |
2974 | tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s)); | |
2975 | tcg_gen_addi_i64(tmp, tmp, 8); | |
2976 | tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s)); | |
2977 | gen_helper_load_psw(tmp2, tmp3); | |
2978 | /* we need to keep cc_op intact */ | |
2979 | s->is_jmp = DISAS_JUMP; | |
2980 | tcg_temp_free_i64(tmp); | |
e32a1832 SW |
2981 | tcg_temp_free_i64(tmp2); |
2982 | tcg_temp_free_i64(tmp3); | |
e023e832 AG |
2983 | break; |
2984 | case 0x20: /* SERVC R1,R2 [RRE] */ | |
2985 | /* SCLP Service call (PV hypercall) */ | |
2986 | check_privileged(s, ilc); | |
2987 | potential_page_fault(s); | |
2988 | tmp32_1 = load_reg32(r2); | |
2989 | tmp = load_reg(r1); | |
2990 | gen_helper_servc(cc_op, tmp32_1, tmp); | |
2991 | set_cc_static(s); | |
2992 | tcg_temp_free_i32(tmp32_1); | |
2993 | tcg_temp_free_i64(tmp); | |
2994 | break; | |
2995 | #endif | |
2996 | default: | |
2997 | LOG_DISAS("illegal b2 operation 0x%x\n", op); | |
2998 | gen_illegal_opcode(s, ilc); | |
2999 | break; | |
3000 | } | |
3001 | } | |
3002 | ||
3003 | static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2) | |
3004 | { | |
3005 | TCGv_i64 tmp; | |
3006 | TCGv_i32 tmp32_1, tmp32_2, tmp32_3; | |
3007 | LOG_DISAS("disas_b3: op 0x%x m3 0x%x r1 %d r2 %d\n", op, m3, r1, r2); | |
3008 | #define FP_HELPER(i) \ | |
3009 | tmp32_1 = tcg_const_i32(r1); \ | |
3010 | tmp32_2 = tcg_const_i32(r2); \ | |
3011 | gen_helper_ ## i (tmp32_1, tmp32_2); \ | |
3012 | tcg_temp_free_i32(tmp32_1); \ | |
3013 | tcg_temp_free_i32(tmp32_2); | |
3014 | ||
3015 | #define FP_HELPER_CC(i) \ | |
3016 | tmp32_1 = tcg_const_i32(r1); \ | |
3017 | tmp32_2 = tcg_const_i32(r2); \ | |
3018 | gen_helper_ ## i (cc_op, tmp32_1, tmp32_2); \ | |
3019 | set_cc_static(s); \ | |
3020 | tcg_temp_free_i32(tmp32_1); \ | |
3021 | tcg_temp_free_i32(tmp32_2); | |
3022 | ||
3023 | switch (op) { | |
3024 | case 0x0: /* LPEBR R1,R2 [RRE] */ | |
3025 | FP_HELPER_CC(lpebr); | |
3026 | break; | |
3027 | case 0x2: /* LTEBR R1,R2 [RRE] */ | |
3028 | FP_HELPER_CC(ltebr); | |
3029 | break; | |
3030 | case 0x3: /* LCEBR R1,R2 [RRE] */ | |
3031 | FP_HELPER_CC(lcebr); | |
3032 | break; | |
3033 | case 0x4: /* LDEBR R1,R2 [RRE] */ | |
3034 | FP_HELPER(ldebr); | |
3035 | break; | |
3036 | case 0x5: /* LXDBR R1,R2 [RRE] */ | |
3037 | FP_HELPER(lxdbr); | |
3038 | break; | |
3039 | case 0x9: /* CEBR R1,R2 [RRE] */ | |
3040 | FP_HELPER_CC(cebr); | |
3041 | break; | |
3042 | case 0xa: /* AEBR R1,R2 [RRE] */ | |
3043 | FP_HELPER_CC(aebr); | |
3044 | break; | |
3045 | case 0xb: /* SEBR R1,R2 [RRE] */ | |
3046 | FP_HELPER_CC(sebr); | |
3047 | break; | |
3048 | case 0xd: /* DEBR R1,R2 [RRE] */ | |
3049 | FP_HELPER(debr); | |
3050 | break; | |
3051 | case 0x10: /* LPDBR R1,R2 [RRE] */ | |
3052 | FP_HELPER_CC(lpdbr); | |
3053 | break; | |
3054 | case 0x12: /* LTDBR R1,R2 [RRE] */ | |
3055 | FP_HELPER_CC(ltdbr); | |
3056 | break; | |
3057 | case 0x13: /* LCDBR R1,R2 [RRE] */ | |
3058 | FP_HELPER_CC(lcdbr); | |
3059 | break; | |
3060 | case 0x15: /* SQBDR R1,R2 [RRE] */ | |
3061 | FP_HELPER(sqdbr); | |
3062 | break; | |
3063 | case 0x17: /* MEEBR R1,R2 [RRE] */ | |
3064 | FP_HELPER(meebr); | |
3065 | break; | |
3066 | case 0x19: /* CDBR R1,R2 [RRE] */ | |
3067 | FP_HELPER_CC(cdbr); | |
3068 | break; | |
3069 | case 0x1a: /* ADBR R1,R2 [RRE] */ | |
3070 | FP_HELPER_CC(adbr); | |
3071 | break; | |
3072 | case 0x1b: /* SDBR R1,R2 [RRE] */ | |
3073 | FP_HELPER_CC(sdbr); | |
3074 | break; | |
3075 | case 0x1c: /* MDBR R1,R2 [RRE] */ | |
3076 | FP_HELPER(mdbr); | |
3077 | break; | |
3078 | case 0x1d: /* DDBR R1,R2 [RRE] */ | |
3079 | FP_HELPER(ddbr); | |
3080 | break; | |
3081 | case 0xe: /* MAEBR R1,R3,R2 [RRF] */ | |
3082 | case 0x1e: /* MADBR R1,R3,R2 [RRF] */ | |
3083 | case 0x1f: /* MSDBR R1,R3,R2 [RRF] */ | |
3084 | /* for RRF insns, m3 is R1, r1 is R3, and r2 is R2 */ | |
3085 | tmp32_1 = tcg_const_i32(m3); | |
3086 | tmp32_2 = tcg_const_i32(r2); | |
3087 | tmp32_3 = tcg_const_i32(r1); | |
3088 | switch (op) { | |
3089 | case 0xe: | |
3090 | gen_helper_maebr(tmp32_1, tmp32_3, tmp32_2); | |
3091 | break; | |
3092 | case 0x1e: | |
3093 | gen_helper_madbr(tmp32_1, tmp32_3, tmp32_2); | |
3094 | break; | |
3095 | case 0x1f: | |
3096 | gen_helper_msdbr(tmp32_1, tmp32_3, tmp32_2); | |
3097 | break; | |
3098 | default: | |
3099 | tcg_abort(); | |
3100 | } | |
3101 | tcg_temp_free_i32(tmp32_1); | |
3102 | tcg_temp_free_i32(tmp32_2); | |
3103 | tcg_temp_free_i32(tmp32_3); | |
3104 | break; | |
3105 | case 0x40: /* LPXBR R1,R2 [RRE] */ | |
3106 | FP_HELPER_CC(lpxbr); | |
3107 | break; | |
3108 | case 0x42: /* LTXBR R1,R2 [RRE] */ | |
3109 | FP_HELPER_CC(ltxbr); | |
3110 | break; | |
3111 | case 0x43: /* LCXBR R1,R2 [RRE] */ | |
3112 | FP_HELPER_CC(lcxbr); | |
3113 | break; | |
3114 | case 0x44: /* LEDBR R1,R2 [RRE] */ | |
3115 | FP_HELPER(ledbr); | |
3116 | break; | |
3117 | case 0x45: /* LDXBR R1,R2 [RRE] */ | |
3118 | FP_HELPER(ldxbr); | |
3119 | break; | |
3120 | case 0x46: /* LEXBR R1,R2 [RRE] */ | |
3121 | FP_HELPER(lexbr); | |
3122 | break; | |
3123 | case 0x49: /* CXBR R1,R2 [RRE] */ | |
3124 | FP_HELPER_CC(cxbr); | |
3125 | break; | |
3126 | case 0x4a: /* AXBR R1,R2 [RRE] */ | |
3127 | FP_HELPER_CC(axbr); | |
3128 | break; | |
3129 | case 0x4b: /* SXBR R1,R2 [RRE] */ | |
3130 | FP_HELPER_CC(sxbr); | |
3131 | break; | |
3132 | case 0x4c: /* MXBR R1,R2 [RRE] */ | |
3133 | FP_HELPER(mxbr); | |
3134 | break; | |
3135 | case 0x4d: /* DXBR R1,R2 [RRE] */ | |
3136 | FP_HELPER(dxbr); | |
3137 | break; | |
3138 | case 0x65: /* LXR R1,R2 [RRE] */ | |
3139 | tmp = load_freg(r2); | |
3140 | store_freg(r1, tmp); | |
3141 | tcg_temp_free_i64(tmp); | |
3142 | tmp = load_freg(r2 + 2); | |
3143 | store_freg(r1 + 2, tmp); | |
3144 | tcg_temp_free_i64(tmp); | |
3145 | break; | |
3146 | case 0x74: /* LZER R1 [RRE] */ | |
3147 | tmp32_1 = tcg_const_i32(r1); | |
3148 | gen_helper_lzer(tmp32_1); | |
3149 | tcg_temp_free_i32(tmp32_1); | |
3150 | break; | |
3151 | case 0x75: /* LZDR R1 [RRE] */ | |
3152 | tmp32_1 = tcg_const_i32(r1); | |
3153 | gen_helper_lzdr(tmp32_1); | |
3154 | tcg_temp_free_i32(tmp32_1); | |
3155 | break; | |
3156 | case 0x76: /* LZXR R1 [RRE] */ | |
3157 | tmp32_1 = tcg_const_i32(r1); | |
3158 | gen_helper_lzxr(tmp32_1); | |
3159 | tcg_temp_free_i32(tmp32_1); | |
3160 | break; | |
3161 | case 0x84: /* SFPC R1 [RRE] */ | |
3162 | tmp32_1 = load_reg32(r1); | |
3163 | tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc)); | |
3164 | tcg_temp_free_i32(tmp32_1); | |
3165 | break; | |
3166 | case 0x8c: /* EFPC R1 [RRE] */ | |
3167 | tmp32_1 = tcg_temp_new_i32(); | |
3168 | tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc)); | |
3169 | store_reg32(r1, tmp32_1); | |
3170 | tcg_temp_free_i32(tmp32_1); | |
3171 | break; | |
3172 | case 0x94: /* CEFBR R1,R2 [RRE] */ | |
3173 | case 0x95: /* CDFBR R1,R2 [RRE] */ | |
3174 | case 0x96: /* CXFBR R1,R2 [RRE] */ | |
3175 | tmp32_1 = tcg_const_i32(r1); | |
3176 | tmp32_2 = load_reg32(r2); | |
3177 | switch (op) { | |
3178 | case 0x94: | |
3179 | gen_helper_cefbr(tmp32_1, tmp32_2); | |
3180 | break; | |
3181 | case 0x95: | |
3182 | gen_helper_cdfbr(tmp32_1, tmp32_2); | |
3183 | break; | |
3184 | case 0x96: | |
3185 | gen_helper_cxfbr(tmp32_1, tmp32_2); | |
3186 | break; | |
3187 | default: | |
3188 | tcg_abort(); | |
3189 | } | |
3190 | tcg_temp_free_i32(tmp32_1); | |
3191 | tcg_temp_free_i32(tmp32_2); | |
3192 | break; | |
3193 | case 0x98: /* CFEBR R1,R2 [RRE] */ | |
3194 | case 0x99: /* CFDBR R1,R2 [RRE] */ | |
3195 | case 0x9a: /* CFXBR R1,R2 [RRE] */ | |
3196 | tmp32_1 = tcg_const_i32(r1); | |
3197 | tmp32_2 = tcg_const_i32(r2); | |
3198 | tmp32_3 = tcg_const_i32(m3); | |
3199 | switch (op) { | |
3200 | case 0x98: | |
3201 | gen_helper_cfebr(cc_op, tmp32_1, tmp32_2, tmp32_3); | |
3202 | break; | |
3203 | case 0x99: | |
3204 | gen_helper_cfdbr(cc_op, tmp32_1, tmp32_2, tmp32_3); | |
3205 | break; | |
3206 | case 0x9a: | |
3207 | gen_helper_cfxbr(cc_op, tmp32_1, tmp32_2, tmp32_3); | |
3208 | break; | |
3209 | default: | |
3210 | tcg_abort(); | |
3211 | } | |
3212 | set_cc_static(s); | |
3213 | tcg_temp_free_i32(tmp32_1); | |
3214 | tcg_temp_free_i32(tmp32_2); | |
3215 | tcg_temp_free_i32(tmp32_3); | |
3216 | break; | |
3217 | case 0xa4: /* CEGBR R1,R2 [RRE] */ | |
3218 | case 0xa5: /* CDGBR R1,R2 [RRE] */ | |
3219 | tmp32_1 = tcg_const_i32(r1); | |
3220 | tmp = load_reg(r2); | |
3221 | switch (op) { | |
3222 | case 0xa4: | |
3223 | gen_helper_cegbr(tmp32_1, tmp); | |
3224 | break; | |
3225 | case 0xa5: | |
3226 | gen_helper_cdgbr(tmp32_1, tmp); | |
3227 | break; | |
3228 | default: | |
3229 | tcg_abort(); | |
3230 | } | |
3231 | tcg_temp_free_i32(tmp32_1); | |
3232 | tcg_temp_free_i64(tmp); | |
3233 | break; | |
3234 | case 0xa6: /* CXGBR R1,R2 [RRE] */ | |
3235 | tmp32_1 = tcg_const_i32(r1); | |
3236 | tmp = load_reg(r2); | |
3237 | gen_helper_cxgbr(tmp32_1, tmp); | |
3238 | tcg_temp_free_i32(tmp32_1); | |
3239 | tcg_temp_free_i64(tmp); | |
3240 | break; | |
3241 | case 0xa8: /* CGEBR R1,R2 [RRE] */ | |
3242 | tmp32_1 = tcg_const_i32(r1); | |
3243 | tmp32_2 = tcg_const_i32(r2); | |
3244 | tmp32_3 = tcg_const_i32(m3); | |
3245 | gen_helper_cgebr(cc_op, tmp32_1, tmp32_2, tmp32_3); | |
3246 | set_cc_static(s); | |
3247 | tcg_temp_free_i32(tmp32_1); | |
3248 | tcg_temp_free_i32(tmp32_2); | |
3249 | tcg_temp_free_i32(tmp32_3); | |
3250 | break; | |
3251 | case 0xa9: /* CGDBR R1,R2 [RRE] */ | |
3252 | tmp32_1 = tcg_const_i32(r1); | |
3253 | tmp32_2 = tcg_const_i32(r2); | |
3254 | tmp32_3 = tcg_const_i32(m3); | |
3255 | gen_helper_cgdbr(cc_op, tmp32_1, tmp32_2, tmp32_3); | |
3256 | set_cc_static(s); | |
3257 | tcg_temp_free_i32(tmp32_1); | |
3258 | tcg_temp_free_i32(tmp32_2); | |
3259 | tcg_temp_free_i32(tmp32_3); | |
3260 | break; | |
3261 | case 0xaa: /* CGXBR R1,R2 [RRE] */ | |
3262 | tmp32_1 = tcg_const_i32(r1); | |
3263 | tmp32_2 = tcg_const_i32(r2); | |
3264 | tmp32_3 = tcg_const_i32(m3); | |
3265 | gen_helper_cgxbr(cc_op, tmp32_1, tmp32_2, tmp32_3); | |
3266 | set_cc_static(s); | |
3267 | tcg_temp_free_i32(tmp32_1); | |
3268 | tcg_temp_free_i32(tmp32_2); | |
3269 | tcg_temp_free_i32(tmp32_3); | |
3270 | break; | |
3271 | default: | |
3272 | LOG_DISAS("illegal b3 operation 0x%x\n", op); | |
3273 | gen_illegal_opcode(s, 2); | |
3274 | break; | |
3275 | } | |
3276 | ||
3277 | #undef FP_HELPER_CC | |
3278 | #undef FP_HELPER | |
3279 | } | |
3280 | ||
3281 | static void disas_b9(DisasContext *s, int op, int r1, int r2) | |
3282 | { | |
3283 | TCGv_i64 tmp, tmp2, tmp3; | |
3284 | TCGv_i32 tmp32_1, tmp32_2, tmp32_3; | |
3285 | ||
3286 | LOG_DISAS("disas_b9: op 0x%x r1 %d r2 %d\n", op, r1, r2); | |
3287 | switch (op) { | |
3288 | case 0x0: /* LPGR R1,R2 [RRE] */ | |
3289 | case 0x1: /* LNGR R1,R2 [RRE] */ | |
3290 | case 0x2: /* LTGR R1,R2 [RRE] */ | |
3291 | case 0x3: /* LCGR R1,R2 [RRE] */ | |
3292 | case 0x10: /* LPGFR R1,R2 [RRE] */ | |
3293 | case 0x11: /* LNFGR R1,R2 [RRE] */ | |
3294 | case 0x12: /* LTGFR R1,R2 [RRE] */ | |
3295 | case 0x13: /* LCGFR R1,R2 [RRE] */ | |
3296 | if (op & 0x10) { | |
3297 | tmp = load_reg32_i64(r2); | |
3298 | } else { | |
3299 | tmp = load_reg(r2); | |
3300 | } | |
3301 | switch (op & 0xf) { | |
3302 | case 0x0: /* LP?GR */ | |
3303 | set_cc_abs64(s, tmp); | |
3304 | gen_helper_abs_i64(tmp, tmp); | |
3305 | store_reg(r1, tmp); | |
3306 | break; | |
3307 | case 0x1: /* LN?GR */ | |
3308 | set_cc_nabs64(s, tmp); | |
3309 | gen_helper_nabs_i64(tmp, tmp); | |
3310 | store_reg(r1, tmp); | |
3311 | break; | |
3312 | case 0x2: /* LT?GR */ | |
3313 | if (r1 != r2) { | |
3314 | store_reg(r1, tmp); | |
3315 | } | |
3316 | set_cc_s64(s, tmp); | |
3317 | break; | |
3318 | case 0x3: /* LC?GR */ | |
3319 | tcg_gen_neg_i64(regs[r1], tmp); | |
3320 | set_cc_comp64(s, regs[r1]); | |
3321 | break; | |
3322 | } | |
3323 | tcg_temp_free_i64(tmp); | |
3324 | break; | |
3325 | case 0x4: /* LGR R1,R2 [RRE] */ | |
3326 | store_reg(r1, regs[r2]); | |
3327 | break; | |
3328 | case 0x6: /* LGBR R1,R2 [RRE] */ | |
3329 | tmp2 = load_reg(r2); | |
3330 | tcg_gen_ext8s_i64(tmp2, tmp2); | |
3331 | store_reg(r1, tmp2); | |
3332 | tcg_temp_free_i64(tmp2); | |
3333 | break; | |
3334 | case 0x8: /* AGR R1,R2 [RRE] */ | |
3335 | case 0xa: /* ALGR R1,R2 [RRE] */ | |
3336 | tmp = load_reg(r1); | |
3337 | tmp2 = load_reg(r2); | |
3338 | tmp3 = tcg_temp_new_i64(); | |
3339 | tcg_gen_add_i64(tmp3, tmp, tmp2); | |
3340 | store_reg(r1, tmp3); | |
3341 | switch (op) { | |
3342 | case 0x8: | |
3343 | set_cc_add64(s, tmp, tmp2, tmp3); | |
3344 | break; | |
3345 | case 0xa: | |
3346 | set_cc_addu64(s, tmp, tmp2, tmp3); | |
3347 | break; | |
3348 | default: | |
3349 | tcg_abort(); | |
3350 | } | |
3351 | tcg_temp_free_i64(tmp); | |
3352 | tcg_temp_free_i64(tmp2); | |
3353 | tcg_temp_free_i64(tmp3); | |
3354 | break; | |
3355 | case 0x9: /* SGR R1,R2 [RRE] */ | |
3356 | case 0xb: /* SLGR R1,R2 [RRE] */ | |
3357 | case 0x1b: /* SLGFR R1,R2 [RRE] */ | |
3358 | case 0x19: /* SGFR R1,R2 [RRE] */ | |
3359 | tmp = load_reg(r1); | |
3360 | switch (op) { | |
3361 | case 0x1b: | |
3362 | tmp32_1 = load_reg32(r2); | |
3363 | tmp2 = tcg_temp_new_i64(); | |
3364 | tcg_gen_extu_i32_i64(tmp2, tmp32_1); | |
3365 | tcg_temp_free_i32(tmp32_1); | |
3366 | break; | |
3367 | case 0x19: | |
3368 | tmp32_1 = load_reg32(r2); | |
3369 | tmp2 = tcg_temp_new_i64(); | |
3370 | tcg_gen_ext_i32_i64(tmp2, tmp32_1); | |
3371 | tcg_temp_free_i32(tmp32_1); | |
3372 | break; | |
3373 | default: | |
3374 | tmp2 = load_reg(r2); | |
3375 | break; | |
3376 | } | |
3377 | tmp3 = tcg_temp_new_i64(); | |
3378 | tcg_gen_sub_i64(tmp3, tmp, tmp2); | |
3379 | store_reg(r1, tmp3); | |
3380 | switch (op) { | |
3381 | case 0x9: | |
3382 | case 0x19: | |
3383 | set_cc_sub64(s, tmp, tmp2, tmp3); | |
3384 | break; | |
3385 | case 0xb: | |
3386 | case 0x1b: | |
3387 | set_cc_subu64(s, tmp, tmp2, tmp3); | |
3388 | break; | |
3389 | default: | |
3390 | tcg_abort(); | |
3391 | } | |
3392 | tcg_temp_free_i64(tmp); | |
3393 | tcg_temp_free_i64(tmp2); | |
3394 | tcg_temp_free_i64(tmp3); | |
3395 | break; | |
3396 | case 0xc: /* MSGR R1,R2 [RRE] */ | |
3397 | case 0x1c: /* MSGFR R1,R2 [RRE] */ | |
3398 | tmp = load_reg(r1); | |
3399 | tmp2 = load_reg(r2); | |
3400 | if (op == 0x1c) { | |
3401 | tcg_gen_ext32s_i64(tmp2, tmp2); | |
3402 | } | |
3403 | tcg_gen_mul_i64(tmp, tmp, tmp2); | |
3404 | store_reg(r1, tmp); | |
3405 | tcg_temp_free_i64(tmp); | |
3406 | tcg_temp_free_i64(tmp2); | |
3407 | break; | |
3408 | case 0xd: /* DSGR R1,R2 [RRE] */ | |
3409 | case 0x1d: /* DSGFR R1,R2 [RRE] */ | |
3410 | tmp = load_reg(r1 + 1); | |
3411 | if (op == 0xd) { | |
3412 | tmp2 = load_reg(r2); | |
3413 | } else { | |
3414 | tmp32_1 = load_reg32(r2); | |
3415 | tmp2 = tcg_temp_new_i64(); | |
3416 | tcg_gen_ext_i32_i64(tmp2, tmp32_1); | |
3417 | tcg_temp_free_i32(tmp32_1); | |
3418 | } | |
3419 | tmp3 = tcg_temp_new_i64(); | |
3420 | tcg_gen_div_i64(tmp3, tmp, tmp2); | |
3421 | store_reg(r1 + 1, tmp3); | |
3422 | tcg_gen_rem_i64(tmp3, tmp, tmp2); | |
3423 | store_reg(r1, tmp3); | |
3424 | tcg_temp_free_i64(tmp); | |
3425 | tcg_temp_free_i64(tmp2); | |
3426 | tcg_temp_free_i64(tmp3); | |
3427 | break; | |
3428 | case 0x14: /* LGFR R1,R2 [RRE] */ | |
3429 | tmp32_1 = load_reg32(r2); | |
3430 | tmp = tcg_temp_new_i64(); | |
3431 | tcg_gen_ext_i32_i64(tmp, tmp32_1); | |
3432 | store_reg(r1, tmp); | |
3433 | tcg_temp_free_i32(tmp32_1); | |
3434 | tcg_temp_free_i64(tmp); | |
3435 | break; | |
3436 | case 0x16: /* LLGFR R1,R2 [RRE] */ | |
3437 | tmp32_1 = load_reg32(r2); | |
3438 | tmp = tcg_temp_new_i64(); | |
3439 | tcg_gen_extu_i32_i64(tmp, tmp32_1); | |
3440 | store_reg(r1, tmp); | |
3441 | tcg_temp_free_i32(tmp32_1); | |
3442 | tcg_temp_free_i64(tmp); | |
3443 | break; | |
3444 | case 0x17: /* LLGTR R1,R2 [RRE] */ | |
3445 | tmp32_1 = load_reg32(r2); | |
3446 | tmp = tcg_temp_new_i64(); | |
3447 | tcg_gen_andi_i32(tmp32_1, tmp32_1, 0x7fffffffUL); | |
3448 | tcg_gen_extu_i32_i64(tmp, tmp32_1); | |
3449 | store_reg(r1, tmp); | |
3450 | tcg_temp_free_i32(tmp32_1); | |
3451 | tcg_temp_free_i64(tmp); | |
3452 | break; | |
3453 | case 0x18: /* AGFR R1,R2 [RRE] */ | |
3454 | case 0x1a: /* ALGFR R1,R2 [RRE] */ | |
3455 | tmp32_1 = load_reg32(r2); | |
3456 | tmp2 = tcg_temp_new_i64(); | |
3457 | if (op == 0x18) { | |
3458 | tcg_gen_ext_i32_i64(tmp2, tmp32_1); | |
3459 | } else { | |
3460 | tcg_gen_extu_i32_i64(tmp2, tmp32_1); | |
3461 | } | |
3462 | tcg_temp_free_i32(tmp32_1); | |
3463 | tmp = load_reg(r1); | |
3464 | tmp3 = tcg_temp_new_i64(); | |
3465 | tcg_gen_add_i64(tmp3, tmp, tmp2); | |
3466 | store_reg(r1, tmp3); | |
3467 | if (op == 0x18) { | |
3468 | set_cc_add64(s, tmp, tmp2, tmp3); | |
3469 | } else { | |
3470 | set_cc_addu64(s, tmp, tmp2, tmp3); | |
3471 | } | |
3472 | tcg_temp_free_i64(tmp); | |
3473 | tcg_temp_free_i64(tmp2); | |
3474 | tcg_temp_free_i64(tmp3); | |
3475 | break; | |
e1b45cca AG |
3476 | case 0x0f: /* LRVGR R1,R2 [RRE] */ |
3477 | tcg_gen_bswap64_i64(regs[r1], regs[r2]); | |
3478 | break; | |
e023e832 AG |
3479 | case 0x1f: /* LRVR R1,R2 [RRE] */ |
3480 | tmp32_1 = load_reg32(r2); | |
3481 | tcg_gen_bswap32_i32(tmp32_1, tmp32_1); | |
3482 | store_reg32(r1, tmp32_1); | |
3483 | tcg_temp_free_i32(tmp32_1); | |
3484 | break; | |
3485 | case 0x20: /* CGR R1,R2 [RRE] */ | |
3486 | case 0x30: /* CGFR R1,R2 [RRE] */ | |
3487 | tmp2 = load_reg(r2); | |
3488 | if (op == 0x30) { | |
3489 | tcg_gen_ext32s_i64(tmp2, tmp2); | |
3490 | } | |
3491 | tmp = load_reg(r1); | |
3492 | cmp_s64(s, tmp, tmp2); | |
3493 | tcg_temp_free_i64(tmp); | |
3494 | tcg_temp_free_i64(tmp2); | |
3495 | break; | |
3496 | case 0x21: /* CLGR R1,R2 [RRE] */ | |
3497 | case 0x31: /* CLGFR R1,R2 [RRE] */ | |
3498 | tmp2 = load_reg(r2); | |
3499 | if (op == 0x31) { | |
3500 | tcg_gen_ext32u_i64(tmp2, tmp2); | |
3501 | } | |
3502 | tmp = load_reg(r1); | |
3503 | cmp_u64(s, tmp, tmp2); | |
3504 | tcg_temp_free_i64(tmp); | |
3505 | tcg_temp_free_i64(tmp2); | |
3506 | break; | |
3507 | case 0x26: /* LBR R1,R2 [RRE] */ | |
3508 | tmp32_1 = load_reg32(r2); | |
3509 | tcg_gen_ext8s_i32(tmp32_1, tmp32_1); | |
3510 | store_reg32(r1, tmp32_1); | |
3511 | tcg_temp_free_i32(tmp32_1); | |
3512 | break; | |
3513 | case 0x27: /* LHR R1,R2 [RRE] */ | |
3514 | tmp32_1 = load_reg32(r2); | |
3515 | tcg_gen_ext16s_i32(tmp32_1, tmp32_1); | |
3516 | store_reg32(r1, tmp32_1); | |
3517 | tcg_temp_free_i32(tmp32_1); | |
3518 | break; | |
3519 | case 0x80: /* NGR R1,R2 [RRE] */ | |
3520 | case 0x81: /* OGR R1,R2 [RRE] */ | |
3521 | case 0x82: /* XGR R1,R2 [RRE] */ | |
3522 | tmp = load_reg(r1); | |
3523 | tmp2 = load_reg(r2); | |
3524 | switch (op) { | |
3525 | case 0x80: | |
3526 | tcg_gen_and_i64(tmp, tmp, tmp2); | |
3527 | break; | |
3528 | case 0x81: | |
3529 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
3530 | break; | |
3531 | case 0x82: | |
3532 | tcg_gen_xor_i64(tmp, tmp, tmp2); | |
3533 | break; | |
3534 | default: | |
3535 | tcg_abort(); | |
3536 | } | |
3537 | store_reg(r1, tmp); | |
3538 | set_cc_nz_u64(s, tmp); | |
3539 | tcg_temp_free_i64(tmp); | |
3540 | tcg_temp_free_i64(tmp2); | |
3541 | break; | |
3542 | case 0x83: /* FLOGR R1,R2 [RRE] */ | |
3543 | tmp = load_reg(r2); | |
3544 | tmp32_1 = tcg_const_i32(r1); | |
3545 | gen_helper_flogr(cc_op, tmp32_1, tmp); | |
3546 | set_cc_static(s); | |
3547 | tcg_temp_free_i64(tmp); | |
3548 | tcg_temp_free_i32(tmp32_1); | |
3549 | break; | |
3550 | case 0x84: /* LLGCR R1,R2 [RRE] */ | |
3551 | tmp = load_reg(r2); | |
3552 | tcg_gen_andi_i64(tmp, tmp, 0xff); | |
3553 | store_reg(r1, tmp); | |
3554 | tcg_temp_free_i64(tmp); | |
3555 | break; | |
3556 | case 0x85: /* LLGHR R1,R2 [RRE] */ | |
3557 | tmp = load_reg(r2); | |
3558 | tcg_gen_andi_i64(tmp, tmp, 0xffff); | |
3559 | store_reg(r1, tmp); | |
3560 | tcg_temp_free_i64(tmp); | |
3561 | break; | |
3562 | case 0x87: /* DLGR R1,R2 [RRE] */ | |
3563 | tmp32_1 = tcg_const_i32(r1); | |
3564 | tmp = load_reg(r2); | |
3565 | gen_helper_dlg(tmp32_1, tmp); | |
3566 | tcg_temp_free_i64(tmp); | |
3567 | tcg_temp_free_i32(tmp32_1); | |
3568 | break; | |
3569 | case 0x88: /* ALCGR R1,R2 [RRE] */ | |
3570 | tmp = load_reg(r1); | |
3571 | tmp2 = load_reg(r2); | |
3572 | tmp3 = tcg_temp_new_i64(); | |
3573 | gen_op_calc_cc(s); | |
3574 | tcg_gen_extu_i32_i64(tmp3, cc_op); | |
3575 | tcg_gen_shri_i64(tmp3, tmp3, 1); | |
3576 | tcg_gen_andi_i64(tmp3, tmp3, 1); | |
3577 | tcg_gen_add_i64(tmp3, tmp2, tmp3); | |
3578 | tcg_gen_add_i64(tmp3, tmp, tmp3); | |
3579 | store_reg(r1, tmp3); | |
3580 | set_cc_addu64(s, tmp, tmp2, tmp3); | |
3581 | tcg_temp_free_i64(tmp); | |
3582 | tcg_temp_free_i64(tmp2); | |
3583 | tcg_temp_free_i64(tmp3); | |
3584 | break; | |
3585 | case 0x89: /* SLBGR R1,R2 [RRE] */ | |
3586 | tmp = load_reg(r1); | |
3587 | tmp2 = load_reg(r2); | |
3588 | tmp32_1 = tcg_const_i32(r1); | |
3589 | gen_op_calc_cc(s); | |
3590 | gen_helper_slbg(cc_op, cc_op, tmp32_1, tmp, tmp2); | |
3591 | set_cc_static(s); | |
3592 | tcg_temp_free_i64(tmp); | |
3593 | tcg_temp_free_i64(tmp2); | |
3594 | tcg_temp_free_i32(tmp32_1); | |
3595 | break; | |
3596 | case 0x94: /* LLCR R1,R2 [RRE] */ | |
3597 | tmp32_1 = load_reg32(r2); | |
3598 | tcg_gen_andi_i32(tmp32_1, tmp32_1, 0xff); | |
3599 | store_reg32(r1, tmp32_1); | |
3600 | tcg_temp_free_i32(tmp32_1); | |
3601 | break; | |
3602 | case 0x95: /* LLHR R1,R2 [RRE] */ | |
3603 | tmp32_1 = load_reg32(r2); | |
3604 | tcg_gen_andi_i32(tmp32_1, tmp32_1, 0xffff); | |
3605 | store_reg32(r1, tmp32_1); | |
3606 | tcg_temp_free_i32(tmp32_1); | |
3607 | break; | |
3608 | case 0x96: /* MLR R1,R2 [RRE] */ | |
3609 | /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */ | |
3610 | tmp2 = load_reg(r2); | |
3611 | tmp3 = load_reg((r1 + 1) & 15); | |
3612 | tcg_gen_ext32u_i64(tmp2, tmp2); | |
3613 | tcg_gen_ext32u_i64(tmp3, tmp3); | |
3614 | tcg_gen_mul_i64(tmp2, tmp2, tmp3); | |
3615 | store_reg32_i64((r1 + 1) & 15, tmp2); | |
3616 | tcg_gen_shri_i64(tmp2, tmp2, 32); | |
3617 | store_reg32_i64(r1, tmp2); | |
3618 | tcg_temp_free_i64(tmp2); | |
3619 | tcg_temp_free_i64(tmp3); | |
3620 | break; | |
3621 | case 0x97: /* DLR R1,R2 [RRE] */ | |
3622 | /* reg(r1) = reg(r1, r1+1) % reg(r2) */ | |
3623 | /* reg(r1+1) = reg(r1, r1+1) / reg(r2) */ | |
3624 | tmp = load_reg(r1); | |
3625 | tmp2 = load_reg(r2); | |
3626 | tmp3 = load_reg((r1 + 1) & 15); | |
3627 | tcg_gen_ext32u_i64(tmp2, tmp2); | |
3628 | tcg_gen_ext32u_i64(tmp3, tmp3); | |
3629 | tcg_gen_shli_i64(tmp, tmp, 32); | |
3630 | tcg_gen_or_i64(tmp, tmp, tmp3); | |
3631 | ||
3632 | tcg_gen_rem_i64(tmp3, tmp, tmp2); | |
3633 | tcg_gen_div_i64(tmp, tmp, tmp2); | |
3634 | store_reg32_i64((r1 + 1) & 15, tmp); | |
3635 | store_reg32_i64(r1, tmp3); | |
3636 | tcg_temp_free_i64(tmp); | |
3637 | tcg_temp_free_i64(tmp2); | |
3638 | tcg_temp_free_i64(tmp3); | |
3639 | break; | |
3640 | case 0x98: /* ALCR R1,R2 [RRE] */ | |
3641 | tmp32_1 = load_reg32(r1); | |
3642 | tmp32_2 = load_reg32(r2); | |
3643 | tmp32_3 = tcg_temp_new_i32(); | |
3644 | /* XXX possible optimization point */ | |
3645 | gen_op_calc_cc(s); | |
3646 | gen_helper_addc_u32(tmp32_3, cc_op, tmp32_1, tmp32_2); | |
3647 | set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3); | |
3648 | store_reg32(r1, tmp32_3); | |
3649 | tcg_temp_free_i32(tmp32_1); | |
3650 | tcg_temp_free_i32(tmp32_2); | |
3651 | tcg_temp_free_i32(tmp32_3); | |
3652 | break; | |
3653 | case 0x99: /* SLBR R1,R2 [RRE] */ | |
3654 | tmp32_1 = load_reg32(r2); | |
3655 | tmp32_2 = tcg_const_i32(r1); | |
3656 | gen_op_calc_cc(s); | |
3657 | gen_helper_slb(cc_op, cc_op, tmp32_2, tmp32_1); | |
3658 | set_cc_static(s); | |
3659 | tcg_temp_free_i32(tmp32_1); | |
3660 | tcg_temp_free_i32(tmp32_2); | |
3661 | break; | |
3662 | default: | |
3663 | LOG_DISAS("illegal b9 operation 0x%x\n", op); | |
3664 | gen_illegal_opcode(s, 2); | |
3665 | break; | |
3666 | } | |
3667 | } | |
3668 | ||
3669 | static void disas_c0(DisasContext *s, int op, int r1, int i2) | |
3670 | { | |
3671 | TCGv_i64 tmp; | |
3672 | TCGv_i32 tmp32_1, tmp32_2; | |
3673 | uint64_t target = s->pc + i2 * 2LL; | |
3674 | int l1; | |
3675 | ||
3676 | LOG_DISAS("disas_c0: op 0x%x r1 %d i2 %d\n", op, r1, i2); | |
3677 | ||
3678 | switch (op) { | |
3679 | case 0: /* larl r1, i2 */ | |
3680 | tmp = tcg_const_i64(target); | |
3681 | store_reg(r1, tmp); | |
3682 | tcg_temp_free_i64(tmp); | |
3683 | break; | |
3684 | case 0x1: /* LGFI R1,I2 [RIL] */ | |
3685 | tmp = tcg_const_i64((int64_t)i2); | |
3686 | store_reg(r1, tmp); | |
3687 | tcg_temp_free_i64(tmp); | |
3688 | break; | |
3689 | case 0x4: /* BRCL M1,I2 [RIL] */ | |
3690 | /* m1 & (1 << (3 - cc)) */ | |
3691 | tmp32_1 = tcg_const_i32(3); | |
3692 | tmp32_2 = tcg_const_i32(1); | |
3693 | gen_op_calc_cc(s); | |
3694 | tcg_gen_sub_i32(tmp32_1, tmp32_1, cc_op); | |
3695 | tcg_gen_shl_i32(tmp32_2, tmp32_2, tmp32_1); | |
3696 | tcg_temp_free_i32(tmp32_1); | |
3697 | tmp32_1 = tcg_const_i32(r1); /* m1 == r1 */ | |
3698 | tcg_gen_and_i32(tmp32_1, tmp32_1, tmp32_2); | |
3699 | l1 = gen_new_label(); | |
3700 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp32_1, 0, l1); | |
3701 | gen_goto_tb(s, 0, target); | |
3702 | gen_set_label(l1); | |
3703 | gen_goto_tb(s, 1, s->pc + 6); | |
3704 | s->is_jmp = DISAS_TB_JUMP; | |
3705 | tcg_temp_free_i32(tmp32_1); | |
3706 | tcg_temp_free_i32(tmp32_2); | |
3707 | break; | |
3708 | case 0x5: /* brasl r1, i2 */ | |
3709 | tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 6)); | |
3710 | store_reg(r1, tmp); | |
3711 | tcg_temp_free_i64(tmp); | |
3712 | gen_goto_tb(s, 0, target); | |
3713 | s->is_jmp = DISAS_TB_JUMP; | |
3714 | break; | |
3715 | case 0x7: /* XILF R1,I2 [RIL] */ | |
3716 | case 0xb: /* NILF R1,I2 [RIL] */ | |
3717 | case 0xd: /* OILF R1,I2 [RIL] */ | |
3718 | tmp32_1 = load_reg32(r1); | |
3719 | switch (op) { | |
3720 | case 0x7: | |
3721 | tcg_gen_xori_i32(tmp32_1, tmp32_1, (uint32_t)i2); | |
3722 | break; | |
3723 | case 0xb: | |
3724 | tcg_gen_andi_i32(tmp32_1, tmp32_1, (uint32_t)i2); | |
3725 | break; | |
3726 | case 0xd: | |
3727 | tcg_gen_ori_i32(tmp32_1, tmp32_1, (uint32_t)i2); | |
3728 | break; | |
3729 | default: | |
3730 | tcg_abort(); | |
3731 | } | |
3732 | store_reg32(r1, tmp32_1); | |
3733 | set_cc_nz_u32(s, tmp32_1); | |
3734 | tcg_temp_free_i32(tmp32_1); | |
3735 | break; | |
3736 | case 0x9: /* IILF R1,I2 [RIL] */ | |
3737 | tmp32_1 = tcg_const_i32((uint32_t)i2); | |
3738 | store_reg32(r1, tmp32_1); | |
3739 | tcg_temp_free_i32(tmp32_1); | |
3740 | break; | |
3741 | case 0xa: /* NIHF R1,I2 [RIL] */ | |
3742 | tmp = load_reg(r1); | |
3743 | tmp32_1 = tcg_temp_new_i32(); | |
3744 | tcg_gen_andi_i64(tmp, tmp, (((uint64_t)((uint32_t)i2)) << 32) | |
3745 | | 0xffffffffULL); | |
3746 | store_reg(r1, tmp); | |
3747 | tcg_gen_shri_i64(tmp, tmp, 32); | |
3748 | tcg_gen_trunc_i64_i32(tmp32_1, tmp); | |
3749 | set_cc_nz_u32(s, tmp32_1); | |
3750 | tcg_temp_free_i64(tmp); | |
3751 | tcg_temp_free_i32(tmp32_1); | |
3752 | break; | |
3753 | case 0xe: /* LLIHF R1,I2 [RIL] */ | |
3754 | tmp = tcg_const_i64(((uint64_t)(uint32_t)i2) << 32); | |
3755 | store_reg(r1, tmp); | |
3756 | tcg_temp_free_i64(tmp); | |
3757 | break; | |
3758 | case 0xf: /* LLILF R1,I2 [RIL] */ | |
3759 | tmp = tcg_const_i64((uint32_t)i2); | |
3760 | store_reg(r1, tmp); | |
3761 | tcg_temp_free_i64(tmp); | |
3762 | break; | |
3763 | default: | |
3764 | LOG_DISAS("illegal c0 operation 0x%x\n", op); | |
3765 | gen_illegal_opcode(s, 3); | |
3766 | break; | |
3767 | } | |
3768 | } | |
3769 | ||
3770 | static void disas_c2(DisasContext *s, int op, int r1, int i2) | |
3771 | { | |
3772 | TCGv_i64 tmp, tmp2, tmp3; | |
3773 | TCGv_i32 tmp32_1, tmp32_2, tmp32_3; | |
3774 | ||
3775 | switch (op) { | |
3776 | case 0x4: /* SLGFI R1,I2 [RIL] */ | |
3777 | case 0xa: /* ALGFI R1,I2 [RIL] */ | |
3778 | tmp = load_reg(r1); | |
3779 | tmp2 = tcg_const_i64((uint64_t)(uint32_t)i2); | |
3780 | tmp3 = tcg_temp_new_i64(); | |
3781 | switch (op) { | |
3782 | case 0x4: | |
3783 | tcg_gen_sub_i64(tmp3, tmp, tmp2); | |
3784 | set_cc_subu64(s, tmp, tmp2, tmp3); | |
3785 | break; | |
3786 | case 0xa: | |
3787 | tcg_gen_add_i64(tmp3, tmp, tmp2); | |
3788 | set_cc_addu64(s, tmp, tmp2, tmp3); | |
3789 | break; | |
3790 | default: | |
3791 | tcg_abort(); | |
3792 | } | |
3793 | store_reg(r1, tmp3); | |
3794 | tcg_temp_free_i64(tmp); | |
3795 | tcg_temp_free_i64(tmp2); | |
3796 | tcg_temp_free_i64(tmp3); | |
3797 | break; | |
3798 | case 0x5: /* SLFI R1,I2 [RIL] */ | |
3799 | case 0xb: /* ALFI R1,I2 [RIL] */ | |
3800 | tmp32_1 = load_reg32(r1); | |
3801 | tmp32_2 = tcg_const_i32(i2); | |
3802 | tmp32_3 = tcg_temp_new_i32(); | |
3803 | switch (op) { | |
3804 | case 0x5: | |
3805 | tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2); | |
3806 | set_cc_subu32(s, tmp32_1, tmp32_2, tmp32_3); | |
3807 | break; | |
3808 | case 0xb: | |
3809 | tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2); | |
3810 | set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3); | |
3811 | break; | |
3812 | default: | |
3813 | tcg_abort(); | |
3814 | } | |
3815 | store_reg32(r1, tmp32_3); | |
3816 | tcg_temp_free_i32(tmp32_1); | |
3817 | tcg_temp_free_i32(tmp32_2); | |
3818 | tcg_temp_free_i32(tmp32_3); | |
3819 | break; | |
3820 | case 0xc: /* CGFI R1,I2 [RIL] */ | |
3821 | tmp = load_reg(r1); | |
3822 | cmp_s64c(s, tmp, (int64_t)i2); | |
3823 | tcg_temp_free_i64(tmp); | |
3824 | break; | |
3825 | case 0xe: /* CLGFI R1,I2 [RIL] */ | |
3826 | tmp = load_reg(r1); | |
3827 | cmp_u64c(s, tmp, (uint64_t)(uint32_t)i2); | |
3828 | tcg_temp_free_i64(tmp); | |
3829 | break; | |
3830 | case 0xd: /* CFI R1,I2 [RIL] */ | |
3831 | tmp32_1 = load_reg32(r1); | |
3832 | cmp_s32c(s, tmp32_1, i2); | |
3833 | tcg_temp_free_i32(tmp32_1); | |
3834 | break; | |
3835 | case 0xf: /* CLFI R1,I2 [RIL] */ | |
3836 | tmp32_1 = load_reg32(r1); | |
3837 | cmp_u32c(s, tmp32_1, i2); | |
3838 | tcg_temp_free_i32(tmp32_1); | |
3839 | break; | |
3840 | default: | |
3841 | LOG_DISAS("illegal c2 operation 0x%x\n", op); | |
3842 | gen_illegal_opcode(s, 3); | |
3843 | break; | |
3844 | } | |
3845 | } | |
3846 | ||
3847 | static void gen_and_or_xor_i32(int opc, TCGv_i32 tmp, TCGv_i32 tmp2) | |
3848 | { | |
3849 | switch (opc & 0xf) { | |
3850 | case 0x4: | |
3851 | tcg_gen_and_i32(tmp, tmp, tmp2); | |
3852 | break; | |
3853 | case 0x6: | |
3854 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
3855 | break; | |
3856 | case 0x7: | |
3857 | tcg_gen_xor_i32(tmp, tmp, tmp2); | |
3858 | break; | |
3859 | default: | |
3860 | tcg_abort(); | |
3861 | } | |
3862 | } | |
3863 | ||
3864 | static void disas_s390_insn(DisasContext *s) | |
3865 | { | |
3866 | TCGv_i64 tmp, tmp2, tmp3, tmp4; | |
3867 | TCGv_i32 tmp32_1, tmp32_2, tmp32_3, tmp32_4; | |
3868 | unsigned char opc; | |
3869 | uint64_t insn; | |
3870 | int op, r1, r2, r3, d1, d2, x2, b1, b2, i, i2, r1b; | |
3871 | TCGv_i32 vl; | |
3872 | int ilc; | |
3873 | int l1; | |
3874 | ||
3875 | opc = ldub_code(s->pc); | |
3876 | LOG_DISAS("opc 0x%x\n", opc); | |
3877 | ||
3878 | ilc = get_ilc(opc); | |
3879 | ||
3880 | switch (opc) { | |
3881 | #ifndef CONFIG_USER_ONLY | |
3882 | case 0x01: /* SAM */ | |
3883 | insn = ld_code2(s->pc); | |
3884 | /* set addressing mode, but we only do 64bit anyways */ | |
3885 | break; | |
3886 | #endif | |
3887 | case 0x6: /* BCTR R1,R2 [RR] */ | |
3888 | insn = ld_code2(s->pc); | |
3889 | decode_rr(s, insn, &r1, &r2); | |
3890 | tmp32_1 = load_reg32(r1); | |
3891 | tcg_gen_subi_i32(tmp32_1, tmp32_1, 1); | |
3892 | store_reg32(r1, tmp32_1); | |
3893 | ||
3894 | if (r2) { | |
3895 | gen_update_cc_op(s); | |
3896 | l1 = gen_new_label(); | |
3897 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp32_1, 0, l1); | |
3898 | ||
3899 | /* not taking the branch, jump to after the instruction */ | |
3900 | gen_goto_tb(s, 0, s->pc + 2); | |
3901 | gen_set_label(l1); | |
3902 | ||
3903 | /* take the branch, move R2 into psw.addr */ | |
3904 | tmp32_1 = load_reg32(r2); | |
3905 | tmp = tcg_temp_new_i64(); | |
3906 | tcg_gen_extu_i32_i64(tmp, tmp32_1); | |
3907 | tcg_gen_mov_i64(psw_addr, tmp); | |
3908 | s->is_jmp = DISAS_JUMP; | |
3909 | tcg_temp_free_i32(tmp32_1); | |
3910 | tcg_temp_free_i64(tmp); | |
3911 | } | |
3912 | break; | |
3913 | case 0x7: /* BCR M1,R2 [RR] */ | |
3914 | insn = ld_code2(s->pc); | |
3915 | decode_rr(s, insn, &r1, &r2); | |
3916 | if (r2) { | |
3917 | tmp = load_reg(r2); | |
3918 | gen_bcr(s, r1, tmp, s->pc); | |
3919 | tcg_temp_free_i64(tmp); | |
3920 | s->is_jmp = DISAS_TB_JUMP; | |
3921 | } else { | |
3922 | /* XXX: "serialization and checkpoint-synchronization function"? */ | |
3923 | } | |
3924 | break; | |
3925 | case 0xa: /* SVC I [RR] */ | |
3926 | insn = ld_code2(s->pc); | |
3927 | debug_insn(insn); | |
3928 | i = insn & 0xff; | |
3929 | update_psw_addr(s); | |
3930 | gen_op_calc_cc(s); | |
3931 | tmp32_1 = tcg_const_i32(i); | |
3932 | tmp32_2 = tcg_const_i32(ilc * 2); | |
3933 | tmp32_3 = tcg_const_i32(EXCP_SVC); | |
3934 | tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, int_svc_code)); | |
3935 | tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUState, int_svc_ilc)); | |
3936 | gen_helper_exception(tmp32_3); | |
3937 | s->is_jmp = DISAS_EXCP; | |
3938 | tcg_temp_free_i32(tmp32_1); | |
3939 | tcg_temp_free_i32(tmp32_2); | |
3940 | tcg_temp_free_i32(tmp32_3); | |
3941 | break; | |
3942 | case 0xd: /* BASR R1,R2 [RR] */ | |
3943 | insn = ld_code2(s->pc); | |
3944 | decode_rr(s, insn, &r1, &r2); | |
3945 | tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 2)); | |
3946 | store_reg(r1, tmp); | |
3947 | if (r2) { | |
3948 | tmp2 = load_reg(r2); | |
3949 | tcg_gen_mov_i64(psw_addr, tmp2); | |
3950 | tcg_temp_free_i64(tmp2); | |
3951 | s->is_jmp = DISAS_JUMP; | |
3952 | } | |
3953 | tcg_temp_free_i64(tmp); | |
3954 | break; | |
3955 | case 0xe: /* MVCL R1,R2 [RR] */ | |
3956 | insn = ld_code2(s->pc); | |
3957 | decode_rr(s, insn, &r1, &r2); | |
3958 | tmp32_1 = tcg_const_i32(r1); | |
3959 | tmp32_2 = tcg_const_i32(r2); | |
3960 | potential_page_fault(s); | |
3961 | gen_helper_mvcl(cc_op, tmp32_1, tmp32_2); | |
3962 | set_cc_static(s); | |
3963 | tcg_temp_free_i32(tmp32_1); | |
3964 | tcg_temp_free_i32(tmp32_2); | |
3965 | break; | |
3966 | case 0x10: /* LPR R1,R2 [RR] */ | |
3967 | insn = ld_code2(s->pc); | |
3968 | decode_rr(s, insn, &r1, &r2); | |
3969 | tmp32_1 = load_reg32(r2); | |
3970 | set_cc_abs32(s, tmp32_1); | |
3971 | gen_helper_abs_i32(tmp32_1, tmp32_1); | |
3972 | store_reg32(r1, tmp32_1); | |
3973 | tcg_temp_free_i32(tmp32_1); | |
3974 | break; | |
3975 | case 0x11: /* LNR R1,R2 [RR] */ | |
3976 | insn = ld_code2(s->pc); | |
3977 | decode_rr(s, insn, &r1, &r2); | |
3978 | tmp32_1 = load_reg32(r2); | |
3979 | set_cc_nabs32(s, tmp32_1); | |
3980 | gen_helper_nabs_i32(tmp32_1, tmp32_1); | |
3981 | store_reg32(r1, tmp32_1); | |
3982 | tcg_temp_free_i32(tmp32_1); | |
3983 | break; | |
3984 | case 0x12: /* LTR R1,R2 [RR] */ | |
3985 | insn = ld_code2(s->pc); | |
3986 | decode_rr(s, insn, &r1, &r2); | |
3987 | tmp32_1 = load_reg32(r2); | |
3988 | if (r1 != r2) { | |
3989 | store_reg32(r1, tmp32_1); | |
3990 | } | |
3991 | set_cc_s32(s, tmp32_1); | |
3992 | tcg_temp_free_i32(tmp32_1); | |
3993 | break; | |
3994 | case 0x13: /* LCR R1,R2 [RR] */ | |
3995 | insn = ld_code2(s->pc); | |
3996 | decode_rr(s, insn, &r1, &r2); | |
3997 | tmp32_1 = load_reg32(r2); | |
3998 | tcg_gen_neg_i32(tmp32_1, tmp32_1); | |
3999 | store_reg32(r1, tmp32_1); | |
4000 | set_cc_comp32(s, tmp32_1); | |
4001 | tcg_temp_free_i32(tmp32_1); | |
4002 | break; | |
4003 | case 0x14: /* NR R1,R2 [RR] */ | |
4004 | case 0x16: /* OR R1,R2 [RR] */ | |
4005 | case 0x17: /* XR R1,R2 [RR] */ | |
4006 | insn = ld_code2(s->pc); | |
4007 | decode_rr(s, insn, &r1, &r2); | |
4008 | tmp32_2 = load_reg32(r2); | |
4009 | tmp32_1 = load_reg32(r1); | |
4010 | gen_and_or_xor_i32(opc, tmp32_1, tmp32_2); | |
4011 | store_reg32(r1, tmp32_1); | |
4012 | set_cc_nz_u32(s, tmp32_1); | |
4013 | tcg_temp_free_i32(tmp32_1); | |
4014 | tcg_temp_free_i32(tmp32_2); | |
4015 | break; | |
4016 | case 0x18: /* LR R1,R2 [RR] */ | |
4017 | insn = ld_code2(s->pc); | |
4018 | decode_rr(s, insn, &r1, &r2); | |
4019 | tmp32_1 = load_reg32(r2); | |
4020 | store_reg32(r1, tmp32_1); | |
4021 | tcg_temp_free_i32(tmp32_1); | |
4022 | break; | |
4023 | case 0x15: /* CLR R1,R2 [RR] */ | |
4024 | case 0x19: /* CR R1,R2 [RR] */ | |
4025 | insn = ld_code2(s->pc); | |
4026 | decode_rr(s, insn, &r1, &r2); | |
4027 | tmp32_1 = load_reg32(r1); | |
4028 | tmp32_2 = load_reg32(r2); | |
4029 | if (opc == 0x15) { | |
4030 | cmp_u32(s, tmp32_1, tmp32_2); | |
4031 | } else { | |
4032 | cmp_s32(s, tmp32_1, tmp32_2); | |
4033 | } | |
4034 | tcg_temp_free_i32(tmp32_1); | |
4035 | tcg_temp_free_i32(tmp32_2); | |
4036 | break; | |
4037 | case 0x1a: /* AR R1,R2 [RR] */ | |
4038 | case 0x1e: /* ALR R1,R2 [RR] */ | |
4039 | insn = ld_code2(s->pc); | |
4040 | decode_rr(s, insn, &r1, &r2); | |
4041 | tmp32_1 = load_reg32(r1); | |
4042 | tmp32_2 = load_reg32(r2); | |
4043 | tmp32_3 = tcg_temp_new_i32(); | |
4044 | tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2); | |
4045 | store_reg32(r1, tmp32_3); | |
4046 | if (opc == 0x1a) { | |
4047 | set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3); | |
4048 | } else { | |
4049 | set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3); | |
4050 | } | |
4051 | tcg_temp_free_i32(tmp32_1); | |
4052 | tcg_temp_free_i32(tmp32_2); | |
4053 | tcg_temp_free_i32(tmp32_3); | |
4054 | break; | |
4055 | case 0x1b: /* SR R1,R2 [RR] */ | |
4056 | case 0x1f: /* SLR R1,R2 [RR] */ | |
4057 | insn = ld_code2(s->pc); | |
4058 | decode_rr(s, insn, &r1, &r2); | |
4059 | tmp32_1 = load_reg32(r1); | |
4060 | tmp32_2 = load_reg32(r2); | |
4061 | tmp32_3 = tcg_temp_new_i32(); | |
4062 | tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2); | |
4063 | store_reg32(r1, tmp32_3); | |
4064 | if (opc == 0x1b) { | |
4065 | set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3); | |
4066 | } else { | |
4067 | set_cc_subu32(s, tmp32_1, tmp32_2, tmp32_3); | |
4068 | } | |
4069 | tcg_temp_free_i32(tmp32_1); | |
4070 | tcg_temp_free_i32(tmp32_2); | |
4071 | tcg_temp_free_i32(tmp32_3); | |
4072 | break; | |
4073 | case 0x1c: /* MR R1,R2 [RR] */ | |
4074 | /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */ | |
4075 | insn = ld_code2(s->pc); | |
4076 | decode_rr(s, insn, &r1, &r2); | |
4077 | tmp2 = load_reg(r2); | |
4078 | tmp3 = load_reg((r1 + 1) & 15); | |
4079 | tcg_gen_ext32s_i64(tmp2, tmp2); | |
4080 | tcg_gen_ext32s_i64(tmp3, tmp3); | |
4081 | tcg_gen_mul_i64(tmp2, tmp2, tmp3); | |
4082 | store_reg32_i64((r1 + 1) & 15, tmp2); | |
4083 | tcg_gen_shri_i64(tmp2, tmp2, 32); | |
4084 | store_reg32_i64(r1, tmp2); | |
4085 | tcg_temp_free_i64(tmp2); | |
4086 | tcg_temp_free_i64(tmp3); | |
4087 | break; | |
4088 | case 0x1d: /* DR R1,R2 [RR] */ | |
4089 | insn = ld_code2(s->pc); | |
4090 | decode_rr(s, insn, &r1, &r2); | |
4091 | tmp32_1 = load_reg32(r1); | |
4092 | tmp32_2 = load_reg32(r1 + 1); | |
4093 | tmp32_3 = load_reg32(r2); | |
4094 | ||
4095 | tmp = tcg_temp_new_i64(); /* dividend */ | |
4096 | tmp2 = tcg_temp_new_i64(); /* divisor */ | |
4097 | tmp3 = tcg_temp_new_i64(); | |
4098 | ||
4099 | /* dividend is r(r1 << 32) | r(r1 + 1) */ | |
4100 | tcg_gen_extu_i32_i64(tmp, tmp32_1); | |
4101 | tcg_gen_extu_i32_i64(tmp2, tmp32_2); | |
4102 | tcg_gen_shli_i64(tmp, tmp, 32); | |
4103 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
4104 | ||
4105 | /* divisor is r(r2) */ | |
4106 | tcg_gen_ext_i32_i64(tmp2, tmp32_3); | |
4107 | ||
4108 | tcg_gen_div_i64(tmp3, tmp, tmp2); | |
4109 | tcg_gen_rem_i64(tmp, tmp, tmp2); | |
4110 | ||
4111 | tcg_gen_trunc_i64_i32(tmp32_1, tmp); | |
4112 | tcg_gen_trunc_i64_i32(tmp32_2, tmp3); | |
4113 | ||
4114 | store_reg32(r1, tmp32_1); /* remainder */ | |
4115 | store_reg32(r1 + 1, tmp32_2); /* quotient */ | |
4116 | tcg_temp_free_i32(tmp32_1); | |
4117 | tcg_temp_free_i32(tmp32_2); | |
4118 | tcg_temp_free_i32(tmp32_3); | |
4119 | tcg_temp_free_i64(tmp); | |
4120 | tcg_temp_free_i64(tmp2); | |
4121 | tcg_temp_free_i64(tmp3); | |
4122 | break; | |
4123 | case 0x28: /* LDR R1,R2 [RR] */ | |
4124 | insn = ld_code2(s->pc); | |
4125 | decode_rr(s, insn, &r1, &r2); | |
4126 | tmp = load_freg(r2); | |
4127 | store_freg(r1, tmp); | |
4128 | tcg_temp_free_i64(tmp); | |
4129 | break; | |
4130 | case 0x38: /* LER R1,R2 [RR] */ | |
4131 | insn = ld_code2(s->pc); | |
4132 | decode_rr(s, insn, &r1, &r2); | |
4133 | tmp32_1 = load_freg32(r2); | |
4134 | store_freg32(r1, tmp32_1); | |
4135 | tcg_temp_free_i32(tmp32_1); | |
4136 | break; | |
4137 | case 0x40: /* STH R1,D2(X2,B2) [RX] */ | |
4138 | insn = ld_code4(s->pc); | |
4139 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4140 | tmp2 = load_reg(r1); | |
4141 | tcg_gen_qemu_st16(tmp2, tmp, get_mem_index(s)); | |
4142 | tcg_temp_free_i64(tmp); | |
4143 | tcg_temp_free_i64(tmp2); | |
4144 | break; | |
4145 | case 0x41: /* la */ | |
4146 | insn = ld_code4(s->pc); | |
4147 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4148 | store_reg(r1, tmp); /* FIXME: 31/24-bit addressing */ | |
4149 | tcg_temp_free_i64(tmp); | |
4150 | break; | |
4151 | case 0x42: /* STC R1,D2(X2,B2) [RX] */ | |
4152 | insn = ld_code4(s->pc); | |
4153 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4154 | tmp2 = load_reg(r1); | |
4155 | tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s)); | |
4156 | tcg_temp_free_i64(tmp); | |
4157 | tcg_temp_free_i64(tmp2); | |
4158 | break; | |
4159 | case 0x43: /* IC R1,D2(X2,B2) [RX] */ | |
4160 | insn = ld_code4(s->pc); | |
4161 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4162 | tmp2 = tcg_temp_new_i64(); | |
4163 | tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s)); | |
4164 | store_reg8(r1, tmp2); | |
4165 | tcg_temp_free_i64(tmp); | |
4166 | tcg_temp_free_i64(tmp2); | |
4167 | break; | |
4168 | case 0x44: /* EX R1,D2(X2,B2) [RX] */ | |
4169 | insn = ld_code4(s->pc); | |
4170 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4171 | tmp2 = load_reg(r1); | |
4172 | tmp3 = tcg_const_i64(s->pc + 4); | |
4173 | update_psw_addr(s); | |
4174 | gen_op_calc_cc(s); | |
4175 | gen_helper_ex(cc_op, cc_op, tmp2, tmp, tmp3); | |
4176 | set_cc_static(s); | |
4177 | tcg_temp_free_i64(tmp); | |
4178 | tcg_temp_free_i64(tmp2); | |
4179 | tcg_temp_free_i64(tmp3); | |
4180 | break; | |
4181 | case 0x46: /* BCT R1,D2(X2,B2) [RX] */ | |
4182 | insn = ld_code4(s->pc); | |
4183 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4184 | tcg_temp_free_i64(tmp); | |
4185 | ||
4186 | tmp32_1 = load_reg32(r1); | |
4187 | tcg_gen_subi_i32(tmp32_1, tmp32_1, 1); | |
4188 | store_reg32(r1, tmp32_1); | |
4189 | ||
4190 | gen_update_cc_op(s); | |
4191 | l1 = gen_new_label(); | |
4192 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp32_1, 0, l1); | |
4193 | ||
4194 | /* not taking the branch, jump to after the instruction */ | |
4195 | gen_goto_tb(s, 0, s->pc + 4); | |
4196 | gen_set_label(l1); | |
4197 | ||
4198 | /* take the branch, move R2 into psw.addr */ | |
4199 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4200 | tcg_gen_mov_i64(psw_addr, tmp); | |
4201 | s->is_jmp = DISAS_JUMP; | |
4202 | tcg_temp_free_i32(tmp32_1); | |
4203 | tcg_temp_free_i64(tmp); | |
4204 | break; | |
4205 | case 0x47: /* BC M1,D2(X2,B2) [RX] */ | |
4206 | insn = ld_code4(s->pc); | |
4207 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4208 | gen_bcr(s, r1, tmp, s->pc + 4); | |
4209 | tcg_temp_free_i64(tmp); | |
4210 | s->is_jmp = DISAS_TB_JUMP; | |
4211 | break; | |
4212 | case 0x48: /* LH R1,D2(X2,B2) [RX] */ | |
4213 | insn = ld_code4(s->pc); | |
4214 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4215 | tmp2 = tcg_temp_new_i64(); | |
4216 | tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s)); | |
4217 | store_reg32_i64(r1, tmp2); | |
4218 | tcg_temp_free_i64(tmp); | |
4219 | tcg_temp_free_i64(tmp2); | |
4220 | break; | |
4221 | case 0x49: /* CH R1,D2(X2,B2) [RX] */ | |
4222 | insn = ld_code4(s->pc); | |
4223 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4224 | tmp32_1 = load_reg32(r1); | |
4225 | tmp32_2 = tcg_temp_new_i32(); | |
4226 | tmp2 = tcg_temp_new_i64(); | |
4227 | tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s)); | |
4228 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
4229 | cmp_s32(s, tmp32_1, tmp32_2); | |
4230 | tcg_temp_free_i32(tmp32_1); | |
4231 | tcg_temp_free_i32(tmp32_2); | |
4232 | tcg_temp_free_i64(tmp); | |
4233 | tcg_temp_free_i64(tmp2); | |
4234 | break; | |
4235 | case 0x4a: /* AH R1,D2(X2,B2) [RX] */ | |
4236 | case 0x4b: /* SH R1,D2(X2,B2) [RX] */ | |
4237 | case 0x4c: /* MH R1,D2(X2,B2) [RX] */ | |
4238 | insn = ld_code4(s->pc); | |
4239 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4240 | tmp2 = tcg_temp_new_i64(); | |
4241 | tmp32_1 = load_reg32(r1); | |
4242 | tmp32_2 = tcg_temp_new_i32(); | |
4243 | tmp32_3 = tcg_temp_new_i32(); | |
4244 | ||
4245 | tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s)); | |
4246 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
4247 | switch (opc) { | |
4248 | case 0x4a: | |
4249 | tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2); | |
4250 | set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3); | |
4251 | break; | |
4252 | case 0x4b: | |
4253 | tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2); | |
4254 | set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3); | |
4255 | break; | |
4256 | case 0x4c: | |
4257 | tcg_gen_mul_i32(tmp32_3, tmp32_1, tmp32_2); | |
4258 | break; | |
4259 | default: | |
4260 | tcg_abort(); | |
4261 | } | |
4262 | store_reg32(r1, tmp32_3); | |
4263 | ||
4264 | tcg_temp_free_i32(tmp32_1); | |
4265 | tcg_temp_free_i32(tmp32_2); | |
4266 | tcg_temp_free_i32(tmp32_3); | |
4267 | tcg_temp_free_i64(tmp); | |
4268 | tcg_temp_free_i64(tmp2); | |
4269 | break; | |
4270 | case 0x4d: /* BAS R1,D2(X2,B2) [RX] */ | |
4271 | insn = ld_code4(s->pc); | |
4272 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4273 | tmp2 = tcg_const_i64(pc_to_link_info(s, s->pc + 4)); | |
4274 | store_reg(r1, tmp2); | |
4275 | tcg_gen_mov_i64(psw_addr, tmp); | |
4276 | tcg_temp_free_i64(tmp); | |
4277 | tcg_temp_free_i64(tmp2); | |
4278 | s->is_jmp = DISAS_JUMP; | |
4279 | break; | |
4280 | case 0x4e: /* CVD R1,D2(X2,B2) [RX] */ | |
4281 | insn = ld_code4(s->pc); | |
4282 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4283 | tmp2 = tcg_temp_new_i64(); | |
4284 | tmp32_1 = tcg_temp_new_i32(); | |
4285 | tcg_gen_trunc_i64_i32(tmp32_1, regs[r1]); | |
4286 | gen_helper_cvd(tmp2, tmp32_1); | |
4287 | tcg_gen_qemu_st64(tmp2, tmp, get_mem_index(s)); | |
4288 | tcg_temp_free_i64(tmp); | |
4289 | tcg_temp_free_i64(tmp2); | |
4290 | tcg_temp_free_i32(tmp32_1); | |
4291 | break; | |
4292 | case 0x50: /* st r1, d2(x2, b2) */ | |
4293 | insn = ld_code4(s->pc); | |
4294 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4295 | tmp2 = load_reg(r1); | |
4296 | tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s)); | |
4297 | tcg_temp_free_i64(tmp); | |
4298 | tcg_temp_free_i64(tmp2); | |
4299 | break; | |
4300 | case 0x55: /* CL R1,D2(X2,B2) [RX] */ | |
4301 | insn = ld_code4(s->pc); | |
4302 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4303 | tmp2 = tcg_temp_new_i64(); | |
4304 | tmp32_1 = tcg_temp_new_i32(); | |
4305 | tmp32_2 = load_reg32(r1); | |
4306 | tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); | |
4307 | tcg_gen_trunc_i64_i32(tmp32_1, tmp2); | |
4308 | cmp_u32(s, tmp32_2, tmp32_1); | |
4309 | tcg_temp_free_i64(tmp); | |
4310 | tcg_temp_free_i64(tmp2); | |
4311 | tcg_temp_free_i32(tmp32_1); | |
4312 | tcg_temp_free_i32(tmp32_2); | |
4313 | break; | |
4314 | case 0x54: /* N R1,D2(X2,B2) [RX] */ | |
4315 | case 0x56: /* O R1,D2(X2,B2) [RX] */ | |
4316 | case 0x57: /* X R1,D2(X2,B2) [RX] */ | |
4317 | insn = ld_code4(s->pc); | |
4318 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4319 | tmp2 = tcg_temp_new_i64(); | |
4320 | tmp32_1 = load_reg32(r1); | |
4321 | tmp32_2 = tcg_temp_new_i32(); | |
4322 | tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); | |
4323 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
4324 | gen_and_or_xor_i32(opc, tmp32_1, tmp32_2); | |
4325 | store_reg32(r1, tmp32_1); | |
4326 | set_cc_nz_u32(s, tmp32_1); | |
4327 | tcg_temp_free_i64(tmp); | |
4328 | tcg_temp_free_i64(tmp2); | |
4329 | tcg_temp_free_i32(tmp32_1); | |
4330 | tcg_temp_free_i32(tmp32_2); | |
4331 | break; | |
4332 | case 0x58: /* l r1, d2(x2, b2) */ | |
4333 | insn = ld_code4(s->pc); | |
4334 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4335 | tmp2 = tcg_temp_new_i64(); | |
4336 | tmp32_1 = tcg_temp_new_i32(); | |
4337 | tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); | |
4338 | tcg_gen_trunc_i64_i32(tmp32_1, tmp2); | |
4339 | store_reg32(r1, tmp32_1); | |
4340 | tcg_temp_free_i64(tmp); | |
4341 | tcg_temp_free_i64(tmp2); | |
4342 | tcg_temp_free_i32(tmp32_1); | |
4343 | break; | |
4344 | case 0x59: /* C R1,D2(X2,B2) [RX] */ | |
4345 | insn = ld_code4(s->pc); | |
4346 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4347 | tmp2 = tcg_temp_new_i64(); | |
4348 | tmp32_1 = tcg_temp_new_i32(); | |
4349 | tmp32_2 = load_reg32(r1); | |
4350 | tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s)); | |
4351 | tcg_gen_trunc_i64_i32(tmp32_1, tmp2); | |
4352 | cmp_s32(s, tmp32_2, tmp32_1); | |
4353 | tcg_temp_free_i64(tmp); | |
4354 | tcg_temp_free_i64(tmp2); | |
4355 | tcg_temp_free_i32(tmp32_1); | |
4356 | tcg_temp_free_i32(tmp32_2); | |
4357 | break; | |
4358 | case 0x5a: /* A R1,D2(X2,B2) [RX] */ | |
4359 | case 0x5b: /* S R1,D2(X2,B2) [RX] */ | |
4360 | case 0x5e: /* AL R1,D2(X2,B2) [RX] */ | |
4361 | case 0x5f: /* SL R1,D2(X2,B2) [RX] */ | |
4362 | insn = ld_code4(s->pc); | |
4363 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4364 | tmp32_1 = load_reg32(r1); | |
4365 | tmp32_2 = tcg_temp_new_i32(); | |
4366 | tmp32_3 = tcg_temp_new_i32(); | |
4367 | tcg_gen_qemu_ld32s(tmp, tmp, get_mem_index(s)); | |
4368 | tcg_gen_trunc_i64_i32(tmp32_2, tmp); | |
4369 | switch (opc) { | |
4370 | case 0x5a: | |
4371 | case 0x5e: | |
4372 | tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2); | |
4373 | break; | |
4374 | case 0x5b: | |
4375 | case 0x5f: | |
4376 | tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2); | |
4377 | break; | |
4378 | default: | |
4379 | tcg_abort(); | |
4380 | } | |
4381 | store_reg32(r1, tmp32_3); | |
4382 | switch (opc) { | |
4383 | case 0x5a: | |
4384 | set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3); | |
4385 | break; | |
4386 | case 0x5e: | |
4387 | set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3); | |
4388 | break; | |
4389 | case 0x5b: | |
4390 | set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3); | |
4391 | break; | |
4392 | case 0x5f: | |
4393 | set_cc_subu32(s, tmp32_1, tmp32_2, tmp32_3); | |
4394 | break; | |
4395 | default: | |
4396 | tcg_abort(); | |
4397 | } | |
4398 | tcg_temp_free_i64(tmp); | |
4399 | tcg_temp_free_i32(tmp32_1); | |
4400 | tcg_temp_free_i32(tmp32_2); | |
4401 | tcg_temp_free_i32(tmp32_3); | |
4402 | break; | |
4403 | case 0x5c: /* M R1,D2(X2,B2) [RX] */ | |
4404 | /* reg(r1, r1+1) = reg(r1+1) * *(s32*)addr */ | |
4405 | insn = ld_code4(s->pc); | |
4406 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4407 | tmp2 = tcg_temp_new_i64(); | |
4408 | tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s)); | |
4409 | tmp3 = load_reg((r1 + 1) & 15); | |
4410 | tcg_gen_ext32s_i64(tmp2, tmp2); | |
4411 | tcg_gen_ext32s_i64(tmp3, tmp3); | |
4412 | tcg_gen_mul_i64(tmp2, tmp2, tmp3); | |
4413 | store_reg32_i64((r1 + 1) & 15, tmp2); | |
4414 | tcg_gen_shri_i64(tmp2, tmp2, 32); | |
4415 | store_reg32_i64(r1, tmp2); | |
4416 | tcg_temp_free_i64(tmp); | |
4417 | tcg_temp_free_i64(tmp2); | |
4418 | tcg_temp_free_i64(tmp3); | |
4419 | break; | |
4420 | case 0x5d: /* D R1,D2(X2,B2) [RX] */ | |
4421 | insn = ld_code4(s->pc); | |
4422 | tmp3 = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4423 | tmp32_1 = load_reg32(r1); | |
4424 | tmp32_2 = load_reg32(r1 + 1); | |
4425 | ||
4426 | tmp = tcg_temp_new_i64(); | |
4427 | tmp2 = tcg_temp_new_i64(); | |
4428 | ||
4429 | /* dividend is r(r1 << 32) | r(r1 + 1) */ | |
4430 | tcg_gen_extu_i32_i64(tmp, tmp32_1); | |
4431 | tcg_gen_extu_i32_i64(tmp2, tmp32_2); | |
4432 | tcg_gen_shli_i64(tmp, tmp, 32); | |
4433 | tcg_gen_or_i64(tmp, tmp, tmp2); | |
4434 | ||
4435 | /* divisor is in memory */ | |
4436 | tcg_gen_qemu_ld32s(tmp2, tmp3, get_mem_index(s)); | |
4437 | ||
4438 | /* XXX divisor == 0 -> FixP divide exception */ | |
4439 | ||
4440 | tcg_gen_div_i64(tmp3, tmp, tmp2); | |
4441 | tcg_gen_rem_i64(tmp, tmp, tmp2); | |
4442 | ||
4443 | tcg_gen_trunc_i64_i32(tmp32_1, tmp); | |
4444 | tcg_gen_trunc_i64_i32(tmp32_2, tmp3); | |
4445 | ||
4446 | store_reg32(r1, tmp32_1); /* remainder */ | |
4447 | store_reg32(r1 + 1, tmp32_2); /* quotient */ | |
4448 | tcg_temp_free_i32(tmp32_1); | |
4449 | tcg_temp_free_i32(tmp32_2); | |
4450 | tcg_temp_free_i64(tmp); | |
4451 | tcg_temp_free_i64(tmp2); | |
4452 | tcg_temp_free_i64(tmp3); | |
4453 | break; | |
4454 | case 0x60: /* STD R1,D2(X2,B2) [RX] */ | |
4455 | insn = ld_code4(s->pc); | |
4456 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4457 | tmp2 = load_freg(r1); | |
4458 | tcg_gen_qemu_st64(tmp2, tmp, get_mem_index(s)); | |
4459 | tcg_temp_free_i64(tmp); | |
4460 | tcg_temp_free_i64(tmp2); | |
4461 | break; | |
4462 | case 0x68: /* LD R1,D2(X2,B2) [RX] */ | |
4463 | insn = ld_code4(s->pc); | |
4464 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4465 | tmp2 = tcg_temp_new_i64(); | |
4466 | tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s)); | |
4467 | store_freg(r1, tmp2); | |
4468 | tcg_temp_free_i64(tmp); | |
4469 | tcg_temp_free_i64(tmp2); | |
4470 | break; | |
4471 | case 0x70: /* STE R1,D2(X2,B2) [RX] */ | |
4472 | insn = ld_code4(s->pc); | |
4473 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4474 | tmp2 = tcg_temp_new_i64(); | |
4475 | tmp32_1 = load_freg32(r1); | |
4476 | tcg_gen_extu_i32_i64(tmp2, tmp32_1); | |
4477 | tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s)); | |
4478 | tcg_temp_free_i64(tmp); | |
4479 | tcg_temp_free_i64(tmp2); | |
4480 | tcg_temp_free_i32(tmp32_1); | |
4481 | break; | |
4482 | case 0x71: /* MS R1,D2(X2,B2) [RX] */ | |
4483 | insn = ld_code4(s->pc); | |
4484 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4485 | tmp2 = tcg_temp_new_i64(); | |
4486 | tmp32_1 = load_reg32(r1); | |
4487 | tmp32_2 = tcg_temp_new_i32(); | |
4488 | tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s)); | |
4489 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
4490 | tcg_gen_mul_i32(tmp32_1, tmp32_1, tmp32_2); | |
4491 | store_reg32(r1, tmp32_1); | |
4492 | tcg_temp_free_i64(tmp); | |
4493 | tcg_temp_free_i64(tmp2); | |
4494 | tcg_temp_free_i32(tmp32_1); | |
4495 | tcg_temp_free_i32(tmp32_2); | |
4496 | break; | |
4497 | case 0x78: /* LE R1,D2(X2,B2) [RX] */ | |
4498 | insn = ld_code4(s->pc); | |
4499 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4500 | tmp2 = tcg_temp_new_i64(); | |
4501 | tmp32_1 = tcg_temp_new_i32(); | |
4502 | tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); | |
4503 | tcg_gen_trunc_i64_i32(tmp32_1, tmp2); | |
4504 | store_freg32(r1, tmp32_1); | |
4505 | tcg_temp_free_i64(tmp); | |
4506 | tcg_temp_free_i64(tmp2); | |
4507 | tcg_temp_free_i32(tmp32_1); | |
4508 | break; | |
4509 | #ifndef CONFIG_USER_ONLY | |
4510 | case 0x80: /* SSM D2(B2) [S] */ | |
4511 | /* Set System Mask */ | |
4512 | check_privileged(s, ilc); | |
4513 | insn = ld_code4(s->pc); | |
4514 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4515 | tmp = get_address(s, 0, b2, d2); | |
4516 | tmp2 = tcg_temp_new_i64(); | |
4517 | tmp3 = tcg_temp_new_i64(); | |
4518 | tcg_gen_andi_i64(tmp3, psw_mask, ~0xff00000000000000ULL); | |
4519 | tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s)); | |
4520 | tcg_gen_shli_i64(tmp2, tmp2, 56); | |
4521 | tcg_gen_or_i64(psw_mask, tmp3, tmp2); | |
4522 | tcg_temp_free_i64(tmp); | |
4523 | tcg_temp_free_i64(tmp2); | |
4524 | tcg_temp_free_i64(tmp3); | |
4525 | break; | |
4526 | case 0x82: /* LPSW D2(B2) [S] */ | |
4527 | /* Load PSW */ | |
4528 | check_privileged(s, ilc); | |
4529 | insn = ld_code4(s->pc); | |
4530 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4531 | tmp = get_address(s, 0, b2, d2); | |
4532 | tmp2 = tcg_temp_new_i64(); | |
4533 | tmp3 = tcg_temp_new_i64(); | |
4534 | tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); | |
4535 | tcg_gen_addi_i64(tmp, tmp, 4); | |
4536 | tcg_gen_qemu_ld32u(tmp3, tmp, get_mem_index(s)); | |
4537 | gen_helper_load_psw(tmp2, tmp3); | |
4538 | tcg_temp_free_i64(tmp); | |
4539 | tcg_temp_free_i64(tmp2); | |
4540 | tcg_temp_free_i64(tmp3); | |
4541 | /* we need to keep cc_op intact */ | |
4542 | s->is_jmp = DISAS_JUMP; | |
4543 | break; | |
4544 | case 0x83: /* DIAG R1,R3,D2 [RS] */ | |
4545 | /* Diagnose call (KVM hypercall) */ | |
4546 | check_privileged(s, ilc); | |
4547 | potential_page_fault(s); | |
4548 | insn = ld_code4(s->pc); | |
4549 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4550 | tmp32_1 = tcg_const_i32(insn & 0xfff); | |
4551 | tmp2 = load_reg(2); | |
4552 | tmp3 = load_reg(1); | |
4553 | gen_helper_diag(tmp2, tmp32_1, tmp2, tmp3); | |
4554 | store_reg(2, tmp2); | |
4555 | tcg_temp_free_i32(tmp32_1); | |
4556 | tcg_temp_free_i64(tmp2); | |
4557 | tcg_temp_free_i64(tmp3); | |
4558 | break; | |
4559 | #endif | |
4560 | case 0x88: /* SRL R1,D2(B2) [RS] */ | |
4561 | case 0x89: /* SLL R1,D2(B2) [RS] */ | |
4562 | case 0x8a: /* SRA R1,D2(B2) [RS] */ | |
4563 | insn = ld_code4(s->pc); | |
4564 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4565 | tmp = get_address(s, 0, b2, d2); | |
4566 | tmp32_1 = load_reg32(r1); | |
4567 | tmp32_2 = tcg_temp_new_i32(); | |
4568 | tcg_gen_trunc_i64_i32(tmp32_2, tmp); | |
4569 | tcg_gen_andi_i32(tmp32_2, tmp32_2, 0x3f); | |
4570 | switch (opc) { | |
4571 | case 0x88: | |
4572 | tcg_gen_shr_i32(tmp32_1, tmp32_1, tmp32_2); | |
4573 | break; | |
4574 | case 0x89: | |
4575 | tcg_gen_shl_i32(tmp32_1, tmp32_1, tmp32_2); | |
4576 | break; | |
4577 | case 0x8a: | |
4578 | tcg_gen_sar_i32(tmp32_1, tmp32_1, tmp32_2); | |
4579 | set_cc_s32(s, tmp32_1); | |
4580 | break; | |
4581 | default: | |
4582 | tcg_abort(); | |
4583 | } | |
4584 | store_reg32(r1, tmp32_1); | |
4585 | tcg_temp_free_i64(tmp); | |
4586 | tcg_temp_free_i32(tmp32_1); | |
4587 | tcg_temp_free_i32(tmp32_2); | |
4588 | break; | |
4589 | case 0x8c: /* SRDL R1,D2(B2) [RS] */ | |
4590 | case 0x8d: /* SLDL R1,D2(B2) [RS] */ | |
4591 | case 0x8e: /* SRDA R1,D2(B2) [RS] */ | |
4592 | insn = ld_code4(s->pc); | |
4593 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4594 | tmp = get_address(s, 0, b2, d2); /* shift */ | |
4595 | tmp2 = tcg_temp_new_i64(); | |
4596 | tmp32_1 = load_reg32(r1); | |
4597 | tmp32_2 = load_reg32(r1 + 1); | |
4598 | tcg_gen_concat_i32_i64(tmp2, tmp32_2, tmp32_1); /* operand */ | |
4599 | switch (opc) { | |
4600 | case 0x8c: | |
4601 | tcg_gen_shr_i64(tmp2, tmp2, tmp); | |
4602 | break; | |
4603 | case 0x8d: | |
4604 | tcg_gen_shl_i64(tmp2, tmp2, tmp); | |
4605 | break; | |
4606 | case 0x8e: | |
4607 | tcg_gen_sar_i64(tmp2, tmp2, tmp); | |
4608 | set_cc_s64(s, tmp2); | |
4609 | break; | |
4610 | } | |
4611 | tcg_gen_shri_i64(tmp, tmp2, 32); | |
4612 | tcg_gen_trunc_i64_i32(tmp32_1, tmp); | |
4613 | store_reg32(r1, tmp32_1); | |
4614 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
4615 | store_reg32(r1 + 1, tmp32_2); | |
225b6af7 SW |
4616 | tcg_temp_free_i64(tmp); |
4617 | tcg_temp_free_i64(tmp2); | |
e023e832 AG |
4618 | break; |
4619 | case 0x98: /* LM R1,R3,D2(B2) [RS] */ | |
4620 | case 0x90: /* STM R1,R3,D2(B2) [RS] */ | |
4621 | insn = ld_code4(s->pc); | |
4622 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4623 | ||
4624 | tmp = get_address(s, 0, b2, d2); | |
4625 | tmp2 = tcg_temp_new_i64(); | |
4626 | tmp3 = tcg_const_i64(4); | |
4627 | tmp4 = tcg_const_i64(0xffffffff00000000ULL); | |
4628 | for (i = r1;; i = (i + 1) % 16) { | |
4629 | if (opc == 0x98) { | |
4630 | tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); | |
4631 | tcg_gen_and_i64(regs[i], regs[i], tmp4); | |
4632 | tcg_gen_or_i64(regs[i], regs[i], tmp2); | |
4633 | } else { | |
4634 | tcg_gen_qemu_st32(regs[i], tmp, get_mem_index(s)); | |
4635 | } | |
4636 | if (i == r3) { | |
4637 | break; | |
4638 | } | |
4639 | tcg_gen_add_i64(tmp, tmp, tmp3); | |
4640 | } | |
bbf9f3b4 | 4641 | tcg_temp_free_i64(tmp); |
e023e832 AG |
4642 | tcg_temp_free_i64(tmp2); |
4643 | tcg_temp_free_i64(tmp3); | |
4644 | tcg_temp_free_i64(tmp4); | |
4645 | break; | |
4646 | case 0x91: /* TM D1(B1),I2 [SI] */ | |
4647 | insn = ld_code4(s->pc); | |
4648 | tmp = decode_si(s, insn, &i2, &b1, &d1); | |
4649 | tmp2 = tcg_const_i64(i2); | |
4650 | tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s)); | |
4651 | cmp_64(s, tmp, tmp2, CC_OP_TM_32); | |
4652 | tcg_temp_free_i64(tmp); | |
4653 | tcg_temp_free_i64(tmp2); | |
4654 | break; | |
4655 | case 0x92: /* MVI D1(B1),I2 [SI] */ | |
4656 | insn = ld_code4(s->pc); | |
4657 | tmp = decode_si(s, insn, &i2, &b1, &d1); | |
4658 | tmp2 = tcg_const_i64(i2); | |
4659 | tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s)); | |
4660 | tcg_temp_free_i64(tmp); | |
4661 | tcg_temp_free_i64(tmp2); | |
4662 | break; | |
4663 | case 0x94: /* NI D1(B1),I2 [SI] */ | |
4664 | case 0x96: /* OI D1(B1),I2 [SI] */ | |
4665 | case 0x97: /* XI D1(B1),I2 [SI] */ | |
4666 | insn = ld_code4(s->pc); | |
4667 | tmp = decode_si(s, insn, &i2, &b1, &d1); | |
4668 | tmp2 = tcg_temp_new_i64(); | |
4669 | tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s)); | |
4670 | switch (opc) { | |
4671 | case 0x94: | |
4672 | tcg_gen_andi_i64(tmp2, tmp2, i2); | |
4673 | break; | |
4674 | case 0x96: | |
4675 | tcg_gen_ori_i64(tmp2, tmp2, i2); | |
4676 | break; | |
4677 | case 0x97: | |
4678 | tcg_gen_xori_i64(tmp2, tmp2, i2); | |
4679 | break; | |
4680 | default: | |
4681 | tcg_abort(); | |
4682 | } | |
4683 | tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s)); | |
4684 | set_cc_nz_u64(s, tmp2); | |
4685 | tcg_temp_free_i64(tmp); | |
4686 | tcg_temp_free_i64(tmp2); | |
4687 | break; | |
4688 | case 0x95: /* CLI D1(B1),I2 [SI] */ | |
4689 | insn = ld_code4(s->pc); | |
4690 | tmp = decode_si(s, insn, &i2, &b1, &d1); | |
4691 | tmp2 = tcg_temp_new_i64(); | |
4692 | tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s)); | |
4693 | cmp_u64c(s, tmp2, i2); | |
4694 | tcg_temp_free_i64(tmp); | |
4695 | tcg_temp_free_i64(tmp2); | |
4696 | break; | |
4697 | case 0x9a: /* LAM R1,R3,D2(B2) [RS] */ | |
4698 | insn = ld_code4(s->pc); | |
4699 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4700 | tmp = get_address(s, 0, b2, d2); | |
4701 | tmp32_1 = tcg_const_i32(r1); | |
4702 | tmp32_2 = tcg_const_i32(r3); | |
4703 | potential_page_fault(s); | |
4704 | gen_helper_lam(tmp32_1, tmp, tmp32_2); | |
4705 | tcg_temp_free_i64(tmp); | |
4706 | tcg_temp_free_i32(tmp32_1); | |
4707 | tcg_temp_free_i32(tmp32_2); | |
4708 | break; | |
4709 | case 0x9b: /* STAM R1,R3,D2(B2) [RS] */ | |
4710 | insn = ld_code4(s->pc); | |
4711 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4712 | tmp = get_address(s, 0, b2, d2); | |
4713 | tmp32_1 = tcg_const_i32(r1); | |
4714 | tmp32_2 = tcg_const_i32(r3); | |
4715 | potential_page_fault(s); | |
4716 | gen_helper_stam(tmp32_1, tmp, tmp32_2); | |
4717 | tcg_temp_free_i64(tmp); | |
4718 | tcg_temp_free_i32(tmp32_1); | |
4719 | tcg_temp_free_i32(tmp32_2); | |
4720 | break; | |
4721 | case 0xa5: | |
4722 | insn = ld_code4(s->pc); | |
4723 | r1 = (insn >> 20) & 0xf; | |
4724 | op = (insn >> 16) & 0xf; | |
4725 | i2 = insn & 0xffff; | |
4726 | disas_a5(s, op, r1, i2); | |
4727 | break; | |
4728 | case 0xa7: | |
4729 | insn = ld_code4(s->pc); | |
4730 | r1 = (insn >> 20) & 0xf; | |
4731 | op = (insn >> 16) & 0xf; | |
4732 | i2 = (short)insn; | |
4733 | disas_a7(s, op, r1, i2); | |
4734 | break; | |
4735 | case 0xa8: /* MVCLE R1,R3,D2(B2) [RS] */ | |
4736 | insn = ld_code4(s->pc); | |
4737 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4738 | tmp = get_address(s, 0, b2, d2); | |
4739 | tmp32_1 = tcg_const_i32(r1); | |
4740 | tmp32_2 = tcg_const_i32(r3); | |
4741 | potential_page_fault(s); | |
4742 | gen_helper_mvcle(cc_op, tmp32_1, tmp, tmp32_2); | |
4743 | set_cc_static(s); | |
4744 | tcg_temp_free_i64(tmp); | |
4745 | tcg_temp_free_i32(tmp32_1); | |
4746 | tcg_temp_free_i32(tmp32_2); | |
4747 | break; | |
4748 | case 0xa9: /* CLCLE R1,R3,D2(B2) [RS] */ | |
4749 | insn = ld_code4(s->pc); | |
4750 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4751 | tmp = get_address(s, 0, b2, d2); | |
4752 | tmp32_1 = tcg_const_i32(r1); | |
4753 | tmp32_2 = tcg_const_i32(r3); | |
4754 | potential_page_fault(s); | |
4755 | gen_helper_clcle(cc_op, tmp32_1, tmp, tmp32_2); | |
4756 | set_cc_static(s); | |
4757 | tcg_temp_free_i64(tmp); | |
4758 | tcg_temp_free_i32(tmp32_1); | |
4759 | tcg_temp_free_i32(tmp32_2); | |
4760 | break; | |
4761 | #ifndef CONFIG_USER_ONLY | |
4762 | case 0xac: /* STNSM D1(B1),I2 [SI] */ | |
4763 | case 0xad: /* STOSM D1(B1),I2 [SI] */ | |
4764 | check_privileged(s, ilc); | |
4765 | insn = ld_code4(s->pc); | |
4766 | tmp = decode_si(s, insn, &i2, &b1, &d1); | |
4767 | tmp2 = tcg_temp_new_i64(); | |
4768 | tcg_gen_shri_i64(tmp2, psw_mask, 56); | |
4769 | tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s)); | |
4770 | if (opc == 0xac) { | |
4771 | tcg_gen_andi_i64(psw_mask, psw_mask, | |
4772 | ((uint64_t)i2 << 56) | 0x00ffffffffffffffULL); | |
4773 | } else { | |
4774 | tcg_gen_ori_i64(psw_mask, psw_mask, (uint64_t)i2 << 56); | |
4775 | } | |
4776 | tcg_temp_free_i64(tmp); | |
4777 | tcg_temp_free_i64(tmp2); | |
4778 | break; | |
4779 | case 0xae: /* SIGP R1,R3,D2(B2) [RS] */ | |
4780 | check_privileged(s, ilc); | |
4781 | insn = ld_code4(s->pc); | |
4782 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4783 | tmp = get_address(s, 0, b2, d2); | |
4784 | tmp2 = load_reg(r3); | |
4785 | tmp32_1 = tcg_const_i32(r1); | |
4786 | potential_page_fault(s); | |
4787 | gen_helper_sigp(cc_op, tmp, tmp32_1, tmp2); | |
4788 | set_cc_static(s); | |
4789 | tcg_temp_free_i64(tmp); | |
4790 | tcg_temp_free_i64(tmp2); | |
4791 | tcg_temp_free_i32(tmp32_1); | |
4792 | break; | |
4793 | case 0xb1: /* LRA R1,D2(X2, B2) [RX] */ | |
4794 | check_privileged(s, ilc); | |
4795 | insn = ld_code4(s->pc); | |
4796 | tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); | |
4797 | tmp32_1 = tcg_const_i32(r1); | |
4798 | potential_page_fault(s); | |
4799 | gen_helper_lra(cc_op, tmp, tmp32_1); | |
4800 | set_cc_static(s); | |
4801 | tcg_temp_free_i64(tmp); | |
4802 | tcg_temp_free_i32(tmp32_1); | |
4803 | break; | |
4804 | #endif | |
4805 | case 0xb2: | |
4806 | insn = ld_code4(s->pc); | |
4807 | op = (insn >> 16) & 0xff; | |
4808 | switch (op) { | |
4809 | case 0x9c: /* STFPC D2(B2) [S] */ | |
4810 | d2 = insn & 0xfff; | |
4811 | b2 = (insn >> 12) & 0xf; | |
4812 | tmp32_1 = tcg_temp_new_i32(); | |
4813 | tmp = tcg_temp_new_i64(); | |
4814 | tmp2 = get_address(s, 0, b2, d2); | |
4815 | tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc)); | |
4816 | tcg_gen_extu_i32_i64(tmp, tmp32_1); | |
4817 | tcg_gen_qemu_st32(tmp, tmp2, get_mem_index(s)); | |
4818 | tcg_temp_free_i32(tmp32_1); | |
4819 | tcg_temp_free_i64(tmp); | |
4820 | tcg_temp_free_i64(tmp2); | |
4821 | break; | |
4822 | default: | |
4823 | disas_b2(s, op, insn); | |
4824 | break; | |
4825 | } | |
4826 | break; | |
4827 | case 0xb3: | |
4828 | insn = ld_code4(s->pc); | |
4829 | op = (insn >> 16) & 0xff; | |
4830 | r3 = (insn >> 12) & 0xf; /* aka m3 */ | |
4831 | r1 = (insn >> 4) & 0xf; | |
4832 | r2 = insn & 0xf; | |
4833 | disas_b3(s, op, r3, r1, r2); | |
4834 | break; | |
4835 | #ifndef CONFIG_USER_ONLY | |
4836 | case 0xb6: /* STCTL R1,R3,D2(B2) [RS] */ | |
4837 | /* Store Control */ | |
4838 | check_privileged(s, ilc); | |
4839 | insn = ld_code4(s->pc); | |
4840 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4841 | tmp = get_address(s, 0, b2, d2); | |
4842 | tmp32_1 = tcg_const_i32(r1); | |
4843 | tmp32_2 = tcg_const_i32(r3); | |
4844 | potential_page_fault(s); | |
4845 | gen_helper_stctl(tmp32_1, tmp, tmp32_2); | |
4846 | tcg_temp_free_i64(tmp); | |
4847 | tcg_temp_free_i32(tmp32_1); | |
4848 | tcg_temp_free_i32(tmp32_2); | |
4849 | break; | |
4850 | case 0xb7: /* LCTL R1,R3,D2(B2) [RS] */ | |
4851 | /* Load Control */ | |
4852 | check_privileged(s, ilc); | |
4853 | insn = ld_code4(s->pc); | |
4854 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4855 | tmp = get_address(s, 0, b2, d2); | |
4856 | tmp32_1 = tcg_const_i32(r1); | |
4857 | tmp32_2 = tcg_const_i32(r3); | |
4858 | potential_page_fault(s); | |
4859 | gen_helper_lctl(tmp32_1, tmp, tmp32_2); | |
4860 | tcg_temp_free_i64(tmp); | |
4861 | tcg_temp_free_i32(tmp32_1); | |
4862 | tcg_temp_free_i32(tmp32_2); | |
4863 | break; | |
4864 | #endif | |
4865 | case 0xb9: | |
4866 | insn = ld_code4(s->pc); | |
4867 | r1 = (insn >> 4) & 0xf; | |
4868 | r2 = insn & 0xf; | |
4869 | op = (insn >> 16) & 0xff; | |
4870 | disas_b9(s, op, r1, r2); | |
4871 | break; | |
4872 | case 0xba: /* CS R1,R3,D2(B2) [RS] */ | |
4873 | insn = ld_code4(s->pc); | |
4874 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4875 | tmp = get_address(s, 0, b2, d2); | |
4876 | tmp32_1 = tcg_const_i32(r1); | |
4877 | tmp32_2 = tcg_const_i32(r3); | |
4878 | potential_page_fault(s); | |
4879 | gen_helper_cs(cc_op, tmp32_1, tmp, tmp32_2); | |
4880 | set_cc_static(s); | |
4881 | tcg_temp_free_i64(tmp); | |
4882 | tcg_temp_free_i32(tmp32_1); | |
4883 | tcg_temp_free_i32(tmp32_2); | |
4884 | break; | |
4885 | case 0xbd: /* CLM R1,M3,D2(B2) [RS] */ | |
4886 | insn = ld_code4(s->pc); | |
4887 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4888 | tmp = get_address(s, 0, b2, d2); | |
4889 | tmp32_1 = load_reg32(r1); | |
4890 | tmp32_2 = tcg_const_i32(r3); | |
4891 | potential_page_fault(s); | |
4892 | gen_helper_clm(cc_op, tmp32_1, tmp32_2, tmp); | |
4893 | set_cc_static(s); | |
4894 | tcg_temp_free_i64(tmp); | |
4895 | tcg_temp_free_i32(tmp32_1); | |
4896 | tcg_temp_free_i32(tmp32_2); | |
4897 | break; | |
4898 | case 0xbe: /* STCM R1,M3,D2(B2) [RS] */ | |
4899 | insn = ld_code4(s->pc); | |
4900 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4901 | tmp = get_address(s, 0, b2, d2); | |
4902 | tmp32_1 = load_reg32(r1); | |
4903 | tmp32_2 = tcg_const_i32(r3); | |
4904 | potential_page_fault(s); | |
4905 | gen_helper_stcm(tmp32_1, tmp32_2, tmp); | |
4906 | tcg_temp_free_i64(tmp); | |
4907 | tcg_temp_free_i32(tmp32_1); | |
4908 | tcg_temp_free_i32(tmp32_2); | |
4909 | break; | |
4910 | case 0xbf: /* ICM R1,M3,D2(B2) [RS] */ | |
4911 | insn = ld_code4(s->pc); | |
4912 | decode_rs(s, insn, &r1, &r3, &b2, &d2); | |
4913 | if (r3 == 15) { | |
4914 | /* effectively a 32-bit load */ | |
4915 | tmp = get_address(s, 0, b2, d2); | |
4916 | tmp32_1 = tcg_temp_new_i32(); | |
4917 | tmp32_2 = tcg_const_i32(r3); | |
4918 | tcg_gen_qemu_ld32u(tmp, tmp, get_mem_index(s)); | |
4919 | store_reg32_i64(r1, tmp); | |
4920 | tcg_gen_trunc_i64_i32(tmp32_1, tmp); | |
4921 | set_cc_icm(s, tmp32_2, tmp32_1); | |
4922 | tcg_temp_free_i64(tmp); | |
4923 | tcg_temp_free_i32(tmp32_1); | |
4924 | tcg_temp_free_i32(tmp32_2); | |
4925 | } else if (r3) { | |
4926 | uint32_t mask = 0x00ffffffUL; | |
4927 | uint32_t shift = 24; | |
4928 | int m3 = r3; | |
4929 | tmp = get_address(s, 0, b2, d2); | |
4930 | tmp2 = tcg_temp_new_i64(); | |
4931 | tmp32_1 = load_reg32(r1); | |
4932 | tmp32_2 = tcg_temp_new_i32(); | |
4933 | tmp32_3 = tcg_const_i32(r3); | |
4934 | tmp32_4 = tcg_const_i32(0); | |
4935 | while (m3) { | |
4936 | if (m3 & 8) { | |
4937 | tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s)); | |
4938 | tcg_gen_trunc_i64_i32(tmp32_2, tmp2); | |
4939 | if (shift) { | |
4940 | tcg_gen_shli_i32(tmp32_2, tmp32_2, shift); | |
4941 | } | |
4942 | tcg_gen_andi_i32(tmp32_1, tmp32_1, mask); | |
4943 | tcg_gen_or_i32(tmp32_1, tmp32_1, tmp32_2); | |
4944 | tcg_gen_or_i32(tmp32_4, tmp32_4, tmp32_2); | |
4945 | tcg_gen_addi_i64(tmp, tmp, 1); | |
4946 | } | |
4947 | m3 = (m3 << 1) & 0xf; | |
4948 | mask = (mask >> 8) | 0xff000000UL; | |
4949 | shift -= 8; | |
4950 | } | |
4951 | store_reg32(r1, tmp32_1); | |
4952 | set_cc_icm(s, tmp32_3, tmp32_4); | |
4953 | tcg_temp_free_i64(tmp); | |
4954 | tcg_temp_free_i64(tmp2); | |
4955 | tcg_temp_free_i32(tmp32_1); | |
4956 | tcg_temp_free_i32(tmp32_2); | |
4957 | tcg_temp_free_i32(tmp32_3); | |
4958 | tcg_temp_free_i32(tmp32_4); | |
4959 | } else { | |
4960 | /* i.e. env->cc = 0 */ | |
4961 | gen_op_movi_cc(s, 0); | |
4962 | } | |
4963 | break; | |
4964 | case 0xc0: | |
4965 | case 0xc2: | |
4966 | insn = ld_code6(s->pc); | |
4967 | r1 = (insn >> 36) & 0xf; | |
4968 | op = (insn >> 32) & 0xf; | |
4969 | i2 = (int)insn; | |
4970 | switch (opc) { | |
4971 | case 0xc0: | |
4972 | disas_c0(s, op, r1, i2); | |
4973 | break; | |
4974 | case 0xc2: | |
4975 | disas_c2(s, op, r1, i2); | |
4976 | break; | |
4977 | default: | |
4978 | tcg_abort(); | |
4979 | } | |
4980 | break; | |
4981 | case 0xd2: /* MVC D1(L,B1),D2(B2) [SS] */ | |
4982 | case 0xd4: /* NC D1(L,B1),D2(B2) [SS] */ | |
4983 | case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */ | |
4984 | case 0xd6: /* OC D1(L,B1),D2(B2) [SS] */ | |
4985 | case 0xd7: /* XC D1(L,B1),D2(B2) [SS] */ | |
4986 | case 0xdc: /* TR D1(L,B1),D2(B2) [SS] */ | |
4987 | case 0xf3: /* UNPK D1(L1,B1),D2(L2,B2) [SS] */ | |
4988 | insn = ld_code6(s->pc); | |
4989 | vl = tcg_const_i32((insn >> 32) & 0xff); | |
4990 | b1 = (insn >> 28) & 0xf; | |
4991 | b2 = (insn >> 12) & 0xf; | |
4992 | d1 = (insn >> 16) & 0xfff; | |
4993 | d2 = insn & 0xfff; | |
4994 | tmp = get_address(s, 0, b1, d1); | |
4995 | tmp2 = get_address(s, 0, b2, d2); | |
4996 | switch (opc) { | |
4997 | case 0xd2: | |
4998 | gen_op_mvc(s, (insn >> 32) & 0xff, tmp, tmp2); | |
4999 | break; | |
5000 | case 0xd4: | |
5001 | potential_page_fault(s); | |
5002 | gen_helper_nc(cc_op, vl, tmp, tmp2); | |
5003 | set_cc_static(s); | |
5004 | break; | |
5005 | case 0xd5: | |
5006 | gen_op_clc(s, (insn >> 32) & 0xff, tmp, tmp2); | |
5007 | break; | |
5008 | case 0xd6: | |
5009 | potential_page_fault(s); | |
5010 | gen_helper_oc(cc_op, vl, tmp, tmp2); | |
5011 | set_cc_static(s); | |
5012 | break; | |
5013 | case 0xd7: | |
5014 | potential_page_fault(s); | |
5015 | gen_helper_xc(cc_op, vl, tmp, tmp2); | |
5016 | set_cc_static(s); | |
5017 | break; | |
5018 | case 0xdc: | |
5019 | potential_page_fault(s); | |
5020 | gen_helper_tr(vl, tmp, tmp2); | |
5021 | set_cc_static(s); | |
5022 | break; | |
5023 | case 0xf3: | |
5024 | potential_page_fault(s); | |
5025 | gen_helper_unpk(vl, tmp, tmp2); | |
5026 | break; | |
5027 | default: | |
5028 | tcg_abort(); | |
5029 | } | |
5030 | tcg_temp_free_i64(tmp); | |
5031 | tcg_temp_free_i64(tmp2); | |
5032 | break; | |
5033 | #ifndef CONFIG_USER_ONLY | |
5034 | case 0xda: /* MVCP D1(R1,B1),D2(B2),R3 [SS] */ | |
5035 | case 0xdb: /* MVCS D1(R1,B1),D2(B2),R3 [SS] */ | |
5036 | check_privileged(s, ilc); | |
5037 | potential_page_fault(s); | |
5038 | insn = ld_code6(s->pc); | |
5039 | r1 = (insn >> 36) & 0xf; | |
5040 | r3 = (insn >> 32) & 0xf; | |
5041 | b1 = (insn >> 28) & 0xf; | |
5042 | d1 = (insn >> 16) & 0xfff; | |
5043 | b2 = (insn >> 12) & 0xf; | |
5044 | d2 = insn & 0xfff; | |
5045 | tmp = load_reg(r1); | |
5046 | /* XXX key in r3 */ | |
5047 | tmp2 = get_address(s, 0, b1, d1); | |
5048 | tmp3 = get_address(s, 0, b2, d2); | |
5049 | if (opc == 0xda) { | |
5050 | gen_helper_mvcp(cc_op, tmp, tmp2, tmp3); | |
5051 | } else { | |
5052 | gen_helper_mvcs(cc_op, tmp, tmp2, tmp3); | |
5053 | } | |
5054 | set_cc_static(s); | |
5055 | tcg_temp_free_i64(tmp); | |
5056 | tcg_temp_free_i64(tmp2); | |
5057 | tcg_temp_free_i64(tmp3); | |
5058 | break; | |
5059 | #endif | |
5060 | case 0xe3: | |
5061 | insn = ld_code6(s->pc); | |
5062 | debug_insn(insn); | |
5063 | op = insn & 0xff; | |
5064 | r1 = (insn >> 36) & 0xf; | |
5065 | x2 = (insn >> 32) & 0xf; | |
5066 | b2 = (insn >> 28) & 0xf; | |
5067 | d2 = ((int)((((insn >> 16) & 0xfff) | |
5068 | | ((insn << 4) & 0xff000)) << 12)) >> 12; | |
5069 | disas_e3(s, op, r1, x2, b2, d2 ); | |
5070 | break; | |
5071 | #ifndef CONFIG_USER_ONLY | |
5072 | case 0xe5: | |
5073 | /* Test Protection */ | |
5074 | check_privileged(s, ilc); | |
5075 | insn = ld_code6(s->pc); | |
5076 | debug_insn(insn); | |
5077 | disas_e5(s, insn); | |
5078 | break; | |
5079 | #endif | |
5080 | case 0xeb: | |
5081 | insn = ld_code6(s->pc); | |
5082 | debug_insn(insn); | |
5083 | op = insn & 0xff; | |
5084 | r1 = (insn >> 36) & 0xf; | |
5085 | r3 = (insn >> 32) & 0xf; | |
5086 | b2 = (insn >> 28) & 0xf; | |
5087 | d2 = ((int)((((insn >> 16) & 0xfff) | |
5088 | | ((insn << 4) & 0xff000)) << 12)) >> 12; | |
5089 | disas_eb(s, op, r1, r3, b2, d2); | |
5090 | break; | |
5091 | case 0xed: | |
5092 | insn = ld_code6(s->pc); | |
5093 | debug_insn(insn); | |
5094 | op = insn & 0xff; | |
5095 | r1 = (insn >> 36) & 0xf; | |
5096 | x2 = (insn >> 32) & 0xf; | |
5097 | b2 = (insn >> 28) & 0xf; | |
5098 | d2 = (short)((insn >> 16) & 0xfff); | |
5099 | r1b = (insn >> 12) & 0xf; | |
5100 | disas_ed(s, op, r1, x2, b2, d2, r1b); | |
5101 | break; | |
5102 | default: | |
5103 | LOG_DISAS("unimplemented opcode 0x%x\n", opc); | |
5104 | gen_illegal_opcode(s, ilc); | |
5105 | break; | |
5106 | } | |
5107 | ||
5108 | /* Instruction length is encoded in the opcode */ | |
5109 | s->pc += (ilc * 2); | |
5110 | } | |
5111 | ||
5112 | static inline void gen_intermediate_code_internal(CPUState *env, | |
5113 | TranslationBlock *tb, | |
5114 | int search_pc) | |
5115 | { | |
5116 | DisasContext dc; | |
5117 | target_ulong pc_start; | |
5118 | uint64_t next_page_start; | |
5119 | uint16_t *gen_opc_end; | |
5120 | int j, lj = -1; | |
5121 | int num_insns, max_insns; | |
5122 | CPUBreakpoint *bp; | |
5123 | ||
5124 | pc_start = tb->pc; | |
5125 | ||
5126 | /* 31-bit mode */ | |
5127 | if (!(tb->flags & FLAG_MASK_64)) { | |
5128 | pc_start &= 0x7fffffff; | |
5129 | } | |
5130 | ||
5131 | dc.pc = pc_start; | |
5132 | dc.is_jmp = DISAS_NEXT; | |
5133 | dc.tb = tb; | |
5134 | dc.cc_op = CC_OP_DYNAMIC; | |
5135 | ||
5136 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; | |
5137 | ||
5138 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
5139 | ||
5140 | num_insns = 0; | |
5141 | max_insns = tb->cflags & CF_COUNT_MASK; | |
5142 | if (max_insns == 0) { | |
5143 | max_insns = CF_COUNT_MASK; | |
5144 | } | |
5145 | ||
5146 | gen_icount_start(); | |
5147 | ||
5148 | do { | |
5149 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { | |
5150 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
5151 | if (bp->pc == dc.pc) { | |
5152 | gen_debug(&dc); | |
5153 | break; | |
5154 | } | |
5155 | } | |
5156 | } | |
5157 | if (search_pc) { | |
5158 | j = gen_opc_ptr - gen_opc_buf; | |
5159 | if (lj < j) { | |
5160 | lj++; | |
5161 | while (lj < j) { | |
5162 | gen_opc_instr_start[lj++] = 0; | |
5163 | } | |
5164 | } | |
5165 | gen_opc_pc[lj] = dc.pc; | |
5166 | gen_opc_cc_op[lj] = dc.cc_op; | |
5167 | gen_opc_instr_start[lj] = 1; | |
5168 | gen_opc_icount[lj] = num_insns; | |
5169 | } | |
5170 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { | |
5171 | gen_io_start(); | |
5172 | } | |
5173 | #if defined(S390X_DEBUG_DISAS_VERBOSE) | |
5174 | LOG_DISAS("pc " TARGET_FMT_lx "\n", | |
5175 | dc.pc); | |
5176 | #endif | |
5177 | disas_s390_insn(&dc); | |
5178 | ||
5179 | num_insns++; | |
5180 | if (env->singlestep_enabled) { | |
5181 | gen_debug(&dc); | |
5182 | } | |
5183 | } while (!dc.is_jmp && gen_opc_ptr < gen_opc_end && dc.pc < next_page_start | |
5184 | && num_insns < max_insns && !env->singlestep_enabled | |
5185 | && !singlestep); | |
5186 | ||
5187 | if (!dc.is_jmp) { | |
5188 | update_psw_addr(&dc); | |
5189 | } | |
5190 | ||
5191 | if (singlestep && dc.cc_op != CC_OP_DYNAMIC) { | |
5192 | gen_op_calc_cc(&dc); | |
5193 | } else { | |
5194 | /* next TB starts off with CC_OP_DYNAMIC, so make sure the cc op type | |
5195 | is in env */ | |
5196 | gen_op_set_cc_op(&dc); | |
5197 | } | |
5198 | ||
5199 | if (tb->cflags & CF_LAST_IO) { | |
5200 | gen_io_end(); | |
5201 | } | |
5202 | /* Generate the return instruction */ | |
5203 | if (dc.is_jmp != DISAS_TB_JUMP) { | |
5204 | tcg_gen_exit_tb(0); | |
5205 | } | |
5206 | gen_icount_end(tb, num_insns); | |
5207 | *gen_opc_ptr = INDEX_op_end; | |
5208 | if (search_pc) { | |
5209 | j = gen_opc_ptr - gen_opc_buf; | |
5210 | lj++; | |
5211 | while (lj <= j) { | |
5212 | gen_opc_instr_start[lj++] = 0; | |
5213 | } | |
5214 | } else { | |
5215 | tb->size = dc.pc - pc_start; | |
5216 | tb->icount = num_insns; | |
5217 | } | |
5218 | #if defined(S390X_DEBUG_DISAS) | |
5219 | log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0); | |
5220 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
5221 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
5222 | log_target_disas(pc_start, dc.pc - pc_start, 1); | |
5223 | qemu_log("\n"); | |
5224 | } | |
5225 | #endif | |
5226 | } | |
5227 | ||
5228 | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) | |
5229 | { | |
5230 | gen_intermediate_code_internal(env, tb, 0); | |
5231 | } | |
5232 | ||
5233 | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) | |
5234 | { | |
5235 | gen_intermediate_code_internal(env, tb, 1); | |
5236 | } | |
5237 | ||
5238 | void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) | |
5239 | { | |
5240 | int cc_op; | |
5241 | env->psw.addr = gen_opc_pc[pc_pos]; | |
5242 | cc_op = gen_opc_cc_op[pc_pos]; | |
5243 | if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) { | |
5244 | env->cc_op = cc_op; | |
5245 | } | |
10ec5117 | 5246 | } |