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10ec5117 AG |
1 | /* |
2 | * S/390 translation | |
3 | * | |
4 | * Copyright (c) 2009 Ulrich Hecht | |
e023e832 | 5 | * Copyright (c) 2010 Alexander Graf |
10ec5117 AG |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
70539e18 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
10ec5117 | 19 | */ |
e023e832 | 20 | |
e023e832 AG |
21 | /* #define DEBUG_INLINE_BRANCHES */ |
22 | #define S390X_DEBUG_DISAS | |
23 | /* #define S390X_DEBUG_DISAS_VERBOSE */ | |
24 | ||
25 | #ifdef S390X_DEBUG_DISAS_VERBOSE | |
26 | # define LOG_DISAS(...) qemu_log(__VA_ARGS__) | |
27 | #else | |
28 | # define LOG_DISAS(...) do { } while (0) | |
29 | #endif | |
10ec5117 AG |
30 | |
31 | #include "cpu.h" | |
76cad711 | 32 | #include "disas/disas.h" |
10ec5117 | 33 | #include "tcg-op.h" |
1de7afc9 | 34 | #include "qemu/log.h" |
58a9e35b | 35 | #include "qemu/host-utils.h" |
10ec5117 | 36 | |
e023e832 AG |
37 | /* global register indexes */ |
38 | static TCGv_ptr cpu_env; | |
39 | ||
022c62cb | 40 | #include "exec/gen-icount.h" |
3208afbe | 41 | #include "helper.h" |
e023e832 | 42 | #define GEN_HELPER 1 |
3208afbe | 43 | #include "helper.h" |
e023e832 | 44 | |
ad044d09 RH |
45 | |
46 | /* Information that (most) every instruction needs to manipulate. */ | |
e023e832 | 47 | typedef struct DisasContext DisasContext; |
ad044d09 RH |
48 | typedef struct DisasInsn DisasInsn; |
49 | typedef struct DisasFields DisasFields; | |
50 | ||
e023e832 | 51 | struct DisasContext { |
e023e832 | 52 | struct TranslationBlock *tb; |
ad044d09 RH |
53 | const DisasInsn *insn; |
54 | DisasFields *fields; | |
55 | uint64_t pc, next_pc; | |
56 | enum cc_op cc_op; | |
57 | bool singlestep_enabled; | |
e023e832 AG |
58 | }; |
59 | ||
3fde06f5 RH |
60 | /* Information carried about a condition to be evaluated. */ |
61 | typedef struct { | |
62 | TCGCond cond:8; | |
63 | bool is_64; | |
64 | bool g1; | |
65 | bool g2; | |
66 | union { | |
67 | struct { TCGv_i64 a, b; } s64; | |
68 | struct { TCGv_i32 a, b; } s32; | |
69 | } u; | |
70 | } DisasCompare; | |
71 | ||
e023e832 AG |
72 | #define DISAS_EXCP 4 |
73 | ||
e023e832 AG |
74 | #ifdef DEBUG_INLINE_BRANCHES |
75 | static uint64_t inline_branch_hit[CC_OP_MAX]; | |
76 | static uint64_t inline_branch_miss[CC_OP_MAX]; | |
77 | #endif | |
78 | ||
4f3adfb2 | 79 | static uint64_t pc_to_link_info(DisasContext *s, uint64_t pc) |
e023e832 AG |
80 | { |
81 | if (!(s->tb->flags & FLAG_MASK_64)) { | |
82 | if (s->tb->flags & FLAG_MASK_32) { | |
83 | return pc | 0x80000000; | |
84 | } | |
85 | } | |
86 | return pc; | |
87 | } | |
88 | ||
a4e3ad19 | 89 | void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf, |
10ec5117 AG |
90 | int flags) |
91 | { | |
92 | int i; | |
e023e832 | 93 | |
d885bdd4 RH |
94 | if (env->cc_op > 3) { |
95 | cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n", | |
96 | env->psw.mask, env->psw.addr, cc_name(env->cc_op)); | |
97 | } else { | |
98 | cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n", | |
99 | env->psw.mask, env->psw.addr, env->cc_op); | |
100 | } | |
101 | ||
10ec5117 | 102 | for (i = 0; i < 16; i++) { |
e023e832 | 103 | cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]); |
10ec5117 AG |
104 | if ((i % 4) == 3) { |
105 | cpu_fprintf(f, "\n"); | |
106 | } else { | |
107 | cpu_fprintf(f, " "); | |
108 | } | |
109 | } | |
e023e832 | 110 | |
10ec5117 | 111 | for (i = 0; i < 16; i++) { |
431253c2 | 112 | cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll); |
10ec5117 AG |
113 | if ((i % 4) == 3) { |
114 | cpu_fprintf(f, "\n"); | |
115 | } else { | |
116 | cpu_fprintf(f, " "); | |
117 | } | |
118 | } | |
e023e832 | 119 | |
e023e832 AG |
120 | #ifndef CONFIG_USER_ONLY |
121 | for (i = 0; i < 16; i++) { | |
122 | cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]); | |
123 | if ((i % 4) == 3) { | |
124 | cpu_fprintf(f, "\n"); | |
125 | } else { | |
126 | cpu_fprintf(f, " "); | |
127 | } | |
128 | } | |
129 | #endif | |
130 | ||
e023e832 AG |
131 | #ifdef DEBUG_INLINE_BRANCHES |
132 | for (i = 0; i < CC_OP_MAX; i++) { | |
133 | cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i), | |
134 | inline_branch_miss[i], inline_branch_hit[i]); | |
135 | } | |
136 | #endif | |
d885bdd4 RH |
137 | |
138 | cpu_fprintf(f, "\n"); | |
10ec5117 AG |
139 | } |
140 | ||
e023e832 AG |
141 | static TCGv_i64 psw_addr; |
142 | static TCGv_i64 psw_mask; | |
143 | ||
144 | static TCGv_i32 cc_op; | |
145 | static TCGv_i64 cc_src; | |
146 | static TCGv_i64 cc_dst; | |
147 | static TCGv_i64 cc_vr; | |
148 | ||
431253c2 | 149 | static char cpu_reg_names[32][4]; |
e023e832 | 150 | static TCGv_i64 regs[16]; |
431253c2 | 151 | static TCGv_i64 fregs[16]; |
e023e832 AG |
152 | |
153 | static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; | |
154 | ||
d5a43964 AG |
155 | void s390x_translate_init(void) |
156 | { | |
e023e832 | 157 | int i; |
e023e832 AG |
158 | |
159 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
431253c2 RH |
160 | psw_addr = tcg_global_mem_new_i64(TCG_AREG0, |
161 | offsetof(CPUS390XState, psw.addr), | |
e023e832 | 162 | "psw_addr"); |
431253c2 RH |
163 | psw_mask = tcg_global_mem_new_i64(TCG_AREG0, |
164 | offsetof(CPUS390XState, psw.mask), | |
e023e832 AG |
165 | "psw_mask"); |
166 | ||
a4e3ad19 | 167 | cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op), |
e023e832 | 168 | "cc_op"); |
a4e3ad19 | 169 | cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src), |
e023e832 | 170 | "cc_src"); |
a4e3ad19 | 171 | cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst), |
e023e832 | 172 | "cc_dst"); |
a4e3ad19 | 173 | cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr), |
e023e832 AG |
174 | "cc_vr"); |
175 | ||
e023e832 | 176 | for (i = 0; i < 16; i++) { |
431253c2 | 177 | snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i); |
e023e832 | 178 | regs[i] = tcg_global_mem_new(TCG_AREG0, |
431253c2 RH |
179 | offsetof(CPUS390XState, regs[i]), |
180 | cpu_reg_names[i]); | |
181 | } | |
182 | ||
183 | for (i = 0; i < 16; i++) { | |
184 | snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i); | |
185 | fregs[i] = tcg_global_mem_new(TCG_AREG0, | |
186 | offsetof(CPUS390XState, fregs[i].d), | |
187 | cpu_reg_names[i + 16]); | |
e023e832 | 188 | } |
7e68da2a RH |
189 | |
190 | /* register helpers */ | |
191 | #define GEN_HELPER 2 | |
192 | #include "helper.h" | |
d5a43964 AG |
193 | } |
194 | ||
4f3adfb2 | 195 | static TCGv_i64 load_reg(int reg) |
10ec5117 | 196 | { |
e023e832 AG |
197 | TCGv_i64 r = tcg_temp_new_i64(); |
198 | tcg_gen_mov_i64(r, regs[reg]); | |
199 | return r; | |
10ec5117 AG |
200 | } |
201 | ||
4f3adfb2 | 202 | static TCGv_i64 load_freg32_i64(int reg) |
d764a8d1 RH |
203 | { |
204 | TCGv_i64 r = tcg_temp_new_i64(); | |
205 | tcg_gen_shri_i64(r, fregs[reg], 32); | |
206 | return r; | |
207 | } | |
208 | ||
4f3adfb2 | 209 | static void store_reg(int reg, TCGv_i64 v) |
e023e832 AG |
210 | { |
211 | tcg_gen_mov_i64(regs[reg], v); | |
212 | } | |
213 | ||
4f3adfb2 | 214 | static void store_freg(int reg, TCGv_i64 v) |
e023e832 | 215 | { |
431253c2 | 216 | tcg_gen_mov_i64(fregs[reg], v); |
e023e832 AG |
217 | } |
218 | ||
4f3adfb2 | 219 | static void store_reg32_i64(int reg, TCGv_i64 v) |
e023e832 AG |
220 | { |
221 | /* 32 bit register writes keep the upper half */ | |
e023e832 | 222 | tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32); |
e023e832 AG |
223 | } |
224 | ||
4f3adfb2 | 225 | static void store_reg32h_i64(int reg, TCGv_i64 v) |
77f8d6c3 RH |
226 | { |
227 | tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32); | |
228 | } | |
229 | ||
4f3adfb2 | 230 | static void store_freg32_i64(int reg, TCGv_i64 v) |
d764a8d1 RH |
231 | { |
232 | tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32); | |
233 | } | |
234 | ||
4f3adfb2 | 235 | static void return_low128(TCGv_i64 dest) |
1ac5889f RH |
236 | { |
237 | tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); | |
238 | } | |
239 | ||
4f3adfb2 | 240 | static void update_psw_addr(DisasContext *s) |
e023e832 AG |
241 | { |
242 | /* psw.addr */ | |
243 | tcg_gen_movi_i64(psw_addr, s->pc); | |
244 | } | |
245 | ||
7a6c7067 RH |
246 | static void update_cc_op(DisasContext *s) |
247 | { | |
248 | if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) { | |
249 | tcg_gen_movi_i32(cc_op, s->cc_op); | |
250 | } | |
251 | } | |
252 | ||
4f3adfb2 | 253 | static void potential_page_fault(DisasContext *s) |
e023e832 | 254 | { |
e023e832 | 255 | update_psw_addr(s); |
7a6c7067 | 256 | update_cc_op(s); |
e023e832 AG |
257 | } |
258 | ||
46ee3d84 | 259 | static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc) |
e023e832 | 260 | { |
46ee3d84 | 261 | return (uint64_t)cpu_lduw_code(env, pc); |
e023e832 AG |
262 | } |
263 | ||
46ee3d84 | 264 | static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc) |
e023e832 | 265 | { |
ad044d09 | 266 | return (uint64_t)(uint32_t)cpu_ldl_code(env, pc); |
e023e832 AG |
267 | } |
268 | ||
46ee3d84 | 269 | static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc) |
e023e832 | 270 | { |
ad044d09 | 271 | return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2); |
e023e832 AG |
272 | } |
273 | ||
4f3adfb2 | 274 | static int get_mem_index(DisasContext *s) |
e023e832 AG |
275 | { |
276 | switch (s->tb->flags & FLAG_MASK_ASC) { | |
277 | case PSW_ASC_PRIMARY >> 32: | |
278 | return 0; | |
279 | case PSW_ASC_SECONDARY >> 32: | |
280 | return 1; | |
281 | case PSW_ASC_HOME >> 32: | |
282 | return 2; | |
283 | default: | |
284 | tcg_abort(); | |
285 | break; | |
286 | } | |
287 | } | |
288 | ||
d5a103cd | 289 | static void gen_exception(int excp) |
e023e832 | 290 | { |
d5a103cd | 291 | TCGv_i32 tmp = tcg_const_i32(excp); |
089f5c06 | 292 | gen_helper_exception(cpu_env, tmp); |
e023e832 | 293 | tcg_temp_free_i32(tmp); |
e023e832 AG |
294 | } |
295 | ||
d5a103cd | 296 | static void gen_program_exception(DisasContext *s, int code) |
e023e832 AG |
297 | { |
298 | TCGv_i32 tmp; | |
299 | ||
d5a103cd | 300 | /* Remember what pgm exeption this was. */ |
e023e832 | 301 | tmp = tcg_const_i32(code); |
a4e3ad19 | 302 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code)); |
e023e832 AG |
303 | tcg_temp_free_i32(tmp); |
304 | ||
d5a103cd RH |
305 | tmp = tcg_const_i32(s->next_pc - s->pc); |
306 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen)); | |
e023e832 AG |
307 | tcg_temp_free_i32(tmp); |
308 | ||
d5a103cd RH |
309 | /* Advance past instruction. */ |
310 | s->pc = s->next_pc; | |
e023e832 AG |
311 | update_psw_addr(s); |
312 | ||
d5a103cd | 313 | /* Save off cc. */ |
7a6c7067 | 314 | update_cc_op(s); |
e023e832 | 315 | |
d5a103cd RH |
316 | /* Trigger exception. */ |
317 | gen_exception(EXCP_PGM); | |
e023e832 AG |
318 | } |
319 | ||
d5a103cd | 320 | static inline void gen_illegal_opcode(DisasContext *s) |
e023e832 | 321 | { |
d5a103cd | 322 | gen_program_exception(s, PGM_SPECIFICATION); |
e023e832 AG |
323 | } |
324 | ||
d5a103cd | 325 | static inline void check_privileged(DisasContext *s) |
e023e832 AG |
326 | { |
327 | if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) { | |
d5a103cd | 328 | gen_program_exception(s, PGM_PRIVILEGED); |
e023e832 AG |
329 | } |
330 | } | |
331 | ||
e023e832 AG |
332 | static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2) |
333 | { | |
334 | TCGv_i64 tmp; | |
335 | ||
336 | /* 31-bitify the immediate part; register contents are dealt with below */ | |
337 | if (!(s->tb->flags & FLAG_MASK_64)) { | |
338 | d2 &= 0x7fffffffUL; | |
339 | } | |
340 | ||
341 | if (x2) { | |
342 | if (d2) { | |
343 | tmp = tcg_const_i64(d2); | |
344 | tcg_gen_add_i64(tmp, tmp, regs[x2]); | |
345 | } else { | |
346 | tmp = load_reg(x2); | |
347 | } | |
348 | if (b2) { | |
349 | tcg_gen_add_i64(tmp, tmp, regs[b2]); | |
350 | } | |
351 | } else if (b2) { | |
352 | if (d2) { | |
353 | tmp = tcg_const_i64(d2); | |
354 | tcg_gen_add_i64(tmp, tmp, regs[b2]); | |
355 | } else { | |
356 | tmp = load_reg(b2); | |
357 | } | |
358 | } else { | |
359 | tmp = tcg_const_i64(d2); | |
360 | } | |
361 | ||
362 | /* 31-bit mode mask if there are values loaded from registers */ | |
363 | if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) { | |
364 | tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL); | |
365 | } | |
366 | ||
367 | return tmp; | |
368 | } | |
369 | ||
aa31bf60 | 370 | static inline void gen_op_movi_cc(DisasContext *s, uint32_t val) |
e023e832 AG |
371 | { |
372 | s->cc_op = CC_OP_CONST0 + val; | |
373 | } | |
374 | ||
375 | static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst) | |
376 | { | |
377 | tcg_gen_discard_i64(cc_src); | |
378 | tcg_gen_mov_i64(cc_dst, dst); | |
379 | tcg_gen_discard_i64(cc_vr); | |
380 | s->cc_op = op; | |
381 | } | |
382 | ||
e023e832 AG |
383 | static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src, |
384 | TCGv_i64 dst) | |
385 | { | |
386 | tcg_gen_mov_i64(cc_src, src); | |
387 | tcg_gen_mov_i64(cc_dst, dst); | |
388 | tcg_gen_discard_i64(cc_vr); | |
389 | s->cc_op = op; | |
390 | } | |
391 | ||
e023e832 AG |
392 | static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src, |
393 | TCGv_i64 dst, TCGv_i64 vr) | |
394 | { | |
395 | tcg_gen_mov_i64(cc_src, src); | |
396 | tcg_gen_mov_i64(cc_dst, dst); | |
397 | tcg_gen_mov_i64(cc_vr, vr); | |
398 | s->cc_op = op; | |
399 | } | |
400 | ||
4f3adfb2 | 401 | static void set_cc_nz_u64(DisasContext *s, TCGv_i64 val) |
e023e832 AG |
402 | { |
403 | gen_op_update1_cc_i64(s, CC_OP_NZ, val); | |
404 | } | |
405 | ||
4f3adfb2 | 406 | static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val) |
68c8bd93 RH |
407 | { |
408 | gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val); | |
409 | } | |
410 | ||
4f3adfb2 | 411 | static void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val) |
68c8bd93 RH |
412 | { |
413 | gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val); | |
414 | } | |
415 | ||
4f3adfb2 | 416 | static void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl) |
68c8bd93 RH |
417 | { |
418 | gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl); | |
419 | } | |
420 | ||
e023e832 | 421 | /* CC value is in env->cc_op */ |
4f3adfb2 | 422 | static void set_cc_static(DisasContext *s) |
e023e832 AG |
423 | { |
424 | tcg_gen_discard_i64(cc_src); | |
425 | tcg_gen_discard_i64(cc_dst); | |
426 | tcg_gen_discard_i64(cc_vr); | |
427 | s->cc_op = CC_OP_STATIC; | |
428 | } | |
429 | ||
e023e832 AG |
430 | /* calculates cc into cc_op */ |
431 | static void gen_op_calc_cc(DisasContext *s) | |
432 | { | |
7a6c7067 RH |
433 | TCGv_i32 local_cc_op; |
434 | TCGv_i64 dummy; | |
435 | ||
436 | TCGV_UNUSED_I32(local_cc_op); | |
437 | TCGV_UNUSED_I64(dummy); | |
438 | switch (s->cc_op) { | |
439 | default: | |
440 | dummy = tcg_const_i64(0); | |
441 | /* FALLTHRU */ | |
442 | case CC_OP_ADD_64: | |
443 | case CC_OP_ADDU_64: | |
444 | case CC_OP_ADDC_64: | |
445 | case CC_OP_SUB_64: | |
446 | case CC_OP_SUBU_64: | |
447 | case CC_OP_SUBB_64: | |
448 | case CC_OP_ADD_32: | |
449 | case CC_OP_ADDU_32: | |
450 | case CC_OP_ADDC_32: | |
451 | case CC_OP_SUB_32: | |
452 | case CC_OP_SUBU_32: | |
453 | case CC_OP_SUBB_32: | |
454 | local_cc_op = tcg_const_i32(s->cc_op); | |
455 | break; | |
456 | case CC_OP_CONST0: | |
457 | case CC_OP_CONST1: | |
458 | case CC_OP_CONST2: | |
459 | case CC_OP_CONST3: | |
460 | case CC_OP_STATIC: | |
461 | case CC_OP_DYNAMIC: | |
462 | break; | |
463 | } | |
e023e832 AG |
464 | |
465 | switch (s->cc_op) { | |
466 | case CC_OP_CONST0: | |
467 | case CC_OP_CONST1: | |
468 | case CC_OP_CONST2: | |
469 | case CC_OP_CONST3: | |
470 | /* s->cc_op is the cc value */ | |
471 | tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0); | |
472 | break; | |
473 | case CC_OP_STATIC: | |
474 | /* env->cc_op already is the cc value */ | |
475 | break; | |
476 | case CC_OP_NZ: | |
477 | case CC_OP_ABS_64: | |
478 | case CC_OP_NABS_64: | |
479 | case CC_OP_ABS_32: | |
480 | case CC_OP_NABS_32: | |
481 | case CC_OP_LTGT0_32: | |
482 | case CC_OP_LTGT0_64: | |
483 | case CC_OP_COMP_32: | |
484 | case CC_OP_COMP_64: | |
485 | case CC_OP_NZ_F32: | |
486 | case CC_OP_NZ_F64: | |
102bf2c6 | 487 | case CC_OP_FLOGR: |
e023e832 | 488 | /* 1 argument */ |
932385a3 | 489 | gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy); |
e023e832 AG |
490 | break; |
491 | case CC_OP_ICM: | |
492 | case CC_OP_LTGT_32: | |
493 | case CC_OP_LTGT_64: | |
494 | case CC_OP_LTUGTU_32: | |
495 | case CC_OP_LTUGTU_64: | |
496 | case CC_OP_TM_32: | |
497 | case CC_OP_TM_64: | |
cbe24bfa RH |
498 | case CC_OP_SLA_32: |
499 | case CC_OP_SLA_64: | |
587626f8 | 500 | case CC_OP_NZ_F128: |
e023e832 | 501 | /* 2 arguments */ |
932385a3 | 502 | gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy); |
e023e832 AG |
503 | break; |
504 | case CC_OP_ADD_64: | |
505 | case CC_OP_ADDU_64: | |
4e4bb438 | 506 | case CC_OP_ADDC_64: |
e023e832 AG |
507 | case CC_OP_SUB_64: |
508 | case CC_OP_SUBU_64: | |
4e4bb438 | 509 | case CC_OP_SUBB_64: |
e023e832 AG |
510 | case CC_OP_ADD_32: |
511 | case CC_OP_ADDU_32: | |
4e4bb438 | 512 | case CC_OP_ADDC_32: |
e023e832 AG |
513 | case CC_OP_SUB_32: |
514 | case CC_OP_SUBU_32: | |
4e4bb438 | 515 | case CC_OP_SUBB_32: |
e023e832 | 516 | /* 3 arguments */ |
932385a3 | 517 | gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr); |
e023e832 AG |
518 | break; |
519 | case CC_OP_DYNAMIC: | |
520 | /* unknown operation - assume 3 arguments and cc_op in env */ | |
932385a3 | 521 | gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr); |
e023e832 AG |
522 | break; |
523 | default: | |
524 | tcg_abort(); | |
525 | } | |
526 | ||
7a6c7067 RH |
527 | if (!TCGV_IS_UNUSED_I32(local_cc_op)) { |
528 | tcg_temp_free_i32(local_cc_op); | |
529 | } | |
530 | if (!TCGV_IS_UNUSED_I64(dummy)) { | |
531 | tcg_temp_free_i64(dummy); | |
532 | } | |
e023e832 AG |
533 | |
534 | /* We now have cc in cc_op as constant */ | |
535 | set_cc_static(s); | |
536 | } | |
537 | ||
8ac33cdb | 538 | static int use_goto_tb(DisasContext *s, uint64_t dest) |
e023e832 | 539 | { |
8ac33cdb RH |
540 | /* NOTE: we handle the case where the TB spans two pages here */ |
541 | return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) | |
542 | || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) | |
543 | && !s->singlestep_enabled | |
544 | && !(s->tb->cflags & CF_LAST_IO)); | |
545 | } | |
e023e832 | 546 | |
4f3adfb2 | 547 | static void account_noninline_branch(DisasContext *s, int cc_op) |
e023e832 AG |
548 | { |
549 | #ifdef DEBUG_INLINE_BRANCHES | |
550 | inline_branch_miss[cc_op]++; | |
551 | #endif | |
552 | } | |
553 | ||
4f3adfb2 | 554 | static void account_inline_branch(DisasContext *s, int cc_op) |
e023e832 AG |
555 | { |
556 | #ifdef DEBUG_INLINE_BRANCHES | |
3fde06f5 | 557 | inline_branch_hit[cc_op]++; |
e023e832 AG |
558 | #endif |
559 | } | |
560 | ||
3fde06f5 RH |
561 | /* Table of mask values to comparison codes, given a comparison as input. |
562 | For a true comparison CC=3 will never be set, but we treat this | |
563 | conservatively for possible use when CC=3 indicates overflow. */ | |
564 | static const TCGCond ltgt_cond[16] = { | |
565 | TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */ | |
566 | TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */ | |
567 | TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */ | |
568 | TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */ | |
569 | TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */ | |
570 | TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */ | |
571 | TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */ | |
572 | TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */ | |
573 | }; | |
574 | ||
575 | /* Table of mask values to comparison codes, given a logic op as input. | |
576 | For such, only CC=0 and CC=1 should be possible. */ | |
577 | static const TCGCond nz_cond[16] = { | |
578 | /* | | x | x */ | |
579 | TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, | |
580 | /* | NE | x | x */ | |
581 | TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, | |
582 | /* EQ | | x | x */ | |
583 | TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, | |
584 | /* EQ | NE | x | x */ | |
585 | TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, | |
586 | }; | |
587 | ||
588 | /* Interpret MASK in terms of S->CC_OP, and fill in C with all the | |
589 | details required to generate a TCG comparison. */ | |
590 | static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) | |
e023e832 | 591 | { |
3fde06f5 RH |
592 | TCGCond cond; |
593 | enum cc_op old_cc_op = s->cc_op; | |
e023e832 | 594 | |
3fde06f5 RH |
595 | if (mask == 15 || mask == 0) { |
596 | c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER); | |
597 | c->u.s32.a = cc_op; | |
598 | c->u.s32.b = cc_op; | |
599 | c->g1 = c->g2 = true; | |
600 | c->is_64 = false; | |
601 | return; | |
602 | } | |
603 | ||
604 | /* Find the TCG condition for the mask + cc op. */ | |
605 | switch (old_cc_op) { | |
e023e832 | 606 | case CC_OP_LTGT0_32: |
e023e832 | 607 | case CC_OP_LTGT0_64: |
e023e832 | 608 | case CC_OP_LTGT_32: |
e023e832 | 609 | case CC_OP_LTGT_64: |
3fde06f5 RH |
610 | cond = ltgt_cond[mask]; |
611 | if (cond == TCG_COND_NEVER) { | |
e023e832 AG |
612 | goto do_dynamic; |
613 | } | |
3fde06f5 | 614 | account_inline_branch(s, old_cc_op); |
e023e832 | 615 | break; |
3fde06f5 | 616 | |
e023e832 | 617 | case CC_OP_LTUGTU_32: |
e023e832 | 618 | case CC_OP_LTUGTU_64: |
3fde06f5 RH |
619 | cond = tcg_unsigned_cond(ltgt_cond[mask]); |
620 | if (cond == TCG_COND_NEVER) { | |
e023e832 AG |
621 | goto do_dynamic; |
622 | } | |
3fde06f5 | 623 | account_inline_branch(s, old_cc_op); |
e023e832 | 624 | break; |
3fde06f5 | 625 | |
e023e832 | 626 | case CC_OP_NZ: |
3fde06f5 RH |
627 | cond = nz_cond[mask]; |
628 | if (cond == TCG_COND_NEVER) { | |
e023e832 AG |
629 | goto do_dynamic; |
630 | } | |
3fde06f5 | 631 | account_inline_branch(s, old_cc_op); |
e023e832 | 632 | break; |
e023e832 | 633 | |
3fde06f5 | 634 | case CC_OP_TM_32: |
e023e832 | 635 | case CC_OP_TM_64: |
e023e832 | 636 | switch (mask) { |
3fde06f5 RH |
637 | case 8: |
638 | cond = TCG_COND_EQ; | |
e023e832 | 639 | break; |
3fde06f5 RH |
640 | case 4 | 2 | 1: |
641 | cond = TCG_COND_NE; | |
e023e832 AG |
642 | break; |
643 | default: | |
644 | goto do_dynamic; | |
645 | } | |
3fde06f5 | 646 | account_inline_branch(s, old_cc_op); |
e023e832 | 647 | break; |
3fde06f5 | 648 | |
e023e832 AG |
649 | case CC_OP_ICM: |
650 | switch (mask) { | |
3fde06f5 RH |
651 | case 8: |
652 | cond = TCG_COND_EQ; | |
e023e832 | 653 | break; |
3fde06f5 RH |
654 | case 4 | 2 | 1: |
655 | case 4 | 2: | |
656 | cond = TCG_COND_NE; | |
e023e832 AG |
657 | break; |
658 | default: | |
659 | goto do_dynamic; | |
660 | } | |
3fde06f5 | 661 | account_inline_branch(s, old_cc_op); |
e023e832 | 662 | break; |
3fde06f5 | 663 | |
102bf2c6 RH |
664 | case CC_OP_FLOGR: |
665 | switch (mask & 0xa) { | |
666 | case 8: /* src == 0 -> no one bit found */ | |
667 | cond = TCG_COND_EQ; | |
668 | break; | |
669 | case 2: /* src != 0 -> one bit found */ | |
670 | cond = TCG_COND_NE; | |
671 | break; | |
672 | default: | |
673 | goto do_dynamic; | |
674 | } | |
675 | account_inline_branch(s, old_cc_op); | |
676 | break; | |
677 | ||
e023e832 | 678 | default: |
3fde06f5 RH |
679 | do_dynamic: |
680 | /* Calculate cc value. */ | |
e023e832 | 681 | gen_op_calc_cc(s); |
3fde06f5 | 682 | /* FALLTHRU */ |
e023e832 | 683 | |
3fde06f5 RH |
684 | case CC_OP_STATIC: |
685 | /* Jump based on CC. We'll load up the real cond below; | |
686 | the assignment here merely avoids a compiler warning. */ | |
e023e832 | 687 | account_noninline_branch(s, old_cc_op); |
3fde06f5 RH |
688 | old_cc_op = CC_OP_STATIC; |
689 | cond = TCG_COND_NEVER; | |
690 | break; | |
691 | } | |
e023e832 | 692 | |
3fde06f5 RH |
693 | /* Load up the arguments of the comparison. */ |
694 | c->is_64 = true; | |
695 | c->g1 = c->g2 = false; | |
696 | switch (old_cc_op) { | |
697 | case CC_OP_LTGT0_32: | |
698 | c->is_64 = false; | |
699 | c->u.s32.a = tcg_temp_new_i32(); | |
700 | tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst); | |
701 | c->u.s32.b = tcg_const_i32(0); | |
702 | break; | |
703 | case CC_OP_LTGT_32: | |
704 | case CC_OP_LTUGTU_32: | |
705 | c->is_64 = false; | |
706 | c->u.s32.a = tcg_temp_new_i32(); | |
707 | tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src); | |
708 | c->u.s32.b = tcg_temp_new_i32(); | |
709 | tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst); | |
710 | break; | |
711 | ||
712 | case CC_OP_LTGT0_64: | |
713 | case CC_OP_NZ: | |
102bf2c6 | 714 | case CC_OP_FLOGR: |
3fde06f5 RH |
715 | c->u.s64.a = cc_dst; |
716 | c->u.s64.b = tcg_const_i64(0); | |
717 | c->g1 = true; | |
718 | break; | |
719 | case CC_OP_LTGT_64: | |
720 | case CC_OP_LTUGTU_64: | |
721 | c->u.s64.a = cc_src; | |
722 | c->u.s64.b = cc_dst; | |
723 | c->g1 = c->g2 = true; | |
724 | break; | |
725 | ||
726 | case CC_OP_TM_32: | |
727 | case CC_OP_TM_64: | |
58a9e35b | 728 | case CC_OP_ICM: |
3fde06f5 RH |
729 | c->u.s64.a = tcg_temp_new_i64(); |
730 | c->u.s64.b = tcg_const_i64(0); | |
731 | tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst); | |
732 | break; | |
733 | ||
734 | case CC_OP_STATIC: | |
735 | c->is_64 = false; | |
736 | c->u.s32.a = cc_op; | |
737 | c->g1 = true; | |
e023e832 | 738 | switch (mask) { |
e023e832 | 739 | case 0x8 | 0x4 | 0x2: /* cc != 3 */ |
3fde06f5 RH |
740 | cond = TCG_COND_NE; |
741 | c->u.s32.b = tcg_const_i32(3); | |
e023e832 AG |
742 | break; |
743 | case 0x8 | 0x4 | 0x1: /* cc != 2 */ | |
3fde06f5 RH |
744 | cond = TCG_COND_NE; |
745 | c->u.s32.b = tcg_const_i32(2); | |
e023e832 AG |
746 | break; |
747 | case 0x8 | 0x2 | 0x1: /* cc != 1 */ | |
3fde06f5 RH |
748 | cond = TCG_COND_NE; |
749 | c->u.s32.b = tcg_const_i32(1); | |
e023e832 | 750 | break; |
3fde06f5 RH |
751 | case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */ |
752 | cond = TCG_COND_EQ; | |
753 | c->g1 = false; | |
754 | c->u.s32.a = tcg_temp_new_i32(); | |
755 | c->u.s32.b = tcg_const_i32(0); | |
756 | tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); | |
e023e832 AG |
757 | break; |
758 | case 0x8 | 0x4: /* cc < 2 */ | |
3fde06f5 RH |
759 | cond = TCG_COND_LTU; |
760 | c->u.s32.b = tcg_const_i32(2); | |
e023e832 AG |
761 | break; |
762 | case 0x8: /* cc == 0 */ | |
3fde06f5 RH |
763 | cond = TCG_COND_EQ; |
764 | c->u.s32.b = tcg_const_i32(0); | |
e023e832 AG |
765 | break; |
766 | case 0x4 | 0x2 | 0x1: /* cc != 0 */ | |
3fde06f5 RH |
767 | cond = TCG_COND_NE; |
768 | c->u.s32.b = tcg_const_i32(0); | |
e023e832 | 769 | break; |
3fde06f5 RH |
770 | case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */ |
771 | cond = TCG_COND_NE; | |
772 | c->g1 = false; | |
773 | c->u.s32.a = tcg_temp_new_i32(); | |
774 | c->u.s32.b = tcg_const_i32(0); | |
775 | tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); | |
e023e832 AG |
776 | break; |
777 | case 0x4: /* cc == 1 */ | |
3fde06f5 RH |
778 | cond = TCG_COND_EQ; |
779 | c->u.s32.b = tcg_const_i32(1); | |
e023e832 AG |
780 | break; |
781 | case 0x2 | 0x1: /* cc > 1 */ | |
3fde06f5 RH |
782 | cond = TCG_COND_GTU; |
783 | c->u.s32.b = tcg_const_i32(1); | |
e023e832 AG |
784 | break; |
785 | case 0x2: /* cc == 2 */ | |
3fde06f5 RH |
786 | cond = TCG_COND_EQ; |
787 | c->u.s32.b = tcg_const_i32(2); | |
e023e832 AG |
788 | break; |
789 | case 0x1: /* cc == 3 */ | |
3fde06f5 RH |
790 | cond = TCG_COND_EQ; |
791 | c->u.s32.b = tcg_const_i32(3); | |
e023e832 | 792 | break; |
3fde06f5 RH |
793 | default: |
794 | /* CC is masked by something else: (8 >> cc) & mask. */ | |
795 | cond = TCG_COND_NE; | |
796 | c->g1 = false; | |
797 | c->u.s32.a = tcg_const_i32(8); | |
798 | c->u.s32.b = tcg_const_i32(0); | |
799 | tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op); | |
800 | tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask); | |
e023e832 AG |
801 | break; |
802 | } | |
803 | break; | |
3fde06f5 RH |
804 | |
805 | default: | |
806 | abort(); | |
e023e832 | 807 | } |
3fde06f5 RH |
808 | c->cond = cond; |
809 | } | |
810 | ||
811 | static void free_compare(DisasCompare *c) | |
812 | { | |
813 | if (!c->g1) { | |
814 | if (c->is_64) { | |
815 | tcg_temp_free_i64(c->u.s64.a); | |
816 | } else { | |
817 | tcg_temp_free_i32(c->u.s32.a); | |
818 | } | |
819 | } | |
820 | if (!c->g2) { | |
821 | if (c->is_64) { | |
822 | tcg_temp_free_i64(c->u.s64.b); | |
823 | } else { | |
824 | tcg_temp_free_i32(c->u.s32.b); | |
825 | } | |
826 | } | |
827 | } | |
828 | ||
ad044d09 RH |
829 | /* ====================================================================== */ |
830 | /* Define the insn format enumeration. */ | |
831 | #define F0(N) FMT_##N, | |
832 | #define F1(N, X1) F0(N) | |
833 | #define F2(N, X1, X2) F0(N) | |
834 | #define F3(N, X1, X2, X3) F0(N) | |
835 | #define F4(N, X1, X2, X3, X4) F0(N) | |
836 | #define F5(N, X1, X2, X3, X4, X5) F0(N) | |
837 | ||
838 | typedef enum { | |
839 | #include "insn-format.def" | |
840 | } DisasFormat; | |
841 | ||
842 | #undef F0 | |
843 | #undef F1 | |
844 | #undef F2 | |
845 | #undef F3 | |
846 | #undef F4 | |
847 | #undef F5 | |
848 | ||
849 | /* Define a structure to hold the decoded fields. We'll store each inside | |
850 | an array indexed by an enum. In order to conserve memory, we'll arrange | |
851 | for fields that do not exist at the same time to overlap, thus the "C" | |
852 | for compact. For checking purposes there is an "O" for original index | |
853 | as well that will be applied to availability bitmaps. */ | |
854 | ||
855 | enum DisasFieldIndexO { | |
856 | FLD_O_r1, | |
857 | FLD_O_r2, | |
858 | FLD_O_r3, | |
859 | FLD_O_m1, | |
860 | FLD_O_m3, | |
861 | FLD_O_m4, | |
862 | FLD_O_b1, | |
863 | FLD_O_b2, | |
864 | FLD_O_b4, | |
865 | FLD_O_d1, | |
866 | FLD_O_d2, | |
867 | FLD_O_d4, | |
868 | FLD_O_x2, | |
869 | FLD_O_l1, | |
870 | FLD_O_l2, | |
871 | FLD_O_i1, | |
872 | FLD_O_i2, | |
873 | FLD_O_i3, | |
874 | FLD_O_i4, | |
875 | FLD_O_i5 | |
876 | }; | |
877 | ||
878 | enum DisasFieldIndexC { | |
879 | FLD_C_r1 = 0, | |
880 | FLD_C_m1 = 0, | |
881 | FLD_C_b1 = 0, | |
882 | FLD_C_i1 = 0, | |
883 | ||
884 | FLD_C_r2 = 1, | |
885 | FLD_C_b2 = 1, | |
886 | FLD_C_i2 = 1, | |
887 | ||
888 | FLD_C_r3 = 2, | |
889 | FLD_C_m3 = 2, | |
890 | FLD_C_i3 = 2, | |
891 | ||
892 | FLD_C_m4 = 3, | |
893 | FLD_C_b4 = 3, | |
894 | FLD_C_i4 = 3, | |
895 | FLD_C_l1 = 3, | |
896 | ||
897 | FLD_C_i5 = 4, | |
898 | FLD_C_d1 = 4, | |
899 | ||
900 | FLD_C_d2 = 5, | |
901 | ||
902 | FLD_C_d4 = 6, | |
903 | FLD_C_x2 = 6, | |
904 | FLD_C_l2 = 6, | |
905 | ||
906 | NUM_C_FIELD = 7 | |
907 | }; | |
908 | ||
909 | struct DisasFields { | |
910 | unsigned op:8; | |
911 | unsigned op2:8; | |
912 | unsigned presentC:16; | |
913 | unsigned int presentO; | |
914 | int c[NUM_C_FIELD]; | |
915 | }; | |
916 | ||
917 | /* This is the way fields are to be accessed out of DisasFields. */ | |
918 | #define have_field(S, F) have_field1((S), FLD_O_##F) | |
919 | #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F) | |
920 | ||
921 | static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c) | |
922 | { | |
923 | return (f->presentO >> c) & 1; | |
924 | } | |
925 | ||
926 | static int get_field1(const DisasFields *f, enum DisasFieldIndexO o, | |
927 | enum DisasFieldIndexC c) | |
928 | { | |
929 | assert(have_field1(f, o)); | |
930 | return f->c[c]; | |
931 | } | |
932 | ||
933 | /* Describe the layout of each field in each format. */ | |
934 | typedef struct DisasField { | |
935 | unsigned int beg:8; | |
936 | unsigned int size:8; | |
937 | unsigned int type:2; | |
938 | unsigned int indexC:6; | |
939 | enum DisasFieldIndexO indexO:8; | |
940 | } DisasField; | |
941 | ||
942 | typedef struct DisasFormatInfo { | |
943 | DisasField op[NUM_C_FIELD]; | |
944 | } DisasFormatInfo; | |
945 | ||
946 | #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N } | |
947 | #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N } | |
948 | #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \ | |
949 | { BD, 12, 0, FLD_C_d##N, FLD_O_d##N } | |
950 | #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \ | |
951 | { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \ | |
952 | { 20, 12, 0, FLD_C_d##N, FLD_O_d##N } | |
953 | #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \ | |
954 | { 20, 20, 2, FLD_C_d##N, FLD_O_d##N } | |
955 | #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \ | |
956 | { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \ | |
957 | { 20, 20, 2, FLD_C_d##N, FLD_O_d##N } | |
958 | #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N } | |
959 | #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N } | |
960 | ||
961 | #define F0(N) { { } }, | |
962 | #define F1(N, X1) { { X1 } }, | |
963 | #define F2(N, X1, X2) { { X1, X2 } }, | |
964 | #define F3(N, X1, X2, X3) { { X1, X2, X3 } }, | |
965 | #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } }, | |
966 | #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } }, | |
967 | ||
968 | static const DisasFormatInfo format_info[] = { | |
969 | #include "insn-format.def" | |
970 | }; | |
971 | ||
972 | #undef F0 | |
973 | #undef F1 | |
974 | #undef F2 | |
975 | #undef F3 | |
976 | #undef F4 | |
977 | #undef F5 | |
978 | #undef R | |
979 | #undef M | |
980 | #undef BD | |
981 | #undef BXD | |
982 | #undef BDL | |
983 | #undef BXDL | |
984 | #undef I | |
985 | #undef L | |
986 | ||
987 | /* Generally, we'll extract operands into this structures, operate upon | |
988 | them, and store them back. See the "in1", "in2", "prep", "wout" sets | |
989 | of routines below for more details. */ | |
990 | typedef struct { | |
991 | bool g_out, g_out2, g_in1, g_in2; | |
992 | TCGv_i64 out, out2, in1, in2; | |
993 | TCGv_i64 addr1; | |
994 | } DisasOps; | |
995 | ||
49f7ee80 RH |
996 | /* Instructions can place constraints on their operands, raising specification |
997 | exceptions if they are violated. To make this easy to automate, each "in1", | |
998 | "in2", "prep", "wout" helper will have a SPEC_<name> define that equals one | |
999 | of the following, or 0. To make this easy to document, we'll put the | |
1000 | SPEC_<name> defines next to <name>. */ | |
1001 | ||
1002 | #define SPEC_r1_even 1 | |
1003 | #define SPEC_r2_even 2 | |
1004 | #define SPEC_r1_f128 4 | |
1005 | #define SPEC_r2_f128 8 | |
1006 | ||
ad044d09 RH |
1007 | /* Return values from translate_one, indicating the state of the TB. */ |
1008 | typedef enum { | |
1009 | /* Continue the TB. */ | |
1010 | NO_EXIT, | |
1011 | /* We have emitted one or more goto_tb. No fixup required. */ | |
1012 | EXIT_GOTO_TB, | |
1013 | /* We are not using a goto_tb (for whatever reason), but have updated | |
1014 | the PC (for whatever reason), so there's no need to do it again on | |
1015 | exiting the TB. */ | |
1016 | EXIT_PC_UPDATED, | |
1017 | /* We are exiting the TB, but have neither emitted a goto_tb, nor | |
1018 | updated the PC for the next instruction to be executed. */ | |
1019 | EXIT_PC_STALE, | |
1020 | /* We are ending the TB with a noreturn function call, e.g. longjmp. | |
1021 | No following code will be executed. */ | |
1022 | EXIT_NORETURN, | |
1023 | } ExitStatus; | |
1024 | ||
1025 | typedef enum DisasFacility { | |
1026 | FAC_Z, /* zarch (default) */ | |
1027 | FAC_CASS, /* compare and swap and store */ | |
1028 | FAC_CASS2, /* compare and swap and store 2*/ | |
1029 | FAC_DFP, /* decimal floating point */ | |
1030 | FAC_DFPR, /* decimal floating point rounding */ | |
1031 | FAC_DO, /* distinct operands */ | |
1032 | FAC_EE, /* execute extensions */ | |
1033 | FAC_EI, /* extended immediate */ | |
1034 | FAC_FPE, /* floating point extension */ | |
1035 | FAC_FPSSH, /* floating point support sign handling */ | |
1036 | FAC_FPRGR, /* FPR-GR transfer */ | |
1037 | FAC_GIE, /* general instructions extension */ | |
1038 | FAC_HFP_MA, /* HFP multiply-and-add/subtract */ | |
1039 | FAC_HW, /* high-word */ | |
1040 | FAC_IEEEE_SIM, /* IEEE exception sumilation */ | |
1041 | FAC_LOC, /* load/store on condition */ | |
1042 | FAC_LD, /* long displacement */ | |
1043 | FAC_PC, /* population count */ | |
1044 | FAC_SCF, /* store clock fast */ | |
1045 | FAC_SFLE, /* store facility list extended */ | |
1046 | } DisasFacility; | |
1047 | ||
1048 | struct DisasInsn { | |
1049 | unsigned opc:16; | |
1050 | DisasFormat fmt:6; | |
1051 | DisasFacility fac:6; | |
49f7ee80 | 1052 | unsigned spec:4; |
ad044d09 RH |
1053 | |
1054 | const char *name; | |
1055 | ||
1056 | void (*help_in1)(DisasContext *, DisasFields *, DisasOps *); | |
1057 | void (*help_in2)(DisasContext *, DisasFields *, DisasOps *); | |
1058 | void (*help_prep)(DisasContext *, DisasFields *, DisasOps *); | |
1059 | void (*help_wout)(DisasContext *, DisasFields *, DisasOps *); | |
1060 | void (*help_cout)(DisasContext *, DisasOps *); | |
1061 | ExitStatus (*help_op)(DisasContext *, DisasOps *); | |
1062 | ||
1063 | uint64_t data; | |
1064 | }; | |
1065 | ||
8ac33cdb RH |
1066 | /* ====================================================================== */ |
1067 | /* Miscelaneous helpers, used by several operations. */ | |
1068 | ||
cbe24bfa RH |
1069 | static void help_l2_shift(DisasContext *s, DisasFields *f, |
1070 | DisasOps *o, int mask) | |
1071 | { | |
1072 | int b2 = get_field(f, b2); | |
1073 | int d2 = get_field(f, d2); | |
1074 | ||
1075 | if (b2 == 0) { | |
1076 | o->in2 = tcg_const_i64(d2 & mask); | |
1077 | } else { | |
1078 | o->in2 = get_address(s, 0, b2, d2); | |
1079 | tcg_gen_andi_i64(o->in2, o->in2, mask); | |
1080 | } | |
1081 | } | |
1082 | ||
8ac33cdb RH |
1083 | static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest) |
1084 | { | |
1085 | if (dest == s->next_pc) { | |
1086 | return NO_EXIT; | |
1087 | } | |
1088 | if (use_goto_tb(s, dest)) { | |
7a6c7067 | 1089 | update_cc_op(s); |
8ac33cdb RH |
1090 | tcg_gen_goto_tb(0); |
1091 | tcg_gen_movi_i64(psw_addr, dest); | |
1092 | tcg_gen_exit_tb((tcg_target_long)s->tb); | |
1093 | return EXIT_GOTO_TB; | |
1094 | } else { | |
1095 | tcg_gen_movi_i64(psw_addr, dest); | |
1096 | return EXIT_PC_UPDATED; | |
1097 | } | |
1098 | } | |
1099 | ||
7233f2ed RH |
1100 | static ExitStatus help_branch(DisasContext *s, DisasCompare *c, |
1101 | bool is_imm, int imm, TCGv_i64 cdest) | |
1102 | { | |
1103 | ExitStatus ret; | |
1104 | uint64_t dest = s->pc + 2 * imm; | |
1105 | int lab; | |
1106 | ||
1107 | /* Take care of the special cases first. */ | |
1108 | if (c->cond == TCG_COND_NEVER) { | |
1109 | ret = NO_EXIT; | |
1110 | goto egress; | |
1111 | } | |
1112 | if (is_imm) { | |
1113 | if (dest == s->next_pc) { | |
1114 | /* Branch to next. */ | |
1115 | ret = NO_EXIT; | |
1116 | goto egress; | |
1117 | } | |
1118 | if (c->cond == TCG_COND_ALWAYS) { | |
1119 | ret = help_goto_direct(s, dest); | |
1120 | goto egress; | |
1121 | } | |
1122 | } else { | |
1123 | if (TCGV_IS_UNUSED_I64(cdest)) { | |
1124 | /* E.g. bcr %r0 -> no branch. */ | |
1125 | ret = NO_EXIT; | |
1126 | goto egress; | |
1127 | } | |
1128 | if (c->cond == TCG_COND_ALWAYS) { | |
1129 | tcg_gen_mov_i64(psw_addr, cdest); | |
1130 | ret = EXIT_PC_UPDATED; | |
1131 | goto egress; | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | if (use_goto_tb(s, s->next_pc)) { | |
1136 | if (is_imm && use_goto_tb(s, dest)) { | |
1137 | /* Both exits can use goto_tb. */ | |
7a6c7067 | 1138 | update_cc_op(s); |
7233f2ed RH |
1139 | |
1140 | lab = gen_new_label(); | |
1141 | if (c->is_64) { | |
1142 | tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); | |
1143 | } else { | |
1144 | tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); | |
1145 | } | |
1146 | ||
1147 | /* Branch not taken. */ | |
1148 | tcg_gen_goto_tb(0); | |
1149 | tcg_gen_movi_i64(psw_addr, s->next_pc); | |
1150 | tcg_gen_exit_tb((tcg_target_long)s->tb + 0); | |
1151 | ||
1152 | /* Branch taken. */ | |
1153 | gen_set_label(lab); | |
1154 | tcg_gen_goto_tb(1); | |
1155 | tcg_gen_movi_i64(psw_addr, dest); | |
1156 | tcg_gen_exit_tb((tcg_target_long)s->tb + 1); | |
1157 | ||
1158 | ret = EXIT_GOTO_TB; | |
1159 | } else { | |
1160 | /* Fallthru can use goto_tb, but taken branch cannot. */ | |
1161 | /* Store taken branch destination before the brcond. This | |
1162 | avoids having to allocate a new local temp to hold it. | |
1163 | We'll overwrite this in the not taken case anyway. */ | |
1164 | if (!is_imm) { | |
1165 | tcg_gen_mov_i64(psw_addr, cdest); | |
1166 | } | |
1167 | ||
1168 | lab = gen_new_label(); | |
1169 | if (c->is_64) { | |
1170 | tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); | |
1171 | } else { | |
1172 | tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); | |
1173 | } | |
1174 | ||
1175 | /* Branch not taken. */ | |
7a6c7067 | 1176 | update_cc_op(s); |
7233f2ed RH |
1177 | tcg_gen_goto_tb(0); |
1178 | tcg_gen_movi_i64(psw_addr, s->next_pc); | |
1179 | tcg_gen_exit_tb((tcg_target_long)s->tb + 0); | |
1180 | ||
1181 | gen_set_label(lab); | |
1182 | if (is_imm) { | |
1183 | tcg_gen_movi_i64(psw_addr, dest); | |
1184 | } | |
1185 | ret = EXIT_PC_UPDATED; | |
1186 | } | |
1187 | } else { | |
1188 | /* Fallthru cannot use goto_tb. This by itself is vanishingly rare. | |
1189 | Most commonly we're single-stepping or some other condition that | |
1190 | disables all use of goto_tb. Just update the PC and exit. */ | |
1191 | ||
1192 | TCGv_i64 next = tcg_const_i64(s->next_pc); | |
1193 | if (is_imm) { | |
1194 | cdest = tcg_const_i64(dest); | |
1195 | } | |
1196 | ||
1197 | if (c->is_64) { | |
1198 | tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b, | |
1199 | cdest, next); | |
1200 | } else { | |
1201 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1202 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1203 | TCGv_i64 z = tcg_const_i64(0); | |
1204 | tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); | |
1205 | tcg_gen_extu_i32_i64(t1, t0); | |
1206 | tcg_temp_free_i32(t0); | |
1207 | tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); | |
1208 | tcg_temp_free_i64(t1); | |
1209 | tcg_temp_free_i64(z); | |
1210 | } | |
1211 | ||
1212 | if (is_imm) { | |
1213 | tcg_temp_free_i64(cdest); | |
1214 | } | |
1215 | tcg_temp_free_i64(next); | |
1216 | ||
1217 | ret = EXIT_PC_UPDATED; | |
1218 | } | |
1219 | ||
1220 | egress: | |
1221 | free_compare(c); | |
1222 | return ret; | |
1223 | } | |
1224 | ||
ad044d09 RH |
1225 | /* ====================================================================== */ |
1226 | /* The operations. These perform the bulk of the work for any insn, | |
1227 | usually after the operands have been loaded and output initialized. */ | |
1228 | ||
b9bca3e5 RH |
1229 | static ExitStatus op_abs(DisasContext *s, DisasOps *o) |
1230 | { | |
1231 | gen_helper_abs_i64(o->out, o->in2); | |
1232 | return NO_EXIT; | |
1233 | } | |
1234 | ||
5d7fd045 RH |
1235 | static ExitStatus op_absf32(DisasContext *s, DisasOps *o) |
1236 | { | |
1237 | tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull); | |
1238 | return NO_EXIT; | |
1239 | } | |
1240 | ||
1241 | static ExitStatus op_absf64(DisasContext *s, DisasOps *o) | |
1242 | { | |
1243 | tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull); | |
1244 | return NO_EXIT; | |
1245 | } | |
1246 | ||
1247 | static ExitStatus op_absf128(DisasContext *s, DisasOps *o) | |
1248 | { | |
1249 | tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull); | |
1250 | tcg_gen_mov_i64(o->out2, o->in2); | |
1251 | return NO_EXIT; | |
1252 | } | |
1253 | ||
ad044d09 RH |
1254 | static ExitStatus op_add(DisasContext *s, DisasOps *o) |
1255 | { | |
1256 | tcg_gen_add_i64(o->out, o->in1, o->in2); | |
1257 | return NO_EXIT; | |
1258 | } | |
1259 | ||
4e4bb438 RH |
1260 | static ExitStatus op_addc(DisasContext *s, DisasOps *o) |
1261 | { | |
1262 | TCGv_i64 cc; | |
1263 | ||
1264 | tcg_gen_add_i64(o->out, o->in1, o->in2); | |
1265 | ||
1266 | /* XXX possible optimization point */ | |
1267 | gen_op_calc_cc(s); | |
1268 | cc = tcg_temp_new_i64(); | |
1269 | tcg_gen_extu_i32_i64(cc, cc_op); | |
1270 | tcg_gen_shri_i64(cc, cc, 1); | |
1271 | ||
1272 | tcg_gen_add_i64(o->out, o->out, cc); | |
1273 | tcg_temp_free_i64(cc); | |
1274 | return NO_EXIT; | |
1275 | } | |
1276 | ||
587626f8 RH |
1277 | static ExitStatus op_aeb(DisasContext *s, DisasOps *o) |
1278 | { | |
1279 | gen_helper_aeb(o->out, cpu_env, o->in1, o->in2); | |
1280 | return NO_EXIT; | |
1281 | } | |
1282 | ||
1283 | static ExitStatus op_adb(DisasContext *s, DisasOps *o) | |
1284 | { | |
1285 | gen_helper_adb(o->out, cpu_env, o->in1, o->in2); | |
1286 | return NO_EXIT; | |
1287 | } | |
1288 | ||
1289 | static ExitStatus op_axb(DisasContext *s, DisasOps *o) | |
1290 | { | |
1291 | gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); | |
1292 | return_low128(o->out2); | |
1293 | return NO_EXIT; | |
1294 | } | |
1295 | ||
3bbfbd1f RH |
1296 | static ExitStatus op_and(DisasContext *s, DisasOps *o) |
1297 | { | |
1298 | tcg_gen_and_i64(o->out, o->in1, o->in2); | |
1299 | return NO_EXIT; | |
1300 | } | |
1301 | ||
facfc864 RH |
1302 | static ExitStatus op_andi(DisasContext *s, DisasOps *o) |
1303 | { | |
1304 | int shift = s->insn->data & 0xff; | |
1305 | int size = s->insn->data >> 8; | |
1306 | uint64_t mask = ((1ull << size) - 1) << shift; | |
1307 | ||
1308 | assert(!o->g_in2); | |
1309 | tcg_gen_shli_i64(o->in2, o->in2, shift); | |
1310 | tcg_gen_ori_i64(o->in2, o->in2, ~mask); | |
1311 | tcg_gen_and_i64(o->out, o->in1, o->in2); | |
1312 | ||
1313 | /* Produce the CC from only the bits manipulated. */ | |
1314 | tcg_gen_andi_i64(cc_dst, o->out, mask); | |
1315 | set_cc_nz_u64(s, cc_dst); | |
1316 | return NO_EXIT; | |
1317 | } | |
1318 | ||
8ac33cdb RH |
1319 | static ExitStatus op_bas(DisasContext *s, DisasOps *o) |
1320 | { | |
1321 | tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc)); | |
1322 | if (!TCGV_IS_UNUSED_I64(o->in2)) { | |
1323 | tcg_gen_mov_i64(psw_addr, o->in2); | |
1324 | return EXIT_PC_UPDATED; | |
1325 | } else { | |
1326 | return NO_EXIT; | |
1327 | } | |
1328 | } | |
1329 | ||
1330 | static ExitStatus op_basi(DisasContext *s, DisasOps *o) | |
1331 | { | |
1332 | tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc)); | |
1333 | return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2)); | |
1334 | } | |
1335 | ||
7233f2ed RH |
1336 | static ExitStatus op_bc(DisasContext *s, DisasOps *o) |
1337 | { | |
1338 | int m1 = get_field(s->fields, m1); | |
1339 | bool is_imm = have_field(s->fields, i2); | |
1340 | int imm = is_imm ? get_field(s->fields, i2) : 0; | |
1341 | DisasCompare c; | |
1342 | ||
1343 | disas_jcc(s, &c, m1); | |
1344 | return help_branch(s, &c, is_imm, imm, o->in2); | |
1345 | } | |
1346 | ||
c61aad69 RH |
1347 | static ExitStatus op_bct32(DisasContext *s, DisasOps *o) |
1348 | { | |
1349 | int r1 = get_field(s->fields, r1); | |
1350 | bool is_imm = have_field(s->fields, i2); | |
1351 | int imm = is_imm ? get_field(s->fields, i2) : 0; | |
1352 | DisasCompare c; | |
1353 | TCGv_i64 t; | |
1354 | ||
1355 | c.cond = TCG_COND_NE; | |
1356 | c.is_64 = false; | |
1357 | c.g1 = false; | |
1358 | c.g2 = false; | |
1359 | ||
1360 | t = tcg_temp_new_i64(); | |
1361 | tcg_gen_subi_i64(t, regs[r1], 1); | |
1362 | store_reg32_i64(r1, t); | |
1363 | c.u.s32.a = tcg_temp_new_i32(); | |
1364 | c.u.s32.b = tcg_const_i32(0); | |
1365 | tcg_gen_trunc_i64_i32(c.u.s32.a, t); | |
1366 | tcg_temp_free_i64(t); | |
1367 | ||
1368 | return help_branch(s, &c, is_imm, imm, o->in2); | |
1369 | } | |
1370 | ||
1371 | static ExitStatus op_bct64(DisasContext *s, DisasOps *o) | |
1372 | { | |
1373 | int r1 = get_field(s->fields, r1); | |
1374 | bool is_imm = have_field(s->fields, i2); | |
1375 | int imm = is_imm ? get_field(s->fields, i2) : 0; | |
1376 | DisasCompare c; | |
1377 | ||
1378 | c.cond = TCG_COND_NE; | |
1379 | c.is_64 = true; | |
1380 | c.g1 = true; | |
1381 | c.g2 = false; | |
1382 | ||
1383 | tcg_gen_subi_i64(regs[r1], regs[r1], 1); | |
1384 | c.u.s64.a = regs[r1]; | |
1385 | c.u.s64.b = tcg_const_i64(0); | |
1386 | ||
2cf5e350 RH |
1387 | return help_branch(s, &c, is_imm, imm, o->in2); |
1388 | } | |
1389 | ||
1390 | static ExitStatus op_bx32(DisasContext *s, DisasOps *o) | |
1391 | { | |
1392 | int r1 = get_field(s->fields, r1); | |
1393 | int r3 = get_field(s->fields, r3); | |
1394 | bool is_imm = have_field(s->fields, i2); | |
1395 | int imm = is_imm ? get_field(s->fields, i2) : 0; | |
1396 | DisasCompare c; | |
1397 | TCGv_i64 t; | |
1398 | ||
1399 | c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT); | |
1400 | c.is_64 = false; | |
1401 | c.g1 = false; | |
1402 | c.g2 = false; | |
1403 | ||
1404 | t = tcg_temp_new_i64(); | |
1405 | tcg_gen_add_i64(t, regs[r1], regs[r3]); | |
1406 | c.u.s32.a = tcg_temp_new_i32(); | |
1407 | c.u.s32.b = tcg_temp_new_i32(); | |
1408 | tcg_gen_trunc_i64_i32(c.u.s32.a, t); | |
1409 | tcg_gen_trunc_i64_i32(c.u.s32.b, regs[r3 | 1]); | |
1410 | store_reg32_i64(r1, t); | |
1411 | tcg_temp_free_i64(t); | |
1412 | ||
1413 | return help_branch(s, &c, is_imm, imm, o->in2); | |
1414 | } | |
1415 | ||
1416 | static ExitStatus op_bx64(DisasContext *s, DisasOps *o) | |
1417 | { | |
1418 | int r1 = get_field(s->fields, r1); | |
1419 | int r3 = get_field(s->fields, r3); | |
1420 | bool is_imm = have_field(s->fields, i2); | |
1421 | int imm = is_imm ? get_field(s->fields, i2) : 0; | |
1422 | DisasCompare c; | |
1423 | ||
1424 | c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT); | |
1425 | c.is_64 = true; | |
1426 | ||
1427 | if (r1 == (r3 | 1)) { | |
1428 | c.u.s64.b = load_reg(r3 | 1); | |
1429 | c.g2 = false; | |
1430 | } else { | |
1431 | c.u.s64.b = regs[r3 | 1]; | |
1432 | c.g2 = true; | |
1433 | } | |
1434 | ||
1435 | tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]); | |
1436 | c.u.s64.a = regs[r1]; | |
1437 | c.g1 = true; | |
1438 | ||
c61aad69 RH |
1439 | return help_branch(s, &c, is_imm, imm, o->in2); |
1440 | } | |
1441 | ||
5550359f RH |
1442 | static ExitStatus op_cj(DisasContext *s, DisasOps *o) |
1443 | { | |
1444 | int imm, m3 = get_field(s->fields, m3); | |
1445 | bool is_imm; | |
1446 | DisasCompare c; | |
1447 | ||
1448 | /* Bit 3 of the m3 field is reserved and should be zero. | |
1449 | Choose to ignore it wrt the ltgt_cond table above. */ | |
1450 | c.cond = ltgt_cond[m3 & 14]; | |
1451 | if (s->insn->data) { | |
1452 | c.cond = tcg_unsigned_cond(c.cond); | |
1453 | } | |
1454 | c.is_64 = c.g1 = c.g2 = true; | |
1455 | c.u.s64.a = o->in1; | |
1456 | c.u.s64.b = o->in2; | |
1457 | ||
1458 | is_imm = have_field(s->fields, i4); | |
1459 | if (is_imm) { | |
1460 | imm = get_field(s->fields, i4); | |
1461 | } else { | |
1462 | imm = 0; | |
1463 | o->out = get_address(s, 0, get_field(s->fields, b4), | |
1464 | get_field(s->fields, d4)); | |
1465 | } | |
1466 | ||
1467 | return help_branch(s, &c, is_imm, imm, o->out); | |
1468 | } | |
1469 | ||
587626f8 RH |
1470 | static ExitStatus op_ceb(DisasContext *s, DisasOps *o) |
1471 | { | |
1472 | gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2); | |
1473 | set_cc_static(s); | |
1474 | return NO_EXIT; | |
1475 | } | |
1476 | ||
1477 | static ExitStatus op_cdb(DisasContext *s, DisasOps *o) | |
1478 | { | |
1479 | gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2); | |
1480 | set_cc_static(s); | |
1481 | return NO_EXIT; | |
1482 | } | |
1483 | ||
1484 | static ExitStatus op_cxb(DisasContext *s, DisasOps *o) | |
1485 | { | |
1486 | gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2); | |
1487 | set_cc_static(s); | |
1488 | return NO_EXIT; | |
1489 | } | |
1490 | ||
68c8bd93 RH |
1491 | static ExitStatus op_cfeb(DisasContext *s, DisasOps *o) |
1492 | { | |
1493 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1494 | gen_helper_cfeb(o->out, cpu_env, o->in2, m3); | |
1495 | tcg_temp_free_i32(m3); | |
1496 | gen_set_cc_nz_f32(s, o->in2); | |
1497 | return NO_EXIT; | |
1498 | } | |
1499 | ||
1500 | static ExitStatus op_cfdb(DisasContext *s, DisasOps *o) | |
1501 | { | |
1502 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1503 | gen_helper_cfdb(o->out, cpu_env, o->in2, m3); | |
1504 | tcg_temp_free_i32(m3); | |
1505 | gen_set_cc_nz_f64(s, o->in2); | |
1506 | return NO_EXIT; | |
1507 | } | |
1508 | ||
1509 | static ExitStatus op_cfxb(DisasContext *s, DisasOps *o) | |
1510 | { | |
1511 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1512 | gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3); | |
1513 | tcg_temp_free_i32(m3); | |
1514 | gen_set_cc_nz_f128(s, o->in1, o->in2); | |
1515 | return NO_EXIT; | |
1516 | } | |
1517 | ||
1518 | static ExitStatus op_cgeb(DisasContext *s, DisasOps *o) | |
1519 | { | |
1520 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1521 | gen_helper_cgeb(o->out, cpu_env, o->in2, m3); | |
1522 | tcg_temp_free_i32(m3); | |
1523 | gen_set_cc_nz_f32(s, o->in2); | |
1524 | return NO_EXIT; | |
1525 | } | |
1526 | ||
1527 | static ExitStatus op_cgdb(DisasContext *s, DisasOps *o) | |
1528 | { | |
1529 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1530 | gen_helper_cgdb(o->out, cpu_env, o->in2, m3); | |
1531 | tcg_temp_free_i32(m3); | |
1532 | gen_set_cc_nz_f64(s, o->in2); | |
1533 | return NO_EXIT; | |
1534 | } | |
1535 | ||
1536 | static ExitStatus op_cgxb(DisasContext *s, DisasOps *o) | |
1537 | { | |
1538 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1539 | gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3); | |
1540 | tcg_temp_free_i32(m3); | |
1541 | gen_set_cc_nz_f128(s, o->in1, o->in2); | |
1542 | return NO_EXIT; | |
1543 | } | |
1544 | ||
6ac1b45f RH |
1545 | static ExitStatus op_clfeb(DisasContext *s, DisasOps *o) |
1546 | { | |
1547 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1548 | gen_helper_clfeb(o->out, cpu_env, o->in2, m3); | |
1549 | tcg_temp_free_i32(m3); | |
1550 | gen_set_cc_nz_f32(s, o->in2); | |
1551 | return NO_EXIT; | |
1552 | } | |
1553 | ||
1554 | static ExitStatus op_clfdb(DisasContext *s, DisasOps *o) | |
1555 | { | |
1556 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1557 | gen_helper_clfdb(o->out, cpu_env, o->in2, m3); | |
1558 | tcg_temp_free_i32(m3); | |
1559 | gen_set_cc_nz_f64(s, o->in2); | |
1560 | return NO_EXIT; | |
1561 | } | |
1562 | ||
1563 | static ExitStatus op_clfxb(DisasContext *s, DisasOps *o) | |
1564 | { | |
1565 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1566 | gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m3); | |
1567 | tcg_temp_free_i32(m3); | |
1568 | gen_set_cc_nz_f128(s, o->in1, o->in2); | |
1569 | return NO_EXIT; | |
1570 | } | |
1571 | ||
1572 | static ExitStatus op_clgeb(DisasContext *s, DisasOps *o) | |
1573 | { | |
1574 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1575 | gen_helper_clgeb(o->out, cpu_env, o->in2, m3); | |
1576 | tcg_temp_free_i32(m3); | |
1577 | gen_set_cc_nz_f32(s, o->in2); | |
1578 | return NO_EXIT; | |
1579 | } | |
1580 | ||
1581 | static ExitStatus op_clgdb(DisasContext *s, DisasOps *o) | |
1582 | { | |
1583 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1584 | gen_helper_clgdb(o->out, cpu_env, o->in2, m3); | |
1585 | tcg_temp_free_i32(m3); | |
1586 | gen_set_cc_nz_f64(s, o->in2); | |
1587 | return NO_EXIT; | |
1588 | } | |
1589 | ||
1590 | static ExitStatus op_clgxb(DisasContext *s, DisasOps *o) | |
1591 | { | |
1592 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1593 | gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m3); | |
1594 | tcg_temp_free_i32(m3); | |
1595 | gen_set_cc_nz_f128(s, o->in1, o->in2); | |
1596 | return NO_EXIT; | |
1597 | } | |
1598 | ||
683bb9a8 RH |
1599 | static ExitStatus op_cegb(DisasContext *s, DisasOps *o) |
1600 | { | |
1601 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1602 | gen_helper_cegb(o->out, cpu_env, o->in2, m3); | |
1603 | tcg_temp_free_i32(m3); | |
1604 | return NO_EXIT; | |
1605 | } | |
1606 | ||
1607 | static ExitStatus op_cdgb(DisasContext *s, DisasOps *o) | |
1608 | { | |
1609 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1610 | gen_helper_cdgb(o->out, cpu_env, o->in2, m3); | |
1611 | tcg_temp_free_i32(m3); | |
1612 | return NO_EXIT; | |
1613 | } | |
1614 | ||
1615 | static ExitStatus op_cxgb(DisasContext *s, DisasOps *o) | |
1616 | { | |
1617 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1618 | gen_helper_cxgb(o->out, cpu_env, o->in2, m3); | |
1619 | tcg_temp_free_i32(m3); | |
2112bf1b RH |
1620 | return_low128(o->out2); |
1621 | return NO_EXIT; | |
1622 | } | |
1623 | ||
1624 | static ExitStatus op_celgb(DisasContext *s, DisasOps *o) | |
1625 | { | |
1626 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1627 | gen_helper_celgb(o->out, cpu_env, o->in2, m3); | |
1628 | tcg_temp_free_i32(m3); | |
1629 | return NO_EXIT; | |
1630 | } | |
1631 | ||
1632 | static ExitStatus op_cdlgb(DisasContext *s, DisasOps *o) | |
1633 | { | |
1634 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1635 | gen_helper_cdlgb(o->out, cpu_env, o->in2, m3); | |
1636 | tcg_temp_free_i32(m3); | |
1637 | return NO_EXIT; | |
1638 | } | |
1639 | ||
1640 | static ExitStatus op_cxlgb(DisasContext *s, DisasOps *o) | |
1641 | { | |
1642 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1643 | gen_helper_cxlgb(o->out, cpu_env, o->in2, m3); | |
1644 | tcg_temp_free_i32(m3); | |
683bb9a8 RH |
1645 | return_low128(o->out2); |
1646 | return NO_EXIT; | |
1647 | } | |
1648 | ||
374724f9 RH |
1649 | static ExitStatus op_cksm(DisasContext *s, DisasOps *o) |
1650 | { | |
1651 | int r2 = get_field(s->fields, r2); | |
1652 | TCGv_i64 len = tcg_temp_new_i64(); | |
1653 | ||
1654 | potential_page_fault(s); | |
1655 | gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]); | |
1656 | set_cc_static(s); | |
1657 | return_low128(o->out); | |
1658 | ||
1659 | tcg_gen_add_i64(regs[r2], regs[r2], len); | |
1660 | tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len); | |
1661 | tcg_temp_free_i64(len); | |
1662 | ||
1663 | return NO_EXIT; | |
1664 | } | |
1665 | ||
4f7403d5 RH |
1666 | static ExitStatus op_clc(DisasContext *s, DisasOps *o) |
1667 | { | |
1668 | int l = get_field(s->fields, l1); | |
1669 | TCGv_i32 vl; | |
1670 | ||
1671 | switch (l + 1) { | |
1672 | case 1: | |
1673 | tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s)); | |
1674 | tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s)); | |
1675 | break; | |
1676 | case 2: | |
1677 | tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s)); | |
1678 | tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s)); | |
1679 | break; | |
1680 | case 4: | |
1681 | tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s)); | |
1682 | tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s)); | |
1683 | break; | |
1684 | case 8: | |
1685 | tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s)); | |
1686 | tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s)); | |
1687 | break; | |
1688 | default: | |
1689 | potential_page_fault(s); | |
1690 | vl = tcg_const_i32(l); | |
1691 | gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2); | |
1692 | tcg_temp_free_i32(vl); | |
1693 | set_cc_static(s); | |
1694 | return NO_EXIT; | |
1695 | } | |
1696 | gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst); | |
1697 | return NO_EXIT; | |
1698 | } | |
1699 | ||
eb66e6a9 RH |
1700 | static ExitStatus op_clcle(DisasContext *s, DisasOps *o) |
1701 | { | |
1702 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
1703 | TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); | |
1704 | potential_page_fault(s); | |
1705 | gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3); | |
1706 | tcg_temp_free_i32(r1); | |
1707 | tcg_temp_free_i32(r3); | |
1708 | set_cc_static(s); | |
1709 | return NO_EXIT; | |
1710 | } | |
1711 | ||
32a44d58 RH |
1712 | static ExitStatus op_clm(DisasContext *s, DisasOps *o) |
1713 | { | |
1714 | TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3)); | |
1715 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1716 | tcg_gen_trunc_i64_i32(t1, o->in1); | |
1717 | potential_page_fault(s); | |
1718 | gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2); | |
1719 | set_cc_static(s); | |
1720 | tcg_temp_free_i32(t1); | |
1721 | tcg_temp_free_i32(m3); | |
1722 | return NO_EXIT; | |
1723 | } | |
1724 | ||
aa31bf60 RH |
1725 | static ExitStatus op_clst(DisasContext *s, DisasOps *o) |
1726 | { | |
1727 | potential_page_fault(s); | |
1728 | gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2); | |
1729 | set_cc_static(s); | |
1730 | return_low128(o->in2); | |
1731 | return NO_EXIT; | |
1732 | } | |
1733 | ||
2db014b5 RH |
1734 | static ExitStatus op_cps(DisasContext *s, DisasOps *o) |
1735 | { | |
1736 | TCGv_i64 t = tcg_temp_new_i64(); | |
1737 | tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull); | |
1738 | tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull); | |
1739 | tcg_gen_or_i64(o->out, o->out, t); | |
1740 | tcg_temp_free_i64(t); | |
1741 | return NO_EXIT; | |
1742 | } | |
1743 | ||
f3de39c4 RH |
1744 | static ExitStatus op_cs(DisasContext *s, DisasOps *o) |
1745 | { | |
1746 | int r3 = get_field(s->fields, r3); | |
1747 | potential_page_fault(s); | |
1748 | gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]); | |
1749 | set_cc_static(s); | |
1750 | return NO_EXIT; | |
1751 | } | |
1752 | ||
1753 | static ExitStatus op_csg(DisasContext *s, DisasOps *o) | |
1754 | { | |
1755 | int r3 = get_field(s->fields, r3); | |
1756 | potential_page_fault(s); | |
1757 | gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]); | |
1758 | set_cc_static(s); | |
1759 | return NO_EXIT; | |
1760 | } | |
1761 | ||
3d596f49 RH |
1762 | #ifndef CONFIG_USER_ONLY |
1763 | static ExitStatus op_csp(DisasContext *s, DisasOps *o) | |
1764 | { | |
1765 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
1766 | check_privileged(s); | |
1767 | gen_helper_csp(cc_op, cpu_env, r1, o->in2); | |
1768 | tcg_temp_free_i32(r1); | |
1769 | set_cc_static(s); | |
1770 | return NO_EXIT; | |
1771 | } | |
1772 | #endif | |
1773 | ||
f3de39c4 RH |
1774 | static ExitStatus op_cds(DisasContext *s, DisasOps *o) |
1775 | { | |
1776 | int r3 = get_field(s->fields, r3); | |
1777 | TCGv_i64 in3 = tcg_temp_new_i64(); | |
1778 | tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32); | |
1779 | potential_page_fault(s); | |
1780 | gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3); | |
1781 | tcg_temp_free_i64(in3); | |
1782 | set_cc_static(s); | |
1783 | return NO_EXIT; | |
1784 | } | |
1785 | ||
1786 | static ExitStatus op_cdsg(DisasContext *s, DisasOps *o) | |
1787 | { | |
1788 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
1789 | TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); | |
1790 | potential_page_fault(s); | |
1791 | /* XXX rewrite in tcg */ | |
1792 | gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3); | |
1793 | set_cc_static(s); | |
1794 | return NO_EXIT; | |
1795 | } | |
1796 | ||
c49daa51 RH |
1797 | static ExitStatus op_cvd(DisasContext *s, DisasOps *o) |
1798 | { | |
1799 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1800 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1801 | tcg_gen_trunc_i64_i32(t2, o->in1); | |
1802 | gen_helper_cvd(t1, t2); | |
1803 | tcg_temp_free_i32(t2); | |
1804 | tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s)); | |
1805 | tcg_temp_free_i64(t1); | |
1806 | return NO_EXIT; | |
1807 | } | |
1808 | ||
1c268751 RH |
1809 | static ExitStatus op_ct(DisasContext *s, DisasOps *o) |
1810 | { | |
1811 | int m3 = get_field(s->fields, m3); | |
1812 | int lab = gen_new_label(); | |
1813 | TCGv_i32 t; | |
1814 | TCGCond c; | |
1815 | ||
1816 | /* Bit 3 of the m3 field is reserved and should be zero. | |
1817 | Choose to ignore it wrt the ltgt_cond table above. */ | |
1818 | c = tcg_invert_cond(ltgt_cond[m3 & 14]); | |
1819 | if (s->insn->data) { | |
1820 | c = tcg_unsigned_cond(c); | |
1821 | } | |
1822 | tcg_gen_brcond_i64(c, o->in1, o->in2, lab); | |
1823 | ||
1824 | /* Set DXC to 0xff. */ | |
1825 | t = tcg_temp_new_i32(); | |
1826 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUS390XState, fpc)); | |
1827 | tcg_gen_ori_i32(t, t, 0xff00); | |
1828 | tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, fpc)); | |
1829 | tcg_temp_free_i32(t); | |
1830 | ||
1831 | /* Trap. */ | |
1832 | gen_program_exception(s, PGM_DATA); | |
1833 | ||
1834 | gen_set_label(lab); | |
1835 | return NO_EXIT; | |
1836 | } | |
1837 | ||
972e35b9 RH |
1838 | #ifndef CONFIG_USER_ONLY |
1839 | static ExitStatus op_diag(DisasContext *s, DisasOps *o) | |
1840 | { | |
1841 | TCGv_i32 tmp; | |
1842 | ||
1843 | check_privileged(s); | |
1844 | potential_page_fault(s); | |
1845 | ||
1846 | /* We pretend the format is RX_a so that D2 is the field we want. */ | |
1847 | tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff); | |
1848 | gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]); | |
1849 | tcg_temp_free_i32(tmp); | |
1850 | return NO_EXIT; | |
1851 | } | |
1852 | #endif | |
1853 | ||
891452e5 RH |
1854 | static ExitStatus op_divs32(DisasContext *s, DisasOps *o) |
1855 | { | |
1856 | gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2); | |
1857 | return_low128(o->out); | |
1858 | return NO_EXIT; | |
1859 | } | |
1860 | ||
1861 | static ExitStatus op_divu32(DisasContext *s, DisasOps *o) | |
1862 | { | |
1863 | gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2); | |
1864 | return_low128(o->out); | |
1865 | return NO_EXIT; | |
1866 | } | |
1867 | ||
1868 | static ExitStatus op_divs64(DisasContext *s, DisasOps *o) | |
1869 | { | |
1870 | gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2); | |
1871 | return_low128(o->out); | |
1872 | return NO_EXIT; | |
1873 | } | |
1874 | ||
1875 | static ExitStatus op_divu64(DisasContext *s, DisasOps *o) | |
1876 | { | |
1877 | gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2); | |
1878 | return_low128(o->out); | |
1879 | return NO_EXIT; | |
1880 | } | |
1881 | ||
f08a5c31 RH |
1882 | static ExitStatus op_deb(DisasContext *s, DisasOps *o) |
1883 | { | |
1884 | gen_helper_deb(o->out, cpu_env, o->in1, o->in2); | |
1885 | return NO_EXIT; | |
1886 | } | |
1887 | ||
1888 | static ExitStatus op_ddb(DisasContext *s, DisasOps *o) | |
1889 | { | |
1890 | gen_helper_ddb(o->out, cpu_env, o->in1, o->in2); | |
1891 | return NO_EXIT; | |
1892 | } | |
1893 | ||
1894 | static ExitStatus op_dxb(DisasContext *s, DisasOps *o) | |
1895 | { | |
1896 | gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); | |
1897 | return_low128(o->out2); | |
1898 | return NO_EXIT; | |
1899 | } | |
1900 | ||
d62a4c97 RH |
1901 | static ExitStatus op_ear(DisasContext *s, DisasOps *o) |
1902 | { | |
1903 | int r2 = get_field(s->fields, r2); | |
1904 | tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2])); | |
1905 | return NO_EXIT; | |
1906 | } | |
1907 | ||
ea20490f RH |
1908 | static ExitStatus op_efpc(DisasContext *s, DisasOps *o) |
1909 | { | |
1910 | tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc)); | |
1911 | return NO_EXIT; | |
1912 | } | |
1913 | ||
6e764e97 RH |
1914 | static ExitStatus op_ex(DisasContext *s, DisasOps *o) |
1915 | { | |
1916 | /* ??? Perhaps a better way to implement EXECUTE is to set a bit in | |
1917 | tb->flags, (ab)use the tb->cs_base field as the address of | |
1918 | the template in memory, and grab 8 bits of tb->flags/cflags for | |
1919 | the contents of the register. We would then recognize all this | |
1920 | in gen_intermediate_code_internal, generating code for exactly | |
1921 | one instruction. This new TB then gets executed normally. | |
1922 | ||
1923 | On the other hand, this seems to be mostly used for modifying | |
1924 | MVC inside of memcpy, which needs a helper call anyway. So | |
1925 | perhaps this doesn't bear thinking about any further. */ | |
1926 | ||
1927 | TCGv_i64 tmp; | |
1928 | ||
1929 | update_psw_addr(s); | |
7a6c7067 | 1930 | update_cc_op(s); |
6e764e97 RH |
1931 | |
1932 | tmp = tcg_const_i64(s->next_pc); | |
1933 | gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp); | |
1934 | tcg_temp_free_i64(tmp); | |
1935 | ||
1936 | set_cc_static(s); | |
1937 | return NO_EXIT; | |
1938 | } | |
1939 | ||
102bf2c6 RH |
1940 | static ExitStatus op_flogr(DisasContext *s, DisasOps *o) |
1941 | { | |
1942 | /* We'll use the original input for cc computation, since we get to | |
1943 | compare that against 0, which ought to be better than comparing | |
1944 | the real output against 64. It also lets cc_dst be a convenient | |
1945 | temporary during our computation. */ | |
1946 | gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2); | |
1947 | ||
1948 | /* R1 = IN ? CLZ(IN) : 64. */ | |
1949 | gen_helper_clz(o->out, o->in2); | |
1950 | ||
1951 | /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this | |
1952 | value by 64, which is undefined. But since the shift is 64 iff the | |
1953 | input is zero, we still get the correct result after and'ing. */ | |
1954 | tcg_gen_movi_i64(o->out2, 0x8000000000000000ull); | |
1955 | tcg_gen_shr_i64(o->out2, o->out2, o->out); | |
1956 | tcg_gen_andc_i64(o->out2, cc_dst, o->out2); | |
1957 | return NO_EXIT; | |
1958 | } | |
1959 | ||
58a9e35b RH |
1960 | static ExitStatus op_icm(DisasContext *s, DisasOps *o) |
1961 | { | |
1962 | int m3 = get_field(s->fields, m3); | |
1963 | int pos, len, base = s->insn->data; | |
1964 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
1965 | uint64_t ccm; | |
1966 | ||
1967 | switch (m3) { | |
1968 | case 0xf: | |
1969 | /* Effectively a 32-bit load. */ | |
1970 | tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s)); | |
1971 | len = 32; | |
1972 | goto one_insert; | |
1973 | ||
1974 | case 0xc: | |
1975 | case 0x6: | |
1976 | case 0x3: | |
1977 | /* Effectively a 16-bit load. */ | |
1978 | tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s)); | |
1979 | len = 16; | |
1980 | goto one_insert; | |
1981 | ||
1982 | case 0x8: | |
1983 | case 0x4: | |
1984 | case 0x2: | |
1985 | case 0x1: | |
1986 | /* Effectively an 8-bit load. */ | |
1987 | tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s)); | |
1988 | len = 8; | |
1989 | goto one_insert; | |
1990 | ||
1991 | one_insert: | |
1992 | pos = base + ctz32(m3) * 8; | |
1993 | tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len); | |
1994 | ccm = ((1ull << len) - 1) << pos; | |
1995 | break; | |
1996 | ||
1997 | default: | |
1998 | /* This is going to be a sequence of loads and inserts. */ | |
1999 | pos = base + 32 - 8; | |
2000 | ccm = 0; | |
2001 | while (m3) { | |
2002 | if (m3 & 0x8) { | |
2003 | tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s)); | |
2004 | tcg_gen_addi_i64(o->in2, o->in2, 1); | |
2005 | tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8); | |
2006 | ccm |= 0xff << pos; | |
2007 | } | |
2008 | m3 = (m3 << 1) & 0xf; | |
2009 | pos -= 8; | |
2010 | } | |
2011 | break; | |
2012 | } | |
2013 | ||
2014 | tcg_gen_movi_i64(tmp, ccm); | |
2015 | gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out); | |
2016 | tcg_temp_free_i64(tmp); | |
2017 | return NO_EXIT; | |
2018 | } | |
2019 | ||
facfc864 RH |
2020 | static ExitStatus op_insi(DisasContext *s, DisasOps *o) |
2021 | { | |
2022 | int shift = s->insn->data & 0xff; | |
2023 | int size = s->insn->data >> 8; | |
2024 | tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size); | |
2025 | return NO_EXIT; | |
2026 | } | |
2027 | ||
6e2704e7 RH |
2028 | static ExitStatus op_ipm(DisasContext *s, DisasOps *o) |
2029 | { | |
2030 | TCGv_i64 t1; | |
2031 | ||
2032 | gen_op_calc_cc(s); | |
2033 | tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull); | |
2034 | ||
2035 | t1 = tcg_temp_new_i64(); | |
2036 | tcg_gen_shli_i64(t1, psw_mask, 20); | |
2037 | tcg_gen_shri_i64(t1, t1, 36); | |
2038 | tcg_gen_or_i64(o->out, o->out, t1); | |
2039 | ||
2040 | tcg_gen_extu_i32_i64(t1, cc_op); | |
2041 | tcg_gen_shli_i64(t1, t1, 28); | |
2042 | tcg_gen_or_i64(o->out, o->out, t1); | |
2043 | tcg_temp_free_i64(t1); | |
2044 | return NO_EXIT; | |
2045 | } | |
2046 | ||
cfef53e3 RH |
2047 | #ifndef CONFIG_USER_ONLY |
2048 | static ExitStatus op_ipte(DisasContext *s, DisasOps *o) | |
2049 | { | |
2050 | check_privileged(s); | |
2051 | gen_helper_ipte(cpu_env, o->in1, o->in2); | |
2052 | return NO_EXIT; | |
2053 | } | |
8026417c RH |
2054 | |
2055 | static ExitStatus op_iske(DisasContext *s, DisasOps *o) | |
2056 | { | |
2057 | check_privileged(s); | |
2058 | gen_helper_iske(o->out, cpu_env, o->in2); | |
2059 | return NO_EXIT; | |
2060 | } | |
cfef53e3 RH |
2061 | #endif |
2062 | ||
587626f8 RH |
2063 | static ExitStatus op_ldeb(DisasContext *s, DisasOps *o) |
2064 | { | |
2065 | gen_helper_ldeb(o->out, cpu_env, o->in2); | |
2066 | return NO_EXIT; | |
2067 | } | |
2068 | ||
2069 | static ExitStatus op_ledb(DisasContext *s, DisasOps *o) | |
2070 | { | |
2071 | gen_helper_ledb(o->out, cpu_env, o->in2); | |
2072 | return NO_EXIT; | |
2073 | } | |
2074 | ||
2075 | static ExitStatus op_ldxb(DisasContext *s, DisasOps *o) | |
2076 | { | |
2077 | gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2); | |
2078 | return NO_EXIT; | |
2079 | } | |
2080 | ||
2081 | static ExitStatus op_lexb(DisasContext *s, DisasOps *o) | |
2082 | { | |
2083 | gen_helper_lexb(o->out, cpu_env, o->in1, o->in2); | |
2084 | return NO_EXIT; | |
2085 | } | |
2086 | ||
2087 | static ExitStatus op_lxdb(DisasContext *s, DisasOps *o) | |
2088 | { | |
2089 | gen_helper_lxdb(o->out, cpu_env, o->in2); | |
2090 | return_low128(o->out2); | |
2091 | return NO_EXIT; | |
2092 | } | |
2093 | ||
2094 | static ExitStatus op_lxeb(DisasContext *s, DisasOps *o) | |
2095 | { | |
2096 | gen_helper_lxeb(o->out, cpu_env, o->in2); | |
2097 | return_low128(o->out2); | |
2098 | return NO_EXIT; | |
2099 | } | |
2100 | ||
7691c23b RH |
2101 | static ExitStatus op_llgt(DisasContext *s, DisasOps *o) |
2102 | { | |
2103 | tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff); | |
2104 | return NO_EXIT; | |
2105 | } | |
2106 | ||
c698d876 RH |
2107 | static ExitStatus op_ld8s(DisasContext *s, DisasOps *o) |
2108 | { | |
2109 | tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s)); | |
2110 | return NO_EXIT; | |
2111 | } | |
2112 | ||
2113 | static ExitStatus op_ld8u(DisasContext *s, DisasOps *o) | |
2114 | { | |
2115 | tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s)); | |
2116 | return NO_EXIT; | |
2117 | } | |
2118 | ||
2119 | static ExitStatus op_ld16s(DisasContext *s, DisasOps *o) | |
2120 | { | |
2121 | tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s)); | |
2122 | return NO_EXIT; | |
2123 | } | |
2124 | ||
2125 | static ExitStatus op_ld16u(DisasContext *s, DisasOps *o) | |
2126 | { | |
2127 | tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s)); | |
2128 | return NO_EXIT; | |
2129 | } | |
2130 | ||
22c37a08 RH |
2131 | static ExitStatus op_ld32s(DisasContext *s, DisasOps *o) |
2132 | { | |
2133 | tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s)); | |
2134 | return NO_EXIT; | |
2135 | } | |
2136 | ||
2137 | static ExitStatus op_ld32u(DisasContext *s, DisasOps *o) | |
2138 | { | |
2139 | tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s)); | |
2140 | return NO_EXIT; | |
2141 | } | |
2142 | ||
2143 | static ExitStatus op_ld64(DisasContext *s, DisasOps *o) | |
2144 | { | |
2145 | tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s)); | |
2146 | return NO_EXIT; | |
2147 | } | |
2148 | ||
632086da RH |
2149 | static ExitStatus op_loc(DisasContext *s, DisasOps *o) |
2150 | { | |
2151 | DisasCompare c; | |
2152 | ||
2153 | disas_jcc(s, &c, get_field(s->fields, m3)); | |
2154 | ||
2155 | if (c.is_64) { | |
2156 | tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b, | |
2157 | o->in2, o->in1); | |
2158 | free_compare(&c); | |
2159 | } else { | |
2160 | TCGv_i32 t32 = tcg_temp_new_i32(); | |
2161 | TCGv_i64 t, z; | |
2162 | ||
2163 | tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b); | |
2164 | free_compare(&c); | |
2165 | ||
2166 | t = tcg_temp_new_i64(); | |
2167 | tcg_gen_extu_i32_i64(t, t32); | |
2168 | tcg_temp_free_i32(t32); | |
2169 | ||
2170 | z = tcg_const_i64(0); | |
2171 | tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1); | |
2172 | tcg_temp_free_i64(t); | |
2173 | tcg_temp_free_i64(z); | |
2174 | } | |
2175 | ||
2176 | return NO_EXIT; | |
2177 | } | |
2178 | ||
8b5ff571 | 2179 | #ifndef CONFIG_USER_ONLY |
504488b8 RH |
2180 | static ExitStatus op_lctl(DisasContext *s, DisasOps *o) |
2181 | { | |
2182 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
2183 | TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); | |
2184 | check_privileged(s); | |
2185 | potential_page_fault(s); | |
2186 | gen_helper_lctl(cpu_env, r1, o->in2, r3); | |
2187 | tcg_temp_free_i32(r1); | |
2188 | tcg_temp_free_i32(r3); | |
2189 | return NO_EXIT; | |
2190 | } | |
2191 | ||
3e398cf9 RH |
2192 | static ExitStatus op_lctlg(DisasContext *s, DisasOps *o) |
2193 | { | |
2194 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
2195 | TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); | |
2196 | check_privileged(s); | |
2197 | potential_page_fault(s); | |
2198 | gen_helper_lctlg(cpu_env, r1, o->in2, r3); | |
2199 | tcg_temp_free_i32(r1); | |
2200 | tcg_temp_free_i32(r3); | |
2201 | return NO_EXIT; | |
2202 | } | |
d8fe4a9c RH |
2203 | static ExitStatus op_lra(DisasContext *s, DisasOps *o) |
2204 | { | |
2205 | check_privileged(s); | |
2206 | potential_page_fault(s); | |
2207 | gen_helper_lra(o->out, cpu_env, o->in2); | |
2208 | set_cc_static(s); | |
2209 | return NO_EXIT; | |
2210 | } | |
2211 | ||
8b5ff571 RH |
2212 | static ExitStatus op_lpsw(DisasContext *s, DisasOps *o) |
2213 | { | |
2214 | TCGv_i64 t1, t2; | |
2215 | ||
2216 | check_privileged(s); | |
2217 | ||
2218 | t1 = tcg_temp_new_i64(); | |
2219 | t2 = tcg_temp_new_i64(); | |
2220 | tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); | |
2221 | tcg_gen_addi_i64(o->in2, o->in2, 4); | |
2222 | tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s)); | |
2223 | /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */ | |
2224 | tcg_gen_shli_i64(t1, t1, 32); | |
2225 | gen_helper_load_psw(cpu_env, t1, t2); | |
2226 | tcg_temp_free_i64(t1); | |
2227 | tcg_temp_free_i64(t2); | |
2228 | return EXIT_NORETURN; | |
2229 | } | |
7ab938d7 RH |
2230 | |
2231 | static ExitStatus op_lpswe(DisasContext *s, DisasOps *o) | |
2232 | { | |
2233 | TCGv_i64 t1, t2; | |
2234 | ||
2235 | check_privileged(s); | |
2236 | ||
2237 | t1 = tcg_temp_new_i64(); | |
2238 | t2 = tcg_temp_new_i64(); | |
2239 | tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s)); | |
2240 | tcg_gen_addi_i64(o->in2, o->in2, 8); | |
2241 | tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s)); | |
2242 | gen_helper_load_psw(cpu_env, t1, t2); | |
2243 | tcg_temp_free_i64(t1); | |
2244 | tcg_temp_free_i64(t2); | |
2245 | return EXIT_NORETURN; | |
2246 | } | |
8b5ff571 RH |
2247 | #endif |
2248 | ||
7df3e93a RH |
2249 | static ExitStatus op_lam(DisasContext *s, DisasOps *o) |
2250 | { | |
2251 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
2252 | TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); | |
2253 | potential_page_fault(s); | |
2254 | gen_helper_lam(cpu_env, r1, o->in2, r3); | |
2255 | tcg_temp_free_i32(r1); | |
2256 | tcg_temp_free_i32(r3); | |
2257 | return NO_EXIT; | |
2258 | } | |
2259 | ||
77f8d6c3 RH |
2260 | static ExitStatus op_lm32(DisasContext *s, DisasOps *o) |
2261 | { | |
2262 | int r1 = get_field(s->fields, r1); | |
2263 | int r3 = get_field(s->fields, r3); | |
2264 | TCGv_i64 t = tcg_temp_new_i64(); | |
2265 | TCGv_i64 t4 = tcg_const_i64(4); | |
2266 | ||
2267 | while (1) { | |
2268 | tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s)); | |
2269 | store_reg32_i64(r1, t); | |
2270 | if (r1 == r3) { | |
2271 | break; | |
2272 | } | |
2273 | tcg_gen_add_i64(o->in2, o->in2, t4); | |
2274 | r1 = (r1 + 1) & 15; | |
2275 | } | |
2276 | ||
2277 | tcg_temp_free_i64(t); | |
2278 | tcg_temp_free_i64(t4); | |
2279 | return NO_EXIT; | |
2280 | } | |
2281 | ||
2282 | static ExitStatus op_lmh(DisasContext *s, DisasOps *o) | |
2283 | { | |
2284 | int r1 = get_field(s->fields, r1); | |
2285 | int r3 = get_field(s->fields, r3); | |
2286 | TCGv_i64 t = tcg_temp_new_i64(); | |
2287 | TCGv_i64 t4 = tcg_const_i64(4); | |
2288 | ||
2289 | while (1) { | |
2290 | tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s)); | |
2291 | store_reg32h_i64(r1, t); | |
2292 | if (r1 == r3) { | |
2293 | break; | |
2294 | } | |
2295 | tcg_gen_add_i64(o->in2, o->in2, t4); | |
2296 | r1 = (r1 + 1) & 15; | |
2297 | } | |
2298 | ||
2299 | tcg_temp_free_i64(t); | |
2300 | tcg_temp_free_i64(t4); | |
2301 | return NO_EXIT; | |
2302 | } | |
2303 | ||
2304 | static ExitStatus op_lm64(DisasContext *s, DisasOps *o) | |
2305 | { | |
2306 | int r1 = get_field(s->fields, r1); | |
2307 | int r3 = get_field(s->fields, r3); | |
2308 | TCGv_i64 t8 = tcg_const_i64(8); | |
2309 | ||
2310 | while (1) { | |
2311 | tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s)); | |
2312 | if (r1 == r3) { | |
2313 | break; | |
2314 | } | |
2315 | tcg_gen_add_i64(o->in2, o->in2, t8); | |
2316 | r1 = (r1 + 1) & 15; | |
2317 | } | |
2318 | ||
2319 | tcg_temp_free_i64(t8); | |
2320 | return NO_EXIT; | |
2321 | } | |
2322 | ||
22c37a08 RH |
2323 | static ExitStatus op_mov2(DisasContext *s, DisasOps *o) |
2324 | { | |
2325 | o->out = o->in2; | |
2326 | o->g_out = o->g_in2; | |
2327 | TCGV_UNUSED_I64(o->in2); | |
2328 | o->g_in2 = false; | |
2329 | return NO_EXIT; | |
2330 | } | |
2331 | ||
d764a8d1 RH |
2332 | static ExitStatus op_movx(DisasContext *s, DisasOps *o) |
2333 | { | |
2334 | o->out = o->in1; | |
2335 | o->out2 = o->in2; | |
2336 | o->g_out = o->g_in1; | |
2337 | o->g_out2 = o->g_in2; | |
2338 | TCGV_UNUSED_I64(o->in1); | |
2339 | TCGV_UNUSED_I64(o->in2); | |
2340 | o->g_in1 = o->g_in2 = false; | |
2341 | return NO_EXIT; | |
2342 | } | |
2343 | ||
af9e5a04 RH |
2344 | static ExitStatus op_mvc(DisasContext *s, DisasOps *o) |
2345 | { | |
2346 | TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); | |
2347 | potential_page_fault(s); | |
2348 | gen_helper_mvc(cpu_env, l, o->addr1, o->in2); | |
2349 | tcg_temp_free_i32(l); | |
2350 | return NO_EXIT; | |
2351 | } | |
2352 | ||
e1eaada9 RH |
2353 | static ExitStatus op_mvcl(DisasContext *s, DisasOps *o) |
2354 | { | |
2355 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
2356 | TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2)); | |
2357 | potential_page_fault(s); | |
2358 | gen_helper_mvcl(cc_op, cpu_env, r1, r2); | |
2359 | tcg_temp_free_i32(r1); | |
2360 | tcg_temp_free_i32(r2); | |
2361 | set_cc_static(s); | |
2362 | return NO_EXIT; | |
2363 | } | |
2364 | ||
eb66e6a9 RH |
2365 | static ExitStatus op_mvcle(DisasContext *s, DisasOps *o) |
2366 | { | |
2367 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
2368 | TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); | |
2369 | potential_page_fault(s); | |
2370 | gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3); | |
2371 | tcg_temp_free_i32(r1); | |
2372 | tcg_temp_free_i32(r3); | |
2373 | set_cc_static(s); | |
2374 | return NO_EXIT; | |
2375 | } | |
2376 | ||
97c3ab61 RH |
2377 | #ifndef CONFIG_USER_ONLY |
2378 | static ExitStatus op_mvcp(DisasContext *s, DisasOps *o) | |
2379 | { | |
2380 | int r1 = get_field(s->fields, l1); | |
2381 | check_privileged(s); | |
2382 | potential_page_fault(s); | |
2383 | gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2); | |
2384 | set_cc_static(s); | |
2385 | return NO_EXIT; | |
2386 | } | |
2387 | ||
2388 | static ExitStatus op_mvcs(DisasContext *s, DisasOps *o) | |
2389 | { | |
2390 | int r1 = get_field(s->fields, l1); | |
2391 | check_privileged(s); | |
2392 | potential_page_fault(s); | |
2393 | gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2); | |
2394 | set_cc_static(s); | |
2395 | return NO_EXIT; | |
2396 | } | |
2397 | #endif | |
2398 | ||
ee6c38d5 RH |
2399 | static ExitStatus op_mvpg(DisasContext *s, DisasOps *o) |
2400 | { | |
2401 | potential_page_fault(s); | |
2402 | gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2); | |
2403 | set_cc_static(s); | |
2404 | return NO_EXIT; | |
2405 | } | |
2406 | ||
aa31bf60 RH |
2407 | static ExitStatus op_mvst(DisasContext *s, DisasOps *o) |
2408 | { | |
2409 | potential_page_fault(s); | |
2410 | gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2); | |
2411 | set_cc_static(s); | |
2412 | return_low128(o->in2); | |
2413 | return NO_EXIT; | |
2414 | } | |
2415 | ||
d1c04a2b RH |
2416 | static ExitStatus op_mul(DisasContext *s, DisasOps *o) |
2417 | { | |
2418 | tcg_gen_mul_i64(o->out, o->in1, o->in2); | |
2419 | return NO_EXIT; | |
2420 | } | |
2421 | ||
1ac5889f RH |
2422 | static ExitStatus op_mul128(DisasContext *s, DisasOps *o) |
2423 | { | |
2424 | gen_helper_mul128(o->out, cpu_env, o->in1, o->in2); | |
2425 | return_low128(o->out2); | |
2426 | return NO_EXIT; | |
2427 | } | |
2428 | ||
83b00736 RH |
2429 | static ExitStatus op_meeb(DisasContext *s, DisasOps *o) |
2430 | { | |
2431 | gen_helper_meeb(o->out, cpu_env, o->in1, o->in2); | |
2432 | return NO_EXIT; | |
2433 | } | |
2434 | ||
2435 | static ExitStatus op_mdeb(DisasContext *s, DisasOps *o) | |
2436 | { | |
2437 | gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2); | |
2438 | return NO_EXIT; | |
2439 | } | |
2440 | ||
2441 | static ExitStatus op_mdb(DisasContext *s, DisasOps *o) | |
2442 | { | |
2443 | gen_helper_mdb(o->out, cpu_env, o->in1, o->in2); | |
2444 | return NO_EXIT; | |
2445 | } | |
2446 | ||
2447 | static ExitStatus op_mxb(DisasContext *s, DisasOps *o) | |
2448 | { | |
2449 | gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); | |
2450 | return_low128(o->out2); | |
2451 | return NO_EXIT; | |
2452 | } | |
2453 | ||
2454 | static ExitStatus op_mxdb(DisasContext *s, DisasOps *o) | |
2455 | { | |
2456 | gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2); | |
2457 | return_low128(o->out2); | |
2458 | return NO_EXIT; | |
2459 | } | |
2460 | ||
722bfec3 RH |
2461 | static ExitStatus op_maeb(DisasContext *s, DisasOps *o) |
2462 | { | |
2463 | TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3)); | |
2464 | gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3); | |
2465 | tcg_temp_free_i64(r3); | |
2466 | return NO_EXIT; | |
2467 | } | |
2468 | ||
2469 | static ExitStatus op_madb(DisasContext *s, DisasOps *o) | |
2470 | { | |
2471 | int r3 = get_field(s->fields, r3); | |
2472 | gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]); | |
2473 | return NO_EXIT; | |
2474 | } | |
2475 | ||
2476 | static ExitStatus op_mseb(DisasContext *s, DisasOps *o) | |
2477 | { | |
2478 | TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3)); | |
2479 | gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3); | |
2480 | tcg_temp_free_i64(r3); | |
2481 | return NO_EXIT; | |
2482 | } | |
2483 | ||
2484 | static ExitStatus op_msdb(DisasContext *s, DisasOps *o) | |
2485 | { | |
2486 | int r3 = get_field(s->fields, r3); | |
2487 | gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]); | |
2488 | return NO_EXIT; | |
2489 | } | |
2490 | ||
b9bca3e5 RH |
2491 | static ExitStatus op_nabs(DisasContext *s, DisasOps *o) |
2492 | { | |
2493 | gen_helper_nabs_i64(o->out, o->in2); | |
2494 | return NO_EXIT; | |
2495 | } | |
2496 | ||
5d7fd045 RH |
2497 | static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o) |
2498 | { | |
2499 | tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull); | |
2500 | return NO_EXIT; | |
2501 | } | |
2502 | ||
2503 | static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o) | |
2504 | { | |
2505 | tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull); | |
2506 | return NO_EXIT; | |
2507 | } | |
2508 | ||
2509 | static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o) | |
2510 | { | |
2511 | tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull); | |
2512 | tcg_gen_mov_i64(o->out2, o->in2); | |
2513 | return NO_EXIT; | |
2514 | } | |
2515 | ||
0a949039 RH |
2516 | static ExitStatus op_nc(DisasContext *s, DisasOps *o) |
2517 | { | |
2518 | TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); | |
2519 | potential_page_fault(s); | |
2520 | gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2); | |
2521 | tcg_temp_free_i32(l); | |
2522 | set_cc_static(s); | |
2523 | return NO_EXIT; | |
2524 | } | |
2525 | ||
b9bca3e5 RH |
2526 | static ExitStatus op_neg(DisasContext *s, DisasOps *o) |
2527 | { | |
2528 | tcg_gen_neg_i64(o->out, o->in2); | |
2529 | return NO_EXIT; | |
2530 | } | |
2531 | ||
5d7fd045 RH |
2532 | static ExitStatus op_negf32(DisasContext *s, DisasOps *o) |
2533 | { | |
2534 | tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull); | |
2535 | return NO_EXIT; | |
2536 | } | |
2537 | ||
2538 | static ExitStatus op_negf64(DisasContext *s, DisasOps *o) | |
2539 | { | |
2540 | tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull); | |
2541 | return NO_EXIT; | |
2542 | } | |
2543 | ||
2544 | static ExitStatus op_negf128(DisasContext *s, DisasOps *o) | |
2545 | { | |
2546 | tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull); | |
2547 | tcg_gen_mov_i64(o->out2, o->in2); | |
2548 | return NO_EXIT; | |
2549 | } | |
2550 | ||
0a949039 RH |
2551 | static ExitStatus op_oc(DisasContext *s, DisasOps *o) |
2552 | { | |
2553 | TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); | |
2554 | potential_page_fault(s); | |
2555 | gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2); | |
2556 | tcg_temp_free_i32(l); | |
2557 | set_cc_static(s); | |
2558 | return NO_EXIT; | |
2559 | } | |
2560 | ||
3bbfbd1f RH |
2561 | static ExitStatus op_or(DisasContext *s, DisasOps *o) |
2562 | { | |
2563 | tcg_gen_or_i64(o->out, o->in1, o->in2); | |
2564 | return NO_EXIT; | |
2565 | } | |
2566 | ||
facfc864 RH |
2567 | static ExitStatus op_ori(DisasContext *s, DisasOps *o) |
2568 | { | |
2569 | int shift = s->insn->data & 0xff; | |
2570 | int size = s->insn->data >> 8; | |
2571 | uint64_t mask = ((1ull << size) - 1) << shift; | |
2572 | ||
2573 | assert(!o->g_in2); | |
2574 | tcg_gen_shli_i64(o->in2, o->in2, shift); | |
2575 | tcg_gen_or_i64(o->out, o->in1, o->in2); | |
2576 | ||
2577 | /* Produce the CC from only the bits manipulated. */ | |
2578 | tcg_gen_andi_i64(cc_dst, o->out, mask); | |
2579 | set_cc_nz_u64(s, cc_dst); | |
2580 | return NO_EXIT; | |
2581 | } | |
2582 | ||
99b4f24b RH |
2583 | static ExitStatus op_popcnt(DisasContext *s, DisasOps *o) |
2584 | { | |
2585 | gen_helper_popcnt(o->out, o->in2); | |
2586 | return NO_EXIT; | |
2587 | } | |
2588 | ||
0568d8aa RH |
2589 | #ifndef CONFIG_USER_ONLY |
2590 | static ExitStatus op_ptlb(DisasContext *s, DisasOps *o) | |
2591 | { | |
2592 | check_privileged(s); | |
2593 | gen_helper_ptlb(cpu_env); | |
2594 | return NO_EXIT; | |
2595 | } | |
2596 | #endif | |
2597 | ||
2d6a8698 RH |
2598 | static ExitStatus op_risbg(DisasContext *s, DisasOps *o) |
2599 | { | |
2600 | int i3 = get_field(s->fields, i3); | |
2601 | int i4 = get_field(s->fields, i4); | |
2602 | int i5 = get_field(s->fields, i5); | |
2603 | int do_zero = i4 & 0x80; | |
2604 | uint64_t mask, imask, pmask; | |
2605 | int pos, len, rot; | |
2606 | ||
2607 | /* Adjust the arguments for the specific insn. */ | |
2608 | switch (s->fields->op2) { | |
2609 | case 0x55: /* risbg */ | |
2610 | i3 &= 63; | |
2611 | i4 &= 63; | |
2612 | pmask = ~0; | |
2613 | break; | |
2614 | case 0x5d: /* risbhg */ | |
2615 | i3 &= 31; | |
2616 | i4 &= 31; | |
2617 | pmask = 0xffffffff00000000ull; | |
2618 | break; | |
2619 | case 0x51: /* risblg */ | |
2620 | i3 &= 31; | |
2621 | i4 &= 31; | |
2622 | pmask = 0x00000000ffffffffull; | |
2623 | break; | |
2624 | default: | |
2625 | abort(); | |
2626 | } | |
2627 | ||
2628 | /* MASK is the set of bits to be inserted from R2. | |
2629 | Take care for I3/I4 wraparound. */ | |
2630 | mask = pmask >> i3; | |
2631 | if (i3 <= i4) { | |
2632 | mask ^= pmask >> i4 >> 1; | |
2633 | } else { | |
2634 | mask |= ~(pmask >> i4 >> 1); | |
2635 | } | |
2636 | mask &= pmask; | |
2637 | ||
2638 | /* IMASK is the set of bits to be kept from R1. In the case of the high/low | |
2639 | insns, we need to keep the other half of the register. */ | |
2640 | imask = ~mask | ~pmask; | |
2641 | if (do_zero) { | |
2642 | if (s->fields->op2 == 0x55) { | |
2643 | imask = 0; | |
2644 | } else { | |
2645 | imask = ~pmask; | |
2646 | } | |
2647 | } | |
2648 | ||
2649 | /* In some cases we can implement this with deposit, which can be more | |
2650 | efficient on some hosts. */ | |
2651 | if (~mask == imask && i3 <= i4) { | |
2652 | if (s->fields->op2 == 0x5d) { | |
2653 | i3 += 32, i4 += 32; | |
2654 | } | |
2655 | /* Note that we rotate the bits to be inserted to the lsb, not to | |
2656 | the position as described in the PoO. */ | |
2657 | len = i4 - i3 + 1; | |
2658 | pos = 63 - i4; | |
2659 | rot = (i5 - pos) & 63; | |
2660 | } else { | |
2661 | pos = len = -1; | |
2662 | rot = i5 & 63; | |
2663 | } | |
2664 | ||
2665 | /* Rotate the input as necessary. */ | |
2666 | tcg_gen_rotli_i64(o->in2, o->in2, rot); | |
2667 | ||
2668 | /* Insert the selected bits into the output. */ | |
2669 | if (pos >= 0) { | |
2670 | tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len); | |
2671 | } else if (imask == 0) { | |
2672 | tcg_gen_andi_i64(o->out, o->in2, mask); | |
2673 | } else { | |
2674 | tcg_gen_andi_i64(o->in2, o->in2, mask); | |
2675 | tcg_gen_andi_i64(o->out, o->out, imask); | |
2676 | tcg_gen_or_i64(o->out, o->out, o->in2); | |
2677 | } | |
2678 | return NO_EXIT; | |
d6c6372e RH |
2679 | } |
2680 | ||
2681 | static ExitStatus op_rosbg(DisasContext *s, DisasOps *o) | |
2682 | { | |
2683 | int i3 = get_field(s->fields, i3); | |
2684 | int i4 = get_field(s->fields, i4); | |
2685 | int i5 = get_field(s->fields, i5); | |
2686 | uint64_t mask; | |
2687 | ||
2688 | /* If this is a test-only form, arrange to discard the result. */ | |
2689 | if (i3 & 0x80) { | |
2690 | o->out = tcg_temp_new_i64(); | |
2691 | o->g_out = false; | |
2692 | } | |
2693 | ||
2694 | i3 &= 63; | |
2695 | i4 &= 63; | |
2696 | i5 &= 63; | |
2697 | ||
2698 | /* MASK is the set of bits to be operated on from R2. | |
2699 | Take care for I3/I4 wraparound. */ | |
2700 | mask = ~0ull >> i3; | |
2701 | if (i3 <= i4) { | |
2702 | mask ^= ~0ull >> i4 >> 1; | |
2703 | } else { | |
2704 | mask |= ~(~0ull >> i4 >> 1); | |
2705 | } | |
2706 | ||
2707 | /* Rotate the input as necessary. */ | |
2708 | tcg_gen_rotli_i64(o->in2, o->in2, i5); | |
2709 | ||
2710 | /* Operate. */ | |
2711 | switch (s->fields->op2) { | |
2712 | case 0x55: /* AND */ | |
2713 | tcg_gen_ori_i64(o->in2, o->in2, ~mask); | |
2714 | tcg_gen_and_i64(o->out, o->out, o->in2); | |
2715 | break; | |
2716 | case 0x56: /* OR */ | |
2717 | tcg_gen_andi_i64(o->in2, o->in2, mask); | |
2718 | tcg_gen_or_i64(o->out, o->out, o->in2); | |
2719 | break; | |
2720 | case 0x57: /* XOR */ | |
2721 | tcg_gen_andi_i64(o->in2, o->in2, mask); | |
2722 | tcg_gen_xor_i64(o->out, o->out, o->in2); | |
2723 | break; | |
2724 | default: | |
2725 | abort(); | |
2726 | } | |
2727 | ||
2728 | /* Set the CC. */ | |
2729 | tcg_gen_andi_i64(cc_dst, o->out, mask); | |
2730 | set_cc_nz_u64(s, cc_dst); | |
2731 | return NO_EXIT; | |
2d6a8698 RH |
2732 | } |
2733 | ||
d54f5865 RH |
2734 | static ExitStatus op_rev16(DisasContext *s, DisasOps *o) |
2735 | { | |
2736 | tcg_gen_bswap16_i64(o->out, o->in2); | |
2737 | return NO_EXIT; | |
2738 | } | |
2739 | ||
2740 | static ExitStatus op_rev32(DisasContext *s, DisasOps *o) | |
2741 | { | |
2742 | tcg_gen_bswap32_i64(o->out, o->in2); | |
2743 | return NO_EXIT; | |
2744 | } | |
2745 | ||
2746 | static ExitStatus op_rev64(DisasContext *s, DisasOps *o) | |
2747 | { | |
2748 | tcg_gen_bswap64_i64(o->out, o->in2); | |
2749 | return NO_EXIT; | |
2750 | } | |
2751 | ||
cbe24bfa RH |
2752 | static ExitStatus op_rll32(DisasContext *s, DisasOps *o) |
2753 | { | |
2754 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
2755 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
2756 | TCGv_i32 to = tcg_temp_new_i32(); | |
2757 | tcg_gen_trunc_i64_i32(t1, o->in1); | |
2758 | tcg_gen_trunc_i64_i32(t2, o->in2); | |
2759 | tcg_gen_rotl_i32(to, t1, t2); | |
2760 | tcg_gen_extu_i32_i64(o->out, to); | |
2761 | tcg_temp_free_i32(t1); | |
2762 | tcg_temp_free_i32(t2); | |
2763 | tcg_temp_free_i32(to); | |
2764 | return NO_EXIT; | |
2765 | } | |
2766 | ||
2767 | static ExitStatus op_rll64(DisasContext *s, DisasOps *o) | |
2768 | { | |
2769 | tcg_gen_rotl_i64(o->out, o->in1, o->in2); | |
2770 | return NO_EXIT; | |
2771 | } | |
2772 | ||
5cc69c54 RH |
2773 | #ifndef CONFIG_USER_ONLY |
2774 | static ExitStatus op_rrbe(DisasContext *s, DisasOps *o) | |
2775 | { | |
2776 | check_privileged(s); | |
2777 | gen_helper_rrbe(cc_op, cpu_env, o->in2); | |
2778 | set_cc_static(s); | |
2779 | return NO_EXIT; | |
2780 | } | |
14244b21 RH |
2781 | |
2782 | static ExitStatus op_sacf(DisasContext *s, DisasOps *o) | |
2783 | { | |
2784 | check_privileged(s); | |
2785 | gen_helper_sacf(cpu_env, o->in2); | |
2786 | /* Addressing mode has changed, so end the block. */ | |
2787 | return EXIT_PC_STALE; | |
2788 | } | |
5cc69c54 RH |
2789 | #endif |
2790 | ||
d62a4c97 RH |
2791 | static ExitStatus op_sar(DisasContext *s, DisasOps *o) |
2792 | { | |
2793 | int r1 = get_field(s->fields, r1); | |
2794 | tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1])); | |
2795 | return NO_EXIT; | |
2796 | } | |
2797 | ||
1a800a2d RH |
2798 | static ExitStatus op_seb(DisasContext *s, DisasOps *o) |
2799 | { | |
2800 | gen_helper_seb(o->out, cpu_env, o->in1, o->in2); | |
2801 | return NO_EXIT; | |
2802 | } | |
2803 | ||
2804 | static ExitStatus op_sdb(DisasContext *s, DisasOps *o) | |
2805 | { | |
2806 | gen_helper_sdb(o->out, cpu_env, o->in1, o->in2); | |
2807 | return NO_EXIT; | |
2808 | } | |
2809 | ||
2810 | static ExitStatus op_sxb(DisasContext *s, DisasOps *o) | |
2811 | { | |
2812 | gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); | |
2813 | return_low128(o->out2); | |
2814 | return NO_EXIT; | |
2815 | } | |
2816 | ||
16d7b2a4 RH |
2817 | static ExitStatus op_sqeb(DisasContext *s, DisasOps *o) |
2818 | { | |
2819 | gen_helper_sqeb(o->out, cpu_env, o->in2); | |
2820 | return NO_EXIT; | |
2821 | } | |
2822 | ||
2823 | static ExitStatus op_sqdb(DisasContext *s, DisasOps *o) | |
2824 | { | |
2825 | gen_helper_sqdb(o->out, cpu_env, o->in2); | |
2826 | return NO_EXIT; | |
2827 | } | |
2828 | ||
2829 | static ExitStatus op_sqxb(DisasContext *s, DisasOps *o) | |
2830 | { | |
2831 | gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2); | |
2832 | return_low128(o->out2); | |
2833 | return NO_EXIT; | |
2834 | } | |
2835 | ||
0c240015 | 2836 | #ifndef CONFIG_USER_ONLY |
dc458df9 RH |
2837 | static ExitStatus op_servc(DisasContext *s, DisasOps *o) |
2838 | { | |
2839 | check_privileged(s); | |
2840 | potential_page_fault(s); | |
2841 | gen_helper_servc(cc_op, cpu_env, o->in2, o->in1); | |
2842 | set_cc_static(s); | |
2843 | return NO_EXIT; | |
2844 | } | |
2845 | ||
0c240015 RH |
2846 | static ExitStatus op_sigp(DisasContext *s, DisasOps *o) |
2847 | { | |
2848 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
2849 | check_privileged(s); | |
2850 | potential_page_fault(s); | |
2851 | gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1); | |
2852 | tcg_temp_free_i32(r1); | |
2853 | return NO_EXIT; | |
2854 | } | |
2855 | #endif | |
2856 | ||
b92fa334 RH |
2857 | static ExitStatus op_soc(DisasContext *s, DisasOps *o) |
2858 | { | |
2859 | DisasCompare c; | |
2860 | TCGv_i64 a; | |
2861 | int lab, r1; | |
2862 | ||
2863 | disas_jcc(s, &c, get_field(s->fields, m3)); | |
2864 | ||
2865 | lab = gen_new_label(); | |
2866 | if (c.is_64) { | |
2867 | tcg_gen_brcond_i64(c.cond, c.u.s64.a, c.u.s64.b, lab); | |
2868 | } else { | |
2869 | tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab); | |
2870 | } | |
2871 | free_compare(&c); | |
2872 | ||
2873 | r1 = get_field(s->fields, r1); | |
2874 | a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2)); | |
2875 | if (s->insn->data) { | |
2876 | tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s)); | |
2877 | } else { | |
2878 | tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s)); | |
2879 | } | |
2880 | tcg_temp_free_i64(a); | |
2881 | ||
2882 | gen_set_label(lab); | |
2883 | return NO_EXIT; | |
2884 | } | |
2885 | ||
cbe24bfa RH |
2886 | static ExitStatus op_sla(DisasContext *s, DisasOps *o) |
2887 | { | |
2888 | uint64_t sign = 1ull << s->insn->data; | |
2889 | enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64; | |
2890 | gen_op_update2_cc_i64(s, cco, o->in1, o->in2); | |
2891 | tcg_gen_shl_i64(o->out, o->in1, o->in2); | |
2892 | /* The arithmetic left shift is curious in that it does not affect | |
2893 | the sign bit. Copy that over from the source unchanged. */ | |
2894 | tcg_gen_andi_i64(o->out, o->out, ~sign); | |
2895 | tcg_gen_andi_i64(o->in1, o->in1, sign); | |
2896 | tcg_gen_or_i64(o->out, o->out, o->in1); | |
2897 | return NO_EXIT; | |
2898 | } | |
2899 | ||
2900 | static ExitStatus op_sll(DisasContext *s, DisasOps *o) | |
2901 | { | |
2902 | tcg_gen_shl_i64(o->out, o->in1, o->in2); | |
2903 | return NO_EXIT; | |
2904 | } | |
2905 | ||
2906 | static ExitStatus op_sra(DisasContext *s, DisasOps *o) | |
2907 | { | |
2908 | tcg_gen_sar_i64(o->out, o->in1, o->in2); | |
2909 | return NO_EXIT; | |
2910 | } | |
2911 | ||
2912 | static ExitStatus op_srl(DisasContext *s, DisasOps *o) | |
2913 | { | |
2914 | tcg_gen_shr_i64(o->out, o->in1, o->in2); | |
2915 | return NO_EXIT; | |
2916 | } | |
2917 | ||
8379bfdb RH |
2918 | static ExitStatus op_sfpc(DisasContext *s, DisasOps *o) |
2919 | { | |
2920 | gen_helper_sfpc(cpu_env, o->in2); | |
2921 | return NO_EXIT; | |
2922 | } | |
2923 | ||
7d30bb73 | 2924 | #ifndef CONFIG_USER_ONLY |
28d55556 RH |
2925 | static ExitStatus op_spka(DisasContext *s, DisasOps *o) |
2926 | { | |
2927 | check_privileged(s); | |
2928 | tcg_gen_shri_i64(o->in2, o->in2, 4); | |
2929 | tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4); | |
2930 | return NO_EXIT; | |
2931 | } | |
2932 | ||
2bbde27f RH |
2933 | static ExitStatus op_sske(DisasContext *s, DisasOps *o) |
2934 | { | |
2935 | check_privileged(s); | |
2936 | gen_helper_sske(cpu_env, o->in1, o->in2); | |
2937 | return NO_EXIT; | |
2938 | } | |
2939 | ||
7d30bb73 RH |
2940 | static ExitStatus op_ssm(DisasContext *s, DisasOps *o) |
2941 | { | |
2942 | check_privileged(s); | |
2943 | tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8); | |
2944 | return NO_EXIT; | |
2945 | } | |
145cdb40 | 2946 | |
411fea3d RH |
2947 | static ExitStatus op_stap(DisasContext *s, DisasOps *o) |
2948 | { | |
2949 | check_privileged(s); | |
2950 | /* ??? Surely cpu address != cpu number. In any case the previous | |
2951 | version of this stored more than the required half-word, so it | |
2952 | is unlikely this has ever been tested. */ | |
2953 | tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num)); | |
2954 | return NO_EXIT; | |
2955 | } | |
2956 | ||
434c91a5 RH |
2957 | static ExitStatus op_stck(DisasContext *s, DisasOps *o) |
2958 | { | |
2959 | gen_helper_stck(o->out, cpu_env); | |
2960 | /* ??? We don't implement clock states. */ | |
2961 | gen_op_movi_cc(s, 0); | |
2962 | return NO_EXIT; | |
39a5003c RH |
2963 | } |
2964 | ||
2965 | static ExitStatus op_stcke(DisasContext *s, DisasOps *o) | |
2966 | { | |
2967 | TCGv_i64 c1 = tcg_temp_new_i64(); | |
2968 | TCGv_i64 c2 = tcg_temp_new_i64(); | |
2969 | gen_helper_stck(c1, cpu_env); | |
2970 | /* Shift the 64-bit value into its place as a zero-extended | |
2971 | 104-bit value. Note that "bit positions 64-103 are always | |
2972 | non-zero so that they compare differently to STCK"; we set | |
2973 | the least significant bit to 1. */ | |
2974 | tcg_gen_shli_i64(c2, c1, 56); | |
2975 | tcg_gen_shri_i64(c1, c1, 8); | |
2976 | tcg_gen_ori_i64(c2, c2, 0x10000); | |
2977 | tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s)); | |
2978 | tcg_gen_addi_i64(o->in2, o->in2, 8); | |
2979 | tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s)); | |
2980 | tcg_temp_free_i64(c1); | |
2981 | tcg_temp_free_i64(c2); | |
2982 | /* ??? We don't implement clock states. */ | |
2983 | gen_op_movi_cc(s, 0); | |
2984 | return NO_EXIT; | |
434c91a5 RH |
2985 | } |
2986 | ||
dd3eb7b5 RH |
2987 | static ExitStatus op_sckc(DisasContext *s, DisasOps *o) |
2988 | { | |
2989 | check_privileged(s); | |
2990 | gen_helper_sckc(cpu_env, o->in2); | |
2991 | return NO_EXIT; | |
2992 | } | |
2993 | ||
2994 | static ExitStatus op_stckc(DisasContext *s, DisasOps *o) | |
2995 | { | |
2996 | check_privileged(s); | |
2997 | gen_helper_stckc(o->out, cpu_env); | |
2998 | return NO_EXIT; | |
2999 | } | |
3000 | ||
3e398cf9 RH |
3001 | static ExitStatus op_stctg(DisasContext *s, DisasOps *o) |
3002 | { | |
3003 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
3004 | TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); | |
3005 | check_privileged(s); | |
3006 | potential_page_fault(s); | |
3007 | gen_helper_stctg(cpu_env, r1, o->in2, r3); | |
3008 | tcg_temp_free_i32(r1); | |
3009 | tcg_temp_free_i32(r3); | |
3010 | return NO_EXIT; | |
3011 | } | |
3012 | ||
504488b8 RH |
3013 | static ExitStatus op_stctl(DisasContext *s, DisasOps *o) |
3014 | { | |
3015 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
3016 | TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); | |
3017 | check_privileged(s); | |
3018 | potential_page_fault(s); | |
3019 | gen_helper_stctl(cpu_env, r1, o->in2, r3); | |
3020 | tcg_temp_free_i32(r1); | |
3021 | tcg_temp_free_i32(r3); | |
3022 | return NO_EXIT; | |
3023 | } | |
3024 | ||
71bd6669 RH |
3025 | static ExitStatus op_stidp(DisasContext *s, DisasOps *o) |
3026 | { | |
3027 | check_privileged(s); | |
3028 | tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num)); | |
3029 | return NO_EXIT; | |
3030 | } | |
3031 | ||
c4f0a863 RH |
3032 | static ExitStatus op_spt(DisasContext *s, DisasOps *o) |
3033 | { | |
3034 | check_privileged(s); | |
3035 | gen_helper_spt(cpu_env, o->in2); | |
3036 | return NO_EXIT; | |
3037 | } | |
3038 | ||
fc778b55 RH |
3039 | static ExitStatus op_stfl(DisasContext *s, DisasOps *o) |
3040 | { | |
3041 | TCGv_i64 f, a; | |
3042 | /* We really ought to have more complete indication of facilities | |
3043 | that we implement. Address this when STFLE is implemented. */ | |
3044 | check_privileged(s); | |
3045 | f = tcg_const_i64(0xc0000000); | |
3046 | a = tcg_const_i64(200); | |
3047 | tcg_gen_qemu_st32(f, a, get_mem_index(s)); | |
3048 | tcg_temp_free_i64(f); | |
3049 | tcg_temp_free_i64(a); | |
3050 | return NO_EXIT; | |
3051 | } | |
3052 | ||
c4f0a863 RH |
3053 | static ExitStatus op_stpt(DisasContext *s, DisasOps *o) |
3054 | { | |
3055 | check_privileged(s); | |
3056 | gen_helper_stpt(o->out, cpu_env); | |
3057 | return NO_EXIT; | |
3058 | } | |
3059 | ||
d14b3e09 RH |
3060 | static ExitStatus op_stsi(DisasContext *s, DisasOps *o) |
3061 | { | |
3062 | check_privileged(s); | |
3063 | potential_page_fault(s); | |
3064 | gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]); | |
3065 | set_cc_static(s); | |
3066 | return NO_EXIT; | |
3067 | } | |
3068 | ||
e805a0d3 RH |
3069 | static ExitStatus op_spx(DisasContext *s, DisasOps *o) |
3070 | { | |
3071 | check_privileged(s); | |
3072 | gen_helper_spx(cpu_env, o->in2); | |
3073 | return NO_EXIT; | |
3074 | } | |
3075 | ||
2c423fc0 RH |
3076 | static ExitStatus op_subchannel(DisasContext *s, DisasOps *o) |
3077 | { | |
3078 | check_privileged(s); | |
3079 | /* Not operational. */ | |
3080 | gen_op_movi_cc(s, 3); | |
3081 | return NO_EXIT; | |
3082 | } | |
3083 | ||
e805a0d3 RH |
3084 | static ExitStatus op_stpx(DisasContext *s, DisasOps *o) |
3085 | { | |
3086 | check_privileged(s); | |
3087 | tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa)); | |
3088 | tcg_gen_andi_i64(o->out, o->out, 0x7fffe000); | |
3089 | return NO_EXIT; | |
3090 | } | |
3091 | ||
145cdb40 RH |
3092 | static ExitStatus op_stnosm(DisasContext *s, DisasOps *o) |
3093 | { | |
3094 | uint64_t i2 = get_field(s->fields, i2); | |
3095 | TCGv_i64 t; | |
3096 | ||
3097 | check_privileged(s); | |
3098 | ||
3099 | /* It is important to do what the instruction name says: STORE THEN. | |
3100 | If we let the output hook perform the store then if we fault and | |
3101 | restart, we'll have the wrong SYSTEM MASK in place. */ | |
3102 | t = tcg_temp_new_i64(); | |
3103 | tcg_gen_shri_i64(t, psw_mask, 56); | |
3104 | tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s)); | |
3105 | tcg_temp_free_i64(t); | |
3106 | ||
3107 | if (s->fields->op == 0xac) { | |
3108 | tcg_gen_andi_i64(psw_mask, psw_mask, | |
3109 | (i2 << 56) | 0x00ffffffffffffffull); | |
3110 | } else { | |
3111 | tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56); | |
3112 | } | |
3113 | return NO_EXIT; | |
3114 | } | |
204504e2 RH |
3115 | |
3116 | static ExitStatus op_stura(DisasContext *s, DisasOps *o) | |
3117 | { | |
3118 | check_privileged(s); | |
3119 | potential_page_fault(s); | |
3120 | gen_helper_stura(cpu_env, o->in2, o->in1); | |
3121 | return NO_EXIT; | |
3122 | } | |
7d30bb73 RH |
3123 | #endif |
3124 | ||
2b280b97 RH |
3125 | static ExitStatus op_st8(DisasContext *s, DisasOps *o) |
3126 | { | |
3127 | tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s)); | |
3128 | return NO_EXIT; | |
3129 | } | |
3130 | ||
3131 | static ExitStatus op_st16(DisasContext *s, DisasOps *o) | |
3132 | { | |
3133 | tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s)); | |
3134 | return NO_EXIT; | |
3135 | } | |
3136 | ||
3137 | static ExitStatus op_st32(DisasContext *s, DisasOps *o) | |
3138 | { | |
3139 | tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s)); | |
3140 | return NO_EXIT; | |
3141 | } | |
3142 | ||
3143 | static ExitStatus op_st64(DisasContext *s, DisasOps *o) | |
3144 | { | |
3145 | tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s)); | |
3146 | return NO_EXIT; | |
3147 | } | |
3148 | ||
7df3e93a RH |
3149 | static ExitStatus op_stam(DisasContext *s, DisasOps *o) |
3150 | { | |
3151 | TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); | |
3152 | TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); | |
3153 | potential_page_fault(s); | |
3154 | gen_helper_stam(cpu_env, r1, o->in2, r3); | |
3155 | tcg_temp_free_i32(r1); | |
3156 | tcg_temp_free_i32(r3); | |
3157 | return NO_EXIT; | |
3158 | } | |
3159 | ||
2ae68059 RH |
3160 | static ExitStatus op_stcm(DisasContext *s, DisasOps *o) |
3161 | { | |
3162 | int m3 = get_field(s->fields, m3); | |
3163 | int pos, base = s->insn->data; | |
3164 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
3165 | ||
3166 | pos = base + ctz32(m3) * 8; | |
3167 | switch (m3) { | |
3168 | case 0xf: | |
3169 | /* Effectively a 32-bit store. */ | |
3170 | tcg_gen_shri_i64(tmp, o->in1, pos); | |
3171 | tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s)); | |
3172 | break; | |
3173 | ||
3174 | case 0xc: | |
3175 | case 0x6: | |
3176 | case 0x3: | |
3177 | /* Effectively a 16-bit store. */ | |
3178 | tcg_gen_shri_i64(tmp, o->in1, pos); | |
3179 | tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s)); | |
3180 | break; | |
3181 | ||
3182 | case 0x8: | |
3183 | case 0x4: | |
3184 | case 0x2: | |
3185 | case 0x1: | |
3186 | /* Effectively an 8-bit store. */ | |
3187 | tcg_gen_shri_i64(tmp, o->in1, pos); | |
3188 | tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s)); | |
3189 | break; | |
3190 | ||
3191 | default: | |
3192 | /* This is going to be a sequence of shifts and stores. */ | |
3193 | pos = base + 32 - 8; | |
3194 | while (m3) { | |
3195 | if (m3 & 0x8) { | |
3196 | tcg_gen_shri_i64(tmp, o->in1, pos); | |
3197 | tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s)); | |
3198 | tcg_gen_addi_i64(o->in2, o->in2, 1); | |
3199 | } | |
3200 | m3 = (m3 << 1) & 0xf; | |
3201 | pos -= 8; | |
3202 | } | |
3203 | break; | |
3204 | } | |
3205 | tcg_temp_free_i64(tmp); | |
3206 | return NO_EXIT; | |
3207 | } | |
3208 | ||
77f8d6c3 RH |
3209 | static ExitStatus op_stm(DisasContext *s, DisasOps *o) |
3210 | { | |
3211 | int r1 = get_field(s->fields, r1); | |
3212 | int r3 = get_field(s->fields, r3); | |
3213 | int size = s->insn->data; | |
3214 | TCGv_i64 tsize = tcg_const_i64(size); | |
3215 | ||
3216 | while (1) { | |
3217 | if (size == 8) { | |
3218 | tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s)); | |
3219 | } else { | |
3220 | tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s)); | |
3221 | } | |
3222 | if (r1 == r3) { | |
3223 | break; | |
3224 | } | |
3225 | tcg_gen_add_i64(o->in2, o->in2, tsize); | |
3226 | r1 = (r1 + 1) & 15; | |
3227 | } | |
3228 | ||
3229 | tcg_temp_free_i64(tsize); | |
3230 | return NO_EXIT; | |
3231 | } | |
3232 | ||
3233 | static ExitStatus op_stmh(DisasContext *s, DisasOps *o) | |
3234 | { | |
3235 | int r1 = get_field(s->fields, r1); | |
3236 | int r3 = get_field(s->fields, r3); | |
3237 | TCGv_i64 t = tcg_temp_new_i64(); | |
3238 | TCGv_i64 t4 = tcg_const_i64(4); | |
3239 | TCGv_i64 t32 = tcg_const_i64(32); | |
3240 | ||
3241 | while (1) { | |
3242 | tcg_gen_shl_i64(t, regs[r1], t32); | |
3243 | tcg_gen_qemu_st32(t, o->in2, get_mem_index(s)); | |
3244 | if (r1 == r3) { | |
3245 | break; | |
3246 | } | |
3247 | tcg_gen_add_i64(o->in2, o->in2, t4); | |
3248 | r1 = (r1 + 1) & 15; | |
3249 | } | |
3250 | ||
3251 | tcg_temp_free_i64(t); | |
3252 | tcg_temp_free_i64(t4); | |
3253 | tcg_temp_free_i64(t32); | |
3254 | return NO_EXIT; | |
3255 | } | |
3256 | ||
4600c994 RH |
3257 | static ExitStatus op_srst(DisasContext *s, DisasOps *o) |
3258 | { | |
3259 | potential_page_fault(s); | |
3260 | gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2); | |
3261 | set_cc_static(s); | |
3262 | return_low128(o->in2); | |
3263 | return NO_EXIT; | |
3264 | } | |
3265 | ||
ad044d09 RH |
3266 | static ExitStatus op_sub(DisasContext *s, DisasOps *o) |
3267 | { | |
3268 | tcg_gen_sub_i64(o->out, o->in1, o->in2); | |
3269 | return NO_EXIT; | |
3270 | } | |
3271 | ||
4e4bb438 RH |
3272 | static ExitStatus op_subb(DisasContext *s, DisasOps *o) |
3273 | { | |
3274 | TCGv_i64 cc; | |
3275 | ||
3276 | assert(!o->g_in2); | |
3277 | tcg_gen_not_i64(o->in2, o->in2); | |
3278 | tcg_gen_add_i64(o->out, o->in1, o->in2); | |
3279 | ||
3280 | /* XXX possible optimization point */ | |
3281 | gen_op_calc_cc(s); | |
3282 | cc = tcg_temp_new_i64(); | |
3283 | tcg_gen_extu_i32_i64(cc, cc_op); | |
3284 | tcg_gen_shri_i64(cc, cc, 1); | |
3285 | tcg_gen_add_i64(o->out, o->out, cc); | |
3286 | tcg_temp_free_i64(cc); | |
3287 | return NO_EXIT; | |
3288 | } | |
3289 | ||
b9836c1a RH |
3290 | static ExitStatus op_svc(DisasContext *s, DisasOps *o) |
3291 | { | |
3292 | TCGv_i32 t; | |
3293 | ||
3294 | update_psw_addr(s); | |
7a6c7067 | 3295 | update_cc_op(s); |
b9836c1a RH |
3296 | |
3297 | t = tcg_const_i32(get_field(s->fields, i1) & 0xff); | |
3298 | tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code)); | |
3299 | tcg_temp_free_i32(t); | |
3300 | ||
3301 | t = tcg_const_i32(s->next_pc - s->pc); | |
3302 | tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen)); | |
3303 | tcg_temp_free_i32(t); | |
3304 | ||
3305 | gen_exception(EXCP_SVC); | |
3306 | return EXIT_NORETURN; | |
3307 | } | |
3308 | ||
31aa97d1 RH |
3309 | static ExitStatus op_tceb(DisasContext *s, DisasOps *o) |
3310 | { | |
3311 | gen_helper_tceb(cc_op, o->in1, o->in2); | |
3312 | set_cc_static(s); | |
3313 | return NO_EXIT; | |
3314 | } | |
3315 | ||
3316 | static ExitStatus op_tcdb(DisasContext *s, DisasOps *o) | |
3317 | { | |
3318 | gen_helper_tcdb(cc_op, o->in1, o->in2); | |
3319 | set_cc_static(s); | |
3320 | return NO_EXIT; | |
3321 | } | |
3322 | ||
3323 | static ExitStatus op_tcxb(DisasContext *s, DisasOps *o) | |
3324 | { | |
3325 | gen_helper_tcxb(cc_op, o->out, o->out2, o->in2); | |
3326 | set_cc_static(s); | |
3327 | return NO_EXIT; | |
3328 | } | |
3329 | ||
112bf079 RH |
3330 | #ifndef CONFIG_USER_ONLY |
3331 | static ExitStatus op_tprot(DisasContext *s, DisasOps *o) | |
3332 | { | |
3333 | potential_page_fault(s); | |
3334 | gen_helper_tprot(cc_op, o->addr1, o->in2); | |
3335 | set_cc_static(s); | |
3336 | return NO_EXIT; | |
3337 | } | |
3338 | #endif | |
3339 | ||
0a949039 RH |
3340 | static ExitStatus op_tr(DisasContext *s, DisasOps *o) |
3341 | { | |
3342 | TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); | |
3343 | potential_page_fault(s); | |
3344 | gen_helper_tr(cpu_env, l, o->addr1, o->in2); | |
3345 | tcg_temp_free_i32(l); | |
3346 | set_cc_static(s); | |
3347 | return NO_EXIT; | |
3348 | } | |
3349 | ||
3350 | static ExitStatus op_unpk(DisasContext *s, DisasOps *o) | |
3351 | { | |
3352 | TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); | |
3353 | potential_page_fault(s); | |
3354 | gen_helper_unpk(cpu_env, l, o->addr1, o->in2); | |
3355 | tcg_temp_free_i32(l); | |
3356 | return NO_EXIT; | |
3357 | } | |
3358 | ||
3359 | static ExitStatus op_xc(DisasContext *s, DisasOps *o) | |
3360 | { | |
3361 | TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); | |
3362 | potential_page_fault(s); | |
3363 | gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2); | |
3364 | tcg_temp_free_i32(l); | |
3365 | set_cc_static(s); | |
3366 | return NO_EXIT; | |
3367 | } | |
3368 | ||
3bbfbd1f RH |
3369 | static ExitStatus op_xor(DisasContext *s, DisasOps *o) |
3370 | { | |
3371 | tcg_gen_xor_i64(o->out, o->in1, o->in2); | |
3372 | return NO_EXIT; | |
3373 | } | |
3374 | ||
facfc864 RH |
3375 | static ExitStatus op_xori(DisasContext *s, DisasOps *o) |
3376 | { | |
3377 | int shift = s->insn->data & 0xff; | |
3378 | int size = s->insn->data >> 8; | |
3379 | uint64_t mask = ((1ull << size) - 1) << shift; | |
3380 | ||
3381 | assert(!o->g_in2); | |
3382 | tcg_gen_shli_i64(o->in2, o->in2, shift); | |
3383 | tcg_gen_xor_i64(o->out, o->in1, o->in2); | |
3384 | ||
3385 | /* Produce the CC from only the bits manipulated. */ | |
3386 | tcg_gen_andi_i64(cc_dst, o->out, mask); | |
3387 | set_cc_nz_u64(s, cc_dst); | |
3388 | return NO_EXIT; | |
3389 | } | |
3390 | ||
24db8412 RH |
3391 | static ExitStatus op_zero(DisasContext *s, DisasOps *o) |
3392 | { | |
3393 | o->out = tcg_const_i64(0); | |
3394 | return NO_EXIT; | |
3395 | } | |
3396 | ||
3397 | static ExitStatus op_zero2(DisasContext *s, DisasOps *o) | |
3398 | { | |
3399 | o->out = tcg_const_i64(0); | |
3400 | o->out2 = o->out; | |
3401 | o->g_out2 = true; | |
3402 | return NO_EXIT; | |
3403 | } | |
3404 | ||
ad044d09 RH |
3405 | /* ====================================================================== */ |
3406 | /* The "Cc OUTput" generators. Given the generated output (and in some cases | |
3407 | the original inputs), update the various cc data structures in order to | |
3408 | be able to compute the new condition code. */ | |
3409 | ||
b9bca3e5 RH |
3410 | static void cout_abs32(DisasContext *s, DisasOps *o) |
3411 | { | |
3412 | gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out); | |
3413 | } | |
3414 | ||
3415 | static void cout_abs64(DisasContext *s, DisasOps *o) | |
3416 | { | |
3417 | gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out); | |
3418 | } | |
3419 | ||
ad044d09 RH |
3420 | static void cout_adds32(DisasContext *s, DisasOps *o) |
3421 | { | |
3422 | gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out); | |
3423 | } | |
3424 | ||
3425 | static void cout_adds64(DisasContext *s, DisasOps *o) | |
3426 | { | |
3427 | gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out); | |
3428 | } | |
3429 | ||
3430 | static void cout_addu32(DisasContext *s, DisasOps *o) | |
3431 | { | |
3432 | gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out); | |
3433 | } | |
3434 | ||
3435 | static void cout_addu64(DisasContext *s, DisasOps *o) | |
3436 | { | |
3437 | gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out); | |
3438 | } | |
3439 | ||
4e4bb438 RH |
3440 | static void cout_addc32(DisasContext *s, DisasOps *o) |
3441 | { | |
3442 | gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out); | |
3443 | } | |
3444 | ||
3445 | static void cout_addc64(DisasContext *s, DisasOps *o) | |
3446 | { | |
3447 | gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out); | |
3448 | } | |
3449 | ||
a7e836d5 RH |
3450 | static void cout_cmps32(DisasContext *s, DisasOps *o) |
3451 | { | |
3452 | gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2); | |
3453 | } | |
3454 | ||
3455 | static void cout_cmps64(DisasContext *s, DisasOps *o) | |
3456 | { | |
3457 | gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2); | |
3458 | } | |
3459 | ||
3460 | static void cout_cmpu32(DisasContext *s, DisasOps *o) | |
3461 | { | |
3462 | gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2); | |
3463 | } | |
3464 | ||
3465 | static void cout_cmpu64(DisasContext *s, DisasOps *o) | |
3466 | { | |
3467 | gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2); | |
3468 | } | |
3469 | ||
587626f8 RH |
3470 | static void cout_f32(DisasContext *s, DisasOps *o) |
3471 | { | |
3472 | gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out); | |
3473 | } | |
3474 | ||
3475 | static void cout_f64(DisasContext *s, DisasOps *o) | |
3476 | { | |
3477 | gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out); | |
3478 | } | |
3479 | ||
3480 | static void cout_f128(DisasContext *s, DisasOps *o) | |
3481 | { | |
3482 | gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2); | |
3483 | } | |
3484 | ||
b9bca3e5 RH |
3485 | static void cout_nabs32(DisasContext *s, DisasOps *o) |
3486 | { | |
3487 | gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out); | |
3488 | } | |
3489 | ||
3490 | static void cout_nabs64(DisasContext *s, DisasOps *o) | |
3491 | { | |
3492 | gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out); | |
3493 | } | |
3494 | ||
3495 | static void cout_neg32(DisasContext *s, DisasOps *o) | |
3496 | { | |
3497 | gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out); | |
3498 | } | |
3499 | ||
3500 | static void cout_neg64(DisasContext *s, DisasOps *o) | |
3501 | { | |
3502 | gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out); | |
3503 | } | |
3504 | ||
3bbfbd1f RH |
3505 | static void cout_nz32(DisasContext *s, DisasOps *o) |
3506 | { | |
3507 | tcg_gen_ext32u_i64(cc_dst, o->out); | |
3508 | gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst); | |
3509 | } | |
3510 | ||
3511 | static void cout_nz64(DisasContext *s, DisasOps *o) | |
3512 | { | |
3513 | gen_op_update1_cc_i64(s, CC_OP_NZ, o->out); | |
3514 | } | |
3515 | ||
11bf2d73 RH |
3516 | static void cout_s32(DisasContext *s, DisasOps *o) |
3517 | { | |
3518 | gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out); | |
3519 | } | |
3520 | ||
3521 | static void cout_s64(DisasContext *s, DisasOps *o) | |
3522 | { | |
3523 | gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out); | |
3524 | } | |
3525 | ||
ad044d09 RH |
3526 | static void cout_subs32(DisasContext *s, DisasOps *o) |
3527 | { | |
3528 | gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out); | |
3529 | } | |
3530 | ||
3531 | static void cout_subs64(DisasContext *s, DisasOps *o) | |
3532 | { | |
3533 | gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out); | |
3534 | } | |
3535 | ||
3536 | static void cout_subu32(DisasContext *s, DisasOps *o) | |
3537 | { | |
3538 | gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out); | |
3539 | } | |
3540 | ||
3541 | static void cout_subu64(DisasContext *s, DisasOps *o) | |
3542 | { | |
3543 | gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out); | |
3544 | } | |
3545 | ||
4e4bb438 RH |
3546 | static void cout_subb32(DisasContext *s, DisasOps *o) |
3547 | { | |
3548 | gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out); | |
3549 | } | |
3550 | ||
3551 | static void cout_subb64(DisasContext *s, DisasOps *o) | |
3552 | { | |
3553 | gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out); | |
3554 | } | |
3555 | ||
00d2dc19 RH |
3556 | static void cout_tm32(DisasContext *s, DisasOps *o) |
3557 | { | |
3558 | gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2); | |
3559 | } | |
3560 | ||
3561 | static void cout_tm64(DisasContext *s, DisasOps *o) | |
3562 | { | |
3563 | gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2); | |
3564 | } | |
3565 | ||
ad044d09 RH |
3566 | /* ====================================================================== */ |
3567 | /* The "PREPeration" generators. These initialize the DisasOps.OUT fields | |
3568 | with the TCG register to which we will write. Used in combination with | |
3569 | the "wout" generators, in some cases we need a new temporary, and in | |
3570 | some cases we can write to a TCG global. */ | |
3571 | ||
3572 | static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o) | |
3573 | { | |
3574 | o->out = tcg_temp_new_i64(); | |
3575 | } | |
49f7ee80 | 3576 | #define SPEC_prep_new 0 |
ad044d09 | 3577 | |
891452e5 RH |
3578 | static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o) |
3579 | { | |
3580 | o->out = tcg_temp_new_i64(); | |
3581 | o->out2 = tcg_temp_new_i64(); | |
3582 | } | |
49f7ee80 | 3583 | #define SPEC_prep_new_P 0 |
891452e5 | 3584 | |
ad044d09 RH |
3585 | static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o) |
3586 | { | |
3587 | o->out = regs[get_field(f, r1)]; | |
3588 | o->g_out = true; | |
3589 | } | |
49f7ee80 | 3590 | #define SPEC_prep_r1 0 |
ad044d09 | 3591 | |
1ac5889f RH |
3592 | static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o) |
3593 | { | |
1ac5889f RH |
3594 | int r1 = get_field(f, r1); |
3595 | o->out = regs[r1]; | |
49f7ee80 | 3596 | o->out2 = regs[r1 + 1]; |
1ac5889f RH |
3597 | o->g_out = o->g_out2 = true; |
3598 | } | |
49f7ee80 | 3599 | #define SPEC_prep_r1_P SPEC_r1_even |
1ac5889f | 3600 | |
587626f8 RH |
3601 | static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o) |
3602 | { | |
3603 | o->out = fregs[get_field(f, r1)]; | |
3604 | o->g_out = true; | |
3605 | } | |
49f7ee80 | 3606 | #define SPEC_prep_f1 0 |
587626f8 RH |
3607 | |
3608 | static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o) | |
3609 | { | |
587626f8 RH |
3610 | int r1 = get_field(f, r1); |
3611 | o->out = fregs[r1]; | |
49f7ee80 | 3612 | o->out2 = fregs[r1 + 2]; |
587626f8 RH |
3613 | o->g_out = o->g_out2 = true; |
3614 | } | |
49f7ee80 | 3615 | #define SPEC_prep_x1 SPEC_r1_f128 |
587626f8 | 3616 | |
ad044d09 RH |
3617 | /* ====================================================================== */ |
3618 | /* The "Write OUTput" generators. These generally perform some non-trivial | |
3619 | copy of data to TCG globals, or to main memory. The trivial cases are | |
3620 | generally handled by having a "prep" generator install the TCG global | |
3621 | as the destination of the operation. */ | |
3622 | ||
22c37a08 RH |
3623 | static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o) |
3624 | { | |
3625 | store_reg(get_field(f, r1), o->out); | |
3626 | } | |
49f7ee80 | 3627 | #define SPEC_wout_r1 0 |
22c37a08 | 3628 | |
afdc70be RH |
3629 | static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o) |
3630 | { | |
3631 | int r1 = get_field(f, r1); | |
3632 | tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8); | |
3633 | } | |
49f7ee80 | 3634 | #define SPEC_wout_r1_8 0 |
afdc70be | 3635 | |
d54f5865 RH |
3636 | static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o) |
3637 | { | |
3638 | int r1 = get_field(f, r1); | |
3639 | tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16); | |
3640 | } | |
49f7ee80 | 3641 | #define SPEC_wout_r1_16 0 |
d54f5865 | 3642 | |
ad044d09 RH |
3643 | static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o) |
3644 | { | |
3645 | store_reg32_i64(get_field(f, r1), o->out); | |
3646 | } | |
49f7ee80 | 3647 | #define SPEC_wout_r1_32 0 |
ad044d09 | 3648 | |
891452e5 RH |
3649 | static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o) |
3650 | { | |
891452e5 RH |
3651 | int r1 = get_field(f, r1); |
3652 | store_reg32_i64(r1, o->out); | |
49f7ee80 | 3653 | store_reg32_i64(r1 + 1, o->out2); |
891452e5 | 3654 | } |
49f7ee80 | 3655 | #define SPEC_wout_r1_P32 SPEC_r1_even |
891452e5 | 3656 | |
d87aaf93 RH |
3657 | static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o) |
3658 | { | |
d87aaf93 | 3659 | int r1 = get_field(f, r1); |
49f7ee80 | 3660 | store_reg32_i64(r1 + 1, o->out); |
d87aaf93 RH |
3661 | tcg_gen_shri_i64(o->out, o->out, 32); |
3662 | store_reg32_i64(r1, o->out); | |
3663 | } | |
49f7ee80 | 3664 | #define SPEC_wout_r1_D32 SPEC_r1_even |
22c37a08 | 3665 | |
d764a8d1 RH |
3666 | static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o) |
3667 | { | |
3668 | store_freg32_i64(get_field(f, r1), o->out); | |
3669 | } | |
49f7ee80 | 3670 | #define SPEC_wout_e1 0 |
d764a8d1 RH |
3671 | |
3672 | static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o) | |
3673 | { | |
3674 | store_freg(get_field(f, r1), o->out); | |
3675 | } | |
49f7ee80 | 3676 | #define SPEC_wout_f1 0 |
d764a8d1 RH |
3677 | |
3678 | static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o) | |
3679 | { | |
3680 | int f1 = get_field(s->fields, r1); | |
3681 | store_freg(f1, o->out); | |
49f7ee80 | 3682 | store_freg(f1 + 2, o->out2); |
d764a8d1 | 3683 | } |
49f7ee80 | 3684 | #define SPEC_wout_x1 SPEC_r1_f128 |
d764a8d1 | 3685 | |
22c37a08 RH |
3686 | static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o) |
3687 | { | |
3688 | if (get_field(f, r1) != get_field(f, r2)) { | |
3689 | store_reg32_i64(get_field(f, r1), o->out); | |
3690 | } | |
3691 | } | |
49f7ee80 | 3692 | #define SPEC_wout_cond_r1r2_32 0 |
d87aaf93 | 3693 | |
d764a8d1 RH |
3694 | static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o) |
3695 | { | |
3696 | if (get_field(f, r1) != get_field(f, r2)) { | |
3697 | store_freg32_i64(get_field(f, r1), o->out); | |
3698 | } | |
3699 | } | |
49f7ee80 | 3700 | #define SPEC_wout_cond_e1e2 0 |
d764a8d1 | 3701 | |
6a04d76a RH |
3702 | static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o) |
3703 | { | |
3704 | tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s)); | |
3705 | } | |
49f7ee80 | 3706 | #define SPEC_wout_m1_8 0 |
6a04d76a RH |
3707 | |
3708 | static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o) | |
3709 | { | |
3710 | tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s)); | |
3711 | } | |
49f7ee80 | 3712 | #define SPEC_wout_m1_16 0 |
6a04d76a | 3713 | |
ad044d09 RH |
3714 | static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o) |
3715 | { | |
3716 | tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s)); | |
3717 | } | |
49f7ee80 | 3718 | #define SPEC_wout_m1_32 0 |
ad044d09 RH |
3719 | |
3720 | static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o) | |
3721 | { | |
3722 | tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s)); | |
3723 | } | |
49f7ee80 | 3724 | #define SPEC_wout_m1_64 0 |
ad044d09 | 3725 | |
ea20490f RH |
3726 | static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o) |
3727 | { | |
3728 | tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s)); | |
3729 | } | |
49f7ee80 | 3730 | #define SPEC_wout_m2_32 0 |
ea20490f | 3731 | |
ad044d09 RH |
3732 | /* ====================================================================== */ |
3733 | /* The "INput 1" generators. These load the first operand to an insn. */ | |
3734 | ||
3735 | static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o) | |
3736 | { | |
3737 | o->in1 = load_reg(get_field(f, r1)); | |
3738 | } | |
49f7ee80 | 3739 | #define SPEC_in1_r1 0 |
ad044d09 | 3740 | |
d1c04a2b RH |
3741 | static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o) |
3742 | { | |
3743 | o->in1 = regs[get_field(f, r1)]; | |
3744 | o->g_in1 = true; | |
3745 | } | |
49f7ee80 | 3746 | #define SPEC_in1_r1_o 0 |
d1c04a2b | 3747 | |
cbe24bfa RH |
3748 | static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o) |
3749 | { | |
3750 | o->in1 = tcg_temp_new_i64(); | |
3751 | tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]); | |
3752 | } | |
49f7ee80 | 3753 | #define SPEC_in1_r1_32s 0 |
cbe24bfa RH |
3754 | |
3755 | static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o) | |
3756 | { | |
3757 | o->in1 = tcg_temp_new_i64(); | |
3758 | tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]); | |
3759 | } | |
49f7ee80 | 3760 | #define SPEC_in1_r1_32u 0 |
cbe24bfa | 3761 | |
32a44d58 RH |
3762 | static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o) |
3763 | { | |
3764 | o->in1 = tcg_temp_new_i64(); | |
3765 | tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32); | |
3766 | } | |
49f7ee80 | 3767 | #define SPEC_in1_r1_sr32 0 |
32a44d58 | 3768 | |
1ac5889f RH |
3769 | static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o) |
3770 | { | |
49f7ee80 | 3771 | o->in1 = load_reg(get_field(f, r1) + 1); |
1ac5889f | 3772 | } |
49f7ee80 | 3773 | #define SPEC_in1_r1p1 SPEC_r1_even |
1ac5889f | 3774 | |
d87aaf93 RH |
3775 | static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o) |
3776 | { | |
d87aaf93 | 3777 | o->in1 = tcg_temp_new_i64(); |
49f7ee80 | 3778 | tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1) + 1]); |
d87aaf93 | 3779 | } |
49f7ee80 | 3780 | #define SPEC_in1_r1p1_32s SPEC_r1_even |
d87aaf93 RH |
3781 | |
3782 | static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o) | |
3783 | { | |
d87aaf93 | 3784 | o->in1 = tcg_temp_new_i64(); |
49f7ee80 | 3785 | tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1) + 1]); |
d87aaf93 | 3786 | } |
49f7ee80 | 3787 | #define SPEC_in1_r1p1_32u SPEC_r1_even |
d87aaf93 | 3788 | |
891452e5 RH |
3789 | static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o) |
3790 | { | |
891452e5 RH |
3791 | int r1 = get_field(f, r1); |
3792 | o->in1 = tcg_temp_new_i64(); | |
3793 | tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]); | |
3794 | } | |
49f7ee80 | 3795 | #define SPEC_in1_r1_D32 SPEC_r1_even |
891452e5 | 3796 | |
ad044d09 RH |
3797 | static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o) |
3798 | { | |
3799 | o->in1 = load_reg(get_field(f, r2)); | |
3800 | } | |
49f7ee80 | 3801 | #define SPEC_in1_r2 0 |
ad044d09 RH |
3802 | |
3803 | static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o) | |
3804 | { | |
3805 | o->in1 = load_reg(get_field(f, r3)); | |
3806 | } | |
49f7ee80 | 3807 | #define SPEC_in1_r3 0 |
ad044d09 | 3808 | |
cbe24bfa RH |
3809 | static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o) |
3810 | { | |
3811 | o->in1 = regs[get_field(f, r3)]; | |
3812 | o->g_in1 = true; | |
3813 | } | |
49f7ee80 | 3814 | #define SPEC_in1_r3_o 0 |
cbe24bfa RH |
3815 | |
3816 | static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o) | |
3817 | { | |
3818 | o->in1 = tcg_temp_new_i64(); | |
3819 | tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]); | |
3820 | } | |
49f7ee80 | 3821 | #define SPEC_in1_r3_32s 0 |
cbe24bfa RH |
3822 | |
3823 | static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o) | |
3824 | { | |
3825 | o->in1 = tcg_temp_new_i64(); | |
3826 | tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]); | |
3827 | } | |
49f7ee80 | 3828 | #define SPEC_in1_r3_32u 0 |
cbe24bfa | 3829 | |
00574261 RH |
3830 | static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o) |
3831 | { | |
3832 | o->in1 = load_freg32_i64(get_field(f, r1)); | |
3833 | } | |
49f7ee80 | 3834 | #define SPEC_in1_e1 0 |
00574261 RH |
3835 | |
3836 | static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o) | |
3837 | { | |
3838 | o->in1 = fregs[get_field(f, r1)]; | |
3839 | o->g_in1 = true; | |
3840 | } | |
49f7ee80 | 3841 | #define SPEC_in1_f1_o 0 |
00574261 | 3842 | |
587626f8 RH |
3843 | static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o) |
3844 | { | |
587626f8 RH |
3845 | int r1 = get_field(f, r1); |
3846 | o->out = fregs[r1]; | |
49f7ee80 | 3847 | o->out2 = fregs[r1 + 2]; |
587626f8 RH |
3848 | o->g_out = o->g_out2 = true; |
3849 | } | |
49f7ee80 | 3850 | #define SPEC_in1_x1_o SPEC_r1_f128 |
587626f8 | 3851 | |
2db014b5 RH |
3852 | static void in1_f3_o(DisasContext *s, DisasFields *f, DisasOps *o) |
3853 | { | |
3854 | o->in1 = fregs[get_field(f, r3)]; | |
3855 | o->g_in1 = true; | |
3856 | } | |
49f7ee80 | 3857 | #define SPEC_in1_f3_o 0 |
2db014b5 | 3858 | |
ad044d09 RH |
3859 | static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o) |
3860 | { | |
3861 | o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1)); | |
3862 | } | |
49f7ee80 | 3863 | #define SPEC_in1_la1 0 |
ad044d09 | 3864 | |
e025e52a RH |
3865 | static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o) |
3866 | { | |
3867 | int x2 = have_field(f, x2) ? get_field(f, x2) : 0; | |
3868 | o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2)); | |
3869 | } | |
49f7ee80 | 3870 | #define SPEC_in1_la2 0 |
e025e52a | 3871 | |
a7e836d5 RH |
3872 | static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o) |
3873 | { | |
3874 | in1_la1(s, f, o); | |
3875 | o->in1 = tcg_temp_new_i64(); | |
3876 | tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s)); | |
3877 | } | |
49f7ee80 | 3878 | #define SPEC_in1_m1_8u 0 |
a7e836d5 RH |
3879 | |
3880 | static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o) | |
3881 | { | |
3882 | in1_la1(s, f, o); | |
3883 | o->in1 = tcg_temp_new_i64(); | |
3884 | tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s)); | |
3885 | } | |
49f7ee80 | 3886 | #define SPEC_in1_m1_16s 0 |
a7e836d5 RH |
3887 | |
3888 | static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o) | |
3889 | { | |
3890 | in1_la1(s, f, o); | |
3891 | o->in1 = tcg_temp_new_i64(); | |
3892 | tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s)); | |
3893 | } | |
49f7ee80 | 3894 | #define SPEC_in1_m1_16u 0 |
a7e836d5 | 3895 | |
ad044d09 RH |
3896 | static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o) |
3897 | { | |
3898 | in1_la1(s, f, o); | |
3899 | o->in1 = tcg_temp_new_i64(); | |
3900 | tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s)); | |
3901 | } | |
49f7ee80 | 3902 | #define SPEC_in1_m1_32s 0 |
ad044d09 | 3903 | |
e272b3ac RH |
3904 | static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o) |
3905 | { | |
3906 | in1_la1(s, f, o); | |
3907 | o->in1 = tcg_temp_new_i64(); | |
3908 | tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s)); | |
3909 | } | |
49f7ee80 | 3910 | #define SPEC_in1_m1_32u 0 |
e272b3ac | 3911 | |
ad044d09 RH |
3912 | static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o) |
3913 | { | |
3914 | in1_la1(s, f, o); | |
3915 | o->in1 = tcg_temp_new_i64(); | |
3916 | tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s)); | |
3917 | } | |
49f7ee80 | 3918 | #define SPEC_in1_m1_64 0 |
ad044d09 RH |
3919 | |
3920 | /* ====================================================================== */ | |
3921 | /* The "INput 2" generators. These load the second operand to an insn. */ | |
3922 | ||
e025e52a RH |
3923 | static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o) |
3924 | { | |
3925 | o->in2 = regs[get_field(f, r1)]; | |
3926 | o->g_in2 = true; | |
3927 | } | |
49f7ee80 | 3928 | #define SPEC_in2_r1_o 0 |
e025e52a RH |
3929 | |
3930 | static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o) | |
3931 | { | |
3932 | o->in2 = tcg_temp_new_i64(); | |
3933 | tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]); | |
3934 | } | |
49f7ee80 | 3935 | #define SPEC_in2_r1_16u 0 |
e025e52a RH |
3936 | |
3937 | static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o) | |
3938 | { | |
3939 | o->in2 = tcg_temp_new_i64(); | |
3940 | tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]); | |
3941 | } | |
49f7ee80 | 3942 | #define SPEC_in2_r1_32u 0 |
e025e52a | 3943 | |
ad044d09 RH |
3944 | static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o) |
3945 | { | |
3946 | o->in2 = load_reg(get_field(f, r2)); | |
3947 | } | |
49f7ee80 | 3948 | #define SPEC_in2_r2 0 |
ad044d09 | 3949 | |
d1c04a2b RH |
3950 | static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o) |
3951 | { | |
3952 | o->in2 = regs[get_field(f, r2)]; | |
3953 | o->g_in2 = true; | |
3954 | } | |
49f7ee80 | 3955 | #define SPEC_in2_r2_o 0 |
d1c04a2b | 3956 | |
8ac33cdb RH |
3957 | static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o) |
3958 | { | |
3959 | int r2 = get_field(f, r2); | |
3960 | if (r2 != 0) { | |
3961 | o->in2 = load_reg(r2); | |
3962 | } | |
3963 | } | |
49f7ee80 | 3964 | #define SPEC_in2_r2_nz 0 |
8ac33cdb | 3965 | |
c698d876 RH |
3966 | static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o) |
3967 | { | |
3968 | o->in2 = tcg_temp_new_i64(); | |
3969 | tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]); | |
3970 | } | |
49f7ee80 | 3971 | #define SPEC_in2_r2_8s 0 |
c698d876 RH |
3972 | |
3973 | static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o) | |
3974 | { | |
3975 | o->in2 = tcg_temp_new_i64(); | |
3976 | tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]); | |
3977 | } | |
49f7ee80 | 3978 | #define SPEC_in2_r2_8u 0 |
c698d876 RH |
3979 | |
3980 | static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o) | |
3981 | { | |
3982 | o->in2 = tcg_temp_new_i64(); | |
3983 | tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]); | |
3984 | } | |
49f7ee80 | 3985 | #define SPEC_in2_r2_16s 0 |
c698d876 RH |
3986 | |
3987 | static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o) | |
3988 | { | |
3989 | o->in2 = tcg_temp_new_i64(); | |
3990 | tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]); | |
3991 | } | |
49f7ee80 | 3992 | #define SPEC_in2_r2_16u 0 |
c698d876 | 3993 | |
ad044d09 RH |
3994 | static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o) |
3995 | { | |
3996 | o->in2 = load_reg(get_field(f, r3)); | |
3997 | } | |
49f7ee80 | 3998 | #define SPEC_in2_r3 0 |
ad044d09 RH |
3999 | |
4000 | static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o) | |
4001 | { | |
4002 | o->in2 = tcg_temp_new_i64(); | |
4003 | tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]); | |
4004 | } | |
49f7ee80 | 4005 | #define SPEC_in2_r2_32s 0 |
ad044d09 RH |
4006 | |
4007 | static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o) | |
4008 | { | |
4009 | o->in2 = tcg_temp_new_i64(); | |
4010 | tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]); | |
4011 | } | |
49f7ee80 | 4012 | #define SPEC_in2_r2_32u 0 |
ad044d09 | 4013 | |
d764a8d1 RH |
4014 | static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o) |
4015 | { | |
4016 | o->in2 = load_freg32_i64(get_field(f, r2)); | |
4017 | } | |
49f7ee80 | 4018 | #define SPEC_in2_e2 0 |
d764a8d1 RH |
4019 | |
4020 | static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o) | |
4021 | { | |
4022 | o->in2 = fregs[get_field(f, r2)]; | |
4023 | o->g_in2 = true; | |
4024 | } | |
49f7ee80 | 4025 | #define SPEC_in2_f2_o 0 |
d764a8d1 RH |
4026 | |
4027 | static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o) | |
4028 | { | |
587626f8 RH |
4029 | int r2 = get_field(f, r2); |
4030 | o->in1 = fregs[r2]; | |
49f7ee80 | 4031 | o->in2 = fregs[r2 + 2]; |
d764a8d1 RH |
4032 | o->g_in1 = o->g_in2 = true; |
4033 | } | |
49f7ee80 | 4034 | #define SPEC_in2_x2_o SPEC_r2_f128 |
d764a8d1 | 4035 | |
374724f9 RH |
4036 | static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o) |
4037 | { | |
4038 | o->in2 = get_address(s, 0, get_field(f, r2), 0); | |
4039 | } | |
49f7ee80 | 4040 | #define SPEC_in2_ra2 0 |
374724f9 | 4041 | |
ad044d09 RH |
4042 | static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o) |
4043 | { | |
4044 | int x2 = have_field(f, x2) ? get_field(f, x2) : 0; | |
4045 | o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2)); | |
4046 | } | |
49f7ee80 | 4047 | #define SPEC_in2_a2 0 |
ad044d09 | 4048 | |
a7e836d5 RH |
4049 | static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o) |
4050 | { | |
4051 | o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2); | |
4052 | } | |
49f7ee80 | 4053 | #define SPEC_in2_ri2 0 |
a7e836d5 | 4054 | |
cbe24bfa RH |
4055 | static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o) |
4056 | { | |
4057 | help_l2_shift(s, f, o, 31); | |
4058 | } | |
49f7ee80 | 4059 | #define SPEC_in2_sh32 0 |
cbe24bfa RH |
4060 | |
4061 | static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o) | |
4062 | { | |
4063 | help_l2_shift(s, f, o, 63); | |
4064 | } | |
49f7ee80 | 4065 | #define SPEC_in2_sh64 0 |
cbe24bfa | 4066 | |
afdc70be RH |
4067 | static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o) |
4068 | { | |
4069 | in2_a2(s, f, o); | |
4070 | tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s)); | |
4071 | } | |
49f7ee80 | 4072 | #define SPEC_in2_m2_8u 0 |
afdc70be | 4073 | |
d82287de RH |
4074 | static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o) |
4075 | { | |
4076 | in2_a2(s, f, o); | |
4077 | tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s)); | |
4078 | } | |
49f7ee80 | 4079 | #define SPEC_in2_m2_16s 0 |
d82287de | 4080 | |
d54f5865 RH |
4081 | static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o) |
4082 | { | |
4083 | in2_a2(s, f, o); | |
4084 | tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s)); | |
4085 | } | |
49f7ee80 | 4086 | #define SPEC_in2_m2_16u 0 |
d54f5865 | 4087 | |
ad044d09 RH |
4088 | static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o) |
4089 | { | |
4090 | in2_a2(s, f, o); | |
4091 | tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s)); | |
4092 | } | |
49f7ee80 | 4093 | #define SPEC_in2_m2_32s 0 |
ad044d09 RH |
4094 | |
4095 | static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o) | |
4096 | { | |
4097 | in2_a2(s, f, o); | |
4098 | tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s)); | |
4099 | } | |
49f7ee80 | 4100 | #define SPEC_in2_m2_32u 0 |
ad044d09 RH |
4101 | |
4102 | static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o) | |
4103 | { | |
4104 | in2_a2(s, f, o); | |
4105 | tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s)); | |
4106 | } | |
49f7ee80 | 4107 | #define SPEC_in2_m2_64 0 |
ad044d09 | 4108 | |
a7e836d5 RH |
4109 | static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o) |
4110 | { | |
4111 | in2_ri2(s, f, o); | |
4112 | tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s)); | |
4113 | } | |
49f7ee80 | 4114 | #define SPEC_in2_mri2_16u 0 |
a7e836d5 RH |
4115 | |
4116 | static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o) | |
4117 | { | |
4118 | in2_ri2(s, f, o); | |
4119 | tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s)); | |
4120 | } | |
49f7ee80 | 4121 | #define SPEC_in2_mri2_32s 0 |
a7e836d5 RH |
4122 | |
4123 | static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o) | |
4124 | { | |
4125 | in2_ri2(s, f, o); | |
4126 | tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s)); | |
4127 | } | |
49f7ee80 | 4128 | #define SPEC_in2_mri2_32u 0 |
a7e836d5 RH |
4129 | |
4130 | static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o) | |
4131 | { | |
4132 | in2_ri2(s, f, o); | |
4133 | tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s)); | |
4134 | } | |
49f7ee80 | 4135 | #define SPEC_in2_mri2_64 0 |
a7e836d5 | 4136 | |
ad044d09 RH |
4137 | static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o) |
4138 | { | |
4139 | o->in2 = tcg_const_i64(get_field(f, i2)); | |
4140 | } | |
49f7ee80 | 4141 | #define SPEC_in2_i2 0 |
ad044d09 | 4142 | |
a7e836d5 RH |
4143 | static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o) |
4144 | { | |
4145 | o->in2 = tcg_const_i64((uint8_t)get_field(f, i2)); | |
4146 | } | |
49f7ee80 | 4147 | #define SPEC_in2_i2_8u 0 |
a7e836d5 RH |
4148 | |
4149 | static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o) | |
4150 | { | |
4151 | o->in2 = tcg_const_i64((uint16_t)get_field(f, i2)); | |
4152 | } | |
49f7ee80 | 4153 | #define SPEC_in2_i2_16u 0 |
a7e836d5 | 4154 | |
ad044d09 RH |
4155 | static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o) |
4156 | { | |
4157 | o->in2 = tcg_const_i64((uint32_t)get_field(f, i2)); | |
4158 | } | |
49f7ee80 | 4159 | #define SPEC_in2_i2_32u 0 |
ad044d09 | 4160 | |
ade9dea4 RH |
4161 | static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o) |
4162 | { | |
4163 | uint64_t i2 = (uint16_t)get_field(f, i2); | |
4164 | o->in2 = tcg_const_i64(i2 << s->insn->data); | |
4165 | } | |
49f7ee80 | 4166 | #define SPEC_in2_i2_16u_shl 0 |
ade9dea4 RH |
4167 | |
4168 | static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o) | |
4169 | { | |
4170 | uint64_t i2 = (uint32_t)get_field(f, i2); | |
4171 | o->in2 = tcg_const_i64(i2 << s->insn->data); | |
4172 | } | |
49f7ee80 | 4173 | #define SPEC_in2_i2_32u_shl 0 |
ade9dea4 | 4174 | |
ad044d09 RH |
4175 | /* ====================================================================== */ |
4176 | ||
4177 | /* Find opc within the table of insns. This is formulated as a switch | |
4178 | statement so that (1) we get compile-time notice of cut-paste errors | |
4179 | for duplicated opcodes, and (2) the compiler generates the binary | |
4180 | search tree, rather than us having to post-process the table. */ | |
4181 | ||
4182 | #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \ | |
4183 | D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0) | |
4184 | ||
4185 | #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM, | |
4186 | ||
4187 | enum DisasInsnEnum { | |
4188 | #include "insn-data.def" | |
4189 | }; | |
4190 | ||
4191 | #undef D | |
49f7ee80 RH |
4192 | #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \ |
4193 | .opc = OPC, \ | |
4194 | .fmt = FMT_##FT, \ | |
4195 | .fac = FAC_##FC, \ | |
4196 | .spec = SPEC_in1_##I1 | SPEC_in2_##I2 | SPEC_prep_##P | SPEC_wout_##W, \ | |
4197 | .name = #NM, \ | |
4198 | .help_in1 = in1_##I1, \ | |
4199 | .help_in2 = in2_##I2, \ | |
4200 | .help_prep = prep_##P, \ | |
4201 | .help_wout = wout_##W, \ | |
4202 | .help_cout = cout_##CC, \ | |
4203 | .help_op = op_##OP, \ | |
4204 | .data = D \ | |
ad044d09 RH |
4205 | }, |
4206 | ||
4207 | /* Allow 0 to be used for NULL in the table below. */ | |
4208 | #define in1_0 NULL | |
4209 | #define in2_0 NULL | |
4210 | #define prep_0 NULL | |
4211 | #define wout_0 NULL | |
4212 | #define cout_0 NULL | |
4213 | #define op_0 NULL | |
4214 | ||
49f7ee80 RH |
4215 | #define SPEC_in1_0 0 |
4216 | #define SPEC_in2_0 0 | |
4217 | #define SPEC_prep_0 0 | |
4218 | #define SPEC_wout_0 0 | |
4219 | ||
ad044d09 RH |
4220 | static const DisasInsn insn_info[] = { |
4221 | #include "insn-data.def" | |
4222 | }; | |
4223 | ||
4224 | #undef D | |
4225 | #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \ | |
4226 | case OPC: return &insn_info[insn_ ## NM]; | |
4227 | ||
4228 | static const DisasInsn *lookup_opc(uint16_t opc) | |
4229 | { | |
4230 | switch (opc) { | |
4231 | #include "insn-data.def" | |
4232 | default: | |
4233 | return NULL; | |
4234 | } | |
4235 | } | |
4236 | ||
4237 | #undef D | |
4238 | #undef C | |
4239 | ||
4240 | /* Extract a field from the insn. The INSN should be left-aligned in | |
4241 | the uint64_t so that we can more easily utilize the big-bit-endian | |
4242 | definitions we extract from the Principals of Operation. */ | |
4243 | ||
4244 | static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn) | |
4245 | { | |
4246 | uint32_t r, m; | |
4247 | ||
4248 | if (f->size == 0) { | |
4249 | return; | |
4250 | } | |
4251 | ||
4252 | /* Zero extract the field from the insn. */ | |
4253 | r = (insn << f->beg) >> (64 - f->size); | |
4254 | ||
4255 | /* Sign-extend, or un-swap the field as necessary. */ | |
4256 | switch (f->type) { | |
4257 | case 0: /* unsigned */ | |
4258 | break; | |
4259 | case 1: /* signed */ | |
4260 | assert(f->size <= 32); | |
4261 | m = 1u << (f->size - 1); | |
4262 | r = (r ^ m) - m; | |
4263 | break; | |
4264 | case 2: /* dl+dh split, signed 20 bit. */ | |
4265 | r = ((int8_t)r << 12) | (r >> 8); | |
4266 | break; | |
4267 | default: | |
4268 | abort(); | |
4269 | } | |
4270 | ||
4271 | /* Validate that the "compressed" encoding we selected above is valid. | |
4272 | I.e. we havn't make two different original fields overlap. */ | |
4273 | assert(((o->presentC >> f->indexC) & 1) == 0); | |
4274 | o->presentC |= 1 << f->indexC; | |
4275 | o->presentO |= 1 << f->indexO; | |
4276 | ||
4277 | o->c[f->indexC] = r; | |
4278 | } | |
4279 | ||
4280 | /* Lookup the insn at the current PC, extracting the operands into O and | |
4281 | returning the info struct for the insn. Returns NULL for invalid insn. */ | |
4282 | ||
4283 | static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s, | |
4284 | DisasFields *f) | |
4285 | { | |
4286 | uint64_t insn, pc = s->pc; | |
d5a103cd | 4287 | int op, op2, ilen; |
ad044d09 RH |
4288 | const DisasInsn *info; |
4289 | ||
4290 | insn = ld_code2(env, pc); | |
4291 | op = (insn >> 8) & 0xff; | |
d5a103cd RH |
4292 | ilen = get_ilen(op); |
4293 | s->next_pc = s->pc + ilen; | |
4294 | ||
4295 | switch (ilen) { | |
4296 | case 2: | |
ad044d09 RH |
4297 | insn = insn << 48; |
4298 | break; | |
d5a103cd | 4299 | case 4: |
ad044d09 RH |
4300 | insn = ld_code4(env, pc) << 32; |
4301 | break; | |
d5a103cd | 4302 | case 6: |
ad044d09 RH |
4303 | insn = (insn << 48) | (ld_code4(env, pc + 2) << 16); |
4304 | break; | |
4305 | default: | |
4306 | abort(); | |
4307 | } | |
4308 | ||
4309 | /* We can't actually determine the insn format until we've looked up | |
4310 | the full insn opcode. Which we can't do without locating the | |
4311 | secondary opcode. Assume by default that OP2 is at bit 40; for | |
4312 | those smaller insns that don't actually have a secondary opcode | |
4313 | this will correctly result in OP2 = 0. */ | |
4314 | switch (op) { | |
4315 | case 0x01: /* E */ | |
4316 | case 0x80: /* S */ | |
4317 | case 0x82: /* S */ | |
4318 | case 0x93: /* S */ | |
4319 | case 0xb2: /* S, RRF, RRE */ | |
4320 | case 0xb3: /* RRE, RRD, RRF */ | |
4321 | case 0xb9: /* RRE, RRF */ | |
4322 | case 0xe5: /* SSE, SIL */ | |
4323 | op2 = (insn << 8) >> 56; | |
4324 | break; | |
4325 | case 0xa5: /* RI */ | |
4326 | case 0xa7: /* RI */ | |
4327 | case 0xc0: /* RIL */ | |
4328 | case 0xc2: /* RIL */ | |
4329 | case 0xc4: /* RIL */ | |
4330 | case 0xc6: /* RIL */ | |
4331 | case 0xc8: /* SSF */ | |
4332 | case 0xcc: /* RIL */ | |
4333 | op2 = (insn << 12) >> 60; | |
4334 | break; | |
4335 | case 0xd0 ... 0xdf: /* SS */ | |
4336 | case 0xe1: /* SS */ | |
4337 | case 0xe2: /* SS */ | |
4338 | case 0xe8: /* SS */ | |
4339 | case 0xe9: /* SS */ | |
4340 | case 0xea: /* SS */ | |
4341 | case 0xee ... 0xf3: /* SS */ | |
4342 | case 0xf8 ... 0xfd: /* SS */ | |
4343 | op2 = 0; | |
4344 | break; | |
4345 | default: | |
4346 | op2 = (insn << 40) >> 56; | |
4347 | break; | |
4348 | } | |
4349 | ||
4350 | memset(f, 0, sizeof(*f)); | |
4351 | f->op = op; | |
4352 | f->op2 = op2; | |
4353 | ||
4354 | /* Lookup the instruction. */ | |
4355 | info = lookup_opc(op << 8 | op2); | |
4356 | ||
4357 | /* If we found it, extract the operands. */ | |
4358 | if (info != NULL) { | |
4359 | DisasFormat fmt = info->fmt; | |
4360 | int i; | |
4361 | ||
4362 | for (i = 0; i < NUM_C_FIELD; ++i) { | |
4363 | extract_field(f, &format_info[fmt].op[i], insn); | |
4364 | } | |
4365 | } | |
4366 | return info; | |
4367 | } | |
4368 | ||
4369 | static ExitStatus translate_one(CPUS390XState *env, DisasContext *s) | |
4370 | { | |
4371 | const DisasInsn *insn; | |
4372 | ExitStatus ret = NO_EXIT; | |
4373 | DisasFields f; | |
4374 | DisasOps o; | |
4375 | ||
4f3adfb2 | 4376 | /* Search for the insn in the table. */ |
ad044d09 | 4377 | insn = extract_insn(env, s, &f); |
e023e832 | 4378 | |
4f3adfb2 | 4379 | /* Not found means unimplemented/illegal opcode. */ |
ad044d09 | 4380 | if (insn == NULL) { |
4f3adfb2 RH |
4381 | qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n", |
4382 | f.op, f.op2); | |
4383 | gen_illegal_opcode(s); | |
4384 | return EXIT_NORETURN; | |
ad044d09 RH |
4385 | } |
4386 | ||
49f7ee80 RH |
4387 | /* Check for insn specification exceptions. */ |
4388 | if (insn->spec) { | |
4389 | int spec = insn->spec, excp = 0, r; | |
4390 | ||
4391 | if (spec & SPEC_r1_even) { | |
4392 | r = get_field(&f, r1); | |
4393 | if (r & 1) { | |
4394 | excp = PGM_SPECIFICATION; | |
4395 | } | |
4396 | } | |
4397 | if (spec & SPEC_r2_even) { | |
4398 | r = get_field(&f, r2); | |
4399 | if (r & 1) { | |
4400 | excp = PGM_SPECIFICATION; | |
4401 | } | |
4402 | } | |
4403 | if (spec & SPEC_r1_f128) { | |
4404 | r = get_field(&f, r1); | |
4405 | if (r > 13) { | |
4406 | excp = PGM_SPECIFICATION; | |
4407 | } | |
4408 | } | |
4409 | if (spec & SPEC_r2_f128) { | |
4410 | r = get_field(&f, r2); | |
4411 | if (r > 13) { | |
4412 | excp = PGM_SPECIFICATION; | |
4413 | } | |
4414 | } | |
4415 | if (excp) { | |
4416 | gen_program_exception(s, excp); | |
4417 | return EXIT_NORETURN; | |
4418 | } | |
4419 | } | |
4420 | ||
ad044d09 RH |
4421 | /* Set up the strutures we use to communicate with the helpers. */ |
4422 | s->insn = insn; | |
4423 | s->fields = &f; | |
4424 | o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false; | |
4425 | TCGV_UNUSED_I64(o.out); | |
4426 | TCGV_UNUSED_I64(o.out2); | |
4427 | TCGV_UNUSED_I64(o.in1); | |
4428 | TCGV_UNUSED_I64(o.in2); | |
4429 | TCGV_UNUSED_I64(o.addr1); | |
4430 | ||
4431 | /* Implement the instruction. */ | |
4432 | if (insn->help_in1) { | |
4433 | insn->help_in1(s, &f, &o); | |
4434 | } | |
4435 | if (insn->help_in2) { | |
4436 | insn->help_in2(s, &f, &o); | |
4437 | } | |
4438 | if (insn->help_prep) { | |
4439 | insn->help_prep(s, &f, &o); | |
4440 | } | |
4441 | if (insn->help_op) { | |
4442 | ret = insn->help_op(s, &o); | |
4443 | } | |
4444 | if (insn->help_wout) { | |
4445 | insn->help_wout(s, &f, &o); | |
4446 | } | |
4447 | if (insn->help_cout) { | |
4448 | insn->help_cout(s, &o); | |
4449 | } | |
4450 | ||
4451 | /* Free any temporaries created by the helpers. */ | |
4452 | if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) { | |
4453 | tcg_temp_free_i64(o.out); | |
4454 | } | |
4455 | if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) { | |
4456 | tcg_temp_free_i64(o.out2); | |
4457 | } | |
4458 | if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) { | |
4459 | tcg_temp_free_i64(o.in1); | |
4460 | } | |
4461 | if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) { | |
4462 | tcg_temp_free_i64(o.in2); | |
4463 | } | |
4464 | if (!TCGV_IS_UNUSED_I64(o.addr1)) { | |
4465 | tcg_temp_free_i64(o.addr1); | |
4466 | } | |
4467 | ||
4468 | /* Advance to the next instruction. */ | |
4469 | s->pc = s->next_pc; | |
4470 | return ret; | |
e023e832 AG |
4471 | } |
4472 | ||
a4e3ad19 | 4473 | static inline void gen_intermediate_code_internal(CPUS390XState *env, |
e023e832 AG |
4474 | TranslationBlock *tb, |
4475 | int search_pc) | |
4476 | { | |
4477 | DisasContext dc; | |
4478 | target_ulong pc_start; | |
4479 | uint64_t next_page_start; | |
4480 | uint16_t *gen_opc_end; | |
4481 | int j, lj = -1; | |
4482 | int num_insns, max_insns; | |
4483 | CPUBreakpoint *bp; | |
ad044d09 | 4484 | ExitStatus status; |
d5a103cd | 4485 | bool do_debug; |
e023e832 AG |
4486 | |
4487 | pc_start = tb->pc; | |
4488 | ||
4489 | /* 31-bit mode */ | |
4490 | if (!(tb->flags & FLAG_MASK_64)) { | |
4491 | pc_start &= 0x7fffffff; | |
4492 | } | |
4493 | ||
e023e832 | 4494 | dc.tb = tb; |
ad044d09 | 4495 | dc.pc = pc_start; |
e023e832 | 4496 | dc.cc_op = CC_OP_DYNAMIC; |
d5a103cd | 4497 | do_debug = dc.singlestep_enabled = env->singlestep_enabled; |
e023e832 | 4498 | |
92414b31 | 4499 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
e023e832 AG |
4500 | |
4501 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
4502 | ||
4503 | num_insns = 0; | |
4504 | max_insns = tb->cflags & CF_COUNT_MASK; | |
4505 | if (max_insns == 0) { | |
4506 | max_insns = CF_COUNT_MASK; | |
4507 | } | |
4508 | ||
4509 | gen_icount_start(); | |
4510 | ||
4511 | do { | |
e023e832 | 4512 | if (search_pc) { |
92414b31 | 4513 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
e023e832 AG |
4514 | if (lj < j) { |
4515 | lj++; | |
4516 | while (lj < j) { | |
ab1103de | 4517 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
e023e832 AG |
4518 | } |
4519 | } | |
25983cad | 4520 | tcg_ctx.gen_opc_pc[lj] = dc.pc; |
e023e832 | 4521 | gen_opc_cc_op[lj] = dc.cc_op; |
ab1103de | 4522 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 4523 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
e023e832 | 4524 | } |
ad044d09 | 4525 | if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
e023e832 AG |
4526 | gen_io_start(); |
4527 | } | |
7193b5f6 RH |
4528 | |
4529 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { | |
4530 | tcg_gen_debug_insn_start(dc.pc); | |
4531 | } | |
4532 | ||
d5a103cd RH |
4533 | status = NO_EXIT; |
4534 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { | |
4535 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
4536 | if (bp->pc == dc.pc) { | |
4537 | status = EXIT_PC_STALE; | |
4538 | do_debug = true; | |
4539 | break; | |
4540 | } | |
4541 | } | |
4542 | } | |
4543 | if (status == NO_EXIT) { | |
4544 | status = translate_one(env, &dc); | |
4545 | } | |
ad044d09 RH |
4546 | |
4547 | /* If we reach a page boundary, are single stepping, | |
4548 | or exhaust instruction count, stop generation. */ | |
4549 | if (status == NO_EXIT | |
4550 | && (dc.pc >= next_page_start | |
4551 | || tcg_ctx.gen_opc_ptr >= gen_opc_end | |
4552 | || num_insns >= max_insns | |
4553 | || singlestep | |
4554 | || env->singlestep_enabled)) { | |
4555 | status = EXIT_PC_STALE; | |
e023e832 | 4556 | } |
ad044d09 | 4557 | } while (status == NO_EXIT); |
e023e832 AG |
4558 | |
4559 | if (tb->cflags & CF_LAST_IO) { | |
4560 | gen_io_end(); | |
4561 | } | |
ad044d09 RH |
4562 | |
4563 | switch (status) { | |
4564 | case EXIT_GOTO_TB: | |
4565 | case EXIT_NORETURN: | |
4566 | break; | |
4567 | case EXIT_PC_STALE: | |
4568 | update_psw_addr(&dc); | |
4569 | /* FALLTHRU */ | |
4570 | case EXIT_PC_UPDATED: | |
7a6c7067 RH |
4571 | /* Next TB starts off with CC_OP_DYNAMIC, so make sure the |
4572 | cc op type is in env */ | |
4573 | update_cc_op(&dc); | |
4574 | /* Exit the TB, either by raising a debug exception or by return. */ | |
d5a103cd RH |
4575 | if (do_debug) { |
4576 | gen_exception(EXCP_DEBUG); | |
ad044d09 | 4577 | } else { |
ad044d09 RH |
4578 | tcg_gen_exit_tb(0); |
4579 | } | |
4580 | break; | |
4581 | default: | |
4582 | abort(); | |
e023e832 | 4583 | } |
ad044d09 | 4584 | |
e023e832 | 4585 | gen_icount_end(tb, num_insns); |
efd7f486 | 4586 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
e023e832 | 4587 | if (search_pc) { |
92414b31 | 4588 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
e023e832 AG |
4589 | lj++; |
4590 | while (lj <= j) { | |
ab1103de | 4591 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
e023e832 AG |
4592 | } |
4593 | } else { | |
4594 | tb->size = dc.pc - pc_start; | |
4595 | tb->icount = num_insns; | |
4596 | } | |
ad044d09 | 4597 | |
e023e832 | 4598 | #if defined(S390X_DEBUG_DISAS) |
e023e832 AG |
4599 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
4600 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
f4359b9f | 4601 | log_target_disas(env, pc_start, dc.pc - pc_start, 1); |
e023e832 AG |
4602 | qemu_log("\n"); |
4603 | } | |
4604 | #endif | |
4605 | } | |
4606 | ||
a4e3ad19 | 4607 | void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb) |
e023e832 AG |
4608 | { |
4609 | gen_intermediate_code_internal(env, tb, 0); | |
4610 | } | |
4611 | ||
a4e3ad19 | 4612 | void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb) |
e023e832 AG |
4613 | { |
4614 | gen_intermediate_code_internal(env, tb, 1); | |
4615 | } | |
4616 | ||
a4e3ad19 | 4617 | void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos) |
e023e832 AG |
4618 | { |
4619 | int cc_op; | |
25983cad | 4620 | env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos]; |
e023e832 AG |
4621 | cc_op = gen_opc_cc_op[pc_pos]; |
4622 | if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) { | |
4623 | env->cc_op = cc_op; | |
4624 | } | |
10ec5117 | 4625 | } |