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fdf9b3e8 FB |
1 | /* |
2 | * SH4 emulation | |
5fafdf24 | 3 | * |
fdf9b3e8 FB |
4 | * Copyright (c) 2005 Samuel Tardieu |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #ifndef _CPU_SH4_H | |
21 | #define _CPU_SH4_H | |
22 | ||
23 | #include "config.h" | |
24 | ||
25 | #define TARGET_LONG_BITS 32 | |
26 | #define TARGET_HAS_ICE 1 | |
27 | ||
9042c0e2 TS |
28 | #define ELF_MACHINE EM_SH |
29 | ||
0fd3ca30 AJ |
30 | /* CPU Subtypes */ |
31 | #define SH_CPU_SH7750 (1 << 0) | |
32 | #define SH_CPU_SH7750S (1 << 1) | |
33 | #define SH_CPU_SH7750R (1 << 2) | |
34 | #define SH_CPU_SH7751 (1 << 3) | |
35 | #define SH_CPU_SH7751R (1 << 4) | |
36 | #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) | |
37 | #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) | |
38 | ||
fdf9b3e8 FB |
39 | #include "cpu-defs.h" |
40 | ||
eda9b09b FB |
41 | #include "softfloat.h" |
42 | ||
fdf9b3e8 FB |
43 | #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ |
44 | ||
45 | #define SR_MD (1 << 30) | |
46 | #define SR_RB (1 << 29) | |
47 | #define SR_BL (1 << 28) | |
48 | #define SR_FD (1 << 15) | |
49 | #define SR_M (1 << 9) | |
50 | #define SR_Q (1 << 8) | |
51 | #define SR_S (1 << 1) | |
52 | #define SR_T (1 << 0) | |
53 | ||
54 | #define FPSCR_FR (1 << 21) | |
55 | #define FPSCR_SZ (1 << 20) | |
56 | #define FPSCR_PR (1 << 19) | |
57 | #define FPSCR_DN (1 << 18) | |
823029f9 | 58 | #define DELAY_SLOT (1 << 0) |
fdf9b3e8 | 59 | #define DELAY_SLOT_CONDITIONAL (1 << 1) |
823029f9 TS |
60 | #define DELAY_SLOT_TRUE (1 << 2) |
61 | #define DELAY_SLOT_CLEARME (1 << 3) | |
62 | /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump | |
63 | * after the delay slot should be taken or not. It is calculated from SR_T. | |
64 | * | |
65 | * It is unclear if it is permitted to modify the SR_T flag in a delay slot. | |
66 | * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification. | |
67 | */ | |
fdf9b3e8 FB |
68 | |
69 | /* XXXXX The structure could be made more compact */ | |
70 | typedef struct tlb_t { | |
71 | uint8_t asid; /* address space identifier */ | |
72 | uint32_t vpn; /* virtual page number */ | |
73 | uint8_t v; /* validity */ | |
74 | uint32_t ppn; /* physical page number */ | |
75 | uint8_t sz; /* page size */ | |
76 | uint32_t size; /* cached page size in bytes */ | |
77 | uint8_t sh; /* share status */ | |
78 | uint8_t c; /* cacheability */ | |
79 | uint8_t pr; /* protection key */ | |
80 | uint8_t d; /* dirty */ | |
81 | uint8_t wt; /* write through */ | |
82 | uint8_t sa; /* space attribute (PCMCIA) */ | |
83 | uint8_t tc; /* timing control */ | |
84 | } tlb_t; | |
85 | ||
86 | #define UTLB_SIZE 64 | |
87 | #define ITLB_SIZE 4 | |
88 | ||
6ebbf390 JM |
89 | #define NB_MMU_MODES 2 |
90 | ||
fdf9b3e8 | 91 | typedef struct CPUSH4State { |
0fd3ca30 AJ |
92 | int id; /* CPU model */ |
93 | ||
fdf9b3e8 FB |
94 | uint32_t flags; /* general execution flags */ |
95 | uint32_t gregs[24]; /* general registers */ | |
e04ea3dc | 96 | float32 fregs[32]; /* floating point registers */ |
fdf9b3e8 FB |
97 | uint32_t sr; /* status register */ |
98 | uint32_t ssr; /* saved status register */ | |
99 | uint32_t spc; /* saved program counter */ | |
100 | uint32_t gbr; /* global base register */ | |
101 | uint32_t vbr; /* vector base register */ | |
102 | uint32_t sgr; /* saved global register 15 */ | |
103 | uint32_t dbr; /* debug base register */ | |
104 | uint32_t pc; /* program counter */ | |
105 | uint32_t delayed_pc; /* target of delayed jump */ | |
106 | uint32_t mach; /* multiply and accumulate high */ | |
107 | uint32_t macl; /* multiply and accumulate low */ | |
108 | uint32_t pr; /* procedure register */ | |
109 | uint32_t fpscr; /* floating point status/control register */ | |
110 | uint32_t fpul; /* floating point communication register */ | |
111 | ||
17b086f7 | 112 | /* float point status register */ |
ea6cf6be | 113 | float_status fp_status; |
eda9b09b | 114 | |
fdf9b3e8 FB |
115 | /* Those belong to the specific unit (SH7750) but are handled here */ |
116 | uint32_t mmucr; /* MMU control register */ | |
117 | uint32_t pteh; /* page table entry high register */ | |
118 | uint32_t ptel; /* page table entry low register */ | |
119 | uint32_t ptea; /* page table entry assistance register */ | |
120 | uint32_t ttb; /* tranlation table base register */ | |
121 | uint32_t tea; /* TLB exception address register */ | |
122 | uint32_t tra; /* TRAPA exception register */ | |
123 | uint32_t expevt; /* exception event register */ | |
124 | uint32_t intevt; /* interrupt event register */ | |
125 | ||
0fd3ca30 AJ |
126 | uint32_t pvr; /* Processor Version Register */ |
127 | uint32_t prr; /* Processor Revision Register */ | |
128 | uint32_t cvr; /* Cache Version Register */ | |
129 | ||
fdf9b3e8 FB |
130 | CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */ |
131 | tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ | |
e96e2044 | 132 | void *intc_handle; |
833ed386 | 133 | int intr_at_halt; /* SR_BL ignored during sleep */ |
fdf9b3e8 FB |
134 | } CPUSH4State; |
135 | ||
aaed909a | 136 | CPUSH4State *cpu_sh4_init(const char *cpu_model); |
fdf9b3e8 | 137 | int cpu_sh4_exec(CPUSH4State * s); |
5fafdf24 | 138 | int cpu_sh4_signal_handler(int host_signum, void *pinfo, |
5a7b542b | 139 | void *puc); |
0fd3ca30 | 140 | void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
29e179bc AJ |
141 | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, |
142 | uint32_t mem_value); | |
fdf9b3e8 | 143 | |
0b6d3ae0 AJ |
144 | static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls) |
145 | { | |
146 | env->gbr = newtls; | |
147 | } | |
148 | ||
fdf9b3e8 FB |
149 | #include "softfloat.h" |
150 | ||
9467d44c TS |
151 | #define CPUState CPUSH4State |
152 | #define cpu_init cpu_sh4_init | |
153 | #define cpu_exec cpu_sh4_exec | |
154 | #define cpu_gen_code cpu_sh4_gen_code | |
155 | #define cpu_signal_handler cpu_sh4_signal_handler | |
0fd3ca30 | 156 | #define cpu_list sh4_cpu_list |
9467d44c | 157 | |
6ebbf390 JM |
158 | /* MMU modes definitions */ |
159 | #define MMU_MODE0_SUFFIX _kernel | |
160 | #define MMU_MODE1_SUFFIX _user | |
161 | #define MMU_USER_IDX 1 | |
162 | static inline int cpu_mmu_index (CPUState *env) | |
163 | { | |
164 | return (env->sr & SR_MD) == 0 ? 1 : 0; | |
165 | } | |
166 | ||
6e68e076 PB |
167 | #if defined(CONFIG_USER_ONLY) |
168 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) | |
169 | { | |
f8ed7070 | 170 | if (newsp) |
6e68e076 PB |
171 | env->gregs[15] = newsp; |
172 | env->gregs[0] = 0; | |
173 | } | |
174 | #endif | |
175 | ||
fdf9b3e8 | 176 | #include "cpu-all.h" |
622ed360 | 177 | #include "exec-all.h" |
fdf9b3e8 FB |
178 | |
179 | /* Memory access type */ | |
180 | enum { | |
181 | /* Privilege */ | |
182 | ACCESS_PRIV = 0x01, | |
183 | /* Direction */ | |
184 | ACCESS_WRITE = 0x02, | |
185 | /* Type of instruction */ | |
186 | ACCESS_CODE = 0x10, | |
187 | ACCESS_INT = 0x20 | |
188 | }; | |
189 | ||
190 | /* MMU control register */ | |
191 | #define MMUCR 0x1F000010 | |
192 | #define MMUCR_AT (1<<0) | |
193 | #define MMUCR_SV (1<<8) | |
ea2b542a AJ |
194 | #define MMUCR_URC_BITS (6) |
195 | #define MMUCR_URC_OFFSET (10) | |
196 | #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) | |
197 | #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) | |
198 | static inline int cpu_mmucr_urc (uint32_t mmucr) | |
199 | { | |
200 | return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET); | |
201 | } | |
202 | ||
203 | /* PTEH : Page Translation Entry High register */ | |
204 | #define PTEH_ASID_BITS (8) | |
205 | #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) | |
206 | #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) | |
207 | #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK) | |
208 | #define PTEH_VPN_BITS (22) | |
209 | #define PTEH_VPN_OFFSET (10) | |
210 | #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) | |
211 | #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) | |
212 | static inline int cpu_pteh_vpn (uint32_t pteh) | |
213 | { | |
214 | return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET); | |
215 | } | |
216 | ||
217 | /* PTEL : Page Translation Entry Low register */ | |
218 | #define PTEL_V (1 << 8) | |
219 | #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) | |
220 | #define PTEL_C (1 << 3) | |
221 | #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) | |
222 | #define PTEL_D (1 << 2) | |
223 | #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) | |
224 | #define PTEL_SH (1 << 1) | |
225 | #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) | |
226 | #define PTEL_WT (1 << 0) | |
227 | #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT) | |
228 | ||
229 | #define PTEL_SZ_HIGH_OFFSET (7) | |
230 | #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) | |
231 | #define PTEL_SZ_LOW_OFFSET (4) | |
232 | #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) | |
233 | static inline int cpu_ptel_sz (uint32_t ptel) | |
234 | { | |
235 | int sz; | |
236 | sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; | |
237 | sz <<= 1; | |
238 | sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; | |
239 | return sz; | |
240 | } | |
241 | ||
242 | #define PTEL_PPN_BITS (19) | |
243 | #define PTEL_PPN_OFFSET (10) | |
244 | #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) | |
245 | #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) | |
246 | static inline int cpu_ptel_ppn (uint32_t ptel) | |
247 | { | |
248 | return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET); | |
249 | } | |
250 | ||
251 | #define PTEL_PR_BITS (2) | |
252 | #define PTEL_PR_OFFSET (5) | |
253 | #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) | |
254 | #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) | |
255 | static inline int cpu_ptel_pr (uint32_t ptel) | |
256 | { | |
257 | return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET); | |
258 | } | |
259 | ||
260 | /* PTEA : Page Translation Entry Assistance register */ | |
261 | #define PTEA_SA_BITS (3) | |
262 | #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) | |
263 | #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) | |
264 | #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK) | |
265 | #define PTEA_TC (1 << 3) | |
266 | #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) | |
fdf9b3e8 | 267 | |
622ed360 AL |
268 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
269 | { | |
270 | env->pc = tb->pc; | |
271 | env->flags = tb->flags; | |
272 | } | |
273 | ||
6b917547 AL |
274 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
275 | target_ulong *cs_base, int *flags) | |
276 | { | |
277 | *pc = env->pc; | |
278 | *cs_base = 0; | |
279 | *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL | |
280 | | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */ | |
281 | | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */ | |
282 | | (env->sr & (SR_MD | SR_RB)); /* Bits 29-30 */ | |
283 | } | |
284 | ||
fdf9b3e8 | 285 | #endif /* _CPU_SH4_H */ |