[qemu.git] / target-sh4 / cpu.h

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef _CPU_SH4_H
#define _CPU_SH4_H

#include "config.h"

#define TARGET_LONG_BITS 32
#define TARGET_HAS_ICE 1

#define ELF_MACHINE	EM_SH

/* CPU Subtypes */
#define SH_CPU_SH7750  (1 << 0)
#define SH_CPU_SH7750S (1 << 1)
#define SH_CPU_SH7750R (1 << 2)
#define SH_CPU_SH7751  (1 << 3)
#define SH_CPU_SH7751R (1 << 4)
#define SH_CPU_SH7785  (1 << 5)
#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)

#define CPUState struct CPUSH4State

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_PAGE_BITS 12	/* 4k XXXXX */

#define SR_MD (1 << 30)
#define SR_RB (1 << 29)
#define SR_BL (1 << 28)
#define SR_FD (1 << 15)
#define SR_M  (1 << 9)
#define SR_Q  (1 << 8)
#define SR_I3 (1 << 7)
#define SR_I2 (1 << 6)
#define SR_I1 (1 << 5)
#define SR_I0 (1 << 4)
#define SR_S  (1 << 1)
#define SR_T  (1 << 0)

#define FPSCR_FR (1 << 21)
#define FPSCR_SZ (1 << 20)
#define FPSCR_PR (1 << 19)
#define FPSCR_DN (1 << 18)
#define DELAY_SLOT             (1 << 0)
#define DELAY_SLOT_CONDITIONAL (1 << 1)
#define DELAY_SLOT_TRUE        (1 << 2)
#define DELAY_SLOT_CLEARME     (1 << 3)
/* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
 * after the delay slot should be taken or not. It is calculated from SR_T.
 *
 * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
 */

typedef struct tlb_t {
    uint32_t vpn;		/* virtual page number */
    uint32_t ppn;		/* physical page number */
    uint32_t size;		/* mapped page size in bytes */
    uint8_t asid;		/* address space identifier */
    uint8_t v:1;		/* validity */
    uint8_t sz:2;		/* page size */
    uint8_t sh:1;		/* share status */
    uint8_t c:1;		/* cacheability */
    uint8_t pr:2;		/* protection key */
    uint8_t d:1;		/* dirty */
    uint8_t wt:1;		/* write through */
    uint8_t sa:3;		/* space attribute (PCMCIA) */
    uint8_t tc:1;		/* timing control */
} tlb_t;

#define UTLB_SIZE 64
#define ITLB_SIZE 4

#define NB_MMU_MODES 2

enum sh_features {
    SH_FEATURE_SH4A = 1,
    SH_FEATURE_BCR3_AND_BCR4 = 2,
};

typedef struct memory_content {
    uint32_t address;
    uint32_t value;
    struct memory_content *next;
} memory_content;

typedef struct CPUSH4State {
    int id;			/* CPU model */

    uint32_t flags;		/* general execution flags */
    uint32_t gregs[24];		/* general registers */
    float32 fregs[32];		/* floating point registers */
    uint32_t sr;		/* status register */
    uint32_t ssr;		/* saved status register */
    uint32_t spc;		/* saved program counter */
    uint32_t gbr;		/* global base register */
    uint32_t vbr;		/* vector base register */
    uint32_t sgr;		/* saved global register 15 */
    uint32_t dbr;		/* debug base register */
    uint32_t pc;		/* program counter */
    uint32_t delayed_pc;	/* target of delayed jump */
    uint32_t mach;		/* multiply and accumulate high */
    uint32_t macl;		/* multiply and accumulate low */
    uint32_t pr;		/* procedure register */
    uint32_t fpscr;		/* floating point status/control register */
    uint32_t fpul;		/* floating point communication register */

    /* float point status register */
    float_status fp_status;

    /* The features that we should emulate. See sh_features above.  */
    uint32_t features;

    /* Those belong to the specific unit (SH7750) but are handled here */
    uint32_t mmucr;		/* MMU control register */
    uint32_t pteh;		/* page table entry high register */
    uint32_t ptel;		/* page table entry low register */
    uint32_t ptea;		/* page table entry assistance register */
    uint32_t ttb;		/* tranlation table base register */
    uint32_t tea;		/* TLB exception address register */
    uint32_t tra;		/* TRAPA exception register */
    uint32_t expevt;		/* exception event register */
    uint32_t intevt;		/* interrupt event register */

    uint32_t pvr;		/* Processor Version Register */
    uint32_t prr;		/* Processor Revision Register */
    uint32_t cvr;		/* Cache Version Register */

    uint32_t ldst;

     CPU_COMMON tlb_t utlb[UTLB_SIZE];	/* unified translation table */
    tlb_t itlb[ITLB_SIZE];	/* instruction translation table */
    void *intc_handle;
    int intr_at_halt;		/* SR_BL ignored during sleep */
    memory_content *movcal_backup;
    memory_content **movcal_backup_tail;
} CPUSH4State;

CPUSH4State *cpu_sh4_init(const char *cpu_model);
int cpu_sh4_exec(CPUSH4State * s);
int cpu_sh4_signal_handler(int host_signum, void *pinfo,
                           void *puc);
int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu);
#define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
void do_interrupt(CPUSH4State * env);

void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
void cpu_sh4_invalidate_tlb(CPUSH4State *s);
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
				    uint32_t mem_value);

int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);

static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
{
  env->gbr = newtls;
}

void cpu_load_tlb(CPUSH4State * env);

#include "softfloat.h"

#define cpu_init cpu_sh4_init
#define cpu_exec cpu_sh4_exec
#define cpu_gen_code cpu_sh4_gen_code
#define cpu_signal_handler cpu_sh4_signal_handler
#define cpu_list sh4_cpu_list

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env)
{
    return (env->sr & SR_MD) == 0 ? 1 : 0;
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
    if (newsp)
        env->gregs[15] = newsp;
    env->gregs[0] = 0;
}
#endif

#include "cpu-all.h"
#include "exec-all.h"

/* Memory access type */
enum {
    /* Privilege */
    ACCESS_PRIV = 0x01,
    /* Direction */
    ACCESS_WRITE = 0x02,
    /* Type of instruction */
    ACCESS_CODE = 0x10,
    ACCESS_INT = 0x20
};

/* MMU control register */
#define MMUCR    0x1F000010
#define MMUCR_AT (1<<0)
#define MMUCR_TI (1<<2)
#define MMUCR_SV (1<<8)
#define MMUCR_URC_BITS (6)
#define MMUCR_URC_OFFSET (10)
#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
static inline int cpu_mmucr_urc (uint32_t mmucr)
{
    return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
}

/* PTEH : Page Translation Entry High register */
#define PTEH_ASID_BITS (8)
#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
#define PTEH_VPN_BITS (22)
#define PTEH_VPN_OFFSET (10)
#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
static inline int cpu_pteh_vpn (uint32_t pteh)
{
    return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
}

/* PTEL : Page Translation Entry Low register */
#define PTEL_V        (1 << 8)
#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
#define PTEL_C        (1 << 3)
#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
#define PTEL_D        (1 << 2)
#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
#define PTEL_SH       (1 << 1)
#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
#define PTEL_WT       (1 << 0)
#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)

#define PTEL_SZ_HIGH_OFFSET  (7)
#define PTEL_SZ_HIGH  (1 << PTEL_SZ_HIGH_OFFSET)
#define PTEL_SZ_LOW_OFFSET   (4)
#define PTEL_SZ_LOW   (1 << PTEL_SZ_LOW_OFFSET)
static inline int cpu_ptel_sz (uint32_t ptel)
{
    int sz;
    sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
    sz <<= 1;
    sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
    return sz;
}

#define PTEL_PPN_BITS (19)
#define PTEL_PPN_OFFSET (10)
#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
static inline int cpu_ptel_ppn (uint32_t ptel)
{
    return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
}

#define PTEL_PR_BITS   (2)
#define PTEL_PR_OFFSET (5)
#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
static inline int cpu_ptel_pr (uint32_t ptel)
{
    return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
}

/* PTEA : Page Translation Entry Assistance register */
#define PTEA_SA_BITS (3)
#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
#define PTEA_TC        (1 << 3)
#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)

static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
    env->flags = tb->flags;
}

#define TB_FLAG_PENDING_MOVCA  (1 << 4)

static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
                    | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME))   /* Bits  0- 3 */
            | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */
            | (env->sr & (SR_MD | SR_RB))                      /* Bits 29-30 */
            | (env->sr & SR_FD)                                /* Bit 15 */
            | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
}

#endif				/* _CPU_SH4_H */
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
fdf9b3e8 FB	18	*/
	19	#ifndef _CPU_SH4_H
	20	#define _CPU_SH4_H
	21
	22	#include "config.h"
	23
	24	#define TARGET_LONG_BITS 32
	25	#define TARGET_HAS_ICE 1
	26
9042c0e2 TS	27	#define ELF_MACHINE EM_SH
9042c0e2 TS	28
0fd3ca30 AJ	29	/* CPU Subtypes */
	30	#define SH_CPU_SH7750 (1 << 0)
	31	#define SH_CPU_SH7750S (1 << 1)
	32	#define SH_CPU_SH7750R (1 << 2)
	33	#define SH_CPU_SH7751 (1 << 3)
	34	#define SH_CPU_SH7751R (1 << 4)
a9c43f8e	35	#define SH_CPU_SH7785 (1 << 5)
0fd3ca30 AJ	36	#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 \| SH_CPU_SH7750S \| SH_CPU_SH7750R)
	37	#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 \| SH_CPU_SH7751R)
	38
c2764719 PB	39	#define CPUState struct CPUSH4State
c2764719 PB	40
fdf9b3e8 FB	41	#include "cpu-defs.h"
fdf9b3e8 FB	42
eda9b09b FB	43	#include "softfloat.h"
eda9b09b FB	44
fdf9b3e8 FB	45	#define TARGET_PAGE_BITS 12 /* 4k XXXXX */
	46
	47	#define SR_MD (1 << 30)
	48	#define SR_RB (1 << 29)
	49	#define SR_BL (1 << 28)
	50	#define SR_FD (1 << 15)
	51	#define SR_M (1 << 9)
	52	#define SR_Q (1 << 8)
56cd2b96 AJ	53	#define SR_I3 (1 << 7)
	54	#define SR_I2 (1 << 6)
	55	#define SR_I1 (1 << 5)
	56	#define SR_I0 (1 << 4)
fdf9b3e8 FB	57	#define SR_S (1 << 1)
	58	#define SR_T (1 << 0)
	59
	60	#define FPSCR_FR (1 << 21)
	61	#define FPSCR_SZ (1 << 20)
	62	#define FPSCR_PR (1 << 19)
	63	#define FPSCR_DN (1 << 18)
823029f9	64	#define DELAY_SLOT (1 << 0)
fdf9b3e8	65	#define DELAY_SLOT_CONDITIONAL (1 << 1)
823029f9 TS	66	#define DELAY_SLOT_TRUE (1 << 2)
	67	#define DELAY_SLOT_CLEARME (1 << 3)
	68	/* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
	69	* after the delay slot should be taken or not. It is calculated from SR_T.
	70	*
	71	* It is unclear if it is permitted to modify the SR_T flag in a delay slot.
	72	* The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
	73	*/
fdf9b3e8	74
fdf9b3e8	75	typedef struct tlb_t {
fdf9b3e8	76	uint32_t vpn; /* virtual page number */
fdf9b3e8	77	uint32_t ppn; /* physical page number */
af090497 AJ	78	uint32_t size; /* mapped page size in bytes */
	79	uint8_t asid; /* address space identifier */
	80	uint8_t v:1; /* validity */
	81	uint8_t sz:2; /* page size */
	82	uint8_t sh:1; /* share status */
	83	uint8_t c:1; /* cacheability */
	84	uint8_t pr:2; /* protection key */
	85	uint8_t d:1; /* dirty */
	86	uint8_t wt:1; /* write through */
	87	uint8_t sa:3; /* space attribute (PCMCIA) */
	88	uint8_t tc:1; /* timing control */
fdf9b3e8 FB	89	} tlb_t;
	90
	91	#define UTLB_SIZE 64
	92	#define ITLB_SIZE 4
	93
6ebbf390 JM	94	#define NB_MMU_MODES 2
6ebbf390 JM	95
71968fa6 AJ	96	enum sh_features {
71968fa6 AJ	97	SH_FEATURE_SH4A = 1,
c2432a42	98	SH_FEATURE_BCR3_AND_BCR4 = 2,
71968fa6 AJ	99	};
71968fa6 AJ	100
852d481f EI	101	typedef struct memory_content {
	102	uint32_t address;
	103	uint32_t value;
	104	struct memory_content *next;
	105	} memory_content;
	106
fdf9b3e8	107	typedef struct CPUSH4State {
0fd3ca30 AJ	108	int id; /* CPU model */
0fd3ca30 AJ	109
fdf9b3e8 FB	110	uint32_t flags; /* general execution flags */
fdf9b3e8 FB	111	uint32_t gregs[24]; /* general registers */
e04ea3dc	112	float32 fregs[32]; /* floating point registers */
fdf9b3e8 FB	113	uint32_t sr; /* status register */
	114	uint32_t ssr; /* saved status register */
	115	uint32_t spc; /* saved program counter */
	116	uint32_t gbr; /* global base register */
	117	uint32_t vbr; /* vector base register */
	118	uint32_t sgr; /* saved global register 15 */
	119	uint32_t dbr; /* debug base register */
	120	uint32_t pc; /* program counter */
	121	uint32_t delayed_pc; /* target of delayed jump */
	122	uint32_t mach; /* multiply and accumulate high */
	123	uint32_t macl; /* multiply and accumulate low */
	124	uint32_t pr; /* procedure register */
	125	uint32_t fpscr; /* floating point status/control register */
	126	uint32_t fpul; /* floating point communication register */
	127
17b086f7	128	/* float point status register */
ea6cf6be	129	float_status fp_status;
eda9b09b	130
71968fa6 AJ	131	/* The features that we should emulate. See sh_features above. */
	132	uint32_t features;
	133
fdf9b3e8 FB	134	/* Those belong to the specific unit (SH7750) but are handled here */
	135	uint32_t mmucr; /* MMU control register */
	136	uint32_t pteh; /* page table entry high register */
	137	uint32_t ptel; /* page table entry low register */
	138	uint32_t ptea; /* page table entry assistance register */
	139	uint32_t ttb; /* tranlation table base register */
	140	uint32_t tea; /* TLB exception address register */
	141	uint32_t tra; /* TRAPA exception register */
	142	uint32_t expevt; /* exception event register */
	143	uint32_t intevt; /* interrupt event register */
	144
0fd3ca30 AJ	145	uint32_t pvr; /* Processor Version Register */
	146	uint32_t prr; /* Processor Revision Register */
	147	uint32_t cvr; /* Cache Version Register */
	148
66c7c806 AJ	149	uint32_t ldst;
66c7c806 AJ	150
fdf9b3e8 FB	151	CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
fdf9b3e8 FB	152	tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
e96e2044	153	void *intc_handle;
833ed386	154	int intr_at_halt; /* SR_BL ignored during sleep */
852d481f EI	155	memory_content *movcal_backup;
852d481f EI	156	memory_content **movcal_backup_tail;
fdf9b3e8 FB	157	} CPUSH4State;
fdf9b3e8 FB	158
aaed909a	159	CPUSH4State cpu_sh4_init(const char cpu_model);
fdf9b3e8	160	int cpu_sh4_exec(CPUSH4State * s);
5fafdf24	161	int cpu_sh4_signal_handler(int host_signum, void *pinfo,
5a7b542b	162	void *puc);
42083220 AJ	163	int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
42083220 AJ	164	int mmu_idx, int is_softmmu);
0b5c1ce8	165	#define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
42083220 AJ	166	void do_interrupt(CPUSH4State * env);
42083220 AJ	167
0fd3ca30	168	void sh4_cpu_list(FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...));
e0bcb9ca	169	void cpu_sh4_invalidate_tlb(CPUSH4State *s);
c227f099	170	void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
29e179bc	171	uint32_t mem_value);
fdf9b3e8	172
852d481f EI	173	int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
852d481f EI	174
0b6d3ae0 AJ	175	static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
	176	{
	177	env->gbr = newtls;
	178	}
	179
ef7ec1c1 AJ	180	void cpu_load_tlb(CPUSH4State * env);
ef7ec1c1 AJ	181
fdf9b3e8 FB	182	#include "softfloat.h"
fdf9b3e8 FB	183
9467d44c TS	184	#define cpu_init cpu_sh4_init
	185	#define cpu_exec cpu_sh4_exec
	186	#define cpu_gen_code cpu_sh4_gen_code
	187	#define cpu_signal_handler cpu_sh4_signal_handler
0fd3ca30	188	#define cpu_list sh4_cpu_list
9467d44c	189
6ebbf390 JM	190	/* MMU modes definitions */
	191	#define MMU_MODE0_SUFFIX _kernel
	192	#define MMU_MODE1_SUFFIX _user
	193	#define MMU_USER_IDX 1
	194	static inline int cpu_mmu_index (CPUState *env)
	195	{
	196	return (env->sr & SR_MD) == 0 ? 1 : 0;
	197	}
	198
6e68e076 PB	199	#if defined(CONFIG_USER_ONLY)
	200	static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
	201	{
f8ed7070	202	if (newsp)
6e68e076 PB	203	env->gregs[15] = newsp;
	204	env->gregs[0] = 0;
	205	}
	206	#endif
	207
fdf9b3e8	208	#include "cpu-all.h"
622ed360	209	#include "exec-all.h"
fdf9b3e8 FB	210
	211	/* Memory access type */
	212	enum {
	213	/* Privilege */
	214	ACCESS_PRIV = 0x01,
	215	/* Direction */
	216	ACCESS_WRITE = 0x02,
	217	/* Type of instruction */
	218	ACCESS_CODE = 0x10,
	219	ACCESS_INT = 0x20
	220	};
	221
	222	/* MMU control register */
	223	#define MMUCR 0x1F000010
	224	#define MMUCR_AT (1<<0)
e0bcb9ca	225	#define MMUCR_TI (1<<2)
fdf9b3e8	226	#define MMUCR_SV (1<<8)
ea2b542a AJ	227	#define MMUCR_URC_BITS (6)
	228	#define MMUCR_URC_OFFSET (10)
	229	#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
	230	#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
	231	static inline int cpu_mmucr_urc (uint32_t mmucr)
	232	{
	233	return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
	234	}
	235
	236	/* PTEH : Page Translation Entry High register */
	237	#define PTEH_ASID_BITS (8)
	238	#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
	239	#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
	240	#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
	241	#define PTEH_VPN_BITS (22)
	242	#define PTEH_VPN_OFFSET (10)
	243	#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
	244	#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
	245	static inline int cpu_pteh_vpn (uint32_t pteh)
	246	{
	247	return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
	248	}
	249
	250	/* PTEL : Page Translation Entry Low register */
	251	#define PTEL_V (1 << 8)
	252	#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
	253	#define PTEL_C (1 << 3)
	254	#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
	255	#define PTEL_D (1 << 2)
	256	#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
	257	#define PTEL_SH (1 << 1)
	258	#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
	259	#define PTEL_WT (1 << 0)
	260	#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
	261
	262	#define PTEL_SZ_HIGH_OFFSET (7)
	263	#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
	264	#define PTEL_SZ_LOW_OFFSET (4)
	265	#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
	266	static inline int cpu_ptel_sz (uint32_t ptel)
	267	{
	268	int sz;
	269	sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
	270	sz <<= 1;
	271	sz \|= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
	272	return sz;
	273	}
	274
	275	#define PTEL_PPN_BITS (19)
	276	#define PTEL_PPN_OFFSET (10)
	277	#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
	278	#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
	279	static inline int cpu_ptel_ppn (uint32_t ptel)
	280	{
	281	return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
	282	}
	283
	284	#define PTEL_PR_BITS (2)
	285	#define PTEL_PR_OFFSET (5)
	286	#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
	287	#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
	288	static inline int cpu_ptel_pr (uint32_t ptel)
	289	{
	290	return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
291	}
292
293	/* PTEA : Page Translation Entry Assistance register */
294	#define PTEA_SA_BITS (3)
295	#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
296	#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
297	#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
298	#define PTEA_TC (1 << 3)
299	#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
fdf9b3e8	300
622ed360 AL	301	static inline void cpu_pc_from_tb(CPUState env, TranslationBlock tb)
	302	{
	303	env->pc = tb->pc;
	304	env->flags = tb->flags;
	305	}
	306
852d481f EI	307	#define TB_FLAG_PENDING_MOVCA (1 << 4)
852d481f EI	308
6b917547 AL	309	static inline void cpu_get_tb_cpu_state(CPUState env, target_ulong pc,
	310	target_ulong cs_base, int flags)
	311	{
	312	*pc = env->pc;
	313	*cs_base = 0;
	314	*flags = (env->flags & (DELAY_SLOT \| DELAY_SLOT_CONDITIONAL
	315	\| DELAY_SLOT_TRUE \| DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
	316	\| (env->fpscr & (FPSCR_FR \| FPSCR_SZ \| FPSCR_PR)) /* Bits 19-21 */
d8299bcc	317	\| (env->sr & (SR_MD \| SR_RB)) /* Bits 29-30 */
852d481f EI	318	\| (env->sr & SR_FD) /* Bit 15 */
852d481f EI	319	\| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
6b917547 AL	320	}
6b917547 AL	321
fdf9b3e8	322	#endif /* _CPU_SH4_H */