[qemu.git] / target-sh4 / helper.c

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"
#include "hw/sh_intc.h"

#if defined(CONFIG_USER_ONLY)

void do_interrupt (CPUState *env)
{
  env->exception_index = -1;
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    env->tea = address;
    env->exception_index = 0;
    switch (rw) {
    case 0:
        env->exception_index = 0x0a0;
        break;
    case 1:
        env->exception_index = 0x0c0;
        break;
    case 2:
        env->exception_index = 0x0a0;
        break;
    }
    return 1;
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    return addr;
}

int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
{
    /* For user mode, only U0 area is cachable. */
    return !!(addr & 0x80000000);
}

#else /* !CONFIG_USER_ONLY */

#define MMU_OK                   0
#define MMU_ITLB_MISS            (-1)
#define MMU_ITLB_MULTIPLE        (-2)
#define MMU_ITLB_VIOLATION       (-3)
#define MMU_DTLB_MISS_READ       (-4)
#define MMU_DTLB_MISS_WRITE      (-5)
#define MMU_DTLB_INITIAL_WRITE   (-6)
#define MMU_DTLB_VIOLATION_READ  (-7)
#define MMU_DTLB_VIOLATION_WRITE (-8)
#define MMU_DTLB_MULTIPLE        (-9)
#define MMU_DTLB_MISS            (-10)
#define MMU_IADDR_ERROR          (-11)
#define MMU_DADDR_ERROR_READ     (-12)
#define MMU_DADDR_ERROR_WRITE    (-13)

void do_interrupt(CPUState * env)
{
    int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
    int do_exp, irq_vector = env->exception_index;

    /* prioritize exceptions over interrupts */

    do_exp = env->exception_index != -1;
    do_irq = do_irq && (env->exception_index == -1);

    if (env->sr & SR_BL) {
        if (do_exp && env->exception_index != 0x1e0) {
            env->exception_index = 0x000; /* masked exception -> reset */
        }
        if (do_irq && !env->intr_at_halt) {
            return; /* masked */
        }
        env->intr_at_halt = 0;
    }

    if (do_irq) {
        irq_vector = sh_intc_get_pending_vector(env->intc_handle,
						(env->sr >> 4) & 0xf);
        if (irq_vector == -1) {
            return; /* masked */
	}
    }

    if (qemu_loglevel_mask(CPU_LOG_INT)) {
	const char *expname;
	switch (env->exception_index) {
	case 0x0e0:
	    expname = "addr_error";
	    break;
	case 0x040:
	    expname = "tlb_miss";
	    break;
	case 0x0a0:
	    expname = "tlb_violation";
	    break;
	case 0x180:
	    expname = "illegal_instruction";
	    break;
	case 0x1a0:
	    expname = "slot_illegal_instruction";
	    break;
	case 0x800:
	    expname = "fpu_disable";
	    break;
	case 0x820:
	    expname = "slot_fpu";
	    break;
	case 0x100:
	    expname = "data_write";
	    break;
	case 0x060:
	    expname = "dtlb_miss_write";
	    break;
	case 0x0c0:
	    expname = "dtlb_violation_write";
	    break;
	case 0x120:
	    expname = "fpu_exception";
	    break;
	case 0x080:
	    expname = "initial_page_write";
	    break;
	case 0x160:
	    expname = "trapa";
	    break;
	default:
            expname = do_irq ? "interrupt" : "???";
            break;
	}
	qemu_log("exception 0x%03x [%s] raised\n",
		  irq_vector, expname);
	log_cpu_state(env, 0);
    }

    env->ssr = env->sr;
    env->spc = env->pc;
    env->sgr = env->gregs[15];
    env->sr |= SR_BL | SR_MD | SR_RB;

    if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
        /* Branch instruction should be executed again before delay slot. */
	env->spc -= 2;
	/* Clear flags for exception/interrupt routine. */
	env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
    }
    if (env->flags & DELAY_SLOT_CLEARME)
        env->flags = 0;

    if (do_exp) {
        env->expevt = env->exception_index;
        switch (env->exception_index) {
        case 0x000:
        case 0x020:
        case 0x140:
            env->sr &= ~SR_FD;
            env->sr |= 0xf << 4; /* IMASK */
            env->pc = 0xa0000000;
            break;
        case 0x040:
        case 0x060:
            env->pc = env->vbr + 0x400;
            break;
        case 0x160:
            env->spc += 2; /* special case for TRAPA */
            /* fall through */
        default:
            env->pc = env->vbr + 0x100;
            break;
        }
        return;
    }

    if (do_irq) {
        env->intevt = irq_vector;
        env->pc = env->vbr + 0x600;
        return;
    }
}

static void update_itlb_use(CPUState * env, int itlbnb)
{
    uint8_t or_mask = 0, and_mask = (uint8_t) - 1;

    switch (itlbnb) {
    case 0:
	and_mask = 0x1f;
	break;
    case 1:
	and_mask = 0xe7;
	or_mask = 0x80;
	break;
    case 2:
	and_mask = 0xfb;
	or_mask = 0x50;
	break;
    case 3:
	or_mask = 0x2c;
	break;
    }

    env->mmucr &= (and_mask << 24) | 0x00ffffff;
    env->mmucr |= (or_mask << 24);
}

static int itlb_replacement(CPUState * env)
{
    if ((env->mmucr & 0xe0000000) == 0xe0000000)
	return 0;
    if ((env->mmucr & 0x98000000) == 0x18000000)
	return 1;
    if ((env->mmucr & 0x54000000) == 0x04000000)
	return 2;
    if ((env->mmucr & 0x2c000000) == 0x00000000)
	return 3;
    assert(0);
}

/* Find the corresponding entry in the right TLB
   Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
static int find_tlb_entry(CPUState * env, target_ulong address,
			  tlb_t * entries, uint8_t nbtlb, int use_asid)
{
    int match = MMU_DTLB_MISS;
    uint32_t start, end;
    uint8_t asid;
    int i;

    asid = env->pteh & 0xff;

    for (i = 0; i < nbtlb; i++) {
	if (!entries[i].v)
	    continue;		/* Invalid entry */
	if (!entries[i].sh && use_asid && entries[i].asid != asid)
	    continue;		/* Bad ASID */
#if 0
	switch (entries[i].sz) {
	case 0:
	    size = 1024;	/* 1kB */
	    break;
	case 1:
	    size = 4 * 1024;	/* 4kB */
	    break;
	case 2:
	    size = 64 * 1024;	/* 64kB */
	    break;
	case 3:
	    size = 1024 * 1024;	/* 1MB */
	    break;
	default:
	    assert(0);
	}
#endif
	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
	end = start + entries[i].size - 1;
	if (address >= start && address <= end) {	/* Match */
	    if (match != MMU_DTLB_MISS)
		return MMU_DTLB_MULTIPLE;	/* Multiple match */
	    match = i;
	}
    }
    return match;
}

static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
				 const tlb_t * needle)
{
    int i;
    for (i = 0; i < nbtlb; i++)
        if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
	    return 1;
    return 0;
}

static void increment_urc(CPUState * env)
{
    uint8_t urb, urc;

    /* Increment URC */
    urb = ((env->mmucr) >> 18) & 0x3f;
    urc = ((env->mmucr) >> 10) & 0x3f;
    urc++;
    if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
	urc = 0;
    env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
}

/* Find itlb entry - update itlb from utlb if necessary and asked for
   Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
   Update the itlb from utlb if update is not 0
*/
static int find_itlb_entry(CPUState * env, target_ulong address,
                           int use_asid, int update)
{
    int e, n;

    e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
    if (e == MMU_DTLB_MULTIPLE)
	e = MMU_ITLB_MULTIPLE;
    else if (e == MMU_DTLB_MISS && update) {
	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	if (e >= 0) {
	    tlb_t * ientry;
	    n = itlb_replacement(env);
	    ientry = &env->itlb[n];
	    if (ientry->v) {
		if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
		    tlb_flush_page(env, ientry->vpn << 10);
	    }
	    *ientry = env->utlb[e];
	    e = n;
	} else if (e == MMU_DTLB_MISS)
	    e = MMU_ITLB_MISS;
    } else if (e == MMU_DTLB_MISS)
	e = MMU_ITLB_MISS;
    if (e >= 0)
	update_itlb_use(env, e);
    return e;
}

/* Find utlb entry
   Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
{
    /* per utlb access */
    increment_urc(env);

    /* Return entry */
    return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
}

/* Match address against MMU
   Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
   MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
   MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
   MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
   MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/
static int get_mmu_address(CPUState * env, target_ulong * physical,
			   int *prot, target_ulong address,
			   int rw, int access_type)
{
    int use_asid, n;
    tlb_t *matching = NULL;

    use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;

    if (rw == 2) {
	n = find_itlb_entry(env, address, use_asid, 1);
	if (n >= 0) {
	    matching = &env->itlb[n];
	    if ((env->sr & SR_MD) & !(matching->pr & 2))
		n = MMU_ITLB_VIOLATION;
	    else
		*prot = PAGE_READ;
	}
    } else {
	n = find_utlb_entry(env, address, use_asid);
	if (n >= 0) {
	    matching = &env->utlb[n];
	    switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
	    case 0:		/* 000 */
	    case 2:		/* 010 */
		n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
		    MMU_DTLB_VIOLATION_READ;
		break;
	    case 1:		/* 001 */
	    case 4:		/* 100 */
	    case 5:		/* 101 */
		if (rw == 1)
		    n = MMU_DTLB_VIOLATION_WRITE;
		else
		    *prot = PAGE_READ;
		break;
	    case 3:		/* 011 */
	    case 6:		/* 110 */
	    case 7:		/* 111 */
		*prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
		break;
	    }
	} else if (n == MMU_DTLB_MISS) {
	    n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
		MMU_DTLB_MISS_READ;
	}
    }
    if (n >= 0) {
	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
	    (address & (matching->size - 1));
	if ((rw == 1) & !matching->d)
	    n = MMU_DTLB_INITIAL_WRITE;
	else
	    n = MMU_OK;
    }
    return n;
}

static int get_physical_address(CPUState * env, target_ulong * physical,
                                int *prot, target_ulong address,
                                int rw, int access_type)
{
    /* P1, P2 and P4 areas do not use translation */
    if ((address >= 0x80000000 && address < 0xc0000000) ||
	address >= 0xe0000000) {
	if (!(env->sr & SR_MD)
	    && (address < 0xe0000000 || address > 0xe4000000)) {
	    /* Unauthorized access in user mode (only store queues are available) */
	    fprintf(stderr, "Unauthorized access\n");
	    if (rw == 0)
		return MMU_DADDR_ERROR_READ;
	    else if (rw == 1)
		return MMU_DADDR_ERROR_WRITE;
	    else
		return MMU_IADDR_ERROR;
	}
	if (address >= 0x80000000 && address < 0xc0000000) {
	    /* Mask upper 3 bits for P1 and P2 areas */
	    *physical = address & 0x1fffffff;
	} else {
	    *physical = address;
	}
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* If MMU is disabled, return the corresponding physical page */
    if (!env->mmucr & MMUCR_AT) {
	*physical = address & 0x1FFFFFFF;
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* We need to resort to the MMU */
    return get_mmu_address(env, physical, prot, address, rw, access_type);
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    target_ulong physical, page_offset, page_size;
    int prot, ret, access_type;

    access_type = ACCESS_INT;
    ret =
	get_physical_address(env, &physical, &prot, address, rw,
			     access_type);

    if (ret != MMU_OK) {
	env->tea = address;
	switch (ret) {
	case MMU_ITLB_MISS:
	case MMU_DTLB_MISS_READ:
	    env->exception_index = 0x040;
	    break;
	case MMU_DTLB_MULTIPLE:
	case MMU_ITLB_MULTIPLE:
	    env->exception_index = 0x140;
	    break;
	case MMU_ITLB_VIOLATION:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_MISS_WRITE:
	    env->exception_index = 0x060;
	    break;
	case MMU_DTLB_INITIAL_WRITE:
	    env->exception_index = 0x080;
	    break;
	case MMU_DTLB_VIOLATION_READ:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_VIOLATION_WRITE:
	    env->exception_index = 0x0c0;
	    break;
	case MMU_IADDR_ERROR:
	case MMU_DADDR_ERROR_READ:
	    env->exception_index = 0x0c0;
	    break;
	case MMU_DADDR_ERROR_WRITE:
	    env->exception_index = 0x100;
	    break;
	default:
	    assert(0);
	}
	return 1;
    }

    page_size = TARGET_PAGE_SIZE;
    page_offset =
	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
    address = (address & TARGET_PAGE_MASK) + page_offset;
    physical = (physical & TARGET_PAGE_MASK) + page_offset;

    return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    target_ulong physical;
    int prot;

    get_physical_address(env, &physical, &prot, addr, 0, 0);
    return physical;
}

void cpu_load_tlb(CPUSH4State * env)
{
    int n = cpu_mmucr_urc(env->mmucr);
    tlb_t * entry = &env->utlb[n];

    if (entry->v) {
        /* Overwriting valid entry in utlb. */
        target_ulong address = entry->vpn << 10;
	if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
	    tlb_flush_page(env, address);
	}
    }

    /* Take values into cpu status from registers. */
    entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
    entry->vpn  = cpu_pteh_vpn(env->pteh);
    entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
    entry->ppn  = cpu_ptel_ppn(env->ptel);
    entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
    switch (entry->sz) {
    case 0: /* 00 */
        entry->size = 1024; /* 1K */
        break;
    case 1: /* 01 */
        entry->size = 1024 * 4; /* 4K */
        break;
    case 2: /* 10 */
        entry->size = 1024 * 64; /* 64K */
        break;
    case 3: /* 11 */
        entry->size = 1024 * 1024; /* 1M */
        break;
    default:
        assert(0);
        break;
    }
    entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
    entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
    entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
    entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
    entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
    entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
    entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
}

void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
				    uint32_t mem_value)
{
    int associate = addr & 0x0000080;
    uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
    uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
    uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
    uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
    int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;

    if (associate) {
        int i;
	tlb_t * utlb_match_entry = NULL;
	int needs_tlb_flush = 0;

	/* search UTLB */
	for (i = 0; i < UTLB_SIZE; i++) {
            tlb_t * entry = &s->utlb[i];
            if (!entry->v)
	        continue;

            if (entry->vpn == vpn
                && (!use_asid || entry->asid == asid || entry->sh)) {
	        if (utlb_match_entry) {
		    /* Multiple TLB Exception */
		    s->exception_index = 0x140;
		    s->tea = addr;
		    break;
	        }
		if (entry->v && !v)
		    needs_tlb_flush = 1;
		entry->v = v;
		entry->d = d;
	        utlb_match_entry = entry;
	    }
	    increment_urc(s); /* per utlb access */
	}

	/* search ITLB */
	for (i = 0; i < ITLB_SIZE; i++) {
            tlb_t * entry = &s->itlb[i];
            if (entry->vpn == vpn
                && (!use_asid || entry->asid == asid || entry->sh)) {
	        if (entry->v && !v)
		    needs_tlb_flush = 1;
	        if (utlb_match_entry)
		    *entry = *utlb_match_entry;
	        else
		    entry->v = v;
		break;
	    }
	}

	if (needs_tlb_flush)
	    tlb_flush_page(s, vpn << 10);
        
    } else {
        int index = (addr & 0x00003f00) >> 8;
        tlb_t * entry = &s->utlb[index];
	if (entry->v) {
	    /* Overwriting valid entry in utlb. */
            target_ulong address = entry->vpn << 10;
	    if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
	        tlb_flush_page(s, address);
	    }
	}
	entry->asid = asid;
	entry->vpn = vpn;
	entry->d = d;
	entry->v = v;
	increment_urc(s);
    }
}

int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
{
    int n;
    int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;

    /* check area */
    if (env->sr & SR_MD) {
        /* For previledged mode, P2 and P4 area is not cachable. */
        if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
            return 0;
    } else {
        /* For user mode, only U0 area is cachable. */
        if (0x80000000 <= addr)
            return 0;
    }

    /*
     * TODO : Evaluate CCR and check if the cache is on or off.
     *        Now CCR is not in CPUSH4State, but in SH7750State.
     *        When you move the ccr inot CPUSH4State, the code will be
     *        as follows.
     */
#if 0
    /* check if operand cache is enabled or not. */
    if (!(env->ccr & 1))
        return 0;
#endif

    /* if MMU is off, no check for TLB. */
    if (env->mmucr & MMUCR_AT)
        return 1;

    /* check TLB */
    n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
    if (n >= 0)
        return env->itlb[n].c;

    n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
    if (n >= 0)
        return env->utlb[n].c;

    return 0;
}

#endif
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
fad6cb1a	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
fdf9b3e8 FB	19	*/
	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
e96e2044	30	#include "hw/sh_intc.h"
fdf9b3e8	31
355fb23d PB	32	#if defined(CONFIG_USER_ONLY)
	33
	34	void do_interrupt (CPUState *env)
	35	{
	36	env->exception_index = -1;
	37	}
	38
	39	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	40	int mmu_idx, int is_softmmu)
355fb23d PB	41	{
355fb23d PB	42	env->tea = address;
c3b5bc8a	43	env->exception_index = 0;
355fb23d PB	44	switch (rw) {
	45	case 0:
	46	env->exception_index = 0x0a0;
	47	break;
	48	case 1:
	49	env->exception_index = 0x0c0;
	50	break;
cf7055bd AJ	51	case 2:
	52	env->exception_index = 0x0a0;
	53	break;
355fb23d PB	54	}
	55	return 1;
	56	}
	57
9b3c35e0	58	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	59	{
	60	return addr;
	61	}
	62
3c1adf12 EI	63	int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
	64	{
	65	/* For user mode, only U0 area is cachable. */
	66	return !!(addr & 0x80000000);
	67	}
	68
355fb23d PB	69	#else /* !CONFIG_USER_ONLY */
355fb23d PB	70
fdf9b3e8 FB	71	#define MMU_OK 0
	72	#define MMU_ITLB_MISS (-1)
	73	#define MMU_ITLB_MULTIPLE (-2)
	74	#define MMU_ITLB_VIOLATION (-3)
	75	#define MMU_DTLB_MISS_READ (-4)
	76	#define MMU_DTLB_MISS_WRITE (-5)
	77	#define MMU_DTLB_INITIAL_WRITE (-6)
	78	#define MMU_DTLB_VIOLATION_READ (-7)
	79	#define MMU_DTLB_VIOLATION_WRITE (-8)
	80	#define MMU_DTLB_MULTIPLE (-9)
	81	#define MMU_DTLB_MISS (-10)
cf7055bd AJ	82	#define MMU_IADDR_ERROR (-11)
	83	#define MMU_DADDR_ERROR_READ (-12)
	84	#define MMU_DADDR_ERROR_WRITE (-13)
fdf9b3e8 FB	85
	86	void do_interrupt(CPUState * env)
	87	{
e96e2044 TS	88	int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
	89	int do_exp, irq_vector = env->exception_index;
	90
	91	/* prioritize exceptions over interrupts */
	92
	93	do_exp = env->exception_index != -1;
	94	do_irq = do_irq && (env->exception_index == -1);
	95
	96	if (env->sr & SR_BL) {
	97	if (do_exp && env->exception_index != 0x1e0) {
	98	env->exception_index = 0x000; /* masked exception -> reset */
	99	}
833ed386	100	if (do_irq && !env->intr_at_halt) {
e96e2044 TS	101	return; /* masked */
e96e2044 TS	102	}
833ed386	103	env->intr_at_halt = 0;
e96e2044 TS	104	}
	105
	106	if (do_irq) {
	107	irq_vector = sh_intc_get_pending_vector(env->intc_handle,
	108	(env->sr >> 4) & 0xf);
	109	if (irq_vector == -1) {
	110	return; /* masked */
	111	}
	112	}
	113
8fec2b8c	114	if (qemu_loglevel_mask(CPU_LOG_INT)) {
fdf9b3e8 FB	115	const char *expname;
	116	switch (env->exception_index) {
	117	case 0x0e0:
	118	expname = "addr_error";
	119	break;
	120	case 0x040:
	121	expname = "tlb_miss";
	122	break;
	123	case 0x0a0:
	124	expname = "tlb_violation";
	125	break;
	126	case 0x180:
	127	expname = "illegal_instruction";
	128	break;
	129	case 0x1a0:
	130	expname = "slot_illegal_instruction";
	131	break;
	132	case 0x800:
	133	expname = "fpu_disable";
	134	break;
	135	case 0x820:
	136	expname = "slot_fpu";
	137	break;
	138	case 0x100:
	139	expname = "data_write";
	140	break;
	141	case 0x060:
	142	expname = "dtlb_miss_write";
	143	break;
	144	case 0x0c0:
	145	expname = "dtlb_violation_write";
	146	break;
	147	case 0x120:
	148	expname = "fpu_exception";
	149	break;
	150	case 0x080:
	151	expname = "initial_page_write";
	152	break;
	153	case 0x160:
	154	expname = "trapa";
	155	break;
	156	default:
e96e2044 TS	157	expname = do_irq ? "interrupt" : "???";
e96e2044 TS	158	break;
fdf9b3e8	159	}
93fcfe39 AL	160	qemu_log("exception 0x%03x [%s] raised\n",
	161	irq_vector, expname);
	162	log_cpu_state(env, 0);
fdf9b3e8 FB	163	}
	164
	165	env->ssr = env->sr;
e96e2044	166	env->spc = env->pc;
fdf9b3e8 FB	167	env->sgr = env->gregs[15];
	168	env->sr \|= SR_BL \| SR_MD \| SR_RB;
	169
274a9e70 AJ	170	if (env->flags & (DELAY_SLOT \| DELAY_SLOT_CONDITIONAL)) {
	171	/* Branch instruction should be executed again before delay slot. */
	172	env->spc -= 2;
	173	/* Clear flags for exception/interrupt routine. */
	174	env->flags &= ~(DELAY_SLOT \| DELAY_SLOT_CONDITIONAL \| DELAY_SLOT_TRUE);
	175	}
	176	if (env->flags & DELAY_SLOT_CLEARME)
	177	env->flags = 0;
	178
e96e2044 TS	179	if (do_exp) {
	180	env->expevt = env->exception_index;
	181	switch (env->exception_index) {
	182	case 0x000:
	183	case 0x020:
	184	case 0x140:
	185	env->sr &= ~SR_FD;
	186	env->sr \|= 0xf << 4; /* IMASK */
	187	env->pc = 0xa0000000;
	188	break;
	189	case 0x040:
	190	case 0x060:
	191	env->pc = env->vbr + 0x400;
	192	break;
	193	case 0x160:
	194	env->spc += 2; /* special case for TRAPA */
	195	/* fall through */
	196	default:
	197	env->pc = env->vbr + 0x100;
	198	break;
	199	}
	200	return;
	201	}
	202
	203	if (do_irq) {
	204	env->intevt = irq_vector;
	205	env->pc = env->vbr + 0x600;
	206	return;
fdf9b3e8 FB	207	}
	208	}
	209
	210	static void update_itlb_use(CPUState * env, int itlbnb)
	211	{
	212	uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
	213
	214	switch (itlbnb) {
	215	case 0:
ea2b542a	216	and_mask = 0x1f;
fdf9b3e8 FB	217	break;
	218	case 1:
	219	and_mask = 0xe7;
	220	or_mask = 0x80;
	221	break;
	222	case 2:
	223	and_mask = 0xfb;
	224	or_mask = 0x50;
	225	break;
	226	case 3:
	227	or_mask = 0x2c;
	228	break;
	229	}
	230
ea2b542a	231	env->mmucr &= (and_mask << 24) \| 0x00ffffff;
fdf9b3e8 FB	232	env->mmucr \|= (or_mask << 24);
	233	}
	234
	235	static int itlb_replacement(CPUState * env)
	236	{
	237	if ((env->mmucr & 0xe0000000) == 0xe0000000)
	238	return 0;
ea2b542a	239	if ((env->mmucr & 0x98000000) == 0x18000000)
fdf9b3e8 FB	240	return 1;
	241	if ((env->mmucr & 0x54000000) == 0x04000000)
	242	return 2;
	243	if ((env->mmucr & 0x2c000000) == 0x00000000)
	244	return 3;
	245	assert(0);
	246	}
	247
	248	/* Find the corresponding entry in the right TLB
	249	Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
	250	*/
	251	static int find_tlb_entry(CPUState * env, target_ulong address,
	252	tlb_t * entries, uint8_t nbtlb, int use_asid)
	253	{
	254	int match = MMU_DTLB_MISS;
	255	uint32_t start, end;
	256	uint8_t asid;
	257	int i;
	258
	259	asid = env->pteh & 0xff;
	260
	261	for (i = 0; i < nbtlb; i++) {
	262	if (!entries[i].v)
	263	continue; /* Invalid entry */
eeda6778	264	if (!entries[i].sh && use_asid && entries[i].asid != asid)
fdf9b3e8 FB	265	continue; /* Bad ASID */
	266	#if 0
	267	switch (entries[i].sz) {
	268	case 0:
	269	size = 1024; /* 1kB */
	270	break;
	271	case 1:
	272	size = 4 * 1024; /* 4kB */
	273	break;
	274	case 2:
	275	size = 64 * 1024; /* 64kB */
	276	break;
	277	case 3:
	278	size = 1024 * 1024; /* 1MB */
	279	break;
	280	default:
	281	assert(0);
	282	}
	283	#endif
	284	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
	285	end = start + entries[i].size - 1;
	286	if (address >= start && address <= end) { /* Match */
ea2b542a	287	if (match != MMU_DTLB_MISS)
fdf9b3e8 FB	288	return MMU_DTLB_MULTIPLE; /* Multiple match */
	289	match = i;
	290	}
	291	}
	292	return match;
	293	}
	294
29e179bc AJ	295	static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
	296	const tlb_t * needle)
	297	{
	298	int i;
	299	for (i = 0; i < nbtlb; i++)
	300	if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
	301	return 1;
	302	return 0;
	303	}
	304
	305	static void increment_urc(CPUState * env)
	306	{
	307	uint8_t urb, urc;
	308
	309	/* Increment URC */
	310	urb = ((env->mmucr) >> 18) & 0x3f;
	311	urc = ((env->mmucr) >> 10) & 0x3f;
	312	urc++;
927e3a4e	313	if ((urb > 0 && urc > urb) \|\| urc > (UTLB_SIZE - 1))
29e179bc AJ	314	urc = 0;
	315	env->mmucr = (env->mmucr & 0xffff03ff) \| (urc << 10);
	316	}
	317
fdf9b3e8 FB	318	/* Find itlb entry - update itlb from utlb if necessary and asked for
	319	Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
	320	Update the itlb from utlb if update is not 0
	321	*/
ef7ec1c1 AJ	322	static int find_itlb_entry(CPUState * env, target_ulong address,
ef7ec1c1 AJ	323	int use_asid, int update)
fdf9b3e8 FB	324	{
	325	int e, n;
	326
	327	e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
	328	if (e == MMU_DTLB_MULTIPLE)
	329	e = MMU_ITLB_MULTIPLE;
	330	else if (e == MMU_DTLB_MISS && update) {
	331	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	332	if (e >= 0) {
06afe2c8	333	tlb_t * ientry;
fdf9b3e8	334	n = itlb_replacement(env);
06afe2c8 AJ	335	ientry = &env->itlb[n];
	336	if (ientry->v) {
	337	if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
	338	tlb_flush_page(env, ientry->vpn << 10);
	339	}
	340	*ientry = env->utlb[e];
fdf9b3e8	341	e = n;
ea2b542a AJ	342	} else if (e == MMU_DTLB_MISS)
	343	e = MMU_ITLB_MISS;
	344	} else if (e == MMU_DTLB_MISS)
	345	e = MMU_ITLB_MISS;
fdf9b3e8 FB	346	if (e >= 0)
	347	update_itlb_use(env, e);
	348	return e;
	349	}
	350
	351	/* Find utlb entry
	352	Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
ef7ec1c1	353	static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
fdf9b3e8	354	{
29e179bc AJ	355	/* per utlb access */
29e179bc AJ	356	increment_urc(env);
fdf9b3e8 FB	357
	358	/* Return entry */
	359	return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	360	}
	361
	362	/* Match address against MMU
	363	Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
	364	MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
	365	MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
cf7055bd AJ	366	MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
cf7055bd AJ	367	MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
fdf9b3e8 FB	368	*/
	369	static int get_mmu_address(CPUState * env, target_ulong * physical,
	370	int *prot, target_ulong address,
	371	int rw, int access_type)
	372	{
cf7055bd	373	int use_asid, n;
fdf9b3e8 FB	374	tlb_t *matching = NULL;
fdf9b3e8 FB	375
06afe2c8	376	use_asid = (env->mmucr & MMUCR_SV) == 0 \|\| (env->sr & SR_MD) == 0;
fdf9b3e8	377
cf7055bd	378	if (rw == 2) {
fdf9b3e8 FB	379	n = find_itlb_entry(env, address, use_asid, 1);
	380	if (n >= 0) {
	381	matching = &env->itlb[n];
	382	if ((env->sr & SR_MD) & !(matching->pr & 2))
	383	n = MMU_ITLB_VIOLATION;
	384	else
	385	*prot = PAGE_READ;
	386	}
	387	} else {
	388	n = find_utlb_entry(env, address, use_asid);
	389	if (n >= 0) {
	390	matching = &env->utlb[n];
	391	switch ((matching->pr << 1) \| ((env->sr & SR_MD) ? 1 : 0)) {
	392	case 0: /* 000 */
	393	case 2: /* 010 */
cf7055bd	394	n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
fdf9b3e8 FB	395	MMU_DTLB_VIOLATION_READ;
	396	break;
	397	case 1: /* 001 */
	398	case 4: /* 100 */
	399	case 5: /* 101 */
cf7055bd	400	if (rw == 1)
fdf9b3e8 FB	401	n = MMU_DTLB_VIOLATION_WRITE;
	402	else
	403	*prot = PAGE_READ;
	404	break;
	405	case 3: /* 011 */
	406	case 6: /* 110 */
	407	case 7: /* 111 */
cf7055bd	408	*prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
fdf9b3e8 FB	409	break;
	410	}
	411	} else if (n == MMU_DTLB_MISS) {
cf7055bd	412	n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
fdf9b3e8 FB	413	MMU_DTLB_MISS_READ;
	414	}
	415	}
	416	if (n >= 0) {
	417	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) \|
	418	(address & (matching->size - 1));
cf7055bd	419	if ((rw == 1) & !matching->d)
fdf9b3e8 FB	420	n = MMU_DTLB_INITIAL_WRITE;
	421	else
	422	n = MMU_OK;
	423	}
	424	return n;
	425	}
	426
ef7ec1c1 AJ	427	static int get_physical_address(CPUState * env, target_ulong * physical,
	428	int *prot, target_ulong address,
	429	int rw, int access_type)
fdf9b3e8 FB	430	{
	431	/* P1, P2 and P4 areas do not use translation */
	432	if ((address >= 0x80000000 && address < 0xc0000000) \|\|
	433	address >= 0xe0000000) {
	434	if (!(env->sr & SR_MD)
	435	&& (address < 0xe0000000 \|\| address > 0xe4000000)) {
	436	/* Unauthorized access in user mode (only store queues are available) */
	437	fprintf(stderr, "Unauthorized access\n");
cf7055bd AJ	438	if (rw == 0)
	439	return MMU_DADDR_ERROR_READ;
	440	else if (rw == 1)
	441	return MMU_DADDR_ERROR_WRITE;
	442	else
	443	return MMU_IADDR_ERROR;
fdf9b3e8	444	}
29e179bc AJ	445	if (address >= 0x80000000 && address < 0xc0000000) {
	446	/* Mask upper 3 bits for P1 and P2 areas */
	447	*physical = address & 0x1fffffff;
29e179bc	448	} else {
29e179bc AJ	449	*physical = address;
29e179bc AJ	450	}
fdf9b3e8 FB	451	*prot = PAGE_READ \| PAGE_WRITE;
	452	return MMU_OK;
	453	}
	454
	455	/* If MMU is disabled, return the corresponding physical page */
	456	if (!env->mmucr & MMUCR_AT) {
	457	*physical = address & 0x1FFFFFFF;
	458	*prot = PAGE_READ \| PAGE_WRITE;
	459	return MMU_OK;
	460	}
	461
	462	/* We need to resort to the MMU */
	463	return get_mmu_address(env, physical, prot, address, rw, access_type);
	464	}
	465
	466	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	467	int mmu_idx, int is_softmmu)
fdf9b3e8 FB	468	{
	469	target_ulong physical, page_offset, page_size;
	470	int prot, ret, access_type;
	471
fdf9b3e8 FB	472	access_type = ACCESS_INT;
	473	ret =
	474	get_physical_address(env, &physical, &prot, address, rw,
	475	access_type);
	476
	477	if (ret != MMU_OK) {
	478	env->tea = address;
	479	switch (ret) {
	480	case MMU_ITLB_MISS:
	481	case MMU_DTLB_MISS_READ:
	482	env->exception_index = 0x040;
	483	break;
	484	case MMU_DTLB_MULTIPLE:
	485	case MMU_ITLB_MULTIPLE:
	486	env->exception_index = 0x140;
	487	break;
	488	case MMU_ITLB_VIOLATION:
	489	env->exception_index = 0x0a0;
	490	break;
	491	case MMU_DTLB_MISS_WRITE:
	492	env->exception_index = 0x060;
	493	break;
	494	case MMU_DTLB_INITIAL_WRITE:
	495	env->exception_index = 0x080;
	496	break;
	497	case MMU_DTLB_VIOLATION_READ:
	498	env->exception_index = 0x0a0;
	499	break;
	500	case MMU_DTLB_VIOLATION_WRITE:
	501	env->exception_index = 0x0c0;
	502	break;
cf7055bd AJ	503	case MMU_IADDR_ERROR:
	504	case MMU_DADDR_ERROR_READ:
	505	env->exception_index = 0x0c0;
	506	break;
	507	case MMU_DADDR_ERROR_WRITE:
	508	env->exception_index = 0x100;
	509	break;
fdf9b3e8 FB	510	default:
	511	assert(0);
	512	}
	513	return 1;
	514	}
	515
	516	page_size = TARGET_PAGE_SIZE;
	517	page_offset =
	518	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
	519	address = (address & TARGET_PAGE_MASK) + page_offset;
	520	physical = (physical & TARGET_PAGE_MASK) + page_offset;
	521
6ebbf390	522	return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
fdf9b3e8	523	}
355fb23d	524
9b3c35e0	525	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	526	{
	527	target_ulong physical;
	528	int prot;
	529
cf7055bd	530	get_physical_address(env, &physical, &prot, addr, 0, 0);
355fb23d PB	531	return physical;
	532	}
	533
ef7ec1c1	534	void cpu_load_tlb(CPUSH4State * env)
ea2b542a AJ	535	{
	536	int n = cpu_mmucr_urc(env->mmucr);
	537	tlb_t * entry = &env->utlb[n];
	538
06afe2c8 AJ	539	if (entry->v) {
	540	/* Overwriting valid entry in utlb. */
	541	target_ulong address = entry->vpn << 10;
	542	if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
	543	tlb_flush_page(env, address);
	544	}
	545	}
	546
ea2b542a AJ	547	/* Take values into cpu status from registers. */
	548	entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
	549	entry->vpn = cpu_pteh_vpn(env->pteh);
	550	entry->v = (uint8_t)cpu_ptel_v(env->ptel);
	551	entry->ppn = cpu_ptel_ppn(env->ptel);
	552	entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
	553	switch (entry->sz) {
	554	case 0: /* 00 */
	555	entry->size = 1024; /* 1K */
	556	break;
	557	case 1: /* 01 */
	558	entry->size = 1024 * 4; /* 4K */
	559	break;
	560	case 2: /* 10 */
	561	entry->size = 1024 * 64; /* 64K */
	562	break;
	563	case 3: /* 11 */
	564	entry->size = 1024 * 1024; /* 1M */
	565	break;
	566	default:
	567	assert(0);
	568	break;
	569	}
	570	entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
	571	entry->c = (uint8_t)cpu_ptel_c(env->ptel);
	572	entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
	573	entry->d = (uint8_t)cpu_ptel_d(env->ptel);
	574	entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
	575	entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
	576	entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
	577	}
	578
29e179bc AJ	579	void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
	580	uint32_t mem_value)
	581	{
	582	int associate = addr & 0x0000080;
	583	uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
	584	uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
	585	uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
	586	uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
eeda6778	587	int use_asid = (s->mmucr & MMUCR_SV) == 0 \|\| (s->sr & SR_MD) == 0;
29e179bc AJ	588
	589	if (associate) {
	590	int i;
	591	tlb_t * utlb_match_entry = NULL;
	592	int needs_tlb_flush = 0;
	593
	594	/* search UTLB */
	595	for (i = 0; i < UTLB_SIZE; i++) {
	596	tlb_t * entry = &s->utlb[i];
	597	if (!entry->v)
	598	continue;
	599
eeda6778 AJ	600	if (entry->vpn == vpn
eeda6778 AJ	601	&& (!use_asid \|\| entry->asid == asid \|\| entry->sh)) {
29e179bc AJ	602	if (utlb_match_entry) {
	603	/* Multiple TLB Exception */
	604	s->exception_index = 0x140;
	605	s->tea = addr;
	606	break;
	607	}
	608	if (entry->v && !v)
	609	needs_tlb_flush = 1;
	610	entry->v = v;
	611	entry->d = d;
	612	utlb_match_entry = entry;
	613	}
	614	increment_urc(s); /* per utlb access */
	615	}
	616
	617	/* search ITLB */
	618	for (i = 0; i < ITLB_SIZE; i++) {
	619	tlb_t * entry = &s->itlb[i];
eeda6778 AJ	620	if (entry->vpn == vpn
eeda6778 AJ	621	&& (!use_asid \|\| entry->asid == asid \|\| entry->sh)) {
29e179bc AJ	622	if (entry->v && !v)
	623	needs_tlb_flush = 1;
	624	if (utlb_match_entry)
	625	entry = utlb_match_entry;
	626	else
	627	entry->v = v;
	628	break;
	629	}
	630	}
	631
	632	if (needs_tlb_flush)
	633	tlb_flush_page(s, vpn << 10);
	634
	635	} else {
	636	int index = (addr & 0x00003f00) >> 8;
	637	tlb_t * entry = &s->utlb[index];
	638	if (entry->v) {
	639	/* Overwriting valid entry in utlb. */
	640	target_ulong address = entry->vpn << 10;
	641	if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
	642	tlb_flush_page(s, address);
	643	}
	644	}
	645	entry->asid = asid;
	646	entry->vpn = vpn;
	647	entry->d = d;
	648	entry->v = v;
	649	increment_urc(s);
	650	}
	651	}
	652
852d481f EI	653	int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
	654	{
	655	int n;
	656	int use_asid = (env->mmucr & MMUCR_SV) == 0 \|\| (env->sr & SR_MD) == 0;
	657
	658	/* check area */
	659	if (env->sr & SR_MD) {
	660	/* For previledged mode, P2 and P4 area is not cachable. */
	661	if ((0xA0000000 <= addr && addr < 0xC0000000) \|\| 0xE0000000 <= addr)
	662	return 0;
	663	} else {
	664	/* For user mode, only U0 area is cachable. */
	665	if (0x80000000 <= addr)
	666	return 0;
	667	}
	668
	669	/*
	670	* TODO : Evaluate CCR and check if the cache is on or off.
	671	* Now CCR is not in CPUSH4State, but in SH7750State.
	672	* When you move the ccr inot CPUSH4State, the code will be
	673	* as follows.
	674	*/
	675	#if 0
	676	/* check if operand cache is enabled or not. */
	677	if (!(env->ccr & 1))
	678	return 0;
	679	#endif
	680
	681	/* if MMU is off, no check for TLB. */
	682	if (env->mmucr & MMUCR_AT)
	683	return 1;
	684
	685	/* check TLB */
	686	n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
	687	if (n >= 0)
	688	return env->itlb[n].c;
	689
	690	n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
	691	if (n >= 0)
	692	return env->utlb[n].c;
	693
	694	return 0;
	695	}
	696
355fb23d	697	#endif