[qemu.git] / target-sh4 / helper.c

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"
#include "hw/sh_intc.h"

#if defined(CONFIG_USER_ONLY)

void do_interrupt (CPUState *env)
{
  env->exception_index = -1;
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    env->tea = address;
    env->exception_index = 0;
    switch (rw) {
    case 0:
	env->tea = address;
        env->exception_index = 0x0a0;
        break;
    case 1:
	env->tea = address;
        env->exception_index = 0x0c0;
        break;
    }
    return 1;
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    return addr;
}

#else /* !CONFIG_USER_ONLY */

#define MMU_OK                   0
#define MMU_ITLB_MISS            (-1)
#define MMU_ITLB_MULTIPLE        (-2)
#define MMU_ITLB_VIOLATION       (-3)
#define MMU_DTLB_MISS_READ       (-4)
#define MMU_DTLB_MISS_WRITE      (-5)
#define MMU_DTLB_INITIAL_WRITE   (-6)
#define MMU_DTLB_VIOLATION_READ  (-7)
#define MMU_DTLB_VIOLATION_WRITE (-8)
#define MMU_DTLB_MULTIPLE        (-9)
#define MMU_DTLB_MISS            (-10)

void do_interrupt(CPUState * env)
{
    int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
    int do_exp, irq_vector = env->exception_index;

    /* prioritize exceptions over interrupts */

    do_exp = env->exception_index != -1;
    do_irq = do_irq && (env->exception_index == -1);

    if (env->sr & SR_BL) {
        if (do_exp && env->exception_index != 0x1e0) {
            env->exception_index = 0x000; /* masked exception -> reset */
        }
        if (do_irq && !env->intr_at_halt) {
            return; /* masked */
        }
        env->intr_at_halt = 0;
    }

    if (do_irq) {
        irq_vector = sh_intc_get_pending_vector(env->intc_handle,
						(env->sr >> 4) & 0xf);
        if (irq_vector == -1) {
            return; /* masked */
	}
    }

    if (loglevel & CPU_LOG_INT) {
	const char *expname;
	switch (env->exception_index) {
	case 0x0e0:
	    expname = "addr_error";
	    break;
	case 0x040:
	    expname = "tlb_miss";
	    break;
	case 0x0a0:
	    expname = "tlb_violation";
	    break;
	case 0x180:
	    expname = "illegal_instruction";
	    break;
	case 0x1a0:
	    expname = "slot_illegal_instruction";
	    break;
	case 0x800:
	    expname = "fpu_disable";
	    break;
	case 0x820:
	    expname = "slot_fpu";
	    break;
	case 0x100:
	    expname = "data_write";
	    break;
	case 0x060:
	    expname = "dtlb_miss_write";
	    break;
	case 0x0c0:
	    expname = "dtlb_violation_write";
	    break;
	case 0x120:
	    expname = "fpu_exception";
	    break;
	case 0x080:
	    expname = "initial_page_write";
	    break;
	case 0x160:
	    expname = "trapa";
	    break;
	default:
            expname = do_irq ? "interrupt" : "???";
            break;
	}
	fprintf(logfile, "exception 0x%03x [%s] raised\n",
		irq_vector, expname);
	cpu_dump_state(env, logfile, fprintf, 0);
    }

    env->ssr = env->sr;
    env->spc = env->pc;
    env->sgr = env->gregs[15];
    env->sr |= SR_BL | SR_MD | SR_RB;

    if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
        /* Branch instruction should be executed again before delay slot. */
	env->spc -= 2;
	/* Clear flags for exception/interrupt routine. */
	env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
    }
    if (env->flags & DELAY_SLOT_CLEARME)
        env->flags = 0;

    if (do_exp) {
        env->expevt = env->exception_index;
        switch (env->exception_index) {
        case 0x000:
        case 0x020:
        case 0x140:
            env->sr &= ~SR_FD;
            env->sr |= 0xf << 4; /* IMASK */
            env->pc = 0xa0000000;
            break;
        case 0x040:
        case 0x060:
            env->pc = env->vbr + 0x400;
            break;
        case 0x160:
            env->spc += 2; /* special case for TRAPA */
            /* fall through */
        default:
            env->pc = env->vbr + 0x100;
            break;
        }
        return;
    }

    if (do_irq) {
        env->intevt = irq_vector;
        env->pc = env->vbr + 0x600;
        return;
    }
}

static void update_itlb_use(CPUState * env, int itlbnb)
{
    uint8_t or_mask = 0, and_mask = (uint8_t) - 1;

    switch (itlbnb) {
    case 0:
	and_mask = 0x1f;
	break;
    case 1:
	and_mask = 0xe7;
	or_mask = 0x80;
	break;
    case 2:
	and_mask = 0xfb;
	or_mask = 0x50;
	break;
    case 3:
	or_mask = 0x2c;
	break;
    }

    env->mmucr &= (and_mask << 24) | 0x00ffffff;
    env->mmucr |= (or_mask << 24);
}

static int itlb_replacement(CPUState * env)
{
    if ((env->mmucr & 0xe0000000) == 0xe0000000)
	return 0;
    if ((env->mmucr & 0x98000000) == 0x18000000)
	return 1;
    if ((env->mmucr & 0x54000000) == 0x04000000)
	return 2;
    if ((env->mmucr & 0x2c000000) == 0x00000000)
	return 3;
    assert(0);
}

/* Find the corresponding entry in the right TLB
   Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
static int find_tlb_entry(CPUState * env, target_ulong address,
			  tlb_t * entries, uint8_t nbtlb, int use_asid)
{
    int match = MMU_DTLB_MISS;
    uint32_t start, end;
    uint8_t asid;
    int i;

    asid = env->pteh & 0xff;

    for (i = 0; i < nbtlb; i++) {
	if (!entries[i].v)
	    continue;		/* Invalid entry */
	if (use_asid && entries[i].asid != asid && !entries[i].sh)
	    continue;		/* Bad ASID */
#if 0
	switch (entries[i].sz) {
	case 0:
	    size = 1024;	/* 1kB */
	    break;
	case 1:
	    size = 4 * 1024;	/* 4kB */
	    break;
	case 2:
	    size = 64 * 1024;	/* 64kB */
	    break;
	case 3:
	    size = 1024 * 1024;	/* 1MB */
	    break;
	default:
	    assert(0);
	}
#endif
	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
	end = start + entries[i].size - 1;
	if (address >= start && address <= end) {	/* Match */
	    if (match != MMU_DTLB_MISS)
		return MMU_DTLB_MULTIPLE;	/* Multiple match */
	    match = i;
	}
    }
    return match;
}

static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
				 const tlb_t * needle)
{
    int i;
    for (i = 0; i < nbtlb; i++)
        if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
	    return 1;
    return 0;
}

static void increment_urc(CPUState * env)
{
    uint8_t urb, urc;

    /* Increment URC */
    urb = ((env->mmucr) >> 18) & 0x3f;
    urc = ((env->mmucr) >> 10) & 0x3f;
    urc++;
    if (urc == urb || urc == UTLB_SIZE - 1)
	urc = 0;
    env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
}

/* Find itlb entry - update itlb from utlb if necessary and asked for
   Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
   Update the itlb from utlb if update is not 0
*/
int find_itlb_entry(CPUState * env, target_ulong address,
		    int use_asid, int update)
{
    int e, n;

    e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
    if (e == MMU_DTLB_MULTIPLE)
	e = MMU_ITLB_MULTIPLE;
    else if (e == MMU_DTLB_MISS && update) {
	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	if (e >= 0) {
	    n = itlb_replacement(env);
	    env->itlb[n] = env->utlb[e];
	    e = n;
	} else if (e == MMU_DTLB_MISS)
	    e = MMU_ITLB_MISS;
    } else if (e == MMU_DTLB_MISS)
	e = MMU_ITLB_MISS;
    if (e >= 0)
	update_itlb_use(env, e);
    return e;
}

/* Find utlb entry
   Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
{
    /* per utlb access */
    increment_urc(env);

    /* Return entry */
    return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
}

/* Match address against MMU
   Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
   MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
   MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
   MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
*/
static int get_mmu_address(CPUState * env, target_ulong * physical,
			   int *prot, target_ulong address,
			   int rw, int access_type)
{
    int use_asid, is_code, n;
    tlb_t *matching = NULL;

    use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
    is_code = env->pc == address;	/* Hack */

    /* Use a hack to find if this is an instruction or data access */
    if (env->pc == address && !(rw & PAGE_WRITE)) {
	n = find_itlb_entry(env, address, use_asid, 1);
	if (n >= 0) {
	    matching = &env->itlb[n];
	    if ((env->sr & SR_MD) & !(matching->pr & 2))
		n = MMU_ITLB_VIOLATION;
	    else
		*prot = PAGE_READ;
	}
    } else {
	n = find_utlb_entry(env, address, use_asid);
	if (n >= 0) {
	    matching = &env->utlb[n];
	    switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
	    case 0:		/* 000 */
	    case 2:		/* 010 */
		n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
		    MMU_DTLB_VIOLATION_READ;
		break;
	    case 1:		/* 001 */
	    case 4:		/* 100 */
	    case 5:		/* 101 */
		if (rw & PAGE_WRITE)
		    n = MMU_DTLB_VIOLATION_WRITE;
		else
		    *prot = PAGE_READ;
		break;
	    case 3:		/* 011 */
	    case 6:		/* 110 */
	    case 7:		/* 111 */
		*prot = rw & (PAGE_READ | PAGE_WRITE);
		break;
	    }
	} else if (n == MMU_DTLB_MISS) {
	    n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
		MMU_DTLB_MISS_READ;
	}
    }
    if (n >= 0) {
	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
	    (address & (matching->size - 1));
	if ((rw & PAGE_WRITE) & !matching->d)
	    n = MMU_DTLB_INITIAL_WRITE;
	else
	    n = MMU_OK;
    }
    return n;
}

int get_physical_address(CPUState * env, target_ulong * physical,
			 int *prot, target_ulong address,
			 int rw, int access_type)
{
    /* P1, P2 and P4 areas do not use translation */
    if ((address >= 0x80000000 && address < 0xc0000000) ||
	address >= 0xe0000000) {
	if (!(env->sr & SR_MD)
	    && (address < 0xe0000000 || address > 0xe4000000)) {
	    /* Unauthorized access in user mode (only store queues are available) */
	    fprintf(stderr, "Unauthorized access\n");
	    return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
		MMU_DTLB_MISS_READ;
	}
	if (address >= 0x80000000 && address < 0xc0000000) {
	    /* Mask upper 3 bits for P1 and P2 areas */
	    *physical = address & 0x1fffffff;
	} else if (address >= 0xfc000000) {
	    /*
	     * Mask upper 3 bits for control registers in P4 area,
	     * to unify access to control registers via P0-P3 area.
	     * The addresses for cache store queue, TLB address array
	     * are not masked.
	     */
	*physical = address & 0x1fffffff;
	} else {
	    /* access to cache store queue, or TLB address array. */
	    *physical = address;
	}
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* If MMU is disabled, return the corresponding physical page */
    if (!env->mmucr & MMUCR_AT) {
	*physical = address & 0x1FFFFFFF;
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* We need to resort to the MMU */
    return get_mmu_address(env, physical, prot, address, rw, access_type);
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    target_ulong physical, page_offset, page_size;
    int prot, ret, access_type;

    switch (rw) {
    case 0:
        rw = PAGE_READ;
        break;
    case 1:
        rw = PAGE_WRITE;
        break;
    case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */
        rw = PAGE_READ;
        break;
    default:
        /* fatal error */
        assert(0);
    }

    /* XXXXX */
#if 0
    fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
	    __func__, env->pc, address, rw, mmu_idx, is_softmmu);
#endif

    access_type = ACCESS_INT;
    ret =
	get_physical_address(env, &physical, &prot, address, rw,
			     access_type);

    if (ret != MMU_OK) {
	env->tea = address;
	switch (ret) {
	case MMU_ITLB_MISS:
	case MMU_DTLB_MISS_READ:
	    env->exception_index = 0x040;
	    break;
	case MMU_DTLB_MULTIPLE:
	case MMU_ITLB_MULTIPLE:
	    env->exception_index = 0x140;
	    break;
	case MMU_ITLB_VIOLATION:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_MISS_WRITE:
	    env->exception_index = 0x060;
	    break;
	case MMU_DTLB_INITIAL_WRITE:
	    env->exception_index = 0x080;
	    break;
	case MMU_DTLB_VIOLATION_READ:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_VIOLATION_WRITE:
	    env->exception_index = 0x0c0;
	    break;
	default:
	    assert(0);
	}
	return 1;
    }

    page_size = TARGET_PAGE_SIZE;
    page_offset =
	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
    address = (address & TARGET_PAGE_MASK) + page_offset;
    physical = (physical & TARGET_PAGE_MASK) + page_offset;

    return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    target_ulong physical;
    int prot;

    get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
    return physical;
}

void cpu_load_tlb(CPUState * env)
{
    int n = cpu_mmucr_urc(env->mmucr);
    tlb_t * entry = &env->utlb[n];

    /* Take values into cpu status from registers. */
    entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
    entry->vpn  = cpu_pteh_vpn(env->pteh);
    entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
    entry->ppn  = cpu_ptel_ppn(env->ptel);
    entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
    switch (entry->sz) {
    case 0: /* 00 */
        entry->size = 1024; /* 1K */
        break;
    case 1: /* 01 */
        entry->size = 1024 * 4; /* 4K */
        break;
    case 2: /* 10 */
        entry->size = 1024 * 64; /* 64K */
        break;
    case 3: /* 11 */
        entry->size = 1024 * 1024; /* 1M */
        break;
    default:
        assert(0);
        break;
    }
    entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
    entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
    entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
    entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
    entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
    entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
    entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
}

void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
				    uint32_t mem_value)
{
    int associate = addr & 0x0000080;
    uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
    uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
    uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
    uint8_t asid = (uint8_t)(mem_value & 0x000000ff);

    if (associate) {
        int i;
	tlb_t * utlb_match_entry = NULL;
	int needs_tlb_flush = 0;

	/* search UTLB */
	for (i = 0; i < UTLB_SIZE; i++) {
            tlb_t * entry = &s->utlb[i];
            if (!entry->v)
	        continue;

            if (entry->vpn == vpn && entry->asid == asid) {
	        if (utlb_match_entry) {
		    /* Multiple TLB Exception */
		    s->exception_index = 0x140;
		    s->tea = addr;
		    break;
	        }
		if (entry->v && !v)
		    needs_tlb_flush = 1;
		entry->v = v;
		entry->d = d;
	        utlb_match_entry = entry;
	    }
	    increment_urc(s); /* per utlb access */
	}

	/* search ITLB */
	for (i = 0; i < ITLB_SIZE; i++) {
            tlb_t * entry = &s->itlb[i];
            if (entry->vpn == vpn && entry->asid == asid) {
	        if (entry->v && !v)
		    needs_tlb_flush = 1;
	        if (utlb_match_entry)
		    *entry = *utlb_match_entry;
	        else
		    entry->v = v;
		break;
	    }
	}

	if (needs_tlb_flush)
	    tlb_flush_page(s, vpn << 10);
        
    } else {
        int index = (addr & 0x00003f00) >> 8;
        tlb_t * entry = &s->utlb[index];
	if (entry->v) {
	    /* Overwriting valid entry in utlb. */
            target_ulong address = entry->vpn << 10;
	    if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
	        tlb_flush_page(s, address);
	    }
	}
	entry->asid = asid;
	entry->vpn = vpn;
	entry->d = d;
	entry->v = v;
	increment_urc(s);
    }
}

#endif
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
e96e2044	30	#include "hw/sh_intc.h"
fdf9b3e8	31
355fb23d PB	32	#if defined(CONFIG_USER_ONLY)
	33
	34	void do_interrupt (CPUState *env)
	35	{
	36	env->exception_index = -1;
	37	}
	38
	39	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	40	int mmu_idx, int is_softmmu)
355fb23d PB	41	{
355fb23d PB	42	env->tea = address;
c3b5bc8a	43	env->exception_index = 0;
355fb23d PB	44	switch (rw) {
355fb23d PB	45	case 0:
c3b5bc8a	46	env->tea = address;
355fb23d PB	47	env->exception_index = 0x0a0;
	48	break;
	49	case 1:
c3b5bc8a	50	env->tea = address;
355fb23d PB	51	env->exception_index = 0x0c0;
355fb23d PB	52	break;
355fb23d PB	53	}
	54	return 1;
	55	}
	56
9b3c35e0	57	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	58	{
	59	return addr;
	60	}
	61
	62	#else /* !CONFIG_USER_ONLY */
	63
fdf9b3e8 FB	64	#define MMU_OK 0
	65	#define MMU_ITLB_MISS (-1)
	66	#define MMU_ITLB_MULTIPLE (-2)
	67	#define MMU_ITLB_VIOLATION (-3)
	68	#define MMU_DTLB_MISS_READ (-4)
	69	#define MMU_DTLB_MISS_WRITE (-5)
	70	#define MMU_DTLB_INITIAL_WRITE (-6)
	71	#define MMU_DTLB_VIOLATION_READ (-7)
	72	#define MMU_DTLB_VIOLATION_WRITE (-8)
	73	#define MMU_DTLB_MULTIPLE (-9)
	74	#define MMU_DTLB_MISS (-10)
	75
	76	void do_interrupt(CPUState * env)
	77	{
e96e2044 TS	78	int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
	79	int do_exp, irq_vector = env->exception_index;
	80
	81	/* prioritize exceptions over interrupts */
	82
	83	do_exp = env->exception_index != -1;
	84	do_irq = do_irq && (env->exception_index == -1);
	85
	86	if (env->sr & SR_BL) {
	87	if (do_exp && env->exception_index != 0x1e0) {
	88	env->exception_index = 0x000; /* masked exception -> reset */
	89	}
833ed386	90	if (do_irq && !env->intr_at_halt) {
e96e2044 TS	91	return; /* masked */
e96e2044 TS	92	}
833ed386	93	env->intr_at_halt = 0;
e96e2044 TS	94	}
	95
	96	if (do_irq) {
	97	irq_vector = sh_intc_get_pending_vector(env->intc_handle,
	98	(env->sr >> 4) & 0xf);
	99	if (irq_vector == -1) {
	100	return; /* masked */
	101	}
	102	}
	103
fdf9b3e8 FB	104	if (loglevel & CPU_LOG_INT) {
	105	const char *expname;
	106	switch (env->exception_index) {
	107	case 0x0e0:
	108	expname = "addr_error";
	109	break;
	110	case 0x040:
	111	expname = "tlb_miss";
	112	break;
	113	case 0x0a0:
	114	expname = "tlb_violation";
	115	break;
	116	case 0x180:
	117	expname = "illegal_instruction";
	118	break;
	119	case 0x1a0:
	120	expname = "slot_illegal_instruction";
	121	break;
	122	case 0x800:
	123	expname = "fpu_disable";
	124	break;
	125	case 0x820:
	126	expname = "slot_fpu";
	127	break;
	128	case 0x100:
	129	expname = "data_write";
	130	break;
	131	case 0x060:
	132	expname = "dtlb_miss_write";
	133	break;
	134	case 0x0c0:
	135	expname = "dtlb_violation_write";
	136	break;
	137	case 0x120:
	138	expname = "fpu_exception";
	139	break;
	140	case 0x080:
	141	expname = "initial_page_write";
	142	break;
	143	case 0x160:
	144	expname = "trapa";
	145	break;
	146	default:
e96e2044 TS	147	expname = do_irq ? "interrupt" : "???";
e96e2044 TS	148	break;
fdf9b3e8 FB	149	}
fdf9b3e8 FB	150	fprintf(logfile, "exception 0x%03x [%s] raised\n",
e96e2044	151	irq_vector, expname);
fdf9b3e8 FB	152	cpu_dump_state(env, logfile, fprintf, 0);
	153	}
	154
	155	env->ssr = env->sr;
e96e2044	156	env->spc = env->pc;
fdf9b3e8 FB	157	env->sgr = env->gregs[15];
	158	env->sr \|= SR_BL \| SR_MD \| SR_RB;
	159
274a9e70 AJ	160	if (env->flags & (DELAY_SLOT \| DELAY_SLOT_CONDITIONAL)) {
	161	/* Branch instruction should be executed again before delay slot. */
	162	env->spc -= 2;
	163	/* Clear flags for exception/interrupt routine. */
	164	env->flags &= ~(DELAY_SLOT \| DELAY_SLOT_CONDITIONAL \| DELAY_SLOT_TRUE);
	165	}
	166	if (env->flags & DELAY_SLOT_CLEARME)
	167	env->flags = 0;
	168
e96e2044 TS	169	if (do_exp) {
	170	env->expevt = env->exception_index;
	171	switch (env->exception_index) {
	172	case 0x000:
	173	case 0x020:
	174	case 0x140:
	175	env->sr &= ~SR_FD;
	176	env->sr \|= 0xf << 4; /* IMASK */
	177	env->pc = 0xa0000000;
	178	break;
	179	case 0x040:
	180	case 0x060:
	181	env->pc = env->vbr + 0x400;
	182	break;
	183	case 0x160:
	184	env->spc += 2; /* special case for TRAPA */
	185	/* fall through */
	186	default:
	187	env->pc = env->vbr + 0x100;
	188	break;
	189	}
	190	return;
	191	}
	192
	193	if (do_irq) {
	194	env->intevt = irq_vector;
	195	env->pc = env->vbr + 0x600;
	196	return;
fdf9b3e8 FB	197	}
	198	}
	199
	200	static void update_itlb_use(CPUState * env, int itlbnb)
	201	{
	202	uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
	203
	204	switch (itlbnb) {
	205	case 0:
ea2b542a	206	and_mask = 0x1f;
fdf9b3e8 FB	207	break;
	208	case 1:
	209	and_mask = 0xe7;
	210	or_mask = 0x80;
	211	break;
	212	case 2:
	213	and_mask = 0xfb;
	214	or_mask = 0x50;
	215	break;
	216	case 3:
	217	or_mask = 0x2c;
	218	break;
	219	}
	220
ea2b542a	221	env->mmucr &= (and_mask << 24) \| 0x00ffffff;
fdf9b3e8 FB	222	env->mmucr \|= (or_mask << 24);
	223	}
	224
	225	static int itlb_replacement(CPUState * env)
	226	{
	227	if ((env->mmucr & 0xe0000000) == 0xe0000000)
	228	return 0;
ea2b542a	229	if ((env->mmucr & 0x98000000) == 0x18000000)
fdf9b3e8 FB	230	return 1;
	231	if ((env->mmucr & 0x54000000) == 0x04000000)
	232	return 2;
	233	if ((env->mmucr & 0x2c000000) == 0x00000000)
	234	return 3;
	235	assert(0);
	236	}
	237
	238	/* Find the corresponding entry in the right TLB
	239	Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
	240	*/
	241	static int find_tlb_entry(CPUState * env, target_ulong address,
	242	tlb_t * entries, uint8_t nbtlb, int use_asid)
	243	{
	244	int match = MMU_DTLB_MISS;
	245	uint32_t start, end;
	246	uint8_t asid;
	247	int i;
	248
	249	asid = env->pteh & 0xff;
	250
	251	for (i = 0; i < nbtlb; i++) {
	252	if (!entries[i].v)
	253	continue; /* Invalid entry */
	254	if (use_asid && entries[i].asid != asid && !entries[i].sh)
	255	continue; /* Bad ASID */
	256	#if 0
	257	switch (entries[i].sz) {
	258	case 0:
	259	size = 1024; /* 1kB */
	260	break;
	261	case 1:
	262	size = 4 * 1024; /* 4kB */
	263	break;
	264	case 2:
	265	size = 64 * 1024; /* 64kB */
	266	break;
	267	case 3:
	268	size = 1024 * 1024; /* 1MB */
	269	break;
	270	default:
	271	assert(0);
	272	}
	273	#endif
	274	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
	275	end = start + entries[i].size - 1;
	276	if (address >= start && address <= end) { /* Match */
ea2b542a	277	if (match != MMU_DTLB_MISS)
fdf9b3e8 FB	278	return MMU_DTLB_MULTIPLE; /* Multiple match */
	279	match = i;
	280	}
	281	}
	282	return match;
	283	}
	284
29e179bc AJ	285	static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
	286	const tlb_t * needle)
	287	{
	288	int i;
	289	for (i = 0; i < nbtlb; i++)
	290	if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
	291	return 1;
	292	return 0;
	293	}
	294
	295	static void increment_urc(CPUState * env)
	296	{
	297	uint8_t urb, urc;
	298
	299	/* Increment URC */
	300	urb = ((env->mmucr) >> 18) & 0x3f;
	301	urc = ((env->mmucr) >> 10) & 0x3f;
	302	urc++;
	303	if (urc == urb \|\| urc == UTLB_SIZE - 1)
	304	urc = 0;
	305	env->mmucr = (env->mmucr & 0xffff03ff) \| (urc << 10);
	306	}
	307
fdf9b3e8 FB	308	/* Find itlb entry - update itlb from utlb if necessary and asked for
	309	Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
	310	Update the itlb from utlb if update is not 0
	311	*/
	312	int find_itlb_entry(CPUState * env, target_ulong address,
	313	int use_asid, int update)
	314	{
	315	int e, n;
	316
	317	e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
	318	if (e == MMU_DTLB_MULTIPLE)
	319	e = MMU_ITLB_MULTIPLE;
	320	else if (e == MMU_DTLB_MISS && update) {
	321	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	322	if (e >= 0) {
	323	n = itlb_replacement(env);
	324	env->itlb[n] = env->utlb[e];
	325	e = n;
ea2b542a AJ	326	} else if (e == MMU_DTLB_MISS)
	327	e = MMU_ITLB_MISS;
	328	} else if (e == MMU_DTLB_MISS)
	329	e = MMU_ITLB_MISS;
fdf9b3e8 FB	330	if (e >= 0)
	331	update_itlb_use(env, e);
	332	return e;
	333	}
	334
	335	/* Find utlb entry
	336	Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
	337	int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
	338	{
29e179bc AJ	339	/* per utlb access */
29e179bc AJ	340	increment_urc(env);
fdf9b3e8 FB	341
	342	/* Return entry */
	343	return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	344	}
	345
	346	/* Match address against MMU
	347	Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
	348	MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
	349	MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
	350	MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
	351	*/
	352	static int get_mmu_address(CPUState * env, target_ulong * physical,
	353	int *prot, target_ulong address,
	354	int rw, int access_type)
	355	{
	356	int use_asid, is_code, n;
	357	tlb_t *matching = NULL;
	358
	359	use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
	360	is_code = env->pc == address; /* Hack */
	361
	362	/* Use a hack to find if this is an instruction or data access */
	363	if (env->pc == address && !(rw & PAGE_WRITE)) {
	364	n = find_itlb_entry(env, address, use_asid, 1);
	365	if (n >= 0) {
	366	matching = &env->itlb[n];
	367	if ((env->sr & SR_MD) & !(matching->pr & 2))
	368	n = MMU_ITLB_VIOLATION;
	369	else
	370	*prot = PAGE_READ;
	371	}
	372	} else {
	373	n = find_utlb_entry(env, address, use_asid);
	374	if (n >= 0) {
	375	matching = &env->utlb[n];
	376	switch ((matching->pr << 1) \| ((env->sr & SR_MD) ? 1 : 0)) {
	377	case 0: /* 000 */
	378	case 2: /* 010 */
	379	n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
	380	MMU_DTLB_VIOLATION_READ;
	381	break;
	382	case 1: /* 001 */
	383	case 4: /* 100 */
	384	case 5: /* 101 */
	385	if (rw & PAGE_WRITE)
	386	n = MMU_DTLB_VIOLATION_WRITE;
	387	else
	388	*prot = PAGE_READ;
	389	break;
	390	case 3: /* 011 */
	391	case 6: /* 110 */
	392	case 7: /* 111 */
	393	*prot = rw & (PAGE_READ \| PAGE_WRITE);
	394	break;
	395	}
	396	} else if (n == MMU_DTLB_MISS) {
	397	n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
	398	MMU_DTLB_MISS_READ;
	399	}
	400	}
	401	if (n >= 0) {
	402	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) \|
	403	(address & (matching->size - 1));
	404	if ((rw & PAGE_WRITE) & !matching->d)
405	n = MMU_DTLB_INITIAL_WRITE;
406	else
407	n = MMU_OK;
408	}
409	return n;
410	}
411
412	int get_physical_address(CPUState * env, target_ulong * physical,
413	int *prot, target_ulong address,
414	int rw, int access_type)
415	{
416	/* P1, P2 and P4 areas do not use translation */
417	if ((address >= 0x80000000 && address < 0xc0000000) \|\|
418	address >= 0xe0000000) {
419	if (!(env->sr & SR_MD)
420	&& (address < 0xe0000000 \|\| address > 0xe4000000)) {
421	/* Unauthorized access in user mode (only store queues are available) */
422	fprintf(stderr, "Unauthorized access\n");
423	return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
424	MMU_DTLB_MISS_READ;
425	}
29e179bc AJ	426	if (address >= 0x80000000 && address < 0xc0000000) {
	427	/* Mask upper 3 bits for P1 and P2 areas */
	428	*physical = address & 0x1fffffff;
	429	} else if (address >= 0xfc000000) {
	430	/*
	431	* Mask upper 3 bits for control registers in P4 area,
	432	* to unify access to control registers via P0-P3 area.
	433	* The addresses for cache store queue, TLB address array
	434	* are not masked.
	435	*/
	436	*physical = address & 0x1fffffff;
	437	} else {
	438	/* access to cache store queue, or TLB address array. */
	439	*physical = address;
	440	}
fdf9b3e8 FB	441	*prot = PAGE_READ \| PAGE_WRITE;
	442	return MMU_OK;
	443	}
	444
	445	/* If MMU is disabled, return the corresponding physical page */
	446	if (!env->mmucr & MMUCR_AT) {
	447	*physical = address & 0x1FFFFFFF;
	448	*prot = PAGE_READ \| PAGE_WRITE;
	449	return MMU_OK;
	450	}
	451
	452	/* We need to resort to the MMU */
	453	return get_mmu_address(env, physical, prot, address, rw, access_type);
	454	}
	455
	456	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	457	int mmu_idx, int is_softmmu)
fdf9b3e8 FB	458	{
	459	target_ulong physical, page_offset, page_size;
	460	int prot, ret, access_type;
	461
ea2b542a AJ	462	switch (rw) {
	463	case 0:
	464	rw = PAGE_READ;
	465	break;
	466	case 1:
	467	rw = PAGE_WRITE;
	468	break;
	469	case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */
	470	rw = PAGE_READ;
	471	break;
	472	default:
	473	/* fatal error */
	474	assert(0);
	475	}
	476
fdf9b3e8 FB	477	/* XXXXX */
fdf9b3e8 FB	478	#if 0
6ebbf390 JM	479	fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
6ebbf390 JM	480	__func__, env->pc, address, rw, mmu_idx, is_softmmu);
fdf9b3e8 FB	481	#endif
	482
	483	access_type = ACCESS_INT;
	484	ret =
	485	get_physical_address(env, &physical, &prot, address, rw,
	486	access_type);
	487
	488	if (ret != MMU_OK) {
	489	env->tea = address;
	490	switch (ret) {
	491	case MMU_ITLB_MISS:
	492	case MMU_DTLB_MISS_READ:
	493	env->exception_index = 0x040;
	494	break;
	495	case MMU_DTLB_MULTIPLE:
	496	case MMU_ITLB_MULTIPLE:
	497	env->exception_index = 0x140;
	498	break;
	499	case MMU_ITLB_VIOLATION:
	500	env->exception_index = 0x0a0;
	501	break;
	502	case MMU_DTLB_MISS_WRITE:
	503	env->exception_index = 0x060;
	504	break;
	505	case MMU_DTLB_INITIAL_WRITE:
	506	env->exception_index = 0x080;
	507	break;
	508	case MMU_DTLB_VIOLATION_READ:
	509	env->exception_index = 0x0a0;
	510	break;
	511	case MMU_DTLB_VIOLATION_WRITE:
	512	env->exception_index = 0x0c0;
	513	break;
	514	default:
	515	assert(0);
	516	}
	517	return 1;
	518	}
	519
	520	page_size = TARGET_PAGE_SIZE;
	521	page_offset =
	522	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
	523	address = (address & TARGET_PAGE_MASK) + page_offset;
	524	physical = (physical & TARGET_PAGE_MASK) + page_offset;
	525
6ebbf390	526	return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
fdf9b3e8	527	}
355fb23d	528
9b3c35e0	529	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	530	{
	531	target_ulong physical;
	532	int prot;
	533
	534	get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
	535	return physical;
	536	}
	537
ea2b542a AJ	538	void cpu_load_tlb(CPUState * env)
	539	{
	540	int n = cpu_mmucr_urc(env->mmucr);
	541	tlb_t * entry = &env->utlb[n];
	542
	543	/* Take values into cpu status from registers. */
	544	entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
	545	entry->vpn = cpu_pteh_vpn(env->pteh);
	546	entry->v = (uint8_t)cpu_ptel_v(env->ptel);
	547	entry->ppn = cpu_ptel_ppn(env->ptel);
	548	entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
	549	switch (entry->sz) {
	550	case 0: /* 00 */
	551	entry->size = 1024; /* 1K */
	552	break;
	553	case 1: /* 01 */
	554	entry->size = 1024 * 4; /* 4K */
	555	break;
	556	case 2: /* 10 */
	557	entry->size = 1024 * 64; /* 64K */
	558	break;
	559	case 3: /* 11 */
	560	entry->size = 1024 * 1024; /* 1M */
	561	break;
	562	default:
	563	assert(0);
	564	break;
	565	}
	566	entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
	567	entry->c = (uint8_t)cpu_ptel_c(env->ptel);
	568	entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
	569	entry->d = (uint8_t)cpu_ptel_d(env->ptel);
	570	entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
	571	entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
	572	entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
	573	}
	574
29e179bc AJ	575	void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
	576	uint32_t mem_value)
	577	{
	578	int associate = addr & 0x0000080;
	579	uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
	580	uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
	581	uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
	582	uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
	583
	584	if (associate) {
	585	int i;
	586	tlb_t * utlb_match_entry = NULL;
	587	int needs_tlb_flush = 0;
	588
	589	/* search UTLB */
	590	for (i = 0; i < UTLB_SIZE; i++) {
	591	tlb_t * entry = &s->utlb[i];
	592	if (!entry->v)
	593	continue;
	594
	595	if (entry->vpn == vpn && entry->asid == asid) {
	596	if (utlb_match_entry) {
	597	/* Multiple TLB Exception */
	598	s->exception_index = 0x140;
	599	s->tea = addr;
	600	break;
	601	}
	602	if (entry->v && !v)
	603	needs_tlb_flush = 1;
	604	entry->v = v;
	605	entry->d = d;
	606	utlb_match_entry = entry;
	607	}
	608	increment_urc(s); /* per utlb access */
	609	}
	610
	611	/* search ITLB */
	612	for (i = 0; i < ITLB_SIZE; i++) {
	613	tlb_t * entry = &s->itlb[i];
	614	if (entry->vpn == vpn && entry->asid == asid) {
	615	if (entry->v && !v)
	616	needs_tlb_flush = 1;
	617	if (utlb_match_entry)
	618	entry = utlb_match_entry;
	619	else
	620	entry->v = v;
	621	break;
	622	}
	623	}
	624
	625	if (needs_tlb_flush)
	626	tlb_flush_page(s, vpn << 10);
	627
	628	} else {
	629	int index = (addr & 0x00003f00) >> 8;
	630	tlb_t * entry = &s->utlb[index];
	631	if (entry->v) {
	632	/* Overwriting valid entry in utlb. */
	633	target_ulong address = entry->vpn << 10;
	634	if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
	635	tlb_flush_page(s, address);
	636	}
	637	}
	638	entry->asid = asid;
639	entry->vpn = vpn;
640	entry->d = d;
641	entry->v = v;
642	increment_urc(s);
643	}
644	}
645
355fb23d	646	#endif